Bug Summary

File:dev/pci/drm/radeon/rs600.c
Warning:line 543, column 2
Value stored to 'tmp' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name rs600.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/radeon/rs600.c
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
38
39#include <linux/io-64-nonatomic-lo-hi.h>
40#include <linux/pci.h>
41
42#include <drm/drm_device.h>
43#include <drm/drm_vblank.h>
44#include <drm/drm_fourcc.h>
45#include <drm/drm_framebuffer.h>
46
47#include "atom.h"
48#include "radeon.h"
49#include "radeon_asic.h"
50#include "radeon_audio.h"
51#include "rs600_reg_safe.h"
52#include "rs600d.h"
53
54static void rs600_gpu_init(struct radeon_device *rdev);
55int rs600_mc_wait_for_idle(struct radeon_device *rdev);
56
57static const u32 crtc_offsets[2] =
58{
59 0,
60 AVIVO_D2CRTC_H_TOTAL0x6800 - AVIVO_D1CRTC_H_TOTAL0x6000
61};
62
63static bool_Bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
64{
65 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc])r100_mm_rreg(rdev, (0x609c + crtc_offsets[crtc]), 0) & AVIVO_D1CRTC_V_BLANK(1 << 0))
66 return true1;
67 else
68 return false0;
69}
70
71static bool_Bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
72{
73 u32 pos1, pos2;
74
75 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc])r100_mm_rreg(rdev, (0x60a0 + crtc_offsets[crtc]), 0);
76 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc])r100_mm_rreg(rdev, (0x60a0 + crtc_offsets[crtc]), 0);
77
78 if (pos1 != pos2)
79 return true1;
80 else
81 return false0;
82}
83
84/**
85 * avivo_wait_for_vblank - vblank wait asic callback.
86 *
87 * @rdev: radeon_device pointer
88 * @crtc: crtc to wait for vblank on
89 *
90 * Wait for vblank on the requested crtc (r5xx-r7xx).
91 */
92void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
93{
94 unsigned i = 0;
95
96 if (crtc >= rdev->num_crtc)
97 return;
98
99 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc])r100_mm_rreg(rdev, (0x6080 + crtc_offsets[crtc]), 0) & AVIVO_CRTC_EN(1 << 0)))
100 return;
101
102 /* depending on when we hit vblank, we may be close to active; if so,
103 * wait for another frame.
104 */
105 while (avivo_is_in_vblank(rdev, crtc)) {
106 if (i++ % 100 == 0) {
107 if (!avivo_is_counter_moving(rdev, crtc))
108 break;
109 }
110 }
111
112 while (!avivo_is_in_vblank(rdev, crtc)) {
113 if (i++ % 100 == 0) {
114 if (!avivo_is_counter_moving(rdev, crtc))
115 break;
116 }
117 }
118}
119
120void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool_Bool async)
121{
122 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
123 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset)r100_mm_rreg(rdev, (0x6144 + radeon_crtc->crtc_offset), 0);
125 int i;
126
127 /* Lock the graphics update lock */
128 tmp |= AVIVO_D1GRPH_UPDATE_LOCK(1 << 16);
129 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp)r100_mm_wreg(rdev, (0x6144 + radeon_crtc->crtc_offset), (tmp
), 0);
130
131 /* flip at hsync for async, default is vsync */
132 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6148 + radeon_crtc->crtc_offset), (async
? (1 << 0) : 0), 0)
133 async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0)r100_mm_wreg(rdev, (0x6148 + radeon_crtc->crtc_offset), (async
? (1 << 0) : 0), 0);
134 /* update pitch */
135 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6120 + radeon_crtc->crtc_offset), (fb
->pitches[0] / fb->format->cpp[0]), 0)
136 fb->pitches[0] / fb->format->cpp[0])r100_mm_wreg(rdev, (0x6120 + radeon_crtc->crtc_offset), (fb
->pitches[0] / fb->format->cpp[0]), 0);
137 /* update the scanout addresses */
138 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6118 + radeon_crtc->crtc_offset), ((
u32)crtc_base), 0)
139 (u32)crtc_base)r100_mm_wreg(rdev, (0x6118 + radeon_crtc->crtc_offset), ((
u32)crtc_base), 0);
140 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,r100_mm_wreg(rdev, (0x6110 + radeon_crtc->crtc_offset), ((
u32)crtc_base), 0)
141 (u32)crtc_base)r100_mm_wreg(rdev, (0x6110 + radeon_crtc->crtc_offset), ((
u32)crtc_base), 0);
142
143 /* Wait for update_pending to go high. */
144 for (i = 0; i < rdev->usec_timeout; i++) {
145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset)r100_mm_rreg(rdev, (0x6144 + radeon_crtc->crtc_offset), 0) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING(1 << 2))
146 break;
147 udelay(1);
148 }
149 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n")___drm_dbg(((void *)0), DRM_UT_CORE, "Update pending now high. Unlocking vupdate_lock.\n"
);
150
151 /* Unlock the lock, so double-buffering can take place inside vblank */
152 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK(1 << 16);
153 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp)r100_mm_wreg(rdev, (0x6144 + radeon_crtc->crtc_offset), (tmp
), 0);
154}
155
156bool_Bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
157{
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
159
160 /* Return current update_pending status: */
161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset)r100_mm_rreg(rdev, (0x6144 + radeon_crtc->crtc_offset), 0) &
162 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING(1 << 2));
163}
164
165void avivo_program_fmt(struct drm_encoder *encoder)
166{
167 struct drm_device *dev = encoder->dev;
168 struct radeon_device *rdev = dev->dev_private;
169 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );});
170 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
171 int bpc = 0;
172 u32 tmp = 0;
173 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
174
175 if (connector) {
176 struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
- __builtin_offsetof(struct radeon_connector, base) );});
177 bpc = radeon_get_monitor_bpc(connector);
178 dither = radeon_connector->dither;
179 }
180
181 /* LVDS FMT is set up by atom */
182 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))
183 return;
184
185 if (bpc == 0)
186 return;
187
188 switch (bpc) {
189 case 6:
190 if (dither == RADEON_FMT_DITHER_ENABLE)
191 /* XXX sort out optimal dither settings */
192 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN(1 << 8);
193 else
194 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN(1 << 0);
195 break;
196 case 8:
197 if (dither == RADEON_FMT_DITHER_ENABLE)
198 /* XXX sort out optimal dither settings */
199 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN(1 << 8) |
200 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH(1 << 12));
201 else
202 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN(1 << 0) |
203 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH(1 << 4));
204 break;
205 case 10:
206 default:
207 /* not needed */
208 break;
209 }
210
211 switch (radeon_encoder->encoder_id) {
212 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS10x13:
213 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp)r100_mm_wreg(rdev, (0x7894), (tmp), 0);
214 break;
215 case ENCODER_OBJECT_ID_INTERNAL_LVTM10x0F:
216 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp)r100_mm_wreg(rdev, (0x7a94), (tmp), 0);
217 break;
218 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
219 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp)r100_mm_wreg(rdev, (0x7988), (tmp), 0);
220 break;
221 case ENCODER_OBJECT_ID_INTERNAL_DDI0x19:
222 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp)r100_mm_wreg(rdev, (0x7214), (tmp), 0);
223 break;
224 default:
225 break;
226 }
227}
228
229void rs600_pm_misc(struct radeon_device *rdev)
230{
231 int requested_index = rdev->pm.requested_power_state_index;
232 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
233 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
234 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
235 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
236
237 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
238 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT0x00000004L) {
239 tmp = RREG32(voltage->gpio.reg)r100_mm_rreg(rdev, (voltage->gpio.reg), 0);
240 if (voltage->active_high)
241 tmp |= voltage->gpio.mask;
242 else
243 tmp &= ~(voltage->gpio.mask);
244 WREG32(voltage->gpio.reg, tmp)r100_mm_wreg(rdev, (voltage->gpio.reg), (tmp), 0);
245 if (voltage->delay)
246 udelay(voltage->delay);
247 } else {
248 tmp = RREG32(voltage->gpio.reg)r100_mm_rreg(rdev, (voltage->gpio.reg), 0);
249 if (voltage->active_high)
250 tmp &= ~voltage->gpio.mask;
251 else
252 tmp |= voltage->gpio.mask;
253 WREG32(voltage->gpio.reg, tmp)r100_mm_wreg(rdev, (voltage->gpio.reg), (tmp), 0);
254 if (voltage->delay)
255 udelay(voltage->delay);
256 }
257 } else if (voltage->type == VOLTAGE_VDDC)
258 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC1);
259
260 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH)rdev->pll_rreg(rdev, (0xc));
261 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf)((0xf) << 8);
262 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf)((0xf) << 12);
263 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN0x00000100L) {
264 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_20x00800000L) {
265 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2)((2) << 8);
266 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2)((2) << 12);
267 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_40x01000000L) {
268 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4)((4) << 8);
269 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4)((4) << 12);
270 }
271 } else {
272 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1)((1) << 8);
273 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1)((1) << 12);
274 }
275 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length)rdev->pll_wreg(rdev, (0xc), (dyn_pwrmgt_sclk_length));
276
277 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL)rdev->pll_rreg(rdev, (0xe));
278 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN0x00000200L) {
279 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP(1 << 0);
280 if (voltage->delay) {
281 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC(1 << 2);
282 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay)((voltage->delay) << 3);
283 } else
284 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC(1 << 2);
285 } else
286 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP(1 << 0);
287 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl)rdev->pll_wreg(rdev, (0xe), (dyn_sclk_vol_cntl));
288
289 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL)rdev->pll_rreg(rdev, (0x10));
290 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN0x02000000L)
291 hdp_dyn_cntl &= ~HDP_FORCEON(1 << 0);
292 else
293 hdp_dyn_cntl |= HDP_FORCEON(1 << 0);
294 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl)rdev->pll_wreg(rdev, (0x10), (hdp_dyn_cntl));
295#if 0
296 /* mc_host_dyn seems to cause hangs from time to time */
297 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL)rdev->pll_rreg(rdev, (0x1e));
298 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN0x04000000L)
299 mc_host_dyn_cntl &= ~MC_HOST_FORCEON(1 << 0);
300 else
301 mc_host_dyn_cntl |= MC_HOST_FORCEON(1 << 0);
302 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl)rdev->pll_wreg(rdev, (0x1e), (mc_host_dyn_cntl));
303#endif
304 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL)rdev->pll_rreg(rdev, (0x29));
305 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN0x00000004L)
306 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN(1 << 0);
307 else
308 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN(1 << 0);
309 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl)rdev->pll_wreg(rdev, (0x29), (dyn_backbias_cntl));
310
311 /* set pcie lanes */
312 if ((rdev->flags & RADEON_IS_PCIE) &&
313 !(rdev->flags & RADEON_IS_IGP) &&
314 rdev->asic->pm.set_pcie_lanes &&
315 (ps->pcie_lanes !=
316 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
317 radeon_set_pcie_lanes(rdev,(rdev)->asic->pm.set_pcie_lanes((rdev), (ps->pcie_lanes
))
318 ps->pcie_lanes)(rdev)->asic->pm.set_pcie_lanes((rdev), (ps->pcie_lanes
));
319 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes)___drm_dbg(((void *)0), DRM_UT_CORE, "Setting: p: %d\n", ps->
pcie_lanes);
320 }
321}
322
323void rs600_pm_prepare(struct radeon_device *rdev)
324{
325 struct drm_device *ddev = rdev->ddev;
326 struct drm_crtc *crtc;
327 struct radeon_crtc *radeon_crtc;
328 u32 tmp;
329
330 /* disable any active CRTCs */
331 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
) *__mptr = ((&ddev->mode_config.crtc_list)->next)
; (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&ddev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
);})) {
332 radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );});
333 if (radeon_crtc->enabled) {
334 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset)r100_mm_rreg(rdev, (0x6080 + radeon_crtc->crtc_offset), 0);
335 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE(1 << 24);
336 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp)r100_mm_wreg(rdev, (0x6080 + radeon_crtc->crtc_offset), (tmp
), 0);
337 }
338 }
339}
340
341void rs600_pm_finish(struct radeon_device *rdev)
342{
343 struct drm_device *ddev = rdev->ddev;
344 struct drm_crtc *crtc;
345 struct radeon_crtc *radeon_crtc;
346 u32 tmp;
347
348 /* enable any active CRTCs */
349 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
) *__mptr = ((&ddev->mode_config.crtc_list)->next)
; (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&ddev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
);})) {
350 radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
= (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );});
351 if (radeon_crtc->enabled) {
352 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset)r100_mm_rreg(rdev, (0x6080 + radeon_crtc->crtc_offset), 0);
353 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE(1 << 24);
354 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp)r100_mm_wreg(rdev, (0x6080 + radeon_crtc->crtc_offset), (tmp
), 0);
355 }
356 }
357}
358
359/* hpd for digital panel detect/disconnect */
360bool_Bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
361{
362 u32 tmp;
363 bool_Bool connected = false0;
364
365 switch (hpd) {
366 case RADEON_HPD_1:
367 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS)r100_mm_rreg(rdev, (0x007D04), 0);
368 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)(((tmp) >> 1) & 0x1))
369 connected = true1;
370 break;
371 case RADEON_HPD_2:
372 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS)r100_mm_rreg(rdev, (0x007D14), 0);
373 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)(((tmp) >> 1) & 0x1))
374 connected = true1;
375 break;
376 default:
377 break;
378 }
379 return connected;
380}
381
382void rs600_hpd_set_polarity(struct radeon_device *rdev,
383 enum radeon_hpd_id hpd)
384{
385 u32 tmp;
386 bool_Bool connected = rs600_hpd_sense(rdev, hpd);
387
388 switch (hpd) {
389 case RADEON_HPD_1:
390 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL)r100_mm_rreg(rdev, (0x007D08), 0);
391 if (connected)
392 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1)(((1) & 0x1) << 8);
393 else
394 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1)(((1) & 0x1) << 8);
395 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x007D08), (tmp), 0);
396 break;
397 case RADEON_HPD_2:
398 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL)r100_mm_rreg(rdev, (0x007D18), 0);
399 if (connected)
400 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1)(((1) & 0x1) << 8);
401 else
402 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1)(((1) & 0x1) << 8);
403 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x007D18), (tmp), 0);
404 break;
405 default:
406 break;
407 }
408}
409
410void rs600_hpd_init(struct radeon_device *rdev)
411{
412 struct drm_device *dev = rdev->ddev;
413 struct drm_connector *connector;
414 unsigned enable = 0;
415
416 list_for_each_entry(connector, &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
(&dev->mode_config.connector_list); connector = ({ const
__typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*connector), head) );})) {
417 struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
- __builtin_offsetof(struct radeon_connector, base) );});
418 switch (radeon_connector->hpd.hpd) {
419 case RADEON_HPD_1:
420 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,r100_mm_wreg(rdev, (0x007D00), ((((1) & 0x1) << 0))
, 0)
421 S_007D00_DC_HOT_PLUG_DETECT1_EN(1))r100_mm_wreg(rdev, (0x007D00), ((((1) & 0x1) << 0))
, 0);
422 break;
423 case RADEON_HPD_2:
424 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,r100_mm_wreg(rdev, (0x007D10), ((((1) & 0x1) << 0))
, 0)
425 S_007D10_DC_HOT_PLUG_DETECT2_EN(1))r100_mm_wreg(rdev, (0x007D10), ((((1) & 0x1) << 0))
, 0);
426 break;
427 default:
428 break;
429 }
430 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
431 enable |= 1 << radeon_connector->hpd.hpd;
432 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd)(rdev)->asic->hpd.set_polarity((rdev), (radeon_connector
->hpd.hpd));
433 }
434 radeon_irq_kms_enable_hpd(rdev, enable);
435}
436
437void rs600_hpd_fini(struct radeon_device *rdev)
438{
439 struct drm_device *dev = rdev->ddev;
440 struct drm_connector *connector;
441 unsigned disable = 0;
442
443 list_for_each_entry(connector, &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
(&dev->mode_config.connector_list); connector = ({ const
__typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*connector), head) );})) {
444 struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
- __builtin_offsetof(struct radeon_connector, base) );});
445 switch (radeon_connector->hpd.hpd) {
446 case RADEON_HPD_1:
447 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,r100_mm_wreg(rdev, (0x007D00), ((((0) & 0x1) << 0))
, 0)
448 S_007D00_DC_HOT_PLUG_DETECT1_EN(0))r100_mm_wreg(rdev, (0x007D00), ((((0) & 0x1) << 0))
, 0);
449 break;
450 case RADEON_HPD_2:
451 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,r100_mm_wreg(rdev, (0x007D10), ((((0) & 0x1) << 0))
, 0)
452 S_007D10_DC_HOT_PLUG_DETECT2_EN(0))r100_mm_wreg(rdev, (0x007D10), ((((0) & 0x1) << 0))
, 0);
453 break;
454 default:
455 break;
456 }
457 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
458 disable |= 1 << radeon_connector->hpd.hpd;
459 }
460 radeon_irq_kms_disable_hpd(rdev, disable);
461}
462
463int rs600_asic_reset(struct radeon_device *rdev, bool_Bool hard)
464{
465 struct rv515_mc_save save;
466 u32 status, tmp;
467 int ret = 0;
468
469 status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
470 if (!G_000E40_GUI_ACTIVE(status)(((status) >> 31) & 0x1)) {
471 return 0;
472 }
473 /* Stops all mc clients */
474 rv515_mc_stop(rdev, &save);
475 status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
476 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status)do { } while(0);
477 /* stop CP */
478 WREG32(RADEON_CP_CSQ_CNTL, 0)r100_mm_wreg(rdev, (0x0740), (0), 0);
479 tmp = RREG32(RADEON_CP_RB_CNTL)r100_mm_rreg(rdev, (0x0704), 0);
480 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA)r100_mm_wreg(rdev, (0x0704), (tmp | (1 << 31)), 0);
481 WREG32(RADEON_CP_RB_RPTR_WR, 0)r100_mm_wreg(rdev, (0x071c), (0), 0);
482 WREG32(RADEON_CP_RB_WPTR, 0)r100_mm_wreg(rdev, (0x0714), (0), 0);
483 WREG32(RADEON_CP_RB_CNTL, tmp)r100_mm_wreg(rdev, (0x0704), (tmp), 0);
484 pci_save_state(rdev->pdev);
485 /* disable bus mastering */
486 pci_clear_master(rdev->pdev);
487 mdelay(1);
488 /* reset GA+VAP */
489 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 2) |
(((1) & 0x1) << 13)), 0)
490 S_0000F0_SOFT_RESET_GA(1))r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 2) |
(((1) & 0x1) << 13)), 0);
491 RREG32(R_0000F0_RBBM_SOFT_RESET)r100_mm_rreg(rdev, (0x0000F0), 0);
492 mdelay(500);
493 WREG32(R_0000F0_RBBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0x0000F0), (0), 0);
494 mdelay(1);
495 status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
496 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status)do { } while(0);
497 /* reset CP */
498 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1))r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 0))
, 0);
499 RREG32(R_0000F0_RBBM_SOFT_RESET)r100_mm_rreg(rdev, (0x0000F0), 0);
500 mdelay(500);
501 WREG32(R_0000F0_RBBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0x0000F0), (0), 0);
502 mdelay(1);
503 status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
504 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status)do { } while(0);
505 /* reset MC */
506 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1))r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 8))
, 0);
507 RREG32(R_0000F0_RBBM_SOFT_RESET)r100_mm_rreg(rdev, (0x0000F0), 0);
508 mdelay(500);
509 WREG32(R_0000F0_RBBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0x0000F0), (0), 0);
510 mdelay(1);
511 status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
512 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status)do { } while(0);
513 /* restore PCI & busmastering */
514 pci_restore_state(rdev->pdev);
515 /* Check if GPU is idle */
516 if (G_000E40_GA_BUSY(status)(((status) >> 26) & 0x1) || G_000E40_VAP_BUSY(status)(((status) >> 20) & 0x1)) {
517 dev_err(rdev->dev, "failed to reset GPU\n")printf("drm:pid%d:%s *ERROR* " "failed to reset GPU\n", ({struct
cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__);
518 ret = -1;
519 } else
520 dev_info(rdev->dev, "GPU reset succeed\n")do { } while(0);
521 rv515_mc_resume(rdev, &save);
522 return ret;
523}
524
525/*
526 * GART.
527 */
528void rs600_gart_tlb_flush(struct radeon_device *rdev)
529{
530 uint32_t tmp;
531
532 tmp = RREG32_MC(R_000100_MC_PT0_CNTL)rdev->mc_rreg(rdev, (0x000100));
533 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS0xEFFFFFFF & C_000100_INVALIDATE_L2_CACHE0xDFFFFFFF;
534 WREG32_MC(R_000100_MC_PT0_CNTL, tmp)rdev->mc_wreg(rdev, (0x000100), (tmp));
535
536 tmp = RREG32_MC(R_000100_MC_PT0_CNTL)rdev->mc_rreg(rdev, (0x000100));
537 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1)(((1) & 0x1) << 28) | S_000100_INVALIDATE_L2_CACHE(1)(((1) & 0x1) << 29);
538 WREG32_MC(R_000100_MC_PT0_CNTL, tmp)rdev->mc_wreg(rdev, (0x000100), (tmp));
539
540 tmp = RREG32_MC(R_000100_MC_PT0_CNTL)rdev->mc_rreg(rdev, (0x000100));
541 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS0xEFFFFFFF & C_000100_INVALIDATE_L2_CACHE0xDFFFFFFF;
542 WREG32_MC(R_000100_MC_PT0_CNTL, tmp)rdev->mc_wreg(rdev, (0x000100), (tmp));
543 tmp = RREG32_MC(R_000100_MC_PT0_CNTL)rdev->mc_rreg(rdev, (0x000100));
Value stored to 'tmp' is never read
544}
545
546static int rs600_gart_init(struct radeon_device *rdev)
547{
548 int r;
549
550 if (rdev->gart.robj) {
551 WARN(1, "RS600 GART already initialized\n")({ int __ret = !!(1); if (__ret) printf("RS600 GART already initialized\n"
); __builtin_expect(!!(__ret), 0); });
552 return 0;
553 }
554 /* Initialize common gart structure */
555 r = radeon_gart_init(rdev);
556 if (r) {
557 return r;
558 }
559 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
560 return radeon_gart_table_vram_alloc(rdev);
561}
562
563static int rs600_gart_enable(struct radeon_device *rdev)
564{
565 u32 tmp;
566 int r, i;
567
568 if (rdev->gart.robj == NULL((void *)0)) {
569 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n")printf("drm:pid%d:%s *ERROR* " "No VRAM object for PCIE GART.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
570 return -EINVAL22;
571 }
572 r = radeon_gart_table_vram_pin(rdev);
573 if (r)
574 return r;
575 /* Enable bus master */
576 tmp = RREG32(RADEON_BUS_CNTL)r100_mm_rreg(rdev, (0x0030), 0) & ~RS600_BUS_MASTER_DIS(1 << 14);
577 WREG32(RADEON_BUS_CNTL, tmp)r100_mm_wreg(rdev, (0x0030), (tmp), 0);
578 /* FIXME: setup default page */
579 WREG32_MC(R_000100_MC_PT0_CNTL,rdev->mc_wreg(rdev, (0x000100), (((((6) & 0x7) <<
15) | (((6) & 0x7) << 21))))
580 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |rdev->mc_wreg(rdev, (0x000100), (((((6) & 0x7) <<
15) | (((6) & 0x7) << 21))))
581 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)))rdev->mc_wreg(rdev, (0x000100), (((((6) & 0x7) <<
15) | (((6) & 0x7) << 21))));
582
583 for (i = 0; i < 19; i++) {
584 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)))
585 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)))
586 S_00016C_SYSTEM_ACCESS_MODE_MASK(rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)))
587 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)))
588 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)))
589 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)))
590 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)))
591 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)))
592 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3))rdev->mc_wreg(rdev, (0x00016C + i), ((((1) & 0x1) <<
0) | (((3) & 0x3) << 8) | (((0) & 0x1) <<
10) | (((3) & 0x7) << 11) | (((1) & 0x1) <<
14) | (((3) & 0x7) << 15)));
593 }
594 /* enable first context */
595 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,rdev->mc_wreg(rdev, (0x000102), ((((1) & 0x1) <<
0) | (((0) & 0x3) << 1)))
596 S_000102_ENABLE_PAGE_TABLE(1) |rdev->mc_wreg(rdev, (0x000102), ((((1) & 0x1) <<
0) | (((0) & 0x3) << 1)))
597 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT))rdev->mc_wreg(rdev, (0x000102), ((((1) & 0x1) <<
0) | (((0) & 0x3) << 1)));
598
599 /* disable all other contexts */
600 for (i = 1; i < 8; i++)
601 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0)rdev->mc_wreg(rdev, (0x000102 + i), (0));
602
603 /* setup the page table */
604 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,rdev->mc_wreg(rdev, (0x00012C), (rdev->gart.table_addr)
)
605 rdev->gart.table_addr)rdev->mc_wreg(rdev, (0x00012C), (rdev->gart.table_addr)
);
606 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start)rdev->mc_wreg(rdev, (0x00013C), (rdev->mc.gtt_start));
607 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end)rdev->mc_wreg(rdev, (0x00014C), (rdev->mc.gtt_end));
608 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0)rdev->mc_wreg(rdev, (0x00011C), (0));
609
610 /* System context maps to VRAM space */
611 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start)rdev->mc_wreg(rdev, (0x000112), (rdev->mc.vram_start));
612 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end)rdev->mc_wreg(rdev, (0x000114), (rdev->mc.vram_end));
613
614 /* enable page tables */
615 tmp = RREG32_MC(R_000100_MC_PT0_CNTL)rdev->mc_rreg(rdev, (0x000100));
616 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)))rdev->mc_wreg(rdev, (0x000100), ((tmp | (((1) & 0x1) <<
0))));
617 tmp = RREG32_MC(R_000009_MC_CNTL1)rdev->mc_rreg(rdev, (0x000009));
618 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)))rdev->mc_wreg(rdev, (0x000009), ((tmp | (((1) & 0x1) <<
26))));
619 rs600_gart_tlb_flush(rdev);
620 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
long)rdev->gart.table_addr)
621 (unsigned)(rdev->mc.gtt_size >> 20),printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
long)rdev->gart.table_addr)
622 (unsigned long long)rdev->gart.table_addr)printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
long)rdev->gart.table_addr);
623 rdev->gart.ready = true1;
624 return 0;
625}
626
627static void rs600_gart_disable(struct radeon_device *rdev)
628{
629 u32 tmp;
630
631 /* FIXME: disable out of gart access */
632 WREG32_MC(R_000100_MC_PT0_CNTL, 0)rdev->mc_wreg(rdev, (0x000100), (0));
633 tmp = RREG32_MC(R_000009_MC_CNTL1)rdev->mc_rreg(rdev, (0x000009));
634 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES)rdev->mc_wreg(rdev, (0x000009), (tmp & 0xFBFFFFFF));
635 radeon_gart_table_vram_unpin(rdev);
636}
637
638static void rs600_gart_fini(struct radeon_device *rdev)
639{
640 radeon_gart_fini(rdev);
641 rs600_gart_disable(rdev);
642 radeon_gart_table_vram_free(rdev);
643}
644
645uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
646{
647 addr = addr & 0xFFFFFFFFFFFFF000ULL;
648 addr |= R600_PTE_SYSTEM(1 << 1);
649 if (flags & RADEON_GART_PAGE_VALID(1 << 0))
650 addr |= R600_PTE_VALID(1 << 0);
651 if (flags & RADEON_GART_PAGE_READ(1 << 1))
652 addr |= R600_PTE_READABLE(1 << 5);
653 if (flags & RADEON_GART_PAGE_WRITE(1 << 2))
654 addr |= R600_PTE_WRITEABLE(1 << 6);
655 if (flags & RADEON_GART_PAGE_SNOOP(1 << 3))
656 addr |= R600_PTE_SNOOPED(1 << 2);
657 return addr;
658}
659
660void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
661 uint64_t entry)
662{
663 void __iomem *ptr = (void *)rdev->gart.ptr;
664 writeq(entry, ptr + (i * 8))iowrite64(entry, ptr + (i * 8));
665}
666
667int rs600_irq_set(struct radeon_device *rdev)
668{
669 uint32_t tmp = 0;
670 uint32_t mode_int = 0;
671 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL)r100_mm_rreg(rdev, (0x007D08), 0) &
672 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1)(((1) & 0x1) << 16);
673 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL)r100_mm_rreg(rdev, (0x007D18), 0) &
674 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1)(((1) & 0x1) << 16);
675 u32 hdmi0;
676 if (ASIC_IS_DCE2(rdev)((rdev->family == CHIP_RS600) || (rdev->family == CHIP_RS690
) || (rdev->family == CHIP_RS740) || (rdev->family >=
CHIP_R600)))
677 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x007408), 0) &
678 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1)(((1) & 0x1) << 28);
679 else
680 hdmi0 = 0;
681
682 if (!rdev->irq.installed) {
683 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n")({ int __ret = !!(1); if (__ret) printf("Can't enable IRQ/MSI because no handler is installed\n"
); __builtin_expect(!!(__ret), 0); });
684 WREG32(R_000040_GEN_INT_CNTL, 0)r100_mm_wreg(rdev, (0x000040), (0), 0);
685 return -EINVAL22;
686 }
687 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])({ typeof(*(&rdev->irq.ring_int[0])) __tmp = *(volatile
typeof(*(&rdev->irq.ring_int[0])) *)&(*(&rdev
->irq.ring_int[0])); membar_datadep_consumer(); __tmp; })) {
688 tmp |= S_000040_SW_INT_EN(1)(((1) & 0x1) << 25);
689 }
690 if (rdev->irq.crtc_vblank_int[0] ||
691 atomic_read(&rdev->irq.pflip[0])({ typeof(*(&rdev->irq.pflip[0])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[0])) *)&(*(&rdev->irq.pflip
[0])); membar_datadep_consumer(); __tmp; })) {
692 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1)(((1) & 0x1) << 0);
693 }
694 if (rdev->irq.crtc_vblank_int[1] ||
695 atomic_read(&rdev->irq.pflip[1])({ typeof(*(&rdev->irq.pflip[1])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[1])) *)&(*(&rdev->irq.pflip
[1])); membar_datadep_consumer(); __tmp; })) {
696 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1)(((1) & 0x1) << 8);
697 }
698 if (rdev->irq.hpd[0]) {
699 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1)(((1) & 0x1) << 16);
700 }
701 if (rdev->irq.hpd[1]) {
702 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1)(((1) & 0x1) << 16);
703 }
704 if (rdev->irq.afmt[0]) {
705 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1)(((1) & 0x1) << 28);
706 }
707 WREG32(R_000040_GEN_INT_CNTL, tmp)r100_mm_wreg(rdev, (0x000040), (tmp), 0);
708 WREG32(R_006540_DxMODE_INT_MASK, mode_int)r100_mm_wreg(rdev, (0x006540), (mode_int), 0);
709 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1)r100_mm_wreg(rdev, (0x007D08), (hpd1), 0);
710 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2)r100_mm_wreg(rdev, (0x007D18), (hpd2), 0);
711 if (ASIC_IS_DCE2(rdev)((rdev->family == CHIP_RS600) || (rdev->family == CHIP_RS690
) || (rdev->family == CHIP_RS740) || (rdev->family >=
CHIP_R600)))
712 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0)r100_mm_wreg(rdev, (0x007408), (hdmi0), 0);
713
714 /* posting read */
715 RREG32(R_000040_GEN_INT_CNTL)r100_mm_rreg(rdev, (0x000040), 0);
716
717 return 0;
718}
719
720static inline u32 rs600_irq_ack(struct radeon_device *rdev)
721{
722 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS)r100_mm_rreg(rdev, (0x000044), 0);
723 uint32_t irq_mask = S_000044_SW_INT(1)(((1) & 0x1) << 25);
724 u32 tmp;
725
726 if (G_000044_DISPLAY_INT_STAT(irqs)(((irqs) >> 0) & 0x1)) {
727 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS)r100_mm_rreg(rdev, (0x007EDC), 0);
728 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)(((rdev->irq.stat_regs.r500.disp_int) >> 4) & 0x1
)) {
729 WREG32(R_006534_D1MODE_VBLANK_STATUS,r100_mm_wreg(rdev, (0x006534), ((((1) & 0x1) << 4))
, 0)
730 S_006534_D1MODE_VBLANK_ACK(1))r100_mm_wreg(rdev, (0x006534), ((((1) & 0x1) << 4))
, 0);
731 }
732 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)(((rdev->irq.stat_regs.r500.disp_int) >> 5) & 0x1
)) {
733 WREG32(R_006D34_D2MODE_VBLANK_STATUS,r100_mm_wreg(rdev, (0x006D34), ((((1) & 0x1) << 4))
, 0)
734 S_006D34_D2MODE_VBLANK_ACK(1))r100_mm_wreg(rdev, (0x006D34), ((((1) & 0x1) << 4))
, 0);
735 }
736 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)(((rdev->irq.stat_regs.r500.disp_int) >> 18) & 0x1
)) {
737 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL)r100_mm_rreg(rdev, (0x007D08), 0);
738 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1)(((1) & 0x1) << 0);
739 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x007D08), (tmp), 0);
740 }
741 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)(((rdev->irq.stat_regs.r500.disp_int) >> 19) & 0x1
)) {
742 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL)r100_mm_rreg(rdev, (0x007D18), 0);
743 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1)(((1) & 0x1) << 0);
744 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp)r100_mm_wreg(rdev, (0x007D18), (tmp), 0);
745 }
746 } else {
747 rdev->irq.stat_regs.r500.disp_int = 0;
748 }
749
750 if (ASIC_IS_DCE2(rdev)((rdev->family == CHIP_RS600) || (rdev->family == CHIP_RS690
) || (rdev->family == CHIP_RS740) || (rdev->family >=
CHIP_R600))) {
751 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS)r100_mm_rreg(rdev, (0x007404), 0) &
752 S_007404_HDMI0_AZ_FORMAT_WTRIG(1)(((1) & 0x1) << 28);
753 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)(((rdev->irq.stat_regs.r500.hdmi0_status) >> 28) &
0x1)) {
754 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x007408), 0);
755 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1)(((1) & 0x1) << 29);
756 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp)r100_mm_wreg(rdev, (0x007408), (tmp), 0);
757 }
758 } else
759 rdev->irq.stat_regs.r500.hdmi0_status = 0;
760
761 if (irqs) {
762 WREG32(R_000044_GEN_INT_STATUS, irqs)r100_mm_wreg(rdev, (0x000044), (irqs), 0);
763 }
764 return irqs & irq_mask;
765}
766
767void rs600_irq_disable(struct radeon_device *rdev)
768{
769 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL)r100_mm_rreg(rdev, (0x007408), 0) &
770 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1)(((1) & 0x1) << 28);
771 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0)r100_mm_wreg(rdev, (0x007408), (hdmi0), 0);
772 WREG32(R_000040_GEN_INT_CNTL, 0)r100_mm_wreg(rdev, (0x000040), (0), 0);
773 WREG32(R_006540_DxMODE_INT_MASK, 0)r100_mm_wreg(rdev, (0x006540), (0), 0);
774 /* Wait and acknowledge irq */
775 mdelay(1);
776 rs600_irq_ack(rdev);
777}
778
779int rs600_irq_process(struct radeon_device *rdev)
780{
781 u32 status, msi_rearm;
782 bool_Bool queue_hotplug = false0;
783 bool_Bool queue_hdmi = false0;
784
785 status = rs600_irq_ack(rdev);
786 if (!status &&
787 !rdev->irq.stat_regs.r500.disp_int &&
788 !rdev->irq.stat_regs.r500.hdmi0_status) {
789 return IRQ_NONE;
790 }
791 while (status ||
792 rdev->irq.stat_regs.r500.disp_int ||
793 rdev->irq.stat_regs.r500.hdmi0_status) {
794 /* SW interrupt */
795 if (G_000044_SW_INT(status)(((status) >> 25) & 0x1)) {
796 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX0);
797 }
798 /* Vertical blank interrupts */
799 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)(((rdev->irq.stat_regs.r500.disp_int) >> 4) & 0x1
)) {
800 if (rdev->irq.crtc_vblank_int[0]) {
801 drm_handle_vblank(rdev->ddev, 0);
802 rdev->pm.vblank_sync = true1;
803 wake_up(&rdev->irq.vblank_queue);
804 }
805 if (atomic_read(&rdev->irq.pflip[0])({ typeof(*(&rdev->irq.pflip[0])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[0])) *)&(*(&rdev->irq.pflip
[0])); membar_datadep_consumer(); __tmp; }))
806 radeon_crtc_handle_vblank(rdev, 0);
807 }
808 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)(((rdev->irq.stat_regs.r500.disp_int) >> 5) & 0x1
)) {
809 if (rdev->irq.crtc_vblank_int[1]) {
810 drm_handle_vblank(rdev->ddev, 1);
811 rdev->pm.vblank_sync = true1;
812 wake_up(&rdev->irq.vblank_queue);
813 }
814 if (atomic_read(&rdev->irq.pflip[1])({ typeof(*(&rdev->irq.pflip[1])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[1])) *)&(*(&rdev->irq.pflip
[1])); membar_datadep_consumer(); __tmp; }))
815 radeon_crtc_handle_vblank(rdev, 1);
816 }
817 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)(((rdev->irq.stat_regs.r500.disp_int) >> 18) & 0x1
)) {
818 queue_hotplug = true1;
819 DRM_DEBUG("HPD1\n")___drm_dbg(((void *)0), DRM_UT_CORE, "HPD1\n");
820 }
821 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)(((rdev->irq.stat_regs.r500.disp_int) >> 19) & 0x1
)) {
822 queue_hotplug = true1;
823 DRM_DEBUG("HPD2\n")___drm_dbg(((void *)0), DRM_UT_CORE, "HPD2\n");
824 }
825 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)(((rdev->irq.stat_regs.r500.hdmi0_status) >> 28) &
0x1)) {
826 queue_hdmi = true1;
827 DRM_DEBUG("HDMI0\n")___drm_dbg(((void *)0), DRM_UT_CORE, "HDMI0\n");
828 }
829 status = rs600_irq_ack(rdev);
830 }
831 if (queue_hotplug)
832 schedule_delayed_work(&rdev->hotplug_work, 0);
833 if (queue_hdmi)
834 schedule_work(&rdev->audio_work);
835 if (rdev->msi_enabled) {
836 switch (rdev->family) {
837 case CHIP_RS600:
838 case CHIP_RS690:
839 case CHIP_RS740:
840 msi_rearm = RREG32(RADEON_BUS_CNTL)r100_mm_rreg(rdev, (0x0030), 0) & ~RS600_MSI_REARM(1 << 20);
841 WREG32(RADEON_BUS_CNTL, msi_rearm)r100_mm_wreg(rdev, (0x0030), (msi_rearm), 0);
842 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM)r100_mm_wreg(rdev, (0x0030), (msi_rearm | (1 << 20)), 0
);
843 break;
844 default:
845 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN)r100_mm_wreg(rdev, (0x0160), ((1 << 0)), 0);
846 break;
847 }
848 }
849 return IRQ_HANDLED;
850}
851
852u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
853{
854 if (crtc == 0)
855 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT)r100_mm_rreg(rdev, (0x0060A4), 0);
856 else
857 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT)r100_mm_rreg(rdev, (0x0068A4), 0);
858}
859
860int rs600_mc_wait_for_idle(struct radeon_device *rdev)
861{
862 unsigned i;
863
864 for (i = 0; i < rdev->usec_timeout; i++) {
865 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))(((rdev->mc_rreg(rdev, (0x000000))) >> 0) & 0x1))
866 return 0;
867 udelay(1);
868 }
869 return -1;
870}
871
872static void rs600_gpu_init(struct radeon_device *rdev)
873{
874 r420_pipes_init(rdev);
875 /* Wait for mc idle */
876 if (rs600_mc_wait_for_idle(rdev))
877 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n")printf("drm:pid%d:%s *WARNING* " "Wait MC idle timeout before updating MC.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
878}
879
880static void rs600_mc_init(struct radeon_device *rdev)
881{
882 u64 base;
883
884 rdev->mc.aper_base = rdev->fb_aper_offset;
885 rdev->mc.aper_size = rdev->fb_aper_size;
886 rdev->mc.vram_is_ddr = true1;
887 rdev->mc.vram_width = 128;
888 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE)r100_mm_rreg(rdev, (0x00f8), 0);
889 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
890 rdev->mc.visible_vram_size = rdev->mc.aper_size;
891 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
892 base = RREG32_MC(R_000004_MC_FB_LOCATION)rdev->mc_rreg(rdev, (0x000004));
893 base = G_000004_MC_FB_START(base)(((base) >> 0) & 0xFFFF) << 16;
894 radeon_vram_location(rdev, &rdev->mc, base);
895 rdev->mc.gtt_base_align = 0;
896 radeon_gtt_location(rdev, &rdev->mc);
897 radeon_update_bandwidth_info(rdev);
898}
899
900void rs600_bandwidth_update(struct radeon_device *rdev)
901{
902 struct drm_display_mode *mode0 = NULL((void *)0);
903 struct drm_display_mode *mode1 = NULL((void *)0);
904 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
905 /* FIXME: implement full support */
906
907 if (!rdev->mode_info.mode_config_initialized)
908 return;
909
910 radeon_update_display_priority(rdev);
911
912 if (rdev->mode_info.crtcs[0]->base.enabled)
913 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
914 if (rdev->mode_info.crtcs[1]->base.enabled)
915 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
916
917 rs690_line_buffer_adjust(rdev, mode0, mode1);
918
919 if (rdev->disp_priority == 2) {
920 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT)r100_mm_rreg(rdev, (0x006548), 0);
921 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT)r100_mm_rreg(rdev, (0x006D48), 0);
922 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1)(((1) & 0x1) << 20);
923 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1)(((1) & 0x1) << 20);
924 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt)r100_mm_wreg(rdev, (0x006548), (d1mode_priority_a_cnt), 0);
925 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt)r100_mm_wreg(rdev, (0x00654C), (d1mode_priority_a_cnt), 0);
926 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt)r100_mm_wreg(rdev, (0x006D48), (d2mode_priority_a_cnt), 0);
927 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt)r100_mm_wreg(rdev, (0x006D4C), (d2mode_priority_a_cnt), 0);
928 }
929}
930
931uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
932{
933 unsigned long flags;
934 u32 r;
935
936 spin_lock_irqsave(&rdev->mc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mc_idx_lock); } while
(0);
937 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |r100_mm_wreg(rdev, (0x000070), ((((reg) & 0xFFFF) <<
0) | (((1) & 0x1) << 21)), 0)
938 S_000070_MC_IND_CITF_ARB0(1))r100_mm_wreg(rdev, (0x000070), ((((reg) & 0xFFFF) <<
0) | (((1) & 0x1) << 21)), 0);
939 r = RREG32(R_000074_MC_IND_DATA)r100_mm_rreg(rdev, (0x000074), 0);
940 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mc_idx_lock); } while
(0);
941 return r;
942}
943
944void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
945{
946 unsigned long flags;
947
948 spin_lock_irqsave(&rdev->mc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mc_idx_lock); } while
(0);
949 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |r100_mm_wreg(rdev, (0x000070), ((((reg) & 0xFFFF) <<
0) | (((1) & 0x1) << 21) | (((1) & 0x1) <<
23)), 0)
950 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1))r100_mm_wreg(rdev, (0x000070), ((((reg) & 0xFFFF) <<
0) | (((1) & 0x1) << 21) | (((1) & 0x1) <<
23)), 0);
951 WREG32(R_000074_MC_IND_DATA, v)r100_mm_wreg(rdev, (0x000074), (v), 0);
952 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mc_idx_lock); } while
(0);
953}
954
955void rs600_set_safe_registers(struct radeon_device *rdev)
956{
957 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
958 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm)(sizeof((rs600_reg_safe_bm)) / sizeof((rs600_reg_safe_bm)[0])
);
959}
960
961static void rs600_mc_program(struct radeon_device *rdev)
962{
963 struct rv515_mc_save save;
964
965 /* Stops all mc clients */
966 rv515_mc_stop(rdev, &save);
967
968 /* Wait for mc idle */
969 if (rs600_mc_wait_for_idle(rdev))
970 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n")printf("drm:pid%d:%s *WARNING* " "Wait MC idle timeout before updating MC.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
971
972 /* FIXME: What does AGP means for such chipset ? */
973 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF)rdev->mc_wreg(rdev, (0x000005), (0x0FFFFFFF));
974 WREG32_MC(R_000006_AGP_BASE, 0)rdev->mc_wreg(rdev, (0x000006), (0));
975 WREG32_MC(R_000007_AGP_BASE_2, 0)rdev->mc_wreg(rdev, (0x000007), (0));
976 /* Program MC */
977 WREG32_MC(R_000004_MC_FB_LOCATION,rdev->mc_wreg(rdev, (0x000004), ((((rdev->mc.vram_start
>> 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end
>> 16) & 0xFFFF) << 16)))
978 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |rdev->mc_wreg(rdev, (0x000004), ((((rdev->mc.vram_start
>> 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end
>> 16) & 0xFFFF) << 16)))
979 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16))rdev->mc_wreg(rdev, (0x000004), ((((rdev->mc.vram_start
>> 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end
>> 16) & 0xFFFF) << 16)));
980 WREG32(R_000134_HDP_FB_LOCATION,r100_mm_wreg(rdev, (0x000134), ((((rdev->mc.vram_start >>
16) & 0xFFFF) << 0)), 0)
981 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16))r100_mm_wreg(rdev, (0x000134), ((((rdev->mc.vram_start >>
16) & 0xFFFF) << 0)), 0);
982
983 rv515_mc_resume(rdev, &save);
984}
985
986static int rs600_startup(struct radeon_device *rdev)
987{
988 int r;
989
990 rs600_mc_program(rdev);
991 /* Resume clock */
992 rv515_clock_startup(rdev);
993 /* Initialize GPU configuration (# pipes, ...) */
994 rs600_gpu_init(rdev);
995 /* Initialize GART (initialize after TTM so we can allocate
996 * memory through TTM but finalize after TTM) */
997 r = rs600_gart_enable(rdev);
998 if (r)
999 return r;
1000
1001 /* allocate wb buffer */
1002 r = radeon_wb_init(rdev);
1003 if (r)
1004 return r;
1005
1006 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX0);
1007 if (r) {
1008 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
1009 return r;
1010 }
1011
1012 /* Enable IRQ */
1013 if (!rdev->irq.installed) {
1014 r = radeon_irq_kms_init(rdev);
1015 if (r)
1016 return r;
1017 }
1018
1019 rs600_irq_set(rdev);
1020 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL)r100_mm_rreg(rdev, (0x0130), 0);
1021 /* 1M ring buffer */
1022 r = r100_cp_init(rdev, 1024 * 1024);
1023 if (r) {
1024 dev_err(rdev->dev, "failed initializing CP (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
1025 return r;
1026 }
1027
1028 r = radeon_ib_pool_init(rdev);
1029 if (r) {
1030 dev_err(rdev->dev, "IB initialization failed (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "IB initialization failed (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
1031 return r;
1032 }
1033
1034 r = radeon_audio_init(rdev);
1035 if (r) {
1036 dev_err(rdev->dev, "failed initializing audio\n")printf("drm:pid%d:%s *ERROR* " "failed initializing audio\n",
({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1037 return r;
1038 }
1039
1040 return 0;
1041}
1042
1043int rs600_resume(struct radeon_device *rdev)
1044{
1045 int r;
1046
1047 /* Make sur GART are not working */
1048 rs600_gart_disable(rdev);
1049 /* Resume clock before doing reset */
1050 rv515_clock_startup(rdev);
1051 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1052 if (radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0)) {
1053 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
1054 RREG32(R_000E40_RBBM_STATUS),printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
1055 RREG32(R_0007C0_CP_STAT))printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0));
1056 }
1057 /* post */
1058 atom_asic_init(rdev->mode_info.atom_context);
1059 /* Resume clock after posting */
1060 rv515_clock_startup(rdev);
1061 /* Initialize surface registers */
1062 radeon_surface_init(rdev);
1063
1064 rdev->accel_working = true1;
1065 r = rs600_startup(rdev);
1066 if (r) {
1067 rdev->accel_working = false0;
1068 }
1069 return r;
1070}
1071
1072int rs600_suspend(struct radeon_device *rdev)
1073{
1074 radeon_pm_suspend(rdev);
1075 radeon_audio_fini(rdev);
1076 r100_cp_disable(rdev);
1077 radeon_wb_disable(rdev);
1078 rs600_irq_disable(rdev);
1079 rs600_gart_disable(rdev);
1080 return 0;
1081}
1082
1083void rs600_fini(struct radeon_device *rdev)
1084{
1085 radeon_pm_fini(rdev);
1086 radeon_audio_fini(rdev);
1087 r100_cp_fini(rdev);
1088 radeon_wb_fini(rdev);
1089 radeon_ib_pool_fini(rdev);
1090 radeon_gem_fini(rdev);
1091 rs600_gart_fini(rdev);
1092 radeon_irq_kms_fini(rdev);
1093 radeon_fence_driver_fini(rdev);
1094 radeon_bo_fini(rdev);
1095 radeon_atombios_fini(rdev);
1096 kfree(rdev->bios);
1097 rdev->bios = NULL((void *)0);
1098}
1099
1100int rs600_init(struct radeon_device *rdev)
1101{
1102 int r;
1103
1104 /* Disable VGA */
1105 rv515_vga_render_disable(rdev);
1106 /* Initialize scratch registers */
1107 radeon_scratch_init(rdev);
1108 /* Initialize surface registers */
1109 radeon_surface_init(rdev);
1110 /* restore some register to sane defaults */
1111 r100_restore_sanity(rdev);
1112 /* BIOS */
1113 if (!radeon_get_bios(rdev)) {
1114 if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
1115 return -EINVAL22;
1116 }
1117 if (rdev->is_atom_bios) {
1118 r = radeon_atombios_init(rdev);
1119 if (r)
1120 return r;
1121 } else {
1122 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n")printf("drm:pid%d:%s *ERROR* " "Expecting atombios for RS600 GPU\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1123 return -EINVAL22;
1124 }
1125 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1126 if (radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0)) {
1127 dev_warn(rdev->dev,printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
1128 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
1129 RREG32(R_000E40_RBBM_STATUS),printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
1130 RREG32(R_0007C0_CP_STAT))printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0));
1131 }
1132 /* check if cards are posted or not */
1133 if (radeon_boot_test_post_card(rdev) == false0)
1134 return -EINVAL22;
1135
1136 /* Initialize clocks */
1137 radeon_get_clock_info(rdev->ddev);
1138 /* initialize memory controller */
1139 rs600_mc_init(rdev);
1140 r100_debugfs_rbbm_init(rdev);
1141 /* Fence driver */
1142 radeon_fence_driver_init(rdev);
1143 /* Memory manager */
1144 r = radeon_bo_init(rdev);
1145 if (r)
1146 return r;
1147 r = rs600_gart_init(rdev);
1148 if (r)
1149 return r;
1150 rs600_set_safe_registers(rdev);
1151
1152 /* Initialize power management */
1153 radeon_pm_init(rdev);
1154
1155 rdev->accel_working = true1;
1156 r = rs600_startup(rdev);
1157 if (r) {
1158 /* Somethings want wront with the accel init stop accel */
1159 dev_err(rdev->dev, "Disabling GPU acceleration\n")printf("drm:pid%d:%s *ERROR* " "Disabling GPU acceleration\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1160 r100_cp_fini(rdev);
1161 radeon_wb_fini(rdev);
1162 radeon_ib_pool_fini(rdev);
1163 rs600_gart_fini(rdev);
1164 radeon_irq_kms_fini(rdev);
1165 rdev->accel_working = false0;
1166 }
1167 return 0;
1168}