File: | dev/usb/if_run.c |
Warning: | line 4475, column 6 Assigned value is garbage or undefined |
Press '?' to see keyboard shortcuts
Keyboard shortcuts:
1 | /* $OpenBSD: if_run.c,v 1.138 2023/03/08 04:43:08 guenther Exp $ */ | |||
2 | ||||
3 | /*- | |||
4 | * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> | |||
5 | * Copyright (c) 2013-2014 Kevin Lo | |||
6 | * | |||
7 | * Permission to use, copy, modify, and distribute this software for any | |||
8 | * purpose with or without fee is hereby granted, provided that the above | |||
9 | * copyright notice and this permission notice appear in all copies. | |||
10 | * | |||
11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |||
12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |||
13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |||
14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |||
15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |||
16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |||
17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |||
18 | */ | |||
19 | ||||
20 | /*- | |||
21 | * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. | |||
22 | * http://www.ralinktech.com/ | |||
23 | */ | |||
24 | ||||
25 | #include "bpfilter.h" | |||
26 | ||||
27 | #include <sys/param.h> | |||
28 | #include <sys/sockio.h> | |||
29 | #include <sys/mbuf.h> | |||
30 | #include <sys/kernel.h> | |||
31 | #include <sys/socket.h> | |||
32 | #include <sys/systm.h> | |||
33 | #include <sys/timeout.h> | |||
34 | #include <sys/conf.h> | |||
35 | #include <sys/device.h> | |||
36 | #include <sys/endian.h> | |||
37 | ||||
38 | #include <machine/intr.h> | |||
39 | ||||
40 | #if NBPFILTER1 > 0 | |||
41 | #include <net/bpf.h> | |||
42 | #endif | |||
43 | #include <net/if.h> | |||
44 | #include <net/if_dl.h> | |||
45 | #include <net/if_media.h> | |||
46 | ||||
47 | #include <netinet/in.h> | |||
48 | #include <netinet/if_ether.h> | |||
49 | ||||
50 | #include <net80211/ieee80211_var.h> | |||
51 | #include <net80211/ieee80211_amrr.h> | |||
52 | #include <net80211/ieee80211_radiotap.h> | |||
53 | ||||
54 | #include <dev/usb/usb.h> | |||
55 | #include <dev/usb/usbdi.h> | |||
56 | #include <dev/usb/usbdi_util.h> | |||
57 | #include <dev/usb/usbdevs.h> | |||
58 | ||||
59 | #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ | |||
60 | #include <dev/usb/if_runvar.h> | |||
61 | ||||
62 | #ifdef RUN_DEBUG | |||
63 | #define DPRINTF(x) do { if (run_debug) printf x; } while (0) | |||
64 | #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) | |||
65 | int run_debug = 0; | |||
66 | #else | |||
67 | #define DPRINTF(x) | |||
68 | #define DPRINTFN(n, x) | |||
69 | #endif | |||
70 | ||||
71 | #define USB_ID(v, p){ USB_VENDOR_v, USB_PRODUCT_v_p } { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } | |||
72 | static const struct usb_devno run_devs[] = { | |||
73 | USB_ID(ABOCOM, RT2770){ 0x07b8, 0x2770 }, | |||
74 | USB_ID(ABOCOM, RT2870){ 0x07b8, 0x2870 }, | |||
75 | USB_ID(ABOCOM, RT3070){ 0x07b8, 0x3070 }, | |||
76 | USB_ID(ABOCOM, RT3071){ 0x07b8, 0x3071 }, | |||
77 | USB_ID(ABOCOM, RT3072){ 0x07b8, 0x3072 }, | |||
78 | USB_ID(ABOCOM2, RT2870_1){ 0x1482, 0x3c09 }, | |||
79 | USB_ID(ACCTON, RT2770){ 0x083a, 0x7512 }, | |||
80 | USB_ID(ACCTON, RT2870_1){ 0x083a, 0xb522 }, | |||
81 | USB_ID(ACCTON, RT2870_2){ 0x083a, 0x6618 }, | |||
82 | USB_ID(ACCTON, RT2870_3){ 0x083a, 0x7522 }, | |||
83 | USB_ID(ACCTON, RT2870_4){ 0x083a, 0xa618 }, | |||
84 | USB_ID(ACCTON, RT2870_5){ 0x083a, 0x8522 }, | |||
85 | USB_ID(ACCTON, RT3070){ 0x083a, 0x7511 }, | |||
86 | USB_ID(ACCTON, RT3070_1){ 0x083a, 0xa701 }, | |||
87 | USB_ID(ACCTON, RT3070_2){ 0x083a, 0xa702 }, | |||
88 | USB_ID(ACCTON, RT3070_3){ 0x083a, 0xc522 }, | |||
89 | USB_ID(ACCTON, RT3070_4){ 0x083a, 0xa512 }, | |||
90 | USB_ID(ACCTON, RT3070_5){ 0x083a, 0xd522 }, | |||
91 | USB_ID(ACCTON, RT3070_6){ 0x083a, 0xa703 }, | |||
92 | USB_ID(AIRTIES, RT3070){ 0x1eda, 0x2310 }, | |||
93 | USB_ID(AIRTIES, RT3070_2){ 0x1eda, 0x2012 }, | |||
94 | USB_ID(ALLWIN, RT2070){ 0x8516, 0x2070 }, | |||
95 | USB_ID(ALLWIN, RT2770){ 0x8516, 0x2770 }, | |||
96 | USB_ID(ALLWIN, RT2870){ 0x8516, 0x2870 }, | |||
97 | USB_ID(ALLWIN, RT3070){ 0x8516, 0x3070 }, | |||
98 | USB_ID(ALLWIN, RT3071){ 0x8516, 0x3071 }, | |||
99 | USB_ID(ALLWIN, RT3072){ 0x8516, 0x3072 }, | |||
100 | USB_ID(ALLWIN, RT3572){ 0x8516, 0x3572 }, | |||
101 | USB_ID(AMIGO, RT2870_1){ 0x0e0b, 0x9031 }, | |||
102 | USB_ID(AMIGO, RT2870_2){ 0x0e0b, 0x9041 }, | |||
103 | USB_ID(AMIT, CGWLUSB2GNR){ 0x18c5, 0x0008 }, | |||
104 | USB_ID(AMIT, RT2870_1){ 0x18c5, 0x0012 }, | |||
105 | USB_ID(AMIT2, RT2870){ 0x15c5, 0x0008 }, | |||
106 | USB_ID(ASUS, RT2870_1){ 0x0b05, 0x1731 }, | |||
107 | USB_ID(ASUS, RT2870_2){ 0x0b05, 0x1732 }, | |||
108 | USB_ID(ASUS, RT2870_3){ 0x0b05, 0x1742 }, | |||
109 | USB_ID(ASUS, RT2870_4){ 0x0b05, 0x1760 }, | |||
110 | USB_ID(ASUS, RT2870_5){ 0x0b05, 0x1761 }, | |||
111 | USB_ID(ASUS, RT3070_1){ 0x0b05, 0x1790 }, | |||
112 | USB_ID(ASUS, USBN13){ 0x0b05, 0x1784 }, | |||
113 | USB_ID(ASUS, USBN53){ 0x0b05, 0x179d }, | |||
114 | USB_ID(ASUS, USBN66){ 0x0b05, 0x17ad }, | |||
115 | USB_ID(ASUS2, USBN11){ 0x1761, 0x0b05 }, | |||
116 | USB_ID(AZUREWAVE, RT2870_1){ 0x13d3, 0x3247 }, | |||
117 | USB_ID(AZUREWAVE, RT2870_2){ 0x13d3, 0x3262 }, | |||
118 | USB_ID(AZUREWAVE, RT3070_1){ 0x13d3, 0x3273 }, | |||
119 | USB_ID(AZUREWAVE, RT3070_2){ 0x13d3, 0x3284 }, | |||
120 | USB_ID(AZUREWAVE, RT3070_3){ 0x13d3, 0x3305 }, | |||
121 | USB_ID(AZUREWAVE, RT3070_4){ 0x13d3, 0x3307 }, | |||
122 | USB_ID(AZUREWAVE, RT3070_5){ 0x13d3, 0x3321 }, | |||
123 | USB_ID(BELKIN, F9L1103){ 0x050d, 0x1103 }, | |||
124 | USB_ID(BELKIN, F5D8053V3){ 0x050d, 0x815c }, | |||
125 | USB_ID(BELKIN, F5D8055){ 0x050d, 0x825a }, | |||
126 | USB_ID(BELKIN, F5D8055V2){ 0x050d, 0x825b }, | |||
127 | USB_ID(BELKIN, F6D4050V1){ 0x050d, 0x935a }, | |||
128 | USB_ID(BELKIN, F6D4050V2){ 0x050d, 0x935b }, | |||
129 | USB_ID(BELKIN, F7D1101V2){ 0x050d, 0x945b }, | |||
130 | USB_ID(BELKIN, RT2870_1){ 0x050d, 0x8053 }, | |||
131 | USB_ID(BELKIN, RT2870_2){ 0x050d, 0x805c }, | |||
132 | USB_ID(BEWAN, RT3070){ 0x07fa, 0x7712 }, | |||
133 | USB_ID(CISCOLINKSYS, AE1000){ 0x13b1, 0x002f }, | |||
134 | USB_ID(CISCOLINKSYS, AM10){ 0x13b1, 0x0031 }, | |||
135 | USB_ID(CISCOLINKSYS2, RT3070){ 0x167b, 0x4001 }, | |||
136 | USB_ID(CISCOLINKSYS3, RT3070){ 0x05a6, 0x0101 }, | |||
137 | USB_ID(CONCEPTRONIC2, RT2870_1){ 0x14b2, 0x3c06 }, | |||
138 | USB_ID(CONCEPTRONIC2, RT2870_2){ 0x14b2, 0x3c07 }, | |||
139 | USB_ID(CONCEPTRONIC2, RT2870_3){ 0x14b2, 0x3c23 }, | |||
140 | USB_ID(CONCEPTRONIC2, RT2870_5){ 0x14b2, 0x3c27 }, | |||
141 | USB_ID(CONCEPTRONIC2, RT2870_6){ 0x14b2, 0x3c28 }, | |||
142 | USB_ID(CONCEPTRONIC2, RT2870_7){ 0x14b2, 0x3c09 }, | |||
143 | USB_ID(CONCEPTRONIC2, RT2870_8){ 0x14b2, 0x3c12 }, | |||
144 | USB_ID(CONCEPTRONIC2, RT3070_1){ 0x14b2, 0x3c08 }, | |||
145 | USB_ID(CONCEPTRONIC2, RT3070_2){ 0x14b2, 0x3c11 }, | |||
146 | USB_ID(CONCEPTRONIC2, RT3070_3){ 0x14b2, 0x3c2c }, | |||
147 | USB_ID(CONCEPTRONIC2, VIGORN61){ 0x14b2, 0x3c25 }, | |||
148 | USB_ID(COREGA, CGWLUSB300GNM){ 0x07aa, 0x0042 }, | |||
149 | USB_ID(COREGA, RT2870_1){ 0x07aa, 0x002f }, | |||
150 | USB_ID(COREGA, RT2870_2){ 0x07aa, 0x003c }, | |||
151 | USB_ID(COREGA, RT2870_3){ 0x07aa, 0x003f }, | |||
152 | USB_ID(COREGA, RT3070){ 0x07aa, 0x0041 }, | |||
153 | USB_ID(CYBERTAN, RT2870){ 0x129b, 0x1828 }, | |||
154 | USB_ID(DLINK, DWA125B2){ 0x2001, 0x3c1e }, | |||
155 | USB_ID(DLINK, DWA127){ 0x2001, 0x3c1b }, | |||
156 | USB_ID(DLINK, DWA130F1){ 0x2001, 0x3c25 }, | |||
157 | USB_ID(DLINK, DWA137A1){ 0x2001, 0x3317 }, | |||
158 | USB_ID(DLINK, DWA140B3){ 0x2001, 0x3c15 }, | |||
159 | USB_ID(DLINK, DWA140D1){ 0x2001, 0x3c20 }, | |||
160 | USB_ID(DLINK, DWA160B2){ 0x2001, 0x3c1a }, | |||
161 | USB_ID(DLINK, DWA162){ 0x2001, 0x3c1f }, | |||
162 | USB_ID(DLINK, RT2870){ 0x2001, 0x3c09 }, | |||
163 | USB_ID(DLINK, RT3072){ 0x2001, 0x3c0a }, | |||
164 | USB_ID(DLINK2, DWA130){ 0x07d1, 0x3c13 }, | |||
165 | USB_ID(DLINK2, RT2870_1){ 0x07d1, 0x3c09 }, | |||
166 | USB_ID(DLINK2, RT2870_2){ 0x07d1, 0x3c11 }, | |||
167 | USB_ID(DLINK2, RT3070_1){ 0x07d1, 0x3c0d }, | |||
168 | USB_ID(DLINK2, RT3070_2){ 0x07d1, 0x3c0e }, | |||
169 | USB_ID(DLINK2, RT3070_3){ 0x07d1, 0x3c0f }, | |||
170 | USB_ID(DLINK2, RT3070_4){ 0x07d1, 0x3c15 }, | |||
171 | USB_ID(DLINK2, RT3070_5){ 0x07d1, 0x3c16 }, | |||
172 | USB_ID(DLINK2, RT3072){ 0x07d1, 0x3c0a }, | |||
173 | USB_ID(DLINK2, RT3072_1){ 0x07d1, 0x3c0b }, | |||
174 | USB_ID(DVICO, RT3070){ 0x0fe9, 0xb307 }, | |||
175 | USB_ID(EDIMAX, EW7717){ 0x7392, 0x7717 }, | |||
176 | USB_ID(EDIMAX, EW7718){ 0x7392, 0x7718 }, | |||
177 | USB_ID(EDIMAX, EW7722UTN){ 0x7392, 0x7722 }, | |||
178 | USB_ID(EDIMAX, RT2870_1){ 0x7392, 0x7711 }, | |||
179 | USB_ID(ENCORE, RT3070_1){ 0x203d, 0x1480 }, | |||
180 | USB_ID(ENCORE, RT3070_2){ 0x203d, 0x14a1 }, | |||
181 | USB_ID(ENCORE, RT3070_3){ 0x203d, 0x14a9 }, | |||
182 | USB_ID(GIGABYTE, GNWB31N){ 0x1044, 0x800c }, | |||
183 | USB_ID(GIGABYTE, GNWB32L){ 0x1044, 0x800d }, | |||
184 | USB_ID(GIGABYTE, RT2870_1){ 0x1044, 0x800b }, | |||
185 | USB_ID(GIGASET, RT3070_1){ 0x1690, 0x0740 }, | |||
186 | USB_ID(GIGASET, RT3070_2){ 0x1690, 0x0744 }, | |||
187 | USB_ID(GUILLEMOT, HWNU300){ 0x06f8, 0xe030 }, | |||
188 | USB_ID(HAWKING, HWDN2){ 0x0e66, 0x000b }, | |||
189 | USB_ID(HAWKING, HWUN2){ 0x0e66, 0x0009 }, | |||
190 | USB_ID(HAWKING, RT2870_1){ 0x0e66, 0x0001 }, | |||
191 | USB_ID(HAWKING, RT2870_2){ 0x0e66, 0x0003 }, | |||
192 | USB_ID(HAWKING, RT2870_3){ 0x0e66, 0x0013 }, | |||
193 | USB_ID(HAWKING, RT2870_4){ 0x0e66, 0x0017 }, | |||
194 | USB_ID(HAWKING, RT2870_5){ 0x0e66, 0x0018 }, | |||
195 | USB_ID(IODATA, RT3072_1){ 0x04bb, 0x0944 }, | |||
196 | USB_ID(IODATA, RT3072_2){ 0x04bb, 0x0945 }, | |||
197 | USB_ID(IODATA, RT3072_3){ 0x04bb, 0x0947 }, | |||
198 | USB_ID(IODATA, RT3072_4){ 0x04bb, 0x0948 }, | |||
199 | USB_ID(LINKSYS4, RT3070){ 0x1737, 0x0078 }, | |||
200 | USB_ID(LINKSYS4, WUSB100){ 0x1737, 0x0070 }, | |||
201 | USB_ID(LINKSYS4, WUSB54GCV3){ 0x1737, 0x0077 }, | |||
202 | USB_ID(LINKSYS4, WUSB600N){ 0x1737, 0x0071 }, | |||
203 | USB_ID(LINKSYS4, WUSB600NV2){ 0x1737, 0x0079 }, | |||
204 | USB_ID(LOGITEC, LANW150NU2){ 0x0789, 0x0168 }, | |||
205 | USB_ID(LOGITEC, LANW300NU2){ 0x0789, 0x0166 }, | |||
206 | USB_ID(LOGITEC, LANW300NU2S){ 0x0789, 0x0169 }, | |||
207 | USB_ID(LOGITEC, RT2870_1){ 0x0789, 0x0162 }, | |||
208 | USB_ID(LOGITEC, RT2870_2){ 0x0789, 0x0163 }, | |||
209 | USB_ID(LOGITEC, RT2870_3){ 0x0789, 0x0164 }, | |||
210 | USB_ID(MELCO, RT2870_1){ 0x0411, 0x0148 }, | |||
211 | USB_ID(MELCO, RT2870_2){ 0x0411, 0x0150 }, | |||
212 | USB_ID(MELCO, WLIUCAG300N){ 0x0411, 0x012e }, | |||
213 | USB_ID(MELCO, WLIUCG300N){ 0x0411, 0x00e8 }, | |||
214 | USB_ID(MELCO, WLIUCG301N){ 0x0411, 0x016f }, | |||
215 | USB_ID(MELCO, WLIUCGN){ 0x0411, 0x015d }, | |||
216 | USB_ID(MELCO, WLIUCGNHP){ 0x0411, 0x0158 }, | |||
217 | USB_ID(MELCO, WLIUCGNM){ 0x0411, 0x01a2 }, | |||
218 | USB_ID(MELCO, WLIUCGNM2){ 0x0411, 0x01ee }, | |||
219 | USB_ID(MOTOROLA4, RT2770){ 0x100d, 0x9031 }, | |||
220 | USB_ID(MOTOROLA4, RT3070){ 0x100d, 0x9032 }, | |||
221 | USB_ID(MSI, RT3070_1){ 0x0db0, 0x3820 }, | |||
222 | USB_ID(MSI, RT3070_2){ 0x0db0, 0x3821 }, | |||
223 | USB_ID(MSI, RT3070_3){ 0x0db0, 0x3870 }, | |||
224 | USB_ID(MSI, RT3070_4){ 0x0db0, 0x6899 }, | |||
225 | USB_ID(MSI, RT3070_5){ 0x0db0, 0x821a }, | |||
226 | USB_ID(MSI, RT3070_6){ 0x0db0, 0x870a }, | |||
227 | USB_ID(MSI, RT3070_7){ 0x0db0, 0x899a }, | |||
228 | USB_ID(MSI, RT3070_8){ 0x0db0, 0x3822 }, | |||
229 | USB_ID(MSI, RT3070_9){ 0x0db0, 0x3871 }, | |||
230 | USB_ID(MSI, RT3070_10){ 0x0db0, 0x822a }, | |||
231 | USB_ID(MSI, RT3070_11){ 0x0db0, 0x871a }, | |||
232 | USB_ID(MSI, RT3070_12){ 0x0db0, 0x822b }, | |||
233 | USB_ID(MSI, RT3070_13){ 0x0db0, 0x822c }, | |||
234 | USB_ID(MSI, RT3070_14){ 0x0db0, 0x871b }, | |||
235 | USB_ID(MSI, RT3070_15){ 0x0db0, 0x871c }, | |||
236 | USB_ID(OVISLINK, RT3071){ 0x1b75, 0x3071 }, | |||
237 | USB_ID(OVISLINK, RT3072){ 0x1b75, 0x3072 }, | |||
238 | USB_ID(PARA, RT3070){ 0x20b8, 0x8888 }, | |||
239 | USB_ID(PEGATRON, RT2870){ 0x1d4d, 0x0002 }, | |||
240 | USB_ID(PEGATRON, RT3070){ 0x1d4d, 0x000c }, | |||
241 | USB_ID(PEGATRON, RT3070_2){ 0x1d4d, 0x000e }, | |||
242 | USB_ID(PEGATRON, RT3070_3){ 0x1d4d, 0x0010 }, | |||
243 | USB_ID(PEGATRON, RT3072){ 0x1d4d, 0x0011 }, | |||
244 | USB_ID(PHILIPS, RT2870){ 0x0471, 0x200f }, | |||
245 | USB_ID(PLANEX2, GWUS300MINIS){ 0x2019, 0xab24 }, | |||
246 | USB_ID(PLANEX2, GWUSMICRO300){ 0x2019, 0xab29 }, | |||
247 | USB_ID(PLANEX2, GWUSMICRON){ 0x2019, 0xed14 }, | |||
248 | USB_ID(PLANEX2, RT2870){ 0x2019, 0xed06 }, | |||
249 | USB_ID(PLANEX2, RT3070){ 0x2019, 0xab25 }, | |||
250 | USB_ID(QCOM, RT2870){ 0x18e8, 0x6259 }, | |||
251 | USB_ID(QUANTA, RT3070){ 0x1a32, 0x0304 }, | |||
252 | USB_ID(RALINK, RT2070){ 0x148f, 0x2070 }, | |||
253 | USB_ID(RALINK, RT2770){ 0x148f, 0x2770 }, | |||
254 | USB_ID(RALINK, RT2870){ 0x148f, 0x2870 }, | |||
255 | USB_ID(RALINK, RT3070){ 0x148f, 0x3070 }, | |||
256 | USB_ID(RALINK, RT3071){ 0x148f, 0x3071 }, | |||
257 | USB_ID(RALINK, RT3072){ 0x148f, 0x3072 }, | |||
258 | USB_ID(RALINK, RT3370){ 0x148f, 0x3370 }, | |||
259 | USB_ID(RALINK, RT3572){ 0x148f, 0x3572 }, | |||
260 | USB_ID(RALINK, RT3573){ 0x148f, 0x3573 }, | |||
261 | USB_ID(RALINK, RT5370){ 0x148f, 0x5370 }, | |||
262 | USB_ID(RALINK, RT5372){ 0x148f, 0x5372 }, | |||
263 | USB_ID(RALINK, RT5572){ 0x148f, 0x5572 }, | |||
264 | USB_ID(RALINK, RT8070){ 0x148f, 0x8070 }, | |||
265 | USB_ID(SAMSUNG, WIS09ABGN){ 0x055d, 0x2018 }, | |||
266 | USB_ID(SAMSUNG2, RT2870_1){ 0x04e8, 0x2018 }, | |||
267 | USB_ID(SENAO, RT2870_1){ 0x1740, 0x9701 }, | |||
268 | USB_ID(SENAO, RT2870_2){ 0x1740, 0x9702 }, | |||
269 | USB_ID(SENAO, RT2870_3){ 0x1740, 0x0605 }, | |||
270 | USB_ID(SENAO, RT2870_4){ 0x1740, 0x0615 }, | |||
271 | USB_ID(SENAO, RT3070){ 0x1740, 0x9703 }, | |||
272 | USB_ID(SENAO, RT3071){ 0x1740, 0x9705 }, | |||
273 | USB_ID(SENAO, RT3072_1){ 0x1740, 0x9706 }, | |||
274 | USB_ID(SENAO, RT3072_2){ 0x1740, 0x9707 }, | |||
275 | USB_ID(SENAO, RT3072_3){ 0x1740, 0x9708 }, | |||
276 | USB_ID(SENAO, RT3072_4){ 0x1740, 0x9709 }, | |||
277 | USB_ID(SENAO, RT3072_5){ 0x1740, 0x9801 }, | |||
278 | USB_ID(SITECOMEU, WL302){ 0x0df6, 0x002d }, | |||
279 | USB_ID(SITECOMEU, WL315){ 0x0df6, 0x0039 }, | |||
280 | USB_ID(SITECOMEU, WL321){ 0x0df6, 0x003b }, | |||
281 | USB_ID(SITECOMEU, RT3070_3){ 0x0df6, 0x003c }, | |||
282 | USB_ID(SITECOMEU, WL302){ 0x0df6, 0x002d }, | |||
283 | USB_ID(SITECOMEU, WL344){ 0x0df6, 0x0040 }, | |||
284 | USB_ID(SITECOMEU, WL329){ 0x0df6, 0x0041 }, | |||
285 | USB_ID(SITECOMEU, WL345){ 0x0df6, 0x0042 }, | |||
286 | USB_ID(SITECOMEU, RT2870_1){ 0x0df6, 0x0017 }, | |||
287 | USB_ID(SITECOMEU, RT2870_2){ 0x0df6, 0x002b }, | |||
288 | USB_ID(SITECOMEU, RT2870_3){ 0x0df6, 0x002c }, | |||
289 | USB_ID(SITECOMEU, RT3070_1){ 0x0df6, 0x0051 }, | |||
290 | USB_ID(SITECOMEU, RT3072_3){ 0x0df6, 0x0047 }, | |||
291 | USB_ID(SITECOMEU, RT3072_4){ 0x0df6, 0x0048 }, | |||
292 | USB_ID(SITECOMEU, RT3072_5){ 0x0df6, 0x005f }, | |||
293 | USB_ID(SITECOMEU, RT3072_6){ 0x0df6, 0x004d }, | |||
294 | USB_ID(SITECOMEU, WL302){ 0x0df6, 0x002d }, | |||
295 | USB_ID(SITECOMEU, WL315){ 0x0df6, 0x0039 }, | |||
296 | USB_ID(SITECOMEU, WL321){ 0x0df6, 0x003b }, | |||
297 | USB_ID(SITECOMEU, WL324){ 0x0df6, 0x003d }, | |||
298 | USB_ID(SITECOMEU, WL329){ 0x0df6, 0x0041 }, | |||
299 | USB_ID(SITECOMEU, WL343){ 0x0df6, 0x003e }, | |||
300 | USB_ID(SITECOMEU, WL344){ 0x0df6, 0x0040 }, | |||
301 | USB_ID(SITECOMEU, WL345){ 0x0df6, 0x0042 }, | |||
302 | USB_ID(SITECOMEU, WL349V4){ 0x0df6, 0x0050 }, | |||
303 | USB_ID(SITECOMEU, WL608){ 0x0df6, 0x003f }, | |||
304 | USB_ID(SITECOMEU, WLA4000){ 0x0df6, 0x0060 }, | |||
305 | USB_ID(SITECOMEU, WLA5000){ 0x0df6, 0x0062 }, | |||
306 | USB_ID(SPARKLAN, RT2870_1){ 0x15a9, 0x0006 }, | |||
307 | USB_ID(SPARKLAN, RT2870_2){ 0x15a9, 0x0012 }, | |||
308 | USB_ID(SPARKLAN, RT3070){ 0x15a9, 0x0010 }, | |||
309 | USB_ID(SWEEX2, LW153){ 0x177f, 0x0153 }, | |||
310 | USB_ID(SWEEX2, LW303){ 0x177f, 0x0302 }, | |||
311 | USB_ID(SWEEX2, LW313){ 0x177f, 0x0313 }, | |||
312 | USB_ID(TOSHIBA, RT3070){ 0x0930, 0x0a07 }, | |||
313 | USB_ID(UMEDIA, RT2870_1){ 0x157e, 0x300e }, | |||
314 | USB_ID(UMEDIA, TEW645UB){ 0x157e, 0x3013 }, | |||
315 | USB_ID(ZCOM, RT2870_1){ 0x0cde, 0x0022 }, | |||
316 | USB_ID(ZCOM, RT2870_2){ 0x0cde, 0x0025 }, | |||
317 | USB_ID(ZINWELL, RT2870_1){ 0x5a57, 0x0280 }, | |||
318 | USB_ID(ZINWELL, RT2870_2){ 0x5a57, 0x0282 }, | |||
319 | USB_ID(ZINWELL, RT3070){ 0x5a57, 0x5257 }, | |||
320 | USB_ID(ZINWELL, RT3072_1){ 0x5a57, 0x0283 }, | |||
321 | USB_ID(ZINWELL, RT3072_2){ 0x5a57, 0x0284 }, | |||
322 | USB_ID(ZYXEL, NWD2105){ 0x0586, 0x341e }, | |||
323 | USB_ID(ZYXEL, NWD211AN){ 0x0586, 0x3418 }, | |||
324 | USB_ID(ZYXEL, RT2870_1){ 0x0586, 0x3416 }, | |||
325 | USB_ID(ZYXEL, RT2870_2){ 0x0586, 0x341a }, | |||
326 | USB_ID(ZYXEL, RT3070){ 0x0586, 0x343e } | |||
327 | }; | |||
328 | ||||
329 | int run_match(struct device *, void *, void *); | |||
330 | void run_attach(struct device *, struct device *, void *); | |||
331 | int run_detach(struct device *, int); | |||
332 | int run_alloc_rx_ring(struct run_softc *); | |||
333 | void run_free_rx_ring(struct run_softc *); | |||
334 | int run_alloc_tx_ring(struct run_softc *, int); | |||
335 | void run_free_tx_ring(struct run_softc *, int); | |||
336 | int run_load_microcode(struct run_softc *); | |||
337 | int run_reset(struct run_softc *); | |||
338 | int run_read(struct run_softc *, uint16_t, uint32_t *); | |||
339 | int run_read_region_1(struct run_softc *, uint16_t, uint8_t *, | |||
340 | int); | |||
341 | int run_write_2(struct run_softc *, uint16_t, uint16_t); | |||
342 | int run_write(struct run_softc *, uint16_t, uint32_t); | |||
343 | int run_write_region_1(struct run_softc *, uint16_t, | |||
344 | const uint8_t *, int); | |||
345 | int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int); | |||
346 | int run_efuse_read(struct run_softc *, uint16_t, uint16_t *); | |||
347 | int run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *); | |||
348 | int run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *); | |||
349 | int run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t); | |||
350 | int run_rt3070_rf_read(struct run_softc *, uint8_t, uint8_t *); | |||
351 | int run_rt3070_rf_write(struct run_softc *, uint8_t, uint8_t); | |||
352 | int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); | |||
353 | int run_bbp_write(struct run_softc *, uint8_t, uint8_t); | |||
354 | int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); | |||
355 | const char * run_get_rf(int); | |||
356 | void run_get_txpower(struct run_softc *); | |||
357 | void run_rt3593_get_txpower(struct run_softc *); | |||
358 | int run_read_eeprom(struct run_softc *); | |||
359 | struct ieee80211_node *run_node_alloc(struct ieee80211com *); | |||
360 | int run_media_change(struct ifnet *); | |||
361 | void run_next_scan(void *); | |||
362 | void run_task(void *); | |||
363 | void run_do_async(struct run_softc *, void (*)(struct run_softc *, | |||
364 | void *), void *, int); | |||
365 | int run_newstate(struct ieee80211com *, enum ieee80211_state, int); | |||
366 | void run_newstate_cb(struct run_softc *, void *); | |||
367 | void run_updateedca(struct ieee80211com *); | |||
368 | void run_updateedca_cb(struct run_softc *, void *); | |||
369 | int run_set_key(struct ieee80211com *, struct ieee80211_node *, | |||
370 | struct ieee80211_key *); | |||
371 | void run_set_key_cb(struct run_softc *, void *); | |||
372 | void run_delete_key(struct ieee80211com *, struct ieee80211_node *, | |||
373 | struct ieee80211_key *); | |||
374 | void run_delete_key_cb(struct run_softc *, void *); | |||
375 | void run_calibrate_to(void *); | |||
376 | void run_calibrate_cb(struct run_softc *, void *); | |||
377 | void run_newassoc(struct ieee80211com *, struct ieee80211_node *, | |||
378 | int); | |||
379 | void run_rx_frame(struct run_softc *, uint8_t *, int, | |||
380 | struct mbuf_list *); | |||
381 | void run_rxeof(struct usbd_xfer *, void *, usbd_status); | |||
382 | void run_txeof(struct usbd_xfer *, void *, usbd_status); | |||
383 | int run_tx(struct run_softc *, struct mbuf *, | |||
384 | struct ieee80211_node *); | |||
385 | void run_start(struct ifnet *); | |||
386 | void run_watchdog(struct ifnet *); | |||
387 | int run_ioctl(struct ifnet *, u_long, caddr_t); | |||
388 | void run_iq_calib(struct run_softc *, u_int); | |||
389 | void run_select_chan_group(struct run_softc *, int); | |||
390 | void run_set_agc(struct run_softc *, uint8_t); | |||
391 | void run_set_rx_antenna(struct run_softc *, int); | |||
392 | void run_rt2870_set_chan(struct run_softc *, u_int); | |||
393 | void run_rt3070_set_chan(struct run_softc *, u_int); | |||
394 | void run_rt3572_set_chan(struct run_softc *, u_int); | |||
395 | void run_rt3593_set_chan(struct run_softc *, u_int); | |||
396 | void run_rt5390_set_chan(struct run_softc *, u_int); | |||
397 | void run_rt5592_set_chan(struct run_softc *, u_int); | |||
398 | int run_set_chan(struct run_softc *, struct ieee80211_channel *); | |||
399 | void run_enable_tsf_sync(struct run_softc *); | |||
400 | void run_enable_mrr(struct run_softc *); | |||
401 | void run_set_txpreamble(struct run_softc *); | |||
402 | void run_set_basicrates(struct run_softc *); | |||
403 | void run_set_leds(struct run_softc *, uint16_t); | |||
404 | void run_set_bssid(struct run_softc *, const uint8_t *); | |||
405 | void run_set_macaddr(struct run_softc *, const uint8_t *); | |||
406 | void run_updateslot(struct ieee80211com *); | |||
407 | void run_updateslot_cb(struct run_softc *, void *); | |||
408 | #if NBPFILTER1 > 0 | |||
409 | int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); | |||
410 | #endif | |||
411 | void run_rt5390_bbp_init(struct run_softc *); | |||
412 | int run_bbp_init(struct run_softc *); | |||
413 | int run_rt3070_rf_init(struct run_softc *); | |||
414 | void run_rt3593_rf_init(struct run_softc *); | |||
415 | void run_rt5390_rf_init(struct run_softc *); | |||
416 | int run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t, | |||
417 | uint8_t *); | |||
418 | void run_rt3070_rf_setup(struct run_softc *); | |||
419 | void run_rt3593_rf_setup(struct run_softc *); | |||
420 | void run_rt5390_rf_setup(struct run_softc *); | |||
421 | int run_txrx_enable(struct run_softc *); | |||
422 | void run_adjust_freq_offset(struct run_softc *); | |||
423 | int run_init(struct ifnet *); | |||
424 | void run_stop(struct ifnet *, int); | |||
425 | ||||
426 | struct cfdriver run_cd = { | |||
427 | NULL((void *)0), "run", DV_IFNET | |||
428 | }; | |||
429 | ||||
430 | const struct cfattach run_ca = { | |||
431 | sizeof (struct run_softc), run_match, run_attach, run_detach | |||
432 | }; | |||
433 | ||||
434 | static const struct { | |||
435 | uint32_t reg; | |||
436 | uint32_t val; | |||
437 | } rt2870_def_mac[] = { | |||
438 | RT2870_DEF_MAC{ 0x042c, 0xf8f0e8e0 }, { 0x1408, 0x0000013f }, { 0x140c, 0x00008003 }, { 0x1004, 0x00000000 }, { 0x1104, 0x00000209 }, { 0x1330, 0x00000000 }, { 0x1334, 0x00080606 }, { 0x1350, 0x00001020 } , { 0x1348, 0x000a2090 }, { 0x102c, 0x7f031e46 }, { 0x0214, 0x00002273 }, { 0x0218, 0x00002344 }, { 0x021c, 0x000034aa }, { 0x040c, 0x1f3fbf9f }, { 0x134c, 0x47d01f0f }, { 0x1404, 0x00000013 } , { 0x1364, 0x05740003 }, { 0x1368, 0x05740003 }, { 0x0408, 0x00f40006 }, { 0x0208, 0x00000030 }, { 0x1374, 0x01744004 }, { 0x1378, 0x03f44084 }, { 0x136c, 0x01744004 }, { 0x1370, 0x03f44084 } , { 0x1340, 0x0000583f }, { 0x1608, 0x00000002 }, { 0x1344, 0x00092b20 }, { 0x1380, 0x002400ca }, { 0x1100, 0x33a41010 }, { 0x1204, 0x00000003 } | |||
439 | }; | |||
440 | ||||
441 | static const struct { | |||
442 | uint8_t reg; | |||
443 | uint8_t val; | |||
444 | } rt2860_def_bbp[] = { | |||
445 | RT2860_DEF_BBP{ 65, 0x2c }, { 66, 0x38 }, { 68, 0x0b }, { 69, 0x12 }, { 70, 0x0a }, { 73, 0x10 }, { 81, 0x37 }, { 82, 0x62 }, { 83, 0x6a }, { 84, 0x99 }, { 86, 0x00 }, { 91, 0x04 }, { 92, 0x00 }, { 103, 0x00 }, { 105, 0x05 }, { 106, 0x35 } | |||
446 | },rt5390_def_bbp[] = { | |||
447 | RT5390_DEF_BBP{ 31, 0x08 }, { 65, 0x2c }, { 66, 0x38 }, { 68, 0x0b }, { 69, 0x0d }, { 70, 0x06 }, { 73, 0x13 }, { 75, 0x46 }, { 76, 0x28 }, { 77, 0x59 }, { 81, 0x37 }, { 82, 0x62 }, { 83, 0x7a }, { 84, 0x9a }, { 86, 0x38 }, { 91, 0x04 }, { 92, 0x02 }, { 103, 0xc0 }, { 104, 0x92 }, { 105, 0x3c }, { 106, 0x03 }, { 128, 0x12 } | |||
448 | },rt5592_def_bbp[] = { | |||
449 | RT5592_DEF_BBP{ 20, 0x06 }, { 31, 0x08 }, { 65, 0x2c }, { 66, 0x38 }, { 68, 0xdd }, { 69, 0x1a }, { 70, 0x05 }, { 73, 0x13 }, { 74, 0x0f }, { 75, 0x4f }, { 76, 0x28 }, { 77, 0x59 }, { 81, 0x37 }, { 82, 0x62 }, { 83, 0x6a }, { 84, 0x9a }, { 86, 0x38 }, { 88, 0x90 }, { 91, 0x04 }, { 92, 0x02 }, { 95, 0x9a }, { 98, 0x12 }, { 103, 0xc0 }, { 104, 0x92 }, { 105, 0x3c }, { 106, 0x35 }, { 128 , 0x12 }, { 134, 0xd0 }, { 135, 0xf6 }, { 137, 0x0f } | |||
450 | }; | |||
451 | ||||
452 | /* | |||
453 | * Default values for BBP register R196 for RT5592. | |||
454 | */ | |||
455 | static const uint8_t rt5592_bbp_r196[] = { | |||
456 | 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, | |||
457 | 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, | |||
458 | 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, | |||
459 | 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, | |||
460 | 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, | |||
461 | 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, | |||
462 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |||
463 | 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, | |||
464 | 0x2e, 0x36, 0x30, 0x6e | |||
465 | }; | |||
466 | ||||
467 | static const struct rfprog { | |||
468 | uint8_t chan; | |||
469 | uint32_t r1, r2, r3, r4; | |||
470 | } rt2860_rf2850[] = { | |||
471 | RT2860_RF2850{ 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, { 3, 0x100bb3, 0x1301e2, 0x05a014 , 0x001402 }, { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, { 6, 0x100bb3, 0x1301e3 , 0x05a014, 0x001407 }, { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, { 9, 0x100bb3 , 0x1301e5, 0x05a014, 0x001402 }, { 10, 0x100bb3, 0x1301e5, 0x05a014 , 0x001407 }, { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, { 13, 0x100bb3 , 0x1301e7, 0x05a014, 0x001402 }, { 14, 0x100bb3, 0x1301e8, 0x05a014 , 0x001404 }, { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, { 40, 0x100bb2 , 0x1301a0, 0x056014, 0x001400 }, { 44, 0x100bb2, 0x1301a0, 0x056014 , 0x001408 }, { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, { 52, 0x100bb2 , 0x1301a2, 0x056014, 0x001404 }, { 54, 0x100bb2, 0x1301a2, 0x056014 , 0x001408 }, { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, { 62, 0x100bb2 , 0x1301a4, 0x056014, 0x001404 }, { 64, 0x100bb2, 0x1301a4, 0x056014 , 0x001408 }, { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 } , { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, { 104, 0x100bb2 , 0x1701ac, 0x15e014, 0x001408 }, { 108, 0x100bb3, 0x17028c, 0x15e014 , 0x001404 }, { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 } , { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, { 116, 0x100bb3 , 0x13028e, 0x05e014, 0x001408 }, { 118, 0x100bb3, 0x13028f, 0x05e014 , 0x001404 }, { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 } , { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, { 126, 0x100bb1 , 0x1300e0, 0x05e014, 0x001406 }, { 128, 0x100bb1, 0x1300e0, 0x05e014 , 0x001408 }, { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 } , { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, { 136, 0x100bb1 , 0x1300e1, 0x05e014, 0x001406 }, { 140, 0x100bb1, 0x1300e2, 0x05e014 , 0x001400 }, { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 } , { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, { 153, 0x100bb1 , 0x1300e3, 0x05e014, 0x001403 }, { 157, 0x100bb1, 0x1300e3, 0x05e014 , 0x001407 }, { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 } , { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, { 165, 0x100bb1 , 0x1300e4, 0x05e014, 0x001405 }, { 167, 0x100bb1, 0x1300f4, 0x05e014 , 0x001407 }, { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 } , { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, { 173, 0x100bb1 , 0x1300f5, 0x05e014, 0x001403 } | |||
472 | }; | |||
473 | ||||
474 | struct { | |||
475 | uint8_t n, r, k; | |||
476 | } rt3070_freqs[] = { | |||
477 | RT3070_RF3052{ 0xf1, 2, 2 }, { 0xf1, 2, 7 }, { 0xf2, 2, 2 }, { 0xf2, 2, 7 } , { 0xf3, 2, 2 }, { 0xf3, 2, 7 }, { 0xf4, 2, 2 }, { 0xf4, 2, 7 }, { 0xf5, 2, 2 }, { 0xf5, 2, 7 }, { 0xf6, 2, 2 }, { 0xf6, 2 , 7 }, { 0xf7, 2, 2 }, { 0xf8, 2, 4 }, { 0x56, 0, 4 }, { 0x56 , 0, 6 }, { 0x56, 0, 8 }, { 0x57, 0, 0 }, { 0x57, 0, 2 }, { 0x57 , 0, 4 }, { 0x57, 0, 8 }, { 0x57, 0, 10 }, { 0x58, 0, 0 }, { 0x58 , 0, 4 }, { 0x58, 0, 6 }, { 0x58, 0, 8 }, { 0x5b, 0, 8 }, { 0x5b , 0, 10 }, { 0x5c, 0, 0 }, { 0x5c, 0, 4 }, { 0x5c, 0, 6 }, { 0x5c , 0, 8 }, { 0x5d, 0, 0 }, { 0x5d, 0, 2 }, { 0x5d, 0, 4 }, { 0x5d , 0, 8 }, { 0x5d, 0, 10 }, { 0x5e, 0, 0 }, { 0x5e, 0, 4 }, { 0x5e , 0, 6 }, { 0x5e, 0, 8 }, { 0x5f, 0, 0 }, { 0x5f, 0, 9 }, { 0x5f , 0, 11 }, { 0x60, 0, 1 }, { 0x60, 0, 5 }, { 0x60, 0, 7 }, { 0x60 , 0, 9 }, { 0x61, 0, 1 }, { 0x61, 0, 3 }, { 0x61, 0, 5 }, { 0x61 , 0, 7 }, { 0x61, 0, 9 } | |||
478 | }; | |||
479 | ||||
480 | static const struct rt5592_freqs { | |||
481 | uint16_t n; | |||
482 | uint8_t k, m, r; | |||
483 | } rt5592_freqs_20mhz[] = { | |||
484 | RT5592_RF5592_20MHZ{ 0x1e2, 4, 10, 3 }, { 0x1e3, 4, 10, 3 }, { 0x1e4, 4, 10, 3 } , { 0x1e5, 4, 10, 3 }, { 0x1e6, 4, 10, 3 }, { 0x1e7, 4, 10, 3 }, { 0x1e8, 4, 10, 3 }, { 0x1e9, 4, 10, 3 }, { 0x1ea, 4, 10, 3 }, { 0x1eb, 4, 10, 3 }, { 0x1ec, 4, 10, 3 }, { 0x1ed, 4, 10 , 3 }, { 0x1ee, 4, 10, 3 }, { 0x1f0, 8, 10, 3 }, { 0xac, 8, 12 , 1 }, { 0xad, 0, 12, 1 }, { 0xad, 4, 12, 1 }, { 0xae, 0, 12, 1 }, { 0xae, 4, 12, 1 }, { 0xae, 8, 12, 1 }, { 0xaf, 4, 12, 1 }, { 0xaf, 8, 12, 1 }, { 0xb0, 0, 12, 1 }, { 0xb0, 8, 12, 1 } , { 0xb1, 0, 12, 1 }, { 0xb1, 4, 12, 1 }, { 0xb7, 4, 12, 1 }, { 0xb7, 8, 12, 1 }, { 0xb8, 0, 12, 1 }, { 0xb8, 8, 12, 1 }, { 0xb9, 0, 12, 1 }, { 0xb9, 4, 12, 1 }, { 0xba, 0, 12, 1 }, { 0xba , 4, 12, 1 }, { 0xba, 8, 12, 1 }, { 0xbb, 4, 12, 1 }, { 0xbb, 8, 12, 1 }, { 0xbc, 0, 12, 1 }, { 0xbc, 8, 12, 1 }, { 0xbd, 0 , 12, 1 }, { 0xbd, 4, 12, 1 }, { 0xbe, 0, 12, 1 }, { 0xbf, 6, 12, 1 }, { 0xbf, 10, 12, 1 }, { 0xc0, 2, 12, 1 }, { 0xc0, 10 , 12, 1 }, { 0xc1, 2, 12, 1 }, { 0xc1, 6, 12, 1 }, { 0xc2, 2, 12, 1 }, { 0xa4, 0, 12, 1 }, { 0xa4, 4, 12, 1 }, { 0xa5, 8, 12 , 1 }, { 0xa6, 0, 12, 1 } | |||
485 | },rt5592_freqs_40mhz[] = { | |||
486 | RT5592_RF5592_40MHZ{ 0xf1, 2, 10, 3 }, { 0xf1, 7, 10, 3 }, { 0xf2, 2, 10, 3 }, { 0xf2, 7, 10, 3 }, { 0xf3, 2, 10, 3 }, { 0xf3, 7, 10, 3 }, { 0xf4 , 2, 10, 3 }, { 0xf4, 7, 10, 3 }, { 0xf5, 2, 10, 3 }, { 0xf5, 7, 10, 3 }, { 0xf6, 2, 10, 3 }, { 0xf6, 7, 10, 3 }, { 0xf7, 2 , 10, 3 }, { 0xf8, 4, 10, 3 }, { 0x56, 4, 12, 1 }, { 0x56, 6, 12, 1 }, { 0x56, 8, 12, 1 }, { 0x57, 0, 12, 1 }, { 0x57, 2, 12 , 1 }, { 0x57, 4, 12, 1 }, { 0x57, 8, 12, 1 }, { 0x57, 10, 12 , 1 }, { 0x58, 0, 12, 1 }, { 0x58, 4, 12, 1 }, { 0x58, 6, 12, 1 }, { 0x58, 8, 12, 1 }, { 0x5b, 8, 12, 1 }, { 0x5b, 10, 12, 1 }, { 0x5c, 0, 12, 1 }, { 0x5c, 4, 12, 1 }, { 0x5c, 6, 12, 1 }, { 0x5c, 8, 12, 1 }, { 0x5d, 0, 12, 1 }, { 0x5d, 2, 12, 1 } , { 0x5d, 4, 12, 1 }, { 0x5d, 8, 12, 1 }, { 0x5d, 10, 12, 1 } , { 0x5e, 0, 12, 1 }, { 0x5e, 4, 12, 1 }, { 0x5e, 6, 12, 1 }, { 0x5e, 8, 12, 1 }, { 0x5f, 0, 12, 1 }, { 0x5f, 9, 12, 1 }, { 0x5f, 11, 12, 1 }, { 0x60, 1, 12, 1 }, { 0x60, 5, 12, 1 }, { 0x60, 7, 12, 1 }, { 0x60, 9, 12, 1 }, { 0x61, 1, 12, 1 }, { 0x52 , 0, 12, 1 }, { 0x52, 4, 12, 1 }, { 0x52, 8, 12, 1 }, { 0x53, 0, 12, 1 } | |||
487 | }; | |||
488 | ||||
489 | static const struct { | |||
490 | uint8_t reg; | |||
491 | uint8_t val; | |||
492 | } rt3070_def_rf[] = { | |||
493 | RT3070_DEF_RF{ 4, 0x40 }, { 5, 0x03 }, { 6, 0x02 }, { 7, 0x60 }, { 9, 0x0f }, { 10, 0x41 }, { 11, 0x21 }, { 12, 0x7b }, { 14, 0x90 }, { 15, 0x58 }, { 16, 0xb3 }, { 17, 0x92 }, { 18, 0x2c }, { 19, 0x02 }, { 20, 0xba }, { 21, 0xdb }, { 24, 0x16 }, { 25, 0x01 }, { 29, 0x1f } | |||
494 | },rt3572_def_rf[] = { | |||
495 | RT3572_DEF_RF{ 0, 0x70 }, { 1, 0x81 }, { 2, 0xf1 }, { 3, 0x02 }, { 4, 0x4c }, { 5, 0x05 }, { 6, 0x4a }, { 7, 0xd8 }, { 9, 0xc3 }, { 10, 0xf1 }, { 11, 0xb9 }, { 12, 0x70 }, { 13, 0x65 }, { 14, 0xa0 }, { 15, 0x53 }, { 16, 0x4c }, { 17, 0x23 }, { 18, 0xac }, { 19, 0x93 }, { 20, 0xb3 }, { 21, 0xd0 }, { 22, 0x00 }, { 23, 0x3c }, { 24, 0x16 }, { 25, 0x15 }, { 26, 0x85 }, { 27, 0x00 }, { 28, 0x00 }, { 29, 0x9b }, { 30, 0x09 }, { 31, 0x10 } | |||
496 | },rt3593_def_rf[] = { | |||
497 | RT3593_DEF_RF{ 1, 0x03 }, { 3, 0x80 }, { 5, 0x00 }, { 6, 0x40 }, { 8, 0xf1 }, { 9, 0x02 }, { 10, 0xd3 }, { 11, 0x40 }, { 12, 0x4e }, { 13 , 0x12 }, { 18, 0x40 }, { 22, 0x20 }, { 30, 0x10 }, { 31, 0x80 }, { 32, 0x78 }, { 33, 0x3b }, { 34, 0x3c }, { 35, 0xe0 }, { 38, 0x86 }, { 39, 0x23 }, { 44, 0xd3 }, { 45, 0xbb }, { 46, 0x60 }, { 49, 0x81 }, { 50, 0x86 }, { 51, 0x75 }, { 52, 0x45 }, { 53, 0x18 }, { 54, 0x18 }, { 55, 0x18 }, { 56, 0xdb }, { 57, 0x6e } | |||
498 | },rt5390_def_rf[] = { | |||
499 | RT5390_DEF_RF{ 1, 0x0f }, { 2, 0x80 }, { 3, 0x88 }, { 5, 0x10 }, { 6, 0xa0 }, { 7, 0x00 }, { 10, 0x53 }, { 11, 0x4a }, { 12, 0x46 }, { 13 , 0x9f }, { 14, 0x00 }, { 15, 0x00 }, { 16, 0x00 }, { 18, 0x03 }, { 19, 0x00 }, { 20, 0x00 }, { 21, 0x00 }, { 22, 0x20 }, { 23, 0x00 }, { 24, 0x00 }, { 25, 0xc0 }, { 26, 0x00 }, { 27, 0x09 }, { 28, 0x00 }, { 29, 0x10 }, { 30, 0x10 }, { 31, 0x80 }, { 32, 0x80 }, { 33, 0x00 }, { 34, 0x07 }, { 35, 0x12 }, { 36, 0x00 }, { 37, 0x08 }, { 38, 0x85 }, { 39, 0x1b }, { 40, 0x0b }, { 41, 0xbb }, { 42, 0xd2 }, { 43, 0x9a }, { 44, 0x0e }, { 45, 0xa2 }, { 46, 0x7b }, { 47, 0x00 }, { 48, 0x10 }, { 49, 0x94 }, { 52, 0x38 }, { 53, 0x84 }, { 54, 0x78 }, { 55, 0x44 }, { 56, 0x22 }, { 57, 0x80 }, { 58, 0x7f }, { 59, 0x8f }, { 60, 0x45 }, { 61, 0xdd }, { 62, 0x00 }, { 63, 0x00 } | |||
500 | },rt5392_def_rf[] = { | |||
501 | RT5392_DEF_RF{ 1, 0x17 }, { 3, 0x88 }, { 5, 0x10 }, { 6, 0xe0 }, { 7, 0x00 }, { 10, 0x53 }, { 11, 0x4a }, { 12, 0x46 }, { 13, 0x9f }, { 14, 0x00 }, { 15, 0x00 }, { 16, 0x00 }, { 18, 0x03 }, { 19, 0x4d }, { 20, 0x00 }, { 21, 0x8d }, { 22, 0x20 }, { 23, 0x0b }, { 24, 0x44 }, { 25, 0x80 }, { 26, 0x82 }, { 27, 0x09 }, { 28, 0x00 }, { 29, 0x10 }, { 30, 0x10 }, { 31, 0x80 }, { 32, 0x20 }, { 33, 0xc0 }, { 34, 0x07 }, { 35, 0x12 }, { 36, 0x00 }, { 37, 0x08 }, { 38, 0x89 }, { 39, 0x1b }, { 40, 0x0f }, { 41, 0xbb }, { 42, 0xd5 }, { 43, 0x9b }, { 44, 0x0e }, { 45, 0xa2 }, { 46, 0x73 }, { 47, 0x0c }, { 48, 0x10 }, { 49, 0x94 }, { 50, 0x94 }, { 51, 0x3a }, { 52, 0x48 }, { 53, 0x44 }, { 54, 0x38 }, { 55, 0x43 }, { 56, 0xa1 }, { 57, 0x00 }, { 58, 0x39 }, { 59, 0x07 }, { 60, 0x45 }, { 61, 0x91 }, { 62, 0x39 }, { 63, 0x07 } | |||
502 | },rt5592_def_rf[] = { | |||
503 | RT5592_DEF_RF{ 1, 0x3f }, { 3, 0x08 }, { 5, 0x10 }, { 6, 0xe4 }, { 7, 0x00 }, { 14, 0x00 }, { 15, 0x00 }, { 16, 0x00 }, { 18, 0x03 }, { 19, 0x4d }, { 20, 0x10 }, { 21, 0x8d }, { 26, 0x82 }, { 28, 0x00 }, { 29, 0x10 }, { 33, 0xc0 }, { 34, 0x07 }, { 35, 0x12 }, { 47, 0x0c }, { 53, 0x22 }, { 63, 0x07 } | |||
504 | },rt5592_2ghz_def_rf[] = { | |||
505 | RT5592_2GHZ_DEF_RF{ 10, 0x90 }, { 11, 0x4a }, { 12, 0x52 }, { 13, 0x42 }, { 22, 0x40 }, { 24, 0x4a }, { 25, 0x80 }, { 27, 0x42 }, { 36, 0x80 }, { 37, 0x08 }, { 38, 0x89 }, { 39, 0x1b }, { 40, 0x0d }, { 41, 0x9b }, { 42, 0xd5 }, { 43, 0x72 }, { 44, 0x0e }, { 45, 0xa2 }, { 46, 0x6b }, { 48, 0x10 }, { 51, 0x3e }, { 52, 0x48 }, { 54, 0x38 }, { 56, 0xa1 }, { 57, 0x00 }, { 58, 0x39 }, { 60, 0x45 }, { 61, 0x91 }, { 62, 0x39 } | |||
506 | },rt5592_5ghz_def_rf[] = { | |||
507 | RT5592_5GHZ_DEF_RF{ 10, 0x97 }, { 11, 0x40 }, { 25, 0xbf }, { 27, 0x42 }, { 36, 0x00 }, { 37, 0x04 }, { 38, 0x85 }, { 40, 0x42 }, { 41, 0xbb }, { 42, 0xd7 }, { 45, 0x41 }, { 48, 0x00 }, { 57, 0x77 }, { 60, 0x05 }, { 61, 0x01 } | |||
508 | }; | |||
509 | ||||
510 | static const struct { | |||
511 | u_int firstchan; | |||
512 | u_int lastchan; | |||
513 | uint8_t reg; | |||
514 | uint8_t val; | |||
515 | } rt5592_chan_5ghz[] = { | |||
516 | RT5592_CHAN_5GHZ{ 36, 64, 12, 0x2e }, { 100, 165, 12, 0x0e }, { 36, 64, 13, 0x22 }, { 100, 165, 13, 0x42 }, { 36, 64, 22, 0x60 }, { 100, 165, 22, 0x40 }, { 36, 64, 23, 0x7f }, { 100, 153, 23, 0x3c }, { 155 , 165, 23, 0x38 }, { 36, 50, 24, 0x09 }, { 52, 64, 24, 0x07 } , { 100, 153, 24, 0x06 }, { 155, 165, 24, 0x05 }, { 36, 64, 39 , 0x1c }, { 100, 138, 39, 0x1a }, { 140, 165, 39, 0x18 }, { 36 , 64, 43, 0x5b }, { 100, 138, 43, 0x3b }, { 140, 165, 43, 0x1b }, { 36, 64, 44, 0x40 }, { 100, 138, 44, 0x20 }, { 140, 165, 44, 0x10 }, { 36, 64, 46, 0x00 }, { 100, 138, 46, 0x18 }, { 140 , 165, 46, 0x08 }, { 36, 64, 51, 0xfe }, { 100, 124, 51, 0xfc }, { 126, 165, 51, 0xec }, { 36, 64, 52, 0x0c }, { 100, 138, 52, 0x06 }, { 140, 165, 52, 0x06 }, { 36, 64, 54, 0xf8 }, { 100 , 165, 54, 0xeb }, { 36, 50, 55, 0x06 }, { 52, 64, 55, 0x04 } , { 100, 138, 55, 0x01 }, { 140, 165, 55, 0x00 }, { 36, 50, 56 , 0xd3 }, { 52, 128, 56, 0xbb }, { 130, 165, 56, 0xab }, { 36 , 64, 58, 0x15 }, { 100, 116, 58, 0x1d }, { 118, 165, 58, 0x15 }, { 36, 64, 59, 0x7f }, { 100, 138, 59, 0x3f }, { 140, 165, 59, 0x7c }, { 36, 64, 62, 0x15 }, { 100, 116, 62, 0x1d }, { 118 , 165, 62, 0x15 } | |||
517 | }; | |||
518 | ||||
519 | int | |||
520 | run_match(struct device *parent, void *match, void *aux) | |||
521 | { | |||
522 | struct usb_attach_arg *uaa = aux; | |||
523 | ||||
524 | if (uaa->iface == NULL((void *)0) || uaa->configno != 1) | |||
525 | return UMATCH_NONE0; | |||
526 | ||||
527 | return (usb_lookup(run_devs, uaa->vendor, uaa->product)usbd_match_device((const struct usb_devno *)(run_devs), sizeof (run_devs) / sizeof ((run_devs)[0]), sizeof ((run_devs)[0]), (uaa->vendor), (uaa->product)) != NULL((void *)0)) ? | |||
528 | UMATCH_VENDOR_PRODUCT_CONF_IFACE8 : UMATCH_NONE0; | |||
529 | } | |||
530 | ||||
531 | void | |||
532 | run_attach(struct device *parent, struct device *self, void *aux) | |||
533 | { | |||
534 | struct run_softc *sc = (struct run_softc *)self; | |||
535 | struct usb_attach_arg *uaa = aux; | |||
536 | struct ieee80211com *ic = &sc->sc_ic; | |||
537 | struct ifnet *ifp = &ic->ic_ific_ac.ac_if; | |||
538 | usb_interface_descriptor_t *id; | |||
539 | usb_endpoint_descriptor_t *ed; | |||
540 | int i, nrx, ntx, ntries; | |||
541 | uint32_t ver; | |||
542 | ||||
543 | sc->sc_udev = uaa->device; | |||
544 | sc->sc_iface = uaa->iface; | |||
545 | ||||
546 | /* | |||
547 | * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX | |||
548 | * and 6 for TX (4 EDCAs + HCCA + Prio). | |||
549 | * Update 03-14-2009: some devices like the Planex GW-US300MiniS | |||
550 | * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). | |||
551 | */ | |||
552 | nrx = ntx = 0; | |||
553 | id = usbd_get_interface_descriptor(sc->sc_iface); | |||
554 | for (i = 0; i < id->bNumEndpoints; i++) { | |||
555 | ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); | |||
556 | if (ed == NULL((void *)0) || UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) != UE_BULK0x02) | |||
557 | continue; | |||
558 | ||||
559 | if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_IN0x80) { | |||
560 | sc->rxq.pipe_no = ed->bEndpointAddress; | |||
561 | nrx++; | |||
562 | } else if (ntx < 4) { | |||
563 | sc->txq[ntx].pipe_no = ed->bEndpointAddress; | |||
564 | ntx++; | |||
565 | } | |||
566 | } | |||
567 | /* make sure we've got them all */ | |||
568 | if (nrx < 1 || ntx < 4) { | |||
569 | printf("%s: missing endpoint\n", sc->sc_dev.dv_xname); | |||
570 | return; | |||
571 | } | |||
572 | ||||
573 | usb_init_task(&sc->sc_task, run_task, sc, USB_TASK_TYPE_GENERIC)((&sc->sc_task)->fun = (run_task), (&sc->sc_task )->arg = (sc), (&sc->sc_task)->type = (0), (& sc->sc_task)->state = 0x0); | |||
574 | timeout_set(&sc->scan_to, run_next_scan, sc); | |||
575 | timeout_set(&sc->calib_to, run_calibrate_to, sc); | |||
576 | ||||
577 | sc->amrr.amrr_min_success_threshold = 1; | |||
578 | sc->amrr.amrr_max_success_threshold = 10; | |||
579 | ||||
580 | /* wait for the chip to settle */ | |||
581 | for (ntries = 0; ntries < 100; ntries++) { | |||
582 | if (run_read(sc, RT2860_ASIC_VER_ID0x1000, &ver) != 0) | |||
583 | return; | |||
584 | if (ver != 0 && ver != 0xffffffff) | |||
585 | break; | |||
586 | DELAY(10)(*delay_func)(10); | |||
587 | } | |||
588 | if (ntries == 100) { | |||
589 | printf("%s: timeout waiting for NIC to initialize\n", | |||
590 | sc->sc_dev.dv_xname); | |||
591 | return; | |||
592 | } | |||
593 | sc->mac_ver = ver >> 16; | |||
594 | sc->mac_rev = ver & 0xffff; | |||
595 | ||||
596 | /* retrieve RF rev. no and various other things from EEPROM */ | |||
597 | run_read_eeprom(sc); | |||
598 | ||||
599 | printf("%s: MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), " | |||
600 | "address %s\n", sc->sc_dev.dv_xname, sc->mac_ver, | |||
601 | sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, | |||
602 | sc->nrxchains, ether_sprintf(ic->ic_myaddr)); | |||
603 | ||||
604 | ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ | |||
605 | ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ | |||
606 | ic->ic_state = IEEE80211_S_INIT; | |||
607 | ||||
608 | /* set device capabilities */ | |||
609 | ic->ic_caps = | |||
610 | IEEE80211_C_MONITOR0x00000200 | /* monitor mode supported */ | |||
611 | IEEE80211_C_SHPREAMBLE0x00000100 | /* short preamble supported */ | |||
612 | IEEE80211_C_SHSLOT0x00000080 | /* short slot time supported */ | |||
613 | IEEE80211_C_WEP0x00000001 | /* WEP */ | |||
614 | IEEE80211_C_RSN0x00001000; /* WPA/RSN */ | |||
615 | ||||
616 | if (sc->rf_rev == RT2860_RF_27500x0004 || | |||
617 | sc->rf_rev == RT2860_RF_28500x0002 || | |||
618 | sc->rf_rev == RT3070_RF_30520x0009 || | |||
619 | sc->rf_rev == RT3070_RF_30530x000d || | |||
620 | sc->rf_rev == RT5592_RF_55920x000f) { | |||
621 | /* set supported .11a rates */ | |||
622 | ic->ic_sup_rates[IEEE80211_MODE_11A] = | |||
623 | ieee80211_std_rateset_11a; | |||
624 | ||||
625 | /* set supported .11a channels */ | |||
626 | for (i = 14; i < nitems(rt2860_rf2850)(sizeof((rt2860_rf2850)) / sizeof((rt2860_rf2850)[0])); i++) { | |||
627 | uint8_t chan = rt2860_rf2850[i].chan; | |||
628 | ic->ic_channels[chan].ic_freq = | |||
629 | ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ0x0100); | |||
630 | ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A(0x0100 | 0x0040); | |||
631 | } | |||
632 | } | |||
633 | ||||
634 | /* set supported .11b and .11g rates */ | |||
635 | ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; | |||
636 | ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; | |||
637 | ||||
638 | /* set supported .11b and .11g channels (1 through 14) */ | |||
639 | for (i = 1; i <= 14; i++) { | |||
640 | ic->ic_channels[i].ic_freq = | |||
641 | ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ0x0080); | |||
642 | ic->ic_channels[i].ic_flags = | |||
643 | IEEE80211_CHAN_CCK0x0020 | IEEE80211_CHAN_OFDM0x0040 | | |||
644 | IEEE80211_CHAN_DYN0x0400 | IEEE80211_CHAN_2GHZ0x0080; | |||
645 | } | |||
646 | ||||
647 | ifp->if_softc = sc; | |||
648 | ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000; | |||
649 | ifp->if_ioctl = run_ioctl; | |||
650 | ifp->if_start = run_start; | |||
651 | ifp->if_watchdog = run_watchdog; | |||
652 | memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ)__builtin_memcpy((ifp->if_xname), (sc->sc_dev.dv_xname) , (16)); | |||
653 | ||||
654 | if_attach(ifp); | |||
655 | ieee80211_ifattach(ifp); | |||
656 | ic->ic_node_alloc = run_node_alloc; | |||
657 | ic->ic_newassoc = run_newassoc; | |||
658 | ic->ic_updateslot = run_updateslot; | |||
659 | ic->ic_updateedca = run_updateedca; | |||
660 | ic->ic_set_key = run_set_key; | |||
661 | ic->ic_delete_key = run_delete_key; | |||
662 | /* override state transition machine */ | |||
663 | sc->sc_newstate = ic->ic_newstate; | |||
664 | ic->ic_newstate = run_newstate; | |||
665 | ieee80211_media_init(ifp, run_media_change, ieee80211_media_status); | |||
666 | ||||
667 | #if NBPFILTER1 > 0 | |||
668 | bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO127, | |||
669 | sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN64); | |||
670 | ||||
671 | sc->sc_rxtap_len = sizeof sc->sc_rxtapu; | |||
672 | sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_len = htole16(sc->sc_rxtap_len)((__uint16_t)(sc->sc_rxtap_len)); | |||
673 | sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 << IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL | 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | 1 << IEEE80211_RADIOTAP_ANTENNA | 1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL))); | |||
674 | ||||
675 | sc->sc_txtap_len = sizeof sc->sc_txtapu; | |||
676 | sc->sc_txtapsc_txtapu.th.wt_ihdr.it_len = htole16(sc->sc_txtap_len)((__uint16_t)(sc->sc_txtap_len)); | |||
677 | sc->sc_txtapsc_txtapu.th.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 << IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL ))); | |||
678 | #endif | |||
679 | } | |||
680 | ||||
681 | int | |||
682 | run_detach(struct device *self, int flags) | |||
683 | { | |||
684 | struct run_softc *sc = (struct run_softc *)self; | |||
685 | struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if; | |||
686 | int qid, s; | |||
687 | ||||
688 | s = splusb()splraise(0x2); | |||
689 | ||||
690 | if (timeout_initialized(&sc->scan_to)((&sc->scan_to)->to_flags & 0x04)) | |||
691 | timeout_del(&sc->scan_to); | |||
692 | if (timeout_initialized(&sc->calib_to)((&sc->calib_to)->to_flags & 0x04)) | |||
693 | timeout_del(&sc->calib_to); | |||
694 | ||||
695 | /* wait for all queued asynchronous commands to complete */ | |||
696 | usb_rem_wait_task(sc->sc_udev, &sc->sc_task); | |||
697 | ||||
698 | usbd_ref_wait(sc->sc_udev); | |||
699 | ||||
700 | if (ifp->if_softc != NULL((void *)0)) { | |||
701 | ifp->if_flags &= ~IFF_RUNNING0x40; | |||
702 | ifq_clr_oactive(&ifp->if_snd); | |||
703 | ieee80211_ifdetach(ifp); | |||
704 | if_detach(ifp); | |||
705 | } | |||
706 | ||||
707 | for (qid = 0; qid < 4; qid++) | |||
708 | run_free_tx_ring(sc, qid); | |||
709 | run_free_rx_ring(sc); | |||
710 | ||||
711 | splx(s)spllower(s); | |||
712 | ||||
713 | return 0; | |||
714 | } | |||
715 | ||||
716 | int | |||
717 | run_alloc_rx_ring(struct run_softc *sc) | |||
718 | { | |||
719 | struct run_rx_ring *rxq = &sc->rxq; | |||
720 | int i, error; | |||
721 | ||||
722 | error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); | |||
723 | if (error != 0) | |||
724 | goto fail; | |||
725 | ||||
726 | for (i = 0; i < RUN_RX_RING_COUNT1; i++) { | |||
727 | struct run_rx_data *data = &rxq->data[i]; | |||
728 | ||||
729 | data->sc = sc; /* backpointer for callbacks */ | |||
730 | ||||
731 | data->xfer = usbd_alloc_xfer(sc->sc_udev); | |||
732 | if (data->xfer == NULL((void *)0)) { | |||
733 | error = ENOMEM12; | |||
734 | goto fail; | |||
735 | } | |||
736 | data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_RXSZ4096); | |||
737 | if (data->buf == NULL((void *)0)) { | |||
738 | error = ENOMEM12; | |||
739 | goto fail; | |||
740 | } | |||
741 | } | |||
742 | if (error != 0) | |||
743 | fail: run_free_rx_ring(sc); | |||
744 | return error; | |||
745 | } | |||
746 | ||||
747 | void | |||
748 | run_free_rx_ring(struct run_softc *sc) | |||
749 | { | |||
750 | struct run_rx_ring *rxq = &sc->rxq; | |||
751 | int i; | |||
752 | ||||
753 | if (rxq->pipeh != NULL((void *)0)) { | |||
754 | usbd_close_pipe(rxq->pipeh); | |||
755 | rxq->pipeh = NULL((void *)0); | |||
756 | } | |||
757 | for (i = 0; i < RUN_RX_RING_COUNT1; i++) { | |||
758 | if (rxq->data[i].xfer != NULL((void *)0)) | |||
759 | usbd_free_xfer(rxq->data[i].xfer); | |||
760 | rxq->data[i].xfer = NULL((void *)0); | |||
761 | } | |||
762 | } | |||
763 | ||||
764 | int | |||
765 | run_alloc_tx_ring(struct run_softc *sc, int qid) | |||
766 | { | |||
767 | struct run_tx_ring *txq = &sc->txq[qid]; | |||
768 | int i, error; | |||
769 | uint16_t txwisize; | |||
770 | ||||
771 | txwisize = sizeof(struct rt2860_txwi); | |||
772 | if (sc->mac_ver == 0x5592) | |||
773 | txwisize += sizeof(uint32_t); | |||
774 | ||||
775 | txq->cur = txq->queued = 0; | |||
776 | ||||
777 | error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); | |||
778 | if (error != 0) | |||
779 | goto fail; | |||
780 | ||||
781 | for (i = 0; i < RUN_TX_RING_COUNT8; i++) { | |||
782 | struct run_tx_data *data = &txq->data[i]; | |||
783 | ||||
784 | data->sc = sc; /* backpointer for callbacks */ | |||
785 | data->qid = qid; | |||
786 | ||||
787 | data->xfer = usbd_alloc_xfer(sc->sc_udev); | |||
788 | if (data->xfer == NULL((void *)0)) { | |||
789 | error = ENOMEM12; | |||
790 | goto fail; | |||
791 | } | |||
792 | data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_TXSZ(sizeof (struct rt2870_txd) + sizeof (struct rt2860_txwi) + ( 1 << 11) + 11)); | |||
793 | if (data->buf == NULL((void *)0)) { | |||
794 | error = ENOMEM12; | |||
795 | goto fail; | |||
796 | } | |||
797 | /* zeroize the TXD + TXWI part */ | |||
798 | memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize)__builtin_memset((data->buf), (0), (sizeof(struct rt2870_txd ) + txwisize)); | |||
799 | } | |||
800 | if (error != 0) | |||
801 | fail: run_free_tx_ring(sc, qid); | |||
802 | return error; | |||
803 | } | |||
804 | ||||
805 | void | |||
806 | run_free_tx_ring(struct run_softc *sc, int qid) | |||
807 | { | |||
808 | struct run_tx_ring *txq = &sc->txq[qid]; | |||
809 | int i; | |||
810 | ||||
811 | if (txq->pipeh != NULL((void *)0)) { | |||
812 | usbd_close_pipe(txq->pipeh); | |||
813 | txq->pipeh = NULL((void *)0); | |||
814 | } | |||
815 | for (i = 0; i < RUN_TX_RING_COUNT8; i++) { | |||
816 | if (txq->data[i].xfer != NULL((void *)0)) | |||
817 | usbd_free_xfer(txq->data[i].xfer); | |||
818 | txq->data[i].xfer = NULL((void *)0); | |||
819 | } | |||
820 | } | |||
821 | ||||
822 | int | |||
823 | run_load_microcode(struct run_softc *sc) | |||
824 | { | |||
825 | usb_device_request_t req; | |||
826 | const char *fwname; | |||
827 | u_char *ucode; | |||
828 | size_t size; | |||
829 | uint32_t tmp; | |||
830 | int ntries, error; | |||
831 | ||||
832 | /* RT3071/RT3072 use a different firmware */ | |||
833 | if (sc->mac_ver != 0x2860 && | |||
834 | sc->mac_ver != 0x2872 && | |||
835 | sc->mac_ver != 0x3070) | |||
836 | fwname = "run-rt3071"; | |||
837 | else | |||
838 | fwname = "run-rt2870"; | |||
839 | ||||
840 | if ((error = loadfirmware(fwname, &ucode, &size)) != 0) { | |||
841 | printf("%s: failed loadfirmware of file %s (error %d)\n", | |||
842 | sc->sc_dev.dv_xname, fwname, error); | |||
843 | return error; | |||
844 | } | |||
845 | if (size != 4096) { | |||
846 | printf("%s: invalid firmware size (should be 4KB)\n", | |||
847 | sc->sc_dev.dv_xname); | |||
848 | free(ucode, M_DEVBUF2, size); | |||
849 | return EINVAL22; | |||
850 | } | |||
851 | ||||
852 | /* write microcode image */ | |||
853 | run_write_region_1(sc, RT2870_FW_BASE0x3000, ucode, size); | |||
854 | free(ucode, M_DEVBUF2, size); | |||
855 | run_write(sc, RT2860_H2M_MAILBOX_CID0x7014, 0xffffffff); | |||
856 | run_write(sc, RT2860_H2M_MAILBOX_STATUS0x701c, 0xffffffff); | |||
857 | ||||
858 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00); | |||
859 | req.bRequest = RT2870_RESET1; | |||
860 | USETW(req.wValue, 8)(*(u_int16_t *)(req.wValue) = (8)); | |||
861 | USETW(req.wIndex, 0)(*(u_int16_t *)(req.wIndex) = (0)); | |||
862 | USETW(req.wLength, 0)(*(u_int16_t *)(req.wLength) = (0)); | |||
863 | if ((error = usbd_do_request(sc->sc_udev, &req, NULL((void *)0))) != 0) | |||
864 | return error; | |||
865 | ||||
866 | usbd_delay_ms(sc->sc_udev, 10); | |||
867 | run_write(sc, RT2860_H2M_BBPAGENT0x7028, 0); | |||
868 | run_write(sc, RT2860_H2M_MAILBOX0x7010, 0); | |||
869 | run_write(sc, RT2860_H2M_INTSRC0x7024, 0); | |||
870 | if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET0x72, 0)) != 0) | |||
871 | return error; | |||
872 | ||||
873 | /* wait until microcontroller is ready */ | |||
874 | for (ntries = 0; ntries < 1000; ntries++) { | |||
875 | if ((error = run_read(sc, RT2860_SYS_CTRL0x0400, &tmp)) != 0) | |||
876 | return error; | |||
877 | if (tmp & RT2860_MCU_READY(1 << 7)) | |||
878 | break; | |||
879 | DELAY(1000)(*delay_func)(1000); | |||
880 | } | |||
881 | if (ntries == 1000) { | |||
882 | printf("%s: timeout waiting for MCU to initialize\n", | |||
883 | sc->sc_dev.dv_xname); | |||
884 | return ETIMEDOUT60; | |||
885 | } | |||
886 | DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); | |||
887 | return 0; | |||
888 | } | |||
889 | ||||
890 | int | |||
891 | run_reset(struct run_softc *sc) | |||
892 | { | |||
893 | usb_device_request_t req; | |||
894 | ||||
895 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00); | |||
896 | req.bRequest = RT2870_RESET1; | |||
897 | USETW(req.wValue, 1)(*(u_int16_t *)(req.wValue) = (1)); | |||
898 | USETW(req.wIndex, 0)(*(u_int16_t *)(req.wIndex) = (0)); | |||
899 | USETW(req.wLength, 0)(*(u_int16_t *)(req.wLength) = (0)); | |||
900 | return usbd_do_request(sc->sc_udev, &req, NULL((void *)0)); | |||
901 | } | |||
902 | ||||
903 | int | |||
904 | run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) | |||
905 | { | |||
906 | uint32_t tmp; | |||
907 | int error; | |||
908 | ||||
909 | error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp); | |||
910 | if (error == 0) | |||
911 | *val = letoh32(tmp)((__uint32_t)(tmp)); | |||
912 | else | |||
913 | *val = 0xffffffff; | |||
914 | return error; | |||
915 | } | |||
916 | ||||
917 | int | |||
918 | run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) | |||
919 | { | |||
920 | usb_device_request_t req; | |||
921 | ||||
922 | req.bmRequestType = UT_READ_VENDOR_DEVICE(0x80 | 0x40 | 0x00); | |||
923 | req.bRequest = RT2870_READ_REGION_17; | |||
924 | USETW(req.wValue, 0)(*(u_int16_t *)(req.wValue) = (0)); | |||
925 | USETW(req.wIndex, reg)(*(u_int16_t *)(req.wIndex) = (reg)); | |||
926 | USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len)); | |||
927 | return usbd_do_request(sc->sc_udev, &req, buf); | |||
928 | } | |||
929 | ||||
930 | int | |||
931 | run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) | |||
932 | { | |||
933 | usb_device_request_t req; | |||
934 | ||||
935 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00); | |||
936 | req.bRequest = RT2870_WRITE_22; | |||
937 | USETW(req.wValue, val)(*(u_int16_t *)(req.wValue) = (val)); | |||
938 | USETW(req.wIndex, reg)(*(u_int16_t *)(req.wIndex) = (reg)); | |||
939 | USETW(req.wLength, 0)(*(u_int16_t *)(req.wLength) = (0)); | |||
940 | return usbd_do_request(sc->sc_udev, &req, NULL((void *)0)); | |||
941 | } | |||
942 | ||||
943 | int | |||
944 | run_write(struct run_softc *sc, uint16_t reg, uint32_t val) | |||
945 | { | |||
946 | int error; | |||
947 | ||||
948 | if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) | |||
949 | error = run_write_2(sc, reg + 2, val >> 16); | |||
950 | return error; | |||
951 | } | |||
952 | ||||
953 | int | |||
954 | run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, | |||
955 | int len) | |||
956 | { | |||
957 | #if 1 | |||
958 | int i, error = 0; | |||
959 | /* | |||
960 | * NB: the WRITE_REGION_1 command is not stable on RT2860. | |||
961 | * We thus issue multiple WRITE_2 commands instead. | |||
962 | */ | |||
963 | KASSERT((len & 1) == 0)(((len & 1) == 0) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/usb/if_run.c" , 963, "(len & 1) == 0")); | |||
964 | for (i = 0; i < len && error == 0; i += 2) | |||
965 | error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); | |||
966 | return error; | |||
967 | #else | |||
968 | usb_device_request_t req; | |||
969 | ||||
970 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00); | |||
971 | req.bRequest = RT2870_WRITE_REGION_16; | |||
972 | USETW(req.wValue, 0)(*(u_int16_t *)(req.wValue) = (0)); | |||
973 | USETW(req.wIndex, reg)(*(u_int16_t *)(req.wIndex) = (reg)); | |||
974 | USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len)); | |||
975 | return usbd_do_request(sc->sc_udev, &req, buf); | |||
976 | #endif | |||
977 | } | |||
978 | ||||
979 | int | |||
980 | run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) | |||
981 | { | |||
982 | int error = 0; | |||
983 | ||||
984 | for (; count > 0 && error == 0; count--, reg += 4) | |||
985 | error = run_write(sc, reg, val); | |||
986 | return error; | |||
987 | } | |||
988 | ||||
989 | /* Read 16-bit from eFUSE ROM. */ | |||
990 | int | |||
991 | run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val) | |||
992 | { | |||
993 | uint32_t tmp; | |||
994 | uint16_t reg; | |||
995 | int error, ntries; | |||
996 | ||||
997 | if ((error = run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp)) != 0) | |||
998 | return error; | |||
999 | ||||
1000 | /*- | |||
1001 | * Read one 16-byte block into registers EFUSE_DATA[0-3]: | |||
1002 | * DATA0: F E D C | |||
1003 | * DATA1: B A 9 8 | |||
1004 | * DATA2: 7 6 5 4 | |||
1005 | * DATA3: 3 2 1 0 | |||
1006 | */ | |||
1007 | tmp &= ~(RT3070_EFSROM_MODE_MASK0x000000c0 | RT3070_EFSROM_AIN_MASK0x03ff0000); | |||
1008 | tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT16 | RT3070_EFSROM_KICK(1U << 30); | |||
1009 | run_write(sc, RT3070_EFUSE_CTRL0x0580, tmp); | |||
1010 | for (ntries = 0; ntries < 100; ntries++) { | |||
1011 | if ((error = run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp)) != 0) | |||
1012 | return error; | |||
1013 | if (!(tmp & RT3070_EFSROM_KICK(1U << 30))) | |||
1014 | break; | |||
1015 | DELAY(2)(*delay_func)(2); | |||
1016 | } | |||
1017 | if (ntries == 100) | |||
1018 | return ETIMEDOUT60; | |||
1019 | ||||
1020 | if ((tmp & RT3070_EFUSE_AOUT_MASK0x0000003f) == RT3070_EFUSE_AOUT_MASK0x0000003f) { | |||
1021 | *val = 0xffff; /* address not found */ | |||
1022 | return 0; | |||
1023 | } | |||
1024 | /* determine to which 32-bit register our 16-bit word belongs */ | |||
1025 | reg = RT3070_EFUSE_DATA30x059c - (addr & 0xc); | |||
1026 | if ((error = run_read(sc, reg, &tmp)) != 0) | |||
1027 | return error; | |||
1028 | ||||
1029 | tmp >>= (8 * (addr & 0x3)); | |||
1030 | *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; | |||
1031 | return 0; | |||
1032 | } | |||
1033 | ||||
1034 | /* Read 16-bit from eFUSE ROM for RT3xxx. */ | |||
1035 | int | |||
1036 | run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) | |||
1037 | { | |||
1038 | uint32_t tmp; | |||
1039 | uint16_t reg; | |||
1040 | int error, ntries; | |||
1041 | ||||
1042 | if ((error = run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp)) != 0) | |||
1043 | return error; | |||
1044 | ||||
1045 | addr *= 2; | |||
1046 | /*- | |||
1047 | * Read one 16-byte block into registers EFUSE_DATA[0-3]: | |||
1048 | * DATA0: F E D C | |||
1049 | * DATA1: B A 9 8 | |||
1050 | * DATA2: 7 6 5 4 | |||
1051 | * DATA3: 3 2 1 0 | |||
1052 | */ | |||
1053 | tmp &= ~(RT3070_EFSROM_MODE_MASK0x000000c0 | RT3070_EFSROM_AIN_MASK0x03ff0000); | |||
1054 | tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT16 | RT3070_EFSROM_KICK(1U << 30); | |||
1055 | run_write(sc, RT3070_EFUSE_CTRL0x0580, tmp); | |||
1056 | for (ntries = 0; ntries < 100; ntries++) { | |||
1057 | if ((error = run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp)) != 0) | |||
1058 | return error; | |||
1059 | if (!(tmp & RT3070_EFSROM_KICK(1U << 30))) | |||
1060 | break; | |||
1061 | DELAY(2)(*delay_func)(2); | |||
1062 | } | |||
1063 | if (ntries == 100) | |||
1064 | return ETIMEDOUT60; | |||
1065 | ||||
1066 | if ((tmp & RT3070_EFUSE_AOUT_MASK0x0000003f) == RT3070_EFUSE_AOUT_MASK0x0000003f) { | |||
1067 | *val = 0xffff; /* address not found */ | |||
1068 | return 0; | |||
1069 | } | |||
1070 | /* determine to which 32-bit register our 16-bit word belongs */ | |||
1071 | reg = RT3070_EFUSE_DATA30x059c - (addr & 0xc); | |||
1072 | if ((error = run_read(sc, reg, &tmp)) != 0) | |||
1073 | return error; | |||
1074 | ||||
1075 | *val = (addr & 2) ? tmp >> 16 : tmp & 0xffff; | |||
1076 | return 0; | |||
1077 | } | |||
1078 | ||||
1079 | int | |||
1080 | run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) | |||
1081 | { | |||
1082 | usb_device_request_t req; | |||
1083 | uint16_t tmp; | |||
1084 | int error; | |||
1085 | ||||
1086 | addr *= 2; | |||
1087 | req.bmRequestType = UT_READ_VENDOR_DEVICE(0x80 | 0x40 | 0x00); | |||
1088 | req.bRequest = RT2870_EEPROM_READ9; | |||
1089 | USETW(req.wValue, 0)(*(u_int16_t *)(req.wValue) = (0)); | |||
1090 | USETW(req.wIndex, addr)(*(u_int16_t *)(req.wIndex) = (addr)); | |||
1091 | USETW(req.wLength, sizeof tmp)(*(u_int16_t *)(req.wLength) = (sizeof tmp)); | |||
1092 | error = usbd_do_request(sc->sc_udev, &req, &tmp); | |||
1093 | if (error == 0) | |||
1094 | *val = letoh16(tmp)((__uint16_t)(tmp)); | |||
1095 | else | |||
1096 | *val = 0xffff; | |||
1097 | return error; | |||
1098 | } | |||
1099 | ||||
1100 | static __inline int | |||
1101 | run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) | |||
1102 | { | |||
1103 | /* either eFUSE ROM or EEPROM */ | |||
1104 | return sc->sc_srom_read(sc, addr, val); | |||
1105 | } | |||
1106 | ||||
1107 | int | |||
1108 | run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) | |||
1109 | { | |||
1110 | uint32_t tmp; | |||
1111 | int error, ntries; | |||
1112 | ||||
1113 | for (ntries = 0; ntries < 10; ntries++) { | |||
1114 | if ((error = run_read(sc, RT2860_RF_CSR_CFG00x1020, &tmp)) != 0) | |||
1115 | return error; | |||
1116 | if (!(tmp & RT2860_RF_REG_CTRL(1U << 31))) | |||
1117 | break; | |||
1118 | } | |||
1119 | if (ntries == 10) | |||
1120 | return ETIMEDOUT60; | |||
1121 | ||||
1122 | /* RF registers are 24-bit on the RT2860 */ | |||
1123 | tmp = RT2860_RF_REG_CTRL(1U << 31) | 24 << RT2860_RF_REG_WIDTH_SHIFT24 | | |||
1124 | (val & 0x3fffff) << 2 | (reg & 3); | |||
1125 | return run_write(sc, RT2860_RF_CSR_CFG00x1020, tmp); | |||
1126 | } | |||
1127 | ||||
1128 | int | |||
1129 | run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) | |||
1130 | { | |||
1131 | uint32_t tmp; | |||
1132 | int error, ntries; | |||
1133 | ||||
1134 | for (ntries = 0; ntries < 100; ntries++) { | |||
1135 | if ((error = run_read(sc, RT3070_RF_CSR_CFG0x0500, &tmp)) != 0) | |||
1136 | return error; | |||
1137 | if (!(tmp & RT3070_RF_KICK(1 << 17))) | |||
1138 | break; | |||
1139 | } | |||
1140 | if (ntries == 100) | |||
1141 | return ETIMEDOUT60; | |||
1142 | ||||
1143 | tmp = RT3070_RF_KICK(1 << 17) | reg << 8; | |||
1144 | if ((error = run_write(sc, RT3070_RF_CSR_CFG0x0500, tmp)) != 0) | |||
1145 | return error; | |||
1146 | ||||
1147 | for (ntries = 0; ntries < 100; ntries++) { | |||
1148 | if ((error = run_read(sc, RT3070_RF_CSR_CFG0x0500, &tmp)) != 0) | |||
1149 | return error; | |||
1150 | if (!(tmp & RT3070_RF_KICK(1 << 17))) | |||
1151 | break; | |||
1152 | } | |||
1153 | if (ntries == 100) | |||
1154 | return ETIMEDOUT60; | |||
1155 | ||||
1156 | *val = tmp & 0xff; | |||
1157 | return 0; | |||
1158 | } | |||
1159 | ||||
1160 | int | |||
1161 | run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) | |||
1162 | { | |||
1163 | uint32_t tmp; | |||
1164 | int error, ntries; | |||
1165 | ||||
1166 | for (ntries = 0; ntries < 10; ntries++) { | |||
1167 | if ((error = run_read(sc, RT3070_RF_CSR_CFG0x0500, &tmp)) != 0) | |||
1168 | return error; | |||
1169 | if (!(tmp & RT3070_RF_KICK(1 << 17))) | |||
1170 | break; | |||
1171 | } | |||
1172 | if (ntries == 10) | |||
1173 | return ETIMEDOUT60; | |||
1174 | ||||
1175 | tmp = RT3070_RF_WRITE(1 << 16) | RT3070_RF_KICK(1 << 17) | reg << 8 | val; | |||
1176 | return run_write(sc, RT3070_RF_CSR_CFG0x0500, tmp); | |||
1177 | } | |||
1178 | ||||
1179 | int | |||
1180 | run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) | |||
1181 | { | |||
1182 | uint32_t tmp; | |||
1183 | int ntries, error; | |||
1184 | ||||
1185 | for (ntries = 0; ntries < 10; ntries++) { | |||
1186 | if ((error = run_read(sc, RT2860_BBP_CSR_CFG0x101c, &tmp)) != 0) | |||
1187 | return error; | |||
1188 | if (!(tmp & RT2860_BBP_CSR_KICK(1 << 17))) | |||
1189 | break; | |||
1190 | } | |||
1191 | if (ntries == 10) | |||
1192 | return ETIMEDOUT60; | |||
1193 | ||||
1194 | tmp = RT2860_BBP_CSR_READ(1 << 16) | RT2860_BBP_CSR_KICK(1 << 17) | reg << 8; | |||
1195 | if ((error = run_write(sc, RT2860_BBP_CSR_CFG0x101c, tmp)) != 0) | |||
1196 | return error; | |||
1197 | ||||
1198 | for (ntries = 0; ntries < 10; ntries++) { | |||
1199 | if ((error = run_read(sc, RT2860_BBP_CSR_CFG0x101c, &tmp)) != 0) | |||
1200 | return error; | |||
1201 | if (!(tmp & RT2860_BBP_CSR_KICK(1 << 17))) | |||
1202 | break; | |||
1203 | } | |||
1204 | if (ntries == 10) | |||
1205 | return ETIMEDOUT60; | |||
1206 | ||||
1207 | *val = tmp & 0xff; | |||
1208 | return 0; | |||
1209 | } | |||
1210 | ||||
1211 | int | |||
1212 | run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) | |||
1213 | { | |||
1214 | uint32_t tmp; | |||
1215 | int ntries, error; | |||
1216 | ||||
1217 | for (ntries = 0; ntries < 10; ntries++) { | |||
1218 | if ((error = run_read(sc, RT2860_BBP_CSR_CFG0x101c, &tmp)) != 0) | |||
1219 | return error; | |||
1220 | if (!(tmp & RT2860_BBP_CSR_KICK(1 << 17))) | |||
1221 | break; | |||
1222 | } | |||
1223 | if (ntries == 10) | |||
1224 | return ETIMEDOUT60; | |||
1225 | ||||
1226 | tmp = RT2860_BBP_CSR_KICK(1 << 17) | reg << 8 | val; | |||
1227 | return run_write(sc, RT2860_BBP_CSR_CFG0x101c, tmp); | |||
1228 | } | |||
1229 | ||||
1230 | /* | |||
1231 | * Send a command to the 8051 microcontroller unit. | |||
1232 | */ | |||
1233 | int | |||
1234 | run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) | |||
1235 | { | |||
1236 | uint32_t tmp; | |||
1237 | int error, ntries; | |||
1238 | ||||
1239 | for (ntries = 0; ntries < 100; ntries++) { | |||
1240 | if ((error = run_read(sc, RT2860_H2M_MAILBOX0x7010, &tmp)) != 0) | |||
1241 | return error; | |||
1242 | if (!(tmp & RT2860_H2M_BUSY(1 << 24))) | |||
1243 | break; | |||
1244 | } | |||
1245 | if (ntries == 100) | |||
1246 | return ETIMEDOUT60; | |||
1247 | ||||
1248 | tmp = RT2860_H2M_BUSY(1 << 24) | RT2860_TOKEN_NO_INTR0xff << 16 | arg; | |||
1249 | if ((error = run_write(sc, RT2860_H2M_MAILBOX0x7010, tmp)) == 0) | |||
1250 | error = run_write(sc, RT2860_HOST_CMD0x0404, cmd); | |||
1251 | return error; | |||
1252 | } | |||
1253 | ||||
1254 | /* | |||
1255 | * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. | |||
1256 | * Used to adjust per-rate Tx power registers. | |||
1257 | */ | |||
1258 | static __inline uint32_t | |||
1259 | b4inc(uint32_t b32, int8_t delta) | |||
1260 | { | |||
1261 | int8_t i, b4; | |||
1262 | ||||
1263 | for (i = 0; i < 8; i++) { | |||
1264 | b4 = b32 & 0xf; | |||
1265 | b4 += delta; | |||
1266 | if (b4 < 0) | |||
1267 | b4 = 0; | |||
1268 | else if (b4 > 0xf) | |||
1269 | b4 = 0xf; | |||
1270 | b32 = b32 >> 4 | b4 << 28; | |||
1271 | } | |||
1272 | return b32; | |||
1273 | } | |||
1274 | ||||
1275 | const char * | |||
1276 | run_get_rf(int rev) | |||
1277 | { | |||
1278 | switch (rev) { | |||
1279 | case RT2860_RF_28200x0001: return "RT2820"; | |||
1280 | case RT2860_RF_28500x0002: return "RT2850"; | |||
1281 | case RT2860_RF_27200x0003: return "RT2720"; | |||
1282 | case RT2860_RF_27500x0004: return "RT2750"; | |||
1283 | case RT3070_RF_30200x0005: return "RT3020"; | |||
1284 | case RT3070_RF_20200x0006: return "RT2020"; | |||
1285 | case RT3070_RF_30210x0007: return "RT3021"; | |||
1286 | case RT3070_RF_30220x0008: return "RT3022"; | |||
1287 | case RT3070_RF_30520x0009: return "RT3052"; | |||
1288 | case RT3070_RF_30530x000d: return "RT3053"; | |||
1289 | case RT5592_RF_55920x000f: return "RT5592"; | |||
1290 | case RT5390_RF_53700x5370: return "RT5370"; | |||
1291 | case RT5390_RF_53720x5372: return "RT5372"; | |||
1292 | } | |||
1293 | return "unknown"; | |||
1294 | } | |||
1295 | ||||
1296 | void | |||
1297 | run_rt3593_get_txpower(struct run_softc *sc) | |||
1298 | { | |||
1299 | uint16_t addr, val; | |||
1300 | int i; | |||
1301 | ||||
1302 | /* Read power settings for 2GHz channels. */ | |||
1303 | for (i = 0; i < 14; i += 2) { | |||
1304 | addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE10x30 : | |||
1305 | RT2860_EEPROM_PWR2GHZ_BASE10x29; | |||
1306 | run_srom_read(sc, addr + i / 2, &val); | |||
1307 | sc->txpow1[i + 0] = (int8_t)(val & 0xff); | |||
1308 | sc->txpow1[i + 1] = (int8_t)(val >> 8); | |||
1309 | ||||
1310 | addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE20x37 : | |||
1311 | RT2860_EEPROM_PWR2GHZ_BASE20x30; | |||
1312 | run_srom_read(sc, addr + i / 2, &val); | |||
1313 | sc->txpow2[i + 0] = (int8_t)(val & 0xff); | |||
1314 | sc->txpow2[i + 1] = (int8_t)(val >> 8); | |||
1315 | ||||
1316 | if (sc->ntxchains == 3) { | |||
1317 | run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE30x3e + i / 2, | |||
1318 | &val); | |||
1319 | sc->txpow3[i + 0] = (int8_t)(val & 0xff); | |||
1320 | sc->txpow3[i + 1] = (int8_t)(val >> 8); | |||
1321 | } | |||
1322 | } | |||
1323 | /* Fix broken Tx power entries. */ | |||
1324 | for (i = 0; i < 14; i++) { | |||
1325 | if (sc->txpow1[i] > 31) | |||
1326 | sc->txpow1[i] = 5; | |||
1327 | if (sc->txpow2[i] > 31) | |||
1328 | sc->txpow2[i] = 5; | |||
1329 | if (sc->ntxchains == 3) { | |||
1330 | if (sc->txpow3[i] > 31) | |||
1331 | sc->txpow3[i] = 5; | |||
1332 | } | |||
1333 | } | |||
1334 | /* Read power settings for 5GHz channels. */ | |||
1335 | for (i = 0; i < 40; i += 2) { | |||
1336 | run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE10x4b + i / 2, &val); | |||
1337 | sc->txpow1[i + 14] = (int8_t)(val & 0xff); | |||
1338 | sc->txpow1[i + 15] = (int8_t)(val >> 8); | |||
1339 | ||||
1340 | run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE20x65 + i / 2, &val); | |||
1341 | sc->txpow2[i + 14] = (int8_t)(val & 0xff); | |||
1342 | sc->txpow2[i + 15] = (int8_t)(val >> 8); | |||
1343 | ||||
1344 | if (sc->ntxchains == 3) { | |||
1345 | run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE30x7f + i / 2, | |||
1346 | &val); | |||
1347 | sc->txpow3[i + 14] = (int8_t)(val & 0xff); | |||
1348 | sc->txpow3[i + 15] = (int8_t)(val >> 8); | |||
1349 | } | |||
1350 | } | |||
1351 | } | |||
1352 | ||||
1353 | void | |||
1354 | run_get_txpower(struct run_softc *sc) | |||
1355 | { | |||
1356 | uint16_t val; | |||
1357 | int i; | |||
1358 | ||||
1359 | /* Read power settings for 2GHz channels. */ | |||
1360 | for (i = 0; i < 14; i += 2) { | |||
1361 | run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE10x29 + i / 2, &val); | |||
1362 | sc->txpow1[i + 0] = (int8_t)(val & 0xff); | |||
1363 | sc->txpow1[i + 1] = (int8_t)(val >> 8); | |||
1364 | ||||
1365 | if (sc->mac_ver != 0x5390) { | |||
1366 | run_srom_read(sc, | |||
1367 | RT2860_EEPROM_PWR2GHZ_BASE20x30 + i / 2, &val); | |||
1368 | sc->txpow2[i + 0] = (int8_t)(val & 0xff); | |||
1369 | sc->txpow2[i + 1] = (int8_t)(val >> 8); | |||
1370 | } | |||
1371 | } | |||
1372 | /* Fix broken Tx power entries. */ | |||
1373 | for (i = 0; i < 14; i++) { | |||
1374 | if (sc->mac_ver >= 0x5390) { | |||
1375 | if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27) | |||
1376 | sc->txpow1[i] = 5; | |||
1377 | } else { | |||
1378 | if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) | |||
1379 | sc->txpow1[i] = 5; | |||
1380 | } | |||
1381 | if (sc->mac_ver > 0x5390) { | |||
1382 | if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27) | |||
1383 | sc->txpow2[i] = 5; | |||
1384 | } else if (sc->mac_ver < 0x5390) { | |||
1385 | if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) | |||
1386 | sc->txpow2[i] = 5; | |||
1387 | } | |||
1388 | DPRINTF(("chan %d: power1=%d, power2=%d\n", | |||
1389 | rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); | |||
1390 | } | |||
1391 | /* Read power settings for 5GHz channels. */ | |||
1392 | for (i = 0; i < 40; i += 2) { | |||
1393 | run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE10x3c + i / 2, &val); | |||
1394 | sc->txpow1[i + 14] = (int8_t)(val & 0xff); | |||
1395 | sc->txpow1[i + 15] = (int8_t)(val >> 8); | |||
1396 | ||||
1397 | run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE20x53 + i / 2, &val); | |||
1398 | sc->txpow2[i + 14] = (int8_t)(val & 0xff); | |||
1399 | sc->txpow2[i + 15] = (int8_t)(val >> 8); | |||
1400 | } | |||
1401 | /* Fix broken Tx power entries. */ | |||
1402 | for (i = 0; i < 40; i++ ) { | |||
1403 | if (sc->mac_ver != 0x5592) { | |||
1404 | if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) | |||
1405 | sc->txpow1[14 + i] = 5; | |||
1406 | if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) | |||
1407 | sc->txpow2[14 + i] = 5; | |||
1408 | } | |||
1409 | DPRINTF(("chan %d: power1=%d, power2=%d\n", | |||
1410 | rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], | |||
1411 | sc->txpow2[14 + i])); | |||
1412 | } | |||
1413 | } | |||
1414 | ||||
1415 | int | |||
1416 | run_read_eeprom(struct run_softc *sc) | |||
1417 | { | |||
1418 | struct ieee80211com *ic = &sc->sc_ic; | |||
1419 | int8_t delta_2ghz, delta_5ghz; | |||
1420 | uint32_t tmp; | |||
1421 | uint16_t val; | |||
1422 | int ridx, ant, i; | |||
1423 | ||||
1424 | /* check whether the ROM is eFUSE ROM or EEPROM */ | |||
1425 | sc->sc_srom_read = run_eeprom_read_2; | |||
1426 | if (sc->mac_ver >= 0x3070) { | |||
1427 | run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp); | |||
1428 | DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); | |||
1429 | if (tmp & RT3070_SEL_EFUSE(1U << 31) || sc->mac_ver == 0x3593) | |||
1430 | sc->sc_srom_read = run_efuse_read_2; | |||
1431 | } | |||
1432 | ||||
1433 | /* read ROM version */ | |||
1434 | run_srom_read(sc, RT2860_EEPROM_VERSION0x01, &val); | |||
1435 | DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); | |||
1436 | ||||
1437 | /* read MAC address */ | |||
1438 | run_srom_read(sc, RT2860_EEPROM_MAC010x02, &val); | |||
1439 | ic->ic_myaddr[0] = val & 0xff; | |||
1440 | ic->ic_myaddr[1] = val >> 8; | |||
1441 | run_srom_read(sc, RT2860_EEPROM_MAC230x03, &val); | |||
1442 | ic->ic_myaddr[2] = val & 0xff; | |||
1443 | ic->ic_myaddr[3] = val >> 8; | |||
1444 | run_srom_read(sc, RT2860_EEPROM_MAC450x04, &val); | |||
1445 | ic->ic_myaddr[4] = val & 0xff; | |||
1446 | ic->ic_myaddr[5] = val >> 8; | |||
1447 | ||||
1448 | if (sc->mac_ver < 0x3593) { | |||
1449 | /* read vendor BBP settings */ | |||
1450 | for (i = 0; i < 10; i++) { | |||
1451 | run_srom_read(sc, RT2860_EEPROM_BBP_BASE0x78 + i, &val); | |||
1452 | sc->bbp[i].val = val & 0xff; | |||
1453 | sc->bbp[i].reg = val >> 8; | |||
1454 | DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, | |||
1455 | sc->bbp[i].val)); | |||
1456 | } | |||
1457 | if (sc->mac_ver >= 0x3071) { | |||
1458 | /* read vendor RF settings */ | |||
1459 | for (i = 0; i < 10; i++) { | |||
1460 | run_srom_read(sc, RT3071_EEPROM_RF_BASE0x82 + i, | |||
1461 | &val); | |||
1462 | sc->rf[i].val = val & 0xff; | |||
1463 | sc->rf[i].reg = val >> 8; | |||
1464 | DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, | |||
1465 | sc->rf[i].val)); | |||
1466 | } | |||
1467 | } | |||
1468 | } | |||
1469 | ||||
1470 | /* read RF frequency offset from EEPROM */ | |||
1471 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS0x1d : | |||
1472 | RT3593_EEPROM_FREQ0x22, &val); | |||
1473 | sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; | |||
1474 | DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); | |||
1475 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS0x1d : | |||
1476 | RT3593_EEPROM_FREQ_LEDS0x21, &val); | |||
1477 | if ((val >> 8) != 0xff) { | |||
1478 | /* read LEDs operating mode */ | |||
1479 | sc->leds = val >> 8; | |||
1480 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED10x1e : | |||
1481 | RT3593_EEPROM_LED10x22, &sc->led[0]); | |||
1482 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED20x1f : | |||
1483 | RT3593_EEPROM_LED20x23, &sc->led[1]); | |||
1484 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED30x20 : | |||
1485 | RT3593_EEPROM_LED30x24, &sc->led[2]); | |||
1486 | } else { | |||
1487 | /* broken EEPROM, use default settings */ | |||
1488 | sc->leds = 0x01; | |||
1489 | sc->led[0] = 0x5555; | |||
1490 | sc->led[1] = 0x2221; | |||
1491 | sc->led[2] = 0x5627; /* differs from RT2860 */ | |||
1492 | } | |||
1493 | DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", | |||
1494 | sc->leds, sc->led[0], sc->led[1], sc->led[2])); | |||
1495 | ||||
1496 | /* read RF information */ | |||
1497 | if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) | |||
1498 | run_srom_read(sc, 0x00, &val); | |||
1499 | else | |||
1500 | run_srom_read(sc, RT2860_EEPROM_ANTENNA0x1a, &val); | |||
1501 | if (val == 0xffff) { | |||
1502 | DPRINTF(("invalid EEPROM antenna info, using default\n")); | |||
1503 | if (sc->mac_ver == 0x3572) { | |||
1504 | /* default to RF3052 2T2R */ | |||
1505 | sc->rf_rev = RT3070_RF_30520x0009; | |||
1506 | sc->ntxchains = 2; | |||
1507 | sc->nrxchains = 2; | |||
1508 | } else if (sc->mac_ver >= 0x3070) { | |||
1509 | /* default to RF3020 1T1R */ | |||
1510 | sc->rf_rev = RT3070_RF_30200x0005; | |||
1511 | sc->ntxchains = 1; | |||
1512 | sc->nrxchains = 1; | |||
1513 | } else { | |||
1514 | /* default to RF2820 1T2R */ | |||
1515 | sc->rf_rev = RT2860_RF_28200x0001; | |||
1516 | sc->ntxchains = 1; | |||
1517 | sc->nrxchains = 2; | |||
1518 | } | |||
1519 | } else { | |||
1520 | if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { | |||
1521 | sc->rf_rev = val; | |||
1522 | run_srom_read(sc, RT2860_EEPROM_ANTENNA0x1a, &val); | |||
1523 | } else | |||
1524 | sc->rf_rev = (val >> 8) & 0xf; | |||
1525 | sc->ntxchains = (val >> 4) & 0xf; | |||
1526 | sc->nrxchains = val & 0xf; | |||
1527 | } | |||
1528 | DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", | |||
1529 | sc->rf_rev, sc->ntxchains, sc->nrxchains)); | |||
1530 | ||||
1531 | /* check if RF supports automatic Tx access gain control */ | |||
1532 | run_srom_read(sc, RT2860_EEPROM_CONFIG0x1b, &val); | |||
1533 | DPRINTF(("EEPROM CFG 0x%04x\n", val)); | |||
1534 | /* check if driver should patch the DAC issue */ | |||
1535 | if ((val >> 8) != 0xff) | |||
1536 | sc->patch_dac = (val >> 15) & 1; | |||
1537 | if ((val & 0xff) != 0xff) { | |||
1538 | sc->ext_5ghz_lna = (val >> 3) & 1; | |||
1539 | sc->ext_2ghz_lna = (val >> 2) & 1; | |||
1540 | /* check if RF supports automatic Tx access gain control */ | |||
1541 | sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; | |||
1542 | /* check if we have a hardware radio switch */ | |||
1543 | sc->rfswitch = val & 1; | |||
1544 | } | |||
1545 | ||||
1546 | /* Read Tx power settings. */ | |||
1547 | if (sc->mac_ver == 0x3593) | |||
1548 | run_rt3593_get_txpower(sc); | |||
1549 | else | |||
1550 | run_get_txpower(sc); | |||
1551 | ||||
1552 | /* read Tx power compensation for each Tx rate */ | |||
1553 | run_srom_read(sc, RT2860_EEPROM_DELTAPWR0x28, &val); | |||
1554 | delta_2ghz = delta_5ghz = 0; | |||
1555 | if ((val & 0xff) != 0xff && (val & 0x80)) { | |||
1556 | delta_2ghz = val & 0xf; | |||
1557 | if (!(val & 0x40)) /* negative number */ | |||
1558 | delta_2ghz = -delta_2ghz; | |||
1559 | } | |||
1560 | val >>= 8; | |||
1561 | if ((val & 0xff) != 0xff && (val & 0x80)) { | |||
1562 | delta_5ghz = val & 0xf; | |||
1563 | if (!(val & 0x40)) /* negative number */ | |||
1564 | delta_5ghz = -delta_5ghz; | |||
1565 | } | |||
1566 | DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", | |||
1567 | delta_2ghz, delta_5ghz)); | |||
1568 | ||||
1569 | for (ridx = 0; ridx < 5; ridx++) { | |||
1570 | uint32_t reg; | |||
1571 | ||||
1572 | run_srom_read(sc, RT2860_EEPROM_RPWR0x6f + ridx * 2, &val); | |||
1573 | reg = val; | |||
1574 | run_srom_read(sc, RT2860_EEPROM_RPWR0x6f + ridx * 2 + 1, &val); | |||
1575 | reg |= (uint32_t)val << 16; | |||
1576 | ||||
1577 | sc->txpow20mhz[ridx] = reg; | |||
1578 | sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); | |||
1579 | sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); | |||
1580 | ||||
1581 | DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " | |||
1582 | "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], | |||
1583 | sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); | |||
1584 | } | |||
1585 | ||||
1586 | /* read RSSI offsets and LNA gains from EEPROM */ | |||
1587 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ0x23 : | |||
1588 | RT3593_EEPROM_RSSI1_2GHZ0x28, &val); | |||
1589 | sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ | |||
1590 | sc->rssi_2ghz[1] = val >> 8; /* Ant B */ | |||
1591 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ0x24 : | |||
1592 | RT3593_EEPROM_RSSI2_2GHZ0x29, &val); | |||
1593 | if (sc->mac_ver >= 0x3070) { | |||
1594 | if (sc->mac_ver == 0x3593) { | |||
1595 | sc->txmixgain_2ghz = 0; | |||
1596 | sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ | |||
1597 | } else { | |||
1598 | /* | |||
1599 | * On RT3070 chips (limited to 2 Rx chains), this ROM | |||
1600 | * field contains the Tx mixer gain for the 2GHz band. | |||
1601 | */ | |||
1602 | if ((val & 0xff) != 0xff) | |||
1603 | sc->txmixgain_2ghz = val & 0x7; | |||
1604 | } | |||
1605 | DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); | |||
1606 | } else | |||
1607 | sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ | |||
1608 | if (sc->mac_ver == 0x3593) | |||
1609 | run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ0x27, &val); | |||
1610 | sc->lna[2] = val >> 8; /* channel group 2 */ | |||
1611 | ||||
1612 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ0x25 : | |||
1613 | RT3593_EEPROM_RSSI1_5GHZ0x2a, &val); | |||
1614 | sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ | |||
1615 | sc->rssi_5ghz[1] = val >> 8; /* Ant B */ | |||
1616 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ0x26 : | |||
1617 | RT3593_EEPROM_RSSI2_5GHZ0x2b, &val); | |||
1618 | if (sc->mac_ver == 0x3572) { | |||
1619 | /* | |||
1620 | * On RT3572 chips (limited to 2 Rx chains), this ROM | |||
1621 | * field contains the Tx mixer gain for the 5GHz band. | |||
1622 | */ | |||
1623 | if ((val & 0xff) != 0xff) | |||
1624 | sc->txmixgain_5ghz = val & 0x7; | |||
1625 | DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); | |||
1626 | } else | |||
1627 | sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ | |||
1628 | if (sc->mac_ver == 0x3593) { | |||
1629 | sc->txmixgain_5ghz = 0; | |||
1630 | run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ0x27, &val); | |||
1631 | } | |||
1632 | sc->lna[3] = val >> 8; /* channel group 3 */ | |||
1633 | ||||
1634 | run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA0x22 : | |||
1635 | RT3593_EEPROM_LNA0x26, &val); | |||
1636 | sc->lna[0] = val & 0xff; /* channel group 0 */ | |||
1637 | sc->lna[1] = val >> 8; /* channel group 1 */ | |||
1638 | ||||
1639 | /* fix broken 5GHz LNA entries */ | |||
1640 | if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { | |||
1641 | DPRINTF(("invalid LNA for channel group %d\n", 2)); | |||
1642 | sc->lna[2] = sc->lna[1]; | |||
1643 | } | |||
1644 | if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { | |||
1645 | DPRINTF(("invalid LNA for channel group %d\n", 3)); | |||
1646 | sc->lna[3] = sc->lna[1]; | |||
1647 | } | |||
1648 | ||||
1649 | /* fix broken RSSI offset entries */ | |||
1650 | for (ant = 0; ant < 3; ant++) { | |||
1651 | if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { | |||
1652 | DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", | |||
1653 | ant + 1, sc->rssi_2ghz[ant])); | |||
1654 | sc->rssi_2ghz[ant] = 0; | |||
1655 | } | |||
1656 | if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { | |||
1657 | DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", | |||
1658 | ant + 1, sc->rssi_5ghz[ant])); | |||
1659 | sc->rssi_5ghz[ant] = 0; | |||
1660 | } | |||
1661 | } | |||
1662 | return 0; | |||
1663 | } | |||
1664 | ||||
1665 | struct ieee80211_node * | |||
1666 | run_node_alloc(struct ieee80211com *ic) | |||
1667 | { | |||
1668 | return malloc(sizeof (struct run_node), M_USBDEV102, M_NOWAIT0x0002 | M_ZERO0x0008); | |||
1669 | } | |||
1670 | ||||
1671 | int | |||
1672 | run_media_change(struct ifnet *ifp) | |||
1673 | { | |||
1674 | struct run_softc *sc = ifp->if_softc; | |||
1675 | struct ieee80211com *ic = &sc->sc_ic; | |||
1676 | uint8_t rate, ridx; | |||
1677 | int error; | |||
1678 | ||||
1679 | error = ieee80211_media_change(ifp); | |||
1680 | if (error != ENETRESET52) | |||
1681 | return error; | |||
1682 | ||||
1683 | if (ic->ic_fixed_rate != -1) { | |||
1684 | rate = ic->ic_sup_rates[ic->ic_curmode]. | |||
1685 | rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL0x7f; | |||
1686 | for (ridx = 0; ridx <= RT2860_RIDX_MAX11; ridx++) | |||
1687 | if (rt2860_rates[ridx].rate == rate) | |||
1688 | break; | |||
1689 | sc->fixed_ridx = ridx; | |||
1690 | } | |||
1691 | ||||
1692 | if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) == | |||
1693 | (IFF_UP0x1 | IFF_RUNNING0x40)) { | |||
1694 | run_stop(ifp, 0); | |||
1695 | error = run_init(ifp); | |||
1696 | } | |||
1697 | ||||
1698 | return error; | |||
1699 | } | |||
1700 | ||||
1701 | void | |||
1702 | run_next_scan(void *arg) | |||
1703 | { | |||
1704 | struct run_softc *sc = arg; | |||
1705 | int s; | |||
1706 | ||||
1707 | if (usbd_is_dying(sc->sc_udev)) | |||
1708 | return; | |||
1709 | ||||
1710 | usbd_ref_incr(sc->sc_udev); | |||
1711 | ||||
1712 | s = splnet()splraise(0x4); | |||
1713 | if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) | |||
1714 | ieee80211_next_scan(&sc->sc_ic.ic_ific_ac.ac_if); | |||
1715 | splx(s)spllower(s); | |||
1716 | ||||
1717 | usbd_ref_decr(sc->sc_udev); | |||
1718 | } | |||
1719 | ||||
1720 | void | |||
1721 | run_task(void *arg) | |||
1722 | { | |||
1723 | struct run_softc *sc = arg; | |||
1724 | struct run_host_cmd_ring *ring = &sc->cmdq; | |||
1725 | struct run_host_cmd *cmd; | |||
1726 | int s; | |||
1727 | ||||
1728 | if (usbd_is_dying(sc->sc_udev)) | |||
1729 | return; | |||
1730 | ||||
1731 | /* process host commands */ | |||
1732 | s = splusb()splraise(0x2); | |||
1733 | while (ring->next != ring->cur) { | |||
1734 | cmd = &ring->cmd[ring->next]; | |||
1735 | splx(s)spllower(s); | |||
1736 | /* callback */ | |||
1737 | cmd->cb(sc, cmd->data); | |||
1738 | s = splusb()splraise(0x2); | |||
1739 | ring->queued--; | |||
1740 | ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT32; | |||
1741 | } | |||
1742 | splx(s)spllower(s); | |||
1743 | } | |||
1744 | ||||
1745 | void | |||
1746 | run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), | |||
1747 | void *arg, int len) | |||
1748 | { | |||
1749 | struct run_host_cmd_ring *ring = &sc->cmdq; | |||
1750 | struct run_host_cmd *cmd; | |||
1751 | int s; | |||
1752 | ||||
1753 | if (usbd_is_dying(sc->sc_udev)) | |||
1754 | return; | |||
1755 | ||||
1756 | s = splusb()splraise(0x2); | |||
1757 | cmd = &ring->cmd[ring->cur]; | |||
1758 | cmd->cb = cb; | |||
1759 | KASSERT(len <= sizeof (cmd->data))((len <= sizeof (cmd->data)) ? (void)0 : __assert("diagnostic " , "/usr/src/sys/dev/usb/if_run.c", 1759, "len <= sizeof (cmd->data)" )); | |||
1760 | memcpy(cmd->data, arg, len)__builtin_memcpy((cmd->data), (arg), (len)); | |||
1761 | ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT32; | |||
1762 | ||||
1763 | /* if there is no pending command already, schedule a task */ | |||
1764 | if (++ring->queued == 1) | |||
1765 | usb_add_task(sc->sc_udev, &sc->sc_task); | |||
1766 | splx(s)spllower(s); | |||
1767 | } | |||
1768 | ||||
1769 | int | |||
1770 | run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) | |||
1771 | { | |||
1772 | struct run_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; | |||
1773 | struct run_cmd_newstate cmd; | |||
1774 | ||||
1775 | /* do it in a process context */ | |||
1776 | cmd.state = nstate; | |||
1777 | cmd.arg = arg; | |||
1778 | run_do_async(sc, run_newstate_cb, &cmd, sizeof cmd); | |||
1779 | return 0; | |||
1780 | } | |||
1781 | ||||
1782 | void | |||
1783 | run_newstate_cb(struct run_softc *sc, void *arg) | |||
1784 | { | |||
1785 | struct run_cmd_newstate *cmd = arg; | |||
1786 | struct ieee80211com *ic = &sc->sc_ic; | |||
1787 | enum ieee80211_state ostate; | |||
1788 | struct ieee80211_node *ni; | |||
1789 | uint32_t tmp, sta[3]; | |||
1790 | uint8_t wcid; | |||
1791 | int s; | |||
1792 | ||||
1793 | s = splnet()splraise(0x4); | |||
1794 | ostate = ic->ic_state; | |||
1795 | ||||
1796 | if (ostate == IEEE80211_S_RUN) { | |||
1797 | /* turn link LED off */ | |||
1798 | run_set_leds(sc, RT2860_LED_RADIO(1 << 13)); | |||
1799 | } | |||
1800 | ||||
1801 | switch (cmd->state) { | |||
1802 | case IEEE80211_S_INIT: | |||
1803 | if (ostate == IEEE80211_S_RUN) { | |||
1804 | /* abort TSF synchronization */ | |||
1805 | run_read(sc, RT2860_BCN_TIME_CFG0x1114, &tmp); | |||
1806 | run_write(sc, RT2860_BCN_TIME_CFG0x1114, | |||
1807 | tmp & ~(RT2860_BCN_TX_EN(1 << 20) | RT2860_TSF_TIMER_EN(1 << 16) | | |||
1808 | RT2860_TBTT_TIMER_EN(1 << 19))); | |||
1809 | } | |||
1810 | break; | |||
1811 | ||||
1812 | case IEEE80211_S_SCAN: | |||
1813 | run_set_chan(sc, ic->ic_bss->ni_chan); | |||
1814 | if (!usbd_is_dying(sc->sc_udev)) | |||
1815 | timeout_add_msec(&sc->scan_to, 200); | |||
1816 | break; | |||
1817 | ||||
1818 | case IEEE80211_S_AUTH: | |||
1819 | case IEEE80211_S_ASSOC: | |||
1820 | run_set_chan(sc, ic->ic_bss->ni_chan); | |||
1821 | break; | |||
1822 | ||||
1823 | case IEEE80211_S_RUN: | |||
1824 | run_set_chan(sc, ic->ic_bss->ni_chan); | |||
1825 | ||||
1826 | ni = ic->ic_bss; | |||
1827 | ||||
1828 | if (ic->ic_opmode != IEEE80211_M_MONITOR) { | |||
1829 | run_updateslot(ic); | |||
1830 | run_enable_mrr(sc); | |||
1831 | run_set_txpreamble(sc); | |||
1832 | run_set_basicrates(sc); | |||
1833 | run_set_bssid(sc, ni->ni_bssid); | |||
1834 | } | |||
1835 | if (ic->ic_opmode == IEEE80211_M_STA) { | |||
1836 | /* add BSS entry to the WCID table */ | |||
1837 | wcid = RUN_AID2WCID(ni->ni_associd)((ni->ni_associd) & 0xff); | |||
1838 | run_write_region_1(sc, RT2860_WCID_ENTRY(wcid)(0x1800 + (wcid) * 8), | |||
1839 | ni->ni_macaddr, IEEE80211_ADDR_LEN6); | |||
1840 | ||||
1841 | /* fake a join to init the tx rate */ | |||
1842 | run_newassoc(ic, ni, 1); | |||
1843 | } | |||
1844 | if (ic->ic_opmode != IEEE80211_M_MONITOR) { | |||
1845 | run_enable_tsf_sync(sc); | |||
1846 | ||||
1847 | /* clear statistic registers used by AMRR */ | |||
1848 | run_read_region_1(sc, RT2860_TX_STA_CNT00x170c, | |||
1849 | (uint8_t *)sta, sizeof sta); | |||
1850 | /* start calibration timer */ | |||
1851 | if (!usbd_is_dying(sc->sc_udev)) | |||
1852 | timeout_add_sec(&sc->calib_to, 1); | |||
1853 | } | |||
1854 | ||||
1855 | /* turn link LED on */ | |||
1856 | run_set_leds(sc, RT2860_LED_RADIO(1 << 13) | | |||
1857 | (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)(((ic->ic_bss->ni_chan)->ic_flags & 0x0080) != 0 ) ? | |||
1858 | RT2860_LED_LINK_2GHZ(1 << 14) : RT2860_LED_LINK_5GHZ(1 << 15))); | |||
1859 | break; | |||
1860 | } | |||
1861 | (void)sc->sc_newstate(ic, cmd->state, cmd->arg); | |||
1862 | splx(s)spllower(s); | |||
1863 | } | |||
1864 | ||||
1865 | void | |||
1866 | run_updateedca(struct ieee80211com *ic) | |||
1867 | { | |||
1868 | /* do it in a process context */ | |||
1869 | run_do_async(ic->ic_softcic_ac.ac_if.if_softc, run_updateedca_cb, NULL((void *)0), 0); | |||
1870 | } | |||
1871 | ||||
1872 | void | |||
1873 | run_updateedca_cb(struct run_softc *sc, void *arg) | |||
1874 | { | |||
1875 | struct ieee80211com *ic = &sc->sc_ic; | |||
1876 | int s, aci; | |||
1877 | ||||
1878 | s = splnet()splraise(0x4); | |||
1879 | /* update MAC TX configuration registers */ | |||
1880 | for (aci = 0; aci < EDCA_NUM_AC4; aci++) { | |||
1881 | run_write(sc, RT2860_EDCA_AC_CFG(aci)(0x1300 + (aci) * 4), | |||
1882 | ic->ic_edca_ac[aci].ac_ecwmax << 16 | | |||
1883 | ic->ic_edca_ac[aci].ac_ecwmin << 12 | | |||
1884 | ic->ic_edca_ac[aci].ac_aifsn << 8 | | |||
1885 | ic->ic_edca_ac[aci].ac_txoplimit); | |||
1886 | } | |||
1887 | ||||
1888 | /* update SCH/DMA registers too */ | |||
1889 | run_write(sc, RT2860_WMM_AIFSN_CFG0x0214, | |||
1890 | ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | | |||
1891 | ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | | |||
1892 | ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | | |||
1893 | ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); | |||
1894 | run_write(sc, RT2860_WMM_CWMIN_CFG0x0218, | |||
1895 | ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | | |||
1896 | ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | | |||
1897 | ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | | |||
1898 | ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); | |||
1899 | run_write(sc, RT2860_WMM_CWMAX_CFG0x021c, | |||
1900 | ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | | |||
1901 | ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | | |||
1902 | ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | | |||
1903 | ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); | |||
1904 | run_write(sc, RT2860_WMM_TXOP0_CFG0x0220, | |||
1905 | ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | | |||
1906 | ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); | |||
1907 | run_write(sc, RT2860_WMM_TXOP1_CFG0x0224, | |||
1908 | ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | | |||
1909 | ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); | |||
1910 | splx(s)spllower(s); | |||
1911 | } | |||
1912 | ||||
1913 | int | |||
1914 | run_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, | |||
1915 | struct ieee80211_key *k) | |||
1916 | { | |||
1917 | struct run_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; | |||
1918 | struct run_cmd_key cmd; | |||
1919 | ||||
1920 | /* defer setting of WEP keys until interface is brought up */ | |||
1921 | if ((ic->ic_ific_ac.ac_if.if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) != | |||
1922 | (IFF_UP0x1 | IFF_RUNNING0x40)) | |||
1923 | return 0; | |||
1924 | ||||
1925 | /* do it in a process context */ | |||
1926 | cmd.key = *k; | |||
1927 | cmd.ni = ni; | |||
1928 | run_do_async(sc, run_set_key_cb, &cmd, sizeof cmd); | |||
1929 | sc->sc_key_tasks++; | |||
1930 | ||||
1931 | return EBUSY16; | |||
1932 | } | |||
1933 | ||||
1934 | void | |||
1935 | run_set_key_cb(struct run_softc *sc, void *arg) | |||
1936 | { | |||
1937 | struct ieee80211com *ic = &sc->sc_ic; | |||
1938 | struct run_cmd_key *cmd = arg; | |||
1939 | struct ieee80211_key *k = &cmd->key; | |||
1940 | uint32_t attr; | |||
1941 | uint16_t base; | |||
1942 | uint8_t mode, wcid, iv[8]; | |||
1943 | ||||
1944 | sc->sc_key_tasks--; | |||
1945 | ||||
1946 | /* map net80211 cipher to RT2860 security mode */ | |||
1947 | switch (k->k_cipher) { | |||
1948 | case IEEE80211_CIPHER_WEP40: | |||
1949 | mode = RT2860_MODE_WEP401; | |||
1950 | break; | |||
1951 | case IEEE80211_CIPHER_WEP104: | |||
1952 | mode = RT2860_MODE_WEP1042; | |||
1953 | break; | |||
1954 | case IEEE80211_CIPHER_TKIP: | |||
1955 | mode = RT2860_MODE_TKIP3; | |||
1956 | break; | |||
1957 | case IEEE80211_CIPHER_CCMP: | |||
1958 | mode = RT2860_MODE_AES_CCMP4; | |||
1959 | break; | |||
1960 | default: | |||
1961 | IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH,((*(ic)->ic_send_mgmt)(ic, cmd->ni, 0xc0, IEEE80211_REASON_AUTH_LEAVE , 0)) | |||
1962 | IEEE80211_REASON_AUTH_LEAVE)((*(ic)->ic_send_mgmt)(ic, cmd->ni, 0xc0, IEEE80211_REASON_AUTH_LEAVE , 0)); | |||
1963 | ieee80211_new_state(ic, IEEE80211_S_SCAN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_SCAN), (-1))); | |||
1964 | return; | |||
1965 | } | |||
1966 | ||||
1967 | if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) { | |||
1968 | wcid = 0; /* NB: update WCID0 for group keys */ | |||
1969 | base = RT2860_SKEY(0, k->k_id)(0x6c00 + (0) * 128 + (k->k_id) * 32); | |||
1970 | } else { | |||
1971 | wcid = (cmd->ni != NULL((void *)0)) ? RUN_AID2WCID(cmd->ni->ni_associd)((cmd->ni->ni_associd) & 0xff) : 0; | |||
1972 | base = RT2860_PKEY(wcid)(0x4000 + (wcid) * 32); | |||
1973 | } | |||
1974 | ||||
1975 | if (k->k_cipher == IEEE80211_CIPHER_TKIP) { | |||
1976 | run_write_region_1(sc, base, k->k_key, 16); | |||
1977 | run_write_region_1(sc, base + 16, &k->k_key[24], 8); | |||
1978 | run_write_region_1(sc, base + 24, &k->k_key[16], 8); | |||
1979 | } else { | |||
1980 | /* roundup len to 16-bit: XXX fix write_region_1() instead */ | |||
1981 | run_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1); | |||
1982 | } | |||
1983 | ||||
1984 | if (!(k->k_flags & IEEE80211_KEY_GROUP0x00000001) || | |||
1985 | (k->k_flags & IEEE80211_KEY_TX0x00000002)) { | |||
1986 | /* set initial packet number in IV+EIV */ | |||
1987 | if (k->k_cipher == IEEE80211_CIPHER_WEP40 || | |||
1988 | k->k_cipher == IEEE80211_CIPHER_WEP104) { | |||
1989 | memset(iv, 0, sizeof iv)__builtin_memset((iv), (0), (sizeof iv)); | |||
1990 | iv[3] = sc->sc_ic.ic_def_txkey << 6; | |||
1991 | } else { | |||
1992 | if (k->k_cipher == IEEE80211_CIPHER_TKIP) { | |||
1993 | iv[0] = k->k_tsc >> 8; | |||
1994 | iv[1] = (iv[0] | 0x20) & 0x7f; | |||
1995 | iv[2] = k->k_tsc; | |||
1996 | } else /* CCMP */ { | |||
1997 | iv[0] = k->k_tsc; | |||
1998 | iv[1] = k->k_tsc >> 8; | |||
1999 | iv[2] = 0; | |||
2000 | } | |||
2001 | iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV0x20; | |||
2002 | iv[4] = k->k_tsc >> 16; | |||
2003 | iv[5] = k->k_tsc >> 24; | |||
2004 | iv[6] = k->k_tsc >> 32; | |||
2005 | iv[7] = k->k_tsc >> 40; | |||
2006 | } | |||
2007 | run_write_region_1(sc, RT2860_IVEIV(wcid)(0x6000 + (wcid) * 8), iv, 8); | |||
2008 | } | |||
2009 | ||||
2010 | if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) { | |||
2011 | /* install group key */ | |||
2012 | run_read(sc, RT2860_SKEY_MODE_0_70x7000, &attr); | |||
2013 | attr &= ~(0xf << (k->k_id * 4)); | |||
2014 | attr |= mode << (k->k_id * 4); | |||
2015 | run_write(sc, RT2860_SKEY_MODE_0_70x7000, attr); | |||
2016 | } else { | |||
2017 | /* install pairwise key */ | |||
2018 | run_read(sc, RT2860_WCID_ATTR(wcid)(0x6800 + (wcid) * 4), &attr); | |||
2019 | attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN(1 << 0); | |||
2020 | run_write(sc, RT2860_WCID_ATTR(wcid)(0x6800 + (wcid) * 4), attr); | |||
2021 | } | |||
2022 | ||||
2023 | if (sc->sc_key_tasks == 0) { | |||
2024 | if (cmd->ni != NULL((void *)0)) | |||
2025 | cmd->ni->ni_port_valid = 1; | |||
2026 | ieee80211_set_link_state(ic, LINK_STATE_UP4); | |||
2027 | } | |||
2028 | } | |||
2029 | ||||
2030 | void | |||
2031 | run_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, | |||
2032 | struct ieee80211_key *k) | |||
2033 | { | |||
2034 | struct run_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; | |||
2035 | struct run_cmd_key cmd; | |||
2036 | ||||
2037 | if (!(ic->ic_ific_ac.ac_if.if_flags & IFF_RUNNING0x40) || | |||
2038 | ic->ic_state != IEEE80211_S_RUN) | |||
2039 | return; /* nothing to do */ | |||
2040 | ||||
2041 | /* do it in a process context */ | |||
2042 | cmd.key = *k; | |||
2043 | cmd.ni = ni; | |||
2044 | run_do_async(sc, run_delete_key_cb, &cmd, sizeof cmd); | |||
2045 | } | |||
2046 | ||||
2047 | void | |||
2048 | run_delete_key_cb(struct run_softc *sc, void *arg) | |||
2049 | { | |||
2050 | struct run_cmd_key *cmd = arg; | |||
2051 | struct ieee80211_key *k = &cmd->key; | |||
2052 | uint32_t attr; | |||
2053 | uint8_t wcid; | |||
2054 | ||||
2055 | if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) { | |||
2056 | /* remove group key */ | |||
2057 | run_read(sc, RT2860_SKEY_MODE_0_70x7000, &attr); | |||
2058 | attr &= ~(0xf << (k->k_id * 4)); | |||
2059 | run_write(sc, RT2860_SKEY_MODE_0_70x7000, attr); | |||
2060 | ||||
2061 | } else { | |||
2062 | /* remove pairwise key */ | |||
2063 | wcid = (cmd->ni != NULL((void *)0)) ? RUN_AID2WCID(cmd->ni->ni_associd)((cmd->ni->ni_associd) & 0xff) : 0; | |||
2064 | run_read(sc, RT2860_WCID_ATTR(wcid)(0x6800 + (wcid) * 4), &attr); | |||
2065 | attr &= ~0xf; | |||
2066 | run_write(sc, RT2860_WCID_ATTR(wcid)(0x6800 + (wcid) * 4), attr); | |||
2067 | } | |||
2068 | } | |||
2069 | ||||
2070 | void | |||
2071 | run_calibrate_to(void *arg) | |||
2072 | { | |||
2073 | /* do it in a process context */ | |||
2074 | run_do_async(arg, run_calibrate_cb, NULL((void *)0), 0); | |||
2075 | /* next timeout will be rescheduled in the calibration task */ | |||
2076 | } | |||
2077 | ||||
2078 | void | |||
2079 | run_calibrate_cb(struct run_softc *sc, void *arg) | |||
2080 | { | |||
2081 | struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if; | |||
2082 | uint32_t sta[3]; | |||
2083 | int s, error; | |||
2084 | ||||
2085 | /* read statistic counters (clear on read) and update AMRR state */ | |||
2086 | error = run_read_region_1(sc, RT2860_TX_STA_CNT00x170c, (uint8_t *)sta, | |||
2087 | sizeof sta); | |||
2088 | if (error != 0) | |||
2089 | goto skip; | |||
2090 | ||||
2091 | DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", | |||
2092 | letoh32(sta[1]) >> 16, letoh32(sta[1]) & 0xffff, | |||
2093 | letoh32(sta[0]) & 0xffff)); | |||
2094 | ||||
2095 | s = splnet()splraise(0x4); | |||
2096 | /* count failed TX as errors */ | |||
2097 | ifp->if_oerrorsif_data.ifi_oerrors += letoh32(sta[0])((__uint32_t)(sta[0])) & 0xffff; | |||
2098 | ||||
2099 | sc->amn.amn_retrycnt = | |||
2100 | (letoh32(sta[0])((__uint32_t)(sta[0])) & 0xffff) + /* failed TX count */ | |||
2101 | (letoh32(sta[1])((__uint32_t)(sta[1])) >> 16); /* TX retransmission count */ | |||
2102 | ||||
2103 | sc->amn.amn_txcnt = | |||
2104 | sc->amn.amn_retrycnt + | |||
2105 | (letoh32(sta[1])((__uint32_t)(sta[1])) & 0xffff); /* successful TX count */ | |||
2106 | ||||
2107 | ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); | |||
2108 | splx(s)spllower(s); | |||
2109 | ||||
2110 | skip: | |||
2111 | if (!usbd_is_dying(sc->sc_udev)) | |||
2112 | timeout_add_sec(&sc->calib_to, 1); | |||
2113 | } | |||
2114 | ||||
2115 | void | |||
2116 | run_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) | |||
2117 | { | |||
2118 | struct run_softc *sc = ic->ic_softcic_ac.ac_if.if_softc; | |||
2119 | struct run_node *rn = (void *)ni; | |||
2120 | struct ieee80211_rateset *rs = &ni->ni_rates; | |||
2121 | uint8_t rate; | |||
2122 | int ridx, i, j; | |||
2123 | ||||
2124 | DPRINTF(("new assoc isnew=%d addr=%s\n", | |||
2125 | isnew, ether_sprintf(ni->ni_macaddr))); | |||
2126 | ||||
2127 | ieee80211_amrr_node_init(&sc->amrr, &sc->amn); | |||
2128 | /* start at lowest available bit-rate, AMRR will raise */ | |||
2129 | ni->ni_txrate = 0; | |||
2130 | ||||
2131 | for (i = 0; i < rs->rs_nrates; i++) { | |||
2132 | rate = rs->rs_rates[i] & IEEE80211_RATE_VAL0x7f; | |||
2133 | /* convert 802.11 rate to hardware rate index */ | |||
2134 | for (ridx = 0; ridx < RT2860_RIDX_MAX11; ridx++) | |||
2135 | if (rt2860_rates[ridx].rate == rate) | |||
2136 | break; | |||
2137 | rn->ridx[i] = ridx; | |||
2138 | /* determine rate of control response frames */ | |||
2139 | for (j = i; j >= 0; j--) { | |||
2140 | if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC0x80) && | |||
2141 | rt2860_rates[rn->ridx[i]].phy == | |||
2142 | rt2860_rates[rn->ridx[j]].phy) | |||
2143 | break; | |||
2144 | } | |||
2145 | if (j >= 0) { | |||
2146 | rn->ctl_ridx[i] = rn->ridx[j]; | |||
2147 | } else { | |||
2148 | /* no basic rate found, use mandatory one */ | |||
2149 | rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; | |||
2150 | } | |||
2151 | DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", | |||
2152 | rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); | |||
2153 | } | |||
2154 | } | |||
2155 | ||||
2156 | /* | |||
2157 | * Return the Rx chain with the highest RSSI for a given frame. | |||
2158 | */ | |||
2159 | static __inline uint8_t | |||
2160 | run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) | |||
2161 | { | |||
2162 | uint8_t rxchain = 0; | |||
2163 | ||||
2164 | if (sc->nrxchains > 1) { | |||
2165 | if (rxwi->rssi[1] > rxwi->rssi[rxchain]) | |||
2166 | rxchain = 1; | |||
2167 | if (sc->nrxchains > 2) | |||
2168 | if (rxwi->rssi[2] > rxwi->rssi[rxchain]) | |||
2169 | rxchain = 2; | |||
2170 | } | |||
2171 | return rxchain; | |||
2172 | } | |||
2173 | ||||
2174 | void | |||
2175 | run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen, | |||
2176 | struct mbuf_list *ml) | |||
2177 | { | |||
2178 | struct ieee80211com *ic = &sc->sc_ic; | |||
2179 | struct ifnet *ifp = &ic->ic_ific_ac.ac_if; | |||
2180 | struct ieee80211_frame *wh; | |||
2181 | struct ieee80211_rxinfo rxi; | |||
2182 | struct ieee80211_node *ni; | |||
2183 | struct rt2870_rxd *rxd; | |||
2184 | struct rt2860_rxwi *rxwi; | |||
2185 | struct mbuf *m; | |||
2186 | uint32_t flags; | |||
2187 | uint16_t len; | |||
2188 | #if NBPFILTER1 > 0 | |||
2189 | uint16_t phy; | |||
2190 | #endif | |||
2191 | uint16_t rxwisize; | |||
2192 | uint8_t ant, rssi; | |||
2193 | int s; | |||
2194 | ||||
2195 | rxwi = (struct rt2860_rxwi *)buf; | |||
2196 | rxwisize = sizeof(struct rt2860_rxwi); | |||
2197 | if (sc->mac_ver == 0x5592) | |||
2198 | rxwisize += sizeof(uint64_t); | |||
2199 | else if (sc->mac_ver == 0x3593) | |||
2200 | rxwisize += sizeof(uint32_t); | |||
2201 | len = letoh16(rxwi->len)((__uint16_t)(rxwi->len)) & 0xfff; | |||
2202 | if (__predict_false(len > dmalen)__builtin_expect(((len > dmalen) != 0), 0)) { | |||
2203 | DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); | |||
2204 | return; | |||
2205 | } | |||
2206 | if (len > MCLBYTES(1 << 11)) { | |||
2207 | DPRINTF(("frame too large (length=%d)\n", len)); | |||
2208 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
2209 | return; | |||
2210 | } | |||
2211 | /* Rx descriptor is located at the end */ | |||
2212 | rxd = (struct rt2870_rxd *)(buf + dmalen); | |||
2213 | flags = letoh32(rxd->flags)((__uint32_t)(rxd->flags)); | |||
2214 | ||||
2215 | if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))__builtin_expect(((flags & ((1 << 8) | (1 << 9 ))) != 0), 0)) { | |||
2216 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
2217 | return; | |||
2218 | } | |||
2219 | ||||
2220 | if (__predict_false((flags & RT2860_RX_MICERR))__builtin_expect((((flags & (1 << 10))) != 0), 0)) { | |||
2221 | /* report MIC failures to net80211 for TKIP */ | |||
2222 | ic->ic_stats.is_rx_locmicfail++; | |||
2223 | ieee80211_michael_mic_failure(ic, 0/* XXX */); | |||
2224 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
2225 | return; | |||
2226 | } | |||
2227 | ||||
2228 | wh = (struct ieee80211_frame *)(buf + rxwisize); | |||
2229 | memset(&rxi, 0, sizeof(rxi))__builtin_memset((&rxi), (0), (sizeof(rxi))); | |||
2230 | if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED0x40) { | |||
2231 | wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED0x40; | |||
2232 | rxi.rxi_flags |= IEEE80211_RXI_HWDEC0x00000001; | |||
2233 | } | |||
2234 | ||||
2235 | if (flags & RT2860_RX_L2PAD(1 << 14)) { | |||
2236 | u_int hdrlen = ieee80211_get_hdrlen(wh); | |||
2237 | memmove((caddr_t)wh + 2, wh, hdrlen)__builtin_memmove(((caddr_t)wh + 2), (wh), (hdrlen)); | |||
2238 | wh = (struct ieee80211_frame *)((caddr_t)wh + 2); | |||
2239 | } | |||
2240 | ||||
2241 | /* could use m_devget but net80211 wants contig mgmt frames */ | |||
2242 | MGETHDR(m, M_DONTWAIT, MT_DATA)m = m_gethdr((0x0002), (1)); | |||
2243 | if (__predict_false(m == NULL)__builtin_expect(((m == ((void *)0)) != 0), 0)) { | |||
2244 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
2245 | return; | |||
2246 | } | |||
2247 | if (len > MHLEN((256 - sizeof(struct m_hdr)) - sizeof(struct pkthdr))) { | |||
2248 | MCLGET(m, M_DONTWAIT)(void) m_clget((m), (0x0002), (1 << 11)); | |||
2249 | if (__predict_false(!(m->m_flags & M_EXT))__builtin_expect(((!(m->m_hdr.mh_flags & 0x0001)) != 0 ), 0)) { | |||
2250 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
2251 | m_freem(m); | |||
2252 | return; | |||
2253 | } | |||
2254 | } | |||
2255 | /* finalize mbuf */ | |||
2256 | memcpy(mtod(m, caddr_t), wh, len)__builtin_memcpy((((caddr_t)((m)->m_hdr.mh_data))), (wh), ( len)); | |||
2257 | m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len = len; | |||
2258 | ||||
2259 | ant = run_maxrssi_chain(sc, rxwi); | |||
2260 | rssi = rxwi->rssi[ant]; | |||
2261 | ||||
2262 | #if NBPFILTER1 > 0 | |||
2263 | if (__predict_false(sc->sc_drvbpf != NULL)__builtin_expect(((sc->sc_drvbpf != ((void *)0)) != 0), 0)) { | |||
2264 | struct run_rx_radiotap_header *tap = &sc->sc_rxtapsc_rxtapu.th; | |||
2265 | struct mbuf mb; | |||
2266 | ||||
2267 | tap->wr_flags = 0; | |||
2268 | tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq)((__uint16_t)(ic->ic_ibss_chan->ic_freq)); | |||
2269 | tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags)((__uint16_t)(ic->ic_ibss_chan->ic_flags)); | |||
2270 | tap->wr_antsignal = rssi; | |||
2271 | tap->wr_antenna = ant; | |||
2272 | tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); | |||
2273 | tap->wr_rate = 2; /* in case it can't be found below */ | |||
2274 | phy = letoh16(rxwi->phy)((__uint16_t)(rxwi->phy)); | |||
2275 | switch (phy & RT2860_PHY_MODE0xc000) { | |||
2276 | case RT2860_PHY_CCK(0 << 14): | |||
2277 | switch ((phy & RT2860_PHY_MCS0x7f) & ~RT2860_PHY_SHPRE(1 << 3)) { | |||
2278 | case 0: tap->wr_rate = 2; break; | |||
2279 | case 1: tap->wr_rate = 4; break; | |||
2280 | case 2: tap->wr_rate = 11; break; | |||
2281 | case 3: tap->wr_rate = 22; break; | |||
2282 | } | |||
2283 | if (phy & RT2860_PHY_SHPRE(1 << 3)) | |||
2284 | tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE0x02; | |||
2285 | break; | |||
2286 | case RT2860_PHY_OFDM(1 << 14): | |||
2287 | switch (phy & RT2860_PHY_MCS0x7f) { | |||
2288 | case 0: tap->wr_rate = 12; break; | |||
2289 | case 1: tap->wr_rate = 18; break; | |||
2290 | case 2: tap->wr_rate = 24; break; | |||
2291 | case 3: tap->wr_rate = 36; break; | |||
2292 | case 4: tap->wr_rate = 48; break; | |||
2293 | case 5: tap->wr_rate = 72; break; | |||
2294 | case 6: tap->wr_rate = 96; break; | |||
2295 | case 7: tap->wr_rate = 108; break; | |||
2296 | } | |||
2297 | break; | |||
2298 | } | |||
2299 | mb.m_datam_hdr.mh_data = (caddr_t)tap; | |||
2300 | mb.m_lenm_hdr.mh_len = sc->sc_rxtap_len; | |||
2301 | mb.m_nextm_hdr.mh_next = m; | |||
2302 | mb.m_nextpktm_hdr.mh_nextpkt = NULL((void *)0); | |||
2303 | mb.m_typem_hdr.mh_type = 0; | |||
2304 | mb.m_flagsm_hdr.mh_flags = 0; | |||
2305 | bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN(1 << 0)); | |||
2306 | } | |||
2307 | #endif | |||
2308 | ||||
2309 | s = splnet()splraise(0x4); | |||
2310 | ni = ieee80211_find_rxnode(ic, wh); | |||
2311 | rxi.rxi_rssi = rssi; | |||
2312 | ieee80211_inputm(ifp, m, ni, &rxi, ml); | |||
2313 | ||||
2314 | /* node is no longer needed */ | |||
2315 | ieee80211_release_node(ic, ni); | |||
2316 | splx(s)spllower(s); | |||
2317 | } | |||
2318 | ||||
2319 | void | |||
2320 | run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) | |||
2321 | { | |||
2322 | struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 }; | |||
2323 | struct run_rx_data *data = priv; | |||
2324 | struct run_softc *sc = data->sc; | |||
2325 | uint8_t *buf; | |||
2326 | uint32_t dmalen; | |||
2327 | int xferlen; | |||
2328 | uint16_t rxwisize; | |||
2329 | ||||
2330 | rxwisize = sizeof(struct rt2860_rxwi); | |||
2331 | if (sc->mac_ver == 0x5592) | |||
2332 | rxwisize += sizeof(uint64_t); | |||
2333 | else if (sc->mac_ver == 0x3593) | |||
2334 | rxwisize += sizeof(uint32_t); | |||
2335 | ||||
2336 | if (__predict_false(status != USBD_NORMAL_COMPLETION)__builtin_expect(((status != USBD_NORMAL_COMPLETION) != 0), 0 )) { | |||
2337 | DPRINTF(("RX status=%d\n", status)); | |||
2338 | if (status == USBD_STALLED) | |||
2339 | usbd_clear_endpoint_stall_async(sc->rxq.pipeh); | |||
2340 | if (status != USBD_CANCELLED) | |||
2341 | goto skip; | |||
2342 | return; | |||
2343 | } | |||
2344 | usbd_get_xfer_status(xfer, NULL((void *)0), NULL((void *)0), &xferlen, NULL((void *)0)); | |||
2345 | ||||
2346 | if (__predict_false(xferlen < sizeof (uint32_t) + rxwisize +__builtin_expect(((xferlen < sizeof (uint32_t) + rxwisize + sizeof(struct rt2870_rxd)) != 0), 0) | |||
2347 | sizeof(struct rt2870_rxd))__builtin_expect(((xferlen < sizeof (uint32_t) + rxwisize + sizeof(struct rt2870_rxd)) != 0), 0)) { | |||
2348 | DPRINTF(("xfer too short %d\n", xferlen)); | |||
2349 | goto skip; | |||
2350 | } | |||
2351 | ||||
2352 | /* HW can aggregate multiple 802.11 frames in a single USB xfer */ | |||
2353 | buf = data->buf; | |||
2354 | while (xferlen > 8) { | |||
2355 | dmalen = letoh32(*(uint32_t *)buf)((__uint32_t)(*(uint32_t *)buf)) & 0xffff; | |||
2356 | ||||
2357 | if (__predict_false(dmalen == 0 || (dmalen & 3) != 0)__builtin_expect(((dmalen == 0 || (dmalen & 3) != 0) != 0 ), 0)) { | |||
2358 | DPRINTF(("bad DMA length %u\n", dmalen)); | |||
2359 | break; | |||
2360 | } | |||
2361 | if (__predict_false(dmalen + 8 > xferlen)__builtin_expect(((dmalen + 8 > xferlen) != 0), 0)) { | |||
2362 | DPRINTF(("bad DMA length %u > %d\n", | |||
2363 | dmalen + 8, xferlen)); | |||
2364 | break; | |||
2365 | } | |||
2366 | run_rx_frame(sc, buf + sizeof (uint32_t), dmalen, &ml); | |||
2367 | buf += dmalen + 8; | |||
2368 | xferlen -= dmalen + 8; | |||
2369 | } | |||
2370 | if_input(&sc->sc_ic.ic_ific_ac.ac_if, &ml); | |||
2371 | ||||
2372 | skip: /* setup a new transfer */ | |||
2373 | usbd_setup_xfer(xfer, sc->rxq.pipeh, data, data->buf, RUN_MAX_RXSZ4096, | |||
2374 | USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01, USBD_NO_TIMEOUT0, run_rxeof); | |||
2375 | (void)usbd_transfer(data->xfer); | |||
2376 | } | |||
2377 | ||||
2378 | void | |||
2379 | run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) | |||
2380 | { | |||
2381 | struct run_tx_data *data = priv; | |||
2382 | struct run_softc *sc = data->sc; | |||
2383 | struct run_tx_ring *txq = &sc->txq[data->qid]; | |||
2384 | struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if; | |||
2385 | int s; | |||
2386 | ||||
2387 | s = splnet()splraise(0x4); | |||
2388 | txq->queued--; | |||
2389 | sc->qfullmsk &= ~(1 << data->qid); | |||
2390 | ||||
2391 | if (__predict_false(status != USBD_NORMAL_COMPLETION)__builtin_expect(((status != USBD_NORMAL_COMPLETION) != 0), 0 )) { | |||
2392 | DPRINTF(("TX status=%d\n", status)); | |||
2393 | if (status == USBD_STALLED) | |||
2394 | usbd_clear_endpoint_stall_async(txq->pipeh); | |||
2395 | ifp->if_oerrorsif_data.ifi_oerrors++; | |||
2396 | splx(s)spllower(s); | |||
2397 | return; | |||
2398 | } | |||
2399 | ||||
2400 | sc->sc_tx_timer = 0; | |||
2401 | ifq_clr_oactive(&ifp->if_snd); | |||
2402 | run_start(ifp); | |||
2403 | splx(s)spllower(s); | |||
2404 | } | |||
2405 | ||||
2406 | int | |||
2407 | run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) | |||
2408 | { | |||
2409 | struct ieee80211com *ic = &sc->sc_ic; | |||
2410 | struct run_node *rn = (void *)ni; | |||
2411 | struct ieee80211_frame *wh; | |||
2412 | struct run_tx_ring *ring; | |||
2413 | struct run_tx_data *data; | |||
2414 | struct rt2870_txd *txd; | |||
2415 | struct rt2860_txwi *txwi; | |||
2416 | uint16_t qos, dur; | |||
2417 | uint16_t txwisize; | |||
2418 | uint8_t type, mcs, tid, qid; | |||
2419 | int error, hasqos, ridx, ctl_ridx, xferlen; | |||
2420 | ||||
2421 | wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data)); | |||
2422 | type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c; | |||
2423 | ||||
2424 | if ((hasqos = ieee80211_has_qos(wh))) { | |||
2425 | qos = ieee80211_get_qos(wh); | |||
2426 | tid = qos & IEEE80211_QOS_TID0x000f; | |||
2427 | qid = ieee80211_up_to_ac(ic, tid); | |||
2428 | } else { | |||
2429 | qos = 0; | |||
2430 | tid = 0; | |||
2431 | qid = EDCA_AC_BE; | |||
2432 | } | |||
2433 | ring = &sc->txq[qid]; | |||
2434 | data = &ring->data[ring->cur]; | |||
2435 | ||||
2436 | /* pickup a rate index */ | |||
2437 | if (IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) || | |||
2438 | type != IEEE80211_FC0_TYPE_DATA0x08) { | |||
2439 | ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? | |||
2440 | RT2860_RIDX_OFDM64 : RT2860_RIDX_CCK10; | |||
2441 | ctl_ridx = rt2860_rates[ridx].ctl_ridx; | |||
2442 | } else if (ic->ic_fixed_rate != -1) { | |||
2443 | ridx = sc->fixed_ridx; | |||
2444 | ctl_ridx = rt2860_rates[ridx].ctl_ridx; | |||
2445 | } else { | |||
2446 | ridx = rn->ridx[ni->ni_txrate]; | |||
2447 | ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; | |||
2448 | } | |||
2449 | ||||
2450 | /* get MCS code from rate index */ | |||
2451 | mcs = rt2860_rates[ridx].mcs; | |||
2452 | ||||
2453 | txwisize = sizeof(struct rt2860_txwi); | |||
2454 | if (sc->mac_ver == 0x5592) | |||
2455 | txwisize += sizeof(uint32_t); | |||
2456 | xferlen = txwisize + m->m_pkthdrM_dat.MH.MH_pkthdr.len; | |||
2457 | ||||
2458 | /* roundup to 32-bit alignment */ | |||
2459 | xferlen = (xferlen + 3) & ~3; | |||
2460 | ||||
2461 | txd = (struct rt2870_txd *)data->buf; | |||
2462 | txd->flags = RT2860_TX_QSEL_EDCA(2 << 1); | |||
2463 | txd->len = htole16(xferlen)((__uint16_t)(xferlen)); | |||
2464 | ||||
2465 | /* setup TX Wireless Information */ | |||
2466 | txwi = (struct rt2860_txwi *)(txd + 1); | |||
2467 | txwi->flags = 0; | |||
2468 | txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ(1 << 1); | |||
2469 | txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA0x08) ? | |||
2470 | RUN_AID2WCID(ni->ni_associd)((ni->ni_associd) & 0xff) : 0xff; | |||
2471 | txwi->len = htole16(m->m_pkthdr.len)((__uint16_t)(m->M_dat.MH.MH_pkthdr.len)); | |||
2472 | if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { | |||
2473 | txwi->phy = htole16(RT2860_PHY_CCK)((__uint16_t)((0 << 14))); | |||
2474 | if (ridx != RT2860_RIDX_CCK10 && | |||
2475 | (ic->ic_flags & IEEE80211_F_SHPREAMBLE0x00040000)) | |||
2476 | mcs |= RT2860_PHY_SHPRE(1 << 3); | |||
2477 | } else | |||
2478 | txwi->phy = htole16(RT2860_PHY_OFDM)((__uint16_t)((1 << 14))); | |||
2479 | txwi->phy |= htole16(mcs)((__uint16_t)(mcs)); | |||
2480 | ||||
2481 | txwi->txop = RT2860_TX_TXOP_BACKOFF3; | |||
2482 | ||||
2483 | if (!IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) && | |||
2484 | (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK0x0060) != | |||
2485 | IEEE80211_QOS_ACK_POLICY_NOACK0x0020)) { | |||
2486 | txwi->xflags |= RT2860_TX_ACK(1 << 0); | |||
2487 | if (ic->ic_flags & IEEE80211_F_SHPREAMBLE0x00040000) | |||
2488 | dur = rt2860_rates[ctl_ridx].sp_ack_dur; | |||
2489 | else | |||
2490 | dur = rt2860_rates[ctl_ridx].lp_ack_dur; | |||
2491 | *(uint16_t *)wh->i_dur = htole16(dur)((__uint16_t)(dur)); | |||
2492 | } | |||
2493 | ||||
2494 | #if NBPFILTER1 > 0 | |||
2495 | if (__predict_false(sc->sc_drvbpf != NULL)__builtin_expect(((sc->sc_drvbpf != ((void *)0)) != 0), 0)) { | |||
2496 | struct run_tx_radiotap_header *tap = &sc->sc_txtapsc_txtapu.th; | |||
2497 | struct mbuf mb; | |||
2498 | ||||
2499 | tap->wt_flags = 0; | |||
2500 | tap->wt_rate = rt2860_rates[ridx].rate; | |||
2501 | tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq)((__uint16_t)(ic->ic_bss->ni_chan->ic_freq)); | |||
2502 | tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags)((__uint16_t)(ic->ic_bss->ni_chan->ic_flags)); | |||
2503 | if (mcs & RT2860_PHY_SHPRE(1 << 3)) | |||
2504 | tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE0x02; | |||
2505 | ||||
2506 | mb.m_datam_hdr.mh_data = (caddr_t)tap; | |||
2507 | mb.m_lenm_hdr.mh_len = sc->sc_txtap_len; | |||
2508 | mb.m_nextm_hdr.mh_next = m; | |||
2509 | mb.m_nextpktm_hdr.mh_nextpkt = NULL((void *)0); | |||
2510 | mb.m_typem_hdr.mh_type = 0; | |||
2511 | mb.m_flagsm_hdr.mh_flags = 0; | |||
2512 | bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT(1 << 1)); | |||
2513 | } | |||
2514 | #endif | |||
2515 | ||||
2516 | m_copydata(m, 0, m->m_pkthdrM_dat.MH.MH_pkthdr.len, (caddr_t)txwi + txwisize); | |||
2517 | m_freem(m); | |||
2518 | ||||
2519 | xferlen += sizeof (*txd) + 4; | |||
2520 | ||||
2521 | usbd_setup_xfer(data->xfer, ring->pipeh, data, data->buf, xferlen, | |||
2522 | USBD_FORCE_SHORT_XFER0x08 | USBD_NO_COPY0x01, RUN_TX_TIMEOUT5000, run_txeof); | |||
2523 | error = usbd_transfer(data->xfer); | |||
2524 | if (__predict_false(error != USBD_IN_PROGRESS && error != 0)__builtin_expect(((error != USBD_IN_PROGRESS && error != 0) != 0), 0)) | |||
2525 | return error; | |||
2526 | ||||
2527 | ieee80211_release_node(ic, ni); | |||
2528 | ||||
2529 | ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT8; | |||
2530 | if (++ring->queued >= RUN_TX_RING_COUNT8) | |||
2531 | sc->qfullmsk |= 1 << qid; | |||
2532 | ||||
2533 | return 0; | |||
2534 | } | |||
2535 | ||||
2536 | void | |||
2537 | run_start(struct ifnet *ifp) | |||
2538 | { | |||
2539 | struct run_softc *sc = ifp->if_softc; | |||
2540 | struct ieee80211com *ic = &sc->sc_ic; | |||
2541 | struct ieee80211_node *ni; | |||
2542 | struct mbuf *m; | |||
2543 | ||||
2544 | if (!(ifp->if_flags & IFF_RUNNING0x40) || ifq_is_oactive(&ifp->if_snd)) | |||
2545 | return; | |||
2546 | ||||
2547 | for (;;) { | |||
2548 | if (sc->qfullmsk != 0) { | |||
2549 | ifq_set_oactive(&ifp->if_snd); | |||
2550 | break; | |||
2551 | } | |||
2552 | /* send pending management frames first */ | |||
2553 | m = mq_dequeue(&ic->ic_mgtq); | |||
2554 | if (m != NULL((void *)0)) { | |||
2555 | ni = m->m_pkthdrM_dat.MH.MH_pkthdr.ph_cookie; | |||
2556 | goto sendit; | |||
2557 | } | |||
2558 | if (ic->ic_state != IEEE80211_S_RUN) | |||
2559 | break; | |||
2560 | ||||
2561 | /* encapsulate and send data frames */ | |||
2562 | m = ifq_dequeue(&ifp->if_snd); | |||
2563 | if (m == NULL((void *)0)) | |||
2564 | break; | |||
2565 | #if NBPFILTER1 > 0 | |||
2566 | if (ifp->if_bpf != NULL((void *)0)) | |||
2567 | bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1)); | |||
2568 | #endif | |||
2569 | if ((m = ieee80211_encap(ifp, m, &ni)) == NULL((void *)0)) | |||
2570 | continue; | |||
2571 | sendit: | |||
2572 | #if NBPFILTER1 > 0 | |||
2573 | if (ic->ic_rawbpf != NULL((void *)0)) | |||
2574 | bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT(1 << 1)); | |||
2575 | #endif | |||
2576 | if (run_tx(sc, m, ni) != 0) { | |||
2577 | ieee80211_release_node(ic, ni); | |||
2578 | ifp->if_oerrorsif_data.ifi_oerrors++; | |||
2579 | continue; | |||
2580 | } | |||
2581 | ||||
2582 | sc->sc_tx_timer = 5; | |||
2583 | ifp->if_timer = 1; | |||
2584 | } | |||
2585 | } | |||
2586 | ||||
2587 | void | |||
2588 | run_watchdog(struct ifnet *ifp) | |||
2589 | { | |||
2590 | struct run_softc *sc = ifp->if_softc; | |||
2591 | ||||
2592 | ifp->if_timer = 0; | |||
2593 | ||||
2594 | if (sc->sc_tx_timer > 0) { | |||
2595 | if (--sc->sc_tx_timer == 0) { | |||
2596 | printf("%s: device timeout\n", sc->sc_dev.dv_xname); | |||
2597 | /* run_init(ifp); XXX needs a process context! */ | |||
2598 | ifp->if_oerrorsif_data.ifi_oerrors++; | |||
2599 | return; | |||
2600 | } | |||
2601 | ifp->if_timer = 1; | |||
2602 | } | |||
2603 | ||||
2604 | ieee80211_watchdog(ifp); | |||
2605 | } | |||
2606 | ||||
2607 | int | |||
2608 | run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) | |||
2609 | { | |||
2610 | struct run_softc *sc = ifp->if_softc; | |||
2611 | struct ieee80211com *ic = &sc->sc_ic; | |||
2612 | int s, error = 0; | |||
2613 | ||||
2614 | if (usbd_is_dying(sc->sc_udev)) | |||
| ||||
2615 | return ENXIO6; | |||
2616 | ||||
2617 | usbd_ref_incr(sc->sc_udev); | |||
2618 | ||||
2619 | s = splnet()splraise(0x4); | |||
2620 | ||||
2621 | switch (cmd) { | |||
2622 | case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((12))): | |||
2623 | ifp->if_flags |= IFF_UP0x1; | |||
2624 | /* FALLTHROUGH */ | |||
2625 | case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((16))): | |||
2626 | if (ifp->if_flags & IFF_UP0x1) { | |||
2627 | if (!(ifp->if_flags & IFF_RUNNING0x40)) | |||
2628 | run_init(ifp); | |||
2629 | } else { | |||
2630 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
2631 | run_stop(ifp, 1); | |||
2632 | } | |||
2633 | break; | |||
2634 | ||||
2635 | case SIOCS80211CHANNEL((unsigned long)0x80000000 | ((sizeof(struct ieee80211chanreq ) & 0x1fff) << 16) | ((('i')) << 8) | ((238)) ): | |||
2636 | /* | |||
2637 | * This allows for fast channel switching in monitor mode | |||
2638 | * (used by kismet). | |||
2639 | */ | |||
2640 | error = ieee80211_ioctl(ifp, cmd, data); | |||
2641 | if (error == ENETRESET52 && | |||
2642 | ic->ic_opmode == IEEE80211_M_MONITOR) { | |||
2643 | if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) == | |||
2644 | (IFF_UP0x1 | IFF_RUNNING0x40)) | |||
2645 | run_set_chan(sc, ic->ic_ibss_chan); | |||
2646 | error = 0; | |||
2647 | } | |||
2648 | break; | |||
2649 | ||||
2650 | default: | |||
2651 | error = ieee80211_ioctl(ifp, cmd, data); | |||
2652 | } | |||
2653 | ||||
2654 | if (error == ENETRESET52) { | |||
2655 | if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) == | |||
2656 | (IFF_UP0x1 | IFF_RUNNING0x40)) { | |||
2657 | run_stop(ifp, 0); | |||
2658 | run_init(ifp); | |||
2659 | } | |||
2660 | error = 0; | |||
2661 | } | |||
2662 | ||||
2663 | splx(s)spllower(s); | |||
2664 | ||||
2665 | usbd_ref_decr(sc->sc_udev); | |||
2666 | ||||
2667 | return error; | |||
2668 | } | |||
2669 | ||||
2670 | void | |||
2671 | run_iq_calib(struct run_softc *sc, u_int chan) | |||
2672 | { | |||
2673 | uint16_t val; | |||
2674 | ||||
2675 | /* Tx0 IQ gain. */ | |||
2676 | run_bbp_write(sc, 158, 0x2c); | |||
2677 | if (chan <= 14) | |||
2678 | run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ0x130, &val); | |||
2679 | else if (chan <= 64) { | |||
2680 | run_efuse_read(sc, | |||
2681 | RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ0x144, &val); | |||
2682 | } else if (chan <= 138) { | |||
2683 | run_efuse_read(sc, | |||
2684 | RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ0x146, &val); | |||
2685 | } else if (chan <= 165) { | |||
2686 | run_efuse_read(sc, | |||
2687 | RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ0x148, | |||
2688 | &val); | |||
2689 | } else | |||
2690 | val = 0; | |||
2691 | run_bbp_write(sc, 159, val); | |||
2692 | ||||
2693 | /* Tx0 IQ phase. */ | |||
2694 | run_bbp_write(sc, 158, 0x2d); | |||
2695 | if (chan <= 14) { | |||
2696 | run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ0x131, &val); | |||
2697 | } else if (chan <= 64) { | |||
2698 | run_efuse_read(sc, | |||
2699 | RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ0x145, &val); | |||
2700 | } else if (chan <= 138) { | |||
2701 | run_efuse_read(sc, | |||
2702 | RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ0x147, &val); | |||
2703 | } else if (chan <= 165) { | |||
2704 | run_efuse_read(sc, | |||
2705 | RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ0x149, &val); | |||
2706 | } else | |||
2707 | val = 0; | |||
2708 | run_bbp_write(sc, 159, val); | |||
2709 | ||||
2710 | /* Tx1 IQ gain. */ | |||
2711 | run_bbp_write(sc, 158, 0x4a); | |||
2712 | if (chan <= 14) { | |||
2713 | run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ0x133, &val); | |||
2714 | } else if (chan <= 64) { | |||
2715 | run_efuse_read(sc, | |||
2716 | RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ0x14a, &val); | |||
2717 | } else if (chan <= 138) { | |||
2718 | run_efuse_read(sc, | |||
2719 | RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ0x14c, &val); | |||
2720 | } else if (chan <= 165) { | |||
2721 | run_efuse_read(sc, | |||
2722 | RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ0x14e, &val); | |||
2723 | } else | |||
2724 | val = 0; | |||
2725 | run_bbp_write(sc, 159, val); | |||
2726 | ||||
2727 | /* Tx1 IQ phase. */ | |||
2728 | run_bbp_write(sc, 158, 0x4b); | |||
2729 | if (chan <= 14) { | |||
2730 | run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ0x134, &val); | |||
2731 | } else if (chan <= 64) { | |||
2732 | run_efuse_read(sc, | |||
2733 | RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ0x14b, &val); | |||
2734 | } else if (chan <= 138) { | |||
2735 | run_efuse_read(sc, | |||
2736 | RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ0x14d, &val); | |||
2737 | } else if (chan <= 165) { | |||
2738 | run_efuse_read(sc, | |||
2739 | RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ0x14f, &val); | |||
2740 | } else | |||
2741 | val = 0; | |||
2742 | run_bbp_write(sc, 159, val); | |||
2743 | ||||
2744 | /* RF IQ compensation control. */ | |||
2745 | run_bbp_write(sc, 158, 0x04); | |||
2746 | run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL0x13c, &val); | |||
2747 | run_bbp_write(sc, 159, val); | |||
2748 | ||||
2749 | /* RF IQ imbalance compensation control. */ | |||
2750 | run_bbp_write(sc, 158, 0x03); | |||
2751 | run_efuse_read(sc, | |||
2752 | RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL0x13d, &val); | |||
2753 | run_bbp_write(sc, 159, val); | |||
2754 | } | |||
2755 | ||||
2756 | void | |||
2757 | run_select_chan_group(struct run_softc *sc, int group) | |||
2758 | { | |||
2759 | uint32_t tmp; | |||
2760 | uint8_t agc; | |||
2761 | ||||
2762 | run_bbp_write(sc, 62, 0x37 - sc->lna[group]); | |||
2763 | run_bbp_write(sc, 63, 0x37 - sc->lna[group]); | |||
2764 | run_bbp_write(sc, 64, 0x37 - sc->lna[group]); | |||
2765 | if (sc->mac_ver < 0x3572) | |||
2766 | run_bbp_write(sc, 86, 0x00); | |||
2767 | ||||
2768 | if (sc->mac_ver == 0x3593) { | |||
2769 | run_bbp_write(sc, 77, 0x98); | |||
2770 | run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); | |||
2771 | } | |||
2772 | ||||
2773 | if (group == 0) { | |||
2774 | if (sc->ext_2ghz_lna) { | |||
2775 | if (sc->mac_ver >= 0x5390) | |||
2776 | run_bbp_write(sc, 75, 0x52); | |||
2777 | else { | |||
2778 | run_bbp_write(sc, 82, 0x62); | |||
2779 | run_bbp_write(sc, 75, 0x46); | |||
2780 | } | |||
2781 | } else { | |||
2782 | if (sc->mac_ver == 0x5592) { | |||
2783 | run_bbp_write(sc, 79, 0x1c); | |||
2784 | run_bbp_write(sc, 80, 0x0e); | |||
2785 | run_bbp_write(sc, 81, 0x3a); | |||
2786 | run_bbp_write(sc, 82, 0x62); | |||
2787 | ||||
2788 | run_bbp_write(sc, 195, 0x80); | |||
2789 | run_bbp_write(sc, 196, 0xe0); | |||
2790 | run_bbp_write(sc, 195, 0x81); | |||
2791 | run_bbp_write(sc, 196, 0x1f); | |||
2792 | run_bbp_write(sc, 195, 0x82); | |||
2793 | run_bbp_write(sc, 196, 0x38); | |||
2794 | run_bbp_write(sc, 195, 0x83); | |||
2795 | run_bbp_write(sc, 196, 0x32); | |||
2796 | run_bbp_write(sc, 195, 0x85); | |||
2797 | run_bbp_write(sc, 196, 0x28); | |||
2798 | run_bbp_write(sc, 195, 0x86); | |||
2799 | run_bbp_write(sc, 196, 0x19); | |||
2800 | } else if (sc->mac_ver >= 0x5390) | |||
2801 | run_bbp_write(sc, 75, 0x50); | |||
2802 | else { | |||
2803 | run_bbp_write(sc, 82, | |||
2804 | (sc->mac_ver == 0x3593) ? 0x62 : 0x84); | |||
2805 | run_bbp_write(sc, 75, 0x50); | |||
2806 | } | |||
2807 | } | |||
2808 | } else { | |||
2809 | if (sc->mac_ver == 0x5592) { | |||
2810 | run_bbp_write(sc, 79, 0x18); | |||
2811 | run_bbp_write(sc, 80, 0x08); | |||
2812 | run_bbp_write(sc, 81, 0x38); | |||
2813 | run_bbp_write(sc, 82, 0x92); | |||
2814 | ||||
2815 | run_bbp_write(sc, 195, 0x80); | |||
2816 | run_bbp_write(sc, 196, 0xf0); | |||
2817 | run_bbp_write(sc, 195, 0x81); | |||
2818 | run_bbp_write(sc, 196, 0x1e); | |||
2819 | run_bbp_write(sc, 195, 0x82); | |||
2820 | run_bbp_write(sc, 196, 0x28); | |||
2821 | run_bbp_write(sc, 195, 0x83); | |||
2822 | run_bbp_write(sc, 196, 0x20); | |||
2823 | run_bbp_write(sc, 195, 0x85); | |||
2824 | run_bbp_write(sc, 196, 0x7f); | |||
2825 | run_bbp_write(sc, 195, 0x86); | |||
2826 | run_bbp_write(sc, 196, 0x7f); | |||
2827 | } else if (sc->mac_ver == 0x3572) | |||
2828 | run_bbp_write(sc, 82, 0x94); | |||
2829 | else | |||
2830 | run_bbp_write(sc, 82, | |||
2831 | (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); | |||
2832 | if (sc->ext_5ghz_lna) | |||
2833 | run_bbp_write(sc, 75, 0x46); | |||
2834 | else | |||
2835 | run_bbp_write(sc, 75, 0x50); | |||
2836 | } | |||
2837 | ||||
2838 | run_read(sc, RT2860_TX_BAND_CFG0x132c, &tmp); | |||
2839 | tmp &= ~(RT2860_5G_BAND_SEL_N(1 << 2) | RT2860_5G_BAND_SEL_P(1 << 1)); | |||
2840 | tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N(1 << 2) : RT2860_5G_BAND_SEL_P(1 << 1); | |||
2841 | run_write(sc, RT2860_TX_BAND_CFG0x132c, tmp); | |||
2842 | ||||
2843 | /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ | |||
2844 | tmp = RT2860_RFTR_EN(1U << 16) | RT2860_TRSW_EN(1U << 18) | RT2860_LNA_PE0_EN((1U << 8) | (1U << 9)); | |||
2845 | if (sc->mac_ver == 0x3593) | |||
2846 | tmp |= 1 << 29 | 1 << 28; | |||
2847 | if (sc->nrxchains > 1) | |||
2848 | tmp |= RT2860_LNA_PE1_EN((1U << 10) | (1U << 11)); | |||
2849 | if (group == 0) { /* 2GHz */ | |||
2850 | tmp |= RT2860_PA_PE_G0_EN(1U << 1); | |||
2851 | if (sc->ntxchains > 1) | |||
2852 | tmp |= RT2860_PA_PE_G1_EN(1U << 3); | |||
2853 | if (sc->mac_ver == 0x3593) { | |||
2854 | if (sc->ntxchains > 2) | |||
2855 | tmp |= 1 << 25; | |||
2856 | } | |||
2857 | } else { /* 5GHz */ | |||
2858 | tmp |= RT2860_PA_PE_A0_EN(1U << 0); | |||
2859 | if (sc->ntxchains > 1) | |||
2860 | tmp |= RT2860_PA_PE_A1_EN(1U << 2); | |||
2861 | } | |||
2862 | if (sc->mac_ver == 0x3572) { | |||
2863 | run_rt3070_rf_write(sc, 8, 0x00); | |||
2864 | run_write(sc, RT2860_TX_PIN_CFG0x1328, tmp); | |||
2865 | run_rt3070_rf_write(sc, 8, 0x80); | |||
2866 | } else | |||
2867 | run_write(sc, RT2860_TX_PIN_CFG0x1328, tmp); | |||
2868 | ||||
2869 | if (sc->mac_ver == 0x5592) { | |||
2870 | run_bbp_write(sc, 195, 0x8d); | |||
2871 | run_bbp_write(sc, 196, 0x1a); | |||
2872 | } | |||
2873 | ||||
2874 | if (sc->mac_ver == 0x3593) { | |||
2875 | run_read(sc, RT2860_GPIO_CTRL0x0228, &tmp); | |||
2876 | tmp &= ~0x01010000; | |||
2877 | if (group == 0) | |||
2878 | tmp |= 0x00010000; | |||
2879 | tmp = (tmp & ~0x00009090) | 0x00000090; | |||
2880 | run_write(sc, RT2860_GPIO_CTRL0x0228, tmp); | |||
2881 | } | |||
2882 | ||||
2883 | /* set initial AGC value */ | |||
2884 | if (group == 0) { /* 2GHz band */ | |||
2885 | if (sc->mac_ver >= 0x3070) | |||
2886 | agc = 0x1c + sc->lna[0] * 2; | |||
2887 | else | |||
2888 | agc = 0x2e + sc->lna[0]; | |||
2889 | } else { /* 5GHz band */ | |||
2890 | if (sc->mac_ver == 0x5592) | |||
2891 | agc = 0x24 + sc->lna[group] * 2; | |||
2892 | else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593) | |||
2893 | agc = 0x22 + (sc->lna[group] * 5) / 3; | |||
2894 | else | |||
2895 | agc = 0x32 + (sc->lna[group] * 5) / 3; | |||
2896 | } | |||
2897 | run_set_agc(sc, agc); | |||
2898 | } | |||
2899 | ||||
2900 | void | |||
2901 | run_rt2870_set_chan(struct run_softc *sc, u_int chan) | |||
2902 | { | |||
2903 | const struct rfprog *rfprog = rt2860_rf2850; | |||
2904 | uint32_t r2, r3, r4; | |||
2905 | int8_t txpow1, txpow2; | |||
2906 | int i; | |||
2907 | ||||
2908 | /* find the settings for this channel (we know it exists) */ | |||
2909 | for (i = 0; rfprog[i].chan != chan; i++); | |||
2910 | ||||
2911 | r2 = rfprog[i].r2; | |||
2912 | if (sc->ntxchains == 1) | |||
2913 | r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ | |||
2914 | if (sc->nrxchains == 1) | |||
2915 | r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ | |||
2916 | else if (sc->nrxchains == 2) | |||
2917 | r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ | |||
2918 | ||||
2919 | /* use Tx power values from EEPROM */ | |||
2920 | txpow1 = sc->txpow1[i]; | |||
2921 | txpow2 = sc->txpow2[i]; | |||
2922 | if (chan > 14) { | |||
2923 | if (txpow1 >= 0) | |||
2924 | txpow1 = txpow1 << 1 | 1; | |||
2925 | else | |||
2926 | txpow1 = (7 + txpow1) << 1; | |||
2927 | if (txpow2 >= 0) | |||
2928 | txpow2 = txpow2 << 1 | 1; | |||
2929 | else | |||
2930 | txpow2 = (7 + txpow2) << 1; | |||
2931 | } | |||
2932 | r3 = rfprog[i].r3 | txpow1 << 7; | |||
2933 | r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; | |||
2934 | ||||
2935 | run_rt2870_rf_write(sc, RT2860_RF10, rfprog[i].r1); | |||
2936 | run_rt2870_rf_write(sc, RT2860_RF22, r2); | |||
2937 | run_rt2870_rf_write(sc, RT2860_RF31, r3); | |||
2938 | run_rt2870_rf_write(sc, RT2860_RF43, r4); | |||
2939 | ||||
2940 | DELAY(200)(*delay_func)(200); | |||
2941 | ||||
2942 | run_rt2870_rf_write(sc, RT2860_RF10, rfprog[i].r1); | |||
2943 | run_rt2870_rf_write(sc, RT2860_RF22, r2); | |||
2944 | run_rt2870_rf_write(sc, RT2860_RF31, r3 | 1); | |||
2945 | run_rt2870_rf_write(sc, RT2860_RF43, r4); | |||
2946 | ||||
2947 | DELAY(200)(*delay_func)(200); | |||
2948 | ||||
2949 | run_rt2870_rf_write(sc, RT2860_RF10, rfprog[i].r1); | |||
2950 | run_rt2870_rf_write(sc, RT2860_RF22, r2); | |||
2951 | run_rt2870_rf_write(sc, RT2860_RF31, r3); | |||
2952 | run_rt2870_rf_write(sc, RT2860_RF43, r4); | |||
2953 | } | |||
2954 | ||||
2955 | void | |||
2956 | run_rt3070_set_chan(struct run_softc *sc, u_int chan) | |||
2957 | { | |||
2958 | int8_t txpow1, txpow2; | |||
2959 | uint8_t rf; | |||
2960 | int i; | |||
2961 | ||||
2962 | /* find the settings for this channel (we know it exists) */ | |||
2963 | for (i = 0; rt2860_rf2850[i].chan != chan; i++); | |||
2964 | ||||
2965 | /* use Tx power values from EEPROM */ | |||
2966 | txpow1 = sc->txpow1[i]; | |||
2967 | txpow2 = sc->txpow2[i]; | |||
2968 | ||||
2969 | run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); | |||
2970 | ||||
2971 | /* RT3370/RT3390: RF R3 [7:4] is not reserved bits. */ | |||
2972 | run_rt3070_rf_read(sc, 3, &rf); | |||
2973 | rf = (rf & ~0x0f) | rt3070_freqs[i].k; | |||
2974 | run_rt3070_rf_write(sc, 3, rf); | |||
2975 | ||||
2976 | run_rt3070_rf_read(sc, 6, &rf); | |||
2977 | rf = (rf & ~0x03) | rt3070_freqs[i].r; | |||
2978 | run_rt3070_rf_write(sc, 6, rf); | |||
2979 | ||||
2980 | /* set Tx0 power */ | |||
2981 | run_rt3070_rf_read(sc, 12, &rf); | |||
2982 | rf = (rf & ~0x1f) | txpow1; | |||
2983 | run_rt3070_rf_write(sc, 12, rf); | |||
2984 | ||||
2985 | /* set Tx1 power */ | |||
2986 | run_rt3070_rf_read(sc, 13, &rf); | |||
2987 | rf = (rf & ~0x1f) | txpow2; | |||
2988 | run_rt3070_rf_write(sc, 13, rf); | |||
2989 | ||||
2990 | run_rt3070_rf_read(sc, 1, &rf); | |||
2991 | rf &= ~0xfc; | |||
2992 | if (sc->ntxchains == 1) | |||
2993 | rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ | |||
2994 | else if (sc->ntxchains == 2) | |||
2995 | rf |= 1 << 7; /* 2T: disable Tx chain 3 */ | |||
2996 | if (sc->nrxchains == 1) | |||
2997 | rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ | |||
2998 | else if (sc->nrxchains == 2) | |||
2999 | rf |= 1 << 6; /* 2R: disable Rx chain 3 */ | |||
3000 | run_rt3070_rf_write(sc, 1, rf); | |||
3001 | ||||
3002 | /* set RF offset */ | |||
3003 | run_rt3070_rf_read(sc, 23, &rf); | |||
3004 | rf = (rf & ~0x7f) | sc->freq; | |||
3005 | run_rt3070_rf_write(sc, 23, rf); | |||
3006 | ||||
3007 | /* program RF filter */ | |||
3008 | run_rt3070_rf_read(sc, 24, &rf); /* Tx */ | |||
3009 | rf = (rf & ~0x3f) | sc->rf24_20mhz; | |||
3010 | run_rt3070_rf_write(sc, 24, rf); | |||
3011 | run_rt3070_rf_read(sc, 31, &rf); /* Rx */ | |||
3012 | rf = (rf & ~0x3f) | sc->rf24_20mhz; | |||
3013 | run_rt3070_rf_write(sc, 31, rf); | |||
3014 | ||||
3015 | /* enable RF tuning */ | |||
3016 | run_rt3070_rf_read(sc, 7, &rf); | |||
3017 | run_rt3070_rf_write(sc, 7, rf | 0x01); | |||
3018 | } | |||
3019 | ||||
3020 | void | |||
3021 | run_rt3572_set_chan(struct run_softc *sc, u_int chan) | |||
3022 | { | |||
3023 | int8_t txpow1, txpow2; | |||
3024 | uint32_t tmp; | |||
3025 | uint8_t rf; | |||
3026 | int i; | |||
3027 | ||||
3028 | /* find the settings for this channel (we know it exists) */ | |||
3029 | for (i = 0; rt2860_rf2850[i].chan != chan; i++); | |||
3030 | ||||
3031 | /* use Tx power values from EEPROM */ | |||
3032 | txpow1 = sc->txpow1[i]; | |||
3033 | txpow2 = sc->txpow2[i]; | |||
3034 | ||||
3035 | if (chan <= 14) { | |||
3036 | run_bbp_write(sc, 25, sc->bbp25); | |||
3037 | run_bbp_write(sc, 26, sc->bbp26); | |||
3038 | } else { | |||
3039 | /* enable IQ phase correction */ | |||
3040 | run_bbp_write(sc, 25, 0x09); | |||
3041 | run_bbp_write(sc, 26, 0xff); | |||
3042 | } | |||
3043 | ||||
3044 | run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); | |||
3045 | run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); | |||
3046 | run_rt3070_rf_read(sc, 6, &rf); | |||
3047 | rf = (rf & ~0x0f) | rt3070_freqs[i].r; | |||
3048 | rf |= (chan <= 14) ? 0x08 : 0x04; | |||
3049 | run_rt3070_rf_write(sc, 6, rf); | |||
3050 | ||||
3051 | /* set PLL mode */ | |||
3052 | run_rt3070_rf_read(sc, 5, &rf); | |||
3053 | rf &= ~(0x08 | 0x04); | |||
3054 | rf |= (chan <= 14) ? 0x04 : 0x08; | |||
3055 | run_rt3070_rf_write(sc, 5, rf); | |||
3056 | ||||
3057 | /* set Tx power for chain 0 */ | |||
3058 | if (chan <= 14) | |||
3059 | rf = 0x60 | txpow1; | |||
3060 | else | |||
3061 | rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); | |||
3062 | run_rt3070_rf_write(sc, 12, rf); | |||
3063 | ||||
3064 | /* set Tx power for chain 1 */ | |||
3065 | if (chan <= 14) | |||
3066 | rf = 0x60 | txpow2; | |||
3067 | else | |||
3068 | rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); | |||
3069 | run_rt3070_rf_write(sc, 13, rf); | |||
3070 | ||||
3071 | /* set Tx/Rx streams */ | |||
3072 | run_rt3070_rf_read(sc, 1, &rf); | |||
3073 | rf &= ~0xfc; | |||
3074 | if (sc->ntxchains == 1) | |||
3075 | rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ | |||
3076 | else if (sc->ntxchains == 2) | |||
3077 | rf |= 1 << 7; /* 2T: disable Tx chain 3 */ | |||
3078 | if (sc->nrxchains == 1) | |||
3079 | rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ | |||
3080 | else if (sc->nrxchains == 2) | |||
3081 | rf |= 1 << 6; /* 2R: disable Rx chain 3 */ | |||
3082 | run_rt3070_rf_write(sc, 1, rf); | |||
3083 | ||||
3084 | /* set RF offset */ | |||
3085 | run_rt3070_rf_read(sc, 23, &rf); | |||
3086 | rf = (rf & ~0x7f) | sc->freq; | |||
3087 | run_rt3070_rf_write(sc, 23, rf); | |||
3088 | ||||
3089 | /* program RF filter */ | |||
3090 | rf = sc->rf24_20mhz; | |||
3091 | run_rt3070_rf_write(sc, 24, rf); /* Tx */ | |||
3092 | run_rt3070_rf_write(sc, 31, rf); /* Rx */ | |||
3093 | ||||
3094 | /* enable RF tuning */ | |||
3095 | run_rt3070_rf_read(sc, 7, &rf); | |||
3096 | rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); | |||
3097 | run_rt3070_rf_write(sc, 7, rf); | |||
3098 | ||||
3099 | /* TSSI */ | |||
3100 | rf = (chan <= 14) ? 0xc3 : 0xc0; | |||
3101 | run_rt3070_rf_write(sc, 9, rf); | |||
3102 | ||||
3103 | /* set loop filter 1 */ | |||
3104 | run_rt3070_rf_write(sc, 10, 0xf1); | |||
3105 | /* set loop filter 2 */ | |||
3106 | run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); | |||
3107 | ||||
3108 | /* set tx_mx2_ic */ | |||
3109 | run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); | |||
3110 | /* set tx_mx1_ic */ | |||
3111 | if (chan <= 14) | |||
3112 | rf = 0x48 | sc->txmixgain_2ghz; | |||
3113 | else | |||
3114 | rf = 0x78 | sc->txmixgain_5ghz; | |||
3115 | run_rt3070_rf_write(sc, 16, rf); | |||
3116 | ||||
3117 | /* set tx_lo1 */ | |||
3118 | run_rt3070_rf_write(sc, 17, 0x23); | |||
3119 | /* set tx_lo2 */ | |||
3120 | if (chan <= 14) | |||
3121 | rf = 0x93; | |||
3122 | else if (chan <= 64) | |||
3123 | rf = 0xb7; | |||
3124 | else if (chan <= 128) | |||
3125 | rf = 0x74; | |||
3126 | else | |||
3127 | rf = 0x72; | |||
3128 | run_rt3070_rf_write(sc, 19, rf); | |||
3129 | ||||
3130 | /* set rx_lo1 */ | |||
3131 | if (chan <= 14) | |||
3132 | rf = 0xb3; | |||
3133 | else if (chan <= 64) | |||
3134 | rf = 0xf6; | |||
3135 | else if (chan <= 128) | |||
3136 | rf = 0xf4; | |||
3137 | else | |||
3138 | rf = 0xf3; | |||
3139 | run_rt3070_rf_write(sc, 20, rf); | |||
3140 | ||||
3141 | /* set pfd_delay */ | |||
3142 | if (chan <= 14) | |||
3143 | rf = 0x15; | |||
3144 | else if (chan <= 64) | |||
3145 | rf = 0x3d; | |||
3146 | else | |||
3147 | rf = 0x01; | |||
3148 | run_rt3070_rf_write(sc, 25, rf); | |||
3149 | ||||
3150 | /* set rx_lo2 */ | |||
3151 | run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); | |||
3152 | /* set ldo_rf_vc */ | |||
3153 | run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); | |||
3154 | /* set drv_cc */ | |||
3155 | run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); | |||
3156 | ||||
3157 | run_read(sc, RT2860_GPIO_CTRL0x0228, &tmp); | |||
3158 | tmp &= ~0x8080; | |||
3159 | if (chan <= 14) | |||
3160 | tmp |= 0x80; | |||
3161 | run_write(sc, RT2860_GPIO_CTRL0x0228, tmp); | |||
3162 | ||||
3163 | /* enable RF tuning */ | |||
3164 | run_rt3070_rf_read(sc, 7, &rf); | |||
3165 | run_rt3070_rf_write(sc, 7, rf | 0x01); | |||
3166 | ||||
3167 | DELAY(2000)(*delay_func)(2000); | |||
3168 | } | |||
3169 | ||||
3170 | void | |||
3171 | run_rt3593_set_chan(struct run_softc *sc, u_int chan) | |||
3172 | { | |||
3173 | int8_t txpow1, txpow2, txpow3; | |||
3174 | uint8_t h20mhz, rf; | |||
3175 | int i; | |||
3176 | ||||
3177 | /* find the settings for this channel (we know it exists) */ | |||
3178 | for (i = 0; rt2860_rf2850[i].chan != chan; i++); | |||
3179 | ||||
3180 | /* use Tx power values from EEPROM */ | |||
3181 | txpow1 = sc->txpow1[i]; | |||
3182 | txpow2 = sc->txpow2[i]; | |||
3183 | txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; | |||
3184 | ||||
3185 | if (chan <= 14) { | |||
3186 | run_bbp_write(sc, 25, sc->bbp25); | |||
3187 | run_bbp_write(sc, 26, sc->bbp26); | |||
3188 | } else { | |||
3189 | /* Enable IQ phase correction. */ | |||
3190 | run_bbp_write(sc, 25, 0x09); | |||
3191 | run_bbp_write(sc, 26, 0xff); | |||
3192 | } | |||
3193 | ||||
3194 | run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); | |||
3195 | run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); | |||
3196 | run_rt3070_rf_read(sc, 11, &rf); | |||
3197 | rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); | |||
3198 | run_rt3070_rf_write(sc, 11, rf); | |||
3199 | ||||
3200 | /* Set pll_idoh. */ | |||
3201 | run_rt3070_rf_read(sc, 11, &rf); | |||
3202 | rf &= ~0x4c; | |||
3203 | rf |= (chan <= 14) ? 0x44 : 0x48; | |||
3204 | run_rt3070_rf_write(sc, 11, rf); | |||
3205 | ||||
3206 | if (chan <= 14) | |||
3207 | rf = txpow1 & 0x1f; | |||
3208 | else | |||
3209 | rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); | |||
3210 | run_rt3070_rf_write(sc, 53, rf); | |||
3211 | ||||
3212 | if (chan <= 14) | |||
3213 | rf = txpow2 & 0x1f; | |||
3214 | else | |||
3215 | rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); | |||
3216 | run_rt3070_rf_write(sc, 55, rf); | |||
3217 | ||||
3218 | if (chan <= 14) | |||
3219 | rf = txpow3 & 0x1f; | |||
3220 | else | |||
3221 | rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); | |||
3222 | run_rt3070_rf_write(sc, 54, rf); | |||
3223 | ||||
3224 | rf = RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1); | |||
3225 | if (sc->ntxchains == 3) | |||
3226 | rf |= RT3070_TX0_PD(1 << 3) | RT3070_TX1_PD(1 << 5) | RT3070_TX2_PD(1 << 7); | |||
3227 | else | |||
3228 | rf |= RT3070_TX0_PD(1 << 3) | RT3070_TX1_PD(1 << 5); | |||
3229 | rf |= RT3070_RX0_PD(1 << 2) | RT3070_RX1_PD(1 << 4) | RT3070_RX2_PD(1 << 6); | |||
3230 | run_rt3070_rf_write(sc, 1, rf); | |||
3231 | ||||
3232 | run_adjust_freq_offset(sc); | |||
3233 | ||||
3234 | run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); | |||
3235 | ||||
3236 | h20mhz = (sc->rf24_20mhz & 0x20) >> 5; | |||
3237 | run_rt3070_rf_read(sc, 30, &rf); | |||
3238 | rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); | |||
3239 | run_rt3070_rf_write(sc, 30, rf); | |||
3240 | ||||
3241 | run_rt3070_rf_read(sc, 36, &rf); | |||
3242 | if (chan <= 14) | |||
3243 | rf |= 0x80; | |||
3244 | else | |||
3245 | rf &= ~0x80; | |||
3246 | run_rt3070_rf_write(sc, 36, rf); | |||
3247 | ||||
3248 | /* Set vcolo_bs. */ | |||
3249 | run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); | |||
3250 | /* Set pfd_delay. */ | |||
3251 | run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); | |||
3252 | ||||
3253 | /* Set vco bias current control. */ | |||
3254 | run_rt3070_rf_read(sc, 6, &rf); | |||
3255 | rf &= ~0xc0; | |||
3256 | if (chan <= 14) | |||
3257 | rf |= 0x40; | |||
3258 | else if (chan <= 128) | |||
3259 | rf |= 0x80; | |||
3260 | else | |||
3261 | rf |= 0x40; | |||
3262 | run_rt3070_rf_write(sc, 6, rf); | |||
3263 | ||||
3264 | run_rt3070_rf_read(sc, 30, &rf); | |||
3265 | rf = (rf & ~0x18) | 0x10; | |||
3266 | run_rt3070_rf_write(sc, 30, rf); | |||
3267 | ||||
3268 | run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); | |||
3269 | run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); | |||
3270 | ||||
3271 | run_rt3070_rf_read(sc, 51, &rf); | |||
3272 | rf = (rf & ~0x03) | 0x01; | |||
3273 | run_rt3070_rf_write(sc, 51, rf); | |||
3274 | /* Set tx_mx1_cc. */ | |||
3275 | run_rt3070_rf_read(sc, 51, &rf); | |||
3276 | rf &= ~0x1c; | |||
3277 | rf |= (chan <= 14) ? 0x14 : 0x10; | |||
3278 | run_rt3070_rf_write(sc, 51, rf); | |||
3279 | /* Set tx_mx1_ic. */ | |||
3280 | run_rt3070_rf_read(sc, 51, &rf); | |||
3281 | rf &= ~0xe0; | |||
3282 | rf |= (chan <= 14) ? 0x60 : 0x40; | |||
3283 | run_rt3070_rf_write(sc, 51, rf); | |||
3284 | /* Set tx_lo1_ic. */ | |||
3285 | run_rt3070_rf_read(sc, 49, &rf); | |||
3286 | rf &= ~0x1c; | |||
3287 | rf |= (chan <= 14) ? 0x0c : 0x08; | |||
3288 | run_rt3070_rf_write(sc, 49, rf); | |||
3289 | /* Set tx_lo1_en. */ | |||
3290 | run_rt3070_rf_read(sc, 50, &rf); | |||
3291 | run_rt3070_rf_write(sc, 50, rf & ~0x20); | |||
3292 | /* Set drv_cc. */ | |||
3293 | run_rt3070_rf_read(sc, 57, &rf); | |||
3294 | rf &= ~0xfc; | |||
3295 | rf |= (chan <= 14) ? 0x6c : 0x3c; | |||
3296 | run_rt3070_rf_write(sc, 57, rf); | |||
3297 | /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ | |||
3298 | run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); | |||
3299 | /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ | |||
3300 | run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); | |||
3301 | /* Enable VCO calibration. */ | |||
3302 | run_rt3070_rf_read(sc, 3, &rf); | |||
3303 | rf &= ~RT3593_VCOCAL(1 << 7); | |||
3304 | rf |= (chan <= 14) ? RT3593_VCOCAL(1 << 7) : 0xbe; | |||
3305 | run_rt3070_rf_write(sc, 3, rf); | |||
3306 | ||||
3307 | if (chan <= 14) | |||
3308 | rf = 0x23; | |||
3309 | else if (chan <= 64) | |||
3310 | rf = 0x36; | |||
3311 | else if (chan <= 128) | |||
3312 | rf = 0x32; | |||
3313 | else | |||
3314 | rf = 0x30; | |||
3315 | run_rt3070_rf_write(sc, 39, rf); | |||
3316 | if (chan <= 14) | |||
3317 | rf = 0xbb; | |||
3318 | else if (chan <= 64) | |||
3319 | rf = 0xeb; | |||
3320 | else if (chan <= 128) | |||
3321 | rf = 0xb3; | |||
3322 | else | |||
3323 | rf = 0x9b; | |||
3324 | run_rt3070_rf_write(sc, 45, rf); | |||
3325 | ||||
3326 | /* Set FEQ/AEQ control. */ | |||
3327 | run_bbp_write(sc, 105, 0x34); | |||
3328 | } | |||
3329 | ||||
3330 | void | |||
3331 | run_rt5390_set_chan(struct run_softc *sc, u_int chan) | |||
3332 | { | |||
3333 | int8_t txpow1, txpow2; | |||
3334 | uint8_t rf; | |||
3335 | int i; | |||
3336 | ||||
3337 | /* find the settings for this channel (we know it exists) */ | |||
3338 | for (i = 0; rt2860_rf2850[i].chan != chan; i++); | |||
3339 | ||||
3340 | /* use Tx power values from EEPROM */ | |||
3341 | txpow1 = sc->txpow1[i]; | |||
3342 | txpow2 = sc->txpow2[i]; | |||
3343 | ||||
3344 | run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); | |||
3345 | run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); | |||
3346 | run_rt3070_rf_read(sc, 11, &rf); | |||
3347 | rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); | |||
3348 | run_rt3070_rf_write(sc, 11, rf); | |||
3349 | ||||
3350 | run_rt3070_rf_read(sc, 49, &rf); | |||
3351 | rf = (rf & ~0x3f) | (txpow1 & 0x3f); | |||
3352 | /* The valid range of the RF R49 is 0x00 to 0x27. */ | |||
3353 | if ((rf & 0x3f) > 0x27) | |||
3354 | rf = (rf & ~0x3f) | 0x27; | |||
3355 | run_rt3070_rf_write(sc, 49, rf); | |||
3356 | ||||
3357 | if (sc->mac_ver == 0x5392) { | |||
3358 | run_rt3070_rf_read(sc, 50, &rf); | |||
3359 | rf = (rf & ~0x3f) | (txpow2 & 0x3f); | |||
3360 | /* The valid range of the RF R50 is 0x00 to 0x27. */ | |||
3361 | if ((rf & 0x3f) > 0x27) | |||
3362 | rf = (rf & ~0x3f) | 0x27; | |||
3363 | run_rt3070_rf_write(sc, 50, rf); | |||
3364 | } | |||
3365 | ||||
3366 | run_rt3070_rf_read(sc, 1, &rf); | |||
3367 | rf |= RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1) | RT3070_RX0_PD(1 << 2) | RT3070_TX0_PD(1 << 3); | |||
3368 | if (sc->mac_ver
| |||
3369 | rf |= RT3070_RX1_PD(1 << 4) | RT3070_TX1_PD(1 << 5); | |||
3370 | run_rt3070_rf_write(sc, 1, rf); | |||
3371 | ||||
3372 | if (sc->mac_ver
| |||
3373 | run_rt3070_rf_read(sc, 2, &rf); | |||
3374 | rf |= 0x80; | |||
3375 | run_rt3070_rf_write(sc, 2, rf); | |||
3376 | DELAY(10)(*delay_func)(10); | |||
3377 | rf &= 0x7f; | |||
3378 | run_rt3070_rf_write(sc, 2, rf); | |||
3379 | } | |||
3380 | ||||
3381 | run_adjust_freq_offset(sc); | |||
3382 | ||||
3383 | if (sc->mac_ver == 0x5392) { | |||
3384 | /* Fix for RT5392C. */ | |||
3385 | if (sc->mac_rev >= 0x0223) { | |||
3386 | if (chan <= 4) | |||
3387 | rf = 0x0f; | |||
3388 | else if (chan >= 5 && chan <= 7) | |||
3389 | rf = 0x0e; | |||
3390 | else | |||
3391 | rf = 0x0d; | |||
3392 | run_rt3070_rf_write(sc, 23, rf); | |||
3393 | ||||
3394 | if (chan <= 4) | |||
3395 | rf = 0x0c; | |||
3396 | else if (chan == 5) | |||
3397 | rf = 0x0b; | |||
3398 | else if (chan >= 6 && chan <= 7) | |||
3399 | rf = 0x0a; | |||
3400 | else if (chan >= 8 && chan <= 10) | |||
3401 | rf = 0x09; | |||
3402 | else | |||
3403 | rf = 0x08; | |||
3404 | run_rt3070_rf_write(sc, 59, rf); | |||
3405 | } else { | |||
3406 | if (chan <= 11) | |||
3407 | rf = 0x0f; | |||
3408 | else | |||
3409 | rf = 0x0b; | |||
3410 | run_rt3070_rf_write(sc, 59, rf); | |||
3411 | } | |||
3412 | } else { | |||
3413 | /* Fix for RT5390F. */ | |||
3414 | if (sc->mac_rev >= 0x0502) { | |||
3415 | if (chan <= 11) | |||
3416 | rf = 0x43; | |||
3417 | else | |||
3418 | rf = 0x23; | |||
3419 | run_rt3070_rf_write(sc, 55, rf); | |||
3420 | ||||
3421 | if (chan <= 11) | |||
3422 | rf = 0x0f; | |||
3423 | else if (chan == 12) | |||
3424 | rf = 0x0d; | |||
3425 | else | |||
3426 | rf = 0x0b; | |||
3427 | run_rt3070_rf_write(sc, 59, rf); | |||
3428 | } else { | |||
3429 | run_rt3070_rf_write(sc, 55, 0x44); | |||
3430 | run_rt3070_rf_write(sc, 59, 0x8f); | |||
3431 | } | |||
3432 | } | |||
3433 | ||||
3434 | /* Enable VCO calibration. */ | |||
3435 | run_rt3070_rf_read(sc, 3, &rf); | |||
3436 | rf |= RT3593_VCOCAL(1 << 7); | |||
3437 | run_rt3070_rf_write(sc, 3, rf); | |||
3438 | } | |||
3439 | ||||
3440 | void | |||
3441 | run_rt5592_set_chan(struct run_softc *sc, u_int chan) | |||
3442 | { | |||
3443 | const struct rt5592_freqs *freqs; | |||
3444 | uint32_t tmp; | |||
3445 | uint8_t reg, rf, txpow_bound; | |||
3446 | int8_t txpow1, txpow2; | |||
3447 | int i; | |||
3448 | ||||
3449 | run_read(sc, RT5592_DEBUG_INDEX0x05e8, &tmp); | |||
3450 | freqs = (tmp & RT5592_SEL_XTAL(1U << 31)) ? | |||
3451 | rt5592_freqs_40mhz : rt5592_freqs_20mhz; | |||
3452 | ||||
3453 | /* find the settings for this channel (we know it exists) */ | |||
3454 | for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); | |||
3455 | ||||
3456 | /* use Tx power values from EEPROM */ | |||
3457 | txpow1 = sc->txpow1[i]; | |||
3458 | txpow2 = sc->txpow2[i]; | |||
3459 | ||||
3460 | run_read(sc, RT3070_LDO_CFG00x05d4, &tmp); | |||
3461 | tmp &= ~0x1c000000; | |||
3462 | if (chan > 14) | |||
3463 | tmp |= 0x14000000; | |||
3464 | run_write(sc, RT3070_LDO_CFG00x05d4, tmp); | |||
3465 | ||||
3466 | /* N setting. */ | |||
3467 | run_rt3070_rf_write(sc, 8, freqs->n & 0xff); | |||
3468 | run_rt3070_rf_read(sc, 9, &rf); | |||
3469 | rf &= ~(1 << 4); | |||
3470 | rf |= ((freqs->n & 0x0100) >> 8) << 4; | |||
3471 | run_rt3070_rf_write(sc, 9, rf); | |||
3472 | ||||
3473 | /* K setting. */ | |||
3474 | run_rt3070_rf_read(sc, 9, &rf); | |||
3475 | rf &= ~0x0f; | |||
3476 | rf |= (freqs->k & 0x0f); | |||
3477 | run_rt3070_rf_write(sc, 9, rf); | |||
3478 | ||||
3479 | /* Mode setting. */ | |||
3480 | run_rt3070_rf_read(sc, 11, &rf); | |||
3481 | rf &= ~0x0c; | |||
3482 | rf |= ((freqs->m - 0x8) & 0x3) << 2; | |||
3483 | run_rt3070_rf_write(sc, 11, rf); | |||
3484 | run_rt3070_rf_read(sc, 9, &rf); | |||
3485 | rf &= ~(1 << 7); | |||
3486 | rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; | |||
3487 | run_rt3070_rf_write(sc, 9, rf); | |||
3488 | ||||
3489 | /* R setting. */ | |||
3490 | run_rt3070_rf_read(sc, 11, &rf); | |||
3491 | rf &= ~0x03; | |||
3492 | rf |= (freqs->r - 0x1); | |||
3493 | run_rt3070_rf_write(sc, 11, rf); | |||
3494 | ||||
3495 | if (chan <= 14) { | |||
3496 | /* Initialize RF registers for 2GHZ. */ | |||
3497 | for (i = 0; i < nitems(rt5592_2ghz_def_rf)(sizeof((rt5592_2ghz_def_rf)) / sizeof((rt5592_2ghz_def_rf)[0 ])); i++) { | |||
3498 | run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, | |||
3499 | rt5592_2ghz_def_rf[i].val); | |||
3500 | } | |||
3501 | ||||
3502 | rf = (chan <= 10) ? 0x07 : 0x06; | |||
3503 | run_rt3070_rf_write(sc, 23, rf); | |||
3504 | run_rt3070_rf_write(sc, 59, rf); | |||
3505 | ||||
3506 | run_rt3070_rf_write(sc, 55, 0x43); | |||
3507 | ||||
3508 | /* | |||
3509 | * RF R49/R50 Tx power ALC code. | |||
3510 | * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. | |||
3511 | */ | |||
3512 | reg = 2; | |||
3513 | txpow_bound = 0x27; | |||
3514 | } else { | |||
3515 | /* Initialize RF registers for 5GHZ. */ | |||
3516 | for (i = 0; i < nitems(rt5592_5ghz_def_rf)(sizeof((rt5592_5ghz_def_rf)) / sizeof((rt5592_5ghz_def_rf)[0 ])); i++) { | |||
3517 | run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, | |||
3518 | rt5592_5ghz_def_rf[i].val); | |||
3519 | } | |||
3520 | for (i = 0; i < nitems(rt5592_chan_5ghz)(sizeof((rt5592_chan_5ghz)) / sizeof((rt5592_chan_5ghz)[0])); i++) { | |||
3521 | if (chan >= rt5592_chan_5ghz[i].firstchan && | |||
3522 | chan <= rt5592_chan_5ghz[i].lastchan) { | |||
3523 | run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, | |||
3524 | rt5592_chan_5ghz[i].val); | |||
3525 | } | |||
3526 | } | |||
3527 | ||||
3528 | /* | |||
3529 | * RF R49/R50 Tx power ALC code. | |||
3530 | * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. | |||
3531 | */ | |||
3532 | reg = 3; | |||
3533 | txpow_bound = 0x2b; | |||
3534 | } | |||
3535 | ||||
3536 | /* RF R49 ch0 Tx power ALC code. */ | |||
3537 | run_rt3070_rf_read(sc, 49, &rf); | |||
3538 | rf &= ~0xc0; | |||
3539 | rf |= (reg << 6); | |||
3540 | rf = (rf & ~0x3f) | (txpow1 & 0x3f); | |||
3541 | if ((rf & 0x3f) > txpow_bound) | |||
3542 | rf = (rf & ~0x3f) | txpow_bound; | |||
3543 | run_rt3070_rf_write(sc, 49, rf); | |||
3544 | ||||
3545 | /* RF R50 ch1 Tx power ALC code. */ | |||
3546 | run_rt3070_rf_read(sc, 50, &rf); | |||
3547 | rf &= ~(1 << 7 | 1 << 6); | |||
3548 | rf |= (reg << 6); | |||
3549 | rf = (rf & ~0x3f) | (txpow2 & 0x3f); | |||
3550 | if ((rf & 0x3f) > txpow_bound) | |||
3551 | rf = (rf & ~0x3f) | txpow_bound; | |||
3552 | run_rt3070_rf_write(sc, 50, rf); | |||
3553 | ||||
3554 | /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ | |||
3555 | run_rt3070_rf_read(sc, 1, &rf); | |||
3556 | rf |= (RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1) | RT3070_RX0_PD(1 << 2) | RT3070_TX0_PD(1 << 3)); | |||
3557 | if (sc->ntxchains > 1) | |||
3558 | rf |= RT3070_TX1_PD(1 << 5); | |||
3559 | if (sc->nrxchains > 1) | |||
3560 | rf |= RT3070_RX1_PD(1 << 4); | |||
3561 | run_rt3070_rf_write(sc, 1, rf); | |||
3562 | ||||
3563 | run_rt3070_rf_write(sc, 6, 0xe4); | |||
3564 | ||||
3565 | run_rt3070_rf_write(sc, 30, 0x10); | |||
3566 | run_rt3070_rf_write(sc, 31, 0x80); | |||
3567 | run_rt3070_rf_write(sc, 32, 0x80); | |||
3568 | ||||
3569 | run_adjust_freq_offset(sc); | |||
3570 | ||||
3571 | /* Enable VCO calibration. */ | |||
3572 | run_rt3070_rf_read(sc, 3, &rf); | |||
3573 | rf |= RT3593_VCOCAL(1 << 7); | |||
3574 | run_rt3070_rf_write(sc, 3, rf); | |||
3575 | } | |||
3576 | ||||
3577 | void | |||
3578 | run_set_agc(struct run_softc *sc, uint8_t agc) | |||
3579 | { | |||
3580 | uint8_t bbp; | |||
3581 | ||||
3582 | if (sc->mac_ver == 0x3572) { | |||
3583 | run_bbp_read(sc, 27, &bbp); | |||
3584 | bbp &= ~(0x3 << 5); | |||
3585 | run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ | |||
3586 | run_bbp_write(sc, 66, agc); | |||
3587 | run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ | |||
3588 | run_bbp_write(sc, 66, agc); | |||
3589 | } else | |||
3590 | run_bbp_write(sc, 66, agc); | |||
3591 | } | |||
3592 | ||||
3593 | void | |||
3594 | run_set_rx_antenna(struct run_softc *sc, int aux) | |||
3595 | { | |||
3596 | uint32_t tmp; | |||
3597 | uint8_t bbp152; | |||
3598 | ||||
3599 | if (aux) { | |||
3600 | if (sc->rf_rev == RT5390_RF_53700x5370) { | |||
3601 | run_bbp_read(sc, 152, &bbp152); | |||
3602 | run_bbp_write(sc, 152, bbp152 & ~0x80); | |||
3603 | } else { | |||
3604 | run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL0x73, 0); | |||
3605 | run_read(sc, RT2860_GPIO_CTRL0x0228, &tmp); | |||
3606 | run_write(sc, RT2860_GPIO_CTRL0x0228, (tmp & ~0x0808) | 0x08); | |||
3607 | } | |||
3608 | } else { | |||
3609 | if (sc->rf_rev == RT5390_RF_53700x5370) { | |||
3610 | run_bbp_read(sc, 152, &bbp152); | |||
3611 | run_bbp_write(sc, 152, bbp152 | 0x80); | |||
3612 | } else { | |||
3613 | run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL0x73, 1); | |||
3614 | run_read(sc, RT2860_GPIO_CTRL0x0228, &tmp); | |||
3615 | run_write(sc, RT2860_GPIO_CTRL0x0228, tmp & ~0x0808); | |||
3616 | } | |||
3617 | } | |||
3618 | } | |||
3619 | ||||
3620 | int | |||
3621 | run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) | |||
3622 | { | |||
3623 | struct ieee80211com *ic = &sc->sc_ic; | |||
3624 | u_int chan, group; | |||
3625 | ||||
3626 | chan = ieee80211_chan2ieee(ic, c); | |||
3627 | if (chan == 0 || chan == IEEE80211_CHAN_ANY0xffff) | |||
3628 | return EINVAL22; | |||
3629 | ||||
3630 | if (sc->mac_ver == 0x5592) | |||
3631 | run_rt5592_set_chan(sc, chan); | |||
3632 | else if (sc->mac_ver >= 0x5390) | |||
3633 | run_rt5390_set_chan(sc, chan); | |||
3634 | else if (sc->mac_ver == 0x3593) | |||
3635 | run_rt3593_set_chan(sc, chan); | |||
3636 | else if (sc->mac_ver == 0x3572) | |||
3637 | run_rt3572_set_chan(sc, chan); | |||
3638 | else if (sc->mac_ver >= 0x3070) | |||
3639 | run_rt3070_set_chan(sc, chan); | |||
3640 | else | |||
3641 | run_rt2870_set_chan(sc, chan); | |||
3642 | ||||
3643 | /* determine channel group */ | |||
3644 | if (chan <= 14) | |||
3645 | group = 0; | |||
3646 | else if (chan <= 64) | |||
3647 | group = 1; | |||
3648 | else if (chan <= 128) | |||
3649 | group = 2; | |||
3650 | else | |||
3651 | group = 3; | |||
3652 | ||||
3653 | /* XXX necessary only when group has changed! */ | |||
3654 | run_select_chan_group(sc, group); | |||
3655 | ||||
3656 | DELAY(1000)(*delay_func)(1000); | |||
3657 | ||||
3658 | /* Perform IQ calibration. */ | |||
3659 | if (sc->mac_ver >= 0x5392) | |||
3660 | run_iq_calib(sc, chan); | |||
3661 | ||||
3662 | return 0; | |||
3663 | } | |||
3664 | ||||
3665 | void | |||
3666 | run_enable_tsf_sync(struct run_softc *sc) | |||
3667 | { | |||
3668 | struct ieee80211com *ic = &sc->sc_ic; | |||
3669 | uint32_t tmp; | |||
3670 | ||||
3671 | run_read(sc, RT2860_BCN_TIME_CFG0x1114, &tmp); | |||
3672 | tmp &= ~0x1fffff; | |||
3673 | tmp |= ic->ic_bss->ni_intval * 16; | |||
3674 | tmp |= RT2860_TSF_TIMER_EN(1 << 16) | RT2860_TBTT_TIMER_EN(1 << 19); | |||
3675 | /* local TSF is always updated with remote TSF on beacon reception */ | |||
3676 | tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT17; | |||
3677 | run_write(sc, RT2860_BCN_TIME_CFG0x1114, tmp); | |||
3678 | } | |||
3679 | ||||
3680 | void | |||
3681 | run_enable_mrr(struct run_softc *sc) | |||
3682 | { | |||
3683 | #define CCK(mcs) (mcs) | |||
3684 | #define OFDM(mcs) (1 << 3 | (mcs)) | |||
3685 | run_write(sc, RT2860_LG_FBK_CFG00x135c, | |||
3686 | OFDM(6) << 28 | /* 54->48 */ | |||
3687 | OFDM(5) << 24 | /* 48->36 */ | |||
3688 | OFDM(4) << 20 | /* 36->24 */ | |||
3689 | OFDM(3) << 16 | /* 24->18 */ | |||
3690 | OFDM(2) << 12 | /* 18->12 */ | |||
3691 | OFDM(1) << 8 | /* 12-> 9 */ | |||
3692 | OFDM(0) << 4 | /* 9-> 6 */ | |||
3693 | OFDM(0)); /* 6-> 6 */ | |||
3694 | ||||
3695 | run_write(sc, RT2860_LG_FBK_CFG10x1360, | |||
3696 | CCK(2) << 12 | /* 11->5.5 */ | |||
3697 | CCK(1) << 8 | /* 5.5-> 2 */ | |||
3698 | CCK(0) << 4 | /* 2-> 1 */ | |||
3699 | CCK(0)); /* 1-> 1 */ | |||
3700 | #undef OFDM | |||
3701 | #undef CCK | |||
3702 | } | |||
3703 | ||||
3704 | void | |||
3705 | run_set_txpreamble(struct run_softc *sc) | |||
3706 | { | |||
3707 | uint32_t tmp; | |||
3708 | ||||
3709 | run_read(sc, RT2860_AUTO_RSP_CFG0x1404, &tmp); | |||
3710 | if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE0x00040000) | |||
3711 | tmp |= RT2860_CCK_SHORT_EN(1 << 4); | |||
3712 | else | |||
3713 | tmp &= ~RT2860_CCK_SHORT_EN(1 << 4); | |||
3714 | run_write(sc, RT2860_AUTO_RSP_CFG0x1404, tmp); | |||
3715 | } | |||
3716 | ||||
3717 | void | |||
3718 | run_set_basicrates(struct run_softc *sc) | |||
3719 | { | |||
3720 | struct ieee80211com *ic = &sc->sc_ic; | |||
3721 | ||||
3722 | /* set basic rates mask */ | |||
3723 | if (ic->ic_curmode == IEEE80211_MODE_11B) | |||
3724 | run_write(sc, RT2860_LEGACY_BASIC_RATE0x1408, 0x003); | |||
3725 | else if (ic->ic_curmode == IEEE80211_MODE_11A) | |||
3726 | run_write(sc, RT2860_LEGACY_BASIC_RATE0x1408, 0x150); | |||
3727 | else /* 11g */ | |||
3728 | run_write(sc, RT2860_LEGACY_BASIC_RATE0x1408, 0x15f); | |||
3729 | } | |||
3730 | ||||
3731 | void | |||
3732 | run_set_leds(struct run_softc *sc, uint16_t which) | |||
3733 | { | |||
3734 | (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS0x50, | |||
3735 | which | (sc->leds & 0x7f)); | |||
3736 | } | |||
3737 | ||||
3738 | void | |||
3739 | run_set_bssid(struct run_softc *sc, const uint8_t *bssid) | |||
3740 | { | |||
3741 | run_write(sc, RT2860_MAC_BSSID_DW00x1010, | |||
3742 | bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); | |||
3743 | run_write(sc, RT2860_MAC_BSSID_DW10x1014, | |||
3744 | bssid[4] | bssid[5] << 8); | |||
3745 | } | |||
3746 | ||||
3747 | void | |||
3748 | run_set_macaddr(struct run_softc *sc, const uint8_t *addr) | |||
3749 | { | |||
3750 | run_write(sc, RT2860_MAC_ADDR_DW00x1008, | |||
3751 | addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); | |||
3752 | run_write(sc, RT2860_MAC_ADDR_DW10x100c, | |||
3753 | addr[4] | addr[5] << 8 | 0xff << 16); | |||
3754 | } | |||
3755 | ||||
3756 | void | |||
3757 | run_updateslot(struct ieee80211com *ic) | |||
3758 | { | |||
3759 | /* do it in a process context */ | |||
3760 | run_do_async(ic->ic_softcic_ac.ac_if.if_softc, run_updateslot_cb, NULL((void *)0), 0); | |||
3761 | } | |||
3762 | ||||
3763 | void | |||
3764 | run_updateslot_cb(struct run_softc *sc, void *arg) | |||
3765 | { | |||
3766 | uint32_t tmp; | |||
3767 | ||||
3768 | run_read(sc, RT2860_BKOFF_SLOT_CFG0x1104, &tmp); | |||
3769 | tmp &= ~0xff; | |||
3770 | tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT0x00020000) ? | |||
3771 | IEEE80211_DUR_DS_SHSLOT9 : IEEE80211_DUR_DS_SLOT20; | |||
3772 | run_write(sc, RT2860_BKOFF_SLOT_CFG0x1104, tmp); | |||
3773 | } | |||
3774 | ||||
3775 | #if NBPFILTER1 > 0 | |||
3776 | int8_t | |||
3777 | run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) | |||
3778 | { | |||
3779 | struct ieee80211com *ic = &sc->sc_ic; | |||
3780 | struct ieee80211_channel *c = ic->ic_ibss_chan; | |||
3781 | int delta; | |||
3782 | ||||
3783 | if (IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0)) { | |||
3784 | u_int chan = ieee80211_chan2ieee(ic, c); | |||
3785 | delta = sc->rssi_5ghz[rxchain]; | |||
3786 | ||||
3787 | /* determine channel group */ | |||
3788 | if (chan <= 64) | |||
3789 | delta -= sc->lna[1]; | |||
3790 | else if (chan <= 128) | |||
3791 | delta -= sc->lna[2]; | |||
3792 | else | |||
3793 | delta -= sc->lna[3]; | |||
3794 | } else | |||
3795 | delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; | |||
3796 | ||||
3797 | return -12 - delta - rssi; | |||
3798 | } | |||
3799 | #endif | |||
3800 | ||||
3801 | void | |||
3802 | run_rt5390_bbp_init(struct run_softc *sc) | |||
3803 | { | |||
3804 | int i; | |||
3805 | uint8_t bbp; | |||
3806 | ||||
3807 | /* Apply maximum likelihood detection for 2 stream case. */ | |||
3808 | run_bbp_read(sc, 105, &bbp); | |||
3809 | if (sc->nrxchains > 1) | |||
3810 | run_bbp_write(sc, 105, bbp | RT5390_MLD(1 << 2)); | |||
3811 | ||||
3812 | /* Avoid data lost and CRC error. */ | |||
3813 | run_bbp_read(sc, 4, &bbp); | |||
3814 | run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL(1 << 6)); | |||
3815 | ||||
3816 | if (sc->mac_ver == 0x5592) { | |||
3817 | for (i = 0; i < nitems(rt5592_def_bbp)(sizeof((rt5592_def_bbp)) / sizeof((rt5592_def_bbp)[0])); i++) { | |||
3818 | run_bbp_write(sc, rt5592_def_bbp[i].reg, | |||
3819 | rt5592_def_bbp[i].val); | |||
3820 | } | |||
3821 | for (i = 0; i < nitems(rt5592_bbp_r196)(sizeof((rt5592_bbp_r196)) / sizeof((rt5592_bbp_r196)[0])); i++) { | |||
3822 | run_bbp_write(sc, 195, i + 0x80); | |||
3823 | run_bbp_write(sc, 196, rt5592_bbp_r196[i]); | |||
3824 | } | |||
3825 | } else { | |||
3826 | for (i = 0; i < nitems(rt5390_def_bbp)(sizeof((rt5390_def_bbp)) / sizeof((rt5390_def_bbp)[0])); i++) { | |||
3827 | run_bbp_write(sc, rt5390_def_bbp[i].reg, | |||
3828 | rt5390_def_bbp[i].val); | |||
3829 | } | |||
3830 | } | |||
3831 | if (sc->mac_ver == 0x5392) { | |||
3832 | run_bbp_write(sc, 88, 0x90); | |||
3833 | run_bbp_write(sc, 95, 0x9a); | |||
3834 | run_bbp_write(sc, 98, 0x12); | |||
3835 | run_bbp_write(sc, 106, 0x12); | |||
3836 | run_bbp_write(sc, 134, 0xd0); | |||
3837 | run_bbp_write(sc, 135, 0xf6); | |||
3838 | run_bbp_write(sc, 148, 0x84); | |||
3839 | } | |||
3840 | ||||
3841 | run_bbp_read(sc, 152, &bbp); | |||
3842 | run_bbp_write(sc, 152, bbp | 0x80); | |||
3843 | ||||
3844 | /* Fix BBP254 for RT5592C. */ | |||
3845 | if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { | |||
3846 | run_bbp_read(sc, 254, &bbp); | |||
3847 | run_bbp_write(sc, 254, bbp | 0x80); | |||
3848 | } | |||
3849 | ||||
3850 | /* Disable hardware antenna diversity. */ | |||
3851 | if (sc->mac_ver == 0x5390) | |||
3852 | run_bbp_write(sc, 154, 0); | |||
3853 | ||||
3854 | /* Initialize Rx CCK/OFDM frequency offset report. */ | |||
3855 | run_bbp_write(sc, 142, 1); | |||
3856 | run_bbp_write(sc, 143, 57); | |||
3857 | } | |||
3858 | ||||
3859 | int | |||
3860 | run_bbp_init(struct run_softc *sc) | |||
3861 | { | |||
3862 | int i, error, ntries; | |||
3863 | uint8_t bbp0; | |||
3864 | ||||
3865 | /* wait for BBP to wake up */ | |||
3866 | for (ntries = 0; ntries < 20; ntries++) { | |||
3867 | if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) | |||
3868 | return error; | |||
3869 | if (bbp0 != 0 && bbp0 != 0xff) | |||
3870 | break; | |||
3871 | } | |||
3872 | if (ntries == 20) | |||
3873 | return ETIMEDOUT60; | |||
3874 | ||||
3875 | /* initialize BBP registers to default values */ | |||
3876 | if (sc->mac_ver >= 0x5390) | |||
3877 | run_rt5390_bbp_init(sc); | |||
3878 | else { | |||
3879 | for (i = 0; i < nitems(rt2860_def_bbp)(sizeof((rt2860_def_bbp)) / sizeof((rt2860_def_bbp)[0])); i++) { | |||
3880 | run_bbp_write(sc, rt2860_def_bbp[i].reg, | |||
3881 | rt2860_def_bbp[i].val); | |||
3882 | } | |||
3883 | } | |||
3884 | ||||
3885 | if (sc->mac_ver == 0x3593) { | |||
3886 | run_bbp_write(sc, 79, 0x13); | |||
3887 | run_bbp_write(sc, 80, 0x05); | |||
3888 | run_bbp_write(sc, 81, 0x33); | |||
3889 | run_bbp_write(sc, 86, 0x46); | |||
3890 | run_bbp_write(sc, 137, 0x0f); | |||
3891 | } | |||
3892 | ||||
3893 | /* fix BBP84 for RT2860E */ | |||
3894 | if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) | |||
3895 | run_bbp_write(sc, 84, 0x19); | |||
3896 | ||||
3897 | if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && | |||
3898 | sc->mac_ver != 0x5592)) { | |||
3899 | run_bbp_write(sc, 79, 0x13); | |||
3900 | run_bbp_write(sc, 80, 0x05); | |||
3901 | run_bbp_write(sc, 81, 0x33); | |||
3902 | } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { | |||
3903 | run_bbp_write(sc, 69, 0x16); | |||
3904 | run_bbp_write(sc, 73, 0x12); | |||
3905 | } | |||
3906 | return 0; | |||
3907 | } | |||
3908 | ||||
3909 | int | |||
3910 | run_rt3070_rf_init(struct run_softc *sc) | |||
3911 | { | |||
3912 | uint32_t tmp; | |||
3913 | uint8_t bbp4, mingain, rf, target; | |||
3914 | int i; | |||
3915 | ||||
3916 | run_rt3070_rf_read(sc, 30, &rf); | |||
3917 | /* toggle RF R30 bit 7 */ | |||
3918 | run_rt3070_rf_write(sc, 30, rf | 0x80); | |||
3919 | DELAY(1000)(*delay_func)(1000); | |||
3920 | run_rt3070_rf_write(sc, 30, rf & ~0x80); | |||
3921 | ||||
3922 | /* initialize RF registers to default value */ | |||
3923 | if (sc->mac_ver == 0x3572) { | |||
3924 | for (i = 0; i < nitems(rt3572_def_rf)(sizeof((rt3572_def_rf)) / sizeof((rt3572_def_rf)[0])); i++) { | |||
3925 | run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, | |||
3926 | rt3572_def_rf[i].val); | |||
3927 | } | |||
3928 | } else { | |||
3929 | for (i = 0; i < nitems(rt3070_def_rf)(sizeof((rt3070_def_rf)) / sizeof((rt3070_def_rf)[0])); i++) { | |||
3930 | run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, | |||
3931 | rt3070_def_rf[i].val); | |||
3932 | } | |||
3933 | } | |||
3934 | if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { | |||
3935 | /* | |||
3936 | * Change voltage from 1.2V to 1.35V for RT3070. | |||
3937 | * The DAC issue (RT3070_LDO_CFG0) has been fixed | |||
3938 | * in RT3070(F). | |||
3939 | */ | |||
3940 | run_read(sc, RT3070_LDO_CFG00x05d4, &tmp); | |||
3941 | tmp = (tmp & ~0x0f000000) | 0x0d000000; | |||
3942 | run_write(sc, RT3070_LDO_CFG00x05d4, tmp); | |||
3943 | ||||
3944 | } else if (sc->mac_ver == 0x3071) { | |||
3945 | run_rt3070_rf_read(sc, 6, &rf); | |||
3946 | run_rt3070_rf_write(sc, 6, rf | 0x40); | |||
3947 | run_rt3070_rf_write(sc, 31, 0x14); | |||
3948 | ||||
3949 | run_read(sc, RT3070_LDO_CFG00x05d4, &tmp); | |||
3950 | tmp &= ~0x1f000000; | |||
3951 | if (sc->mac_rev < 0x0211) | |||
3952 | tmp |= 0x0d000000; /* 1.35V */ | |||
3953 | else | |||
3954 | tmp |= 0x01000000; /* 1.2V */ | |||
3955 | run_write(sc, RT3070_LDO_CFG00x05d4, tmp); | |||
3956 | ||||
3957 | /* patch LNA_PE_G1 */ | |||
3958 | run_read(sc, RT3070_GPIO_SWITCH0x05dc, &tmp); | |||
3959 | run_write(sc, RT3070_GPIO_SWITCH0x05dc, tmp & ~0x20); | |||
3960 | ||||
3961 | } else if (sc->mac_ver == 0x3572) { | |||
3962 | run_rt3070_rf_read(sc, 6, &rf); | |||
3963 | run_rt3070_rf_write(sc, 6, rf | 0x40); | |||
3964 | /* increase voltage from 1.2V to 1.35V */ | |||
3965 | run_read(sc, RT3070_LDO_CFG00x05d4, &tmp); | |||
3966 | tmp = (tmp & ~0x1f000000) | 0x0d000000; | |||
3967 | run_write(sc, RT3070_LDO_CFG00x05d4, tmp); | |||
3968 | ||||
3969 | if (sc->mac_rev < 0x0211 || !sc->patch_dac) { | |||
3970 | DELAY(1)(*delay_func)(1); /* wait for 1msec */ | |||
3971 | /* decrease voltage back to 1.2V */ | |||
3972 | tmp = (tmp & ~0x1f000000) | 0x01000000; | |||
3973 | run_write(sc, RT3070_LDO_CFG00x05d4, tmp); | |||
3974 | } | |||
3975 | } | |||
3976 | ||||
3977 | /* select 20MHz bandwidth */ | |||
3978 | run_rt3070_rf_read(sc, 31, &rf); | |||
3979 | run_rt3070_rf_write(sc, 31, rf & ~0x20); | |||
3980 | ||||
3981 | /* calibrate filter for 20MHz bandwidth */ | |||
3982 | sc->rf24_20mhz = 0x1f; /* default value */ | |||
3983 | target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; | |||
3984 | run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); | |||
3985 | ||||
3986 | /* select 40MHz bandwidth */ | |||
3987 | run_bbp_read(sc, 4, &bbp4); | |||
3988 | run_bbp_write(sc, 4, (bbp4 & ~0x18) | 0x10); | |||
3989 | run_rt3070_rf_read(sc, 31, &rf); | |||
3990 | run_rt3070_rf_write(sc, 31, rf | 0x20); | |||
3991 | ||||
3992 | /* calibrate filter for 40MHz bandwidth */ | |||
3993 | sc->rf24_40mhz = 0x2f; /* default value */ | |||
3994 | target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; | |||
3995 | run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); | |||
3996 | ||||
3997 | /* go back to 20MHz bandwidth */ | |||
3998 | run_bbp_read(sc, 4, &bbp4); | |||
3999 | run_bbp_write(sc, 4, bbp4 & ~0x18); | |||
4000 | ||||
4001 | if (sc->mac_ver == 0x3572) { | |||
4002 | /* save default BBP registers 25 and 26 values */ | |||
4003 | run_bbp_read(sc, 25, &sc->bbp25); | |||
4004 | run_bbp_read(sc, 26, &sc->bbp26); | |||
4005 | ||||
4006 | } else if (sc->mac_rev < 0x0201 || sc->mac_rev < 0x0211) | |||
4007 | run_rt3070_rf_write(sc, 27, 0x03); | |||
4008 | ||||
4009 | run_read(sc, RT3070_OPT_140x0114, &tmp); | |||
4010 | run_write(sc, RT3070_OPT_140x0114, tmp | 1); | |||
4011 | ||||
4012 | if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { | |||
4013 | run_rt3070_rf_read(sc, 17, &rf); | |||
4014 | rf &= ~RT3070_TX_LO1(1 << 3); | |||
4015 | if ((sc->mac_ver == 0x3070 || | |||
4016 | (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && | |||
4017 | !sc->ext_2ghz_lna) | |||
4018 | rf |= 0x20; /* fix for long range Rx issue */ | |||
4019 | mingain = (sc->mac_ver == 0x3070) ? 1 : 2; | |||
4020 | if (sc->txmixgain_2ghz >= mingain) | |||
4021 | rf = (rf & ~0x7) | sc->txmixgain_2ghz; | |||
4022 | run_rt3070_rf_write(sc, 17, rf); | |||
4023 | } | |||
4024 | if (sc->mac_ver == 0x3071) { | |||
4025 | run_rt3070_rf_read(sc, 1, &rf); | |||
4026 | rf &= ~(RT3070_RX0_PD(1 << 2) | RT3070_TX0_PD(1 << 3)); | |||
4027 | rf |= RT3070_RF_BLOCK(1 << 0) | RT3070_RX1_PD(1 << 4) | RT3070_TX1_PD(1 << 5); | |||
4028 | run_rt3070_rf_write(sc, 1, rf); | |||
4029 | ||||
4030 | run_rt3070_rf_read(sc, 15, &rf); | |||
4031 | run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2(1 << 3)); | |||
4032 | ||||
4033 | run_rt3070_rf_read(sc, 20, &rf); | |||
4034 | run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1(1 << 3)); | |||
4035 | ||||
4036 | run_rt3070_rf_read(sc, 21, &rf); | |||
4037 | run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2(1 << 3)); | |||
4038 | } | |||
4039 | if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { | |||
4040 | /* fix Tx to Rx IQ glitch by raising RF voltage */ | |||
4041 | run_rt3070_rf_read(sc, 27, &rf); | |||
4042 | rf &= ~0x77; | |||
4043 | if (sc->mac_rev < 0x0211) | |||
4044 | rf |= 0x03; | |||
4045 | run_rt3070_rf_write(sc, 27, rf); | |||
4046 | } | |||
4047 | return 0; | |||
4048 | } | |||
4049 | ||||
4050 | void | |||
4051 | run_rt3593_rf_init(struct run_softc *sc) | |||
4052 | { | |||
4053 | uint32_t tmp; | |||
4054 | uint8_t rf; | |||
4055 | int i; | |||
4056 | ||||
4057 | /* Disable the GPIO bits 4 and 7 for LNA PE control. */ | |||
4058 | run_read(sc, RT3070_GPIO_SWITCH0x05dc, &tmp); | |||
4059 | tmp &= ~(1 << 4 | 1 << 7); | |||
4060 | run_write(sc, RT3070_GPIO_SWITCH0x05dc, tmp); | |||
4061 | ||||
4062 | /* Initialize RF registers to default value. */ | |||
4063 | for (i = 0; i < nitems(rt3593_def_rf)(sizeof((rt3593_def_rf)) / sizeof((rt3593_def_rf)[0])); i++) { | |||
4064 | run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, | |||
4065 | rt3593_def_rf[i].val); | |||
4066 | } | |||
4067 | ||||
4068 | /* Toggle RF R2 to initiate calibration. */ | |||
4069 | run_rt3070_rf_write(sc, 2, RT3593_RESCAL(1 << 7)); | |||
4070 | ||||
4071 | /* Initialize RF frequency offset. */ | |||
4072 | run_adjust_freq_offset(sc); | |||
4073 | ||||
4074 | run_rt3070_rf_read(sc, 18, &rf); | |||
4075 | run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS(1 << 6)); | |||
4076 | ||||
4077 | /* | |||
4078 | * Increase voltage from 1.2V to 1.35V, wait for 1 msec to | |||
4079 | * decrease voltage back to 1.2V. | |||
4080 | */ | |||
4081 | run_read(sc, RT3070_LDO_CFG00x05d4, &tmp); | |||
4082 | tmp = (tmp & ~0x1f000000) | 0x0d000000; | |||
4083 | run_write(sc, RT3070_LDO_CFG00x05d4, tmp); | |||
4084 | DELAY(1)(*delay_func)(1); | |||
4085 | tmp = (tmp & ~0x1f000000) | 0x01000000; | |||
4086 | run_write(sc, RT3070_LDO_CFG00x05d4, tmp); | |||
4087 | ||||
4088 | sc->rf24_20mhz = 0x1f; | |||
4089 | sc->rf24_40mhz = 0x2f; | |||
4090 | ||||
4091 | /* Save default BBP registers 25 and 26 values. */ | |||
4092 | run_bbp_read(sc, 25, &sc->bbp25); | |||
4093 | run_bbp_read(sc, 26, &sc->bbp26); | |||
4094 | ||||
4095 | run_read(sc, RT3070_OPT_140x0114, &tmp); | |||
4096 | run_write(sc, RT3070_OPT_140x0114, tmp | 1); | |||
4097 | } | |||
4098 | ||||
4099 | void | |||
4100 | run_rt5390_rf_init(struct run_softc *sc) | |||
4101 | { | |||
4102 | uint32_t tmp; | |||
4103 | uint8_t rf; | |||
4104 | int i; | |||
4105 | ||||
4106 | /* Toggle RF R2 to initiate calibration. */ | |||
4107 | if (sc->mac_ver == 0x5390) { | |||
4108 | run_rt3070_rf_read(sc, 2, &rf); | |||
4109 | run_rt3070_rf_write(sc, 2, rf | RT3593_RESCAL(1 << 7)); | |||
4110 | DELAY(10)(*delay_func)(10); | |||
4111 | run_rt3070_rf_write(sc, 2, rf & ~RT3593_RESCAL(1 << 7)); | |||
4112 | } else { | |||
4113 | run_rt3070_rf_write(sc, 2, RT3593_RESCAL(1 << 7)); | |||
4114 | DELAY(10)(*delay_func)(10); | |||
4115 | } | |||
4116 | ||||
4117 | /* Initialize RF registers to default value. */ | |||
4118 | if (sc->mac_ver == 0x5592) { | |||
4119 | for (i = 0; i < nitems(rt5592_def_rf)(sizeof((rt5592_def_rf)) / sizeof((rt5592_def_rf)[0])); i++) { | |||
4120 | run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, | |||
4121 | rt5592_def_rf[i].val); | |||
4122 | } | |||
4123 | /* Initialize RF frequency offset. */ | |||
4124 | run_adjust_freq_offset(sc); | |||
4125 | } else if (sc->mac_ver == 0x5392) { | |||
4126 | for (i = 0; i < nitems(rt5392_def_rf)(sizeof((rt5392_def_rf)) / sizeof((rt5392_def_rf)[0])); i++) { | |||
4127 | run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, | |||
4128 | rt5392_def_rf[i].val); | |||
4129 | } | |||
4130 | if (sc->mac_rev >= 0x0223) { | |||
4131 | run_rt3070_rf_write(sc, 23, 0x0f); | |||
4132 | run_rt3070_rf_write(sc, 24, 0x3e); | |||
4133 | run_rt3070_rf_write(sc, 51, 0x32); | |||
4134 | run_rt3070_rf_write(sc, 53, 0x22); | |||
4135 | run_rt3070_rf_write(sc, 56, 0xc1); | |||
4136 | run_rt3070_rf_write(sc, 59, 0x0f); | |||
4137 | } | |||
4138 | } else { | |||
4139 | for (i = 0; i < nitems(rt5390_def_rf)(sizeof((rt5390_def_rf)) / sizeof((rt5390_def_rf)[0])); i++) { | |||
4140 | run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, | |||
4141 | rt5390_def_rf[i].val); | |||
4142 | } | |||
4143 | if (sc->mac_rev >= 0x0502) { | |||
4144 | run_rt3070_rf_write(sc, 6, 0xe0); | |||
4145 | run_rt3070_rf_write(sc, 25, 0x80); | |||
4146 | run_rt3070_rf_write(sc, 46, 0x73); | |||
4147 | run_rt3070_rf_write(sc, 53, 0x00); | |||
4148 | run_rt3070_rf_write(sc, 56, 0x42); | |||
4149 | run_rt3070_rf_write(sc, 61, 0xd1); | |||
4150 | } | |||
4151 | } | |||
4152 | ||||
4153 | sc->rf24_20mhz = 0x1f; /* default value */ | |||
4154 | sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; | |||
4155 | ||||
4156 | if (sc->mac_rev < 0x0211) | |||
4157 | run_rt3070_rf_write(sc, 27, 0x3); | |||
4158 | ||||
4159 | run_read(sc, RT3070_OPT_140x0114, &tmp); | |||
4160 | run_write(sc, RT3070_OPT_140x0114, tmp | 1); | |||
4161 | } | |||
4162 | ||||
4163 | int | |||
4164 | run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, | |||
4165 | uint8_t *val) | |||
4166 | { | |||
4167 | uint8_t rf22, rf24; | |||
4168 | uint8_t bbp55_pb, bbp55_sb, delta; | |||
4169 | int ntries; | |||
4170 | ||||
4171 | /* program filter */ | |||
4172 | run_rt3070_rf_read(sc, 24, &rf24); | |||
4173 | rf24 = (rf24 & 0xc0) | init; /* initial filter value */ | |||
4174 | run_rt3070_rf_write(sc, 24, rf24); | |||
4175 | ||||
4176 | /* enable baseband loopback mode */ | |||
4177 | run_rt3070_rf_read(sc, 22, &rf22); | |||
4178 | run_rt3070_rf_write(sc, 22, rf22 | 0x01); | |||
4179 | ||||
4180 | /* set power and frequency of passband test tone */ | |||
4181 | run_bbp_write(sc, 24, 0x00); | |||
4182 | for (ntries = 0; ntries < 100; ntries++) { | |||
4183 | /* transmit test tone */ | |||
4184 | run_bbp_write(sc, 25, 0x90); | |||
4185 | DELAY(1000)(*delay_func)(1000); | |||
4186 | /* read received power */ | |||
4187 | run_bbp_read(sc, 55, &bbp55_pb); | |||
4188 | if (bbp55_pb != 0) | |||
4189 | break; | |||
4190 | } | |||
4191 | if (ntries == 100) | |||
4192 | return ETIMEDOUT60; | |||
4193 | ||||
4194 | /* set power and frequency of stopband test tone */ | |||
4195 | run_bbp_write(sc, 24, 0x06); | |||
4196 | for (ntries = 0; ntries < 100; ntries++) { | |||
4197 | /* transmit test tone */ | |||
4198 | run_bbp_write(sc, 25, 0x90); | |||
4199 | DELAY(1000)(*delay_func)(1000); | |||
4200 | /* read received power */ | |||
4201 | run_bbp_read(sc, 55, &bbp55_sb); | |||
4202 | ||||
4203 | delta = bbp55_pb - bbp55_sb; | |||
4204 | if (delta > target) | |||
4205 | break; | |||
4206 | ||||
4207 | /* reprogram filter */ | |||
4208 | rf24++; | |||
4209 | run_rt3070_rf_write(sc, 24, rf24); | |||
4210 | } | |||
4211 | if (ntries < 100) { | |||
4212 | if (rf24 != init) | |||
4213 | rf24--; /* backtrack */ | |||
4214 | *val = rf24; | |||
4215 | run_rt3070_rf_write(sc, 24, rf24); | |||
4216 | } | |||
4217 | ||||
4218 | /* restore initial state */ | |||
4219 | run_bbp_write(sc, 24, 0x00); | |||
4220 | ||||
4221 | /* disable baseband loopback mode */ | |||
4222 | run_rt3070_rf_read(sc, 22, &rf22); | |||
4223 | run_rt3070_rf_write(sc, 22, rf22 & ~0x01); | |||
4224 | ||||
4225 | return 0; | |||
4226 | } | |||
4227 | ||||
4228 | void | |||
4229 | run_rt3070_rf_setup(struct run_softc *sc) | |||
4230 | { | |||
4231 | uint8_t bbp, rf; | |||
4232 | int i; | |||
4233 | ||||
4234 | if (sc->mac_ver == 0x3572) { | |||
4235 | /* enable DC filter */ | |||
4236 | if (sc->mac_rev >= 0x0201) | |||
4237 | run_bbp_write(sc, 103, 0xc0); | |||
4238 | ||||
4239 | run_bbp_read(sc, 138, &bbp); | |||
4240 | if (sc->ntxchains == 1) | |||
4241 | bbp |= 0x20; /* turn off DAC1 */ | |||
4242 | if (sc->nrxchains == 1) | |||
4243 | bbp &= ~0x02; /* turn off ADC1 */ | |||
4244 | run_bbp_write(sc, 138, bbp); | |||
4245 | ||||
4246 | if (sc->mac_rev >= 0x0211) { | |||
4247 | /* improve power consumption */ | |||
4248 | run_bbp_read(sc, 31, &bbp); | |||
4249 | run_bbp_write(sc, 31, bbp & ~0x03); | |||
4250 | } | |||
4251 | ||||
4252 | run_rt3070_rf_read(sc, 16, &rf); | |||
4253 | rf = (rf & ~0x07) | sc->txmixgain_2ghz; | |||
4254 | run_rt3070_rf_write(sc, 16, rf); | |||
4255 | ||||
4256 | } else if (sc->mac_ver == 0x3071) { | |||
4257 | /* enable DC filter */ | |||
4258 | if (sc->mac_rev >= 0x0211) { | |||
4259 | run_bbp_write(sc, 103, 0xc0); | |||
4260 | ||||
4261 | /* improve power consumption */ | |||
4262 | run_bbp_read(sc, 31, &bbp); | |||
4263 | run_bbp_write(sc, 31, bbp & ~0x03); | |||
4264 | } | |||
4265 | ||||
4266 | run_bbp_read(sc, 138, &bbp); | |||
4267 | if (sc->ntxchains == 1) | |||
4268 | bbp |= 0x20; /* turn off DAC1 */ | |||
4269 | if (sc->nrxchains == 1) | |||
4270 | bbp &= ~0x02; /* turn off ADC1 */ | |||
4271 | run_bbp_write(sc, 138, bbp); | |||
4272 | ||||
4273 | run_write(sc, RT2860_TX_SW_CFG10x1334, 0); | |||
4274 | if (sc->mac_rev < 0x0211) { | |||
4275 | run_write(sc, RT2860_TX_SW_CFG20x1338, | |||
4276 | sc->patch_dac ? 0x2c : 0x0f); | |||
4277 | } else | |||
4278 | run_write(sc, RT2860_TX_SW_CFG20x1338, 0); | |||
4279 | ||||
4280 | } else if (sc->mac_ver == 0x3070) { | |||
4281 | if (sc->mac_rev >= 0x0201) { | |||
4282 | /* enable DC filter */ | |||
4283 | run_bbp_write(sc, 103, 0xc0); | |||
4284 | ||||
4285 | /* improve power consumption */ | |||
4286 | run_bbp_read(sc, 31, &bbp); | |||
4287 | run_bbp_write(sc, 31, bbp & ~0x03); | |||
4288 | } | |||
4289 | ||||
4290 | if (sc->mac_rev < 0x0201) { | |||
4291 | run_write(sc, RT2860_TX_SW_CFG10x1334, 0); | |||
4292 | run_write(sc, RT2860_TX_SW_CFG20x1338, 0x2c); | |||
4293 | } else | |||
4294 | run_write(sc, RT2860_TX_SW_CFG20x1338, 0); | |||
4295 | } | |||
4296 | ||||
4297 | /* initialize RF registers from ROM for >=RT3071*/ | |||
4298 | if (sc->mac_ver >= 0x3071) { | |||
4299 | for (i = 0; i < 10; i++) { | |||
4300 | if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) | |||
4301 | continue; | |||
4302 | run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); | |||
4303 | } | |||
4304 | } | |||
4305 | } | |||
4306 | ||||
4307 | void | |||
4308 | run_rt3593_rf_setup(struct run_softc *sc) | |||
4309 | { | |||
4310 | uint8_t bbp, rf; | |||
4311 | ||||
4312 | if (sc->mac_rev >= 0x0211) { | |||
4313 | /* Enable DC filter. */ | |||
4314 | run_bbp_write(sc, 103, 0xc0); | |||
4315 | } | |||
4316 | run_write(sc, RT2860_TX_SW_CFG10x1334, 0); | |||
4317 | if (sc->mac_rev < 0x0211) { | |||
4318 | run_write(sc, RT2860_TX_SW_CFG20x1338, | |||
4319 | sc->patch_dac ? 0x2c : 0x0f); | |||
4320 | } else | |||
4321 | run_write(sc, RT2860_TX_SW_CFG20x1338, 0); | |||
4322 | ||||
4323 | run_rt3070_rf_read(sc, 50, &rf); | |||
4324 | run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2(1 << 4)); | |||
4325 | ||||
4326 | run_rt3070_rf_read(sc, 51, &rf); | |||
4327 | rf = (rf & ~(RT3593_TX_LO1(1 << 4) | 0x0c)) | | |||
4328 | ((sc->txmixgain_2ghz & 0x07) << 2); | |||
4329 | run_rt3070_rf_write(sc, 51, rf); | |||
4330 | ||||
4331 | run_rt3070_rf_read(sc, 38, &rf); | |||
4332 | run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1(1 << 5)); | |||
4333 | ||||
4334 | run_rt3070_rf_read(sc, 39, &rf); | |||
4335 | run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2(1 << 7)); | |||
4336 | ||||
4337 | run_rt3070_rf_read(sc, 1, &rf); | |||
4338 | run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1))); | |||
4339 | ||||
4340 | run_rt3070_rf_read(sc, 30, &rf); | |||
4341 | rf = (rf & ~0x18) | 0x10; | |||
4342 | run_rt3070_rf_write(sc, 30, rf); | |||
4343 | ||||
4344 | /* Apply maximum likelihood detection for 2 stream case. */ | |||
4345 | run_bbp_read(sc, 105, &bbp); | |||
4346 | if (sc->nrxchains > 1) | |||
4347 | run_bbp_write(sc, 105, bbp | RT5390_MLD(1 << 2)); | |||
4348 | ||||
4349 | /* Avoid data lost and CRC error. */ | |||
4350 | run_bbp_read(sc, 4, &bbp); | |||
4351 | run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL(1 << 6)); | |||
4352 | ||||
4353 | run_bbp_write(sc, 92, 0x02); | |||
4354 | run_bbp_write(sc, 82, 0x82); | |||
4355 | run_bbp_write(sc, 106, 0x05); | |||
4356 | run_bbp_write(sc, 104, 0x92); | |||
4357 | run_bbp_write(sc, 88, 0x90); | |||
4358 | run_bbp_write(sc, 148, 0xc8); | |||
4359 | run_bbp_write(sc, 47, 0x48); | |||
4360 | run_bbp_write(sc, 120, 0x50); | |||
4361 | ||||
4362 | run_bbp_write(sc, 163, 0x9d); | |||
4363 | ||||
4364 | /* SNR mapping. */ | |||
4365 | run_bbp_write(sc, 142, 0x06); | |||
4366 | run_bbp_write(sc, 143, 0xa0); | |||
4367 | run_bbp_write(sc, 142, 0x07); | |||
4368 | run_bbp_write(sc, 143, 0xa1); | |||
4369 | run_bbp_write(sc, 142, 0x08); | |||
4370 | run_bbp_write(sc, 143, 0xa2); | |||
4371 | ||||
4372 | run_bbp_write(sc, 31, 0x08); | |||
4373 | run_bbp_write(sc, 68, 0x0b); | |||
4374 | run_bbp_write(sc, 105, 0x04); | |||
4375 | } | |||
4376 | ||||
4377 | void | |||
4378 | run_rt5390_rf_setup(struct run_softc *sc) | |||
4379 | { | |||
4380 | uint8_t bbp, rf; | |||
4381 | ||||
4382 | if (sc->mac_rev >= 0x0211) { | |||
4383 | /* Enable DC filter. */ | |||
4384 | run_bbp_write(sc, 103, 0xc0); | |||
4385 | ||||
4386 | if (sc->mac_ver != 0x5592) { | |||
4387 | /* Improve power consumption. */ | |||
4388 | run_bbp_read(sc, 31, &bbp); | |||
4389 | run_bbp_write(sc, 31, bbp & ~0x03); | |||
4390 | } | |||
4391 | } | |||
4392 | ||||
4393 | run_bbp_read(sc, 138, &bbp); | |||
4394 | if (sc->ntxchains == 1) | |||
4395 | bbp |= 0x20; /* turn off DAC1 */ | |||
4396 | if (sc->nrxchains == 1) | |||
4397 | bbp &= ~0x02; /* turn off ADC1 */ | |||
4398 | run_bbp_write(sc, 138, bbp); | |||
4399 | ||||
4400 | run_rt3070_rf_read(sc, 38, &rf); | |||
4401 | run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1(1 << 5)); | |||
4402 | ||||
4403 | run_rt3070_rf_read(sc, 39, &rf); | |||
4404 | run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2(1 << 7)); | |||
4405 | ||||
4406 | /* Avoid data lost and CRC error. */ | |||
4407 | run_bbp_read(sc, 4, &bbp); | |||
4408 | run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL(1 << 6)); | |||
4409 | ||||
4410 | run_rt3070_rf_read(sc, 30, &rf); | |||
4411 | rf = (rf & ~0x18) | 0x10; | |||
4412 | run_rt3070_rf_write(sc, 30, rf); | |||
4413 | ||||
4414 | if (sc->mac_ver != 0x5592) { | |||
4415 | run_write(sc, RT2860_TX_SW_CFG10x1334, 0); | |||
4416 | if (sc->mac_rev < 0x0211) { | |||
4417 | run_write(sc, RT2860_TX_SW_CFG20x1338, | |||
4418 | sc->patch_dac ? 0x2c : 0x0f); | |||
4419 | } else | |||
4420 | run_write(sc, RT2860_TX_SW_CFG20x1338, 0); | |||
4421 | } | |||
4422 | } | |||
4423 | ||||
4424 | int | |||
4425 | run_txrx_enable(struct run_softc *sc) | |||
4426 | { | |||
4427 | uint32_t tmp; | |||
4428 | int error, ntries; | |||
4429 | ||||
4430 | run_write(sc, RT2860_MAC_SYS_CTRL0x1004, RT2860_MAC_TX_EN(1 << 2)); | |||
4431 | for (ntries = 0; ntries < 200; ntries++) { | |||
4432 | if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG0x0208, &tmp)) != 0) | |||
4433 | return error; | |||
4434 | if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0) | |||
4435 | break; | |||
4436 | DELAY(1000)(*delay_func)(1000); | |||
4437 | } | |||
4438 | if (ntries == 200) | |||
4439 | return ETIMEDOUT60; | |||
4440 | ||||
4441 | DELAY(50)(*delay_func)(50); | |||
4442 | ||||
4443 | tmp |= RT2860_RX_DMA_EN(1 << 2) | RT2860_TX_DMA_EN(1 << 0) | RT2860_TX_WB_DDONE(1 << 6); | |||
4444 | run_write(sc, RT2860_WPDMA_GLO_CFG0x0208, tmp); | |||
4445 | ||||
4446 | /* enable Rx bulk aggregation (set timeout and limit) */ | |||
4447 | tmp = RT2860_USB_TX_EN(1U << 23) | RT2860_USB_RX_EN(1U << 22) | RT2860_USB_RX_AGG_EN(1U << 21) | | |||
4448 | RT2860_USB_RX_AGG_TO(128)((128) & 0xff) | RT2860_USB_RX_AGG_LMT(2)((2) << 8); | |||
4449 | run_write(sc, RT2860_USB_DMA_CFG0x02a0, tmp); | |||
4450 | ||||
4451 | /* set Rx filter */ | |||
4452 | tmp = RT2860_DROP_CRC_ERR(1 << 0) | RT2860_DROP_PHY_ERR(1 << 1); | |||
4453 | if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { | |||
4454 | tmp |= RT2860_DROP_UC_NOME(1 << 2) | RT2860_DROP_DUPL(1 << 7) | | |||
4455 | RT2860_DROP_CTS(1 << 11) | RT2860_DROP_BA(1 << 14) | RT2860_DROP_ACK(1 << 10) | | |||
4456 | RT2860_DROP_VER_ERR(1 << 4) | RT2860_DROP_CTRL_RSV(1 << 16) | | |||
4457 | RT2860_DROP_CFACK(1 << 8) | RT2860_DROP_CFEND(1 << 9); | |||
4458 | if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) | |||
4459 | tmp |= RT2860_DROP_RTS(1 << 12) | RT2860_DROP_PSPOLL(1 << 13); | |||
4460 | } | |||
4461 | run_write(sc, RT2860_RX_FILTR_CFG0x1400, tmp); | |||
4462 | ||||
4463 | run_write(sc, RT2860_MAC_SYS_CTRL0x1004, | |||
4464 | RT2860_MAC_RX_EN(1 << 3) | RT2860_MAC_TX_EN(1 << 2)); | |||
4465 | ||||
4466 | return 0; | |||
4467 | } | |||
4468 | ||||
4469 | void | |||
4470 | run_adjust_freq_offset(struct run_softc *sc) | |||
4471 | { | |||
4472 | uint8_t rf, tmp; | |||
4473 | ||||
4474 | run_rt3070_rf_read(sc, 17, &rf); | |||
4475 | tmp = rf; | |||
| ||||
4476 | rf = (rf & ~0x7f) | (sc->freq & 0x7f); | |||
4477 | rf = MIN(rf, 0x5f)(((rf)<(0x5f))?(rf):(0x5f)); | |||
4478 | ||||
4479 | if (tmp != rf) | |||
4480 | run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); | |||
4481 | } | |||
4482 | ||||
4483 | int | |||
4484 | run_init(struct ifnet *ifp) | |||
4485 | { | |||
4486 | struct run_softc *sc = ifp->if_softc; | |||
4487 | struct ieee80211com *ic = &sc->sc_ic; | |||
4488 | uint32_t tmp; | |||
4489 | uint8_t bbp1, bbp3; | |||
4490 | int i, error, qid, ridx, ntries; | |||
4491 | ||||
4492 | if (usbd_is_dying(sc->sc_udev)) | |||
4493 | return ENXIO6; | |||
4494 | ||||
4495 | for (ntries = 0; ntries < 100; ntries++) { | |||
4496 | if ((error = run_read(sc, RT2860_ASIC_VER_ID0x1000, &tmp)) != 0) | |||
4497 | goto fail; | |||
4498 | if (tmp != 0 && tmp != 0xffffffff) | |||
4499 | break; | |||
4500 | DELAY(10)(*delay_func)(10); | |||
4501 | } | |||
4502 | if (ntries == 100) { | |||
4503 | error = ETIMEDOUT60; | |||
4504 | goto fail; | |||
4505 | } | |||
4506 | ||||
4507 | if ((error = run_load_microcode(sc)) != 0) { | |||
4508 | printf("%s: could not load 8051 microcode\n", | |||
4509 | sc->sc_dev.dv_xname); | |||
4510 | goto fail; | |||
4511 | } | |||
4512 | ||||
4513 | /* init host command ring */ | |||
4514 | sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; | |||
4515 | ||||
4516 | /* init Tx rings (4 EDCAs) */ | |||
4517 | for (qid = 0; qid < 4; qid++) { | |||
4518 | if ((error = run_alloc_tx_ring(sc, qid)) != 0) | |||
4519 | goto fail; | |||
4520 | } | |||
4521 | /* init Rx ring */ | |||
4522 | if ((error = run_alloc_rx_ring(sc)) != 0) | |||
4523 | goto fail; | |||
4524 | ||||
4525 | IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl))__builtin_memcpy((ic->ic_myaddr), (((caddr_t)((ifp->if_sadl )->sdl_data + (ifp->if_sadl)->sdl_nlen))), (6)); | |||
4526 | run_set_macaddr(sc, ic->ic_myaddr); | |||
4527 | ||||
4528 | for (ntries = 0; ntries < 100; ntries++) { | |||
4529 | if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG0x0208, &tmp)) != 0) | |||
4530 | goto fail; | |||
4531 | if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0) | |||
4532 | break; | |||
4533 | DELAY(1000)(*delay_func)(1000); | |||
4534 | } | |||
4535 | if (ntries == 100) { | |||
4536 | printf("%s: timeout waiting for DMA engine\n", | |||
4537 | sc->sc_dev.dv_xname); | |||
4538 | error = ETIMEDOUT60; | |||
4539 | goto fail; | |||
4540 | } | |||
4541 | tmp &= 0xff0; | |||
4542 | tmp |= RT2860_TX_WB_DDONE(1 << 6); | |||
4543 | run_write(sc, RT2860_WPDMA_GLO_CFG0x0208, tmp); | |||
4544 | ||||
4545 | /* turn off PME_OEN to solve high-current issue */ | |||
4546 | run_read(sc, RT2860_SYS_CTRL0x0400, &tmp); | |||
4547 | run_write(sc, RT2860_SYS_CTRL0x0400, tmp & ~RT2860_PME_OEN(1 << 13)); | |||
4548 | ||||
4549 | run_write(sc, RT2860_MAC_SYS_CTRL0x1004, | |||
4550 | RT2860_BBP_HRST(1 << 1) | RT2860_MAC_SRST(1 << 0)); | |||
4551 | run_write(sc, RT2860_USB_DMA_CFG0x02a0, 0); | |||
4552 | ||||
4553 | if ((error = run_reset(sc)) != 0) { | |||
4554 | printf("%s: could not reset chipset\n", sc->sc_dev.dv_xname); | |||
4555 | goto fail; | |||
4556 | } | |||
4557 | ||||
4558 | run_write(sc, RT2860_MAC_SYS_CTRL0x1004, 0); | |||
4559 | ||||
4560 | /* init Tx power for all Tx rates (from EEPROM) */ | |||
4561 | for (ridx = 0; ridx < 5; ridx++) { | |||
4562 | if (sc->txpow20mhz[ridx] == 0xffffffff) | |||
4563 | continue; | |||
4564 | run_write(sc, RT2860_TX_PWR_CFG(ridx)(0x1314 + (ridx) * 4), sc->txpow20mhz[ridx]); | |||
4565 | } | |||
4566 | ||||
4567 | for (i = 0; i < nitems(rt2870_def_mac)(sizeof((rt2870_def_mac)) / sizeof((rt2870_def_mac)[0])); i++) | |||
4568 | run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); | |||
4569 | run_write(sc, RT2860_WMM_AIFSN_CFG0x0214, 0x00002273); | |||
4570 | run_write(sc, RT2860_WMM_CWMIN_CFG0x0218, 0x00002344); | |||
4571 | run_write(sc, RT2860_WMM_CWMAX_CFG0x021c, 0x000034aa); | |||
4572 | ||||
4573 | if (sc->mac_ver >= 0x5390) { | |||
4574 | run_write(sc, RT2860_TX_SW_CFG00x1330, | |||
4575 | 4 << RT2860_DLY_PAPE_EN_SHIFT8 | 4); | |||
4576 | if (sc->mac_ver >= 0x5392) { | |||
4577 | run_write(sc, RT2860_MAX_LEN_CFG0x1018, 0x00002fff); | |||
4578 | if (sc->mac_ver == 0x5592) { | |||
4579 | run_write(sc, RT2860_HT_FBK_CFG10x1358, 0xedcba980); | |||
4580 | run_write(sc, RT2860_TXOP_HLDR_ET0x1608, 0x00000082); | |||
4581 | } else { | |||
4582 | run_write(sc, RT2860_HT_FBK_CFG10x1358, 0xedcb4980); | |||
4583 | run_write(sc, RT2860_LG_FBK_CFG00x135c, 0xedcba322); | |||
4584 | } | |||
4585 | } | |||
4586 | } else if (sc->mac_ver == 0x3593) { | |||
4587 | run_write(sc, RT2860_TX_SW_CFG00x1330, | |||
4588 | 4 << RT2860_DLY_PAPE_EN_SHIFT8 | 2); | |||
4589 | } else if (sc->mac_ver >= 0x3070) { | |||
4590 | /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ | |||
4591 | run_write(sc, RT2860_TX_SW_CFG00x1330, | |||
4592 | 4 << RT2860_DLY_PAPE_EN_SHIFT8); | |||
4593 | } | |||
4594 | ||||
4595 | /* wait while MAC is busy */ | |||
4596 | for (ntries = 0; ntries < 100; ntries++) { | |||
4597 | if ((error = run_read(sc, RT2860_MAC_STATUS_REG0x1200, &tmp)) != 0) | |||
4598 | goto fail; | |||
4599 | if (!(tmp & (RT2860_RX_STATUS_BUSY(1 << 1) | RT2860_TX_STATUS_BUSY(1 << 0)))) | |||
4600 | break; | |||
4601 | DELAY(1000)(*delay_func)(1000); | |||
4602 | } | |||
4603 | if (ntries == 100) { | |||
4604 | error = ETIMEDOUT60; | |||
4605 | goto fail; | |||
4606 | } | |||
4607 | ||||
4608 | /* clear Host to MCU mailbox */ | |||
4609 | run_write(sc, RT2860_H2M_BBPAGENT0x7028, 0); | |||
4610 | run_write(sc, RT2860_H2M_MAILBOX0x7010, 0); | |||
4611 | DELAY(1000)(*delay_func)(1000); | |||
4612 | ||||
4613 | if ((error = run_bbp_init(sc)) != 0) { | |||
4614 | printf("%s: could not initialize BBP\n", sc->sc_dev.dv_xname); | |||
4615 | goto fail; | |||
4616 | } | |||
4617 | ||||
4618 | /* abort TSF synchronization */ | |||
4619 | run_read(sc, RT2860_BCN_TIME_CFG0x1114, &tmp); | |||
4620 | tmp &= ~(RT2860_BCN_TX_EN(1 << 20) | RT2860_TSF_TIMER_EN(1 << 16) | | |||
4621 | RT2860_TBTT_TIMER_EN(1 << 19)); | |||
4622 | run_write(sc, RT2860_BCN_TIME_CFG0x1114, tmp); | |||
4623 | ||||
4624 | /* clear RX WCID search table */ | |||
4625 | run_set_region_4(sc, RT2860_WCID_ENTRY(0)(0x1800 + (0) * 8), 0, 512); | |||
4626 | /* clear WCID attribute table */ | |||
4627 | run_set_region_4(sc, RT2860_WCID_ATTR(0)(0x6800 + (0) * 4), 0, 8 * 32); | |||
4628 | /* clear shared key table */ | |||
4629 | run_set_region_4(sc, RT2860_SKEY(0, 0)(0x6c00 + (0) * 128 + (0) * 32), 0, 8 * 32); | |||
4630 | /* clear shared key mode */ | |||
4631 | run_set_region_4(sc, RT2860_SKEY_MODE_0_70x7000, 0, 4); | |||
4632 | ||||
4633 | run_read(sc, RT2860_US_CYC_CNT0x02a4, &tmp); | |||
4634 | tmp = (tmp & ~0xff) | 0x1e; | |||
4635 | run_write(sc, RT2860_US_CYC_CNT0x02a4, tmp); | |||
4636 | ||||
4637 | if (sc->mac_rev != 0x0101) | |||
4638 | run_write(sc, RT2860_TXOP_CTRL_CFG0x1340, 0x0000583f); | |||
4639 | ||||
4640 | run_write(sc, RT2860_WMM_TXOP0_CFG0x0220, 0); | |||
4641 | run_write(sc, RT2860_WMM_TXOP1_CFG0x0224, 48 << 16 | 96); | |||
4642 | ||||
4643 | /* write vendor-specific BBP values (from EEPROM) */ | |||
4644 | if (sc->mac_ver < 0x3593) { | |||
4645 | for (i = 0; i < 8; i++) { | |||
4646 | if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) | |||
4647 | continue; | |||
4648 | run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); | |||
4649 | } | |||
4650 | } | |||
4651 | ||||
4652 | /* select Main antenna for 1T1R devices */ | |||
4653 | if (sc->rf_rev == RT3070_RF_30200x0005 || sc->rf_rev == RT5390_RF_53700x5370) | |||
4654 | run_set_rx_antenna(sc, 0); | |||
4655 | ||||
4656 | /* send LEDs operating mode to microcontroller */ | |||
4657 | (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED10x52, sc->led[0]); | |||
4658 | (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED20x53, sc->led[1]); | |||
4659 | (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED30x54, sc->led[2]); | |||
4660 | ||||
4661 | if (sc->mac_ver >= 0x5390) | |||
4662 | run_rt5390_rf_init(sc); | |||
4663 | else if (sc->mac_ver == 0x3593) | |||
4664 | run_rt3593_rf_init(sc); | |||
4665 | else if (sc->mac_ver >= 0x3070) | |||
4666 | run_rt3070_rf_init(sc); | |||
4667 | ||||
4668 | /* disable non-existing Rx chains */ | |||
4669 | run_bbp_read(sc, 3, &bbp3); | |||
4670 | bbp3 &= ~(1 << 3 | 1 << 4); | |||
4671 | if (sc->nrxchains == 2) | |||
4672 | bbp3 |= 1 << 3; | |||
4673 | else if (sc->nrxchains == 3) | |||
4674 | bbp3 |= 1 << 4; | |||
4675 | run_bbp_write(sc, 3, bbp3); | |||
4676 | ||||
4677 | /* disable non-existing Tx chains */ | |||
4678 | run_bbp_read(sc, 1, &bbp1); | |||
4679 | if (sc->ntxchains == 1) | |||
4680 | bbp1 &= ~(1 << 3 | 1 << 4); | |||
4681 | run_bbp_write(sc, 1, bbp1); | |||
4682 | ||||
4683 | if (sc->mac_ver >= 0x5390) | |||
4684 | run_rt5390_rf_setup(sc); | |||
4685 | else if (sc->mac_ver == 0x3593) | |||
4686 | run_rt3593_rf_setup(sc); | |||
4687 | else if (sc->mac_ver >= 0x3070) | |||
4688 | run_rt3070_rf_setup(sc); | |||
4689 | ||||
4690 | /* select default channel */ | |||
4691 | ic->ic_bss->ni_chan = ic->ic_ibss_chan; | |||
4692 | run_set_chan(sc, ic->ic_ibss_chan); | |||
4693 | ||||
4694 | /* turn radio LED on */ | |||
4695 | run_set_leds(sc, RT2860_LED_RADIO(1 << 13)); | |||
4696 | ||||
4697 | for (i = 0; i < RUN_RX_RING_COUNT1; i++) { | |||
4698 | struct run_rx_data *data = &sc->rxq.data[i]; | |||
4699 | ||||
4700 | usbd_setup_xfer(data->xfer, sc->rxq.pipeh, data, data->buf, | |||
4701 | RUN_MAX_RXSZ4096, USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01, | |||
4702 | USBD_NO_TIMEOUT0, run_rxeof); | |||
4703 | error = usbd_transfer(data->xfer); | |||
4704 | if (error != 0 && error != USBD_IN_PROGRESS) | |||
4705 | goto fail; | |||
4706 | } | |||
4707 | ||||
4708 | if ((error = run_txrx_enable(sc)) != 0) | |||
4709 | goto fail; | |||
4710 | ||||
4711 | ifp->if_flags |= IFF_RUNNING0x40; | |||
4712 | ifq_clr_oactive(&ifp->if_snd); | |||
4713 | ||||
4714 | if (ic->ic_flags & IEEE80211_F_WEPON0x00000100) { | |||
4715 | /* install WEP keys */ | |||
4716 | for (i = 0; i < IEEE80211_WEP_NKID4; i++) { | |||
4717 | if (ic->ic_nw_keys[i].k_cipher != IEEE80211_CIPHER_NONE) | |||
4718 | (void)run_set_key(ic, NULL((void *)0), &ic->ic_nw_keys[i]); | |||
4719 | } | |||
4720 | } | |||
4721 | ||||
4722 | if (ic->ic_opmode == IEEE80211_M_MONITOR) | |||
4723 | ieee80211_new_state(ic, IEEE80211_S_RUN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_RUN), (-1))); | |||
4724 | else | |||
4725 | ieee80211_new_state(ic, IEEE80211_S_SCAN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_SCAN), (-1))); | |||
4726 | ||||
4727 | if (error != 0) | |||
4728 | fail: run_stop(ifp, 1); | |||
4729 | return error; | |||
4730 | } | |||
4731 | ||||
4732 | void | |||
4733 | run_stop(struct ifnet *ifp, int disable) | |||
4734 | { | |||
4735 | struct run_softc *sc = ifp->if_softc; | |||
4736 | struct ieee80211com *ic = &sc->sc_ic; | |||
4737 | uint32_t tmp; | |||
4738 | int s, ntries, qid; | |||
4739 | ||||
4740 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
4741 | run_set_leds(sc, 0); /* turn all LEDs off */ | |||
4742 | ||||
4743 | sc->sc_tx_timer = 0; | |||
4744 | ifp->if_timer = 0; | |||
4745 | ifp->if_flags &= ~IFF_RUNNING0x40; | |||
4746 | ifq_clr_oactive(&ifp->if_snd); | |||
4747 | ||||
4748 | timeout_del(&sc->scan_to); | |||
4749 | timeout_del(&sc->calib_to); | |||
4750 | ||||
4751 | s = splusb()splraise(0x2); | |||
4752 | ieee80211_new_state(ic, IEEE80211_S_INIT, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_INIT), (-1))); | |||
4753 | /* wait for all queued asynchronous commands to complete */ | |||
4754 | usb_wait_task(sc->sc_udev, &sc->sc_task); | |||
4755 | splx(s)spllower(s); | |||
4756 | ||||
4757 | /* Disable Tx/Rx DMA. */ | |||
4758 | run_read(sc, RT2860_WPDMA_GLO_CFG0x0208, &tmp); | |||
4759 | tmp &= ~(RT2860_RX_DMA_EN(1 << 2) | RT2860_TX_DMA_EN(1 << 0)); | |||
4760 | run_write(sc, RT2860_WPDMA_GLO_CFG0x0208, tmp); | |||
4761 | ||||
4762 | for (ntries = 0; ntries < 100; ntries++) { | |||
4763 | if (run_read(sc, RT2860_WPDMA_GLO_CFG0x0208, &tmp) != 0) | |||
4764 | break; | |||
4765 | if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0) | |||
4766 | break; | |||
4767 | DELAY(10)(*delay_func)(10); | |||
4768 | } | |||
4769 | if (ntries == 100) { | |||
4770 | printf("%s: timeout waiting for DMA engine\n", | |||
4771 | sc->sc_dev.dv_xname); | |||
4772 | } | |||
4773 | ||||
4774 | /* disable Tx/Rx */ | |||
4775 | run_read(sc, RT2860_MAC_SYS_CTRL0x1004, &tmp); | |||
4776 | tmp &= ~(RT2860_MAC_RX_EN(1 << 3) | RT2860_MAC_TX_EN(1 << 2)); | |||
4777 | run_write(sc, RT2860_MAC_SYS_CTRL0x1004, tmp); | |||
4778 | ||||
4779 | /* wait for pending Tx to complete */ | |||
4780 | for (ntries = 0; ntries < 100; ntries++) { | |||
4781 | if (run_read(sc, RT2860_TXRXQ_PCNT0x0438, &tmp) != 0) | |||
4782 | break; | |||
4783 | if ((tmp & RT2860_TX2Q_PCNT_MASK0x00ff0000) == 0) | |||
4784 | break; | |||
4785 | } | |||
4786 | DELAY(1000)(*delay_func)(1000); | |||
4787 | run_write(sc, RT2860_USB_DMA_CFG0x02a0, 0); | |||
4788 | ||||
4789 | /* reset adapter */ | |||
4790 | run_write(sc, RT2860_MAC_SYS_CTRL0x1004, RT2860_BBP_HRST(1 << 1) | RT2860_MAC_SRST(1 << 0)); | |||
4791 | run_write(sc, RT2860_MAC_SYS_CTRL0x1004, 0); | |||
4792 | ||||
4793 | /* reset Tx and Rx rings */ | |||
4794 | sc->qfullmsk = 0; | |||
4795 | for (qid = 0; qid < 4; qid++) | |||
4796 | run_free_tx_ring(sc, qid); | |||
4797 | run_free_rx_ring(sc); | |||
4798 | } |