Bug Summary

File:dev/pci/igc_i225.c
Warning:line 1006, column 3
Value stored to 'ret_val' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name igc_i225.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/igc_i225.c
1/* $OpenBSD: igc_i225.c,v 1.4 2023/02/03 11:31:52 mbuhl Exp $ */
2/*-
3 * Copyright 2021 Intel Corp
4 * Copyright 2021 Rubicon Communications, LLC (Netgate)
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <dev/pci/igc_api.h>
9
10int igc_init_nvm_params_i225(struct igc_hw *);
11int igc_init_mac_params_i225(struct igc_hw *);
12int igc_init_phy_params_i225(struct igc_hw *);
13int igc_reset_hw_i225(struct igc_hw *);
14int igc_acquire_nvm_i225(struct igc_hw *);
15void igc_release_nvm_i225(struct igc_hw *);
16int igc_get_hw_semaphore_i225(struct igc_hw *);
17int __igc_write_nvm_srwr(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
18int igc_pool_flash_update_done_i225(struct igc_hw *);
19
20/**
21 * igc_init_nvm_params_i225 - Init NVM func ptrs.
22 * @hw: pointer to the HW structure
23 **/
24int
25igc_init_nvm_params_i225(struct igc_hw *hw)
26{
27 struct igc_nvm_info *nvm = &hw->nvm;
28 uint32_t eecd = IGC_READ_REG(hw, IGC_EECD)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00010)
));
29 uint16_t size;
30
31 DEBUGFUNC("igc_init_nvm_params_i225")do { if (0) printf("igc_init_nvm_params_i225" "\n"); } while (
0);
32
33 size = (uint16_t)((eecd & IGC_EECD_SIZE_EX_MASK0x00007800) >>
34 IGC_EECD_SIZE_EX_SHIFT11);
35 /*
36 * Added to a constant, "size" becomes the left-shift value
37 * for setting word_size.
38 */
39 size += NVM_WORD_SIZE_BASE_SHIFT6;
40
41 /* Just in case size is out of range, cap it to the largest
42 * EEPROM size supported.
43 */
44 if (size > 15)
45 size = 15;
46
47 nvm->word_size = 1 << size;
48 nvm->opcode_bits = 8;
49 nvm->delay_usec = 1;
50 nvm->type = igc_nvm_eeprom_spi;
51
52 nvm->page_size = eecd & IGC_EECD_ADDR_BITS0x00000400 ? 32 : 8;
53 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS0x00000400 ? 16 : 8;
54
55 if (nvm->word_size == (1 << 15))
56 nvm->page_size = 128;
57
58 nvm->ops.acquire = igc_acquire_nvm_i225;
59 nvm->ops.release = igc_release_nvm_i225;
60 if (igc_get_flash_presence_i225(hw)) {
61 hw->nvm.type = igc_nvm_flash_hw;
62 nvm->ops.read = igc_read_nvm_srrd_i225;
63 nvm->ops.write = igc_write_nvm_srwr_i225;
64 nvm->ops.validate = igc_validate_nvm_checksum_i225;
65 nvm->ops.update = igc_update_nvm_checksum_i225;
66 } else {
67 hw->nvm.type = igc_nvm_invm;
68 nvm->ops.write = igc_null_write_nvm;
69 nvm->ops.validate = igc_null_ops_generic;
70 nvm->ops.update = igc_null_ops_generic;
71 }
72
73 return IGC_SUCCESS0;
74}
75
76/**
77 * igc_init_mac_params_i225 - Init MAC func ptrs.
78 * @hw: pointer to the HW structure
79 **/
80int
81igc_init_mac_params_i225(struct igc_hw *hw)
82{
83 struct igc_mac_info *mac = &hw->mac;
84 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225;
85
86 DEBUGFUNC("igc_init_mac_params_i225")do { if (0) printf("igc_init_mac_params_i225" "\n"); } while (
0);
87
88 /* Initialize function pointer */
89 igc_init_mac_ops_generic(hw);
90
91 /* Set media type */
92 hw->phy.media_type = igc_media_type_copper;
93 /* Set mta register count */
94 mac->mta_reg_count = 128;
95 /* Set rar entry count */
96 mac->rar_entry_count = IGC_RAR_ENTRIES_BASE16;
97
98 /* reset */
99 mac->ops.reset_hw = igc_reset_hw_i225;
100 /* hw initialization */
101 mac->ops.init_hw = igc_init_hw_i225;
102 /* link setup */
103 mac->ops.setup_link = igc_setup_link_generic;
104 /* check for link */
105 mac->ops.check_for_link = igc_check_for_link_i225;
106 /* link info */
107 mac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic;
108 /* acquire SW_FW sync */
109 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;
110 /* release SW_FW sync */
111 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;
112
113 /* Allow a single clear of the SW semaphore on I225 */
114 dev_spec->clear_semaphore_once = true1;
115 mac->ops.setup_physical_interface = igc_setup_copper_link_i225;
116
117 /* Set if part includes ASF firmware */
118 mac->asf_firmware_present = true1;
119
120 /* multicast address update */
121 mac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic;
122
123 mac->ops.write_vfta = igc_write_vfta_generic;
124
125 return IGC_SUCCESS0;
126}
127
128/**
129 * igc_init_phy_params_i225 - Init PHY func ptrs.
130 * @hw: pointer to the HW structure
131 **/
132int
133igc_init_phy_params_i225(struct igc_hw *hw)
134{
135 struct igc_phy_info *phy = &hw->phy;
136 int ret_val = IGC_SUCCESS0;
137
138 DEBUGFUNC("igc_init_phy_params_i225")do { if (0) printf("igc_init_phy_params_i225" "\n"); } while (
0);
139
140 if (hw->phy.media_type != igc_media_type_copper) {
141 phy->type = igc_phy_none;
142 goto out;
143 }
144
145 phy->ops.power_up = igc_power_up_phy_copper;
146 phy->ops.power_down = igc_power_down_phy_copper_base;
147 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500( 0x0001 | 0x0002 | 0x0004 | 0x0008 | 0x0020 | 0x0080);
148 phy->reset_delay_us = 100;
149 phy->ops.acquire = igc_acquire_phy_base;
150 phy->ops.check_reset_block = igc_check_reset_block_generic;
151 phy->ops.release = igc_release_phy_base;
152 phy->ops.reset = igc_phy_hw_reset_generic;
153 phy->ops.read_reg = igc_read_phy_reg_gpy;
154 phy->ops.write_reg = igc_write_phy_reg_gpy;
155
156 /* Make sure the PHY is in a good state. Several people have reported
157 * firmware leaving the PHY's page select register set to something
158 * other than the default of zero, which causes the PHY ID read to
159 * access something other than the intended register.
160 */
161 ret_val = hw->phy.ops.reset(hw);
162 if (ret_val)
163 goto out;
164
165 ret_val = igc_get_phy_id(hw);
166 phy->type = igc_phy_i225;
167
168out:
169 return ret_val;
170}
171
172/**
173 * igc_reset_hw_i225 - Reset hardware
174 * @hw: pointer to the HW structure
175 *
176 * This resets the hardware into a known state.
177 **/
178int
179igc_reset_hw_i225(struct igc_hw *hw)
180{
181 uint32_t ctrl;
182 int ret_val;
183
184 DEBUGFUNC("igc_reset_hw_i225")do { if (0) printf("igc_reset_hw_i225" "\n"); } while (0);
185
186 /*
187 * Prevent the PCI-E bus from sticking if there is no TLP connection
188 * on the last TLP read/write transaction when MAC is reset.
189 */
190 ret_val = igc_disable_pcie_master_generic(hw);
191 if (ret_val)
192 DEBUGOUT("PCI-E Master disable polling has failed.\n")do { if (0) printf("PCI-E Master disable polling has failed.\n"
); } while (0);
193
194 DEBUGOUT("Masking off all interrupts\n")do { if (0) printf("Masking off all interrupts\n"); } while (
0);
195 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0150C)
, (0xffffffff)));
196
197 IGC_WRITE_REG(hw, IGC_RCTL, 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00100)
, (0)));
198 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00400)
, (0x00000008)));
199 IGC_WRITE_FLUSH(hw)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00008)
));
200
201 msec_delay(10)(*delay_func)(1000 * (10));
202
203 ctrl = IGC_READ_REG(hw, IGC_CTRL)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00000)
));
204
205 DEBUGOUT("Issuing a global reset to MAC\n")do { if (0) printf("Issuing a global reset to MAC\n"); } while
(0);
206 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00000)
, (ctrl | 0x20000000)));
207
208 ret_val = igc_get_auto_rd_done_generic(hw);
209 if (ret_val) {
210 /*
211 * When auto config read does not complete, do not
212 * return with an error. This can happen in situations
213 * where there is no eeprom and prevents getting link.
214 */
215 DEBUGOUT("Auto Read Done did not complete\n")do { if (0) printf("Auto Read Done did not complete\n"); } while
(0);
216 }
217
218 /* Clear any pending interrupt events. */
219 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0150C)
, (0xffffffff)));
220 IGC_READ_REG(hw, IGC_ICR)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01500)
));
221
222 /* Install any alternate MAC address into RAR0 */
223 ret_val = igc_check_alt_mac_addr_generic(hw);
224
225 return ret_val;
226}
227
228/* igc_acquire_nvm_i225 - Request for access to EEPROM
229 * @hw: pointer to the HW structure
230 *
231 * Acquire the necessary semaphores for exclusive access to the EEPROM.
232 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
233 * Return successful if access grant bit set, else clear the request for
234 * EEPROM access and return -IGC_ERR_NVM (-1).
235 */
236int
237igc_acquire_nvm_i225(struct igc_hw *hw)
238{
239 int ret_val;
240
241 DEBUGFUNC("igc_acquire_nvm_i225")do { if (0) printf("igc_acquire_nvm_i225" "\n"); } while (0);
242
243 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM0x01);
244
245 return ret_val;
246}
247
248/* igc_release_nvm_i225 - Release exclusive access to EEPROM
249 * @hw: pointer to the HW structure
250 *
251 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
252 * then release the semaphores acquired.
253 */
254void
255igc_release_nvm_i225(struct igc_hw *hw)
256{
257 DEBUGFUNC("igc_release_nvm_i225")do { if (0) printf("igc_release_nvm_i225" "\n"); } while (0);
258
259 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM0x01);
260}
261
262/* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore
263 * @hw: pointer to the HW structure
264 * @mask: specifies which semaphore to acquire
265 *
266 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
267 * will also specify which port we're acquiring the lock for.
268 */
269int
270igc_acquire_swfw_sync_i225(struct igc_hw *hw, uint16_t mask)
271{
272 uint32_t swfw_sync;
273 uint32_t swmask = mask;
274 uint32_t fwmask = mask << 16;
275 int ret_val = IGC_SUCCESS0;
276 int i = 0, timeout = 200; /* FIXME: find real value to use here */
277
278 DEBUGFUNC("igc_acquire_swfw_sync_i225")do { if (0) printf("igc_acquire_swfw_sync_i225" "\n"); } while
(0);
279
280 while (i < timeout) {
281 if (igc_get_hw_semaphore_i225(hw)) {
282 ret_val = -IGC_ERR_SWFW_SYNC13;
283 goto out;
284 }
285
286 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B5C)
));
287 if (!(swfw_sync & (fwmask | swmask)))
288 break;
289
290 /* Firmware currently using resource (fwmask)
291 * or other software thread using resource (swmask)
292 */
293 igc_put_hw_semaphore_generic(hw);
294 msec_delay(5)(*delay_func)(1000 * (5));
295 i++;
296 }
297
298 if (i == timeout) {
299 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n")do { if (0) printf("Driver can't access resource, SW_FW_SYNC timeout.\n"
); } while (0);
300 ret_val = -IGC_ERR_SWFW_SYNC13;
301 goto out;
302 }
303
304 swfw_sync |= swmask;
305 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B5C)
, (swfw_sync)));
306
307 igc_put_hw_semaphore_generic(hw);
308
309out:
310 return ret_val;
311}
312
313/* igc_release_swfw_sync_i225 - Release SW/FW semaphore
314 * @hw: pointer to the HW structure
315 * @mask: specifies which semaphore to acquire
316 *
317 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
318 * will also specify which port we're releasing the lock for.
319 */
320void
321igc_release_swfw_sync_i225(struct igc_hw *hw, uint16_t mask)
322{
323 uint32_t swfw_sync;
324
325 DEBUGFUNC("igc_release_swfw_sync_i225")do { if (0) printf("igc_release_swfw_sync_i225" "\n"); } while
(0);
326
327 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS0)
328 ; /* Empty */
329
330 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B5C)
));
331 swfw_sync &= ~mask;
332 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B5C)
, (swfw_sync)));
333
334 igc_put_hw_semaphore_generic(hw);
335}
336
337/*
338 * igc_setup_copper_link_i225 - Configure copper link settings
339 * @hw: pointer to the HW structure
340 *
341 * Configures the link for auto-neg or forced speed and duplex. Then we check
342 * for link, once link is established calls to configure collision distance
343 * and flow control are called.
344 */
345int
346igc_setup_copper_link_i225(struct igc_hw *hw)
347{
348 uint32_t ctrl, phpm_reg;
349 int ret_val;
350
351 DEBUGFUNC("igc_setup_copper_link_i225")do { if (0) printf("igc_setup_copper_link_i225" "\n"); } while
(0);
352
353 ctrl = IGC_READ_REG(hw, IGC_CTRL)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00000)
));
354 ctrl |= IGC_CTRL_SLU0x00000040;
355 ctrl &= ~(IGC_CTRL_FRCSPD0x00000800 | IGC_CTRL_FRCDPX0x00001000);
356 IGC_WRITE_REG(hw, IGC_CTRL, ctrl)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00000)
, (ctrl)));
357
358 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E14))
);
359 phpm_reg &= ~IGC_I225_PHPM_GO_LINKD0x0020;
360 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E14),
(phpm_reg)));
361
362 ret_val = igc_setup_copper_link_generic(hw);
363
364 return ret_val;
365}
366
367/* igc_get_hw_semaphore_i225 - Acquire hardware semaphore
368 * @hw: pointer to the HW structure
369 *
370 * Acquire the HW semaphore to access the PHY or NVM
371 */
372int
373igc_get_hw_semaphore_i225(struct igc_hw *hw)
374{
375 uint32_t swsm;
376 int timeout = hw->nvm.word_size + 1;
377 int i = 0;
378
379 DEBUGFUNC("igc_get_hw_semaphore_i225")do { if (0) printf("igc_get_hw_semaphore_i225" "\n"); } while
(0);
380
381 /* Get the SW semaphore */
382 while (i < timeout) {
383 swsm = IGC_READ_REG(hw, IGC_SWSM)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B50)
));
384 if (!(swsm & IGC_SWSM_SMBI0x00000001))
385 break;
386
387 DELAY(50)(*delay_func)(50);
388 i++;
389 }
390
391 if (i == timeout) {
392 /* In rare circumstances, the SW semaphore may already be held
393 * unintentionally. Clear the semaphore once before giving up.
394 */
395 if (hw->dev_spec._i225.clear_semaphore_once) {
396 hw->dev_spec._i225.clear_semaphore_once = false0;
397 igc_put_hw_semaphore_generic(hw);
398 for (i = 0; i < timeout; i++) {
399 swsm = IGC_READ_REG(hw, IGC_SWSM)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B50)
));
400 if (!(swsm & IGC_SWSM_SMBI0x00000001))
401 break;
402
403 DELAY(50)(*delay_func)(50);
404 }
405 }
406
407 /* If we do not have the semaphore here, we have to give up. */
408 if (i == timeout) {
409 DEBUGOUT("Driver can't access device -\n")do { if (0) printf("Driver can't access device -\n"); } while
(0);
410 DEBUGOUT("SMBI bit is set.\n")do { if (0) printf("SMBI bit is set.\n"); } while (0);
411 return -IGC_ERR_NVM1;
412 }
413 }
414
415 /* Get the FW semaphore. */
416 for (i = 0; i < timeout; i++) {
417 swsm = IGC_READ_REG(hw, IGC_SWSM)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B50)
));
418 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B50)
, (swsm | 0x00000002)));
419
420 /* Semaphore acquired if bit latched */
421 if (IGC_READ_REG(hw, IGC_SWSM)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B50)
)) & IGC_SWSM_SWESMBI0x00000002)
422 break;
423
424 DELAY(50)(*delay_func)(50);
425 }
426
427 if (i == timeout) {
428 /* Release semaphores */
429 igc_put_hw_semaphore_generic(hw);
430 DEBUGOUT("Driver can't access the NVM\n")do { if (0) printf("Driver can't access the NVM\n"); } while (
0);
431 return -IGC_ERR_NVM1;
432 }
433
434 return IGC_SUCCESS0;
435}
436
437/* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register
438 * @hw: pointer to the HW structure
439 * @offset: offset of word in the Shadow Ram to read
440 * @words: number of words to read
441 * @data: word read from the Shadow Ram
442 *
443 * Reads a 16 bit word from the Shadow Ram using the EERD register.
444 * Uses necessary synchronization semaphores.
445 */
446int
447igc_read_nvm_srrd_i225(struct igc_hw *hw, uint16_t offset, uint16_t words,
448 uint16_t *data)
449{
450 uint16_t i, count;
451 int status = IGC_SUCCESS0;
452
453 DEBUGFUNC("igc_read_nvm_srrd_i225")do { if (0) printf("igc_read_nvm_srrd_i225" "\n"); } while (0
);
454
455 /* We cannot hold synchronization semaphores for too long,
456 * because of forceful takeover procedure. However it is more efficient
457 * to read in bursts than synchronizing access for each word.
458 */
459 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT512) {
460 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT512 > 0 ?
461 IGC_EERD_EEWR_MAX_COUNT512 : (words - i);
462 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS0) {
463 status = igc_read_nvm_eerd(hw, offset, count, data + i);
464 hw->nvm.ops.release(hw);
465 } else {
466 status = IGC_ERR_SWFW_SYNC13;
467 }
468
469 if (status != IGC_SUCCESS0)
470 break;
471 }
472
473 return status;
474}
475
476/* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR
477 * @hw: pointer to the HW structure
478 * @offset: offset within the Shadow RAM to be written to
479 * @words: number of words to write
480 * @data: 16 bit word(s) to be written to the Shadow RAM
481 *
482 * Writes data to Shadow RAM at offset using EEWR register.
483 *
484 * If igc_update_nvm_checksum is not called after this function , the
485 * data will not be committed to FLASH and also Shadow RAM will most likely
486 * contain an invalid checksum.
487 *
488 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
489 * partially written.
490 */
491int
492igc_write_nvm_srwr_i225(struct igc_hw *hw, uint16_t offset, uint16_t words,
493 uint16_t *data)
494{
495 uint16_t i, count;
496 int status = IGC_SUCCESS0;
497
498 DEBUGFUNC("igc_write_nvm_srwr_i225")do { if (0) printf("igc_write_nvm_srwr_i225" "\n"); } while (
0);
499
500 /* We cannot hold synchronization semaphores for too long,
501 * because of forceful takeover procedure. However it is more efficient
502 * to write in bursts than synchronizing access for each word.
503 */
504 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT512) {
505 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT512 > 0 ?
506 IGC_EERD_EEWR_MAX_COUNT512 : (words - i);
507 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS0) {
508 status = __igc_write_nvm_srwr(hw, offset, count,
509 data + i);
510 hw->nvm.ops.release(hw);
511 } else
512 status = IGC_ERR_SWFW_SYNC13;
513
514 if (status != IGC_SUCCESS0)
515 break;
516 }
517
518 return status;
519}
520
521/* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR
522 * @hw: pointer to the HW structure
523 * @offset: offset within the Shadow Ram to be written to
524 * @words: number of words to write
525 * @data: 16 bit word(s) to be written to the Shadow Ram
526 *
527 * Writes data to Shadow Ram at offset using EEWR register.
528 *
529 * If igc_update_nvm_checksum is not called after this function , the
530 * Shadow Ram will most likely contain an invalid checksum.
531 */
532int
533__igc_write_nvm_srwr(struct igc_hw *hw, uint16_t offset, uint16_t words,
534 uint16_t *data)
535{
536 struct igc_nvm_info *nvm = &hw->nvm;
537 uint32_t i, k, eewr = 0;
538 uint32_t attempts = 100000;
539 int ret_val = IGC_SUCCESS0;
540
541 DEBUGFUNC("__igc_write_nvm_srwr")do { if (0) printf("__igc_write_nvm_srwr" "\n"); } while (0);
542
543 /* A check for invalid values: offset too large, too many words,
544 * too many words for the offset, and not enough words.
545 */
546 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
547 (words == 0)) {
548 DEBUGOUT("nvm parameter(s) out of bounds\n")do { if (0) printf("nvm parameter(s) out of bounds\n"); } while
(0);
549 ret_val = -IGC_ERR_NVM1;
550 goto out;
551 }
552
553 for (i = 0; i < words; i++) {
554 eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT2) |
555 (data[i] << IGC_NVM_RW_REG_DATA16) | IGC_NVM_RW_REG_START1;
556
557 IGC_WRITE_REG(hw, IGC_SRWR, eewr)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x12018)
, (eewr)));
558
559 for (k = 0; k < attempts; k++) {
560 if (IGC_NVM_RW_REG_DONE2 & IGC_READ_REG(hw, IGC_SRWR)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x12018)
))) {
561 ret_val = IGC_SUCCESS0;
562 break;
563 }
564 DELAY(5)(*delay_func)(5);
565 }
566
567 if (ret_val != IGC_SUCCESS0) {
568 DEBUGOUT("Shadow RAM write EEWR timed out\n")do { if (0) printf("Shadow RAM write EEWR timed out\n"); } while
(0);
569 break;
570 }
571 }
572
573out:
574 return ret_val;
575}
576
577/* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum
578 * @hw: pointer to the HW structure
579 *
580 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
581 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
582 */
583int
584igc_validate_nvm_checksum_i225(struct igc_hw *hw)
585{
586 int status = IGC_SUCCESS0;
587 int (*read_op_ptr)(struct igc_hw *, uint16_t, uint16_t, uint16_t *);
588
589 DEBUGFUNC("igc_validate_nvm_checksum_i225")do { if (0) printf("igc_validate_nvm_checksum_i225" "\n"); } while
(0);
590
591 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS0) {
592 /* Replace the read function with semaphore grabbing with
593 * the one that skips this for a while.
594 * We have semaphore taken already here.
595 */
596 read_op_ptr = hw->nvm.ops.read;
597 hw->nvm.ops.read = igc_read_nvm_eerd;
598
599 status = igc_validate_nvm_checksum_generic(hw);
600
601 /* Revert original read operation. */
602 hw->nvm.ops.read = read_op_ptr;
603
604 hw->nvm.ops.release(hw);
605 } else {
606 status = IGC_ERR_SWFW_SYNC13;
607 }
608
609 return status;
610}
611
612/* igc_update_nvm_checksum_i225 - Update EEPROM checksum
613 * @hw: pointer to the HW structure
614 *
615 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
616 * up to the checksum. Then calculates the EEPROM checksum and writes the
617 * value to the EEPROM. Next commit EEPROM data onto the Flash.
618 */
619int
620igc_update_nvm_checksum_i225(struct igc_hw *hw)
621{
622 uint16_t checksum = 0;
623 uint16_t i, nvm_data;
624 int ret_val;
625
626 DEBUGFUNC("igc_update_nvm_checksum_i225")do { if (0) printf("igc_update_nvm_checksum_i225" "\n"); } while
(0);
627
628 /* Read the first word from the EEPROM. If this times out or fails, do
629 * not continue or we could be in for a very long wait while every
630 * EEPROM read fails
631 */
632 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);
633 if (ret_val != IGC_SUCCESS0) {
634 DEBUGOUT("EEPROM read failed\n")do { if (0) printf("EEPROM read failed\n"); } while (0);
635 goto out;
636 }
637
638 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS0) {
639 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
640 * because we do not want to take the synchronization
641 * semaphores twice here.
642 */
643
644 for (i = 0; i < NVM_CHECKSUM_REG0x003F; i++) {
645 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);
646 if (ret_val) {
647 hw->nvm.ops.release(hw);
648 DEBUGOUT("NVM Read Error while updating\n")do { if (0) printf("NVM Read Error while updating\n"); } while
(0);
649 DEBUGOUT("checksum.\n")do { if (0) printf("checksum.\n"); } while (0);
650 goto out;
651 }
652 checksum += nvm_data;
653 }
654 checksum = (uint16_t)NVM_SUM0xBABA - checksum;
655 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG0x003F, 1,
656 &checksum);
657 if (ret_val != IGC_SUCCESS0) {
658 hw->nvm.ops.release(hw);
659 DEBUGOUT("NVM Write Error while updating checksum.\n")do { if (0) printf("NVM Write Error while updating checksum.\n"
); } while (0);
660 goto out;
661 }
662
663 hw->nvm.ops.release(hw);
664
665 ret_val = igc_update_flash_i225(hw);
666 } else {
667 ret_val = IGC_ERR_SWFW_SYNC13;
668 }
669out:
670 return ret_val;
671}
672
673/* igc_get_flash_presence_i225 - Check if flash device is detected.
674 * @hw: pointer to the HW structure
675 */
676bool_Bool
677igc_get_flash_presence_i225(struct igc_hw *hw)
678{
679 uint32_t eec = 0;
680 bool_Bool ret_val = false0;
681
682 DEBUGFUNC("igc_get_flash_presence_i225")do { if (0) printf("igc_get_flash_presence_i225" "\n"); } while
(0);
683
684 eec = IGC_READ_REG(hw, IGC_EECD)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00010)
));
685
686 if (eec & IGC_EECD_FLASH_DETECTED_I2250x00080000)
687 ret_val = true1;
688
689 return ret_val;
690}
691
692/* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst
693 * Counter in FLSWCNT register.
694 *
695 * @hw: pointer to the HW structure
696 * @burst_counter: size in bytes of the Flash burst to read or write
697 */
698int
699igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, uint32_t burst_counter)
700{
701 int ret_val = IGC_SUCCESS0;
702
703 DEBUGFUNC("igc_set_flsw_flash_burst_counter_i225")do { if (0) printf("igc_set_flsw_flash_burst_counter_i225" "\n"
); } while (0);
704
705 /* Validate input data */
706 if (burst_counter < IGC_I225_SHADOW_RAM_SIZE4096) {
707 /* Write FLSWCNT - burst counter */
708 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x12050)
, (burst_counter)));
709 } else {
710 ret_val = IGC_ERR_INVALID_ARGUMENT16;
711 }
712
713 return ret_val;
714}
715
716
717/* igc_write_erase_flash_command_i225 - write/erase to a sector
718 * region on a given address.
719 *
720 * @hw: pointer to the HW structure
721 * @opcode: opcode to be used for the write command
722 * @address: the offset to write into the FLASH image
723 */
724int
725igc_write_erase_flash_command_i225(struct igc_hw *hw, uint32_t opcode,
726 uint32_t address)
727{
728 uint32_t flswctl = 0;
729 int timeout = IGC_NVM_GRANT_ATTEMPTS1000;
730 int ret_val = IGC_SUCCESS0;
731
732 DEBUGFUNC("igc_write_erase_flash_command_i225")do { if (0) printf("igc_write_erase_flash_command_i225" "\n")
; } while (0);
733
734 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x12048)
));
735 /* Polling done bit on FLSWCTL register */
736 while (timeout) {
737 if (flswctl & IGC_FLSWCTL_DONE0x40000000)
738 break;
739 DELAY(5)(*delay_func)(5);
740 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x12048)
));
741 timeout--;
742 }
743
744 if (!timeout) {
745 DEBUGOUT("Flash transaction was not done\n")do { if (0) printf("Flash transaction was not done\n"); } while
(0);
746 return -IGC_ERR_NVM1;
747 }
748
749 /* Build and issue command on FLSWCTL register */
750 flswctl = address | opcode;
751 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x12048)
, (flswctl)));
752
753 /* Check if issued command is valid on FLSWCTL register */
754 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x12048)
));
755 if (!(flswctl & IGC_FLSWCTL_CMDV0x10000000)) {
756 DEBUGOUT("Write flash command failed\n")do { if (0) printf("Write flash command failed\n"); } while (
0);
757 ret_val = IGC_ERR_INVALID_ARGUMENT16;
758 }
759
760 return ret_val;
761}
762
763/* igc_update_flash_i225 - Commit EEPROM to the flash
764 * if fw_valid_bit is set, FW is active. setting FLUPD bit in EEC
765 * register makes the FW load the internal shadow RAM into the flash.
766 * Otherwise, fw_valid_bit is 0. if FL_SECU.block_prtotected_sw = 0
767 * then FW is not active so the SW is responsible shadow RAM dump.
768 *
769 * @hw: pointer to the HW structure
770 */
771int
772igc_update_flash_i225(struct igc_hw *hw)
773{
774 uint32_t block_sw_protect = 1;
775 uint32_t i, flup, fw_valid_bit;
776 uint16_t current_offset;
777 uint16_t base_address = 0x0;
778 uint16_t current_offset_data = 0;
779 int ret_val = 0;
780
781 DEBUGFUNC("igc_update_flash_i225")do { if (0) printf("igc_update_flash_i225" "\n"); } while (0);
782
783 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x12114)
)) &
784 IGC_FLSECU_BLK_SW_ACCESS_I2250x00000004;
785
786 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05B54)
)) & IGC_FWSM_FW_VALID_I2250x8000;
787 if (fw_valid_bit) {
788 ret_val = igc_pool_flash_update_done_i225(hw);
789 if (ret_val == -IGC_ERR_NVM1) {
790 DEBUGOUT("Flash update time out\n")do { if (0) printf("Flash update time out\n"); } while (0);
791 goto out;
792 }
793
794 flup = IGC_READ_REG(hw, IGC_EECD)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00010)
)) | IGC_EECD_FLUPD_I2250x00800000;
795 IGC_WRITE_REG(hw, IGC_EECD, flup)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00010)
, (flup)));
796
797 ret_val = igc_pool_flash_update_done_i225(hw);
798 if (ret_val == IGC_SUCCESS0)
799 DEBUGOUT("Flash update complete\n")do { if (0) printf("Flash update complete\n"); } while (0);
800 else
801 DEBUGOUT("Flash update time out\n")do { if (0) printf("Flash update time out\n"); } while (0);
802 } else if (!block_sw_protect) {
803 /* FW is not active and security protection is disabled.
804 * therefore, SW is in charge of shadow RAM dump.
805 * Check which sector is valid. if sector 0 is valid,
806 * base address remains 0x0. otherwise, sector 1 is
807 * valid and its base address is 0x1000
808 */
809 if (IGC_READ_REG(hw, IGC_EECD)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00010)
)) & IGC_EECD_SEC1VAL_I2250x02000000)
810 base_address = 0x1000;
811
812 /* Valid sector erase */
813 ret_val = igc_write_erase_flash_command_i225(hw,
814 IGC_I225_ERASE_CMD_OPCODE0x02000000, base_address);
815 if (!ret_val) {
816 DEBUGOUT("Sector erase failed\n")do { if (0) printf("Sector erase failed\n"); } while (0);
817 goto out;
818 }
819
820 current_offset = base_address;
821
822 /* Write */
823 for (i = 0; i < IGC_I225_SHADOW_RAM_SIZE4096 / 2; i++) {
824 /* Set burst write length */
825 ret_val = igc_set_flsw_flash_burst_counter_i225(hw,
826 0x2);
827 if (ret_val != IGC_SUCCESS0)
828 break;
829
830 /* Set address and opcode */
831 ret_val = igc_write_erase_flash_command_i225(hw,
832 IGC_I225_WRITE_CMD_OPCODE0x01000000, 2 * current_offset);
833 if (ret_val != IGC_SUCCESS0)
834 break;
835
836 ret_val = igc_read_nvm_eerd(hw, current_offset, 1,
837 &current_offset_data);
838 if (ret_val) {
839 DEBUGOUT("Failed to read from EEPROM\n")do { if (0) printf("Failed to read from EEPROM\n"); } while (
0);
840 goto out;
841 }
842
843 /* Write CurrentOffseData to FLSWDATA register */
844 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA,((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x1204C)
, (current_offset_data)))
845 current_offset_data)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x1204C)
, (current_offset_data)));
846 current_offset++;
847
848 /* Wait till operation has finished */
849 ret_val = igc_poll_eerd_eewr_done(hw,
850 IGC_NVM_POLL_READ0);
851 if (ret_val)
852 break;
853
854 DELAY(1000)(*delay_func)(1000);
855 }
856 }
857out:
858 return ret_val;
859}
860
861/* igc_pool_flash_update_done_i225 - Pool FLUDONE status.
862 * @hw: pointer to the HW structure
863 */
864int
865igc_pool_flash_update_done_i225(struct igc_hw *hw)
866{
867 uint32_t i, reg;
868 int ret_val = -IGC_ERR_NVM1;
869
870 DEBUGFUNC("igc_pool_flash_update_done_i225")do { if (0) printf("igc_pool_flash_update_done_i225" "\n"); }
while (0);
871
872 for (i = 0; i < IGC_FLUDONE_ATTEMPTS20000; i++) {
873 reg = IGC_READ_REG(hw, IGC_EECD)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00010)
));
874 if (reg & IGC_EECD_FLUDONE_I2250x04000000) {
875 ret_val = IGC_SUCCESS0;
876 break;
877 }
878 DELAY(5)(*delay_func)(5);
879 }
880
881 return ret_val;
882}
883
884/* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds.
885 * @hw: pointer to the HW structure
886 * @link: bool indicating link status
887 *
888 * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC
889 * settings, otherwise specify that there is no LTR requirement.
890 */
891int
892igc_set_ltr_i225(struct igc_hw *hw, bool_Bool link)
893{
894 uint16_t speed, duplex;
895 uint32_t tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max;
896 int size;
897
898 DEBUGFUNC("igc_set_ltr_i225")do { if (0) printf("igc_set_ltr_i225" "\n"); } while (0);
899
900 /* If we do not have link, LTR thresholds are zero. */
901 if (link) {
902 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
903
904 /* Check if using copper interface with EEE enabled or if the
905 * link speed is 10 Mbps.
906 */
907 if ((hw->phy.media_type == igc_media_type_copper) &&
908 !(hw->dev_spec._i225.eee_disable) &&
909 (speed != SPEED_1010)) {
910 /* EEE enabled, so send LTRMAX threshold. */
911 ltrc = IGC_READ_REG(hw, IGC_LTRC)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01A0))
) | IGC_LTRC_EEEMS_EN0x00000020;
912 IGC_WRITE_REG(hw, IGC_LTRC, ltrc)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01A0),
(ltrc)));
913
914 /* Calculate tw_system (nsec). */
915 if (speed == SPEED_100100) {
916 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E34))
) &
917 IGC_TW_SYSTEM_100_MASK0x0000FF00) >>
918 IGC_TW_SYSTEM_100_SHIFT8) * 500;
919 } else {
920 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E34))
) &
921 IGC_TW_SYSTEM_1000_MASK0x000000FF) * 500;
922 }
923 } else {
924 tw_system = 0;
925 }
926
927 /* Get the Rx packet buffer size. */
928 size = IGC_READ_REG(hw, IGC_RXPBS)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02404)
)) & IGC_RXPBS_SIZE_I225_MASK0x0000003F;
929
930 /* Calculations vary based on DMAC settings. */
931 if (IGC_READ_REG(hw, IGC_DMACR)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02508)
)) & IGC_DMACR_DMAC_EN0x80000000) {
932 size -= (IGC_READ_REG(hw, IGC_DMACR)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02508)
)) &
933 IGC_DMACR_DMACTHR_MASK0x00FF0000) >> IGC_DMACR_DMACTHR_SHIFT16;
934 /* Convert size to bits. */
935 size *= 1024 * 8;
936 } else {
937 /* Convert size to bytes, subtract the MTU, and then
938 * convert the size to bits.
939 */
940 size *= 1024;
941 size -= hw->dev_spec._i225.mtu;
942 size *= 8;
943 }
944
945 if (size < 0) {
946 DEBUGOUT1("Invalid effective Rx buffer size %d\n",do { if (0) printf("Invalid effective Rx buffer size %d\n", size
); } while (0)
947 size)do { if (0) printf("Invalid effective Rx buffer size %d\n", size
); } while (0);
948 return -IGC_ERR_CONFIG3;
949 }
950
951 /* Calculate the thresholds. Since speed is in Mbps, simplify
952 * the calculation by multiplying size/speed by 1000 for result
953 * to be in nsec before dividing by the scale in nsec. Set the
954 * scale such that the LTR threshold fits in the register.
955 */
956 ltr_min = (1000 * size) / speed;
957 ltr_max = ltr_min + tw_system;
958 scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_10242 :
959 IGC_LTRMINV_SCALE_327683;
960 scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_10242 :
961 IGC_LTRMAXV_SCALE_327683;
962 ltr_min /= scale_min == IGC_LTRMINV_SCALE_10242 ? 1024 : 32768;
963 ltr_max /= scale_max == IGC_LTRMAXV_SCALE_10242 ? 1024 : 32768;
964
965 /* Only write the LTR thresholds if they differ from before. */
966 ltrv = IGC_READ_REG(hw, IGC_LTRMINV)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x5BB0))
);
967 if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK0x000003FF)) {
968 ltrv = IGC_LTRMINV_LSNP_REQ0x00008000 | ltr_min |
969 (scale_min << IGC_LTRMINV_SCALE_SHIFT10);
970 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x5BB0),
(ltrv)));
971 }
972
973 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x5BB4))
);
974 if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK0x000003FF)) {
975 ltrv = IGC_LTRMAXV_LSNP_REQ0x00008000 | ltr_max |
976 (scale_min << IGC_LTRMAXV_SCALE_SHIFT10);
977 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x5BB4),
(ltrv)));
978 }
979 }
980
981 return IGC_SUCCESS0;
982}
983
984/* igc_check_for_link_i225 - Check for link
985 * @hw: pointer to the HW structure
986 *
987 * Checks to see of the link status of the hardware has changed. If a
988 * change in link status has been detected, then we read the PHY registers
989 * to get the current speed/duplex if link exists.
990 */
991int
992igc_check_for_link_i225(struct igc_hw *hw)
993{
994 struct igc_mac_info *mac = &hw->mac;
995 int ret_val;
996 bool_Bool link = false0;
997
998 DEBUGFUNC("igc_check_for_link_i225")do { if (0) printf("igc_check_for_link_i225" "\n"); } while (
0);
999
1000 /* We only want to go out to the PHY registers to see if
1001 * Auto-Neg has completed and/or if our link status has
1002 * changed. The get_link_status flag is set upon receiving
1003 * a Link Status Change or Rx Sequence Error interrupt.
1004 */
1005 if (!mac->get_link_status) {
1006 ret_val = IGC_SUCCESS0;
Value stored to 'ret_val' is never read
1007 goto out;
1008 }
1009
1010 /* First we want to see if the MII Status Register reports
1011 * link. If so, then we want to get the current speed/duplex
1012 * of the PHY.
1013 */
1014 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1015 if (ret_val)
1016 goto out;
1017
1018 if (!link)
1019 goto out; /* No link detected */
1020
1021 /* First we want to see if the MII Status Register reports
1022 * link. If so, then we want to get the current speed/duplex
1023 * of the PHY.
1024 */
1025 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1026 if (ret_val)
1027 goto out;
1028
1029 if (!link)
1030 goto out; /* No link detected */
1031
1032 mac->get_link_status = false0;
1033
1034 /* Check if there was DownShift, must be checked
1035 * immediately after link-up
1036 */
1037 igc_check_downshift_generic(hw);
1038
1039 /* If we are forcing speed/duplex, then we simply return since
1040 * we have already determined whether we have link or not.
1041 */
1042 if (!mac->autoneg)
1043 goto out;
1044
1045 /* Auto-Neg is enabled. Auto Speed Detection takes care
1046 * of MAC speed/duplex configuration. So we only need to
1047 * configure Collision Distance in the MAC.
1048 */
1049 mac->ops.config_collision_dist(hw);
1050
1051 /* Configure Flow Control now that Auto-Neg has completed.
1052 * First, we need to restore the desired flow control
1053 * settings because we may have had to re-autoneg with a
1054 * different link partner.
1055 */
1056 ret_val = igc_config_fc_after_link_up_generic(hw);
1057 if (ret_val)
1058 DEBUGOUT("Error configuring flow control\n")do { if (0) printf("Error configuring flow control\n"); } while
(0);
1059out:
1060 /* Now that we are aware of our link settings, we can set the LTR
1061 * thresholds.
1062 */
1063 ret_val = igc_set_ltr_i225(hw, link);
1064
1065 return ret_val;
1066}
1067
1068/* igc_init_function_pointers_i225 - Init func ptrs.
1069 * @hw: pointer to the HW structure
1070 *
1071 * Called to initialize all function pointers and parameters.
1072 */
1073void
1074igc_init_function_pointers_i225(struct igc_hw *hw)
1075{
1076 igc_init_mac_ops_generic(hw);
1077 igc_init_phy_ops_generic(hw);
1078 igc_init_nvm_ops_generic(hw);
1079 hw->mac.ops.init_params = igc_init_mac_params_i225;
1080 hw->nvm.ops.init_params = igc_init_nvm_params_i225;
1081 hw->phy.ops.init_params = igc_init_phy_params_i225;
1082}
1083
1084/* igc_init_hw_i225 - Init hw for I225
1085 * @hw: pointer to the HW structure
1086 *
1087 * Called to initialize hw for i225 hw family.
1088 */
1089int
1090igc_init_hw_i225(struct igc_hw *hw)
1091{
1092 int ret_val;
1093
1094 DEBUGFUNC("igc_init_hw_i225")do { if (0) printf("igc_init_hw_i225" "\n"); } while (0);
1095
1096 ret_val = igc_init_hw_base(hw);
1097 return ret_val;
1098}
1099
1100/**
1101 * igc_set_eee_i225 - Enable/disable EEE support
1102 * @hw: pointer to the HW structure
1103 * @adv2p5G: boolean flag enabling 2.5G EEE advertisement
1104 * @adv1G: boolean flag enabling 1G EEE advertisement
1105 * @adv100M: boolean flag enabling 100M EEE advertisement
1106 *
1107 * Enable/disable EEE based on setting in dev_spec structure.
1108 *
1109 **/
1110int
1111igc_set_eee_i225(struct igc_hw *hw, bool_Bool adv2p5G, bool_Bool adv1G,
1112 bool_Bool adv100M)
1113{
1114 uint32_t ipcnfg, eeer;
1115
1116 DEBUGFUNC("igc_set_eee_i225")do { if (0) printf("igc_set_eee_i225" "\n"); } while (0);
1117
1118 if (hw->mac.type != igc_i225 ||
1119 hw->phy.media_type != igc_media_type_copper)
1120 goto out;
1121 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E38))
);
1122 eeer = IGC_READ_REG(hw, IGC_EEER)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E30))
);
1123
1124 /* enable or disable per user setting */
1125 if (!(hw->dev_spec._i225.eee_disable)) {
1126 uint32_t eee_su = IGC_READ_REG(hw, IGC_EEE_SU)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E34))
);
1127
1128 if (adv100M)
1129 ipcnfg |= IGC_IPCNFG_EEE_100M_AN0x00000004;
1130 else
1131 ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN0x00000004;
1132
1133 if (adv1G)
1134 ipcnfg |= IGC_IPCNFG_EEE_1G_AN0x00000008;
1135 else
1136 ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN0x00000008;
1137
1138 if (adv2p5G)
1139 ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN0x00000010;
1140 else
1141 ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN0x00000010;
1142
1143 eeer |= (IGC_EEER_TX_LPI_EN0x00010000 | IGC_EEER_RX_LPI_EN0x00020000 |
1144 IGC_EEER_LPI_FC0x00040000);
1145
1146 /* This bit should not be set in normal operation. */
1147 if (eee_su & IGC_EEE_SU_LPI_CLK_STP0x00800000)
1148 DEBUGOUT("LPI Clock Stop Bit should not be set!\n")do { if (0) printf("LPI Clock Stop Bit should not be set!\n")
; } while (0);
1149 } else {
1150 ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN0x00000010 | IGC_IPCNFG_EEE_1G_AN0x00000008 |
1151 IGC_IPCNFG_EEE_100M_AN0x00000004);
1152 eeer &= ~(IGC_EEER_TX_LPI_EN0x00010000 | IGC_EEER_RX_LPI_EN0x00020000 |
1153 IGC_EEER_LPI_FC0x00040000);
1154 }
1155 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E38),
(ipcnfg)));
1156 IGC_WRITE_REG(hw, IGC_EEER, eeer)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E30),
(eeer)));
1157 IGC_READ_REG(hw, IGC_IPCNFG)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E38))
);
1158 IGC_READ_REG(hw, IGC_EEER)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0E30))
);
1159out:
1160
1161 return IGC_SUCCESS0;
1162}