| File: | dev/pci/drm/i915/display/intel_sdvo.c |
| Warning: | line 2459, column 21 Value stored to 'sdvo' during its initialization is never read |
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| 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/export.h> |
| 31 | #include <linux/i2c.h> |
| 32 | #include <linux/slab.h> |
| 33 | |
| 34 | #include <drm/display/drm_hdmi_helper.h> |
| 35 | #include <drm/drm_atomic_helper.h> |
| 36 | #include <drm/drm_crtc.h> |
| 37 | #include <drm/drm_edid.h> |
| 38 | |
| 39 | #include "i915_drv.h" |
| 40 | #include "intel_atomic.h" |
| 41 | #include "intel_connector.h" |
| 42 | #include "intel_crtc.h" |
| 43 | #include "intel_de.h" |
| 44 | #include "intel_display_types.h" |
| 45 | #include "intel_fifo_underrun.h" |
| 46 | #include "intel_gmbus.h" |
| 47 | #include "intel_hdmi.h" |
| 48 | #include "intel_hotplug.h" |
| 49 | #include "intel_panel.h" |
| 50 | #include "intel_sdvo.h" |
| 51 | #include "intel_sdvo_regs.h" |
| 52 | |
| 53 | #define SDVO_TMDS_MASK((1 << 0) | (1 << 8)) (SDVO_OUTPUT_TMDS0(1 << 0) | SDVO_OUTPUT_TMDS1(1 << 8)) |
| 54 | #define SDVO_RGB_MASK((1 << 1) | (1 << 9)) (SDVO_OUTPUT_RGB0(1 << 1) | SDVO_OUTPUT_RGB1(1 << 9)) |
| 55 | #define SDVO_LVDS_MASK((1 << 6) | (1 << 14)) (SDVO_OUTPUT_LVDS0(1 << 6) | SDVO_OUTPUT_LVDS1(1 << 14)) |
| 56 | #define SDVO_TV_MASK((1 << 2) | (1 << 3) | (1 << 4)) (SDVO_OUTPUT_CVBS0(1 << 2) | SDVO_OUTPUT_SVID0(1 << 3) | SDVO_OUTPUT_YPRPB0(1 << 4)) |
| 57 | |
| 58 | #define SDVO_OUTPUT_MASK(((1 << 0) | (1 << 8)) | ((1 << 1) | (1 << 9)) | ((1 << 6) | (1 << 14)) | ((1 << 2) | (1 << 3) | (1 << 4))) (SDVO_TMDS_MASK((1 << 0) | (1 << 8)) | SDVO_RGB_MASK((1 << 1) | (1 << 9)) | SDVO_LVDS_MASK((1 << 6) | (1 << 14)) |\ |
| 59 | SDVO_TV_MASK((1 << 2) | (1 << 3) | (1 << 4))) |
| 60 | |
| 61 | #define IS_TV(c)(c->output_flag & ((1 << 2) | (1 << 3) | ( 1 << 4))) (c->output_flag & SDVO_TV_MASK((1 << 2) | (1 << 3) | (1 << 4))) |
| 62 | #define IS_TMDS(c)(c->output_flag & ((1 << 0) | (1 << 8))) (c->output_flag & SDVO_TMDS_MASK((1 << 0) | (1 << 8))) |
| 63 | #define IS_LVDS(c)(c->output_flag & ((1 << 6) | (1 << 14))) (c->output_flag & SDVO_LVDS_MASK((1 << 6) | (1 << 14))) |
| 64 | #define IS_TV_OR_LVDS(c)(c->output_flag & (((1 << 2) | (1 << 3) | ( 1 << 4)) | ((1 << 6) | (1 << 14)))) (c->output_flag & (SDVO_TV_MASK((1 << 2) | (1 << 3) | (1 << 4)) | SDVO_LVDS_MASK((1 << 6) | (1 << 14)))) |
| 65 | #define IS_DIGITAL(c)(c->output_flag & (((1 << 0) | (1 << 8)) | ((1 << 6) | (1 << 14)))) (c->output_flag & (SDVO_TMDS_MASK((1 << 0) | (1 << 8)) | SDVO_LVDS_MASK((1 << 6) | (1 << 14)))) |
| 66 | |
| 67 | |
| 68 | static const char * const tv_format_names[] = { |
| 69 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 70 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 71 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 72 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 73 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 74 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 75 | "SECAM_60" |
| 76 | }; |
| 77 | |
| 78 | #define TV_FORMAT_NUM(sizeof((tv_format_names)) / sizeof((tv_format_names)[0])) ARRAY_SIZE(tv_format_names)(sizeof((tv_format_names)) / sizeof((tv_format_names)[0])) |
| 79 | |
| 80 | struct intel_sdvo { |
| 81 | struct intel_encoder base; |
| 82 | |
| 83 | struct i2c_adapter *i2c; |
| 84 | u8 slave_addr; |
| 85 | |
| 86 | struct i2c_adapter ddc; |
| 87 | |
| 88 | /* Register for the SDVO device: SDVOB or SDVOC */ |
| 89 | i915_reg_t sdvo_reg; |
| 90 | |
| 91 | /* Active outputs controlled by this SDVO output */ |
| 92 | u16 controlled_output; |
| 93 | |
| 94 | /* |
| 95 | * Capabilities of the SDVO device returned by |
| 96 | * intel_sdvo_get_capabilities() |
| 97 | */ |
| 98 | struct intel_sdvo_caps caps; |
| 99 | |
| 100 | u8 colorimetry_cap; |
| 101 | |
| 102 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
| 103 | int pixel_clock_min, pixel_clock_max; |
| 104 | |
| 105 | /* |
| 106 | * For multiple function SDVO device, |
| 107 | * this is for current attached outputs. |
| 108 | */ |
| 109 | u16 attached_output; |
| 110 | |
| 111 | /* |
| 112 | * Hotplug activation bits for this device |
| 113 | */ |
| 114 | u16 hotplug_active; |
| 115 | |
| 116 | enum port port; |
| 117 | |
| 118 | bool_Bool has_hdmi_audio; |
| 119 | |
| 120 | /* DDC bus used by this SDVO encoder */ |
| 121 | u8 ddc_bus; |
| 122 | |
| 123 | /* |
| 124 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd |
| 125 | */ |
| 126 | u8 dtd_sdvo_flags; |
| 127 | }; |
| 128 | |
| 129 | struct intel_sdvo_connector { |
| 130 | struct intel_connector base; |
| 131 | |
| 132 | /* Mark the type of connector */ |
| 133 | u16 output_flag; |
| 134 | |
| 135 | /* This contains all current supported TV format */ |
| 136 | u8 tv_format_supported[TV_FORMAT_NUM(sizeof((tv_format_names)) / sizeof((tv_format_names)[0]))]; |
| 137 | int format_supported_num; |
| 138 | struct drm_property *tv_format; |
| 139 | |
| 140 | /* add the property for the SDVO-TV */ |
| 141 | struct drm_property *left; |
| 142 | struct drm_property *right; |
| 143 | struct drm_property *top; |
| 144 | struct drm_property *bottom; |
| 145 | struct drm_property *hpos; |
| 146 | struct drm_property *vpos; |
| 147 | struct drm_property *contrast; |
| 148 | struct drm_property *saturation; |
| 149 | struct drm_property *hue; |
| 150 | struct drm_property *sharpness; |
| 151 | struct drm_property *flicker_filter; |
| 152 | struct drm_property *flicker_filter_adaptive; |
| 153 | struct drm_property *flicker_filter_2d; |
| 154 | struct drm_property *tv_chroma_filter; |
| 155 | struct drm_property *tv_luma_filter; |
| 156 | struct drm_property *dot_crawl; |
| 157 | |
| 158 | /* add the property for the SDVO-TV/LVDS */ |
| 159 | struct drm_property *brightness; |
| 160 | |
| 161 | /* this is to get the range of margin.*/ |
| 162 | u32 max_hscan, max_vscan; |
| 163 | |
| 164 | /** |
| 165 | * This is set if we treat the device as HDMI, instead of DVI. |
| 166 | */ |
| 167 | bool_Bool is_hdmi; |
| 168 | }; |
| 169 | |
| 170 | struct intel_sdvo_connector_state { |
| 171 | /* base.base: tv.saturation/contrast/hue/brightness */ |
| 172 | struct intel_digital_connector_state base; |
| 173 | |
| 174 | struct { |
| 175 | unsigned overscan_h, overscan_v, hpos, vpos, sharpness; |
| 176 | unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive; |
| 177 | unsigned chroma_filter, luma_filter, dot_crawl; |
| 178 | } tv; |
| 179 | }; |
| 180 | |
| 181 | static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) |
| 182 | { |
| 183 | return container_of(encoder, struct intel_sdvo, base)({ const __typeof( ((struct intel_sdvo *)0)->base ) *__mptr = (encoder); (struct intel_sdvo *)( (char *)__mptr - __builtin_offsetof (struct intel_sdvo, base) );}); |
| 184 | } |
| 185 | |
| 186 | static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector) |
| 187 | { |
| 188 | return to_sdvo(intel_attached_encoder(connector)); |
| 189 | } |
| 190 | |
| 191 | static struct intel_sdvo_connector * |
| 192 | to_intel_sdvo_connector(struct drm_connector *connector) |
| 193 | { |
| 194 | return container_of(connector, struct intel_sdvo_connector, base.base)({ const __typeof( ((struct intel_sdvo_connector *)0)->base .base ) *__mptr = (connector); (struct intel_sdvo_connector * )( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector , base.base) );}); |
| 195 | } |
| 196 | |
| 197 | #define to_intel_sdvo_connector_state(conn_state)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = ((conn_state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}) \ |
| 198 | container_of((conn_state), struct intel_sdvo_connector_state, base.base)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = ((conn_state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}) |
| 199 | |
| 200 | static bool_Bool |
| 201 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags); |
| 202 | static bool_Bool |
| 203 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 204 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 205 | int type); |
| 206 | static bool_Bool |
| 207 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 208 | struct intel_sdvo_connector *intel_sdvo_connector); |
| 209 | |
| 210 | /* |
| 211 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 212 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 213 | * comments in the BIOS). |
| 214 | */ |
| 215 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
| 216 | { |
| 217 | struct drm_device *dev = intel_sdvo->base.base.dev; |
| 218 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 219 | u32 bval = val, cval = val; |
| 220 | int i; |
| 221 | |
| 222 | if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 223 | intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); |
| 224 | intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); |
| 225 | /* |
| 226 | * HW workaround, need to write this twice for issue |
| 227 | * that may result in first write getting masked. |
| 228 | */ |
| 229 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) { |
| 230 | intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); |
| 231 | intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); |
| 232 | } |
| 233 | return; |
| 234 | } |
| 235 | |
| 236 | if (intel_sdvo->port == PORT_B) |
| 237 | cval = intel_de_read(dev_priv, GEN3_SDVOC((const i915_reg_t){ .reg = (0x61160) })); |
| 238 | else |
| 239 | bval = intel_de_read(dev_priv, GEN3_SDVOB((const i915_reg_t){ .reg = (0x61140) })); |
| 240 | |
| 241 | /* |
| 242 | * Write the registers twice for luck. Sometimes, |
| 243 | * writing them only once doesn't appear to 'stick'. |
| 244 | * The BIOS does this too. Yay, magic |
| 245 | */ |
| 246 | for (i = 0; i < 2; i++) { |
| 247 | intel_de_write(dev_priv, GEN3_SDVOB((const i915_reg_t){ .reg = (0x61140) }), bval); |
| 248 | intel_de_posting_read(dev_priv, GEN3_SDVOB((const i915_reg_t){ .reg = (0x61140) })); |
| 249 | |
| 250 | intel_de_write(dev_priv, GEN3_SDVOC((const i915_reg_t){ .reg = (0x61160) }), cval); |
| 251 | intel_de_posting_read(dev_priv, GEN3_SDVOC((const i915_reg_t){ .reg = (0x61160) })); |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | static bool_Bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
| 256 | { |
| 257 | struct i2c_msg msgs[] = { |
| 258 | { |
| 259 | .addr = intel_sdvo->slave_addr, |
| 260 | .flags = 0, |
| 261 | .len = 1, |
| 262 | .buf = &addr, |
| 263 | }, |
| 264 | { |
| 265 | .addr = intel_sdvo->slave_addr, |
| 266 | .flags = I2C_M_RD0x0001, |
| 267 | .len = 1, |
| 268 | .buf = ch, |
| 269 | } |
| 270 | }; |
| 271 | int ret; |
| 272 | |
| 273 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
| 274 | return true1; |
| 275 | |
| 276 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret)___drm_dbg(((void *)0), DRM_UT_KMS, "i2c transfer returned %d\n" , ret); |
| 277 | return false0; |
| 278 | } |
| 279 | |
| 280 | #define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ } |
| 281 | |
| 282 | /** Mapping of command numbers to names, for debug output */ |
| 283 | static const struct { |
| 284 | u8 cmd; |
| 285 | const char *name; |
| 286 | } __packed__attribute__((__packed__)) sdvo_cmd_names[] = { |
| 287 | SDVO_CMD_NAME_ENTRY(RESET), |
| 288 | SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS), |
| 289 | SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV), |
| 290 | SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS), |
| 291 | SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS), |
| 292 | SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS), |
| 293 | SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP), |
| 294 | SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP), |
| 295 | SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS), |
| 296 | SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT), |
| 297 | SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG), |
| 298 | SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG), |
| 299 | SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE), |
| 300 | SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT), |
| 301 | SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT), |
| 302 | SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1), |
| 303 | SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2), |
| 304 | SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1), |
| 305 | SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2), |
| 306 | SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1), |
| 307 | SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2), |
| 308 | SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1), |
| 309 | SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2), |
| 310 | SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING), |
| 311 | SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1), |
| 312 | SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2), |
| 313 | SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE), |
| 314 | SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 315 | SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 316 | SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT), |
| 317 | SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT), |
| 318 | SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS), |
| 319 | SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT), |
| 320 | SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT), |
| 321 | SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES), |
| 322 | SDVO_CMD_NAME_ENTRY(GET_POWER_STATE), |
| 323 | SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE), |
| 324 | SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE), |
| 325 | SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH), |
| 326 | SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT), |
| 327 | SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 328 | SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS), |
| 329 | |
| 330 | /* Add the op code for SDVO enhancements */ |
| 331 | SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS), |
| 332 | SDVO_CMD_NAME_ENTRY(GET_HPOS), |
| 333 | SDVO_CMD_NAME_ENTRY(SET_HPOS), |
| 334 | SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS), |
| 335 | SDVO_CMD_NAME_ENTRY(GET_VPOS), |
| 336 | SDVO_CMD_NAME_ENTRY(SET_VPOS), |
| 337 | SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION), |
| 338 | SDVO_CMD_NAME_ENTRY(GET_SATURATION), |
| 339 | SDVO_CMD_NAME_ENTRY(SET_SATURATION), |
| 340 | SDVO_CMD_NAME_ENTRY(GET_MAX_HUE), |
| 341 | SDVO_CMD_NAME_ENTRY(GET_HUE), |
| 342 | SDVO_CMD_NAME_ENTRY(SET_HUE), |
| 343 | SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST), |
| 344 | SDVO_CMD_NAME_ENTRY(GET_CONTRAST), |
| 345 | SDVO_CMD_NAME_ENTRY(SET_CONTRAST), |
| 346 | SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS), |
| 347 | SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS), |
| 348 | SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS), |
| 349 | SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H), |
| 350 | SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H), |
| 351 | SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H), |
| 352 | SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V), |
| 353 | SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V), |
| 354 | SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V), |
| 355 | SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER), |
| 356 | SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER), |
| 357 | SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER), |
| 358 | SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE), |
| 359 | SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE), |
| 360 | SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE), |
| 361 | SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D), |
| 362 | SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D), |
| 363 | SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D), |
| 364 | SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS), |
| 365 | SDVO_CMD_NAME_ENTRY(GET_SHARPNESS), |
| 366 | SDVO_CMD_NAME_ENTRY(SET_SHARPNESS), |
| 367 | SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL), |
| 368 | SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL), |
| 369 | SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER), |
| 370 | SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER), |
| 371 | SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER), |
| 372 | SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER), |
| 373 | SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER), |
| 374 | SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER), |
| 375 | |
| 376 | /* HDMI op code */ |
| 377 | SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE), |
| 378 | SDVO_CMD_NAME_ENTRY(GET_ENCODE), |
| 379 | SDVO_CMD_NAME_ENTRY(SET_ENCODE), |
| 380 | SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI), |
| 381 | SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI), |
| 382 | SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP), |
| 383 | SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY), |
| 384 | SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY), |
| 385 | SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER), |
| 386 | SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT), |
| 387 | SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT), |
| 388 | SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX), |
| 389 | SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX), |
| 390 | SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO), |
| 391 | SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT), |
| 392 | SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT), |
| 393 | SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE), |
| 394 | SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE), |
| 395 | SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA), |
| 396 | SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA), |
| 397 | }; |
| 398 | |
| 399 | #undef SDVO_CMD_NAME_ENTRY |
| 400 | |
| 401 | static const char *sdvo_cmd_name(u8 cmd) |
| 402 | { |
| 403 | int i; |
| 404 | |
| 405 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names)(sizeof((sdvo_cmd_names)) / sizeof((sdvo_cmd_names)[0])); i++) { |
| 406 | if (cmd == sdvo_cmd_names[i].cmd) |
| 407 | return sdvo_cmd_names[i].name; |
| 408 | } |
| 409 | |
| 410 | return NULL((void *)0); |
| 411 | } |
| 412 | |
| 413 | #define SDVO_NAME(svdo)((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") |
| 414 | |
| 415 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 416 | const void *args, int args_len) |
| 417 | { |
| 418 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_sdvo->base.base.dev); |
| 419 | const char *cmd_name; |
| 420 | int i, pos = 0; |
| 421 | char buffer[64]; |
| 422 | |
| 423 | #define BUF_PRINT(args...) \ |
| 424 | pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0)({ int __max_a = (sizeof(buffer) - pos); int __max_b = (0); __max_a > __max_b ? __max_a : __max_b; }), args) |
| 425 | |
| 426 | for (i = 0; i < args_len; i++) { |
| 427 | BUF_PRINT("%02X ", ((u8 *)args)[i]); |
| 428 | } |
| 429 | for (; i < 8; i++) { |
| 430 | BUF_PRINT(" "); |
| 431 | } |
| 432 | |
| 433 | cmd_name = sdvo_cmd_name(cmd); |
| 434 | if (cmd_name) |
| 435 | BUF_PRINT("(%s)", cmd_name); |
| 436 | else |
| 437 | BUF_PRINT("(%02X)", cmd); |
| 438 | |
| 439 | drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1)({ int __ret = !!((pos >= sizeof(buffer) - 1)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "pos >= sizeof(buffer) - 1" ")"); __builtin_expect(!!(__ret), 0); }); |
| 440 | #undef BUF_PRINT |
| 441 | |
| 442 | DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: W: %02X %s\n", ((intel_sdvo )->port == PORT_B ? "SDVOB" : "SDVOC"), cmd, buffer); |
| 443 | } |
| 444 | |
| 445 | static const char * const cmd_status_names[] = { |
| 446 | [SDVO_CMD_STATUS_POWER_ON0x0] = "Power on", |
| 447 | [SDVO_CMD_STATUS_SUCCESS0x1] = "Success", |
| 448 | [SDVO_CMD_STATUS_NOTSUPP0x2] = "Not supported", |
| 449 | [SDVO_CMD_STATUS_INVALID_ARG0x3] = "Invalid arg", |
| 450 | [SDVO_CMD_STATUS_PENDING0x4] = "Pending", |
| 451 | [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED0x5] = "Target not specified", |
| 452 | [SDVO_CMD_STATUS_SCALING_NOT_SUPP0x6] = "Scaling not supported", |
| 453 | }; |
| 454 | |
| 455 | static const char *sdvo_cmd_status(u8 status) |
| 456 | { |
| 457 | if (status < ARRAY_SIZE(cmd_status_names)(sizeof((cmd_status_names)) / sizeof((cmd_status_names)[0]))) |
| 458 | return cmd_status_names[status]; |
| 459 | else |
| 460 | return NULL((void *)0); |
| 461 | } |
| 462 | |
| 463 | static bool_Bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 464 | const void *args, int args_len, |
| 465 | bool_Bool unlocked) |
| 466 | { |
| 467 | u8 *buf, status; |
| 468 | struct i2c_msg *msgs; |
| 469 | int i, ret = true1; |
| 470 | |
| 471 | /* Would be simpler to allocate both in one go ? */ |
| 472 | buf = kzalloc(args_len * 2 + 2, GFP_KERNEL(0x0001 | 0x0004)); |
| 473 | if (!buf) |
| 474 | return false0; |
| 475 | |
| 476 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL(0x0001 | 0x0004)); |
| 477 | if (!msgs) { |
| 478 | kfree(buf); |
| 479 | return false0; |
| 480 | } |
| 481 | |
| 482 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
| 483 | |
| 484 | for (i = 0; i < args_len; i++) { |
| 485 | msgs[i].addr = intel_sdvo->slave_addr; |
| 486 | msgs[i].flags = 0; |
| 487 | msgs[i].len = 2; |
| 488 | msgs[i].buf = buf + 2 *i; |
| 489 | buf[2*i + 0] = SDVO_I2C_ARG_00x07 - i; |
| 490 | buf[2*i + 1] = ((u8*)args)[i]; |
| 491 | } |
| 492 | msgs[i].addr = intel_sdvo->slave_addr; |
| 493 | msgs[i].flags = 0; |
| 494 | msgs[i].len = 2; |
| 495 | msgs[i].buf = buf + 2*i; |
| 496 | buf[2*i + 0] = SDVO_I2C_OPCODE0x08; |
| 497 | buf[2*i + 1] = cmd; |
| 498 | |
| 499 | /* the following two are to read the response */ |
| 500 | status = SDVO_I2C_CMD_STATUS0x09; |
| 501 | msgs[i+1].addr = intel_sdvo->slave_addr; |
| 502 | msgs[i+1].flags = 0; |
| 503 | msgs[i+1].len = 1; |
| 504 | msgs[i+1].buf = &status; |
| 505 | |
| 506 | msgs[i+2].addr = intel_sdvo->slave_addr; |
| 507 | msgs[i+2].flags = I2C_M_RD0x0001; |
| 508 | msgs[i+2].len = 1; |
| 509 | msgs[i+2].buf = &status; |
| 510 | |
| 511 | if (unlocked) |
| 512 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
| 513 | else |
| 514 | ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); |
| 515 | if (ret < 0) { |
| 516 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret)___drm_dbg(((void *)0), DRM_UT_KMS, "I2c transfer returned %d\n" , ret); |
| 517 | ret = false0; |
| 518 | goto out; |
| 519 | } |
| 520 | if (ret != i+3) { |
| 521 | /* failure in I2C transfer */ |
| 522 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3)___drm_dbg(((void *)0), DRM_UT_KMS, "I2c transfer returned %d/%d\n" , ret, i+3); |
| 523 | ret = false0; |
| 524 | } |
| 525 | |
| 526 | out: |
| 527 | kfree(msgs); |
| 528 | kfree(buf); |
| 529 | return ret; |
| 530 | } |
| 531 | |
| 532 | static bool_Bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 533 | const void *args, int args_len) |
| 534 | { |
| 535 | return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true1); |
| 536 | } |
| 537 | |
| 538 | static bool_Bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
| 539 | void *response, int response_len) |
| 540 | { |
| 541 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_sdvo->base.base.dev); |
| 542 | const char *cmd_status; |
| 543 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
| 544 | u8 status; |
| 545 | int i, pos = 0; |
| 546 | char buffer[64]; |
| 547 | |
| 548 | buffer[0] = '\0'; |
| 549 | |
| 550 | /* |
| 551 | * The documentation states that all commands will be |
| 552 | * processed within 15µs, and that we need only poll |
| 553 | * the status byte a maximum of 3 times in order for the |
| 554 | * command to be complete. |
| 555 | * |
| 556 | * Check 5 times in case the hardware failed to read the docs. |
| 557 | * |
| 558 | * Also beware that the first response by many devices is to |
| 559 | * reply PENDING and stall for time. TVs are notorious for |
| 560 | * requiring longer than specified to complete their replies. |
| 561 | * Originally (in the DDX long ago), the delay was only ever 15ms |
| 562 | * with an additional delay of 30ms applied for TVs added later after |
| 563 | * many experiments. To accommodate both sets of delays, we do a |
| 564 | * sequence of slow checks if the device is falling behind and fails |
| 565 | * to reply within 5*15µs. |
| 566 | */ |
| 567 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 568 | SDVO_I2C_CMD_STATUS0x09, |
| 569 | &status)) |
| 570 | goto log_fail; |
| 571 | |
| 572 | while ((status == SDVO_CMD_STATUS_PENDING0x4 || |
| 573 | status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED0x5) && --retry) { |
| 574 | if (retry < 10) |
| 575 | drm_msleep(15)mdelay(15); |
| 576 | else |
| 577 | udelay(15); |
| 578 | |
| 579 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 580 | SDVO_I2C_CMD_STATUS0x09, |
| 581 | &status)) |
| 582 | goto log_fail; |
| 583 | } |
| 584 | |
| 585 | #define BUF_PRINT(args...) \ |
| 586 | pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0)({ int __max_a = (sizeof(buffer) - pos); int __max_b = (0); __max_a > __max_b ? __max_a : __max_b; }), args) |
| 587 | |
| 588 | cmd_status = sdvo_cmd_status(status); |
| 589 | if (cmd_status) |
| 590 | BUF_PRINT("(%s)", cmd_status); |
| 591 | else |
| 592 | BUF_PRINT("(??? %d)", status); |
| 593 | |
| 594 | if (status != SDVO_CMD_STATUS_SUCCESS0x1) |
| 595 | goto log_fail; |
| 596 | |
| 597 | /* Read the command response */ |
| 598 | for (i = 0; i < response_len; i++) { |
| 599 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 600 | SDVO_I2C_RETURN_00x0a + i, |
| 601 | &((u8 *)response)[i])) |
| 602 | goto log_fail; |
| 603 | BUF_PRINT(" %02X", ((u8 *)response)[i]); |
| 604 | } |
| 605 | |
| 606 | drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1)({ int __ret = !!((pos >= sizeof(buffer) - 1)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "pos >= sizeof(buffer) - 1" ")"); __builtin_expect(!!(__ret), 0); }); |
| 607 | #undef BUF_PRINT |
| 608 | |
| 609 | DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: R: %s\n", ((intel_sdvo )->port == PORT_B ? "SDVOB" : "SDVOC"), buffer); |
| 610 | return true1; |
| 611 | |
| 612 | log_fail: |
| 613 | DRM_DEBUG_KMS("%s: R: ... failed %s\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: R: ... failed %s\n", ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), buffer ) |
| 614 | SDVO_NAME(intel_sdvo), buffer)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: R: ... failed %s\n", ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), buffer ); |
| 615 | return false0; |
| 616 | } |
| 617 | |
| 618 | static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) |
| 619 | { |
| 620 | if (adjusted_mode->crtc_clock >= 100000) |
| 621 | return 1; |
| 622 | else if (adjusted_mode->crtc_clock >= 50000) |
| 623 | return 2; |
| 624 | else |
| 625 | return 4; |
| 626 | } |
| 627 | |
| 628 | static bool_Bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
| 629 | u8 ddc_bus) |
| 630 | { |
| 631 | /* This must be the immediately preceding write before the i2c xfer */ |
| 632 | return __intel_sdvo_write_cmd(intel_sdvo, |
| 633 | SDVO_CMD_SET_CONTROL_BUS_SWITCH0x7a, |
| 634 | &ddc_bus, 1, false0); |
| 635 | } |
| 636 | |
| 637 | static bool_Bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
| 638 | { |
| 639 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
| 640 | return false0; |
| 641 | |
| 642 | return intel_sdvo_read_response(intel_sdvo, NULL((void *)0), 0); |
| 643 | } |
| 644 | |
| 645 | static bool_Bool |
| 646 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
| 647 | { |
| 648 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL((void *)0), 0)) |
| 649 | return false0; |
| 650 | |
| 651 | return intel_sdvo_read_response(intel_sdvo, value, len); |
| 652 | } |
| 653 | |
| 654 | static bool_Bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
| 655 | { |
| 656 | struct intel_sdvo_set_target_input_args targets = {0}; |
| 657 | return intel_sdvo_set_value(intel_sdvo, |
| 658 | SDVO_CMD_SET_TARGET_INPUT0x10, |
| 659 | &targets, sizeof(targets)); |
| 660 | } |
| 661 | |
| 662 | /* |
| 663 | * Return whether each input is trained. |
| 664 | * |
| 665 | * This function is making an assumption about the layout of the response, |
| 666 | * which should be checked against the docs. |
| 667 | */ |
| 668 | static bool_Bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool_Bool *input_1, bool_Bool *input_2) |
| 669 | { |
| 670 | struct intel_sdvo_get_trained_inputs_response response; |
| 671 | |
| 672 | BUILD_BUG_ON(sizeof(response) != 1)extern char _ctassert[(!(sizeof(response) != 1)) ? 1 : -1 ] __attribute__ ((__unused__)); |
| 673 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS0x03, |
| 674 | &response, sizeof(response))) |
| 675 | return false0; |
| 676 | |
| 677 | *input_1 = response.input0_trained; |
| 678 | *input_2 = response.input1_trained; |
| 679 | return true1; |
| 680 | } |
| 681 | |
| 682 | static bool_Bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
| 683 | u16 outputs) |
| 684 | { |
| 685 | return intel_sdvo_set_value(intel_sdvo, |
| 686 | SDVO_CMD_SET_ACTIVE_OUTPUTS0x05, |
| 687 | &outputs, sizeof(outputs)); |
| 688 | } |
| 689 | |
| 690 | static bool_Bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
| 691 | u16 *outputs) |
| 692 | { |
| 693 | return intel_sdvo_get_value(intel_sdvo, |
| 694 | SDVO_CMD_GET_ACTIVE_OUTPUTS0x04, |
| 695 | outputs, sizeof(*outputs)); |
| 696 | } |
| 697 | |
| 698 | static bool_Bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
| 699 | int mode) |
| 700 | { |
| 701 | u8 state = SDVO_ENCODER_STATE_ON(1 << 0); |
| 702 | |
| 703 | switch (mode) { |
| 704 | case DRM_MODE_DPMS_ON0: |
| 705 | state = SDVO_ENCODER_STATE_ON(1 << 0); |
| 706 | break; |
| 707 | case DRM_MODE_DPMS_STANDBY1: |
| 708 | state = SDVO_ENCODER_STATE_STANDBY(1 << 1); |
| 709 | break; |
| 710 | case DRM_MODE_DPMS_SUSPEND2: |
| 711 | state = SDVO_ENCODER_STATE_SUSPEND(1 << 2); |
| 712 | break; |
| 713 | case DRM_MODE_DPMS_OFF3: |
| 714 | state = SDVO_ENCODER_STATE_OFF(1 << 3); |
| 715 | break; |
| 716 | } |
| 717 | |
| 718 | return intel_sdvo_set_value(intel_sdvo, |
| 719 | SDVO_CMD_SET_ENCODER_POWER_STATE0x2c, &state, sizeof(state)); |
| 720 | } |
| 721 | |
| 722 | static bool_Bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
| 723 | int *clock_min, |
| 724 | int *clock_max) |
| 725 | { |
| 726 | struct intel_sdvo_pixel_clock_range clocks; |
| 727 | |
| 728 | BUILD_BUG_ON(sizeof(clocks) != 4)extern char _ctassert[(!(sizeof(clocks) != 4)) ? 1 : -1 ] __attribute__ ((__unused__)); |
| 729 | if (!intel_sdvo_get_value(intel_sdvo, |
| 730 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE0x1d, |
| 731 | &clocks, sizeof(clocks))) |
| 732 | return false0; |
| 733 | |
| 734 | /* Convert the values from units of 10 kHz to kHz. */ |
| 735 | *clock_min = clocks.min * 10; |
| 736 | *clock_max = clocks.max * 10; |
| 737 | return true1; |
| 738 | } |
| 739 | |
| 740 | static bool_Bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
| 741 | u16 outputs) |
| 742 | { |
| 743 | return intel_sdvo_set_value(intel_sdvo, |
| 744 | SDVO_CMD_SET_TARGET_OUTPUT0x11, |
| 745 | &outputs, sizeof(outputs)); |
| 746 | } |
| 747 | |
| 748 | static bool_Bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 749 | struct intel_sdvo_dtd *dtd) |
| 750 | { |
| 751 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 752 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
| 753 | } |
| 754 | |
| 755 | static bool_Bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 756 | struct intel_sdvo_dtd *dtd) |
| 757 | { |
| 758 | return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 759 | intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
| 760 | } |
| 761 | |
| 762 | static bool_Bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
| 763 | struct intel_sdvo_dtd *dtd) |
| 764 | { |
| 765 | return intel_sdvo_set_timing(intel_sdvo, |
| 766 | SDVO_CMD_SET_INPUT_TIMINGS_PART10x14, dtd); |
| 767 | } |
| 768 | |
| 769 | static bool_Bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
| 770 | struct intel_sdvo_dtd *dtd) |
| 771 | { |
| 772 | return intel_sdvo_set_timing(intel_sdvo, |
| 773 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART10x16, dtd); |
| 774 | } |
| 775 | |
| 776 | static bool_Bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, |
| 777 | struct intel_sdvo_dtd *dtd) |
| 778 | { |
| 779 | return intel_sdvo_get_timing(intel_sdvo, |
| 780 | SDVO_CMD_GET_INPUT_TIMINGS_PART10x12, dtd); |
| 781 | } |
| 782 | |
| 783 | static bool_Bool |
| 784 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
| 785 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 786 | const struct drm_display_mode *mode) |
| 787 | { |
| 788 | struct intel_sdvo_preferred_input_timing_args args; |
| 789 | |
| 790 | memset(&args, 0, sizeof(args))__builtin_memset((&args), (0), (sizeof(args))); |
| 791 | args.clock = mode->clock / 10; |
| 792 | args.width = mode->hdisplay; |
| 793 | args.height = mode->vdisplay; |
| 794 | args.interlace = 0; |
| 795 | |
| 796 | if (IS_LVDS(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 6) | (1 << 14)))) { |
| 797 | const struct drm_display_mode *fixed_mode = |
| 798 | intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); |
| 799 | |
| 800 | if (fixed_mode->hdisplay != args.width || |
| 801 | fixed_mode->vdisplay != args.height) |
| 802 | args.scaled = 1; |
| 803 | } |
| 804 | |
| 805 | return intel_sdvo_set_value(intel_sdvo, |
| 806 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING0x1a, |
| 807 | &args, sizeof(args)); |
| 808 | } |
| 809 | |
| 810 | static bool_Bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
| 811 | struct intel_sdvo_dtd *dtd) |
| 812 | { |
| 813 | BUILD_BUG_ON(sizeof(dtd->part1) != 8)extern char _ctassert[(!(sizeof(dtd->part1) != 8)) ? 1 : - 1 ] __attribute__((__unused__)); |
| 814 | BUILD_BUG_ON(sizeof(dtd->part2) != 8)extern char _ctassert[(!(sizeof(dtd->part2) != 8)) ? 1 : - 1 ] __attribute__((__unused__)); |
| 815 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART10x1b, |
| 816 | &dtd->part1, sizeof(dtd->part1)) && |
| 817 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART20x1c, |
| 818 | &dtd->part2, sizeof(dtd->part2)); |
| 819 | } |
| 820 | |
| 821 | static bool_Bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
| 822 | { |
| 823 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT0x21, &val, 1); |
| 824 | } |
| 825 | |
| 826 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
| 827 | const struct drm_display_mode *mode) |
| 828 | { |
| 829 | u16 width, height; |
| 830 | u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 831 | u16 h_sync_offset, v_sync_offset; |
| 832 | int mode_clock; |
| 833 | |
| 834 | memset(dtd, 0, sizeof(*dtd))__builtin_memset((dtd), (0), (sizeof(*dtd))); |
| 835 | |
| 836 | width = mode->hdisplay; |
| 837 | height = mode->vdisplay; |
| 838 | |
| 839 | /* do some mode translations */ |
| 840 | h_blank_len = mode->htotal - mode->hdisplay; |
| 841 | h_sync_len = mode->hsync_end - mode->hsync_start; |
| 842 | |
| 843 | v_blank_len = mode->vtotal - mode->vdisplay; |
| 844 | v_sync_len = mode->vsync_end - mode->vsync_start; |
| 845 | |
| 846 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
| 847 | v_sync_offset = mode->vsync_start - mode->vdisplay; |
| 848 | |
| 849 | mode_clock = mode->clock; |
| 850 | mode_clock /= 10; |
| 851 | dtd->part1.clock = mode_clock; |
| 852 | |
| 853 | dtd->part1.h_active = width & 0xff; |
| 854 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 855 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
| 856 | ((h_blank_len >> 8) & 0xf); |
| 857 | dtd->part1.v_active = height & 0xff; |
| 858 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 859 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
| 860 | ((v_blank_len >> 8) & 0xf); |
| 861 | |
| 862 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
| 863 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 864 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
| 865 | (v_sync_len & 0xf); |
| 866 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
| 867 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 868 | ((v_sync_len & 0x30) >> 4); |
| 869 | |
| 870 | dtd->part2.dtd_flags = 0x18; |
| 871 | if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 872 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE(1 << 7); |
| 873 | if (mode->flags & DRM_MODE_FLAG_PHSYNC(1<<0)) |
| 874 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE(1 << 1); |
| 875 | if (mode->flags & DRM_MODE_FLAG_PVSYNC(1<<2)) |
| 876 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE(1 << 2); |
| 877 | |
| 878 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
| 879 | } |
| 880 | |
| 881 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, |
| 882 | const struct intel_sdvo_dtd *dtd) |
| 883 | { |
| 884 | struct drm_display_mode mode = {}; |
| 885 | |
| 886 | mode.hdisplay = dtd->part1.h_active; |
| 887 | mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 888 | mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; |
| 889 | mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
| 890 | mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; |
| 891 | mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 892 | mode.htotal = mode.hdisplay + dtd->part1.h_blank; |
| 893 | mode.htotal += (dtd->part1.h_high & 0xf) << 8; |
| 894 | |
| 895 | mode.vdisplay = dtd->part1.v_active; |
| 896 | mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 897 | mode.vsync_start = mode.vdisplay; |
| 898 | mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
| 899 | mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
| 900 | mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 901 | mode.vsync_end = mode.vsync_start + |
| 902 | (dtd->part2.v_sync_off_width & 0xf); |
| 903 | mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 904 | mode.vtotal = mode.vdisplay + dtd->part1.v_blank; |
| 905 | mode.vtotal += (dtd->part1.v_high & 0xf) << 8; |
| 906 | |
| 907 | mode.clock = dtd->part1.clock * 10; |
| 908 | |
| 909 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE(1 << 7)) |
| 910 | mode.flags |= DRM_MODE_FLAG_INTERLACE(1<<4); |
| 911 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE(1 << 1)) |
| 912 | mode.flags |= DRM_MODE_FLAG_PHSYNC(1<<0); |
| 913 | else |
| 914 | mode.flags |= DRM_MODE_FLAG_NHSYNC(1<<1); |
| 915 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE(1 << 2)) |
| 916 | mode.flags |= DRM_MODE_FLAG_PVSYNC(1<<2); |
| 917 | else |
| 918 | mode.flags |= DRM_MODE_FLAG_NVSYNC(1<<3); |
| 919 | |
| 920 | drm_mode_set_crtcinfo(&mode, 0); |
| 921 | |
| 922 | drm_mode_copy(pmode, &mode); |
| 923 | } |
| 924 | |
| 925 | static bool_Bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
| 926 | { |
| 927 | struct intel_sdvo_encode encode; |
| 928 | |
| 929 | BUILD_BUG_ON(sizeof(encode) != 2)extern char _ctassert[(!(sizeof(encode) != 2)) ? 1 : -1 ] __attribute__ ((__unused__)); |
| 930 | return intel_sdvo_get_value(intel_sdvo, |
| 931 | SDVO_CMD_GET_SUPP_ENCODE0x9d, |
| 932 | &encode, sizeof(encode)); |
| 933 | } |
| 934 | |
| 935 | static bool_Bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
| 936 | u8 mode) |
| 937 | { |
| 938 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE0x9f, &mode, 1); |
| 939 | } |
| 940 | |
| 941 | static bool_Bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
| 942 | u8 mode) |
| 943 | { |
| 944 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY0x8e, &mode, 1); |
| 945 | } |
| 946 | |
| 947 | static bool_Bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo, |
| 948 | u8 pixel_repeat) |
| 949 | { |
| 950 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI0x8b, |
| 951 | &pixel_repeat, 1); |
| 952 | } |
| 953 | |
| 954 | static bool_Bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, |
| 955 | u8 audio_state) |
| 956 | { |
| 957 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT0x91, |
| 958 | &audio_state, 1); |
| 959 | } |
| 960 | |
| 961 | static bool_Bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo, |
| 962 | u8 *hbuf_size) |
| 963 | { |
| 964 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO0x95, |
| 965 | hbuf_size, 1)) |
| 966 | return false0; |
| 967 | |
| 968 | /* Buffer size is 0 based, hooray! However zero means zero. */ |
| 969 | if (*hbuf_size) |
| 970 | (*hbuf_size)++; |
| 971 | |
| 972 | return true1; |
| 973 | } |
| 974 | |
| 975 | #if 0 |
| 976 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
| 977 | { |
| 978 | int i, j; |
| 979 | u8 set_buf_index[2]; |
| 980 | u8 av_split; |
| 981 | u8 buf_size; |
| 982 | u8 buf[48]; |
| 983 | u8 *pos; |
| 984 | |
| 985 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT0x97, &av_split, 1); |
| 986 | |
| 987 | for (i = 0; i <= av_split; i++) { |
| 988 | set_buf_index[0] = i; set_buf_index[1] = 0; |
| 989 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX0x93, |
| 990 | set_buf_index, 2); |
| 991 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO0x95, NULL((void *)0), 0); |
| 992 | intel_sdvo_read_response(encoder, &buf_size, 1); |
| 993 | |
| 994 | pos = buf; |
| 995 | for (j = 0; j <= buf_size; j += 8) { |
| 996 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA0x99, |
| 997 | NULL((void *)0), 0); |
| 998 | intel_sdvo_read_response(encoder, pos, 8); |
| 999 | pos += 8; |
| 1000 | } |
| 1001 | } |
| 1002 | } |
| 1003 | #endif |
| 1004 | |
| 1005 | static bool_Bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
| 1006 | unsigned int if_index, u8 tx_rate, |
| 1007 | const u8 *data, unsigned int length) |
| 1008 | { |
| 1009 | u8 set_buf_index[2] = { if_index, 0 }; |
| 1010 | u8 hbuf_size, tmp[8]; |
| 1011 | int i; |
| 1012 | |
| 1013 | if (!intel_sdvo_set_value(intel_sdvo, |
| 1014 | SDVO_CMD_SET_HBUF_INDEX0x93, |
| 1015 | set_buf_index, 2)) |
| 1016 | return false0; |
| 1017 | |
| 1018 | if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) |
| 1019 | return false0; |
| 1020 | |
| 1021 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",___drm_dbg(((void *)0), DRM_UT_KMS, "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n" , if_index, length, hbuf_size) |
| 1022 | if_index, length, hbuf_size)___drm_dbg(((void *)0), DRM_UT_KMS, "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n" , if_index, length, hbuf_size); |
| 1023 | |
| 1024 | if (hbuf_size < length) |
| 1025 | return false0; |
| 1026 | |
| 1027 | for (i = 0; i < hbuf_size; i += 8) { |
| 1028 | memset(tmp, 0, 8)__builtin_memset((tmp), (0), (8)); |
| 1029 | if (i < length) |
| 1030 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i))__builtin_memcpy((tmp), (data + i), (({ unsigned __min_a = (8 ); unsigned __min_b = (length - i); __min_a < __min_b ? __min_a : __min_b; }))); |
| 1031 | |
| 1032 | if (!intel_sdvo_set_value(intel_sdvo, |
| 1033 | SDVO_CMD_SET_HBUF_DATA0x98, |
| 1034 | tmp, 8)) |
| 1035 | return false0; |
| 1036 | } |
| 1037 | |
| 1038 | return intel_sdvo_set_value(intel_sdvo, |
| 1039 | SDVO_CMD_SET_HBUF_TXRATE0x9a, |
| 1040 | &tx_rate, 1); |
| 1041 | } |
| 1042 | |
| 1043 | static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, |
| 1044 | unsigned int if_index, |
| 1045 | u8 *data, unsigned int length) |
| 1046 | { |
| 1047 | u8 set_buf_index[2] = { if_index, 0 }; |
| 1048 | u8 hbuf_size, tx_rate, av_split; |
| 1049 | int i; |
| 1050 | |
| 1051 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1052 | SDVO_CMD_GET_HBUF_AV_SPLIT0x97, |
| 1053 | &av_split, 1)) |
| 1054 | return -ENXIO6; |
| 1055 | |
| 1056 | if (av_split < if_index) |
| 1057 | return 0; |
| 1058 | |
| 1059 | if (!intel_sdvo_set_value(intel_sdvo, |
| 1060 | SDVO_CMD_SET_HBUF_INDEX0x93, |
| 1061 | set_buf_index, 2)) |
| 1062 | return -ENXIO6; |
| 1063 | |
| 1064 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1065 | SDVO_CMD_GET_HBUF_TXRATE0x9b, |
| 1066 | &tx_rate, 1)) |
| 1067 | return -ENXIO6; |
| 1068 | |
| 1069 | if (tx_rate == SDVO_HBUF_TX_DISABLED(0 << 6)) |
| 1070 | return 0; |
| 1071 | |
| 1072 | if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) |
| 1073 | return false0; |
| 1074 | |
| 1075 | DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",___drm_dbg(((void *)0), DRM_UT_KMS, "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n" , if_index, length, hbuf_size) |
| 1076 | if_index, length, hbuf_size)___drm_dbg(((void *)0), DRM_UT_KMS, "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n" , if_index, length, hbuf_size); |
| 1077 | |
| 1078 | hbuf_size = min_t(unsigned int, length, hbuf_size)({ unsigned int __min_a = (length); unsigned int __min_b = (hbuf_size ); __min_a < __min_b ? __min_a : __min_b; }); |
| 1079 | |
| 1080 | for (i = 0; i < hbuf_size; i += 8) { |
| 1081 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA0x99, NULL((void *)0), 0)) |
| 1082 | return -ENXIO6; |
| 1083 | if (!intel_sdvo_read_response(intel_sdvo, &data[i], |
| 1084 | min_t(unsigned int, 8, hbuf_size - i)({ unsigned int __min_a = (8); unsigned int __min_b = (hbuf_size - i); __min_a < __min_b ? __min_a : __min_b; }))) |
| 1085 | return -ENXIO6; |
| 1086 | } |
| 1087 | |
| 1088 | return hbuf_size; |
| 1089 | } |
| 1090 | |
| 1091 | static bool_Bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, |
| 1092 | struct intel_crtc_state *crtc_state, |
| 1093 | struct drm_connector_state *conn_state) |
| 1094 | { |
| 1095 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_sdvo->base.base.dev); |
| 1096 | struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; |
| 1097 | const struct drm_display_mode *adjusted_mode = |
| 1098 | &crtc_state->hw.adjusted_mode; |
| 1099 | int ret; |
| 1100 | |
| 1101 | if (!crtc_state->has_hdmi_sink) |
| 1102 | return true1; |
| 1103 | |
| 1104 | crtc_state->infoframes.enable |= |
| 1105 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); |
| 1106 | |
| 1107 | ret = drm_hdmi_avi_infoframe_from_display_mode(frame, |
| 1108 | conn_state->connector, |
| 1109 | adjusted_mode); |
| 1110 | if (ret) |
| 1111 | return false0; |
| 1112 | |
| 1113 | drm_hdmi_avi_infoframe_quant_range(frame, |
| 1114 | conn_state->connector, |
| 1115 | adjusted_mode, |
| 1116 | crtc_state->limited_color_range ? |
| 1117 | HDMI_QUANTIZATION_RANGE_LIMITED : |
| 1118 | HDMI_QUANTIZATION_RANGE_FULL); |
| 1119 | |
| 1120 | ret = hdmi_avi_infoframe_check(frame); |
| 1121 | if (drm_WARN_ON(&dev_priv->drm, ret)({ int __ret = !!((ret)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "ret" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1122 | return false0; |
| 1123 | |
| 1124 | return true1; |
| 1125 | } |
| 1126 | |
| 1127 | static bool_Bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
| 1128 | const struct intel_crtc_state *crtc_state) |
| 1129 | { |
| 1130 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_sdvo->base.base.dev); |
| 1131 | u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)(4 + 13)]; |
| 1132 | const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; |
| 1133 | ssize_t len; |
| 1134 | |
| 1135 | if ((crtc_state->infoframes.enable & |
| 1136 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) |
| 1137 | return true1; |
| 1138 | |
| 1139 | if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((frame->any.type != HDMI_INFOFRAME_TYPE_AVI )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "frame->any.type != HDMI_INFOFRAME_TYPE_AVI" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1140 | frame->any.type != HDMI_INFOFRAME_TYPE_AVI)({ int __ret = !!((frame->any.type != HDMI_INFOFRAME_TYPE_AVI )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "frame->any.type != HDMI_INFOFRAME_TYPE_AVI" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1141 | return false0; |
| 1142 | |
| 1143 | len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); |
| 1144 | if (drm_WARN_ON(&dev_priv->drm, len < 0)({ int __ret = !!((len < 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "len < 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1145 | return false0; |
| 1146 | |
| 1147 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF1, |
| 1148 | SDVO_HBUF_TX_VSYNC(3 << 6), |
| 1149 | sdvo_data, len); |
| 1150 | } |
| 1151 | |
| 1152 | static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, |
| 1153 | struct intel_crtc_state *crtc_state) |
| 1154 | { |
| 1155 | u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)(4 + 13)]; |
| 1156 | union hdmi_infoframe *frame = &crtc_state->infoframes.avi; |
| 1157 | ssize_t len; |
| 1158 | int ret; |
| 1159 | |
| 1160 | if (!crtc_state->has_hdmi_sink) |
| 1161 | return; |
| 1162 | |
| 1163 | len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF1, |
| 1164 | sdvo_data, sizeof(sdvo_data)); |
| 1165 | if (len < 0) { |
| 1166 | DRM_DEBUG_KMS("failed to read AVI infoframe\n")___drm_dbg(((void *)0), DRM_UT_KMS, "failed to read AVI infoframe\n" ); |
| 1167 | return; |
| 1168 | } else if (len == 0) { |
| 1169 | return; |
| 1170 | } |
| 1171 | |
| 1172 | crtc_state->infoframes.enable |= |
| 1173 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); |
| 1174 | |
| 1175 | ret = hdmi_infoframe_unpack(frame, sdvo_data, len); |
| 1176 | if (ret) { |
| 1177 | DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Failed to unpack AVI infoframe\n" ); |
| 1178 | return; |
| 1179 | } |
| 1180 | |
| 1181 | if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) |
| 1182 | DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Found the wrong infoframe type 0x%x (expected 0x%02x)\n" , frame->any.type, HDMI_INFOFRAME_TYPE_AVI) |
| 1183 | frame->any.type, HDMI_INFOFRAME_TYPE_AVI)___drm_dbg(((void *)0), DRM_UT_KMS, "Found the wrong infoframe type 0x%x (expected 0x%02x)\n" , frame->any.type, HDMI_INFOFRAME_TYPE_AVI); |
| 1184 | } |
| 1185 | |
| 1186 | static bool_Bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, |
| 1187 | const struct drm_connector_state *conn_state) |
| 1188 | { |
| 1189 | struct intel_sdvo_tv_format format; |
| 1190 | u32 format_map; |
| 1191 | |
| 1192 | format_map = 1 << conn_state->tv.mode; |
| 1193 | memset(&format, 0, sizeof(format))__builtin_memset((&format), (0), (sizeof(format))); |
| 1194 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)))__builtin_memcpy((&format), (&format_map), ((((sizeof (format))<(sizeof(format_map)))?(sizeof(format)):(sizeof(format_map ))))); |
| 1195 | |
| 1196 | BUILD_BUG_ON(sizeof(format) != 6)extern char _ctassert[(!(sizeof(format) != 6)) ? 1 : -1 ] __attribute__ ((__unused__)); |
| 1197 | return intel_sdvo_set_value(intel_sdvo, |
| 1198 | SDVO_CMD_SET_TV_FORMAT0x29, |
| 1199 | &format, sizeof(format)); |
| 1200 | } |
| 1201 | |
| 1202 | static bool_Bool |
| 1203 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
| 1204 | const struct drm_display_mode *mode) |
| 1205 | { |
| 1206 | struct intel_sdvo_dtd output_dtd; |
| 1207 | |
| 1208 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1209 | intel_sdvo->attached_output)) |
| 1210 | return false0; |
| 1211 | |
| 1212 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
| 1213 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 1214 | return false0; |
| 1215 | |
| 1216 | return true1; |
| 1217 | } |
| 1218 | |
| 1219 | /* |
| 1220 | * Asks the sdvo controller for the preferred input mode given the output mode. |
| 1221 | * Unfortunately we have to set up the full output mode to do that. |
| 1222 | */ |
| 1223 | static bool_Bool |
| 1224 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
| 1225 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 1226 | const struct drm_display_mode *mode, |
| 1227 | struct drm_display_mode *adjusted_mode) |
| 1228 | { |
| 1229 | struct intel_sdvo_dtd input_dtd; |
| 1230 | |
| 1231 | /* Reset the input timing to the screen. Assume always input 0. */ |
| 1232 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1233 | return false0; |
| 1234 | |
| 1235 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
| 1236 | intel_sdvo_connector, |
| 1237 | mode)) |
| 1238 | return false0; |
| 1239 | |
| 1240 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
| 1241 | &input_dtd)) |
| 1242 | return false0; |
| 1243 | |
| 1244 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
| 1245 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
| 1246 | |
| 1247 | return true1; |
| 1248 | } |
| 1249 | |
| 1250 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) |
| 1251 | { |
| 1252 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(pipe_config->uapi.crtc->dev); |
| 1253 | unsigned dotclock = pipe_config->port_clock; |
| 1254 | struct dpll *clock = &pipe_config->dpll; |
| 1255 | |
| 1256 | /* |
| 1257 | * SDVO TV has fixed PLL values depend on its clock range, |
| 1258 | * this mirrors vbios setting. |
| 1259 | */ |
| 1260 | if (dotclock >= 100000 && dotclock < 140500) { |
| 1261 | clock->p1 = 2; |
| 1262 | clock->p2 = 10; |
| 1263 | clock->n = 3; |
| 1264 | clock->m1 = 16; |
| 1265 | clock->m2 = 8; |
| 1266 | } else if (dotclock >= 140500 && dotclock <= 200000) { |
| 1267 | clock->p1 = 1; |
| 1268 | clock->p2 = 10; |
| 1269 | clock->n = 6; |
| 1270 | clock->m1 = 12; |
| 1271 | clock->m2 = 8; |
| 1272 | } else { |
| 1273 | drm_WARN(&dev_priv->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "SDVO TV clock out of range: %i\n" , dev_driver_string((&dev_priv->drm)->dev), "", dotclock ); __builtin_expect(!!(__ret), 0); }) |
| 1274 | "SDVO TV clock out of range: %i\n", dotclock)({ int __ret = !!(1); if (__ret) printf("%s %s: " "SDVO TV clock out of range: %i\n" , dev_driver_string((&dev_priv->drm)->dev), "", dotclock ); __builtin_expect(!!(__ret), 0); }); |
| 1275 | } |
| 1276 | |
| 1277 | pipe_config->clock_set = true1; |
| 1278 | } |
| 1279 | |
| 1280 | static bool_Bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector, |
| 1281 | const struct drm_connector_state *conn_state) |
| 1282 | { |
| 1283 | struct drm_connector *connector = conn_state->connector; |
| 1284 | |
| 1285 | return intel_sdvo_connector->is_hdmi && |
| 1286 | connector->display_info.is_hdmi && |
| 1287 | READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio)({ typeof(({ const __typeof( ((struct intel_digital_connector_state *)0)->base ) *__mptr = (conn_state); (struct intel_digital_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_digital_connector_state , base) );})->force_audio) __tmp = *(volatile typeof(({ const __typeof( ((struct intel_digital_connector_state *)0)->base ) *__mptr = (conn_state); (struct intel_digital_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_digital_connector_state , base) );})->force_audio) *)&(({ const __typeof( ((struct intel_digital_connector_state *)0)->base ) *__mptr = (conn_state ); (struct intel_digital_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_digital_connector_state, base ) );})->force_audio); membar_datadep_consumer(); __tmp; }) != HDMI_AUDIO_OFF_DVI; |
| 1288 | } |
| 1289 | |
| 1290 | static bool_Bool intel_sdvo_limited_color_range(struct intel_encoder *encoder, |
| 1291 | const struct intel_crtc_state *crtc_state, |
| 1292 | const struct drm_connector_state *conn_state) |
| 1293 | { |
| 1294 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
| 1295 | |
| 1296 | if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220(1 << 1)) == 0) |
| 1297 | return false0; |
| 1298 | |
| 1299 | return intel_hdmi_limited_color_range(crtc_state, conn_state); |
| 1300 | } |
| 1301 | |
| 1302 | static int intel_sdvo_compute_config(struct intel_encoder *encoder, |
| 1303 | struct intel_crtc_state *pipe_config, |
| 1304 | struct drm_connector_state *conn_state) |
| 1305 | { |
| 1306 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
| 1307 | struct intel_sdvo_connector_state *intel_sdvo_state = |
| 1308 | to_intel_sdvo_connector_state(conn_state)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = ((conn_state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}); |
| 1309 | struct intel_sdvo_connector *intel_sdvo_connector = |
| 1310 | to_intel_sdvo_connector(conn_state->connector); |
| 1311 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
| 1312 | struct drm_display_mode *mode = &pipe_config->hw.mode; |
| 1313 | |
| 1314 | DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n")___drm_dbg(((void *)0), DRM_UT_KMS, "forcing bpc to 8 for SDVO\n" ); |
| 1315 | pipe_config->pipe_bpp = 8*3; |
| 1316 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 1317 | |
| 1318 | if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))(((to_i915(encoder->base.dev))->pch_type) != PCH_NONE)) |
| 1319 | pipe_config->has_pch_encoder = true1; |
| 1320 | |
| 1321 | /* |
| 1322 | * We need to construct preferred input timings based on our |
| 1323 | * output timings. To do that, we have to set the output |
| 1324 | * timings, even though this isn't really the right place in |
| 1325 | * the sequence to do it. Oh well. |
| 1326 | */ |
| 1327 | if (IS_TV(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 2) | (1 << 3) | (1 << 4)))) { |
| 1328 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
| 1329 | return -EINVAL22; |
| 1330 | |
| 1331 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
| 1332 | intel_sdvo_connector, |
| 1333 | mode, |
| 1334 | adjusted_mode); |
| 1335 | pipe_config->sdvo_tv_clock = true1; |
| 1336 | } else if (IS_LVDS(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 6) | (1 << 14)))) { |
| 1337 | const struct drm_display_mode *fixed_mode = |
| 1338 | intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); |
| 1339 | int ret; |
| 1340 | |
| 1341 | ret = intel_panel_compute_config(&intel_sdvo_connector->base, |
| 1342 | adjusted_mode); |
| 1343 | if (ret) |
| 1344 | return ret; |
| 1345 | |
| 1346 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, fixed_mode)) |
| 1347 | return -EINVAL22; |
| 1348 | |
| 1349 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
| 1350 | intel_sdvo_connector, |
| 1351 | mode, |
| 1352 | adjusted_mode); |
| 1353 | } |
| 1354 | |
| 1355 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5)) |
| 1356 | return -EINVAL22; |
| 1357 | |
| 1358 | /* |
| 1359 | * Make the CRTC code factor in the SDVO pixel multiplier. The |
| 1360 | * SDVO device will factor out the multiplier during mode_set. |
| 1361 | */ |
| 1362 | pipe_config->pixel_multiplier = |
| 1363 | intel_sdvo_get_pixel_multiplier(adjusted_mode); |
| 1364 | |
| 1365 | pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state); |
| 1366 | |
| 1367 | if (pipe_config->has_hdmi_sink) { |
| 1368 | if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO) |
| 1369 | pipe_config->has_audio = intel_sdvo->has_hdmi_audio; |
| 1370 | else |
| 1371 | pipe_config->has_audio = |
| 1372 | intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON; |
| 1373 | } |
| 1374 | |
| 1375 | pipe_config->limited_color_range = |
| 1376 | intel_sdvo_limited_color_range(encoder, pipe_config, |
| 1377 | conn_state); |
| 1378 | |
| 1379 | /* Clock computation needs to happen after pixel multiplier. */ |
| 1380 | if (IS_TV(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 2) | (1 << 3) | (1 << 4)))) |
| 1381 | i9xx_adjust_sdvo_tv_clock(pipe_config); |
| 1382 | |
| 1383 | if (conn_state->picture_aspect_ratio) |
| 1384 | adjusted_mode->picture_aspect_ratio = |
| 1385 | conn_state->picture_aspect_ratio; |
| 1386 | |
| 1387 | if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, |
| 1388 | pipe_config, conn_state)) { |
| 1389 | DRM_DEBUG_KMS("bad AVI infoframe\n")___drm_dbg(((void *)0), DRM_UT_KMS, "bad AVI infoframe\n"); |
| 1390 | return -EINVAL22; |
| 1391 | } |
| 1392 | |
| 1393 | return 0; |
| 1394 | } |
| 1395 | |
| 1396 | #define UPDATE_PROPERTY(input, NAME) \ |
| 1397 | do { \ |
| 1398 | val = input; \ |
| 1399 | intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \ |
| 1400 | } while (0) |
| 1401 | |
| 1402 | static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo, |
| 1403 | const struct intel_sdvo_connector_state *sdvo_state) |
| 1404 | { |
| 1405 | const struct drm_connector_state *conn_state = &sdvo_state->base.base; |
| 1406 | struct intel_sdvo_connector *intel_sdvo_conn = |
| 1407 | to_intel_sdvo_connector(conn_state->connector); |
| 1408 | u16 val; |
| 1409 | |
| 1410 | if (intel_sdvo_conn->left) |
| 1411 | UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H); |
| 1412 | |
| 1413 | if (intel_sdvo_conn->top) |
| 1414 | UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V); |
| 1415 | |
| 1416 | if (intel_sdvo_conn->hpos) |
| 1417 | UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS); |
| 1418 | |
| 1419 | if (intel_sdvo_conn->vpos) |
| 1420 | UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS); |
| 1421 | |
| 1422 | if (intel_sdvo_conn->saturation) |
| 1423 | UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION); |
| 1424 | |
| 1425 | if (intel_sdvo_conn->contrast) |
| 1426 | UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST); |
| 1427 | |
| 1428 | if (intel_sdvo_conn->hue) |
| 1429 | UPDATE_PROPERTY(conn_state->tv.hue, HUE); |
| 1430 | |
| 1431 | if (intel_sdvo_conn->brightness) |
| 1432 | UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS); |
| 1433 | |
| 1434 | if (intel_sdvo_conn->sharpness) |
| 1435 | UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS); |
| 1436 | |
| 1437 | if (intel_sdvo_conn->flicker_filter) |
| 1438 | UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER); |
| 1439 | |
| 1440 | if (intel_sdvo_conn->flicker_filter_2d) |
| 1441 | UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D); |
| 1442 | |
| 1443 | if (intel_sdvo_conn->flicker_filter_adaptive) |
| 1444 | UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
| 1445 | |
| 1446 | if (intel_sdvo_conn->tv_chroma_filter) |
| 1447 | UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER); |
| 1448 | |
| 1449 | if (intel_sdvo_conn->tv_luma_filter) |
| 1450 | UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER); |
| 1451 | |
| 1452 | if (intel_sdvo_conn->dot_crawl) |
| 1453 | UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL); |
| 1454 | |
| 1455 | #undef UPDATE_PROPERTY |
| 1456 | } |
| 1457 | |
| 1458 | static void intel_sdvo_pre_enable(struct intel_atomic_state *state, |
| 1459 | struct intel_encoder *intel_encoder, |
| 1460 | const struct intel_crtc_state *crtc_state, |
| 1461 | const struct drm_connector_state *conn_state) |
| 1462 | { |
| 1463 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_encoder->base.dev); |
| 1464 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1465 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
| 1466 | const struct intel_sdvo_connector_state *sdvo_state = |
| 1467 | to_intel_sdvo_connector_state(conn_state)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = ((conn_state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}); |
| 1468 | struct intel_sdvo_connector *intel_sdvo_connector = |
| 1469 | to_intel_sdvo_connector(conn_state->connector); |
| 1470 | const struct drm_display_mode *mode = &crtc_state->hw.mode; |
| 1471 | struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); |
| 1472 | u32 sdvox; |
| 1473 | struct intel_sdvo_in_out_map in_out; |
| 1474 | struct intel_sdvo_dtd input_dtd, output_dtd; |
| 1475 | int rate; |
| 1476 | |
| 1477 | intel_sdvo_update_props(intel_sdvo, sdvo_state); |
| 1478 | |
| 1479 | /* |
| 1480 | * First, set the input mapping for the first input to our controlled |
| 1481 | * output. This is only correct if we're a single-input device, in |
| 1482 | * which case the first input is the output from the appropriate SDVO |
| 1483 | * channel on the motherboard. In a two-input device, the first input |
| 1484 | * will be SDVOB and the second SDVOC. |
| 1485 | */ |
| 1486 | in_out.in0 = intel_sdvo->attached_output; |
| 1487 | in_out.in1 = 0; |
| 1488 | |
| 1489 | intel_sdvo_set_value(intel_sdvo, |
| 1490 | SDVO_CMD_SET_IN_OUT_MAP0x07, |
| 1491 | &in_out, sizeof(in_out)); |
| 1492 | |
| 1493 | /* Set the output timings to the screen */ |
| 1494 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1495 | intel_sdvo->attached_output)) |
| 1496 | return; |
| 1497 | |
| 1498 | /* lvds has a special fixed output timing. */ |
| 1499 | if (IS_LVDS(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 6) | (1 << 14)))) { |
| 1500 | const struct drm_display_mode *fixed_mode = |
| 1501 | intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); |
| 1502 | |
| 1503 | intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode); |
| 1504 | } else { |
| 1505 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
| 1506 | } |
| 1507 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 1508 | drm_info(&dev_priv->drm,do { } while(0) |
| 1509 | "Setting output timings on %s failed\n",do { } while(0) |
| 1510 | SDVO_NAME(intel_sdvo))do { } while(0); |
| 1511 | |
| 1512 | /* Set the input timing to the screen. Assume always input 0. */ |
| 1513 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1514 | return; |
| 1515 | |
| 1516 | if (crtc_state->has_hdmi_sink) { |
| 1517 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI0x1); |
| 1518 | intel_sdvo_set_colorimetry(intel_sdvo, |
| 1519 | crtc_state->limited_color_range ? |
| 1520 | SDVO_COLORIMETRY_RGB220(1 << 1) : |
| 1521 | SDVO_COLORIMETRY_RGB256(1 << 0)); |
| 1522 | intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); |
| 1523 | intel_sdvo_set_pixel_replication(intel_sdvo, |
| 1524 | !!(adjusted_mode->flags & |
| 1525 | DRM_MODE_FLAG_DBLCLK(1<<12))); |
| 1526 | } else |
| 1527 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI0x0); |
| 1528 | |
| 1529 | if (IS_TV(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 2) | (1 << 3) | (1 << 4))) && |
| 1530 | !intel_sdvo_set_tv_format(intel_sdvo, conn_state)) |
| 1531 | return; |
| 1532 | |
| 1533 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
| 1534 | |
| 1535 | if (IS_TV(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 2) | (1 << 3) | (1 << 4))) || IS_LVDS(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 6) | (1 << 14)))) |
| 1536 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; |
| 1537 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
| 1538 | drm_info(&dev_priv->drm,do { } while(0) |
| 1539 | "Setting input timings on %s failed\n",do { } while(0) |
| 1540 | SDVO_NAME(intel_sdvo))do { } while(0); |
| 1541 | |
| 1542 | switch (crtc_state->pixel_multiplier) { |
| 1543 | default: |
| 1544 | drm_WARN(&dev_priv->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "unknown pixel multiplier specified\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }) |
| 1545 | "unknown pixel multiplier specified\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "unknown pixel multiplier specified\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }); |
| 1546 | fallthroughdo {} while (0); |
| 1547 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X(1 << 0); break; |
| 1548 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X(1 << 1); break; |
| 1549 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X(1 << 3); break; |
| 1550 | } |
| 1551 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
| 1552 | return; |
| 1553 | |
| 1554 | /* Set the SDVO control regs. */ |
| 1555 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
| 1556 | /* The real mode polarity is set by the SDVO commands, using |
| 1557 | * struct intel_sdvo_dtd. */ |
| 1558 | sdvox = SDVO_VSYNC_ACTIVE_HIGH(1 << 4) | SDVO_HSYNC_ACTIVE_HIGH(1 << 3); |
| 1559 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 5) |
| 1560 | sdvox |= SDVO_BORDER_ENABLE(1 << 7); |
| 1561 | } else { |
| 1562 | sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); |
| 1563 | if (intel_sdvo->port == PORT_B) |
| 1564 | sdvox &= SDVOB_PRESERVE_MASK((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)); |
| 1565 | else |
| 1566 | sdvox &= SDVOC_PRESERVE_MASK((1 << 17) | (1 << 26)); |
| 1567 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE(1 << 7); |
| 1568 | } |
| 1569 | |
| 1570 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) |
| 1571 | sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe)((crtc->pipe) << 29); |
| 1572 | else |
| 1573 | sdvox |= SDVO_PIPE_SEL(crtc->pipe)((crtc->pipe) << 30); |
| 1574 | |
| 1575 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
| 1576 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1577 | } else if (IS_I945G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945G) || IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) || |
| 1578 | IS_G33(dev_priv)IS_PLATFORM(dev_priv, INTEL_G33) || IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
| 1579 | /* done in crtc_mode_set as it lives inside the dpll register */ |
| 1580 | } else { |
| 1581 | sdvox |= (crtc_state->pixel_multiplier - 1) |
| 1582 | << SDVO_PORT_MULTIPLY_SHIFT23; |
| 1583 | } |
| 1584 | |
| 1585 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL(1 << 7) && |
| 1586 | DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 5) |
| 1587 | sdvox |= SDVO_STALL_SELECT(1 << 29); |
| 1588 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
| 1589 | } |
| 1590 | |
| 1591 | static bool_Bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
| 1592 | { |
| 1593 | struct intel_sdvo_connector *intel_sdvo_connector = |
| 1594 | to_intel_sdvo_connector(&connector->base); |
| 1595 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
| 1596 | u16 active_outputs = 0; |
| 1597 | |
| 1598 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
| 1599 | |
| 1600 | return active_outputs & intel_sdvo_connector->output_flag; |
| 1601 | } |
| 1602 | |
| 1603 | bool_Bool intel_sdvo_port_enabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1604 | i915_reg_t sdvo_reg, enum pipe *pipe) |
| 1605 | { |
| 1606 | u32 val; |
| 1607 | |
| 1608 | val = intel_de_read(dev_priv, sdvo_reg); |
| 1609 | |
| 1610 | /* asserts want to know the pipe even if the port is disabled */ |
| 1611 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) |
| 1612 | *pipe = (val & SDVO_PIPE_SEL_MASK_CPT(3 << 29)) >> SDVO_PIPE_SEL_SHIFT_CPT29; |
| 1613 | else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 1614 | *pipe = (val & SDVO_PIPE_SEL_MASK_CHV(3 << 24)) >> SDVO_PIPE_SEL_SHIFT_CHV24; |
| 1615 | else |
| 1616 | *pipe = (val & SDVO_PIPE_SEL_MASK(1 << 30)) >> SDVO_PIPE_SEL_SHIFT30; |
| 1617 | |
| 1618 | return val & SDVO_ENABLE(1 << 31); |
| 1619 | } |
| 1620 | |
| 1621 | static bool_Bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, |
| 1622 | enum pipe *pipe) |
| 1623 | { |
| 1624 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 1625 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
| 1626 | u16 active_outputs = 0; |
| 1627 | bool_Bool ret; |
| 1628 | |
| 1629 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
| 1630 | |
| 1631 | ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); |
| 1632 | |
| 1633 | return ret || active_outputs; |
| 1634 | } |
| 1635 | |
| 1636 | static void intel_sdvo_get_config(struct intel_encoder *encoder, |
| 1637 | struct intel_crtc_state *pipe_config) |
| 1638 | { |
| 1639 | struct drm_device *dev = encoder->base.dev; |
| 1640 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 1641 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
| 1642 | struct intel_sdvo_dtd dtd; |
| 1643 | int encoder_pixel_multiplier = 0; |
| 1644 | int dotclock; |
| 1645 | u32 flags = 0, sdvox; |
| 1646 | u8 val; |
| 1647 | bool_Bool ret; |
| 1648 | |
| 1649 | pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO)(1UL << (INTEL_OUTPUT_SDVO)); |
| 1650 | |
| 1651 | sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); |
| 1652 | |
| 1653 | ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); |
| 1654 | if (!ret) { |
| 1655 | /* |
| 1656 | * Some sdvo encoders are not spec compliant and don't |
| 1657 | * implement the mandatory get_timings function. |
| 1658 | */ |
| 1659 | drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "failed to retrieve SDVO DTD\n" ); |
| 1660 | pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS(1<<0); |
| 1661 | } else { |
| 1662 | if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE(1 << 1)) |
| 1663 | flags |= DRM_MODE_FLAG_PHSYNC(1<<0); |
| 1664 | else |
| 1665 | flags |= DRM_MODE_FLAG_NHSYNC(1<<1); |
| 1666 | |
| 1667 | if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE(1 << 2)) |
| 1668 | flags |= DRM_MODE_FLAG_PVSYNC(1<<2); |
| 1669 | else |
| 1670 | flags |= DRM_MODE_FLAG_NVSYNC(1<<3); |
| 1671 | } |
| 1672 | |
| 1673 | pipe_config->hw.adjusted_mode.flags |= flags; |
| 1674 | |
| 1675 | /* |
| 1676 | * pixel multiplier readout is tricky: Only on i915g/gm it is stored in |
| 1677 | * the sdvo port register, on all other platforms it is part of the dpll |
| 1678 | * state. Since the general pipe state readout happens before the |
| 1679 | * encoder->get_config we so already have a valid pixel multplier on all |
| 1680 | * other platfroms. |
| 1681 | */ |
| 1682 | if (IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM)) { |
| 1683 | pipe_config->pixel_multiplier = |
| 1684 | ((sdvox & SDVO_PORT_MULTIPLY_MASK(7 << 23)) |
| 1685 | >> SDVO_PORT_MULTIPLY_SHIFT23) + 1; |
| 1686 | } |
| 1687 | |
| 1688 | dotclock = pipe_config->port_clock; |
| 1689 | |
| 1690 | if (pipe_config->pixel_multiplier) |
| 1691 | dotclock /= pipe_config->pixel_multiplier; |
| 1692 | |
| 1693 | pipe_config->hw.adjusted_mode.crtc_clock = dotclock; |
| 1694 | |
| 1695 | /* Cross check the port pixel multiplier with the sdvo encoder state. */ |
| 1696 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT0x20, |
| 1697 | &val, 1)) { |
| 1698 | switch (val) { |
| 1699 | case SDVO_CLOCK_RATE_MULT_1X(1 << 0): |
| 1700 | encoder_pixel_multiplier = 1; |
| 1701 | break; |
| 1702 | case SDVO_CLOCK_RATE_MULT_2X(1 << 1): |
| 1703 | encoder_pixel_multiplier = 2; |
| 1704 | break; |
| 1705 | case SDVO_CLOCK_RATE_MULT_4X(1 << 3): |
| 1706 | encoder_pixel_multiplier = 4; |
| 1707 | break; |
| 1708 | } |
| 1709 | } |
| 1710 | |
| 1711 | drm_WARN(dev,({ int __ret = !!(encoder_pixel_multiplier != pipe_config-> pixel_multiplier); if (__ret) printf("%s %s: " "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n" , dev_driver_string((dev)->dev), "", pipe_config->pixel_multiplier , encoder_pixel_multiplier); __builtin_expect(!!(__ret), 0); } ) |
| 1712 | encoder_pixel_multiplier != pipe_config->pixel_multiplier,({ int __ret = !!(encoder_pixel_multiplier != pipe_config-> pixel_multiplier); if (__ret) printf("%s %s: " "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n" , dev_driver_string((dev)->dev), "", pipe_config->pixel_multiplier , encoder_pixel_multiplier); __builtin_expect(!!(__ret), 0); } ) |
| 1713 | "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",({ int __ret = !!(encoder_pixel_multiplier != pipe_config-> pixel_multiplier); if (__ret) printf("%s %s: " "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n" , dev_driver_string((dev)->dev), "", pipe_config->pixel_multiplier , encoder_pixel_multiplier); __builtin_expect(!!(__ret), 0); } ) |
| 1714 | pipe_config->pixel_multiplier, encoder_pixel_multiplier)({ int __ret = !!(encoder_pixel_multiplier != pipe_config-> pixel_multiplier); if (__ret) printf("%s %s: " "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n" , dev_driver_string((dev)->dev), "", pipe_config->pixel_multiplier , encoder_pixel_multiplier); __builtin_expect(!!(__ret), 0); } ); |
| 1715 | |
| 1716 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY0x8f, |
| 1717 | &val, 1)) { |
| 1718 | if (val == SDVO_COLORIMETRY_RGB220(1 << 1)) |
| 1719 | pipe_config->limited_color_range = true1; |
| 1720 | } |
| 1721 | |
| 1722 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT0x92, |
| 1723 | &val, 1)) { |
| 1724 | u8 mask = SDVO_AUDIO_ELD_VALID(1 << 0) | SDVO_AUDIO_PRESENCE_DETECT(1 << 1); |
| 1725 | |
| 1726 | if ((val & mask) == mask) |
| 1727 | pipe_config->has_audio = true1; |
| 1728 | } |
| 1729 | |
| 1730 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE0x9e, |
| 1731 | &val, 1)) { |
| 1732 | if (val == SDVO_ENCODE_HDMI0x1) |
| 1733 | pipe_config->has_hdmi_sink = true1; |
| 1734 | } |
| 1735 | |
| 1736 | intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); |
| 1737 | } |
| 1738 | |
| 1739 | static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo) |
| 1740 | { |
| 1741 | intel_sdvo_set_audio_state(intel_sdvo, 0); |
| 1742 | } |
| 1743 | |
| 1744 | static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo, |
| 1745 | const struct intel_crtc_state *crtc_state, |
| 1746 | const struct drm_connector_state *conn_state) |
| 1747 | { |
| 1748 | const struct drm_display_mode *adjusted_mode = |
| 1749 | &crtc_state->hw.adjusted_mode; |
| 1750 | struct drm_connector *connector = conn_state->connector; |
| 1751 | u8 *eld = connector->eld; |
| 1752 | |
| 1753 | eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; |
| 1754 | |
| 1755 | intel_sdvo_set_audio_state(intel_sdvo, 0); |
| 1756 | |
| 1757 | intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD0, |
| 1758 | SDVO_HBUF_TX_DISABLED(0 << 6), |
| 1759 | eld, drm_eld_size(eld)); |
| 1760 | |
| 1761 | intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID(1 << 0) | |
| 1762 | SDVO_AUDIO_PRESENCE_DETECT(1 << 1)); |
| 1763 | } |
| 1764 | |
| 1765 | static void intel_disable_sdvo(struct intel_atomic_state *state, |
| 1766 | struct intel_encoder *encoder, |
| 1767 | const struct intel_crtc_state *old_crtc_state, |
| 1768 | const struct drm_connector_state *conn_state) |
| 1769 | { |
| 1770 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 1771 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
| 1772 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1773 | u32 temp; |
| 1774 | |
| 1775 | if (old_crtc_state->has_audio) |
| 1776 | intel_sdvo_disable_audio(intel_sdvo); |
| 1777 | |
| 1778 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
| 1779 | if (0) |
| 1780 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
| 1781 | DRM_MODE_DPMS_OFF3); |
| 1782 | |
| 1783 | temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); |
| 1784 | |
| 1785 | temp &= ~SDVO_ENABLE(1 << 31); |
| 1786 | intel_sdvo_write_sdvox(intel_sdvo, temp); |
| 1787 | |
| 1788 | /* |
| 1789 | * HW workaround for IBX, we need to move the port |
| 1790 | * to transcoder A after disabling it to allow the |
| 1791 | * matching DP port to be enabled on transcoder A. |
| 1792 | */ |
| 1793 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) && crtc->pipe == PIPE_B) { |
| 1794 | /* |
| 1795 | * We get CPU/PCH FIFO underruns on the other pipe when |
| 1796 | * doing the workaround. Sweep them under the rug. |
| 1797 | */ |
| 1798 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false0); |
| 1799 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false0); |
| 1800 | |
| 1801 | temp &= ~SDVO_PIPE_SEL_MASK(1 << 30); |
| 1802 | temp |= SDVO_ENABLE(1 << 31) | SDVO_PIPE_SEL(PIPE_A)((PIPE_A) << 30); |
| 1803 | intel_sdvo_write_sdvox(intel_sdvo, temp); |
| 1804 | |
| 1805 | temp &= ~SDVO_ENABLE(1 << 31); |
| 1806 | intel_sdvo_write_sdvox(intel_sdvo, temp); |
| 1807 | |
| 1808 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
| 1809 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true1); |
| 1810 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true1); |
| 1811 | } |
| 1812 | } |
| 1813 | |
| 1814 | static void pch_disable_sdvo(struct intel_atomic_state *state, |
| 1815 | struct intel_encoder *encoder, |
| 1816 | const struct intel_crtc_state *old_crtc_state, |
| 1817 | const struct drm_connector_state *old_conn_state) |
| 1818 | { |
| 1819 | } |
| 1820 | |
| 1821 | static void pch_post_disable_sdvo(struct intel_atomic_state *state, |
| 1822 | struct intel_encoder *encoder, |
| 1823 | const struct intel_crtc_state *old_crtc_state, |
| 1824 | const struct drm_connector_state *old_conn_state) |
| 1825 | { |
| 1826 | intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state); |
| 1827 | } |
| 1828 | |
| 1829 | static void intel_enable_sdvo(struct intel_atomic_state *state, |
| 1830 | struct intel_encoder *encoder, |
| 1831 | const struct intel_crtc_state *pipe_config, |
| 1832 | const struct drm_connector_state *conn_state) |
| 1833 | { |
| 1834 | struct drm_device *dev = encoder->base.dev; |
| 1835 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 1836 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
| 1837 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1838 | u32 temp; |
| 1839 | bool_Bool input1, input2; |
| 1840 | int i; |
| 1841 | bool_Bool success; |
| 1842 | |
| 1843 | temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); |
| 1844 | temp |= SDVO_ENABLE(1 << 31); |
| 1845 | intel_sdvo_write_sdvox(intel_sdvo, temp); |
| 1846 | |
| 1847 | for (i = 0; i < 2; i++) |
| 1848 | intel_crtc_wait_for_next_vblank(crtc); |
| 1849 | |
| 1850 | success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
| 1851 | /* |
| 1852 | * Warn if the device reported failure to sync. |
| 1853 | * |
| 1854 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1855 | * a given it the status is a success, we succeeded. |
| 1856 | */ |
| 1857 | if (success && !input1) { |
| 1858 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "First %s output reported failure to " "sync\n", ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC" )) |
| 1859 | "First %s output reported failure to "__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "First %s output reported failure to " "sync\n", ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC" )) |
| 1860 | "sync\n", SDVO_NAME(intel_sdvo))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "First %s output reported failure to " "sync\n", ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC" )); |
| 1861 | } |
| 1862 | |
| 1863 | if (0) |
| 1864 | intel_sdvo_set_encoder_power_state(intel_sdvo, |
| 1865 | DRM_MODE_DPMS_ON0); |
| 1866 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
| 1867 | |
| 1868 | if (pipe_config->has_audio) |
| 1869 | intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); |
| 1870 | } |
| 1871 | |
| 1872 | static enum drm_mode_status |
| 1873 | intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1874 | struct drm_display_mode *mode) |
| 1875 | { |
| 1876 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(connector->dev); |
| 1877 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 1878 | struct intel_sdvo_connector *intel_sdvo_connector = |
| 1879 | to_intel_sdvo_connector(connector); |
| 1880 | bool_Bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); |
| 1881 | int max_dotclk = i915->max_dotclk_freq; |
| 1882 | enum drm_mode_status status; |
| 1883 | int clock = mode->clock; |
| 1884 | |
| 1885 | status = intel_cpu_transcoder_mode_valid(i915, mode); |
| 1886 | if (status != MODE_OK) |
| 1887 | return status; |
| 1888 | |
| 1889 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5)) |
| 1890 | return MODE_NO_DBLESCAN; |
| 1891 | |
| 1892 | if (clock > max_dotclk) |
| 1893 | return MODE_CLOCK_HIGH; |
| 1894 | |
| 1895 | if (mode->flags & DRM_MODE_FLAG_DBLCLK(1<<12)) { |
| 1896 | if (!has_hdmi_sink) |
| 1897 | return MODE_CLOCK_LOW; |
| 1898 | clock *= 2; |
| 1899 | } |
| 1900 | |
| 1901 | if (intel_sdvo->pixel_clock_min > clock) |
| 1902 | return MODE_CLOCK_LOW; |
| 1903 | |
| 1904 | if (intel_sdvo->pixel_clock_max < clock) |
| 1905 | return MODE_CLOCK_HIGH; |
| 1906 | |
| 1907 | if (IS_LVDS(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 6) | (1 << 14)))) { |
| 1908 | enum drm_mode_status status; |
| 1909 | |
| 1910 | status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode); |
| 1911 | if (status != MODE_OK) |
| 1912 | return status; |
| 1913 | } |
| 1914 | |
| 1915 | return MODE_OK; |
| 1916 | } |
| 1917 | |
| 1918 | static bool_Bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
| 1919 | { |
| 1920 | BUILD_BUG_ON(sizeof(*caps) != 8)extern char _ctassert[(!(sizeof(*caps) != 8)) ? 1 : -1 ] __attribute__ ((__unused__)); |
| 1921 | if (!intel_sdvo_get_value(intel_sdvo, |
| 1922 | SDVO_CMD_GET_DEVICE_CAPS0x02, |
| 1923 | caps, sizeof(*caps))) |
| 1924 | return false0; |
| 1925 | |
| 1926 | DRM_DEBUG_KMS("SDVO capabilities:\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1927 | " vendor_id: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1928 | " device_id: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1929 | " device_rev_id: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1930 | " sdvo_version_major: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1931 | " sdvo_version_minor: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1932 | " sdvo_inputs_mask: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1933 | " smooth_scaling: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1934 | " sharp_scaling: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1935 | " up_scaling: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1936 | " down_scaling: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1937 | " stall_support: %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1938 | " output_flags: %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1939 | caps->vendor_id,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1940 | caps->device_id,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1941 | caps->device_rev_id,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1942 | caps->sdvo_version_major,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1943 | caps->sdvo_version_minor,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1944 | caps->sdvo_inputs_mask,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1945 | caps->smooth_scaling,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1946 | caps->sharp_scaling,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1947 | caps->up_scaling,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1948 | caps->down_scaling,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1949 | caps->stall_support,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ) |
| 1950 | caps->output_flags)___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" " sdvo_version_major: %d\n" " sdvo_version_minor: %d\n" " sdvo_inputs_mask: %d\n" " smooth_scaling: %d\n" " sharp_scaling: %d\n" " up_scaling: %d\n" " down_scaling: %d\n" " stall_support: %d\n" " output_flags: %d\n", caps->vendor_id , caps->device_id, caps->device_rev_id, caps->sdvo_version_major , caps->sdvo_version_minor, caps->sdvo_inputs_mask, caps ->smooth_scaling, caps->sharp_scaling, caps->up_scaling , caps->down_scaling, caps->stall_support, caps->output_flags ); |
| 1951 | |
| 1952 | return true1; |
| 1953 | } |
| 1954 | |
| 1955 | static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) |
| 1956 | { |
| 1957 | u8 cap; |
| 1958 | |
| 1959 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP0x8d, |
| 1960 | &cap, sizeof(cap))) |
| 1961 | return SDVO_COLORIMETRY_RGB256(1 << 0); |
| 1962 | |
| 1963 | return cap; |
| 1964 | } |
| 1965 | |
| 1966 | static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
| 1967 | { |
| 1968 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_sdvo->base.base.dev); |
| 1969 | u16 hotplug; |
| 1970 | |
| 1971 | if (!I915_HAS_HOTPLUG(dev_priv)((&(dev_priv)->__info)->display.has_hotplug)) |
| 1972 | return 0; |
| 1973 | |
| 1974 | /* |
| 1975 | * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
| 1976 | * on the line. |
| 1977 | */ |
| 1978 | if (IS_I945G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945G) || IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM)) |
| 1979 | return 0; |
| 1980 | |
| 1981 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT0x0c, |
| 1982 | &hotplug, sizeof(hotplug))) |
| 1983 | return 0; |
| 1984 | |
| 1985 | return hotplug; |
| 1986 | } |
| 1987 | |
| 1988 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
| 1989 | { |
| 1990 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
| 1991 | |
| 1992 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG0x0d, |
| 1993 | &intel_sdvo->hotplug_active, 2); |
| 1994 | } |
| 1995 | |
| 1996 | static enum intel_hotplug_state |
| 1997 | intel_sdvo_hotplug(struct intel_encoder *encoder, |
| 1998 | struct intel_connector *connector) |
| 1999 | { |
| 2000 | intel_sdvo_enable_hotplug(encoder); |
| 2001 | |
| 2002 | return intel_encoder_hotplug(encoder, connector); |
| 2003 | } |
| 2004 | |
| 2005 | static bool_Bool |
| 2006 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
| 2007 | { |
| 2008 | /* Is there more than one type of output? */ |
| 2009 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
| 2010 | } |
| 2011 | |
| 2012 | static struct edid * |
| 2013 | intel_sdvo_get_edid(struct drm_connector *connector) |
| 2014 | { |
| 2015 | struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 2016 | return drm_get_edid(connector, &sdvo->ddc); |
| 2017 | } |
| 2018 | |
| 2019 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 2020 | static struct edid * |
| 2021 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
| 2022 | { |
| 2023 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->dev); |
| 2024 | |
| 2025 | return drm_get_edid(connector, |
| 2026 | intel_gmbus_get_adapter(dev_priv, |
| 2027 | dev_priv->display.vbt.crt_ddc_pin)); |
| 2028 | } |
| 2029 | |
| 2030 | static enum drm_connector_status |
| 2031 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
| 2032 | { |
| 2033 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 2034 | struct intel_sdvo_connector *intel_sdvo_connector = |
| 2035 | to_intel_sdvo_connector(connector); |
| 2036 | enum drm_connector_status status; |
| 2037 | struct edid *edid; |
| 2038 | |
| 2039 | edid = intel_sdvo_get_edid(connector); |
| 2040 | |
| 2041 | if (edid == NULL((void *)0) && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
| 2042 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
| 2043 | |
| 2044 | /* |
| 2045 | * Don't use the 1 as the argument of DDC bus switch to get |
| 2046 | * the EDID. It is used for SDVO SPD ROM. |
| 2047 | */ |
| 2048 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
| 2049 | intel_sdvo->ddc_bus = ddc; |
| 2050 | edid = intel_sdvo_get_edid(connector); |
| 2051 | if (edid) |
| 2052 | break; |
| 2053 | } |
| 2054 | /* |
| 2055 | * If we found the EDID on the other bus, |
| 2056 | * assume that is the correct DDC bus. |
| 2057 | */ |
| 2058 | if (edid == NULL((void *)0)) |
| 2059 | intel_sdvo->ddc_bus = saved_ddc; |
| 2060 | } |
| 2061 | |
| 2062 | /* |
| 2063 | * When there is no edid and no monitor is connected with VGA |
| 2064 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
| 2065 | */ |
| 2066 | if (edid == NULL((void *)0)) |
| 2067 | edid = intel_sdvo_get_analog_edid(connector); |
| 2068 | |
| 2069 | status = connector_status_unknown; |
| 2070 | if (edid != NULL((void *)0)) { |
| 2071 | /* DDC bus is shared, match EDID to connector type */ |
| 2072 | if (edid->input & DRM_EDID_INPUT_DIGITAL(1 << 7)) { |
| 2073 | status = connector_status_connected; |
| 2074 | if (intel_sdvo_connector->is_hdmi) { |
| 2075 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); |
| 2076 | } |
| 2077 | } else |
| 2078 | status = connector_status_disconnected; |
| 2079 | kfree(edid); |
| 2080 | } |
| 2081 | |
| 2082 | return status; |
| 2083 | } |
| 2084 | |
| 2085 | static bool_Bool |
| 2086 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, |
| 2087 | struct edid *edid) |
| 2088 | { |
| 2089 | bool_Bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL(1 << 7)); |
| 2090 | bool_Bool connector_is_digital = !!IS_DIGITAL(sdvo)(sdvo->output_flag & (((1 << 0) | (1 << 8) ) | ((1 << 6) | (1 << 14)))); |
| 2091 | |
| 2092 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "connector_is_digital? %d, monitor_is_digital? %d\n" , connector_is_digital, monitor_is_digital) |
| 2093 | connector_is_digital, monitor_is_digital)___drm_dbg(((void *)0), DRM_UT_KMS, "connector_is_digital? %d, monitor_is_digital? %d\n" , connector_is_digital, monitor_is_digital); |
| 2094 | return connector_is_digital == monitor_is_digital; |
| 2095 | } |
| 2096 | |
| 2097 | static enum drm_connector_status |
| 2098 | intel_sdvo_detect(struct drm_connector *connector, bool_Bool force) |
| 2099 | { |
| 2100 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(connector->dev); |
| 2101 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 2102 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
| 2103 | enum drm_connector_status ret; |
| 2104 | u16 response; |
| 2105 | |
| 2106 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",___drm_dbg(((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s]\n", connector ->base.id, connector->name) |
| 2107 | connector->base.id, connector->name)___drm_dbg(((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s]\n", connector ->base.id, connector->name); |
| 2108 | |
| 2109 | if (!INTEL_DISPLAY_ENABLED(i915)(({ int __ret = !!((!((&(i915)->__runtime)->pipe_mask != 0))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(i915)->drm))->dev), "", "drm_WARN_ON(" "!((&(i915)->__runtime)->pipe_mask != 0)" ")"); __builtin_expect(!!(__ret), 0); }), !(i915)->params .disable_display && !intel_opregion_headless_sku(i915 ))) |
| 2110 | return connector_status_disconnected; |
| 2111 | |
| 2112 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2113 | SDVO_CMD_GET_ATTACHED_DISPLAYS0x0b, |
| 2114 | &response, 2)) |
| 2115 | return connector_status_unknown; |
| 2116 | |
| 2117 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO response %d %d [%x]\n" , response & 0xff, response >> 8, intel_sdvo_connector ->output_flag) |
| 2118 | response & 0xff, response >> 8,___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO response %d %d [%x]\n" , response & 0xff, response >> 8, intel_sdvo_connector ->output_flag) |
| 2119 | intel_sdvo_connector->output_flag)___drm_dbg(((void *)0), DRM_UT_KMS, "SDVO response %d %d [%x]\n" , response & 0xff, response >> 8, intel_sdvo_connector ->output_flag); |
| 2120 | |
| 2121 | if (response == 0) |
| 2122 | return connector_status_disconnected; |
| 2123 | |
| 2124 | intel_sdvo->attached_output = response; |
| 2125 | |
| 2126 | intel_sdvo->has_hdmi_audio = false0; |
| 2127 | |
| 2128 | if ((intel_sdvo_connector->output_flag & response) == 0) |
| 2129 | ret = connector_status_disconnected; |
| 2130 | else if (IS_TMDS(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 0) | (1 << 8)))) |
| 2131 | ret = intel_sdvo_tmds_sink_detect(connector); |
| 2132 | else { |
| 2133 | struct edid *edid; |
| 2134 | |
| 2135 | /* if we have an edid check it matches the connection */ |
| 2136 | edid = intel_sdvo_get_edid(connector); |
| 2137 | if (edid == NULL((void *)0)) |
| 2138 | edid = intel_sdvo_get_analog_edid(connector); |
| 2139 | if (edid != NULL((void *)0)) { |
| 2140 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
| 2141 | edid)) |
| 2142 | ret = connector_status_connected; |
| 2143 | else |
| 2144 | ret = connector_status_disconnected; |
| 2145 | |
| 2146 | kfree(edid); |
| 2147 | } else |
| 2148 | ret = connector_status_connected; |
| 2149 | } |
| 2150 | |
| 2151 | return ret; |
| 2152 | } |
| 2153 | |
| 2154 | static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
| 2155 | { |
| 2156 | int num_modes = 0; |
| 2157 | struct edid *edid; |
| 2158 | |
| 2159 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",___drm_dbg(((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s]\n", connector ->base.id, connector->name) |
| 2160 | connector->base.id, connector->name)___drm_dbg(((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s]\n", connector ->base.id, connector->name); |
| 2161 | |
| 2162 | /* set the bus switch and get the modes */ |
| 2163 | edid = intel_sdvo_get_edid(connector); |
| 2164 | |
| 2165 | /* |
| 2166 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 2167 | * link between analog and digital outputs. So, if the regular SDVO |
| 2168 | * DDC fails, check to see if the analog output is disconnected, in |
| 2169 | * which case we'll look there for the digital DDC data. |
| 2170 | */ |
| 2171 | if (!edid) |
| 2172 | edid = intel_sdvo_get_analog_edid(connector); |
| 2173 | |
| 2174 | if (!edid) |
| 2175 | return 0; |
| 2176 | |
| 2177 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
| 2178 | edid)) |
| 2179 | num_modes += intel_connector_update_modes(connector, edid); |
| 2180 | |
| 2181 | kfree(edid); |
| 2182 | |
| 2183 | return num_modes; |
| 2184 | } |
| 2185 | |
| 2186 | /* |
| 2187 | * Set of SDVO TV modes. |
| 2188 | * Note! This is in reply order (see loop in get_tv_modes). |
| 2189 | * XXX: all 60Hz refresh? |
| 2190 | */ |
| 2191 | static const struct drm_display_mode sdvo_tv_modes[] = { |
| 2192 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,.name = "320x200", .status = 0, .type = ((1<<6)), .clock = (5815), .hdisplay = (320), .hsync_start = (321), .hsync_end = (384), .htotal = (416), .hskew = (0), .vdisplay = (200), . vsync_start = (201), .vsync_end = (232), .vtotal = (233), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2193 | 416, 0, 200, 201, 232, 233, 0,.name = "320x200", .status = 0, .type = ((1<<6)), .clock = (5815), .hdisplay = (320), .hsync_start = (321), .hsync_end = (384), .htotal = (416), .hskew = (0), .vdisplay = (200), . vsync_start = (201), .vsync_end = (232), .vtotal = (233), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2194 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "320x200", .status = 0, .type = ((1<<6)), .clock = (5815), .hdisplay = (320), .hsync_start = (321), .hsync_end = (384), .htotal = (416), .hskew = (0), .vdisplay = (200), . vsync_start = (201), .vsync_end = (232), .vtotal = (233), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2195 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,.name = "320x240", .status = 0, .type = ((1<<6)), .clock = (6814), .hdisplay = (320), .hsync_start = (321), .hsync_end = (384), .htotal = (416), .hskew = (0), .vdisplay = (240), . vsync_start = (241), .vsync_end = (272), .vtotal = (273), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2196 | 416, 0, 240, 241, 272, 273, 0,.name = "320x240", .status = 0, .type = ((1<<6)), .clock = (6814), .hdisplay = (320), .hsync_start = (321), .hsync_end = (384), .htotal = (416), .hskew = (0), .vdisplay = (240), . vsync_start = (241), .vsync_end = (272), .vtotal = (273), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2197 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "320x240", .status = 0, .type = ((1<<6)), .clock = (6814), .hdisplay = (320), .hsync_start = (321), .hsync_end = (384), .htotal = (416), .hskew = (0), .vdisplay = (240), . vsync_start = (241), .vsync_end = (272), .vtotal = (273), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2198 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,.name = "400x300", .status = 0, .type = ((1<<6)), .clock = (9910), .hdisplay = (400), .hsync_start = (401), .hsync_end = (464), .htotal = (496), .hskew = (0), .vdisplay = (300), . vsync_start = (301), .vsync_end = (332), .vtotal = (333), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2199 | 496, 0, 300, 301, 332, 333, 0,.name = "400x300", .status = 0, .type = ((1<<6)), .clock = (9910), .hdisplay = (400), .hsync_start = (401), .hsync_end = (464), .htotal = (496), .hskew = (0), .vdisplay = (300), . vsync_start = (301), .vsync_end = (332), .vtotal = (333), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2200 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "400x300", .status = 0, .type = ((1<<6)), .clock = (9910), .hdisplay = (400), .hsync_start = (401), .hsync_end = (464), .htotal = (496), .hskew = (0), .vdisplay = (300), . vsync_start = (301), .vsync_end = (332), .vtotal = (333), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2201 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,.name = "640x350", .status = 0, .type = ((1<<6)), .clock = (16913), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (350), . vsync_start = (351), .vsync_end = (382), .vtotal = (383), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2202 | 736, 0, 350, 351, 382, 383, 0,.name = "640x350", .status = 0, .type = ((1<<6)), .clock = (16913), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (350), . vsync_start = (351), .vsync_end = (382), .vtotal = (383), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2203 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "640x350", .status = 0, .type = ((1<<6)), .clock = (16913), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (350), . vsync_start = (351), .vsync_end = (382), .vtotal = (383), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2204 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,.name = "640x400", .status = 0, .type = ((1<<6)), .clock = (19121), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (432), .vtotal = (433), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2205 | 736, 0, 400, 401, 432, 433, 0,.name = "640x400", .status = 0, .type = ((1<<6)), .clock = (19121), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (432), .vtotal = (433), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2206 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "640x400", .status = 0, .type = ((1<<6)), .clock = (19121), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (432), .vtotal = (433), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2207 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (22654), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2208 | 736, 0, 480, 481, 512, 513, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (22654), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2209 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (22654), .hdisplay = (640), .hsync_start = (641), .hsync_end = (704), .htotal = (736), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2210 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,.name = "704x480", .status = 0, .type = ((1<<6)), .clock = (24624), .hdisplay = (704), .hsync_start = (705), .hsync_end = (768), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2211 | 800, 0, 480, 481, 512, 513, 0,.name = "704x480", .status = 0, .type = ((1<<6)), .clock = (24624), .hdisplay = (704), .hsync_start = (705), .hsync_end = (768), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2212 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "704x480", .status = 0, .type = ((1<<6)), .clock = (24624), .hdisplay = (704), .hsync_start = (705), .hsync_end = (768), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2213 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,.name = "704x576", .status = 0, .type = ((1<<6)), .clock = (29232), .hdisplay = (704), .hsync_start = (705), .hsync_end = (768), .htotal = (800), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2214 | 800, 0, 576, 577, 608, 609, 0,.name = "704x576", .status = 0, .type = ((1<<6)), .clock = (29232), .hdisplay = (704), .hsync_start = (705), .hsync_end = (768), .htotal = (800), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2215 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "704x576", .status = 0, .type = ((1<<6)), .clock = (29232), .hdisplay = (704), .hsync_start = (705), .hsync_end = (768), .htotal = (800), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2216 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,.name = "720x350", .status = 0, .type = ((1<<6)), .clock = (18751), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (350), . vsync_start = (351), .vsync_end = (382), .vtotal = (383), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2217 | 816, 0, 350, 351, 382, 383, 0,.name = "720x350", .status = 0, .type = ((1<<6)), .clock = (18751), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (350), . vsync_start = (351), .vsync_end = (382), .vtotal = (383), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2218 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x350", .status = 0, .type = ((1<<6)), .clock = (18751), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (350), . vsync_start = (351), .vsync_end = (382), .vtotal = (383), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2219 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (21199), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (432), .vtotal = (433), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2220 | 816, 0, 400, 401, 432, 433, 0,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (21199), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (432), .vtotal = (433), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2221 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x400", .status = 0, .type = ((1<<6)), .clock = (21199), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (432), .vtotal = (433), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2222 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (25116), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2223 | 816, 0, 480, 481, 512, 513, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (25116), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2224 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (25116), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (512), .vtotal = (513), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2225 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,.name = "720x540", .status = 0, .type = ((1<<6)), .clock = (28054), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (540), . vsync_start = (541), .vsync_end = (572), .vtotal = (573), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2226 | 816, 0, 540, 541, 572, 573, 0,.name = "720x540", .status = 0, .type = ((1<<6)), .clock = (28054), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (540), . vsync_start = (541), .vsync_end = (572), .vtotal = (573), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2227 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x540", .status = 0, .type = ((1<<6)), .clock = (28054), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (540), . vsync_start = (541), .vsync_end = (572), .vtotal = (573), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2228 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (29816), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2229 | 816, 0, 576, 577, 608, 609, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (29816), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2230 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (29816), .hdisplay = (720), .hsync_start = (721), .hsync_end = (784), .htotal = (816), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2231 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,.name = "768x576", .status = 0, .type = ((1<<6)), .clock = (31570), .hdisplay = (768), .hsync_start = (769), .hsync_end = (832), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2232 | 864, 0, 576, 577, 608, 609, 0,.name = "768x576", .status = 0, .type = ((1<<6)), .clock = (31570), .hdisplay = (768), .hsync_start = (769), .hsync_end = (832), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2233 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "768x576", .status = 0, .type = ((1<<6)), .clock = (31570), .hdisplay = (768), .hsync_start = (769), .hsync_end = (832), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (577), .vsync_end = (608), .vtotal = (609), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2234 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (34030), .hdisplay = (800), .hsync_start = (801), .hsync_end = (864), .htotal = (896), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (632), .vtotal = (633), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2235 | 896, 0, 600, 601, 632, 633, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (34030), .hdisplay = (800), .hsync_start = (801), .hsync_end = (864), .htotal = (896), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (632), .vtotal = (633), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2236 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (34030), .hdisplay = (800), .hsync_start = (801), .hsync_end = (864), .htotal = (896), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (632), .vtotal = (633), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2237 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,.name = "832x624", .status = 0, .type = ((1<<6)), .clock = (36581), .hdisplay = (832), .hsync_start = (833), .hsync_end = (896), .htotal = (928), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (656), .vtotal = (657), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2238 | 928, 0, 624, 625, 656, 657, 0,.name = "832x624", .status = 0, .type = ((1<<6)), .clock = (36581), .hdisplay = (832), .hsync_start = (833), .hsync_end = (896), .htotal = (928), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (656), .vtotal = (657), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2239 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "832x624", .status = 0, .type = ((1<<6)), .clock = (36581), .hdisplay = (832), .hsync_start = (833), .hsync_end = (896), .htotal = (928), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (656), .vtotal = (657), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2240 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,.name = "920x766", .status = 0, .type = ((1<<6)), .clock = (48707), .hdisplay = (920), .hsync_start = (921), .hsync_end = (984), .htotal = (1016), .hskew = (0), .vdisplay = (766), . vsync_start = (767), .vsync_end = (798), .vtotal = (799), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2241 | 1016, 0, 766, 767, 798, 799, 0,.name = "920x766", .status = 0, .type = ((1<<6)), .clock = (48707), .hdisplay = (920), .hsync_start = (921), .hsync_end = (984), .htotal = (1016), .hskew = (0), .vdisplay = (766), . vsync_start = (767), .vsync_end = (798), .vtotal = (799), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2242 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "920x766", .status = 0, .type = ((1<<6)), .clock = (48707), .hdisplay = (920), .hsync_start = (921), .hsync_end = (984), .htotal = (1016), .hskew = (0), .vdisplay = (766), . vsync_start = (767), .vsync_end = (798), .vtotal = (799), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2243 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (53827), .hdisplay = (1024), .hsync_start = (1025), .hsync_end = (1088), .htotal = (1120), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (800), .vtotal = (801), . vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2244 | 1120, 0, 768, 769, 800, 801, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (53827), .hdisplay = (1024), .hsync_start = (1025), .hsync_end = (1088), .htotal = (1120), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (800), .vtotal = (801), . vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2245 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (53827), .hdisplay = (1024), .hsync_start = (1025), .hsync_end = (1088), .htotal = (1120), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (800), .vtotal = (801), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2246 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (87265), .hdisplay = (1280), .hsync_start = (1281), .hsync_end = (1344), .htotal = (1376), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1056), .vtotal = (1057 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2247 | 1376, 0, 1024, 1025, 1056, 1057, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (87265), .hdisplay = (1280), .hsync_start = (1281), .hsync_end = (1344), .htotal = (1376), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1056), .vtotal = (1057 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) |
| 2248 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (87265), .hdisplay = (1280), .hsync_start = (1281), .hsync_end = (1344), .htotal = (1376), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1056), .vtotal = (1057 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, |
| 2249 | }; |
| 2250 | |
| 2251 | static int intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 2252 | { |
| 2253 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 2254 | const struct drm_connector_state *conn_state = connector->state; |
| 2255 | struct intel_sdvo_sdtv_resolution_request tv_res; |
| 2256 | u32 reply = 0, format_map = 0; |
| 2257 | int num_modes = 0; |
| 2258 | int i; |
| 2259 | |
| 2260 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",___drm_dbg(((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s]\n", connector ->base.id, connector->name) |
| 2261 | connector->base.id, connector->name)___drm_dbg(((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s]\n", connector ->base.id, connector->name); |
| 2262 | |
| 2263 | /* |
| 2264 | * Read the list of supported input resolutions for the selected TV |
| 2265 | * format. |
| 2266 | */ |
| 2267 | format_map = 1 << conn_state->tv.mode; |
| 2268 | memcpy(&tv_res, &format_map,__builtin_memcpy((&tv_res), (&format_map), ((((sizeof (format_map))<(sizeof(struct intel_sdvo_sdtv_resolution_request )))?(sizeof(format_map)):(sizeof(struct intel_sdvo_sdtv_resolution_request ))))) |
| 2269 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)))__builtin_memcpy((&tv_res), (&format_map), ((((sizeof (format_map))<(sizeof(struct intel_sdvo_sdtv_resolution_request )))?(sizeof(format_map)):(sizeof(struct intel_sdvo_sdtv_resolution_request ))))); |
| 2270 | |
| 2271 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
| 2272 | return 0; |
| 2273 | |
| 2274 | BUILD_BUG_ON(sizeof(tv_res) != 3)extern char _ctassert[(!(sizeof(tv_res) != 3)) ? 1 : -1 ] __attribute__ ((__unused__)); |
| 2275 | if (!intel_sdvo_write_cmd(intel_sdvo, |
| 2276 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT0x83, |
| 2277 | &tv_res, sizeof(tv_res))) |
| 2278 | return 0; |
| 2279 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
| 2280 | return 0; |
| 2281 | |
| 2282 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes)(sizeof((sdvo_tv_modes)) / sizeof((sdvo_tv_modes)[0])); i++) { |
| 2283 | if (reply & (1 << i)) { |
| 2284 | struct drm_display_mode *nmode; |
| 2285 | nmode = drm_mode_duplicate(connector->dev, |
| 2286 | &sdvo_tv_modes[i]); |
| 2287 | if (nmode) { |
| 2288 | drm_mode_probed_add(connector, nmode); |
| 2289 | num_modes++; |
| 2290 | } |
| 2291 | } |
| 2292 | } |
| 2293 | |
| 2294 | return num_modes; |
| 2295 | } |
| 2296 | |
| 2297 | static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 2298 | { |
| 2299 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 2300 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->dev); |
| 2301 | int num_modes = 0; |
| 2302 | |
| 2303 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s]\n" , connector->base.id, connector->name) |
| 2304 | connector->base.id, connector->name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s]\n" , connector->base.id, connector->name); |
| 2305 | |
| 2306 | num_modes += intel_panel_get_modes(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 2307 | num_modes += intel_ddc_get_modes(connector, &intel_sdvo->ddc); |
| 2308 | |
| 2309 | return num_modes; |
| 2310 | } |
| 2311 | |
| 2312 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 2313 | { |
| 2314 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
| 2315 | |
| 2316 | if (IS_TV(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 2) | (1 << 3) | (1 << 4)))) |
| 2317 | return intel_sdvo_get_tv_modes(connector); |
| 2318 | else if (IS_LVDS(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 6) | (1 << 14)))) |
| 2319 | return intel_sdvo_get_lvds_modes(connector); |
| 2320 | else |
| 2321 | return intel_sdvo_get_ddc_modes(connector); |
| 2322 | } |
| 2323 | |
| 2324 | static int |
| 2325 | intel_sdvo_connector_atomic_get_property(struct drm_connector *connector, |
| 2326 | const struct drm_connector_state *state, |
| 2327 | struct drm_property *property, |
| 2328 | u64 *val) |
| 2329 | { |
| 2330 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
| 2331 | const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = (((void *)state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}); |
| 2332 | |
| 2333 | if (property == intel_sdvo_connector->tv_format) { |
| 2334 | int i; |
| 2335 | |
| 2336 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
| 2337 | if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) { |
| 2338 | *val = i; |
| 2339 | |
| 2340 | return 0; |
| 2341 | } |
| 2342 | |
| 2343 | drm_WARN_ON(connector->dev, 1)({ int __ret = !!((1)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((connector->dev))->dev), "", "drm_WARN_ON(" "1" ")"); __builtin_expect(!!(__ret), 0); }); |
| 2344 | *val = 0; |
| 2345 | } else if (property == intel_sdvo_connector->top || |
| 2346 | property == intel_sdvo_connector->bottom) |
| 2347 | *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v; |
| 2348 | else if (property == intel_sdvo_connector->left || |
| 2349 | property == intel_sdvo_connector->right) |
| 2350 | *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h; |
| 2351 | else if (property == intel_sdvo_connector->hpos) |
| 2352 | *val = sdvo_state->tv.hpos; |
| 2353 | else if (property == intel_sdvo_connector->vpos) |
| 2354 | *val = sdvo_state->tv.vpos; |
| 2355 | else if (property == intel_sdvo_connector->saturation) |
| 2356 | *val = state->tv.saturation; |
| 2357 | else if (property == intel_sdvo_connector->contrast) |
| 2358 | *val = state->tv.contrast; |
| 2359 | else if (property == intel_sdvo_connector->hue) |
| 2360 | *val = state->tv.hue; |
| 2361 | else if (property == intel_sdvo_connector->brightness) |
| 2362 | *val = state->tv.brightness; |
| 2363 | else if (property == intel_sdvo_connector->sharpness) |
| 2364 | *val = sdvo_state->tv.sharpness; |
| 2365 | else if (property == intel_sdvo_connector->flicker_filter) |
| 2366 | *val = sdvo_state->tv.flicker_filter; |
| 2367 | else if (property == intel_sdvo_connector->flicker_filter_2d) |
| 2368 | *val = sdvo_state->tv.flicker_filter_2d; |
| 2369 | else if (property == intel_sdvo_connector->flicker_filter_adaptive) |
| 2370 | *val = sdvo_state->tv.flicker_filter_adaptive; |
| 2371 | else if (property == intel_sdvo_connector->tv_chroma_filter) |
| 2372 | *val = sdvo_state->tv.chroma_filter; |
| 2373 | else if (property == intel_sdvo_connector->tv_luma_filter) |
| 2374 | *val = sdvo_state->tv.luma_filter; |
| 2375 | else if (property == intel_sdvo_connector->dot_crawl) |
| 2376 | *val = sdvo_state->tv.dot_crawl; |
| 2377 | else |
| 2378 | return intel_digital_connector_atomic_get_property(connector, state, property, val); |
| 2379 | |
| 2380 | return 0; |
| 2381 | } |
| 2382 | |
| 2383 | static int |
| 2384 | intel_sdvo_connector_atomic_set_property(struct drm_connector *connector, |
| 2385 | struct drm_connector_state *state, |
| 2386 | struct drm_property *property, |
| 2387 | u64 val) |
| 2388 | { |
| 2389 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
| 2390 | struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = ((state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}); |
| 2391 | |
| 2392 | if (property == intel_sdvo_connector->tv_format) { |
| 2393 | state->tv.mode = intel_sdvo_connector->tv_format_supported[val]; |
| 2394 | |
| 2395 | if (state->crtc) { |
| 2396 | struct drm_crtc_state *crtc_state = |
| 2397 | drm_atomic_get_new_crtc_state(state->state, state->crtc); |
| 2398 | |
| 2399 | crtc_state->connectors_changed = true1; |
| 2400 | } |
| 2401 | } else if (property == intel_sdvo_connector->top || |
| 2402 | property == intel_sdvo_connector->bottom) |
| 2403 | /* Cannot set these independent from each other */ |
| 2404 | sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val; |
| 2405 | else if (property == intel_sdvo_connector->left || |
| 2406 | property == intel_sdvo_connector->right) |
| 2407 | /* Cannot set these independent from each other */ |
| 2408 | sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val; |
| 2409 | else if (property == intel_sdvo_connector->hpos) |
| 2410 | sdvo_state->tv.hpos = val; |
| 2411 | else if (property == intel_sdvo_connector->vpos) |
| 2412 | sdvo_state->tv.vpos = val; |
| 2413 | else if (property == intel_sdvo_connector->saturation) |
| 2414 | state->tv.saturation = val; |
| 2415 | else if (property == intel_sdvo_connector->contrast) |
| 2416 | state->tv.contrast = val; |
| 2417 | else if (property == intel_sdvo_connector->hue) |
| 2418 | state->tv.hue = val; |
| 2419 | else if (property == intel_sdvo_connector->brightness) |
| 2420 | state->tv.brightness = val; |
| 2421 | else if (property == intel_sdvo_connector->sharpness) |
| 2422 | sdvo_state->tv.sharpness = val; |
| 2423 | else if (property == intel_sdvo_connector->flicker_filter) |
| 2424 | sdvo_state->tv.flicker_filter = val; |
| 2425 | else if (property == intel_sdvo_connector->flicker_filter_2d) |
| 2426 | sdvo_state->tv.flicker_filter_2d = val; |
| 2427 | else if (property == intel_sdvo_connector->flicker_filter_adaptive) |
| 2428 | sdvo_state->tv.flicker_filter_adaptive = val; |
| 2429 | else if (property == intel_sdvo_connector->tv_chroma_filter) |
| 2430 | sdvo_state->tv.chroma_filter = val; |
| 2431 | else if (property == intel_sdvo_connector->tv_luma_filter) |
| 2432 | sdvo_state->tv.luma_filter = val; |
| 2433 | else if (property == intel_sdvo_connector->dot_crawl) |
| 2434 | sdvo_state->tv.dot_crawl = val; |
| 2435 | else |
| 2436 | return intel_digital_connector_atomic_set_property(connector, state, property, val); |
| 2437 | |
| 2438 | return 0; |
| 2439 | } |
| 2440 | |
| 2441 | static int |
| 2442 | intel_sdvo_connector_register(struct drm_connector *connector) |
| 2443 | { |
| 2444 | struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 2445 | int ret; |
| 2446 | |
| 2447 | ret = intel_connector_register(connector); |
| 2448 | if (ret) |
| 2449 | return ret; |
| 2450 | |
| 2451 | return sysfs_create_link(&connector->kdev->kobj,0 |
| 2452 | &sdvo->ddc.dev.kobj,0 |
| 2453 | sdvo->ddc.dev.kobj.name)0; |
| 2454 | } |
| 2455 | |
| 2456 | static void |
| 2457 | intel_sdvo_connector_unregister(struct drm_connector *connector) |
| 2458 | { |
| 2459 | struct intel_sdvo *sdvo = intel_attached_sdvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
Value stored to 'sdvo' during its initialization is never read | |
| 2460 | |
| 2461 | sysfs_remove_link(&connector->kdev->kobj, |
| 2462 | sdvo->ddc.dev.kobj.name); |
| 2463 | intel_connector_unregister(connector); |
| 2464 | } |
| 2465 | |
| 2466 | static struct drm_connector_state * |
| 2467 | intel_sdvo_connector_duplicate_state(struct drm_connector *connector) |
| 2468 | { |
| 2469 | struct intel_sdvo_connector_state *state; |
| 2470 | |
| 2471 | state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL(0x0001 | 0x0004)); |
| 2472 | if (!state) |
| 2473 | return NULL((void *)0); |
| 2474 | |
| 2475 | __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base); |
| 2476 | return &state->base.base; |
| 2477 | } |
| 2478 | |
| 2479 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
| 2480 | .detect = intel_sdvo_detect, |
| 2481 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 2482 | .atomic_get_property = intel_sdvo_connector_atomic_get_property, |
| 2483 | .atomic_set_property = intel_sdvo_connector_atomic_set_property, |
| 2484 | .late_register = intel_sdvo_connector_register, |
| 2485 | .early_unregister = intel_sdvo_connector_unregister, |
| 2486 | .destroy = intel_connector_destroy, |
| 2487 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
| 2488 | .atomic_duplicate_state = intel_sdvo_connector_duplicate_state, |
| 2489 | }; |
| 2490 | |
| 2491 | static int intel_sdvo_atomic_check(struct drm_connector *conn, |
| 2492 | struct drm_atomic_state *state) |
| 2493 | { |
| 2494 | struct drm_connector_state *new_conn_state = |
| 2495 | drm_atomic_get_new_connector_state(state, conn); |
| 2496 | struct drm_connector_state *old_conn_state = |
| 2497 | drm_atomic_get_old_connector_state(state, conn); |
| 2498 | struct intel_sdvo_connector_state *old_state = |
| 2499 | to_intel_sdvo_connector_state(old_conn_state)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = ((old_conn_state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}); |
| 2500 | struct intel_sdvo_connector_state *new_state = |
| 2501 | to_intel_sdvo_connector_state(new_conn_state)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = ((new_conn_state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}); |
| 2502 | |
| 2503 | if (new_conn_state->crtc && |
| 2504 | (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv))__builtin_memcmp((&old_state->tv), (&new_state-> tv), (sizeof(old_state->tv))) || |
| 2505 | memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv))__builtin_memcmp((&old_conn_state->tv), (&new_conn_state ->tv), (sizeof(old_conn_state->tv))))) { |
| 2506 | struct drm_crtc_state *crtc_state = |
| 2507 | drm_atomic_get_new_crtc_state(state, |
| 2508 | new_conn_state->crtc); |
| 2509 | |
| 2510 | crtc_state->connectors_changed = true1; |
| 2511 | } |
| 2512 | |
| 2513 | return intel_digital_connector_atomic_check(conn, state); |
| 2514 | } |
| 2515 | |
| 2516 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 2517 | .get_modes = intel_sdvo_get_modes, |
| 2518 | .mode_valid = intel_sdvo_mode_valid, |
| 2519 | .atomic_check = intel_sdvo_atomic_check, |
| 2520 | }; |
| 2521 | |
| 2522 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
| 2523 | { |
| 2524 | struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof (struct intel_encoder, base) );})); |
| 2525 | |
| 2526 | i2c_del_adapter(&intel_sdvo->ddc); |
| 2527 | intel_encoder_destroy(encoder); |
| 2528 | } |
| 2529 | |
| 2530 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 2531 | .destroy = intel_sdvo_enc_destroy, |
| 2532 | }; |
| 2533 | |
| 2534 | static void |
| 2535 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
| 2536 | { |
| 2537 | u16 mask = 0; |
| 2538 | unsigned int num_bits; |
| 2539 | |
| 2540 | /* |
| 2541 | * Make a mask of outputs less than or equal to our own priority in the |
| 2542 | * list. |
| 2543 | */ |
| 2544 | switch (sdvo->controlled_output) { |
| 2545 | case SDVO_OUTPUT_LVDS1(1 << 14): |
| 2546 | mask |= SDVO_OUTPUT_LVDS1(1 << 14); |
| 2547 | fallthroughdo {} while (0); |
| 2548 | case SDVO_OUTPUT_LVDS0(1 << 6): |
| 2549 | mask |= SDVO_OUTPUT_LVDS0(1 << 6); |
| 2550 | fallthroughdo {} while (0); |
| 2551 | case SDVO_OUTPUT_TMDS1(1 << 8): |
| 2552 | mask |= SDVO_OUTPUT_TMDS1(1 << 8); |
| 2553 | fallthroughdo {} while (0); |
| 2554 | case SDVO_OUTPUT_TMDS0(1 << 0): |
| 2555 | mask |= SDVO_OUTPUT_TMDS0(1 << 0); |
| 2556 | fallthroughdo {} while (0); |
| 2557 | case SDVO_OUTPUT_RGB1(1 << 9): |
| 2558 | mask |= SDVO_OUTPUT_RGB1(1 << 9); |
| 2559 | fallthroughdo {} while (0); |
| 2560 | case SDVO_OUTPUT_RGB0(1 << 1): |
| 2561 | mask |= SDVO_OUTPUT_RGB0(1 << 1); |
| 2562 | break; |
| 2563 | } |
| 2564 | |
| 2565 | /* Count bits to find what number we are in the priority list. */ |
| 2566 | mask &= sdvo->caps.output_flags; |
| 2567 | num_bits = hweight16(mask); |
| 2568 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
| 2569 | if (num_bits > 3) |
| 2570 | num_bits = 3; |
| 2571 | |
| 2572 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
| 2573 | sdvo->ddc_bus = 1 << num_bits; |
| 2574 | } |
| 2575 | |
| 2576 | /* |
| 2577 | * Choose the appropriate DDC bus for control bus switch command for this |
| 2578 | * SDVO output based on the controlled output. |
| 2579 | * |
| 2580 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 2581 | * outputs, then LVDS outputs. |
| 2582 | */ |
| 2583 | static void |
| 2584 | intel_sdvo_select_ddc_bus(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 2585 | struct intel_sdvo *sdvo) |
| 2586 | { |
| 2587 | struct sdvo_device_mapping *mapping; |
| 2588 | |
| 2589 | if (sdvo->port == PORT_B) |
| 2590 | mapping = &dev_priv->display.vbt.sdvo_mappings[0]; |
| 2591 | else |
| 2592 | mapping = &dev_priv->display.vbt.sdvo_mappings[1]; |
| 2593 | |
| 2594 | if (mapping->initialized) |
| 2595 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
| 2596 | else |
| 2597 | intel_sdvo_guess_ddc_bus(sdvo); |
| 2598 | } |
| 2599 | |
| 2600 | static void |
| 2601 | intel_sdvo_select_i2c_bus(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 2602 | struct intel_sdvo *sdvo) |
| 2603 | { |
| 2604 | struct sdvo_device_mapping *mapping; |
| 2605 | u8 pin; |
| 2606 | |
| 2607 | if (sdvo->port == PORT_B) |
| 2608 | mapping = &dev_priv->display.vbt.sdvo_mappings[0]; |
| 2609 | else |
| 2610 | mapping = &dev_priv->display.vbt.sdvo_mappings[1]; |
| 2611 | |
| 2612 | if (mapping->initialized && |
| 2613 | intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) |
| 2614 | pin = mapping->i2c_pin; |
| 2615 | else |
| 2616 | pin = GMBUS_PIN_DPB5; |
| 2617 | |
| 2618 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
| 2619 | |
| 2620 | /* |
| 2621 | * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow |
| 2622 | * our code totally fails once we start using gmbus. Hence fall back to |
| 2623 | * bit banging for now. |
| 2624 | */ |
| 2625 | intel_gmbus_force_bit(sdvo->i2c, true1); |
| 2626 | } |
| 2627 | |
| 2628 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
| 2629 | static void |
| 2630 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) |
| 2631 | { |
| 2632 | intel_gmbus_force_bit(sdvo->i2c, false0); |
| 2633 | } |
| 2634 | |
| 2635 | static bool_Bool |
| 2636 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
| 2637 | { |
| 2638 | return intel_sdvo_check_supp_encode(intel_sdvo); |
| 2639 | } |
| 2640 | |
| 2641 | static u8 |
| 2642 | intel_sdvo_get_slave_addr(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 2643 | struct intel_sdvo *sdvo) |
| 2644 | { |
| 2645 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 2646 | |
| 2647 | if (sdvo->port == PORT_B) { |
| 2648 | my_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; |
| 2649 | other_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; |
| 2650 | } else { |
| 2651 | my_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; |
| 2652 | other_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; |
| 2653 | } |
| 2654 | |
| 2655 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 2656 | if (my_mapping->slave_addr) |
| 2657 | return my_mapping->slave_addr; |
| 2658 | |
| 2659 | /* |
| 2660 | * If the BIOS only described a different SDVO device, use the |
| 2661 | * address that it isn't using. |
| 2662 | */ |
| 2663 | if (other_mapping->slave_addr) { |
| 2664 | if (other_mapping->slave_addr == 0x70) |
| 2665 | return 0x72; |
| 2666 | else |
| 2667 | return 0x70; |
| 2668 | } |
| 2669 | |
| 2670 | /* |
| 2671 | * No SDVO device info is found for another DVO port, |
| 2672 | * so use mapping assumption we had before BIOS parsing. |
| 2673 | */ |
| 2674 | if (sdvo->port == PORT_B) |
| 2675 | return 0x70; |
| 2676 | else |
| 2677 | return 0x72; |
| 2678 | } |
| 2679 | |
| 2680 | static int |
| 2681 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
| 2682 | struct intel_sdvo *encoder) |
| 2683 | { |
| 2684 | struct drm_connector *drm_connector; |
| 2685 | int ret; |
| 2686 | |
| 2687 | drm_connector = &connector->base.base; |
| 2688 | ret = drm_connector_init(encoder->base.base.dev, |
| 2689 | drm_connector, |
| 2690 | &intel_sdvo_connector_funcs, |
| 2691 | connector->base.base.connector_type); |
| 2692 | if (ret < 0) |
| 2693 | return ret; |
| 2694 | |
| 2695 | drm_connector_helper_add(drm_connector, |
| 2696 | &intel_sdvo_connector_helper_funcs); |
| 2697 | |
| 2698 | connector->base.base.interlace_allowed = 1; |
| 2699 | connector->base.base.doublescan_allowed = 0; |
| 2700 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
| 2701 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
| 2702 | |
| 2703 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
| 2704 | |
| 2705 | return 0; |
| 2706 | } |
| 2707 | |
| 2708 | static void |
| 2709 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
| 2710 | struct intel_sdvo_connector *connector) |
| 2711 | { |
| 2712 | intel_attach_force_audio_property(&connector->base.base); |
| 2713 | if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220(1 << 1)) |
| 2714 | intel_attach_broadcast_rgb_property(&connector->base.base); |
| 2715 | intel_attach_aspect_ratio_property(&connector->base.base); |
| 2716 | } |
| 2717 | |
| 2718 | static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) |
| 2719 | { |
| 2720 | struct intel_sdvo_connector *sdvo_connector; |
| 2721 | struct intel_sdvo_connector_state *conn_state; |
| 2722 | |
| 2723 | sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL(0x0001 | 0x0004)); |
| 2724 | if (!sdvo_connector) |
| 2725 | return NULL((void *)0); |
| 2726 | |
| 2727 | conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL(0x0001 | 0x0004)); |
| 2728 | if (!conn_state) { |
| 2729 | kfree(sdvo_connector); |
| 2730 | return NULL((void *)0); |
| 2731 | } |
| 2732 | |
| 2733 | __drm_atomic_helper_connector_reset(&sdvo_connector->base.base, |
| 2734 | &conn_state->base.base); |
| 2735 | |
| 2736 | intel_panel_init_alloc(&sdvo_connector->base); |
| 2737 | |
| 2738 | return sdvo_connector; |
| 2739 | } |
| 2740 | |
| 2741 | static bool_Bool |
| 2742 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
| 2743 | { |
| 2744 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2745 | struct drm_connector *connector; |
| 2746 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof (struct intel_encoder, base) );}); |
| 2747 | struct intel_connector *intel_connector; |
| 2748 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2749 | |
| 2750 | DRM_DEBUG_KMS("initialising DVI device %d\n", device)___drm_dbg(((void *)0), DRM_UT_KMS, "initialising DVI device %d\n" , device); |
| 2751 | |
| 2752 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
| 2753 | if (!intel_sdvo_connector) |
| 2754 | return false0; |
| 2755 | |
| 2756 | if (device == 0) |
| 2757 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0(1 << 0); |
| 2758 | else if (device == 1) |
| 2759 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1(1 << 8); |
| 2760 | |
| 2761 | intel_connector = &intel_sdvo_connector->base; |
| 2762 | connector = &intel_connector->base; |
| 2763 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
| 2764 | intel_sdvo_connector->output_flag) { |
| 2765 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
| 2766 | /* |
| 2767 | * Some SDVO devices have one-shot hotplug interrupts. |
| 2768 | * Ensure that they get re-enabled when an interrupt happens. |
| 2769 | */ |
| 2770 | intel_connector->polled = DRM_CONNECTOR_POLL_HPD(1 << 0); |
| 2771 | intel_encoder->hotplug = intel_sdvo_hotplug; |
| 2772 | intel_sdvo_enable_hotplug(intel_encoder); |
| 2773 | } else { |
| 2774 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT(1 << 1) | DRM_CONNECTOR_POLL_DISCONNECT(1 << 2); |
| 2775 | } |
| 2776 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS2; |
| 2777 | connector->connector_type = DRM_MODE_CONNECTOR_DVID3; |
| 2778 | |
| 2779 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
| 2780 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA11; |
| 2781 | intel_sdvo_connector->is_hdmi = true1; |
| 2782 | } |
| 2783 | |
| 2784 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
| 2785 | kfree(intel_sdvo_connector); |
| 2786 | return false0; |
| 2787 | } |
| 2788 | |
| 2789 | if (intel_sdvo_connector->is_hdmi) |
| 2790 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
| 2791 | |
| 2792 | return true1; |
| 2793 | } |
| 2794 | |
| 2795 | static bool_Bool |
| 2796 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
| 2797 | { |
| 2798 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2799 | struct drm_connector *connector; |
| 2800 | struct intel_connector *intel_connector; |
| 2801 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2802 | |
| 2803 | DRM_DEBUG_KMS("initialising TV type %d\n", type)___drm_dbg(((void *)0), DRM_UT_KMS, "initialising TV type %d\n" , type); |
| 2804 | |
| 2805 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
| 2806 | if (!intel_sdvo_connector) |
| 2807 | return false0; |
| 2808 | |
| 2809 | intel_connector = &intel_sdvo_connector->base; |
| 2810 | connector = &intel_connector->base; |
| 2811 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC4; |
| 2812 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO6; |
| 2813 | |
| 2814 | intel_sdvo_connector->output_flag = type; |
| 2815 | |
| 2816 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
| 2817 | kfree(intel_sdvo_connector); |
| 2818 | return false0; |
| 2819 | } |
| 2820 | |
| 2821 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
| 2822 | goto err; |
| 2823 | |
| 2824 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
| 2825 | goto err; |
| 2826 | |
| 2827 | return true1; |
| 2828 | |
| 2829 | err: |
| 2830 | intel_connector_destroy(connector); |
| 2831 | return false0; |
| 2832 | } |
| 2833 | |
| 2834 | static bool_Bool |
| 2835 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
| 2836 | { |
| 2837 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2838 | struct drm_connector *connector; |
| 2839 | struct intel_connector *intel_connector; |
| 2840 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2841 | |
| 2842 | DRM_DEBUG_KMS("initialising analog device %d\n", device)___drm_dbg(((void *)0), DRM_UT_KMS, "initialising analog device %d\n" , device); |
| 2843 | |
| 2844 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
| 2845 | if (!intel_sdvo_connector) |
| 2846 | return false0; |
| 2847 | |
| 2848 | intel_connector = &intel_sdvo_connector->base; |
| 2849 | connector = &intel_connector->base; |
| 2850 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT(1 << 1); |
| 2851 | encoder->encoder_type = DRM_MODE_ENCODER_DAC1; |
| 2852 | connector->connector_type = DRM_MODE_CONNECTOR_VGA1; |
| 2853 | |
| 2854 | if (device == 0) |
| 2855 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0(1 << 1); |
| 2856 | else if (device == 1) |
| 2857 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1(1 << 9); |
| 2858 | |
| 2859 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
| 2860 | kfree(intel_sdvo_connector); |
| 2861 | return false0; |
| 2862 | } |
| 2863 | |
| 2864 | return true1; |
| 2865 | } |
| 2866 | |
| 2867 | static bool_Bool |
| 2868 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
| 2869 | { |
| 2870 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2871 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->dev); |
| 2872 | struct drm_connector *connector; |
| 2873 | struct intel_connector *intel_connector; |
| 2874 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2875 | |
| 2876 | DRM_DEBUG_KMS("initialising LVDS device %d\n", device)___drm_dbg(((void *)0), DRM_UT_KMS, "initialising LVDS device %d\n" , device); |
| 2877 | |
| 2878 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
| 2879 | if (!intel_sdvo_connector) |
| 2880 | return false0; |
| 2881 | |
| 2882 | intel_connector = &intel_sdvo_connector->base; |
| 2883 | connector = &intel_connector->base; |
| 2884 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS3; |
| 2885 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS7; |
| 2886 | |
| 2887 | if (device == 0) |
| 2888 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0(1 << 6); |
| 2889 | else if (device == 1) |
| 2890 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1(1 << 14); |
| 2891 | |
| 2892 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
| 2893 | kfree(intel_sdvo_connector); |
| 2894 | return false0; |
| 2895 | } |
| 2896 | |
| 2897 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
| 2898 | goto err; |
| 2899 | |
| 2900 | intel_bios_init_panel_late(i915, &intel_connector->panel, NULL((void *)0), NULL((void *)0)); |
| 2901 | |
| 2902 | /* |
| 2903 | * Fetch modes from VBT. For SDVO prefer the VBT mode since some |
| 2904 | * SDVO->LVDS transcoders can't cope with the EDID mode. |
| 2905 | */ |
| 2906 | intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); |
| 2907 | |
| 2908 | if (!intel_panel_preferred_fixed_mode(intel_connector)) { |
| 2909 | mutex_lock(&i915->drm.mode_config.mutex)rw_enter_write(&i915->drm.mode_config.mutex); |
| 2910 | |
| 2911 | intel_ddc_get_modes(connector, &intel_sdvo->ddc); |
| 2912 | intel_panel_add_edid_fixed_modes(intel_connector, false0); |
| 2913 | |
| 2914 | mutex_unlock(&i915->drm.mode_config.mutex)rw_exit_write(&i915->drm.mode_config.mutex); |
| 2915 | } |
| 2916 | |
| 2917 | intel_panel_init(intel_connector); |
| 2918 | |
| 2919 | if (!intel_panel_preferred_fixed_mode(intel_connector)) |
| 2920 | goto err; |
| 2921 | |
| 2922 | return true1; |
| 2923 | |
| 2924 | err: |
| 2925 | intel_connector_destroy(connector); |
| 2926 | return false0; |
| 2927 | } |
| 2928 | |
| 2929 | static u16 intel_sdvo_filter_output_flags(u16 flags) |
| 2930 | { |
| 2931 | flags &= SDVO_OUTPUT_MASK(((1 << 0) | (1 << 8)) | ((1 << 1) | (1 << 9)) | ((1 << 6) | (1 << 14)) | ((1 << 2) | (1 << 3) | (1 << 4))); |
| 2932 | |
| 2933 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
| 2934 | if (!(flags & SDVO_OUTPUT_TMDS0(1 << 0))) |
| 2935 | flags &= ~SDVO_OUTPUT_TMDS1(1 << 8); |
| 2936 | |
| 2937 | if (!(flags & SDVO_OUTPUT_RGB0(1 << 1))) |
| 2938 | flags &= ~SDVO_OUTPUT_RGB1(1 << 9); |
| 2939 | |
| 2940 | if (!(flags & SDVO_OUTPUT_LVDS0(1 << 6))) |
| 2941 | flags &= ~SDVO_OUTPUT_LVDS1(1 << 14); |
| 2942 | |
| 2943 | return flags; |
| 2944 | } |
| 2945 | |
| 2946 | static bool_Bool |
| 2947 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags) |
| 2948 | { |
| 2949 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_sdvo->base.base.dev); |
| 2950 | |
| 2951 | flags = intel_sdvo_filter_output_flags(flags); |
| 2952 | |
| 2953 | intel_sdvo->controlled_output = flags; |
| 2954 | |
| 2955 | intel_sdvo_select_ddc_bus(i915, intel_sdvo); |
| 2956 | |
| 2957 | if (flags & SDVO_OUTPUT_TMDS0(1 << 0)) |
| 2958 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
| 2959 | return false0; |
| 2960 | |
| 2961 | if (flags & SDVO_OUTPUT_TMDS1(1 << 8)) |
| 2962 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
| 2963 | return false0; |
| 2964 | |
| 2965 | /* TV has no XXX1 function block */ |
| 2966 | if (flags & SDVO_OUTPUT_SVID0(1 << 3)) |
| 2967 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0(1 << 3))) |
| 2968 | return false0; |
| 2969 | |
| 2970 | if (flags & SDVO_OUTPUT_CVBS0(1 << 2)) |
| 2971 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0(1 << 2))) |
| 2972 | return false0; |
| 2973 | |
| 2974 | if (flags & SDVO_OUTPUT_YPRPB0(1 << 4)) |
| 2975 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0(1 << 4))) |
| 2976 | return false0; |
| 2977 | |
| 2978 | if (flags & SDVO_OUTPUT_RGB0(1 << 1)) |
| 2979 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
| 2980 | return false0; |
| 2981 | |
| 2982 | if (flags & SDVO_OUTPUT_RGB1(1 << 9)) |
| 2983 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
| 2984 | return false0; |
| 2985 | |
| 2986 | if (flags & SDVO_OUTPUT_LVDS0(1 << 6)) |
| 2987 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
| 2988 | return false0; |
| 2989 | |
| 2990 | if (flags & SDVO_OUTPUT_LVDS1(1 << 14)) |
| 2991 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
| 2992 | return false0; |
| 2993 | |
| 2994 | if (flags == 0) { |
| 2995 | unsigned char bytes[2]; |
| 2996 | |
| 2997 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2)__builtin_memcpy((bytes), (&intel_sdvo->caps.output_flags ), (2)); |
| 2998 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Unknown SDVO output type (0x%02x%02x)\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), bytes [0], bytes[1]) |
| 2999 | SDVO_NAME(intel_sdvo),___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Unknown SDVO output type (0x%02x%02x)\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), bytes [0], bytes[1]) |
| 3000 | bytes[0], bytes[1])___drm_dbg(((void *)0), DRM_UT_KMS, "%s: Unknown SDVO output type (0x%02x%02x)\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), bytes [0], bytes[1]); |
| 3001 | return false0; |
| 3002 | } |
| 3003 | intel_sdvo->base.pipe_mask = ~0; |
| 3004 | |
| 3005 | return true1; |
| 3006 | } |
| 3007 | |
| 3008 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
| 3009 | { |
| 3010 | struct drm_device *dev = intel_sdvo->base.base.dev; |
| 3011 | struct drm_connector *connector, *tmp; |
| 3012 | |
| 3013 | list_for_each_entry_safe(connector, tmp,for (connector = ({ const __typeof( ((__typeof(*connector) *) 0)->head ) *__mptr = ((&dev->mode_config.connector_list )->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof (__typeof(*connector), head) );}), tmp = ({ const __typeof( ( (__typeof(*connector) *)0)->head ) *__mptr = (connector-> head.next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof (__typeof(*connector), head) );}); &connector->head != (&dev->mode_config.connector_list); connector = tmp, tmp = ({ const __typeof( ((__typeof(*tmp) *)0)->head ) *__mptr = (tmp->head.next); (__typeof(*tmp) *)( (char *)__mptr - __builtin_offsetof (__typeof(*tmp), head) );})) |
| 3014 | &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *) 0)->head ) *__mptr = ((&dev->mode_config.connector_list )->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof (__typeof(*connector), head) );}), tmp = ({ const __typeof( ( (__typeof(*connector) *)0)->head ) *__mptr = (connector-> head.next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof (__typeof(*connector), head) );}); &connector->head != (&dev->mode_config.connector_list); connector = tmp, tmp = ({ const __typeof( ((__typeof(*tmp) *)0)->head ) *__mptr = (tmp->head.next); (__typeof(*tmp) *)( (char *)__mptr - __builtin_offsetof (__typeof(*tmp), head) );})) { |
| 3015 | if (intel_attached_encoder(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})) == &intel_sdvo->base) { |
| 3016 | drm_connector_unregister(connector); |
| 3017 | intel_connector_destroy(connector); |
| 3018 | } |
| 3019 | } |
| 3020 | } |
| 3021 | |
| 3022 | static bool_Bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 3023 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 3024 | int type) |
| 3025 | { |
| 3026 | struct drm_device *dev = intel_sdvo->base.base.dev; |
| 3027 | struct intel_sdvo_tv_format format; |
| 3028 | u32 format_map, i; |
| 3029 | |
| 3030 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
| 3031 | return false0; |
| 3032 | |
| 3033 | BUILD_BUG_ON(sizeof(format) != 6)extern char _ctassert[(!(sizeof(format) != 6)) ? 1 : -1 ] __attribute__ ((__unused__)); |
| 3034 | if (!intel_sdvo_get_value(intel_sdvo, |
| 3035 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS0x27, |
| 3036 | &format, sizeof(format))) |
| 3037 | return false0; |
| 3038 | |
| 3039 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)))__builtin_memcpy((&format_map), (&format), ((((sizeof (format_map))<(sizeof(format)))?(sizeof(format_map)):(sizeof (format))))); |
| 3040 | |
| 3041 | if (format_map == 0) |
| 3042 | return false0; |
| 3043 | |
| 3044 | intel_sdvo_connector->format_supported_num = 0; |
| 3045 | for (i = 0 ; i < TV_FORMAT_NUM(sizeof((tv_format_names)) / sizeof((tv_format_names)[0])); i++) |
| 3046 | if (format_map & (1 << i)) |
| 3047 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
| 3048 | |
| 3049 | |
| 3050 | intel_sdvo_connector->tv_format = |
| 3051 | drm_property_create(dev, DRM_MODE_PROP_ENUM(1<<3), |
| 3052 | "mode", intel_sdvo_connector->format_supported_num); |
| 3053 | if (!intel_sdvo_connector->tv_format) |
| 3054 | return false0; |
| 3055 | |
| 3056 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
| 3057 | drm_property_add_enum(intel_sdvo_connector->tv_format, i, |
| 3058 | tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
| 3059 | |
| 3060 | intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0]; |
| 3061 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
| 3062 | intel_sdvo_connector->tv_format, 0); |
| 3063 | return true1; |
| 3064 | |
| 3065 | } |
| 3066 | |
| 3067 | #define _ENHANCEMENT(state_assignment, name, NAME) do { \ |
| 3068 | if (enhancements.name) { \ |
| 3069 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
| 3070 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
| 3071 | return false0; \ |
| 3072 | intel_sdvo_connector->name = \ |
| 3073 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
| 3074 | if (!intel_sdvo_connector->name) return false0; \ |
| 3075 | state_assignment = response; \ |
| 3076 | drm_object_attach_property(&connector->base, \ |
| 3077 | intel_sdvo_connector->name, 0); \ |
| 3078 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \___drm_dbg(((void *)0), DRM_UT_KMS, #name ": max %d, default %d, current %d\n" , data_value[0], data_value[1], response) |
| 3079 | data_value[0], data_value[1], response)___drm_dbg(((void *)0), DRM_UT_KMS, #name ": max %d, default %d, current %d\n" , data_value[0], data_value[1], response); \ |
| 3080 | } \ |
| 3081 | } while (0) |
| 3082 | |
| 3083 | #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME) |
| 3084 | |
| 3085 | static bool_Bool |
| 3086 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
| 3087 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 3088 | struct intel_sdvo_enhancements_reply enhancements) |
| 3089 | { |
| 3090 | struct drm_device *dev = intel_sdvo->base.base.dev; |
| 3091 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
| 3092 | struct drm_connector_state *conn_state = connector->state; |
| 3093 | struct intel_sdvo_connector_state *sdvo_state = |
| 3094 | to_intel_sdvo_connector_state(conn_state)({ const __typeof( ((struct intel_sdvo_connector_state *)0)-> base.base ) *__mptr = ((conn_state)); (struct intel_sdvo_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_sdvo_connector_state , base.base) );}); |
| 3095 | u16 response, data_value[2]; |
| 3096 | |
| 3097 | /* when horizontal overscan is supported, Add the left/right property */ |
| 3098 | if (enhancements.overscan_h) { |
| 3099 | if (!intel_sdvo_get_value(intel_sdvo, |
| 3100 | SDVO_CMD_GET_MAX_OVERSCAN_H0x61, |
| 3101 | &data_value, 4)) |
| 3102 | return false0; |
| 3103 | |
| 3104 | if (!intel_sdvo_get_value(intel_sdvo, |
| 3105 | SDVO_CMD_GET_OVERSCAN_H0x62, |
| 3106 | &response, 2)) |
| 3107 | return false0; |
| 3108 | |
| 3109 | sdvo_state->tv.overscan_h = response; |
| 3110 | |
| 3111 | intel_sdvo_connector->max_hscan = data_value[0]; |
| 3112 | intel_sdvo_connector->left = |
| 3113 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
| 3114 | if (!intel_sdvo_connector->left) |
| 3115 | return false0; |
| 3116 | |
| 3117 | drm_object_attach_property(&connector->base, |
| 3118 | intel_sdvo_connector->left, 0); |
| 3119 | |
| 3120 | intel_sdvo_connector->right = |
| 3121 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
| 3122 | if (!intel_sdvo_connector->right) |
| 3123 | return false0; |
| 3124 | |
| 3125 | drm_object_attach_property(&connector->base, |
| 3126 | intel_sdvo_connector->right, 0); |
| 3127 | DRM_DEBUG_KMS("h_overscan: max %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "h_overscan: max %d, " "default %d, current %d\n" , data_value[0], data_value[1], response) |
| 3128 | "default %d, current %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "h_overscan: max %d, " "default %d, current %d\n" , data_value[0], data_value[1], response) |
| 3129 | data_value[0], data_value[1], response)___drm_dbg(((void *)0), DRM_UT_KMS, "h_overscan: max %d, " "default %d, current %d\n" , data_value[0], data_value[1], response); |
| 3130 | } |
| 3131 | |
| 3132 | if (enhancements.overscan_v) { |
| 3133 | if (!intel_sdvo_get_value(intel_sdvo, |
| 3134 | SDVO_CMD_GET_MAX_OVERSCAN_V0x64, |
| 3135 | &data_value, 4)) |
| 3136 | return false0; |
| 3137 | |
| 3138 | if (!intel_sdvo_get_value(intel_sdvo, |
| 3139 | SDVO_CMD_GET_OVERSCAN_V0x65, |
| 3140 | &response, 2)) |
| 3141 | return false0; |
| 3142 | |
| 3143 | sdvo_state->tv.overscan_v = response; |
| 3144 | |
| 3145 | intel_sdvo_connector->max_vscan = data_value[0]; |
| 3146 | intel_sdvo_connector->top = |
| 3147 | drm_property_create_range(dev, 0, |
| 3148 | "top_margin", 0, data_value[0]); |
| 3149 | if (!intel_sdvo_connector->top) |
| 3150 | return false0; |
| 3151 | |
| 3152 | drm_object_attach_property(&connector->base, |
| 3153 | intel_sdvo_connector->top, 0); |
| 3154 | |
| 3155 | intel_sdvo_connector->bottom = |
| 3156 | drm_property_create_range(dev, 0, |
| 3157 | "bottom_margin", 0, data_value[0]); |
| 3158 | if (!intel_sdvo_connector->bottom) |
| 3159 | return false0; |
| 3160 | |
| 3161 | drm_object_attach_property(&connector->base, |
| 3162 | intel_sdvo_connector->bottom, 0); |
| 3163 | DRM_DEBUG_KMS("v_overscan: max %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "v_overscan: max %d, " "default %d, current %d\n" , data_value[0], data_value[1], response) |
| 3164 | "default %d, current %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "v_overscan: max %d, " "default %d, current %d\n" , data_value[0], data_value[1], response) |
| 3165 | data_value[0], data_value[1], response)___drm_dbg(((void *)0), DRM_UT_KMS, "v_overscan: max %d, " "default %d, current %d\n" , data_value[0], data_value[1], response); |
| 3166 | } |
| 3167 | |
| 3168 | ENHANCEMENT(&sdvo_state->tv, hpos, HPOS); |
| 3169 | ENHANCEMENT(&sdvo_state->tv, vpos, VPOS); |
| 3170 | ENHANCEMENT(&conn_state->tv, saturation, SATURATION); |
| 3171 | ENHANCEMENT(&conn_state->tv, contrast, CONTRAST); |
| 3172 | ENHANCEMENT(&conn_state->tv, hue, HUE); |
| 3173 | ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS); |
| 3174 | ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS); |
| 3175 | ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER); |
| 3176 | ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
| 3177 | ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D); |
| 3178 | _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER); |
| 3179 | _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER); |
| 3180 | |
| 3181 | if (enhancements.dot_crawl) { |
| 3182 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL0x70, &response, 2)) |
| 3183 | return false0; |
| 3184 | |
| 3185 | sdvo_state->tv.dot_crawl = response & 0x1; |
| 3186 | intel_sdvo_connector->dot_crawl = |
| 3187 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
| 3188 | if (!intel_sdvo_connector->dot_crawl) |
| 3189 | return false0; |
| 3190 | |
| 3191 | drm_object_attach_property(&connector->base, |
| 3192 | intel_sdvo_connector->dot_crawl, 0); |
| 3193 | DRM_DEBUG_KMS("dot crawl: current %d\n", response)___drm_dbg(((void *)0), DRM_UT_KMS, "dot crawl: current %d\n" , response); |
| 3194 | } |
| 3195 | |
| 3196 | return true1; |
| 3197 | } |
| 3198 | |
| 3199 | static bool_Bool |
| 3200 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
| 3201 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 3202 | struct intel_sdvo_enhancements_reply enhancements) |
| 3203 | { |
| 3204 | struct drm_device *dev = intel_sdvo->base.base.dev; |
| 3205 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
| 3206 | u16 response, data_value[2]; |
| 3207 | |
| 3208 | ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS); |
| 3209 | |
| 3210 | return true1; |
| 3211 | } |
| 3212 | #undef ENHANCEMENT |
| 3213 | #undef _ENHANCEMENT |
| 3214 | |
| 3215 | static bool_Bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 3216 | struct intel_sdvo_connector *intel_sdvo_connector) |
| 3217 | { |
| 3218 | union { |
| 3219 | struct intel_sdvo_enhancements_reply reply; |
| 3220 | u16 response; |
| 3221 | } enhancements; |
| 3222 | |
| 3223 | BUILD_BUG_ON(sizeof(enhancements) != 2)extern char _ctassert[(!(sizeof(enhancements) != 2)) ? 1 : -1 ] __attribute__((__unused__)); |
| 3224 | |
| 3225 | if (!intel_sdvo_get_value(intel_sdvo, |
| 3226 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS0x84, |
| 3227 | &enhancements, sizeof(enhancements)) || |
| 3228 | enhancements.response == 0) { |
| 3229 | DRM_DEBUG_KMS("No enhancement is supported\n")___drm_dbg(((void *)0), DRM_UT_KMS, "No enhancement is supported\n" ); |
| 3230 | return true1; |
| 3231 | } |
| 3232 | |
| 3233 | if (IS_TV(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 2) | (1 << 3) | (1 << 4)))) |
| 3234 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 3235 | else if (IS_LVDS(intel_sdvo_connector)(intel_sdvo_connector->output_flag & ((1 << 6) | (1 << 14)))) |
| 3236 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 3237 | else |
| 3238 | return true1; |
| 3239 | } |
| 3240 | |
| 3241 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, |
| 3242 | struct i2c_msg *msgs, |
| 3243 | int num) |
| 3244 | { |
| 3245 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 3246 | |
| 3247 | if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
| 3248 | return -EIO5; |
| 3249 | |
| 3250 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); |
| 3251 | } |
| 3252 | |
| 3253 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) |
| 3254 | { |
| 3255 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 3256 | return sdvo->i2c->algo->functionality(sdvo->i2c); |
| 3257 | } |
| 3258 | |
| 3259 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { |
| 3260 | .master_xfer = intel_sdvo_ddc_proxy_xfer, |
| 3261 | .functionality = intel_sdvo_ddc_proxy_func |
| 3262 | }; |
| 3263 | |
| 3264 | static void proxy_lock_bus(struct i2c_adapter *adapter, |
| 3265 | unsigned int flags) |
| 3266 | { |
| 3267 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 3268 | sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); |
| 3269 | } |
| 3270 | |
| 3271 | static int proxy_trylock_bus(struct i2c_adapter *adapter, |
| 3272 | unsigned int flags) |
| 3273 | { |
| 3274 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 3275 | return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); |
| 3276 | } |
| 3277 | |
| 3278 | static void proxy_unlock_bus(struct i2c_adapter *adapter, |
| 3279 | unsigned int flags) |
| 3280 | { |
| 3281 | struct intel_sdvo *sdvo = adapter->algo_data; |
| 3282 | sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); |
| 3283 | } |
| 3284 | |
| 3285 | static const struct i2c_lock_operations proxy_lock_ops = { |
| 3286 | .lock_bus = proxy_lock_bus, |
| 3287 | .trylock_bus = proxy_trylock_bus, |
| 3288 | .unlock_bus = proxy_unlock_bus, |
| 3289 | }; |
| 3290 | |
| 3291 | static bool_Bool |
| 3292 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, |
| 3293 | struct drm_i915_privateinteldrm_softc *dev_priv) |
| 3294 | { |
| 3295 | struct pci_dev *pdev = dev_priv->drm.pdev; |
| 3296 | |
| 3297 | #ifdef __linux__ |
| 3298 | sdvo->ddc.owner = THIS_MODULE((void *)0); |
| 3299 | sdvo->ddc.class = I2C_CLASS_DDC; |
| 3300 | #endif |
| 3301 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE20, "SDVO DDC proxy"); |
| 3302 | #ifdef __linux__ |
| 3303 | sdvo->ddc.dev.parent = &pdev->dev; |
| 3304 | #endif |
| 3305 | sdvo->ddc.algo_data = sdvo; |
| 3306 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; |
| 3307 | sdvo->ddc.lock_ops = &proxy_lock_ops; |
| 3308 | |
| 3309 | return i2c_add_adapter(&sdvo->ddc) == 0; |
| 3310 | } |
| 3311 | |
| 3312 | static void assert_sdvo_port_valid(const struct drm_i915_privateinteldrm_softc *dev_priv, |
| 3313 | enum port port) |
| 3314 | { |
| 3315 | if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) |
| 3316 | drm_WARN_ON(&dev_priv->drm, port != PORT_B)({ int __ret = !!((port != PORT_B)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "port != PORT_B" ")"); __builtin_expect(!!(__ret ), 0); }); |
| 3317 | else |
| 3318 | drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C)({ int __ret = !!((port != PORT_B && port != PORT_C)) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "port != PORT_B && port != PORT_C" ")"); __builtin_expect(!!(__ret), 0); }); |
| 3319 | } |
| 3320 | |
| 3321 | bool_Bool intel_sdvo_init(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 3322 | i915_reg_t sdvo_reg, enum port port) |
| 3323 | { |
| 3324 | struct intel_encoder *intel_encoder; |
| 3325 | struct intel_sdvo *intel_sdvo; |
| 3326 | int i; |
| 3327 | |
| 3328 | assert_sdvo_port_valid(dev_priv, port); |
| 3329 | |
| 3330 | intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL(0x0001 | 0x0004)); |
| 3331 | if (!intel_sdvo) |
| 3332 | return false0; |
| 3333 | |
| 3334 | intel_sdvo->sdvo_reg = sdvo_reg; |
| 3335 | intel_sdvo->port = port; |
| 3336 | intel_sdvo->slave_addr = |
| 3337 | intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1; |
| 3338 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); |
| 3339 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv)) |
| 3340 | goto err_i2c_bus; |
| 3341 | |
| 3342 | /* encoder type will be decided later */ |
| 3343 | intel_encoder = &intel_sdvo->base; |
| 3344 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
| 3345 | intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; |
| 3346 | intel_encoder->port = port; |
| 3347 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
| 3348 | &intel_sdvo_enc_funcs, 0, |
| 3349 | "SDVO %c", port_name(port)((port) + 'A')); |
| 3350 | |
| 3351 | /* Read the regs to test if we can talk to the device */ |
| 3352 | for (i = 0; i < 0x40; i++) { |
| 3353 | u8 byte; |
| 3354 | |
| 3355 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
| 3356 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "No SDVO device found on %s\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC")) |
| 3357 | "No SDVO device found on %s\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "No SDVO device found on %s\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC")) |
| 3358 | SDVO_NAME(intel_sdvo))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "No SDVO device found on %s\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC")); |
| 3359 | goto err; |
| 3360 | } |
| 3361 | } |
| 3362 | |
| 3363 | intel_encoder->compute_config = intel_sdvo_compute_config; |
| 3364 | if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 3365 | intel_encoder->disable = pch_disable_sdvo; |
| 3366 | intel_encoder->post_disable = pch_post_disable_sdvo; |
| 3367 | } else { |
| 3368 | intel_encoder->disable = intel_disable_sdvo; |
| 3369 | } |
| 3370 | intel_encoder->pre_enable = intel_sdvo_pre_enable; |
| 3371 | intel_encoder->enable = intel_enable_sdvo; |
| 3372 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
| 3373 | intel_encoder->get_config = intel_sdvo_get_config; |
| 3374 | |
| 3375 | /* In default case sdvo lvds is false */ |
| 3376 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
| 3377 | goto err; |
| 3378 | |
| 3379 | intel_sdvo->colorimetry_cap = |
| 3380 | intel_sdvo_get_colorimetry_cap(intel_sdvo); |
| 3381 | |
| 3382 | if (intel_sdvo_output_setup(intel_sdvo, |
| 3383 | intel_sdvo->caps.output_flags) != true1) { |
| 3384 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "SDVO output failed to setup on %s\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC")) |
| 3385 | "SDVO output failed to setup on %s\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "SDVO output failed to setup on %s\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC")) |
| 3386 | SDVO_NAME(intel_sdvo))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "SDVO output failed to setup on %s\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC")); |
| 3387 | /* Output_setup can leave behind connectors! */ |
| 3388 | goto err_output; |
| 3389 | } |
| 3390 | |
| 3391 | /* |
| 3392 | * Only enable the hotplug irq if we need it, to work around noisy |
| 3393 | * hotplug lines. |
| 3394 | */ |
| 3395 | if (intel_sdvo->hotplug_active) { |
| 3396 | if (intel_sdvo->port == PORT_B) |
| 3397 | intel_encoder->hpd_pin = HPD_SDVO_B; |
| 3398 | else |
| 3399 | intel_encoder->hpd_pin = HPD_SDVO_C; |
| 3400 | } |
| 3401 | |
| 3402 | /* |
| 3403 | * Cloning SDVO with anything is often impossible, since the SDVO |
| 3404 | * encoder can request a special input timing mode. And even if that's |
| 3405 | * not the case we have evidence that cloning a plain unscaled mode with |
| 3406 | * VGA doesn't really work. Furthermore the cloning flags are way too |
| 3407 | * simplistic anyway to express such constraints, so just give up on |
| 3408 | * cloning for SDVO encoders. |
| 3409 | */ |
| 3410 | intel_sdvo->base.cloneable = 0; |
| 3411 | |
| 3412 | /* Set the input timing to the screen. Assume always input 0. */ |
| 3413 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 3414 | goto err_output; |
| 3415 | |
| 3416 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
| 3417 | &intel_sdvo->pixel_clock_min, |
| 3418 | &intel_sdvo->pixel_clock_max)) |
| 3419 | goto err_output; |
| 3420 | |
| 3421 | drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3422 | "clock range %dMHz - %dMHz, "__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3423 | "input 1: %c, input 2: %c, "__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3424 | "output 1: %c, output 2: %c\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3425 | SDVO_NAME(intel_sdvo),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3426 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3427 | intel_sdvo->caps.device_rev_id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3428 | intel_sdvo->pixel_clock_min / 1000,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3429 | intel_sdvo->pixel_clock_max / 1000,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3430 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3431 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3432 | /* check currently supported outputs */__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3433 | intel_sdvo->caps.output_flags &__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3434 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3435 | intel_sdvo->caps.output_flags &__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N') |
| 3436 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N')__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n" , ((intel_sdvo)->port == PORT_B ? "SDVOB" : "SDVOC"), intel_sdvo ->caps.vendor_id, intel_sdvo->caps.device_id, intel_sdvo ->caps.device_rev_id, intel_sdvo->pixel_clock_min / 1000 , intel_sdvo->pixel_clock_max / 1000, (intel_sdvo->caps .sdvo_inputs_mask & 0x1) ? 'Y' : 'N', (intel_sdvo->caps .sdvo_inputs_mask & 0x2) ? 'Y' : 'N', intel_sdvo->caps .output_flags & ((1 << 0) | (1 << 1)) ? 'Y' : 'N', intel_sdvo->caps.output_flags & ((1 << 8) | (1 << 9)) ? 'Y' : 'N'); |
| 3437 | return true1; |
| 3438 | |
| 3439 | err_output: |
| 3440 | intel_sdvo_output_cleanup(intel_sdvo); |
| 3441 | |
| 3442 | err: |
| 3443 | drm_encoder_cleanup(&intel_encoder->base); |
| 3444 | i2c_del_adapter(&intel_sdvo->ddc); |
| 3445 | err_i2c_bus: |
| 3446 | intel_sdvo_unselect_i2c_bus(intel_sdvo); |
| 3447 | kfree(intel_sdvo); |
| 3448 | |
| 3449 | return false0; |
| 3450 | } |