File: | dev/pci/drm/amd/display/dc/core/amdgpu_dc.c |
Warning: | line 3949, column 31 Assigned value is garbage or undefined |
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1 | /* | ||||
2 | * Copyright 2015 Advanced Micro Devices, Inc. | ||||
3 | * | ||||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||||
5 | * copy of this software and associated documentation files (the "Software"), | ||||
6 | * to deal in the Software without restriction, including without limitation | ||||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||||
9 | * Software is furnished to do so, subject to the following conditions: | ||||
10 | * | ||||
11 | * The above copyright notice and this permission notice shall be included in | ||||
12 | * all copies or substantial portions of the Software. | ||||
13 | * | ||||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||||
21 | * | ||||
22 | * Authors: AMD | ||||
23 | */ | ||||
24 | |||||
25 | #include "dm_services.h" | ||||
26 | |||||
27 | #include "dc.h" | ||||
28 | |||||
29 | #include "core_status.h" | ||||
30 | #include "core_types.h" | ||||
31 | #include "hw_sequencer.h" | ||||
32 | #include "dce/dce_hwseq.h" | ||||
33 | |||||
34 | #include "resource.h" | ||||
35 | |||||
36 | #include "clk_mgr.h" | ||||
37 | #include "clock_source.h" | ||||
38 | #include "dc_bios_types.h" | ||||
39 | |||||
40 | #include "bios_parser_interface.h" | ||||
41 | #include "bios/bios_parser_helper.h" | ||||
42 | #include "include/irq_service_interface.h" | ||||
43 | #include "transform.h" | ||||
44 | #include "dmcu.h" | ||||
45 | #include "dpp.h" | ||||
46 | #include "timing_generator.h" | ||||
47 | #include "abm.h" | ||||
48 | #include "virtual/virtual_link_encoder.h" | ||||
49 | #include "hubp.h" | ||||
50 | |||||
51 | #include "link_hwss.h" | ||||
52 | #include "link_encoder.h" | ||||
53 | #include "link_enc_cfg.h" | ||||
54 | |||||
55 | #include "dc_link.h" | ||||
56 | #include "dc_link_ddc.h" | ||||
57 | #include "dm_helpers.h" | ||||
58 | #include "mem_input.h" | ||||
59 | |||||
60 | #include "dc_link_dp.h" | ||||
61 | #include "dc_dmub_srv.h" | ||||
62 | |||||
63 | #include "dsc.h" | ||||
64 | |||||
65 | #include "vm_helper.h" | ||||
66 | |||||
67 | #include "dce/dce_i2c.h" | ||||
68 | |||||
69 | #include "dmub/dmub_srv.h" | ||||
70 | |||||
71 | #include "i2caux_interface.h" | ||||
72 | |||||
73 | #include "dce/dmub_psr.h" | ||||
74 | |||||
75 | #include "dce/dmub_hw_lock_mgr.h" | ||||
76 | |||||
77 | #include "dc_trace.h" | ||||
78 | |||||
79 | #include "dce/dmub_outbox.h" | ||||
80 | |||||
81 | #define CTXdc->ctx \ | ||||
82 | dc->ctx | ||||
83 | |||||
84 | #define DC_LOGGERdc->ctx->logger \ | ||||
85 | dc->ctx->logger | ||||
86 | |||||
87 | static const char DC_BUILD_ID[] = "production-build"; | ||||
88 | |||||
89 | /** | ||||
90 | * DOC: Overview | ||||
91 | * | ||||
92 | * DC is the OS-agnostic component of the amdgpu DC driver. | ||||
93 | * | ||||
94 | * DC maintains and validates a set of structs representing the state of the | ||||
95 | * driver and writes that state to AMD hardware | ||||
96 | * | ||||
97 | * Main DC HW structs: | ||||
98 | * | ||||
99 | * struct dc - The central struct. One per driver. Created on driver load, | ||||
100 | * destroyed on driver unload. | ||||
101 | * | ||||
102 | * struct dc_context - One per driver. | ||||
103 | * Used as a backpointer by most other structs in dc. | ||||
104 | * | ||||
105 | * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP | ||||
106 | * plugpoints). Created on driver load, destroyed on driver unload. | ||||
107 | * | ||||
108 | * struct dc_sink - One per display. Created on boot or hotplug. | ||||
109 | * Destroyed on shutdown or hotunplug. A dc_link can have a local sink | ||||
110 | * (the display directly attached). It may also have one or more remote | ||||
111 | * sinks (in the Multi-Stream Transport case) | ||||
112 | * | ||||
113 | * struct resource_pool - One per driver. Represents the hw blocks not in the | ||||
114 | * main pipeline. Not directly accessible by dm. | ||||
115 | * | ||||
116 | * Main dc state structs: | ||||
117 | * | ||||
118 | * These structs can be created and destroyed as needed. There is a full set of | ||||
119 | * these structs in dc->current_state representing the currently programmed state. | ||||
120 | * | ||||
121 | * struct dc_state - The global DC state to track global state information, | ||||
122 | * such as bandwidth values. | ||||
123 | * | ||||
124 | * struct dc_stream_state - Represents the hw configuration for the pipeline from | ||||
125 | * a framebuffer to a display. Maps one-to-one with dc_sink. | ||||
126 | * | ||||
127 | * struct dc_plane_state - Represents a framebuffer. Each stream has at least one, | ||||
128 | * and may have more in the Multi-Plane Overlay case. | ||||
129 | * | ||||
130 | * struct resource_context - Represents the programmable state of everything in | ||||
131 | * the resource_pool. Not directly accessible by dm. | ||||
132 | * | ||||
133 | * struct pipe_ctx - A member of struct resource_context. Represents the | ||||
134 | * internal hardware pipeline components. Each dc_plane_state has either | ||||
135 | * one or two (in the pipe-split case). | ||||
136 | */ | ||||
137 | |||||
138 | /* Private functions */ | ||||
139 | |||||
140 | static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new) | ||||
141 | { | ||||
142 | if (new > *original) | ||||
143 | *original = new; | ||||
144 | } | ||||
145 | |||||
146 | static void destroy_links(struct dc *dc) | ||||
147 | { | ||||
148 | uint32_t i; | ||||
149 | |||||
150 | for (i = 0; i < dc->link_count; i++) { | ||||
151 | if (NULL((void *)0) != dc->links[i]) | ||||
152 | link_destroy(&dc->links[i]); | ||||
153 | } | ||||
154 | } | ||||
155 | |||||
156 | static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links) | ||||
157 | { | ||||
158 | int i; | ||||
159 | uint32_t count = 0; | ||||
160 | |||||
161 | for (i = 0; i < num_links; i++) { | ||||
162 | if (links[i]->connector_signal == SIGNAL_TYPE_EDP || | ||||
163 | links[i]->is_internal_display) | ||||
164 | count++; | ||||
165 | } | ||||
166 | |||||
167 | return count; | ||||
168 | } | ||||
169 | |||||
170 | static int get_seamless_boot_stream_count(struct dc_state *ctx) | ||||
171 | { | ||||
172 | uint8_t i; | ||||
173 | uint8_t seamless_boot_stream_count = 0; | ||||
174 | |||||
175 | for (i = 0; i < ctx->stream_count; i++) | ||||
176 | if (ctx->streams[i]->apply_seamless_boot_optimization) | ||||
177 | seamless_boot_stream_count++; | ||||
178 | |||||
179 | return seamless_boot_stream_count; | ||||
180 | } | ||||
181 | |||||
182 | static bool_Bool create_links( | ||||
183 | struct dc *dc, | ||||
184 | uint32_t num_virtual_links) | ||||
185 | { | ||||
186 | int i; | ||||
187 | int connectors_num; | ||||
188 | struct dc_bios *bios = dc->ctx->dc_bios; | ||||
189 | |||||
190 | dc->link_count = 0; | ||||
191 | |||||
192 | connectors_num = bios->funcs->get_connectors_number(bios); | ||||
193 | |||||
194 | DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - number of connectors: %d" , connectors_num); | ||||
195 | |||||
196 | if (connectors_num > ENUM_ID_COUNT) { | ||||
197 | dm_error(__drm_err("DC: Number of connectors %d exceeds maximum of %d!\n" , connectors_num, ENUM_ID_COUNT) | ||||
198 | "DC: Number of connectors %d exceeds maximum of %d!\n",__drm_err("DC: Number of connectors %d exceeds maximum of %d!\n" , connectors_num, ENUM_ID_COUNT) | ||||
199 | connectors_num,__drm_err("DC: Number of connectors %d exceeds maximum of %d!\n" , connectors_num, ENUM_ID_COUNT) | ||||
200 | ENUM_ID_COUNT)__drm_err("DC: Number of connectors %d exceeds maximum of %d!\n" , connectors_num, ENUM_ID_COUNT); | ||||
201 | return false0; | ||||
202 | } | ||||
203 | |||||
204 | dm_output_to_console(___drm_dbg(((void *)0), DRM_UT_KMS, "DC: %s: connectors_num: physical:%d, virtual:%d\n" , __func__, connectors_num, num_virtual_links) | ||||
205 | "DC: %s: connectors_num: physical:%d, virtual:%d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "DC: %s: connectors_num: physical:%d, virtual:%d\n" , __func__, connectors_num, num_virtual_links) | ||||
206 | __func__,___drm_dbg(((void *)0), DRM_UT_KMS, "DC: %s: connectors_num: physical:%d, virtual:%d\n" , __func__, connectors_num, num_virtual_links) | ||||
207 | connectors_num,___drm_dbg(((void *)0), DRM_UT_KMS, "DC: %s: connectors_num: physical:%d, virtual:%d\n" , __func__, connectors_num, num_virtual_links) | ||||
208 | num_virtual_links)___drm_dbg(((void *)0), DRM_UT_KMS, "DC: %s: connectors_num: physical:%d, virtual:%d\n" , __func__, connectors_num, num_virtual_links); | ||||
209 | |||||
210 | for (i = 0; i < connectors_num; i++) { | ||||
211 | struct link_init_data link_init_params = {0}; | ||||
212 | struct dc_link *link; | ||||
213 | |||||
214 | DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count)___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - printing link object info for connector number: %d, link_index: %d" , i, dc->link_count); | ||||
215 | |||||
216 | link_init_params.ctx = dc->ctx; | ||||
217 | /* next BIOS object table connector */ | ||||
218 | link_init_params.connector_index = i; | ||||
219 | link_init_params.link_index = dc->link_count; | ||||
220 | link_init_params.dc = dc; | ||||
221 | link = link_create(&link_init_params); | ||||
222 | |||||
223 | if (link) { | ||||
224 | dc->links[dc->link_count] = link; | ||||
225 | link->dc = dc; | ||||
226 | ++dc->link_count; | ||||
227 | } | ||||
228 | } | ||||
229 | |||||
230 | DC_LOG_DC("BIOS object table - end")___drm_dbg(((void *)0), DRM_UT_KMS, "BIOS object table - end" ); | ||||
231 | |||||
232 | /* Create a link for each usb4 dpia port */ | ||||
233 | for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { | ||||
234 | struct link_init_data link_init_params = {0}; | ||||
235 | struct dc_link *link; | ||||
236 | |||||
237 | link_init_params.ctx = dc->ctx; | ||||
238 | link_init_params.connector_index = i; | ||||
239 | link_init_params.link_index = dc->link_count; | ||||
240 | link_init_params.dc = dc; | ||||
241 | link_init_params.is_dpia_link = true1; | ||||
242 | |||||
243 | link = link_create(&link_init_params); | ||||
244 | if (link) { | ||||
245 | dc->links[dc->link_count] = link; | ||||
246 | link->dc = dc; | ||||
247 | ++dc->link_count; | ||||
248 | } | ||||
249 | } | ||||
250 | |||||
251 | for (i = 0; i < num_virtual_links; i++) { | ||||
252 | struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL(0x0001 | 0x0004)); | ||||
253 | struct encoder_init_data enc_init = {0}; | ||||
254 | |||||
255 | if (link == NULL((void *)0)) { | ||||
256 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 256); do {} while (0); } while (0); | ||||
257 | goto failed_alloc; | ||||
258 | } | ||||
259 | |||||
260 | link->link_index = dc->link_count; | ||||
261 | dc->links[dc->link_count] = link; | ||||
262 | dc->link_count++; | ||||
263 | |||||
264 | link->ctx = dc->ctx; | ||||
265 | link->dc = dc; | ||||
266 | link->connector_signal = SIGNAL_TYPE_VIRTUAL; | ||||
267 | link->link_id.type = OBJECT_TYPE_CONNECTOR; | ||||
268 | link->link_id.id = CONNECTOR_ID_VIRTUAL; | ||||
269 | link->link_id.enum_id = ENUM_ID_1; | ||||
270 | link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL(0x0001 | 0x0004)); | ||||
271 | |||||
272 | if (!link->link_enc) { | ||||
273 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 273); do {} while (0); } while (0); | ||||
274 | goto failed_alloc; | ||||
275 | } | ||||
276 | |||||
277 | link->link_status.dpcd_caps = &link->dpcd_caps; | ||||
278 | |||||
279 | enc_init.ctx = dc->ctx; | ||||
280 | enc_init.channel = CHANNEL_ID_UNKNOWN; | ||||
281 | enc_init.hpd_source = HPD_SOURCEID_UNKNOWN; | ||||
282 | enc_init.transmitter = TRANSMITTER_UNKNOWN; | ||||
283 | enc_init.connector = link->link_id; | ||||
284 | enc_init.encoder.type = OBJECT_TYPE_ENCODER; | ||||
285 | enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL; | ||||
286 | enc_init.encoder.enum_id = ENUM_ID_1; | ||||
287 | virtual_link_encoder_construct(link->link_enc, &enc_init); | ||||
288 | } | ||||
289 | |||||
290 | dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count); | ||||
291 | |||||
292 | return true1; | ||||
293 | |||||
294 | failed_alloc: | ||||
295 | return false0; | ||||
296 | } | ||||
297 | |||||
298 | /* Create additional DIG link encoder objects if fewer than the platform | ||||
299 | * supports were created during link construction. This can happen if the | ||||
300 | * number of physical connectors is less than the number of DIGs. | ||||
301 | */ | ||||
302 | static bool_Bool create_link_encoders(struct dc *dc) | ||||
303 | { | ||||
304 | bool_Bool res = true1; | ||||
305 | unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; | ||||
306 | unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; | ||||
307 | int i; | ||||
308 | |||||
309 | /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG | ||||
310 | * link encoders and physical display endpoints and does not require | ||||
311 | * additional link encoder objects. | ||||
312 | */ | ||||
313 | if (num_usb4_dpia == 0) | ||||
314 | return res; | ||||
315 | |||||
316 | /* Create as many link encoder objects as the platform supports. DPIA | ||||
317 | * endpoints can be programmably mapped to any DIG. | ||||
318 | */ | ||||
319 | if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { | ||||
320 | for (i = 0; i < num_dig_link_enc; i++) { | ||||
321 | struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; | ||||
322 | |||||
323 | if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { | ||||
324 | link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, | ||||
325 | (enum engine_id)(ENGINE_ID_DIGA + i)); | ||||
326 | if (link_enc) { | ||||
327 | dc->res_pool->link_encoders[i] = link_enc; | ||||
328 | dc->res_pool->dig_link_enc_count++; | ||||
329 | } else { | ||||
330 | res = false0; | ||||
331 | } | ||||
332 | } | ||||
333 | } | ||||
334 | } | ||||
335 | |||||
336 | return res; | ||||
337 | } | ||||
338 | |||||
339 | /* Destroy any additional DIG link encoder objects created by | ||||
340 | * create_link_encoders(). | ||||
341 | * NB: Must only be called after destroy_links(). | ||||
342 | */ | ||||
343 | static void destroy_link_encoders(struct dc *dc) | ||||
344 | { | ||||
345 | unsigned int num_usb4_dpia; | ||||
346 | unsigned int num_dig_link_enc; | ||||
347 | int i; | ||||
348 | |||||
349 | if (!dc->res_pool) | ||||
350 | return; | ||||
351 | |||||
352 | num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; | ||||
353 | num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; | ||||
354 | |||||
355 | /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG | ||||
356 | * link encoders and physical display endpoints and does not require | ||||
357 | * additional link encoder objects. | ||||
358 | */ | ||||
359 | if (num_usb4_dpia == 0) | ||||
360 | return; | ||||
361 | |||||
362 | for (i = 0; i < num_dig_link_enc; i++) { | ||||
363 | struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; | ||||
364 | |||||
365 | if (link_enc) { | ||||
366 | link_enc->funcs->destroy(&link_enc); | ||||
367 | dc->res_pool->link_encoders[i] = NULL((void *)0); | ||||
368 | dc->res_pool->dig_link_enc_count--; | ||||
369 | } | ||||
370 | } | ||||
371 | } | ||||
372 | |||||
373 | static struct dc_perf_trace *dc_perf_trace_create(void) | ||||
374 | { | ||||
375 | return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL(0x0001 | 0x0004)); | ||||
376 | } | ||||
377 | |||||
378 | static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace) | ||||
379 | { | ||||
380 | kfree(*perf_trace); | ||||
381 | *perf_trace = NULL((void *)0); | ||||
382 | } | ||||
383 | |||||
384 | /** | ||||
385 | * dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR | ||||
386 | * @dc: dc reference | ||||
387 | * @stream: Initial dc stream state | ||||
388 | * @adjust: Updated parameters for vertical_total_min and vertical_total_max | ||||
389 | * | ||||
390 | * Looks up the pipe context of dc_stream_state and updates the | ||||
391 | * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh | ||||
392 | * Rate, which is a power-saving feature that targets reducing panel | ||||
393 | * refresh rate while the screen is static | ||||
394 | * | ||||
395 | * Return: %true if the pipe context is found and adjusted; | ||||
396 | * %false if the pipe context is not found. | ||||
397 | */ | ||||
398 | bool_Bool dc_stream_adjust_vmin_vmax(struct dc *dc, | ||||
399 | struct dc_stream_state *stream, | ||||
400 | struct dc_crtc_timing_adjust *adjust) | ||||
401 | { | ||||
402 | int i; | ||||
403 | |||||
404 | /* | ||||
405 | * Don't adjust DRR while there's bandwidth optimizations pending to | ||||
406 | * avoid conflicting with firmware updates. | ||||
407 | */ | ||||
408 | if (dc->ctx->dce_version > DCE_VERSION_MAX) | ||||
409 | if (dc->optimized_required || dc->wm_optimized_required) | ||||
410 | return false0; | ||||
411 | |||||
412 | stream->adjust.v_total_max = adjust->v_total_max; | ||||
413 | stream->adjust.v_total_mid = adjust->v_total_mid; | ||||
414 | stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num; | ||||
415 | stream->adjust.v_total_min = adjust->v_total_min; | ||||
416 | |||||
417 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
418 | struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
419 | |||||
420 | if (pipe->stream == stream && pipe->stream_res.tg) { | ||||
421 | dc->hwss.set_drr(&pipe, | ||||
422 | 1, | ||||
423 | *adjust); | ||||
424 | |||||
425 | return true1; | ||||
426 | } | ||||
427 | } | ||||
428 | return false0; | ||||
429 | } | ||||
430 | |||||
431 | /** | ||||
432 | * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of | ||||
433 | * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate) | ||||
434 | * | ||||
435 | * @dc: [in] dc reference | ||||
436 | * @stream: [in] Initial dc stream state | ||||
437 | * @refresh_rate: [in] new refresh_rate | ||||
438 | * | ||||
439 | * Return: %true if the pipe context is found and there is an associated | ||||
440 | * timing_generator for the DC; | ||||
441 | * %false if the pipe context is not found or there is no | ||||
442 | * timing_generator for the DC. | ||||
443 | */ | ||||
444 | bool_Bool dc_stream_get_last_used_drr_vtotal(struct dc *dc, | ||||
445 | struct dc_stream_state *stream, | ||||
446 | uint32_t *refresh_rate) | ||||
447 | { | ||||
448 | bool_Bool status = false0; | ||||
449 | |||||
450 | int i = 0; | ||||
451 | |||||
452 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
453 | struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
454 | |||||
455 | if (pipe->stream == stream && pipe->stream_res.tg) { | ||||
456 | /* Only execute if a function pointer has been defined for | ||||
457 | * the DC version in question | ||||
458 | */ | ||||
459 | if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) { | ||||
460 | pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate); | ||||
461 | |||||
462 | status = true1; | ||||
463 | |||||
464 | break; | ||||
465 | } | ||||
466 | } | ||||
467 | } | ||||
468 | |||||
469 | return status; | ||||
470 | } | ||||
471 | |||||
472 | bool_Bool dc_stream_get_crtc_position(struct dc *dc, | ||||
473 | struct dc_stream_state **streams, int num_streams, | ||||
474 | unsigned int *v_pos, unsigned int *nom_v_pos) | ||||
475 | { | ||||
476 | /* TODO: Support multiple streams */ | ||||
477 | const struct dc_stream_state *stream = streams[0]; | ||||
478 | int i; | ||||
479 | bool_Bool ret = false0; | ||||
480 | struct crtc_position position; | ||||
481 | |||||
482 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
483 | struct pipe_ctx *pipe = | ||||
484 | &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
485 | |||||
486 | if (pipe->stream == stream && pipe->stream_res.stream_enc) { | ||||
487 | dc->hwss.get_position(&pipe, 1, &position); | ||||
488 | |||||
489 | *v_pos = position.vertical_count; | ||||
490 | *nom_v_pos = position.nominal_vcount; | ||||
491 | ret = true1; | ||||
492 | } | ||||
493 | } | ||||
494 | return ret; | ||||
495 | } | ||||
496 | |||||
497 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) | ||||
498 | bool_Bool dc_stream_forward_dmcu_crc_window(struct dc *dc, struct dc_stream_state *stream, | ||||
499 | struct crc_params *crc_window) | ||||
500 | { | ||||
501 | int i; | ||||
502 | struct dmcu *dmcu = dc->res_pool->dmcu; | ||||
503 | struct pipe_ctx *pipe; | ||||
504 | struct crc_region tmp_win, *crc_win; | ||||
505 | struct otg_phy_mux mapping_tmp, *mux_mapping; | ||||
506 | |||||
507 | /*crc window can't be null*/ | ||||
508 | if (!crc_window) | ||||
509 | return false0; | ||||
510 | |||||
511 | if ((dmcu != NULL((void *)0) && dmcu->funcs->is_dmcu_initialized(dmcu))) { | ||||
512 | crc_win = &tmp_win; | ||||
513 | mux_mapping = &mapping_tmp; | ||||
514 | /*set crc window*/ | ||||
515 | tmp_win.x_start = crc_window->windowa_x_start; | ||||
516 | tmp_win.y_start = crc_window->windowa_y_start; | ||||
517 | tmp_win.x_end = crc_window->windowa_x_end; | ||||
518 | tmp_win.y_end = crc_window->windowa_y_end; | ||||
519 | |||||
520 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
521 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
522 | if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) | ||||
523 | break; | ||||
524 | } | ||||
525 | |||||
526 | /* Stream not found */ | ||||
527 | if (i == MAX_PIPES6) | ||||
528 | return false0; | ||||
529 | |||||
530 | |||||
531 | /*set mux routing info*/ | ||||
532 | mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst; | ||||
533 | mapping_tmp.otg_output_num = pipe->stream_res.tg->inst; | ||||
534 | |||||
535 | dmcu->funcs->forward_crc_window(dmcu, crc_win, mux_mapping); | ||||
536 | } else { | ||||
537 | DC_LOG_DC("dmcu is not initialized")___drm_dbg(((void *)0), DRM_UT_KMS, "dmcu is not initialized" ); | ||||
538 | return false0; | ||||
539 | } | ||||
540 | |||||
541 | return true1; | ||||
542 | } | ||||
543 | |||||
544 | bool_Bool dc_stream_stop_dmcu_crc_win_update(struct dc *dc, struct dc_stream_state *stream) | ||||
545 | { | ||||
546 | int i; | ||||
547 | struct dmcu *dmcu = dc->res_pool->dmcu; | ||||
548 | struct pipe_ctx *pipe; | ||||
549 | struct otg_phy_mux mapping_tmp, *mux_mapping; | ||||
550 | |||||
551 | if ((dmcu != NULL((void *)0) && dmcu->funcs->is_dmcu_initialized(dmcu))) { | ||||
552 | mux_mapping = &mapping_tmp; | ||||
553 | |||||
554 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
555 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
556 | if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) | ||||
557 | break; | ||||
558 | } | ||||
559 | |||||
560 | /* Stream not found */ | ||||
561 | if (i == MAX_PIPES6) | ||||
562 | return false0; | ||||
563 | |||||
564 | |||||
565 | /*set mux routing info*/ | ||||
566 | mapping_tmp.phy_output_num = stream->link->link_enc_hw_inst; | ||||
567 | mapping_tmp.otg_output_num = pipe->stream_res.tg->inst; | ||||
568 | |||||
569 | dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping); | ||||
570 | } else { | ||||
571 | DC_LOG_DC("dmcu is not initialized")___drm_dbg(((void *)0), DRM_UT_KMS, "dmcu is not initialized" ); | ||||
572 | return false0; | ||||
573 | } | ||||
574 | |||||
575 | return true1; | ||||
576 | } | ||||
577 | #endif | ||||
578 | |||||
579 | /** | ||||
580 | * dc_stream_configure_crc() - Configure CRC capture for the given stream. | ||||
581 | * @dc: DC Object | ||||
582 | * @stream: The stream to configure CRC on. | ||||
583 | * @enable: Enable CRC if true, disable otherwise. | ||||
584 | * @crc_window: CRC window (x/y start/end) information | ||||
585 | * @continuous: Capture CRC on every frame if true. Otherwise, only capture | ||||
586 | * once. | ||||
587 | * | ||||
588 | * By default, only CRC0 is configured, and the entire frame is used to | ||||
589 | * calculate the CRC. | ||||
590 | * | ||||
591 | * Return: %false if the stream is not found or CRC capture is not supported; | ||||
592 | * %true if the stream has been configured. | ||||
593 | */ | ||||
594 | bool_Bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, | ||||
595 | struct crc_params *crc_window, bool_Bool enable, bool_Bool continuous) | ||||
596 | { | ||||
597 | int i; | ||||
598 | struct pipe_ctx *pipe; | ||||
599 | struct crc_params param; | ||||
600 | struct timing_generator *tg; | ||||
601 | |||||
602 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
603 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
604 | if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) | ||||
605 | break; | ||||
606 | } | ||||
607 | /* Stream not found */ | ||||
608 | if (i == MAX_PIPES6) | ||||
609 | return false0; | ||||
610 | |||||
611 | /* By default, capture the full frame */ | ||||
612 | param.windowa_x_start = 0; | ||||
613 | param.windowa_y_start = 0; | ||||
614 | param.windowa_x_end = pipe->stream->timing.h_addressable; | ||||
615 | param.windowa_y_end = pipe->stream->timing.v_addressable; | ||||
616 | param.windowb_x_start = 0; | ||||
617 | param.windowb_y_start = 0; | ||||
618 | param.windowb_x_end = pipe->stream->timing.h_addressable; | ||||
619 | param.windowb_y_end = pipe->stream->timing.v_addressable; | ||||
620 | |||||
621 | if (crc_window) { | ||||
622 | param.windowa_x_start = crc_window->windowa_x_start; | ||||
623 | param.windowa_y_start = crc_window->windowa_y_start; | ||||
624 | param.windowa_x_end = crc_window->windowa_x_end; | ||||
625 | param.windowa_y_end = crc_window->windowa_y_end; | ||||
626 | param.windowb_x_start = crc_window->windowb_x_start; | ||||
627 | param.windowb_y_start = crc_window->windowb_y_start; | ||||
628 | param.windowb_x_end = crc_window->windowb_x_end; | ||||
629 | param.windowb_y_end = crc_window->windowb_y_end; | ||||
630 | } | ||||
631 | |||||
632 | param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; | ||||
633 | param.odm_mode = pipe->next_odm_pipe ? 1:0; | ||||
634 | |||||
635 | /* Default to the union of both windows */ | ||||
636 | param.selection = UNION_WINDOW_A_B; | ||||
637 | param.continuous_mode = continuous; | ||||
638 | param.enable = enable; | ||||
639 | |||||
640 | tg = pipe->stream_res.tg; | ||||
641 | |||||
642 | /* Only call if supported */ | ||||
643 | if (tg->funcs->configure_crc) | ||||
644 | return tg->funcs->configure_crc(tg, ¶m); | ||||
645 | DC_LOG_WARNING("CRC capture not supported.")printk("\0014" "[" "drm" "] " "CRC capture not supported."); | ||||
646 | return false0; | ||||
647 | } | ||||
648 | |||||
649 | /** | ||||
650 | * dc_stream_get_crc() - Get CRC values for the given stream. | ||||
651 | * | ||||
652 | * @dc: DC object. | ||||
653 | * @stream: The DC stream state of the stream to get CRCs from. | ||||
654 | * @r_cr: CRC value for the red component. | ||||
655 | * @g_y: CRC value for the green component. | ||||
656 | * @b_cb: CRC value for the blue component. | ||||
657 | * | ||||
658 | * dc_stream_configure_crc needs to be called beforehand to enable CRCs. | ||||
659 | * | ||||
660 | * Return: | ||||
661 | * %false if stream is not found, or if CRCs are not enabled. | ||||
662 | */ | ||||
663 | bool_Bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, | ||||
664 | uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) | ||||
665 | { | ||||
666 | int i; | ||||
667 | struct pipe_ctx *pipe; | ||||
668 | struct timing_generator *tg; | ||||
669 | |||||
670 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
671 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
672 | if (pipe->stream == stream) | ||||
673 | break; | ||||
674 | } | ||||
675 | /* Stream not found */ | ||||
676 | if (i == MAX_PIPES6) | ||||
677 | return false0; | ||||
678 | |||||
679 | tg = pipe->stream_res.tg; | ||||
680 | |||||
681 | if (tg->funcs->get_crc) | ||||
682 | return tg->funcs->get_crc(tg, r_cr, g_y, b_cb); | ||||
683 | DC_LOG_WARNING("CRC capture not supported.")printk("\0014" "[" "drm" "] " "CRC capture not supported."); | ||||
684 | return false0; | ||||
685 | } | ||||
686 | |||||
687 | void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream, | ||||
688 | enum dc_dynamic_expansion option) | ||||
689 | { | ||||
690 | /* OPP FMT dyn expansion updates*/ | ||||
691 | int i; | ||||
692 | struct pipe_ctx *pipe_ctx; | ||||
693 | |||||
694 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
695 | if (dc->current_state->res_ctx.pipe_ctx[i].stream | ||||
696 | == stream) { | ||||
697 | pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
698 | pipe_ctx->stream_res.opp->dyn_expansion = option; | ||||
699 | pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( | ||||
700 | pipe_ctx->stream_res.opp, | ||||
701 | COLOR_SPACE_YCBCR601, | ||||
702 | stream->timing.display_color_depth, | ||||
703 | stream->signal); | ||||
704 | } | ||||
705 | } | ||||
706 | } | ||||
707 | |||||
708 | void dc_stream_set_dither_option(struct dc_stream_state *stream, | ||||
709 | enum dc_dither_option option) | ||||
710 | { | ||||
711 | struct bit_depth_reduction_params params; | ||||
712 | struct dc_link *link = stream->link; | ||||
713 | struct pipe_ctx *pipes = NULL((void *)0); | ||||
714 | int i; | ||||
715 | |||||
716 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
717 | if (link->dc->current_state->res_ctx.pipe_ctx[i].stream == | ||||
718 | stream) { | ||||
719 | pipes = &link->dc->current_state->res_ctx.pipe_ctx[i]; | ||||
720 | break; | ||||
721 | } | ||||
722 | } | ||||
723 | |||||
724 | if (!pipes) | ||||
725 | return; | ||||
726 | if (option > DITHER_OPTION_MAX) | ||||
727 | return; | ||||
728 | |||||
729 | stream->dither_option = option; | ||||
730 | |||||
731 | memset(¶ms, 0, sizeof(params))__builtin_memset((¶ms), (0), (sizeof(params))); | ||||
732 | resource_build_bit_depth_reduction_params(stream, ¶ms); | ||||
733 | stream->bit_depth_params = params; | ||||
734 | |||||
735 | if (pipes->plane_res.xfm && | ||||
736 | pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) { | ||||
737 | pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth( | ||||
738 | pipes->plane_res.xfm, | ||||
739 | pipes->plane_res.scl_data.lb_params.depth, | ||||
740 | &stream->bit_depth_params); | ||||
741 | } | ||||
742 | |||||
743 | pipes->stream_res.opp->funcs-> | ||||
744 | opp_program_bit_depth_reduction(pipes->stream_res.opp, ¶ms); | ||||
745 | } | ||||
746 | |||||
747 | bool_Bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) | ||||
748 | { | ||||
749 | int i; | ||||
750 | bool_Bool ret = false0; | ||||
751 | struct pipe_ctx *pipes; | ||||
752 | |||||
753 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
754 | if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { | ||||
755 | pipes = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
756 | dc->hwss.program_gamut_remap(pipes); | ||||
757 | ret = true1; | ||||
758 | } | ||||
759 | } | ||||
760 | |||||
761 | return ret; | ||||
762 | } | ||||
763 | |||||
764 | bool_Bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) | ||||
765 | { | ||||
766 | int i; | ||||
767 | bool_Bool ret = false0; | ||||
768 | struct pipe_ctx *pipes; | ||||
769 | |||||
770 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
771 | if (dc->current_state->res_ctx.pipe_ctx[i].stream | ||||
772 | == stream) { | ||||
773 | |||||
774 | pipes = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
775 | dc->hwss.program_output_csc(dc, | ||||
776 | pipes, | ||||
777 | stream->output_color_space, | ||||
778 | stream->csc_color_matrix.matrix, | ||||
779 | pipes->stream_res.opp->inst); | ||||
780 | ret = true1; | ||||
781 | } | ||||
782 | } | ||||
783 | |||||
784 | return ret; | ||||
785 | } | ||||
786 | |||||
787 | void dc_stream_set_static_screen_params(struct dc *dc, | ||||
788 | struct dc_stream_state **streams, | ||||
789 | int num_streams, | ||||
790 | const struct dc_static_screen_params *params) | ||||
791 | { | ||||
792 | int i, j; | ||||
793 | struct pipe_ctx *pipes_affected[MAX_PIPES6]; | ||||
794 | int num_pipes_affected = 0; | ||||
795 | |||||
796 | for (i = 0; i < num_streams; i++) { | ||||
797 | struct dc_stream_state *stream = streams[i]; | ||||
798 | |||||
799 | for (j = 0; j < MAX_PIPES6; j++) { | ||||
800 | if (dc->current_state->res_ctx.pipe_ctx[j].stream | ||||
801 | == stream) { | ||||
802 | pipes_affected[num_pipes_affected++] = | ||||
803 | &dc->current_state->res_ctx.pipe_ctx[j]; | ||||
804 | } | ||||
805 | } | ||||
806 | } | ||||
807 | |||||
808 | dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params); | ||||
809 | } | ||||
810 | |||||
811 | static void dc_destruct(struct dc *dc) | ||||
812 | { | ||||
813 | // reset link encoder assignment table on destruct | ||||
814 | if (dc->res_pool && dc->res_pool->funcs->link_encs_assign) | ||||
815 | link_enc_cfg_init(dc, dc->current_state); | ||||
816 | |||||
817 | if (dc->current_state) { | ||||
818 | dc_release_state(dc->current_state); | ||||
819 | dc->current_state = NULL((void *)0); | ||||
820 | } | ||||
821 | |||||
822 | destroy_links(dc); | ||||
823 | |||||
824 | destroy_link_encoders(dc); | ||||
825 | |||||
826 | if (dc->clk_mgr) { | ||||
827 | dc_destroy_clk_mgr(dc->clk_mgr); | ||||
828 | dc->clk_mgr = NULL((void *)0); | ||||
829 | } | ||||
830 | |||||
831 | dc_destroy_resource_pool(dc); | ||||
832 | |||||
833 | if (dc->ctx->gpio_service) | ||||
834 | dal_gpio_service_destroy(&dc->ctx->gpio_service); | ||||
835 | |||||
836 | if (dc->ctx->created_bios) | ||||
837 | dal_bios_parser_destroy(&dc->ctx->dc_bios); | ||||
838 | |||||
839 | dc_perf_trace_destroy(&dc->ctx->perf_trace); | ||||
840 | |||||
841 | kfree(dc->ctx); | ||||
842 | dc->ctx = NULL((void *)0); | ||||
843 | |||||
844 | kfree(dc->bw_vbios); | ||||
845 | dc->bw_vbios = NULL((void *)0); | ||||
846 | |||||
847 | kfree(dc->bw_dceip); | ||||
848 | dc->bw_dceip = NULL((void *)0); | ||||
849 | |||||
850 | kfree(dc->dcn_soc); | ||||
851 | dc->dcn_soc = NULL((void *)0); | ||||
852 | |||||
853 | kfree(dc->dcn_ip); | ||||
854 | dc->dcn_ip = NULL((void *)0); | ||||
855 | |||||
856 | kfree(dc->vm_helper); | ||||
857 | dc->vm_helper = NULL((void *)0); | ||||
858 | |||||
859 | } | ||||
860 | |||||
861 | static bool_Bool dc_construct_ctx(struct dc *dc, | ||||
862 | const struct dc_init_data *init_params) | ||||
863 | { | ||||
864 | struct dc_context *dc_ctx; | ||||
865 | enum dce_version dc_version = DCE_VERSION_UNKNOWN; | ||||
866 | |||||
867 | dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL(0x0001 | 0x0004)); | ||||
868 | if (!dc_ctx) | ||||
869 | return false0; | ||||
870 | |||||
871 | dc_ctx->cgs_device = init_params->cgs_device; | ||||
872 | dc_ctx->driver_context = init_params->driver; | ||||
873 | dc_ctx->dc = dc; | ||||
874 | dc_ctx->asic_id = init_params->asic_id; | ||||
875 | dc_ctx->dc_sink_id_count = 0; | ||||
876 | dc_ctx->dc_stream_id_count = 0; | ||||
877 | dc_ctx->dce_environment = init_params->dce_environment; | ||||
878 | dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets; | ||||
879 | dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets; | ||||
880 | |||||
881 | /* Create logger */ | ||||
882 | |||||
883 | dc_version = resource_parse_asic_id(init_params->asic_id); | ||||
884 | dc_ctx->dce_version = dc_version; | ||||
885 | |||||
886 | dc_ctx->perf_trace = dc_perf_trace_create(); | ||||
887 | if (!dc_ctx->perf_trace) { | ||||
888 | kfree(dc_ctx); | ||||
889 | ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c" , 889); __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
890 | return false0; | ||||
891 | } | ||||
892 | |||||
893 | dc->ctx = dc_ctx; | ||||
894 | |||||
895 | return true1; | ||||
896 | } | ||||
897 | |||||
898 | static bool_Bool dc_construct(struct dc *dc, | ||||
899 | const struct dc_init_data *init_params) | ||||
900 | { | ||||
901 | struct dc_context *dc_ctx; | ||||
902 | struct bw_calcs_dceip *dc_dceip; | ||||
903 | struct bw_calcs_vbios *dc_vbios; | ||||
904 | struct dcn_soc_bounding_box *dcn_soc; | ||||
905 | struct dcn_ip_params *dcn_ip; | ||||
906 | |||||
907 | dc->config = init_params->flags; | ||||
908 | |||||
909 | // Allocate memory for the vm_helper | ||||
910 | dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL(0x0001 | 0x0004)); | ||||
911 | if (!dc->vm_helper) { | ||||
912 | dm_error("%s: failed to create dc->vm_helper\n", __func__)__drm_err("%s: failed to create dc->vm_helper\n", __func__ ); | ||||
913 | goto fail; | ||||
914 | } | ||||
915 | |||||
916 | memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides))__builtin_memcpy((&dc->bb_overrides), (&init_params ->bb_overrides), (sizeof(dc->bb_overrides))); | ||||
917 | |||||
918 | dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL(0x0001 | 0x0004)); | ||||
919 | if (!dc_dceip) { | ||||
920 | dm_error("%s: failed to create dceip\n", __func__)__drm_err("%s: failed to create dceip\n", __func__); | ||||
921 | goto fail; | ||||
922 | } | ||||
923 | |||||
924 | dc->bw_dceip = dc_dceip; | ||||
925 | |||||
926 | dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL(0x0001 | 0x0004)); | ||||
927 | if (!dc_vbios) { | ||||
928 | dm_error("%s: failed to create vbios\n", __func__)__drm_err("%s: failed to create vbios\n", __func__); | ||||
929 | goto fail; | ||||
930 | } | ||||
931 | |||||
932 | dc->bw_vbios = dc_vbios; | ||||
933 | dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL(0x0001 | 0x0004)); | ||||
934 | if (!dcn_soc) { | ||||
935 | dm_error("%s: failed to create dcn_soc\n", __func__)__drm_err("%s: failed to create dcn_soc\n", __func__); | ||||
936 | goto fail; | ||||
937 | } | ||||
938 | |||||
939 | dc->dcn_soc = dcn_soc; | ||||
940 | |||||
941 | dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL(0x0001 | 0x0004)); | ||||
942 | if (!dcn_ip) { | ||||
943 | dm_error("%s: failed to create dcn_ip\n", __func__)__drm_err("%s: failed to create dcn_ip\n", __func__); | ||||
944 | goto fail; | ||||
945 | } | ||||
946 | |||||
947 | dc->dcn_ip = dcn_ip; | ||||
948 | |||||
949 | if (!dc_construct_ctx(dc, init_params)) { | ||||
950 | dm_error("%s: failed to create ctx\n", __func__)__drm_err("%s: failed to create ctx\n", __func__); | ||||
951 | goto fail; | ||||
952 | } | ||||
953 | |||||
954 | dc_ctx = dc->ctx; | ||||
955 | |||||
956 | /* Resource should construct all asic specific resources. | ||||
957 | * This should be the only place where we need to parse the asic id | ||||
958 | */ | ||||
959 | if (init_params->vbios_override) | ||||
960 | dc_ctx->dc_bios = init_params->vbios_override; | ||||
961 | else { | ||||
962 | /* Create BIOS parser */ | ||||
963 | struct bp_init_data bp_init_data; | ||||
964 | |||||
965 | bp_init_data.ctx = dc_ctx; | ||||
966 | bp_init_data.bios = init_params->asic_id.atombios_base_address; | ||||
967 | |||||
968 | dc_ctx->dc_bios = dal_bios_parser_create( | ||||
969 | &bp_init_data, dc_ctx->dce_version); | ||||
970 | |||||
971 | if (!dc_ctx->dc_bios) { | ||||
972 | ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c" , 972); __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
973 | goto fail; | ||||
974 | } | ||||
975 | |||||
976 | dc_ctx->created_bios = true1; | ||||
977 | } | ||||
978 | |||||
979 | dc->vendor_signature = init_params->vendor_signature; | ||||
980 | |||||
981 | /* Create GPIO service */ | ||||
982 | dc_ctx->gpio_service = dal_gpio_service_create( | ||||
983 | dc_ctx->dce_version, | ||||
984 | dc_ctx->dce_environment, | ||||
985 | dc_ctx); | ||||
986 | |||||
987 | if (!dc_ctx->gpio_service) { | ||||
988 | ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c" , 988); __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
989 | goto fail; | ||||
990 | } | ||||
991 | |||||
992 | dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version); | ||||
993 | if (!dc->res_pool) | ||||
994 | goto fail; | ||||
995 | |||||
996 | /* set i2c speed if not done by the respective dcnxxx__resource.c */ | ||||
997 | if (dc->caps.i2c_speed_in_khz_hdcp == 0) | ||||
998 | dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz; | ||||
999 | if (dc->caps.max_optimizable_video_width == 0) | ||||
1000 | dc->caps.max_optimizable_video_width = 5120; | ||||
1001 | dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); | ||||
1002 | if (!dc->clk_mgr) | ||||
1003 | goto fail; | ||||
1004 | #ifdef CONFIG_DRM_AMD_DC_DCN1 | ||||
1005 | dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present; | ||||
1006 | |||||
1007 | if (dc->res_pool->funcs->update_bw_bounding_box) { | ||||
1008 | DC_FP_START()dc_fpu_begin(__func__, 1008); | ||||
1009 | dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); | ||||
1010 | DC_FP_END()dc_fpu_end(__func__, 1010); | ||||
1011 | } | ||||
1012 | #endif | ||||
1013 | |||||
1014 | /* Creation of current_state must occur after dc->dml | ||||
1015 | * is initialized in dc_create_resource_pool because | ||||
1016 | * on creation it copies the contents of dc->dml | ||||
1017 | */ | ||||
1018 | |||||
1019 | dc->current_state = dc_create_state(dc); | ||||
1020 | |||||
1021 | if (!dc->current_state) { | ||||
1022 | dm_error("%s: failed to create validate ctx\n", __func__)__drm_err("%s: failed to create validate ctx\n", __func__); | ||||
1023 | goto fail; | ||||
1024 | } | ||||
1025 | |||||
1026 | if (!create_links(dc, init_params->num_virtual_links)) | ||||
1027 | goto fail; | ||||
1028 | |||||
1029 | /* Create additional DIG link encoder objects if fewer than the platform | ||||
1030 | * supports were created during link construction. | ||||
1031 | */ | ||||
1032 | if (!create_link_encoders(dc)) | ||||
1033 | goto fail; | ||||
1034 | |||||
1035 | dc_resource_state_construct(dc, dc->current_state); | ||||
1036 | |||||
1037 | return true1; | ||||
1038 | |||||
1039 | fail: | ||||
1040 | return false0; | ||||
1041 | } | ||||
1042 | |||||
1043 | static void disable_all_writeback_pipes_for_stream( | ||||
1044 | const struct dc *dc, | ||||
1045 | struct dc_stream_state *stream, | ||||
1046 | struct dc_state *context) | ||||
1047 | { | ||||
1048 | int i; | ||||
1049 | |||||
1050 | for (i = 0; i < stream->num_wb_info; i++) | ||||
1051 | stream->writeback_info[i].wb_enabled = false0; | ||||
1052 | } | ||||
1053 | |||||
1054 | static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context, | ||||
1055 | struct dc_stream_state *stream, bool_Bool lock) | ||||
1056 | { | ||||
1057 | int i; | ||||
1058 | |||||
1059 | /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */ | ||||
1060 | if (dc->hwss.interdependent_update_lock) | ||||
1061 | dc->hwss.interdependent_update_lock(dc, context, lock); | ||||
1062 | else { | ||||
1063 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
1064 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | ||||
1065 | struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
1066 | |||||
1067 | // Copied conditions that were previously in dce110_apply_ctx_for_surface | ||||
1068 | if (stream == pipe_ctx->stream) { | ||||
1069 | if (!pipe_ctx->top_pipe && | ||||
1070 | (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) | ||||
1071 | dc->hwss.pipe_control_lock(dc, pipe_ctx, lock); | ||||
1072 | } | ||||
1073 | } | ||||
1074 | } | ||||
1075 | } | ||||
1076 | |||||
1077 | static void disable_dangling_plane(struct dc *dc, struct dc_state *context) | ||||
1078 | { | ||||
1079 | int i, j; | ||||
1080 | struct dc_state *dangling_context = dc_create_state(dc); | ||||
1081 | struct dc_state *current_ctx; | ||||
1082 | struct pipe_ctx *pipe; | ||||
1083 | struct timing_generator *tg; | ||||
1084 | |||||
1085 | if (dangling_context == NULL((void *)0)) | ||||
1086 | return; | ||||
1087 | |||||
1088 | dc_resource_state_copy_construct(dc->current_state, dangling_context); | ||||
1089 | |||||
1090 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
1091 | struct dc_stream_state *old_stream = | ||||
1092 | dc->current_state->res_ctx.pipe_ctx[i].stream; | ||||
1093 | bool_Bool should_disable = true1; | ||||
1094 | bool_Bool pipe_split_change = false0; | ||||
1095 | |||||
1096 | if ((context->res_ctx.pipe_ctx[i].top_pipe) && | ||||
1097 | (dc->current_state->res_ctx.pipe_ctx[i].top_pipe)) | ||||
1098 | pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx != | ||||
1099 | dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx; | ||||
1100 | else | ||||
1101 | pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe != | ||||
1102 | dc->current_state->res_ctx.pipe_ctx[i].top_pipe; | ||||
1103 | |||||
1104 | for (j = 0; j < context->stream_count; j++) { | ||||
1105 | if (old_stream == context->streams[j]) { | ||||
1106 | should_disable = false0; | ||||
1107 | break; | ||||
1108 | } | ||||
1109 | } | ||||
1110 | if (!should_disable && pipe_split_change && | ||||
1111 | dc->current_state->stream_count != context->stream_count) | ||||
1112 | should_disable = true1; | ||||
1113 | |||||
1114 | if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe && | ||||
1115 | !dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) { | ||||
1116 | struct pipe_ctx *old_pipe, *new_pipe; | ||||
1117 | |||||
1118 | old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
1119 | new_pipe = &context->res_ctx.pipe_ctx[i]; | ||||
1120 | |||||
1121 | if (old_pipe->plane_state && !new_pipe->plane_state) | ||||
1122 | should_disable = true1; | ||||
1123 | } | ||||
1124 | |||||
1125 | if (should_disable && old_stream) { | ||||
1126 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
1127 | tg = pipe->stream_res.tg; | ||||
1128 | /* When disabling plane for a phantom pipe, we must turn on the | ||||
1129 | * phantom OTG so the disable programming gets the double buffer | ||||
1130 | * update. Otherwise the pipe will be left in a partially disabled | ||||
1131 | * state that can result in underflow or hang when enabling it | ||||
1132 | * again for different use. | ||||
1133 | */ | ||||
1134 | if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) { | ||||
1135 | if (tg->funcs->enable_crtc) | ||||
1136 | tg->funcs->enable_crtc(tg); | ||||
1137 | } | ||||
1138 | dc_rem_all_planes_for_stream(dc, old_stream, dangling_context); | ||||
1139 | disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context); | ||||
1140 | |||||
1141 | if (dc->hwss.apply_ctx_for_surface) { | ||||
1142 | apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true1); | ||||
1143 | dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context); | ||||
1144 | apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false0); | ||||
1145 | dc->hwss.post_unlock_program_front_end(dc, dangling_context); | ||||
1146 | } | ||||
1147 | if (dc->hwss.program_front_end_for_ctx) { | ||||
1148 | dc->hwss.interdependent_update_lock(dc, dc->current_state, true1); | ||||
1149 | dc->hwss.program_front_end_for_ctx(dc, dangling_context); | ||||
1150 | dc->hwss.interdependent_update_lock(dc, dc->current_state, false0); | ||||
1151 | dc->hwss.post_unlock_program_front_end(dc, dangling_context); | ||||
1152 | } | ||||
1153 | /* We need to put the phantom OTG back into it's default (disabled) state or we | ||||
1154 | * can get corruption when transition from one SubVP config to a different one. | ||||
1155 | * The OTG is set to disable on falling edge of VUPDATE so the plane disable | ||||
1156 | * will still get it's double buffer update. | ||||
1157 | */ | ||||
1158 | if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) { | ||||
1159 | if (tg->funcs->disable_phantom_crtc) | ||||
1160 | tg->funcs->disable_phantom_crtc(tg); | ||||
1161 | } | ||||
1162 | } | ||||
1163 | } | ||||
1164 | |||||
1165 | current_ctx = dc->current_state; | ||||
1166 | dc->current_state = dangling_context; | ||||
1167 | dc_release_state(current_ctx); | ||||
1168 | } | ||||
1169 | |||||
1170 | static void disable_vbios_mode_if_required( | ||||
1171 | struct dc *dc, | ||||
1172 | struct dc_state *context) | ||||
1173 | { | ||||
1174 | unsigned int i, j; | ||||
1175 | |||||
1176 | /* check if timing_changed, disable stream*/ | ||||
1177 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
1178 | struct dc_stream_state *stream = NULL((void *)0); | ||||
1179 | struct dc_link *link = NULL((void *)0); | ||||
1180 | struct pipe_ctx *pipe = NULL((void *)0); | ||||
1181 | |||||
1182 | pipe = &context->res_ctx.pipe_ctx[i]; | ||||
1183 | stream = pipe->stream; | ||||
1184 | if (stream == NULL((void *)0)) | ||||
1185 | continue; | ||||
1186 | |||||
1187 | if (stream->apply_seamless_boot_optimization) | ||||
1188 | continue; | ||||
1189 | |||||
1190 | // only looking for first odm pipe | ||||
1191 | if (pipe->prev_odm_pipe) | ||||
1192 | continue; | ||||
1193 | |||||
1194 | if (stream->link->local_sink && | ||||
1195 | stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { | ||||
1196 | link = stream->link; | ||||
1197 | } | ||||
1198 | |||||
1199 | if (link != NULL((void *)0) && link->link_enc->funcs->is_dig_enabled(link->link_enc)) { | ||||
1200 | unsigned int enc_inst, tg_inst = 0; | ||||
1201 | unsigned int pix_clk_100hz; | ||||
1202 | |||||
1203 | enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); | ||||
1204 | if (enc_inst != ENGINE_ID_UNKNOWN) { | ||||
1205 | for (j = 0; j < dc->res_pool->stream_enc_count; j++) { | ||||
1206 | if (dc->res_pool->stream_enc[j]->id == enc_inst) { | ||||
1207 | tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg( | ||||
1208 | dc->res_pool->stream_enc[j]); | ||||
1209 | break; | ||||
1210 | } | ||||
1211 | } | ||||
1212 | |||||
1213 | dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( | ||||
1214 | dc->res_pool->dp_clock_source, | ||||
1215 | tg_inst, &pix_clk_100hz); | ||||
1216 | |||||
1217 | if (link->link_status.link_active) { | ||||
1218 | uint32_t requested_pix_clk_100hz = | ||||
1219 | pipe->stream_res.pix_clk_params.requested_pix_clk_100hz; | ||||
1220 | |||||
1221 | if (pix_clk_100hz != requested_pix_clk_100hz) { | ||||
1222 | core_link_disable_stream(pipe); | ||||
1223 | pipe->stream->dpms_off = false0; | ||||
1224 | } | ||||
1225 | } | ||||
1226 | } | ||||
1227 | } | ||||
1228 | } | ||||
1229 | } | ||||
1230 | |||||
1231 | static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context) | ||||
1232 | { | ||||
1233 | int i; | ||||
1234 | PERF_TRACE()dm_perf_trace_timestamp(__func__, 1234, dc->ctx); | ||||
1235 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
1236 | int count = 0; | ||||
1237 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | ||||
1238 | |||||
1239 | if (!pipe->plane_state || pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) | ||||
1240 | continue; | ||||
1241 | |||||
1242 | /* Timeout 100 ms */ | ||||
1243 | while (count < 100000) { | ||||
1244 | /* Must set to false to start with, due to OR in update function */ | ||||
1245 | pipe->plane_state->status.is_flip_pending = false0; | ||||
1246 | dc->hwss.update_pending_status(pipe); | ||||
1247 | if (!pipe->plane_state->status.is_flip_pending) | ||||
1248 | break; | ||||
1249 | udelay(1); | ||||
1250 | count++; | ||||
1251 | } | ||||
1252 | ASSERT(!pipe->plane_state->status.is_flip_pending)do { if (({ static int __warned; int __ret = !!(!(!pipe->plane_state ->status.is_flip_pending)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(!pipe->plane_state->status.is_flip_pending)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c", 1252); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1253 | } | ||||
1254 | PERF_TRACE()dm_perf_trace_timestamp(__func__, 1254, dc->ctx); | ||||
1255 | } | ||||
1256 | |||||
1257 | /* Public functions */ | ||||
1258 | |||||
1259 | struct dc *dc_create(const struct dc_init_data *init_params) | ||||
1260 | { | ||||
1261 | struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL(0x0001 | 0x0004)); | ||||
1262 | unsigned int full_pipe_count; | ||||
1263 | |||||
1264 | if (!dc) | ||||
1265 | return NULL((void *)0); | ||||
1266 | |||||
1267 | if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) { | ||||
1268 | if (!dc_construct_ctx(dc, init_params)) | ||||
1269 | goto destruct_dc; | ||||
1270 | } else { | ||||
1271 | if (!dc_construct(dc, init_params)) | ||||
1272 | goto destruct_dc; | ||||
1273 | |||||
1274 | full_pipe_count = dc->res_pool->pipe_count; | ||||
1275 | if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE-1) | ||||
1276 | full_pipe_count--; | ||||
1277 | dc->caps.max_streams = min((((full_pipe_count)<(dc->res_pool->stream_enc_count) )?(full_pipe_count):(dc->res_pool->stream_enc_count)) | ||||
1278 | full_pipe_count,(((full_pipe_count)<(dc->res_pool->stream_enc_count) )?(full_pipe_count):(dc->res_pool->stream_enc_count)) | ||||
1279 | dc->res_pool->stream_enc_count)(((full_pipe_count)<(dc->res_pool->stream_enc_count) )?(full_pipe_count):(dc->res_pool->stream_enc_count)); | ||||
1280 | |||||
1281 | dc->caps.max_links = dc->link_count; | ||||
1282 | dc->caps.max_audios = dc->res_pool->audio_count; | ||||
1283 | dc->caps.linear_pitch_alignment = 64; | ||||
1284 | |||||
1285 | dc->caps.max_dp_protocol_version = DP_VERSION_1_4; | ||||
1286 | |||||
1287 | dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator; | ||||
1288 | |||||
1289 | if (dc->res_pool->dmcu != NULL((void *)0)) | ||||
1290 | dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version; | ||||
1291 | } | ||||
1292 | |||||
1293 | dc->dcn_reg_offsets = init_params->dcn_reg_offsets; | ||||
1294 | dc->nbio_reg_offsets = init_params->nbio_reg_offsets; | ||||
1295 | |||||
1296 | /* Populate versioning information */ | ||||
1297 | dc->versions.dc_ver = DC_VER"3.2.207"; | ||||
1298 | |||||
1299 | dc->build_id = DC_BUILD_ID; | ||||
1300 | |||||
1301 | DC_LOG_DC("Display Core initialized\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Display Core initialized\n" ); | ||||
1302 | |||||
1303 | |||||
1304 | |||||
1305 | return dc; | ||||
1306 | |||||
1307 | destruct_dc: | ||||
1308 | dc_destruct(dc); | ||||
1309 | kfree(dc); | ||||
1310 | return NULL((void *)0); | ||||
1311 | } | ||||
1312 | |||||
1313 | static void detect_edp_presence(struct dc *dc) | ||||
1314 | { | ||||
1315 | struct dc_link *edp_links[MAX_NUM_EDP2]; | ||||
1316 | struct dc_link *edp_link = NULL((void *)0); | ||||
1317 | enum dc_connection_type type; | ||||
1318 | int i; | ||||
1319 | int edp_num; | ||||
1320 | |||||
1321 | get_edp_links(dc, edp_links, &edp_num); | ||||
1322 | if (!edp_num) | ||||
1323 | return; | ||||
1324 | |||||
1325 | for (i = 0; i < edp_num; i++) { | ||||
1326 | edp_link = edp_links[i]; | ||||
1327 | if (dc->config.edp_not_connected) { | ||||
1328 | edp_link->edp_sink_present = false0; | ||||
1329 | } else { | ||||
1330 | dc_link_detect_sink(edp_link, &type); | ||||
1331 | edp_link->edp_sink_present = (type != dc_connection_none); | ||||
1332 | } | ||||
1333 | } | ||||
1334 | } | ||||
1335 | |||||
1336 | void dc_hardware_init(struct dc *dc) | ||||
1337 | { | ||||
1338 | |||||
1339 | detect_edp_presence(dc); | ||||
1340 | if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) | ||||
1341 | dc->hwss.init_hw(dc); | ||||
1342 | } | ||||
1343 | |||||
1344 | void dc_init_callbacks(struct dc *dc, | ||||
1345 | const struct dc_callback_init *init_params) | ||||
1346 | { | ||||
1347 | #ifdef CONFIG_DRM_AMD_DC_HDCP | ||||
1348 | dc->ctx->cp_psp = init_params->cp_psp; | ||||
1349 | #endif | ||||
1350 | } | ||||
1351 | |||||
1352 | void dc_deinit_callbacks(struct dc *dc) | ||||
1353 | { | ||||
1354 | #ifdef CONFIG_DRM_AMD_DC_HDCP | ||||
1355 | memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp))__builtin_memset((&dc->ctx->cp_psp), (0), (sizeof(dc ->ctx->cp_psp))); | ||||
1356 | #endif | ||||
1357 | } | ||||
1358 | |||||
1359 | void dc_destroy(struct dc **dc) | ||||
1360 | { | ||||
1361 | dc_destruct(*dc); | ||||
1362 | kfree(*dc); | ||||
1363 | *dc = NULL((void *)0); | ||||
1364 | } | ||||
1365 | |||||
1366 | static void enable_timing_multisync( | ||||
1367 | struct dc *dc, | ||||
1368 | struct dc_state *ctx) | ||||
1369 | { | ||||
1370 | int i, multisync_count = 0; | ||||
1371 | int pipe_count = dc->res_pool->pipe_count; | ||||
1372 | struct pipe_ctx *multisync_pipes[MAX_PIPES6] = { NULL((void *)0) }; | ||||
1373 | |||||
1374 | for (i = 0; i < pipe_count; i++) { | ||||
1375 | if (!ctx->res_ctx.pipe_ctx[i].stream || | ||||
1376 | !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled) | ||||
1377 | continue; | ||||
1378 | if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source) | ||||
1379 | continue; | ||||
1380 | multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i]; | ||||
1381 | multisync_count++; | ||||
1382 | } | ||||
1383 | |||||
1384 | if (multisync_count > 0) { | ||||
1385 | dc->hwss.enable_per_frame_crtc_position_reset( | ||||
1386 | dc, multisync_count, multisync_pipes); | ||||
1387 | } | ||||
1388 | } | ||||
1389 | |||||
1390 | static void program_timing_sync( | ||||
1391 | struct dc *dc, | ||||
1392 | struct dc_state *ctx) | ||||
1393 | { | ||||
1394 | int i, j, k; | ||||
1395 | int group_index = 0; | ||||
1396 | int num_group = 0; | ||||
1397 | int pipe_count = dc->res_pool->pipe_count; | ||||
1398 | struct pipe_ctx *unsynced_pipes[MAX_PIPES6] = { NULL((void *)0) }; | ||||
1399 | |||||
1400 | for (i = 0; i < pipe_count; i++) { | ||||
1401 | if (!ctx->res_ctx.pipe_ctx[i].stream | ||||
1402 | || ctx->res_ctx.pipe_ctx[i].top_pipe | ||||
1403 | || ctx->res_ctx.pipe_ctx[i].prev_odm_pipe) | ||||
1404 | continue; | ||||
1405 | |||||
1406 | unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i]; | ||||
1407 | } | ||||
1408 | |||||
1409 | for (i = 0; i < pipe_count; i++) { | ||||
1410 | int group_size = 1; | ||||
1411 | enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE; | ||||
1412 | struct pipe_ctx *pipe_set[MAX_PIPES6]; | ||||
1413 | |||||
1414 | if (!unsynced_pipes[i]) | ||||
1415 | continue; | ||||
1416 | |||||
1417 | pipe_set[0] = unsynced_pipes[i]; | ||||
1418 | unsynced_pipes[i] = NULL((void *)0); | ||||
1419 | |||||
1420 | /* Add tg to the set, search rest of the tg's for ones with | ||||
1421 | * same timing, add all tgs with same timing to the group | ||||
1422 | */ | ||||
1423 | for (j = i + 1; j < pipe_count; j++) { | ||||
1424 | if (!unsynced_pipes[j]) | ||||
1425 | continue; | ||||
1426 | if (sync_type != TIMING_SYNCHRONIZABLE && | ||||
1427 | dc->hwss.enable_vblanks_synchronization && | ||||
1428 | unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks && | ||||
1429 | resource_are_vblanks_synchronizable( | ||||
1430 | unsynced_pipes[j]->stream, | ||||
1431 | pipe_set[0]->stream)) { | ||||
1432 | sync_type = VBLANK_SYNCHRONIZABLE; | ||||
1433 | pipe_set[group_size] = unsynced_pipes[j]; | ||||
1434 | unsynced_pipes[j] = NULL((void *)0); | ||||
1435 | group_size++; | ||||
1436 | } else | ||||
1437 | if (sync_type != VBLANK_SYNCHRONIZABLE && | ||||
1438 | resource_are_streams_timing_synchronizable( | ||||
1439 | unsynced_pipes[j]->stream, | ||||
1440 | pipe_set[0]->stream)) { | ||||
1441 | sync_type = TIMING_SYNCHRONIZABLE; | ||||
1442 | pipe_set[group_size] = unsynced_pipes[j]; | ||||
1443 | unsynced_pipes[j] = NULL((void *)0); | ||||
1444 | group_size++; | ||||
1445 | } | ||||
1446 | } | ||||
1447 | |||||
1448 | /* set first unblanked pipe as master */ | ||||
1449 | for (j = 0; j < group_size; j++) { | ||||
1450 | bool_Bool is_blanked; | ||||
1451 | |||||
1452 | if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked) | ||||
1453 | is_blanked = | ||||
1454 | pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp); | ||||
1455 | else | ||||
1456 | is_blanked = | ||||
1457 | pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg); | ||||
1458 | if (!is_blanked) { | ||||
1459 | if (j == 0) | ||||
1460 | break; | ||||
1461 | |||||
1462 | swap(pipe_set[0], pipe_set[j])do { __typeof(pipe_set[0]) __tmp = (pipe_set[0]); (pipe_set[0 ]) = (pipe_set[j]); (pipe_set[j]) = __tmp; } while(0); | ||||
1463 | break; | ||||
1464 | } | ||||
1465 | } | ||||
1466 | |||||
1467 | for (k = 0; k < group_size; k++) { | ||||
1468 | struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream); | ||||
1469 | |||||
1470 | status->timing_sync_info.group_id = num_group; | ||||
1471 | status->timing_sync_info.group_size = group_size; | ||||
1472 | if (k == 0) | ||||
1473 | status->timing_sync_info.master = true1; | ||||
1474 | else | ||||
1475 | status->timing_sync_info.master = false0; | ||||
1476 | |||||
1477 | } | ||||
1478 | |||||
1479 | /* remove any other pipes that are already been synced */ | ||||
1480 | if (dc->config.use_pipe_ctx_sync_logic) { | ||||
1481 | /* check pipe's syncd to decide which pipe to be removed */ | ||||
1482 | for (j = 1; j < group_size; j++) { | ||||
1483 | if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) { | ||||
1484 | group_size--; | ||||
1485 | pipe_set[j] = pipe_set[group_size]; | ||||
1486 | j--; | ||||
1487 | } else | ||||
1488 | /* link slave pipe's syncd with master pipe */ | ||||
1489 | pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd; | ||||
1490 | } | ||||
1491 | } else { | ||||
1492 | for (j = j + 1; j < group_size; j++) { | ||||
1493 | bool_Bool is_blanked; | ||||
1494 | |||||
1495 | if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked) | ||||
1496 | is_blanked = | ||||
1497 | pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp); | ||||
1498 | else | ||||
1499 | is_blanked = | ||||
1500 | pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg); | ||||
1501 | if (!is_blanked) { | ||||
1502 | group_size--; | ||||
1503 | pipe_set[j] = pipe_set[group_size]; | ||||
1504 | j--; | ||||
1505 | } | ||||
1506 | } | ||||
1507 | } | ||||
1508 | |||||
1509 | if (group_size > 1) { | ||||
1510 | if (sync_type == TIMING_SYNCHRONIZABLE) { | ||||
1511 | dc->hwss.enable_timing_synchronization( | ||||
1512 | dc, group_index, group_size, pipe_set); | ||||
1513 | } else | ||||
1514 | if (sync_type == VBLANK_SYNCHRONIZABLE) { | ||||
1515 | dc->hwss.enable_vblanks_synchronization( | ||||
1516 | dc, group_index, group_size, pipe_set); | ||||
1517 | } | ||||
1518 | group_index++; | ||||
1519 | } | ||||
1520 | num_group++; | ||||
1521 | } | ||||
1522 | } | ||||
1523 | |||||
1524 | static bool_Bool streams_changed(struct dc *dc, | ||||
1525 | struct dc_stream_state *streams[], | ||||
1526 | uint8_t stream_count) | ||||
1527 | { | ||||
1528 | uint8_t i; | ||||
1529 | |||||
1530 | if (stream_count != dc->current_state->stream_count) | ||||
1531 | return true1; | ||||
1532 | |||||
1533 | for (i = 0; i < dc->current_state->stream_count; i++) { | ||||
1534 | if (dc->current_state->streams[i] != streams[i]) | ||||
1535 | return true1; | ||||
1536 | if (!streams[i]->link->link_state_valid) | ||||
1537 | return true1; | ||||
1538 | } | ||||
1539 | |||||
1540 | return false0; | ||||
1541 | } | ||||
1542 | |||||
1543 | bool_Bool dc_validate_boot_timing(const struct dc *dc, | ||||
1544 | const struct dc_sink *sink, | ||||
1545 | struct dc_crtc_timing *crtc_timing) | ||||
1546 | { | ||||
1547 | struct timing_generator *tg; | ||||
1548 | struct stream_encoder *se = NULL((void *)0); | ||||
1549 | |||||
1550 | struct dc_crtc_timing hw_crtc_timing = {0}; | ||||
1551 | |||||
1552 | struct dc_link *link = sink->link; | ||||
1553 | unsigned int i, enc_inst, tg_inst = 0; | ||||
1554 | |||||
1555 | /* Support seamless boot on EDP displays only */ | ||||
1556 | if (sink->sink_signal != SIGNAL_TYPE_EDP) { | ||||
1557 | return false0; | ||||
1558 | } | ||||
1559 | |||||
1560 | if (dc->debug.force_odm_combine) | ||||
1561 | return false0; | ||||
1562 | |||||
1563 | /* Check for enabled DIG to identify enabled display */ | ||||
1564 | if (!link->link_enc->funcs->is_dig_enabled(link->link_enc)) | ||||
1565 | return false0; | ||||
1566 | |||||
1567 | enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc); | ||||
1568 | |||||
1569 | if (enc_inst == ENGINE_ID_UNKNOWN) | ||||
1570 | return false0; | ||||
1571 | |||||
1572 | for (i = 0; i < dc->res_pool->stream_enc_count; i++) { | ||||
1573 | if (dc->res_pool->stream_enc[i]->id == enc_inst) { | ||||
1574 | |||||
1575 | se = dc->res_pool->stream_enc[i]; | ||||
1576 | |||||
1577 | tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg( | ||||
1578 | dc->res_pool->stream_enc[i]); | ||||
1579 | break; | ||||
1580 | } | ||||
1581 | } | ||||
1582 | |||||
1583 | // tg_inst not found | ||||
1584 | if (i == dc->res_pool->stream_enc_count) | ||||
1585 | return false0; | ||||
1586 | |||||
1587 | if (tg_inst >= dc->res_pool->timing_generator_count) | ||||
1588 | return false0; | ||||
1589 | |||||
1590 | tg = dc->res_pool->timing_generators[tg_inst]; | ||||
1591 | |||||
1592 | if (!tg->funcs->get_hw_timing) | ||||
1593 | return false0; | ||||
1594 | |||||
1595 | if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing)) | ||||
1596 | return false0; | ||||
1597 | |||||
1598 | if (crtc_timing->h_total != hw_crtc_timing.h_total) | ||||
1599 | return false0; | ||||
1600 | |||||
1601 | if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left) | ||||
1602 | return false0; | ||||
1603 | |||||
1604 | if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable) | ||||
1605 | return false0; | ||||
1606 | |||||
1607 | if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right) | ||||
1608 | return false0; | ||||
1609 | |||||
1610 | if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch) | ||||
1611 | return false0; | ||||
1612 | |||||
1613 | if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width) | ||||
1614 | return false0; | ||||
1615 | |||||
1616 | if (crtc_timing->v_total != hw_crtc_timing.v_total) | ||||
1617 | return false0; | ||||
1618 | |||||
1619 | if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top) | ||||
1620 | return false0; | ||||
1621 | |||||
1622 | if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable) | ||||
1623 | return false0; | ||||
1624 | |||||
1625 | if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom) | ||||
1626 | return false0; | ||||
1627 | |||||
1628 | if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch) | ||||
1629 | return false0; | ||||
1630 | |||||
1631 | if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width) | ||||
1632 | return false0; | ||||
1633 | |||||
1634 | /* block DSC for now, as VBIOS does not currently support DSC timings */ | ||||
1635 | if (crtc_timing->flags.DSC) | ||||
1636 | return false0; | ||||
1637 | |||||
1638 | if (dc_is_dp_signal(link->connector_signal)) { | ||||
1639 | unsigned int pix_clk_100hz; | ||||
1640 | uint32_t numOdmPipes = 1; | ||||
1641 | uint32_t id_src[4] = {0}; | ||||
1642 | |||||
1643 | dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz( | ||||
1644 | dc->res_pool->dp_clock_source, | ||||
1645 | tg_inst, &pix_clk_100hz); | ||||
1646 | |||||
1647 | if (tg->funcs->get_optc_source) | ||||
1648 | tg->funcs->get_optc_source(tg, | ||||
1649 | &numOdmPipes, &id_src[0], &id_src[1]); | ||||
1650 | |||||
1651 | if (numOdmPipes == 2) | ||||
1652 | pix_clk_100hz *= 2; | ||||
1653 | if (numOdmPipes == 4) | ||||
1654 | pix_clk_100hz *= 4; | ||||
1655 | |||||
1656 | // Note: In rare cases, HW pixclk may differ from crtc's pixclk | ||||
1657 | // slightly due to rounding issues in 10 kHz units. | ||||
1658 | if (crtc_timing->pix_clk_100hz != pix_clk_100hz) | ||||
1659 | return false0; | ||||
1660 | |||||
1661 | if (!se->funcs->dp_get_pixel_format) | ||||
1662 | return false0; | ||||
1663 | |||||
1664 | if (!se->funcs->dp_get_pixel_format( | ||||
1665 | se, | ||||
1666 | &hw_crtc_timing.pixel_encoding, | ||||
1667 | &hw_crtc_timing.display_color_depth)) | ||||
1668 | return false0; | ||||
1669 | |||||
1670 | if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth) | ||||
1671 | return false0; | ||||
1672 | |||||
1673 | if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding) | ||||
1674 | return false0; | ||||
1675 | } | ||||
1676 | |||||
1677 | if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) { | ||||
1678 | return false0; | ||||
1679 | } | ||||
1680 | |||||
1681 | if (is_edp_ilr_optimization_required(link, crtc_timing)) { | ||||
1682 | DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Seamless boot disabled to optimize eDP link rate\n" ); | ||||
1683 | return false0; | ||||
1684 | } | ||||
1685 | |||||
1686 | return true1; | ||||
1687 | } | ||||
1688 | |||||
1689 | static inline bool_Bool should_update_pipe_for_stream( | ||||
1690 | struct dc_state *context, | ||||
1691 | struct pipe_ctx *pipe_ctx, | ||||
1692 | struct dc_stream_state *stream) | ||||
1693 | { | ||||
1694 | return (pipe_ctx->stream && pipe_ctx->stream == stream); | ||||
1695 | } | ||||
1696 | |||||
1697 | static inline bool_Bool should_update_pipe_for_plane( | ||||
1698 | struct dc_state *context, | ||||
1699 | struct pipe_ctx *pipe_ctx, | ||||
1700 | struct dc_plane_state *plane_state) | ||||
1701 | { | ||||
1702 | return (pipe_ctx->plane_state == plane_state); | ||||
1703 | } | ||||
1704 | |||||
1705 | void dc_enable_stereo( | ||||
1706 | struct dc *dc, | ||||
1707 | struct dc_state *context, | ||||
1708 | struct dc_stream_state *streams[], | ||||
1709 | uint8_t stream_count) | ||||
1710 | { | ||||
1711 | int i, j; | ||||
1712 | struct pipe_ctx *pipe; | ||||
1713 | |||||
1714 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
1715 | if (context != NULL((void *)0)) { | ||||
1716 | pipe = &context->res_ctx.pipe_ctx[i]; | ||||
1717 | } else { | ||||
1718 | context = dc->current_state; | ||||
1719 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
1720 | } | ||||
1721 | |||||
1722 | for (j = 0; pipe && j < stream_count; j++) { | ||||
1723 | if (should_update_pipe_for_stream(context, pipe, streams[j]) && | ||||
1724 | dc->hwss.setup_stereo) | ||||
1725 | dc->hwss.setup_stereo(pipe, dc); | ||||
1726 | } | ||||
1727 | } | ||||
1728 | } | ||||
1729 | |||||
1730 | void dc_trigger_sync(struct dc *dc, struct dc_state *context) | ||||
1731 | { | ||||
1732 | if (context->stream_count > 1 && !dc->debug.disable_timing_sync) { | ||||
1733 | enable_timing_multisync(dc, context); | ||||
1734 | program_timing_sync(dc, context); | ||||
1735 | } | ||||
1736 | } | ||||
1737 | |||||
1738 | static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context) | ||||
1739 | { | ||||
1740 | int i; | ||||
1741 | unsigned int stream_mask = 0; | ||||
1742 | |||||
1743 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
1744 | if (context->res_ctx.pipe_ctx[i].stream) | ||||
1745 | stream_mask |= 1 << i; | ||||
1746 | } | ||||
1747 | |||||
1748 | return stream_mask; | ||||
1749 | } | ||||
1750 | |||||
1751 | void dc_z10_restore(const struct dc *dc) | ||||
1752 | { | ||||
1753 | if (dc->hwss.z10_restore) | ||||
1754 | dc->hwss.z10_restore(dc); | ||||
1755 | } | ||||
1756 | |||||
1757 | void dc_z10_save_init(struct dc *dc) | ||||
1758 | { | ||||
1759 | if (dc->hwss.z10_save_init) | ||||
1760 | dc->hwss.z10_save_init(dc); | ||||
1761 | } | ||||
1762 | |||||
1763 | /* | ||||
1764 | * Applies given context to HW and copy it into current context. | ||||
1765 | * It's up to the user to release the src context afterwards. | ||||
1766 | * | ||||
1767 | * Return: an enum dc_status result code for the operation | ||||
1768 | */ | ||||
1769 | static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context) | ||||
1770 | { | ||||
1771 | struct dc_bios *dcb = dc->ctx->dc_bios; | ||||
1772 | enum dc_status result = DC_ERROR_UNEXPECTED; | ||||
1773 | struct pipe_ctx *pipe; | ||||
1774 | int i, k, l; | ||||
1775 | struct dc_stream_state *dc_streams[MAX_STREAMS6] = {0}; | ||||
1776 | struct dc_state *old_state; | ||||
1777 | bool_Bool subvp_prev_use = false0; | ||||
1778 | |||||
1779 | dc_z10_restore(dc); | ||||
1780 | dc_allow_idle_optimizations(dc, false0); | ||||
1781 | |||||
1782 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
1783 | struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
1784 | |||||
1785 | /* Check old context for SubVP */ | ||||
1786 | subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM); | ||||
1787 | if (subvp_prev_use) | ||||
1788 | break; | ||||
1789 | } | ||||
1790 | |||||
1791 | for (i = 0; i < context->stream_count; i++) | ||||
1792 | dc_streams[i] = context->streams[i]; | ||||
1793 | |||||
1794 | if (!dcb->funcs->is_accelerated_mode(dcb)) { | ||||
1795 | disable_vbios_mode_if_required(dc, context); | ||||
1796 | dc->hwss.enable_accelerated_mode(dc, context); | ||||
1797 | } | ||||
1798 | |||||
1799 | if (context->stream_count > get_seamless_boot_stream_count(context) || | ||||
1800 | context->stream_count == 0) | ||||
1801 | dc->hwss.prepare_bandwidth(dc, context); | ||||
1802 | |||||
1803 | /* When SubVP is active, all HW programming must be done while | ||||
1804 | * SubVP lock is acquired | ||||
1805 | */ | ||||
1806 | if (dc->hwss.subvp_pipe_control_lock) | ||||
1807 | dc->hwss.subvp_pipe_control_lock(dc, context, true1, true1, NULL((void *)0), subvp_prev_use); | ||||
1808 | |||||
1809 | if (dc->hwss.update_dsc_pg) | ||||
1810 | dc->hwss.update_dsc_pg(dc, context, false0); | ||||
1811 | |||||
1812 | disable_dangling_plane(dc, context); | ||||
1813 | /* re-program planes for existing stream, in case we need to | ||||
1814 | * free up plane resource for later use | ||||
1815 | */ | ||||
1816 | if (dc->hwss.apply_ctx_for_surface) { | ||||
1817 | for (i = 0; i < context->stream_count; i++) { | ||||
1818 | if (context->streams[i]->mode_changed) | ||||
1819 | continue; | ||||
1820 | apply_ctx_interdependent_lock(dc, context, context->streams[i], true1); | ||||
1821 | dc->hwss.apply_ctx_for_surface( | ||||
1822 | dc, context->streams[i], | ||||
1823 | context->stream_status[i].plane_count, | ||||
1824 | context); /* use new pipe config in new context */ | ||||
1825 | apply_ctx_interdependent_lock(dc, context, context->streams[i], false0); | ||||
1826 | dc->hwss.post_unlock_program_front_end(dc, context); | ||||
1827 | } | ||||
1828 | } | ||||
1829 | |||||
1830 | /* Program hardware */ | ||||
1831 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
1832 | pipe = &context->res_ctx.pipe_ctx[i]; | ||||
1833 | dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe); | ||||
1834 | } | ||||
1835 | |||||
1836 | result = dc->hwss.apply_ctx_to_hw(dc, context); | ||||
1837 | |||||
1838 | if (result != DC_OK) { | ||||
1839 | /* Application of dc_state to hardware stopped. */ | ||||
1840 | dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY; | ||||
1841 | return result; | ||||
1842 | } | ||||
1843 | |||||
1844 | dc_trigger_sync(dc, context); | ||||
1845 | |||||
1846 | /* Program all planes within new context*/ | ||||
1847 | if (dc->hwss.program_front_end_for_ctx) { | ||||
1848 | dc->hwss.interdependent_update_lock(dc, context, true1); | ||||
1849 | dc->hwss.program_front_end_for_ctx(dc, context); | ||||
1850 | dc->hwss.interdependent_update_lock(dc, context, false0); | ||||
1851 | dc->hwss.post_unlock_program_front_end(dc, context); | ||||
1852 | } | ||||
1853 | |||||
1854 | if (dc->hwss.commit_subvp_config) | ||||
1855 | dc->hwss.commit_subvp_config(dc, context); | ||||
1856 | if (dc->hwss.subvp_pipe_control_lock) | ||||
1857 | dc->hwss.subvp_pipe_control_lock(dc, context, false0, true1, NULL((void *)0), subvp_prev_use); | ||||
1858 | |||||
1859 | for (i = 0; i < context->stream_count; i++) { | ||||
1860 | const struct dc_link *link = context->streams[i]->link; | ||||
1861 | |||||
1862 | if (!context->streams[i]->mode_changed) | ||||
1863 | continue; | ||||
1864 | |||||
1865 | if (dc->hwss.apply_ctx_for_surface) { | ||||
1866 | apply_ctx_interdependent_lock(dc, context, context->streams[i], true1); | ||||
1867 | dc->hwss.apply_ctx_for_surface( | ||||
1868 | dc, context->streams[i], | ||||
1869 | context->stream_status[i].plane_count, | ||||
1870 | context); | ||||
1871 | apply_ctx_interdependent_lock(dc, context, context->streams[i], false0); | ||||
1872 | dc->hwss.post_unlock_program_front_end(dc, context); | ||||
1873 | } | ||||
1874 | |||||
1875 | /* | ||||
1876 | * enable stereo | ||||
1877 | * TODO rework dc_enable_stereo call to work with validation sets? | ||||
1878 | */ | ||||
1879 | for (k = 0; k < MAX_PIPES6; k++) { | ||||
1880 | pipe = &context->res_ctx.pipe_ctx[k]; | ||||
1881 | |||||
1882 | for (l = 0 ; pipe && l < context->stream_count; l++) { | ||||
1883 | if (context->streams[l] && | ||||
1884 | context->streams[l] == pipe->stream && | ||||
1885 | dc->hwss.setup_stereo) | ||||
1886 | dc->hwss.setup_stereo(pipe, dc); | ||||
1887 | } | ||||
1888 | } | ||||
1889 | |||||
1890 | CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "{%dx%d, %dx%d@%dKhz}" , context->streams[i]->timing.h_addressable, context-> streams[i]->timing.v_addressable, context->streams[i]-> timing.h_total, context->streams[i]->timing.v_total, context ->streams[i]->timing.pix_clk_100hz / 10); } while (0) | ||||
1891 | context->streams[i]->timing.h_addressable,do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "{%dx%d, %dx%d@%dKhz}" , context->streams[i]->timing.h_addressable, context-> streams[i]->timing.v_addressable, context->streams[i]-> timing.h_total, context->streams[i]->timing.v_total, context ->streams[i]->timing.pix_clk_100hz / 10); } while (0) | ||||
1892 | context->streams[i]->timing.v_addressable,do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "{%dx%d, %dx%d@%dKhz}" , context->streams[i]->timing.h_addressable, context-> streams[i]->timing.v_addressable, context->streams[i]-> timing.h_total, context->streams[i]->timing.v_total, context ->streams[i]->timing.pix_clk_100hz / 10); } while (0) | ||||
1893 | context->streams[i]->timing.h_total,do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "{%dx%d, %dx%d@%dKhz}" , context->streams[i]->timing.h_addressable, context-> streams[i]->timing.v_addressable, context->streams[i]-> timing.h_total, context->streams[i]->timing.v_total, context ->streams[i]->timing.pix_clk_100hz / 10); } while (0) | ||||
1894 | context->streams[i]->timing.v_total,do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "{%dx%d, %dx%d@%dKhz}" , context->streams[i]->timing.h_addressable, context-> streams[i]->timing.v_addressable, context->streams[i]-> timing.h_total, context->streams[i]->timing.v_total, context ->streams[i]->timing.pix_clk_100hz / 10); } while (0) | ||||
1895 | context->streams[i]->timing.pix_clk_100hz / 10)do { (void)(link); ___drm_dbg(((void *)0), DRM_UT_KMS, "{%dx%d, %dx%d@%dKhz}" , context->streams[i]->timing.h_addressable, context-> streams[i]->timing.v_addressable, context->streams[i]-> timing.h_total, context->streams[i]->timing.v_total, context ->streams[i]->timing.pix_clk_100hz / 10); } while (0); | ||||
1896 | } | ||||
1897 | |||||
1898 | dc_enable_stereo(dc, context, dc_streams, context->stream_count); | ||||
1899 | |||||
1900 | if (context->stream_count > get_seamless_boot_stream_count(context) || | ||||
1901 | context->stream_count == 0) { | ||||
1902 | /* Must wait for no flips to be pending before doing optimize bw */ | ||||
1903 | wait_for_no_pipes_pending(dc, context); | ||||
1904 | /* pplib is notified if disp_num changed */ | ||||
1905 | dc->hwss.optimize_bandwidth(dc, context); | ||||
1906 | } | ||||
1907 | |||||
1908 | if (dc->hwss.update_dsc_pg) | ||||
1909 | dc->hwss.update_dsc_pg(dc, context, true1); | ||||
1910 | |||||
1911 | if (dc->ctx->dce_version >= DCE_VERSION_MAX) | ||||
1912 | TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk)trace_amdgpu_dm_dc_clocks_state(&context->bw_ctx.bw.dcn .clk); | ||||
1913 | else | ||||
1914 | TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce)trace_amdgpu_dm_dce_clocks_state(&context->bw_ctx.bw.dce ); | ||||
1915 | |||||
1916 | context->stream_mask = get_stream_mask(dc, context); | ||||
1917 | |||||
1918 | if (context->stream_mask != dc->current_state->stream_mask) | ||||
1919 | dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask); | ||||
1920 | |||||
1921 | for (i = 0; i < context->stream_count; i++) | ||||
1922 | context->streams[i]->mode_changed = false0; | ||||
1923 | |||||
1924 | old_state = dc->current_state; | ||||
1925 | dc->current_state = context; | ||||
1926 | |||||
1927 | dc_release_state(old_state); | ||||
1928 | |||||
1929 | dc_retain_state(dc->current_state); | ||||
1930 | |||||
1931 | return result; | ||||
1932 | } | ||||
1933 | |||||
1934 | static bool_Bool commit_minimal_transition_state(struct dc *dc, | ||||
1935 | struct dc_state *transition_base_context); | ||||
1936 | |||||
1937 | /** | ||||
1938 | * dc_commit_streams - Commit current stream state | ||||
1939 | * | ||||
1940 | * @dc: DC object with the commit state to be configured in the hardware | ||||
1941 | * @streams: Array with a list of stream state | ||||
1942 | * @stream_count: Total of streams | ||||
1943 | * | ||||
1944 | * Function responsible for commit streams change to the hardware. | ||||
1945 | * | ||||
1946 | * Return: | ||||
1947 | * Return DC_OK if everything work as expected, otherwise, return a dc_status | ||||
1948 | * code. | ||||
1949 | */ | ||||
1950 | enum dc_status dc_commit_streams(struct dc *dc, | ||||
1951 | struct dc_stream_state *streams[], | ||||
1952 | uint8_t stream_count) | ||||
1953 | { | ||||
1954 | int i, j; | ||||
1955 | struct dc_state *context; | ||||
1956 | enum dc_status res = DC_OK; | ||||
1957 | struct dc_validation_set set[MAX_STREAMS6] = {0}; | ||||
1958 | struct pipe_ctx *pipe; | ||||
1959 | bool_Bool handle_exit_odm2to1 = false0; | ||||
1960 | |||||
1961 | if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW) | ||||
1962 | return res; | ||||
1963 | |||||
1964 | if (!streams_changed(dc, streams, stream_count)) | ||||
1965 | return res; | ||||
1966 | |||||
1967 | DC_LOG_DC("%s: %d streams\n", __func__, stream_count)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: %d streams\n", __func__ , stream_count); | ||||
1968 | |||||
1969 | for (i = 0; i < stream_count; i++) { | ||||
1970 | struct dc_stream_state *stream = streams[i]; | ||||
1971 | struct dc_stream_status *status = dc_stream_get_status(stream); | ||||
1972 | |||||
1973 | dc_stream_log(dc, stream); | ||||
1974 | |||||
1975 | set[i].stream = stream; | ||||
1976 | |||||
1977 | if (status) { | ||||
1978 | set[i].plane_count = status->plane_count; | ||||
1979 | for (j = 0; j < status->plane_count; j++) | ||||
1980 | set[i].plane_states[j] = status->plane_states[j]; | ||||
1981 | } | ||||
1982 | } | ||||
1983 | |||||
1984 | /* ODM Combine 2:1 power optimization is only applied for single stream | ||||
1985 | * scenario, it uses extra pipes than needed to reduce power consumption | ||||
1986 | * We need to switch off this feature to make room for new streams. | ||||
1987 | */ | ||||
1988 | if (stream_count > dc->current_state->stream_count && | ||||
1989 | dc->current_state->stream_count == 1) { | ||||
1990 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
1991 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
1992 | if (pipe->next_odm_pipe) | ||||
1993 | handle_exit_odm2to1 = true1; | ||||
1994 | } | ||||
1995 | } | ||||
1996 | |||||
1997 | if (handle_exit_odm2to1) | ||||
1998 | res = commit_minimal_transition_state(dc, dc->current_state); | ||||
1999 | |||||
2000 | context = dc_create_state(dc); | ||||
2001 | if (!context) | ||||
2002 | goto context_alloc_fail; | ||||
2003 | |||||
2004 | dc_resource_state_copy_construct_current(dc, context); | ||||
2005 | |||||
2006 | res = dc_validate_with_context(dc, set, stream_count, context, false0); | ||||
2007 | if (res != DC_OK) { | ||||
2008 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2008); do {} while (0); } while (0); | ||||
2009 | goto fail; | ||||
2010 | } | ||||
2011 | |||||
2012 | res = dc_commit_state_no_check(dc, context); | ||||
2013 | |||||
2014 | for (i = 0; i < stream_count; i++) { | ||||
2015 | for (j = 0; j < context->stream_count; j++) { | ||||
2016 | if (streams[i]->stream_id == context->streams[j]->stream_id) | ||||
2017 | streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst; | ||||
2018 | |||||
2019 | if (dc_is_embedded_signal(streams[i]->signal)) { | ||||
2020 | struct dc_stream_status *status = dc_stream_get_status_from_state(context, streams[i]); | ||||
2021 | |||||
2022 | if (dc->hwss.is_abm_supported) | ||||
2023 | status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, streams[i]); | ||||
2024 | else | ||||
2025 | status->is_abm_supported = true1; | ||||
2026 | } | ||||
2027 | } | ||||
2028 | } | ||||
2029 | |||||
2030 | fail: | ||||
2031 | dc_release_state(context); | ||||
2032 | |||||
2033 | context_alloc_fail: | ||||
2034 | |||||
2035 | DC_LOG_DC("%s Finished.\n", __func__)___drm_dbg(((void *)0), DRM_UT_KMS, "%s Finished.\n", __func__ ); | ||||
2036 | |||||
2037 | return (res == DC_OK); | ||||
2038 | } | ||||
2039 | |||||
2040 | /* TODO: When the transition to the new commit sequence is done, remove this | ||||
2041 | * function in favor of dc_commit_streams. */ | ||||
2042 | bool_Bool dc_commit_state(struct dc *dc, struct dc_state *context) | ||||
2043 | { | ||||
2044 | enum dc_status result = DC_ERROR_UNEXPECTED; | ||||
2045 | int i; | ||||
2046 | |||||
2047 | /* TODO: Since change commit sequence can have a huge impact, | ||||
2048 | * we decided to only enable it for DCN3x. However, as soon as | ||||
2049 | * we get more confident about this change we'll need to enable | ||||
2050 | * the new sequence for all ASICs. */ | ||||
2051 | if (dc->ctx->dce_version >= DCN_VERSION_3_2) { | ||||
2052 | result = dc_commit_streams(dc, context->streams, context->stream_count); | ||||
2053 | return result == DC_OK; | ||||
2054 | } | ||||
2055 | |||||
2056 | if (!streams_changed(dc, context->streams, context->stream_count)) | ||||
2057 | return DC_OK; | ||||
2058 | |||||
2059 | DC_LOG_DC("%s: %d streams\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: %d streams\n", __func__ , context->stream_count) | ||||
2060 | __func__, context->stream_count)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: %d streams\n", __func__ , context->stream_count); | ||||
2061 | |||||
2062 | for (i = 0; i < context->stream_count; i++) { | ||||
2063 | struct dc_stream_state *stream = context->streams[i]; | ||||
2064 | |||||
2065 | dc_stream_log(dc, stream); | ||||
2066 | } | ||||
2067 | |||||
2068 | /* | ||||
2069 | * Previous validation was perfomred with fast_validation = true and | ||||
2070 | * the full DML state required for hardware programming was skipped. | ||||
2071 | * | ||||
2072 | * Re-validate here to calculate these parameters / watermarks. | ||||
2073 | */ | ||||
2074 | result = dc_validate_global_state(dc, context, false0); | ||||
2075 | if (result != DC_OK) { | ||||
2076 | DC_LOG_ERROR("DC commit global validation failure: %s (%d)",__drm_err("DC commit global validation failure: %s (%d)", dc_status_to_str (result), result) | ||||
2077 | dc_status_to_str(result), result)__drm_err("DC commit global validation failure: %s (%d)", dc_status_to_str (result), result); | ||||
2078 | return result; | ||||
2079 | } | ||||
2080 | |||||
2081 | result = dc_commit_state_no_check(dc, context); | ||||
2082 | |||||
2083 | return (result == DC_OK); | ||||
2084 | } | ||||
2085 | |||||
2086 | bool_Bool dc_acquire_release_mpc_3dlut( | ||||
2087 | struct dc *dc, bool_Bool acquire, | ||||
2088 | struct dc_stream_state *stream, | ||||
2089 | struct dc_3dlut **lut, | ||||
2090 | struct dc_transfer_func **shaper) | ||||
2091 | { | ||||
2092 | int pipe_idx; | ||||
2093 | bool_Bool ret = false0; | ||||
2094 | bool_Bool found_pipe_idx = false0; | ||||
2095 | const struct resource_pool *pool = dc->res_pool; | ||||
2096 | struct resource_context *res_ctx = &dc->current_state->res_ctx; | ||||
2097 | int mpcc_id = 0; | ||||
2098 | |||||
2099 | if (pool && res_ctx) { | ||||
2100 | if (acquire) { | ||||
2101 | /*find pipe idx for the given stream*/ | ||||
2102 | for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) { | ||||
2103 | if (res_ctx->pipe_ctx[pipe_idx].stream == stream) { | ||||
2104 | found_pipe_idx = true1; | ||||
2105 | mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; | ||||
2106 | break; | ||||
2107 | } | ||||
2108 | } | ||||
2109 | } else | ||||
2110 | found_pipe_idx = true1;/*for release pipe_idx is not required*/ | ||||
2111 | |||||
2112 | if (found_pipe_idx) { | ||||
2113 | if (acquire && pool->funcs->acquire_post_bldn_3dlut) | ||||
2114 | ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper); | ||||
2115 | else if (!acquire && pool->funcs->release_post_bldn_3dlut) | ||||
2116 | ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper); | ||||
2117 | } | ||||
2118 | } | ||||
2119 | return ret; | ||||
2120 | } | ||||
2121 | |||||
2122 | static bool_Bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context) | ||||
2123 | { | ||||
2124 | int i; | ||||
2125 | struct pipe_ctx *pipe; | ||||
2126 | |||||
2127 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
2128 | pipe = &context->res_ctx.pipe_ctx[i]; | ||||
2129 | |||||
2130 | // Don't check flip pending on phantom pipes | ||||
2131 | if (!pipe->plane_state || (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)) | ||||
2132 | continue; | ||||
2133 | |||||
2134 | /* Must set to false to start with, due to OR in update function */ | ||||
2135 | pipe->plane_state->status.is_flip_pending = false0; | ||||
2136 | dc->hwss.update_pending_status(pipe); | ||||
2137 | if (pipe->plane_state->status.is_flip_pending) | ||||
2138 | return true1; | ||||
2139 | } | ||||
2140 | return false0; | ||||
2141 | } | ||||
2142 | |||||
2143 | /* Perform updates here which need to be deferred until next vupdate | ||||
2144 | * | ||||
2145 | * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered | ||||
2146 | * but forcing lut memory to shutdown state is immediate. This causes | ||||
2147 | * single frame corruption as lut gets disabled mid-frame unless shutdown | ||||
2148 | * is deferred until after entering bypass. | ||||
2149 | */ | ||||
2150 | static void process_deferred_updates(struct dc *dc) | ||||
2151 | { | ||||
2152 | int i = 0; | ||||
2153 | |||||
2154 | if (dc->debug.enable_mem_low_power.bits.cm) { | ||||
2155 | ASSERT(dc->dcn_ip->max_num_dpp)do { if (({ static int __warned; int __ret = !!(!(dc->dcn_ip ->max_num_dpp)); if (__ret && !__warned) { printf( "WARNING %s failed at %s:%d\n", "!(dc->dcn_ip->max_num_dpp)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c", 2155); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
2156 | for (i = 0; i < dc->dcn_ip->max_num_dpp; i++) | ||||
2157 | if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update) | ||||
2158 | dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]); | ||||
2159 | } | ||||
2160 | } | ||||
2161 | |||||
2162 | void dc_post_update_surfaces_to_stream(struct dc *dc) | ||||
2163 | { | ||||
2164 | int i; | ||||
2165 | struct dc_state *context = dc->current_state; | ||||
2166 | |||||
2167 | if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0) | ||||
2168 | return; | ||||
2169 | |||||
2170 | post_surface_trace(dc); | ||||
2171 | |||||
2172 | /* | ||||
2173 | * Only relevant for DCN behavior where we can guarantee the optimization | ||||
2174 | * is safe to apply - retain the legacy behavior for DCE. | ||||
2175 | */ | ||||
2176 | |||||
2177 | if (dc->ctx->dce_version < DCE_VERSION_MAX) | ||||
2178 | TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce)trace_amdgpu_dm_dce_clocks_state(&context->bw_ctx.bw.dce ); | ||||
2179 | else { | ||||
2180 | TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk)trace_amdgpu_dm_dc_clocks_state(&context->bw_ctx.bw.dcn .clk); | ||||
2181 | |||||
2182 | if (is_flip_pending_in_pipes(dc, context)) | ||||
2183 | return; | ||||
2184 | |||||
2185 | for (i = 0; i < dc->res_pool->pipe_count; i++) | ||||
2186 | if (context->res_ctx.pipe_ctx[i].stream == NULL((void *)0) || | ||||
2187 | context->res_ctx.pipe_ctx[i].plane_state == NULL((void *)0)) { | ||||
2188 | context->res_ctx.pipe_ctx[i].pipe_idx = i; | ||||
2189 | dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]); | ||||
2190 | } | ||||
2191 | |||||
2192 | process_deferred_updates(dc); | ||||
2193 | |||||
2194 | dc->hwss.optimize_bandwidth(dc, context); | ||||
2195 | |||||
2196 | if (dc->hwss.update_dsc_pg) | ||||
2197 | dc->hwss.update_dsc_pg(dc, context, true1); | ||||
2198 | } | ||||
2199 | |||||
2200 | dc->optimized_required = false0; | ||||
2201 | dc->wm_optimized_required = false0; | ||||
2202 | } | ||||
2203 | |||||
2204 | static void init_state(struct dc *dc, struct dc_state *context) | ||||
2205 | { | ||||
2206 | /* Each context must have their own instance of VBA and in order to | ||||
2207 | * initialize and obtain IP and SOC the base DML instance from DC is | ||||
2208 | * initially copied into every context | ||||
2209 | */ | ||||
2210 | memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib))__builtin_memcpy((&context->bw_ctx.dml), (&dc-> dml), (sizeof(struct display_mode_lib))); | ||||
2211 | } | ||||
2212 | |||||
2213 | struct dc_state *dc_create_state(struct dc *dc) | ||||
2214 | { | ||||
2215 | struct dc_state *context = kvzalloc(sizeof(struct dc_state), | ||||
2216 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
2217 | |||||
2218 | if (!context) | ||||
2219 | return NULL((void *)0); | ||||
2220 | |||||
2221 | init_state(dc, context); | ||||
2222 | |||||
2223 | kref_init(&context->refcount); | ||||
2224 | |||||
2225 | return context; | ||||
2226 | } | ||||
2227 | |||||
2228 | struct dc_state *dc_copy_state(struct dc_state *src_ctx) | ||||
2229 | { | ||||
2230 | int i, j; | ||||
2231 | struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL(0x0001 | 0x0004)); | ||||
2232 | |||||
2233 | if (!new_ctx) | ||||
2234 | return NULL((void *)0); | ||||
2235 | memcpy(new_ctx, src_ctx, sizeof(struct dc_state))__builtin_memcpy((new_ctx), (src_ctx), (sizeof(struct dc_state ))); | ||||
2236 | |||||
2237 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
2238 | struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i]; | ||||
2239 | |||||
2240 | if (cur_pipe->top_pipe) | ||||
2241 | cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; | ||||
2242 | |||||
2243 | if (cur_pipe->bottom_pipe) | ||||
2244 | cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; | ||||
2245 | |||||
2246 | if (cur_pipe->prev_odm_pipe) | ||||
2247 | cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; | ||||
2248 | |||||
2249 | if (cur_pipe->next_odm_pipe) | ||||
2250 | cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; | ||||
2251 | |||||
2252 | } | ||||
2253 | |||||
2254 | for (i = 0; i < new_ctx->stream_count; i++) { | ||||
2255 | dc_stream_retain(new_ctx->streams[i]); | ||||
2256 | for (j = 0; j < new_ctx->stream_status[i].plane_count; j++) | ||||
2257 | dc_plane_state_retain( | ||||
2258 | new_ctx->stream_status[i].plane_states[j]); | ||||
2259 | } | ||||
2260 | |||||
2261 | kref_init(&new_ctx->refcount); | ||||
2262 | |||||
2263 | return new_ctx; | ||||
2264 | } | ||||
2265 | |||||
2266 | void dc_retain_state(struct dc_state *context) | ||||
2267 | { | ||||
2268 | kref_get(&context->refcount); | ||||
2269 | } | ||||
2270 | |||||
2271 | static void dc_state_free(struct kref *kref) | ||||
2272 | { | ||||
2273 | struct dc_state *context = container_of(kref, struct dc_state, refcount)({ const __typeof( ((struct dc_state *)0)->refcount ) *__mptr = (kref); (struct dc_state *)( (char *)__mptr - __builtin_offsetof (struct dc_state, refcount) );}); | ||||
2274 | dc_resource_state_destruct(context); | ||||
2275 | kvfree(context); | ||||
2276 | } | ||||
2277 | |||||
2278 | void dc_release_state(struct dc_state *context) | ||||
2279 | { | ||||
2280 | kref_put(&context->refcount, dc_state_free); | ||||
2281 | } | ||||
2282 | |||||
2283 | bool_Bool dc_set_generic_gpio_for_stereo(bool_Bool enable, | ||||
2284 | struct gpio_service *gpio_service) | ||||
2285 | { | ||||
2286 | enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR; | ||||
2287 | struct gpio_pin_info pin_info; | ||||
2288 | struct gpio *generic; | ||||
2289 | struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config), | ||||
2290 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
2291 | |||||
2292 | if (!config) | ||||
2293 | return false0; | ||||
2294 | pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0); | ||||
2295 | |||||
2296 | if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) { | ||||
2297 | kfree(config); | ||||
2298 | return false0; | ||||
2299 | } else { | ||||
2300 | generic = dal_gpio_service_create_generic_mux( | ||||
2301 | gpio_service, | ||||
2302 | pin_info.offset, | ||||
2303 | pin_info.mask); | ||||
2304 | } | ||||
2305 | |||||
2306 | if (!generic) { | ||||
2307 | kfree(config); | ||||
2308 | return false0; | ||||
2309 | } | ||||
2310 | |||||
2311 | gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT); | ||||
2312 | |||||
2313 | config->enable_output_from_mux = enable; | ||||
2314 | config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC; | ||||
2315 | |||||
2316 | if (gpio_result == GPIO_RESULT_OK) | ||||
2317 | gpio_result = dal_mux_setup_config(generic, config); | ||||
2318 | |||||
2319 | if (gpio_result == GPIO_RESULT_OK) { | ||||
2320 | dal_gpio_close(generic); | ||||
2321 | dal_gpio_destroy_generic_mux(&generic); | ||||
2322 | kfree(config); | ||||
2323 | return true1; | ||||
2324 | } else { | ||||
2325 | dal_gpio_close(generic); | ||||
2326 | dal_gpio_destroy_generic_mux(&generic); | ||||
2327 | kfree(config); | ||||
2328 | return false0; | ||||
2329 | } | ||||
2330 | } | ||||
2331 | |||||
2332 | static bool_Bool is_surface_in_context( | ||||
2333 | const struct dc_state *context, | ||||
2334 | const struct dc_plane_state *plane_state) | ||||
2335 | { | ||||
2336 | int j; | ||||
2337 | |||||
2338 | for (j = 0; j < MAX_PIPES6; j++) { | ||||
2339 | const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
2340 | |||||
2341 | if (plane_state == pipe_ctx->plane_state) { | ||||
2342 | return true1; | ||||
2343 | } | ||||
2344 | } | ||||
2345 | |||||
2346 | return false0; | ||||
2347 | } | ||||
2348 | |||||
2349 | static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u) | ||||
2350 | { | ||||
2351 | union surface_update_flags *update_flags = &u->surface->update_flags; | ||||
2352 | enum surface_update_type update_type = UPDATE_TYPE_FAST; | ||||
2353 | |||||
2354 | if (!u->plane_info) | ||||
2355 | return UPDATE_TYPE_FAST; | ||||
2356 | |||||
2357 | if (u->plane_info->color_space != u->surface->color_space) { | ||||
2358 | update_flags->bits.color_space_change = 1; | ||||
2359 | elevate_update_type(&update_type, UPDATE_TYPE_MED); | ||||
2360 | } | ||||
2361 | |||||
2362 | if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) { | ||||
2363 | update_flags->bits.horizontal_mirror_change = 1; | ||||
2364 | elevate_update_type(&update_type, UPDATE_TYPE_MED); | ||||
2365 | } | ||||
2366 | |||||
2367 | if (u->plane_info->rotation != u->surface->rotation) { | ||||
2368 | update_flags->bits.rotation_change = 1; | ||||
2369 | elevate_update_type(&update_type, UPDATE_TYPE_FULL); | ||||
2370 | } | ||||
2371 | |||||
2372 | if (u->plane_info->format != u->surface->format) { | ||||
2373 | update_flags->bits.pixel_format_change = 1; | ||||
2374 | elevate_update_type(&update_type, UPDATE_TYPE_FULL); | ||||
2375 | } | ||||
2376 | |||||
2377 | if (u->plane_info->stereo_format != u->surface->stereo_format) { | ||||
2378 | update_flags->bits.stereo_format_change = 1; | ||||
2379 | elevate_update_type(&update_type, UPDATE_TYPE_FULL); | ||||
2380 | } | ||||
2381 | |||||
2382 | if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) { | ||||
2383 | update_flags->bits.per_pixel_alpha_change = 1; | ||||
2384 | elevate_update_type(&update_type, UPDATE_TYPE_MED); | ||||
2385 | } | ||||
2386 | |||||
2387 | if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) { | ||||
2388 | update_flags->bits.global_alpha_change = 1; | ||||
2389 | elevate_update_type(&update_type, UPDATE_TYPE_MED); | ||||
2390 | } | ||||
2391 | |||||
2392 | if (u->plane_info->dcc.enable != u->surface->dcc.enable | ||||
2393 | || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk | ||||
2394 | || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) { | ||||
2395 | /* During DCC on/off, stutter period is calculated before | ||||
2396 | * DCC has fully transitioned. This results in incorrect | ||||
2397 | * stutter period calculation. Triggering a full update will | ||||
2398 | * recalculate stutter period. | ||||
2399 | */ | ||||
2400 | update_flags->bits.dcc_change = 1; | ||||
2401 | elevate_update_type(&update_type, UPDATE_TYPE_FULL); | ||||
2402 | } | ||||
2403 | |||||
2404 | if (resource_pixel_format_to_bpp(u->plane_info->format) != | ||||
2405 | resource_pixel_format_to_bpp(u->surface->format)) { | ||||
2406 | /* different bytes per element will require full bandwidth | ||||
2407 | * and DML calculation | ||||
2408 | */ | ||||
2409 | update_flags->bits.bpp_change = 1; | ||||
2410 | elevate_update_type(&update_type, UPDATE_TYPE_FULL); | ||||
2411 | } | ||||
2412 | |||||
2413 | if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch | ||||
2414 | || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) { | ||||
2415 | update_flags->bits.plane_size_change = 1; | ||||
2416 | elevate_update_type(&update_type, UPDATE_TYPE_MED); | ||||
2417 | } | ||||
2418 | |||||
2419 | |||||
2420 | if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,__builtin_memcmp((&u->plane_info->tiling_info), (& u->surface->tiling_info), (sizeof(union dc_tiling_info) )) | ||||
2421 | sizeof(union dc_tiling_info))__builtin_memcmp((&u->plane_info->tiling_info), (& u->surface->tiling_info), (sizeof(union dc_tiling_info) )) != 0) { | ||||
2422 | update_flags->bits.swizzle_change = 1; | ||||
2423 | elevate_update_type(&update_type, UPDATE_TYPE_MED); | ||||
2424 | |||||
2425 | /* todo: below are HW dependent, we should add a hook to | ||||
2426 | * DCE/N resource and validated there. | ||||
2427 | */ | ||||
2428 | if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { | ||||
2429 | /* swizzled mode requires RQ to be setup properly, | ||||
2430 | * thus need to run DML to calculate RQ settings | ||||
2431 | */ | ||||
2432 | update_flags->bits.bandwidth_change = 1; | ||||
2433 | elevate_update_type(&update_type, UPDATE_TYPE_FULL); | ||||
2434 | } | ||||
2435 | } | ||||
2436 | |||||
2437 | /* This should be UPDATE_TYPE_FAST if nothing has changed. */ | ||||
2438 | return update_type; | ||||
2439 | } | ||||
2440 | |||||
2441 | static enum surface_update_type get_scaling_info_update_type( | ||||
2442 | const struct dc *dc, | ||||
2443 | const struct dc_surface_update *u) | ||||
2444 | { | ||||
2445 | union surface_update_flags *update_flags = &u->surface->update_flags; | ||||
2446 | |||||
2447 | if (!u->scaling_info) | ||||
2448 | return UPDATE_TYPE_FAST; | ||||
2449 | |||||
2450 | if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width | ||||
2451 | || u->scaling_info->clip_rect.height != u->surface->clip_rect.height | ||||
2452 | || u->scaling_info->dst_rect.width != u->surface->dst_rect.width | ||||
2453 | || u->scaling_info->dst_rect.height != u->surface->dst_rect.height | ||||
2454 | || u->scaling_info->scaling_quality.integer_scaling != | ||||
2455 | u->surface->scaling_quality.integer_scaling | ||||
2456 | ) { | ||||
2457 | update_flags->bits.scaling_change = 1; | ||||
2458 | |||||
2459 | if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width | ||||
2460 | || u->scaling_info->dst_rect.height < u->surface->dst_rect.height) | ||||
2461 | && (u->scaling_info->dst_rect.width < u->surface->src_rect.width | ||||
2462 | || u->scaling_info->dst_rect.height < u->surface->src_rect.height)) | ||||
2463 | /* Making dst rect smaller requires a bandwidth change */ | ||||
2464 | update_flags->bits.bandwidth_change = 1; | ||||
2465 | } | ||||
2466 | |||||
2467 | if (u->scaling_info->src_rect.width != u->surface->src_rect.width | ||||
2468 | || u->scaling_info->src_rect.height != u->surface->src_rect.height) { | ||||
2469 | |||||
2470 | update_flags->bits.scaling_change = 1; | ||||
2471 | if (u->scaling_info->src_rect.width > u->surface->src_rect.width | ||||
2472 | || u->scaling_info->src_rect.height > u->surface->src_rect.height) | ||||
2473 | /* Making src rect bigger requires a bandwidth change */ | ||||
2474 | update_flags->bits.clock_change = 1; | ||||
2475 | } | ||||
2476 | |||||
2477 | if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width && | ||||
2478 | (u->scaling_info->clip_rect.width > u->surface->clip_rect.width || | ||||
2479 | u->scaling_info->clip_rect.height > u->surface->clip_rect.height)) | ||||
2480 | /* Changing clip size of a large surface may result in MPC slice count change */ | ||||
2481 | update_flags->bits.bandwidth_change = 1; | ||||
2482 | |||||
2483 | if (u->scaling_info->src_rect.x != u->surface->src_rect.x | ||||
2484 | || u->scaling_info->src_rect.y != u->surface->src_rect.y | ||||
2485 | || u->scaling_info->clip_rect.x != u->surface->clip_rect.x | ||||
2486 | || u->scaling_info->clip_rect.y != u->surface->clip_rect.y | ||||
2487 | || u->scaling_info->dst_rect.x != u->surface->dst_rect.x | ||||
2488 | || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) | ||||
2489 | update_flags->bits.position_change = 1; | ||||
2490 | |||||
2491 | if (update_flags->bits.clock_change | ||||
2492 | || update_flags->bits.bandwidth_change | ||||
2493 | || update_flags->bits.scaling_change) | ||||
2494 | return UPDATE_TYPE_FULL; | ||||
2495 | |||||
2496 | if (update_flags->bits.position_change) | ||||
2497 | return UPDATE_TYPE_MED; | ||||
2498 | |||||
2499 | return UPDATE_TYPE_FAST; | ||||
2500 | } | ||||
2501 | |||||
2502 | static enum surface_update_type det_surface_update(const struct dc *dc, | ||||
2503 | const struct dc_surface_update *u) | ||||
2504 | { | ||||
2505 | const struct dc_state *context = dc->current_state; | ||||
2506 | enum surface_update_type type; | ||||
2507 | enum surface_update_type overall_type = UPDATE_TYPE_FAST; | ||||
2508 | union surface_update_flags *update_flags = &u->surface->update_flags; | ||||
2509 | |||||
2510 | if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) { | ||||
2511 | update_flags->raw = 0xFFFFFFFF; | ||||
2512 | return UPDATE_TYPE_FULL; | ||||
2513 | } | ||||
2514 | |||||
2515 | update_flags->raw = 0; // Reset all flags | ||||
2516 | |||||
2517 | type = get_plane_info_update_type(u); | ||||
2518 | elevate_update_type(&overall_type, type); | ||||
2519 | |||||
2520 | type = get_scaling_info_update_type(dc, u); | ||||
2521 | elevate_update_type(&overall_type, type); | ||||
2522 | |||||
2523 | if (u->flip_addr) { | ||||
2524 | update_flags->bits.addr_update = 1; | ||||
2525 | if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) { | ||||
2526 | update_flags->bits.tmz_changed = 1; | ||||
2527 | elevate_update_type(&overall_type, UPDATE_TYPE_FULL); | ||||
2528 | } | ||||
2529 | } | ||||
2530 | if (u->in_transfer_func) | ||||
2531 | update_flags->bits.in_transfer_func_change = 1; | ||||
2532 | |||||
2533 | if (u->input_csc_color_matrix) | ||||
2534 | update_flags->bits.input_csc_change = 1; | ||||
2535 | |||||
2536 | if (u->coeff_reduction_factor) | ||||
2537 | update_flags->bits.coeff_reduction_change = 1; | ||||
2538 | |||||
2539 | if (u->gamut_remap_matrix) | ||||
2540 | update_flags->bits.gamut_remap_change = 1; | ||||
2541 | |||||
2542 | if (u->gamma) { | ||||
2543 | enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN; | ||||
2544 | |||||
2545 | if (u->plane_info) | ||||
2546 | format = u->plane_info->format; | ||||
2547 | else if (u->surface) | ||||
2548 | format = u->surface->format; | ||||
2549 | |||||
2550 | if (dce_use_lut(format)) | ||||
2551 | update_flags->bits.gamma_change = 1; | ||||
2552 | } | ||||
2553 | |||||
2554 | if (u->lut3d_func || u->func_shaper) | ||||
2555 | update_flags->bits.lut_3d = 1; | ||||
2556 | |||||
2557 | if (u->hdr_mult.value) | ||||
2558 | if (u->hdr_mult.value != u->surface->hdr_mult.value) { | ||||
2559 | update_flags->bits.hdr_mult = 1; | ||||
2560 | elevate_update_type(&overall_type, UPDATE_TYPE_MED); | ||||
2561 | } | ||||
2562 | |||||
2563 | if (update_flags->bits.in_transfer_func_change) { | ||||
2564 | type = UPDATE_TYPE_MED; | ||||
2565 | elevate_update_type(&overall_type, type); | ||||
2566 | } | ||||
2567 | |||||
2568 | if (update_flags->bits.input_csc_change | ||||
2569 | || update_flags->bits.coeff_reduction_change | ||||
2570 | || update_flags->bits.lut_3d | ||||
2571 | || update_flags->bits.gamma_change | ||||
2572 | || update_flags->bits.gamut_remap_change) { | ||||
2573 | type = UPDATE_TYPE_FULL; | ||||
2574 | elevate_update_type(&overall_type, type); | ||||
2575 | } | ||||
2576 | |||||
2577 | return overall_type; | ||||
2578 | } | ||||
2579 | |||||
2580 | static enum surface_update_type check_update_surfaces_for_stream( | ||||
2581 | struct dc *dc, | ||||
2582 | struct dc_surface_update *updates, | ||||
2583 | int surface_count, | ||||
2584 | struct dc_stream_update *stream_update, | ||||
2585 | const struct dc_stream_status *stream_status) | ||||
2586 | { | ||||
2587 | int i; | ||||
2588 | enum surface_update_type overall_type = UPDATE_TYPE_FAST; | ||||
2589 | |||||
2590 | if (dc->idle_optimizations_allowed) | ||||
2591 | overall_type = UPDATE_TYPE_FULL; | ||||
2592 | |||||
2593 | if (stream_status == NULL((void *)0) || stream_status->plane_count != surface_count) | ||||
2594 | overall_type = UPDATE_TYPE_FULL; | ||||
2595 | |||||
2596 | if (stream_update && stream_update->pending_test_pattern) { | ||||
2597 | overall_type = UPDATE_TYPE_FULL; | ||||
2598 | } | ||||
2599 | |||||
2600 | /* some stream updates require passive update */ | ||||
2601 | if (stream_update) { | ||||
2602 | union stream_update_flags *su_flags = &stream_update->stream->update_flags; | ||||
2603 | |||||
2604 | if ((stream_update->src.height != 0 && stream_update->src.width != 0) || | ||||
2605 | (stream_update->dst.height != 0 && stream_update->dst.width != 0) || | ||||
2606 | stream_update->integer_scaling_update) | ||||
2607 | su_flags->bits.scaling = 1; | ||||
2608 | |||||
2609 | if (stream_update->out_transfer_func) | ||||
2610 | su_flags->bits.out_tf = 1; | ||||
2611 | |||||
2612 | if (stream_update->abm_level) | ||||
2613 | su_flags->bits.abm_level = 1; | ||||
2614 | |||||
2615 | if (stream_update->dpms_off) | ||||
2616 | su_flags->bits.dpms_off = 1; | ||||
2617 | |||||
2618 | if (stream_update->gamut_remap) | ||||
2619 | su_flags->bits.gamut_remap = 1; | ||||
2620 | |||||
2621 | if (stream_update->wb_update) | ||||
2622 | su_flags->bits.wb_update = 1; | ||||
2623 | |||||
2624 | if (stream_update->dsc_config) | ||||
2625 | su_flags->bits.dsc_changed = 1; | ||||
2626 | |||||
2627 | if (stream_update->mst_bw_update) | ||||
2628 | su_flags->bits.mst_bw = 1; | ||||
2629 | |||||
2630 | if (stream_update->stream && stream_update->stream->freesync_on_desktop && | ||||
2631 | (stream_update->vrr_infopacket || stream_update->allow_freesync || | ||||
2632 | stream_update->vrr_active_variable)) | ||||
2633 | su_flags->bits.fams_changed = 1; | ||||
2634 | |||||
2635 | if (su_flags->raw != 0) | ||||
2636 | overall_type = UPDATE_TYPE_FULL; | ||||
2637 | |||||
2638 | if (stream_update->output_csc_transform || stream_update->output_color_space) | ||||
2639 | su_flags->bits.out_csc = 1; | ||||
2640 | } | ||||
2641 | |||||
2642 | for (i = 0 ; i < surface_count; i++) { | ||||
2643 | enum surface_update_type type = | ||||
2644 | det_surface_update(dc, &updates[i]); | ||||
2645 | |||||
2646 | elevate_update_type(&overall_type, type); | ||||
2647 | } | ||||
2648 | |||||
2649 | return overall_type; | ||||
2650 | } | ||||
2651 | |||||
2652 | static bool_Bool dc_check_is_fullscreen_video(struct rect src, struct rect clip_rect) | ||||
2653 | { | ||||
2654 | int view_height, view_width, clip_x, clip_y, clip_width, clip_height; | ||||
2655 | |||||
2656 | view_height = src.height; | ||||
2657 | view_width = src.width; | ||||
2658 | |||||
2659 | clip_x = clip_rect.x; | ||||
2660 | clip_y = clip_rect.y; | ||||
2661 | |||||
2662 | clip_width = clip_rect.width; | ||||
2663 | clip_height = clip_rect.height; | ||||
2664 | |||||
2665 | /* check for centered video accounting for off by 1 scaling truncation */ | ||||
2666 | if ((view_height - clip_y - clip_height <= clip_y + 1) && | ||||
2667 | (view_width - clip_x - clip_width <= clip_x + 1) && | ||||
2668 | (view_height - clip_y - clip_height >= clip_y - 1) && | ||||
2669 | (view_width - clip_x - clip_width >= clip_x - 1)) { | ||||
2670 | |||||
2671 | /* when OS scales up/down to letter box, it may end up | ||||
2672 | * with few blank pixels on the border due to truncating. | ||||
2673 | * Add offset margin to account for this | ||||
2674 | */ | ||||
2675 | if (clip_x <= 4 || clip_y <= 4) | ||||
2676 | return true1; | ||||
2677 | } | ||||
2678 | |||||
2679 | return false0; | ||||
2680 | } | ||||
2681 | |||||
2682 | static enum surface_update_type check_boundary_crossing_for_windowed_mpo_with_odm(struct dc *dc, | ||||
2683 | struct dc_surface_update *srf_updates, int surface_count, | ||||
2684 | enum surface_update_type update_type) | ||||
2685 | { | ||||
2686 | enum surface_update_type new_update_type = update_type; | ||||
2687 | int i, j; | ||||
2688 | struct pipe_ctx *pipe = NULL((void *)0); | ||||
2689 | struct dc_stream_state *stream; | ||||
2690 | |||||
2691 | /* Check that we are in windowed MPO with ODM | ||||
2692 | * - look for MPO pipe by scanning pipes for first pipe matching | ||||
2693 | * surface that has moved ( position change ) | ||||
2694 | * - MPO pipe will have top pipe | ||||
2695 | * - check that top pipe has ODM pointer | ||||
2696 | */ | ||||
2697 | if ((surface_count > 1) && dc->config.enable_windowed_mpo_odm) { | ||||
2698 | for (i = 0; i < surface_count; i++) { | ||||
2699 | if (srf_updates[i].surface && srf_updates[i].scaling_info | ||||
2700 | && srf_updates[i].surface->update_flags.bits.position_change) { | ||||
2701 | |||||
2702 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
2703 | if (srf_updates[i].surface == dc->current_state->res_ctx.pipe_ctx[j].plane_state) { | ||||
2704 | pipe = &dc->current_state->res_ctx.pipe_ctx[j]; | ||||
2705 | stream = pipe->stream; | ||||
2706 | break; | ||||
2707 | } | ||||
2708 | } | ||||
2709 | |||||
2710 | if (pipe && pipe->top_pipe && (get_num_odm_splits(pipe->top_pipe) > 0) && stream | ||||
2711 | && !dc_check_is_fullscreen_video(stream->src, srf_updates[i].scaling_info->clip_rect)) { | ||||
2712 | struct rect old_clip_rect, new_clip_rect; | ||||
2713 | bool_Bool old_clip_rect_left, old_clip_rect_right, old_clip_rect_middle; | ||||
2714 | bool_Bool new_clip_rect_left, new_clip_rect_right, new_clip_rect_middle; | ||||
2715 | |||||
2716 | old_clip_rect = srf_updates[i].surface->clip_rect; | ||||
2717 | new_clip_rect = srf_updates[i].scaling_info->clip_rect; | ||||
2718 | |||||
2719 | old_clip_rect_left = ((old_clip_rect.x + old_clip_rect.width) <= (stream->src.x + (stream->src.width/2))); | ||||
2720 | old_clip_rect_right = (old_clip_rect.x >= (stream->src.x + (stream->src.width/2))); | ||||
2721 | old_clip_rect_middle = !old_clip_rect_left && !old_clip_rect_right; | ||||
2722 | |||||
2723 | new_clip_rect_left = ((new_clip_rect.x + new_clip_rect.width) <= (stream->src.x + (stream->src.width/2))); | ||||
2724 | new_clip_rect_right = (new_clip_rect.x >= (stream->src.x + (stream->src.width/2))); | ||||
2725 | new_clip_rect_middle = !new_clip_rect_left && !new_clip_rect_right; | ||||
2726 | |||||
2727 | if (old_clip_rect_left && new_clip_rect_middle) | ||||
2728 | new_update_type = UPDATE_TYPE_FULL; | ||||
2729 | else if (old_clip_rect_middle && new_clip_rect_right) | ||||
2730 | new_update_type = UPDATE_TYPE_FULL; | ||||
2731 | else if (old_clip_rect_right && new_clip_rect_middle) | ||||
2732 | new_update_type = UPDATE_TYPE_FULL; | ||||
2733 | else if (old_clip_rect_middle && new_clip_rect_left) | ||||
2734 | new_update_type = UPDATE_TYPE_FULL; | ||||
2735 | } | ||||
2736 | } | ||||
2737 | } | ||||
2738 | } | ||||
2739 | return new_update_type; | ||||
2740 | } | ||||
2741 | |||||
2742 | /* | ||||
2743 | * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full) | ||||
2744 | * | ||||
2745 | * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types | ||||
2746 | */ | ||||
2747 | enum surface_update_type dc_check_update_surfaces_for_stream( | ||||
2748 | struct dc *dc, | ||||
2749 | struct dc_surface_update *updates, | ||||
2750 | int surface_count, | ||||
2751 | struct dc_stream_update *stream_update, | ||||
2752 | const struct dc_stream_status *stream_status) | ||||
2753 | { | ||||
2754 | int i; | ||||
2755 | enum surface_update_type type; | ||||
2756 | |||||
2757 | if (stream_update) | ||||
2758 | stream_update->stream->update_flags.raw = 0; | ||||
2759 | for (i = 0; i < surface_count; i++) | ||||
2760 | updates[i].surface->update_flags.raw = 0; | ||||
2761 | |||||
2762 | type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status); | ||||
2763 | if (type == UPDATE_TYPE_FULL) { | ||||
2764 | if (stream_update) { | ||||
2765 | uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed; | ||||
2766 | stream_update->stream->update_flags.raw = 0xFFFFFFFF; | ||||
2767 | stream_update->stream->update_flags.bits.dsc_changed = dsc_changed; | ||||
2768 | } | ||||
2769 | for (i = 0; i < surface_count; i++) | ||||
2770 | updates[i].surface->update_flags.raw = 0xFFFFFFFF; | ||||
2771 | } | ||||
2772 | |||||
2773 | if (type == UPDATE_TYPE_MED) | ||||
2774 | type = check_boundary_crossing_for_windowed_mpo_with_odm(dc, | ||||
2775 | updates, surface_count, type); | ||||
2776 | |||||
2777 | if (type == UPDATE_TYPE_FAST) { | ||||
2778 | // If there's an available clock comparator, we use that. | ||||
2779 | if (dc->clk_mgr->funcs->are_clock_states_equal) { | ||||
2780 | if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk)) | ||||
2781 | dc->optimized_required = true1; | ||||
2782 | // Else we fallback to mem compare. | ||||
2783 | } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support))__builtin_memcmp((&dc->current_state->bw_ctx.bw.dcn .clk), (&dc->clk_mgr->clks), (__builtin_offsetof(struct dc_clocks, prev_p_state_change_support))) != 0) { | ||||
2784 | dc->optimized_required = true1; | ||||
2785 | } | ||||
2786 | |||||
2787 | dc->optimized_required |= dc->wm_optimized_required; | ||||
2788 | } | ||||
2789 | |||||
2790 | return type; | ||||
2791 | } | ||||
2792 | |||||
2793 | static struct dc_stream_status *stream_get_status( | ||||
2794 | struct dc_state *ctx, | ||||
2795 | struct dc_stream_state *stream) | ||||
2796 | { | ||||
2797 | uint8_t i; | ||||
2798 | |||||
2799 | for (i = 0; i < ctx->stream_count; i++) { | ||||
2800 | if (stream == ctx->streams[i]) { | ||||
2801 | return &ctx->stream_status[i]; | ||||
2802 | } | ||||
2803 | } | ||||
2804 | |||||
2805 | return NULL((void *)0); | ||||
2806 | } | ||||
2807 | |||||
2808 | static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; | ||||
2809 | |||||
2810 | static void copy_surface_update_to_plane( | ||||
2811 | struct dc_plane_state *surface, | ||||
2812 | struct dc_surface_update *srf_update) | ||||
2813 | { | ||||
2814 | if (srf_update->flip_addr) { | ||||
2815 | surface->address = srf_update->flip_addr->address; | ||||
2816 | surface->flip_immediate = | ||||
2817 | srf_update->flip_addr->flip_immediate; | ||||
2818 | surface->time.time_elapsed_in_us[surface->time.index] = | ||||
2819 | srf_update->flip_addr->flip_timestamp_in_us - | ||||
2820 | surface->time.prev_update_time_in_us; | ||||
2821 | surface->time.prev_update_time_in_us = | ||||
2822 | srf_update->flip_addr->flip_timestamp_in_us; | ||||
2823 | surface->time.index++; | ||||
2824 | if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX10) | ||||
2825 | surface->time.index = 0; | ||||
2826 | |||||
2827 | surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips; | ||||
2828 | } | ||||
2829 | |||||
2830 | if (srf_update->scaling_info) { | ||||
2831 | surface->scaling_quality = | ||||
2832 | srf_update->scaling_info->scaling_quality; | ||||
2833 | surface->dst_rect = | ||||
2834 | srf_update->scaling_info->dst_rect; | ||||
2835 | surface->src_rect = | ||||
2836 | srf_update->scaling_info->src_rect; | ||||
2837 | surface->clip_rect = | ||||
2838 | srf_update->scaling_info->clip_rect; | ||||
2839 | } | ||||
2840 | |||||
2841 | if (srf_update->plane_info) { | ||||
2842 | surface->color_space = | ||||
2843 | srf_update->plane_info->color_space; | ||||
2844 | surface->format = | ||||
2845 | srf_update->plane_info->format; | ||||
2846 | surface->plane_size = | ||||
2847 | srf_update->plane_info->plane_size; | ||||
2848 | surface->rotation = | ||||
2849 | srf_update->plane_info->rotation; | ||||
2850 | surface->horizontal_mirror = | ||||
2851 | srf_update->plane_info->horizontal_mirror; | ||||
2852 | surface->stereo_format = | ||||
2853 | srf_update->plane_info->stereo_format; | ||||
2854 | surface->tiling_info = | ||||
2855 | srf_update->plane_info->tiling_info; | ||||
2856 | surface->visible = | ||||
2857 | srf_update->plane_info->visible; | ||||
2858 | surface->per_pixel_alpha = | ||||
2859 | srf_update->plane_info->per_pixel_alpha; | ||||
2860 | surface->global_alpha = | ||||
2861 | srf_update->plane_info->global_alpha; | ||||
2862 | surface->global_alpha_value = | ||||
2863 | srf_update->plane_info->global_alpha_value; | ||||
2864 | surface->dcc = | ||||
2865 | srf_update->plane_info->dcc; | ||||
2866 | surface->layer_index = | ||||
2867 | srf_update->plane_info->layer_index; | ||||
2868 | } | ||||
2869 | |||||
2870 | if (srf_update->gamma && | ||||
2871 | (surface->gamma_correction != | ||||
2872 | srf_update->gamma)) { | ||||
2873 | memcpy(&surface->gamma_correction->entries,__builtin_memcpy((&surface->gamma_correction->entries ), (&srf_update->gamma->entries), (sizeof(struct dc_gamma_entries ))) | ||||
2874 | &srf_update->gamma->entries,__builtin_memcpy((&surface->gamma_correction->entries ), (&srf_update->gamma->entries), (sizeof(struct dc_gamma_entries ))) | ||||
2875 | sizeof(struct dc_gamma_entries))__builtin_memcpy((&surface->gamma_correction->entries ), (&srf_update->gamma->entries), (sizeof(struct dc_gamma_entries ))); | ||||
2876 | surface->gamma_correction->is_identity = | ||||
2877 | srf_update->gamma->is_identity; | ||||
2878 | surface->gamma_correction->num_entries = | ||||
2879 | srf_update->gamma->num_entries; | ||||
2880 | surface->gamma_correction->type = | ||||
2881 | srf_update->gamma->type; | ||||
2882 | } | ||||
2883 | |||||
2884 | if (srf_update->in_transfer_func && | ||||
2885 | (surface->in_transfer_func != | ||||
2886 | srf_update->in_transfer_func)) { | ||||
2887 | surface->in_transfer_func->sdr_ref_white_level = | ||||
2888 | srf_update->in_transfer_func->sdr_ref_white_level; | ||||
2889 | surface->in_transfer_func->tf = | ||||
2890 | srf_update->in_transfer_func->tf; | ||||
2891 | surface->in_transfer_func->type = | ||||
2892 | srf_update->in_transfer_func->type; | ||||
2893 | memcpy(&surface->in_transfer_func->tf_pts,__builtin_memcpy((&surface->in_transfer_func->tf_pts ), (&srf_update->in_transfer_func->tf_pts), (sizeof (struct dc_transfer_func_distributed_points))) | ||||
2894 | &srf_update->in_transfer_func->tf_pts,__builtin_memcpy((&surface->in_transfer_func->tf_pts ), (&srf_update->in_transfer_func->tf_pts), (sizeof (struct dc_transfer_func_distributed_points))) | ||||
2895 | sizeof(struct dc_transfer_func_distributed_points))__builtin_memcpy((&surface->in_transfer_func->tf_pts ), (&srf_update->in_transfer_func->tf_pts), (sizeof (struct dc_transfer_func_distributed_points))); | ||||
2896 | } | ||||
2897 | |||||
2898 | if (srf_update->func_shaper && | ||||
2899 | (surface->in_shaper_func != | ||||
2900 | srf_update->func_shaper)) | ||||
2901 | memcpy(surface->in_shaper_func, srf_update->func_shaper,__builtin_memcpy((surface->in_shaper_func), (srf_update-> func_shaper), (sizeof(*surface->in_shaper_func))) | ||||
2902 | sizeof(*surface->in_shaper_func))__builtin_memcpy((surface->in_shaper_func), (srf_update-> func_shaper), (sizeof(*surface->in_shaper_func))); | ||||
2903 | |||||
2904 | if (srf_update->lut3d_func && | ||||
2905 | (surface->lut3d_func != | ||||
2906 | srf_update->lut3d_func)) | ||||
2907 | memcpy(surface->lut3d_func, srf_update->lut3d_func,__builtin_memcpy((surface->lut3d_func), (srf_update->lut3d_func ), (sizeof(*surface->lut3d_func))) | ||||
2908 | sizeof(*surface->lut3d_func))__builtin_memcpy((surface->lut3d_func), (srf_update->lut3d_func ), (sizeof(*surface->lut3d_func))); | ||||
2909 | |||||
2910 | if (srf_update->hdr_mult.value) | ||||
2911 | surface->hdr_mult = | ||||
2912 | srf_update->hdr_mult; | ||||
2913 | |||||
2914 | if (srf_update->blend_tf && | ||||
2915 | (surface->blend_tf != | ||||
2916 | srf_update->blend_tf)) | ||||
2917 | memcpy(surface->blend_tf, srf_update->blend_tf,__builtin_memcpy((surface->blend_tf), (srf_update->blend_tf ), (sizeof(*surface->blend_tf))) | ||||
2918 | sizeof(*surface->blend_tf))__builtin_memcpy((surface->blend_tf), (srf_update->blend_tf ), (sizeof(*surface->blend_tf))); | ||||
2919 | |||||
2920 | if (srf_update->input_csc_color_matrix) | ||||
2921 | surface->input_csc_color_matrix = | ||||
2922 | *srf_update->input_csc_color_matrix; | ||||
2923 | |||||
2924 | if (srf_update->coeff_reduction_factor) | ||||
2925 | surface->coeff_reduction_factor = | ||||
2926 | *srf_update->coeff_reduction_factor; | ||||
2927 | |||||
2928 | if (srf_update->gamut_remap_matrix) | ||||
2929 | surface->gamut_remap_matrix = | ||||
2930 | *srf_update->gamut_remap_matrix; | ||||
2931 | } | ||||
2932 | |||||
2933 | static void copy_stream_update_to_stream(struct dc *dc, | ||||
2934 | struct dc_state *context, | ||||
2935 | struct dc_stream_state *stream, | ||||
2936 | struct dc_stream_update *update) | ||||
2937 | { | ||||
2938 | struct dc_context *dc_ctx = dc->ctx; | ||||
2939 | |||||
2940 | if (update == NULL((void *)0) || stream == NULL((void *)0)) | ||||
2941 | return; | ||||
2942 | |||||
2943 | if (update->src.height && update->src.width) | ||||
2944 | stream->src = update->src; | ||||
2945 | |||||
2946 | if (update->dst.height && update->dst.width) | ||||
2947 | stream->dst = update->dst; | ||||
2948 | |||||
2949 | if (update->out_transfer_func && | ||||
2950 | stream->out_transfer_func != update->out_transfer_func) { | ||||
2951 | stream->out_transfer_func->sdr_ref_white_level = | ||||
2952 | update->out_transfer_func->sdr_ref_white_level; | ||||
2953 | stream->out_transfer_func->tf = update->out_transfer_func->tf; | ||||
2954 | stream->out_transfer_func->type = | ||||
2955 | update->out_transfer_func->type; | ||||
2956 | memcpy(&stream->out_transfer_func->tf_pts,__builtin_memcpy((&stream->out_transfer_func->tf_pts ), (&update->out_transfer_func->tf_pts), (sizeof(struct dc_transfer_func_distributed_points))) | ||||
2957 | &update->out_transfer_func->tf_pts,__builtin_memcpy((&stream->out_transfer_func->tf_pts ), (&update->out_transfer_func->tf_pts), (sizeof(struct dc_transfer_func_distributed_points))) | ||||
2958 | sizeof(struct dc_transfer_func_distributed_points))__builtin_memcpy((&stream->out_transfer_func->tf_pts ), (&update->out_transfer_func->tf_pts), (sizeof(struct dc_transfer_func_distributed_points))); | ||||
2959 | } | ||||
2960 | |||||
2961 | if (update->hdr_static_metadata) | ||||
2962 | stream->hdr_static_metadata = *update->hdr_static_metadata; | ||||
2963 | |||||
2964 | if (update->abm_level) | ||||
2965 | stream->abm_level = *update->abm_level; | ||||
2966 | |||||
2967 | if (update->periodic_interrupt) | ||||
2968 | stream->periodic_interrupt = *update->periodic_interrupt; | ||||
2969 | |||||
2970 | if (update->gamut_remap) | ||||
2971 | stream->gamut_remap_matrix = *update->gamut_remap; | ||||
2972 | |||||
2973 | /* Note: this being updated after mode set is currently not a use case | ||||
2974 | * however if it arises OCSC would need to be reprogrammed at the | ||||
2975 | * minimum | ||||
2976 | */ | ||||
2977 | if (update->output_color_space) | ||||
2978 | stream->output_color_space = *update->output_color_space; | ||||
2979 | |||||
2980 | if (update->output_csc_transform) | ||||
2981 | stream->csc_color_matrix = *update->output_csc_transform; | ||||
2982 | |||||
2983 | if (update->vrr_infopacket) | ||||
2984 | stream->vrr_infopacket = *update->vrr_infopacket; | ||||
2985 | |||||
2986 | if (update->allow_freesync) | ||||
2987 | stream->allow_freesync = *update->allow_freesync; | ||||
2988 | |||||
2989 | if (update->vrr_active_variable) | ||||
2990 | stream->vrr_active_variable = *update->vrr_active_variable; | ||||
2991 | |||||
2992 | if (update->crtc_timing_adjust) | ||||
2993 | stream->adjust = *update->crtc_timing_adjust; | ||||
2994 | |||||
2995 | if (update->dpms_off) | ||||
2996 | stream->dpms_off = *update->dpms_off; | ||||
2997 | |||||
2998 | if (update->hfvsif_infopacket) | ||||
2999 | stream->hfvsif_infopacket = *update->hfvsif_infopacket; | ||||
3000 | |||||
3001 | if (update->vtem_infopacket) | ||||
3002 | stream->vtem_infopacket = *update->vtem_infopacket; | ||||
3003 | |||||
3004 | if (update->vsc_infopacket) | ||||
3005 | stream->vsc_infopacket = *update->vsc_infopacket; | ||||
3006 | |||||
3007 | if (update->vsp_infopacket) | ||||
3008 | stream->vsp_infopacket = *update->vsp_infopacket; | ||||
3009 | |||||
3010 | if (update->dither_option) | ||||
3011 | stream->dither_option = *update->dither_option; | ||||
3012 | |||||
3013 | if (update->pending_test_pattern) | ||||
3014 | stream->test_pattern = *update->pending_test_pattern; | ||||
3015 | /* update current stream with writeback info */ | ||||
3016 | if (update->wb_update) { | ||||
3017 | int i; | ||||
3018 | |||||
3019 | stream->num_wb_info = update->wb_update->num_wb_info; | ||||
3020 | ASSERT(stream->num_wb_info <= MAX_DWB_PIPES)do { if (({ static int __warned; int __ret = !!(!(stream-> num_wb_info <= 1)); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(stream->num_wb_info <= 1)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c", 3020); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
3021 | for (i = 0; i < stream->num_wb_info; i++) | ||||
3022 | stream->writeback_info[i] = | ||||
3023 | update->wb_update->writeback_info[i]; | ||||
3024 | } | ||||
3025 | if (update->dsc_config) { | ||||
3026 | struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; | ||||
3027 | uint32_t old_dsc_enabled = stream->timing.flags.DSC; | ||||
3028 | uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 && | ||||
3029 | update->dsc_config->num_slices_v != 0); | ||||
3030 | |||||
3031 | /* Use temporarry context for validating new DSC config */ | ||||
3032 | struct dc_state *dsc_validate_context = dc_create_state(dc); | ||||
3033 | |||||
3034 | if (dsc_validate_context) { | ||||
3035 | dc_resource_state_copy_construct(dc->current_state, dsc_validate_context); | ||||
3036 | |||||
3037 | stream->timing.dsc_cfg = *update->dsc_config; | ||||
3038 | stream->timing.flags.DSC = enable_dsc; | ||||
3039 | if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true1)) { | ||||
3040 | stream->timing.dsc_cfg = old_dsc_cfg; | ||||
3041 | stream->timing.flags.DSC = old_dsc_enabled; | ||||
3042 | update->dsc_config = NULL((void *)0); | ||||
3043 | } | ||||
3044 | |||||
3045 | dc_release_state(dsc_validate_context); | ||||
3046 | } else { | ||||
3047 | DC_ERROR("Failed to allocate new validate context for DSC change\n")do { (void)(dc_ctx); __drm_err("Failed to allocate new validate context for DSC change\n" ); } while (0); | ||||
3048 | update->dsc_config = NULL((void *)0); | ||||
3049 | } | ||||
3050 | } | ||||
3051 | } | ||||
3052 | |||||
3053 | static bool_Bool update_planes_and_stream_state(struct dc *dc, | ||||
3054 | struct dc_surface_update *srf_updates, int surface_count, | ||||
3055 | struct dc_stream_state *stream, | ||||
3056 | struct dc_stream_update *stream_update, | ||||
3057 | enum surface_update_type *new_update_type, | ||||
3058 | struct dc_state **new_context) | ||||
3059 | { | ||||
3060 | struct dc_state *context; | ||||
3061 | int i, j; | ||||
3062 | enum surface_update_type update_type; | ||||
3063 | const struct dc_stream_status *stream_status; | ||||
3064 | struct dc_context *dc_ctx = dc->ctx; | ||||
3065 | |||||
3066 | stream_status = dc_stream_get_status(stream); | ||||
3067 | |||||
3068 | if (!stream_status) { | ||||
3069 | if (surface_count) /* Only an error condition if surf_count non-zero*/ | ||||
3070 | ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c" , 3070); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
3071 | |||||
3072 | return false0; /* Cannot commit surface to stream that is not committed */ | ||||
3073 | } | ||||
3074 | |||||
3075 | context = dc->current_state; | ||||
3076 | |||||
3077 | update_type = dc_check_update_surfaces_for_stream( | ||||
3078 | dc, srf_updates, surface_count, stream_update, stream_status); | ||||
3079 | |||||
3080 | /* update current stream with the new updates */ | ||||
3081 | copy_stream_update_to_stream(dc, context, stream, stream_update); | ||||
3082 | |||||
3083 | /* do not perform surface update if surface has invalid dimensions | ||||
3084 | * (all zero) and no scaling_info is provided | ||||
3085 | */ | ||||
3086 | if (surface_count > 0) { | ||||
3087 | for (i = 0; i < surface_count; i++) { | ||||
3088 | if ((srf_updates[i].surface->src_rect.width == 0 || | ||||
3089 | srf_updates[i].surface->src_rect.height == 0 || | ||||
3090 | srf_updates[i].surface->dst_rect.width == 0 || | ||||
3091 | srf_updates[i].surface->dst_rect.height == 0) && | ||||
3092 | (!srf_updates[i].scaling_info || | ||||
3093 | srf_updates[i].scaling_info->src_rect.width == 0 || | ||||
3094 | srf_updates[i].scaling_info->src_rect.height == 0 || | ||||
3095 | srf_updates[i].scaling_info->dst_rect.width == 0 || | ||||
3096 | srf_updates[i].scaling_info->dst_rect.height == 0)) { | ||||
3097 | DC_ERROR("Invalid src/dst rects in surface update!\n")do { (void)(dc_ctx); __drm_err("Invalid src/dst rects in surface update!\n" ); } while (0); | ||||
3098 | return false0; | ||||
3099 | } | ||||
3100 | } | ||||
3101 | } | ||||
3102 | |||||
3103 | if (update_type >= update_surface_trace_level) | ||||
3104 | update_surface_trace(dc, srf_updates, surface_count); | ||||
3105 | |||||
3106 | if (update_type >= UPDATE_TYPE_FULL) { | ||||
3107 | struct dc_plane_state *new_planes[MAX_SURFACES3] = {0}; | ||||
3108 | |||||
3109 | for (i = 0; i < surface_count; i++) | ||||
3110 | new_planes[i] = srf_updates[i].surface; | ||||
3111 | |||||
3112 | /* initialize scratch memory for building context */ | ||||
3113 | context = dc_create_state(dc); | ||||
3114 | if (context == NULL((void *)0)) { | ||||
3115 | DC_ERROR("Failed to allocate new validate context!\n")do { (void)(dc_ctx); __drm_err("Failed to allocate new validate context!\n" ); } while (0); | ||||
3116 | return false0; | ||||
3117 | } | ||||
3118 | |||||
3119 | dc_resource_state_copy_construct( | ||||
3120 | dc->current_state, context); | ||||
3121 | |||||
3122 | /* For each full update, remove all existing phantom pipes first. | ||||
3123 | * Ensures that we have enough pipes for newly added MPO planes | ||||
3124 | */ | ||||
3125 | if (dc->res_pool->funcs->remove_phantom_pipes) | ||||
3126 | dc->res_pool->funcs->remove_phantom_pipes(dc, context); | ||||
3127 | |||||
3128 | /*remove old surfaces from context */ | ||||
3129 | if (!dc_rem_all_planes_for_stream(dc, stream, context)) { | ||||
3130 | |||||
3131 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 3131); do {} while (0); } while (0); | ||||
3132 | goto fail; | ||||
3133 | } | ||||
3134 | |||||
3135 | /* add surface to context */ | ||||
3136 | if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) { | ||||
3137 | |||||
3138 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 3138); do {} while (0); } while (0); | ||||
3139 | goto fail; | ||||
3140 | } | ||||
3141 | } | ||||
3142 | |||||
3143 | /* save update parameters into surface */ | ||||
3144 | for (i = 0; i < surface_count; i++) { | ||||
3145 | struct dc_plane_state *surface = srf_updates[i].surface; | ||||
3146 | |||||
3147 | copy_surface_update_to_plane(surface, &srf_updates[i]); | ||||
3148 | |||||
3149 | if (update_type >= UPDATE_TYPE_MED) { | ||||
3150 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3151 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3152 | |||||
3153 | if (pipe_ctx->plane_state != surface) | ||||
3154 | continue; | ||||
3155 | |||||
3156 | resource_build_scaling_params(pipe_ctx); | ||||
3157 | } | ||||
3158 | } | ||||
3159 | } | ||||
3160 | |||||
3161 | if (update_type == UPDATE_TYPE_FULL) { | ||||
3162 | if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false0)) { | ||||
3163 | /* For phantom pipes we remove and create a new set of phantom pipes | ||||
3164 | * for each full update (because we don't know if we'll need phantom | ||||
3165 | * pipes until after the first round of validation). However, if validation | ||||
3166 | * fails we need to keep the existing phantom pipes (because we don't update | ||||
3167 | * the dc->current_state). | ||||
3168 | * | ||||
3169 | * The phantom stream/plane refcount is decremented for validation because | ||||
3170 | * we assume it'll be removed (the free comes when the dc_state is freed), | ||||
3171 | * but if validation fails we have to increment back the refcount so it's | ||||
3172 | * consistent. | ||||
3173 | */ | ||||
3174 | if (dc->res_pool->funcs->retain_phantom_pipes) | ||||
3175 | dc->res_pool->funcs->retain_phantom_pipes(dc, dc->current_state); | ||||
3176 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 3176); do {} while (0); } while (0); | ||||
3177 | goto fail; | ||||
3178 | } | ||||
3179 | } | ||||
3180 | |||||
3181 | *new_context = context; | ||||
3182 | *new_update_type = update_type; | ||||
3183 | |||||
3184 | return true1; | ||||
3185 | |||||
3186 | fail: | ||||
3187 | dc_release_state(context); | ||||
3188 | |||||
3189 | return false0; | ||||
3190 | |||||
3191 | } | ||||
3192 | |||||
3193 | static void commit_planes_do_stream_update(struct dc *dc, | ||||
3194 | struct dc_stream_state *stream, | ||||
3195 | struct dc_stream_update *stream_update, | ||||
3196 | enum surface_update_type update_type, | ||||
3197 | struct dc_state *context) | ||||
3198 | { | ||||
3199 | int j; | ||||
3200 | |||||
3201 | // Stream updates | ||||
3202 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3203 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3204 | |||||
3205 | if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) { | ||||
3206 | |||||
3207 | if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt) | ||||
3208 | dc->hwss.setup_periodic_interrupt(dc, pipe_ctx); | ||||
3209 | |||||
3210 | if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) || | ||||
3211 | stream_update->vrr_infopacket || | ||||
3212 | stream_update->vsc_infopacket || | ||||
3213 | stream_update->vsp_infopacket || | ||||
3214 | stream_update->hfvsif_infopacket || | ||||
3215 | stream_update->vtem_infopacket) { | ||||
3216 | resource_build_info_frame(pipe_ctx); | ||||
3217 | dc->hwss.update_info_frame(pipe_ctx); | ||||
3218 | |||||
3219 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) | ||||
3220 | dp_source_sequence_trace(pipe_ctx->stream->link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); | ||||
3221 | } | ||||
3222 | |||||
3223 | if (stream_update->hdr_static_metadata && | ||||
3224 | stream->use_dynamic_meta && | ||||
3225 | dc->hwss.set_dmdata_attributes && | ||||
3226 | pipe_ctx->stream->dmdata_address.quad_part != 0) | ||||
3227 | dc->hwss.set_dmdata_attributes(pipe_ctx); | ||||
3228 | |||||
3229 | if (stream_update->gamut_remap) | ||||
3230 | dc_stream_set_gamut_remap(dc, stream); | ||||
3231 | |||||
3232 | if (stream_update->output_csc_transform) | ||||
3233 | dc_stream_program_csc_matrix(dc, stream); | ||||
3234 | |||||
3235 | if (stream_update->dither_option) { | ||||
3236 | struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; | ||||
3237 | resource_build_bit_depth_reduction_params(pipe_ctx->stream, | ||||
3238 | &pipe_ctx->stream->bit_depth_params); | ||||
3239 | pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp, | ||||
3240 | &stream->bit_depth_params, | ||||
3241 | &stream->clamping); | ||||
3242 | while (odm_pipe) { | ||||
3243 | odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp, | ||||
3244 | &stream->bit_depth_params, | ||||
3245 | &stream->clamping); | ||||
3246 | odm_pipe = odm_pipe->next_odm_pipe; | ||||
3247 | } | ||||
3248 | } | ||||
3249 | |||||
3250 | |||||
3251 | /* Full fe update*/ | ||||
3252 | if (update_type == UPDATE_TYPE_FAST) | ||||
3253 | continue; | ||||
3254 | |||||
3255 | if (stream_update->dsc_config) | ||||
3256 | dp_update_dsc_config(pipe_ctx); | ||||
3257 | |||||
3258 | if (stream_update->mst_bw_update) { | ||||
3259 | if (stream_update->mst_bw_update->is_increase) | ||||
3260 | dc_link_increase_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw); | ||||
3261 | else | ||||
3262 | dc_link_reduce_mst_payload(pipe_ctx, stream_update->mst_bw_update->mst_stream_bw); | ||||
3263 | } | ||||
3264 | |||||
3265 | if (stream_update->pending_test_pattern) { | ||||
3266 | dc_link_dp_set_test_pattern(stream->link, | ||||
3267 | stream->test_pattern.type, | ||||
3268 | stream->test_pattern.color_space, | ||||
3269 | stream->test_pattern.p_link_settings, | ||||
3270 | stream->test_pattern.p_custom_pattern, | ||||
3271 | stream->test_pattern.cust_pattern_size); | ||||
3272 | } | ||||
3273 | |||||
3274 | if (stream_update->dpms_off) { | ||||
3275 | if (*stream_update->dpms_off) { | ||||
3276 | core_link_disable_stream(pipe_ctx); | ||||
3277 | /* for dpms, keep acquired resources*/ | ||||
3278 | if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) | ||||
3279 | pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); | ||||
3280 | |||||
3281 | dc->optimized_required = true1; | ||||
3282 | |||||
3283 | } else { | ||||
3284 | if (get_seamless_boot_stream_count(context) == 0) | ||||
3285 | dc->hwss.prepare_bandwidth(dc, dc->current_state); | ||||
3286 | core_link_enable_stream(dc->current_state, pipe_ctx); | ||||
3287 | } | ||||
3288 | } | ||||
3289 | |||||
3290 | if (stream_update->abm_level && pipe_ctx->stream_res.abm) { | ||||
3291 | bool_Bool should_program_abm = true1; | ||||
3292 | |||||
3293 | // if otg funcs defined check if blanked before programming | ||||
3294 | if (pipe_ctx->stream_res.tg->funcs->is_blanked) | ||||
3295 | if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) | ||||
3296 | should_program_abm = false0; | ||||
3297 | |||||
3298 | if (should_program_abm) { | ||||
3299 | if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE255) { | ||||
3300 | dc->hwss.set_abm_immediate_disable(pipe_ctx); | ||||
3301 | } else { | ||||
3302 | pipe_ctx->stream_res.abm->funcs->set_abm_level( | ||||
3303 | pipe_ctx->stream_res.abm, stream->abm_level); | ||||
3304 | } | ||||
3305 | } | ||||
3306 | } | ||||
3307 | } | ||||
3308 | } | ||||
3309 | } | ||||
3310 | |||||
3311 | static bool_Bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream) | ||||
3312 | { | ||||
3313 | if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 | ||||
3314 | || stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) | ||||
3315 | && stream->ctx->dce_version >= DCN_VERSION_3_1) | ||||
3316 | return true1; | ||||
3317 | |||||
3318 | return false0; | ||||
3319 | } | ||||
3320 | |||||
3321 | void dc_dmub_update_dirty_rect(struct dc *dc, | ||||
3322 | int surface_count, | ||||
3323 | struct dc_stream_state *stream, | ||||
3324 | struct dc_surface_update *srf_updates, | ||||
3325 | struct dc_state *context) | ||||
3326 | { | ||||
3327 | union dmub_rb_cmd cmd; | ||||
3328 | struct dc_context *dc_ctx = dc->ctx; | ||||
3329 | struct dmub_cmd_update_dirty_rect_data *update_dirty_rect; | ||||
3330 | unsigned int i, j; | ||||
3331 | unsigned int panel_inst = 0; | ||||
3332 | |||||
3333 | if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) | ||||
3334 | return; | ||||
3335 | |||||
3336 | if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) | ||||
3337 | return; | ||||
3338 | |||||
3339 | memset(&cmd, 0x0, sizeof(cmd))__builtin_memset((&cmd), (0x0), (sizeof(cmd))); | ||||
3340 | cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT; | ||||
3341 | cmd.update_dirty_rect.header.sub_type = 0; | ||||
3342 | cmd.update_dirty_rect.header.payload_bytes = | ||||
3343 | sizeof(cmd.update_dirty_rect) - | ||||
3344 | sizeof(cmd.update_dirty_rect.header); | ||||
3345 | update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data; | ||||
3346 | for (i = 0; i < surface_count; i++) { | ||||
3347 | struct dc_plane_state *plane_state = srf_updates[i].surface; | ||||
3348 | const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr; | ||||
3349 | |||||
3350 | if (!srf_updates[i].surface || !flip_addr) | ||||
3351 | continue; | ||||
3352 | /* Do not send in immediate flip mode */ | ||||
3353 | if (srf_updates[i].surface->flip_immediate) | ||||
3354 | continue; | ||||
3355 | |||||
3356 | update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; | ||||
3357 | memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,__builtin_memcpy((update_dirty_rect->src_dirty_rects), (flip_addr ->dirty_rects), (sizeof(flip_addr->dirty_rects))) | ||||
3358 | sizeof(flip_addr->dirty_rects))__builtin_memcpy((update_dirty_rect->src_dirty_rects), (flip_addr ->dirty_rects), (sizeof(flip_addr->dirty_rects))); | ||||
3359 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3360 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3361 | |||||
3362 | if (pipe_ctx->stream != stream) | ||||
3363 | continue; | ||||
3364 | if (pipe_ctx->plane_state != plane_state) | ||||
3365 | continue; | ||||
3366 | |||||
3367 | update_dirty_rect->panel_inst = panel_inst; | ||||
3368 | update_dirty_rect->pipe_idx = j; | ||||
3369 | dc_dmub_srv_cmd_queue(dc_ctx->dmub_srv, &cmd); | ||||
3370 | dc_dmub_srv_cmd_execute(dc_ctx->dmub_srv); | ||||
3371 | } | ||||
3372 | } | ||||
3373 | } | ||||
3374 | |||||
3375 | static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state *dc_context) | ||||
3376 | { | ||||
3377 | /* | ||||
3378 | * This function calls HWSS to wait for any potentially double buffered | ||||
3379 | * operations to complete. It should be invoked as a pre-amble prior | ||||
3380 | * to full update programming before asserting any HW locks. | ||||
3381 | */ | ||||
3382 | int pipe_idx; | ||||
3383 | int opp_inst; | ||||
3384 | int opp_count = dc->res_pool->pipe_count; | ||||
3385 | struct hubp *hubp; | ||||
3386 | int mpcc_inst; | ||||
3387 | const struct pipe_ctx *pipe_ctx; | ||||
3388 | |||||
3389 | for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { | ||||
3390 | pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx]; | ||||
3391 | |||||
3392 | if (!pipe_ctx->stream) | ||||
3393 | continue; | ||||
3394 | |||||
3395 | if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) | ||||
3396 | pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); | ||||
3397 | |||||
3398 | hubp = pipe_ctx->plane_res.hubp; | ||||
3399 | if (!hubp) | ||||
3400 | continue; | ||||
3401 | |||||
3402 | mpcc_inst = hubp->inst; | ||||
3403 | // MPCC inst is equal to pipe index in practice | ||||
3404 | for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { | ||||
3405 | if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { | ||||
3406 | dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); | ||||
3407 | dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false0; | ||||
3408 | break; | ||||
3409 | } | ||||
3410 | } | ||||
3411 | } | ||||
3412 | } | ||||
3413 | |||||
3414 | static void commit_planes_for_stream(struct dc *dc, | ||||
3415 | struct dc_surface_update *srf_updates, | ||||
3416 | int surface_count, | ||||
3417 | struct dc_stream_state *stream, | ||||
3418 | struct dc_stream_update *stream_update, | ||||
3419 | enum surface_update_type update_type, | ||||
3420 | struct dc_state *context) | ||||
3421 | { | ||||
3422 | int i, j; | ||||
3423 | struct pipe_ctx *top_pipe_to_program = NULL((void *)0); | ||||
3424 | bool_Bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); | ||||
3425 | bool_Bool subvp_prev_use = false0; | ||||
3426 | |||||
3427 | // Once we apply the new subvp context to hardware it won't be in the | ||||
3428 | // dc->current_state anymore, so we have to cache it before we apply | ||||
3429 | // the new SubVP context | ||||
3430 | subvp_prev_use = false0; | ||||
3431 | dc_z10_restore(dc); | ||||
3432 | if (update_type == UPDATE_TYPE_FULL) | ||||
3433 | wait_for_outstanding_hw_updates(dc, context); | ||||
3434 | |||||
3435 | if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) { | ||||
3436 | /* Optimize seamless boot flag keeps clocks and watermarks high until | ||||
3437 | * first flip. After first flip, optimization is required to lower | ||||
3438 | * bandwidth. Important to note that it is expected UEFI will | ||||
3439 | * only light up a single display on POST, therefore we only expect | ||||
3440 | * one stream with seamless boot flag set. | ||||
3441 | */ | ||||
3442 | if (stream->apply_seamless_boot_optimization) { | ||||
3443 | stream->apply_seamless_boot_optimization = false0; | ||||
3444 | |||||
3445 | if (get_seamless_boot_stream_count(context) == 0) | ||||
3446 | dc->optimized_required = true1; | ||||
3447 | } | ||||
3448 | } | ||||
3449 | |||||
3450 | if (update_type == UPDATE_TYPE_FULL) { | ||||
3451 | dc_allow_idle_optimizations(dc, false0); | ||||
3452 | |||||
3453 | if (get_seamless_boot_stream_count(context) == 0) | ||||
3454 | dc->hwss.prepare_bandwidth(dc, context); | ||||
3455 | |||||
3456 | if (dc->hwss.update_dsc_pg) | ||||
3457 | dc->hwss.update_dsc_pg(dc, context, false0); | ||||
3458 | |||||
3459 | context_clock_trace(dc, context); | ||||
3460 | } | ||||
3461 | |||||
3462 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3463 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3464 | |||||
3465 | if (!pipe_ctx->top_pipe && | ||||
3466 | !pipe_ctx->prev_odm_pipe && | ||||
3467 | pipe_ctx->stream && | ||||
3468 | pipe_ctx->stream == stream) { | ||||
3469 | top_pipe_to_program = pipe_ctx; | ||||
3470 | } | ||||
3471 | } | ||||
3472 | |||||
3473 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
3474 | struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
3475 | |||||
3476 | // Check old context for SubVP | ||||
3477 | subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM); | ||||
3478 | if (subvp_prev_use) | ||||
3479 | break; | ||||
3480 | } | ||||
3481 | |||||
3482 | if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) { | ||||
3483 | struct pipe_ctx *mpcc_pipe; | ||||
3484 | struct pipe_ctx *odm_pipe; | ||||
3485 | |||||
3486 | for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) | ||||
3487 | for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) | ||||
3488 | odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU0xffffff; | ||||
3489 | } | ||||
3490 | |||||
3491 | if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) | ||||
3492 | if (top_pipe_to_program && | ||||
3493 | top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { | ||||
3494 | if (should_use_dmub_lock(stream->link)) { | ||||
3495 | union dmub_hw_lock_flags hw_locks = { 0 }; | ||||
3496 | struct dmub_hw_lock_inst_flags inst_flags = { 0 }; | ||||
3497 | |||||
3498 | hw_locks.bits.lock_dig = 1; | ||||
3499 | inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; | ||||
3500 | |||||
3501 | dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, | ||||
3502 | true1, | ||||
3503 | &hw_locks, | ||||
3504 | &inst_flags); | ||||
3505 | } else | ||||
3506 | top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable( | ||||
3507 | top_pipe_to_program->stream_res.tg); | ||||
3508 | } | ||||
3509 | |||||
3510 | if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { | ||||
3511 | if (dc->hwss.subvp_pipe_control_lock) | ||||
3512 | dc->hwss.subvp_pipe_control_lock(dc, context, true1, should_lock_all_pipes, NULL((void *)0), subvp_prev_use); | ||||
3513 | dc->hwss.interdependent_update_lock(dc, context, true1); | ||||
3514 | |||||
3515 | } else { | ||||
3516 | if (dc->hwss.subvp_pipe_control_lock) | ||||
3517 | dc->hwss.subvp_pipe_control_lock(dc, context, true1, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use); | ||||
3518 | /* Lock the top pipe while updating plane addrs, since freesync requires | ||||
3519 | * plane addr update event triggers to be synchronized. | ||||
3520 | * top_pipe_to_program is expected to never be NULL | ||||
3521 | */ | ||||
3522 | dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true1); | ||||
3523 | } | ||||
3524 | |||||
3525 | if (update_type != UPDATE_TYPE_FAST) { | ||||
3526 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
3527 | struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; | ||||
3528 | |||||
3529 | if ((new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) || | ||||
3530 | subvp_prev_use) { | ||||
3531 | // If old context or new context has phantom pipes, apply | ||||
3532 | // the phantom timings now. We can't change the phantom | ||||
3533 | // pipe configuration safely without driver acquiring | ||||
3534 | // the DMCUB lock first. | ||||
3535 | dc->hwss.apply_ctx_to_hw(dc, context); | ||||
3536 | break; | ||||
3537 | } | ||||
3538 | } | ||||
3539 | } | ||||
3540 | |||||
3541 | dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context); | ||||
3542 | |||||
3543 | if (update_type != UPDATE_TYPE_FAST) { | ||||
3544 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
3545 | struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; | ||||
3546 | |||||
3547 | if ((new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) || | ||||
3548 | subvp_prev_use) { | ||||
3549 | // If old context or new context has phantom pipes, apply | ||||
3550 | // the phantom timings now. We can't change the phantom | ||||
3551 | // pipe configuration safely without driver acquiring | ||||
3552 | // the DMCUB lock first. | ||||
3553 | dc->hwss.apply_ctx_to_hw(dc, context); | ||||
3554 | break; | ||||
3555 | } | ||||
3556 | } | ||||
3557 | } | ||||
3558 | |||||
3559 | // Stream updates | ||||
3560 | if (stream_update) | ||||
3561 | commit_planes_do_stream_update(dc, stream, stream_update, update_type, context); | ||||
3562 | |||||
3563 | if (surface_count == 0) { | ||||
3564 | /* | ||||
3565 | * In case of turning off screen, no need to program front end a second time. | ||||
3566 | * just return after program blank. | ||||
3567 | */ | ||||
3568 | if (dc->hwss.apply_ctx_for_surface) | ||||
3569 | dc->hwss.apply_ctx_for_surface(dc, stream, 0, context); | ||||
3570 | if (dc->hwss.program_front_end_for_ctx) | ||||
3571 | dc->hwss.program_front_end_for_ctx(dc, context); | ||||
3572 | |||||
3573 | if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { | ||||
3574 | dc->hwss.interdependent_update_lock(dc, context, false0); | ||||
3575 | } else { | ||||
3576 | dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false0); | ||||
3577 | } | ||||
3578 | dc->hwss.post_unlock_program_front_end(dc, context); | ||||
3579 | |||||
3580 | if (update_type != UPDATE_TYPE_FAST) | ||||
3581 | if (dc->hwss.commit_subvp_config) | ||||
3582 | dc->hwss.commit_subvp_config(dc, context); | ||||
3583 | |||||
3584 | /* Since phantom pipe programming is moved to post_unlock_program_front_end, | ||||
3585 | * move the SubVP lock to after the phantom pipes have been setup | ||||
3586 | */ | ||||
3587 | if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { | ||||
3588 | if (dc->hwss.subvp_pipe_control_lock) | ||||
3589 | dc->hwss.subvp_pipe_control_lock(dc, context, false0, should_lock_all_pipes, NULL((void *)0), subvp_prev_use); | ||||
3590 | } else { | ||||
3591 | if (dc->hwss.subvp_pipe_control_lock) | ||||
3592 | dc->hwss.subvp_pipe_control_lock(dc, context, false0, should_lock_all_pipes, NULL((void *)0), subvp_prev_use); | ||||
3593 | } | ||||
3594 | |||||
3595 | return; | ||||
3596 | } | ||||
3597 | |||||
3598 | if (!IS_DIAG_DC(dc->ctx->dce_environment)((dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) || ( dc->ctx->dce_environment == DCE_ENV_DIAG))) { | ||||
3599 | for (i = 0; i < surface_count; i++) { | ||||
3600 | struct dc_plane_state *plane_state = srf_updates[i].surface; | ||||
3601 | /*set logical flag for lock/unlock use*/ | ||||
3602 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3603 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3604 | if (!pipe_ctx->plane_state) | ||||
3605 | continue; | ||||
3606 | if (should_update_pipe_for_plane(context, pipe_ctx, plane_state)) | ||||
3607 | continue; | ||||
3608 | pipe_ctx->plane_state->triplebuffer_flips = false0; | ||||
3609 | if (update_type == UPDATE_TYPE_FAST && | ||||
3610 | dc->hwss.program_triplebuffer != NULL((void *)0) && | ||||
3611 | !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { | ||||
3612 | /*triple buffer for VUpdate only*/ | ||||
3613 | pipe_ctx->plane_state->triplebuffer_flips = true1; | ||||
3614 | } | ||||
3615 | } | ||||
3616 | if (update_type == UPDATE_TYPE_FULL) { | ||||
3617 | /* force vsync flip when reconfiguring pipes to prevent underflow */ | ||||
3618 | plane_state->flip_immediate = false0; | ||||
3619 | } | ||||
3620 | } | ||||
3621 | } | ||||
3622 | |||||
3623 | // Update Type FULL, Surface updates | ||||
3624 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3625 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3626 | |||||
3627 | if (!pipe_ctx->top_pipe && | ||||
3628 | !pipe_ctx->prev_odm_pipe && | ||||
3629 | should_update_pipe_for_stream(context, pipe_ctx, stream)) { | ||||
3630 | struct dc_stream_status *stream_status = NULL((void *)0); | ||||
3631 | |||||
3632 | if (!pipe_ctx->plane_state) | ||||
3633 | continue; | ||||
3634 | |||||
3635 | /* Full fe update*/ | ||||
3636 | if (update_type == UPDATE_TYPE_FAST) | ||||
3637 | continue; | ||||
3638 | |||||
3639 | ASSERT(!pipe_ctx->plane_state->triplebuffer_flips)do { if (({ static int __warned; int __ret = !!(!(!pipe_ctx-> plane_state->triplebuffer_flips)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(!pipe_ctx->plane_state->triplebuffer_flips)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c", 3639); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
3640 | |||||
3641 | if (dc->hwss.program_triplebuffer != NULL((void *)0) && dc->debug.enable_tri_buf) { | ||||
3642 | /*turn off triple buffer for full update*/ | ||||
3643 | dc->hwss.program_triplebuffer( | ||||
3644 | dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); | ||||
3645 | } | ||||
3646 | stream_status = | ||||
3647 | stream_get_status(context, pipe_ctx->stream); | ||||
3648 | |||||
3649 | if (dc->hwss.apply_ctx_for_surface) | ||||
3650 | dc->hwss.apply_ctx_for_surface( | ||||
3651 | dc, pipe_ctx->stream, stream_status->plane_count, context); | ||||
3652 | } | ||||
3653 | } | ||||
3654 | if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) { | ||||
3655 | dc->hwss.program_front_end_for_ctx(dc, context); | ||||
3656 | if (dc->debug.validate_dml_output) { | ||||
3657 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
3658 | struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; | ||||
3659 | if (cur_pipe->stream == NULL((void *)0)) | ||||
3660 | continue; | ||||
3661 | |||||
3662 | cur_pipe->plane_res.hubp->funcs->validate_dml_output( | ||||
3663 | cur_pipe->plane_res.hubp, dc->ctx, | ||||
3664 | &context->res_ctx.pipe_ctx[i].rq_regs, | ||||
3665 | &context->res_ctx.pipe_ctx[i].dlg_regs, | ||||
3666 | &context->res_ctx.pipe_ctx[i].ttu_regs); | ||||
3667 | } | ||||
3668 | } | ||||
3669 | } | ||||
3670 | |||||
3671 | // Update Type FAST, Surface updates | ||||
3672 | if (update_type == UPDATE_TYPE_FAST) { | ||||
3673 | if (dc->hwss.set_flip_control_gsl) | ||||
3674 | for (i = 0; i < surface_count; i++) { | ||||
3675 | struct dc_plane_state *plane_state = srf_updates[i].surface; | ||||
3676 | |||||
3677 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3678 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3679 | |||||
3680 | if (!should_update_pipe_for_stream(context, pipe_ctx, stream)) | ||||
3681 | continue; | ||||
3682 | |||||
3683 | if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) | ||||
3684 | continue; | ||||
3685 | |||||
3686 | // GSL has to be used for flip immediate | ||||
3687 | dc->hwss.set_flip_control_gsl(pipe_ctx, | ||||
3688 | pipe_ctx->plane_state->flip_immediate); | ||||
3689 | } | ||||
3690 | } | ||||
3691 | |||||
3692 | /* Perform requested Updates */ | ||||
3693 | for (i = 0; i < surface_count; i++) { | ||||
3694 | struct dc_plane_state *plane_state = srf_updates[i].surface; | ||||
3695 | |||||
3696 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3697 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3698 | |||||
3699 | if (!should_update_pipe_for_stream(context, pipe_ctx, stream)) | ||||
3700 | continue; | ||||
3701 | |||||
3702 | if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) | ||||
3703 | continue; | ||||
3704 | |||||
3705 | /*program triple buffer after lock based on flip type*/ | ||||
3706 | if (dc->hwss.program_triplebuffer != NULL((void *)0) && dc->debug.enable_tri_buf) { | ||||
3707 | /*only enable triplebuffer for fast_update*/ | ||||
3708 | dc->hwss.program_triplebuffer( | ||||
3709 | dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); | ||||
3710 | } | ||||
3711 | if (pipe_ctx->plane_state->update_flags.bits.addr_update) | ||||
3712 | dc->hwss.update_plane_addr(dc, pipe_ctx); | ||||
3713 | } | ||||
3714 | } | ||||
3715 | |||||
3716 | } | ||||
3717 | |||||
3718 | if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { | ||||
3719 | dc->hwss.interdependent_update_lock(dc, context, false0); | ||||
3720 | } else { | ||||
3721 | dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false0); | ||||
3722 | } | ||||
3723 | |||||
3724 | if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) | ||||
3725 | if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { | ||||
3726 | top_pipe_to_program->stream_res.tg->funcs->wait_for_state( | ||||
3727 | top_pipe_to_program->stream_res.tg, | ||||
3728 | CRTC_STATE_VACTIVE); | ||||
3729 | top_pipe_to_program->stream_res.tg->funcs->wait_for_state( | ||||
3730 | top_pipe_to_program->stream_res.tg, | ||||
3731 | CRTC_STATE_VBLANK); | ||||
3732 | top_pipe_to_program->stream_res.tg->funcs->wait_for_state( | ||||
3733 | top_pipe_to_program->stream_res.tg, | ||||
3734 | CRTC_STATE_VACTIVE); | ||||
3735 | |||||
3736 | if (should_use_dmub_lock(stream->link)) { | ||||
3737 | union dmub_hw_lock_flags hw_locks = { 0 }; | ||||
3738 | struct dmub_hw_lock_inst_flags inst_flags = { 0 }; | ||||
3739 | |||||
3740 | hw_locks.bits.lock_dig = 1; | ||||
3741 | inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; | ||||
3742 | |||||
3743 | dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, | ||||
3744 | false0, | ||||
3745 | &hw_locks, | ||||
3746 | &inst_flags); | ||||
3747 | } else | ||||
3748 | top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable( | ||||
3749 | top_pipe_to_program->stream_res.tg); | ||||
3750 | } | ||||
3751 | |||||
3752 | if (update_type != UPDATE_TYPE_FAST) | ||||
3753 | dc->hwss.post_unlock_program_front_end(dc, context); | ||||
3754 | if (update_type != UPDATE_TYPE_FAST) | ||||
3755 | if (dc->hwss.commit_subvp_config) | ||||
3756 | dc->hwss.commit_subvp_config(dc, context); | ||||
3757 | |||||
3758 | if (update_type != UPDATE_TYPE_FAST) | ||||
3759 | if (dc->hwss.commit_subvp_config) | ||||
3760 | dc->hwss.commit_subvp_config(dc, context); | ||||
3761 | |||||
3762 | /* Since phantom pipe programming is moved to post_unlock_program_front_end, | ||||
3763 | * move the SubVP lock to after the phantom pipes have been setup | ||||
3764 | */ | ||||
3765 | if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) { | ||||
3766 | if (dc->hwss.subvp_pipe_control_lock) | ||||
3767 | dc->hwss.subvp_pipe_control_lock(dc, context, false0, should_lock_all_pipes, NULL((void *)0), subvp_prev_use); | ||||
3768 | } else { | ||||
3769 | if (dc->hwss.subvp_pipe_control_lock) | ||||
3770 | dc->hwss.subvp_pipe_control_lock(dc, context, false0, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use); | ||||
3771 | } | ||||
3772 | |||||
3773 | // Fire manual trigger only when bottom plane is flipped | ||||
3774 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
3775 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; | ||||
3776 | |||||
3777 | if (!pipe_ctx->plane_state) | ||||
3778 | continue; | ||||
3779 | |||||
3780 | if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe || | ||||
3781 | !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) || | ||||
3782 | !pipe_ctx->plane_state->update_flags.bits.addr_update || | ||||
3783 | pipe_ctx->plane_state->skip_manual_trigger) | ||||
3784 | continue; | ||||
3785 | |||||
3786 | if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) | ||||
3787 | pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); | ||||
3788 | } | ||||
3789 | } | ||||
3790 | |||||
3791 | /* Determines if the incoming context requires a applying transition state with unnecessary | ||||
3792 | * pipe splitting and ODM disabled, due to hardware limitations. In a case where | ||||
3793 | * the OPP associated with an MPCC might change due to plane additions, this function | ||||
3794 | * returns true. | ||||
3795 | */ | ||||
3796 | static bool_Bool could_mpcc_tree_change_for_active_pipes(struct dc *dc, | ||||
3797 | struct dc_stream_state *stream, | ||||
3798 | int surface_count, | ||||
3799 | bool_Bool *is_plane_addition) | ||||
3800 | { | ||||
3801 | |||||
3802 | struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream); | ||||
3803 | bool_Bool force_minimal_pipe_splitting = false0; | ||||
3804 | |||||
3805 | *is_plane_addition = false0; | ||||
3806 | |||||
3807 | if (cur_stream_status && | ||||
3808 | dc->current_state->stream_count > 0 && | ||||
3809 | dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) { | ||||
3810 | /* determine if minimal transition is required due to MPC*/ | ||||
3811 | if (surface_count > 0) { | ||||
3812 | if (cur_stream_status->plane_count > surface_count) { | ||||
3813 | force_minimal_pipe_splitting = true1; | ||||
3814 | } else if (cur_stream_status->plane_count < surface_count) { | ||||
3815 | force_minimal_pipe_splitting = true1; | ||||
3816 | *is_plane_addition = true1; | ||||
3817 | } | ||||
3818 | } | ||||
3819 | } | ||||
3820 | |||||
3821 | if (cur_stream_status && | ||||
3822 | dc->current_state->stream_count == 1 && | ||||
3823 | dc->debug.enable_single_display_2to1_odm_policy) { | ||||
3824 | /* determine if minimal transition is required due to dynamic ODM*/ | ||||
3825 | if (surface_count > 0) { | ||||
3826 | if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) { | ||||
3827 | force_minimal_pipe_splitting = true1; | ||||
3828 | } else if (surface_count > 2 && cur_stream_status->plane_count < surface_count) { | ||||
3829 | force_minimal_pipe_splitting = true1; | ||||
3830 | *is_plane_addition = true1; | ||||
3831 | } | ||||
3832 | } | ||||
3833 | } | ||||
3834 | |||||
3835 | /* For SubVP when adding or removing planes we need to add a minimal transition | ||||
3836 | * (even when disabling all planes). Whenever disabling a phantom pipe, we | ||||
3837 | * must use the minimal transition path to disable the pipe correctly. | ||||
3838 | */ | ||||
3839 | if (cur_stream_status && stream->mall_stream_config.type == SUBVP_MAIN) { | ||||
3840 | /* determine if minimal transition is required due to SubVP*/ | ||||
3841 | if (cur_stream_status->plane_count > surface_count) { | ||||
3842 | force_minimal_pipe_splitting = true1; | ||||
3843 | } else if (cur_stream_status->plane_count < surface_count) { | ||||
3844 | force_minimal_pipe_splitting = true1; | ||||
3845 | *is_plane_addition = true1; | ||||
3846 | } | ||||
3847 | } | ||||
3848 | |||||
3849 | return force_minimal_pipe_splitting; | ||||
3850 | } | ||||
3851 | |||||
3852 | static bool_Bool commit_minimal_transition_state(struct dc *dc, | ||||
3853 | struct dc_state *transition_base_context) | ||||
3854 | { | ||||
3855 | struct dc_state *transition_context = dc_create_state(dc); | ||||
3856 | enum pipe_split_policy tmp_mpc_policy; | ||||
3857 | bool_Bool temp_dynamic_odm_policy; | ||||
3858 | bool_Bool temp_subvp_policy; | ||||
3859 | enum dc_status ret = DC_ERROR_UNEXPECTED; | ||||
3860 | unsigned int i, j; | ||||
3861 | unsigned int pipe_in_use = 0; | ||||
3862 | bool_Bool subvp_in_use = false0; | ||||
3863 | bool_Bool odm_in_use = false0; | ||||
3864 | |||||
3865 | if (!transition_context
| ||||
3866 | return false0; | ||||
3867 | |||||
3868 | /* check current pipes in use*/ | ||||
3869 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
3870 | struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i]; | ||||
3871 | |||||
3872 | if (pipe->plane_state) | ||||
3873 | pipe_in_use++; | ||||
3874 | } | ||||
3875 | |||||
3876 | /* If SubVP is enabled and we are adding or removing planes from any main subvp | ||||
3877 | * pipe, we must use the minimal transition. | ||||
3878 | */ | ||||
3879 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
3880 | struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
3881 | |||||
3882 | if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { | ||||
3883 | subvp_in_use = true1; | ||||
3884 | break; | ||||
3885 | } | ||||
3886 | } | ||||
3887 | |||||
3888 | /* If ODM is enabled and we are adding or removing planes from any ODM | ||||
3889 | * pipe, we must use the minimal transition. | ||||
3890 | */ | ||||
3891 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
3892 | struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
3893 | |||||
3894 | if (pipe->stream && pipe->next_odm_pipe) { | ||||
3895 | odm_in_use = true1; | ||||
3896 | break; | ||||
3897 | } | ||||
3898 | } | ||||
3899 | |||||
3900 | /* When the OS add a new surface if we have been used all of pipes with odm combine | ||||
3901 | * and mpc split feature, it need use commit_minimal_transition_state to transition safely. | ||||
3902 | * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need | ||||
3903 | * call it again. Otherwise return true to skip. | ||||
3904 | * | ||||
3905 | * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially | ||||
3906 | * enter/exit MPO when DCN still have enough resources. | ||||
3907 | */ | ||||
3908 | if (pipe_in_use
| ||||
3909 | dc_release_state(transition_context); | ||||
3910 | return true1; | ||||
3911 | } | ||||
3912 | |||||
3913 | if (!dc->config.is_vmin_only_asic) { | ||||
3914 | tmp_mpc_policy = dc->debug.pipe_split_policy; | ||||
3915 | dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; | ||||
3916 | } | ||||
3917 | |||||
3918 | temp_dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy; | ||||
3919 | dc->debug.enable_single_display_2to1_odm_policy = false0; | ||||
3920 | |||||
3921 | temp_subvp_policy = dc->debug.force_disable_subvp; | ||||
3922 | dc->debug.force_disable_subvp = true1; | ||||
3923 | |||||
3924 | dc_resource_state_copy_construct(transition_base_context, transition_context); | ||||
3925 | |||||
3926 | //commit minimal state | ||||
3927 | if (dc->res_pool->funcs->validate_bandwidth(dc, transition_context, false0)) { | ||||
3928 | for (i = 0; i < transition_context->stream_count; i++) { | ||||
3929 | struct dc_stream_status *stream_status = &transition_context->stream_status[i]; | ||||
3930 | |||||
3931 | for (j = 0; j < stream_status->plane_count; j++) { | ||||
3932 | struct dc_plane_state *plane_state = stream_status->plane_states[j]; | ||||
3933 | |||||
3934 | /* force vsync flip when reconfiguring pipes to prevent underflow | ||||
3935 | * and corruption | ||||
3936 | */ | ||||
3937 | plane_state->flip_immediate = false0; | ||||
3938 | } | ||||
3939 | } | ||||
3940 | |||||
3941 | ret = dc_commit_state_no_check(dc, transition_context); | ||||
3942 | } | ||||
3943 | |||||
3944 | /*always release as dc_commit_state_no_check retains in good case*/ | ||||
3945 | dc_release_state(transition_context); | ||||
3946 | |||||
3947 | /*restore previous pipe split and odm policy*/ | ||||
3948 | if (!dc->config.is_vmin_only_asic) | ||||
3949 | dc->debug.pipe_split_policy = tmp_mpc_policy; | ||||
| |||||
3950 | |||||
3951 | dc->debug.enable_single_display_2to1_odm_policy = temp_dynamic_odm_policy; | ||||
3952 | dc->debug.force_disable_subvp = temp_subvp_policy; | ||||
3953 | |||||
3954 | if (ret != DC_OK) { | ||||
3955 | /*this should never happen*/ | ||||
3956 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 3956); do {} while (0); } while (0); | ||||
3957 | return false0; | ||||
3958 | } | ||||
3959 | |||||
3960 | /*force full surface update*/ | ||||
3961 | for (i = 0; i < dc->current_state->stream_count; i++) { | ||||
3962 | for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) { | ||||
3963 | dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF; | ||||
3964 | } | ||||
3965 | } | ||||
3966 | |||||
3967 | return true1; | ||||
3968 | } | ||||
3969 | |||||
3970 | bool_Bool dc_update_planes_and_stream(struct dc *dc, | ||||
3971 | struct dc_surface_update *srf_updates, int surface_count, | ||||
3972 | struct dc_stream_state *stream, | ||||
3973 | struct dc_stream_update *stream_update) | ||||
3974 | { | ||||
3975 | struct dc_state *context; | ||||
3976 | enum surface_update_type update_type; | ||||
3977 | int i; | ||||
3978 | |||||
3979 | /* In cases where MPO and split or ODM are used transitions can | ||||
3980 | * cause underflow. Apply stream configuration with minimal pipe | ||||
3981 | * split first to avoid unsupported transitions for active pipes. | ||||
3982 | */ | ||||
3983 | bool_Bool force_minimal_pipe_splitting; | ||||
3984 | bool_Bool is_plane_addition; | ||||
3985 | |||||
3986 | force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes( | ||||
3987 | dc, | ||||
3988 | stream, | ||||
3989 | surface_count, | ||||
3990 | &is_plane_addition); | ||||
3991 | |||||
3992 | /* on plane addition, minimal state is the current one */ | ||||
3993 | if (force_minimal_pipe_splitting
| ||||
3994 | !commit_minimal_transition_state(dc, dc->current_state)) | ||||
3995 | return false0; | ||||
3996 | |||||
3997 | if (!update_planes_and_stream_state( | ||||
3998 | dc, | ||||
3999 | srf_updates, | ||||
4000 | surface_count, | ||||
4001 | stream, | ||||
4002 | stream_update, | ||||
4003 | &update_type, | ||||
4004 | &context)) | ||||
4005 | return false0; | ||||
4006 | |||||
4007 | /* on plane removal, minimal state is the new one */ | ||||
4008 | if (force_minimal_pipe_splitting && !is_plane_addition) { | ||||
4009 | if (!commit_minimal_transition_state(dc, context)) { | ||||
4010 | dc_release_state(context); | ||||
4011 | return false0; | ||||
4012 | } | ||||
4013 | |||||
4014 | update_type = UPDATE_TYPE_FULL; | ||||
4015 | } | ||||
4016 | |||||
4017 | commit_planes_for_stream( | ||||
4018 | dc, | ||||
4019 | srf_updates, | ||||
4020 | surface_count, | ||||
4021 | stream, | ||||
4022 | stream_update, | ||||
4023 | update_type, | ||||
4024 | context); | ||||
4025 | |||||
4026 | if (dc->current_state != context) { | ||||
4027 | |||||
4028 | /* Since memory free requires elevated IRQL, an interrupt | ||||
4029 | * request is generated by mem free. If this happens | ||||
4030 | * between freeing and reassigning the context, our vsync | ||||
4031 | * interrupt will call into dc and cause a memory | ||||
4032 | * corruption BSOD. Hence, we first reassign the context, | ||||
4033 | * then free the old context. | ||||
4034 | */ | ||||
4035 | |||||
4036 | struct dc_state *old = dc->current_state; | ||||
4037 | |||||
4038 | dc->current_state = context; | ||||
4039 | dc_release_state(old); | ||||
4040 | |||||
4041 | // clear any forced full updates | ||||
4042 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
4043 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | ||||
4044 | |||||
4045 | if (pipe_ctx->plane_state && pipe_ctx->stream == stream) | ||||
4046 | pipe_ctx->plane_state->force_full_update = false0; | ||||
4047 | } | ||||
4048 | } | ||||
4049 | return true1; | ||||
4050 | } | ||||
4051 | |||||
4052 | void dc_commit_updates_for_stream(struct dc *dc, | ||||
4053 | struct dc_surface_update *srf_updates, | ||||
4054 | int surface_count, | ||||
4055 | struct dc_stream_state *stream, | ||||
4056 | struct dc_stream_update *stream_update, | ||||
4057 | struct dc_state *state) | ||||
4058 | { | ||||
4059 | const struct dc_stream_status *stream_status; | ||||
4060 | enum surface_update_type update_type; | ||||
4061 | struct dc_state *context; | ||||
4062 | struct dc_context *dc_ctx = dc->ctx; | ||||
4063 | int i, j; | ||||
4064 | |||||
4065 | /* TODO: Since change commit sequence can have a huge impact, | ||||
4066 | * we decided to only enable it for DCN3x. However, as soon as | ||||
4067 | * we get more confident about this change we'll need to enable | ||||
4068 | * the new sequence for all ASICs. | ||||
4069 | */ | ||||
4070 | if (dc->ctx->dce_version >= DCN_VERSION_3_2) { | ||||
| |||||
4071 | dc_update_planes_and_stream(dc, srf_updates, | ||||
4072 | surface_count, stream, | ||||
4073 | stream_update); | ||||
4074 | return; | ||||
4075 | } | ||||
4076 | |||||
4077 | stream_status = dc_stream_get_status(stream); | ||||
4078 | context = dc->current_state; | ||||
4079 | |||||
4080 | update_type = dc_check_update_surfaces_for_stream( | ||||
4081 | dc, srf_updates, surface_count, stream_update, stream_status); | ||||
4082 | |||||
4083 | if (update_type >= update_surface_trace_level) | ||||
4084 | update_surface_trace(dc, srf_updates, surface_count); | ||||
4085 | |||||
4086 | |||||
4087 | if (update_type >= UPDATE_TYPE_FULL) { | ||||
4088 | |||||
4089 | /* initialize scratch memory for building context */ | ||||
4090 | context = dc_create_state(dc); | ||||
4091 | if (context == NULL((void *)0)) { | ||||
4092 | DC_ERROR("Failed to allocate new validate context!\n")do { (void)(dc_ctx); __drm_err("Failed to allocate new validate context!\n" ); } while (0); | ||||
4093 | return; | ||||
4094 | } | ||||
4095 | |||||
4096 | dc_resource_state_copy_construct(state, context); | ||||
4097 | |||||
4098 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
4099 | struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; | ||||
4100 | struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
4101 | |||||
4102 | if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state) | ||||
4103 | new_pipe->plane_state->force_full_update = true1; | ||||
4104 | } | ||||
4105 | } else if (update_type == UPDATE_TYPE_FAST) { | ||||
4106 | /* | ||||
4107 | * Previous frame finished and HW is ready for optimization. | ||||
4108 | */ | ||||
4109 | dc_post_update_surfaces_to_stream(dc); | ||||
4110 | } | ||||
4111 | |||||
4112 | |||||
4113 | for (i = 0; i < surface_count; i++) { | ||||
4114 | struct dc_plane_state *surface = srf_updates[i].surface; | ||||
4115 | |||||
4116 | copy_surface_update_to_plane(surface, &srf_updates[i]); | ||||
4117 | |||||
4118 | if (update_type >= UPDATE_TYPE_MED) { | ||||
4119 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||
4120 | struct pipe_ctx *pipe_ctx = | ||||
4121 | &context->res_ctx.pipe_ctx[j]; | ||||
4122 | |||||
4123 | if (pipe_ctx->plane_state != surface) | ||||
4124 | continue; | ||||
4125 | |||||
4126 | resource_build_scaling_params(pipe_ctx); | ||||
4127 | } | ||||
4128 | } | ||||
4129 | } | ||||
4130 | |||||
4131 | copy_stream_update_to_stream(dc, context, stream, stream_update); | ||||
4132 | |||||
4133 | if (update_type >= UPDATE_TYPE_FULL) { | ||||
4134 | if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false0)) { | ||||
4135 | DC_ERROR("Mode validation failed for stream update!\n")do { (void)(dc_ctx); __drm_err("Mode validation failed for stream update!\n" ); } while (0); | ||||
4136 | dc_release_state(context); | ||||
4137 | return; | ||||
4138 | } | ||||
4139 | } | ||||
4140 | |||||
4141 | TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES)for (i = 0; i < 6; ++i) { struct pipe_ctx *pipe_ctx = & dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx-> plane_state) trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx , pipe_ctx->plane_state, pipe_ctx->stream, &pipe_ctx ->plane_res, pipe_ctx->update_flags.raw); }; | ||||
4142 | |||||
4143 | commit_planes_for_stream( | ||||
4144 | dc, | ||||
4145 | srf_updates, | ||||
4146 | surface_count, | ||||
4147 | stream, | ||||
4148 | stream_update, | ||||
4149 | update_type, | ||||
4150 | context); | ||||
4151 | /*update current_State*/ | ||||
4152 | if (dc->current_state != context) { | ||||
4153 | |||||
4154 | struct dc_state *old = dc->current_state; | ||||
4155 | |||||
4156 | dc->current_state = context; | ||||
4157 | dc_release_state(old); | ||||
4158 | |||||
4159 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
4160 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | ||||
4161 | |||||
4162 | if (pipe_ctx->plane_state && pipe_ctx->stream == stream) | ||||
4163 | pipe_ctx->plane_state->force_full_update = false0; | ||||
4164 | } | ||||
4165 | } | ||||
4166 | |||||
4167 | /* Legacy optimization path for DCE. */ | ||||
4168 | if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) { | ||||
4169 | dc_post_update_surfaces_to_stream(dc); | ||||
4170 | TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce)trace_amdgpu_dm_dce_clocks_state(&context->bw_ctx.bw.dce ); | ||||
4171 | } | ||||
4172 | |||||
4173 | return; | ||||
4174 | |||||
4175 | } | ||||
4176 | |||||
4177 | uint8_t dc_get_current_stream_count(struct dc *dc) | ||||
4178 | { | ||||
4179 | return dc->current_state->stream_count; | ||||
4180 | } | ||||
4181 | |||||
4182 | struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) | ||||
4183 | { | ||||
4184 | if (i < dc->current_state->stream_count) | ||||
4185 | return dc->current_state->streams[i]; | ||||
4186 | return NULL((void *)0); | ||||
4187 | } | ||||
4188 | |||||
4189 | enum dc_irq_source dc_interrupt_to_irq_source( | ||||
4190 | struct dc *dc, | ||||
4191 | uint32_t src_id, | ||||
4192 | uint32_t ext_id) | ||||
4193 | { | ||||
4194 | return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id); | ||||
4195 | } | ||||
4196 | |||||
4197 | /* | ||||
4198 | * dc_interrupt_set() - Enable/disable an AMD hw interrupt source | ||||
4199 | */ | ||||
4200 | bool_Bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool_Bool enable) | ||||
4201 | { | ||||
4202 | |||||
4203 | if (dc == NULL((void *)0)) | ||||
4204 | return false0; | ||||
4205 | |||||
4206 | return dal_irq_service_set(dc->res_pool->irqs, src, enable); | ||||
4207 | } | ||||
4208 | |||||
4209 | void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) | ||||
4210 | { | ||||
4211 | dal_irq_service_ack(dc->res_pool->irqs, src); | ||||
4212 | } | ||||
4213 | |||||
4214 | void dc_power_down_on_boot(struct dc *dc) | ||||
4215 | { | ||||
4216 | if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW && | ||||
4217 | dc->hwss.power_down_on_boot) | ||||
4218 | dc->hwss.power_down_on_boot(dc); | ||||
4219 | } | ||||
4220 | |||||
4221 | void dc_set_power_state( | ||||
4222 | struct dc *dc, | ||||
4223 | enum dc_acpi_cm_power_state power_state) | ||||
4224 | { | ||||
4225 | struct kref refcount; | ||||
4226 | struct display_mode_lib *dml; | ||||
4227 | |||||
4228 | if (!dc->current_state) | ||||
4229 | return; | ||||
4230 | |||||
4231 | switch (power_state) { | ||||
4232 | case DC_ACPI_CM_POWER_STATE_D0: | ||||
4233 | dc_resource_state_construct(dc, dc->current_state); | ||||
4234 | |||||
4235 | dc_z10_restore(dc); | ||||
4236 | |||||
4237 | if (dc->ctx->dmub_srv) | ||||
4238 | dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv); | ||||
4239 | |||||
4240 | dc->hwss.init_hw(dc); | ||||
4241 | |||||
4242 | if (dc->hwss.init_sys_ctx != NULL((void *)0) && | ||||
4243 | dc->vm_pa_config.valid) { | ||||
4244 | dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config); | ||||
4245 | } | ||||
4246 | |||||
4247 | break; | ||||
4248 | default: | ||||
4249 | ASSERT(dc->current_state->stream_count == 0)do { if (({ static int __warned; int __ret = !!(!(dc->current_state ->stream_count == 0)); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(dc->current_state->stream_count == 0)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c", 4249); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
4250 | /* Zero out the current context so that on resume we start with | ||||
4251 | * clean state, and dc hw programming optimizations will not | ||||
4252 | * cause any trouble. | ||||
4253 | */ | ||||
4254 | dml = kzalloc(sizeof(struct display_mode_lib), | ||||
4255 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
4256 | |||||
4257 | ASSERT(dml)do { if (({ static int __warned; int __ret = !!(!(dml)); if ( __ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dml)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c" , 4257); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
4258 | if (!dml) | ||||
4259 | return; | ||||
4260 | |||||
4261 | /* Preserve refcount */ | ||||
4262 | refcount = dc->current_state->refcount; | ||||
4263 | /* Preserve display mode lib */ | ||||
4264 | memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib))__builtin_memcpy((dml), (&dc->current_state->bw_ctx .dml), (sizeof(struct display_mode_lib))); | ||||
4265 | |||||
4266 | dc_resource_state_destruct(dc->current_state); | ||||
4267 | memset(dc->current_state, 0,__builtin_memset((dc->current_state), (0), (sizeof(*dc-> current_state))) | ||||
4268 | sizeof(*dc->current_state))__builtin_memset((dc->current_state), (0), (sizeof(*dc-> current_state))); | ||||
4269 | |||||
4270 | dc->current_state->refcount = refcount; | ||||
4271 | dc->current_state->bw_ctx.dml = *dml; | ||||
4272 | |||||
4273 | kfree(dml); | ||||
4274 | |||||
4275 | break; | ||||
4276 | } | ||||
4277 | } | ||||
4278 | |||||
4279 | void dc_resume(struct dc *dc) | ||||
4280 | { | ||||
4281 | uint32_t i; | ||||
4282 | |||||
4283 | for (i = 0; i < dc->link_count; i++) | ||||
4284 | core_link_resume(dc->links[i]); | ||||
4285 | } | ||||
4286 | |||||
4287 | bool_Bool dc_is_dmcu_initialized(struct dc *dc) | ||||
4288 | { | ||||
4289 | struct dmcu *dmcu = dc->res_pool->dmcu; | ||||
4290 | |||||
4291 | if (dmcu) | ||||
4292 | return dmcu->funcs->is_dmcu_initialized(dmcu); | ||||
4293 | return false0; | ||||
4294 | } | ||||
4295 | |||||
4296 | bool_Bool dc_is_oem_i2c_device_present( | ||||
4297 | struct dc *dc, | ||||
4298 | size_t slave_address) | ||||
4299 | { | ||||
4300 | if (dc->res_pool->oem_device) | ||||
4301 | return dce_i2c_oem_device_present( | ||||
4302 | dc->res_pool, | ||||
4303 | dc->res_pool->oem_device, | ||||
4304 | slave_address); | ||||
4305 | |||||
4306 | return false0; | ||||
4307 | } | ||||
4308 | |||||
4309 | bool_Bool dc_submit_i2c( | ||||
4310 | struct dc *dc, | ||||
4311 | uint32_t link_index, | ||||
4312 | struct i2c_command *cmd) | ||||
4313 | { | ||||
4314 | |||||
4315 | struct dc_link *link = dc->links[link_index]; | ||||
4316 | struct ddc_service *ddc = link->ddc; | ||||
4317 | return dce_i2c_submit_command( | ||||
4318 | dc->res_pool, | ||||
4319 | ddc->ddc_pin, | ||||
4320 | cmd); | ||||
4321 | } | ||||
4322 | |||||
4323 | bool_Bool dc_submit_i2c_oem( | ||||
4324 | struct dc *dc, | ||||
4325 | struct i2c_command *cmd) | ||||
4326 | { | ||||
4327 | struct ddc_service *ddc = dc->res_pool->oem_device; | ||||
4328 | if (ddc) | ||||
4329 | return dce_i2c_submit_command( | ||||
4330 | dc->res_pool, | ||||
4331 | ddc->ddc_pin, | ||||
4332 | cmd); | ||||
4333 | |||||
4334 | return false0; | ||||
4335 | } | ||||
4336 | |||||
4337 | static bool_Bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) | ||||
4338 | { | ||||
4339 | if (dc_link->sink_count >= MAX_SINKS_PER_LINK4) { | ||||
4340 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 4340); do {} while (0); } while (0); | ||||
4341 | return false0; | ||||
4342 | } | ||||
4343 | |||||
4344 | dc_sink_retain(sink); | ||||
4345 | |||||
4346 | dc_link->remote_sinks[dc_link->sink_count] = sink; | ||||
4347 | dc_link->sink_count++; | ||||
4348 | |||||
4349 | return true1; | ||||
4350 | } | ||||
4351 | |||||
4352 | /* | ||||
4353 | * dc_link_add_remote_sink() - Create a sink and attach it to an existing link | ||||
4354 | * | ||||
4355 | * EDID length is in bytes | ||||
4356 | */ | ||||
4357 | struct dc_sink *dc_link_add_remote_sink( | ||||
4358 | struct dc_link *link, | ||||
4359 | const uint8_t *edid, | ||||
4360 | int len, | ||||
4361 | struct dc_sink_init_data *init_data) | ||||
4362 | { | ||||
4363 | struct dc_sink *dc_sink; | ||||
4364 | enum dc_edid_status edid_status; | ||||
4365 | |||||
4366 | if (len > DC_MAX_EDID_BUFFER_SIZE2048) { | ||||
4367 | dm_error("Max EDID buffer size breached!\n")__drm_err("Max EDID buffer size breached!\n"); | ||||
4368 | return NULL((void *)0); | ||||
4369 | } | ||||
4370 | |||||
4371 | if (!init_data) { | ||||
4372 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 4372); do {} while (0); } while (0); | ||||
4373 | return NULL((void *)0); | ||||
4374 | } | ||||
4375 | |||||
4376 | if (!init_data->link) { | ||||
4377 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 4377); do {} while (0); } while (0); | ||||
4378 | return NULL((void *)0); | ||||
4379 | } | ||||
4380 | |||||
4381 | dc_sink = dc_sink_create(init_data); | ||||
4382 | |||||
4383 | if (!dc_sink) | ||||
4384 | return NULL((void *)0); | ||||
4385 | |||||
4386 | memmove(dc_sink->dc_edid.raw_edid, edid, len)__builtin_memmove((dc_sink->dc_edid.raw_edid), (edid), (len )); | ||||
4387 | dc_sink->dc_edid.length = len; | ||||
4388 | |||||
4389 | if (!link_add_remote_sink_helper( | ||||
4390 | link, | ||||
4391 | dc_sink)) | ||||
4392 | goto fail_add_sink; | ||||
4393 | |||||
4394 | edid_status = dm_helpers_parse_edid_caps( | ||||
4395 | link, | ||||
4396 | &dc_sink->dc_edid, | ||||
4397 | &dc_sink->edid_caps); | ||||
4398 | |||||
4399 | /* | ||||
4400 | * Treat device as no EDID device if EDID | ||||
4401 | * parsing fails | ||||
4402 | */ | ||||
4403 | if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) { | ||||
4404 | dc_sink->dc_edid.length = 0; | ||||
4405 | dm_error("Bad EDID, status%d!\n", edid_status)__drm_err("Bad EDID, status%d!\n", edid_status); | ||||
4406 | } | ||||
4407 | |||||
4408 | return dc_sink; | ||||
4409 | |||||
4410 | fail_add_sink: | ||||
4411 | dc_sink_release(dc_sink); | ||||
4412 | return NULL((void *)0); | ||||
4413 | } | ||||
4414 | |||||
4415 | /* | ||||
4416 | * dc_link_remove_remote_sink() - Remove a remote sink from a dc_link | ||||
4417 | * | ||||
4418 | * Note that this just removes the struct dc_sink - it doesn't | ||||
4419 | * program hardware or alter other members of dc_link | ||||
4420 | */ | ||||
4421 | void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) | ||||
4422 | { | ||||
4423 | int i; | ||||
4424 | |||||
4425 | if (!link->sink_count) { | ||||
4426 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 4426); do {} while (0); } while (0); | ||||
4427 | return; | ||||
4428 | } | ||||
4429 | |||||
4430 | for (i = 0; i < link->sink_count; i++) { | ||||
4431 | if (link->remote_sinks[i] == sink) { | ||||
4432 | dc_sink_release(sink); | ||||
4433 | link->remote_sinks[i] = NULL((void *)0); | ||||
4434 | |||||
4435 | /* shrink array to remove empty place */ | ||||
4436 | while (i < link->sink_count - 1) { | ||||
4437 | link->remote_sinks[i] = link->remote_sinks[i+1]; | ||||
4438 | i++; | ||||
4439 | } | ||||
4440 | link->remote_sinks[i] = NULL((void *)0); | ||||
4441 | link->sink_count--; | ||||
4442 | return; | ||||
4443 | } | ||||
4444 | } | ||||
4445 | } | ||||
4446 | |||||
4447 | void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info) | ||||
4448 | { | ||||
4449 | info->displayClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz; | ||||
4450 | info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz; | ||||
4451 | info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz; | ||||
4452 | info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; | ||||
4453 | info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz; | ||||
4454 | info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz; | ||||
4455 | info->dcfClockDeepSleep = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz; | ||||
4456 | info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz; | ||||
4457 | info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz; | ||||
4458 | } | ||||
4459 | enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping) | ||||
4460 | { | ||||
4461 | if (dc->hwss.set_clock) | ||||
4462 | return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping); | ||||
4463 | return DC_ERROR_UNEXPECTED; | ||||
4464 | } | ||||
4465 | void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) | ||||
4466 | { | ||||
4467 | if (dc->hwss.get_clock) | ||||
4468 | dc->hwss.get_clock(dc, clock_type, clock_cfg); | ||||
4469 | } | ||||
4470 | |||||
4471 | /* enable/disable eDP PSR without specify stream for eDP */ | ||||
4472 | bool_Bool dc_set_psr_allow_active(struct dc *dc, bool_Bool enable) | ||||
4473 | { | ||||
4474 | int i; | ||||
4475 | bool_Bool allow_active; | ||||
4476 | |||||
4477 | for (i = 0; i < dc->current_state->stream_count ; i++) { | ||||
4478 | struct dc_link *link; | ||||
4479 | struct dc_stream_state *stream = dc->current_state->streams[i]; | ||||
4480 | |||||
4481 | link = stream->link; | ||||
4482 | if (!link) | ||||
4483 | continue; | ||||
4484 | |||||
4485 | if (link->psr_settings.psr_feature_enabled) { | ||||
4486 | if (enable && !link->psr_settings.psr_allow_active) { | ||||
4487 | allow_active = true1; | ||||
4488 | if (!dc_link_set_psr_allow_active(link, &allow_active, false0, false0, NULL((void *)0))) | ||||
4489 | return false0; | ||||
4490 | } else if (!enable && link->psr_settings.psr_allow_active) { | ||||
4491 | allow_active = false0; | ||||
4492 | if (!dc_link_set_psr_allow_active(link, &allow_active, true1, false0, NULL((void *)0))) | ||||
4493 | return false0; | ||||
4494 | } | ||||
4495 | } | ||||
4496 | } | ||||
4497 | |||||
4498 | return true1; | ||||
4499 | } | ||||
4500 | |||||
4501 | void dc_allow_idle_optimizations(struct dc *dc, bool_Bool allow) | ||||
4502 | { | ||||
4503 | if (dc->debug.disable_idle_power_optimizations) | ||||
4504 | return; | ||||
4505 | |||||
4506 | if (dc->clk_mgr != NULL((void *)0) && dc->clk_mgr->funcs->is_smu_present) | ||||
4507 | if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) | ||||
4508 | return; | ||||
4509 | |||||
4510 | if (allow == dc->idle_optimizations_allowed) | ||||
4511 | return; | ||||
4512 | |||||
4513 | if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow)) | ||||
4514 | dc->idle_optimizations_allowed = allow; | ||||
4515 | } | ||||
4516 | |||||
4517 | /* set min and max memory clock to lowest and highest DPM level, respectively */ | ||||
4518 | void dc_unlock_memory_clock_frequency(struct dc *dc) | ||||
4519 | { | ||||
4520 | if (dc->clk_mgr->funcs->set_hard_min_memclk) | ||||
4521 | dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false0); | ||||
4522 | |||||
4523 | if (dc->clk_mgr->funcs->set_hard_max_memclk) | ||||
4524 | dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); | ||||
4525 | } | ||||
4526 | |||||
4527 | /* set min memory clock to the min required for current mode, max to maxDPM */ | ||||
4528 | void dc_lock_memory_clock_frequency(struct dc *dc) | ||||
4529 | { | ||||
4530 | if (dc->clk_mgr->funcs->get_memclk_states_from_smu) | ||||
4531 | dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr); | ||||
4532 | |||||
4533 | if (dc->clk_mgr->funcs->set_hard_min_memclk) | ||||
4534 | dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true1); | ||||
4535 | |||||
4536 | if (dc->clk_mgr->funcs->set_hard_max_memclk) | ||||
4537 | dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); | ||||
4538 | } | ||||
4539 | |||||
4540 | static void blank_and_force_memclk(struct dc *dc, bool_Bool apply, unsigned int memclk_mhz) | ||||
4541 | { | ||||
4542 | struct dc_state *context = dc->current_state; | ||||
4543 | struct hubp *hubp; | ||||
4544 | struct pipe_ctx *pipe; | ||||
4545 | int i; | ||||
4546 | |||||
4547 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
4548 | pipe = &context->res_ctx.pipe_ctx[i]; | ||||
4549 | |||||
4550 | if (pipe->stream != NULL((void *)0)) { | ||||
4551 | dc->hwss.disable_pixel_data(dc, pipe, true1); | ||||
4552 | |||||
4553 | // wait for double buffer | ||||
4554 | pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE); | ||||
4555 | pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); | ||||
4556 | pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE); | ||||
4557 | |||||
4558 | hubp = pipe->plane_res.hubp; | ||||
4559 | hubp->funcs->set_blank_regs(hubp, true1); | ||||
4560 | } | ||||
4561 | } | ||||
4562 | |||||
4563 | dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz); | ||||
4564 | dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz); | ||||
4565 | |||||
4566 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
4567 | pipe = &context->res_ctx.pipe_ctx[i]; | ||||
4568 | |||||
4569 | if (pipe->stream != NULL((void *)0)) { | ||||
4570 | dc->hwss.disable_pixel_data(dc, pipe, false0); | ||||
4571 | |||||
4572 | hubp = pipe->plane_res.hubp; | ||||
4573 | hubp->funcs->set_blank_regs(hubp, false0); | ||||
4574 | } | ||||
4575 | } | ||||
4576 | } | ||||
4577 | |||||
4578 | |||||
4579 | /** | ||||
4580 | * dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode | ||||
4581 | * @dc: pointer to dc of the dm calling this | ||||
4582 | * @enable: True = transition to DC mode, false = transition back to AC mode | ||||
4583 | * | ||||
4584 | * Some SoCs define additional clock limits when in DC mode, DM should | ||||
4585 | * invoke this function when the platform undergoes a power source transition | ||||
4586 | * so DC can apply/unapply the limit. This interface may be disruptive to | ||||
4587 | * the onscreen content. | ||||
4588 | * | ||||
4589 | * Context: Triggered by OS through DM interface, or manually by escape calls. | ||||
4590 | * Need to hold a dclock when doing so. | ||||
4591 | * | ||||
4592 | * Return: none (void function) | ||||
4593 | * | ||||
4594 | */ | ||||
4595 | void dc_enable_dcmode_clk_limit(struct dc *dc, bool_Bool enable) | ||||
4596 | { | ||||
4597 | uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; | ||||
4598 | unsigned int softMax, maxDPM, funcMin; | ||||
4599 | bool_Bool p_state_change_support; | ||||
4600 | |||||
4601 | if (!ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)((hw_internal_rev >= NV_BEIGE_GOBY_P_A0) && (hw_internal_rev < NV_UNKNOWN))) | ||||
4602 | return; | ||||
4603 | |||||
4604 | softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk; | ||||
4605 | maxDPM = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz; | ||||
4606 | funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000; | ||||
4607 | p_state_change_support = dc->clk_mgr->clks.p_state_change_support; | ||||
4608 | |||||
4609 | if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) { | ||||
4610 | if (p_state_change_support) { | ||||
4611 | if (funcMin <= softMax) | ||||
4612 | dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax); | ||||
4613 | // else: No-Op | ||||
4614 | } else { | ||||
4615 | if (funcMin <= softMax) | ||||
4616 | blank_and_force_memclk(dc, true1, softMax); | ||||
4617 | // else: No-Op | ||||
4618 | } | ||||
4619 | } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) { | ||||
4620 | if (p_state_change_support) { | ||||
4621 | if (funcMin <= softMax) | ||||
4622 | dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM); | ||||
4623 | // else: No-Op | ||||
4624 | } else { | ||||
4625 | if (funcMin <= softMax) | ||||
4626 | blank_and_force_memclk(dc, true1, maxDPM); | ||||
4627 | // else: No-Op | ||||
4628 | } | ||||
4629 | } | ||||
4630 | dc->clk_mgr->dc_mode_softmax_enabled = enable; | ||||
4631 | } | ||||
4632 | bool_Bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, | ||||
4633 | struct dc_cursor_attributes *cursor_attr) | ||||
4634 | { | ||||
4635 | if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr)) | ||||
4636 | return true1; | ||||
4637 | return false0; | ||||
4638 | } | ||||
4639 | |||||
4640 | /* cleanup on driver unload */ | ||||
4641 | void dc_hardware_release(struct dc *dc) | ||||
4642 | { | ||||
4643 | dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc); | ||||
4644 | |||||
4645 | if (dc->hwss.hardware_release) | ||||
4646 | dc->hwss.hardware_release(dc); | ||||
4647 | } | ||||
4648 | |||||
4649 | void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc) | ||||
4650 | { | ||||
4651 | if (dc->current_state) | ||||
4652 | dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true1; | ||||
4653 | } | ||||
4654 | |||||
4655 | /** | ||||
4656 | * dc_is_dmub_outbox_supported - Check if DMUB firmware support outbox notification | ||||
4657 | * | ||||
4658 | * @dc: [in] dc structure | ||||
4659 | * | ||||
4660 | * Checks whether DMUB FW supports outbox notifications, if supported DM | ||||
4661 | * should register outbox interrupt prior to actually enabling interrupts | ||||
4662 | * via dc_enable_dmub_outbox | ||||
4663 | * | ||||
4664 | * Return: | ||||
4665 | * True if DMUB FW supports outbox notifications, False otherwise | ||||
4666 | */ | ||||
4667 | bool_Bool dc_is_dmub_outbox_supported(struct dc *dc) | ||||
4668 | { | ||||
4669 | /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */ | ||||
4670 | if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP146 && | ||||
4671 | dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B00x20 && | ||||
4672 | !dc->debug.dpia_debug.bits.disable_dpia) | ||||
4673 | return true1; | ||||
4674 | |||||
4675 | if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1148 && | ||||
4676 | !dc->debug.dpia_debug.bits.disable_dpia) | ||||
4677 | return true1; | ||||
4678 | |||||
4679 | /* dmub aux needs dmub notifications to be enabled */ | ||||
4680 | return dc->debug.enable_dmub_aux_for_legacy_ddc; | ||||
4681 | } | ||||
4682 | |||||
4683 | /** | ||||
4684 | * dc_enable_dmub_notifications - Check if dmub fw supports outbox | ||||
4685 | * | ||||
4686 | * @dc: [in] dc structure | ||||
4687 | * | ||||
4688 | * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox | ||||
4689 | * notifications. All DMs shall switch to dc_is_dmub_outbox_supported. This | ||||
4690 | * API shall be removed after switching. | ||||
4691 | * | ||||
4692 | * Return: | ||||
4693 | * True if DMUB FW supports outbox notifications, False otherwise | ||||
4694 | */ | ||||
4695 | bool_Bool dc_enable_dmub_notifications(struct dc *dc) | ||||
4696 | { | ||||
4697 | return dc_is_dmub_outbox_supported(dc); | ||||
4698 | } | ||||
4699 | |||||
4700 | /** | ||||
4701 | * dc_enable_dmub_outbox - Enables DMUB unsolicited notification | ||||
4702 | * | ||||
4703 | * @dc: [in] dc structure | ||||
4704 | * | ||||
4705 | * Enables DMUB unsolicited notifications to x86 via outbox. | ||||
4706 | */ | ||||
4707 | void dc_enable_dmub_outbox(struct dc *dc) | ||||
4708 | { | ||||
4709 | struct dc_context *dc_ctx = dc->ctx; | ||||
4710 | |||||
4711 | dmub_enable_outbox_notification(dc_ctx->dmub_srv); | ||||
4712 | DC_LOG_DC("%s: dmub outbox notifications enabled\n", __func__)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: dmub outbox notifications enabled\n" , __func__); | ||||
4713 | } | ||||
4714 | |||||
4715 | /** | ||||
4716 | * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message | ||||
4717 | * Sets port index appropriately for legacy DDC | ||||
4718 | * @dc: dc structure | ||||
4719 | * @link_index: link index | ||||
4720 | * @payload: aux payload | ||||
4721 | * | ||||
4722 | * Returns: True if successful, False if failure | ||||
4723 | */ | ||||
4724 | bool_Bool dc_process_dmub_aux_transfer_async(struct dc *dc, | ||||
4725 | uint32_t link_index, | ||||
4726 | struct aux_payload *payload) | ||||
4727 | { | ||||
4728 | uint8_t action; | ||||
4729 | union dmub_rb_cmd cmd = {0}; | ||||
4730 | struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; | ||||
4731 | |||||
4732 | ASSERT(payload->length <= 16)do { if (({ static int __warned; int __ret = !!(!(payload-> length <= 16)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(payload->length <= 16)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c" , 4732); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
4733 | |||||
4734 | cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS; | ||||
4735 | cmd.dp_aux_access.header.payload_bytes = 0; | ||||
4736 | /* For dpia, ddc_pin is set to NULL */ | ||||
4737 | if (!dc->links[link_index]->ddc->ddc_pin) | ||||
4738 | cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA; | ||||
4739 | else | ||||
4740 | cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC; | ||||
4741 | |||||
4742 | cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst; | ||||
4743 | cmd.dp_aux_access.aux_control.sw_crc_enabled = 0; | ||||
4744 | cmd.dp_aux_access.aux_control.timeout = 0; | ||||
4745 | cmd.dp_aux_access.aux_control.dpaux.address = payload->address; | ||||
4746 | cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux; | ||||
4747 | cmd.dp_aux_access.aux_control.dpaux.length = payload->length; | ||||
4748 | |||||
4749 | /* set aux action */ | ||||
4750 | if (payload->i2c_over_aux) { | ||||
4751 | if (payload->write) { | ||||
4752 | if (payload->mot) | ||||
4753 | action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT; | ||||
4754 | else | ||||
4755 | action = DP_AUX_REQ_ACTION_I2C_WRITE; | ||||
4756 | } else { | ||||
4757 | if (payload->mot) | ||||
4758 | action = DP_AUX_REQ_ACTION_I2C_READ_MOT; | ||||
4759 | else | ||||
4760 | action = DP_AUX_REQ_ACTION_I2C_READ; | ||||
4761 | } | ||||
4762 | } else { | ||||
4763 | if (payload->write) | ||||
4764 | action = DP_AUX_REQ_ACTION_DPCD_WRITE; | ||||
4765 | else | ||||
4766 | action = DP_AUX_REQ_ACTION_DPCD_READ; | ||||
4767 | } | ||||
4768 | |||||
4769 | cmd.dp_aux_access.aux_control.dpaux.action = action; | ||||
4770 | |||||
4771 | if (payload->length && payload->write) { | ||||
4772 | memcpy(cmd.dp_aux_access.aux_control.dpaux.data,__builtin_memcpy((cmd.dp_aux_access.aux_control.dpaux.data), ( payload->data), (payload->length)) | ||||
4773 | payload->data,__builtin_memcpy((cmd.dp_aux_access.aux_control.dpaux.data), ( payload->data), (payload->length)) | ||||
4774 | payload->length__builtin_memcpy((cmd.dp_aux_access.aux_control.dpaux.data), ( payload->data), (payload->length)) | ||||
4775 | )__builtin_memcpy((cmd.dp_aux_access.aux_control.dpaux.data), ( payload->data), (payload->length)); | ||||
4776 | } | ||||
4777 | |||||
4778 | dc_dmub_srv_cmd_queue(dmub_srv, &cmd); | ||||
4779 | dc_dmub_srv_cmd_execute(dmub_srv); | ||||
4780 | dc_dmub_srv_wait_idle(dmub_srv); | ||||
4781 | |||||
4782 | return true1; | ||||
4783 | } | ||||
4784 | |||||
4785 | uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, | ||||
4786 | uint8_t dpia_port_index) | ||||
4787 | { | ||||
4788 | uint8_t index, link_index = 0xFF; | ||||
4789 | |||||
4790 | for (index = 0; index < dc->link_count; index++) { | ||||
4791 | /* ddc_hw_inst has dpia port index for dpia links | ||||
4792 | * and ddc instance for legacy links | ||||
4793 | */ | ||||
4794 | if (!dc->links[index]->ddc->ddc_pin) { | ||||
4795 | if (dc->links[index]->ddc_hw_inst == dpia_port_index) { | ||||
4796 | link_index = index; | ||||
4797 | break; | ||||
4798 | } | ||||
4799 | } | ||||
4800 | } | ||||
4801 | ASSERT(link_index != 0xFF)do { if (({ static int __warned; int __ret = !!(!(link_index != 0xFF)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(link_index != 0xFF)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c" , 4801); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
4802 | return link_index; | ||||
4803 | } | ||||
4804 | |||||
4805 | /** | ||||
4806 | * dc_process_dmub_set_config_async - Submits set_config command | ||||
4807 | * | ||||
4808 | * @dc: [in] dc structure | ||||
4809 | * @link_index: [in] link_index: link index | ||||
4810 | * @payload: [in] aux payload | ||||
4811 | * @notify: [out] set_config immediate reply | ||||
4812 | * | ||||
4813 | * Submits set_config command to dmub via inbox message. | ||||
4814 | * | ||||
4815 | * Return: | ||||
4816 | * True if successful, False if failure | ||||
4817 | */ | ||||
4818 | bool_Bool dc_process_dmub_set_config_async(struct dc *dc, | ||||
4819 | uint32_t link_index, | ||||
4820 | struct set_config_cmd_payload *payload, | ||||
4821 | struct dmub_notification *notify) | ||||
4822 | { | ||||
4823 | union dmub_rb_cmd cmd = {0}; | ||||
4824 | struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; | ||||
4825 | bool_Bool is_cmd_complete = true1; | ||||
4826 | |||||
4827 | /* prepare SET_CONFIG command */ | ||||
4828 | cmd.set_config_access.header.type = DMUB_CMD__DPIA; | ||||
4829 | cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS; | ||||
4830 | |||||
4831 | cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst; | ||||
4832 | cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type; | ||||
4833 | cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data; | ||||
4834 | |||||
4835 | if (!dc_dmub_srv_cmd_with_reply_data(dmub_srv, &cmd)) { | ||||
4836 | /* command is not processed by dmub */ | ||||
4837 | notify->sc_status = SET_CONFIG_UNKNOWN_ERROR; | ||||
4838 | return is_cmd_complete; | ||||
4839 | } | ||||
4840 | |||||
4841 | /* command processed by dmub, if ret_status is 1, it is completed instantly */ | ||||
4842 | if (cmd.set_config_access.header.ret_status == 1) | ||||
4843 | notify->sc_status = cmd.set_config_access.set_config_control.immed_status; | ||||
4844 | else | ||||
4845 | /* cmd pending, will receive notification via outbox */ | ||||
4846 | is_cmd_complete = false0; | ||||
4847 | |||||
4848 | return is_cmd_complete; | ||||
4849 | } | ||||
4850 | |||||
4851 | /** | ||||
4852 | * dc_process_dmub_set_mst_slots - Submits MST solt allocation | ||||
4853 | * | ||||
4854 | * @dc: [in] dc structure | ||||
4855 | * @link_index: [in] link index | ||||
4856 | * @mst_alloc_slots: [in] mst slots to be allotted | ||||
4857 | * @mst_slots_in_use: [out] mst slots in use returned in failure case | ||||
4858 | * | ||||
4859 | * Submits mst slot allocation command to dmub via inbox message | ||||
4860 | * | ||||
4861 | * Return: | ||||
4862 | * DC_OK if successful, DC_ERROR if failure | ||||
4863 | */ | ||||
4864 | enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, | ||||
4865 | uint32_t link_index, | ||||
4866 | uint8_t mst_alloc_slots, | ||||
4867 | uint8_t *mst_slots_in_use) | ||||
4868 | { | ||||
4869 | union dmub_rb_cmd cmd = {0}; | ||||
4870 | struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; | ||||
4871 | |||||
4872 | /* prepare MST_ALLOC_SLOTS command */ | ||||
4873 | cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA; | ||||
4874 | cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS; | ||||
4875 | |||||
4876 | cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst; | ||||
4877 | cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots; | ||||
4878 | |||||
4879 | if (!dc_dmub_srv_cmd_with_reply_data(dmub_srv, &cmd)) | ||||
4880 | /* command is not processed by dmub */ | ||||
4881 | return DC_ERROR_UNEXPECTED; | ||||
4882 | |||||
4883 | /* command processed by dmub, if ret_status is 1 */ | ||||
4884 | if (cmd.set_config_access.header.ret_status != 1) | ||||
4885 | /* command processing error */ | ||||
4886 | return DC_ERROR_UNEXPECTED; | ||||
4887 | |||||
4888 | /* command processed and we have a status of 2, mst not enabled in dpia */ | ||||
4889 | if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2) | ||||
4890 | return DC_FAIL_UNSUPPORTED_1; | ||||
4891 | |||||
4892 | /* previously configured mst alloc and used slots did not match */ | ||||
4893 | if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) { | ||||
4894 | *mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use; | ||||
4895 | return DC_NOT_SUPPORTED; | ||||
4896 | } | ||||
4897 | |||||
4898 | return DC_OK; | ||||
4899 | } | ||||
4900 | |||||
4901 | /** | ||||
4902 | * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption | ||||
4903 | * | ||||
4904 | * @dc: [in] dc structure | ||||
4905 | * @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable | ||||
4906 | * | ||||
4907 | * Submits dpia hpd int enable command to dmub via inbox message | ||||
4908 | */ | ||||
4909 | void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, | ||||
4910 | uint32_t hpd_int_enable) | ||||
4911 | { | ||||
4912 | union dmub_rb_cmd cmd = {0}; | ||||
4913 | struct dc_dmub_srv *dmub_srv = dc->ctx->dmub_srv; | ||||
4914 | |||||
4915 | cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE; | ||||
4916 | cmd.dpia_hpd_int_enable.enable = hpd_int_enable; | ||||
4917 | |||||
4918 | dc_dmub_srv_cmd_queue(dmub_srv, &cmd); | ||||
4919 | dc_dmub_srv_cmd_execute(dmub_srv); | ||||
4920 | dc_dmub_srv_wait_idle(dmub_srv); | ||||
4921 | |||||
4922 | DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: hpd_int_enable(%d)\n" , __func__, hpd_int_enable); | ||||
4923 | } | ||||
4924 | |||||
4925 | /** | ||||
4926 | * dc_disable_accelerated_mode - disable accelerated mode | ||||
4927 | * @dc: dc structure | ||||
4928 | */ | ||||
4929 | void dc_disable_accelerated_mode(struct dc *dc) | ||||
4930 | { | ||||
4931 | bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0); | ||||
4932 | } | ||||
4933 | |||||
4934 | |||||
4935 | /** | ||||
4936 | * dc_notify_vsync_int_state - notifies vsync enable/disable state | ||||
4937 | * @dc: dc structure | ||||
4938 | * @stream: stream where vsync int state changed | ||||
4939 | * @enable: whether vsync is enabled or disabled | ||||
4940 | * | ||||
4941 | * Called when vsync is enabled/disabled Will notify DMUB to start/stop ABM | ||||
4942 | * interrupts after steady state is reached. | ||||
4943 | */ | ||||
4944 | void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool_Bool enable) | ||||
4945 | { | ||||
4946 | int i; | ||||
4947 | int edp_num; | ||||
4948 | struct pipe_ctx *pipe = NULL((void *)0); | ||||
4949 | struct dc_link *link = stream->sink->link; | ||||
4950 | struct dc_link *edp_links[MAX_NUM_EDP2]; | ||||
4951 | |||||
4952 | |||||
4953 | if (link->psr_settings.psr_feature_enabled) | ||||
4954 | return; | ||||
4955 | |||||
4956 | /*find primary pipe associated with stream*/ | ||||
4957 | for (i = 0; i < MAX_PIPES6; i++) { | ||||
4958 | pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||
4959 | |||||
4960 | if (pipe->stream == stream && pipe->stream_res.tg) | ||||
4961 | break; | ||||
4962 | } | ||||
4963 | |||||
4964 | if (i == MAX_PIPES6) { | ||||
4965 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c" , 4965); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
4966 | return; | ||||
4967 | } | ||||
4968 | |||||
4969 | get_edp_links(dc, edp_links, &edp_num); | ||||
4970 | |||||
4971 | /* Determine panel inst */ | ||||
4972 | for (i = 0; i < edp_num; i++) { | ||||
4973 | if (edp_links[i] == link) | ||||
4974 | break; | ||||
4975 | } | ||||
4976 | |||||
4977 | if (i == edp_num) { | ||||
4978 | return; | ||||
4979 | } | ||||
4980 | |||||
4981 | if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause) | ||||
4982 | pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst); | ||||
4983 | } |