| File: | dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c |
| Warning: | line 1317, column 2 Value stored to 'min_hratio_fact_c' is never read |
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| 1 | /* |
| 2 | * Copyright 2020 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: AMD |
| 23 | * |
| 24 | */ |
| 25 | |
| 26 | #include <generated/autoconf.h> |
| 27 | |
| 28 | #ifdef CONFIG_DRM_AMD_DC_DCN1 |
| 29 | |
| 30 | #include "../display_mode_lib.h" |
| 31 | #include "../display_mode_vba.h" |
| 32 | #include "../dml_inline_defs.h" |
| 33 | #include "display_rq_dlg_calc_30.h" |
| 34 | #include "display_mode_vba_30.h" |
| 35 | |
| 36 | static bool_Bool is_dual_plane(enum source_format_class source_format) |
| 37 | { |
| 38 | bool_Bool ret_val = 0; |
| 39 | |
| 40 | if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha)) |
| 41 | ret_val = 1; |
| 42 | |
| 43 | return ret_val; |
| 44 | } |
| 45 | |
| 46 | static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, |
| 47 | double refclk_freq_in_mhz, |
| 48 | double pclk_freq_in_mhz, |
| 49 | unsigned int odm_combine, |
| 50 | unsigned int recout_width, |
| 51 | unsigned int hactive, |
| 52 | double vratio, |
| 53 | double hscale_pixel_rate, |
| 54 | unsigned int delivery_width, |
| 55 | unsigned int req_per_swath_ub) |
| 56 | { |
| 57 | double refcyc_per_delivery = 0.0; |
| 58 | |
| 59 | if (vratio <= 1.0) { |
| 60 | if (odm_combine) |
| 61 | refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)((unsigned int)odm_combine*2) |
| 62 | * dml_min((double)recout_width, (double)hactive / ((unsigned int)odm_combine*2)) |
| 63 | / pclk_freq_in_mhz / (double)req_per_swath_ub; |
| 64 | else |
| 65 | refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)recout_width |
| 66 | / pclk_freq_in_mhz / (double)req_per_swath_ub; |
| 67 | } else { |
| 68 | refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)delivery_width |
| 69 | / (double)hscale_pixel_rate / (double)req_per_swath_ub; |
| 70 | } |
| 71 | |
| 72 | dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz){do { } while(0); }; |
| 73 | dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz){do { } while(0); }; |
| 74 | dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width){do { } while(0); }; |
| 75 | dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio){do { } while(0); }; |
| 76 | dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub){do { } while(0); }; |
| 77 | dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery){do { } while(0); }; |
| 78 | |
| 79 | return refcyc_per_delivery; |
| 80 | |
| 81 | } |
| 82 | |
| 83 | static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) |
| 84 | { |
| 85 | if (tile_size == dm_256k_tile) |
| 86 | return (256 * 1024); |
| 87 | else if (tile_size == dm_64k_tile) |
| 88 | return (64 * 1024); |
| 89 | else |
| 90 | return (4 * 1024); |
| 91 | } |
| 92 | |
| 93 | static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, |
| 94 | display_data_rq_regs_st *rq_regs, |
| 95 | const display_data_rq_sizing_params_st *rq_sizing) |
| 96 | { |
| 97 | dml_print("DML_DLG: %s: rq_sizing param\n", __func__){do { } while(0); }; |
| 98 | print__data_rq_sizing_params_st(mode_lib, rq_sizing); |
| 99 | |
| 100 | rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; |
| 101 | |
| 102 | if (rq_sizing->min_chunk_bytes == 0) |
| 103 | rq_regs->min_chunk_size = 0; |
| 104 | else |
| 105 | rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; |
| 106 | |
| 107 | rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; |
| 108 | if (rq_sizing->min_meta_chunk_bytes == 0) |
| 109 | rq_regs->min_meta_chunk_size = 0; |
| 110 | else |
| 111 | rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; |
| 112 | |
| 113 | rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; |
| 114 | rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; |
| 115 | } |
| 116 | |
| 117 | static void extract_rq_regs(struct display_mode_lib *mode_lib, |
| 118 | display_rq_regs_st *rq_regs, |
| 119 | const display_rq_params_st *rq_param) |
| 120 | { |
| 121 | unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; |
| 122 | unsigned int detile_buf_plane1_addr = 0; |
| 123 | |
| 124 | extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); |
| 125 | |
| 126 | rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), |
| 127 | 1) - 3; |
| 128 | |
| 129 | if (rq_param->yuv420) { |
| 130 | extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); |
| 131 | rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), |
| 132 | 1) - 3; |
| 133 | } |
| 134 | |
| 135 | rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); |
| 136 | rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); |
| 137 | |
| 138 | // FIXME: take the max between luma, chroma chunk size? |
| 139 | // okay for now, as we are setting chunk_bytes to 8kb anyways |
| 140 | if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param->yuv420 && rq_param->sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb |
| 141 | rq_regs->drq_expansion_mode = 0; |
| 142 | } else { |
| 143 | rq_regs->drq_expansion_mode = 2; |
| 144 | } |
| 145 | rq_regs->prq_expansion_mode = 1; |
| 146 | rq_regs->mrq_expansion_mode = 1; |
| 147 | rq_regs->crq_expansion_mode = 1; |
| 148 | |
| 149 | if (rq_param->yuv420) { |
| 150 | if ((double)rq_param->misc.rq_l.stored_swath_bytes |
| 151 | / (double)rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { |
| 152 | detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma |
| 153 | } else { |
| 154 | detile_buf_plane1_addr = dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), |
| 155 | 256, |
| 156 | 0) / 64.0; // 2/3 to chroma |
| 157 | } |
| 158 | } |
| 159 | rq_regs->plane1_base_address = detile_buf_plane1_addr; |
| 160 | } |
| 161 | |
| 162 | static void handle_det_buf_split(struct display_mode_lib *mode_lib, |
| 163 | display_rq_params_st *rq_param, |
| 164 | const display_pipe_source_params_st *pipe_src_param) |
| 165 | { |
| 166 | unsigned int total_swath_bytes = 0; |
| 167 | unsigned int swath_bytes_l = 0; |
| 168 | unsigned int swath_bytes_c = 0; |
| 169 | unsigned int full_swath_bytes_packed_l = 0; |
| 170 | unsigned int full_swath_bytes_packed_c = 0; |
| 171 | bool_Bool req128_l = false0; |
| 172 | bool_Bool req128_c = false0; |
| 173 | bool_Bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); |
| 174 | bool_Bool surf_vert = (pipe_src_param->source_scan == dm_vert); |
| 175 | unsigned int log2_swath_height_l = 0; |
| 176 | unsigned int log2_swath_height_c = 0; |
| 177 | unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; |
| 178 | |
| 179 | full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; |
| 180 | full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; |
| 181 | |
| 182 | if (rq_param->yuv420_10bpc) { |
| 183 | full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, |
| 184 | 256, |
| 185 | 1) + 256; |
| 186 | full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, |
| 187 | 256, |
| 188 | 1) + 256; |
| 189 | } |
| 190 | |
| 191 | if (rq_param->yuv420) |
| 192 | total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; |
| 193 | else |
| 194 | total_swath_bytes = 2 * full_swath_bytes_packed_l; |
| 195 | |
| 196 | if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request |
| 197 | req128_l = false0; |
| 198 | req128_c = false0; |
| 199 | swath_bytes_l = full_swath_bytes_packed_l; |
| 200 | swath_bytes_c = full_swath_bytes_packed_c; |
| 201 | } else if (!rq_param->yuv420) { |
| 202 | req128_l = true1; |
| 203 | req128_c = false0; |
| 204 | swath_bytes_c = full_swath_bytes_packed_c; |
| 205 | swath_bytes_l = full_swath_bytes_packed_l / 2; |
| 206 | } else if ((double)full_swath_bytes_packed_l / (double)full_swath_bytes_packed_c < 1.5) { |
| 207 | req128_l = false0; |
| 208 | req128_c = true1; |
| 209 | swath_bytes_l = full_swath_bytes_packed_l; |
| 210 | swath_bytes_c = full_swath_bytes_packed_c / 2; |
| 211 | |
| 212 | total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; |
| 213 | |
| 214 | if (total_swath_bytes > detile_buf_size_in_bytes) { |
| 215 | req128_l = true1; |
| 216 | swath_bytes_l = full_swath_bytes_packed_l / 2; |
| 217 | } |
| 218 | } else { |
| 219 | req128_l = true1; |
| 220 | req128_c = false0; |
| 221 | swath_bytes_l = full_swath_bytes_packed_l/2; |
| 222 | swath_bytes_c = full_swath_bytes_packed_c; |
| 223 | |
| 224 | total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; |
| 225 | |
| 226 | if (total_swath_bytes > detile_buf_size_in_bytes) { |
| 227 | req128_c = true1; |
| 228 | swath_bytes_c = full_swath_bytes_packed_c/2; |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | if (rq_param->yuv420) |
| 233 | total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; |
| 234 | else |
| 235 | total_swath_bytes = 2 * swath_bytes_l; |
| 236 | |
| 237 | rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; |
| 238 | rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; |
| 239 | |
| 240 | if (surf_linear) { |
| 241 | log2_swath_height_l = 0; |
| 242 | log2_swath_height_c = 0; |
| 243 | } else { |
| 244 | unsigned int swath_height_l; |
| 245 | unsigned int swath_height_c; |
| 246 | |
| 247 | if (!surf_vert) { |
| 248 | swath_height_l = rq_param->misc.rq_l.blk256_height; |
| 249 | swath_height_c = rq_param->misc.rq_c.blk256_height; |
| 250 | } else { |
| 251 | swath_height_l = rq_param->misc.rq_l.blk256_width; |
| 252 | swath_height_c = rq_param->misc.rq_c.blk256_width; |
| 253 | } |
| 254 | |
| 255 | if (swath_height_l > 0) |
| 256 | log2_swath_height_l = dml_log2(swath_height_l); |
| 257 | |
| 258 | if (req128_l && log2_swath_height_l > 0) |
| 259 | log2_swath_height_l -= 1; |
| 260 | |
| 261 | if (swath_height_c > 0) |
| 262 | log2_swath_height_c = dml_log2(swath_height_c); |
| 263 | |
| 264 | if (req128_c && log2_swath_height_c > 0) |
| 265 | log2_swath_height_c -= 1; |
| 266 | } |
| 267 | |
| 268 | rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; |
| 269 | rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; |
| 270 | |
| 271 | dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l){do { } while(0); }; |
| 272 | dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c){do { } while(0); }; |
| 273 | dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",{do { } while(0); } |
| 274 | __func__,{do { } while(0); } |
| 275 | full_swath_bytes_packed_l){do { } while(0); }; |
| 276 | dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",{do { } while(0); } |
| 277 | __func__,{do { } while(0); } |
| 278 | full_swath_bytes_packed_c){do { } while(0); }; |
| 279 | } |
| 280 | |
| 281 | static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, |
| 282 | display_data_rq_dlg_params_st *rq_dlg_param, |
| 283 | display_data_rq_misc_params_st *rq_misc_param, |
| 284 | display_data_rq_sizing_params_st *rq_sizing_param, |
| 285 | unsigned int vp_width, |
| 286 | unsigned int vp_height, |
| 287 | unsigned int data_pitch, |
| 288 | unsigned int meta_pitch, |
| 289 | unsigned int source_format, |
| 290 | unsigned int tiling, |
| 291 | unsigned int macro_tile_size, |
| 292 | unsigned int source_scan, |
| 293 | unsigned int hostvm_enable, |
| 294 | unsigned int is_chroma, |
| 295 | unsigned int surface_height) |
| 296 | { |
| 297 | bool_Bool surf_linear = (tiling == dm_sw_linear); |
| 298 | bool_Bool surf_vert = (source_scan == dm_vert); |
| 299 | |
| 300 | unsigned int bytes_per_element = 0; |
| 301 | unsigned int bytes_per_element_y = 0; |
| 302 | unsigned int bytes_per_element_c = 0; |
| 303 | |
| 304 | unsigned int blk256_width = 0; |
| 305 | unsigned int blk256_height = 0; |
| 306 | |
| 307 | unsigned int blk256_width_y = 0; |
| 308 | unsigned int blk256_height_y = 0; |
| 309 | unsigned int blk256_width_c = 0; |
| 310 | unsigned int blk256_height_c = 0; |
| 311 | unsigned int log2_bytes_per_element = 0; |
| 312 | unsigned int log2_blk256_width = 0; |
| 313 | unsigned int log2_blk256_height = 0; |
| 314 | unsigned int blk_bytes = 0; |
| 315 | unsigned int log2_blk_bytes = 0; |
| 316 | unsigned int log2_blk_height = 0; |
| 317 | unsigned int log2_blk_width = 0; |
| 318 | unsigned int log2_meta_req_bytes = 0; |
| 319 | unsigned int log2_meta_req_height = 0; |
| 320 | unsigned int log2_meta_req_width = 0; |
| 321 | unsigned int meta_req_width = 0; |
| 322 | unsigned int meta_req_height = 0; |
| 323 | unsigned int log2_meta_row_height = 0; |
| 324 | unsigned int meta_row_width_ub = 0; |
| 325 | unsigned int log2_meta_chunk_bytes = 0; |
| 326 | unsigned int log2_meta_chunk_height = 0; |
| 327 | |
| 328 | //full sized meta chunk width in unit of data elements |
| 329 | unsigned int log2_meta_chunk_width = 0; |
| 330 | unsigned int log2_min_meta_chunk_bytes = 0; |
| 331 | unsigned int min_meta_chunk_width = 0; |
| 332 | unsigned int meta_chunk_width = 0; |
| 333 | unsigned int meta_chunk_per_row_int = 0; |
| 334 | unsigned int meta_row_remainder = 0; |
| 335 | unsigned int meta_chunk_threshold = 0; |
| 336 | unsigned int meta_blk_bytes = 0; |
| 337 | unsigned int meta_blk_height = 0; |
| 338 | unsigned int meta_blk_width = 0; |
| 339 | unsigned int meta_surface_bytes = 0; |
| 340 | unsigned int vmpg_bytes = 0; |
| 341 | unsigned int meta_pte_req_per_frame_ub = 0; |
| 342 | unsigned int meta_pte_bytes_per_frame_ub = 0; |
| 343 | const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes); |
| 344 | const bool_Bool dual_plane_en = is_dual_plane((enum source_format_class)(source_format)); |
| 345 | const unsigned int dpte_buf_in_pte_reqs = dual_plane_en ? |
| 346 | (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) |
| 347 | : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma); |
| 348 | |
| 349 | unsigned int log2_vmpg_height = 0; |
| 350 | unsigned int log2_vmpg_width = 0; |
| 351 | unsigned int log2_dpte_req_height_ptes = 0; |
| 352 | unsigned int log2_dpte_req_height = 0; |
| 353 | unsigned int log2_dpte_req_width = 0; |
| 354 | unsigned int log2_dpte_row_height_linear = 0; |
| 355 | unsigned int log2_dpte_row_height = 0; |
| 356 | unsigned int log2_dpte_group_width = 0; |
| 357 | unsigned int dpte_row_width_ub = 0; |
| 358 | unsigned int dpte_req_height = 0; |
| 359 | unsigned int dpte_req_width = 0; |
| 360 | unsigned int dpte_group_width = 0; |
| 361 | unsigned int log2_dpte_group_bytes = 0; |
| 362 | unsigned int log2_dpte_group_length = 0; |
| 363 | double byte_per_pixel_det_y = 0; |
| 364 | double byte_per_pixel_det_c = 0; |
| 365 | |
| 366 | dml30_CalculateBytePerPixelAnd256BBlockSizes((enum source_format_class)(source_format), |
| 367 | (enum dm_swizzle_mode)(tiling), |
| 368 | &bytes_per_element_y, |
| 369 | &bytes_per_element_c, |
| 370 | &byte_per_pixel_det_y, |
| 371 | &byte_per_pixel_det_c, |
| 372 | &blk256_height_y, |
| 373 | &blk256_height_c, |
| 374 | &blk256_width_y, |
| 375 | &blk256_width_c); |
| 376 | |
| 377 | if (!is_chroma) { |
| 378 | blk256_width = blk256_width_y; |
| 379 | blk256_height = blk256_height_y; |
| 380 | bytes_per_element = bytes_per_element_y; |
| 381 | } else { |
| 382 | blk256_width = blk256_width_c; |
| 383 | blk256_height = blk256_height_c; |
| 384 | bytes_per_element = bytes_per_element_c; |
| 385 | } |
| 386 | |
| 387 | log2_bytes_per_element = dml_log2(bytes_per_element); |
| 388 | |
| 389 | dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear){do { } while(0); }; |
| 390 | dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert){do { } while(0); }; |
| 391 | dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width){do { } while(0); }; |
| 392 | dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height){do { } while(0); }; |
| 393 | |
| 394 | log2_blk256_width = dml_log2((double)blk256_width); |
| 395 | log2_blk256_height = dml_log2((double)blk256_height); |
| 396 | blk_bytes = surf_linear ? |
| 397 | 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); |
| 398 | log2_blk_bytes = dml_log2((double)blk_bytes); |
| 399 | log2_blk_height = 0; |
| 400 | log2_blk_width = 0; |
| 401 | |
| 402 | // remember log rule |
| 403 | // "+" in log is multiply |
| 404 | // "-" in log is divide |
| 405 | // "/2" is like square root |
| 406 | // blk is vertical biased |
| 407 | if (tiling != dm_sw_linear) |
| 408 | log2_blk_height = log2_blk256_height |
| 409 | + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1); |
| 410 | else |
| 411 | log2_blk_height = 0; // blk height of 1 |
| 412 | |
| 413 | log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; |
| 414 | |
| 415 | if (!surf_vert) { |
| 416 | int unsigned temp = 0; |
| 417 | |
| 418 | temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width; |
| 419 | if (data_pitch < blk256_width) { |
| 420 | dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width){do { } while(0); }; |
| 421 | } else { |
| 422 | if (temp > data_pitch) { |
| 423 | if (data_pitch >= vp_width) |
| 424 | temp = data_pitch; |
| 425 | else |
| 426 | dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width){do { } while(0); }; |
| 427 | } |
| 428 | } |
| 429 | rq_dlg_param->swath_width_ub = temp; |
| 430 | rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width; |
| 431 | } else { |
| 432 | int unsigned temp = 0; |
| 433 | |
| 434 | temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height; |
| 435 | if (surface_height < blk256_height) { |
| 436 | dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height){do { } while(0); }; |
| 437 | } else { |
| 438 | if (temp > surface_height) { |
| 439 | if (surface_height >= vp_height) |
| 440 | temp = surface_height; |
| 441 | else |
| 442 | dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height){do { } while(0); }; |
| 443 | } |
| 444 | } |
| 445 | rq_dlg_param->swath_width_ub = temp; |
| 446 | rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height; |
| 447 | } |
| 448 | |
| 449 | if (!surf_vert) |
| 450 | rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height |
| 451 | * bytes_per_element; |
| 452 | else |
| 453 | rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width |
| 454 | * bytes_per_element; |
| 455 | |
| 456 | rq_misc_param->blk256_height = blk256_height; |
| 457 | rq_misc_param->blk256_width = blk256_width; |
| 458 | |
| 459 | // ------- |
| 460 | // meta |
| 461 | // ------- |
| 462 | log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element |
| 463 | |
| 464 | // each 64b meta request for dcn is 8x8 meta elements and |
| 465 | // a meta element covers one 256b block of the data surface. |
| 466 | log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 |
| 467 | log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element |
| 468 | - log2_meta_req_height; |
| 469 | meta_req_width = 1 << log2_meta_req_width; |
| 470 | meta_req_height = 1 << log2_meta_req_height; |
| 471 | log2_meta_row_height = 0; |
| 472 | meta_row_width_ub = 0; |
| 473 | |
| 474 | // the dimensions of a meta row are meta_row_width x meta_row_height in elements. |
| 475 | // calculate upper bound of the meta_row_width |
| 476 | if (!surf_vert) { |
| 477 | log2_meta_row_height = log2_meta_req_height; |
| 478 | meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) |
| 479 | + meta_req_width; |
| 480 | rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; |
| 481 | } else { |
| 482 | log2_meta_row_height = log2_meta_req_width; |
| 483 | meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) |
| 484 | + meta_req_height; |
| 485 | rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; |
| 486 | } |
| 487 | rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; |
| 488 | |
| 489 | rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; |
| 490 | |
| 491 | log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); |
| 492 | log2_meta_chunk_height = log2_meta_row_height; |
| 493 | |
| 494 | //full sized meta chunk width in unit of data elements |
| 495 | log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element |
| 496 | - log2_meta_chunk_height; |
| 497 | log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); |
| 498 | min_meta_chunk_width = 1 |
| 499 | << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element |
| 500 | - log2_meta_chunk_height); |
| 501 | meta_chunk_width = 1 << log2_meta_chunk_width; |
| 502 | meta_chunk_per_row_int = (unsigned int)(meta_row_width_ub / meta_chunk_width); |
| 503 | meta_row_remainder = meta_row_width_ub % meta_chunk_width; |
| 504 | meta_chunk_threshold = 0; |
| 505 | meta_blk_bytes = 4096; |
| 506 | meta_blk_height = blk256_height * 64; |
| 507 | meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; |
| 508 | meta_surface_bytes = meta_pitch |
| 509 | * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) |
| 510 | * bytes_per_element / 256; |
| 511 | vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes; |
| 512 | meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, |
| 513 | 8 * vmpg_bytes, |
| 514 | 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); |
| 515 | meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request |
| 516 | rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; |
| 517 | |
| 518 | dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height){do { } while(0); }; |
| 519 | dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width){do { } while(0); }; |
| 520 | dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes){do { } while(0); }; |
| 521 | dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n",{do { } while(0); } |
| 522 | __func__,{do { } while(0); } |
| 523 | meta_pte_req_per_frame_ub){do { } while(0); }; |
| 524 | dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",{do { } while(0); } |
| 525 | __func__,{do { } while(0); } |
| 526 | meta_pte_bytes_per_frame_ub){do { } while(0); }; |
| 527 | |
| 528 | if (!surf_vert) |
| 529 | meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; |
| 530 | else |
| 531 | meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; |
| 532 | |
| 533 | if (meta_row_remainder <= meta_chunk_threshold) |
| 534 | rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; |
| 535 | else |
| 536 | rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; |
| 537 | |
| 538 | // ------ |
| 539 | // dpte |
| 540 | // ------ |
| 541 | if (surf_linear) { |
| 542 | log2_vmpg_height = 0; // one line high |
| 543 | } else { |
| 544 | log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; |
| 545 | } |
| 546 | log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; |
| 547 | |
| 548 | // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. |
| 549 | if (surf_linear) { //one 64B PTE request returns 8 PTEs |
| 550 | log2_dpte_req_height_ptes = 0; |
| 551 | log2_dpte_req_width = log2_vmpg_width + 3; |
| 552 | log2_dpte_req_height = 0; |
| 553 | } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size |
| 554 | //one 64B req gives 8x1 PTEs for 4KB tile |
| 555 | log2_dpte_req_height_ptes = 0; |
| 556 | log2_dpte_req_width = log2_blk_width + 3; |
| 557 | log2_dpte_req_height = log2_blk_height + 0; |
| 558 | } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB |
| 559 | //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB |
| 560 | log2_dpte_req_height_ptes = 4; |
| 561 | log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width |
| 562 | log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height |
| 563 | } else { //64KB page size and must 64KB tile block |
| 564 | //one 64B req gives 8x1 PTEs for 64KB tile |
| 565 | log2_dpte_req_height_ptes = 0; |
| 566 | log2_dpte_req_width = log2_blk_width + 3; |
| 567 | log2_dpte_req_height = log2_blk_height + 0; |
| 568 | } |
| 569 | |
| 570 | // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height |
| 571 | // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent |
| 572 | // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) |
| 573 | //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; |
| 574 | //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; |
| 575 | dpte_req_height = 1 << log2_dpte_req_height; |
| 576 | dpte_req_width = 1 << log2_dpte_req_width; |
| 577 | |
| 578 | // calculate pitch dpte row buffer can hold |
| 579 | // round the result down to a power of two. |
| 580 | if (surf_linear) { |
| 581 | unsigned int dpte_row_height = 0; |
| 582 | |
| 583 | log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); |
| 584 | |
| 585 | dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma){do { } while(0); }; |
| 586 | dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs){do { } while(0); }; |
| 587 | dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear){do { } while(0); }; |
| 588 | |
| 589 | ASSERT(log2_dpte_row_height_linear >= 3)do { if (({ static int __warned; int __ret = !!(!(log2_dpte_row_height_linear >= 3)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(log2_dpte_row_height_linear >= 3)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 589); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 590 | |
| 591 | if (log2_dpte_row_height_linear > 7) |
| 592 | log2_dpte_row_height_linear = 7; |
| 593 | |
| 594 | log2_dpte_row_height = log2_dpte_row_height_linear; |
| 595 | // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. |
| 596 | // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. |
| 597 | dpte_row_height = 1 << log2_dpte_row_height; |
| 598 | dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, |
| 599 | dpte_req_width, |
| 600 | 1) + dpte_req_width; |
| 601 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; |
| 602 | } else { |
| 603 | // the upper bound of the dpte_row_width without dependency on viewport position follows. |
| 604 | // for tiled mode, row height is the same as req height and row store up to vp size upper bound |
| 605 | if (!surf_vert) { |
| 606 | log2_dpte_row_height = log2_dpte_req_height; |
| 607 | dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) |
| 608 | + dpte_req_width; |
| 609 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; |
| 610 | } else { |
| 611 | log2_dpte_row_height = |
| 612 | (log2_blk_width < log2_dpte_req_width) ? |
| 613 | log2_blk_width : log2_dpte_req_width; |
| 614 | dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) |
| 615 | + dpte_req_height; |
| 616 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; |
| 617 | } |
| 618 | } |
| 619 | if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB |
| 620 | rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request |
| 621 | else |
| 622 | rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request |
| 623 | |
| 624 | rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; |
| 625 | |
| 626 | // the dpte_group_bytes is reduced for the specific case of vertical |
| 627 | // access of a tile surface that has dpte request of 8x1 ptes. |
| 628 | if (hostvm_enable) |
| 629 | rq_sizing_param->dpte_group_bytes = 512; |
| 630 | else { |
| 631 | if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group |
| 632 | rq_sizing_param->dpte_group_bytes = 512; |
| 633 | else |
| 634 | rq_sizing_param->dpte_group_bytes = 2048; |
| 635 | } |
| 636 | |
| 637 | //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. |
| 638 | log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); |
| 639 | log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests |
| 640 | |
| 641 | // full sized data pte group width in elements |
| 642 | if (!surf_vert) |
| 643 | log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; |
| 644 | else |
| 645 | log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; |
| 646 | |
| 647 | //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B |
| 648 | if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB |
| 649 | log2_dpte_group_width = log2_dpte_group_width - 1; |
| 650 | |
| 651 | dpte_group_width = 1 << log2_dpte_group_width; |
| 652 | |
| 653 | // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, |
| 654 | // the upper bound for the dpte groups per row is as follows. |
| 655 | rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double)dpte_row_width_ub / dpte_group_width, |
| 656 | 1); |
| 657 | } |
| 658 | |
| 659 | static void get_surf_rq_param(struct display_mode_lib *mode_lib, |
| 660 | display_data_rq_sizing_params_st *rq_sizing_param, |
| 661 | display_data_rq_dlg_params_st *rq_dlg_param, |
| 662 | display_data_rq_misc_params_st *rq_misc_param, |
| 663 | const display_pipe_params_st *pipe_param, |
| 664 | bool_Bool is_chroma, |
| 665 | bool_Bool is_alpha) |
| 666 | { |
| 667 | bool_Bool mode_422 = 0; |
| 668 | unsigned int vp_width = 0; |
| 669 | unsigned int vp_height = 0; |
| 670 | unsigned int data_pitch = 0; |
| 671 | unsigned int meta_pitch = 0; |
| 672 | unsigned int surface_height = 0; |
| 673 | unsigned int ppe = mode_422 ? 2 : 1; |
| 674 | |
| 675 | // FIXME check if ppe apply for both luma and chroma in 422 case |
| 676 | if (is_chroma | is_alpha) { |
| 677 | vp_width = pipe_param->src.viewport_width_c / ppe; |
| 678 | vp_height = pipe_param->src.viewport_height_c; |
| 679 | data_pitch = pipe_param->src.data_pitch_c; |
| 680 | meta_pitch = pipe_param->src.meta_pitch_c; |
| 681 | surface_height = pipe_param->src.surface_height_y / 2.0; |
| 682 | } else { |
| 683 | vp_width = pipe_param->src.viewport_width / ppe; |
| 684 | vp_height = pipe_param->src.viewport_height; |
| 685 | data_pitch = pipe_param->src.data_pitch; |
| 686 | meta_pitch = pipe_param->src.meta_pitch; |
| 687 | surface_height = pipe_param->src.surface_height_y; |
| 688 | } |
| 689 | |
| 690 | if (pipe_param->dest.odm_combine) { |
| 691 | unsigned int access_dir = 0; |
| 692 | unsigned int full_src_vp_width = 0; |
| 693 | unsigned int hactive_odm = 0; |
| 694 | unsigned int src_hactive_odm = 0; |
| 695 | access_dir = (pipe_param->src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed |
| 696 | hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine*2); |
| 697 | if (is_chroma) { |
| 698 | full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; |
| 699 | src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio_c * hactive_odm; |
| 700 | } else { |
| 701 | full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; |
| 702 | src_hactive_odm = pipe_param->scale_ratio_depth.hscl_ratio * hactive_odm; |
| 703 | } |
| 704 | |
| 705 | if (access_dir == 0) { |
| 706 | vp_width = dml_min(full_src_vp_width, src_hactive_odm); |
| 707 | dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width){do { } while(0); }; |
| 708 | } else { |
| 709 | vp_height = dml_min(full_src_vp_width, src_hactive_odm); |
| 710 | dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height){do { } while(0); }; |
| 711 | } |
| 712 | dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width){do { } while(0); }; |
| 713 | dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm){do { } while(0); }; |
| 714 | dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm){do { } while(0); }; |
| 715 | } |
| 716 | |
| 717 | rq_sizing_param->chunk_bytes = 8192; |
| 718 | |
| 719 | if (is_alpha) { |
| 720 | rq_sizing_param->chunk_bytes = 4096; |
| 721 | } |
| 722 | |
| 723 | if (rq_sizing_param->chunk_bytes == 64 * 1024) |
| 724 | rq_sizing_param->min_chunk_bytes = 0; |
| 725 | else |
| 726 | rq_sizing_param->min_chunk_bytes = 1024; |
| 727 | |
| 728 | rq_sizing_param->meta_chunk_bytes = 2048; |
| 729 | rq_sizing_param->min_meta_chunk_bytes = 256; |
| 730 | |
| 731 | if (pipe_param->src.hostvm) |
| 732 | rq_sizing_param->mpte_group_bytes = 512; |
| 733 | else |
| 734 | rq_sizing_param->mpte_group_bytes = 2048; |
| 735 | |
| 736 | get_meta_and_pte_attr(mode_lib, |
| 737 | rq_dlg_param, |
| 738 | rq_misc_param, |
| 739 | rq_sizing_param, |
| 740 | vp_width, |
| 741 | vp_height, |
| 742 | data_pitch, |
| 743 | meta_pitch, |
| 744 | pipe_param->src.source_format, |
| 745 | pipe_param->src.sw_mode, |
| 746 | pipe_param->src.macro_tile_size, |
| 747 | pipe_param->src.source_scan, |
| 748 | pipe_param->src.hostvm, |
| 749 | is_chroma, |
| 750 | surface_height); |
| 751 | } |
| 752 | |
| 753 | static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, |
| 754 | display_rq_params_st *rq_param, |
| 755 | const display_pipe_params_st *pipe_param) |
| 756 | { |
| 757 | // get param for luma surface |
| 758 | rq_param->yuv420 = pipe_param->src.source_format == dm_420_8 |
| 759 | || pipe_param->src.source_format == dm_420_10 |
| 760 | || pipe_param->src.source_format == dm_rgbe_alpha |
| 761 | || pipe_param->src.source_format == dm_420_12; |
| 762 | |
| 763 | rq_param->yuv420_10bpc = pipe_param->src.source_format == dm_420_10; |
| 764 | |
| 765 | rq_param->rgbe_alpha = (pipe_param->src.source_format == dm_rgbe_alpha)?1:0; |
| 766 | |
| 767 | get_surf_rq_param(mode_lib, |
| 768 | &(rq_param->sizing.rq_l), |
| 769 | &(rq_param->dlg.rq_l), |
| 770 | &(rq_param->misc.rq_l), |
| 771 | pipe_param, |
| 772 | 0, |
| 773 | 0); |
| 774 | |
| 775 | if (is_dual_plane((enum source_format_class)(pipe_param->src.source_format))) { |
| 776 | // get param for chroma surface |
| 777 | get_surf_rq_param(mode_lib, |
| 778 | &(rq_param->sizing.rq_c), |
| 779 | &(rq_param->dlg.rq_c), |
| 780 | &(rq_param->misc.rq_c), |
| 781 | pipe_param, |
| 782 | 1, |
| 783 | rq_param->rgbe_alpha); |
| 784 | } |
| 785 | |
| 786 | // calculate how to split the det buffer space between luma and chroma |
| 787 | handle_det_buf_split(mode_lib, rq_param, &pipe_param->src); |
| 788 | print__rq_params_st(mode_lib, rq_param); |
| 789 | } |
| 790 | |
| 791 | void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, |
| 792 | display_rq_regs_st *rq_regs, |
| 793 | const display_pipe_params_st *pipe_param) |
| 794 | { |
| 795 | display_rq_params_st rq_param = { 0 }; |
| 796 | |
| 797 | memset(rq_regs, 0, sizeof(*rq_regs))__builtin_memset((rq_regs), (0), (sizeof(*rq_regs))); |
| 798 | dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); |
| 799 | extract_rq_regs(mode_lib, rq_regs, &rq_param); |
| 800 | |
| 801 | print__rq_regs_st(mode_lib, rq_regs); |
| 802 | } |
| 803 | |
| 804 | static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, |
| 805 | double *refcyc_per_req_delivery_pre_cur, |
| 806 | double *refcyc_per_req_delivery_cur, |
| 807 | double refclk_freq_in_mhz, |
| 808 | double ref_freq_to_pix_freq, |
| 809 | double hscale_pixel_rate_l, |
| 810 | double hscl_ratio, |
| 811 | double vratio_pre_l, |
| 812 | double vratio_l, |
| 813 | unsigned int cur_width, |
| 814 | enum cursor_bpp cur_bpp) |
| 815 | { |
| 816 | unsigned int cur_src_width = cur_width; |
| 817 | unsigned int cur_req_size = 0; |
| 818 | unsigned int cur_req_width = 0; |
| 819 | double cur_width_ub = 0.0; |
| 820 | double cur_req_per_width = 0.0; |
| 821 | double hactive_cur = 0.0; |
| 822 | |
| 823 | ASSERT(cur_src_width <= 256)do { if (({ static int __warned; int __ret = !!(!(cur_src_width <= 256)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(cur_src_width <= 256)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 823); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 824 | |
| 825 | *refcyc_per_req_delivery_pre_cur = 0.0; |
| 826 | *refcyc_per_req_delivery_cur = 0.0; |
| 827 | if (cur_src_width > 0) { |
| 828 | unsigned int cur_bit_per_pixel = 0; |
| 829 | |
| 830 | if (cur_bpp == dm_cur_2bit) { |
| 831 | cur_req_size = 64; // byte |
| 832 | cur_bit_per_pixel = 2; |
| 833 | } else { // 32bit |
| 834 | cur_bit_per_pixel = 32; |
| 835 | if (cur_src_width >= 1 && cur_src_width <= 16) |
| 836 | cur_req_size = 64; |
| 837 | else if (cur_src_width >= 17 && cur_src_width <= 31) |
| 838 | cur_req_size = 128; |
| 839 | else |
| 840 | cur_req_size = 256; |
| 841 | } |
| 842 | |
| 843 | cur_req_width = (double)cur_req_size / ((double)cur_bit_per_pixel / 8.0); |
| 844 | cur_width_ub = dml_ceil((double)cur_src_width / (double)cur_req_width, 1) |
| 845 | * (double)cur_req_width; |
| 846 | cur_req_per_width = cur_width_ub / (double)cur_req_width; |
| 847 | hactive_cur = (double)cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor |
| 848 | |
| 849 | if (vratio_pre_l <= 1.0) { |
| 850 | *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq |
| 851 | / (double)cur_req_per_width; |
| 852 | } else { |
| 853 | *refcyc_per_req_delivery_pre_cur = (double)refclk_freq_in_mhz |
| 854 | * (double)cur_src_width / hscale_pixel_rate_l |
| 855 | / (double)cur_req_per_width; |
| 856 | } |
| 857 | |
| 858 | ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 858); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 859 | |
| 860 | if (vratio_l <= 1.0) { |
| 861 | *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq |
| 862 | / (double)cur_req_per_width; |
| 863 | } else { |
| 864 | *refcyc_per_req_delivery_cur = (double)refclk_freq_in_mhz |
| 865 | * (double)cur_src_width / hscale_pixel_rate_l |
| 866 | / (double)cur_req_per_width; |
| 867 | } |
| 868 | |
| 869 | dml_print("DML_DLG: %s: cur_req_width = %d\n",{do { } while(0); } |
| 870 | __func__,{do { } while(0); } |
| 871 | cur_req_width){do { } while(0); }; |
| 872 | dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n",{do { } while(0); } |
| 873 | __func__,{do { } while(0); } |
| 874 | cur_width_ub){do { } while(0); }; |
| 875 | dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n",{do { } while(0); } |
| 876 | __func__,{do { } while(0); } |
| 877 | cur_req_per_width){do { } while(0); }; |
| 878 | dml_print("DML_DLG: %s: hactive_cur = %3.2f\n",{do { } while(0); } |
| 879 | __func__,{do { } while(0); } |
| 880 | hactive_cur){do { } while(0); }; |
| 881 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n",{do { } while(0); } |
| 882 | __func__,{do { } while(0); } |
| 883 | *refcyc_per_req_delivery_pre_cur){do { } while(0); }; |
| 884 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n",{do { } while(0); } |
| 885 | __func__,{do { } while(0); } |
| 886 | *refcyc_per_req_delivery_cur){do { } while(0); }; |
| 887 | |
| 888 | ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(*refcyc_per_req_delivery_cur < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(*refcyc_per_req_delivery_cur < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 888); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 889 | } |
| 890 | } |
| 891 | |
| 892 | // Note: currently taken in as is. |
| 893 | // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. |
| 894 | static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, |
| 895 | const display_e2e_pipe_params_st *e2e_pipe_param, |
| 896 | const unsigned int num_pipes, |
| 897 | const unsigned int pipe_idx, |
| 898 | display_dlg_regs_st *disp_dlg_regs, |
| 899 | display_ttu_regs_st *disp_ttu_regs, |
| 900 | const display_rq_dlg_params_st rq_dlg_param, |
| 901 | const display_dlg_sys_params_st dlg_sys_param, |
| 902 | const bool_Bool cstate_en, |
| 903 | const bool_Bool pstate_en, |
| 904 | const bool_Bool vm_en, |
| 905 | const bool_Bool ignore_viewport_pos, |
| 906 | const bool_Bool immediate_flip_support) |
| 907 | { |
| 908 | const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; |
| 909 | const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; |
| 910 | const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; |
| 911 | const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; |
| 912 | const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; |
| 913 | const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; |
| 914 | |
| 915 | // ------------------------- |
| 916 | // Section 1.15.2.1: OTG dependent Params |
| 917 | // ------------------------- |
| 918 | // Timing |
| 919 | unsigned int htotal = dst->htotal; |
| 920 | // unsigned int hblank_start = dst.hblank_start; // TODO: Remove |
| 921 | unsigned int hblank_end = dst->hblank_end; |
| 922 | unsigned int vblank_start = dst->vblank_start; |
| 923 | unsigned int vblank_end = dst->vblank_end; |
| 924 | unsigned int min_vblank = mode_lib->ip.min_vblank_lines; |
| 925 | |
| 926 | double dppclk_freq_in_mhz = clks->dppclk_mhz; |
| 927 | double dispclk_freq_in_mhz = clks->dispclk_mhz; |
| 928 | double refclk_freq_in_mhz = clks->refclk_mhz; |
| 929 | double pclk_freq_in_mhz = dst->pixel_rate_mhz; |
| 930 | bool_Bool interlaced = dst->interlaced; |
| 931 | |
| 932 | double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; |
| 933 | |
| 934 | double min_dcfclk_mhz = 0; |
| 935 | double t_calc_us = 0; |
| 936 | double min_ttu_vblank = 0; |
| 937 | |
| 938 | double min_dst_y_ttu_vblank = 0; |
| 939 | unsigned int dlg_vblank_start = 0; |
| 940 | bool_Bool dual_plane = false0; |
| 941 | bool_Bool mode_422 = false0; |
| 942 | unsigned int access_dir = 0; |
| 943 | unsigned int vp_height_l = 0; |
| 944 | unsigned int vp_width_l = 0; |
| 945 | unsigned int vp_height_c = 0; |
| 946 | unsigned int vp_width_c = 0; |
| 947 | |
| 948 | // Scaling |
| 949 | unsigned int htaps_l = 0; |
| 950 | unsigned int htaps_c = 0; |
| 951 | double hratio_l = 0; |
| 952 | double hratio_c = 0; |
| 953 | double vratio_l = 0; |
| 954 | double vratio_c = 0; |
| 955 | bool_Bool scl_enable = false0; |
| 956 | |
| 957 | double line_time_in_us = 0; |
| 958 | // double vinit_l; |
| 959 | // double vinit_c; |
| 960 | // double vinit_bot_l; |
| 961 | // double vinit_bot_c; |
| 962 | |
| 963 | // unsigned int swath_height_l; |
| 964 | unsigned int swath_width_ub_l = 0; |
| 965 | // unsigned int dpte_bytes_per_row_ub_l; |
| 966 | unsigned int dpte_groups_per_row_ub_l = 0; |
| 967 | // unsigned int meta_pte_bytes_per_frame_ub_l; |
| 968 | // unsigned int meta_bytes_per_row_ub_l; |
| 969 | |
| 970 | // unsigned int swath_height_c; |
| 971 | unsigned int swath_width_ub_c = 0; |
| 972 | // unsigned int dpte_bytes_per_row_ub_c; |
| 973 | unsigned int dpte_groups_per_row_ub_c = 0; |
| 974 | |
| 975 | unsigned int meta_chunks_per_row_ub_l = 0; |
| 976 | unsigned int meta_chunks_per_row_ub_c = 0; |
| 977 | unsigned int vupdate_offset = 0; |
| 978 | unsigned int vupdate_width = 0; |
| 979 | unsigned int vready_offset = 0; |
| 980 | |
| 981 | unsigned int dppclk_delay_subtotal = 0; |
| 982 | unsigned int dispclk_delay_subtotal = 0; |
| 983 | unsigned int pixel_rate_delay_subtotal = 0; |
| 984 | |
| 985 | unsigned int vstartup_start = 0; |
| 986 | unsigned int dst_x_after_scaler = 0; |
| 987 | unsigned int dst_y_after_scaler = 0; |
| 988 | double line_wait = 0; |
| 989 | double dst_y_prefetch = 0; |
| 990 | double dst_y_per_vm_vblank = 0; |
| 991 | double dst_y_per_row_vblank = 0; |
| 992 | double dst_y_per_vm_flip = 0; |
| 993 | double dst_y_per_row_flip = 0; |
| 994 | double max_dst_y_per_vm_vblank = 0; |
| 995 | double max_dst_y_per_row_vblank = 0; |
| 996 | double lsw = 0; |
| 997 | double vratio_pre_l = 0; |
| 998 | double vratio_pre_c = 0; |
| 999 | unsigned int req_per_swath_ub_l = 0; |
| 1000 | unsigned int req_per_swath_ub_c = 0; |
| 1001 | unsigned int meta_row_height_l = 0; |
| 1002 | unsigned int meta_row_height_c = 0; |
| 1003 | unsigned int swath_width_pixels_ub_l = 0; |
| 1004 | unsigned int swath_width_pixels_ub_c = 0; |
| 1005 | unsigned int scaler_rec_in_width_l = 0; |
| 1006 | unsigned int scaler_rec_in_width_c = 0; |
| 1007 | unsigned int dpte_row_height_l = 0; |
| 1008 | unsigned int dpte_row_height_c = 0; |
| 1009 | double hscale_pixel_rate_l = 0; |
| 1010 | double hscale_pixel_rate_c = 0; |
| 1011 | double min_hratio_fact_l = 0; |
| 1012 | double min_hratio_fact_c = 0; |
| 1013 | double refcyc_per_line_delivery_pre_l = 0; |
| 1014 | double refcyc_per_line_delivery_pre_c = 0; |
| 1015 | double refcyc_per_line_delivery_l = 0; |
| 1016 | double refcyc_per_line_delivery_c = 0; |
| 1017 | |
| 1018 | double refcyc_per_req_delivery_pre_l = 0; |
| 1019 | double refcyc_per_req_delivery_pre_c = 0; |
| 1020 | double refcyc_per_req_delivery_l = 0; |
| 1021 | double refcyc_per_req_delivery_c = 0; |
| 1022 | |
| 1023 | unsigned int full_recout_width = 0; |
| 1024 | double refcyc_per_req_delivery_pre_cur0 = 0; |
| 1025 | double refcyc_per_req_delivery_cur0 = 0; |
| 1026 | double refcyc_per_req_delivery_pre_cur1 = 0; |
| 1027 | double refcyc_per_req_delivery_cur1 = 0; |
| 1028 | |
| 1029 | unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX6] = { 0 }; |
| 1030 | |
| 1031 | memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs))__builtin_memset((disp_dlg_regs), (0), (sizeof(*disp_dlg_regs ))); |
| 1032 | memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs))__builtin_memset((disp_ttu_regs), (0), (sizeof(*disp_ttu_regs ))); |
| 1033 | |
| 1034 | dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en){do { } while(0); }; |
| 1035 | dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en){do { } while(0); }; |
| 1036 | dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en){do { } while(0); }; |
| 1037 | dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos){do { } while(0); }; |
| 1038 | dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support){do { } while(0); }; |
| 1039 | |
| 1040 | dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz){do { } while(0); }; |
| 1041 | dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz){do { } while(0); }; |
| 1042 | dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz){do { } while(0); }; |
| 1043 | dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz){do { } while(0); }; |
| 1044 | dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced){do { } while(0); }; |
| 1045 | ASSERT(ref_freq_to_pix_freq < 4.0)do { if (({ static int __warned; int __ret = !!(!(ref_freq_to_pix_freq < 4.0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(ref_freq_to_pix_freq < 4.0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1045); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1046 | |
| 1047 | disp_dlg_regs->ref_freq_to_pix_freq = |
| 1048 | (unsigned int)(ref_freq_to_pix_freq * dml_pow(2, 19)); |
| 1049 | disp_dlg_regs->refcyc_per_htotal = (unsigned int)(ref_freq_to_pix_freq * (double)htotal |
| 1050 | * dml_pow(2, 8)); |
| 1051 | disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits |
| 1052 | |
| 1053 | min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; |
| 1054 | t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); |
| 1055 | min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1056 | |
| 1057 | min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double)htotal; |
| 1058 | dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; |
| 1059 | |
| 1060 | disp_dlg_regs->min_dst_y_next_start = (unsigned int)(((double)dlg_vblank_start |
| 1061 | ) * dml_pow(2, 2)); |
| 1062 | ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))) ; if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1062); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1063 | |
| 1064 | dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n",{do { } while(0); } |
| 1065 | __func__,{do { } while(0); } |
| 1066 | min_dcfclk_mhz){do { } while(0); }; |
| 1067 | dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n",{do { } while(0); } |
| 1068 | __func__,{do { } while(0); } |
| 1069 | min_ttu_vblank){do { } while(0); }; |
| 1070 | dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n",{do { } while(0); } |
| 1071 | __func__,{do { } while(0); } |
| 1072 | min_dst_y_ttu_vblank){do { } while(0); }; |
| 1073 | dml_print("DML_DLG: %s: t_calc_us = %3.2f\n",{do { } while(0); } |
| 1074 | __func__,{do { } while(0); } |
| 1075 | t_calc_us){do { } while(0); }; |
| 1076 | dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",{do { } while(0); } |
| 1077 | __func__,{do { } while(0); } |
| 1078 | disp_dlg_regs->min_dst_y_next_start){do { } while(0); }; |
| 1079 | dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n",{do { } while(0); } |
| 1080 | __func__,{do { } while(0); } |
| 1081 | ref_freq_to_pix_freq){do { } while(0); }; |
| 1082 | |
| 1083 | // ------------------------- |
| 1084 | // Section 1.15.2.2: Prefetch, Active and TTU |
| 1085 | // ------------------------- |
| 1086 | // Prefetch Calc |
| 1087 | // Source |
| 1088 | // dcc_en = src.dcc; |
| 1089 | dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); |
| 1090 | mode_422 = false0; // TODO |
| 1091 | access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed |
| 1092 | vp_height_l = src->viewport_height; |
| 1093 | vp_width_l = src->viewport_width; |
| 1094 | vp_height_c = src->viewport_height_c; |
| 1095 | vp_width_c = src->viewport_width_c; |
| 1096 | |
| 1097 | // Scaling |
| 1098 | htaps_l = taps->htaps; |
| 1099 | htaps_c = taps->htaps_c; |
| 1100 | hratio_l = scl->hscl_ratio; |
| 1101 | hratio_c = scl->hscl_ratio_c; |
| 1102 | vratio_l = scl->vscl_ratio; |
| 1103 | vratio_c = scl->vscl_ratio_c; |
| 1104 | scl_enable = scl->scl_enable; |
| 1105 | |
| 1106 | line_time_in_us = (htotal / pclk_freq_in_mhz); |
| 1107 | swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; |
| 1108 | dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; |
| 1109 | swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; |
| 1110 | dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; |
| 1111 | |
| 1112 | meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; |
| 1113 | meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; |
| 1114 | vupdate_offset = dst->vupdate_offset; |
| 1115 | vupdate_width = dst->vupdate_width; |
| 1116 | vready_offset = dst->vready_offset; |
| 1117 | |
| 1118 | dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; |
| 1119 | dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; |
| 1120 | |
| 1121 | if (scl_enable) |
| 1122 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; |
| 1123 | else |
| 1124 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; |
| 1125 | |
| 1126 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter |
| 1127 | + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; |
| 1128 | |
| 1129 | if (dout->dsc_enable) { |
| 1130 | double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1131 | |
| 1132 | dispclk_delay_subtotal += dsc_delay; |
| 1133 | } |
| 1134 | |
| 1135 | pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz |
| 1136 | + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; |
| 1137 | |
| 1138 | vstartup_start = dst->vstartup_start; |
| 1139 | if (interlaced) { |
| 1140 | if (vstartup_start / 2.0 |
| 1141 | - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal |
| 1142 | <= vblank_end / 2.0) |
| 1143 | disp_dlg_regs->vready_after_vcount0 = 1; |
| 1144 | else |
| 1145 | disp_dlg_regs->vready_after_vcount0 = 0; |
| 1146 | } else { |
| 1147 | if (vstartup_start |
| 1148 | - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal |
| 1149 | <= vblank_end) |
| 1150 | disp_dlg_regs->vready_after_vcount0 = 1; |
| 1151 | else |
| 1152 | disp_dlg_regs->vready_after_vcount0 = 0; |
| 1153 | } |
| 1154 | |
| 1155 | // TODO: Where is this coming from? |
| 1156 | if (interlaced) |
| 1157 | vstartup_start = vstartup_start / 2; |
| 1158 | |
| 1159 | // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? |
| 1160 | if (vstartup_start >= min_vblank) { |
| 1161 | dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",{do { } while(0); } |
| 1162 | __func__,{do { } while(0); } |
| 1163 | vblank_start,{do { } while(0); } |
| 1164 | vblank_end){do { } while(0); }; |
| 1165 | dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",{do { } while(0); } |
| 1166 | __func__,{do { } while(0); } |
| 1167 | vstartup_start,{do { } while(0); } |
| 1168 | min_vblank){do { } while(0); }; |
| 1169 | min_vblank = vstartup_start + 1; |
| 1170 | dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",{do { } while(0); } |
| 1171 | __func__,{do { } while(0); } |
| 1172 | vstartup_start,{do { } while(0); } |
| 1173 | min_vblank){do { } while(0); }; |
| 1174 | } |
| 1175 | |
| 1176 | dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1177 | dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1178 | |
| 1179 | // do some adjustment on the dst_after scaler to account for odm combine mode |
| 1180 | dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n",{do { } while(0); } |
| 1181 | __func__,{do { } while(0); } |
| 1182 | dst_x_after_scaler){do { } while(0); }; |
| 1183 | dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n",{do { } while(0); } |
| 1184 | __func__,{do { } while(0); } |
| 1185 | dst_y_after_scaler){do { } while(0); }; |
| 1186 | |
| 1187 | // need to figure out which side of odm combine we're in |
| 1188 | if (dst->odm_combine) { |
| 1189 | // figure out which pipes go together |
| 1190 | bool_Bool visited[DC__NUM_PIPES__MAX6] = { false0 }; |
| 1191 | unsigned int i, j, k; |
| 1192 | |
| 1193 | for (k = 0; k < num_pipes; ++k) { |
| 1194 | visited[k] = false0; |
| 1195 | pipe_index_in_combine[k] = 0; |
| 1196 | } |
| 1197 | |
| 1198 | for (i = 0; i < num_pipes; i++) { |
| 1199 | if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) { |
| 1200 | |
| 1201 | unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp; |
| 1202 | unsigned int grp_idx = 0; |
| 1203 | |
| 1204 | for (j = i; j < num_pipes; j++) { |
| 1205 | if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp |
| 1206 | && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) { |
| 1207 | pipe_index_in_combine[j] = grp_idx; |
| 1208 | dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx){do { } while(0); }; |
| 1209 | grp_idx++; |
| 1210 | visited[j] = true1; |
| 1211 | } |
| 1212 | } |
| 1213 | } |
| 1214 | } |
| 1215 | |
| 1216 | } |
| 1217 | |
| 1218 | if (dst->odm_combine == dm_odm_combine_mode_disabled) { |
| 1219 | disp_dlg_regs->refcyc_h_blank_end = (unsigned int)((double) hblank_end * ref_freq_to_pix_freq); |
| 1220 | } else { |
| 1221 | unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4 |
| 1222 | unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; |
| 1223 | disp_dlg_regs->refcyc_h_blank_end = (unsigned int)(((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); |
| 1224 | } |
| 1225 | ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1225); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1226 | |
| 1227 | dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal){do { } while(0); }; |
| 1228 | dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n",{do { } while(0); } |
| 1229 | __func__,{do { } while(0); } |
| 1230 | pixel_rate_delay_subtotal){do { } while(0); }; |
| 1231 | dml_print("DML_DLG: %s: dst_x_after_scaler[%d] = %d\n",{do { } while(0); } |
| 1232 | __func__,{do { } while(0); } |
| 1233 | pipe_idx,{do { } while(0); } |
| 1234 | dst_x_after_scaler){do { } while(0); }; |
| 1235 | dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n",{do { } while(0); } |
| 1236 | __func__,{do { } while(0); } |
| 1237 | pipe_idx,{do { } while(0); } |
| 1238 | dst_y_after_scaler){do { } while(0); }; |
| 1239 | |
| 1240 | // Lwait |
| 1241 | // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? |
| 1242 | line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us; |
| 1243 | if (cstate_en) |
| 1244 | line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); |
| 1245 | if (pstate_en) |
| 1246 | line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us |
| 1247 | + mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? |
| 1248 | line_wait); |
| 1249 | line_wait = line_wait / line_time_in_us; |
| 1250 | |
| 1251 | dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1252 | dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch){do { } while(0); }; |
| 1253 | |
| 1254 | dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, |
| 1255 | e2e_pipe_param, |
| 1256 | num_pipes, |
| 1257 | pipe_idx); |
| 1258 | dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, |
| 1259 | e2e_pipe_param, |
| 1260 | num_pipes, |
| 1261 | pipe_idx); |
| 1262 | dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1263 | dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1264 | |
| 1265 | max_dst_y_per_vm_vblank = 32.0; //U5.2 |
| 1266 | max_dst_y_per_row_vblank = 16.0; //U4.2 |
| 1267 | |
| 1268 | // magic! |
| 1269 | if (htotal <= 75) { |
| 1270 | min_vblank = 300; |
| 1271 | max_dst_y_per_vm_vblank = 100.0; |
| 1272 | max_dst_y_per_row_vblank = 100.0; |
| 1273 | } |
| 1274 | |
| 1275 | dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip){do { } while(0); }; |
| 1276 | dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip){do { } while(0); }; |
| 1277 | dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank){do { } while(0); }; |
| 1278 | dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank){do { } while(0); }; |
| 1279 | |
| 1280 | ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)do { if (({ static int __warned; int __ret = !!(!(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1280); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1281 | ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank)do { if (({ static int __warned; int __ret = !!(!(dst_y_per_row_vblank < max_dst_y_per_row_vblank)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dst_y_per_row_vblank < max_dst_y_per_row_vblank)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1281); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1282 | |
| 1283 | ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))do { if (({ static int __warned; int __ret = !!(!(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1283); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1284 | lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); |
| 1285 | |
| 1286 | dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw){do { } while(0); }; |
| 1287 | |
| 1288 | vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1289 | vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
| 1290 | |
| 1291 | dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l){do { } while(0); }; |
| 1292 | dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c){do { } while(0); }; |
| 1293 | |
| 1294 | // Active |
| 1295 | req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; |
| 1296 | req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; |
| 1297 | meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; |
| 1298 | meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; |
| 1299 | swath_width_pixels_ub_l = 0; |
| 1300 | swath_width_pixels_ub_c = 0; |
| 1301 | scaler_rec_in_width_l = 0; |
| 1302 | scaler_rec_in_width_c = 0; |
| 1303 | dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; |
| 1304 | dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; |
| 1305 | |
| 1306 | if (mode_422) { |
| 1307 | swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element |
| 1308 | swath_width_pixels_ub_c = swath_width_ub_c * 2; |
| 1309 | } else { |
| 1310 | swath_width_pixels_ub_l = swath_width_ub_l * 1; |
| 1311 | swath_width_pixels_ub_c = swath_width_ub_c * 1; |
| 1312 | } |
| 1313 | |
| 1314 | hscale_pixel_rate_l = 0.; |
| 1315 | hscale_pixel_rate_c = 0.; |
| 1316 | min_hratio_fact_l = 1.0; |
| 1317 | min_hratio_fact_c = 1.0; |
Value stored to 'min_hratio_fact_c' is never read | |
| 1318 | |
| 1319 | if (hratio_l <= 1) |
| 1320 | min_hratio_fact_l = 2.0; |
| 1321 | else if (htaps_l <= 6) { |
| 1322 | if ((hratio_l * 2.0) > 4.0) |
| 1323 | min_hratio_fact_l = 4.0; |
| 1324 | else |
| 1325 | min_hratio_fact_l = hratio_l * 2.0; |
| 1326 | } else { |
| 1327 | if (hratio_l > 4.0) |
| 1328 | min_hratio_fact_l = 4.0; |
| 1329 | else |
| 1330 | min_hratio_fact_l = hratio_l; |
| 1331 | } |
| 1332 | |
| 1333 | hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; |
| 1334 | |
| 1335 | if (hratio_c <= 1) |
| 1336 | min_hratio_fact_c = 2.0; |
| 1337 | else if (htaps_c <= 6) { |
| 1338 | if ((hratio_c * 2.0) > 4.0) |
| 1339 | min_hratio_fact_c = 4.0; |
| 1340 | else |
| 1341 | min_hratio_fact_c = hratio_c * 2.0; |
| 1342 | } else { |
| 1343 | if (hratio_c > 4.0) |
| 1344 | min_hratio_fact_c = 4.0; |
| 1345 | else |
| 1346 | min_hratio_fact_c = hratio_c; |
| 1347 | } |
| 1348 | |
| 1349 | hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; |
| 1350 | |
| 1351 | refcyc_per_line_delivery_pre_l = 0.; |
| 1352 | refcyc_per_line_delivery_pre_c = 0.; |
| 1353 | refcyc_per_line_delivery_l = 0.; |
| 1354 | refcyc_per_line_delivery_c = 0.; |
| 1355 | |
| 1356 | refcyc_per_req_delivery_pre_l = 0.; |
| 1357 | refcyc_per_req_delivery_pre_c = 0.; |
| 1358 | refcyc_per_req_delivery_l = 0.; |
| 1359 | refcyc_per_req_delivery_c = 0.; |
| 1360 | |
| 1361 | full_recout_width = 0; |
| 1362 | // In ODM |
| 1363 | if (src->is_hsplit) { |
| 1364 | // This "hack" is only allowed (and valid) for MPC combine. In ODM |
| 1365 | // combine, you MUST specify the full_recout_width...according to Oswin |
| 1366 | if (dst->full_recout_width == 0 && !dst->odm_combine) { |
| 1367 | dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",{do { } while(0); } |
| 1368 | __func__){do { } while(0); }; |
| 1369 | full_recout_width = dst->recout_width * 2; // assume half split for dcn1 |
| 1370 | } else |
| 1371 | full_recout_width = dst->full_recout_width; |
| 1372 | } else |
| 1373 | full_recout_width = dst->recout_width; |
| 1374 | |
| 1375 | // As of DCN2, mpc_combine and odm_combine are mutually exclusive |
| 1376 | refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, |
| 1377 | refclk_freq_in_mhz, |
| 1378 | pclk_freq_in_mhz, |
| 1379 | dst->odm_combine, |
| 1380 | full_recout_width, |
| 1381 | dst->hactive, |
| 1382 | vratio_pre_l, |
| 1383 | hscale_pixel_rate_l, |
| 1384 | swath_width_pixels_ub_l, |
| 1385 | 1); // per line |
| 1386 | |
| 1387 | refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, |
| 1388 | refclk_freq_in_mhz, |
| 1389 | pclk_freq_in_mhz, |
| 1390 | dst->odm_combine, |
| 1391 | full_recout_width, |
| 1392 | dst->hactive, |
| 1393 | vratio_l, |
| 1394 | hscale_pixel_rate_l, |
| 1395 | swath_width_pixels_ub_l, |
| 1396 | 1); // per line |
| 1397 | |
| 1398 | dml_print("DML_DLG: %s: full_recout_width = %d\n",{do { } while(0); } |
| 1399 | __func__,{do { } while(0); } |
| 1400 | full_recout_width){do { } while(0); }; |
| 1401 | dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n",{do { } while(0); } |
| 1402 | __func__,{do { } while(0); } |
| 1403 | hscale_pixel_rate_l){do { } while(0); }; |
| 1404 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",{do { } while(0); } |
| 1405 | __func__,{do { } while(0); } |
| 1406 | refcyc_per_line_delivery_pre_l){do { } while(0); }; |
| 1407 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n",{do { } while(0); } |
| 1408 | __func__,{do { } while(0); } |
| 1409 | refcyc_per_line_delivery_l){do { } while(0); }; |
| 1410 | |
| 1411 | if (dual_plane) { |
| 1412 | refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, |
| 1413 | refclk_freq_in_mhz, |
| 1414 | pclk_freq_in_mhz, |
| 1415 | dst->odm_combine, |
| 1416 | full_recout_width, |
| 1417 | dst->hactive, |
| 1418 | vratio_pre_c, |
| 1419 | hscale_pixel_rate_c, |
| 1420 | swath_width_pixels_ub_c, |
| 1421 | 1); // per line |
| 1422 | |
| 1423 | refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, |
| 1424 | refclk_freq_in_mhz, |
| 1425 | pclk_freq_in_mhz, |
| 1426 | dst->odm_combine, |
| 1427 | full_recout_width, |
| 1428 | dst->hactive, |
| 1429 | vratio_c, |
| 1430 | hscale_pixel_rate_c, |
| 1431 | swath_width_pixels_ub_c, |
| 1432 | 1); // per line |
| 1433 | |
| 1434 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",{do { } while(0); } |
| 1435 | __func__,{do { } while(0); } |
| 1436 | refcyc_per_line_delivery_pre_c){do { } while(0); }; |
| 1437 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n",{do { } while(0); } |
| 1438 | __func__,{do { } while(0); } |
| 1439 | refcyc_per_line_delivery_c){do { } while(0); }; |
| 1440 | } |
| 1441 | |
| 1442 | // smehta: this is a hack added until we get the real dml, sorry, need to make progress |
| 1443 | if (src->dynamic_metadata_enable && src->gpuvm) { |
| 1444 | unsigned int levels = mode_lib->ip.gpuvm_max_page_table_levels; |
| 1445 | double ref_cycles; |
| 1446 | |
| 1447 | if (src->hostvm) |
| 1448 | levels = levels * (mode_lib->ip.hostvm_max_page_table_levels+1); |
| 1449 | |
| 1450 | ref_cycles = (levels * mode_lib->soc.urgent_latency_vm_data_only_us) * refclk_freq_in_mhz; |
| 1451 | dml_print("BENyamin: dst_y_prefetch = %f %d %f %f \n",{do { } while(0); } |
| 1452 | ref_cycles, levels, mode_lib->soc.urgent_latency_vm_data_only_us, refclk_freq_in_mhz){do { } while(0); }; |
| 1453 | disp_dlg_regs->refcyc_per_vm_dmdata = (unsigned int) ref_cycles; |
| 1454 | } |
| 1455 | dml_print("BENyamin: dmdta_en vm = %d %d \n",{do { } while(0); } |
| 1456 | src->dynamic_metadata_enable, src->vm){do { } while(0); }; |
| 1457 | // TTU - Luma / Chroma |
| 1458 | if (access_dir) { // vertical access |
| 1459 | scaler_rec_in_width_l = vp_height_l; |
| 1460 | scaler_rec_in_width_c = vp_height_c; |
| 1461 | } else { |
| 1462 | scaler_rec_in_width_l = vp_width_l; |
| 1463 | scaler_rec_in_width_c = vp_width_c; |
| 1464 | } |
| 1465 | |
| 1466 | refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, |
| 1467 | refclk_freq_in_mhz, |
| 1468 | pclk_freq_in_mhz, |
| 1469 | dst->odm_combine, |
| 1470 | full_recout_width, |
| 1471 | dst->hactive, |
| 1472 | vratio_pre_l, |
| 1473 | hscale_pixel_rate_l, |
| 1474 | scaler_rec_in_width_l, |
| 1475 | req_per_swath_ub_l); // per req |
| 1476 | refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, |
| 1477 | refclk_freq_in_mhz, |
| 1478 | pclk_freq_in_mhz, |
| 1479 | dst->odm_combine, |
| 1480 | full_recout_width, |
| 1481 | dst->hactive, |
| 1482 | vratio_l, |
| 1483 | hscale_pixel_rate_l, |
| 1484 | scaler_rec_in_width_l, |
| 1485 | req_per_swath_ub_l); // per req |
| 1486 | |
| 1487 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",{do { } while(0); } |
| 1488 | __func__,{do { } while(0); } |
| 1489 | refcyc_per_req_delivery_pre_l){do { } while(0); }; |
| 1490 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n",{do { } while(0); } |
| 1491 | __func__,{do { } while(0); } |
| 1492 | refcyc_per_req_delivery_l){do { } while(0); }; |
| 1493 | |
| 1494 | ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1494); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1495 | ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_l < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_l < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1495); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1496 | |
| 1497 | if (dual_plane) { |
| 1498 | refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, |
| 1499 | refclk_freq_in_mhz, |
| 1500 | pclk_freq_in_mhz, |
| 1501 | dst->odm_combine, |
| 1502 | full_recout_width, |
| 1503 | dst->hactive, |
| 1504 | vratio_pre_c, |
| 1505 | hscale_pixel_rate_c, |
| 1506 | scaler_rec_in_width_c, |
| 1507 | req_per_swath_ub_c); // per req |
| 1508 | refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, |
| 1509 | refclk_freq_in_mhz, |
| 1510 | pclk_freq_in_mhz, |
| 1511 | dst->odm_combine, |
| 1512 | full_recout_width, |
| 1513 | dst->hactive, |
| 1514 | vratio_c, |
| 1515 | hscale_pixel_rate_c, |
| 1516 | scaler_rec_in_width_c, |
| 1517 | req_per_swath_ub_c); // per req |
| 1518 | |
| 1519 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",{do { } while(0); } |
| 1520 | __func__,{do { } while(0); } |
| 1521 | refcyc_per_req_delivery_pre_c){do { } while(0); }; |
| 1522 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n",{do { } while(0); } |
| 1523 | __func__,{do { } while(0); } |
| 1524 | refcyc_per_req_delivery_c){do { } while(0); }; |
| 1525 | |
| 1526 | ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1526); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1527 | ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_c < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_c < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1527); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1528 | } |
| 1529 | |
| 1530 | // TTU - Cursor |
| 1531 | refcyc_per_req_delivery_pre_cur0 = 0.0; |
| 1532 | refcyc_per_req_delivery_cur0 = 0.0; |
| 1533 | if (src->num_cursors > 0) { |
| 1534 | calculate_ttu_cursor(mode_lib, |
| 1535 | &refcyc_per_req_delivery_pre_cur0, |
| 1536 | &refcyc_per_req_delivery_cur0, |
| 1537 | refclk_freq_in_mhz, |
| 1538 | ref_freq_to_pix_freq, |
| 1539 | hscale_pixel_rate_l, |
| 1540 | scl->hscl_ratio, |
| 1541 | vratio_pre_l, |
| 1542 | vratio_l, |
| 1543 | src->cur0_src_width, |
| 1544 | (enum cursor_bpp)(src->cur0_bpp)); |
| 1545 | } |
| 1546 | |
| 1547 | refcyc_per_req_delivery_pre_cur1 = 0.0; |
| 1548 | refcyc_per_req_delivery_cur1 = 0.0; |
| 1549 | if (src->num_cursors > 1) { |
| 1550 | calculate_ttu_cursor(mode_lib, |
| 1551 | &refcyc_per_req_delivery_pre_cur1, |
| 1552 | &refcyc_per_req_delivery_cur1, |
| 1553 | refclk_freq_in_mhz, |
| 1554 | ref_freq_to_pix_freq, |
| 1555 | hscale_pixel_rate_l, |
| 1556 | scl->hscl_ratio, |
| 1557 | vratio_pre_l, |
| 1558 | vratio_l, |
| 1559 | src->cur1_src_width, |
| 1560 | (enum cursor_bpp)(src->cur1_bpp)); |
| 1561 | } |
| 1562 | |
| 1563 | // TTU - Misc |
| 1564 | // all hard-coded |
| 1565 | |
| 1566 | // Assignment to register structures |
| 1567 | disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line |
| 1568 | ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8)do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_after_scaler < (unsigned int)8)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1568); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1569 | disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk |
| 1570 | ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)) ); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1570); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1571 | disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); |
| 1572 | disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); |
| 1573 | disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2)); |
| 1574 | disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2)); |
| 1575 | disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2)); |
| 1576 | |
| 1577 | disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19)); |
| 1578 | disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19)); |
| 1579 | |
| 1580 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank){do { } while(0); }; |
| 1581 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank){do { } while(0); }; |
| 1582 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip){do { } while(0); }; |
| 1583 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip){do { } while(0); }; |
| 1584 | disp_dlg_regs->refcyc_per_pte_group_vblank_l = |
| 1585 | (unsigned int)(dst_y_per_row_vblank * (double)htotal |
| 1586 | * ref_freq_to_pix_freq / (double)dpte_groups_per_row_ub_l); |
| 1587 | ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1587); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1588 | |
| 1589 | if (dual_plane) { |
| 1590 | disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)(dst_y_per_row_vblank |
| 1591 | * (double)htotal * ref_freq_to_pix_freq |
| 1592 | / (double)dpte_groups_per_row_ub_c); |
| 1593 | ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_cdo { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1594); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0) |
| 1594 | < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1594); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1595 | } |
| 1596 | |
| 1597 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = |
| 1598 | (unsigned int)(dst_y_per_row_vblank * (double)htotal |
| 1599 | * ref_freq_to_pix_freq / (double)meta_chunks_per_row_ub_l); |
| 1600 | ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1600); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1601 | |
| 1602 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = |
| 1603 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now |
| 1604 | |
| 1605 | disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)(dst_y_per_row_flip * htotal |
| 1606 | * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; |
| 1607 | disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)(dst_y_per_row_flip * htotal |
| 1608 | * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; |
| 1609 | |
| 1610 | if (dual_plane) { |
| 1611 | disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)(dst_y_per_row_flip |
| 1612 | * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; |
| 1613 | disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)(dst_y_per_row_flip |
| 1614 | * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; |
| 1615 | } |
| 1616 | |
| 1617 | disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; |
| 1618 | disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; |
| 1619 | disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); |
| 1620 | disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); |
| 1621 | |
| 1622 | // Clamp to max for now |
| 1623 | if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) |
| 1624 | disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; |
| 1625 | |
| 1626 | if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) |
| 1627 | disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; |
| 1628 | |
| 1629 | if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) |
| 1630 | disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; |
| 1631 | |
| 1632 | if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) |
| 1633 | disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; |
| 1634 | |
| 1635 | disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)((double)dpte_row_height_l |
| 1636 | / (double)vratio_l * dml_pow(2, 2)); |
| 1637 | ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1637); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1638 | |
| 1639 | if (dual_plane) { |
| 1640 | disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)((double)dpte_row_height_c |
| 1641 | / (double)vratio_c * dml_pow(2, 2)); |
| 1642 | if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int)dml_pow(2, 17)) { |
| 1643 | dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",{do { } while(0); } |
| 1644 | __func__,{do { } while(0); } |
| 1645 | disp_dlg_regs->dst_y_per_pte_row_nom_c,{do { } while(0); } |
| 1646 | (unsigned int)dml_pow(2, 17) - 1){do { } while(0); }; |
| 1647 | } |
| 1648 | } |
| 1649 | |
| 1650 | disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)((double)meta_row_height_l |
| 1651 | / (double)vratio_l * dml_pow(2, 2)); |
| 1652 | ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1652); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1653 | |
| 1654 | disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now |
| 1655 | |
| 1656 | dml_print("DML: Trow: %fus\n", line_time_in_us * (double)dpte_row_height_l / (double)vratio_l){do { } while(0); }; |
| 1657 | |
| 1658 | disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)((double)dpte_row_height_l |
| 1659 | / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq |
| 1660 | / (double)dpte_groups_per_row_ub_l); |
| 1661 | if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int)dml_pow(2, 23)) |
| 1662 | disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; |
| 1663 | disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)((double)meta_row_height_l |
| 1664 | / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq |
| 1665 | / (double)meta_chunks_per_row_ub_l); |
| 1666 | if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int)dml_pow(2, 23)) |
| 1667 | disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; |
| 1668 | |
| 1669 | if (dual_plane) { |
| 1670 | disp_dlg_regs->refcyc_per_pte_group_nom_c = |
| 1671 | (unsigned int)((double)dpte_row_height_c / (double)vratio_c |
| 1672 | * (double)htotal * ref_freq_to_pix_freq |
| 1673 | / (double)dpte_groups_per_row_ub_c); |
| 1674 | if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int)dml_pow(2, 23)) |
| 1675 | disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; |
| 1676 | |
| 1677 | // TODO: Is this the right calculation? Does htotal need to be halved? |
| 1678 | disp_dlg_regs->refcyc_per_meta_chunk_nom_c = |
| 1679 | (unsigned int)((double)meta_row_height_c / (double)vratio_c |
| 1680 | * (double)htotal * ref_freq_to_pix_freq |
| 1681 | / (double)meta_chunks_per_row_ub_c); |
| 1682 | if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int)dml_pow(2, 23)) |
| 1683 | disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; |
| 1684 | } |
| 1685 | |
| 1686 | disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int)dml_floor(refcyc_per_line_delivery_pre_l, |
| 1687 | 1); |
| 1688 | disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int)dml_floor(refcyc_per_line_delivery_l, |
| 1689 | 1); |
| 1690 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1690); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1691 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1691); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1692 | |
| 1693 | disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int)dml_floor(refcyc_per_line_delivery_pre_c, |
| 1694 | 1); |
| 1695 | disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int)dml_floor(refcyc_per_line_delivery_c, |
| 1696 | 1); |
| 1697 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1697); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1698 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1698); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1699 | |
| 1700 | disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; |
| 1701 | disp_dlg_regs->dst_y_offset_cur0 = 0; |
| 1702 | disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; |
| 1703 | disp_dlg_regs->dst_y_offset_cur1 = 0; |
| 1704 | |
| 1705 | disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off |
| 1706 | |
| 1707 | disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int)(refcyc_per_req_delivery_pre_l |
| 1708 | * dml_pow(2, 10)); |
| 1709 | disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int)(refcyc_per_req_delivery_l |
| 1710 | * dml_pow(2, 10)); |
| 1711 | disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int)(refcyc_per_req_delivery_pre_c |
| 1712 | * dml_pow(2, 10)); |
| 1713 | disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int)(refcyc_per_req_delivery_c |
| 1714 | * dml_pow(2, 10)); |
| 1715 | disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = |
| 1716 | (unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); |
| 1717 | disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int)(refcyc_per_req_delivery_cur0 |
| 1718 | * dml_pow(2, 10)); |
| 1719 | disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = |
| 1720 | (unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); |
| 1721 | disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int)(refcyc_per_req_delivery_cur1 |
| 1722 | * dml_pow(2, 10)); |
| 1723 | disp_ttu_regs->qos_level_low_wm = 0; |
| 1724 | ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->qos_level_low_wm < dml_pow(2, 14))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1724); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1725 | disp_ttu_regs->qos_level_high_wm = (unsigned int)(4.0 * (double)htotal |
| 1726 | * ref_freq_to_pix_freq); |
| 1727 | ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->qos_level_high_wm < dml_pow(2, 14))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1727); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1728 | |
| 1729 | disp_ttu_regs->qos_level_flip = 14; |
| 1730 | disp_ttu_regs->qos_level_fixed_l = 8; |
| 1731 | disp_ttu_regs->qos_level_fixed_c = 8; |
| 1732 | disp_ttu_regs->qos_level_fixed_cur0 = 8; |
| 1733 | disp_ttu_regs->qos_ramp_disable_l = 0; |
| 1734 | disp_ttu_regs->qos_ramp_disable_c = 0; |
| 1735 | disp_ttu_regs->qos_ramp_disable_cur0 = 0; |
| 1736 | |
| 1737 | disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; |
| 1738 | ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->min_ttu_vblank < dml_pow(2, 24))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1738); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1739 | |
| 1740 | print__ttu_regs_st(mode_lib, disp_ttu_regs); |
| 1741 | print__dlg_regs_st(mode_lib, disp_dlg_regs); |
| 1742 | } |
| 1743 | |
| 1744 | void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, |
| 1745 | display_dlg_regs_st *dlg_regs, |
| 1746 | display_ttu_regs_st *ttu_regs, |
| 1747 | const display_e2e_pipe_params_st *e2e_pipe_param, |
| 1748 | const unsigned int num_pipes, |
| 1749 | const unsigned int pipe_idx, |
| 1750 | const bool_Bool cstate_en, |
| 1751 | const bool_Bool pstate_en, |
| 1752 | const bool_Bool vm_en, |
| 1753 | const bool_Bool ignore_viewport_pos, |
| 1754 | const bool_Bool immediate_flip_support) |
| 1755 | { |
| 1756 | display_rq_params_st rq_param = { 0 }; |
| 1757 | display_dlg_sys_params_st dlg_sys_param = { 0 }; |
| 1758 | |
| 1759 | // Get watermark and Tex. |
| 1760 | dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); |
| 1761 | dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, |
| 1762 | e2e_pipe_param, |
| 1763 | num_pipes); |
| 1764 | dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); |
| 1765 | dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); |
| 1766 | dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); |
| 1767 | dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); |
| 1768 | dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, |
| 1769 | e2e_pipe_param, |
| 1770 | num_pipes); |
| 1771 | dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, |
| 1772 | e2e_pipe_param, |
| 1773 | num_pipes); |
| 1774 | |
| 1775 | print__dlg_sys_params_st(mode_lib, &dlg_sys_param); |
| 1776 | |
| 1777 | // system parameter calculation done |
| 1778 | |
| 1779 | dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx){do { } while(0); }; |
| 1780 | dml_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe); |
| 1781 | dml_rq_dlg_get_dlg_params(mode_lib, |
| 1782 | e2e_pipe_param, |
| 1783 | num_pipes, |
| 1784 | pipe_idx, |
| 1785 | dlg_regs, |
| 1786 | ttu_regs, |
| 1787 | rq_param.dlg, |
| 1788 | dlg_sys_param, |
| 1789 | cstate_en, |
| 1790 | pstate_en, |
| 1791 | vm_en, |
| 1792 | ignore_viewport_pos, |
| 1793 | immediate_flip_support); |
| 1794 | dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx){do { } while(0); }; |
| 1795 | } |
| 1796 | |
| 1797 | #endif |