File: | dev/pci/drm/i915/display/i9xx_plane.c |
Warning: | line 1023, column 3 Value stored to 'offset' is never read |
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1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright © 2020 Intel Corporation |
4 | */ |
5 | #include <linux/kernel.h> |
6 | |
7 | #include <drm/drm_atomic_helper.h> |
8 | #include <drm/drm_blend.h> |
9 | #include <drm/drm_fourcc.h> |
10 | |
11 | #include "intel_atomic.h" |
12 | #include "intel_atomic_plane.h" |
13 | #include "intel_de.h" |
14 | #include "intel_display_types.h" |
15 | #include "intel_fb.h" |
16 | #include "intel_fbc.h" |
17 | #include "intel_sprite.h" |
18 | #include "i9xx_plane.h" |
19 | |
20 | /* Primary plane formats for gen <= 3 */ |
21 | static const u32 i8xx_primary_formats[] = { |
22 | DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)), |
23 | DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)), |
24 | DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), |
25 | DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
26 | }; |
27 | |
28 | /* Primary plane formats for ivb (no fp16 due to hw issue) */ |
29 | static const u32 ivb_primary_formats[] = { |
30 | DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)), |
31 | DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), |
32 | DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
33 | DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
34 | DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
35 | DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
36 | }; |
37 | |
38 | /* Primary plane formats for gen >= 4, except ivb */ |
39 | static const u32 i965_primary_formats[] = { |
40 | DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)), |
41 | DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), |
42 | DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
43 | DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
44 | DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
45 | DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
46 | DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)), |
47 | }; |
48 | |
49 | /* Primary plane formats for vlv/chv */ |
50 | static const u32 vlv_primary_formats[] = { |
51 | DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)), |
52 | DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), |
53 | DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
54 | DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
55 | DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
56 | DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
57 | DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
58 | DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
59 | DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
60 | DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
61 | DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)), |
62 | }; |
63 | |
64 | static bool_Bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, |
65 | u32 format, u64 modifier) |
66 | { |
67 | if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (_plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof (struct intel_plane, base) );}), modifier)) |
68 | return false0; |
69 | |
70 | switch (format) { |
71 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
72 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
73 | case DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
74 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
75 | return modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ) || |
76 | modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
77 | default: |
78 | return false0; |
79 | } |
80 | } |
81 | |
82 | static bool_Bool i965_plane_format_mod_supported(struct drm_plane *_plane, |
83 | u32 format, u64 modifier) |
84 | { |
85 | if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (_plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof (struct intel_plane, base) );}), modifier)) |
86 | return false0; |
87 | |
88 | switch (format) { |
89 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
90 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
91 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
92 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
93 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
94 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
95 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
96 | case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
97 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
98 | case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
99 | case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
100 | return modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ) || |
101 | modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
102 | default: |
103 | return false0; |
104 | } |
105 | } |
106 | |
107 | static bool_Bool i9xx_plane_has_fbc(struct drm_i915_privateinteldrm_softc *dev_priv, |
108 | enum i9xx_plane_id i9xx_plane) |
109 | { |
110 | if (!HAS_FBC(dev_priv)((&(dev_priv)->__runtime)->fbc_mask != 0)) |
111 | return false0; |
112 | |
113 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
114 | return i9xx_plane == PLANE_A; /* tied to pipe A */ |
115 | else if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
116 | return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || |
117 | i9xx_plane == PLANE_C; |
118 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
119 | return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; |
120 | else |
121 | return i9xx_plane == PLANE_A; |
122 | } |
123 | |
124 | static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_privateinteldrm_softc *dev_priv, |
125 | enum i9xx_plane_id i9xx_plane) |
126 | { |
127 | if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) |
128 | return dev_priv->display.fbc[INTEL_FBC_A]; |
129 | else |
130 | return NULL((void *)0); |
131 | } |
132 | |
133 | static bool_Bool i9xx_plane_has_windowing(struct intel_plane *plane) |
134 | { |
135 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
136 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
137 | |
138 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
139 | return i9xx_plane == PLANE_B; |
140 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 5 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
141 | return false0; |
142 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 4) |
143 | return i9xx_plane == PLANE_C; |
144 | else |
145 | return i9xx_plane == PLANE_B || |
146 | i9xx_plane == PLANE_C; |
147 | } |
148 | |
149 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
150 | const struct intel_plane_state *plane_state) |
151 | { |
152 | struct drm_i915_privateinteldrm_softc *dev_priv = |
153 | to_i915(plane_state->uapi.plane->dev); |
154 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
155 | unsigned int rotation = plane_state->hw.rotation; |
156 | u32 dspcntr; |
157 | |
158 | dspcntr = DISP_ENABLE((u32)((1UL << (31)) + 0)); |
159 | |
160 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) || IS_IRONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IRONLAKE) || |
161 | IS_SANDYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) || IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
162 | dspcntr |= DISP_TRICKLE_FEED_DISABLE((u32)((1UL << (14)) + 0)); |
163 | |
164 | switch (fb->format->format) { |
165 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
166 | dspcntr |= DISP_FORMAT_8BPP((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(2) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
167 | break; |
168 | case DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
169 | dspcntr |= DISP_FORMAT_BGRX555((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(4) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
170 | break; |
171 | case DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
172 | dspcntr |= DISP_FORMAT_BGRA555((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(3) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
173 | break; |
174 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
175 | dspcntr |= DISP_FORMAT_BGRX565((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(5) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
176 | break; |
177 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
178 | dspcntr |= DISP_FORMAT_BGRX888((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(6) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
179 | break; |
180 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
181 | dspcntr |= DISP_FORMAT_RGBX888((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(14) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
182 | break; |
183 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
184 | dspcntr |= DISP_FORMAT_BGRA888((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(7) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
185 | break; |
186 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
187 | dspcntr |= DISP_FORMAT_RGBA888((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(15) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
188 | break; |
189 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
190 | dspcntr |= DISP_FORMAT_BGRX101010((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(10) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
191 | break; |
192 | case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
193 | dspcntr |= DISP_FORMAT_RGBX101010((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(8) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
194 | break; |
195 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
196 | dspcntr |= DISP_FORMAT_BGRA101010((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(11) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
197 | break; |
198 | case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
199 | dspcntr |= DISP_FORMAT_RGBA101010((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(9) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
200 | break; |
201 | case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
202 | dspcntr |= DISP_FORMAT_RGBX161616((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(12) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )); |
203 | break; |
204 | default: |
205 | MISSING_CASE(fb->format->format)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb->format->format", (long)(fb->format->format )); __builtin_expect(!!(__ret), 0); }); |
206 | return 0; |
207 | } |
208 | |
209 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4 && |
210 | fb->modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) |
211 | dspcntr |= DISP_TILED((u32)((1UL << (10)) + 0)); |
212 | |
213 | if (rotation & DRM_MODE_ROTATE_180(1<<2)) |
214 | dspcntr |= DISP_ROTATE_180((u32)((1UL << (15)) + 0)); |
215 | |
216 | if (rotation & DRM_MODE_REFLECT_X(1<<4)) |
217 | dspcntr |= DISP_MIRROR((u32)((1UL << (8)) + 0)); |
218 | |
219 | return dspcntr; |
220 | } |
221 | |
222 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
223 | { |
224 | struct drm_i915_privateinteldrm_softc *dev_priv = |
225 | to_i915(plane_state->uapi.plane->dev); |
226 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
227 | int src_x, src_y, src_w; |
228 | u32 offset; |
229 | int ret; |
230 | |
231 | ret = intel_plane_compute_gtt(plane_state); |
232 | if (ret) |
233 | return ret; |
234 | |
235 | if (!plane_state->uapi.visible) |
236 | return 0; |
237 | |
238 | src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
239 | src_x = plane_state->uapi.src.x1 >> 16; |
240 | src_y = plane_state->uapi.src.y1 >> 16; |
241 | |
242 | /* Undocumented hardware limit on i965/g4x/vlv/chv */ |
243 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && fb->format->cpp[0] == 8 && src_w > 2048) |
244 | return -EINVAL22; |
245 | |
246 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
247 | |
248 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
249 | offset = intel_plane_compute_aligned_offset(&src_x, &src_y, |
250 | plane_state, 0); |
251 | else |
252 | offset = 0; |
253 | |
254 | /* |
255 | * When using an X-tiled surface the plane starts to |
256 | * misbehave if the x offset + width exceeds the stride. |
257 | * hsw/bdw: underrun galore |
258 | * ilk/snb/ivb: wrap to the next tile row mid scanout |
259 | * i965/g4x: so far appear immune to this |
260 | * vlv/chv: TODO check |
261 | * |
262 | * Linear surfaces seem to work just fine, even on hsw/bdw |
263 | * despite them not using the linear offset anymore. |
264 | */ |
265 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) { |
266 | u32 alignment = intel_surf_alignment(fb, 0); |
267 | int cpp = fb->format->cpp[0]; |
268 | |
269 | while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { |
270 | if (offset == 0) { |
271 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Unable to find suitable display surface offset due to X-tiling\n" ) |
272 | "Unable to find suitable display surface offset due to X-tiling\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Unable to find suitable display surface offset due to X-tiling\n" ); |
273 | return -EINVAL22; |
274 | } |
275 | |
276 | offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0, |
277 | offset, offset - alignment); |
278 | } |
279 | } |
280 | |
281 | /* |
282 | * Put the final coordinates back so that the src |
283 | * coordinate checks will see the right values. |
284 | */ |
285 | drm_rect_translate_to(&plane_state->uapi.src, |
286 | src_x << 16, src_y << 16); |
287 | |
288 | /* HSW/BDW do this automagically in hardware */ |
289 | if (!IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && !IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
290 | unsigned int rotation = plane_state->hw.rotation; |
291 | int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
292 | int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; |
293 | |
294 | if (rotation & DRM_MODE_ROTATE_180(1<<2)) { |
295 | src_x += src_w - 1; |
296 | src_y += src_h - 1; |
297 | } else if (rotation & DRM_MODE_REFLECT_X(1<<4)) { |
298 | src_x += src_w - 1; |
299 | } |
300 | } |
301 | |
302 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
303 | drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095)({ int __ret = !!((src_x > 8191 || src_y > 4095)); if ( __ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "src_x > 8191 || src_y > 4095" ")"); __builtin_expect(!!(__ret), 0); }); |
304 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4 && |
305 | fb->modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) { |
306 | drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095)({ int __ret = !!((src_x > 4095 || src_y > 4095)); if ( __ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "src_x > 4095 || src_y > 4095" ")"); __builtin_expect(!!(__ret), 0); }); |
307 | } |
308 | |
309 | plane_state->view.color_plane[0].offset = offset; |
310 | plane_state->view.color_plane[0].x = src_x; |
311 | plane_state->view.color_plane[0].y = src_y; |
312 | |
313 | return 0; |
314 | } |
315 | |
316 | static int |
317 | i9xx_plane_check(struct intel_crtc_state *crtc_state, |
318 | struct intel_plane_state *plane_state) |
319 | { |
320 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
321 | int ret; |
322 | |
323 | ret = chv_plane_check_rotation(plane_state); |
324 | if (ret) |
325 | return ret; |
326 | |
327 | ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, |
328 | DRM_PLANE_NO_SCALING(1<<16), |
329 | DRM_PLANE_NO_SCALING(1<<16), |
330 | i9xx_plane_has_windowing(plane)); |
331 | if (ret) |
332 | return ret; |
333 | |
334 | ret = i9xx_check_plane_surface(plane_state); |
335 | if (ret) |
336 | return ret; |
337 | |
338 | if (!plane_state->uapi.visible) |
339 | return 0; |
340 | |
341 | ret = intel_plane_check_src_coordinates(plane_state); |
342 | if (ret) |
343 | return ret; |
344 | |
345 | plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); |
346 | |
347 | return 0; |
348 | } |
349 | |
350 | static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) |
351 | { |
352 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
353 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
354 | u32 dspcntr = 0; |
355 | |
356 | if (crtc_state->gamma_enable) |
357 | dspcntr |= DISP_PIPE_GAMMA_ENABLE((u32)((1UL << (30)) + 0)); |
358 | |
359 | if (crtc_state->csc_enable) |
360 | dspcntr |= DISP_PIPE_CSC_ENABLE((u32)((1UL << (24)) + 0)); |
361 | |
362 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 5) |
363 | dspcntr |= DISP_PIPE_SEL(crtc->pipe)((u32)((((typeof(((u32)((((~0UL) >> (64 - (25) - 1)) & ((~0UL) << (24))) + 0))))((crtc->pipe)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (25) - 1)) & ((~0UL) << (24))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (25 ) - 1)) & ((~0UL) << (24))) + 0)))) + 0 + 0 + 0 + 0 )); |
364 | |
365 | return dspcntr; |
366 | } |
367 | |
368 | static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, |
369 | const struct intel_plane_state *plane_state, |
370 | unsigned int *num, unsigned int *den) |
371 | { |
372 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
373 | unsigned int cpp = fb->format->cpp[0]; |
374 | |
375 | /* |
376 | * g4x bspec says 64bpp pixel rate can't exceed 80% |
377 | * of cdclk when the sprite plane is enabled on the |
378 | * same pipe. ilk/snb bspec says 64bpp pixel rate is |
379 | * never allowed to exceed 80% of cdclk. Let's just go |
380 | * with the ilk/snb limit always. |
381 | */ |
382 | if (cpp == 8) { |
383 | *num = 10; |
384 | *den = 8; |
385 | } else { |
386 | *num = 1; |
387 | *den = 1; |
388 | } |
389 | } |
390 | |
391 | static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, |
392 | const struct intel_plane_state *plane_state) |
393 | { |
394 | unsigned int pixel_rate; |
395 | unsigned int num, den; |
396 | |
397 | /* |
398 | * Note that crtc_state->pixel_rate accounts for both |
399 | * horizontal and vertical panel fitter downscaling factors. |
400 | * Pre-HSW bspec tells us to only consider the horizontal |
401 | * downscaling factor here. We ignore that and just consider |
402 | * both for simplicity. |
403 | */ |
404 | pixel_rate = crtc_state->pixel_rate; |
405 | |
406 | i9xx_plane_ratio(crtc_state, plane_state, &num, &den); |
407 | |
408 | /* two pixels per clock with double wide pipe */ |
409 | if (crtc_state->double_wide) |
410 | den *= 2; |
411 | |
412 | return DIV_ROUND_UP(pixel_rate * num, den)(((pixel_rate * num) + ((den) - 1)) / (den)); |
413 | } |
414 | |
415 | static void i9xx_plane_update_noarm(struct intel_plane *plane, |
416 | const struct intel_crtc_state *crtc_state, |
417 | const struct intel_plane_state *plane_state) |
418 | { |
419 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
420 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
421 | |
422 | intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70188)) }), |
423 | plane_state->view.color_plane[0].mapping_stride); |
424 | |
425 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 4) { |
426 | int crtc_x = plane_state->uapi.dst.x1; |
427 | int crtc_y = plane_state->uapi.dst.y1; |
428 | int crtc_w = drm_rect_width(&plane_state->uapi.dst); |
429 | int crtc_h = drm_rect_height(&plane_state->uapi.dst); |
430 | |
431 | /* |
432 | * PLANE_A doesn't actually have a full window |
433 | * generator but let's assume we still need to |
434 | * program whatever is there. |
435 | */ |
436 | intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x7018C)) }), |
437 | DISP_POS_Y(crtc_y)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))((crtc_y)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )) | DISP_POS_X(crtc_x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))))((crtc_x)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (15 ) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0) )); |
438 | intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70190)) }), |
439 | DISP_HEIGHT(crtc_h - 1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))((crtc_h - 1)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )) | DISP_WIDTH(crtc_w - 1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))))((crtc_w - 1)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (15 ) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0) )); |
440 | } |
441 | } |
442 | |
443 | static void i9xx_plane_update_arm(struct intel_plane *plane, |
444 | const struct intel_crtc_state *crtc_state, |
445 | const struct intel_plane_state *plane_state) |
446 | { |
447 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
448 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
449 | int x = plane_state->view.color_plane[0].x; |
450 | int y = plane_state->view.color_plane[0].y; |
451 | u32 dspcntr, dspaddr_offset, linear_offset; |
452 | |
453 | dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); |
454 | |
455 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
456 | |
457 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
458 | dspaddr_offset = plane_state->view.color_plane[0].offset; |
459 | else |
460 | dspaddr_offset = linear_offset; |
461 | |
462 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && i9xx_plane == PLANE_B) { |
463 | int crtc_x = plane_state->uapi.dst.x1; |
464 | int crtc_y = plane_state->uapi.dst.y1; |
465 | int crtc_w = drm_rect_width(&plane_state->uapi.dst); |
466 | int crtc_h = drm_rect_height(&plane_state->uapi.dst); |
467 | |
468 | intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv) ->__info)->display.mmio_offset) + (0x60a08)) }), |
469 | PRIM_POS_Y(crtc_y)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))((crtc_y)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )) | PRIM_POS_X(crtc_x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))))((crtc_x)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (15 ) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0) )); |
470 | intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv) ->__info)->display.mmio_offset) + (0x60a0c)) }), |
471 | PRIM_HEIGHT(crtc_h - 1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))((crtc_h - 1)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )) | PRIM_WIDTH(crtc_w - 1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))))((crtc_w - 1)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (15 ) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0) )); |
472 | intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv) ->__info)->display.mmio_offset) + (0x60a10)) }), 0); |
473 | } |
474 | |
475 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
476 | intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x701A4)) }), |
477 | DISP_OFFSET_Y(y)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))((y)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )) | DISP_OFFSET_X(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))))((x)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (15 ) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0) )); |
478 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
479 | intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70184)) }), |
480 | linear_offset); |
481 | intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x701A4)) }), |
482 | DISP_OFFSET_Y(y)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))((y)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )) | DISP_OFFSET_X(x)((u32)((((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))))((x)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (15 ) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0) )); |
483 | } |
484 | |
485 | /* |
486 | * The control register self-arms if the plane was previously |
487 | * disabled. Try to make the plane enable atomic by writing |
488 | * the control register just before the surface register. |
489 | */ |
490 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70180)) }), dspcntr); |
491 | |
492 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
493 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x7019C)) }), |
494 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); |
495 | else |
496 | intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70184)) }), |
497 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); |
498 | } |
499 | |
500 | static void i830_plane_update_arm(struct intel_plane *plane, |
501 | const struct intel_crtc_state *crtc_state, |
502 | const struct intel_plane_state *plane_state) |
503 | { |
504 | /* |
505 | * On i830/i845 all registers are self-arming [ALM040]. |
506 | * |
507 | * Additional breakage on i830 causes register reads to return |
508 | * the last latched value instead of the last written value [ALM026]. |
509 | */ |
510 | i9xx_plane_update_noarm(plane, crtc_state, plane_state); |
511 | i9xx_plane_update_arm(plane, crtc_state, plane_state); |
512 | } |
513 | |
514 | static void i9xx_plane_disable_arm(struct intel_plane *plane, |
515 | const struct intel_crtc_state *crtc_state) |
516 | { |
517 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
518 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
519 | u32 dspcntr; |
520 | |
521 | /* |
522 | * DSPCNTR pipe gamma enable on g4x+ and pipe csc |
523 | * enable on ilk+ affect the pipe bottom color as |
524 | * well, so we must configure them even if the plane |
525 | * is disabled. |
526 | * |
527 | * On pre-g4x there is no way to gamma correct the |
528 | * pipe bottom color but we'll keep on doing this |
529 | * anyway so that the crtc state readout works correctly. |
530 | */ |
531 | dspcntr = i9xx_plane_ctl_crtc(crtc_state); |
532 | |
533 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70180)) }), dspcntr); |
534 | |
535 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
536 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x7019C)) }), 0); |
537 | else |
538 | intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70184)) }), 0); |
539 | } |
540 | |
541 | static void |
542 | g4x_primary_async_flip(struct intel_plane *plane, |
543 | const struct intel_crtc_state *crtc_state, |
544 | const struct intel_plane_state *plane_state, |
545 | bool_Bool async_flip) |
546 | { |
547 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
548 | u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); |
549 | u32 dspaddr_offset = plane_state->view.color_plane[0].offset; |
550 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
551 | |
552 | if (async_flip) |
553 | dspcntr |= DISP_ASYNC_FLIP((u32)((1UL << (9)) + 0)); |
554 | |
555 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70180)) }), dspcntr); |
556 | |
557 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x7019C)) }), |
558 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); |
559 | } |
560 | |
561 | static void |
562 | vlv_primary_async_flip(struct intel_plane *plane, |
563 | const struct intel_crtc_state *crtc_state, |
564 | const struct intel_plane_state *plane_state, |
565 | bool_Bool async_flip) |
566 | { |
567 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
568 | u32 dspaddr_offset = plane_state->view.color_plane[0].offset; |
569 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
570 | |
571 | intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x7017C)) }), |
572 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); |
573 | } |
574 | |
575 | static void |
576 | bdw_primary_enable_flip_done(struct intel_plane *plane) |
577 | { |
578 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
579 | enum pipe pipe = plane->pipe; |
580 | |
581 | spin_lock_irq(&i915->irq_lock)mtx_enter(&i915->irq_lock); |
582 | bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE(1 << 4)); |
583 | spin_unlock_irq(&i915->irq_lock)mtx_leave(&i915->irq_lock); |
584 | } |
585 | |
586 | static void |
587 | bdw_primary_disable_flip_done(struct intel_plane *plane) |
588 | { |
589 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
590 | enum pipe pipe = plane->pipe; |
591 | |
592 | spin_lock_irq(&i915->irq_lock)mtx_enter(&i915->irq_lock); |
593 | bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE(1 << 4)); |
594 | spin_unlock_irq(&i915->irq_lock)mtx_leave(&i915->irq_lock); |
595 | } |
596 | |
597 | static void |
598 | ivb_primary_enable_flip_done(struct intel_plane *plane) |
599 | { |
600 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
601 | |
602 | spin_lock_irq(&i915->irq_lock)mtx_enter(&i915->irq_lock); |
603 | ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)(1 << (3 + 5 * (plane->i9xx_plane)))); |
604 | spin_unlock_irq(&i915->irq_lock)mtx_leave(&i915->irq_lock); |
605 | } |
606 | |
607 | static void |
608 | ivb_primary_disable_flip_done(struct intel_plane *plane) |
609 | { |
610 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
611 | |
612 | spin_lock_irq(&i915->irq_lock)mtx_enter(&i915->irq_lock); |
613 | ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)(1 << (3 + 5 * (plane->i9xx_plane)))); |
614 | spin_unlock_irq(&i915->irq_lock)mtx_leave(&i915->irq_lock); |
615 | } |
616 | |
617 | static void |
618 | ilk_primary_enable_flip_done(struct intel_plane *plane) |
619 | { |
620 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
621 | |
622 | spin_lock_irq(&i915->irq_lock)mtx_enter(&i915->irq_lock); |
623 | ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)(1 << (26 + (plane->i9xx_plane)))); |
624 | spin_unlock_irq(&i915->irq_lock)mtx_leave(&i915->irq_lock); |
625 | } |
626 | |
627 | static void |
628 | ilk_primary_disable_flip_done(struct intel_plane *plane) |
629 | { |
630 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
631 | |
632 | spin_lock_irq(&i915->irq_lock)mtx_enter(&i915->irq_lock); |
633 | ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)(1 << (26 + (plane->i9xx_plane)))); |
634 | spin_unlock_irq(&i915->irq_lock)mtx_leave(&i915->irq_lock); |
635 | } |
636 | |
637 | static void |
638 | vlv_primary_enable_flip_done(struct intel_plane *plane) |
639 | { |
640 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
641 | enum pipe pipe = plane->pipe; |
642 | |
643 | spin_lock_irq(&i915->irq_lock)mtx_enter(&i915->irq_lock); |
644 | i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV(1UL << 10)); |
645 | spin_unlock_irq(&i915->irq_lock)mtx_leave(&i915->irq_lock); |
646 | } |
647 | |
648 | static void |
649 | vlv_primary_disable_flip_done(struct intel_plane *plane) |
650 | { |
651 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
652 | enum pipe pipe = plane->pipe; |
653 | |
654 | spin_lock_irq(&i915->irq_lock)mtx_enter(&i915->irq_lock); |
655 | i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV(1UL << 10)); |
656 | spin_unlock_irq(&i915->irq_lock)mtx_leave(&i915->irq_lock); |
657 | } |
658 | |
659 | static bool_Bool i9xx_plane_get_hw_state(struct intel_plane *plane, |
660 | enum pipe *pipe) |
661 | { |
662 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
663 | enum intel_display_power_domain power_domain; |
664 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
665 | intel_wakeref_t wakeref; |
666 | bool_Bool ret; |
667 | u32 val; |
668 | |
669 | /* |
670 | * Not 100% correct for planes that can move between pipes, |
671 | * but that's only the case for gen2-4 which don't have any |
672 | * display power wells. |
673 | */ |
674 | power_domain = POWER_DOMAIN_PIPE(plane->pipe)((plane->pipe) + POWER_DOMAIN_PIPE_A); |
675 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
676 | if (!wakeref) |
677 | return false0; |
678 | |
679 | val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70180)) })); |
680 | |
681 | ret = val & DISP_ENABLE((u32)((1UL << (31)) + 0)); |
682 | |
683 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 5) |
684 | *pipe = plane->pipe; |
685 | else |
686 | *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val)((u32)((typeof(((u32)((((~0UL) >> (64 - (25) - 1)) & ((~0UL) << (24))) + 0))))(((val) & (((u32)((((~0UL ) >> (64 - (25) - 1)) & ((~0UL) << (24))) + 0 )))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - (25) - 1)) & ((~0UL) << (24))) + 0))) - 1)))); |
687 | |
688 | intel_display_power_put(dev_priv, power_domain, wakeref); |
689 | |
690 | return ret; |
691 | } |
692 | |
693 | static unsigned int |
694 | hsw_primary_max_stride(struct intel_plane *plane, |
695 | u32 pixel_format, u64 modifier, |
696 | unsigned int rotation) |
697 | { |
698 | const struct drm_format_info *info = drm_format_info(pixel_format); |
699 | int cpp = info->cpp[0]; |
700 | |
701 | /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */ |
702 | return min(8192 * cpp, 32 * 1024)(((8192 * cpp)<(32 * 1024))?(8192 * cpp):(32 * 1024)); |
703 | } |
704 | |
705 | static unsigned int |
706 | ilk_primary_max_stride(struct intel_plane *plane, |
707 | u32 pixel_format, u64 modifier, |
708 | unsigned int rotation) |
709 | { |
710 | const struct drm_format_info *info = drm_format_info(pixel_format); |
711 | int cpp = info->cpp[0]; |
712 | |
713 | /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ |
714 | if (modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) |
715 | return min(4096 * cpp, 32 * 1024)(((4096 * cpp)<(32 * 1024))?(4096 * cpp):(32 * 1024)); |
716 | else |
717 | return 32 * 1024; |
718 | } |
719 | |
720 | unsigned int |
721 | i965_plane_max_stride(struct intel_plane *plane, |
722 | u32 pixel_format, u64 modifier, |
723 | unsigned int rotation) |
724 | { |
725 | const struct drm_format_info *info = drm_format_info(pixel_format); |
726 | int cpp = info->cpp[0]; |
727 | |
728 | /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ |
729 | if (modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) |
730 | return min(4096 * cpp, 16 * 1024)(((4096 * cpp)<(16 * 1024))?(4096 * cpp):(16 * 1024)); |
731 | else |
732 | return 32 * 1024; |
733 | } |
734 | |
735 | static unsigned int |
736 | i9xx_plane_max_stride(struct intel_plane *plane, |
737 | u32 pixel_format, u64 modifier, |
738 | unsigned int rotation) |
739 | { |
740 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
741 | |
742 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 3) { |
743 | if (modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) |
744 | return 8*1024; |
745 | else |
746 | return 16*1024; |
747 | } else { |
748 | if (plane->i9xx_plane == PLANE_C) |
749 | return 4*1024; |
750 | else |
751 | return 8*1024; |
752 | } |
753 | } |
754 | |
755 | static const struct drm_plane_funcs i965_plane_funcs = { |
756 | .update_plane = drm_atomic_helper_update_plane, |
757 | .disable_plane = drm_atomic_helper_disable_plane, |
758 | .destroy = intel_plane_destroy, |
759 | .atomic_duplicate_state = intel_plane_duplicate_state, |
760 | .atomic_destroy_state = intel_plane_destroy_state, |
761 | .format_mod_supported = i965_plane_format_mod_supported, |
762 | }; |
763 | |
764 | static const struct drm_plane_funcs i8xx_plane_funcs = { |
765 | .update_plane = drm_atomic_helper_update_plane, |
766 | .disable_plane = drm_atomic_helper_disable_plane, |
767 | .destroy = intel_plane_destroy, |
768 | .atomic_duplicate_state = intel_plane_duplicate_state, |
769 | .atomic_destroy_state = intel_plane_destroy_state, |
770 | .format_mod_supported = i8xx_plane_format_mod_supported, |
771 | }; |
772 | |
773 | struct intel_plane * |
774 | intel_primary_plane_create(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
775 | { |
776 | struct intel_plane *plane; |
777 | const struct drm_plane_funcs *plane_funcs; |
778 | unsigned int supported_rotations; |
779 | const u64 *modifiers; |
780 | const u32 *formats; |
781 | int num_formats; |
782 | int ret, zpos; |
783 | |
784 | plane = intel_plane_alloc(); |
785 | if (IS_ERR(plane)) |
786 | return plane; |
787 | |
788 | plane->pipe = pipe; |
789 | /* |
790 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS |
791 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. |
792 | */ |
793 | if (HAS_FBC(dev_priv)((&(dev_priv)->__runtime)->fbc_mask != 0) && DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 4 && |
794 | INTEL_NUM_PIPES(dev_priv)(hweight8((&(dev_priv)->__runtime)->pipe_mask)) == 2) |
795 | plane->i9xx_plane = (enum i9xx_plane_id) !pipe; |
796 | else |
797 | plane->i9xx_plane = (enum i9xx_plane_id) pipe; |
798 | plane->id = PLANE_PRIMARY; |
799 | plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id)(1UL << ((plane->id) + 8 * (pipe)));; |
800 | |
801 | intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane); |
802 | |
803 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
804 | formats = vlv_primary_formats; |
805 | num_formats = ARRAY_SIZE(vlv_primary_formats)(sizeof((vlv_primary_formats)) / sizeof((vlv_primary_formats) [0])); |
806 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
807 | /* |
808 | * WaFP16GammaEnabling:ivb |
809 | * "Workaround : When using the 64-bit format, the plane |
810 | * output on each color channel has one quarter amplitude. |
811 | * It can be brought up to full amplitude by using pipe |
812 | * gamma correction or pipe color space conversion to |
813 | * multiply the plane output by four." |
814 | * |
815 | * There is no dedicated plane gamma for the primary plane, |
816 | * and using the pipe gamma/csc could conflict with other |
817 | * planes, so we choose not to expose fp16 on IVB primary |
818 | * planes. HSW primary planes no longer have this problem. |
819 | */ |
820 | if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) { |
821 | formats = ivb_primary_formats; |
822 | num_formats = ARRAY_SIZE(ivb_primary_formats)(sizeof((ivb_primary_formats)) / sizeof((ivb_primary_formats) [0])); |
823 | } else { |
824 | formats = i965_primary_formats; |
825 | num_formats = ARRAY_SIZE(i965_primary_formats)(sizeof((i965_primary_formats)) / sizeof((i965_primary_formats )[0])); |
826 | } |
827 | } else { |
828 | formats = i8xx_primary_formats; |
829 | num_formats = ARRAY_SIZE(i8xx_primary_formats)(sizeof((i8xx_primary_formats)) / sizeof((i8xx_primary_formats )[0])); |
830 | } |
831 | |
832 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
833 | plane_funcs = &i965_plane_funcs; |
834 | else |
835 | plane_funcs = &i8xx_plane_funcs; |
836 | |
837 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
838 | plane->min_cdclk = vlv_plane_min_cdclk; |
839 | else if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
840 | plane->min_cdclk = hsw_plane_min_cdclk; |
841 | else if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
842 | plane->min_cdclk = ivb_plane_min_cdclk; |
843 | else |
844 | plane->min_cdclk = i9xx_plane_min_cdclk; |
845 | |
846 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) { |
847 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
848 | plane->max_stride = i965_plane_max_stride; |
849 | else |
850 | plane->max_stride = i9xx_plane_max_stride; |
851 | } else { |
852 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
853 | plane->max_stride = hsw_primary_max_stride; |
854 | else |
855 | plane->max_stride = ilk_primary_max_stride; |
856 | } |
857 | |
858 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830) || IS_I845G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I845G)) { |
859 | plane->update_arm = i830_plane_update_arm; |
860 | } else { |
861 | plane->update_noarm = i9xx_plane_update_noarm; |
862 | plane->update_arm = i9xx_plane_update_arm; |
863 | } |
864 | plane->disable_arm = i9xx_plane_disable_arm; |
865 | plane->get_hw_state = i9xx_plane_get_hw_state; |
866 | plane->check_plane = i9xx_plane_check; |
867 | |
868 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
869 | plane->async_flip = vlv_primary_async_flip; |
870 | plane->enable_flip_done = vlv_primary_enable_flip_done; |
871 | plane->disable_flip_done = vlv_primary_disable_flip_done; |
872 | } else if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
873 | plane->need_async_flip_disable_wa = true1; |
874 | plane->async_flip = g4x_primary_async_flip; |
875 | plane->enable_flip_done = bdw_primary_enable_flip_done; |
876 | plane->disable_flip_done = bdw_primary_disable_flip_done; |
877 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 7) { |
878 | plane->async_flip = g4x_primary_async_flip; |
879 | plane->enable_flip_done = ivb_primary_enable_flip_done; |
880 | plane->disable_flip_done = ivb_primary_disable_flip_done; |
881 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 5) { |
882 | plane->async_flip = g4x_primary_async_flip; |
883 | plane->enable_flip_done = ilk_primary_enable_flip_done; |
884 | plane->disable_flip_done = ilk_primary_disable_flip_done; |
885 | } |
886 | |
887 | modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X(1UL << (3))); |
888 | |
889 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 5 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
890 | ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, |
891 | 0, plane_funcs, |
892 | formats, num_formats, |
893 | modifiers, |
894 | DRM_PLANE_TYPE_PRIMARY, |
895 | "primary %c", pipe_name(pipe)((pipe) + 'A')); |
896 | else |
897 | ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, |
898 | 0, plane_funcs, |
899 | formats, num_formats, |
900 | modifiers, |
901 | DRM_PLANE_TYPE_PRIMARY, |
902 | "plane %c", |
903 | plane_name(plane->i9xx_plane)((plane->i9xx_plane) + 'A')); |
904 | |
905 | kfree(modifiers); |
906 | |
907 | if (ret) |
908 | goto fail; |
909 | |
910 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && pipe == PIPE_B) { |
911 | supported_rotations = |
912 | DRM_MODE_ROTATE_0(1<<0) | DRM_MODE_ROTATE_180(1<<2) | |
913 | DRM_MODE_REFLECT_X(1<<4); |
914 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
915 | supported_rotations = |
916 | DRM_MODE_ROTATE_0(1<<0) | DRM_MODE_ROTATE_180(1<<2); |
917 | } else { |
918 | supported_rotations = DRM_MODE_ROTATE_0(1<<0); |
919 | } |
920 | |
921 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
922 | drm_plane_create_rotation_property(&plane->base, |
923 | DRM_MODE_ROTATE_0(1<<0), |
924 | supported_rotations); |
925 | |
926 | zpos = 0; |
927 | drm_plane_create_zpos_immutable_property(&plane->base, zpos); |
928 | |
929 | intel_plane_helper_add(plane); |
930 | |
931 | return plane; |
932 | |
933 | fail: |
934 | intel_plane_free(plane); |
935 | |
936 | return ERR_PTR(ret); |
937 | } |
938 | |
939 | static int i9xx_format_to_fourcc(int format) |
940 | { |
941 | switch (format) { |
942 | case DISP_FORMAT_8BPP((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(2) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
943 | return DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)); |
944 | case DISP_FORMAT_BGRA555((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(3) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
945 | return DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)); |
946 | case DISP_FORMAT_BGRX555((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(4) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
947 | return DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)); |
948 | case DISP_FORMAT_BGRX565((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(5) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
949 | return DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)); |
950 | default: |
951 | case DISP_FORMAT_BGRX888((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(6) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
952 | return DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
953 | case DISP_FORMAT_RGBX888((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(14) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
954 | return DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
955 | case DISP_FORMAT_BGRA888((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(7) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
956 | return DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
957 | case DISP_FORMAT_RGBA888((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(15) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
958 | return DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
959 | case DISP_FORMAT_BGRX101010((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(10) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
960 | return DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
961 | case DISP_FORMAT_RGBX101010((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(8) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
962 | return DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
963 | case DISP_FORMAT_BGRA101010((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(11) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
964 | return DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
965 | case DISP_FORMAT_RGBA101010((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(9) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
966 | return DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
967 | case DISP_FORMAT_RGBX161616((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))))(12) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (26))) + 0)))) + 0 + 0 + 0 + 0 )): |
968 | return DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)); |
969 | } |
970 | } |
971 | |
972 | void |
973 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, |
974 | struct intel_initial_plane_config *plane_config) |
975 | { |
976 | struct drm_device *dev = crtc->base.dev; |
977 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
978 | struct intel_plane *plane = to_intel_plane(crtc->base.primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (crtc->base.primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
979 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
980 | enum pipe pipe; |
981 | u32 val, base, offset; |
982 | int fourcc, pixel_format; |
983 | unsigned int aligned_height; |
984 | struct drm_framebuffer *fb; |
985 | struct intel_framebuffer *intel_fb; |
986 | |
987 | if (!plane->get_hw_state(plane, &pipe)) |
988 | return; |
989 | |
990 | drm_WARN_ON(dev, pipe != crtc->pipe)({ int __ret = !!((pipe != crtc->pipe)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "pipe != crtc->pipe" ")"); __builtin_expect(!!(__ret), 0) ; }); |
991 | |
992 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL(0x0001 | 0x0004)); |
993 | if (!intel_fb) { |
994 | drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "failed to alloc fb\n" ); |
995 | return; |
996 | } |
997 | |
998 | fb = &intel_fb->base; |
999 | |
1000 | fb->dev = dev; |
1001 | |
1002 | val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70180)) })); |
1003 | |
1004 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
1005 | if (val & DISP_TILED((u32)((1UL << (10)) + 0))) { |
1006 | plane_config->tiling = I915_TILING_X1; |
1007 | fb->modifier = I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
1008 | } |
1009 | |
1010 | if (val & DISP_ROTATE_180((u32)((1UL << (15)) + 0))) |
1011 | plane_config->rotation = DRM_MODE_ROTATE_180(1<<2); |
1012 | } |
1013 | |
1014 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && pipe == PIPE_B && |
1015 | val & DISP_MIRROR((u32)((1UL << (8)) + 0))) |
1016 | plane_config->rotation |= DRM_MODE_REFLECT_X(1<<4); |
1017 | |
1018 | pixel_format = val & DISP_FORMAT_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (26))) + 0)); |
1019 | fourcc = i9xx_format_to_fourcc(pixel_format); |
1020 | fb->format = drm_format_info(fourcc); |
1021 | |
1022 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
1023 | offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x701A4)) })); |
Value stored to 'offset' is never read | |
1024 | base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x7019C)) })) & DISP_ADDR_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (12))) + 0)); |
1025 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) { |
1026 | if (plane_config->tiling) |
1027 | offset = intel_de_read(dev_priv, |
1028 | DSPTILEOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x701A4)) })); |
1029 | else |
1030 | offset = intel_de_read(dev_priv, |
1031 | DSPLINOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70184)) })); |
1032 | base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x7019C)) })) & DISP_ADDR_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (12))) + 0)); |
1033 | } else { |
1034 | base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70184)) })); |
1035 | } |
1036 | plane_config->base = base; |
1037 | |
1038 | val = intel_de_read(dev_priv, PIPESRC(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(pipe)] - (&(dev_priv)->__info)-> display.trans_offsets[TRANSCODER_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x6001c)) })); |
1039 | fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val)((u32)((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(((val) & (((u32)((((~0UL ) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0 )))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)))) + 1; |
1040 | fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val)((u32)((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0))))(((val) & (((u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0))) + 0)) )) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - ( 15) - 1)) & ((~0UL) << (0))) + 0))) - 1)))) + 1; |
1041 | |
1042 | val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.pipe_offsets[(i9xx_plane)] - (&(dev_priv)->__info )->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info )->display.mmio_offset) + (0x70188)) })); |
1043 | fb->pitches[0] = val & 0xffffffc0; |
1044 | |
1045 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1046 | |
1047 | plane_config->size = fb->pitches[0] * aligned_height; |
1048 | |
1049 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
1050 | "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
1051 | crtc->base.name, plane->base.name, fb->width, fb->height,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
1052 | fb->format->cpp[0] * 8, base, fb->pitches[0],__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
1053 | plane_config->size)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size); |
1054 | |
1055 | plane_config->fb = intel_fb; |
1056 | } |