| File: | dev/pci/drm/amd/amdgpu/dce_v10_0.c |
| Warning: | line 1259, column 3 Value stored to 'tmp' is never read |
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| 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <drm/drm_fourcc.h> |
| 25 | #include <drm/drm_vblank.h> |
| 26 | |
| 27 | #include "amdgpu.h" |
| 28 | #include "amdgpu_pm.h" |
| 29 | #include "amdgpu_i2c.h" |
| 30 | #include "vid.h" |
| 31 | #include "atom.h" |
| 32 | #include "amdgpu_atombios.h" |
| 33 | #include "atombios_crtc.h" |
| 34 | #include "atombios_encoders.h" |
| 35 | #include "amdgpu_pll.h" |
| 36 | #include "amdgpu_connectors.h" |
| 37 | #include "amdgpu_display.h" |
| 38 | #include "dce_v10_0.h" |
| 39 | |
| 40 | #include "dce/dce_10_0_d.h" |
| 41 | #include "dce/dce_10_0_sh_mask.h" |
| 42 | #include "dce/dce_10_0_enum.h" |
| 43 | #include "oss/oss_3_0_d.h" |
| 44 | #include "oss/oss_3_0_sh_mask.h" |
| 45 | #include "gmc/gmc_8_1_d.h" |
| 46 | #include "gmc/gmc_8_1_sh_mask.h" |
| 47 | |
| 48 | #include "ivsrcid/ivsrcid_vislands30.h" |
| 49 | |
| 50 | static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); |
| 51 | static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); |
| 52 | |
| 53 | static const u32 crtc_offsets[] = |
| 54 | { |
| 55 | CRTC0_REGISTER_OFFSET(0x1b9c - 0x1b9c), |
| 56 | CRTC1_REGISTER_OFFSET(0x1d9c - 0x1b9c), |
| 57 | CRTC2_REGISTER_OFFSET(0x1f9c - 0x1b9c), |
| 58 | CRTC3_REGISTER_OFFSET(0x419c - 0x1b9c), |
| 59 | CRTC4_REGISTER_OFFSET(0x439c - 0x1b9c), |
| 60 | CRTC5_REGISTER_OFFSET(0x459c - 0x1b9c), |
| 61 | CRTC6_REGISTER_OFFSET(0x479c - 0x1b9c) |
| 62 | }; |
| 63 | |
| 64 | static const u32 hpd_offsets[] = |
| 65 | { |
| 66 | HPD0_REGISTER_OFFSET(0x1898 - 0x1898), |
| 67 | HPD1_REGISTER_OFFSET(0x18a0 - 0x1898), |
| 68 | HPD2_REGISTER_OFFSET(0x18a8 - 0x1898), |
| 69 | HPD3_REGISTER_OFFSET(0x18b0 - 0x1898), |
| 70 | HPD4_REGISTER_OFFSET(0x18b8 - 0x1898), |
| 71 | HPD5_REGISTER_OFFSET(0x18c0 - 0x1898) |
| 72 | }; |
| 73 | |
| 74 | static const uint32_t dig_offsets[] = { |
| 75 | DIG0_REGISTER_OFFSET(0x4a00 - 0x4a00), |
| 76 | DIG1_REGISTER_OFFSET(0x4b00 - 0x4a00), |
| 77 | DIG2_REGISTER_OFFSET(0x4c00 - 0x4a00), |
| 78 | DIG3_REGISTER_OFFSET(0x4d00 - 0x4a00), |
| 79 | DIG4_REGISTER_OFFSET(0x4e00 - 0x4a00), |
| 80 | DIG5_REGISTER_OFFSET(0x4f00 - 0x4a00), |
| 81 | DIG6_REGISTER_OFFSET(0x5400 - 0x4a00) |
| 82 | }; |
| 83 | |
| 84 | static const struct { |
| 85 | uint32_t reg; |
| 86 | uint32_t vblank; |
| 87 | uint32_t vline; |
| 88 | uint32_t hpd; |
| 89 | |
| 90 | } interrupt_status_offsets[] = { { |
| 91 | .reg = mmDISP_INTERRUPT_STATUS0x1857, |
| 92 | .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK0x8, |
| 93 | .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK0x4, |
| 94 | .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK0x20000 |
| 95 | }, { |
| 96 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE0x1858, |
| 97 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK0x8, |
| 98 | .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK0x4, |
| 99 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK0x20000 |
| 100 | }, { |
| 101 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE20x1859, |
| 102 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK0x8, |
| 103 | .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK0x4, |
| 104 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK0x20000 |
| 105 | }, { |
| 106 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE30x185a, |
| 107 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK0x8, |
| 108 | .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK0x4, |
| 109 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK0x20000 |
| 110 | }, { |
| 111 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE40x185b, |
| 112 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK0x8, |
| 113 | .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK0x4, |
| 114 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK0x20000 |
| 115 | }, { |
| 116 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE50x185c, |
| 117 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK0x8, |
| 118 | .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK0x4, |
| 119 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK0x20000 |
| 120 | } }; |
| 121 | |
| 122 | static const u32 golden_settings_tonga_a11[] = |
| 123 | { |
| 124 | mmDCI_CLK_CNTL0x319, 0x00000080, 0x00000000, |
| 125 | mmFBC_DEBUG_COMP0x29c, 0x000000f0, 0x00000070, |
| 126 | mmFBC_MISC0x2a2, 0x1f311fff, 0x12300000, |
| 127 | mmHDMI_CONTROL0x4a09, 0x31000111, 0x00000011, |
| 128 | }; |
| 129 | |
| 130 | static const u32 tonga_mgcg_cgcg_init[] = |
| 131 | { |
| 132 | mmXDMA_CLOCK_GATING_CNTL0x3e4, 0xffffffff, 0x00000100, |
| 133 | mmXDMA_MEM_POWER_CNTL0x3e6, 0x00000101, 0x00000000, |
| 134 | }; |
| 135 | |
| 136 | static const u32 golden_settings_fiji_a10[] = |
| 137 | { |
| 138 | mmDCI_CLK_CNTL0x319, 0x00000080, 0x00000000, |
| 139 | mmFBC_DEBUG_COMP0x29c, 0x000000f0, 0x00000070, |
| 140 | mmFBC_MISC0x2a2, 0x1f311fff, 0x12300000, |
| 141 | mmHDMI_CONTROL0x4a09, 0x31000111, 0x00000011, |
| 142 | }; |
| 143 | |
| 144 | static const u32 fiji_mgcg_cgcg_init[] = |
| 145 | { |
| 146 | mmXDMA_CLOCK_GATING_CNTL0x3e4, 0xffffffff, 0x00000100, |
| 147 | mmXDMA_MEM_POWER_CNTL0x3e6, 0x00000101, 0x00000000, |
| 148 | }; |
| 149 | |
| 150 | static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) |
| 151 | { |
| 152 | switch (adev->asic_type) { |
| 153 | case CHIP_FIJI: |
| 154 | amdgpu_device_program_register_sequence(adev, |
| 155 | fiji_mgcg_cgcg_init, |
| 156 | ARRAY_SIZE(fiji_mgcg_cgcg_init)(sizeof((fiji_mgcg_cgcg_init)) / sizeof((fiji_mgcg_cgcg_init) [0]))); |
| 157 | amdgpu_device_program_register_sequence(adev, |
| 158 | golden_settings_fiji_a10, |
| 159 | ARRAY_SIZE(golden_settings_fiji_a10)(sizeof((golden_settings_fiji_a10)) / sizeof((golden_settings_fiji_a10 )[0]))); |
| 160 | break; |
| 161 | case CHIP_TONGA: |
| 162 | amdgpu_device_program_register_sequence(adev, |
| 163 | tonga_mgcg_cgcg_init, |
| 164 | ARRAY_SIZE(tonga_mgcg_cgcg_init)(sizeof((tonga_mgcg_cgcg_init)) / sizeof((tonga_mgcg_cgcg_init )[0]))); |
| 165 | amdgpu_device_program_register_sequence(adev, |
| 166 | golden_settings_tonga_a11, |
| 167 | ARRAY_SIZE(golden_settings_tonga_a11)(sizeof((golden_settings_tonga_a11)) / sizeof((golden_settings_tonga_a11 )[0]))); |
| 168 | break; |
| 169 | default: |
| 170 | break; |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, |
| 175 | u32 block_offset, u32 reg) |
| 176 | { |
| 177 | unsigned long flags; |
| 178 | u32 r; |
| 179 | |
| 180 | spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags)do { flags = 0; mtx_enter(&adev->audio_endpt_idx_lock) ; } while (0); |
| 181 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg)amdgpu_device_wreg(adev, (0x17a8 + block_offset), (reg), 0); |
| 182 | r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset)amdgpu_device_rreg(adev, (0x17a9 + block_offset), 0); |
| 183 | spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags)do { (void)(flags); mtx_leave(&adev->audio_endpt_idx_lock ); } while (0); |
| 184 | |
| 185 | return r; |
| 186 | } |
| 187 | |
| 188 | static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, |
| 189 | u32 block_offset, u32 reg, u32 v) |
| 190 | { |
| 191 | unsigned long flags; |
| 192 | |
| 193 | spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags)do { flags = 0; mtx_enter(&adev->audio_endpt_idx_lock) ; } while (0); |
| 194 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg)amdgpu_device_wreg(adev, (0x17a8 + block_offset), (reg), 0); |
| 195 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v)amdgpu_device_wreg(adev, (0x17a9 + block_offset), (v), 0); |
| 196 | spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags)do { (void)(flags); mtx_leave(&adev->audio_endpt_idx_lock ); } while (0); |
| 197 | } |
| 198 | |
| 199 | static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) |
| 200 | { |
| 201 | if (crtc >= adev->mode_info.num_crtc) |
| 202 | return 0; |
| 203 | else |
| 204 | return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ba6 + crtc_offsets[crtc]), 0); |
| 205 | } |
| 206 | |
| 207 | static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) |
| 208 | { |
| 209 | unsigned i; |
| 210 | |
| 211 | /* Enable pflip interrupts */ |
| 212 | for (i = 0; i < adev->mode_info.num_crtc; i++) |
| 213 | amdgpu_irq_get(adev, &adev->pageflip_irq, i); |
| 214 | } |
| 215 | |
| 216 | static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) |
| 217 | { |
| 218 | unsigned i; |
| 219 | |
| 220 | /* Disable pflip interrupts */ |
| 221 | for (i = 0; i < adev->mode_info.num_crtc; i++) |
| 222 | amdgpu_irq_put(adev, &adev->pageflip_irq, i); |
| 223 | } |
| 224 | |
| 225 | /** |
| 226 | * dce_v10_0_page_flip - pageflip callback. |
| 227 | * |
| 228 | * @adev: amdgpu_device pointer |
| 229 | * @crtc_id: crtc to cleanup pageflip on |
| 230 | * @crtc_base: new address of the crtc (GPU MC address) |
| 231 | * @async: asynchronous flip |
| 232 | * |
| 233 | * Triggers the actual pageflip by updating the primary |
| 234 | * surface base address. |
| 235 | */ |
| 236 | static void dce_v10_0_page_flip(struct amdgpu_device *adev, |
| 237 | int crtc_id, u64 crtc_base, bool_Bool async) |
| 238 | { |
| 239 | struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; |
| 240 | struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; |
| 241 | u32 tmp; |
| 242 | |
| 243 | /* flip at hsync for async, default is vsync */ |
| 244 | tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset ), 0); |
| 245 | tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,(((tmp) & ~0x1) | (0x1 & ((async ? 1 : 0) << 0x0 ))) |
| 246 | GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0)(((tmp) & ~0x1) | (0x1 & ((async ? 1 : 0) << 0x0 ))); |
| 247 | WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 248 | /* update pitch */ |
| 249 | WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset ), (fb->pitches[0] / fb->format->cpp[0]), 0) |
| 250 | fb->pitches[0] / fb->format->cpp[0])amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset ), (fb->pitches[0] / fb->format->cpp[0]), 0); |
| 251 | /* update the primary scanout address */ |
| 252 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset ), (((u32)(((crtc_base) >> 16) >> 16))), 0) |
| 253 | upper_32_bits(crtc_base))amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset ), (((u32)(((crtc_base) >> 16) >> 16))), 0); |
| 254 | /* writing to the low address triggers the update */ |
| 255 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset ), (((u32)(crtc_base))), 0) |
| 256 | lower_32_bits(crtc_base))amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset ), (((u32)(crtc_base))), 0); |
| 257 | /* post the write */ |
| 258 | RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset ), 0); |
| 259 | } |
| 260 | |
| 261 | static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, |
| 262 | u32 *vbl, u32 *position) |
| 263 | { |
| 264 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
| 265 | return -EINVAL22; |
| 266 | |
| 267 | *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1b8d + crtc_offsets[crtc]), 0); |
| 268 | *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ba4 + crtc_offsets[crtc]), 0); |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | /** |
| 274 | * dce_v10_0_hpd_sense - hpd sense callback. |
| 275 | * |
| 276 | * @adev: amdgpu_device pointer |
| 277 | * @hpd: hpd (hotplug detect) pin |
| 278 | * |
| 279 | * Checks if a digital monitor is connected (evergreen+). |
| 280 | * Returns true if connected, false if not connected. |
| 281 | */ |
| 282 | static bool_Bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, |
| 283 | enum amdgpu_hpd_id hpd) |
| 284 | { |
| 285 | bool_Bool connected = false0; |
| 286 | |
| 287 | if (hpd >= adev->mode_info.num_hpd) |
| 288 | return connected; |
| 289 | |
| 290 | if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1898 + hpd_offsets[hpd]), 0) & |
| 291 | DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK0x2) |
| 292 | connected = true1; |
| 293 | |
| 294 | return connected; |
| 295 | } |
| 296 | |
| 297 | /** |
| 298 | * dce_v10_0_hpd_set_polarity - hpd set polarity callback. |
| 299 | * |
| 300 | * @adev: amdgpu_device pointer |
| 301 | * @hpd: hpd (hotplug detect) pin |
| 302 | * |
| 303 | * Set the polarity of the hpd pin (evergreen+). |
| 304 | */ |
| 305 | static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, |
| 306 | enum amdgpu_hpd_id hpd) |
| 307 | { |
| 308 | u32 tmp; |
| 309 | bool_Bool connected = dce_v10_0_hpd_sense(adev, hpd); |
| 310 | |
| 311 | if (hpd >= adev->mode_info.num_hpd) |
| 312 | return; |
| 313 | |
| 314 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0); |
| 315 | if (connected) |
| 316 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8))); |
| 317 | else |
| 318 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8))); |
| 319 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0 ); |
| 320 | } |
| 321 | |
| 322 | /** |
| 323 | * dce_v10_0_hpd_init - hpd setup callback. |
| 324 | * |
| 325 | * @adev: amdgpu_device pointer |
| 326 | * |
| 327 | * Setup the hpd pins used by the card (evergreen+). |
| 328 | * Enable the pin, set the polarity, and enable the hpd interrupts. |
| 329 | */ |
| 330 | static void dce_v10_0_hpd_init(struct amdgpu_device *adev) |
| 331 | { |
| 332 | struct drm_device *dev = adev_to_drm(adev); |
| 333 | struct drm_connector *connector; |
| 334 | struct drm_connector_list_iter iter; |
| 335 | u32 tmp; |
| 336 | |
| 337 | drm_connector_list_iter_begin(dev, &iter); |
| 338 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 339 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) * __mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_connector, base) );}); |
| 340 | |
| 341 | if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) |
| 342 | continue; |
| 343 | |
| 344 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14 || |
| 345 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS7) { |
| 346 | /* don't try to enable hpd on eDP or LVDS avoid breaking the |
| 347 | * aux dp channel on imac and help (but not completely fix) |
| 348 | * https://bugzilla.redhat.com/show_bug.cgi?id=726143 |
| 349 | * also avoid interrupt storms during dpms. |
| 350 | */ |
| 351 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[amdgpu_connector ->hpd.hpd]), 0); |
| 352 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0)(((tmp) & ~0x10000) | (0x10000 & ((0) << 0x10)) ); |
| 353 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[amdgpu_connector ->hpd.hpd]), (tmp), 0); |
| 354 | continue; |
| 355 | } |
| 356 | |
| 357 | tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189a + hpd_offsets[amdgpu_connector ->hpd.hpd]), 0); |
| 358 | tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1)(((tmp) & ~0x10000000) | (0x10000000 & ((1) << 0x1c ))); |
| 359 | WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189a + hpd_offsets[amdgpu_connector ->hpd.hpd]), (tmp), 0); |
| 360 | |
| 361 | tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189c + hpd_offsets[amdgpu_connector ->hpd.hpd]), 0); |
| 362 | tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,(((tmp) & ~0xff) | (0xff & ((50) << 0x0))) |
| 363 | DC_HPD_CONNECT_INT_DELAY,(((tmp) & ~0xff) | (0xff & ((50) << 0x0))) |
| 364 | AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS)(((tmp) & ~0xff) | (0xff & ((50) << 0x0))); |
| 365 | tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14 ))) |
| 366 | DC_HPD_DISCONNECT_INT_DELAY,(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14 ))) |
| 367 | AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS)(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14 ))); |
| 368 | WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189c + hpd_offsets[amdgpu_connector ->hpd.hpd]), (tmp), 0); |
| 369 | |
| 370 | dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); |
| 371 | amdgpu_irq_get(adev, &adev->hpd_irq, |
| 372 | amdgpu_connector->hpd.hpd); |
| 373 | } |
| 374 | drm_connector_list_iter_end(&iter); |
| 375 | } |
| 376 | |
| 377 | /** |
| 378 | * dce_v10_0_hpd_fini - hpd tear down callback. |
| 379 | * |
| 380 | * @adev: amdgpu_device pointer |
| 381 | * |
| 382 | * Tear down the hpd pins used by the card (evergreen+). |
| 383 | * Disable the hpd interrupts. |
| 384 | */ |
| 385 | static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) |
| 386 | { |
| 387 | struct drm_device *dev = adev_to_drm(adev); |
| 388 | struct drm_connector *connector; |
| 389 | struct drm_connector_list_iter iter; |
| 390 | u32 tmp; |
| 391 | |
| 392 | drm_connector_list_iter_begin(dev, &iter); |
| 393 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 394 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) * __mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_connector, base) );}); |
| 395 | |
| 396 | if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) |
| 397 | continue; |
| 398 | |
| 399 | tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189a + hpd_offsets[amdgpu_connector ->hpd.hpd]), 0); |
| 400 | tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0)(((tmp) & ~0x10000000) | (0x10000000 & ((0) << 0x1c ))); |
| 401 | WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189a + hpd_offsets[amdgpu_connector ->hpd.hpd]), (tmp), 0); |
| 402 | |
| 403 | amdgpu_irq_put(adev, &adev->hpd_irq, |
| 404 | amdgpu_connector->hpd.hpd); |
| 405 | } |
| 406 | drm_connector_list_iter_end(&iter); |
| 407 | } |
| 408 | |
| 409 | static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) |
| 410 | { |
| 411 | return mmDC_GPIO_HPD_A0x488d; |
| 412 | } |
| 413 | |
| 414 | static bool_Bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) |
| 415 | { |
| 416 | u32 crtc_hung = 0; |
| 417 | u32 crtc_status[6]; |
| 418 | u32 i, j, tmp; |
| 419 | |
| 420 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 421 | tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0); |
| 422 | if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)(((tmp) & 0x1) >> 0x0)) { |
| 423 | crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1ba8 + crtc_offsets[i]), 0); |
| 424 | crtc_hung |= (1 << i); |
| 425 | } |
| 426 | } |
| 427 | |
| 428 | for (j = 0; j < 10; j++) { |
| 429 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 430 | if (crtc_hung & (1 << i)) { |
| 431 | tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1ba8 + crtc_offsets[i]), 0); |
| 432 | if (tmp != crtc_status[i]) |
| 433 | crtc_hung &= ~(1 << i); |
| 434 | } |
| 435 | } |
| 436 | if (crtc_hung == 0) |
| 437 | return false0; |
| 438 | udelay(100); |
| 439 | } |
| 440 | |
| 441 | return true1; |
| 442 | } |
| 443 | |
| 444 | static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, |
| 445 | bool_Bool render) |
| 446 | { |
| 447 | u32 tmp; |
| 448 | |
| 449 | /* Lockout access through VGA aperture*/ |
| 450 | tmp = RREG32(mmVGA_HDP_CONTROL)amdgpu_device_rreg(adev, (0xca), 0); |
| 451 | if (render) |
| 452 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0)(((tmp) & ~0x10) | (0x10 & ((0) << 0x4))); |
| 453 | else |
| 454 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); |
| 455 | WREG32(mmVGA_HDP_CONTROL, tmp)amdgpu_device_wreg(adev, (0xca), (tmp), 0); |
| 456 | |
| 457 | /* disable VGA render */ |
| 458 | tmp = RREG32(mmVGA_RENDER_CONTROL)amdgpu_device_rreg(adev, (0xc0), 0); |
| 459 | if (render) |
| 460 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1)(((tmp) & ~0x30000) | (0x30000 & ((1) << 0x10)) ); |
| 461 | else |
| 462 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0)(((tmp) & ~0x30000) | (0x30000 & ((0) << 0x10)) ); |
| 463 | WREG32(mmVGA_RENDER_CONTROL, tmp)amdgpu_device_wreg(adev, (0xc0), (tmp), 0); |
| 464 | } |
| 465 | |
| 466 | static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev) |
| 467 | { |
| 468 | int num_crtc = 0; |
| 469 | |
| 470 | switch (adev->asic_type) { |
| 471 | case CHIP_FIJI: |
| 472 | case CHIP_TONGA: |
| 473 | num_crtc = 6; |
| 474 | break; |
| 475 | default: |
| 476 | num_crtc = 0; |
| 477 | } |
| 478 | return num_crtc; |
| 479 | } |
| 480 | |
| 481 | void dce_v10_0_disable_dce(struct amdgpu_device *adev) |
| 482 | { |
| 483 | /*Disable VGA render and enabled crtc, if has DCE engine*/ |
| 484 | if (amdgpu_atombios_has_dce_engine_info(adev)) { |
| 485 | u32 tmp; |
| 486 | int crtc_enabled, i; |
| 487 | |
| 488 | dce_v10_0_set_vga_render_state(adev, false0); |
| 489 | |
| 490 | /*Disable crtc*/ |
| 491 | for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) { |
| 492 | crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),(((amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0)) & 0x1) >> 0x0) |
| 493 | CRTC_CONTROL, CRTC_MASTER_EN)(((amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0)) & 0x1) >> 0x0); |
| 494 | if (crtc_enabled) { |
| 495 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1)amdgpu_device_wreg(adev, (0x1bb5 + crtc_offsets[i]), (1), 0); |
| 496 | tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0); |
| 497 | tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0))); |
| 498 | WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp)amdgpu_device_wreg(adev, (0x1b9c + crtc_offsets[i]), (tmp), 0 ); |
| 499 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0)amdgpu_device_wreg(adev, (0x1bb5 + crtc_offsets[i]), (0), 0); |
| 500 | } |
| 501 | } |
| 502 | } |
| 503 | } |
| 504 | |
| 505 | static void dce_v10_0_program_fmt(struct drm_encoder *encoder) |
| 506 | { |
| 507 | struct drm_device *dev = encoder->dev; |
| 508 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 509 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 510 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) );}); |
| 511 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); |
| 512 | int bpc = 0; |
| 513 | u32 tmp = 0; |
| 514 | enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; |
| 515 | |
| 516 | if (connector) { |
| 517 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) * __mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_connector, base) );}); |
| 518 | bpc = amdgpu_connector_get_monitor_bpc(connector); |
| 519 | dither = amdgpu_connector->dither; |
| 520 | } |
| 521 | |
| 522 | /* LVDS/eDP FMT is set up by atom */ |
| 523 | if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))) |
| 524 | return; |
| 525 | |
| 526 | /* not needed for analog */ |
| 527 | if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15) || |
| 528 | (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16)) |
| 529 | return; |
| 530 | |
| 531 | if (bpc == 0) |
| 532 | return; |
| 533 | |
| 534 | switch (bpc) { |
| 535 | case 6: |
| 536 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { |
| 537 | /* XXX sort out optimal dither settings */ |
| 538 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd))); |
| 539 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf))); |
| 540 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8))); |
| 541 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0)(((tmp) & ~0x1800) | (0x1800 & ((0) << 0xb))); |
| 542 | } else { |
| 543 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
| 544 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0)(((tmp) & ~0x30) | (0x30 & ((0) << 0x4))); |
| 545 | } |
| 546 | break; |
| 547 | case 8: |
| 548 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { |
| 549 | /* XXX sort out optimal dither settings */ |
| 550 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd))); |
| 551 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf))); |
| 552 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1)(((tmp) & ~0x4000) | (0x4000 & ((1) << 0xe))); |
| 553 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8))); |
| 554 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1)(((tmp) & ~0x1800) | (0x1800 & ((1) << 0xb))); |
| 555 | } else { |
| 556 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
| 557 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1)(((tmp) & ~0x30) | (0x30 & ((1) << 0x4))); |
| 558 | } |
| 559 | break; |
| 560 | case 10: |
| 561 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { |
| 562 | /* XXX sort out optimal dither settings */ |
| 563 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd))); |
| 564 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf))); |
| 565 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1)(((tmp) & ~0x4000) | (0x4000 & ((1) << 0xe))); |
| 566 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8))); |
| 567 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2)(((tmp) & ~0x1800) | (0x1800 & ((2) << 0xb))); |
| 568 | } else { |
| 569 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
| 570 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2)(((tmp) & ~0x30) | (0x30 & ((2) << 0x4))); |
| 571 | } |
| 572 | break; |
| 573 | default: |
| 574 | /* not needed */ |
| 575 | break; |
| 576 | } |
| 577 | |
| 578 | WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1bf2 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 579 | } |
| 580 | |
| 581 | |
| 582 | /* display watermark setup */ |
| 583 | /** |
| 584 | * dce_v10_0_line_buffer_adjust - Set up the line buffer |
| 585 | * |
| 586 | * @adev: amdgpu_device pointer |
| 587 | * @amdgpu_crtc: the selected display controller |
| 588 | * @mode: the current display mode on the selected display |
| 589 | * controller |
| 590 | * |
| 591 | * Setup up the line buffer allocation for |
| 592 | * the selected display controller (CIK). |
| 593 | * Returns the line buffer size in pixels. |
| 594 | */ |
| 595 | static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, |
| 596 | struct amdgpu_crtc *amdgpu_crtc, |
| 597 | struct drm_display_mode *mode) |
| 598 | { |
| 599 | u32 tmp, buffer_alloc, i, mem_cfg; |
| 600 | u32 pipe_offset = amdgpu_crtc->crtc_id; |
| 601 | /* |
| 602 | * Line Buffer Setup |
| 603 | * There are 6 line buffers, one for each display controllers. |
| 604 | * There are 3 partitions per LB. Select the number of partitions |
| 605 | * to enable based on the display width. For display widths larger |
| 606 | * than 4096, you need use to use 2 display controllers and combine |
| 607 | * them using the stereo blender. |
| 608 | */ |
| 609 | if (amdgpu_crtc->base.enabled && mode) { |
| 610 | if (mode->crtc_hdisplay < 1920) { |
| 611 | mem_cfg = 1; |
| 612 | buffer_alloc = 2; |
| 613 | } else if (mode->crtc_hdisplay < 2560) { |
| 614 | mem_cfg = 2; |
| 615 | buffer_alloc = 2; |
| 616 | } else if (mode->crtc_hdisplay < 4096) { |
| 617 | mem_cfg = 0; |
| 618 | buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; |
| 619 | } else { |
| 620 | DRM_DEBUG_KMS("Mode too big for LB!\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Mode too big for LB!\n"); |
| 621 | mem_cfg = 0; |
| 622 | buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; |
| 623 | } |
| 624 | } else { |
| 625 | mem_cfg = 1; |
| 626 | buffer_alloc = 0; |
| 627 | } |
| 628 | |
| 629 | tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1ac1 + amdgpu_crtc->crtc_offset ), 0); |
| 630 | tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg)(((tmp) & ~0x300000) | (0x300000 & ((mem_cfg) << 0x14))); |
| 631 | WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1ac1 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 632 | |
| 633 | tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset)amdgpu_device_rreg(adev, (0x321 + pipe_offset), 0); |
| 634 | tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc)(((tmp) & ~0x7) | (0x7 & ((buffer_alloc) << 0x0 ))); |
| 635 | WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp)amdgpu_device_wreg(adev, (0x321 + pipe_offset), (tmp), 0); |
| 636 | |
| 637 | for (i = 0; i < adev->usec_timeout; i++) { |
| 638 | tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset)amdgpu_device_rreg(adev, (0x321 + pipe_offset), 0); |
| 639 | if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)(((tmp) & 0x10) >> 0x4)) |
| 640 | break; |
| 641 | udelay(1); |
| 642 | } |
| 643 | |
| 644 | if (amdgpu_crtc->base.enabled && mode) { |
| 645 | switch (mem_cfg) { |
| 646 | case 0: |
| 647 | default: |
| 648 | return 4096 * 2; |
| 649 | case 1: |
| 650 | return 1920 * 2; |
| 651 | case 2: |
| 652 | return 2560 * 2; |
| 653 | } |
| 654 | } |
| 655 | |
| 656 | /* controller not enabled, so no lb used */ |
| 657 | return 0; |
| 658 | } |
| 659 | |
| 660 | /** |
| 661 | * cik_get_number_of_dram_channels - get the number of dram channels |
| 662 | * |
| 663 | * @adev: amdgpu_device pointer |
| 664 | * |
| 665 | * Look up the number of video ram channels (CIK). |
| 666 | * Used for display watermark bandwidth calculations |
| 667 | * Returns the number of dram channels |
| 668 | */ |
| 669 | static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) |
| 670 | { |
| 671 | u32 tmp = RREG32(mmMC_SHARED_CHMAP)amdgpu_device_rreg(adev, (0x801), 0); |
| 672 | |
| 673 | switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)(((tmp) & 0xf000) >> 0xc)) { |
| 674 | case 0: |
| 675 | default: |
| 676 | return 1; |
| 677 | case 1: |
| 678 | return 2; |
| 679 | case 2: |
| 680 | return 4; |
| 681 | case 3: |
| 682 | return 8; |
| 683 | case 4: |
| 684 | return 3; |
| 685 | case 5: |
| 686 | return 6; |
| 687 | case 6: |
| 688 | return 10; |
| 689 | case 7: |
| 690 | return 12; |
| 691 | case 8: |
| 692 | return 16; |
| 693 | } |
| 694 | } |
| 695 | |
| 696 | struct dce10_wm_params { |
| 697 | u32 dram_channels; /* number of dram channels */ |
| 698 | u32 yclk; /* bandwidth per dram data pin in kHz */ |
| 699 | u32 sclk; /* engine clock in kHz */ |
| 700 | u32 disp_clk; /* display clock in kHz */ |
| 701 | u32 src_width; /* viewport width */ |
| 702 | u32 active_time; /* active display time in ns */ |
| 703 | u32 blank_time; /* blank time in ns */ |
| 704 | bool_Bool interlaced; /* mode is interlaced */ |
| 705 | fixed20_12 vsc; /* vertical scale ratio */ |
| 706 | u32 num_heads; /* number of active crtcs */ |
| 707 | u32 bytes_per_pixel; /* bytes per pixel display + overlay */ |
| 708 | u32 lb_size; /* line buffer allocated to pipe */ |
| 709 | u32 vtaps; /* vertical scaler taps */ |
| 710 | }; |
| 711 | |
| 712 | /** |
| 713 | * dce_v10_0_dram_bandwidth - get the dram bandwidth |
| 714 | * |
| 715 | * @wm: watermark calculation data |
| 716 | * |
| 717 | * Calculate the raw dram bandwidth (CIK). |
| 718 | * Used for display watermark bandwidth calculations |
| 719 | * Returns the dram bandwidth in MBytes/s |
| 720 | */ |
| 721 | static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) |
| 722 | { |
| 723 | /* Calculate raw DRAM Bandwidth */ |
| 724 | fixed20_12 dram_efficiency; /* 0.7 */ |
| 725 | fixed20_12 yclk, dram_channels, bandwidth; |
| 726 | fixed20_12 a; |
| 727 | |
| 728 | a.full = dfixed_const(1000)(u32)(((1000) << 12)); |
| 729 | yclk.full = dfixed_const(wm->yclk)(u32)(((wm->yclk) << 12)); |
| 730 | yclk.full = dfixed_div(yclk, a); |
| 731 | dram_channels.full = dfixed_const(wm->dram_channels * 4)(u32)(((wm->dram_channels * 4) << 12)); |
| 732 | a.full = dfixed_const(10)(u32)(((10) << 12)); |
| 733 | dram_efficiency.full = dfixed_const(7)(u32)(((7) << 12)); |
| 734 | dram_efficiency.full = dfixed_div(dram_efficiency, a); |
| 735 | bandwidth.full = dfixed_mul(dram_channels, yclk)((u64)((u64)(dram_channels).full * (yclk).full + 2048) >> 12); |
| 736 | bandwidth.full = dfixed_mul(bandwidth, dram_efficiency)((u64)((u64)(bandwidth).full * (dram_efficiency).full + 2048) >> 12); |
| 737 | |
| 738 | return dfixed_trunc(bandwidth)((bandwidth).full >> 12); |
| 739 | } |
| 740 | |
| 741 | /** |
| 742 | * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display |
| 743 | * |
| 744 | * @wm: watermark calculation data |
| 745 | * |
| 746 | * Calculate the dram bandwidth used for display (CIK). |
| 747 | * Used for display watermark bandwidth calculations |
| 748 | * Returns the dram bandwidth for display in MBytes/s |
| 749 | */ |
| 750 | static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) |
| 751 | { |
| 752 | /* Calculate DRAM Bandwidth and the part allocated to display. */ |
| 753 | fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ |
| 754 | fixed20_12 yclk, dram_channels, bandwidth; |
| 755 | fixed20_12 a; |
| 756 | |
| 757 | a.full = dfixed_const(1000)(u32)(((1000) << 12)); |
| 758 | yclk.full = dfixed_const(wm->yclk)(u32)(((wm->yclk) << 12)); |
| 759 | yclk.full = dfixed_div(yclk, a); |
| 760 | dram_channels.full = dfixed_const(wm->dram_channels * 4)(u32)(((wm->dram_channels * 4) << 12)); |
| 761 | a.full = dfixed_const(10)(u32)(((10) << 12)); |
| 762 | disp_dram_allocation.full = dfixed_const(3)(u32)(((3) << 12)); /* XXX worse case value 0.3 */ |
| 763 | disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); |
| 764 | bandwidth.full = dfixed_mul(dram_channels, yclk)((u64)((u64)(dram_channels).full * (yclk).full + 2048) >> 12); |
| 765 | bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation)((u64)((u64)(bandwidth).full * (disp_dram_allocation).full + 2048 ) >> 12); |
| 766 | |
| 767 | return dfixed_trunc(bandwidth)((bandwidth).full >> 12); |
| 768 | } |
| 769 | |
| 770 | /** |
| 771 | * dce_v10_0_data_return_bandwidth - get the data return bandwidth |
| 772 | * |
| 773 | * @wm: watermark calculation data |
| 774 | * |
| 775 | * Calculate the data return bandwidth used for display (CIK). |
| 776 | * Used for display watermark bandwidth calculations |
| 777 | * Returns the data return bandwidth in MBytes/s |
| 778 | */ |
| 779 | static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) |
| 780 | { |
| 781 | /* Calculate the display Data return Bandwidth */ |
| 782 | fixed20_12 return_efficiency; /* 0.8 */ |
| 783 | fixed20_12 sclk, bandwidth; |
| 784 | fixed20_12 a; |
| 785 | |
| 786 | a.full = dfixed_const(1000)(u32)(((1000) << 12)); |
| 787 | sclk.full = dfixed_const(wm->sclk)(u32)(((wm->sclk) << 12)); |
| 788 | sclk.full = dfixed_div(sclk, a); |
| 789 | a.full = dfixed_const(10)(u32)(((10) << 12)); |
| 790 | return_efficiency.full = dfixed_const(8)(u32)(((8) << 12)); |
| 791 | return_efficiency.full = dfixed_div(return_efficiency, a); |
| 792 | a.full = dfixed_const(32)(u32)(((32) << 12)); |
| 793 | bandwidth.full = dfixed_mul(a, sclk)((u64)((u64)(a).full * (sclk).full + 2048) >> 12); |
| 794 | bandwidth.full = dfixed_mul(bandwidth, return_efficiency)((u64)((u64)(bandwidth).full * (return_efficiency).full + 2048 ) >> 12); |
| 795 | |
| 796 | return dfixed_trunc(bandwidth)((bandwidth).full >> 12); |
| 797 | } |
| 798 | |
| 799 | /** |
| 800 | * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth |
| 801 | * |
| 802 | * @wm: watermark calculation data |
| 803 | * |
| 804 | * Calculate the dmif bandwidth used for display (CIK). |
| 805 | * Used for display watermark bandwidth calculations |
| 806 | * Returns the dmif bandwidth in MBytes/s |
| 807 | */ |
| 808 | static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) |
| 809 | { |
| 810 | /* Calculate the DMIF Request Bandwidth */ |
| 811 | fixed20_12 disp_clk_request_efficiency; /* 0.8 */ |
| 812 | fixed20_12 disp_clk, bandwidth; |
| 813 | fixed20_12 a, b; |
| 814 | |
| 815 | a.full = dfixed_const(1000)(u32)(((1000) << 12)); |
| 816 | disp_clk.full = dfixed_const(wm->disp_clk)(u32)(((wm->disp_clk) << 12)); |
| 817 | disp_clk.full = dfixed_div(disp_clk, a); |
| 818 | a.full = dfixed_const(32)(u32)(((32) << 12)); |
| 819 | b.full = dfixed_mul(a, disp_clk)((u64)((u64)(a).full * (disp_clk).full + 2048) >> 12); |
| 820 | |
| 821 | a.full = dfixed_const(10)(u32)(((10) << 12)); |
| 822 | disp_clk_request_efficiency.full = dfixed_const(8)(u32)(((8) << 12)); |
| 823 | disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); |
| 824 | |
| 825 | bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency)((u64)((u64)(b).full * (disp_clk_request_efficiency).full + 2048 ) >> 12); |
| 826 | |
| 827 | return dfixed_trunc(bandwidth)((bandwidth).full >> 12); |
| 828 | } |
| 829 | |
| 830 | /** |
| 831 | * dce_v10_0_available_bandwidth - get the min available bandwidth |
| 832 | * |
| 833 | * @wm: watermark calculation data |
| 834 | * |
| 835 | * Calculate the min available bandwidth used for display (CIK). |
| 836 | * Used for display watermark bandwidth calculations |
| 837 | * Returns the min available bandwidth in MBytes/s |
| 838 | */ |
| 839 | static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) |
| 840 | { |
| 841 | /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ |
| 842 | u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); |
| 843 | u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); |
| 844 | u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); |
| 845 | |
| 846 | return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth))(((dram_bandwidth)<((((data_return_bandwidth)<(dmif_req_bandwidth ))?(data_return_bandwidth):(dmif_req_bandwidth))))?(dram_bandwidth ):((((data_return_bandwidth)<(dmif_req_bandwidth))?(data_return_bandwidth ):(dmif_req_bandwidth)))); |
| 847 | } |
| 848 | |
| 849 | /** |
| 850 | * dce_v10_0_average_bandwidth - get the average available bandwidth |
| 851 | * |
| 852 | * @wm: watermark calculation data |
| 853 | * |
| 854 | * Calculate the average available bandwidth used for display (CIK). |
| 855 | * Used for display watermark bandwidth calculations |
| 856 | * Returns the average available bandwidth in MBytes/s |
| 857 | */ |
| 858 | static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) |
| 859 | { |
| 860 | /* Calculate the display mode Average Bandwidth |
| 861 | * DisplayMode should contain the source and destination dimensions, |
| 862 | * timing, etc. |
| 863 | */ |
| 864 | fixed20_12 bpp; |
| 865 | fixed20_12 line_time; |
| 866 | fixed20_12 src_width; |
| 867 | fixed20_12 bandwidth; |
| 868 | fixed20_12 a; |
| 869 | |
| 870 | a.full = dfixed_const(1000)(u32)(((1000) << 12)); |
| 871 | line_time.full = dfixed_const(wm->active_time + wm->blank_time)(u32)(((wm->active_time + wm->blank_time) << 12)); |
| 872 | line_time.full = dfixed_div(line_time, a); |
| 873 | bpp.full = dfixed_const(wm->bytes_per_pixel)(u32)(((wm->bytes_per_pixel) << 12)); |
| 874 | src_width.full = dfixed_const(wm->src_width)(u32)(((wm->src_width) << 12)); |
| 875 | bandwidth.full = dfixed_mul(src_width, bpp)((u64)((u64)(src_width).full * (bpp).full + 2048) >> 12 ); |
| 876 | bandwidth.full = dfixed_mul(bandwidth, wm->vsc)((u64)((u64)(bandwidth).full * (wm->vsc).full + 2048) >> 12); |
| 877 | bandwidth.full = dfixed_div(bandwidth, line_time); |
| 878 | |
| 879 | return dfixed_trunc(bandwidth)((bandwidth).full >> 12); |
| 880 | } |
| 881 | |
| 882 | /** |
| 883 | * dce_v10_0_latency_watermark - get the latency watermark |
| 884 | * |
| 885 | * @wm: watermark calculation data |
| 886 | * |
| 887 | * Calculate the latency watermark (CIK). |
| 888 | * Used for display watermark bandwidth calculations |
| 889 | * Returns the latency watermark in ns |
| 890 | */ |
| 891 | static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) |
| 892 | { |
| 893 | /* First calculate the latency in ns */ |
| 894 | u32 mc_latency = 2000; /* 2000 ns. */ |
| 895 | u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); |
| 896 | u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; |
| 897 | u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; |
| 898 | u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ |
| 899 | u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + |
| 900 | (wm->num_heads * cursor_line_pair_return_time); |
| 901 | u32 latency = mc_latency + other_heads_data_return_time + dc_latency; |
| 902 | u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; |
| 903 | u32 tmp, dmif_size = 12288; |
| 904 | fixed20_12 a, b, c; |
| 905 | |
| 906 | if (wm->num_heads == 0) |
| 907 | return 0; |
| 908 | |
| 909 | a.full = dfixed_const(2)(u32)(((2) << 12)); |
| 910 | b.full = dfixed_const(1)(u32)(((1) << 12)); |
| 911 | if ((wm->vsc.full > a.full) || |
| 912 | ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || |
| 913 | (wm->vtaps >= 5) || |
| 914 | ((wm->vsc.full >= a.full) && wm->interlaced)) |
| 915 | max_src_lines_per_dst_line = 4; |
| 916 | else |
| 917 | max_src_lines_per_dst_line = 2; |
| 918 | |
| 919 | a.full = dfixed_const(available_bandwidth)(u32)(((available_bandwidth) << 12)); |
| 920 | b.full = dfixed_const(wm->num_heads)(u32)(((wm->num_heads) << 12)); |
| 921 | a.full = dfixed_div(a, b); |
| 922 | tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); |
| 923 | tmp = min(dfixed_trunc(a), tmp)(((((a).full >> 12))<(tmp))?(((a).full >> 12)) :(tmp)); |
| 924 | |
| 925 | lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)(((tmp)<(wm->disp_clk * wm->bytes_per_pixel / 1000)) ?(tmp):(wm->disp_clk * wm->bytes_per_pixel / 1000)); |
| 926 | |
| 927 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel)(u32)(((max_src_lines_per_dst_line * wm->src_width * wm-> bytes_per_pixel) << 12)); |
| 928 | b.full = dfixed_const(1000)(u32)(((1000) << 12)); |
| 929 | c.full = dfixed_const(lb_fill_bw)(u32)(((lb_fill_bw) << 12)); |
| 930 | b.full = dfixed_div(c, b); |
| 931 | a.full = dfixed_div(a, b); |
| 932 | line_fill_time = dfixed_trunc(a)((a).full >> 12); |
| 933 | |
| 934 | if (line_fill_time < wm->active_time) |
| 935 | return latency; |
| 936 | else |
| 937 | return latency + (line_fill_time - wm->active_time); |
| 938 | |
| 939 | } |
| 940 | |
| 941 | /** |
| 942 | * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check |
| 943 | * average and available dram bandwidth |
| 944 | * |
| 945 | * @wm: watermark calculation data |
| 946 | * |
| 947 | * Check if the display average bandwidth fits in the display |
| 948 | * dram bandwidth (CIK). |
| 949 | * Used for display watermark bandwidth calculations |
| 950 | * Returns true if the display fits, false if not. |
| 951 | */ |
| 952 | static bool_Bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) |
| 953 | { |
| 954 | if (dce_v10_0_average_bandwidth(wm) <= |
| 955 | (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) |
| 956 | return true1; |
| 957 | else |
| 958 | return false0; |
| 959 | } |
| 960 | |
| 961 | /** |
| 962 | * dce_v10_0_average_bandwidth_vs_available_bandwidth - check |
| 963 | * average and available bandwidth |
| 964 | * |
| 965 | * @wm: watermark calculation data |
| 966 | * |
| 967 | * Check if the display average bandwidth fits in the display |
| 968 | * available bandwidth (CIK). |
| 969 | * Used for display watermark bandwidth calculations |
| 970 | * Returns true if the display fits, false if not. |
| 971 | */ |
| 972 | static bool_Bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) |
| 973 | { |
| 974 | if (dce_v10_0_average_bandwidth(wm) <= |
| 975 | (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) |
| 976 | return true1; |
| 977 | else |
| 978 | return false0; |
| 979 | } |
| 980 | |
| 981 | /** |
| 982 | * dce_v10_0_check_latency_hiding - check latency hiding |
| 983 | * |
| 984 | * @wm: watermark calculation data |
| 985 | * |
| 986 | * Check latency hiding (CIK). |
| 987 | * Used for display watermark bandwidth calculations |
| 988 | * Returns true if the display fits, false if not. |
| 989 | */ |
| 990 | static bool_Bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) |
| 991 | { |
| 992 | u32 lb_partitions = wm->lb_size / wm->src_width; |
| 993 | u32 line_time = wm->active_time + wm->blank_time; |
| 994 | u32 latency_tolerant_lines; |
| 995 | u32 latency_hiding; |
| 996 | fixed20_12 a; |
| 997 | |
| 998 | a.full = dfixed_const(1)(u32)(((1) << 12)); |
| 999 | if (wm->vsc.full > a.full) |
| 1000 | latency_tolerant_lines = 1; |
| 1001 | else { |
| 1002 | if (lb_partitions <= (wm->vtaps + 1)) |
| 1003 | latency_tolerant_lines = 1; |
| 1004 | else |
| 1005 | latency_tolerant_lines = 2; |
| 1006 | } |
| 1007 | |
| 1008 | latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); |
| 1009 | |
| 1010 | if (dce_v10_0_latency_watermark(wm) <= latency_hiding) |
| 1011 | return true1; |
| 1012 | else |
| 1013 | return false0; |
| 1014 | } |
| 1015 | |
| 1016 | /** |
| 1017 | * dce_v10_0_program_watermarks - program display watermarks |
| 1018 | * |
| 1019 | * @adev: amdgpu_device pointer |
| 1020 | * @amdgpu_crtc: the selected display controller |
| 1021 | * @lb_size: line buffer size |
| 1022 | * @num_heads: number of display controllers in use |
| 1023 | * |
| 1024 | * Calculate and program the display watermarks for the |
| 1025 | * selected display controller (CIK). |
| 1026 | */ |
| 1027 | static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, |
| 1028 | struct amdgpu_crtc *amdgpu_crtc, |
| 1029 | u32 lb_size, u32 num_heads) |
| 1030 | { |
| 1031 | struct drm_display_mode *mode = &amdgpu_crtc->base.mode; |
| 1032 | struct dce10_wm_params wm_low, wm_high; |
| 1033 | u32 active_time; |
| 1034 | u32 line_time = 0; |
| 1035 | u32 latency_watermark_a = 0, latency_watermark_b = 0; |
| 1036 | u32 tmp, wm_mask, lb_vblank_lead_lines = 0; |
| 1037 | |
| 1038 | if (amdgpu_crtc->base.enabled && num_heads && mode) { |
| 1039 | active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, |
| 1040 | (u32)mode->clock); |
| 1041 | line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, |
| 1042 | (u32)mode->clock); |
| 1043 | line_time = min(line_time, (u32)65535)(((line_time)<((u32)65535))?(line_time):((u32)65535)); |
| 1044 | |
| 1045 | /* watermark for high clocks */ |
| 1046 | if (adev->pm.dpm_enabled) { |
| 1047 | wm_high.yclk = |
| 1048 | amdgpu_dpm_get_mclk(adev, false0) * 10; |
| 1049 | wm_high.sclk = |
| 1050 | amdgpu_dpm_get_sclk(adev, false0) * 10; |
| 1051 | } else { |
| 1052 | wm_high.yclk = adev->pm.current_mclk * 10; |
| 1053 | wm_high.sclk = adev->pm.current_sclk * 10; |
| 1054 | } |
| 1055 | |
| 1056 | wm_high.disp_clk = mode->clock; |
| 1057 | wm_high.src_width = mode->crtc_hdisplay; |
| 1058 | wm_high.active_time = active_time; |
| 1059 | wm_high.blank_time = line_time - wm_high.active_time; |
| 1060 | wm_high.interlaced = false0; |
| 1061 | if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 1062 | wm_high.interlaced = true1; |
| 1063 | wm_high.vsc = amdgpu_crtc->vsc; |
| 1064 | wm_high.vtaps = 1; |
| 1065 | if (amdgpu_crtc->rmx_type != RMX_OFF) |
| 1066 | wm_high.vtaps = 2; |
| 1067 | wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ |
| 1068 | wm_high.lb_size = lb_size; |
| 1069 | wm_high.dram_channels = cik_get_number_of_dram_channels(adev); |
| 1070 | wm_high.num_heads = num_heads; |
| 1071 | |
| 1072 | /* set for high clocks */ |
| 1073 | latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535)(((dce_v10_0_latency_watermark(&wm_high))<((u32)65535) )?(dce_v10_0_latency_watermark(&wm_high)):((u32)65535)); |
| 1074 | |
| 1075 | /* possibly force display priority to high */ |
| 1076 | /* should really do this at mode validation time... */ |
| 1077 | if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || |
| 1078 | !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || |
| 1079 | !dce_v10_0_check_latency_hiding(&wm_high) || |
| 1080 | (adev->mode_info.disp_priority == 2)) { |
| 1081 | DRM_DEBUG_KMS("force priority to high\n")___drm_dbg(((void *)0), DRM_UT_KMS, "force priority to high\n" ); |
| 1082 | } |
| 1083 | |
| 1084 | /* watermark for low clocks */ |
| 1085 | if (adev->pm.dpm_enabled) { |
| 1086 | wm_low.yclk = |
| 1087 | amdgpu_dpm_get_mclk(adev, true1) * 10; |
| 1088 | wm_low.sclk = |
| 1089 | amdgpu_dpm_get_sclk(adev, true1) * 10; |
| 1090 | } else { |
| 1091 | wm_low.yclk = adev->pm.current_mclk * 10; |
| 1092 | wm_low.sclk = adev->pm.current_sclk * 10; |
| 1093 | } |
| 1094 | |
| 1095 | wm_low.disp_clk = mode->clock; |
| 1096 | wm_low.src_width = mode->crtc_hdisplay; |
| 1097 | wm_low.active_time = active_time; |
| 1098 | wm_low.blank_time = line_time - wm_low.active_time; |
| 1099 | wm_low.interlaced = false0; |
| 1100 | if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 1101 | wm_low.interlaced = true1; |
| 1102 | wm_low.vsc = amdgpu_crtc->vsc; |
| 1103 | wm_low.vtaps = 1; |
| 1104 | if (amdgpu_crtc->rmx_type != RMX_OFF) |
| 1105 | wm_low.vtaps = 2; |
| 1106 | wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ |
| 1107 | wm_low.lb_size = lb_size; |
| 1108 | wm_low.dram_channels = cik_get_number_of_dram_channels(adev); |
| 1109 | wm_low.num_heads = num_heads; |
| 1110 | |
| 1111 | /* set for low clocks */ |
| 1112 | latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535)(((dce_v10_0_latency_watermark(&wm_low))<((u32)65535)) ?(dce_v10_0_latency_watermark(&wm_low)):((u32)65535)); |
| 1113 | |
| 1114 | /* possibly force display priority to high */ |
| 1115 | /* should really do this at mode validation time... */ |
| 1116 | if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || |
| 1117 | !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || |
| 1118 | !dce_v10_0_check_latency_hiding(&wm_low) || |
| 1119 | (adev->mode_info.disp_priority == 2)) { |
| 1120 | DRM_DEBUG_KMS("force priority to high\n")___drm_dbg(((void *)0), DRM_UT_KMS, "force priority to high\n" ); |
| 1121 | } |
| 1122 | lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay)(((lb_size) + ((mode->crtc_hdisplay) - 1)) / (mode->crtc_hdisplay )); |
| 1123 | } |
| 1124 | |
| 1125 | /* select wm A */ |
| 1126 | wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset ), 0); |
| 1127 | tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1)(((wm_mask) & ~0x300) | (0x300 & ((1) << 0x8))); |
| 1128 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 1129 | tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset ), 0); |
| 1130 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a)(((tmp) & ~0xffff) | (0xffff & ((latency_watermark_a) << 0x0))); |
| 1131 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time)(((tmp) & ~0xffff0000) | (0xffff0000 & ((line_time) << 0x10))); |
| 1132 | WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 1133 | /* select wm B */ |
| 1134 | tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2)(((wm_mask) & ~0x300) | (0x300 & ((2) << 0x8))); |
| 1135 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 1136 | tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset ), 0); |
| 1137 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b)(((tmp) & ~0xffff) | (0xffff & ((latency_watermark_b) << 0x0))); |
| 1138 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time)(((tmp) & ~0xffff0000) | (0xffff0000 & ((line_time) << 0x10))); |
| 1139 | WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 1140 | /* restore original selection */ |
| 1141 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset ), (wm_mask), 0); |
| 1142 | |
| 1143 | /* save values for DPM */ |
| 1144 | amdgpu_crtc->line_time = line_time; |
| 1145 | amdgpu_crtc->wm_high = latency_watermark_a; |
| 1146 | amdgpu_crtc->wm_low = latency_watermark_b; |
| 1147 | /* Save number of lines the linebuffer leads before the scanout */ |
| 1148 | amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; |
| 1149 | } |
| 1150 | |
| 1151 | /** |
| 1152 | * dce_v10_0_bandwidth_update - program display watermarks |
| 1153 | * |
| 1154 | * @adev: amdgpu_device pointer |
| 1155 | * |
| 1156 | * Calculate and program the display watermarks and line |
| 1157 | * buffer allocation (CIK). |
| 1158 | */ |
| 1159 | static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) |
| 1160 | { |
| 1161 | struct drm_display_mode *mode = NULL((void *)0); |
| 1162 | u32 num_heads = 0, lb_size; |
| 1163 | int i; |
| 1164 | |
| 1165 | amdgpu_display_update_priority(adev); |
| 1166 | |
| 1167 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 1168 | if (adev->mode_info.crtcs[i]->base.enabled) |
| 1169 | num_heads++; |
| 1170 | } |
| 1171 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 1172 | mode = &adev->mode_info.crtcs[i]->base.mode; |
| 1173 | lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); |
| 1174 | dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], |
| 1175 | lb_size, num_heads); |
| 1176 | } |
| 1177 | } |
| 1178 | |
| 1179 | static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) |
| 1180 | { |
| 1181 | int i; |
| 1182 | u32 offset, tmp; |
| 1183 | |
| 1184 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 1185 | offset = adev->mode_info.audio.pin[i].offset; |
| 1186 | tmp = RREG32_AUDIO_ENDPT(offset,adev->audio_endpt_rreg(adev, (offset), (0x56)) |
| 1187 | ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)adev->audio_endpt_rreg(adev, (offset), (0x56)); |
| 1188 | if (((tmp & |
| 1189 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK0xc0000000) >> |
| 1190 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT0x1e) == 1) |
| 1191 | adev->mode_info.audio.pin[i].connected = false0; |
| 1192 | else |
| 1193 | adev->mode_info.audio.pin[i].connected = true1; |
| 1194 | } |
| 1195 | } |
| 1196 | |
| 1197 | static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) |
| 1198 | { |
| 1199 | int i; |
| 1200 | |
| 1201 | dce_v10_0_audio_get_connected_pins(adev); |
| 1202 | |
| 1203 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 1204 | if (adev->mode_info.audio.pin[i].connected) |
| 1205 | return &adev->mode_info.audio.pin[i]; |
| 1206 | } |
| 1207 | DRM_ERROR("No connected audio pins found!\n")__drm_err("No connected audio pins found!\n"); |
| 1208 | return NULL((void *)0); |
| 1209 | } |
| 1210 | |
| 1211 | static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) |
| 1212 | { |
| 1213 | struct amdgpu_device *adev = drm_to_adev(encoder->dev); |
| 1214 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1215 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1216 | u32 tmp; |
| 1217 | |
| 1218 | if (!dig || !dig->afmt || !dig->afmt->pin) |
| 1219 | return; |
| 1220 | |
| 1221 | tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a45 + dig->afmt->offset), 0 ); |
| 1222 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id)(((tmp) & ~0x7) | (0x7 & ((dig->afmt->pin->id ) << 0x0))); |
| 1223 | WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a45 + dig->afmt->offset), ( tmp), 0); |
| 1224 | } |
| 1225 | |
| 1226 | static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, |
| 1227 | struct drm_display_mode *mode) |
| 1228 | { |
| 1229 | struct drm_device *dev = encoder->dev; |
| 1230 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1231 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1232 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1233 | struct drm_connector *connector; |
| 1234 | struct drm_connector_list_iter iter; |
| 1235 | struct amdgpu_connector *amdgpu_connector = NULL((void *)0); |
| 1236 | u32 tmp; |
| 1237 | int interlace = 0; |
| 1238 | |
| 1239 | if (!dig || !dig->afmt || !dig->afmt->pin) |
| 1240 | return; |
| 1241 | |
| 1242 | drm_connector_list_iter_begin(dev, &iter); |
| 1243 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 1244 | if (connector->encoder == encoder) { |
| 1245 | amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) * __mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_connector, base) );}); |
| 1246 | break; |
| 1247 | } |
| 1248 | } |
| 1249 | drm_connector_list_iter_end(&iter); |
| 1250 | |
| 1251 | if (!amdgpu_connector) { |
| 1252 | DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n"); |
| 1253 | return; |
| 1254 | } |
| 1255 | |
| 1256 | if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 1257 | interlace = 1; |
| 1258 | if (connector->latency_present[interlace]) { |
| 1259 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff) | (0xff & ((connector->video_latency [interlace]) << 0x0))) |
Value stored to 'tmp' is never read | |
| 1260 | VIDEO_LIPSYNC, connector->video_latency[interlace])(((0) & ~0xff) | (0xff & ((connector->video_latency [interlace]) << 0x0))); |
| 1261 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff00) | (0xff00 & ((connector->audio_latency [interlace]) << 0x8))) |
| 1262 | AUDIO_LIPSYNC, connector->audio_latency[interlace])(((0) & ~0xff00) | (0xff00 & ((connector->audio_latency [interlace]) << 0x8))); |
| 1263 | } else { |
| 1264 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff) | (0xff & ((0) << 0x0))) |
| 1265 | VIDEO_LIPSYNC, 0)(((0) & ~0xff) | (0xff & ((0) << 0x0))); |
| 1266 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff00) | (0xff00 & ((0) << 0x8))) |
| 1267 | AUDIO_LIPSYNC, 0)(((0) & ~0xff00) | (0xff00 & ((0) << 0x8))); |
| 1268 | } |
| 1269 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset ), (0x37), (tmp)) |
| 1270 | ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset ), (0x37), (tmp)); |
| 1271 | } |
| 1272 | |
| 1273 | static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) |
| 1274 | { |
| 1275 | struct drm_device *dev = encoder->dev; |
| 1276 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1277 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1278 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1279 | struct drm_connector *connector; |
| 1280 | struct drm_connector_list_iter iter; |
| 1281 | struct amdgpu_connector *amdgpu_connector = NULL((void *)0); |
| 1282 | u32 tmp; |
| 1283 | u8 *sadb = NULL((void *)0); |
| 1284 | int sad_count; |
| 1285 | |
| 1286 | if (!dig || !dig->afmt || !dig->afmt->pin) |
| 1287 | return; |
| 1288 | |
| 1289 | drm_connector_list_iter_begin(dev, &iter); |
| 1290 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 1291 | if (connector->encoder == encoder) { |
| 1292 | amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) * __mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_connector, base) );}); |
| 1293 | break; |
| 1294 | } |
| 1295 | } |
| 1296 | drm_connector_list_iter_end(&iter); |
| 1297 | |
| 1298 | if (!amdgpu_connector) { |
| 1299 | DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n"); |
| 1300 | return; |
| 1301 | } |
| 1302 | |
| 1303 | sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); |
| 1304 | if (sad_count < 0) { |
| 1305 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count)__drm_err("Couldn't read Speaker Allocation Data Block: %d\n" , sad_count); |
| 1306 | sad_count = 0; |
| 1307 | } |
| 1308 | |
| 1309 | /* program the speaker allocation */ |
| 1310 | tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_rreg(adev, (dig->afmt->pin->offset ), (0x25)) |
| 1311 | ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)adev->audio_endpt_rreg(adev, (dig->afmt->pin->offset ), (0x25)); |
| 1312 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x20000) | (0x20000 & ((0) << 0x11)) ) |
| 1313 | DP_CONNECTION, 0)(((tmp) & ~0x20000) | (0x20000 & ((0) << 0x11)) ); |
| 1314 | /* set HDMI mode */ |
| 1315 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10)) ) |
| 1316 | HDMI_CONNECTION, 1)(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10)) ); |
| 1317 | if (sad_count) |
| 1318 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x7f) | (0x7f & ((sadb[0]) << 0x0))) |
| 1319 | SPEAKER_ALLOCATION, sadb[0])(((tmp) & ~0x7f) | (0x7f & ((sadb[0]) << 0x0))); |
| 1320 | else |
| 1321 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x7f) | (0x7f & ((5) << 0x0))) |
| 1322 | SPEAKER_ALLOCATION, 5)(((tmp) & ~0x7f) | (0x7f & ((5) << 0x0))); /* stereo */ |
| 1323 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset ), (0x25), (tmp)) |
| 1324 | ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset ), (0x25), (tmp)); |
| 1325 | |
| 1326 | kfree(sadb); |
| 1327 | } |
| 1328 | |
| 1329 | static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) |
| 1330 | { |
| 1331 | struct drm_device *dev = encoder->dev; |
| 1332 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1333 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1334 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1335 | struct drm_connector *connector; |
| 1336 | struct drm_connector_list_iter iter; |
| 1337 | struct amdgpu_connector *amdgpu_connector = NULL((void *)0); |
| 1338 | struct cea_sad *sads; |
| 1339 | int i, sad_count; |
| 1340 | |
| 1341 | static const u16 eld_reg_to_type[][2] = { |
| 1342 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR00x28, HDMI_AUDIO_CODING_TYPE_PCM }, |
| 1343 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10x29, HDMI_AUDIO_CODING_TYPE_AC3 }, |
| 1344 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR20x2a, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
| 1345 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR30x2b, HDMI_AUDIO_CODING_TYPE_MP3 }, |
| 1346 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR40x2c, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
| 1347 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR50x2d, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
| 1348 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR60x2e, HDMI_AUDIO_CODING_TYPE_DTS }, |
| 1349 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR70x2f, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
| 1350 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR90x31, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
| 1351 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR100x32, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
| 1352 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR110x33, HDMI_AUDIO_CODING_TYPE_MLP }, |
| 1353 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR130x35, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
| 1354 | }; |
| 1355 | |
| 1356 | if (!dig || !dig->afmt || !dig->afmt->pin) |
| 1357 | return; |
| 1358 | |
| 1359 | drm_connector_list_iter_begin(dev, &iter); |
| 1360 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 1361 | if (connector->encoder == encoder) { |
| 1362 | amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) * __mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_connector, base) );}); |
| 1363 | break; |
| 1364 | } |
| 1365 | } |
| 1366 | drm_connector_list_iter_end(&iter); |
| 1367 | |
| 1368 | if (!amdgpu_connector) { |
| 1369 | DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n"); |
| 1370 | return; |
| 1371 | } |
| 1372 | |
| 1373 | sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); |
| 1374 | if (sad_count < 0) |
| 1375 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count)__drm_err("Couldn't read SADs: %d\n", sad_count); |
| 1376 | if (sad_count <= 0) |
| 1377 | return; |
| 1378 | BUG_ON(!sads)((!(!sads)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/dce_v10_0.c" , 1378, "!(!sads)")); |
| 1379 | |
| 1380 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type)(sizeof((eld_reg_to_type)) / sizeof((eld_reg_to_type)[0])); i++) { |
| 1381 | u32 tmp = 0; |
| 1382 | u8 stereo_freqs = 0; |
| 1383 | int max_channels = -1; |
| 1384 | int j; |
| 1385 | |
| 1386 | for (j = 0; j < sad_count; j++) { |
| 1387 | struct cea_sad *sad = &sads[j]; |
| 1388 | |
| 1389 | if (sad->format == eld_reg_to_type[i][1]) { |
| 1390 | if (sad->channels > max_channels) { |
| 1391 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0x7) | (0x7 & ((sad->channels) << 0x0))) |
| 1392 | MAX_CHANNELS, sad->channels)(((tmp) & ~0x7) | (0x7 & ((sad->channels) << 0x0))); |
| 1393 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff0000) | (0xff0000 & ((sad->byte2) << 0x10))) |
| 1394 | DESCRIPTOR_BYTE_2, sad->byte2)(((tmp) & ~0xff0000) | (0xff0000 & ((sad->byte2) << 0x10))); |
| 1395 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff00) | (0xff00 & ((sad->freq) << 0x8))) |
| 1396 | SUPPORTED_FREQUENCIES, sad->freq)(((tmp) & ~0xff00) | (0xff00 & ((sad->freq) << 0x8))); |
| 1397 | max_channels = sad->channels; |
| 1398 | } |
| 1399 | |
| 1400 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
| 1401 | stereo_freqs |= sad->freq; |
| 1402 | else |
| 1403 | break; |
| 1404 | } |
| 1405 | } |
| 1406 | |
| 1407 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff000000) | (0xff000000 & ((stereo_freqs ) << 0x18))) |
| 1408 | SUPPORTED_FREQUENCIES_STEREO, stereo_freqs)(((tmp) & ~0xff000000) | (0xff000000 & ((stereo_freqs ) << 0x18))); |
| 1409 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset ), (eld_reg_to_type[i][0]), (tmp)); |
| 1410 | } |
| 1411 | |
| 1412 | kfree(sads); |
| 1413 | } |
| 1414 | |
| 1415 | static void dce_v10_0_audio_enable(struct amdgpu_device *adev, |
| 1416 | struct amdgpu_audio_pin *pin, |
| 1417 | bool_Bool enable) |
| 1418 | { |
| 1419 | if (!pin) |
| 1420 | return; |
| 1421 | |
| 1422 | WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,adev->audio_endpt_wreg(adev, (pin->offset), (0x54), (enable ? 0x80000000 : 0)) |
| 1423 | enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0)adev->audio_endpt_wreg(adev, (pin->offset), (0x54), (enable ? 0x80000000 : 0)); |
| 1424 | } |
| 1425 | |
| 1426 | static const u32 pin_offsets[] = |
| 1427 | { |
| 1428 | AUD0_REGISTER_OFFSET(0x17a8 - 0x17a8), |
| 1429 | AUD1_REGISTER_OFFSET(0x17ac - 0x17a8), |
| 1430 | AUD2_REGISTER_OFFSET(0x17b0 - 0x17a8), |
| 1431 | AUD3_REGISTER_OFFSET(0x17b4 - 0x17a8), |
| 1432 | AUD4_REGISTER_OFFSET(0x17b8 - 0x17a8), |
| 1433 | AUD5_REGISTER_OFFSET(0x17bc - 0x17a8), |
| 1434 | AUD6_REGISTER_OFFSET(0x17c0 - 0x17a8), |
| 1435 | }; |
| 1436 | |
| 1437 | static int dce_v10_0_audio_init(struct amdgpu_device *adev) |
| 1438 | { |
| 1439 | int i; |
| 1440 | |
| 1441 | if (!amdgpu_audio) |
| 1442 | return 0; |
| 1443 | |
| 1444 | adev->mode_info.audio.enabled = true1; |
| 1445 | |
| 1446 | adev->mode_info.audio.num_pins = 7; |
| 1447 | |
| 1448 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 1449 | adev->mode_info.audio.pin[i].channels = -1; |
| 1450 | adev->mode_info.audio.pin[i].rate = -1; |
| 1451 | adev->mode_info.audio.pin[i].bits_per_sample = -1; |
| 1452 | adev->mode_info.audio.pin[i].status_bits = 0; |
| 1453 | adev->mode_info.audio.pin[i].category_code = 0; |
| 1454 | adev->mode_info.audio.pin[i].connected = false0; |
| 1455 | adev->mode_info.audio.pin[i].offset = pin_offsets[i]; |
| 1456 | adev->mode_info.audio.pin[i].id = i; |
| 1457 | /* disable audio. it will be set up later */ |
| 1458 | /* XXX remove once we switch to ip funcs */ |
| 1459 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0); |
| 1460 | } |
| 1461 | |
| 1462 | return 0; |
| 1463 | } |
| 1464 | |
| 1465 | static void dce_v10_0_audio_fini(struct amdgpu_device *adev) |
| 1466 | { |
| 1467 | int i; |
| 1468 | |
| 1469 | if (!amdgpu_audio) |
| 1470 | return; |
| 1471 | |
| 1472 | if (!adev->mode_info.audio.enabled) |
| 1473 | return; |
| 1474 | |
| 1475 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) |
| 1476 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0); |
| 1477 | |
| 1478 | adev->mode_info.audio.enabled = false0; |
| 1479 | } |
| 1480 | |
| 1481 | /* |
| 1482 | * update the N and CTS parameters for a given pixel clock rate |
| 1483 | */ |
| 1484 | static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
| 1485 | { |
| 1486 | struct drm_device *dev = encoder->dev; |
| 1487 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1488 | struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); |
| 1489 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1490 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1491 | u32 tmp; |
| 1492 | |
| 1493 | tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a2e + dig->afmt->offset), 0 ); |
| 1494 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_32khz ) << 0xc))); |
| 1495 | WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a2e + dig->afmt->offset), ( tmp), 0); |
| 1496 | tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a2f + dig->afmt->offset), 0 ); |
| 1497 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_32khz) << 0x0))); |
| 1498 | WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a2f + dig->afmt->offset), ( tmp), 0); |
| 1499 | |
| 1500 | tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a30 + dig->afmt->offset), 0 ); |
| 1501 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_44_1khz ) << 0xc))); |
| 1502 | WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a30 + dig->afmt->offset), ( tmp), 0); |
| 1503 | tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a31 + dig->afmt->offset), 0 ); |
| 1504 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_44_1khz) << 0x0))); |
| 1505 | WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a31 + dig->afmt->offset), ( tmp), 0); |
| 1506 | |
| 1507 | tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a32 + dig->afmt->offset), 0 ); |
| 1508 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_48khz ) << 0xc))); |
| 1509 | WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a32 + dig->afmt->offset), ( tmp), 0); |
| 1510 | tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a33 + dig->afmt->offset), 0 ); |
| 1511 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_48khz) << 0x0))); |
| 1512 | WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a33 + dig->afmt->offset), ( tmp), 0); |
| 1513 | |
| 1514 | } |
| 1515 | |
| 1516 | /* |
| 1517 | * build a HDMI Video Info Frame |
| 1518 | */ |
| 1519 | static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, |
| 1520 | void *buffer, size_t size) |
| 1521 | { |
| 1522 | struct drm_device *dev = encoder->dev; |
| 1523 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1524 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1525 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1526 | uint8_t *frame = buffer + 3; |
| 1527 | uint8_t *header = buffer; |
| 1528 | |
| 1529 | WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a1e + dig->afmt->offset), ( frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16 ) | (frame[0x3] << 24)), 0) |
| 1530 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24))amdgpu_device_wreg(adev, (0x4a1e + dig->afmt->offset), ( frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16 ) | (frame[0x3] << 24)), 0); |
| 1531 | WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a1f + dig->afmt->offset), ( frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16 ) | (frame[0x7] << 24)), 0) |
| 1532 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24))amdgpu_device_wreg(adev, (0x4a1f + dig->afmt->offset), ( frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16 ) | (frame[0x7] << 24)), 0); |
| 1533 | WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a20 + dig->afmt->offset), ( frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16 ) | (frame[0xB] << 24)), 0) |
| 1534 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24))amdgpu_device_wreg(adev, (0x4a20 + dig->afmt->offset), ( frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16 ) | (frame[0xB] << 24)), 0); |
| 1535 | WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a21 + dig->afmt->offset), ( frame[0xC] | (frame[0xD] << 8) | (header[1] << 24 )), 0) |
| 1536 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24))amdgpu_device_wreg(adev, (0x4a21 + dig->afmt->offset), ( frame[0xC] | (frame[0xD] << 8) | (header[1] << 24 )), 0); |
| 1537 | } |
| 1538 | |
| 1539 | static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
| 1540 | { |
| 1541 | struct drm_device *dev = encoder->dev; |
| 1542 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1543 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1544 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1545 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) );}); |
| 1546 | u32 dto_phase = 24 * 1000; |
| 1547 | u32 dto_modulo = clock; |
| 1548 | u32 tmp; |
| 1549 | |
| 1550 | if (!dig || !dig->afmt) |
| 1551 | return; |
| 1552 | |
| 1553 | /* XXX two dtos; generally use dto0 for hdmi */ |
| 1554 | /* Express [24MHz / target pixel clock] as an exact rational |
| 1555 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 1556 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 1557 | */ |
| 1558 | tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE)amdgpu_device_rreg(adev, (0x16b), 0); |
| 1559 | tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,(((tmp) & ~0x7) | (0x7 & ((amdgpu_crtc->crtc_id) << 0x0))) |
| 1560 | amdgpu_crtc->crtc_id)(((tmp) & ~0x7) | (0x7 & ((amdgpu_crtc->crtc_id) << 0x0))); |
| 1561 | WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp)amdgpu_device_wreg(adev, (0x16b), (tmp), 0); |
| 1562 | WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase)amdgpu_device_wreg(adev, (0x16c), (dto_phase), 0); |
| 1563 | WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo)amdgpu_device_wreg(adev, (0x16d), (dto_modulo), 0); |
| 1564 | } |
| 1565 | |
| 1566 | /* |
| 1567 | * update the info frames with the data from the current display mode |
| 1568 | */ |
| 1569 | static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, |
| 1570 | struct drm_display_mode *mode) |
| 1571 | { |
| 1572 | struct drm_device *dev = encoder->dev; |
| 1573 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1574 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1575 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1576 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); |
| 1577 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE4 + HDMI_AVI_INFOFRAME_SIZE13]; |
| 1578 | struct hdmi_avi_infoframe frame; |
| 1579 | ssize_t err; |
| 1580 | u32 tmp; |
| 1581 | int bpc = 8; |
| 1582 | |
| 1583 | if (!dig || !dig->afmt) |
| 1584 | return; |
| 1585 | |
| 1586 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 1587 | if (!dig->afmt->enabled) |
| 1588 | return; |
| 1589 | |
| 1590 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ |
| 1591 | if (encoder->crtc) { |
| 1592 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) );}); |
| 1593 | bpc = amdgpu_crtc->bpc; |
| 1594 | } |
| 1595 | |
| 1596 | /* disable audio prior to setting up hw */ |
| 1597 | dig->afmt->pin = dce_v10_0_audio_get_pin(adev); |
| 1598 | dce_v10_0_audio_enable(adev, dig->afmt->pin, false0); |
| 1599 | |
| 1600 | dce_v10_0_audio_set_dto(encoder, mode->clock); |
| 1601 | |
| 1602 | tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0d + dig->afmt->offset), 0 ); |
| 1603 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
| 1604 | WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0d + dig->afmt->offset), ( tmp), 0); /* send null packets when required */ |
| 1605 | |
| 1606 | WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000)amdgpu_device_wreg(adev, (0x4a3a + dig->afmt->offset), ( 0x1000), 0); |
| 1607 | |
| 1608 | tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a09 + dig->afmt->offset), 0 ); |
| 1609 | switch (bpc) { |
| 1610 | case 0: |
| 1611 | case 6: |
| 1612 | case 8: |
| 1613 | case 16: |
| 1614 | default: |
| 1615 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0)(((tmp) & ~0x1000000) | (0x1000000 & ((0) << 0x18 ))); |
| 1616 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0)(((tmp) & ~0x30000000) | (0x30000000 & ((0) << 0x1c ))); |
| 1617 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Disabling hdmi deep color for %d bpc.\n" , connector->name, bpc) |
| 1618 | connector->name, bpc)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Disabling hdmi deep color for %d bpc.\n" , connector->name, bpc); |
| 1619 | break; |
| 1620 | case 10: |
| 1621 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1)(((tmp) & ~0x1000000) | (0x1000000 & ((1) << 0x18 ))); |
| 1622 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1)(((tmp) & ~0x30000000) | (0x30000000 & ((1) << 0x1c ))); |
| 1623 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Enabling hdmi deep color 30 for 10 bpc.\n" , connector->name) |
| 1624 | connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Enabling hdmi deep color 30 for 10 bpc.\n" , connector->name); |
| 1625 | break; |
| 1626 | case 12: |
| 1627 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1)(((tmp) & ~0x1000000) | (0x1000000 & ((1) << 0x18 ))); |
| 1628 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2)(((tmp) & ~0x30000000) | (0x30000000 & ((2) << 0x1c ))); |
| 1629 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Enabling hdmi deep color 36 for 12 bpc.\n" , connector->name) |
| 1630 | connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Enabling hdmi deep color 36 for 12 bpc.\n" , connector->name); |
| 1631 | break; |
| 1632 | } |
| 1633 | WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a09 + dig->afmt->offset), ( tmp), 0); |
| 1634 | |
| 1635 | tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0d + dig->afmt->offset), 0 ); |
| 1636 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); /* send null packets when required */ |
| 1637 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); /* send general control packets */ |
| 1638 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1)(((tmp) & ~0x20) | (0x20 & ((1) << 0x5))); /* send general control packets every frame */ |
| 1639 | WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0d + dig->afmt->offset), ( tmp), 0); |
| 1640 | |
| 1641 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0e + dig->afmt->offset), 0 ); |
| 1642 | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| 1643 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); |
| 1644 | /* required for audio info values to be updated */ |
| 1645 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1)(((tmp) & ~0x20) | (0x20 & ((1) << 0x5))); |
| 1646 | WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0e + dig->afmt->offset), ( tmp), 0); |
| 1647 | |
| 1648 | tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a44 + dig->afmt->offset), 0 ); |
| 1649 | /* required for audio info values to be updated */ |
| 1650 | tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1)(((tmp) & ~0x80) | (0x80 & ((1) << 0x7))); |
| 1651 | WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a44 + dig->afmt->offset), ( tmp), 0); |
| 1652 | |
| 1653 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0f + dig->afmt->offset), 0 ); |
| 1654 | /* anything other than 0 */ |
| 1655 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2)(((tmp) & ~0x3f00) | (0x3f00 & ((2) << 0x8))); |
| 1656 | WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0f + dig->afmt->offset), ( tmp), 0); |
| 1657 | |
| 1658 | WREG32(mmHDMI_GC + dig->afmt->offset, 0)amdgpu_device_wreg(adev, (0x4a13 + dig->afmt->offset), ( 0), 0); /* unset HDMI_GC_AVMUTE */ |
| 1659 | |
| 1660 | tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0b + dig->afmt->offset), 0 ); |
| 1661 | /* set the default audio delay */ |
| 1662 | tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1)(((tmp) & ~0x30) | (0x30 & ((1) << 0x4))); |
| 1663 | /* should be suffient for all audio modes and small enough for all hblanks */ |
| 1664 | tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3)(((tmp) & ~0x1f0000) | (0x1f0000 & ((3) << 0x10 ))); |
| 1665 | WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0b + dig->afmt->offset), ( tmp), 0); |
| 1666 | |
| 1667 | tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a42 + dig->afmt->offset), 0 ); |
| 1668 | /* allow 60958 channel status fields to be updated */ |
| 1669 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1)(((tmp) & ~0x4000000) | (0x4000000 & ((1) << 0x1a ))); |
| 1670 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a42 + dig->afmt->offset), ( tmp), 0); |
| 1671 | |
| 1672 | tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0c + dig->afmt->offset), 0 ); |
| 1673 | if (bpc > 8) |
| 1674 | /* clear SW CTS value */ |
| 1675 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8))); |
| 1676 | else |
| 1677 | /* select SW CTS value */ |
| 1678 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8))); |
| 1679 | /* allow hw to sent ACR packets when required */ |
| 1680 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1)(((tmp) & ~0x1000) | (0x1000 & ((1) << 0xc))); |
| 1681 | WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0c + dig->afmt->offset), ( tmp), 0); |
| 1682 | |
| 1683 | dce_v10_0_afmt_update_ACR(encoder, mode->clock); |
| 1684 | |
| 1685 | tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a38 + dig->afmt->offset), 0 ); |
| 1686 | tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1)(((tmp) & ~0xf00000) | (0xf00000 & ((1) << 0x14 ))); |
| 1687 | WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a38 + dig->afmt->offset), ( tmp), 0); |
| 1688 | |
| 1689 | tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a39 + dig->afmt->offset), 0 ); |
| 1690 | tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2)(((tmp) & ~0xf00000) | (0xf00000 & ((2) << 0x14 ))); |
| 1691 | WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a39 + dig->afmt->offset), ( tmp), 0); |
| 1692 | |
| 1693 | tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a3f + dig->afmt->offset), 0 ); |
| 1694 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3)(((tmp) & ~0xf) | (0xf & ((3) << 0x0))); |
| 1695 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4)(((tmp) & ~0xf0) | (0xf0 & ((4) << 0x4))); |
| 1696 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5)(((tmp) & ~0xf00) | (0xf00 & ((5) << 0x8))); |
| 1697 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6)(((tmp) & ~0xf000) | (0xf000 & ((6) << 0xc))); |
| 1698 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7)(((tmp) & ~0xf0000) | (0xf0000 & ((7) << 0x10)) ); |
| 1699 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8)(((tmp) & ~0xf00000) | (0xf00000 & ((8) << 0x14 ))); |
| 1700 | WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a3f + dig->afmt->offset), ( tmp), 0); |
| 1701 | |
| 1702 | dce_v10_0_audio_write_speaker_allocation(encoder); |
| 1703 | |
| 1704 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a14 + dig->afmt->offset), ( (0xff << 0x8)), 0) |
| 1705 | (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT))amdgpu_device_wreg(adev, (0x4a14 + dig->afmt->offset), ( (0xff << 0x8)), 0); |
| 1706 | |
| 1707 | dce_v10_0_afmt_audio_select_pin(encoder); |
| 1708 | dce_v10_0_audio_write_sad_regs(encoder); |
| 1709 | dce_v10_0_audio_write_latency_fields(encoder, mode); |
| 1710 | |
| 1711 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); |
| 1712 | if (err < 0) { |
| 1713 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err)__drm_err("failed to setup AVI infoframe: %zd\n", err); |
| 1714 | return; |
| 1715 | } |
| 1716 | |
| 1717 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 1718 | if (err < 0) { |
| 1719 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err)__drm_err("failed to pack AVI infoframe: %zd\n", err); |
| 1720 | return; |
| 1721 | } |
| 1722 | |
| 1723 | dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
| 1724 | |
| 1725 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0e + dig->afmt->offset), 0 ); |
| 1726 | /* enable AVI info frames */ |
| 1727 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
| 1728 | /* required for audio info values to be updated */ |
| 1729 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1))); |
| 1730 | WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0e + dig->afmt->offset), ( tmp), 0); |
| 1731 | |
| 1732 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0f + dig->afmt->offset), 0 ); |
| 1733 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2)(((tmp) & ~0x3f) | (0x3f & ((2) << 0x0))); |
| 1734 | WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0f + dig->afmt->offset), ( tmp), 0); |
| 1735 | |
| 1736 | tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a42 + dig->afmt->offset), 0 ); |
| 1737 | /* send audio packets */ |
| 1738 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
| 1739 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a42 + dig->afmt->offset), ( tmp), 0); |
| 1740 | |
| 1741 | WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF)amdgpu_device_wreg(adev, (0x4a3b + dig->afmt->offset), ( 0x00FFFFFF), 0); |
| 1742 | WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF)amdgpu_device_wreg(adev, (0x4a3c + dig->afmt->offset), ( 0x007FFFFF), 0); |
| 1743 | WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001)amdgpu_device_wreg(adev, (0x4a3d + dig->afmt->offset), ( 0x00000001), 0); |
| 1744 | WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001)amdgpu_device_wreg(adev, (0x4a3e + dig->afmt->offset), ( 0x00000001), 0); |
| 1745 | |
| 1746 | /* enable audio after to setting up hw */ |
| 1747 | dce_v10_0_audio_enable(adev, dig->afmt->pin, true1); |
| 1748 | } |
| 1749 | |
| 1750 | static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool_Bool enable) |
| 1751 | { |
| 1752 | struct drm_device *dev = encoder->dev; |
| 1753 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1754 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 1755 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1756 | |
| 1757 | if (!dig || !dig->afmt) |
| 1758 | return; |
| 1759 | |
| 1760 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 1761 | if (enable && dig->afmt->enabled) |
| 1762 | return; |
| 1763 | if (!enable && !dig->afmt->enabled) |
| 1764 | return; |
| 1765 | |
| 1766 | if (!enable && dig->afmt->pin) { |
| 1767 | dce_v10_0_audio_enable(adev, dig->afmt->pin, false0); |
| 1768 | dig->afmt->pin = NULL((void *)0); |
| 1769 | } |
| 1770 | |
| 1771 | dig->afmt->enabled = enable; |
| 1772 | |
| 1773 | DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%sabling AFMT interface @ 0x%04X for encoder 0x%x\n" , enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder ->encoder_id) |
| 1774 | enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id)___drm_dbg(((void *)0), DRM_UT_CORE, "%sabling AFMT interface @ 0x%04X for encoder 0x%x\n" , enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder ->encoder_id); |
| 1775 | } |
| 1776 | |
| 1777 | static int dce_v10_0_afmt_init(struct amdgpu_device *adev) |
| 1778 | { |
| 1779 | int i; |
| 1780 | |
| 1781 | for (i = 0; i < adev->mode_info.num_dig; i++) |
| 1782 | adev->mode_info.afmt[i] = NULL((void *)0); |
| 1783 | |
| 1784 | /* DCE10 has audio blocks tied to DIG encoders */ |
| 1785 | for (i = 0; i < adev->mode_info.num_dig; i++) { |
| 1786 | adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL(0x0001 | 0x0004)); |
| 1787 | if (adev->mode_info.afmt[i]) { |
| 1788 | adev->mode_info.afmt[i]->offset = dig_offsets[i]; |
| 1789 | adev->mode_info.afmt[i]->id = i; |
| 1790 | } else { |
| 1791 | int j; |
| 1792 | for (j = 0; j < i; j++) { |
| 1793 | kfree(adev->mode_info.afmt[j]); |
| 1794 | adev->mode_info.afmt[j] = NULL((void *)0); |
| 1795 | } |
| 1796 | return -ENOMEM12; |
| 1797 | } |
| 1798 | } |
| 1799 | return 0; |
| 1800 | } |
| 1801 | |
| 1802 | static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) |
| 1803 | { |
| 1804 | int i; |
| 1805 | |
| 1806 | for (i = 0; i < adev->mode_info.num_dig; i++) { |
| 1807 | kfree(adev->mode_info.afmt[i]); |
| 1808 | adev->mode_info.afmt[i] = NULL((void *)0); |
| 1809 | } |
| 1810 | } |
| 1811 | |
| 1812 | static const u32 vga_control_regs[6] = |
| 1813 | { |
| 1814 | mmD1VGA_CONTROL0xcc, |
| 1815 | mmD2VGA_CONTROL0xce, |
| 1816 | mmD3VGA_CONTROL0xf8, |
| 1817 | mmD4VGA_CONTROL0xf9, |
| 1818 | mmD5VGA_CONTROL0xfa, |
| 1819 | mmD6VGA_CONTROL0xfb, |
| 1820 | }; |
| 1821 | |
| 1822 | static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool_Bool enable) |
| 1823 | { |
| 1824 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 1825 | struct drm_device *dev = crtc->dev; |
| 1826 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1827 | u32 vga_control; |
| 1828 | |
| 1829 | vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id])amdgpu_device_rreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id ]), 0) & ~1; |
| 1830 | if (enable) |
| 1831 | WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1)amdgpu_device_wreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id ]), (vga_control | 1), 0); |
| 1832 | else |
| 1833 | WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control)amdgpu_device_wreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id ]), (vga_control), 0); |
| 1834 | } |
| 1835 | |
| 1836 | static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool_Bool enable) |
| 1837 | { |
| 1838 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 1839 | struct drm_device *dev = crtc->dev; |
| 1840 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1841 | |
| 1842 | if (enable) |
| 1843 | WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1)amdgpu_device_wreg(adev, (0x1a00 + amdgpu_crtc->crtc_offset ), (1), 0); |
| 1844 | else |
| 1845 | WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a00 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 1846 | } |
| 1847 | |
| 1848 | static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, |
| 1849 | struct drm_framebuffer *fb, |
| 1850 | int x, int y, int atomic) |
| 1851 | { |
| 1852 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 1853 | struct drm_device *dev = crtc->dev; |
| 1854 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 1855 | struct drm_framebuffer *target_fb; |
| 1856 | struct drm_gem_object *obj; |
| 1857 | struct amdgpu_bo *abo; |
| 1858 | uint64_t fb_location, tiling_flags; |
| 1859 | uint32_t fb_format, fb_pitch_pixels; |
| 1860 | u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE)(((0) & ~0x3) | (0x3 & ((ENDIAN_NONE) << 0x0))); |
| 1861 | u32 pipe_config; |
| 1862 | u32 tmp, viewport_w, viewport_h; |
| 1863 | int r; |
| 1864 | bool_Bool bypass_lut = false0; |
| 1865 | |
| 1866 | /* no fb bound */ |
| 1867 | if (!atomic && !crtc->primary->fb) { |
| 1868 | DRM_DEBUG_KMS("No FB bound\n")___drm_dbg(((void *)0), DRM_UT_KMS, "No FB bound\n"); |
| 1869 | return 0; |
| 1870 | } |
| 1871 | |
| 1872 | if (atomic) |
| 1873 | target_fb = fb; |
| 1874 | else |
| 1875 | target_fb = crtc->primary->fb; |
| 1876 | |
| 1877 | /* If atomic, assume fb object is pinned & idle & fenced and |
| 1878 | * just update base pointers |
| 1879 | */ |
| 1880 | obj = target_fb->obj[0]; |
| 1881 | abo = gem_to_amdgpu_bo(obj)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr = ((obj)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_bo, tbo.base) );}); |
| 1882 | r = amdgpu_bo_reserve(abo, false0); |
| 1883 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) |
| 1884 | return r; |
| 1885 | |
| 1886 | if (!atomic) { |
| 1887 | r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM0x4); |
| 1888 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) { |
| 1889 | amdgpu_bo_unreserve(abo); |
| 1890 | return -EINVAL22; |
| 1891 | } |
| 1892 | } |
| 1893 | fb_location = amdgpu_bo_gpu_offset(abo); |
| 1894 | |
| 1895 | amdgpu_bo_get_tiling_flags(abo, &tiling_flags); |
| 1896 | amdgpu_bo_unreserve(abo); |
| 1897 | |
| 1898 | pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG)(((__u64)(tiling_flags) >> 4) & 0x1f); |
| 1899 | |
| 1900 | switch (target_fb->format->format) { |
| 1901 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
| 1902 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0)(((0) & ~0x3) | (0x3 & ((0) << 0x0))); |
| 1903 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8) )); |
| 1904 | break; |
| 1905 | case DRM_FORMAT_XRGB4444((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 1906 | case DRM_FORMAT_ARGB4444((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 1907 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0))); |
| 1908 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2)(((fb_format) & ~0x700) | (0x700 & ((2) << 0x8) )); |
| 1909 | #ifdef __BIG_ENDIAN |
| 1910 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) << 0x0))) |
| 1911 | ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) << 0x0))); |
| 1912 | #endif |
| 1913 | break; |
| 1914 | case DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
| 1915 | case DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
| 1916 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0))); |
| 1917 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8) )); |
| 1918 | #ifdef __BIG_ENDIAN |
| 1919 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) << 0x0))) |
| 1920 | ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) << 0x0))); |
| 1921 | #endif |
| 1922 | break; |
| 1923 | case DRM_FORMAT_BGRX5551((__u32)('B') | ((__u32)('X') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
| 1924 | case DRM_FORMAT_BGRA5551((__u32)('B') | ((__u32)('A') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
| 1925 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0))); |
| 1926 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5)(((fb_format) & ~0x700) | (0x700 & ((5) << 0x8) )); |
| 1927 | #ifdef __BIG_ENDIAN |
| 1928 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) << 0x0))) |
| 1929 | ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) << 0x0))); |
| 1930 | #endif |
| 1931 | break; |
| 1932 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 1933 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0))); |
| 1934 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1)(((fb_format) & ~0x700) | (0x700 & ((1) << 0x8) )); |
| 1935 | #ifdef __BIG_ENDIAN |
| 1936 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) << 0x0))) |
| 1937 | ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) << 0x0))); |
| 1938 | #endif |
| 1939 | break; |
| 1940 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 1941 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 1942 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0))); |
| 1943 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8) )); |
| 1944 | #ifdef __BIG_ENDIAN |
| 1945 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) << 0x0))) |
| 1946 | ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) << 0x0))); |
| 1947 | #endif |
| 1948 | break; |
| 1949 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 1950 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 1951 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0))); |
| 1952 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1)(((fb_format) & ~0x700) | (0x700 & ((1) << 0x8) )); |
| 1953 | #ifdef __BIG_ENDIAN |
| 1954 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) << 0x0))) |
| 1955 | ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) << 0x0))); |
| 1956 | #endif |
| 1957 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
| 1958 | bypass_lut = true1; |
| 1959 | break; |
| 1960 | case DRM_FORMAT_BGRX1010102((__u32)('B') | ((__u32)('X') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 1961 | case DRM_FORMAT_BGRA1010102((__u32)('B') | ((__u32)('A') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 1962 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0))); |
| 1963 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4)(((fb_format) & ~0x700) | (0x700 & ((4) << 0x8) )); |
| 1964 | #ifdef __BIG_ENDIAN |
| 1965 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) << 0x0))) |
| 1966 | ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) << 0x0))); |
| 1967 | #endif |
| 1968 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
| 1969 | bypass_lut = true1; |
| 1970 | break; |
| 1971 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 1972 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 1973 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0))); |
| 1974 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8) )); |
| 1975 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2)(((fb_swap) & ~0x30) | (0x30 & ((2) << 0x4))); |
| 1976 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2)(((fb_swap) & ~0x300) | (0x300 & ((2) << 0x8))); |
| 1977 | #ifdef __BIG_ENDIAN |
| 1978 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) << 0x0))) |
| 1979 | ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) << 0x0))); |
| 1980 | #endif |
| 1981 | break; |
| 1982 | default: |
| 1983 | DRM_ERROR("Unsupported screen format %p4cc\n",__drm_err("Unsupported screen format %p4cc\n", &target_fb ->format->format) |
| 1984 | &target_fb->format->format)__drm_err("Unsupported screen format %p4cc\n", &target_fb ->format->format); |
| 1985 | return -EINVAL22; |
| 1986 | } |
| 1987 | |
| 1988 | if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)(((__u64)(tiling_flags) >> 0) & 0xf) == ARRAY_2D_TILED_THIN1) { |
| 1989 | unsigned bankw, bankh, mtaspect, tile_split, num_banks; |
| 1990 | |
| 1991 | bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH)(((__u64)(tiling_flags) >> 15) & 0x3); |
| 1992 | bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT)(((__u64)(tiling_flags) >> 17) & 0x3); |
| 1993 | mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT)(((__u64)(tiling_flags) >> 19) & 0x3); |
| 1994 | tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)(((__u64)(tiling_flags) >> 9) & 0x7); |
| 1995 | num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS)(((__u64)(tiling_flags) >> 21) & 0x3); |
| 1996 | |
| 1997 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks)(((fb_format) & ~0xc) | (0xc & ((num_banks) << 0x2 ))); |
| 1998 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_2D_TILED_THIN1 ) << 0x14))) |
| 1999 | ARRAY_2D_TILED_THIN1)(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_2D_TILED_THIN1 ) << 0x14))); |
| 2000 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,(((fb_format) & ~0xe000) | (0xe000 & ((tile_split) << 0xd))) |
| 2001 | tile_split)(((fb_format) & ~0xe000) | (0xe000 & ((tile_split) << 0xd))); |
| 2002 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw)(((fb_format) & ~0xc0) | (0xc0 & ((bankw) << 0x6 ))); |
| 2003 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh)(((fb_format) & ~0x1800) | (0x1800 & ((bankh) << 0xb))); |
| 2004 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,(((fb_format) & ~0xc0000) | (0xc0000 & ((mtaspect) << 0x12))) |
| 2005 | mtaspect)(((fb_format) & ~0xc0000) | (0xc0000 & ((mtaspect) << 0x12))); |
| 2006 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,(((fb_format) & ~0x60000000) | (0x60000000 & ((ADDR_SURF_MICRO_TILING_DISPLAY ) << 0x1d))) |
| 2007 | ADDR_SURF_MICRO_TILING_DISPLAY)(((fb_format) & ~0x60000000) | (0x60000000 & ((ADDR_SURF_MICRO_TILING_DISPLAY ) << 0x1d))); |
| 2008 | } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)(((__u64)(tiling_flags) >> 0) & 0xf) == ARRAY_1D_TILED_THIN1) { |
| 2009 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_1D_TILED_THIN1 ) << 0x14))) |
| 2010 | ARRAY_1D_TILED_THIN1)(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_1D_TILED_THIN1 ) << 0x14))); |
| 2011 | } |
| 2012 | |
| 2013 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,(((fb_format) & ~0x1f000000) | (0x1f000000 & ((pipe_config ) << 0x18))) |
| 2014 | pipe_config)(((fb_format) & ~0x1f000000) | (0x1f000000 & ((pipe_config ) << 0x18))); |
| 2015 | |
| 2016 | dce_v10_0_vga_enable(crtc, false0); |
| 2017 | |
| 2018 | /* Make sure surface address is updated at vertical blank rather than |
| 2019 | * horizontal blank |
| 2020 | */ |
| 2021 | tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset ), 0); |
| 2022 | tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,(((tmp) & ~0x1) | (0x1 & ((0) << 0x0))) |
| 2023 | GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0))); |
| 2024 | WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2025 | |
| 2026 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset ), (((u32)(((fb_location) >> 16) >> 16))), 0) |
| 2027 | upper_32_bits(fb_location))amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset ), (((u32)(((fb_location) >> 16) >> 16))), 0); |
| 2028 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a08 + amdgpu_crtc->crtc_offset ), (((u32)(((fb_location) >> 16) >> 16))), 0) |
| 2029 | upper_32_bits(fb_location))amdgpu_device_wreg(adev, (0x1a08 + amdgpu_crtc->crtc_offset ), (((u32)(((fb_location) >> 16) >> 16))), 0); |
| 2030 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset ), ((u32)fb_location & 0xffffff00), 0) |
| 2031 | (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK)amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset ), ((u32)fb_location & 0xffffff00), 0); |
| 2032 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a05 + amdgpu_crtc->crtc_offset ), ((u32) fb_location & 0xffffff00), 0) |
| 2033 | (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK)amdgpu_device_wreg(adev, (0x1a05 + amdgpu_crtc->crtc_offset ), ((u32) fb_location & 0xffffff00), 0); |
| 2034 | WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format)amdgpu_device_wreg(adev, (0x1a01 + amdgpu_crtc->crtc_offset ), (fb_format), 0); |
| 2035 | WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap)amdgpu_device_wreg(adev, (0x1a03 + amdgpu_crtc->crtc_offset ), (fb_swap), 0); |
| 2036 | |
| 2037 | /* |
| 2038 | * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT |
| 2039 | * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to |
| 2040 | * retain the full precision throughout the pipeline. |
| 2041 | */ |
| 2042 | tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a02 + amdgpu_crtc->crtc_offset ), 0); |
| 2043 | if (bypass_lut) |
| 2044 | tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8))); |
| 2045 | else |
| 2046 | tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8))); |
| 2047 | WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a02 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2048 | |
| 2049 | if (bypass_lut) |
| 2050 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Bypassing hardware LUT due to 10 bit fb scanout.\n" ); |
| 2051 | |
| 2052 | WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a09 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2053 | WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0a + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2054 | WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0b + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2055 | WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0c + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2056 | WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width)amdgpu_device_wreg(adev, (0x1a0d + amdgpu_crtc->crtc_offset ), (target_fb->width), 0); |
| 2057 | WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height)amdgpu_device_wreg(adev, (0x1a0e + amdgpu_crtc->crtc_offset ), (target_fb->height), 0); |
| 2058 | |
| 2059 | fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; |
| 2060 | WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels)amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset ), (fb_pitch_pixels), 0); |
| 2061 | |
| 2062 | dce_v10_0_grph_enable(crtc, true1); |
| 2063 | |
| 2064 | WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1ac3 + amdgpu_crtc->crtc_offset ), (target_fb->height), 0) |
| 2065 | target_fb->height)amdgpu_device_wreg(adev, (0x1ac3 + amdgpu_crtc->crtc_offset ), (target_fb->height), 0); |
| 2066 | |
| 2067 | x &= ~3; |
| 2068 | y &= ~1; |
| 2069 | WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1b5c + amdgpu_crtc->crtc_offset ), ((x << 16) | y), 0) |
| 2070 | (x << 16) | y)amdgpu_device_wreg(adev, (0x1b5c + amdgpu_crtc->crtc_offset ), ((x << 16) | y), 0); |
| 2071 | viewport_w = crtc->mode.hdisplay; |
| 2072 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
| 2073 | WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1b5d + amdgpu_crtc->crtc_offset ), ((viewport_w << 16) | viewport_h), 0) |
| 2074 | (viewport_w << 16) | viewport_h)amdgpu_device_wreg(adev, (0x1b5d + amdgpu_crtc->crtc_offset ), ((viewport_w << 16) | viewport_h), 0); |
| 2075 | |
| 2076 | /* set pageflip to happen anywhere in vblank interval */ |
| 2077 | WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1bbe + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2078 | |
| 2079 | if (!atomic && fb && fb != crtc->primary->fb) { |
| 2080 | abo = gem_to_amdgpu_bo(fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr = ((fb->obj[0])); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_bo, tbo.base) );}); |
| 2081 | r = amdgpu_bo_reserve(abo, true1); |
| 2082 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) |
| 2083 | return r; |
| 2084 | amdgpu_bo_unpin(abo); |
| 2085 | amdgpu_bo_unreserve(abo); |
| 2086 | } |
| 2087 | |
| 2088 | /* Bytes per pixel may have changed */ |
| 2089 | dce_v10_0_bandwidth_update(adev); |
| 2090 | |
| 2091 | return 0; |
| 2092 | } |
| 2093 | |
| 2094 | static void dce_v10_0_set_interleave(struct drm_crtc *crtc, |
| 2095 | struct drm_display_mode *mode) |
| 2096 | { |
| 2097 | struct drm_device *dev = crtc->dev; |
| 2098 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 2099 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2100 | u32 tmp; |
| 2101 | |
| 2102 | tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1ac0 + amdgpu_crtc->crtc_offset ), 0); |
| 2103 | if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 2104 | tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1)(((tmp) & ~0x8) | (0x8 & ((1) << 0x3))); |
| 2105 | else |
| 2106 | tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0)(((tmp) & ~0x8) | (0x8 & ((0) << 0x3))); |
| 2107 | WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1ac0 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2108 | } |
| 2109 | |
| 2110 | static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) |
| 2111 | { |
| 2112 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2113 | struct drm_device *dev = crtc->dev; |
| 2114 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 2115 | u16 *r, *g, *b; |
| 2116 | int i; |
| 2117 | u32 tmp; |
| 2118 | |
| 2119 | DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id)___drm_dbg(((void *)0), DRM_UT_KMS, "%d\n", amdgpu_crtc->crtc_id ); |
| 2120 | |
| 2121 | tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a35 + amdgpu_crtc->crtc_offset ), 0); |
| 2122 | tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0))); |
| 2123 | tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0)(((tmp) & ~0x30) | (0x30 & ((0) << 0x4))); |
| 2124 | WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a35 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2125 | |
| 2126 | tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a2d + amdgpu_crtc->crtc_offset ), 0); |
| 2127 | tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); |
| 2128 | WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a2d + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2129 | |
| 2130 | tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a31 + amdgpu_crtc->crtc_offset ), 0); |
| 2131 | tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); |
| 2132 | WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a31 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2133 | |
| 2134 | tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a10 + amdgpu_crtc->crtc_offset ), 0); |
| 2135 | tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0))); |
| 2136 | tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0)(((tmp) & ~0x30) | (0x30 & ((0) << 0x4))); |
| 2137 | WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a10 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2138 | |
| 2139 | WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a80 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2140 | |
| 2141 | WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a81 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2142 | WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a82 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2143 | WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a83 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2144 | |
| 2145 | WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a84 + amdgpu_crtc->crtc_offset ), (0xffff), 0); |
| 2146 | WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a85 + amdgpu_crtc->crtc_offset ), (0xffff), 0); |
| 2147 | WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a86 + amdgpu_crtc->crtc_offset ), (0xffff), 0); |
| 2148 | |
| 2149 | WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a78 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2150 | WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007)amdgpu_device_wreg(adev, (0x1a7e + amdgpu_crtc->crtc_offset ), (0x00000007), 0); |
| 2151 | |
| 2152 | WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a79 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2153 | r = crtc->gamma_store; |
| 2154 | g = r + crtc->gamma_size; |
| 2155 | b = g + crtc->gamma_size; |
| 2156 | for (i = 0; i < 256; i++) { |
| 2157 | WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset ), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0) |
| 2158 | ((*r++ & 0xffc0) << 14) |amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset ), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0) |
| 2159 | ((*g++ & 0xffc0) << 4) |amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset ), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0) |
| 2160 | (*b++ >> 6))amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset ), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) << 4) | (*b++ >> 6)), 0); |
| 2161 | } |
| 2162 | |
| 2163 | tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a58 + amdgpu_crtc->crtc_offset ), 0); |
| 2164 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0))); |
| 2165 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0)(((tmp) & ~0x30) | (0x30 & ((0) << 0x4))); |
| 2166 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0)(((tmp) & ~0x3000) | (0x3000 & ((0) << 0xc))); |
| 2167 | WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a58 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2168 | |
| 2169 | tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a59 + amdgpu_crtc->crtc_offset ), 0); |
| 2170 | tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0))); |
| 2171 | tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0)(((tmp) & ~0x30) | (0x30 & ((0) << 0x4))); |
| 2172 | WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a59 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2173 | |
| 2174 | tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1aa0 + amdgpu_crtc->crtc_offset ), 0); |
| 2175 | tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0)(((tmp) & ~0x7) | (0x7 & ((0) << 0x0))); |
| 2176 | tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0)(((tmp) & ~0x70) | (0x70 & ((0) << 0x4))); |
| 2177 | WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1aa0 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2178 | |
| 2179 | tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a3c + amdgpu_crtc->crtc_offset ), 0); |
| 2180 | tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0)(((tmp) & ~0x7) | (0x7 & ((0) << 0x0))); |
| 2181 | tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0)(((tmp) & ~0x70) | (0x70 & ((0) << 0x4))); |
| 2182 | WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a3c + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2183 | |
| 2184 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
| 2185 | WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a50 + amdgpu_crtc->crtc_offset ), (0), 0); |
| 2186 | /* XXX this only needs to be programmed once per crtc at startup, |
| 2187 | * not sure where the best place for it is |
| 2188 | */ |
| 2189 | tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1abc + amdgpu_crtc->crtc_offset ), 0); |
| 2190 | tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1))); |
| 2191 | WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1abc + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2192 | } |
| 2193 | |
| 2194 | static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) |
| 2195 | { |
| 2196 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 2197 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 2198 | |
| 2199 | switch (amdgpu_encoder->encoder_id) { |
| 2200 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E: |
| 2201 | if (dig->linkb) |
| 2202 | return 1; |
| 2203 | else |
| 2204 | return 0; |
| 2205 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20: |
| 2206 | if (dig->linkb) |
| 2207 | return 3; |
| 2208 | else |
| 2209 | return 2; |
| 2210 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21: |
| 2211 | if (dig->linkb) |
| 2212 | return 5; |
| 2213 | else |
| 2214 | return 4; |
| 2215 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25: |
| 2216 | return 6; |
| 2217 | default: |
| 2218 | DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id)__drm_err("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id ); |
| 2219 | return 0; |
| 2220 | } |
| 2221 | } |
| 2222 | |
| 2223 | /** |
| 2224 | * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. |
| 2225 | * |
| 2226 | * @crtc: drm crtc |
| 2227 | * |
| 2228 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors |
| 2229 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP |
| 2230 | * monitors a dedicated PPLL must be used. If a particular board has |
| 2231 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming |
| 2232 | * as there is no need to program the PLL itself. If we are not able to |
| 2233 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to |
| 2234 | * avoid messing up an existing monitor. |
| 2235 | * |
| 2236 | * Asic specific PLL information |
| 2237 | * |
| 2238 | * DCE 10.x |
| 2239 | * Tonga |
| 2240 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) |
| 2241 | * CI |
| 2242 | * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
| 2243 | * |
| 2244 | */ |
| 2245 | static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) |
| 2246 | { |
| 2247 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2248 | struct drm_device *dev = crtc->dev; |
| 2249 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 2250 | u32 pll_in_use; |
| 2251 | int pll; |
| 2252 | |
| 2253 | if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))(((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder )) == 0) || ((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc ->encoder)) == 5))) { |
| 2254 | if (adev->clock.dp_extclk) |
| 2255 | /* skip PPLL programming if using ext clock */ |
| 2256 | return ATOM_PPLL_INVALID0xFF; |
| 2257 | else { |
| 2258 | /* use the same PPLL for all DP monitors */ |
| 2259 | pll = amdgpu_pll_get_shared_dp_ppll(crtc); |
| 2260 | if (pll != ATOM_PPLL_INVALID0xFF) |
| 2261 | return pll; |
| 2262 | } |
| 2263 | } else { |
| 2264 | /* use the same PPLL for all monitors with the same clock */ |
| 2265 | pll = amdgpu_pll_get_shared_nondp_ppll(crtc); |
| 2266 | if (pll != ATOM_PPLL_INVALID0xFF) |
| 2267 | return pll; |
| 2268 | } |
| 2269 | |
| 2270 | /* DCE10 has PPLL0, PPLL1, and PPLL2 */ |
| 2271 | pll_in_use = amdgpu_pll_get_use_mask(crtc); |
| 2272 | if (!(pll_in_use & (1 << ATOM_PPLL21))) |
| 2273 | return ATOM_PPLL21; |
| 2274 | if (!(pll_in_use & (1 << ATOM_PPLL10))) |
| 2275 | return ATOM_PPLL10; |
| 2276 | if (!(pll_in_use & (1 << ATOM_PPLL02))) |
| 2277 | return ATOM_PPLL02; |
| 2278 | DRM_ERROR("unable to allocate a PPLL\n")__drm_err("unable to allocate a PPLL\n"); |
| 2279 | return ATOM_PPLL_INVALID0xFF; |
| 2280 | } |
| 2281 | |
| 2282 | static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool_Bool lock) |
| 2283 | { |
| 2284 | struct amdgpu_device *adev = drm_to_adev(crtc->dev); |
| 2285 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2286 | uint32_t cur_lock; |
| 2287 | |
| 2288 | cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a6e + amdgpu_crtc->crtc_offset ), 0); |
| 2289 | if (lock) |
| 2290 | cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1)(((cur_lock) & ~0x10000) | (0x10000 & ((1) << 0x10 ))); |
| 2291 | else |
| 2292 | cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0)(((cur_lock) & ~0x10000) | (0x10000 & ((0) << 0x10 ))); |
| 2293 | WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock)amdgpu_device_wreg(adev, (0x1a6e + amdgpu_crtc->crtc_offset ), (cur_lock), 0); |
| 2294 | } |
| 2295 | |
| 2296 | static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) |
| 2297 | { |
| 2298 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2299 | struct amdgpu_device *adev = drm_to_adev(crtc->dev); |
| 2300 | u32 tmp; |
| 2301 | |
| 2302 | tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset ), 0); |
| 2303 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0))); |
| 2304 | WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2305 | } |
| 2306 | |
| 2307 | static void dce_v10_0_show_cursor(struct drm_crtc *crtc) |
| 2308 | { |
| 2309 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2310 | struct amdgpu_device *adev = drm_to_adev(crtc->dev); |
| 2311 | u32 tmp; |
| 2312 | |
| 2313 | WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a69 + amdgpu_crtc->crtc_offset ), (((u32)(((amdgpu_crtc->cursor_addr) >> 16) >> 16))), 0) |
| 2314 | upper_32_bits(amdgpu_crtc->cursor_addr))amdgpu_device_wreg(adev, (0x1a69 + amdgpu_crtc->crtc_offset ), (((u32)(((amdgpu_crtc->cursor_addr) >> 16) >> 16))), 0); |
| 2315 | WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a67 + amdgpu_crtc->crtc_offset ), (((u32)(amdgpu_crtc->cursor_addr))), 0) |
| 2316 | lower_32_bits(amdgpu_crtc->cursor_addr))amdgpu_device_wreg(adev, (0x1a67 + amdgpu_crtc->crtc_offset ), (((u32)(amdgpu_crtc->cursor_addr))), 0); |
| 2317 | |
| 2318 | tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset ), 0); |
| 2319 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
| 2320 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2)(((tmp) & ~0x300) | (0x300 & ((2) << 0x8))); |
| 2321 | WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset ), (tmp), 0); |
| 2322 | } |
| 2323 | |
| 2324 | static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, |
| 2325 | int x, int y) |
| 2326 | { |
| 2327 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2328 | struct amdgpu_device *adev = drm_to_adev(crtc->dev); |
| 2329 | int xorigin = 0, yorigin = 0; |
| 2330 | |
| 2331 | amdgpu_crtc->cursor_x = x; |
| 2332 | amdgpu_crtc->cursor_y = y; |
| 2333 | |
| 2334 | /* avivo cursor are offset into the total surface */ |
| 2335 | x += crtc->x; |
| 2336 | y += crtc->y; |
| 2337 | DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y)___drm_dbg(((void *)0), DRM_UT_CORE, "x %d y %d c->x %d c->y %d\n" , x, y, crtc->x, crtc->y); |
| 2338 | |
| 2339 | if (x < 0) { |
| 2340 | xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1)(((-x)<(amdgpu_crtc->max_cursor_width - 1))?(-x):(amdgpu_crtc ->max_cursor_width - 1)); |
| 2341 | x = 0; |
| 2342 | } |
| 2343 | if (y < 0) { |
| 2344 | yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1)(((-y)<(amdgpu_crtc->max_cursor_height - 1))?(-y):(amdgpu_crtc ->max_cursor_height - 1)); |
| 2345 | y = 0; |
| 2346 | } |
| 2347 | |
| 2348 | WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y)amdgpu_device_wreg(adev, (0x1a6a + amdgpu_crtc->crtc_offset ), ((x << 16) | y), 0); |
| 2349 | WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin)amdgpu_device_wreg(adev, (0x1a6b + amdgpu_crtc->crtc_offset ), ((xorigin << 16) | yorigin), 0); |
| 2350 | WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a68 + amdgpu_crtc->crtc_offset ), (((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc ->cursor_height - 1)), 0) |
| 2351 | ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1))amdgpu_device_wreg(adev, (0x1a68 + amdgpu_crtc->crtc_offset ), (((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc ->cursor_height - 1)), 0); |
| 2352 | |
| 2353 | return 0; |
| 2354 | } |
| 2355 | |
| 2356 | static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, |
| 2357 | int x, int y) |
| 2358 | { |
| 2359 | int ret; |
| 2360 | |
| 2361 | dce_v10_0_lock_cursor(crtc, true1); |
| 2362 | ret = dce_v10_0_cursor_move_locked(crtc, x, y); |
| 2363 | dce_v10_0_lock_cursor(crtc, false0); |
| 2364 | |
| 2365 | return ret; |
| 2366 | } |
| 2367 | |
| 2368 | static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, |
| 2369 | struct drm_file *file_priv, |
| 2370 | uint32_t handle, |
| 2371 | uint32_t width, |
| 2372 | uint32_t height, |
| 2373 | int32_t hot_x, |
| 2374 | int32_t hot_y) |
| 2375 | { |
| 2376 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2377 | struct drm_gem_object *obj; |
| 2378 | struct amdgpu_bo *aobj; |
| 2379 | int ret; |
| 2380 | |
| 2381 | if (!handle) { |
| 2382 | /* turn off cursor */ |
| 2383 | dce_v10_0_hide_cursor(crtc); |
| 2384 | obj = NULL((void *)0); |
| 2385 | goto unpin; |
| 2386 | } |
| 2387 | |
| 2388 | if ((width > amdgpu_crtc->max_cursor_width) || |
| 2389 | (height > amdgpu_crtc->max_cursor_height)) { |
| 2390 | DRM_ERROR("bad cursor width or height %d x %d\n", width, height)__drm_err("bad cursor width or height %d x %d\n", width, height ); |
| 2391 | return -EINVAL22; |
| 2392 | } |
| 2393 | |
| 2394 | obj = drm_gem_object_lookup(file_priv, handle); |
| 2395 | if (!obj) { |
| 2396 | DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id)__drm_err("Cannot find cursor object %x for crtc %d\n", handle , amdgpu_crtc->crtc_id); |
| 2397 | return -ENOENT2; |
| 2398 | } |
| 2399 | |
| 2400 | aobj = gem_to_amdgpu_bo(obj)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr = ((obj)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_bo, tbo.base) );}); |
| 2401 | ret = amdgpu_bo_reserve(aobj, false0); |
| 2402 | if (ret != 0) { |
| 2403 | drm_gem_object_put(obj); |
| 2404 | return ret; |
| 2405 | } |
| 2406 | |
| 2407 | ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM0x4); |
| 2408 | amdgpu_bo_unreserve(aobj); |
| 2409 | if (ret) { |
| 2410 | DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret)__drm_err("Failed to pin new cursor BO (%d)\n", ret); |
| 2411 | drm_gem_object_put(obj); |
| 2412 | return ret; |
| 2413 | } |
| 2414 | amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); |
| 2415 | |
| 2416 | dce_v10_0_lock_cursor(crtc, true1); |
| 2417 | |
| 2418 | if (width != amdgpu_crtc->cursor_width || |
| 2419 | height != amdgpu_crtc->cursor_height || |
| 2420 | hot_x != amdgpu_crtc->cursor_hot_x || |
| 2421 | hot_y != amdgpu_crtc->cursor_hot_y) { |
| 2422 | int x, y; |
| 2423 | |
| 2424 | x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; |
| 2425 | y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; |
| 2426 | |
| 2427 | dce_v10_0_cursor_move_locked(crtc, x, y); |
| 2428 | |
| 2429 | amdgpu_crtc->cursor_width = width; |
| 2430 | amdgpu_crtc->cursor_height = height; |
| 2431 | amdgpu_crtc->cursor_hot_x = hot_x; |
| 2432 | amdgpu_crtc->cursor_hot_y = hot_y; |
| 2433 | } |
| 2434 | |
| 2435 | dce_v10_0_show_cursor(crtc); |
| 2436 | dce_v10_0_lock_cursor(crtc, false0); |
| 2437 | |
| 2438 | unpin: |
| 2439 | if (amdgpu_crtc->cursor_bo) { |
| 2440 | struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr = ((amdgpu_crtc->cursor_bo)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_bo, tbo.base) ); }); |
| 2441 | ret = amdgpu_bo_reserve(aobj, true1); |
| 2442 | if (likely(ret == 0)__builtin_expect(!!(ret == 0), 1)) { |
| 2443 | amdgpu_bo_unpin(aobj); |
| 2444 | amdgpu_bo_unreserve(aobj); |
| 2445 | } |
| 2446 | drm_gem_object_put(amdgpu_crtc->cursor_bo); |
| 2447 | } |
| 2448 | |
| 2449 | amdgpu_crtc->cursor_bo = obj; |
| 2450 | return 0; |
| 2451 | } |
| 2452 | |
| 2453 | static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) |
| 2454 | { |
| 2455 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2456 | |
| 2457 | if (amdgpu_crtc->cursor_bo) { |
| 2458 | dce_v10_0_lock_cursor(crtc, true1); |
| 2459 | |
| 2460 | dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, |
| 2461 | amdgpu_crtc->cursor_y); |
| 2462 | |
| 2463 | dce_v10_0_show_cursor(crtc); |
| 2464 | |
| 2465 | dce_v10_0_lock_cursor(crtc, false0); |
| 2466 | } |
| 2467 | } |
| 2468 | |
| 2469 | static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 2470 | u16 *blue, uint32_t size, |
| 2471 | struct drm_modeset_acquire_ctx *ctx) |
| 2472 | { |
| 2473 | dce_v10_0_crtc_load_lut(crtc); |
| 2474 | |
| 2475 | return 0; |
| 2476 | } |
| 2477 | |
| 2478 | static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) |
| 2479 | { |
| 2480 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2481 | |
| 2482 | drm_crtc_cleanup(crtc); |
| 2483 | kfree(amdgpu_crtc); |
| 2484 | } |
| 2485 | |
| 2486 | static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { |
| 2487 | .cursor_set2 = dce_v10_0_crtc_cursor_set2, |
| 2488 | .cursor_move = dce_v10_0_crtc_cursor_move, |
| 2489 | .gamma_set = dce_v10_0_crtc_gamma_set, |
| 2490 | .set_config = amdgpu_display_crtc_set_config, |
| 2491 | .destroy = dce_v10_0_crtc_destroy, |
| 2492 | .page_flip_target = amdgpu_display_crtc_page_flip_target, |
| 2493 | .get_vblank_counter = amdgpu_get_vblank_counter_kms, |
| 2494 | .enable_vblank = amdgpu_enable_vblank_kms, |
| 2495 | .disable_vblank = amdgpu_disable_vblank_kms, |
| 2496 | .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, |
| 2497 | }; |
| 2498 | |
| 2499 | static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2500 | { |
| 2501 | struct drm_device *dev = crtc->dev; |
| 2502 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 2503 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2504 | unsigned type; |
| 2505 | |
| 2506 | switch (mode) { |
| 2507 | case DRM_MODE_DPMS_ON0: |
| 2508 | amdgpu_crtc->enabled = true1; |
| 2509 | amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE1); |
| 2510 | dce_v10_0_vga_enable(crtc, true1); |
| 2511 | amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE0); |
| 2512 | dce_v10_0_vga_enable(crtc, false0); |
| 2513 | /* Make sure VBLANK and PFLIP interrupts are still enabled */ |
| 2514 | type = amdgpu_display_crtc_idx_to_irq_type(adev, |
| 2515 | amdgpu_crtc->crtc_id); |
| 2516 | amdgpu_irq_update(adev, &adev->crtc_irq, type); |
| 2517 | amdgpu_irq_update(adev, &adev->pageflip_irq, type); |
| 2518 | drm_crtc_vblank_on(crtc); |
| 2519 | dce_v10_0_crtc_load_lut(crtc); |
| 2520 | break; |
| 2521 | case DRM_MODE_DPMS_STANDBY1: |
| 2522 | case DRM_MODE_DPMS_SUSPEND2: |
| 2523 | case DRM_MODE_DPMS_OFF3: |
| 2524 | drm_crtc_vblank_off(crtc); |
| 2525 | if (amdgpu_crtc->enabled) { |
| 2526 | dce_v10_0_vga_enable(crtc, true1); |
| 2527 | amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE1); |
| 2528 | dce_v10_0_vga_enable(crtc, false0); |
| 2529 | } |
| 2530 | amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE0); |
| 2531 | amdgpu_crtc->enabled = false0; |
| 2532 | break; |
| 2533 | } |
| 2534 | /* adjust pm to dpms */ |
| 2535 | amdgpu_dpm_compute_clocks(adev); |
| 2536 | } |
| 2537 | |
| 2538 | static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) |
| 2539 | { |
| 2540 | /* disable crtc pair power gating before programming */ |
| 2541 | amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE0); |
| 2542 | amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE1); |
| 2543 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF3); |
| 2544 | } |
| 2545 | |
| 2546 | static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) |
| 2547 | { |
| 2548 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON0); |
| 2549 | amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE0); |
| 2550 | } |
| 2551 | |
| 2552 | static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) |
| 2553 | { |
| 2554 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2555 | struct drm_device *dev = crtc->dev; |
| 2556 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 2557 | struct amdgpu_atom_ss ss; |
| 2558 | int i; |
| 2559 | |
| 2560 | dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF3); |
| 2561 | if (crtc->primary->fb) { |
| 2562 | int r; |
| 2563 | struct amdgpu_bo *abo; |
| 2564 | |
| 2565 | abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr = ((crtc->primary->fb->obj[0])); (struct amdgpu_bo * )( (char *)__mptr - __builtin_offsetof(struct amdgpu_bo, tbo. base) );}); |
| 2566 | r = amdgpu_bo_reserve(abo, true1); |
| 2567 | if (unlikely(r)__builtin_expect(!!(r), 0)) |
| 2568 | DRM_ERROR("failed to reserve abo before unpin\n")__drm_err("failed to reserve abo before unpin\n"); |
| 2569 | else { |
| 2570 | amdgpu_bo_unpin(abo); |
| 2571 | amdgpu_bo_unreserve(abo); |
| 2572 | } |
| 2573 | } |
| 2574 | /* disable the GRPH */ |
| 2575 | dce_v10_0_grph_enable(crtc, false0); |
| 2576 | |
| 2577 | amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE1); |
| 2578 | |
| 2579 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 2580 | if (adev->mode_info.crtcs[i] && |
| 2581 | adev->mode_info.crtcs[i]->enabled && |
| 2582 | i != amdgpu_crtc->crtc_id && |
| 2583 | amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { |
| 2584 | /* one other crtc is using this pll don't turn |
| 2585 | * off the pll |
| 2586 | */ |
| 2587 | goto done; |
| 2588 | } |
| 2589 | } |
| 2590 | |
| 2591 | switch (amdgpu_crtc->pll_id) { |
| 2592 | case ATOM_PPLL02: |
| 2593 | case ATOM_PPLL10: |
| 2594 | case ATOM_PPLL21: |
| 2595 | /* disable the ppll */ |
| 2596 | amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, |
| 2597 | 0, 0, ATOM_DISABLE0, 0, 0, 0, 0, 0, false0, &ss); |
| 2598 | break; |
| 2599 | default: |
| 2600 | break; |
| 2601 | } |
| 2602 | done: |
| 2603 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID0xFF; |
| 2604 | amdgpu_crtc->adjusted_clock = 0; |
| 2605 | amdgpu_crtc->encoder = NULL((void *)0); |
| 2606 | amdgpu_crtc->connector = NULL((void *)0); |
| 2607 | } |
| 2608 | |
| 2609 | static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, |
| 2610 | struct drm_display_mode *mode, |
| 2611 | struct drm_display_mode *adjusted_mode, |
| 2612 | int x, int y, struct drm_framebuffer *old_fb) |
| 2613 | { |
| 2614 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2615 | |
| 2616 | if (!amdgpu_crtc->adjusted_clock) |
| 2617 | return -EINVAL22; |
| 2618 | |
| 2619 | amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); |
| 2620 | amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); |
| 2621 | dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); |
| 2622 | amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); |
| 2623 | amdgpu_atombios_crtc_scaler_setup(crtc); |
| 2624 | dce_v10_0_cursor_reset(crtc); |
| 2625 | /* update the hw version fpr dpm */ |
| 2626 | amdgpu_crtc->hw_mode = *adjusted_mode; |
| 2627 | |
| 2628 | return 0; |
| 2629 | } |
| 2630 | |
| 2631 | static bool_Bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, |
| 2632 | const struct drm_display_mode *mode, |
| 2633 | struct drm_display_mode *adjusted_mode) |
| 2634 | { |
| 2635 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 2636 | struct drm_device *dev = crtc->dev; |
| 2637 | struct drm_encoder *encoder; |
| 2638 | |
| 2639 | /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ |
| 2640 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> head ) *__mptr = ((&dev->mode_config.encoder_list)-> next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), head) );}); &encoder->head != (& dev->mode_config.encoder_list); encoder = ({ const __typeof ( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder-> head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), head) );})) { |
| 2641 | if (encoder->crtc == crtc) { |
| 2642 | amdgpu_crtc->encoder = encoder; |
| 2643 | amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); |
| 2644 | break; |
| 2645 | } |
| 2646 | } |
| 2647 | if ((amdgpu_crtc->encoder == NULL((void *)0)) || (amdgpu_crtc->connector == NULL((void *)0))) { |
| 2648 | amdgpu_crtc->encoder = NULL((void *)0); |
| 2649 | amdgpu_crtc->connector = NULL((void *)0); |
| 2650 | return false0; |
| 2651 | } |
| 2652 | if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
| 2653 | return false0; |
| 2654 | if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
| 2655 | return false0; |
| 2656 | /* pick pll */ |
| 2657 | amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); |
| 2658 | /* if we can't get a PPLL for a non-DP encoder, fail */ |
| 2659 | if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID0xFF) && |
| 2660 | !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))(((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder )) == 0) || ((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc ->encoder)) == 5))) |
| 2661 | return false0; |
| 2662 | |
| 2663 | return true1; |
| 2664 | } |
| 2665 | |
| 2666 | static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 2667 | struct drm_framebuffer *old_fb) |
| 2668 | { |
| 2669 | return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); |
| 2670 | } |
| 2671 | |
| 2672 | static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, |
| 2673 | struct drm_framebuffer *fb, |
| 2674 | int x, int y, enum mode_set_atomic state) |
| 2675 | { |
| 2676 | return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); |
| 2677 | } |
| 2678 | |
| 2679 | static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { |
| 2680 | .dpms = dce_v10_0_crtc_dpms, |
| 2681 | .mode_fixup = dce_v10_0_crtc_mode_fixup, |
| 2682 | .mode_set = dce_v10_0_crtc_mode_set, |
| 2683 | .mode_set_base = dce_v10_0_crtc_set_base, |
| 2684 | .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, |
| 2685 | .prepare = dce_v10_0_crtc_prepare, |
| 2686 | .commit = dce_v10_0_crtc_commit, |
| 2687 | .disable = dce_v10_0_crtc_disable, |
| 2688 | .get_scanout_position = amdgpu_crtc_get_scanout_position, |
| 2689 | }; |
| 2690 | |
| 2691 | static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) |
| 2692 | { |
| 2693 | struct amdgpu_crtc *amdgpu_crtc; |
| 2694 | |
| 2695 | amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + |
| 2696 | (AMDGPUFB_CONN_LIMIT4 * sizeof(struct drm_connector *)), GFP_KERNEL(0x0001 | 0x0004)); |
| 2697 | if (amdgpu_crtc == NULL((void *)0)) |
| 2698 | return -ENOMEM12; |
| 2699 | |
| 2700 | drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); |
| 2701 | |
| 2702 | drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); |
| 2703 | amdgpu_crtc->crtc_id = index; |
| 2704 | adev->mode_info.crtcs[index] = amdgpu_crtc; |
| 2705 | |
| 2706 | amdgpu_crtc->max_cursor_width = 128; |
| 2707 | amdgpu_crtc->max_cursor_height = 128; |
| 2708 | adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; |
| 2709 | adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; |
| 2710 | |
| 2711 | switch (amdgpu_crtc->crtc_id) { |
| 2712 | case 0: |
| 2713 | default: |
| 2714 | amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET(0x1b9c - 0x1b9c); |
| 2715 | break; |
| 2716 | case 1: |
| 2717 | amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET(0x1d9c - 0x1b9c); |
| 2718 | break; |
| 2719 | case 2: |
| 2720 | amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET(0x1f9c - 0x1b9c); |
| 2721 | break; |
| 2722 | case 3: |
| 2723 | amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET(0x419c - 0x1b9c); |
| 2724 | break; |
| 2725 | case 4: |
| 2726 | amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET(0x439c - 0x1b9c); |
| 2727 | break; |
| 2728 | case 5: |
| 2729 | amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET(0x459c - 0x1b9c); |
| 2730 | break; |
| 2731 | } |
| 2732 | |
| 2733 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID0xFF; |
| 2734 | amdgpu_crtc->adjusted_clock = 0; |
| 2735 | amdgpu_crtc->encoder = NULL((void *)0); |
| 2736 | amdgpu_crtc->connector = NULL((void *)0); |
| 2737 | drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); |
| 2738 | |
| 2739 | return 0; |
| 2740 | } |
| 2741 | |
| 2742 | static int dce_v10_0_early_init(void *handle) |
| 2743 | { |
| 2744 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2745 | |
| 2746 | adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; |
| 2747 | adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; |
| 2748 | |
| 2749 | dce_v10_0_set_display_funcs(adev); |
| 2750 | |
| 2751 | adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); |
| 2752 | |
| 2753 | switch (adev->asic_type) { |
| 2754 | case CHIP_FIJI: |
| 2755 | case CHIP_TONGA: |
| 2756 | adev->mode_info.num_hpd = 6; |
| 2757 | adev->mode_info.num_dig = 7; |
| 2758 | break; |
| 2759 | default: |
| 2760 | /* FIXME: not supported yet */ |
| 2761 | return -EINVAL22; |
| 2762 | } |
| 2763 | |
| 2764 | dce_v10_0_set_irq_funcs(adev); |
| 2765 | |
| 2766 | return 0; |
| 2767 | } |
| 2768 | |
| 2769 | static int dce_v10_0_sw_init(void *handle) |
| 2770 | { |
| 2771 | int r, i; |
| 2772 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2773 | |
| 2774 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 2775 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, i + 1, &adev->crtc_irq); |
| 2776 | if (r) |
| 2777 | return r; |
| 2778 | } |
| 2779 | |
| 2780 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8; i < 20; i += 2) { |
| 2781 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, i, &adev->pageflip_irq); |
| 2782 | if (r) |
| 2783 | return r; |
| 2784 | } |
| 2785 | |
| 2786 | /* HPD hotplug */ |
| 2787 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq); |
| 2788 | if (r) |
| 2789 | return r; |
| 2790 | |
| 2791 | adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; |
| 2792 | |
| 2793 | adev_to_drm(adev)->mode_config.async_page_flip = true1; |
| 2794 | |
| 2795 | adev_to_drm(adev)->mode_config.max_width = 16384; |
| 2796 | adev_to_drm(adev)->mode_config.max_height = 16384; |
| 2797 | |
| 2798 | adev_to_drm(adev)->mode_config.preferred_depth = 24; |
| 2799 | adev_to_drm(adev)->mode_config.prefer_shadow = 1; |
| 2800 | |
| 2801 | adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true1; |
| 2802 | |
| 2803 | adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; |
| 2804 | |
| 2805 | r = amdgpu_display_modeset_create_props(adev); |
| 2806 | if (r) |
| 2807 | return r; |
| 2808 | |
| 2809 | adev_to_drm(adev)->mode_config.max_width = 16384; |
| 2810 | adev_to_drm(adev)->mode_config.max_height = 16384; |
| 2811 | |
| 2812 | /* allocate crtcs */ |
| 2813 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 2814 | r = dce_v10_0_crtc_init(adev, i); |
| 2815 | if (r) |
| 2816 | return r; |
| 2817 | } |
| 2818 | |
| 2819 | if (amdgpu_atombios_get_connector_info_from_object_table(adev)) |
| 2820 | amdgpu_display_print_display_setup(adev_to_drm(adev)); |
| 2821 | else |
| 2822 | return -EINVAL22; |
| 2823 | |
| 2824 | /* setup afmt */ |
| 2825 | r = dce_v10_0_afmt_init(adev); |
| 2826 | if (r) |
| 2827 | return r; |
| 2828 | |
| 2829 | r = dce_v10_0_audio_init(adev); |
| 2830 | if (r) |
| 2831 | return r; |
| 2832 | |
| 2833 | drm_kms_helper_poll_init(adev_to_drm(adev)); |
| 2834 | |
| 2835 | adev->mode_info.mode_config_initialized = true1; |
| 2836 | return 0; |
| 2837 | } |
| 2838 | |
| 2839 | static int dce_v10_0_sw_fini(void *handle) |
| 2840 | { |
| 2841 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2842 | |
| 2843 | kfree(adev->mode_info.bios_hardcoded_edid); |
| 2844 | |
| 2845 | drm_kms_helper_poll_fini(adev_to_drm(adev)); |
| 2846 | |
| 2847 | dce_v10_0_audio_fini(adev); |
| 2848 | |
| 2849 | dce_v10_0_afmt_fini(adev); |
| 2850 | |
| 2851 | drm_mode_config_cleanup(adev_to_drm(adev)); |
| 2852 | adev->mode_info.mode_config_initialized = false0; |
| 2853 | |
| 2854 | return 0; |
| 2855 | } |
| 2856 | |
| 2857 | static int dce_v10_0_hw_init(void *handle) |
| 2858 | { |
| 2859 | int i; |
| 2860 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2861 | |
| 2862 | dce_v10_0_init_golden_registers(adev); |
| 2863 | |
| 2864 | /* disable vga render */ |
| 2865 | dce_v10_0_set_vga_render_state(adev, false0); |
| 2866 | /* init dig PHYs, disp eng pll */ |
| 2867 | amdgpu_atombios_encoder_init_dig(adev); |
| 2868 | amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); |
| 2869 | |
| 2870 | /* initialize hpd */ |
| 2871 | dce_v10_0_hpd_init(adev); |
| 2872 | |
| 2873 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 2874 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0); |
| 2875 | } |
| 2876 | |
| 2877 | dce_v10_0_pageflip_interrupt_init(adev); |
| 2878 | |
| 2879 | return 0; |
| 2880 | } |
| 2881 | |
| 2882 | static int dce_v10_0_hw_fini(void *handle) |
| 2883 | { |
| 2884 | int i; |
| 2885 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2886 | |
| 2887 | dce_v10_0_hpd_fini(adev); |
| 2888 | |
| 2889 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 2890 | dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0); |
| 2891 | } |
| 2892 | |
| 2893 | dce_v10_0_pageflip_interrupt_fini(adev); |
| 2894 | |
| 2895 | return 0; |
| 2896 | } |
| 2897 | |
| 2898 | static int dce_v10_0_suspend(void *handle) |
| 2899 | { |
| 2900 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2901 | int r; |
| 2902 | |
| 2903 | r = amdgpu_display_suspend_helper(adev); |
| 2904 | if (r) |
| 2905 | return r; |
| 2906 | |
| 2907 | adev->mode_info.bl_level = |
| 2908 | amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); |
| 2909 | |
| 2910 | return dce_v10_0_hw_fini(handle); |
| 2911 | } |
| 2912 | |
| 2913 | static int dce_v10_0_resume(void *handle) |
| 2914 | { |
| 2915 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2916 | int ret; |
| 2917 | |
| 2918 | amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, |
| 2919 | adev->mode_info.bl_level); |
| 2920 | |
| 2921 | ret = dce_v10_0_hw_init(handle); |
| 2922 | |
| 2923 | /* turn on the BL */ |
| 2924 | if (adev->mode_info.bl_encoder) { |
| 2925 | u8 bl_level = amdgpu_display_backlight_get_level(adev,(adev)->mode_info.funcs->backlight_get_level((adev-> mode_info.bl_encoder)) |
| 2926 | adev->mode_info.bl_encoder)(adev)->mode_info.funcs->backlight_get_level((adev-> mode_info.bl_encoder)); |
| 2927 | amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,(adev)->mode_info.funcs->backlight_set_level((adev-> mode_info.bl_encoder), (bl_level)) |
| 2928 | bl_level)(adev)->mode_info.funcs->backlight_set_level((adev-> mode_info.bl_encoder), (bl_level)); |
| 2929 | } |
| 2930 | if (ret) |
| 2931 | return ret; |
| 2932 | |
| 2933 | return amdgpu_display_resume_helper(adev); |
| 2934 | } |
| 2935 | |
| 2936 | static bool_Bool dce_v10_0_is_idle(void *handle) |
| 2937 | { |
| 2938 | return true1; |
| 2939 | } |
| 2940 | |
| 2941 | static int dce_v10_0_wait_for_idle(void *handle) |
| 2942 | { |
| 2943 | return 0; |
| 2944 | } |
| 2945 | |
| 2946 | static bool_Bool dce_v10_0_check_soft_reset(void *handle) |
| 2947 | { |
| 2948 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2949 | |
| 2950 | return dce_v10_0_is_display_hung(adev); |
| 2951 | } |
| 2952 | |
| 2953 | static int dce_v10_0_soft_reset(void *handle) |
| 2954 | { |
| 2955 | u32 srbm_soft_reset = 0, tmp; |
| 2956 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2957 | |
| 2958 | if (dce_v10_0_is_display_hung(adev)) |
| 2959 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK0x20; |
| 2960 | |
| 2961 | if (srbm_soft_reset) { |
| 2962 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
| 2963 | tmp |= srbm_soft_reset; |
| 2964 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0); |
| 2965 | WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0); |
| 2966 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
| 2967 | |
| 2968 | udelay(50); |
| 2969 | |
| 2970 | tmp &= ~srbm_soft_reset; |
| 2971 | WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0); |
| 2972 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
| 2973 | |
| 2974 | /* Wait a little for things to settle down */ |
| 2975 | udelay(50); |
| 2976 | } |
| 2977 | return 0; |
| 2978 | } |
| 2979 | |
| 2980 | static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, |
| 2981 | int crtc, |
| 2982 | enum amdgpu_interrupt_state state) |
| 2983 | { |
| 2984 | u32 lb_interrupt_mask; |
| 2985 | |
| 2986 | if (crtc >= adev->mode_info.num_crtc) { |
| 2987 | DRM_DEBUG("invalid crtc %d\n", crtc)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid crtc %d\n", crtc ); |
| 2988 | return; |
| 2989 | } |
| 2990 | |
| 2991 | switch (state) { |
| 2992 | case AMDGPU_IRQ_STATE_DISABLE: |
| 2993 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0); |
| 2994 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x1) | (0x1 & ((0) << 0x0 ))) |
| 2995 | VBLANK_INTERRUPT_MASK, 0)(((lb_interrupt_mask) & ~0x1) | (0x1 & ((0) << 0x0 ))); |
| 2996 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask ), 0); |
| 2997 | break; |
| 2998 | case AMDGPU_IRQ_STATE_ENABLE: |
| 2999 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0); |
| 3000 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x1) | (0x1 & ((1) << 0x0 ))) |
| 3001 | VBLANK_INTERRUPT_MASK, 1)(((lb_interrupt_mask) & ~0x1) | (0x1 & ((1) << 0x0 ))); |
| 3002 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask ), 0); |
| 3003 | break; |
| 3004 | default: |
| 3005 | break; |
| 3006 | } |
| 3007 | } |
| 3008 | |
| 3009 | static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, |
| 3010 | int crtc, |
| 3011 | enum amdgpu_interrupt_state state) |
| 3012 | { |
| 3013 | u32 lb_interrupt_mask; |
| 3014 | |
| 3015 | if (crtc >= adev->mode_info.num_crtc) { |
| 3016 | DRM_DEBUG("invalid crtc %d\n", crtc)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid crtc %d\n", crtc ); |
| 3017 | return; |
| 3018 | } |
| 3019 | |
| 3020 | switch (state) { |
| 3021 | case AMDGPU_IRQ_STATE_DISABLE: |
| 3022 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0); |
| 3023 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x10) | (0x10 & ((0) << 0x4))) |
| 3024 | VLINE_INTERRUPT_MASK, 0)(((lb_interrupt_mask) & ~0x10) | (0x10 & ((0) << 0x4))); |
| 3025 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask ), 0); |
| 3026 | break; |
| 3027 | case AMDGPU_IRQ_STATE_ENABLE: |
| 3028 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0); |
| 3029 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x10) | (0x10 & ((1) << 0x4))) |
| 3030 | VLINE_INTERRUPT_MASK, 1)(((lb_interrupt_mask) & ~0x10) | (0x10 & ((1) << 0x4))); |
| 3031 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask ), 0); |
| 3032 | break; |
| 3033 | default: |
| 3034 | break; |
| 3035 | } |
| 3036 | } |
| 3037 | |
| 3038 | static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, |
| 3039 | struct amdgpu_irq_src *source, |
| 3040 | unsigned hpd, |
| 3041 | enum amdgpu_interrupt_state state) |
| 3042 | { |
| 3043 | u32 tmp; |
| 3044 | |
| 3045 | if (hpd >= adev->mode_info.num_hpd) { |
| 3046 | DRM_DEBUG("invalid hdp %d\n", hpd)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid hdp %d\n", hpd); |
| 3047 | return 0; |
| 3048 | } |
| 3049 | |
| 3050 | switch (state) { |
| 3051 | case AMDGPU_IRQ_STATE_DISABLE: |
| 3052 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0); |
| 3053 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0)(((tmp) & ~0x10000) | (0x10000 & ((0) << 0x10)) ); |
| 3054 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0 ); |
| 3055 | break; |
| 3056 | case AMDGPU_IRQ_STATE_ENABLE: |
| 3057 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0); |
| 3058 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1)(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10)) ); |
| 3059 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0 ); |
| 3060 | break; |
| 3061 | default: |
| 3062 | break; |
| 3063 | } |
| 3064 | |
| 3065 | return 0; |
| 3066 | } |
| 3067 | |
| 3068 | static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, |
| 3069 | struct amdgpu_irq_src *source, |
| 3070 | unsigned type, |
| 3071 | enum amdgpu_interrupt_state state) |
| 3072 | { |
| 3073 | switch (type) { |
| 3074 | case AMDGPU_CRTC_IRQ_VBLANK1: |
| 3075 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); |
| 3076 | break; |
| 3077 | case AMDGPU_CRTC_IRQ_VBLANK2: |
| 3078 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); |
| 3079 | break; |
| 3080 | case AMDGPU_CRTC_IRQ_VBLANK3: |
| 3081 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); |
| 3082 | break; |
| 3083 | case AMDGPU_CRTC_IRQ_VBLANK4: |
| 3084 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); |
| 3085 | break; |
| 3086 | case AMDGPU_CRTC_IRQ_VBLANK5: |
| 3087 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); |
| 3088 | break; |
| 3089 | case AMDGPU_CRTC_IRQ_VBLANK6: |
| 3090 | dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); |
| 3091 | break; |
| 3092 | case AMDGPU_CRTC_IRQ_VLINE1: |
| 3093 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); |
| 3094 | break; |
| 3095 | case AMDGPU_CRTC_IRQ_VLINE2: |
| 3096 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); |
| 3097 | break; |
| 3098 | case AMDGPU_CRTC_IRQ_VLINE3: |
| 3099 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); |
| 3100 | break; |
| 3101 | case AMDGPU_CRTC_IRQ_VLINE4: |
| 3102 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); |
| 3103 | break; |
| 3104 | case AMDGPU_CRTC_IRQ_VLINE5: |
| 3105 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); |
| 3106 | break; |
| 3107 | case AMDGPU_CRTC_IRQ_VLINE6: |
| 3108 | dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); |
| 3109 | break; |
| 3110 | default: |
| 3111 | break; |
| 3112 | } |
| 3113 | return 0; |
| 3114 | } |
| 3115 | |
| 3116 | static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, |
| 3117 | struct amdgpu_irq_src *src, |
| 3118 | unsigned type, |
| 3119 | enum amdgpu_interrupt_state state) |
| 3120 | { |
| 3121 | u32 reg; |
| 3122 | |
| 3123 | if (type >= adev->mode_info.num_crtc) { |
| 3124 | DRM_ERROR("invalid pageflip crtc %d\n", type)__drm_err("invalid pageflip crtc %d\n", type); |
| 3125 | return -EINVAL22; |
| 3126 | } |
| 3127 | |
| 3128 | reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type])amdgpu_device_rreg(adev, (0x1a17 + crtc_offsets[type]), 0); |
| 3129 | if (state == AMDGPU_IRQ_STATE_DISABLE) |
| 3130 | WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg & ~0x1), 0) |
| 3131 | reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK)amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg & ~0x1), 0); |
| 3132 | else |
| 3133 | WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg | 0x1), 0) |
| 3134 | reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK)amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg | 0x1), 0); |
| 3135 | |
| 3136 | return 0; |
| 3137 | } |
| 3138 | |
| 3139 | static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, |
| 3140 | struct amdgpu_irq_src *source, |
| 3141 | struct amdgpu_iv_entry *entry) |
| 3142 | { |
| 3143 | unsigned long flags; |
| 3144 | unsigned crtc_id; |
| 3145 | struct amdgpu_crtc *amdgpu_crtc; |
| 3146 | struct amdgpu_flip_work *works; |
| 3147 | |
| 3148 | crtc_id = (entry->src_id - 8) >> 1; |
| 3149 | amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; |
| 3150 | |
| 3151 | if (crtc_id >= adev->mode_info.num_crtc) { |
| 3152 | DRM_ERROR("invalid pageflip crtc %d\n", crtc_id)__drm_err("invalid pageflip crtc %d\n", crtc_id); |
| 3153 | return -EINVAL22; |
| 3154 | } |
| 3155 | |
| 3156 | if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id])amdgpu_device_rreg(adev, (0x1a16 + crtc_offsets[crtc_id]), 0) & |
| 3157 | GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK0x1) |
| 3158 | WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],amdgpu_device_wreg(adev, (0x1a16 + crtc_offsets[crtc_id]), (0x100 ), 0) |
| 3159 | GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK)amdgpu_device_wreg(adev, (0x1a16 + crtc_offsets[crtc_id]), (0x100 ), 0); |
| 3160 | |
| 3161 | /* IRQ could occur when in initial stage */ |
| 3162 | if (amdgpu_crtc == NULL((void *)0)) |
| 3163 | return 0; |
| 3164 | |
| 3165 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock ); } while (0); |
| 3166 | works = amdgpu_crtc->pflip_works; |
| 3167 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { |
| 3168 | DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != " "AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED) |
| 3169 | "AMDGPU_FLIP_SUBMITTED(%d)\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != " "AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED) |
| 3170 | amdgpu_crtc->pflip_status,___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != " "AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED) |
| 3171 | AMDGPU_FLIP_SUBMITTED)___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != " "AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED); |
| 3172 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock ); } while (0); |
| 3173 | return 0; |
| 3174 | } |
| 3175 | |
| 3176 | /* page flip completed. clean up */ |
| 3177 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
| 3178 | amdgpu_crtc->pflip_works = NULL((void *)0); |
| 3179 | |
| 3180 | /* wakeup usersapce */ |
| 3181 | if (works->event) |
| 3182 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); |
| 3183 | |
| 3184 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock ); } while (0); |
| 3185 | |
| 3186 | drm_crtc_vblank_put(&amdgpu_crtc->base); |
| 3187 | schedule_work(&works->unpin_work); |
| 3188 | |
| 3189 | return 0; |
| 3190 | } |
| 3191 | |
| 3192 | static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, |
| 3193 | int hpd) |
| 3194 | { |
| 3195 | u32 tmp; |
| 3196 | |
| 3197 | if (hpd >= adev->mode_info.num_hpd) { |
| 3198 | DRM_DEBUG("invalid hdp %d\n", hpd)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid hdp %d\n", hpd); |
| 3199 | return; |
| 3200 | } |
| 3201 | |
| 3202 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0); |
| 3203 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
| 3204 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0 ); |
| 3205 | } |
| 3206 | |
| 3207 | static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, |
| 3208 | int crtc) |
| 3209 | { |
| 3210 | u32 tmp; |
| 3211 | |
| 3212 | if (crtc >= adev->mode_info.num_crtc) { |
| 3213 | DRM_DEBUG("invalid crtc %d\n", crtc)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid crtc %d\n", crtc ); |
| 3214 | return; |
| 3215 | } |
| 3216 | |
| 3217 | tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1acb + crtc_offsets[crtc]), 0); |
| 3218 | tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); |
| 3219 | WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp)amdgpu_device_wreg(adev, (0x1acb + crtc_offsets[crtc]), (tmp) , 0); |
| 3220 | } |
| 3221 | |
| 3222 | static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, |
| 3223 | int crtc) |
| 3224 | { |
| 3225 | u32 tmp; |
| 3226 | |
| 3227 | if (crtc >= adev->mode_info.num_crtc) { |
| 3228 | DRM_DEBUG("invalid crtc %d\n", crtc)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid crtc %d\n", crtc ); |
| 3229 | return; |
| 3230 | } |
| 3231 | |
| 3232 | tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac9 + crtc_offsets[crtc]), 0); |
| 3233 | tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); |
| 3234 | WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp)amdgpu_device_wreg(adev, (0x1ac9 + crtc_offsets[crtc]), (tmp) , 0); |
| 3235 | } |
| 3236 | |
| 3237 | static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, |
| 3238 | struct amdgpu_irq_src *source, |
| 3239 | struct amdgpu_iv_entry *entry) |
| 3240 | { |
| 3241 | unsigned crtc = entry->src_id - 1; |
| 3242 | uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg)amdgpu_device_rreg(adev, (interrupt_status_offsets[crtc].reg) , 0); |
| 3243 | unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc); |
| 3244 | |
| 3245 | switch (entry->src_data[0]) { |
| 3246 | case 0: /* vblank */ |
| 3247 | if (disp_int & interrupt_status_offsets[crtc].vblank) |
| 3248 | dce_v10_0_crtc_vblank_int_ack(adev, crtc); |
| 3249 | else |
| 3250 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n")___drm_dbg(((void *)0), DRM_UT_CORE, "IH: IH event w/o asserted irq bit?\n" ); |
| 3251 | |
| 3252 | if (amdgpu_irq_enabled(adev, source, irq_type)) { |
| 3253 | drm_handle_vblank(adev_to_drm(adev), crtc); |
| 3254 | } |
| 3255 | DRM_DEBUG("IH: D%d vblank\n", crtc + 1)___drm_dbg(((void *)0), DRM_UT_CORE, "IH: D%d vblank\n", crtc + 1); |
| 3256 | |
| 3257 | break; |
| 3258 | case 1: /* vline */ |
| 3259 | if (disp_int & interrupt_status_offsets[crtc].vline) |
| 3260 | dce_v10_0_crtc_vline_int_ack(adev, crtc); |
| 3261 | else |
| 3262 | DRM_DEBUG("IH: IH event w/o asserted irq bit?\n")___drm_dbg(((void *)0), DRM_UT_CORE, "IH: IH event w/o asserted irq bit?\n" ); |
| 3263 | |
| 3264 | DRM_DEBUG("IH: D%d vline\n", crtc + 1)___drm_dbg(((void *)0), DRM_UT_CORE, "IH: D%d vline\n", crtc + 1); |
| 3265 | |
| 3266 | break; |
| 3267 | default: |
| 3268 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0])___drm_dbg(((void *)0), DRM_UT_CORE, "Unhandled interrupt: %d %d\n" , entry->src_id, entry->src_data[0]); |
| 3269 | break; |
| 3270 | } |
| 3271 | |
| 3272 | return 0; |
| 3273 | } |
| 3274 | |
| 3275 | static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, |
| 3276 | struct amdgpu_irq_src *source, |
| 3277 | struct amdgpu_iv_entry *entry) |
| 3278 | { |
| 3279 | uint32_t disp_int, mask; |
| 3280 | unsigned hpd; |
| 3281 | |
| 3282 | if (entry->src_data[0] >= adev->mode_info.num_hpd) { |
| 3283 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0])___drm_dbg(((void *)0), DRM_UT_CORE, "Unhandled interrupt: %d %d\n" , entry->src_id, entry->src_data[0]); |
| 3284 | return 0; |
| 3285 | } |
| 3286 | |
| 3287 | hpd = entry->src_data[0]; |
| 3288 | disp_int = RREG32(interrupt_status_offsets[hpd].reg)amdgpu_device_rreg(adev, (interrupt_status_offsets[hpd].reg), 0); |
| 3289 | mask = interrupt_status_offsets[hpd].hpd; |
| 3290 | |
| 3291 | if (disp_int & mask) { |
| 3292 | dce_v10_0_hpd_int_ack(adev, hpd); |
| 3293 | schedule_work(&adev->hotplug_work); |
| 3294 | DRM_DEBUG("IH: HPD%d\n", hpd + 1)___drm_dbg(((void *)0), DRM_UT_CORE, "IH: HPD%d\n", hpd + 1); |
| 3295 | } |
| 3296 | |
| 3297 | return 0; |
| 3298 | } |
| 3299 | |
| 3300 | static int dce_v10_0_set_clockgating_state(void *handle, |
| 3301 | enum amd_clockgating_state state) |
| 3302 | { |
| 3303 | return 0; |
| 3304 | } |
| 3305 | |
| 3306 | static int dce_v10_0_set_powergating_state(void *handle, |
| 3307 | enum amd_powergating_state state) |
| 3308 | { |
| 3309 | return 0; |
| 3310 | } |
| 3311 | |
| 3312 | static const struct amd_ip_funcs dce_v10_0_ip_funcs = { |
| 3313 | .name = "dce_v10_0", |
| 3314 | .early_init = dce_v10_0_early_init, |
| 3315 | .late_init = NULL((void *)0), |
| 3316 | .sw_init = dce_v10_0_sw_init, |
| 3317 | .sw_fini = dce_v10_0_sw_fini, |
| 3318 | .hw_init = dce_v10_0_hw_init, |
| 3319 | .hw_fini = dce_v10_0_hw_fini, |
| 3320 | .suspend = dce_v10_0_suspend, |
| 3321 | .resume = dce_v10_0_resume, |
| 3322 | .is_idle = dce_v10_0_is_idle, |
| 3323 | .wait_for_idle = dce_v10_0_wait_for_idle, |
| 3324 | .check_soft_reset = dce_v10_0_check_soft_reset, |
| 3325 | .soft_reset = dce_v10_0_soft_reset, |
| 3326 | .set_clockgating_state = dce_v10_0_set_clockgating_state, |
| 3327 | .set_powergating_state = dce_v10_0_set_powergating_state, |
| 3328 | }; |
| 3329 | |
| 3330 | static void |
| 3331 | dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, |
| 3332 | struct drm_display_mode *mode, |
| 3333 | struct drm_display_mode *adjusted_mode) |
| 3334 | { |
| 3335 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 3336 | |
| 3337 | amdgpu_encoder->pixel_clock = adjusted_mode->clock; |
| 3338 | |
| 3339 | /* need to call this here rather than in prepare() since we need some crtc info */ |
| 3340 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF3); |
| 3341 | |
| 3342 | /* set scaler clears this on some chips */ |
| 3343 | dce_v10_0_set_interleave(encoder->crtc, mode); |
| 3344 | |
| 3345 | if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI3) { |
| 3346 | dce_v10_0_afmt_enable(encoder, true1); |
| 3347 | dce_v10_0_afmt_setmode(encoder, adjusted_mode); |
| 3348 | } |
| 3349 | } |
| 3350 | |
| 3351 | static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) |
| 3352 | { |
| 3353 | struct amdgpu_device *adev = drm_to_adev(encoder->dev); |
| 3354 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 3355 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); |
| 3356 | |
| 3357 | if ((amdgpu_encoder->active_device & |
| 3358 | (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | ( 0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L << 0x0000000B ) | (0x1L << 0x00000006 )) | ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) || |
| 3359 | (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != |
| 3360 | ENCODER_OBJECT_ID_NONE0x00)) { |
| 3361 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 3362 | if (dig) { |
| 3363 | dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); |
| 3364 | if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | ( 0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L << 0x0000000B ) | (0x1L << 0x00000006 ))) |
| 3365 | dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; |
| 3366 | } |
| 3367 | } |
| 3368 | |
| 3369 | amdgpu_atombios_scratch_regs_lock(adev, true1); |
| 3370 | |
| 3371 | if (connector) { |
| 3372 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) * __mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_connector, base) );}); |
| 3373 | |
| 3374 | /* select the clock/data port if it uses a router */ |
| 3375 | if (amdgpu_connector->router.cd_valid) |
| 3376 | amdgpu_i2c_router_select_cd_port(amdgpu_connector); |
| 3377 | |
| 3378 | /* turn eDP panel on for mode set */ |
| 3379 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14) |
| 3380 | amdgpu_atombios_encoder_set_edp_panel_power(connector, |
| 3381 | ATOM_TRANSMITTER_ACTION_POWER_ON12); |
| 3382 | } |
| 3383 | |
| 3384 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
| 3385 | amdgpu_atombios_encoder_set_crtc_source(encoder); |
| 3386 | /* set up the FMT blocks */ |
| 3387 | dce_v10_0_program_fmt(encoder); |
| 3388 | } |
| 3389 | |
| 3390 | static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) |
| 3391 | { |
| 3392 | struct drm_device *dev = encoder->dev; |
| 3393 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 3394 | |
| 3395 | /* need to call this here as we need the crtc set up */ |
| 3396 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON0); |
| 3397 | amdgpu_atombios_scratch_regs_lock(adev, false0); |
| 3398 | } |
| 3399 | |
| 3400 | static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) |
| 3401 | { |
| 3402 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 3403 | struct amdgpu_encoder_atom_dig *dig; |
| 3404 | |
| 3405 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF3); |
| 3406 | |
| 3407 | if (amdgpu_atombios_encoder_is_digital(encoder)) { |
| 3408 | if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI3) |
| 3409 | dce_v10_0_afmt_enable(encoder, false0); |
| 3410 | dig = amdgpu_encoder->enc_priv; |
| 3411 | dig->dig_encoder = -1; |
| 3412 | } |
| 3413 | amdgpu_encoder->active_device = 0; |
| 3414 | } |
| 3415 | |
| 3416 | /* these are handled by the primary encoders */ |
| 3417 | static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) |
| 3418 | { |
| 3419 | |
| 3420 | } |
| 3421 | |
| 3422 | static void dce_v10_0_ext_commit(struct drm_encoder *encoder) |
| 3423 | { |
| 3424 | |
| 3425 | } |
| 3426 | |
| 3427 | static void |
| 3428 | dce_v10_0_ext_mode_set(struct drm_encoder *encoder, |
| 3429 | struct drm_display_mode *mode, |
| 3430 | struct drm_display_mode *adjusted_mode) |
| 3431 | { |
| 3432 | |
| 3433 | } |
| 3434 | |
| 3435 | static void dce_v10_0_ext_disable(struct drm_encoder *encoder) |
| 3436 | { |
| 3437 | |
| 3438 | } |
| 3439 | |
| 3440 | static void |
| 3441 | dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) |
| 3442 | { |
| 3443 | |
| 3444 | } |
| 3445 | |
| 3446 | static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { |
| 3447 | .dpms = dce_v10_0_ext_dpms, |
| 3448 | .prepare = dce_v10_0_ext_prepare, |
| 3449 | .mode_set = dce_v10_0_ext_mode_set, |
| 3450 | .commit = dce_v10_0_ext_commit, |
| 3451 | .disable = dce_v10_0_ext_disable, |
| 3452 | /* no detect for TMDS/LVDS yet */ |
| 3453 | }; |
| 3454 | |
| 3455 | static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { |
| 3456 | .dpms = amdgpu_atombios_encoder_dpms, |
| 3457 | .mode_fixup = amdgpu_atombios_encoder_mode_fixup, |
| 3458 | .prepare = dce_v10_0_encoder_prepare, |
| 3459 | .mode_set = dce_v10_0_encoder_mode_set, |
| 3460 | .commit = dce_v10_0_encoder_commit, |
| 3461 | .disable = dce_v10_0_encoder_disable, |
| 3462 | .detect = amdgpu_atombios_encoder_dig_detect, |
| 3463 | }; |
| 3464 | |
| 3465 | static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { |
| 3466 | .dpms = amdgpu_atombios_encoder_dpms, |
| 3467 | .mode_fixup = amdgpu_atombios_encoder_mode_fixup, |
| 3468 | .prepare = dce_v10_0_encoder_prepare, |
| 3469 | .mode_set = dce_v10_0_encoder_mode_set, |
| 3470 | .commit = dce_v10_0_encoder_commit, |
| 3471 | .detect = amdgpu_atombios_encoder_dac_detect, |
| 3472 | }; |
| 3473 | |
| 3474 | static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) |
| 3475 | { |
| 3476 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 3477 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) |
| 3478 | amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); |
| 3479 | kfree(amdgpu_encoder->enc_priv); |
| 3480 | drm_encoder_cleanup(encoder); |
| 3481 | kfree(amdgpu_encoder); |
| 3482 | } |
| 3483 | |
| 3484 | static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { |
| 3485 | .destroy = dce_v10_0_encoder_destroy, |
| 3486 | }; |
| 3487 | |
| 3488 | static void dce_v10_0_encoder_add(struct amdgpu_device *adev, |
| 3489 | uint32_t encoder_enum, |
| 3490 | uint32_t supported_device, |
| 3491 | u16 caps) |
| 3492 | { |
| 3493 | struct drm_device *dev = adev_to_drm(adev); |
| 3494 | struct drm_encoder *encoder; |
| 3495 | struct amdgpu_encoder *amdgpu_encoder; |
| 3496 | |
| 3497 | /* see if we already added it */ |
| 3498 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> head ) *__mptr = ((&dev->mode_config.encoder_list)-> next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), head) );}); &encoder->head != (& dev->mode_config.encoder_list); encoder = ({ const __typeof ( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder-> head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), head) );})) { |
| 3499 | amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_encoder, base) );}); |
| 3500 | if (amdgpu_encoder->encoder_enum == encoder_enum) { |
| 3501 | amdgpu_encoder->devices |= supported_device; |
| 3502 | return; |
| 3503 | } |
| 3504 | |
| 3505 | } |
| 3506 | |
| 3507 | /* add a new one */ |
| 3508 | amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL(0x0001 | 0x0004)); |
| 3509 | if (!amdgpu_encoder) |
| 3510 | return; |
| 3511 | |
| 3512 | encoder = &amdgpu_encoder->base; |
| 3513 | switch (adev->mode_info.num_crtc) { |
| 3514 | case 1: |
| 3515 | encoder->possible_crtcs = 0x1; |
| 3516 | break; |
| 3517 | case 2: |
| 3518 | default: |
| 3519 | encoder->possible_crtcs = 0x3; |
| 3520 | break; |
| 3521 | case 4: |
| 3522 | encoder->possible_crtcs = 0xf; |
| 3523 | break; |
| 3524 | case 6: |
| 3525 | encoder->possible_crtcs = 0x3f; |
| 3526 | break; |
| 3527 | } |
| 3528 | |
| 3529 | amdgpu_encoder->enc_priv = NULL((void *)0); |
| 3530 | |
| 3531 | amdgpu_encoder->encoder_enum = encoder_enum; |
| 3532 | amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK0x00FF) >> OBJECT_ID_SHIFT0x00; |
| 3533 | amdgpu_encoder->devices = supported_device; |
| 3534 | amdgpu_encoder->rmx_type = RMX_OFF; |
| 3535 | amdgpu_encoder->underscan_type = UNDERSCAN_OFF; |
| 3536 | amdgpu_encoder->is_ext_encoder = false0; |
| 3537 | amdgpu_encoder->caps = caps; |
| 3538 | |
| 3539 | switch (amdgpu_encoder->encoder_id) { |
| 3540 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15: |
| 3541 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16: |
| 3542 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, |
| 3543 | DRM_MODE_ENCODER_DAC1, NULL((void *)0)); |
| 3544 | drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); |
| 3545 | break; |
| 3546 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14: |
| 3547 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E: |
| 3548 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20: |
| 3549 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21: |
| 3550 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25: |
| 3551 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) { |
| 3552 | amdgpu_encoder->rmx_type = RMX_FULL; |
| 3553 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, |
| 3554 | DRM_MODE_ENCODER_LVDS3, NULL((void *)0)); |
| 3555 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); |
| 3556 | } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 )))) { |
| 3557 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, |
| 3558 | DRM_MODE_ENCODER_DAC1, NULL((void *)0)); |
| 3559 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); |
| 3560 | } else { |
| 3561 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, |
| 3562 | DRM_MODE_ENCODER_TMDS2, NULL((void *)0)); |
| 3563 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); |
| 3564 | } |
| 3565 | drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); |
| 3566 | break; |
| 3567 | case ENCODER_OBJECT_ID_SI170B0x08: |
| 3568 | case ENCODER_OBJECT_ID_CH73030x09: |
| 3569 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA0x0C: |
| 3570 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB0x0D: |
| 3571 | case ENCODER_OBJECT_ID_TITFP5130x0E: |
| 3572 | case ENCODER_OBJECT_ID_VT16230x10: |
| 3573 | case ENCODER_OBJECT_ID_HDMI_SI19300x11: |
| 3574 | case ENCODER_OBJECT_ID_TRAVIS0x23: |
| 3575 | case ENCODER_OBJECT_ID_NUTMEG0x22: |
| 3576 | /* these are handled by the primary encoders */ |
| 3577 | amdgpu_encoder->is_ext_encoder = true1; |
| 3578 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) |
| 3579 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, |
| 3580 | DRM_MODE_ENCODER_LVDS3, NULL((void *)0)); |
| 3581 | else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 )))) |
| 3582 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, |
| 3583 | DRM_MODE_ENCODER_DAC1, NULL((void *)0)); |
| 3584 | else |
| 3585 | drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, |
| 3586 | DRM_MODE_ENCODER_TMDS2, NULL((void *)0)); |
| 3587 | drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); |
| 3588 | break; |
| 3589 | } |
| 3590 | } |
| 3591 | |
| 3592 | static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { |
| 3593 | .bandwidth_update = &dce_v10_0_bandwidth_update, |
| 3594 | .vblank_get_counter = &dce_v10_0_vblank_get_counter, |
| 3595 | .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, |
| 3596 | .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, |
| 3597 | .hpd_sense = &dce_v10_0_hpd_sense, |
| 3598 | .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, |
| 3599 | .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, |
| 3600 | .page_flip = &dce_v10_0_page_flip, |
| 3601 | .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, |
| 3602 | .add_encoder = &dce_v10_0_encoder_add, |
| 3603 | .add_connector = &amdgpu_connector_add, |
| 3604 | }; |
| 3605 | |
| 3606 | static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) |
| 3607 | { |
| 3608 | adev->mode_info.funcs = &dce_v10_0_display_funcs; |
| 3609 | } |
| 3610 | |
| 3611 | static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { |
| 3612 | .set = dce_v10_0_set_crtc_irq_state, |
| 3613 | .process = dce_v10_0_crtc_irq, |
| 3614 | }; |
| 3615 | |
| 3616 | static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { |
| 3617 | .set = dce_v10_0_set_pageflip_irq_state, |
| 3618 | .process = dce_v10_0_pageflip_irq, |
| 3619 | }; |
| 3620 | |
| 3621 | static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { |
| 3622 | .set = dce_v10_0_set_hpd_irq_state, |
| 3623 | .process = dce_v10_0_hpd_irq, |
| 3624 | }; |
| 3625 | |
| 3626 | static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) |
| 3627 | { |
| 3628 | if (adev->mode_info.num_crtc > 0) |
| 3629 | adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; |
| 3630 | else |
| 3631 | adev->crtc_irq.num_types = 0; |
| 3632 | adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; |
| 3633 | |
| 3634 | adev->pageflip_irq.num_types = adev->mode_info.num_crtc; |
| 3635 | adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; |
| 3636 | |
| 3637 | adev->hpd_irq.num_types = adev->mode_info.num_hpd; |
| 3638 | adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; |
| 3639 | } |
| 3640 | |
| 3641 | const struct amdgpu_ip_block_version dce_v10_0_ip_block = |
| 3642 | { |
| 3643 | .type = AMD_IP_BLOCK_TYPE_DCE, |
| 3644 | .major = 10, |
| 3645 | .minor = 0, |
| 3646 | .rev = 0, |
| 3647 | .funcs = &dce_v10_0_ip_funcs, |
| 3648 | }; |
| 3649 | |
| 3650 | const struct amdgpu_ip_block_version dce_v10_1_ip_block = |
| 3651 | { |
| 3652 | .type = AMD_IP_BLOCK_TYPE_DCE, |
| 3653 | .major = 10, |
| 3654 | .minor = 1, |
| 3655 | .rev = 0, |
| 3656 | .funcs = &dce_v10_0_ip_funcs, |
| 3657 | }; |