| File: | dev/pci/drm/i915/display/intel_fb.c |
| Warning: | line 1580, column 3 Value stored to 'cpp' is never read |
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| 1 | // SPDX-License-Identifier: MIT |
| 2 | /* |
| 3 | * Copyright © 2021 Intel Corporation |
| 4 | */ |
| 5 | |
| 6 | #include <drm/drm_blend.h> |
| 7 | #include <drm/drm_framebuffer.h> |
| 8 | #include <drm/drm_modeset_helper.h> |
| 9 | |
| 10 | #include "i915_drv.h" |
| 11 | #include "intel_display.h" |
| 12 | #include "intel_display_types.h" |
| 13 | #include "intel_dpt.h" |
| 14 | #include "intel_fb.h" |
| 15 | |
| 16 | #define check_array_bounds(i915, a, i)({ int __ret = !!(((i) >= (sizeof((a)) / sizeof((a)[0])))) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& (i915)->drm))->dev), "", "drm_WARN_ON(" "(i) >= (sizeof((a)) / sizeof((a)[0]))" ")"); __builtin_expect(!!(__ret), 0); }) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))({ int __ret = !!(((i) >= (sizeof((a)) / sizeof((a)[0])))) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& (i915)->drm))->dev), "", "drm_WARN_ON(" "(i) >= (sizeof((a)) / sizeof((a)[0]))" ")"); __builtin_expect(!!(__ret), 0); }) |
| 17 | |
| 18 | /* |
| 19 | * From the Sky Lake PRM: |
| 20 | * "The Color Control Surface (CCS) contains the compression status of |
| 21 | * the cache-line pairs. The compression state of the cache-line pair |
| 22 | * is specified by 2 bits in the CCS. Each CCS cache-line represents |
| 23 | * an area on the main surface of 16 x16 sets of 128 byte Y-tiled |
| 24 | * cache-line-pairs. CCS is always Y tiled." |
| 25 | * |
| 26 | * Since cache line pairs refers to horizontally adjacent cache lines, |
| 27 | * each cache line in the CCS corresponds to an area of 32x16 cache |
| 28 | * lines on the main surface. Since each pixel is 4 bytes, this gives |
| 29 | * us a ratio of one byte in the CCS for each 8x16 pixels in the |
| 30 | * main surface. |
| 31 | */ |
| 32 | static const struct drm_format_info skl_ccs_formats[] = { |
| 33 | { .format = DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 34 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, |
| 35 | { .format = DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 36 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, |
| 37 | { .format = DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 38 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true1, }, |
| 39 | { .format = DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 40 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true1, }, |
| 41 | }; |
| 42 | |
| 43 | /* |
| 44 | * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the |
| 45 | * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles |
| 46 | * in the main surface. With 4 byte pixels and each Y-tile having dimensions of |
| 47 | * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in |
| 48 | * the main surface. |
| 49 | */ |
| 50 | static const struct drm_format_info gen12_ccs_formats[] = { |
| 51 | { .format = DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 52 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 53 | .hsub = 1, .vsub = 1, }, |
| 54 | { .format = DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 55 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 56 | .hsub = 1, .vsub = 1, }, |
| 57 | { .format = DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 58 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 59 | .hsub = 1, .vsub = 1, .has_alpha = true1 }, |
| 60 | { .format = DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 61 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 62 | .hsub = 1, .vsub = 1, .has_alpha = true1 }, |
| 63 | { .format = DRM_FORMAT_YUYV((__u32)('Y') | ((__u32)('U') << 8) | ((__u32)('Y') << 16) | ((__u32)('V') << 24)), .num_planes = 2, |
| 64 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 65 | .hsub = 2, .vsub = 1, .is_yuv = true1 }, |
| 66 | { .format = DRM_FORMAT_YVYU((__u32)('Y') | ((__u32)('V') << 8) | ((__u32)('Y') << 16) | ((__u32)('U') << 24)), .num_planes = 2, |
| 67 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 68 | .hsub = 2, .vsub = 1, .is_yuv = true1 }, |
| 69 | { .format = DRM_FORMAT_UYVY((__u32)('U') | ((__u32)('Y') << 8) | ((__u32)('V') << 16) | ((__u32)('Y') << 24)), .num_planes = 2, |
| 70 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 71 | .hsub = 2, .vsub = 1, .is_yuv = true1 }, |
| 72 | { .format = DRM_FORMAT_VYUY((__u32)('V') | ((__u32)('Y') << 8) | ((__u32)('U') << 16) | ((__u32)('Y') << 24)), .num_planes = 2, |
| 73 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 74 | .hsub = 2, .vsub = 1, .is_yuv = true1 }, |
| 75 | { .format = DRM_FORMAT_XYUV8888((__u32)('X') | ((__u32)('Y') << 8) | ((__u32)('U') << 16) | ((__u32)('V') << 24)), .num_planes = 2, |
| 76 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 77 | .hsub = 1, .vsub = 1, .is_yuv = true1 }, |
| 78 | { .format = DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)), .num_planes = 4, |
| 79 | .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, |
| 80 | .hsub = 2, .vsub = 2, .is_yuv = true1 }, |
| 81 | { .format = DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)), .num_planes = 4, |
| 82 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, |
| 83 | .hsub = 2, .vsub = 2, .is_yuv = true1 }, |
| 84 | { .format = DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)), .num_planes = 4, |
| 85 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, |
| 86 | .hsub = 2, .vsub = 2, .is_yuv = true1 }, |
| 87 | { .format = DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), .num_planes = 4, |
| 88 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, |
| 89 | .hsub = 2, .vsub = 2, .is_yuv = true1 }, |
| 90 | }; |
| 91 | |
| 92 | /* |
| 93 | * Same as gen12_ccs_formats[] above, but with additional surface used |
| 94 | * to pass Clear Color information in plane 2 with 64 bits of data. |
| 95 | */ |
| 96 | static const struct drm_format_info gen12_ccs_cc_formats[] = { |
| 97 | { .format = DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 3, |
| 98 | .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, |
| 99 | .hsub = 1, .vsub = 1, }, |
| 100 | { .format = DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 3, |
| 101 | .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, |
| 102 | .hsub = 1, .vsub = 1, }, |
| 103 | { .format = DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 3, |
| 104 | .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, |
| 105 | .hsub = 1, .vsub = 1, .has_alpha = true1 }, |
| 106 | { .format = DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 3, |
| 107 | .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, |
| 108 | .hsub = 1, .vsub = 1, .has_alpha = true1 }, |
| 109 | }; |
| 110 | |
| 111 | static const struct drm_format_info gen12_flat_ccs_cc_formats[] = { |
| 112 | { .format = DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 113 | .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 114 | .hsub = 1, .vsub = 1, }, |
| 115 | { .format = DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 116 | .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 117 | .hsub = 1, .vsub = 1, }, |
| 118 | { .format = DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 119 | .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 120 | .hsub = 1, .vsub = 1, .has_alpha = true1 }, |
| 121 | { .format = DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 122 | .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 123 | .hsub = 1, .vsub = 1, .has_alpha = true1 }, |
| 124 | }; |
| 125 | |
| 126 | struct intel_modifier_desc { |
| 127 | u64 modifier; |
| 128 | struct { |
| 129 | u8 from; |
| 130 | u8 until; |
| 131 | } display_ver; |
| 132 | #define DISPLAY_VER_ALL{ 0, -1 } { 0, -1 } |
| 133 | |
| 134 | const struct drm_format_info *formats; |
| 135 | int format_count; |
| 136 | #define FORMAT_OVERRIDE(format_list).formats = format_list, .format_count = (sizeof((format_list) ) / sizeof((format_list)[0])) \ |
| 137 | .formats = format_list, \ |
| 138 | .format_count = ARRAY_SIZE(format_list)(sizeof((format_list)) / sizeof((format_list)[0])) |
| 139 | |
| 140 | u8 plane_caps; |
| 141 | |
| 142 | struct { |
| 143 | u8 cc_planes:3; |
| 144 | u8 packed_aux_planes:4; |
| 145 | u8 planar_aux_planes:4; |
| 146 | } ccs; |
| 147 | }; |
| 148 | |
| 149 | #define INTEL_PLANE_CAP_CCS_MASK((1UL << (0)) | (1UL << (1)) | (1UL << (2)) ) (INTEL_PLANE_CAP_CCS_RC(1UL << (0)) | \ |
| 150 | INTEL_PLANE_CAP_CCS_RC_CC(1UL << (1)) | \ |
| 151 | INTEL_PLANE_CAP_CCS_MC(1UL << (2))) |
| 152 | #define INTEL_PLANE_CAP_TILING_MASK((1UL << (3)) | (1UL << (4)) | (1UL << (5)) | (1UL << (6))) (INTEL_PLANE_CAP_TILING_X(1UL << (3)) | \ |
| 153 | INTEL_PLANE_CAP_TILING_Y(1UL << (4)) | \ |
| 154 | INTEL_PLANE_CAP_TILING_Yf(1UL << (5)) | \ |
| 155 | INTEL_PLANE_CAP_TILING_4(1UL << (6))) |
| 156 | #define INTEL_PLANE_CAP_TILING_NONE0 0 |
| 157 | |
| 158 | static const struct intel_modifier_desc intel_modifiers[] = { |
| 159 | { |
| 160 | .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS((((__u64)0x01) << 56) | ((11) & 0x00ffffffffffffffULL )), |
| 161 | .display_ver = { 13, 13 }, |
| 162 | .plane_caps = INTEL_PLANE_CAP_TILING_4(1UL << (6)) | INTEL_PLANE_CAP_CCS_MC(1UL << (2)), |
| 163 | }, { |
| 164 | .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC((((__u64)0x01) << 56) | ((12) & 0x00ffffffffffffffULL )), |
| 165 | .display_ver = { 13, 13 }, |
| 166 | .plane_caps = INTEL_PLANE_CAP_TILING_4(1UL << (6)) | INTEL_PLANE_CAP_CCS_RC_CC(1UL << (1)), |
| 167 | |
| 168 | .ccs.cc_planes = BIT(1)(1UL << (1)), |
| 169 | |
| 170 | FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats).formats = gen12_flat_ccs_cc_formats, .format_count = (sizeof ((gen12_flat_ccs_cc_formats)) / sizeof((gen12_flat_ccs_cc_formats )[0])), |
| 171 | }, { |
| 172 | .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS((((__u64)0x01) << 56) | ((10) & 0x00ffffffffffffffULL )), |
| 173 | .display_ver = { 13, 13 }, |
| 174 | .plane_caps = INTEL_PLANE_CAP_TILING_4(1UL << (6)) | INTEL_PLANE_CAP_CCS_RC(1UL << (0)), |
| 175 | }, { |
| 176 | .modifier = I915_FORMAT_MOD_4_TILED((((__u64)0x01) << 56) | ((9) & 0x00ffffffffffffffULL )), |
| 177 | .display_ver = { 13, 13 }, |
| 178 | .plane_caps = INTEL_PLANE_CAP_TILING_4(1UL << (6)), |
| 179 | }, { |
| 180 | .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )), |
| 181 | .display_ver = { 12, 13 }, |
| 182 | .plane_caps = INTEL_PLANE_CAP_TILING_Y(1UL << (4)) | INTEL_PLANE_CAP_CCS_MC(1UL << (2)), |
| 183 | |
| 184 | .ccs.packed_aux_planes = BIT(1)(1UL << (1)), |
| 185 | .ccs.planar_aux_planes = BIT(2)(1UL << (2)) | BIT(3)(1UL << (3)), |
| 186 | |
| 187 | FORMAT_OVERRIDE(gen12_ccs_formats).formats = gen12_ccs_formats, .format_count = (sizeof((gen12_ccs_formats )) / sizeof((gen12_ccs_formats)[0])), |
| 188 | }, { |
| 189 | .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )), |
| 190 | .display_ver = { 12, 13 }, |
| 191 | .plane_caps = INTEL_PLANE_CAP_TILING_Y(1UL << (4)) | INTEL_PLANE_CAP_CCS_RC(1UL << (0)), |
| 192 | |
| 193 | .ccs.packed_aux_planes = BIT(1)(1UL << (1)), |
| 194 | |
| 195 | FORMAT_OVERRIDE(gen12_ccs_formats).formats = gen12_ccs_formats, .format_count = (sizeof((gen12_ccs_formats )) / sizeof((gen12_ccs_formats)[0])), |
| 196 | }, { |
| 197 | .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC((((__u64)0x01) << 56) | ((8) & 0x00ffffffffffffffULL )), |
| 198 | .display_ver = { 12, 13 }, |
| 199 | .plane_caps = INTEL_PLANE_CAP_TILING_Y(1UL << (4)) | INTEL_PLANE_CAP_CCS_RC_CC(1UL << (1)), |
| 200 | |
| 201 | .ccs.cc_planes = BIT(2)(1UL << (2)), |
| 202 | .ccs.packed_aux_planes = BIT(1)(1UL << (1)), |
| 203 | |
| 204 | FORMAT_OVERRIDE(gen12_ccs_cc_formats).formats = gen12_ccs_cc_formats, .format_count = (sizeof((gen12_ccs_cc_formats )) / sizeof((gen12_ccs_cc_formats)[0])), |
| 205 | }, { |
| 206 | .modifier = I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )), |
| 207 | .display_ver = { 9, 11 }, |
| 208 | .plane_caps = INTEL_PLANE_CAP_TILING_Yf(1UL << (5)) | INTEL_PLANE_CAP_CCS_RC(1UL << (0)), |
| 209 | |
| 210 | .ccs.packed_aux_planes = BIT(1)(1UL << (1)), |
| 211 | |
| 212 | FORMAT_OVERRIDE(skl_ccs_formats).formats = skl_ccs_formats, .format_count = (sizeof((skl_ccs_formats )) / sizeof((skl_ccs_formats)[0])), |
| 213 | }, { |
| 214 | .modifier = I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )), |
| 215 | .display_ver = { 9, 11 }, |
| 216 | .plane_caps = INTEL_PLANE_CAP_TILING_Y(1UL << (4)) | INTEL_PLANE_CAP_CCS_RC(1UL << (0)), |
| 217 | |
| 218 | .ccs.packed_aux_planes = BIT(1)(1UL << (1)), |
| 219 | |
| 220 | FORMAT_OVERRIDE(skl_ccs_formats).formats = skl_ccs_formats, .format_count = (sizeof((skl_ccs_formats )) / sizeof((skl_ccs_formats)[0])), |
| 221 | }, { |
| 222 | .modifier = I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )), |
| 223 | .display_ver = { 9, 11 }, |
| 224 | .plane_caps = INTEL_PLANE_CAP_TILING_Yf(1UL << (5)), |
| 225 | }, { |
| 226 | .modifier = I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )), |
| 227 | .display_ver = { 9, 13 }, |
| 228 | .plane_caps = INTEL_PLANE_CAP_TILING_Y(1UL << (4)), |
| 229 | }, { |
| 230 | .modifier = I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )), |
| 231 | .display_ver = DISPLAY_VER_ALL{ 0, -1 }, |
| 232 | .plane_caps = INTEL_PLANE_CAP_TILING_X(1UL << (3)), |
| 233 | }, { |
| 234 | .modifier = DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ), |
| 235 | .display_ver = DISPLAY_VER_ALL{ 0, -1 }, |
| 236 | }, |
| 237 | }; |
| 238 | |
| 239 | static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier) |
| 240 | { |
| 241 | int i; |
| 242 | |
| 243 | for (i = 0; i < ARRAY_SIZE(intel_modifiers)(sizeof((intel_modifiers)) / sizeof((intel_modifiers)[0])); i++) |
| 244 | if (intel_modifiers[i].modifier == modifier) |
| 245 | return &intel_modifiers[i]; |
| 246 | |
| 247 | return NULL((void *)0); |
| 248 | } |
| 249 | |
| 250 | static const struct intel_modifier_desc *lookup_modifier(u64 modifier) |
| 251 | { |
| 252 | const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); |
| 253 | |
| 254 | if (WARN_ON(!md)({ int __ret = !!(!md); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!md", "/usr/src/sys/dev/pci/drm/i915/display/intel_fb.c", 254 ); __builtin_expect(!!(__ret), 0); })) |
| 255 | return &intel_modifiers[0]; |
| 256 | |
| 257 | return md; |
| 258 | } |
| 259 | |
| 260 | static const struct drm_format_info * |
| 261 | lookup_format_info(const struct drm_format_info formats[], |
| 262 | int num_formats, u32 format) |
| 263 | { |
| 264 | int i; |
| 265 | |
| 266 | for (i = 0; i < num_formats; i++) { |
| 267 | if (formats[i].format == format) |
| 268 | return &formats[i]; |
| 269 | } |
| 270 | |
| 271 | return NULL((void *)0); |
| 272 | } |
| 273 | |
| 274 | /** |
| 275 | * intel_fb_get_format_info: Get a modifier specific format information |
| 276 | * @cmd: FB add command structure |
| 277 | * |
| 278 | * Returns: |
| 279 | * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0], |
| 280 | * or %NULL if the modifier doesn't override the format. |
| 281 | */ |
| 282 | const struct drm_format_info * |
| 283 | intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd) |
| 284 | { |
| 285 | const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]); |
| 286 | |
| 287 | if (!md || !md->formats) |
| 288 | return NULL((void *)0); |
| 289 | |
| 290 | return lookup_format_info(md->formats, md->format_count, cmd->pixel_format); |
| 291 | } |
| 292 | |
| 293 | static bool_Bool plane_caps_contain_any(u8 caps, u8 mask) |
| 294 | { |
| 295 | return caps & mask; |
| 296 | } |
| 297 | |
| 298 | static bool_Bool plane_caps_contain_all(u8 caps, u8 mask) |
| 299 | { |
| 300 | return (caps & mask) == mask; |
| 301 | } |
| 302 | |
| 303 | /** |
| 304 | * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type |
| 305 | * @modifier: Modifier to check |
| 306 | * |
| 307 | * Returns: |
| 308 | * Returns %true if @modifier is a render, render with color clear or |
| 309 | * media compression modifier. |
| 310 | */ |
| 311 | bool_Bool intel_fb_is_ccs_modifier(u64 modifier) |
| 312 | { |
| 313 | return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, |
| 314 | INTEL_PLANE_CAP_CCS_MASK((1UL << (0)) | (1UL << (1)) | (1UL << (2)) )); |
| 315 | } |
| 316 | |
| 317 | /** |
| 318 | * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type |
| 319 | * @modifier: Modifier to check |
| 320 | * |
| 321 | * Returns: |
| 322 | * Returns %true if @modifier is a render with color clear modifier. |
| 323 | */ |
| 324 | bool_Bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier) |
| 325 | { |
| 326 | return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, |
| 327 | INTEL_PLANE_CAP_CCS_RC_CC(1UL << (1))); |
| 328 | } |
| 329 | |
| 330 | /** |
| 331 | * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type |
| 332 | * @modifier: Modifier to check |
| 333 | * |
| 334 | * Returns: |
| 335 | * Returns %true if @modifier is a media compression modifier. |
| 336 | */ |
| 337 | bool_Bool intel_fb_is_mc_ccs_modifier(u64 modifier) |
| 338 | { |
| 339 | return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, |
| 340 | INTEL_PLANE_CAP_CCS_MC(1UL << (2))); |
| 341 | } |
| 342 | |
| 343 | static bool_Bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, |
| 344 | u8 display_ver_from, u8 display_ver_until) |
| 345 | { |
| 346 | return md->display_ver.from <= display_ver_until && |
| 347 | display_ver_from <= md->display_ver.until; |
| 348 | } |
| 349 | |
| 350 | static bool_Bool plane_has_modifier(struct drm_i915_privateinteldrm_softc *i915, |
| 351 | u8 plane_caps, |
| 352 | const struct intel_modifier_desc *md) |
| 353 | { |
| 354 | if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until)(((&(i915)->__runtime)->display.ip.ver) >= (md-> display_ver.from) && ((&(i915)->__runtime)-> display.ip.ver) <= (md->display_ver.until))) |
| 355 | return false0; |
| 356 | |
| 357 | if (!plane_caps_contain_all(plane_caps, md->plane_caps)) |
| 358 | return false0; |
| 359 | |
| 360 | return true1; |
| 361 | } |
| 362 | |
| 363 | /** |
| 364 | * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities |
| 365 | * @i915: i915 device instance |
| 366 | * @plane_caps: capabilities for the plane the modifiers are queried for |
| 367 | * |
| 368 | * Returns: |
| 369 | * Returns the list of modifiers allowed by the @i915 platform and @plane_caps. |
| 370 | * The caller must free the returned buffer. |
| 371 | */ |
| 372 | u64 *intel_fb_plane_get_modifiers(struct drm_i915_privateinteldrm_softc *i915, |
| 373 | u8 plane_caps) |
| 374 | { |
| 375 | u64 *list, *p; |
| 376 | int count = 1; /* +1 for invalid modifier terminator */ |
| 377 | int i; |
| 378 | |
| 379 | for (i = 0; i < ARRAY_SIZE(intel_modifiers)(sizeof((intel_modifiers)) / sizeof((intel_modifiers)[0])); i++) { |
| 380 | if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) |
| 381 | count++; |
| 382 | } |
| 383 | |
| 384 | list = kmalloc_array(count, sizeof(*list), GFP_KERNEL(0x0001 | 0x0004)); |
| 385 | if (drm_WARN_ON(&i915->drm, !list)({ int __ret = !!((!list)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "!list" ")"); __builtin_expect(!!(__ret), 0); })) |
| 386 | return NULL((void *)0); |
| 387 | |
| 388 | p = list; |
| 389 | for (i = 0; i < ARRAY_SIZE(intel_modifiers)(sizeof((intel_modifiers)) / sizeof((intel_modifiers)[0])); i++) { |
| 390 | if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) |
| 391 | *p++ = intel_modifiers[i].modifier; |
| 392 | } |
| 393 | *p++ = DRM_FORMAT_MOD_INVALID((((__u64)0) << 56) | ((((1ULL << 56) - 1)) & 0x00ffffffffffffffULL)); |
| 394 | |
| 395 | return list; |
| 396 | } |
| 397 | |
| 398 | /** |
| 399 | * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane |
| 400 | * @plane: Plane to check the modifier support for |
| 401 | * @modifier: The modifier to check the support for |
| 402 | * |
| 403 | * Returns: |
| 404 | * %true if the @modifier is supported on @plane. |
| 405 | */ |
| 406 | bool_Bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) |
| 407 | { |
| 408 | int i; |
| 409 | |
| 410 | for (i = 0; i < plane->base.modifier_count; i++) |
| 411 | if (plane->base.modifiers[i] == modifier) |
| 412 | return true1; |
| 413 | |
| 414 | return false0; |
| 415 | } |
| 416 | |
| 417 | static bool_Bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md, |
| 418 | const struct drm_format_info *info) |
| 419 | { |
| 420 | if (!info->is_yuv) |
| 421 | return false0; |
| 422 | |
| 423 | if (hweight8(md->ccs.planar_aux_planes) == 2) |
| 424 | return info->num_planes == 4; |
| 425 | else |
| 426 | return info->num_planes == 2; |
| 427 | } |
| 428 | |
| 429 | /** |
| 430 | * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar |
| 431 | * @info: format to check |
| 432 | * @modifier: modifier used with the format |
| 433 | * |
| 434 | * Returns: |
| 435 | * %true if @info / @modifier is YUV semiplanar. |
| 436 | */ |
| 437 | bool_Bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, |
| 438 | u64 modifier) |
| 439 | { |
| 440 | return format_is_yuv_semiplanar(lookup_modifier(modifier), info); |
| 441 | } |
| 442 | |
| 443 | static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md, |
| 444 | const struct drm_format_info *format) |
| 445 | { |
| 446 | if (format_is_yuv_semiplanar(md, format)) |
| 447 | return md->ccs.planar_aux_planes; |
| 448 | else |
| 449 | return md->ccs.packed_aux_planes; |
| 450 | } |
| 451 | |
| 452 | /** |
| 453 | * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane |
| 454 | * @fb: Framebuffer |
| 455 | * @color_plane: color plane index to check |
| 456 | * |
| 457 | * Returns: |
| 458 | * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane. |
| 459 | */ |
| 460 | bool_Bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) |
| 461 | { |
| 462 | const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); |
| 463 | |
| 464 | return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane)(1UL << (color_plane)); |
| 465 | } |
| 466 | |
| 467 | /** |
| 468 | * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane |
| 469 | * @fb: Framebuffer |
| 470 | * @color_plane: color plane index to check |
| 471 | * |
| 472 | * Returns: |
| 473 | * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane. |
| 474 | */ |
| 475 | static bool_Bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) |
| 476 | { |
| 477 | const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); |
| 478 | |
| 479 | return check_modifier_display_ver_range(md, 12, 13) && |
| 480 | ccs_aux_plane_mask(md, fb->format) & BIT(color_plane)(1UL << (color_plane)); |
| 481 | } |
| 482 | |
| 483 | /** |
| 484 | * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer |
| 485 | * @fb: Framebuffer |
| 486 | * |
| 487 | * Returns: |
| 488 | * Returns the index of the color clear plane for @fb, or -1 if @fb is not a |
| 489 | * framebuffer using a render compression/color clear modifier. |
| 490 | */ |
| 491 | int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb) |
| 492 | { |
| 493 | const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); |
| 494 | |
| 495 | if (!md->ccs.cc_planes) |
| 496 | return -1; |
| 497 | |
| 498 | drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1)({ static int __warned; int __ret = !!((hweight8(md->ccs.cc_planes ) > 1)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((fb->dev))->dev), "", "drm_WARN_ON_ONCE(" "hweight8(md->ccs.cc_planes) > 1" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); }); |
| 499 | |
| 500 | return ilog2((int)md->ccs.cc_planes)((sizeof((int)md->ccs.cc_planes) <= 4) ? (fls((int)md-> ccs.cc_planes) - 1) : (flsl((int)md->ccs.cc_planes) - 1)); |
| 501 | } |
| 502 | |
| 503 | static bool_Bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane) |
| 504 | { |
| 505 | return intel_fb_rc_ccs_cc_plane(fb) == color_plane; |
| 506 | } |
| 507 | |
| 508 | static bool_Bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) |
| 509 | { |
| 510 | return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && |
| 511 | color_plane == 1; |
| 512 | } |
| 513 | |
| 514 | bool_Bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) |
| 515 | { |
| 516 | return fb->modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ) || |
| 517 | intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) || |
| 518 | is_gen12_ccs_cc_plane(fb, color_plane); |
| 519 | } |
| 520 | |
| 521 | int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) |
| 522 | { |
| 523 | drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||({ int __ret = !!((!intel_fb_is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format-> num_planes / 2))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((fb->dev))->dev), "", "drm_WARN_ON(" "!intel_fb_is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 524 | (main_plane && main_plane >= fb->format->num_planes / 2))({ int __ret = !!((!intel_fb_is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format-> num_planes / 2))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((fb->dev))->dev), "", "drm_WARN_ON(" "!intel_fb_is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 525 | |
| 526 | return fb->format->num_planes / 2 + main_plane; |
| 527 | } |
| 528 | |
| 529 | int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) |
| 530 | { |
| 531 | drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||({ int __ret = !!((!intel_fb_is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((fb->dev))-> dev), "", "drm_WARN_ON(" "!intel_fb_is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2" ")"); __builtin_expect(!!(__ret), 0); }) |
| 532 | ccs_plane < fb->format->num_planes / 2)({ int __ret = !!((!intel_fb_is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((fb->dev))-> dev), "", "drm_WARN_ON(" "!intel_fb_is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2" ")"); __builtin_expect(!!(__ret), 0); }); |
| 533 | |
| 534 | if (is_gen12_ccs_cc_plane(fb, ccs_plane)) |
| 535 | return 0; |
| 536 | |
| 537 | return ccs_plane - fb->format->num_planes / 2; |
| 538 | } |
| 539 | |
| 540 | static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane) |
| 541 | { |
| 542 | int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane); |
| 543 | unsigned int main_stride = fb->base.pitches[main_plane]; |
| 544 | unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane); |
| 545 | |
| 546 | return DIV_ROUND_UP(main_stride, 4 * main_tile_width)(((main_stride) + ((4 * main_tile_width) - 1)) / (4 * main_tile_width )) * 64; |
| 547 | } |
| 548 | |
| 549 | int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) |
| 550 | { |
| 551 | const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); |
| 552 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->dev); |
| 553 | |
| 554 | if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes) |
| 555 | return main_to_ccs_plane(fb, main_plane); |
| 556 | else if (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) < 11 && |
| 557 | format_is_yuv_semiplanar(md, fb->format)) |
| 558 | return 1; |
| 559 | else |
| 560 | return 0; |
| 561 | } |
| 562 | |
| 563 | unsigned int intel_tile_size(const struct drm_i915_privateinteldrm_softc *i915) |
| 564 | { |
| 565 | return DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) == 2 ? 2048 : 4096; |
| 566 | } |
| 567 | |
| 568 | unsigned int |
| 569 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) |
| 570 | { |
| 571 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev); |
| 572 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 573 | |
| 574 | switch (fb->modifier) { |
| 575 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 576 | return intel_tile_size(dev_priv); |
| 577 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 578 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 2) |
| 579 | return 128; |
| 580 | else |
| 581 | return 512; |
| 582 | case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS((((__u64)0x01) << 56) | ((10) & 0x00ffffffffffffffULL )): |
| 583 | case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC((((__u64)0x01) << 56) | ((12) & 0x00ffffffffffffffULL )): |
| 584 | case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS((((__u64)0x01) << 56) | ((11) & 0x00ffffffffffffffULL )): |
| 585 | case I915_FORMAT_MOD_4_TILED((((__u64)0x01) << 56) | ((9) & 0x00ffffffffffffffULL )): |
| 586 | /* |
| 587 | * Each 4K tile consists of 64B(8*8) subtiles, with |
| 588 | * same shape as Y Tile(i.e 4*16B OWords) |
| 589 | */ |
| 590 | return 128; |
| 591 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 592 | if (intel_fb_is_ccs_aux_plane(fb, color_plane)) |
| 593 | return 128; |
| 594 | fallthroughdo {} while (0); |
| 595 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )): |
| 596 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC((((__u64)0x01) << 56) | ((8) & 0x00ffffffffffffffULL )): |
| 597 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )): |
| 598 | if (intel_fb_is_ccs_aux_plane(fb, color_plane) || |
| 599 | is_gen12_ccs_cc_plane(fb, color_plane)) |
| 600 | return 64; |
| 601 | fallthroughdo {} while (0); |
| 602 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 603 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 2 || HAS_128_BYTE_Y_TILING(dev_priv)(((&(dev_priv)->__runtime)->graphics.ip.ver) != 2 && !(IS_PLATFORM(dev_priv, INTEL_I915G) || IS_PLATFORM(dev_priv , INTEL_I915GM)))) |
| 604 | return 128; |
| 605 | else |
| 606 | return 512; |
| 607 | case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )): |
| 608 | if (intel_fb_is_ccs_aux_plane(fb, color_plane)) |
| 609 | return 128; |
| 610 | fallthroughdo {} while (0); |
| 611 | case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )): |
| 612 | switch (cpp) { |
| 613 | case 1: |
| 614 | return 64; |
| 615 | case 2: |
| 616 | case 4: |
| 617 | return 128; |
| 618 | case 8: |
| 619 | case 16: |
| 620 | return 256; |
| 621 | default: |
| 622 | MISSING_CASE(cpp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "cpp", (long)(cpp)); __builtin_expect(!!(__ret), 0); }); |
| 623 | return cpp; |
| 624 | } |
| 625 | break; |
| 626 | default: |
| 627 | MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb->modifier", (long)(fb->modifier)); __builtin_expect (!!(__ret), 0); }); |
| 628 | return cpp; |
| 629 | } |
| 630 | } |
| 631 | |
| 632 | unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane) |
| 633 | { |
| 634 | return intel_tile_size(to_i915(fb->dev)) / |
| 635 | intel_tile_width_bytes(fb, color_plane); |
| 636 | } |
| 637 | |
| 638 | /* |
| 639 | * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT |
| 640 | * page tile size. |
| 641 | */ |
| 642 | static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, |
| 643 | unsigned int *tile_width, |
| 644 | unsigned int *tile_height) |
| 645 | { |
| 646 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); |
| 647 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 648 | |
| 649 | *tile_width = tile_width_bytes / cpp; |
| 650 | *tile_height = intel_tile_height(fb, color_plane); |
| 651 | } |
| 652 | |
| 653 | /* |
| 654 | * Return the tile dimensions in pixel units, based on the tile block size. |
| 655 | * The block covers the full GTT page sized tile on all tiled surfaces and |
| 656 | * it's a 64 byte portion of the tile on TGL+ CCS surfaces. |
| 657 | */ |
| 658 | static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane, |
| 659 | unsigned int *tile_width, |
| 660 | unsigned int *tile_height) |
| 661 | { |
| 662 | intel_tile_dims(fb, color_plane, tile_width, tile_height); |
| 663 | |
| 664 | if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) |
| 665 | *tile_height = 1; |
| 666 | } |
| 667 | |
| 668 | unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane) |
| 669 | { |
| 670 | unsigned int tile_width, tile_height; |
| 671 | |
| 672 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
| 673 | |
| 674 | return fb->pitches[color_plane] * tile_height; |
| 675 | } |
| 676 | |
| 677 | unsigned int |
| 678 | intel_fb_align_height(const struct drm_framebuffer *fb, |
| 679 | int color_plane, unsigned int height) |
| 680 | { |
| 681 | unsigned int tile_height = intel_tile_height(fb, color_plane); |
| 682 | |
| 683 | return roundup2(height, tile_height)(((height) + ((tile_height) - 1)) & (~((__typeof(height)) (tile_height) - 1))); |
| 684 | } |
| 685 | |
| 686 | static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) |
| 687 | { |
| 688 | u8 tiling_caps = lookup_modifier(fb_modifier)->plane_caps & |
| 689 | INTEL_PLANE_CAP_TILING_MASK((1UL << (3)) | (1UL << (4)) | (1UL << (5)) | (1UL << (6))); |
| 690 | |
| 691 | switch (tiling_caps) { |
| 692 | case INTEL_PLANE_CAP_TILING_Y(1UL << (4)): |
| 693 | return I915_TILING_Y2; |
| 694 | case INTEL_PLANE_CAP_TILING_X(1UL << (3)): |
| 695 | return I915_TILING_X1; |
| 696 | case INTEL_PLANE_CAP_TILING_4(1UL << (6)): |
| 697 | case INTEL_PLANE_CAP_TILING_Yf(1UL << (5)): |
| 698 | case INTEL_PLANE_CAP_TILING_NONE0: |
| 699 | return I915_TILING_NONE0; |
| 700 | default: |
| 701 | MISSING_CASE(tiling_caps)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "tiling_caps", (long)(tiling_caps)); __builtin_expect(!!(__ret ), 0); }); |
| 702 | return I915_TILING_NONE0; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | static bool_Bool intel_modifier_uses_dpt(struct drm_i915_privateinteldrm_softc *i915, u64 modifier) |
| 707 | { |
| 708 | return DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ); |
| 709 | } |
| 710 | |
| 711 | bool_Bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) |
| 712 | { |
| 713 | return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); |
| 714 | } |
| 715 | |
| 716 | unsigned int intel_cursor_alignment(const struct drm_i915_privateinteldrm_softc *i915) |
| 717 | { |
| 718 | if (IS_I830(i915)IS_PLATFORM(i915, INTEL_I830)) |
| 719 | return 16 * 1024; |
| 720 | else if (IS_I85X(i915)IS_PLATFORM(i915, INTEL_I85X)) |
| 721 | return 256; |
| 722 | else if (IS_I845G(i915)IS_PLATFORM(i915, INTEL_I845G) || IS_I865G(i915)IS_PLATFORM(i915, INTEL_I865G)) |
| 723 | return 32; |
| 724 | else |
| 725 | return 4 * 1024; |
| 726 | } |
| 727 | |
| 728 | static unsigned int intel_linear_alignment(const struct drm_i915_privateinteldrm_softc *dev_priv) |
| 729 | { |
| 730 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 9) |
| 731 | return 256 * 1024; |
| 732 | else if (IS_I965G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965G) || IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) || |
| 733 | IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 734 | return 128 * 1024; |
| 735 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 4) |
| 736 | return 4 * 1024; |
| 737 | else |
| 738 | return 0; |
| 739 | } |
| 740 | |
| 741 | unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
| 742 | int color_plane) |
| 743 | { |
| 744 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev); |
| 745 | |
| 746 | if (intel_fb_uses_dpt(fb)) |
| 747 | return 512 * 4096; |
| 748 | |
| 749 | /* AUX_DIST needs only 4K alignment */ |
| 750 | if (intel_fb_is_ccs_aux_plane(fb, color_plane)) |
| 751 | return 4096; |
| 752 | |
| 753 | if (is_semiplanar_uv_plane(fb, color_plane)) { |
| 754 | /* |
| 755 | * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes |
| 756 | * alignment for linear UV planes on all platforms. |
| 757 | */ |
| 758 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
| 759 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) )) |
| 760 | return intel_linear_alignment(dev_priv); |
| 761 | |
| 762 | return intel_tile_row_size(fb, color_plane); |
| 763 | } |
| 764 | |
| 765 | return 4096; |
| 766 | } |
| 767 | |
| 768 | drm_WARN_ON(&dev_priv->drm, color_plane != 0)({ int __ret = !!((color_plane != 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "color_plane != 0" ")"); __builtin_expect(!! (__ret), 0); }); |
| 769 | |
| 770 | switch (fb->modifier) { |
| 771 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 772 | return intel_linear_alignment(dev_priv); |
| 773 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 774 | if (HAS_ASYNC_FLIPS(dev_priv)(((&(dev_priv)->__runtime)->display.ip.ver) >= 5 )) |
| 775 | return 256 * 1024; |
| 776 | return 0; |
| 777 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )): |
| 778 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )): |
| 779 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC((((__u64)0x01) << 56) | ((8) & 0x00ffffffffffffffULL )): |
| 780 | return 16 * 1024; |
| 781 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 782 | case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )): |
| 783 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 784 | case I915_FORMAT_MOD_4_TILED((((__u64)0x01) << 56) | ((9) & 0x00ffffffffffffffULL )): |
| 785 | case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )): |
| 786 | return 1 * 1024 * 1024; |
| 787 | case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS((((__u64)0x01) << 56) | ((10) & 0x00ffffffffffffffULL )): |
| 788 | case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC((((__u64)0x01) << 56) | ((12) & 0x00ffffffffffffffULL )): |
| 789 | case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS((((__u64)0x01) << 56) | ((11) & 0x00ffffffffffffffULL )): |
| 790 | return 16 * 1024; |
| 791 | default: |
| 792 | MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb->modifier", (long)(fb->modifier)); __builtin_expect (!!(__ret), 0); }); |
| 793 | return 0; |
| 794 | } |
| 795 | } |
| 796 | |
| 797 | void intel_fb_plane_get_subsampling(int *hsub, int *vsub, |
| 798 | const struct drm_framebuffer *fb, |
| 799 | int color_plane) |
| 800 | { |
| 801 | int main_plane; |
| 802 | |
| 803 | if (color_plane == 0) { |
| 804 | *hsub = 1; |
| 805 | *vsub = 1; |
| 806 | |
| 807 | return; |
| 808 | } |
| 809 | |
| 810 | /* |
| 811 | * TODO: Deduct the subsampling from the char block for all CCS |
| 812 | * formats and planes. |
| 813 | */ |
| 814 | if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) { |
| 815 | *hsub = fb->format->hsub; |
| 816 | *vsub = fb->format->vsub; |
| 817 | |
| 818 | return; |
| 819 | } |
| 820 | |
| 821 | main_plane = skl_ccs_to_main_plane(fb, color_plane); |
| 822 | *hsub = drm_format_info_block_width(fb->format, color_plane) / |
| 823 | drm_format_info_block_width(fb->format, main_plane); |
| 824 | |
| 825 | /* |
| 826 | * The min stride check in the core framebuffer_check() function |
| 827 | * assumes that format->hsub applies to every plane except for the |
| 828 | * first plane. That's incorrect for the CCS AUX plane of the first |
| 829 | * plane, but for the above check to pass we must define the block |
| 830 | * width with that subsampling applied to it. Adjust the width here |
| 831 | * accordingly, so we can calculate the actual subsampling factor. |
| 832 | */ |
| 833 | if (main_plane == 0) |
| 834 | *hsub *= fb->format->hsub; |
| 835 | |
| 836 | *vsub = 32; |
| 837 | } |
| 838 | |
| 839 | static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h) |
| 840 | { |
| 841 | int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ? |
| 842 | skl_ccs_to_main_plane(&fb->base, color_plane) : 0; |
| 843 | unsigned int main_width = fb->base.width; |
| 844 | unsigned int main_height = fb->base.height; |
| 845 | int main_hsub, main_vsub; |
| 846 | int hsub, vsub; |
| 847 | |
| 848 | intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane); |
| 849 | intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane); |
| 850 | |
| 851 | *w = DIV_ROUND_UP(main_width, main_hsub * hsub)(((main_width) + ((main_hsub * hsub) - 1)) / (main_hsub * hsub )); |
| 852 | *h = DIV_ROUND_UP(main_height, main_vsub * vsub)(((main_height) + ((main_vsub * vsub) - 1)) / (main_vsub * vsub )); |
| 853 | } |
| 854 | |
| 855 | static u32 intel_adjust_tile_offset(int *x, int *y, |
| 856 | unsigned int tile_width, |
| 857 | unsigned int tile_height, |
| 858 | unsigned int tile_size, |
| 859 | unsigned int pitch_tiles, |
| 860 | u32 old_offset, |
| 861 | u32 new_offset) |
| 862 | { |
| 863 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
| 864 | unsigned int tiles; |
| 865 | |
| 866 | WARN_ON(old_offset & (tile_size - 1))({ int __ret = !!(old_offset & (tile_size - 1)); if (__ret ) printf("WARNING %s failed at %s:%d\n", "old_offset & (tile_size - 1)" , "/usr/src/sys/dev/pci/drm/i915/display/intel_fb.c", 866); __builtin_expect (!!(__ret), 0); }); |
| 867 | WARN_ON(new_offset & (tile_size - 1))({ int __ret = !!(new_offset & (tile_size - 1)); if (__ret ) printf("WARNING %s failed at %s:%d\n", "new_offset & (tile_size - 1)" , "/usr/src/sys/dev/pci/drm/i915/display/intel_fb.c", 867); __builtin_expect (!!(__ret), 0); }); |
| 868 | WARN_ON(new_offset > old_offset)({ int __ret = !!(new_offset > old_offset); if (__ret) printf ("WARNING %s failed at %s:%d\n", "new_offset > old_offset" , "/usr/src/sys/dev/pci/drm/i915/display/intel_fb.c", 868); __builtin_expect (!!(__ret), 0); }); |
| 869 | |
| 870 | tiles = (old_offset - new_offset) / tile_size; |
| 871 | |
| 872 | *y += tiles / pitch_tiles * tile_height; |
| 873 | *x += tiles % pitch_tiles * tile_width; |
| 874 | |
| 875 | /* minimize x in case it got needlessly big */ |
| 876 | *y += *x / pitch_pixels * tile_height; |
| 877 | *x %= pitch_pixels; |
| 878 | |
| 879 | return new_offset; |
| 880 | } |
| 881 | |
| 882 | static u32 intel_adjust_linear_offset(int *x, int *y, |
| 883 | unsigned int cpp, |
| 884 | unsigned int pitch, |
| 885 | u32 old_offset, |
| 886 | u32 new_offset) |
| 887 | { |
| 888 | old_offset += *y * pitch + *x * cpp; |
| 889 | |
| 890 | *y = (old_offset - new_offset) / pitch; |
| 891 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; |
| 892 | |
| 893 | return new_offset; |
| 894 | } |
| 895 | |
| 896 | static u32 intel_adjust_aligned_offset(int *x, int *y, |
| 897 | const struct drm_framebuffer *fb, |
| 898 | int color_plane, |
| 899 | unsigned int rotation, |
| 900 | unsigned int pitch, |
| 901 | u32 old_offset, u32 new_offset) |
| 902 | { |
| 903 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->dev); |
| 904 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 905 | |
| 906 | drm_WARN_ON(&i915->drm, new_offset > old_offset)({ int __ret = !!((new_offset > old_offset)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&i915->drm))-> dev), "", "drm_WARN_ON(" "new_offset > old_offset" ")"); __builtin_expect (!!(__ret), 0); }); |
| 907 | |
| 908 | if (!is_surface_linear(fb, color_plane)) { |
| 909 | unsigned int tile_size, tile_width, tile_height; |
| 910 | unsigned int pitch_tiles; |
| 911 | |
| 912 | tile_size = intel_tile_size(i915); |
| 913 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
| 914 | |
| 915 | if (drm_rotation_90_or_270(rotation)) { |
| 916 | pitch_tiles = pitch / tile_height; |
| 917 | swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) = (tile_height); (tile_height) = __tmp; } while(0); |
| 918 | } else { |
| 919 | pitch_tiles = pitch / (tile_width * cpp); |
| 920 | } |
| 921 | |
| 922 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
| 923 | tile_size, pitch_tiles, |
| 924 | old_offset, new_offset); |
| 925 | } else { |
| 926 | intel_adjust_linear_offset(x, y, cpp, pitch, |
| 927 | old_offset, new_offset); |
| 928 | } |
| 929 | |
| 930 | return new_offset; |
| 931 | } |
| 932 | |
| 933 | /* |
| 934 | * Adjust the tile offset by moving the difference into |
| 935 | * the x/y offsets. |
| 936 | */ |
| 937 | u32 intel_plane_adjust_aligned_offset(int *x, int *y, |
| 938 | const struct intel_plane_state *state, |
| 939 | int color_plane, |
| 940 | u32 old_offset, u32 new_offset) |
| 941 | { |
| 942 | return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, |
| 943 | state->hw.rotation, |
| 944 | state->view.color_plane[color_plane].mapping_stride, |
| 945 | old_offset, new_offset); |
| 946 | } |
| 947 | |
| 948 | /* |
| 949 | * Computes the aligned offset to the base tile and adjusts |
| 950 | * x, y. bytes per pixel is assumed to be a power-of-two. |
| 951 | * |
| 952 | * In the 90/270 rotated case, x and y are assumed |
| 953 | * to be already rotated to match the rotated GTT view, and |
| 954 | * pitch is the tile_height aligned framebuffer height. |
| 955 | * |
| 956 | * This function is used when computing the derived information |
| 957 | * under intel_framebuffer, so using any of that information |
| 958 | * here is not allowed. Anything under drm_framebuffer can be |
| 959 | * used. This is why the user has to pass in the pitch since it |
| 960 | * is specified in the rotated orientation. |
| 961 | */ |
| 962 | static u32 intel_compute_aligned_offset(struct drm_i915_privateinteldrm_softc *i915, |
| 963 | int *x, int *y, |
| 964 | const struct drm_framebuffer *fb, |
| 965 | int color_plane, |
| 966 | unsigned int pitch, |
| 967 | unsigned int rotation, |
| 968 | u32 alignment) |
| 969 | { |
| 970 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 971 | u32 offset, offset_aligned; |
| 972 | |
| 973 | if (!is_surface_linear(fb, color_plane)) { |
| 974 | unsigned int tile_size, tile_width, tile_height; |
| 975 | unsigned int tile_rows, tiles, pitch_tiles; |
| 976 | |
| 977 | tile_size = intel_tile_size(i915); |
| 978 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
| 979 | |
| 980 | if (drm_rotation_90_or_270(rotation)) { |
| 981 | pitch_tiles = pitch / tile_height; |
| 982 | swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) = (tile_height); (tile_height) = __tmp; } while(0); |
| 983 | } else { |
| 984 | pitch_tiles = pitch / (tile_width * cpp); |
| 985 | } |
| 986 | |
| 987 | tile_rows = *y / tile_height; |
| 988 | *y %= tile_height; |
| 989 | |
| 990 | tiles = *x / tile_width; |
| 991 | *x %= tile_width; |
| 992 | |
| 993 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
| 994 | |
| 995 | offset_aligned = offset; |
| 996 | if (alignment) |
| 997 | offset_aligned = rounddown(offset_aligned, alignment)(((offset_aligned) / (alignment)) * (alignment)); |
| 998 | |
| 999 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
| 1000 | tile_size, pitch_tiles, |
| 1001 | offset, offset_aligned); |
| 1002 | } else { |
| 1003 | offset = *y * pitch + *x * cpp; |
| 1004 | offset_aligned = offset; |
| 1005 | if (alignment) { |
| 1006 | offset_aligned = rounddown(offset_aligned, alignment)(((offset_aligned) / (alignment)) * (alignment)); |
| 1007 | *y = (offset % alignment) / pitch; |
| 1008 | *x = ((offset % alignment) - *y * pitch) / cpp; |
| 1009 | } else { |
| 1010 | *y = *x = 0; |
| 1011 | } |
| 1012 | } |
| 1013 | |
| 1014 | return offset_aligned; |
| 1015 | } |
| 1016 | |
| 1017 | u32 intel_plane_compute_aligned_offset(int *x, int *y, |
| 1018 | const struct intel_plane_state *state, |
| 1019 | int color_plane) |
| 1020 | { |
| 1021 | struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 1022 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_plane->base.dev); |
| 1023 | const struct drm_framebuffer *fb = state->hw.fb; |
| 1024 | unsigned int rotation = state->hw.rotation; |
| 1025 | int pitch = state->view.color_plane[color_plane].mapping_stride; |
| 1026 | u32 alignment; |
| 1027 | |
| 1028 | if (intel_plane->id == PLANE_CURSOR) |
| 1029 | alignment = intel_cursor_alignment(i915); |
| 1030 | else |
| 1031 | alignment = intel_surf_alignment(fb, color_plane); |
| 1032 | |
| 1033 | return intel_compute_aligned_offset(i915, x, y, fb, color_plane, |
| 1034 | pitch, rotation, alignment); |
| 1035 | } |
| 1036 | |
| 1037 | /* Convert the fb->offset[] into x/y offsets */ |
| 1038 | static int intel_fb_offset_to_xy(int *x, int *y, |
| 1039 | const struct drm_framebuffer *fb, |
| 1040 | int color_plane) |
| 1041 | { |
| 1042 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->dev); |
| 1043 | unsigned int height; |
| 1044 | u32 alignment; |
| 1045 | |
| 1046 | if (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 12 && |
| 1047 | !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );})) && |
| 1048 | is_semiplanar_uv_plane(fb, color_plane)) |
| 1049 | alignment = intel_tile_row_size(fb, color_plane); |
| 1050 | else if (fb->modifier != DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) )) |
| 1051 | alignment = intel_tile_size(i915); |
| 1052 | else |
| 1053 | alignment = 0; |
| 1054 | |
| 1055 | if (alignment != 0 && fb->offsets[color_plane] % alignment) { |
| 1056 | drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n" , fb->offsets[color_plane], color_plane) |
| 1057 | "Misaligned offset 0x%08x for color plane %d\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n" , fb->offsets[color_plane], color_plane) |
| 1058 | fb->offsets[color_plane], color_plane)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n" , fb->offsets[color_plane], color_plane); |
| 1059 | return -EINVAL22; |
| 1060 | } |
| 1061 | |
| 1062 | height = drm_framebuffer_plane_height(fb->height, fb, color_plane); |
| 1063 | height = roundup2(height, intel_tile_height(fb, color_plane))(((height) + ((intel_tile_height(fb, color_plane)) - 1)) & (~((__typeof(height))(intel_tile_height(fb, color_plane)) - 1 ))); |
| 1064 | |
| 1065 | /* Catch potential overflows early */ |
| 1066 | if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),({ typeof(mul_u32_u32(height, fb->pitches[color_plane])) a = (mul_u32_u32(height, fb->pitches[color_plane])); typeof (fb->offsets[color_plane]) b = (fb->offsets[color_plane ]); (u32)(a + b) < a; }) |
| 1067 | fb->offsets[color_plane])({ typeof(mul_u32_u32(height, fb->pitches[color_plane])) a = (mul_u32_u32(height, fb->pitches[color_plane])); typeof (fb->offsets[color_plane]) b = (fb->offsets[color_plane ]); (u32)(a + b) < a; })) { |
| 1068 | drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n" , fb->offsets[color_plane], fb->pitches[color_plane], color_plane ) |
| 1069 | "Bad offset 0x%08x or pitch %d for color plane %d\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n" , fb->offsets[color_plane], fb->pitches[color_plane], color_plane ) |
| 1070 | fb->offsets[color_plane], fb->pitches[color_plane],__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n" , fb->offsets[color_plane], fb->pitches[color_plane], color_plane ) |
| 1071 | color_plane)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n" , fb->offsets[color_plane], fb->pitches[color_plane], color_plane ); |
| 1072 | return -ERANGE34; |
| 1073 | } |
| 1074 | |
| 1075 | *x = 0; |
| 1076 | *y = 0; |
| 1077 | |
| 1078 | intel_adjust_aligned_offset(x, y, |
| 1079 | fb, color_plane, DRM_MODE_ROTATE_0(1<<0), |
| 1080 | fb->pitches[color_plane], |
| 1081 | fb->offsets[color_plane], 0); |
| 1082 | |
| 1083 | return 0; |
| 1084 | } |
| 1085 | |
| 1086 | static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y) |
| 1087 | { |
| 1088 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->dev); |
| 1089 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}); |
| 1090 | int main_plane; |
| 1091 | int hsub, vsub; |
| 1092 | int tile_width, tile_height; |
| 1093 | int ccs_x, ccs_y; |
| 1094 | int main_x, main_y; |
| 1095 | |
| 1096 | if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) |
| 1097 | return 0; |
| 1098 | |
| 1099 | /* |
| 1100 | * While all the tile dimensions are based on a 2k or 4k GTT page size |
| 1101 | * here the main and CCS coordinates must match only within a (64 byte |
| 1102 | * on TGL+) block inside the tile. |
| 1103 | */ |
| 1104 | intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height); |
| 1105 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); |
| 1106 | |
| 1107 | tile_width *= hsub; |
| 1108 | tile_height *= vsub; |
| 1109 | |
| 1110 | ccs_x = (x * hsub) % tile_width; |
| 1111 | ccs_y = (y * vsub) % tile_height; |
| 1112 | |
| 1113 | main_plane = skl_ccs_to_main_plane(fb, ccs_plane); |
| 1114 | main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width; |
| 1115 | main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height; |
| 1116 | |
| 1117 | /* |
| 1118 | * CCS doesn't have its own x/y offset register, so the intra CCS tile |
| 1119 | * x/y offsets must match between CCS and the main surface. |
| 1120 | */ |
| 1121 | if (main_x != ccs_x || main_y != ccs_y) { |
| 1122 | drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal_view.color_plane [main_plane].x, intel_fb->normal_view.color_plane[main_plane ].y, x, y) |
| 1123 | "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal_view.color_plane [main_plane].x, intel_fb->normal_view.color_plane[main_plane ].y, x, y) |
| 1124 | main_x, main_y,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal_view.color_plane [main_plane].x, intel_fb->normal_view.color_plane[main_plane ].y, x, y) |
| 1125 | ccs_x, ccs_y,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal_view.color_plane [main_plane].x, intel_fb->normal_view.color_plane[main_plane ].y, x, y) |
| 1126 | intel_fb->normal_view.color_plane[main_plane].x,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal_view.color_plane [main_plane].x, intel_fb->normal_view.color_plane[main_plane ].y, x, y) |
| 1127 | intel_fb->normal_view.color_plane[main_plane].y,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal_view.color_plane [main_plane].x, intel_fb->normal_view.color_plane[main_plane ].y, x, y) |
| 1128 | x, y)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal_view.color_plane [main_plane].x, intel_fb->normal_view.color_plane[main_plane ].y, x, y); |
| 1129 | return -EINVAL22; |
| 1130 | } |
| 1131 | |
| 1132 | return 0; |
| 1133 | } |
| 1134 | |
| 1135 | static bool_Bool intel_plane_can_remap(const struct intel_plane_state *plane_state) |
| 1136 | { |
| 1137 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 1138 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
| 1139 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 1140 | int i; |
| 1141 | |
| 1142 | /* We don't want to deal with remapping with cursors */ |
| 1143 | if (plane->id == PLANE_CURSOR) |
| 1144 | return false0; |
| 1145 | |
| 1146 | /* |
| 1147 | * The display engine limits already match/exceed the |
| 1148 | * render engine limits, so not much point in remapping. |
| 1149 | * Would also need to deal with the fence POT alignment |
| 1150 | * and gen2 2KiB GTT tile size. |
| 1151 | */ |
| 1152 | if (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) < 4) |
| 1153 | return false0; |
| 1154 | |
| 1155 | /* |
| 1156 | * The new CCS hash mode isn't compatible with remapping as |
| 1157 | * the virtual address of the pages affects the compressed data. |
| 1158 | */ |
| 1159 | if (intel_fb_is_ccs_modifier(fb->modifier)) |
| 1160 | return false0; |
| 1161 | |
| 1162 | /* Linear needs a page aligned stride for remapping */ |
| 1163 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) )) { |
| 1164 | unsigned int alignment = intel_tile_size(i915) - 1; |
| 1165 | |
| 1166 | for (i = 0; i < fb->format->num_planes; i++) { |
| 1167 | if (fb->pitches[i] & alignment) |
| 1168 | return false0; |
| 1169 | } |
| 1170 | } |
| 1171 | |
| 1172 | return true1; |
| 1173 | } |
| 1174 | |
| 1175 | bool_Bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) |
| 1176 | { |
| 1177 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->base.dev); |
| 1178 | |
| 1179 | return (IS_ALDERLAKE_P(i915)IS_PLATFORM(i915, INTEL_ALDERLAKE_P) || DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 14) && |
| 1180 | intel_fb_uses_dpt(&fb->base); |
| 1181 | } |
| 1182 | |
| 1183 | static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) |
| 1184 | { |
| 1185 | if (drm_rotation_90_or_270(rotation)) |
| 1186 | return fb->rotated_view.color_plane[color_plane].mapping_stride; |
| 1187 | else if (intel_fb_needs_pot_stride_remap(fb)) |
| 1188 | return fb->remapped_view.color_plane[color_plane].mapping_stride; |
| 1189 | else |
| 1190 | return fb->normal_view.color_plane[color_plane].mapping_stride; |
| 1191 | } |
| 1192 | |
| 1193 | static bool_Bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) |
| 1194 | { |
| 1195 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 1196 | const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (plane_state->hw.fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer , base) );}); |
| 1197 | unsigned int rotation = plane_state->hw.rotation; |
| 1198 | u32 stride, max_stride; |
| 1199 | |
| 1200 | /* |
| 1201 | * No remapping for invisible planes since we don't have |
| 1202 | * an actual source viewport to remap. |
| 1203 | */ |
| 1204 | if (!plane_state->uapi.visible) |
| 1205 | return false0; |
| 1206 | |
| 1207 | if (!intel_plane_can_remap(plane_state)) |
| 1208 | return false0; |
| 1209 | |
| 1210 | /* |
| 1211 | * FIXME: aux plane limits on gen9+ are |
| 1212 | * unclear in Bspec, for now no checking. |
| 1213 | */ |
| 1214 | stride = intel_fb_pitch(fb, 0, rotation); |
| 1215 | max_stride = plane->max_stride(plane, fb->base.format->format, |
| 1216 | fb->base.modifier, rotation); |
| 1217 | |
| 1218 | return stride > max_stride; |
| 1219 | } |
| 1220 | |
| 1221 | static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane, |
| 1222 | int plane_width, int *x, int *y) |
| 1223 | { |
| 1224 | struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base)((&fb->base) ? to_intel_bo((&fb->base)->obj[ 0]) : ((void *)0)); |
| 1225 | int ret; |
| 1226 | |
| 1227 | ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane); |
| 1228 | if (ret) { |
| 1229 | drm_dbg_kms(fb->base.dev,__drm_dev_dbg(((void *)0), (fb->base.dev) ? (fb->base.dev )->dev : ((void *)0), DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , color_plane, fb->base.offsets[color_plane]) |
| 1230 | "bad fb plane %d offset: 0x%x\n",__drm_dev_dbg(((void *)0), (fb->base.dev) ? (fb->base.dev )->dev : ((void *)0), DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , color_plane, fb->base.offsets[color_plane]) |
| 1231 | color_plane, fb->base.offsets[color_plane])__drm_dev_dbg(((void *)0), (fb->base.dev) ? (fb->base.dev )->dev : ((void *)0), DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , color_plane, fb->base.offsets[color_plane]); |
| 1232 | return ret; |
| 1233 | } |
| 1234 | |
| 1235 | ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y); |
| 1236 | if (ret) |
| 1237 | return ret; |
| 1238 | |
| 1239 | /* |
| 1240 | * The fence (if used) is aligned to the start of the object |
| 1241 | * so having the framebuffer wrap around across the edge of the |
| 1242 | * fenced region doesn't really work. We have no API to configure |
| 1243 | * the fence start offset within the object (nor could we probably |
| 1244 | * on gen2/3). So it's just easier if we just require that the |
| 1245 | * fb layout agrees with the fence layout. We already check that the |
| 1246 | * fb stride matches the fence stride elsewhere. |
| 1247 | */ |
| 1248 | if (color_plane == 0 && i915_gem_object_is_tiled(obj) && |
| 1249 | (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) { |
| 1250 | drm_dbg_kms(fb->base.dev,__drm_dev_dbg(((void *)0), (fb->base.dev) ? (fb->base.dev )->dev : ((void *)0), DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , color_plane, fb->base.offsets[color_plane]) |
| 1251 | "bad fb plane %d offset: 0x%x\n",__drm_dev_dbg(((void *)0), (fb->base.dev) ? (fb->base.dev )->dev : ((void *)0), DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , color_plane, fb->base.offsets[color_plane]) |
| 1252 | color_plane, fb->base.offsets[color_plane])__drm_dev_dbg(((void *)0), (fb->base.dev) ? (fb->base.dev )->dev : ((void *)0), DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , color_plane, fb->base.offsets[color_plane]); |
| 1253 | return -EINVAL22; |
| 1254 | } |
| 1255 | |
| 1256 | return 0; |
| 1257 | } |
| 1258 | |
| 1259 | static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y) |
| 1260 | { |
| 1261 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->base.dev); |
| 1262 | unsigned int tile_size = intel_tile_size(i915); |
| 1263 | u32 offset; |
| 1264 | |
| 1265 | offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane, |
| 1266 | fb->base.pitches[color_plane], |
| 1267 | DRM_MODE_ROTATE_0(1<<0), |
| 1268 | tile_size); |
| 1269 | |
| 1270 | return offset / tile_size; |
| 1271 | } |
| 1272 | |
| 1273 | struct fb_plane_view_dims { |
| 1274 | unsigned int width, height; |
| 1275 | unsigned int tile_width, tile_height; |
| 1276 | }; |
| 1277 | |
| 1278 | static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane, |
| 1279 | unsigned int width, unsigned int height, |
| 1280 | struct fb_plane_view_dims *dims) |
| 1281 | { |
| 1282 | dims->width = width; |
| 1283 | dims->height = height; |
| 1284 | |
| 1285 | intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height); |
| 1286 | } |
| 1287 | |
| 1288 | static unsigned int |
| 1289 | plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane, |
| 1290 | const struct fb_plane_view_dims *dims) |
| 1291 | { |
| 1292 | return DIV_ROUND_UP(fb->base.pitches[color_plane],(((fb->base.pitches[color_plane]) + ((dims->tile_width * fb->base.format->cpp[color_plane]) - 1)) / (dims->tile_width * fb->base.format->cpp[color_plane])) |
| 1293 | dims->tile_width * fb->base.format->cpp[color_plane])(((fb->base.pitches[color_plane]) + ((dims->tile_width * fb->base.format->cpp[color_plane]) - 1)) / (dims->tile_width * fb->base.format->cpp[color_plane])); |
| 1294 | } |
| 1295 | |
| 1296 | static unsigned int |
| 1297 | plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, |
| 1298 | unsigned int pitch_tiles) |
| 1299 | { |
| 1300 | if (intel_fb_needs_pot_stride_remap(fb)) { |
| 1301 | /* |
| 1302 | * ADL_P, the only platform needing a POT stride has a minimum |
| 1303 | * of 8 main surface tiles. |
| 1304 | */ |
| 1305 | return roundup_pow_of_two(max(pitch_tiles, 8u)(((pitch_tiles)>(8u))?(pitch_tiles):(8u))); |
| 1306 | } else { |
| 1307 | return pitch_tiles; |
| 1308 | } |
| 1309 | } |
| 1310 | |
| 1311 | static unsigned int |
| 1312 | plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, |
| 1313 | unsigned int tile_width, |
| 1314 | unsigned int src_stride_tiles, unsigned int dst_stride_tiles) |
| 1315 | { |
| 1316 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->base.dev); |
| 1317 | unsigned int stride_tiles; |
| 1318 | |
| 1319 | if ((IS_ALDERLAKE_P(i915)IS_PLATFORM(i915, INTEL_ALDERLAKE_P) || DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 14) && |
| 1320 | src_stride_tiles < dst_stride_tiles) |
| 1321 | stride_tiles = src_stride_tiles; |
| 1322 | else |
| 1323 | stride_tiles = dst_stride_tiles; |
| 1324 | |
| 1325 | return stride_tiles * tile_width * fb->base.format->cpp[color_plane]; |
| 1326 | } |
| 1327 | |
| 1328 | static unsigned int |
| 1329 | plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane, |
| 1330 | const struct fb_plane_view_dims *dims, |
| 1331 | int x) |
| 1332 | { |
| 1333 | return DIV_ROUND_UP(x + dims->width, dims->tile_width)(((x + dims->width) + ((dims->tile_width) - 1)) / (dims ->tile_width)); |
| 1334 | } |
| 1335 | |
| 1336 | static unsigned int |
| 1337 | plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane, |
| 1338 | const struct fb_plane_view_dims *dims, |
| 1339 | int y) |
| 1340 | { |
| 1341 | return DIV_ROUND_UP(y + dims->height, dims->tile_height)(((y + dims->height) + ((dims->tile_height) - 1)) / (dims ->tile_height)); |
| 1342 | } |
| 1343 | |
| 1344 | static unsigned int |
| 1345 | plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane, |
| 1346 | const struct fb_plane_view_dims *dims, |
| 1347 | int x, int y) |
| 1348 | { |
| 1349 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->base.dev); |
| 1350 | unsigned int size; |
| 1351 | |
| 1352 | size = (y + dims->height) * fb->base.pitches[color_plane] + |
| 1353 | x * fb->base.format->cpp[color_plane]; |
| 1354 | |
| 1355 | return DIV_ROUND_UP(size, intel_tile_size(i915))(((size) + ((intel_tile_size(i915)) - 1)) / (intel_tile_size( i915))); |
| 1356 | } |
| 1357 | |
| 1358 | #define assign_chk_ovf(i915, var, val) ({ \ |
| 1359 | drm_WARN_ON(&(i915)->drm, overflows_type(val, var))({ int __ret = !!(((sizeof(val) > sizeof(var) && ( val) >> (8 * sizeof(var))))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&(i915)->drm))->dev), "" , "drm_WARN_ON(" "(sizeof(val) > sizeof(var) && (val) >> (8 * sizeof(var)))" ")"); __builtin_expect(!!(__ret), 0); }); \ |
| 1360 | (var) = (val); \ |
| 1361 | }) |
| 1362 | |
| 1363 | #define assign_bfld_chk_ovf(i915, var, val)({ (var) = (val); ({ int __ret = !!(((var) != (val))); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&(i915)-> drm))->dev), "", "drm_WARN_ON(" "(var) != (val)" ")"); __builtin_expect (!!(__ret), 0); }); (var); }) ({ \ |
| 1364 | (var) = (val); \ |
| 1365 | drm_WARN_ON(&(i915)->drm, (var) != (val))({ int __ret = !!(((var) != (val))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&(i915)->drm))->dev), "" , "drm_WARN_ON(" "(var) != (val)" ")"); __builtin_expect(!!(__ret ), 0); }); \ |
| 1366 | (var); \ |
| 1367 | }) |
| 1368 | |
| 1369 | static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane, |
| 1370 | const struct fb_plane_view_dims *dims, |
| 1371 | u32 obj_offset, u32 gtt_offset, int x, int y, |
| 1372 | struct intel_fb_view *view) |
| 1373 | { |
| 1374 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->base.dev); |
| 1375 | struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; |
| 1376 | struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; |
| 1377 | unsigned int tile_width = dims->tile_width; |
| 1378 | unsigned int tile_height = dims->tile_height; |
| 1379 | unsigned int tile_size = intel_tile_size(i915); |
| 1380 | struct drm_rect r; |
| 1381 | u32 size = 0; |
| 1382 | |
| 1383 | assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset)({ (remap_info->offset) = (obj_offset); ({ int __ret = !!( ((remap_info->offset) != (obj_offset))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&(i915)->drm))-> dev), "", "drm_WARN_ON(" "(remap_info->offset) != (obj_offset)" ")"); __builtin_expect(!!(__ret), 0); }); (remap_info->offset ); }); |
| 1384 | |
| 1385 | if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) { |
| 1386 | remap_info->linear = 1; |
| 1387 | |
| 1388 | assign_chk_ovf(i915, remap_info->size, |
| 1389 | plane_view_linear_tiles(fb, color_plane, dims, x, y)); |
| 1390 | } else { |
| 1391 | remap_info->linear = 0; |
| 1392 | |
| 1393 | assign_chk_ovf(i915, remap_info->src_stride, |
| 1394 | plane_view_src_stride_tiles(fb, color_plane, dims)); |
| 1395 | assign_chk_ovf(i915, remap_info->width, |
| 1396 | plane_view_width_tiles(fb, color_plane, dims, x)); |
| 1397 | assign_chk_ovf(i915, remap_info->height, |
| 1398 | plane_view_height_tiles(fb, color_plane, dims, y)); |
| 1399 | } |
| 1400 | |
| 1401 | if (view->gtt.type == I915_GTT_VIEW_ROTATED) { |
| 1402 | drm_WARN_ON(&i915->drm, remap_info->linear)({ int __ret = !!((remap_info->linear)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&i915->drm))-> dev), "", "drm_WARN_ON(" "remap_info->linear" ")"); __builtin_expect (!!(__ret), 0); }); |
| 1403 | check_array_bounds(i915, view->gtt.rotated.plane, color_plane)({ int __ret = !!(((color_plane) >= (sizeof((view->gtt. rotated.plane)) / sizeof((view->gtt.rotated.plane)[0])))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&( i915)->drm))->dev), "", "drm_WARN_ON(" "(color_plane) >= (sizeof((view->gtt.rotated.plane)) / sizeof((view->gtt.rotated.plane)[0]))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1404 | |
| 1405 | assign_chk_ovf(i915, remap_info->dst_stride, |
| 1406 | plane_view_dst_stride_tiles(fb, color_plane, remap_info->height)); |
| 1407 | |
| 1408 | /* rotate the x/y offsets to match the GTT view */ |
| 1409 | drm_rect_init(&r, x, y, dims->width, dims->height); |
| 1410 | drm_rect_rotate(&r, |
| 1411 | remap_info->width * tile_width, |
| 1412 | remap_info->height * tile_height, |
| 1413 | DRM_MODE_ROTATE_270(1<<3)); |
| 1414 | |
| 1415 | color_plane_info->x = r.x1; |
| 1416 | color_plane_info->y = r.y1; |
| 1417 | |
| 1418 | color_plane_info->mapping_stride = remap_info->dst_stride * tile_height; |
| 1419 | color_plane_info->scanout_stride = color_plane_info->mapping_stride; |
| 1420 | |
| 1421 | size += remap_info->dst_stride * remap_info->width; |
| 1422 | |
| 1423 | /* rotate the tile dimensions to match the GTT view */ |
| 1424 | swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) = (tile_height); (tile_height) = __tmp; } while(0); |
| 1425 | } else { |
| 1426 | drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED)({ int __ret = !!((view->gtt.type != I915_GTT_VIEW_REMAPPED )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& i915->drm))->dev), "", "drm_WARN_ON(" "view->gtt.type != I915_GTT_VIEW_REMAPPED" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1427 | |
| 1428 | check_array_bounds(i915, view->gtt.remapped.plane, color_plane)({ int __ret = !!(((color_plane) >= (sizeof((view->gtt. remapped.plane)) / sizeof((view->gtt.remapped.plane)[0]))) ); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& (i915)->drm))->dev), "", "drm_WARN_ON(" "(color_plane) >= (sizeof((view->gtt.remapped.plane)) / sizeof((view->gtt.remapped.plane)[0]))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1429 | |
| 1430 | if (view->gtt.remapped.plane_alignment) { |
| 1431 | unsigned int aligned_offset = roundup2(gtt_offset,(((gtt_offset) + ((view->gtt.remapped.plane_alignment) - 1 )) & (~((__typeof(gtt_offset))(view->gtt.remapped.plane_alignment ) - 1))) |
| 1432 | view->gtt.remapped.plane_alignment)(((gtt_offset) + ((view->gtt.remapped.plane_alignment) - 1 )) & (~((__typeof(gtt_offset))(view->gtt.remapped.plane_alignment ) - 1))); |
| 1433 | |
| 1434 | size += aligned_offset - gtt_offset; |
| 1435 | gtt_offset = aligned_offset; |
| 1436 | } |
| 1437 | |
| 1438 | color_plane_info->x = x; |
| 1439 | color_plane_info->y = y; |
| 1440 | |
| 1441 | if (remap_info->linear) { |
| 1442 | color_plane_info->mapping_stride = fb->base.pitches[color_plane]; |
| 1443 | color_plane_info->scanout_stride = color_plane_info->mapping_stride; |
| 1444 | |
| 1445 | size += remap_info->size; |
| 1446 | } else { |
| 1447 | unsigned int dst_stride; |
| 1448 | |
| 1449 | /* |
| 1450 | * The hardware automagically calculates the CCS AUX surface |
| 1451 | * stride from the main surface stride so can't really remap a |
| 1452 | * smaller subset (unless we'd remap in whole AUX page units). |
| 1453 | */ |
| 1454 | if (intel_fb_needs_pot_stride_remap(fb) && |
| 1455 | intel_fb_is_ccs_modifier(fb->base.modifier)) |
| 1456 | dst_stride = remap_info->src_stride; |
| 1457 | else |
| 1458 | dst_stride = remap_info->width; |
| 1459 | |
| 1460 | dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride); |
| 1461 | |
| 1462 | assign_chk_ovf(i915, remap_info->dst_stride, dst_stride); |
| 1463 | color_plane_info->mapping_stride = dst_stride * |
| 1464 | tile_width * |
| 1465 | fb->base.format->cpp[color_plane]; |
| 1466 | color_plane_info->scanout_stride = |
| 1467 | plane_view_scanout_stride(fb, color_plane, tile_width, |
| 1468 | remap_info->src_stride, |
| 1469 | dst_stride); |
| 1470 | |
| 1471 | size += dst_stride * remap_info->height; |
| 1472 | } |
| 1473 | } |
| 1474 | |
| 1475 | /* |
| 1476 | * We only keep the x/y offsets, so push all of the gtt offset into |
| 1477 | * the x/y offsets. x,y will hold the first pixel of the framebuffer |
| 1478 | * plane from the start of the remapped/rotated gtt mapping. |
| 1479 | */ |
| 1480 | if (remap_info->linear) |
| 1481 | intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y, |
| 1482 | fb->base.format->cpp[color_plane], |
| 1483 | color_plane_info->mapping_stride, |
| 1484 | gtt_offset * tile_size, 0); |
| 1485 | else |
| 1486 | intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y, |
| 1487 | tile_width, tile_height, |
| 1488 | tile_size, remap_info->dst_stride, |
| 1489 | gtt_offset * tile_size, 0); |
| 1490 | |
| 1491 | return size; |
| 1492 | } |
| 1493 | |
| 1494 | #undef assign_chk_ovf |
| 1495 | |
| 1496 | /* Return number of tiles @color_plane needs. */ |
| 1497 | static unsigned int |
| 1498 | calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, |
| 1499 | const struct fb_plane_view_dims *dims, |
| 1500 | int x, int y) |
| 1501 | { |
| 1502 | unsigned int tiles; |
| 1503 | |
| 1504 | if (is_surface_linear(&fb->base, color_plane)) { |
| 1505 | tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y); |
| 1506 | } else { |
| 1507 | tiles = plane_view_src_stride_tiles(fb, color_plane, dims) * |
| 1508 | plane_view_height_tiles(fb, color_plane, dims, y); |
| 1509 | /* |
| 1510 | * If the plane isn't horizontally tile aligned, |
| 1511 | * we need one more tile. |
| 1512 | */ |
| 1513 | if (x != 0) |
| 1514 | tiles++; |
| 1515 | } |
| 1516 | |
| 1517 | return tiles; |
| 1518 | } |
| 1519 | |
| 1520 | static void intel_fb_view_init(struct drm_i915_privateinteldrm_softc *i915, struct intel_fb_view *view, |
| 1521 | enum i915_gtt_view_type view_type) |
| 1522 | { |
| 1523 | memset(view, 0, sizeof(*view))__builtin_memset((view), (0), (sizeof(*view))); |
| 1524 | view->gtt.type = view_type; |
| 1525 | |
| 1526 | if (view_type == I915_GTT_VIEW_REMAPPED && |
| 1527 | (IS_ALDERLAKE_P(i915)IS_PLATFORM(i915, INTEL_ALDERLAKE_P) || DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 14)) |
| 1528 | view->gtt.remapped.plane_alignment = SZ_2M(2 << 20) / PAGE_SIZE(1 << 12); |
| 1529 | } |
| 1530 | |
| 1531 | bool_Bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) |
| 1532 | { |
| 1533 | if (DISPLAY_VER(to_i915(fb->base.dev))((&(to_i915(fb->base.dev))->__runtime)->display. ip.ver) >= 13) |
| 1534 | return false0; |
| 1535 | |
| 1536 | return fb->base.modifier == I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )) || |
| 1537 | fb->base.modifier == I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )); |
| 1538 | } |
| 1539 | |
| 1540 | int intel_fill_fb_info(struct drm_i915_privateinteldrm_softc *i915, struct intel_framebuffer *fb) |
| 1541 | { |
| 1542 | struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base)((&fb->base) ? to_intel_bo((&fb->base)->obj[ 0]) : ((void *)0)); |
| 1543 | u32 gtt_offset_rotated = 0; |
| 1544 | u32 gtt_offset_remapped = 0; |
| 1545 | unsigned int max_size = 0; |
| 1546 | int i, num_planes = fb->base.format->num_planes; |
| 1547 | unsigned int tile_size = intel_tile_size(i915); |
| 1548 | |
| 1549 | intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL); |
| 1550 | |
| 1551 | drm_WARN_ON(&i915->drm,({ int __ret = !!((intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1552 | intel_fb_supports_90_270_rotation(fb) &&({ int __ret = !!((intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1553 | intel_fb_needs_pot_stride_remap(fb))({ int __ret = !!((intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1554 | |
| 1555 | if (intel_fb_supports_90_270_rotation(fb)) |
| 1556 | intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED); |
| 1557 | if (intel_fb_needs_pot_stride_remap(fb)) |
| 1558 | intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); |
| 1559 | |
| 1560 | for (i = 0; i < num_planes; i++) { |
| 1561 | struct fb_plane_view_dims view_dims; |
| 1562 | unsigned int width, height; |
| 1563 | unsigned int cpp, size; |
| 1564 | u32 offset; |
| 1565 | int x, y; |
| 1566 | int ret; |
| 1567 | |
| 1568 | /* |
| 1569 | * Plane 2 of Render Compression with Clear Color fb modifier |
| 1570 | * is consumed by the driver and not passed to DE. Skip the |
| 1571 | * arithmetic related to alignment and offset calculation. |
| 1572 | */ |
| 1573 | if (is_gen12_ccs_cc_plane(&fb->base, i)) { |
| 1574 | if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE)(((fb->base.offsets[i]) & (((1 << 12)) - 1)) == 0 )) |
| 1575 | continue; |
| 1576 | else |
| 1577 | return -EINVAL22; |
| 1578 | } |
| 1579 | |
| 1580 | cpp = fb->base.format->cpp[i]; |
Value stored to 'cpp' is never read | |
| 1581 | intel_fb_plane_dims(fb, i, &width, &height); |
| 1582 | |
| 1583 | ret = convert_plane_offset_to_xy(fb, i, width, &x, &y); |
| 1584 | if (ret) |
| 1585 | return ret; |
| 1586 | |
| 1587 | init_plane_view_dims(fb, i, width, height, &view_dims); |
| 1588 | |
| 1589 | /* |
| 1590 | * First pixel of the framebuffer from |
| 1591 | * the start of the normal gtt mapping. |
| 1592 | */ |
| 1593 | fb->normal_view.color_plane[i].x = x; |
| 1594 | fb->normal_view.color_plane[i].y = y; |
| 1595 | fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i]; |
| 1596 | fb->normal_view.color_plane[i].scanout_stride = |
| 1597 | fb->normal_view.color_plane[i].mapping_stride; |
| 1598 | |
| 1599 | offset = calc_plane_aligned_offset(fb, i, &x, &y); |
| 1600 | |
| 1601 | if (intel_fb_supports_90_270_rotation(fb)) |
| 1602 | gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims, |
| 1603 | offset, gtt_offset_rotated, x, y, |
| 1604 | &fb->rotated_view); |
| 1605 | |
| 1606 | if (intel_fb_needs_pot_stride_remap(fb)) |
| 1607 | gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims, |
| 1608 | offset, gtt_offset_remapped, x, y, |
| 1609 | &fb->remapped_view); |
| 1610 | |
| 1611 | size = calc_plane_normal_size(fb, i, &view_dims, x, y); |
| 1612 | /* how many tiles in total needed in the bo */ |
| 1613 | max_size = max(max_size, offset + size)(((max_size)>(offset + size))?(max_size):(offset + size)); |
| 1614 | } |
| 1615 | |
| 1616 | if (mul_u32_u32(max_size, tile_size) > obj->base.size) { |
| 1617 | drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n" , mul_u32_u32(max_size, tile_size), obj->base.size) |
| 1618 | "fb too big for bo (need %llu bytes, have %zu bytes)\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n" , mul_u32_u32(max_size, tile_size), obj->base.size) |
| 1619 | mul_u32_u32(max_size, tile_size), obj->base.size)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n" , mul_u32_u32(max_size, tile_size), obj->base.size); |
| 1620 | return -EINVAL22; |
| 1621 | } |
| 1622 | |
| 1623 | return 0; |
| 1624 | } |
| 1625 | |
| 1626 | static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) |
| 1627 | { |
| 1628 | struct drm_i915_privateinteldrm_softc *i915 = |
| 1629 | to_i915(plane_state->uapi.plane->dev); |
| 1630 | struct drm_framebuffer *fb = plane_state->hw.fb; |
| 1631 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}); |
| 1632 | unsigned int rotation = plane_state->hw.rotation; |
| 1633 | int i, num_planes = fb->format->num_planes; |
| 1634 | unsigned int src_x, src_y; |
| 1635 | unsigned int src_w, src_h; |
| 1636 | u32 gtt_offset = 0; |
| 1637 | |
| 1638 | intel_fb_view_init(i915, &plane_state->view, |
| 1639 | drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED : |
| 1640 | I915_GTT_VIEW_REMAPPED); |
| 1641 | |
| 1642 | src_x = plane_state->uapi.src.x1 >> 16; |
| 1643 | src_y = plane_state->uapi.src.y1 >> 16; |
| 1644 | src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
| 1645 | src_h = drm_rect_height(&plane_state->uapi.src) >> 16; |
| 1646 | |
| 1647 | drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier))({ int __ret = !!((intel_fb_is_ccs_modifier(fb->modifier)) ); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& i915->drm))->dev), "", "drm_WARN_ON(" "intel_fb_is_ccs_modifier(fb->modifier)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1648 | |
| 1649 | /* Make src coordinates relative to the viewport */ |
| 1650 | drm_rect_translate(&plane_state->uapi.src, |
| 1651 | -(src_x << 16), -(src_y << 16)); |
| 1652 | |
| 1653 | /* Rotate src coordinates to match rotated GTT view */ |
| 1654 | if (drm_rotation_90_or_270(rotation)) |
| 1655 | drm_rect_rotate(&plane_state->uapi.src, |
| 1656 | src_w << 16, src_h << 16, |
| 1657 | DRM_MODE_ROTATE_270(1<<3)); |
| 1658 | |
| 1659 | for (i = 0; i < num_planes; i++) { |
| 1660 | unsigned int hsub = i ? fb->format->hsub : 1; |
| 1661 | unsigned int vsub = i ? fb->format->vsub : 1; |
| 1662 | struct fb_plane_view_dims view_dims; |
| 1663 | unsigned int width, height; |
| 1664 | unsigned int x, y; |
| 1665 | u32 offset; |
| 1666 | |
| 1667 | x = src_x / hsub; |
| 1668 | y = src_y / vsub; |
| 1669 | width = src_w / hsub; |
| 1670 | height = src_h / vsub; |
| 1671 | |
| 1672 | init_plane_view_dims(intel_fb, i, width, height, &view_dims); |
| 1673 | |
| 1674 | /* |
| 1675 | * First pixel of the src viewport from the |
| 1676 | * start of the normal gtt mapping. |
| 1677 | */ |
| 1678 | x += intel_fb->normal_view.color_plane[i].x; |
| 1679 | y += intel_fb->normal_view.color_plane[i].y; |
| 1680 | |
| 1681 | offset = calc_plane_aligned_offset(intel_fb, i, &x, &y); |
| 1682 | |
| 1683 | gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims, |
| 1684 | offset, gtt_offset, x, y, |
| 1685 | &plane_state->view); |
| 1686 | } |
| 1687 | } |
| 1688 | |
| 1689 | void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, |
| 1690 | struct intel_fb_view *view) |
| 1691 | { |
| 1692 | if (drm_rotation_90_or_270(rotation)) |
| 1693 | *view = fb->rotated_view; |
| 1694 | else if (intel_fb_needs_pot_stride_remap(fb)) |
| 1695 | *view = fb->remapped_view; |
| 1696 | else |
| 1697 | *view = fb->normal_view; |
| 1698 | } |
| 1699 | |
| 1700 | static |
| 1701 | u32 intel_fb_max_stride(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1702 | u32 pixel_format, u64 modifier) |
| 1703 | { |
| 1704 | /* |
| 1705 | * Arbitrary limit for gen4+ chosen to match the |
| 1706 | * render engine max stride. |
| 1707 | * |
| 1708 | * The new CCS hash mode makes remapping impossible |
| 1709 | */ |
| 1710 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 4 || intel_fb_is_ccs_modifier(modifier) || |
| 1711 | intel_modifier_uses_dpt(dev_priv, modifier)) |
| 1712 | return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); |
| 1713 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 7) |
| 1714 | return 256 * 1024; |
| 1715 | else |
| 1716 | return 128 * 1024; |
| 1717 | } |
| 1718 | |
| 1719 | static u32 |
| 1720 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) |
| 1721 | { |
| 1722 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev); |
| 1723 | u32 tile_width; |
| 1724 | |
| 1725 | if (is_surface_linear(fb, color_plane)) { |
| 1726 | u32 max_stride = intel_plane_fb_max_stride(dev_priv, |
| 1727 | fb->format->format, |
| 1728 | fb->modifier); |
| 1729 | |
| 1730 | /* |
| 1731 | * To make remapping with linear generally feasible |
| 1732 | * we need the stride to be page aligned. |
| 1733 | */ |
| 1734 | if (fb->pitches[color_plane] > max_stride && |
| 1735 | !intel_fb_is_ccs_modifier(fb->modifier)) |
| 1736 | return intel_tile_size(dev_priv); |
| 1737 | else |
| 1738 | return 64; |
| 1739 | } |
| 1740 | |
| 1741 | tile_width = intel_tile_width_bytes(fb, color_plane); |
| 1742 | if (intel_fb_is_ccs_modifier(fb->modifier)) { |
| 1743 | /* |
| 1744 | * On TGL the surface stride must be 4 tile aligned, mapped by |
| 1745 | * one 64 byte cacheline on the CCS AUX surface. |
| 1746 | */ |
| 1747 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
| 1748 | tile_width *= 4; |
| 1749 | /* |
| 1750 | * Display WA #0531: skl,bxt,kbl,glk |
| 1751 | * |
| 1752 | * Render decompression and plane width > 3840 |
| 1753 | * combined with horizontal panning requires the |
| 1754 | * plane stride to be a multiple of 4. We'll just |
| 1755 | * require the entire fb to accommodate that to avoid |
| 1756 | * potential runtime errors at plane configuration time. |
| 1757 | */ |
| 1758 | else if ((DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 9 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) && |
| 1759 | color_plane == 0 && fb->width > 3840) |
| 1760 | tile_width *= 4; |
| 1761 | } |
| 1762 | return tile_width; |
| 1763 | } |
| 1764 | |
| 1765 | static int intel_plane_check_stride(const struct intel_plane_state *plane_state) |
| 1766 | { |
| 1767 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 1768 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 1769 | unsigned int rotation = plane_state->hw.rotation; |
| 1770 | u32 stride, max_stride; |
| 1771 | |
| 1772 | /* |
| 1773 | * We ignore stride for all invisible planes that |
| 1774 | * can be remapped. Otherwise we could end up |
| 1775 | * with a false positive when the remapping didn't |
| 1776 | * kick in due the plane being invisible. |
| 1777 | */ |
| 1778 | if (intel_plane_can_remap(plane_state) && |
| 1779 | !plane_state->uapi.visible) |
| 1780 | return 0; |
| 1781 | |
| 1782 | /* FIXME other color planes? */ |
| 1783 | stride = plane_state->view.color_plane[0].mapping_stride; |
| 1784 | max_stride = plane->max_stride(plane, fb->format->format, |
| 1785 | fb->modifier, rotation); |
| 1786 | |
| 1787 | if (stride > max_stride) { |
| 1788 | DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",___drm_dbg(((void *)0), DRM_UT_KMS, "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n" , fb->base.id, stride, plane->base.base.id, plane->base .name, max_stride) |
| 1789 | fb->base.id, stride,___drm_dbg(((void *)0), DRM_UT_KMS, "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n" , fb->base.id, stride, plane->base.base.id, plane->base .name, max_stride) |
| 1790 | plane->base.base.id, plane->base.name, max_stride)___drm_dbg(((void *)0), DRM_UT_KMS, "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n" , fb->base.id, stride, plane->base.base.id, plane->base .name, max_stride); |
| 1791 | return -EINVAL22; |
| 1792 | } |
| 1793 | |
| 1794 | return 0; |
| 1795 | } |
| 1796 | |
| 1797 | int intel_plane_compute_gtt(struct intel_plane_state *plane_state) |
| 1798 | { |
| 1799 | const struct intel_framebuffer *fb = |
| 1800 | to_intel_framebuffer(plane_state->hw.fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (plane_state->hw.fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer , base) );}); |
| 1801 | unsigned int rotation = plane_state->hw.rotation; |
| 1802 | |
| 1803 | if (!fb) |
| 1804 | return 0; |
| 1805 | |
| 1806 | if (intel_plane_needs_remap(plane_state)) { |
| 1807 | intel_plane_remap_gtt(plane_state); |
| 1808 | |
| 1809 | /* |
| 1810 | * Sometimes even remapping can't overcome |
| 1811 | * the stride limitations :( Can happen with |
| 1812 | * big plane sizes and suitably misaligned |
| 1813 | * offsets. |
| 1814 | */ |
| 1815 | return intel_plane_check_stride(plane_state); |
| 1816 | } |
| 1817 | |
| 1818 | intel_fb_fill_view(fb, rotation, &plane_state->view); |
| 1819 | |
| 1820 | /* Rotate src coordinates to match rotated GTT view */ |
| 1821 | if (drm_rotation_90_or_270(rotation)) |
| 1822 | drm_rect_rotate(&plane_state->uapi.src, |
| 1823 | fb->base.width << 16, fb->base.height << 16, |
| 1824 | DRM_MODE_ROTATE_270(1<<3)); |
| 1825 | |
| 1826 | return intel_plane_check_stride(plane_state); |
| 1827 | } |
| 1828 | |
| 1829 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 1830 | { |
| 1831 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}); |
| 1832 | |
| 1833 | drm_framebuffer_cleanup(fb); |
| 1834 | |
| 1835 | if (intel_fb_uses_dpt(fb)) |
| 1836 | intel_dpt_destroy(intel_fb->dpt_vm); |
| 1837 | |
| 1838 | intel_frontbuffer_put(intel_fb->frontbuffer); |
| 1839 | |
| 1840 | kfree(intel_fb); |
| 1841 | } |
| 1842 | |
| 1843 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
| 1844 | struct drm_file *file, |
| 1845 | unsigned int *handle) |
| 1846 | { |
| 1847 | struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0)); |
| 1848 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(obj->base.dev); |
| 1849 | |
| 1850 | if (i915_gem_object_is_userptr(obj)) { |
| 1851 | drm_dbg(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_DRIVER, "attempting to use a userptr for a framebuffer, denied\n" ) |
| 1852 | "attempting to use a userptr for a framebuffer, denied\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_DRIVER, "attempting to use a userptr for a framebuffer, denied\n" ); |
| 1853 | return -EINVAL22; |
| 1854 | } |
| 1855 | |
| 1856 | return drm_gem_handle_create(file, &obj->base, handle); |
| 1857 | } |
| 1858 | |
| 1859 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
| 1860 | struct drm_file *file, |
| 1861 | unsigned int flags, unsigned int color, |
| 1862 | struct drm_clip_rect *clips, |
| 1863 | unsigned int num_clips) |
| 1864 | { |
| 1865 | struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0)); |
| 1866 | |
| 1867 | i915_gem_object_flush_if_display(obj); |
| 1868 | intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); |
| 1869 | |
| 1870 | return 0; |
| 1871 | } |
| 1872 | |
| 1873 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 1874 | .destroy = intel_user_framebuffer_destroy, |
| 1875 | .create_handle = intel_user_framebuffer_create_handle, |
| 1876 | .dirty = intel_user_framebuffer_dirty, |
| 1877 | }; |
| 1878 | |
| 1879 | int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
| 1880 | struct drm_i915_gem_object *obj, |
| 1881 | struct drm_mode_fb_cmd2 *mode_cmd) |
| 1882 | { |
| 1883 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(obj->base.dev); |
| 1884 | struct drm_framebuffer *fb = &intel_fb->base; |
| 1885 | u32 max_stride; |
| 1886 | unsigned int tiling, stride; |
| 1887 | int ret = -EINVAL22; |
| 1888 | int i; |
| 1889 | |
| 1890 | intel_fb->frontbuffer = intel_frontbuffer_get(obj); |
| 1891 | if (!intel_fb->frontbuffer) |
| 1892 | return -ENOMEM12; |
| 1893 | |
| 1894 | i915_gem_object_lock(obj, NULL((void *)0)); |
| 1895 | tiling = i915_gem_object_get_tiling(obj); |
| 1896 | stride = i915_gem_object_get_stride(obj); |
| 1897 | i915_gem_object_unlock(obj); |
| 1898 | |
| 1899 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS(1<<1)) { |
| 1900 | /* |
| 1901 | * If there's a fence, enforce that |
| 1902 | * the fb modifier and tiling mode match. |
| 1903 | */ |
| 1904 | if (tiling != I915_TILING_NONE0 && |
| 1905 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { |
| 1906 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "tiling_mode doesn't match fb modifier\n" ) |
| 1907 | "tiling_mode doesn't match fb modifier\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "tiling_mode doesn't match fb modifier\n" ); |
| 1908 | goto err; |
| 1909 | } |
| 1910 | } else { |
| 1911 | if (tiling == I915_TILING_X1) { |
| 1912 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
| 1913 | } else if (tiling == I915_TILING_Y2) { |
| 1914 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "No Y tiling for legacy addfb\n" ) |
| 1915 | "No Y tiling for legacy addfb\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "No Y tiling for legacy addfb\n" ); |
| 1916 | goto err; |
| 1917 | } |
| 1918 | } |
| 1919 | |
| 1920 | if (!drm_any_plane_has_format(&dev_priv->drm, |
| 1921 | mode_cmd->pixel_format, |
| 1922 | mode_cmd->modifier[0])) { |
| 1923 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "unsupported pixel format %p4cc / modifier 0x%llx\n" , &mode_cmd->pixel_format, mode_cmd->modifier[0]) |
| 1924 | "unsupported pixel format %p4cc / modifier 0x%llx\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "unsupported pixel format %p4cc / modifier 0x%llx\n" , &mode_cmd->pixel_format, mode_cmd->modifier[0]) |
| 1925 | &mode_cmd->pixel_format, mode_cmd->modifier[0])__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "unsupported pixel format %p4cc / modifier 0x%llx\n" , &mode_cmd->pixel_format, mode_cmd->modifier[0]); |
| 1926 | goto err; |
| 1927 | } |
| 1928 | |
| 1929 | /* |
| 1930 | * gen2/3 display engine uses the fence if present, |
| 1931 | * so the tiling mode must match the fb modifier exactly. |
| 1932 | */ |
| 1933 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 4 && |
| 1934 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { |
| 1935 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "tiling_mode must match fb modifier exactly on gen2/3\n" ) |
| 1936 | "tiling_mode must match fb modifier exactly on gen2/3\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "tiling_mode must match fb modifier exactly on gen2/3\n" ); |
| 1937 | goto err; |
| 1938 | } |
| 1939 | |
| 1940 | max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, |
| 1941 | mode_cmd->modifier[0]); |
| 1942 | if (mode_cmd->pitches[0] > max_stride) { |
| 1943 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride) |
| 1944 | "%s pitch (%u) must be at most %d\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride) |
| 1945 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride) |
| 1946 | "tiled" : "linear",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride) |
| 1947 | mode_cmd->pitches[0], max_stride)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride); |
| 1948 | goto err; |
| 1949 | } |
| 1950 | |
| 1951 | /* |
| 1952 | * If there's a fence, enforce that |
| 1953 | * the fb pitch and fence stride match. |
| 1954 | */ |
| 1955 | if (tiling != I915_TILING_NONE0 && mode_cmd->pitches[0] != stride) { |
| 1956 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "pitch (%d) must match tiling stride (%d)\n" , mode_cmd->pitches[0], stride) |
| 1957 | "pitch (%d) must match tiling stride (%d)\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "pitch (%d) must match tiling stride (%d)\n" , mode_cmd->pitches[0], stride) |
| 1958 | mode_cmd->pitches[0], stride)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "pitch (%d) must match tiling stride (%d)\n" , mode_cmd->pitches[0], stride); |
| 1959 | goto err; |
| 1960 | } |
| 1961 | |
| 1962 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
| 1963 | if (mode_cmd->offsets[0] != 0) { |
| 1964 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "plane 0 offset (0x%08x) must be 0\n" , mode_cmd->offsets[0]) |
| 1965 | "plane 0 offset (0x%08x) must be 0\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "plane 0 offset (0x%08x) must be 0\n" , mode_cmd->offsets[0]) |
| 1966 | mode_cmd->offsets[0])__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "plane 0 offset (0x%08x) must be 0\n" , mode_cmd->offsets[0]); |
| 1967 | goto err; |
| 1968 | } |
| 1969 | |
| 1970 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
| 1971 | |
| 1972 | for (i = 0; i < fb->format->num_planes; i++) { |
| 1973 | u32 stride_alignment; |
| 1974 | |
| 1975 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { |
| 1976 | drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "bad plane %d handle\n" , i) |
| 1977 | i)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "bad plane %d handle\n" , i); |
| 1978 | goto err; |
| 1979 | } |
| 1980 | |
| 1981 | stride_alignment = intel_fb_stride_alignment(fb, i); |
| 1982 | if (fb->pitches[i] & (stride_alignment - 1)) { |
| 1983 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "plane %d pitch (%d) must be at least %u byte aligned\n" , i, fb->pitches[i], stride_alignment) |
| 1984 | "plane %d pitch (%d) must be at least %u byte aligned\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "plane %d pitch (%d) must be at least %u byte aligned\n" , i, fb->pitches[i], stride_alignment) |
| 1985 | i, fb->pitches[i], stride_alignment)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "plane %d pitch (%d) must be at least %u byte aligned\n" , i, fb->pitches[i], stride_alignment); |
| 1986 | goto err; |
| 1987 | } |
| 1988 | |
| 1989 | if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) { |
| 1990 | int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); |
| 1991 | |
| 1992 | if (fb->pitches[i] != ccs_aux_stride) { |
| 1993 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "ccs aux plane %d pitch (%d) must be %d\n" , i, fb->pitches[i], ccs_aux_stride) |
| 1994 | "ccs aux plane %d pitch (%d) must be %d\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "ccs aux plane %d pitch (%d) must be %d\n" , i, fb->pitches[i], ccs_aux_stride) |
| 1995 | i,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "ccs aux plane %d pitch (%d) must be %d\n" , i, fb->pitches[i], ccs_aux_stride) |
| 1996 | fb->pitches[i], ccs_aux_stride)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "ccs aux plane %d pitch (%d) must be %d\n" , i, fb->pitches[i], ccs_aux_stride); |
| 1997 | goto err; |
| 1998 | } |
| 1999 | } |
| 2000 | |
| 2001 | fb->obj[i] = &obj->base; |
| 2002 | } |
| 2003 | |
| 2004 | ret = intel_fill_fb_info(dev_priv, intel_fb); |
| 2005 | if (ret) |
| 2006 | goto err; |
| 2007 | |
| 2008 | if (intel_fb_uses_dpt(fb)) { |
| 2009 | struct i915_address_space *vm; |
| 2010 | |
| 2011 | vm = intel_dpt_create(intel_fb); |
| 2012 | if (IS_ERR(vm)) { |
| 2013 | ret = PTR_ERR(vm); |
| 2014 | goto err; |
| 2015 | } |
| 2016 | |
| 2017 | intel_fb->dpt_vm = vm; |
| 2018 | } |
| 2019 | |
| 2020 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
| 2021 | if (ret) { |
| 2022 | drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "framebuffer init failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
| 2023 | goto err; |
| 2024 | } |
| 2025 | |
| 2026 | return 0; |
| 2027 | |
| 2028 | err: |
| 2029 | intel_frontbuffer_put(intel_fb->frontbuffer); |
| 2030 | return ret; |
| 2031 | } |
| 2032 | |
| 2033 | struct drm_framebuffer * |
| 2034 | intel_user_framebuffer_create(struct drm_device *dev, |
| 2035 | struct drm_file *filp, |
| 2036 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
| 2037 | { |
| 2038 | struct drm_framebuffer *fb; |
| 2039 | struct drm_i915_gem_object *obj; |
| 2040 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
| 2041 | struct drm_i915_privateinteldrm_softc *i915; |
| 2042 | |
| 2043 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
| 2044 | if (!obj) |
| 2045 | return ERR_PTR(-ENOENT2); |
| 2046 | |
| 2047 | /* object is backed with LMEM for discrete */ |
| 2048 | i915 = to_i915(obj->base.dev); |
| 2049 | if (HAS_LMEM(i915)((&(i915)->__runtime)->memory_regions & ((1UL << (INTEL_REGION_LMEM_0)))) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) { |
| 2050 | /* object is "remote", not in local memory */ |
| 2051 | i915_gem_object_put(obj); |
| 2052 | return ERR_PTR(-EREMOTE71); |
| 2053 | } |
| 2054 | |
| 2055 | fb = intel_framebuffer_create(obj, &mode_cmd); |
| 2056 | i915_gem_object_put(obj); |
| 2057 | |
| 2058 | return fb; |
| 2059 | } |
| 2060 | |
| 2061 | struct drm_framebuffer * |
| 2062 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
| 2063 | struct drm_mode_fb_cmd2 *mode_cmd) |
| 2064 | { |
| 2065 | struct intel_framebuffer *intel_fb; |
| 2066 | int ret; |
| 2067 | |
| 2068 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL(0x0001 | 0x0004)); |
| 2069 | if (!intel_fb) |
| 2070 | return ERR_PTR(-ENOMEM12); |
| 2071 | |
| 2072 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
| 2073 | if (ret) |
| 2074 | goto err; |
| 2075 | |
| 2076 | return &intel_fb->base; |
| 2077 | |
| 2078 | err: |
| 2079 | kfree(intel_fb); |
| 2080 | return ERR_PTR(ret); |
| 2081 | } |