/usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11

Bug Summary

File:	dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c
Warning:	line 2143, column 24 Value stored to 'adev' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name smu_v11_0.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c

1	/*
2	* Copyright 2019 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*/
22
23	#include <linux/firmware.h>
24	#include <linux/module.h>
25	#include <linux/pci.h>
26	#include <linux/reboot.h>
27
28	#define SMU_11_0_PARTIAL_PPTABLE
29	#define SWSMU_CODE_LAYER_L3
30
31	#include "amdgpu.h"
32	#include "amdgpu_smu.h"
33	#include "atomfirmware.h"
34	#include "amdgpu_atomfirmware.h"
35	#include "amdgpu_atombios.h"
36	#include "smu_v11_0.h"
37	#include "soc15_common.h"
38	#include "atom.h"
39	#include "amdgpu_ras.h"
40	#include "smu_cmn.h"
41
42	#include "asic_reg/thm/thm_11_0_2_offset.h"
43	#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44	#include "asic_reg/mp/mp_11_0_offset.h"
45	#include "asic_reg/mp/mp_11_0_sh_mask.h"
46	#include "asic_reg/smuio/smuio_11_0_0_offset.h"
47	#include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48
49	/*
50	* DO NOT use these for err/warn/info/debug messages.
51	* Use dev_err, dev_warn, dev_info and dev_dbg instead.
52	* They are more MGPU friendly.
53	*/
54	#undef pr_err
55	#undef pr_warn
56	#undef pr_info
57	#undef pr_debug
58
59	MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60	MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61	MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62	MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63	MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64	MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65	MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
66	MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
67
68	#define SMU11_VOLTAGE_SCALE4 4
69
70	#define SMU11_MODE1_RESET_WAIT_TIME_IN_MS500 500 //500ms
71
72	#define smnPCIE_LC_LINK_WIDTH_CNTL0x11140288 0x11140288
73	#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK0x00000070L 0x00000070L
74	#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT0x4 0x4
75	#define smnPCIE_LC_SPEED_CNTL0x11140290 0x11140290
76	#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK0xC000 0xC000
77	#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT0xE 0xE
78
79	#define mmTHM_BACO_CNTL_ARCT0xA7 0xA7
80	#define mmTHM_BACO_CNTL_ARCT_BASE_IDX0 0
81
82	int smu_v11_0_init_microcode(struct smu_context *smu)
83	{
84	struct amdgpu_device *adev = smu->adev;
85	const char *chip_name;
86	char fw_name[SMU_FW_NAME_LEN0x24];
87	int err = 0;
88	const struct smc_firmware_header_v1_0 *hdr;
89	const struct common_firmware_header *header;
90	struct amdgpu_firmware_info ucode = NULL((void )0);
91
92	if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) &&
93	((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)(((11) << 16) \| ((0) << 8) \| (9))) \|\|
94	(adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)(((11) << 16) \| ((0) << 8) \| (7)))))
95	return 0;
96
97	switch (adev->ip_versions[MP1_HWIP][0]) {
98	case IP_VERSION(11, 0, 0)(((11) << 16) \| ((0) << 8) \| (0)):
99	chip_name = "navi10";
100	break;
101	case IP_VERSION(11, 0, 5)(((11) << 16) \| ((0) << 8) \| (5)):
102	chip_name = "navi14";
103	break;
104	case IP_VERSION(11, 0, 9)(((11) << 16) \| ((0) << 8) \| (9)):
105	chip_name = "navi12";
106	break;
107	case IP_VERSION(11, 0, 7)(((11) << 16) \| ((0) << 8) \| (7)):
108	chip_name = "sienna_cichlid";
109	break;
110	case IP_VERSION(11, 0, 11)(((11) << 16) \| ((0) << 8) \| (11)):
111	chip_name = "navy_flounder";
112	break;
113	case IP_VERSION(11, 0, 12)(((11) << 16) \| ((0) << 8) \| (12)):
114	chip_name = "dimgrey_cavefish";
115	break;
116	case IP_VERSION(11, 0, 13)(((11) << 16) \| ((0) << 8) \| (13)):
117	chip_name = "beige_goby";
118	break;
119	case IP_VERSION(11, 0, 2)(((11) << 16) \| ((0) << 8) \| (2)):
120	chip_name = "arcturus";
121	break;
122	default:
123	dev_err(adev->dev, "Unsupported IP version 0x%x\n",printf("drm:pid%d:%s ERROR " "Unsupported IP version 0x%x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_versions[MP1_HWIP][0])
124	adev->ip_versions[MP1_HWIP][0])printf("drm:pid%d:%s ERROR " "Unsupported IP version 0x%x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_versions[MP1_HWIP][0]);
125	return -EINVAL22;
126	}
127
128	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
129
130	err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
131	if (err)
132	goto out;
133	err = amdgpu_ucode_validate(adev->pm.fw);
134	if (err)
135	goto out;
136
137	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
138	amdgpu_ucode_print_smc_hdr(&hdr->header);
139	adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version));
140
141	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
142	ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
143	ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
144	ucode->fw = adev->pm.fw;
145	header = (const struct common_firmware_header *)ucode->fw->data;
146	adev->firmware.fw_size +=
147	roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1)));
148	}
149
150	out:
151	if (err) {
152	DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",__drm_err("smu_v11_0: Failed to load firmware \"%s\"\n", fw_name )
153	fw_name)__drm_err("smu_v11_0: Failed to load firmware \"%s\"\n", fw_name );
154	release_firmware(adev->pm.fw);
155	adev->pm.fw = NULL((void *)0);
156	}
157	return err;
158	}
159
160	void smu_v11_0_fini_microcode(struct smu_context *smu)
161	{
162	struct amdgpu_device *adev = smu->adev;
163
164	release_firmware(adev->pm.fw);
165	adev->pm.fw = NULL((void *)0);
166	adev->pm.fw_version = 0;
167	}
168
169	int smu_v11_0_load_microcode(struct smu_context *smu)
170	{
171	struct amdgpu_device *adev = smu->adev;
172	const uint32_t *src;
173	const struct smc_firmware_header_v1_0 *hdr;
174	uint32_t addr_start = MP1_SRAM0x03c00004;
175	uint32_t i;
176	uint32_t smc_fw_size;
177	uint32_t mp1_fw_flags;
178
179	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
180	src = (const uint32_t *)(adev->pm.fw->data +
181	le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)));
182	smc_fw_size = hdr->header.ucode_size_bytes;
183
184	for (i = 1; i < smc_fw_size/4 - 1; i++) {
185	WREG32_PCIE(addr_start, src[i])adev->pcie_wreg(adev, (addr_start), (src[i]));
186	addr_start += 4;
187	}
188
189	WREG32_PCIE(MP1_Public \| (smnMP1_PUB_CTRL & 0xffffffff),adev->pcie_wreg(adev, (0x03b00000 \| (0x3010b14 & 0xffffffff )), (1 & 0x00000001L))
190	1 & MP1_SMN_PUB_CTRL__RESET_MASK)adev->pcie_wreg(adev, (0x03b00000 \| (0x3010b14 & 0xffffffff )), (1 & 0x00000001L));
191	WREG32_PCIE(MP1_Public \| (smnMP1_PUB_CTRL & 0xffffffff),adev->pcie_wreg(adev, (0x03b00000 \| (0x3010b14 & 0xffffffff )), (1 & ~0x00000001L))
192	1 & ~MP1_SMN_PUB_CTRL__RESET_MASK)adev->pcie_wreg(adev, (0x03b00000 \| (0x3010b14 & 0xffffffff )), (1 & ~0x00000001L));
193
194	for (i = 0; i < adev->usec_timeout; i++) {
195	mp1_fw_flags = RREG32_PCIE(MP1_Public \|adev->pcie_rreg(adev, (0x03b00000 \| (0x3010024 & 0xffffffff )))
196	(smnMP1_FIRMWARE_FLAGS & 0xffffffff))adev->pcie_rreg(adev, (0x03b00000 \| (0x3010024 & 0xffffffff )));
197	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK0x00000001L) >>
198	MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT0x0)
199	break;
200	udelay(1);
201	}
202
203	if (i == adev->usec_timeout)
204	return -ETIME60;
205
206	return 0;
207	}
208
209	int smu_v11_0_check_fw_status(struct smu_context *smu)
210	{
211	struct amdgpu_device *adev = smu->adev;
212	uint32_t mp1_fw_flags;
213
214	mp1_fw_flags = RREG32_PCIE(MP1_Public \|adev->pcie_rreg(adev, (0x03b00000 \| (0x3010024 & 0xffffffff )))
215	(smnMP1_FIRMWARE_FLAGS & 0xffffffff))adev->pcie_rreg(adev, (0x03b00000 \| (0x3010024 & 0xffffffff )));
216
217	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK0x00000001L) >>
218	MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT0x0)
219	return 0;
220
221	return -EIO5;
222	}
223
224	int smu_v11_0_check_fw_version(struct smu_context *smu)
225	{
226	struct amdgpu_device *adev = smu->adev;
227	uint32_t if_version = 0xff, smu_version = 0xff;
228	uint8_t smu_program, smu_major, smu_minor, smu_debug;
229	int ret = 0;
230
231	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
232	if (ret)
233	return ret;
234
235	smu_program = (smu_version >> 24) & 0xff;
236	smu_major = (smu_version >> 16) & 0xff;
237	smu_minor = (smu_version >> 8) & 0xff;
238	smu_debug = (smu_version >> 0) & 0xff;
239	if (smu->is_apu)
240	adev->pm.fw_version = smu_version;
241
242	switch (adev->ip_versions[MP1_HWIP][0]) {
243	case IP_VERSION(11, 0, 0)(((11) << 16) \| ((0) << 8) \| (0)):
244	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV100x37;
245	break;
246	case IP_VERSION(11, 0, 9)(((11) << 16) \| ((0) << 8) \| (9)):
247	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV120x38;
248	break;
249	case IP_VERSION(11, 0, 5)(((11) << 16) \| ((0) << 8) \| (5)):
250	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV140x38;
251	break;
252	case IP_VERSION(11, 0, 7)(((11) << 16) \| ((0) << 8) \| (7)):
253	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid0x40;
254	break;
255	case IP_VERSION(11, 0, 11)(((11) << 16) \| ((0) << 8) \| (11)):
256	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder0xE;
257	break;
258	case IP_VERSION(11, 5, 0)(((11) << 16) \| ((5) << 8) \| (0)):
259	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH0x03;
260	break;
261	case IP_VERSION(11, 0, 12)(((11) << 16) \| ((0) << 8) \| (12)):
262	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish0xF;
263	break;
264	case IP_VERSION(11, 0, 13)(((11) << 16) \| ((0) << 8) \| (13)):
265	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby0xD;
266	break;
267	case IP_VERSION(11, 0, 8)(((11) << 16) \| ((0) << 8) \| (8)):
268	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish0x8;
269	break;
270	case IP_VERSION(11, 0, 2)(((11) << 16) \| ((0) << 8) \| (2)):
271	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT0x17;
272	break;
273	default:
274	dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",printf("drm:pid%d:%s ERROR " "smu unsupported IP version: 0x%x.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_versions[MP1_HWIP][0])
275	adev->ip_versions[MP1_HWIP][0])printf("drm:pid%d:%s ERROR " "smu unsupported IP version: 0x%x.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_versions[MP1_HWIP][0]);
276	smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV0xFFFFFFFF;
277	break;
278	}
279
280	/*
281	* 1. if_version mismatch is not critical as our fw is designed
282	* to be backward compatible.
283	* 2. New fw usually brings some optimizations. But that's visible
284	* only on the paired driver.
285	* Considering above, we just leave user a warning message instead
286	* of halt driver loading.
287	*/
288	if (if_version != smu->smc_driver_if_version) {
289	dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "do { } while(0)
290	"smu fw program = %d, version = 0x%08x (%d.%d.%d)\n",do { } while(0)
291	smu->smc_driver_if_version, if_version,do { } while(0)
292	smu_program, smu_version, smu_major, smu_minor, smu_debug)do { } while(0);
293	dev_warn(smu->adev->dev, "SMU driver if version not matched\n")printf("drm:pid%d:%s WARNING " "SMU driver if version not matched\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
294	}
295
296	return ret;
297	}
298
299	static int smu_v11_0_set_pptable_v2_0(struct smu_context smu, void table, uint32_t size)
300	{
301	struct amdgpu_device *adev = smu->adev;
302	uint32_t ppt_offset_bytes;
303	const struct smc_firmware_header_v2_0 *v2;
304
305	v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
306
307	ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes)((__uint32_t)(v2->ppt_offset_bytes));
308	*size = le32_to_cpu(v2->ppt_size_bytes)((__uint32_t)(v2->ppt_size_bytes));
309	table = (uint8_t )v2 + ppt_offset_bytes;
310
311	return 0;
312	}
313
314	static int smu_v11_0_set_pptable_v2_1(struct smu_context smu, void *table,
315	uint32_t *size, uint32_t pptable_id)
316	{
317	struct amdgpu_device *adev = smu->adev;
318	const struct smc_firmware_header_v2_1 *v2_1;
319	struct smc_soft_pptable_entry *entries;
320	uint32_t pptable_count = 0;
321	int i = 0;
322
323	v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
324	entries = (struct smc_soft_pptable_entry *)
325	((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)((__uint32_t)(v2_1->pptable_entry_offset)));
326	pptable_count = le32_to_cpu(v2_1->pptable_count)((__uint32_t)(v2_1->pptable_count));
327	for (i = 0; i < pptable_count; i++) {
328	if (le32_to_cpu(entries[i].id)((__uint32_t)(entries[i].id)) == pptable_id) {
329	table = ((uint8_t )v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)((__uint32_t)(entries[i].ppt_offset_bytes)));
330	*size = le32_to_cpu(entries[i].ppt_size_bytes)((__uint32_t)(entries[i].ppt_size_bytes));
331	break;
332	}
333	}
334
335	if (i == pptable_count)
336	return -EINVAL22;
337
338	return 0;
339	}
340
341	int smu_v11_0_setup_pptable(struct smu_context *smu)
342	{
343	struct amdgpu_device *adev = smu->adev;
344	const struct smc_firmware_header_v1_0 *hdr;
345	int ret, index;
346	uint32_t size = 0;
347	uint16_t atom_table_size;
348	uint8_t frev, crev;
349	void *table;
350	uint16_t version_major, version_minor;
351
352	if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
353	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
354	version_major = le16_to_cpu(hdr->header.header_version_major)((__uint16_t)(hdr->header.header_version_major));
355	version_minor = le16_to_cpu(hdr->header.header_version_minor)((__uint16_t)(hdr->header.header_version_minor));
356	if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
357	dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id)do { } while(0);
358	switch (version_minor) {
359	case 0:
360	ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
361	break;
362	case 1:
363	ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
364	smu->smu_table.boot_values.pp_table_id);
365	break;
366	default:
367	ret = -EINVAL22;
368	break;
369	}
370	if (ret)
371	return ret;
372	goto out;
373	}
374	}
375
376	dev_info(adev->dev, "use vbios provided pptable\n")do { } while(0);
377	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , powerplayinfo) / sizeof(uint16_t))
378	powerplayinfo)(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , powerplayinfo) / sizeof(uint16_t));
379
380	ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
381	(uint8_t **)&table);
382	if (ret)
383	return ret;
384	size = atom_table_size;
385
386	out:
387	if (!smu->smu_table.power_play_table)
388	smu->smu_table.power_play_table = table;
389	if (!smu->smu_table.power_play_table_size)
390	smu->smu_table.power_play_table_size = size;
391
392	return 0;
393	}
394
395	int smu_v11_0_init_smc_tables(struct smu_context *smu)
396	{
397	struct smu_table_context *smu_table = &smu->smu_table;
398	struct smu_table *tables = smu_table->tables;
399	int ret = 0;
400
401	smu_table->driver_pptable =
402	kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL(0x0001 \| 0x0004));
403	if (!smu_table->driver_pptable) {
404	ret = -ENOMEM12;
405	goto err0_out;
406	}
407
408	smu_table->max_sustainable_clocks =
409	kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL(0x0001 \| 0x0004));
410	if (!smu_table->max_sustainable_clocks) {
411	ret = -ENOMEM12;
412	goto err1_out;
413	}
414
415	/* Arcturus does not support OVERDRIVE */
416	if (tables[SMU_TABLE_OVERDRIVE].size) {
417	smu_table->overdrive_table =
418	kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL(0x0001 \| 0x0004));
419	if (!smu_table->overdrive_table) {
420	ret = -ENOMEM12;
421	goto err2_out;
422	}
423
424	smu_table->boot_overdrive_table =
425	kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL(0x0001 \| 0x0004));
426	if (!smu_table->boot_overdrive_table) {
427	ret = -ENOMEM12;
428	goto err3_out;
429	}
430
431	smu_table->user_overdrive_table =
432	kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL(0x0001 \| 0x0004));
433	if (!smu_table->user_overdrive_table) {
434	ret = -ENOMEM12;
435	goto err4_out;
436	}
437
438	}
439
440	return 0;
441
442	err4_out:
443	kfree(smu_table->boot_overdrive_table);
444	err3_out:
445	kfree(smu_table->overdrive_table);
446	err2_out:
447	kfree(smu_table->max_sustainable_clocks);
448	err1_out:
449	kfree(smu_table->driver_pptable);
450	err0_out:
451	return ret;
452	}
453
454	int smu_v11_0_fini_smc_tables(struct smu_context *smu)
455	{
456	struct smu_table_context *smu_table = &smu->smu_table;
457	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
458
459	kfree(smu_table->gpu_metrics_table);
460	kfree(smu_table->user_overdrive_table);
461	kfree(smu_table->boot_overdrive_table);
462	kfree(smu_table->overdrive_table);
463	kfree(smu_table->max_sustainable_clocks);
464	kfree(smu_table->driver_pptable);
465	kfree(smu_table->clocks_table);
466	smu_table->gpu_metrics_table = NULL((void *)0);
467	smu_table->user_overdrive_table = NULL((void *)0);
468	smu_table->boot_overdrive_table = NULL((void *)0);
469	smu_table->overdrive_table = NULL((void *)0);
470	smu_table->max_sustainable_clocks = NULL((void *)0);
471	smu_table->driver_pptable = NULL((void *)0);
472	smu_table->clocks_table = NULL((void *)0);
473	kfree(smu_table->hardcode_pptable);
474	smu_table->hardcode_pptable = NULL((void *)0);
475
476	kfree(smu_table->driver_smu_config_table);
477	kfree(smu_table->ecc_table);
478	kfree(smu_table->metrics_table);
479	kfree(smu_table->watermarks_table);
480	smu_table->driver_smu_config_table = NULL((void *)0);
481	smu_table->ecc_table = NULL((void *)0);
482	smu_table->metrics_table = NULL((void *)0);
483	smu_table->watermarks_table = NULL((void *)0);
484	smu_table->metrics_time = 0;
485
486	kfree(smu_dpm->dpm_context);
487	kfree(smu_dpm->golden_dpm_context);
488	kfree(smu_dpm->dpm_current_power_state);
489	kfree(smu_dpm->dpm_request_power_state);
490	smu_dpm->dpm_context = NULL((void *)0);
491	smu_dpm->golden_dpm_context = NULL((void *)0);
492	smu_dpm->dpm_context_size = 0;
493	smu_dpm->dpm_current_power_state = NULL((void *)0);
494	smu_dpm->dpm_request_power_state = NULL((void *)0);
495
496	return 0;
497	}
498
499	int smu_v11_0_init_power(struct smu_context *smu)
500	{
501	struct amdgpu_device *adev = smu->adev;
502	struct smu_power_context *smu_power = &smu->smu_power;
503	size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)(((11) << 16) \| ((5) << 8) \| (0)) ?
504	sizeof(struct smu_11_5_power_context) :
505	sizeof(struct smu_11_0_power_context);
506
507	smu_power->power_context = kzalloc(size, GFP_KERNEL(0x0001 \| 0x0004));
508	if (!smu_power->power_context)
509	return -ENOMEM12;
510	smu_power->power_context_size = size;
511
512	return 0;
513	}
514
515	int smu_v11_0_fini_power(struct smu_context *smu)
516	{
517	struct smu_power_context *smu_power = &smu->smu_power;
518
519	kfree(smu_power->power_context);
520	smu_power->power_context = NULL((void *)0);
521	smu_power->power_context_size = 0;
522
523	return 0;
524	}
525
526	static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
527	uint8_t clk_id,
528	uint8_t syspll_id,
529	uint32_t *clk_freq)
530	{
531	struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
532	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
533	int ret, index;
534
535	input.clk_id = clk_id;
536	input.syspll_id = syspll_id;
537	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
538	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,(__builtin_offsetof(struct atom_master_list_of_command_functions_v2_1 , getsmuclockinfo) / sizeof(uint16_t))
539	getsmuclockinfo)(__builtin_offsetof(struct atom_master_list_of_command_functions_v2_1 , getsmuclockinfo) / sizeof(uint16_t));
540
541	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
542	(uint32_t *)&input);
543	if (ret)
544	return -EINVAL22;
545
546	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
547	*clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz)((__uint32_t)(output->atom_smu_outputclkfreq.smu_clock_freq_hz )) / 10000;
548
549	return 0;
550	}
551
552	int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
553	{
554	int ret, index;
555	uint16_t size;
556	uint8_t frev, crev;
557	struct atom_common_table_header *header;
558	struct atom_firmware_info_v3_3 *v_3_3;
559	struct atom_firmware_info_v3_1 *v_3_1;
560
561	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , firmwareinfo) / sizeof(uint16_t))
562	firmwareinfo)(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , firmwareinfo) / sizeof(uint16_t));
563
564	ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
565	(uint8_t **)&header);
566	if (ret)
567	return ret;
568
569	if (header->format_revision != 3) {
570	dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n")printf("drm:pid%d:%s ERROR " "unknown atom_firmware_info version! for smu11\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
571	return -EINVAL22;
572	}
573
574	switch (header->content_revision) {
575	case 0:
576	case 1:
577	case 2:
578	v_3_1 = (struct atom_firmware_info_v3_1 *)header;
579	smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
580	smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
581	smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
582	smu->smu_table.boot_values.socclk = 0;
583	smu->smu_table.boot_values.dcefclk = 0;
584	smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
585	smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
586	smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
587	smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
588	smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
589	smu->smu_table.boot_values.pp_table_id = 0;
590	smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
591	break;
592	case 3:
593	case 4:
594	default:
595	v_3_3 = (struct atom_firmware_info_v3_3 *)header;
596	smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
597	smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
598	smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
599	smu->smu_table.boot_values.socclk = 0;
600	smu->smu_table.boot_values.dcefclk = 0;
601	smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
602	smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
603	smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
604	smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
605	smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
606	smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
607	smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
608	}
609
610	smu->smu_table.boot_values.format_revision = header->format_revision;
611	smu->smu_table.boot_values.content_revision = header->content_revision;
612
613	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
614	(uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
615	(uint8_t)0,
616	&smu->smu_table.boot_values.socclk);
617
618	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
619	(uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
620	(uint8_t)0,
621	&smu->smu_table.boot_values.dcefclk);
622
623	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
624	(uint8_t)SMU11_SYSPLL0_ECLK_ID,
625	(uint8_t)0,
626	&smu->smu_table.boot_values.eclk);
627
628	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
629	(uint8_t)SMU11_SYSPLL0_VCLK_ID,
630	(uint8_t)0,
631	&smu->smu_table.boot_values.vclk);
632
633	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
634	(uint8_t)SMU11_SYSPLL0_DCLK_ID,
635	(uint8_t)0,
636	&smu->smu_table.boot_values.dclk);
637
638	if ((smu->smu_table.boot_values.format_revision == 3) &&
639	(smu->smu_table.boot_values.content_revision >= 2))
640	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
641	(uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
642	(uint8_t)SMU11_SYSPLL1_2_ID,
643	&smu->smu_table.boot_values.fclk);
644
645	smu_v11_0_atom_get_smu_clockinfo(smu->adev,
646	(uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
647	(uint8_t)SMU11_SYSPLL3_1_ID,
648	&smu->smu_table.boot_values.lclk);
649
650	return 0;
651	}
652
653	int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
654	{
655	struct smu_table_context *smu_table = &smu->smu_table;
656	struct smu_table *memory_pool = &smu_table->memory_pool;
657	int ret = 0;
658	uint64_t address;
659	uint32_t address_low, address_high;
660
661	if (memory_pool->size == 0 \|\| memory_pool->cpu_addr == NULL((void *)0))
662	return ret;
663
664	address = (uintptr_t)memory_pool->cpu_addr;
665	address_high = (uint32_t)upper_32_bits(address)((u32)(((address) >> 16) >> 16));
666	address_low = (uint32_t)lower_32_bits(address)((u32)(address));
667
668	ret = smu_cmn_send_smc_msg_with_param(smu,
669	SMU_MSG_SetSystemVirtualDramAddrHigh,
670	address_high,
671	NULL((void *)0));
672	if (ret)
673	return ret;
674	ret = smu_cmn_send_smc_msg_with_param(smu,
675	SMU_MSG_SetSystemVirtualDramAddrLow,
676	address_low,
677	NULL((void *)0));
678	if (ret)
679	return ret;
680
681	address = memory_pool->mc_address;
682	address_high = (uint32_t)upper_32_bits(address)((u32)(((address) >> 16) >> 16));
683	address_low = (uint32_t)lower_32_bits(address)((u32)(address));
684
685	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
686	address_high, NULL((void *)0));
687	if (ret)
688	return ret;
689	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
690	address_low, NULL((void *)0));
691	if (ret)
692	return ret;
693	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
694	(uint32_t)memory_pool->size, NULL((void *)0));
695	if (ret)
696	return ret;
697
698	return ret;
699	}
700
701	int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
702	{
703	int ret;
704
705	ret = smu_cmn_send_smc_msg_with_param(smu,
706	SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL((void *)0));
707	if (ret)
708	dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!")printf("drm:pid%d:%s ERROR " "SMU11 attempt to set divider for DCEFCLK Failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
709
710	return ret;
711	}
712
713	int smu_v11_0_set_driver_table_location(struct smu_context *smu)
714	{
715	struct smu_table *driver_table = &smu->smu_table.driver_table;
716	int ret = 0;
717
718	if (driver_table->mc_address) {
719	ret = smu_cmn_send_smc_msg_with_param(smu,
720	SMU_MSG_SetDriverDramAddrHigh,
721	upper_32_bits(driver_table->mc_address)((u32)(((driver_table->mc_address) >> 16) >> 16 )),
722	NULL((void *)0));
723	if (!ret)
724	ret = smu_cmn_send_smc_msg_with_param(smu,
725	SMU_MSG_SetDriverDramAddrLow,
726	lower_32_bits(driver_table->mc_address)((u32)(driver_table->mc_address)),
727	NULL((void *)0));
728	}
729
730	return ret;
731	}
732
733	int smu_v11_0_set_tool_table_location(struct smu_context *smu)
734	{
735	int ret = 0;
736	struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
737
738	if (tool_table->mc_address) {
739	ret = smu_cmn_send_smc_msg_with_param(smu,
740	SMU_MSG_SetToolsDramAddrHigh,
741	upper_32_bits(tool_table->mc_address)((u32)(((tool_table->mc_address) >> 16) >> 16) ),
742	NULL((void *)0));
743	if (!ret)
744	ret = smu_cmn_send_smc_msg_with_param(smu,
745	SMU_MSG_SetToolsDramAddrLow,
746	lower_32_bits(tool_table->mc_address)((u32)(tool_table->mc_address)),
747	NULL((void *)0));
748	}
749
750	return ret;
751	}
752
753	int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
754	{
755	struct amdgpu_device *adev = smu->adev;
756
757	/* Navy_Flounder/Dimgrey_Cavefish do not support to change
758	* display num currently
759	*/
760	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)(((11) << 16) \| ((0) << 8) \| (11)) \|\|
761	adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0)(((11) << 16) \| ((5) << 8) \| (0)) \|\|
762	adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12)(((11) << 16) \| ((0) << 8) \| (12)) \|\|
763	adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)(((11) << 16) \| ((0) << 8) \| (13)))
764	return 0;
765
766	return smu_cmn_send_smc_msg_with_param(smu,
767	SMU_MSG_NumOfDisplays,
768	count,
769	NULL((void *)0));
770	}
771
772
773	int smu_v11_0_set_allowed_mask(struct smu_context *smu)
774	{
775	struct smu_feature *feature = &smu->smu_feature;
776	int ret = 0;
777	uint32_t feature_mask[2];
778
779	if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX)(find_first_bit(feature->allowed, (64)) == (64)) \|\| feature->feature_num < 64) {
780	ret = -EINVAL22;
781	goto failed;
782	}
783
784	bitmap_to_arr32(feature_mask, feature->allowed, 64);
785
786	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
787	feature_mask[1], NULL((void *)0));
788	if (ret)
789	goto failed;
790
791	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
792	feature_mask[0], NULL((void *)0));
793	if (ret)
794	goto failed;
795
796	failed:
797	return ret;
798	}
799
800	int smu_v11_0_system_features_control(struct smu_context *smu,
801	bool_Bool en)
802	{
803	return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
804	SMU_MSG_DisableAllSmuFeatures), NULL((void *)0));
805	}
806
807	int smu_v11_0_notify_display_change(struct smu_context *smu)
808	{
809	int ret = 0;
810
811	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
812	smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM6)
813	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL((void *)0));
814
815	return ret;
816	}
817
818	static int
819	smu_v11_0_get_max_sustainable_clock(struct smu_context smu, uint32_t clock,
820	enum smu_clk_type clock_select)
821	{
822	int ret = 0;
823	int clk_id;
824
825	if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) \|\|
826	(smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
827	return 0;
828
829	clk_id = smu_cmn_to_asic_specific_index(smu,
830	CMN2ASIC_MAPPING_CLK,
831	clock_select);
832	if (clk_id < 0)
833	return -EINVAL22;
834
835	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
836	clk_id << 16, clock);
837	if (ret) {
838	dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!")printf("drm:pid%d:%s ERROR " "[GetMaxSustainableClock] Failed to get max DC clock from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
839	return ret;
840	}
841
842	if (*clock != 0)
843	return 0;
844
845	/* if DC limit is zero, return AC limit */
846	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
847	clk_id << 16, clock);
848	if (ret) {
849	dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!")printf("drm:pid%d:%s ERROR " "[GetMaxSustainableClock] failed to get max AC clock from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
850	return ret;
851	}
852
853	return 0;
854	}
855
856	int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
857	{
858	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
859	smu->smu_table.max_sustainable_clocks;
860	int ret = 0;
861
862	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
863	max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
864	max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
865	max_sustainable_clocks->display_clock = 0xFFFFFFFF;
866	max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
867	max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
868
869	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
870	ret = smu_v11_0_get_max_sustainable_clock(smu,
871	&(max_sustainable_clocks->uclock),
872	SMU_UCLK);
873	if (ret) {
874	dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",printf("drm:pid%d:%s ERROR " "[%s] failed to get max UCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ )
875	__func__)printf("drm:pid%d:%s ERROR " "[%s] failed to get max UCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
876	return ret;
877	}
878	}
879
880	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
881	ret = smu_v11_0_get_max_sustainable_clock(smu,
882	&(max_sustainable_clocks->soc_clock),
883	SMU_SOCCLK);
884	if (ret) {
885	dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",printf("drm:pid%d:%s ERROR " "[%s] failed to get max SOCCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ )
886	__func__)printf("drm:pid%d:%s ERROR " "[%s] failed to get max SOCCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
887	return ret;
888	}
889	}
890
891	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
892	ret = smu_v11_0_get_max_sustainable_clock(smu,
893	&(max_sustainable_clocks->dcef_clock),
894	SMU_DCEFCLK);
895	if (ret) {
896	dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",printf("drm:pid%d:%s ERROR " "[%s] failed to get max DCEFCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ )
897	__func__)printf("drm:pid%d:%s ERROR " "[%s] failed to get max DCEFCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
898	return ret;
899	}
900
901	ret = smu_v11_0_get_max_sustainable_clock(smu,
902	&(max_sustainable_clocks->display_clock),
903	SMU_DISPCLK);
904	if (ret) {
905	dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",printf("drm:pid%d:%s ERROR " "[%s] failed to get max DISPCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ )
906	__func__)printf("drm:pid%d:%s ERROR " "[%s] failed to get max DISPCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
907	return ret;
908	}
909	ret = smu_v11_0_get_max_sustainable_clock(smu,
910	&(max_sustainable_clocks->phy_clock),
911	SMU_PHYCLK);
912	if (ret) {
913	dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",printf("drm:pid%d:%s ERROR " "[%s] failed to get max PHYCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ )
914	__func__)printf("drm:pid%d:%s ERROR " "[%s] failed to get max PHYCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
915	return ret;
916	}
917	ret = smu_v11_0_get_max_sustainable_clock(smu,
918	&(max_sustainable_clocks->pixel_clock),
919	SMU_PIXCLK);
920	if (ret) {
921	dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",printf("drm:pid%d:%s ERROR " "[%s] failed to get max PIXCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ )
922	__func__)printf("drm:pid%d:%s ERROR " "[%s] failed to get max PIXCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
923	return ret;
924	}
925	}
926
927	if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
928	max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
929
930	return 0;
931	}
932
933	int smu_v11_0_get_current_power_limit(struct smu_context *smu,
934	uint32_t *power_limit)
935	{
936	int power_src;
937	int ret = 0;
938
939	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
940	return -EINVAL22;
941
942	power_src = smu_cmn_to_asic_specific_index(smu,
943	CMN2ASIC_MAPPING_PWR,
944	smu->adev->pm.ac_power ?
945	SMU_POWER_SOURCE_AC :
946	SMU_POWER_SOURCE_DC);
947	if (power_src < 0)
948	return -EINVAL22;
949
950	/*
951	* BIT 24-31: ControllerId (only PPT0 is supported for now)
952	* BIT 16-23: PowerSource
953	*/
954	ret = smu_cmn_send_smc_msg_with_param(smu,
955	SMU_MSG_GetPptLimit,
956	(0 << 24) \| (power_src << 16),
957	power_limit);
958	if (ret)
959	dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__)printf("drm:pid%d:%s ERROR " "[%s] get PPT limit failed!", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
960
961	return ret;
962	}
963
964	int smu_v11_0_set_power_limit(struct smu_context *smu,
965	enum smu_ppt_limit_type limit_type,
966	uint32_t limit)
967	{
968	int power_src;
969	int ret = 0;
970	uint32_t limit_param;
971
972	if (limit_type != SMU_DEFAULT_PPT_LIMIT)
973	return -EINVAL22;
974
975	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
976	dev_err(smu->adev->dev, "Setting new power limit is not supported!\n")printf("drm:pid%d:%s ERROR " "Setting new power limit is not supported!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
977	return -EOPNOTSUPP45;
978	}
979
980	power_src = smu_cmn_to_asic_specific_index(smu,
981	CMN2ASIC_MAPPING_PWR,
982	smu->adev->pm.ac_power ?
983	SMU_POWER_SOURCE_AC :
984	SMU_POWER_SOURCE_DC);
985	if (power_src < 0)
986	return -EINVAL22;
987
988	/*
989	* BIT 24-31: ControllerId (only PPT0 is supported for now)
990	* BIT 16-23: PowerSource
991	* BIT 0-15: PowerLimit
992	*/
993	limit_param = (limit & 0xFFFF);
994	limit_param \|= 0 << 24;
995	limit_param \|= (power_src) << 16;
996	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL((void *)0));
997	if (ret) {
998	dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__)printf("drm:pid%d:%s ERROR " "[%s] Set power limit Failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
999	return ret;
1000	}
1001
1002	smu->current_power_limit = limit;
1003
1004	return 0;
1005	}
1006
1007	static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
1008	{
1009	return smu_cmn_send_smc_msg(smu,
1010	SMU_MSG_ReenableAcDcInterrupt,
1011	NULL((void *)0));
1012	}
1013
1014	static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
1015	{
1016	int ret = 0;
1017
1018	if (smu->dc_controlled_by_gpio &&
1019	smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1020	ret = smu_v11_0_ack_ac_dc_interrupt(smu);
1021
1022	return ret;
1023	}
1024
1025	void smu_v11_0_interrupt_work(struct smu_context *smu)
1026	{
1027	if (smu_v11_0_ack_ac_dc_interrupt(smu))
1028	dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n")printf("drm:pid%d:%s ERROR " "Ack AC/DC interrupt Failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
1029	}
1030
1031	int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1032	{
1033	int ret = 0;
1034
1035	if (smu->smu_table.thermal_controller_type) {
1036	ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1037	if (ret)
1038	return ret;
1039	}
1040
1041	/*
1042	* After init there might have been missed interrupts triggered
1043	* before driver registers for interrupt (Ex. AC/DC).
1044	*/
1045	return smu_v11_0_process_pending_interrupt(smu);
1046	}
1047
1048	int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1049	{
1050	return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1051	}
1052
1053	static uint16_t convert_to_vddc(uint8_t vid)
1054	{
1055	return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE4);
1056	}
1057
1058	int smu_v11_0_get_gfx_vdd(struct smu_context smu, uint32_t value)
1059	{
1060	struct amdgpu_device *adev = smu->adev;
1061	uint32_t vdd = 0, val_vid = 0;
1062
1063	if (!value)
1064	return -EINVAL22;
1065	val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0 ][0] + 0x0004, 0, SMUIO_HWIP) : amdgpu_device_rreg(adev, (adev ->reg_offset[SMUIO_HWIP][0][0] + 0x0004), 0)) &
1066	SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK0x01FF0000L) >>
1067	SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT0x10;
1068
1069	vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1070
1071	*value = vdd;
1072
1073	return 0;
1074
1075	}
1076
1077	int
1078	smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1079	struct pp_display_clock_request
1080	*clock_req)
1081	{
1082	enum amd_pp_clock_type clk_type = clock_req->clock_type;
1083	int ret = 0;
1084	enum smu_clk_type clk_select = 0;
1085	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1086
1087	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) \|\|
1088	smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1089	switch (clk_type) {
1090	case amd_pp_dcef_clock:
1091	clk_select = SMU_DCEFCLK;
1092	break;
1093	case amd_pp_disp_clock:
1094	clk_select = SMU_DISPCLK;
1095	break;
1096	case amd_pp_pixel_clock:
1097	clk_select = SMU_PIXCLK;
1098	break;
1099	case amd_pp_phy_clock:
1100	clk_select = SMU_PHYCLK;
1101	break;
1102	case amd_pp_mem_clock:
1103	clk_select = SMU_UCLK;
1104	break;
1105	default:
1106	dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__)do { } while(0);
1107	ret = -EINVAL22;
1108	break;
1109	}
1110
1111	if (ret)
1112	goto failed;
1113
1114	if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1115	return 0;
1116
1117	ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1118
1119	if(clk_select == SMU_UCLK)
1120	smu->hard_min_uclk_req_from_dal = clk_freq;
1121	}
1122
1123	failed:
1124	return ret;
1125	}
1126
1127	int smu_v11_0_gfx_off_control(struct smu_context *smu, bool_Bool enable)
1128	{
1129	int ret = 0;
1130	struct amdgpu_device *adev = smu->adev;
1131
1132	switch (adev->ip_versions[MP1_HWIP][0]) {
1133	case IP_VERSION(11, 0, 0)(((11) << 16) \| ((0) << 8) \| (0)):
1134	case IP_VERSION(11, 0, 5)(((11) << 16) \| ((0) << 8) \| (5)):
1135	case IP_VERSION(11, 0, 9)(((11) << 16) \| ((0) << 8) \| (9)):
1136	case IP_VERSION(11, 0, 7)(((11) << 16) \| ((0) << 8) \| (7)):
1137	case IP_VERSION(11, 0, 11)(((11) << 16) \| ((0) << 8) \| (11)):
1138	case IP_VERSION(11, 0, 12)(((11) << 16) \| ((0) << 8) \| (12)):
1139	case IP_VERSION(11, 0, 13)(((11) << 16) \| ((0) << 8) \| (13)):
1140	case IP_VERSION(11, 5, 0)(((11) << 16) \| ((5) << 8) \| (0)):
1141	if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1142	return 0;
1143	if (enable)
1144	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL((void *)0));
1145	else
1146	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL((void *)0));
1147	break;
1148	default:
1149	break;
1150	}
1151
1152	return ret;
1153	}
1154
1155	uint32_t
1156	smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1157	{
1158	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1159	return AMD_FAN_CTRL_AUTO;
1160	else
1161	return smu->user_dpm_profile.fan_mode;
1162	}
1163
1164	static int
1165	smu_v11_0_auto_fan_control(struct smu_context *smu, bool_Bool auto_fan_control)
1166	{
1167	int ret = 0;
1168
1169	if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1170	return 0;
1171
1172	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1173	if (ret)
1174	dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",printf("drm:pid%d:%s ERROR " "[%s]%s smc FAN CONTROL feature failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ , (auto_fan_control ? "Start" : "Stop"))
1175	__func__, (auto_fan_control ? "Start" : "Stop"))printf("drm:pid%d:%s ERROR " "[%s]%s smc FAN CONTROL feature failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ , (auto_fan_control ? "Start" : "Stop"));
1176
1177	return ret;
1178	}
1179
1180	static int
1181	smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1182	{
1183	struct amdgpu_device *adev = smu->adev;
1184
1185	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0069), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x000000FFL) \| (0x000000FFL & ((0) << 0x0))), 0, THM_HWIP ) : amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][ 0][0] + 0x0069)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx .rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x000000FFL) \| (0x000000FFL & ((0) << 0x0)))), 0) )
1186	REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0069), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x000000FFL) \| (0x000000FFL & ((0) << 0x0))), 0, THM_HWIP ) : amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][ 0][0] + 0x0069)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx .rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x000000FFL) \| (0x000000FFL & ((0) << 0x0)))), 0) )
1187	CG_FDO_CTRL2, TMIN, 0))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0069), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x000000FFL) \| (0x000000FFL & ((0) << 0x0))), 0, THM_HWIP ) : amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][ 0][0] + 0x0069)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx .rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x000000FFL) \| (0x000000FFL & ((0) << 0x0)))), 0) );
1188	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0069), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x00003800L) \| (0x00003800L & ((mode) << 0xb))), 0 , THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[ THM_HWIP][0][0] + 0x0069)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x0069), 0))) & ~0x00003800L) \| (0x00003800L & ((mode) << 0xb)))), 0))
1189	REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0069), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x00003800L) \| (0x00003800L & ((mode) << 0xb))), 0 , THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[ THM_HWIP][0][0] + 0x0069)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x0069), 0))) & ~0x00003800L) \| (0x00003800L & ((mode) << 0xb)))), 0))
1190	CG_FDO_CTRL2, FDO_PWM_MODE, mode))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0069), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0069), 0))) & ~0x00003800L) \| (0x00003800L & ((mode) << 0xb))), 0 , THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[ THM_HWIP][0][0] + 0x0069)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x0069, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x0069), 0))) & ~0x00003800L) \| (0x00003800L & ((mode) << 0xb)))), 0));
1191
1192	return 0;
1193	}
1194
1195	int
1196	smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed)
1197	{
1198	struct amdgpu_device *adev = smu->adev;
1199	uint32_t duty100, duty;
1200	uint64_t tmp64;
1201
1202	speed = MIN(speed, 255)(((speed)<(255))?(speed):(255));
1203
1204	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x0068, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x0068), 0))) & 0x000000FFL) >> 0x0)
1205	CG_FDO_CTRL1, FMAX_DUTY100)(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x0068, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x0068), 0))) & 0x000000FFL) >> 0x0);
1206	if (!duty100)
1207	return -EINVAL22;
1208
1209	tmp64 = (uint64_t)speed * duty100;
1210	do_div(tmp64, 255)({ uint32_t __base = (255); uint32_t __rem = ((uint64_t)(tmp64 )) % __base; (tmp64) = ((uint64_t)(tmp64)) / __base; __rem; } );
1211	duty = (uint32_t)tmp64;
1212
1213	WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0067), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0067, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0067), 0))) & ~0x000000FFL) \| (0x000000FFL & ((duty) << 0x0))), 0 , THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[ THM_HWIP][0][0] + 0x0067)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x0067, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x0067), 0))) & ~0x000000FFL) \| (0x000000FFL & ((duty) << 0x0)))), 0))
1214	REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0067), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0067, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0067), 0))) & ~0x000000FFL) \| (0x000000FFL & ((duty) << 0x0))), 0 , THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[ THM_HWIP][0][0] + 0x0067)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x0067, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x0067), 0))) & ~0x000000FFL) \| (0x000000FFL & ((duty) << 0x0)))), 0))
1215	CG_FDO_CTRL0, FDO_STATIC_DUTY, duty))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0067), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x0067, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0067), 0))) & ~0x000000FFL) \| (0x000000FFL & ((duty) << 0x0))), 0 , THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[ THM_HWIP][0][0] + 0x0067)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x0067, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x0067), 0))) & ~0x000000FFL) \| (0x000000FFL & ((duty) << 0x0)))), 0));
1216
1217	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC1);
1218	}
1219
1220	int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1221	uint32_t speed)
1222	{
1223	struct amdgpu_device *adev = smu->adev;
1224	/*
1225	* crystal_clock_freq used for fan speed rpm calculation is
1226	* always 25Mhz. So, hardcode it as 2500(in 10K unit).
1227	*/
1228	uint32_t crystal_clock_freq = 2500;
1229	uint32_t tach_period;
1230
1231	if (speed == 0)
1232	return -EINVAL22;
1233	/*
1234	* To prevent from possible overheat, some ASICs may have requirement
1235	* for minimum fan speed:
1236	* - For some NV10 SKU, the fan speed cannot be set lower than
1237	* 700 RPM.
1238	* - For some Sienna Cichlid SKU, the fan speed cannot be set
1239	* lower than 500 RPM.
1240	*/
1241	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1242	WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x006a), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x006a, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x006a), 0))) & ~0xFFFFFFF8L) \| (0xFFFFFFF8L & ((tach_period) << 0x3 ))), 0, THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [THM_HWIP][0][0] + 0x006a)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x006a, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x006a), 0))) & ~0xFFFFFFF8L) \| (0xFFFFFFF8L & ((tach_period) << 0x3)))), 0))
1243	REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x006a), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x006a, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x006a), 0))) & ~0xFFFFFFF8L) \| (0xFFFFFFF8L & ((tach_period) << 0x3 ))), 0, THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [THM_HWIP][0][0] + 0x006a)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x006a, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x006a), 0))) & ~0xFFFFFFF8L) \| (0xFFFFFFF8L & ((tach_period) << 0x3)))), 0))
1244	CG_TACH_CTRL, TARGET_PERIOD,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x006a), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x006a, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x006a), 0))) & ~0xFFFFFFF8L) \| (0xFFFFFFF8L & ((tach_period) << 0x3 ))), 0, THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [THM_HWIP][0][0] + 0x006a)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x006a, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x006a), 0))) & ~0xFFFFFFF8L) \| (0xFFFFFFF8L & ((tach_period) << 0x3)))), 0))
1245	tach_period))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x006a), (((((((adev)->virt.caps & (1 << 2 )) && adev->gfx.rlc.funcs && adev->gfx. rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev ->reg_offset[THM_HWIP][0][0] + 0x006a, 0, THM_HWIP) : amdgpu_device_rreg (adev, (adev->reg_offset[THM_HWIP][0][0] + 0x006a), 0))) & ~0xFFFFFFF8L) \| (0xFFFFFFF8L & ((tach_period) << 0x3 ))), 0, THM_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset [THM_HWIP][0][0] + 0x006a)), ((((((((adev)->virt.caps & (1 << 2)) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg (adev, adev->reg_offset[THM_HWIP][0][0] + 0x006a, 0, THM_HWIP ) : amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0 ][0] + 0x006a), 0))) & ~0xFFFFFFF8L) \| (0xFFFFFFF8L & ((tach_period) << 0x3)))), 0));
1246
1247	return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM5);
1248	}
1249
1250	int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
1251	uint32_t *speed)
1252	{
1253	struct amdgpu_device *adev = smu->adev;
1254	uint32_t duty100, duty;
1255	uint64_t tmp64;
1256
1257	/*
1258	* For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1259	* detected via register retrieving. To workaround this, we will
1260	* report the fan speed as 0 PWM if user just requested such.
1261	*/
1262	if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM(1 << 2))
1263	&& !smu->user_dpm_profile.fan_speed_pwm) {
1264	*speed = 0;
1265	return 0;
1266	}
1267
1268	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x0068, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x0068), 0))) & 0x000000FFL) >> 0x0)
1269	CG_FDO_CTRL1, FMAX_DUTY100)(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x0068, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x0068), 0))) & 0x000000FFL) >> 0x0);
1270	duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x006C, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x006C), 0))) & 0x0001FE00L) >> 0x9)
1271	CG_THERMAL_STATUS, FDO_PWM_DUTY)(((((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x006C, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x006C), 0))) & 0x0001FE00L) >> 0x9);
1272	if (!duty100)
1273	return -EINVAL22;
1274
1275	tmp64 = (uint64_t)duty * 255;
1276	do_div(tmp64, duty100)({ uint32_t __base = (duty100); uint32_t __rem = ((uint64_t)( tmp64)) % __base; (tmp64) = ((uint64_t)(tmp64)) / __base; __rem ; });
1277	*speed = MIN((uint32_t)tmp64, 255)((((uint32_t)tmp64)<(255))?((uint32_t)tmp64):(255));
1278
1279	return 0;
1280	}
1281
1282	int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1283	uint32_t *speed)
1284	{
1285	struct amdgpu_device *adev = smu->adev;
1286	uint32_t crystal_clock_freq = 2500;
1287	uint32_t tach_status;
1288	uint64_t tmp64;
1289
1290	/*
1291	* For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1292	* detected via register retrieving. To workaround this, we will
1293	* report the fan speed as 0 RPM if user just requested such.
1294	*/
1295	if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM(1 << 1))
1296	&& !smu->user_dpm_profile.fan_speed_rpm) {
1297	*speed = 0;
1298	return 0;
1299	}
1300
1301	tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1302
1303	tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x006b, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x006b), 0));
1304	if (tach_status) {
1305	do_div(tmp64, tach_status)({ uint32_t __base = (tach_status); uint32_t __rem = ((uint64_t )(tmp64)) % __base; (tmp64) = ((uint64_t)(tmp64)) / __base; __rem ; });
1306	*speed = (uint32_t)tmp64;
1307	} else {
1308	dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n")printf("drm:pid%d:%s WARNING " "Got zero output on CG_TACH_STATUS reading!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
1309	*speed = 0;
1310	}
1311
1312	return 0;
1313	}
1314
1315	int
1316	smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1317	uint32_t mode)
1318	{
1319	int ret = 0;
1320
1321	switch (mode) {
1322	case AMD_FAN_CTRL_NONE:
1323	ret = smu_v11_0_auto_fan_control(smu, 0);
1324	if (!ret)
1325	ret = smu_v11_0_set_fan_speed_pwm(smu, 255);
1326	break;
1327	case AMD_FAN_CTRL_MANUAL:
1328	ret = smu_v11_0_auto_fan_control(smu, 0);
1329	break;
1330	case AMD_FAN_CTRL_AUTO:
1331	ret = smu_v11_0_auto_fan_control(smu, 1);
1332	break;
1333	default:
1334	break;
1335	}
1336
1337	if (ret) {
1338	dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__)printf("drm:pid%d:%s ERROR " "[%s]Set fan control mode failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
1339	return -EINVAL22;
1340	}
1341
1342	return ret;
1343	}
1344
1345	int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1346	uint32_t pstate)
1347	{
1348	return smu_cmn_send_smc_msg_with_param(smu,
1349	SMU_MSG_SetXgmiMode,
1350	pstate ? XGMI_MODE_PSTATE_D01 : XGMI_MODE_PSTATE_D30,
1351	NULL((void *)0));
1352	}
1353
1354	static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1355	struct amdgpu_irq_src *source,
1356	unsigned tyep,
1357	enum amdgpu_interrupt_state state)
1358	{
1359	struct smu_context *smu = adev->powerplay.pp_handle;
1360	uint32_t low, high;
1361	uint32_t val = 0;
1362
1363	switch (state) {
1364	case AMDGPU_IRQ_STATE_DISABLE:
1365	/* For THM irqs */
1366	val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x000b, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x000b), 0));
1367	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1)(((val) & ~0x01000000L) \| (0x01000000L & ((1) << 0x18)));
1368	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1)(((val) & ~0x02000000L) \| (0x02000000L & ((1) << 0x19)));
1369	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x000b), val, 0, THM_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[THM_HWIP][0][0] + 0x000b)), (val), 0));
1370
1371	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x000a), 0, 0, THM_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[THM_HWIP][0][0] + 0x000a)), (0), 0));
1372
1373	/* For MP1 SW irqs */
1374	val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[MP1_HWIP][0][ 0] + 0x02c3, 0, MP1_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[MP1_HWIP][0][0] + 0x02c3), 0));
1375	val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1)(((val) & ~0x00000001L) \| (0x00000001L & ((1) << 0x0)));
1376	WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[MP1_HWIP][0] [0] + 0x02c3), val, 0, MP1_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[MP1_HWIP][0][0] + 0x02c3)), (val), 0));
1377
1378	break;
1379	case AMDGPU_IRQ_STATE_ENABLE:
1380	/* For THM irqs */
1381	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,(((0)>(smu->thermal_range.min / 1000))?(0):(smu->thermal_range .min / 1000))
1382	smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES)(((0)>(smu->thermal_range.min / 1000))?(0):(smu->thermal_range .min / 1000));
1383	high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,(((255)<(smu->thermal_range.software_shutdown_temp))?(255 ):(smu->thermal_range.software_shutdown_temp))
1384	smu->thermal_range.software_shutdown_temp)(((255)<(smu->thermal_range.software_shutdown_temp))?(255 ):(smu->thermal_range.software_shutdown_temp));
1385
1386	val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x000b, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x000b), 0));
1387	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5)(((val) & ~0xE0000000L) \| (0xE0000000L & ((5) << 0x1d)));
1388	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1)(((val) & ~0x10000000L) \| (0x10000000L & ((1) << 0x1c)));
1389	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0)(((val) & ~0x01000000L) \| (0x01000000L & ((0) << 0x18)));
1390	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0)(((val) & ~0x02000000L) \| (0x02000000L & ((0) << 0x19)));
1391	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff))(((val) & ~0x000000FFL) \| (0x000000FFL & (((high & 0xff)) << 0x0)));
1392	val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff))(((val) & ~0x0000FF00L) \| (0x0000FF00L & (((low & 0xff)) << 0x8)));
1393	val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK0x04000000L);
1394	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x000b), val, 0, THM_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[THM_HWIP][0][0] + 0x000b)), (val), 0));
1395
1396	val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT0x3);
1397	val \|= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT0x4);
1398	val \|= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT0x5);
1399	WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x000a), val, 0, THM_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[THM_HWIP][0][0] + 0x000a)), (val), 0));
1400
1401	/* For MP1 SW irqs */
1402	val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[MP1_HWIP][0][ 0] + 0x02c2, 0, MP1_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[MP1_HWIP][0][0] + 0x02c2), 0));
1403	val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE)(((val) & ~0x000000FFL) \| (0x000000FFL & ((0xFE) << 0x0)));
1404	val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0)(((val) & ~0x00000100L) \| (0x00000100L & ((0) << 0x8)));
1405	WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[MP1_HWIP][0] [0] + 0x02c2), val, 0, MP1_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[MP1_HWIP][0][0] + 0x02c2)), (val), 0));
1406
1407	val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[MP1_HWIP][0][ 0] + 0x02c3, 0, MP1_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[MP1_HWIP][0][0] + 0x02c3), 0));
1408	val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0)(((val) & ~0x00000001L) \| (0x00000001L & ((0) << 0x0)));
1409	WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[MP1_HWIP][0] [0] + 0x02c3), val, 0, MP1_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[MP1_HWIP][0][0] + 0x02c3)), (val), 0));
1410
1411	break;
1412	default:
1413	break;
1414	}
1415
1416	return 0;
1417	}
1418
1419	#define THM_11_0__SRCID__THM_DIG_THERM_L2H0 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1420	#define THM_11_0__SRCID__THM_DIG_THERM_H2L1 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1421
1422	#define SMUIO_11_0__SRCID__SMUIO_GPIO1983 83
1423
1424	static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1425	struct amdgpu_irq_src *source,
1426	struct amdgpu_iv_entry *entry)
1427	{
1428	struct smu_context *smu = adev->powerplay.pp_handle;
1429	uint32_t client_id = entry->client_id;
1430	uint32_t src_id = entry->src_id;
1431	/*
1432	* ctxid is used to distinguish different
1433	* events for SMCToHost interrupt.
1434	*/
1435	uint32_t ctxid = entry->src_data[0];
1436	uint32_t data;
1437
1438	if (client_id == SOC15_IH_CLIENTID_THM) {
1439	switch (src_id) {
1440	case THM_11_0__SRCID__THM_DIG_THERM_L2H0:
1441	schedule_delayed_work(&smu->swctf_delayed_work,
1442	msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY)(((uint64_t)(50)) * hz / 1000));
1443	break;
1444	case THM_11_0__SRCID__THM_DIG_THERM_H2L1:
1445	dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n")printf("drm:pid%d:%s EMERGENCY " "ERROR: GPU under temperature range detected\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
1446	break;
1447	default:
1448	dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",printf("drm:pid%d:%s EMERGENCY " "ERROR: GPU under temperature range unknown src id (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , src_id )
1449	src_id)printf("drm:pid%d:%s EMERGENCY " "ERROR: GPU under temperature range unknown src id (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , src_id );
1450	break;
1451	}
1452	} else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1453	dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n")printf("drm:pid%d:%s EMERGENCY " "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
1454	/*
1455	* HW CTF just occurred. Shutdown to prevent further damage.
1456	*/
1457	dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n")printf("drm:pid%d:%s EMERGENCY " "ERROR: System is going to shutdown due to GPU HW CTF!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
1458	orderly_poweroff(true1);
1459	} else if (client_id == SOC15_IH_CLIENTID_MP1) {
1460	if (src_id == 0xfe) {
1461	/* ACK SMUToHost interrupt */
1462	data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[MP1_HWIP][0][ 0] + 0x02c3, 0, MP1_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[MP1_HWIP][0][0] + 0x02c3), 0));
1463	data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1)(((data) & ~0x00000100L) \| (0x00000100L & ((1) << 0x8)));
1464	WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[MP1_HWIP][0] [0] + 0x02c3), data, 0, MP1_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[MP1_HWIP][0][0] + 0x02c3)), (data), 0));
1465
1466	switch (ctxid) {
1467	case 0x3:
1468	dev_dbg(adev->dev, "Switched to AC mode!\n")do { } while(0);
1469	schedule_work(&smu->interrupt_work);
1470	break;
1471	case 0x4:
1472	dev_dbg(adev->dev, "Switched to DC mode!\n")do { } while(0);
1473	schedule_work(&smu->interrupt_work);
1474	break;
1475	case 0x7:
1476	/*
1477	* Increment the throttle interrupt counter
1478	*/
1479	atomic64_inc(&smu->throttle_int_counter)__sync_fetch_and_add_8(&smu->throttle_int_counter, 1);
1480
1481	if (!atomic_read(&adev->throttling_logging_enabled)({ typeof((&adev->throttling_logging_enabled)) __tmp = (volatile typeof((&adev->throttling_logging_enabled )) )&(*(&adev->throttling_logging_enabled)); membar_datadep_consumer (); __tmp; }))
1482	return 0;
1483
1484	if (__ratelimit(&adev->throttling_logging_rs))
1485	schedule_work(&smu->throttling_logging_work);
1486
1487	break;
1488	}
1489	}
1490	}
1491
1492	return 0;
1493	}
1494
1495	static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1496	{
1497	.set = smu_v11_0_set_irq_state,
1498	.process = smu_v11_0_irq_process,
1499	};
1500
1501	int smu_v11_0_register_irq_handler(struct smu_context *smu)
1502	{
1503	struct amdgpu_device *adev = smu->adev;
1504	struct amdgpu_irq_src *irq_src = &smu->irq_source;
1505	int ret = 0;
1506
1507	irq_src->num_types = 1;
1508	irq_src->funcs = &smu_v11_0_irq_funcs;
1509
1510	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1511	THM_11_0__SRCID__THM_DIG_THERM_L2H0,
1512	irq_src);
1513	if (ret)
1514	return ret;
1515
1516	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1517	THM_11_0__SRCID__THM_DIG_THERM_H2L1,
1518	irq_src);
1519	if (ret)
1520	return ret;
1521
1522	/* Register CTF(GPIO_19) interrupt */
1523	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1524	SMUIO_11_0__SRCID__SMUIO_GPIO1983,
1525	irq_src);
1526	if (ret)
1527	return ret;
1528
1529	ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1530	0xfe,
1531	irq_src);
1532	if (ret)
1533	return ret;
1534
1535	return ret;
1536	}
1537
1538	int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1539	struct pp_smu_nv_clock_table *max_clocks)
1540	{
1541	struct smu_table_context *table_context = &smu->smu_table;
1542	struct smu_11_0_max_sustainable_clocks sustainable_clocks = NULL((void )0);
1543
1544	if (!max_clocks \|\| !table_context->max_sustainable_clocks)
1545	return -EINVAL22;
1546
1547	sustainable_clocks = table_context->max_sustainable_clocks;
1548
1549	max_clocks->dcfClockInKhz =
1550	(unsigned int) sustainable_clocks->dcef_clock * 1000;
1551	max_clocks->displayClockInKhz =
1552	(unsigned int) sustainable_clocks->display_clock * 1000;
1553	max_clocks->phyClockInKhz =
1554	(unsigned int) sustainable_clocks->phy_clock * 1000;
1555	max_clocks->pixelClockInKhz =
1556	(unsigned int) sustainable_clocks->pixel_clock * 1000;
1557	max_clocks->uClockInKhz =
1558	(unsigned int) sustainable_clocks->uclock * 1000;
1559	max_clocks->socClockInKhz =
1560	(unsigned int) sustainable_clocks->soc_clock * 1000;
1561	max_clocks->dscClockInKhz = 0;
1562	max_clocks->dppClockInKhz = 0;
1563	max_clocks->fabricClockInKhz = 0;
1564
1565	return 0;
1566	}
1567
1568	int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1569	{
1570	return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL((void *)0));
1571	}
1572
1573	int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
1574	enum smu_baco_seq baco_seq)
1575	{
1576	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL((void *)0));
1577	}
1578
1579	bool_Bool smu_v11_0_baco_is_support(struct smu_context *smu)
1580	{
1581	struct smu_baco_context *smu_baco = &smu->smu_baco;
1582
1583	if (amdgpu_sriov_vf(smu->adev)((smu->adev)->virt.caps & (1 << 2)) \|\| !smu_baco->platform_support)
1584	return false0;
1585
1586	/* return true if ASIC is in BACO state already */
1587	if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1588	return true1;
1589
1590	/* Arcturus does not support this bit mask */
1591	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1592	!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1593	return false0;
1594
1595	return true1;
1596	}
1597
1598	enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1599	{
1600	struct smu_baco_context *smu_baco = &smu->smu_baco;
1601
1602	return smu_baco->state;
1603	}
1604
1605	#define D3HOT_BACO_SEQUENCE0 0
1606	#define D3HOT_BAMACO_SEQUENCE2 2
1607
1608	int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1609	{
1610	struct smu_baco_context *smu_baco = &smu->smu_baco;
1611	struct amdgpu_device *adev = smu->adev;
1612	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1613	uint32_t data;
1614	int ret = 0;
1615
1616	if (smu_v11_0_baco_get_state(smu) == state)
1617	return 0;
1618
1619	if (state == SMU_BACO_STATE_ENTER) {
1620	switch (adev->ip_versions[MP1_HWIP][0]) {
1621	case IP_VERSION(11, 0, 7)(((11) << 16) \| ((0) << 8) \| (7)):
1622	case IP_VERSION(11, 0, 11)(((11) << 16) \| ((0) << 8) \| (11)):
1623	case IP_VERSION(11, 0, 12)(((11) << 16) \| ((0) << 8) \| (12)):
1624	case IP_VERSION(11, 0, 13)(((11) << 16) \| ((0) << 8) \| (13)):
1625	if (amdgpu_runtime_pm == 2)
1626	ret = smu_cmn_send_smc_msg_with_param(smu,
1627	SMU_MSG_EnterBaco,
1628	D3HOT_BAMACO_SEQUENCE2,
1629	NULL((void *)0));
1630	else
1631	ret = smu_cmn_send_smc_msg_with_param(smu,
1632	SMU_MSG_EnterBaco,
1633	D3HOT_BACO_SEQUENCE0,
1634	NULL((void *)0));
1635	break;
1636	default:
1637	if (!ras \|\| !adev->ras_enabled \|\|
1638	adev->gmc.xgmi.pending_reset) {
1639	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)(((11) << 16) \| ((0) << 8) \| (2))) {
1640	data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0xA7, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0xA7), 0));
1641	data \|= 0x80000000;
1642	WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0xA7), data, 0, THM_HWIP) : amdgpu_device_wreg(adev, (( adev->reg_offset[THM_HWIP][0][0] + 0xA7)), (data), 0));
1643	} else {
1644	data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[THM_HWIP][0][ 0] + 0x0081, 0, THM_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[THM_HWIP][0][0] + 0x0081), 0));
1645	data \|= 0x80000000;
1646	WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0081), data, 0, THM_HWIP) : amdgpu_device_wreg(adev, ( (adev->reg_offset[THM_HWIP][0][0] + 0x0081)), (data), 0));
1647	}
1648
1649	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL((void *)0));
1650	} else {
1651	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL((void *)0));
1652	}
1653	break;
1654	}
1655
1656	} else {
1657	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL((void *)0));
1658	if (ret)
1659	return ret;
1660
1661	/* clear vbios scratch 6 and 7 for coming asic reinit */
1662	WREG32(adev->bios_scratch_reg_offset + 6, 0)amdgpu_device_wreg(adev, (adev->bios_scratch_reg_offset + 6 ), (0), 0);
1663	WREG32(adev->bios_scratch_reg_offset + 7, 0)amdgpu_device_wreg(adev, (adev->bios_scratch_reg_offset + 7 ), (0), 0);
1664	}
1665
1666	if (!ret)
1667	smu_baco->state = state;
1668
1669	return ret;
1670	}
1671
1672	int smu_v11_0_baco_enter(struct smu_context *smu)
1673	{
1674	int ret = 0;
1675
1676	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1677	if (ret)
1678	return ret;
1679
1680	drm_msleep(10)mdelay(10);
1681
1682	return ret;
1683	}
1684
1685	int smu_v11_0_baco_exit(struct smu_context *smu)
1686	{
1687	return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1688	}
1689
1690	int smu_v11_0_mode1_reset(struct smu_context *smu)
1691	{
1692	int ret = 0;
1693
1694	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL((void *)0));
1695	if (!ret)
1696	drm_msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS)mdelay(500);
1697
1698	return ret;
1699	}
1700
1701	int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool_Bool enable)
1702	{
1703	int ret = 0;
1704
1705	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL((void *)0));
1706
1707	return ret;
1708	}
1709
1710
1711	int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1712	uint32_t min, uint32_t max)
1713	{
1714	int ret = 0, clk_id = 0;
1715	uint32_t param = 0;
1716	uint32_t clock_limit;
1717
1718	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1719	switch (clk_type) {
1720	case SMU_MCLK:
1721	case SMU_UCLK:
1722	clock_limit = smu->smu_table.boot_values.uclk;
1723	break;
1724	case SMU_GFXCLK:
1725	case SMU_SCLK:
1726	clock_limit = smu->smu_table.boot_values.gfxclk;
1727	break;
1728	case SMU_SOCCLK:
1729	clock_limit = smu->smu_table.boot_values.socclk;
1730	break;
1731	default:
1732	clock_limit = 0;
1733	break;
1734	}
1735
1736	/* clock in Mhz unit */
1737	if (min)
1738	*min = clock_limit / 100;
1739	if (max)
1740	*max = clock_limit / 100;
1741
1742	return 0;
1743	}
1744
1745	clk_id = smu_cmn_to_asic_specific_index(smu,
1746	CMN2ASIC_MAPPING_CLK,
1747	clk_type);
1748	if (clk_id < 0) {
1749	ret = -EINVAL22;
1750	goto failed;
1751	}
1752	param = (clk_id & 0xffff) << 16;
1753
1754	if (max) {
1755	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1756	if (ret)
1757	goto failed;
1758	}
1759
1760	if (min) {
1761	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1762	if (ret)
1763	goto failed;
1764	}
1765
1766	failed:
1767	return ret;
1768	}
1769
1770	int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1771	enum smu_clk_type clk_type,
1772	uint32_t min,
1773	uint32_t max)
1774	{
1775	int ret = 0, clk_id = 0;
1776	uint32_t param;
1777
1778	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1779	return 0;
1780
1781	clk_id = smu_cmn_to_asic_specific_index(smu,
1782	CMN2ASIC_MAPPING_CLK,
1783	clk_type);
1784	if (clk_id < 0)
1785	return clk_id;
1786
1787	if (max > 0) {
1788	param = (uint32_t)((clk_id << 16) \| (max & 0xffff));
1789	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1790	param, NULL((void *)0));
1791	if (ret)
1792	goto out;
1793	}
1794
1795	if (min > 0) {
1796	param = (uint32_t)((clk_id << 16) \| (min & 0xffff));
1797	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1798	param, NULL((void *)0));
1799	if (ret)
1800	goto out;
1801	}
1802
1803	out:
1804	return ret;
1805	}
1806
1807	int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1808	enum smu_clk_type clk_type,
1809	uint32_t min,
1810	uint32_t max)
1811	{
1812	int ret = 0, clk_id = 0;
1813	uint32_t param;
1814
1815	if (min <= 0 && max <= 0)
1816	return -EINVAL22;
1817
1818	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1819	return 0;
1820
1821	clk_id = smu_cmn_to_asic_specific_index(smu,
1822	CMN2ASIC_MAPPING_CLK,
1823	clk_type);
1824	if (clk_id < 0)
1825	return clk_id;
1826
1827	if (max > 0) {
1828	param = (uint32_t)((clk_id << 16) \| (max & 0xffff));
1829	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1830	param, NULL((void *)0));
1831	if (ret)
1832	return ret;
1833	}
1834
1835	if (min > 0) {
1836	param = (uint32_t)((clk_id << 16) \| (min & 0xffff));
1837	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1838	param, NULL((void *)0));
1839	if (ret)
1840	return ret;
1841	}
1842
1843	return ret;
1844	}
1845
1846	int smu_v11_0_set_performance_level(struct smu_context *smu,
1847	enum amd_dpm_forced_level level)
1848	{
1849	struct smu_11_0_dpm_context *dpm_context =
1850	smu->smu_dpm.dpm_context;
1851	struct smu_11_0_dpm_table *gfx_table =
1852	&dpm_context->dpm_tables.gfx_table;
1853	struct smu_11_0_dpm_table *mem_table =
1854	&dpm_context->dpm_tables.uclk_table;
1855	struct smu_11_0_dpm_table *soc_table =
1856	&dpm_context->dpm_tables.soc_table;
1857	struct smu_umd_pstate_table *pstate_table =
1858	&smu->pstate_table;
1859	struct amdgpu_device *adev = smu->adev;
1860	uint32_t sclk_min = 0, sclk_max = 0;
1861	uint32_t mclk_min = 0, mclk_max = 0;
1862	uint32_t socclk_min = 0, socclk_max = 0;
1863	int ret = 0;
1864
1865	switch (level) {
1866	case AMD_DPM_FORCED_LEVEL_HIGH:
1867	sclk_min = sclk_max = gfx_table->max;
1868	mclk_min = mclk_max = mem_table->max;
1869	socclk_min = socclk_max = soc_table->max;
1870	break;
1871	case AMD_DPM_FORCED_LEVEL_LOW:
1872	sclk_min = sclk_max = gfx_table->min;
1873	mclk_min = mclk_max = mem_table->min;
1874	socclk_min = socclk_max = soc_table->min;
1875	break;
1876	case AMD_DPM_FORCED_LEVEL_AUTO:
1877	sclk_min = gfx_table->min;
1878	sclk_max = gfx_table->max;
1879	mclk_min = mem_table->min;
1880	mclk_max = mem_table->max;
1881	socclk_min = soc_table->min;
1882	socclk_max = soc_table->max;
1883	break;
1884	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1885	sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1886	mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1887	socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1888	break;
1889	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1890	sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1891	break;
1892	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1893	mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1894	break;
1895	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1896	sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1897	mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1898	socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1899	break;
1900	case AMD_DPM_FORCED_LEVEL_MANUAL:
1901	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1902	return 0;
1903	default:
1904	dev_err(adev->dev, "Invalid performance level %d\n", level)printf("drm:pid%d:%s ERROR " "Invalid performance level %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , level);
1905	return -EINVAL22;
1906	}
1907
1908	/*
1909	* Separate MCLK and SOCCLK soft min/max settings are not allowed
1910	* on Arcturus.
1911	*/
1912	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)(((11) << 16) \| ((0) << 8) \| (2))) {
1913	mclk_min = mclk_max = 0;
1914	socclk_min = socclk_max = 0;
1915	}
1916
1917	if (sclk_min && sclk_max) {
1918	ret = smu_v11_0_set_soft_freq_limited_range(smu,
1919	SMU_GFXCLK,
1920	sclk_min,
1921	sclk_max);
1922	if (ret)
1923	return ret;
1924	}
1925
1926	if (mclk_min && mclk_max) {
1927	ret = smu_v11_0_set_soft_freq_limited_range(smu,
1928	SMU_MCLK,
1929	mclk_min,
1930	mclk_max);
1931	if (ret)
1932	return ret;
1933	}
1934
1935	if (socclk_min && socclk_max) {
1936	ret = smu_v11_0_set_soft_freq_limited_range(smu,
1937	SMU_SOCCLK,
1938	socclk_min,
1939	socclk_max);
1940	if (ret)
1941	return ret;
1942	}
1943
1944	return ret;
1945	}
1946
1947	int smu_v11_0_set_power_source(struct smu_context *smu,
1948	enum smu_power_src_type power_src)
1949	{
1950	int pwr_source;
1951
1952	pwr_source = smu_cmn_to_asic_specific_index(smu,
1953	CMN2ASIC_MAPPING_PWR,
1954	(uint32_t)power_src);
1955	if (pwr_source < 0)
1956	return -EINVAL22;
1957
1958	return smu_cmn_send_smc_msg_with_param(smu,
1959	SMU_MSG_NotifyPowerSource,
1960	pwr_source,
1961	NULL((void *)0));
1962	}
1963
1964	int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1965	enum smu_clk_type clk_type,
1966	uint16_t level,
1967	uint32_t *value)
1968	{
1969	int ret = 0, clk_id = 0;
1970	uint32_t param;
1971
1972	if (!value)
1973	return -EINVAL22;
1974
1975	if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1976	return 0;
1977
1978	clk_id = smu_cmn_to_asic_specific_index(smu,
1979	CMN2ASIC_MAPPING_CLK,
1980	clk_type);
1981	if (clk_id < 0)
1982	return clk_id;
1983
1984	param = (uint32_t)(((clk_id & 0xffff) << 16) \| (level & 0xffff));
1985
1986	ret = smu_cmn_send_smc_msg_with_param(smu,
1987	SMU_MSG_GetDpmFreqByIndex,
1988	param,
1989	value);
1990	if (ret)
1991	return ret;
1992
1993	/*
1994	* BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1995	* now, we un-support it
1996	*/
1997	value = value & 0x7fffffff;
1998
1999	return ret;
2000	}
2001
2002	int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
2003	enum smu_clk_type clk_type,
2004	uint32_t *value)
2005	{
2006	return smu_v11_0_get_dpm_freq_by_index(smu,
2007	clk_type,
2008	0xff,
2009	value);
2010	}
2011
2012	int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
2013	enum smu_clk_type clk_type,
2014	struct smu_11_0_dpm_table *single_dpm_table)
2015	{
2016	int ret = 0;
2017	uint32_t clk;
2018	int i;
2019
2020	ret = smu_v11_0_get_dpm_level_count(smu,
2021	clk_type,
2022	&single_dpm_table->count);
2023	if (ret) {
2024	dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__)printf("drm:pid%d:%s ERROR " "[%s] failed to get dpm levels!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
2025	return ret;
2026	}
2027
2028	for (i = 0; i < single_dpm_table->count; i++) {
2029	ret = smu_v11_0_get_dpm_freq_by_index(smu,
2030	clk_type,
2031	i,
2032	&clk);
2033	if (ret) {
2034	dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__)printf("drm:pid%d:%s ERROR " "[%s] failed to get dpm freq by index!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ );
2035	return ret;
2036	}
2037
2038	single_dpm_table->dpm_levels[i].value = clk;
2039	single_dpm_table->dpm_levels[i].enabled = true1;
2040
2041	if (i == 0)
2042	single_dpm_table->min = clk;
2043	else if (i == single_dpm_table->count - 1)
2044	single_dpm_table->max = clk;
2045	}
2046
2047	return 0;
2048	}
2049
2050	int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
2051	enum smu_clk_type clk_type,
2052	uint32_t *min_value,
2053	uint32_t *max_value)
2054	{
2055	uint32_t level_count = 0;
2056	int ret = 0;
2057
2058	if (!min_value && !max_value)
2059	return -EINVAL22;
2060
2061	if (min_value) {
2062	/* by default, level 0 clock value as min value */
2063	ret = smu_v11_0_get_dpm_freq_by_index(smu,
2064	clk_type,
2065	0,
2066	min_value);
2067	if (ret)
2068	return ret;
2069	}
2070
2071	if (max_value) {
2072	ret = smu_v11_0_get_dpm_level_count(smu,
2073	clk_type,
2074	&level_count);
2075	if (ret)
2076	return ret;
2077
2078	ret = smu_v11_0_get_dpm_freq_by_index(smu,
2079	clk_type,
2080	level_count - 1,
2081	max_value);
2082	if (ret)
2083	return ret;
2084	}
2085
2086	return ret;
2087	}
2088
2089	int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2090	{
2091	struct amdgpu_device *adev = smu->adev;
2092
2093	return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL)adev->pcie_rreg(adev, (0x11140288)) &
2094	PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK0x00000070L)
2095	>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT0x4;
2096	}
2097
2098	uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2099	{
2100	uint32_t width_level;
2101
2102	width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2103	if (width_level > LINK_WIDTH_MAX6)
2104	width_level = 0;
2105
2106	return link_width[width_level];
2107	}
2108
2109	int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2110	{
2111	struct amdgpu_device *adev = smu->adev;
2112
2113	return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL)adev->pcie_rreg(adev, (0x11140290)) &
2114	PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK0xC000)
2115	>> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT0xE;
2116	}
2117
2118	uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2119	{
2120	uint32_t speed_level;
2121
2122	speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2123	if (speed_level > LINK_SPEED_MAX3)
2124	speed_level = 0;
2125
2126	return link_speed[speed_level];
2127	}
2128
2129	int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2130	bool_Bool enablement)
2131	{
2132	int ret = 0;
2133
2134	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2135	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2136
2137	return ret;
2138	}
2139
2140	int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2141	bool_Bool enablement)
2142	{
2143	struct amdgpu_device *adev = smu->adev;
	Value stored to 'adev' during its initialization is never read
2144	int ret = 0;
2145
2146	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2147	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2148	if (ret) {
2149	dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable")printf("drm:pid%d:%s ERROR " "Failed to %s GFXCLK DS!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , enablement ? "enable" : "disable");
2150	return ret;
2151	}
2152	}
2153
2154	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2155	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2156	if (ret) {
2157	dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable")printf("drm:pid%d:%s ERROR " "Failed to %s UCLK DS!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__ , enablement ? "enable" : "disable");
2158	return ret;
2159	}
2160	}
2161
2162	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2163	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2164	if (ret) {
2165	dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable")printf("drm:pid%d:%s ERROR " "Failed to %s FCLK DS!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__ , enablement ? "enable" : "disable");
2166	return ret;
2167	}
2168	}
2169
2170	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2171	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2172	if (ret) {
2173	dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable")printf("drm:pid%d:%s ERROR " "Failed to %s SOCCLK DS!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , enablement ? "enable" : "disable");
2174	return ret;
2175	}
2176	}
2177
2178	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2179	ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2180	if (ret) {
2181	dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable")printf("drm:pid%d:%s ERROR " "Failed to %s LCLK DS!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__ , enablement ? "enable" : "disable");
2182	return ret;
2183	}
2184	}
2185
2186	return ret;
2187	}
2188
2189	int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
2190	{
2191	struct smu_table_context *table_context = &smu->smu_table;
2192	void *user_od_table = table_context->user_overdrive_table;
2193	int ret = 0;
2194
2195	ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true1);
2196	if (ret)
2197	dev_err(smu->adev->dev, "Failed to import overdrive table!\n")printf("drm:pid%d:%s ERROR " "Failed to import overdrive table!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__);
2198
2199	return ret;
2200	}
2201
2202	void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
2203	{
2204	struct amdgpu_device *adev = smu->adev;
2205
2206	smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82)(adev->reg_offset[MP1_HWIP][0][0] + 0x0292);
2207	smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66)(adev->reg_offset[MP1_HWIP][0][0] + 0x0282);
2208	smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90)(adev->reg_offset[MP1_HWIP][0][0] + 0x029a);
2209	}