Bug Summary

File:dev/pci/drm/i915/gt/uc/intel_guc_capture.c
Warning:line 364, column 2
Value stored to 'sseu' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name intel_guc_capture.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/i915/gt/uc/intel_guc_capture.c
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2021-2022 Intel Corporation
4 */
5
6#include <linux/types.h>
7
8#include <drm/drm_print.h>
9
10#include "gt/intel_engine_regs.h"
11#include "gt/intel_gt.h"
12#include "gt/intel_gt_mcr.h"
13#include "gt/intel_gt_regs.h"
14#include "gt/intel_lrc.h"
15#include "guc_capture_fwif.h"
16#include "intel_guc_capture.h"
17#include "intel_guc_fwif.h"
18#include "i915_drv.h"
19#include "i915_gpu_error.h"
20#include "i915_irq.h"
21#include "i915_memcpy.h"
22#include "i915_reg.h"
23
24/*
25 * Define all device tables of GuC error capture register lists
26 * NOTE: For engine-registers, GuC only needs the register offsets
27 * from the engine-mmio-base
28 */
29#define COMMON_BASE_GLOBAL{ ((const i915_reg_t){ .reg = (0xa188) }), 0, 0, "FORCEWAKE" } \
30 { FORCEWAKE_MT((const i915_reg_t){ .reg = (0xa188) }), 0, 0, "FORCEWAKE" }
31
32#define COMMON_GEN9BASE_GLOBAL{ ((const i915_reg_t){ .reg = (0x40a0) }), 0, 0, "ERROR_GEN6"
}, { ((const i915_reg_t){ .reg = (0x40b0) }), 0, 0, "DONE_REG"
}, { ((const i915_reg_t){ .reg = (0x4024) }), 0, 0, "HSW_GTT_CACHE_EN"
} \
33 { ERROR_GEN6((const i915_reg_t){ .reg = (0x40a0) }), 0, 0, "ERROR_GEN6" }, \
34 { DONE_REG((const i915_reg_t){ .reg = (0x40b0) }), 0, 0, "DONE_REG" }, \
35 { HSW_GTT_CACHE_EN((const i915_reg_t){ .reg = (0x4024) }), 0, 0, "HSW_GTT_CACHE_EN" }
36
37#define GEN9_GLOBAL{ ((const i915_reg_t){ .reg = (0x4b10) }), 0, 0, "GEN8_FAULT_TLB_DATA0"
}, { ((const i915_reg_t){ .reg = (0x4b14) }), 0, 0, "GEN8_FAULT_TLB_DATA1"
} \
38 { GEN8_FAULT_TLB_DATA0((const i915_reg_t){ .reg = (0x4b10) }), 0, 0, "GEN8_FAULT_TLB_DATA0" }, \
39 { GEN8_FAULT_TLB_DATA1((const i915_reg_t){ .reg = (0x4b14) }), 0, 0, "GEN8_FAULT_TLB_DATA1" }
40
41#define COMMON_GEN12BASE_GLOBAL{ ((const i915_reg_t){ .reg = (0xceb8) }), 0, 0, "GEN12_FAULT_TLB_DATA0"
}, { ((const i915_reg_t){ .reg = (0xcebc) }), 0, 0, "GEN12_FAULT_TLB_DATA1"
}, { ((const i915_reg_t){ .reg = (0x43f4) }), 0, 0, "AUX_ERR_DBG"
}, { ((const i915_reg_t){ .reg = (0xcf68) }), 0, 0, "GAM_DONE"
}, { ((const i915_reg_t){ .reg = (0xcec4) }), 0, 0, "FAULT_REG"
} \
42 { GEN12_FAULT_TLB_DATA0((const i915_reg_t){ .reg = (0xceb8) }), 0, 0, "GEN12_FAULT_TLB_DATA0" }, \
43 { GEN12_FAULT_TLB_DATA1((const i915_reg_t){ .reg = (0xcebc) }), 0, 0, "GEN12_FAULT_TLB_DATA1" }, \
44 { GEN12_AUX_ERR_DBG((const i915_reg_t){ .reg = (0x43f4) }), 0, 0, "AUX_ERR_DBG" }, \
45 { GEN12_GAM_DONE((const i915_reg_t){ .reg = (0xcf68) }), 0, 0, "GAM_DONE" }, \
46 { GEN12_RING_FAULT_REG((const i915_reg_t){ .reg = (0xcec4) }), 0, 0, "FAULT_REG" }
47
48#define COMMON_BASE_ENGINE_INSTANCE{ ((const i915_reg_t){ .reg = ((0) + 0x50) }), 0, 0, "RC PSMI"
}, { ((const i915_reg_t){ .reg = ((0) + 0xb8) }), 0, 0, "ESR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x78) }), 0, 0, "RING_DMA_FADD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x60) }), 0, 0, "RING_DMA_FADD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x64) }), 0, 0, "IPEIR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x68) }), 0, 0, "IPEHR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x70) }), 0, 0, "INSTPS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x140) }), 0, 0, "RING_BBADDR_LOW32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x168) }), 0, 0, "RING_BBADDR_UP32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x110) }), 0, 0, "BB_STATE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x180) }), 0, 0, "CCID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x74) }), 0, 0, "ACTHD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x5c) }), 0, 0, "ACTHD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0xc0) }), 0, 0, "INSTPM"
}, { ((const i915_reg_t){ .reg = ((0) + 0x6c) }), 0, 0, "INSTDONE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x94) }), 0, 0, "RING_NOPID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x38) }), 0, 0, "START"
}, { ((const i915_reg_t){ .reg = ((0) + 0x34) }), 0, 0, "HEAD"
}, { ((const i915_reg_t){ .reg = ((0) + 0x30) }), 0, 0, "TAIL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x3c) }), 0, 0, "CTL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x9c) }), 0, 0, "MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x244) }), 0, 0, "RING_CONTEXT_CONTROL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x80) }), 0, 0, "HWS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x29c) }), 0, 0, "GFX_MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (0) * 8) }),
0, 0, "PDP0_LDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270
+ (0) * 8 + 4) }), 0, 0, "PDP0_UDW" }, { ((const i915_reg_t)
{ .reg = ((0) + 0x270 + (1) * 8) }), 0, 0, "PDP1_LDW" }, { ((
const i915_reg_t){ .reg = ((0) + 0x270 + (1) * 8 + 4) }), 0, 0
, "PDP1_UDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (
2) * 8) }), 0, 0, "PDP2_LDW" }, { ((const i915_reg_t){ .reg =
((0) + 0x270 + (2) * 8 + 4) }), 0, 0, "PDP2_UDW" }, { ((const
i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8) }), 0, 0, "PDP3_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8 + 4)
}), 0, 0, "PDP3_UDW" } \
49 { RING_PSMI_CTL(0)((const i915_reg_t){ .reg = ((0) + 0x50) }), 0, 0, "RC PSMI" }, \
50 { RING_ESR(0)((const i915_reg_t){ .reg = ((0) + 0xb8) }), 0, 0, "ESR" }, \
51 { RING_DMA_FADD(0)((const i915_reg_t){ .reg = ((0) + 0x78) }), 0, 0, "RING_DMA_FADD_LDW" }, \
52 { RING_DMA_FADD_UDW(0)((const i915_reg_t){ .reg = ((0) + 0x60) }), 0, 0, "RING_DMA_FADD_UDW" }, \
53 { RING_IPEIR(0)((const i915_reg_t){ .reg = ((0) + 0x64) }), 0, 0, "IPEIR" }, \
54 { RING_IPEHR(0)((const i915_reg_t){ .reg = ((0) + 0x68) }), 0, 0, "IPEHR" }, \
55 { RING_INSTPS(0)((const i915_reg_t){ .reg = ((0) + 0x70) }), 0, 0, "INSTPS" }, \
56 { RING_BBADDR(0)((const i915_reg_t){ .reg = ((0) + 0x140) }), 0, 0, "RING_BBADDR_LOW32" }, \
57 { RING_BBADDR_UDW(0)((const i915_reg_t){ .reg = ((0) + 0x168) }), 0, 0, "RING_BBADDR_UP32" }, \
58 { RING_BBSTATE(0)((const i915_reg_t){ .reg = ((0) + 0x110) }), 0, 0, "BB_STATE" }, \
59 { CCID(0)((const i915_reg_t){ .reg = ((0) + 0x180) }), 0, 0, "CCID" }, \
60 { RING_ACTHD(0)((const i915_reg_t){ .reg = ((0) + 0x74) }), 0, 0, "ACTHD_LDW" }, \
61 { RING_ACTHD_UDW(0)((const i915_reg_t){ .reg = ((0) + 0x5c) }), 0, 0, "ACTHD_UDW" }, \
62 { RING_INSTPM(0)((const i915_reg_t){ .reg = ((0) + 0xc0) }), 0, 0, "INSTPM" }, \
63 { RING_INSTDONE(0)((const i915_reg_t){ .reg = ((0) + 0x6c) }), 0, 0, "INSTDONE" }, \
64 { RING_NOPID(0)((const i915_reg_t){ .reg = ((0) + 0x94) }), 0, 0, "RING_NOPID" }, \
65 { RING_START(0)((const i915_reg_t){ .reg = ((0) + 0x38) }), 0, 0, "START" }, \
66 { RING_HEAD(0)((const i915_reg_t){ .reg = ((0) + 0x34) }), 0, 0, "HEAD" }, \
67 { RING_TAIL(0)((const i915_reg_t){ .reg = ((0) + 0x30) }), 0, 0, "TAIL" }, \
68 { RING_CTL(0)((const i915_reg_t){ .reg = ((0) + 0x3c) }), 0, 0, "CTL" }, \
69 { RING_MI_MODE(0)((const i915_reg_t){ .reg = ((0) + 0x9c) }), 0, 0, "MODE" }, \
70 { RING_CONTEXT_CONTROL(0)((const i915_reg_t){ .reg = ((0) + 0x244) }), 0, 0, "RING_CONTEXT_CONTROL" }, \
71 { RING_HWS_PGA(0)((const i915_reg_t){ .reg = ((0) + 0x80) }), 0, 0, "HWS" }, \
72 { RING_MODE_GEN7(0)((const i915_reg_t){ .reg = ((0) + 0x29c) }), 0, 0, "GFX_MODE" }, \
73 { GEN8_RING_PDP_LDW(0, 0)((const i915_reg_t){ .reg = ((0) + 0x270 + (0) * 8) }), 0, 0, "PDP0_LDW" }, \
74 { GEN8_RING_PDP_UDW(0, 0)((const i915_reg_t){ .reg = ((0) + 0x270 + (0) * 8 + 4) }), 0, 0, "PDP0_UDW" }, \
75 { GEN8_RING_PDP_LDW(0, 1)((const i915_reg_t){ .reg = ((0) + 0x270 + (1) * 8) }), 0, 0, "PDP1_LDW" }, \
76 { GEN8_RING_PDP_UDW(0, 1)((const i915_reg_t){ .reg = ((0) + 0x270 + (1) * 8 + 4) }), 0, 0, "PDP1_UDW" }, \
77 { GEN8_RING_PDP_LDW(0, 2)((const i915_reg_t){ .reg = ((0) + 0x270 + (2) * 8) }), 0, 0, "PDP2_LDW" }, \
78 { GEN8_RING_PDP_UDW(0, 2)((const i915_reg_t){ .reg = ((0) + 0x270 + (2) * 8 + 4) }), 0, 0, "PDP2_UDW" }, \
79 { GEN8_RING_PDP_LDW(0, 3)((const i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8) }), 0, 0, "PDP3_LDW" }, \
80 { GEN8_RING_PDP_UDW(0, 3)((const i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8 + 4) }), 0, 0, "PDP3_UDW" }
81
82#define COMMON_BASE_HAS_EU{ ((const i915_reg_t){ .reg = (0x20b0) }), 0, 0, "EIR" } \
83 { EIR((const i915_reg_t){ .reg = (0x20b0) }), 0, 0, "EIR" }
84
85#define COMMON_BASE_RENDER{ ((const i915_reg_t){ .reg = (0x7100) }), 0, 0, "GEN7_SC_INSTDONE"
} \
86 { GEN7_SC_INSTDONE((const i915_reg_t){ .reg = (0x7100) }), 0, 0, "GEN7_SC_INSTDONE" }
87
88#define COMMON_GEN12BASE_RENDER{ ((const i915_reg_t){ .reg = (0x7104) }), 0, 0, "GEN12_SC_INSTDONE_EXTRA"
}, { ((const i915_reg_t){ .reg = (0x7108) }), 0, 0, "GEN12_SC_INSTDONE_EXTRA2"
} \
89 { GEN12_SC_INSTDONE_EXTRA((const i915_reg_t){ .reg = (0x7104) }), 0, 0, "GEN12_SC_INSTDONE_EXTRA" }, \
90 { GEN12_SC_INSTDONE_EXTRA2((const i915_reg_t){ .reg = (0x7108) }), 0, 0, "GEN12_SC_INSTDONE_EXTRA2" }
91
92#define COMMON_GEN12BASE_VEC{ ((const i915_reg_t){ .reg = (0x1cc000 + (0) * 0x1000) }), 0
, 0, "SFC_DONE[0]" }, { ((const i915_reg_t){ .reg = (0x1cc000
+ (1) * 0x1000) }), 0, 0, "SFC_DONE[1]" }, { ((const i915_reg_t
){ .reg = (0x1cc000 + (2) * 0x1000) }), 0, 0, "SFC_DONE[2]" }
, { ((const i915_reg_t){ .reg = (0x1cc000 + (3) * 0x1000) }),
0, 0, "SFC_DONE[3]" } \
93 { GEN12_SFC_DONE(0)((const i915_reg_t){ .reg = (0x1cc000 + (0) * 0x1000) }), 0, 0, "SFC_DONE[0]" }, \
94 { GEN12_SFC_DONE(1)((const i915_reg_t){ .reg = (0x1cc000 + (1) * 0x1000) }), 0, 0, "SFC_DONE[1]" }, \
95 { GEN12_SFC_DONE(2)((const i915_reg_t){ .reg = (0x1cc000 + (2) * 0x1000) }), 0, 0, "SFC_DONE[2]" }, \
96 { GEN12_SFC_DONE(3)((const i915_reg_t){ .reg = (0x1cc000 + (3) * 0x1000) }), 0, 0, "SFC_DONE[3]" }
97
98/* XE_LPD - Global */
99static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
100 COMMON_BASE_GLOBAL{ ((const i915_reg_t){ .reg = (0xa188) }), 0, 0, "FORCEWAKE" },
101 COMMON_GEN9BASE_GLOBAL{ ((const i915_reg_t){ .reg = (0x40a0) }), 0, 0, "ERROR_GEN6"
}, { ((const i915_reg_t){ .reg = (0x40b0) }), 0, 0, "DONE_REG"
}, { ((const i915_reg_t){ .reg = (0x4024) }), 0, 0, "HSW_GTT_CACHE_EN"
},
102 COMMON_GEN12BASE_GLOBAL{ ((const i915_reg_t){ .reg = (0xceb8) }), 0, 0, "GEN12_FAULT_TLB_DATA0"
}, { ((const i915_reg_t){ .reg = (0xcebc) }), 0, 0, "GEN12_FAULT_TLB_DATA1"
}, { ((const i915_reg_t){ .reg = (0x43f4) }), 0, 0, "AUX_ERR_DBG"
}, { ((const i915_reg_t){ .reg = (0xcf68) }), 0, 0, "GAM_DONE"
}, { ((const i915_reg_t){ .reg = (0xcec4) }), 0, 0, "FAULT_REG"
},
103};
104
105/* XE_LPD - Render / Compute Per-Class */
106static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = {
107 COMMON_BASE_HAS_EU{ ((const i915_reg_t){ .reg = (0x20b0) }), 0, 0, "EIR" },
108 COMMON_BASE_RENDER{ ((const i915_reg_t){ .reg = (0x7100) }), 0, 0, "GEN7_SC_INSTDONE"
},
109 COMMON_GEN12BASE_RENDER{ ((const i915_reg_t){ .reg = (0x7104) }), 0, 0, "GEN12_SC_INSTDONE_EXTRA"
}, { ((const i915_reg_t){ .reg = (0x7108) }), 0, 0, "GEN12_SC_INSTDONE_EXTRA2"
},
110};
111
112/* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */
113static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = {
114 COMMON_BASE_ENGINE_INSTANCE{ ((const i915_reg_t){ .reg = ((0) + 0x50) }), 0, 0, "RC PSMI"
}, { ((const i915_reg_t){ .reg = ((0) + 0xb8) }), 0, 0, "ESR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x78) }), 0, 0, "RING_DMA_FADD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x60) }), 0, 0, "RING_DMA_FADD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x64) }), 0, 0, "IPEIR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x68) }), 0, 0, "IPEHR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x70) }), 0, 0, "INSTPS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x140) }), 0, 0, "RING_BBADDR_LOW32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x168) }), 0, 0, "RING_BBADDR_UP32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x110) }), 0, 0, "BB_STATE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x180) }), 0, 0, "CCID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x74) }), 0, 0, "ACTHD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x5c) }), 0, 0, "ACTHD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0xc0) }), 0, 0, "INSTPM"
}, { ((const i915_reg_t){ .reg = ((0) + 0x6c) }), 0, 0, "INSTDONE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x94) }), 0, 0, "RING_NOPID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x38) }), 0, 0, "START"
}, { ((const i915_reg_t){ .reg = ((0) + 0x34) }), 0, 0, "HEAD"
}, { ((const i915_reg_t){ .reg = ((0) + 0x30) }), 0, 0, "TAIL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x3c) }), 0, 0, "CTL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x9c) }), 0, 0, "MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x244) }), 0, 0, "RING_CONTEXT_CONTROL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x80) }), 0, 0, "HWS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x29c) }), 0, 0, "GFX_MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (0) * 8) }),
0, 0, "PDP0_LDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270
+ (0) * 8 + 4) }), 0, 0, "PDP0_UDW" }, { ((const i915_reg_t)
{ .reg = ((0) + 0x270 + (1) * 8) }), 0, 0, "PDP1_LDW" }, { ((
const i915_reg_t){ .reg = ((0) + 0x270 + (1) * 8 + 4) }), 0, 0
, "PDP1_UDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (
2) * 8) }), 0, 0, "PDP2_LDW" }, { ((const i915_reg_t){ .reg =
((0) + 0x270 + (2) * 8 + 4) }), 0, 0, "PDP2_UDW" }, { ((const
i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8) }), 0, 0, "PDP3_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8 + 4)
}), 0, 0, "PDP3_UDW" },
115};
116
117/* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */
118static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = {
119 COMMON_BASE_ENGINE_INSTANCE{ ((const i915_reg_t){ .reg = ((0) + 0x50) }), 0, 0, "RC PSMI"
}, { ((const i915_reg_t){ .reg = ((0) + 0xb8) }), 0, 0, "ESR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x78) }), 0, 0, "RING_DMA_FADD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x60) }), 0, 0, "RING_DMA_FADD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x64) }), 0, 0, "IPEIR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x68) }), 0, 0, "IPEHR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x70) }), 0, 0, "INSTPS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x140) }), 0, 0, "RING_BBADDR_LOW32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x168) }), 0, 0, "RING_BBADDR_UP32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x110) }), 0, 0, "BB_STATE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x180) }), 0, 0, "CCID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x74) }), 0, 0, "ACTHD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x5c) }), 0, 0, "ACTHD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0xc0) }), 0, 0, "INSTPM"
}, { ((const i915_reg_t){ .reg = ((0) + 0x6c) }), 0, 0, "INSTDONE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x94) }), 0, 0, "RING_NOPID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x38) }), 0, 0, "START"
}, { ((const i915_reg_t){ .reg = ((0) + 0x34) }), 0, 0, "HEAD"
}, { ((const i915_reg_t){ .reg = ((0) + 0x30) }), 0, 0, "TAIL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x3c) }), 0, 0, "CTL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x9c) }), 0, 0, "MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x244) }), 0, 0, "RING_CONTEXT_CONTROL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x80) }), 0, 0, "HWS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x29c) }), 0, 0, "GFX_MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (0) * 8) }),
0, 0, "PDP0_LDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270
+ (0) * 8 + 4) }), 0, 0, "PDP0_UDW" }, { ((const i915_reg_t)
{ .reg = ((0) + 0x270 + (1) * 8) }), 0, 0, "PDP1_LDW" }, { ((
const i915_reg_t){ .reg = ((0) + 0x270 + (1) * 8 + 4) }), 0, 0
, "PDP1_UDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (
2) * 8) }), 0, 0, "PDP2_LDW" }, { ((const i915_reg_t){ .reg =
((0) + 0x270 + (2) * 8 + 4) }), 0, 0, "PDP2_UDW" }, { ((const
i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8) }), 0, 0, "PDP3_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8 + 4)
}), 0, 0, "PDP3_UDW" },
120};
121
122/* XE_LPD - Video Enhancement Per-Class */
123static const struct __guc_mmio_reg_descr xe_lpd_vec_class_regs[] = {
124 COMMON_GEN12BASE_VEC{ ((const i915_reg_t){ .reg = (0x1cc000 + (0) * 0x1000) }), 0
, 0, "SFC_DONE[0]" }, { ((const i915_reg_t){ .reg = (0x1cc000
+ (1) * 0x1000) }), 0, 0, "SFC_DONE[1]" }, { ((const i915_reg_t
){ .reg = (0x1cc000 + (2) * 0x1000) }), 0, 0, "SFC_DONE[2]" }
, { ((const i915_reg_t){ .reg = (0x1cc000 + (3) * 0x1000) }),
0, 0, "SFC_DONE[3]" },
125};
126
127/* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */
128static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = {
129 COMMON_BASE_ENGINE_INSTANCE{ ((const i915_reg_t){ .reg = ((0) + 0x50) }), 0, 0, "RC PSMI"
}, { ((const i915_reg_t){ .reg = ((0) + 0xb8) }), 0, 0, "ESR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x78) }), 0, 0, "RING_DMA_FADD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x60) }), 0, 0, "RING_DMA_FADD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x64) }), 0, 0, "IPEIR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x68) }), 0, 0, "IPEHR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x70) }), 0, 0, "INSTPS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x140) }), 0, 0, "RING_BBADDR_LOW32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x168) }), 0, 0, "RING_BBADDR_UP32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x110) }), 0, 0, "BB_STATE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x180) }), 0, 0, "CCID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x74) }), 0, 0, "ACTHD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x5c) }), 0, 0, "ACTHD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0xc0) }), 0, 0, "INSTPM"
}, { ((const i915_reg_t){ .reg = ((0) + 0x6c) }), 0, 0, "INSTDONE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x94) }), 0, 0, "RING_NOPID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x38) }), 0, 0, "START"
}, { ((const i915_reg_t){ .reg = ((0) + 0x34) }), 0, 0, "HEAD"
}, { ((const i915_reg_t){ .reg = ((0) + 0x30) }), 0, 0, "TAIL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x3c) }), 0, 0, "CTL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x9c) }), 0, 0, "MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x244) }), 0, 0, "RING_CONTEXT_CONTROL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x80) }), 0, 0, "HWS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x29c) }), 0, 0, "GFX_MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (0) * 8) }),
0, 0, "PDP0_LDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270
+ (0) * 8 + 4) }), 0, 0, "PDP0_UDW" }, { ((const i915_reg_t)
{ .reg = ((0) + 0x270 + (1) * 8) }), 0, 0, "PDP1_LDW" }, { ((
const i915_reg_t){ .reg = ((0) + 0x270 + (1) * 8 + 4) }), 0, 0
, "PDP1_UDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (
2) * 8) }), 0, 0, "PDP2_LDW" }, { ((const i915_reg_t){ .reg =
((0) + 0x270 + (2) * 8 + 4) }), 0, 0, "PDP2_UDW" }, { ((const
i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8) }), 0, 0, "PDP3_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8 + 4)
}), 0, 0, "PDP3_UDW" },
130};
131
132/* GEN9/XE_LPD - Blitter Per-Engine-Instance */
133static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = {
134 COMMON_BASE_ENGINE_INSTANCE{ ((const i915_reg_t){ .reg = ((0) + 0x50) }), 0, 0, "RC PSMI"
}, { ((const i915_reg_t){ .reg = ((0) + 0xb8) }), 0, 0, "ESR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x78) }), 0, 0, "RING_DMA_FADD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x60) }), 0, 0, "RING_DMA_FADD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x64) }), 0, 0, "IPEIR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x68) }), 0, 0, "IPEHR"
}, { ((const i915_reg_t){ .reg = ((0) + 0x70) }), 0, 0, "INSTPS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x140) }), 0, 0, "RING_BBADDR_LOW32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x168) }), 0, 0, "RING_BBADDR_UP32"
}, { ((const i915_reg_t){ .reg = ((0) + 0x110) }), 0, 0, "BB_STATE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x180) }), 0, 0, "CCID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x74) }), 0, 0, "ACTHD_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x5c) }), 0, 0, "ACTHD_UDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0xc0) }), 0, 0, "INSTPM"
}, { ((const i915_reg_t){ .reg = ((0) + 0x6c) }), 0, 0, "INSTDONE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x94) }), 0, 0, "RING_NOPID"
}, { ((const i915_reg_t){ .reg = ((0) + 0x38) }), 0, 0, "START"
}, { ((const i915_reg_t){ .reg = ((0) + 0x34) }), 0, 0, "HEAD"
}, { ((const i915_reg_t){ .reg = ((0) + 0x30) }), 0, 0, "TAIL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x3c) }), 0, 0, "CTL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x9c) }), 0, 0, "MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x244) }), 0, 0, "RING_CONTEXT_CONTROL"
}, { ((const i915_reg_t){ .reg = ((0) + 0x80) }), 0, 0, "HWS"
}, { ((const i915_reg_t){ .reg = ((0) + 0x29c) }), 0, 0, "GFX_MODE"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (0) * 8) }),
0, 0, "PDP0_LDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270
+ (0) * 8 + 4) }), 0, 0, "PDP0_UDW" }, { ((const i915_reg_t)
{ .reg = ((0) + 0x270 + (1) * 8) }), 0, 0, "PDP1_LDW" }, { ((
const i915_reg_t){ .reg = ((0) + 0x270 + (1) * 8 + 4) }), 0, 0
, "PDP1_UDW" }, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (
2) * 8) }), 0, 0, "PDP2_LDW" }, { ((const i915_reg_t){ .reg =
((0) + 0x270 + (2) * 8 + 4) }), 0, 0, "PDP2_UDW" }, { ((const
i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8) }), 0, 0, "PDP3_LDW"
}, { ((const i915_reg_t){ .reg = ((0) + 0x270 + (3) * 8 + 4)
}), 0, 0, "PDP3_UDW" },
135};
136
137/* GEN9 - Global */
138static const struct __guc_mmio_reg_descr default_global_regs[] = {
139 COMMON_BASE_GLOBAL{ ((const i915_reg_t){ .reg = (0xa188) }), 0, 0, "FORCEWAKE" },
140 COMMON_GEN9BASE_GLOBAL{ ((const i915_reg_t){ .reg = (0x40a0) }), 0, 0, "ERROR_GEN6"
}, { ((const i915_reg_t){ .reg = (0x40b0) }), 0, 0, "DONE_REG"
}, { ((const i915_reg_t){ .reg = (0x4024) }), 0, 0, "HSW_GTT_CACHE_EN"
},
141 GEN9_GLOBAL{ ((const i915_reg_t){ .reg = (0x4b10) }), 0, 0, "GEN8_FAULT_TLB_DATA0"
}, { ((const i915_reg_t){ .reg = (0x4b14) }), 0, 0, "GEN8_FAULT_TLB_DATA1"
},
142};
143
144static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
145 COMMON_BASE_HAS_EU{ ((const i915_reg_t){ .reg = (0x20b0) }), 0, 0, "EIR" },
146 COMMON_BASE_RENDER{ ((const i915_reg_t){ .reg = (0x7100) }), 0, 0, "GEN7_SC_INSTDONE"
},
147};
148
149/*
150 * Empty lists:
151 * GEN9/XE_LPD - Blitter Per-Class
152 * GEN9/XE_LPD - Media Decode/Encode Per-Class
153 * GEN9 - VEC Class
154 */
155static const struct __guc_mmio_reg_descr empty_regs_list[] = {
156};
157
158#define TO_GCAP_DEF_OWNER(x)(GUC_CAPTURE_LIST_INDEX_x) (GUC_CAPTURE_LIST_INDEX_##x)
159#define TO_GCAP_DEF_TYPE(x)(GUC_CAPTURE_LIST_TYPE_x) (GUC_CAPTURE_LIST_TYPE_##x)
160#define MAKE_REGLIST(regslist, regsowner, regstype, class){ regslist, (sizeof((regslist)) / sizeof((regslist)[0])), (GUC_CAPTURE_LIST_INDEX_regsowner
), (GUC_CAPTURE_LIST_TYPE_regstype), class, ((void *)0), } \
161 { \
162 regslist, \
163 ARRAY_SIZE(regslist)(sizeof((regslist)) / sizeof((regslist)[0])), \
164 TO_GCAP_DEF_OWNER(regsowner)(GUC_CAPTURE_LIST_INDEX_regsowner), \
165 TO_GCAP_DEF_TYPE(regstype)(GUC_CAPTURE_LIST_TYPE_regstype), \
166 class, \
167 NULL((void *)0), \
168 }
169
170/* List of lists */
171static const struct __guc_mmio_reg_descr_group default_lists[] = {
172 MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0){ default_global_regs, (sizeof((default_global_regs)) / sizeof
((default_global_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_GLOBAL
), 0, ((void *)0), },
173 MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS){ default_rc_class_regs, (sizeof((default_rc_class_regs)) / sizeof
((default_rc_class_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (
GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS), 0, ((void *)0), },
174 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS){ xe_lpd_rc_inst_regs, (sizeof((xe_lpd_rc_inst_regs)) / sizeof
((xe_lpd_rc_inst_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE
), 0, ((void *)0), },
175 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS){ empty_regs_list, (sizeof((empty_regs_list)) / sizeof((empty_regs_list
)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS
), 1, ((void *)0), },
176 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS){ xe_lpd_vd_inst_regs, (sizeof((xe_lpd_vd_inst_regs)) / sizeof
((xe_lpd_vd_inst_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE
), 1, ((void *)0), },
177 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS){ empty_regs_list, (sizeof((empty_regs_list)) / sizeof((empty_regs_list
)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS
), 2, ((void *)0), },
178 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS){ xe_lpd_vec_inst_regs, (sizeof((xe_lpd_vec_inst_regs)) / sizeof
((xe_lpd_vec_inst_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE
), 2, ((void *)0), },
179 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS){ empty_regs_list, (sizeof((empty_regs_list)) / sizeof((empty_regs_list
)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS
), 3, ((void *)0), },
180 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS){ xe_lpd_blt_inst_regs, (sizeof((xe_lpd_blt_inst_regs)) / sizeof
((xe_lpd_blt_inst_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE
), 3, ((void *)0), },
181 {}
182};
183
184static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = {
185 MAKE_REGLIST(xe_lpd_global_regs, PF, GLOBAL, 0){ xe_lpd_global_regs, (sizeof((xe_lpd_global_regs)) / sizeof(
(xe_lpd_global_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_GLOBAL
), 0, ((void *)0), },
186 MAKE_REGLIST(xe_lpd_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS){ xe_lpd_rc_class_regs, (sizeof((xe_lpd_rc_class_regs)) / sizeof
((xe_lpd_rc_class_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS
), 0, ((void *)0), },
187 MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS){ xe_lpd_rc_inst_regs, (sizeof((xe_lpd_rc_inst_regs)) / sizeof
((xe_lpd_rc_inst_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE
), 0, ((void *)0), },
188 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS){ empty_regs_list, (sizeof((empty_regs_list)) / sizeof((empty_regs_list
)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS
), 1, ((void *)0), },
189 MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS){ xe_lpd_vd_inst_regs, (sizeof((xe_lpd_vd_inst_regs)) / sizeof
((xe_lpd_vd_inst_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE
), 1, ((void *)0), },
190 MAKE_REGLIST(xe_lpd_vec_class_regs, PF, ENGINE_CLASS, GUC_VIDEOENHANCE_CLASS){ xe_lpd_vec_class_regs, (sizeof((xe_lpd_vec_class_regs)) / sizeof
((xe_lpd_vec_class_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (
GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS), 2, ((void *)0), },
191 MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS){ xe_lpd_vec_inst_regs, (sizeof((xe_lpd_vec_inst_regs)) / sizeof
((xe_lpd_vec_inst_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE
), 2, ((void *)0), },
192 MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS){ empty_regs_list, (sizeof((empty_regs_list)) / sizeof((empty_regs_list
)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS
), 3, ((void *)0), },
193 MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS){ xe_lpd_blt_inst_regs, (sizeof((xe_lpd_blt_inst_regs)) / sizeof
((xe_lpd_blt_inst_regs)[0])), (GUC_CAPTURE_LIST_INDEX_PF), (GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE
), 3, ((void *)0), },
194 {}
195};
196
197static const struct __guc_mmio_reg_descr_group *
198guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists,
199 u32 owner, u32 type, u32 id)
200{
201 int i;
202
203 if (!reglists)
204 return NULL((void *)0);
205
206 for (i = 0; reglists[i].list; ++i) {
207 if (reglists[i].owner == owner && reglists[i].type == type &&
208 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL))
209 return &reglists[i];
210 }
211
212 return NULL((void *)0);
213}
214
215static struct __guc_mmio_reg_descr_group *
216guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists,
217 u32 owner, u32 type, u32 id)
218{
219 int i;
220
221 if (!reglists)
222 return NULL((void *)0);
223
224 for (i = 0; reglists[i].extlist; ++i) {
225 if (reglists[i].owner == owner && reglists[i].type == type &&
226 (reglists[i].engine == id || reglists[i].type == GUC_CAPTURE_LIST_TYPE_GLOBAL))
227 return &reglists[i];
228 }
229
230 return NULL((void *)0);
231}
232
233static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group *reglists)
234{
235 int i = 0;
236
237 if (!reglists)
238 return;
239
240 while (reglists[i].extlist)
241 kfree(reglists[i++].extlist);
242}
243
244struct __ext_steer_reg {
245 const char *name;
246 i915_reg_t reg;
247};
248
249static const struct __ext_steer_reg xe_extregs[] = {
250 {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE((const i915_reg_t){ .reg = (0xe160) })},
251 {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE((const i915_reg_t){ .reg = (0xe164) })}
252};
253
254static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
255 const struct __ext_steer_reg *extlist,
256 int slice_id, int subslice_id)
257{
258 ext->reg = extlist->reg;
259 ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id)(((typeof((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(12)))))(slice_id) << (__builtin_ffsll((((~0UL) >>
(64 - (15) - 1)) & ((~0UL) << (12)))) - 1)) & (
(((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (12
)))));
260 ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id)(((typeof((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(20)))))(subslice_id) << (__builtin_ffsll((((~0UL) >>
(64 - (23) - 1)) & ((~0UL) << (20)))) - 1)) & (
(((~0UL) >> (64 - (23) - 1)) & ((~0UL) << (20
)))));
261 ext->regname = extlist->name;
262}
263
264static int
265__alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist,
266 const struct __guc_mmio_reg_descr_group *rootlist, int num_regs)
267{
268 struct __guc_mmio_reg_descr *list;
269
270 list = kcalloc(num_regs, sizeof(struct __guc_mmio_reg_descr), GFP_KERNEL(0x0001 | 0x0004));
271 if (!list)
272 return -ENOMEM12;
273
274 newlist->extlist = list;
275 newlist->num_regs = num_regs;
276 newlist->owner = rootlist->owner;
277 newlist->engine = rootlist->engine;
278 newlist->type = rootlist->type;
279
280 return 0;
281}
282
283static void
284guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc *guc,
285 const struct __guc_mmio_reg_descr_group *lists)
286{
287 struct intel_gt *gt = guc_to_gt(guc);
288 int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0;
289 const struct __guc_mmio_reg_descr_group *list;
290 struct __guc_mmio_reg_descr_group *extlists;
291 struct __guc_mmio_reg_descr *extarray;
292 struct sseu_dev_info *sseu;
293
294 /* In XE_LPD we only have steered registers for the render-class */
295 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
296 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS0);
297 /* skip if extlists was previously allocated */
298 if (!list || guc->capture->extlists)
299 return;
300
301 num_steer_regs = ARRAY_SIZE(xe_extregs)(sizeof((xe_extregs)) / sizeof((xe_extregs)[0]));
302
303 sseu = &gt->info.sseu;
304 for_each_ss_steering(iter, gt, slice, subslice)for (iter = 0, intel_gt_mcr_get_ss_steering(gt, 0, &slice
, &subslice); iter < (2 * 32); iter++, intel_gt_mcr_get_ss_steering
(gt, iter, &slice, &subslice)) if (!(( (((&(gt->
i915)->__runtime)->graphics.ip.ver) << 8 | ((&
(gt->i915)->__runtime)->graphics.ip.rel)) >= ((12
) << 8 | (50)) ? intel_sseu_has_subslice(&(gt)->
info.sseu, 0, iter) : intel_sseu_has_subslice(&(gt)->info
.sseu, slice, subslice)))) {} else
305 num_tot_regs += num_steer_regs;
306
307 if (!num_tot_regs)
308 return;
309
310 /* allocate an extra for an end marker */
311 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL(0x0001 | 0x0004));
312 if (!extlists)
313 return;
314
315 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) {
316 kfree(extlists);
317 return;
318 }
319
320 extarray = extlists[0].extlist;
321 for_each_ss_steering(iter, gt, slice, subslice)for (iter = 0, intel_gt_mcr_get_ss_steering(gt, 0, &slice
, &subslice); iter < (2 * 32); iter++, intel_gt_mcr_get_ss_steering
(gt, iter, &slice, &subslice)) if (!(( (((&(gt->
i915)->__runtime)->graphics.ip.ver) << 8 | ((&
(gt->i915)->__runtime)->graphics.ip.rel)) >= ((12
) << 8 | (50)) ? intel_sseu_has_subslice(&(gt)->
info.sseu, 0, iter) : intel_sseu_has_subslice(&(gt)->info
.sseu, slice, subslice)))) {} else {
322 for (i = 0; i < num_steer_regs; ++i) {
323 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice);
324 ++extarray;
325 }
326 }
327
328 guc->capture->extlists = extlists;
329}
330
331static const struct __ext_steer_reg xehpg_extregs[] = {
332 {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG((const i915_reg_t){ .reg = (0x666c) })}
333};
334
335static bool_Bool __has_xehpg_extregs(u32 ipver)
336{
337 return (ipver >= IP_VER(12, 55)((12) << 8 | (55)));
338}
339
340static void
341guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
342 const struct __guc_mmio_reg_descr_group *lists,
343 u32 ipver)
344{
345 struct intel_gt *gt = guc_to_gt(guc);
346 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
347 struct sseu_dev_info *sseu;
348 int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
349 const struct __guc_mmio_reg_descr_group *list;
350 struct __guc_mmio_reg_descr_group *extlists;
351 struct __guc_mmio_reg_descr *extarray;
352
353 /* In XE_LP / HPG we only have render-class steering registers during error-capture */
354 list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
355 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, GUC_RENDER_CLASS0);
356 /* skip if extlists was previously allocated */
357 if (!list || guc->capture->extlists)
358 return;
359
360 num_steer_regs = ARRAY_SIZE(xe_extregs)(sizeof((xe_extregs)) / sizeof((xe_extregs)[0]));
361 if (__has_xehpg_extregs(ipver))
362 num_steer_regs += ARRAY_SIZE(xehpg_extregs)(sizeof((xehpg_extregs)) / sizeof((xehpg_extregs)[0]));
363
364 sseu = &gt->info.sseu;
Value stored to 'sseu' is never read
365 for_each_ss_steering(iter, gt, slice, subslice)for (iter = 0, intel_gt_mcr_get_ss_steering(gt, 0, &slice
, &subslice); iter < (2 * 32); iter++, intel_gt_mcr_get_ss_steering
(gt, iter, &slice, &subslice)) if (!(( (((&(gt->
i915)->__runtime)->graphics.ip.ver) << 8 | ((&
(gt->i915)->__runtime)->graphics.ip.rel)) >= ((12
) << 8 | (50)) ? intel_sseu_has_subslice(&(gt)->
info.sseu, 0, iter) : intel_sseu_has_subslice(&(gt)->info
.sseu, slice, subslice)))) {} else
366 num_tot_regs += num_steer_regs;
367
368 if (!num_tot_regs)
369 return;
370
371 /* allocate an extra for an end marker */
372 extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL(0x0001 | 0x0004));
373 if (!extlists)
374 return;
375
376 if (__alloc_ext_regs(&extlists[0], list, num_tot_regs)) {
377 kfree(extlists);
378 return;
379 }
380
381 extarray = extlists[0].extlist;
382 for_each_ss_steering(iter, gt, slice, subslice)for (iter = 0, intel_gt_mcr_get_ss_steering(gt, 0, &slice
, &subslice); iter < (2 * 32); iter++, intel_gt_mcr_get_ss_steering
(gt, iter, &slice, &subslice)) if (!(( (((&(gt->
i915)->__runtime)->graphics.ip.ver) << 8 | ((&
(gt->i915)->__runtime)->graphics.ip.rel)) >= ((12
) << 8 | (50)) ? intel_sseu_has_subslice(&(gt)->
info.sseu, 0, iter) : intel_sseu_has_subslice(&(gt)->info
.sseu, slice, subslice)))) {} else {
383 for (i = 0; i < ARRAY_SIZE(xe_extregs)(sizeof((xe_extregs)) / sizeof((xe_extregs)[0])); ++i) {
384 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice);
385 ++extarray;
386 }
387 if (__has_xehpg_extregs(ipver)) {
388 for (i = 0; i < ARRAY_SIZE(xehpg_extregs)(sizeof((xehpg_extregs)) / sizeof((xehpg_extregs)[0])); ++i) {
389 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice);
390 ++extarray;
391 }
392 }
393 }
394
395 drm_dbg(&i915->drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC-capture found %d-ext-regs.\n"
, num_tot_regs);
396 guc->capture->extlists = extlists;
397}
398
399static const struct __guc_mmio_reg_descr_group *
400guc_capture_get_device_reglist(struct intel_guc *guc)
401{
402 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
403
404 if (GRAPHICS_VER(i915)((&(i915)->__runtime)->graphics.ip.ver) > 11) {
405 /*
406 * For certain engine classes, there are slice and subslice
407 * level registers requiring steering. We allocate and populate
408 * these at init time based on hw config add it as an extension
409 * list at the end of the pre-populated render list.
410 */
411 if (IS_DG2(i915)IS_PLATFORM(i915, INTEL_DG2))
412 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 55)((12) << 8 | (55)));
413 else if (IS_XEHPSDV(i915)IS_PLATFORM(i915, INTEL_XEHPSDV))
414 guc_capture_alloc_steered_lists_xe_hpg(guc, xe_lpd_lists, IP_VER(12, 50)((12) << 8 | (50)));
415 else
416 guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists);
417
418 return xe_lpd_lists;
419 }
420
421 /* if GuC submission is enabled on a non-POR platform, just use a common baseline */
422 return default_lists;
423}
424
425static const char *
426__stringify_type(u32 type)
427{
428 switch (type) {
429 case GUC_CAPTURE_LIST_TYPE_GLOBAL:
430 return "Global";
431 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS:
432 return "Class";
433 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE:
434 return "Instance";
435 default:
436 break;
437 }
438
439 return "unknown";
440}
441
442static const char *
443__stringify_engclass(u32 class)
444{
445 switch (class) {
446 case GUC_RENDER_CLASS0:
447 return "Render";
448 case GUC_VIDEO_CLASS1:
449 return "Video";
450 case GUC_VIDEOENHANCE_CLASS2:
451 return "VideoEnhance";
452 case GUC_BLITTER_CLASS3:
453 return "Blitter";
454 case GUC_COMPUTE_CLASS4:
455 return "Compute";
456 default:
457 break;
458 }
459
460 return "unknown";
461}
462
463static int
464guc_capture_list_init(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
465 struct guc_mmio_reg *ptr, u16 num_entries)
466{
467 u32 i = 0, j = 0;
468 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
469 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists;
470 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists;
471 const struct __guc_mmio_reg_descr_group *match;
472 struct __guc_mmio_reg_descr_group *matchext;
473
474 if (!reglists)
475 return -ENODEV19;
476
477 match = guc_capture_get_one_list(reglists, owner, type, classid);
478 if (!match)
479 return -ENODATA91;
480
481 for (i = 0; i < num_entries && i < match->num_regs; ++i) {
482 ptr[i].offset = match->list[i].reg.reg;
483 ptr[i].value = 0xDEADF00D;
484 ptr[i].flags = match->list[i].flags;
485 ptr[i].mask = match->list[i].mask;
486 }
487
488 matchext = guc_capture_get_one_ext_list(extlists, owner, type, classid);
489 if (matchext) {
490 for (i = match->num_regs, j = 0; i < num_entries &&
491 i < (match->num_regs + matchext->num_regs) &&
492 j < matchext->num_regs; ++i, ++j) {
493 ptr[i].offset = matchext->extlist[j].reg.reg;
494 ptr[i].value = 0xDEADF00D;
495 ptr[i].flags = matchext->extlist[j].flags;
496 ptr[i].mask = matchext->extlist[j].mask;
497 }
498 }
499 if (i < num_entries)
500 drm_dbg(&i915->drm, "GuC-capture: Init reglist short %d out %d.\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC-capture: Init reglist short %d out %d.\n"
, (int)i, (int)num_entries)
501 (int)i, (int)num_entries)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC-capture: Init reglist short %d out %d.\n"
, (int)i, (int)num_entries);
502
503 return 0;
504}
505
506static int
507guc_cap_list_num_regs(struct intel_guc_state_capture *gc, u32 owner, u32 type, u32 classid)
508{
509 const struct __guc_mmio_reg_descr_group *match;
510 struct __guc_mmio_reg_descr_group *matchext;
511 int num_regs;
512
513 match = guc_capture_get_one_list(gc->reglists, owner, type, classid);
514 if (!match)
515 return 0;
516
517 num_regs = match->num_regs;
518
519 matchext = guc_capture_get_one_ext_list(gc->extlists, owner, type, classid);
520 if (matchext)
521 num_regs += matchext->num_regs;
522
523 return num_regs;
524}
525
526static int
527guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
528 size_t *size, bool_Bool is_purpose_est)
529{
530 struct intel_guc_state_capture *gc = guc->capture;
531 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
532 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
533 int num_regs;
534
535 if (!gc->reglists) {
536 drm_warn(&i915->drm, "GuC-capture: No reglist on this device\n")printf("drm:pid%d:%s *WARNING* " "[drm] " "GuC-capture: No reglist on this device\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
537 return -ENODEV19;
538 }
539
540 if (cache->is_valid) {
541 *size = cache->size;
542 return cache->status;
543 }
544
545 if (!is_purpose_est && owner == GUC_CAPTURE_LIST_INDEX_PF &&
546 !guc_capture_get_one_list(gc->reglists, owner, type, classid)) {
547 if (type == GUC_CAPTURE_LIST_TYPE_GLOBAL)
548 drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist Global!\n")printf("drm:pid%d:%s *WARNING* " "[drm] " "Missing GuC-Err-Cap reglist Global!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
549 else
550 drm_warn(&i915->drm, "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n",printf("drm:pid%d:%s *WARNING* " "[drm] " "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __stringify_type
(type), type, __stringify_engclass(classid), classid)
551 __stringify_type(type), type,printf("drm:pid%d:%s *WARNING* " "[drm] " "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __stringify_type
(type), type, __stringify_engclass(classid), classid)
552 __stringify_engclass(classid), classid)printf("drm:pid%d:%s *WARNING* " "[drm] " "Missing GuC-Err-Cap reglist %s(%u):%s(%u)!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __stringify_type
(type), type, __stringify_engclass(classid), classid);
553 return -ENODATA91;
554 }
555
556 num_regs = guc_cap_list_num_regs(gc, owner, type, classid);
557 /* intentional empty lists can exist depending on hw config */
558 if (!num_regs)
559 return -ENODATA91;
560
561 if (size)
562 *size = PAGE_ALIGN((sizeof(struct guc_debug_capture_list)) +((((sizeof(struct guc_debug_capture_list)) + (num_regs * sizeof
(struct guc_mmio_reg))) + ((1 << 12) - 1)) & ~((1 <<
12) - 1))
563 (num_regs * sizeof(struct guc_mmio_reg)))((((sizeof(struct guc_debug_capture_list)) + (num_regs * sizeof
(struct guc_mmio_reg))) + ((1 << 12) - 1)) & ~((1 <<
12) - 1));
564
565 return 0;
566}
567
568int
569intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
570 size_t *size)
571{
572 return guc_capture_getlistsize(guc, owner, type, classid, size, false0);
573}
574
575static void guc_capture_create_prealloc_nodes(struct intel_guc *guc);
576
577int
578intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 classid,
579 void **outptr)
580{
581 struct intel_guc_state_capture *gc = guc->capture;
582 struct __guc_capture_ads_cache *cache = &gc->ads_cache[owner][type][classid];
583 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
584 struct guc_debug_capture_list *listnode;
585 int ret, num_regs;
586 u8 *caplist, *tmp;
587 size_t size = 0;
588
589 if (!gc->reglists)
590 return -ENODEV19;
591
592 if (cache->is_valid) {
593 *outptr = cache->ptr;
594 return cache->status;
595 }
596
597 /*
598 * ADS population of input registers is a good
599 * time to pre-allocate cachelist output nodes
600 */
601 guc_capture_create_prealloc_nodes(guc);
602
603 ret = intel_guc_capture_getlistsize(guc, owner, type, classid, &size);
604 if (ret) {
605 cache->is_valid = true1;
606 cache->ptr = NULL((void *)0);
607 cache->size = 0;
608 cache->status = ret;
609 return ret;
610 }
611
612 caplist = kzalloc(size, GFP_KERNEL(0x0001 | 0x0004));
613 if (!caplist) {
614 drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached caplist")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC-capture: failed to alloc cached caplist"
);
615 return -ENOMEM12;
616 }
617
618 /* populate capture list header */
619 tmp = caplist;
620 num_regs = guc_cap_list_num_regs(guc->capture, owner, type, classid);
621 listnode = (struct guc_debug_capture_list *)tmp;
622 listnode->header.info = FIELD_PREP(GUC_CAPTURELISTHDR_NUMDESCR, (u32)num_regs)(((typeof((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(0)))))((u32)num_regs) << (__builtin_ffsll((((~0UL) >>
(64 - (15) - 1)) & ((~0UL) << (0)))) - 1)) & (
(((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (0)
))));
623
624 /* populate list of register descriptor */
625 tmp += sizeof(struct guc_debug_capture_list);
626 guc_capture_list_init(guc, owner, type, classid, (struct guc_mmio_reg *)tmp, num_regs);
627
628 /* cache this list */
629 cache->is_valid = true1;
630 cache->ptr = caplist;
631 cache->size = size;
632 cache->status = 0;
633
634 *outptr = caplist;
635
636 return 0;
637}
638
639int
640intel_guc_capture_getnullheader(struct intel_guc *guc,
641 void **outptr, size_t *size)
642{
643 struct intel_guc_state_capture *gc = guc->capture;
644 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
645 int tmp = sizeof(u32) * 4;
646 void *null_header;
647
648 if (gc->ads_null_cache) {
649 *outptr = gc->ads_null_cache;
650 *size = tmp;
651 return 0;
652 }
653
654 null_header = kzalloc(tmp, GFP_KERNEL(0x0001 | 0x0004));
655 if (!null_header) {
656 drm_dbg(&i915->drm, "GuC-capture: failed to alloc cached nulllist")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC-capture: failed to alloc cached nulllist"
);
657 return -ENOMEM12;
658 }
659
660 gc->ads_null_cache = null_header;
661 *outptr = null_header;
662 *size = tmp;
663
664 return 0;
665}
666
667static int
668guc_capture_output_min_size_est(struct intel_guc *guc)
669{
670 struct intel_gt *gt = guc_to_gt(guc);
671 struct intel_engine_cs *engine;
672 enum intel_engine_id id;
673 int worst_min_size = 0;
674 size_t tmp = 0;
675
676 if (!guc->capture)
677 return -ENODEV19;
678
679 /*
680 * If every single engine-instance suffered a failure in quick succession but
681 * were all unrelated, then a burst of multiple error-capture events would dump
682 * registers for every one engine instance, one at a time. In this case, GuC
683 * would even dump the global-registers repeatedly.
684 *
685 * For each engine instance, there would be 1 x guc_state_capture_group_t output
686 * followed by 3 x guc_state_capture_t lists. The latter is how the register
687 * dumps are split across different register types (where the '3' are global vs class
688 * vs instance).
689 */
690 for_each_engine(engine, gt, id)for ((id) = 0; (id) < I915_NUM_ENGINES; (id)++) if (!((engine
) = (gt)->engine[(id)])) {} else {
691 worst_min_size += sizeof(struct guc_state_capture_group_header_t) +
692 (3 * sizeof(struct guc_state_capture_header_t));
693
694 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, &tmp, true1))
695 worst_min_size += tmp;
696
697 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
698 engine->class, &tmp, true1)) {
699 worst_min_size += tmp;
700 }
701 if (!guc_capture_getlistsize(guc, 0, GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE,
702 engine->class, &tmp, true1)) {
703 worst_min_size += tmp;
704 }
705 }
706
707 return worst_min_size;
708}
709
710/*
711 * Add on a 3x multiplier to allow for multiple back-to-back captures occurring
712 * before the i915 can read the data out and process it
713 */
714#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER3 3
715
716static void check_guc_capture_size(struct intel_guc *guc)
717{
718 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
719 int min_size = guc_capture_output_min_size_est(guc);
720 int spare_size = min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER3;
721 u32 buffer_size = intel_guc_log_section_size_capture(&guc->log);
722
723 /*
724 * NOTE: min_size is much smaller than the capture region allocation (DG2: <80K vs 1MB)
725 * Additionally, its based on space needed to fit all engines getting reset at once
726 * within the same G2H handler task slot. This is very unlikely. However, if GuC really
727 * does run out of space for whatever reason, we will see an separate warning message
728 * when processing the G2H event capture-notification, search for:
729 * INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE.
730 */
731 if (min_size < 0)
732 drm_warn(&i915->drm, "Failed to calculate GuC error state capture buffer minimum size: %d!\n",printf("drm:pid%d:%s *WARNING* " "[drm] " "Failed to calculate GuC error state capture buffer minimum size: %d!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , min_size
)
733 min_size)printf("drm:pid%d:%s *WARNING* " "[drm] " "Failed to calculate GuC error state capture buffer minimum size: %d!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , min_size
);
734 else if (min_size > buffer_size)
735 drm_warn(&i915->drm, "GuC error state capture buffer maybe small: %d < %d\n",printf("drm:pid%d:%s *WARNING* " "[drm] " "GuC error state capture buffer maybe small: %d < %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , buffer_size
, min_size)
736 buffer_size, min_size)printf("drm:pid%d:%s *WARNING* " "[drm] " "GuC error state capture buffer maybe small: %d < %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , buffer_size
, min_size);
737 else if (spare_size > buffer_size)
738 drm_dbg(&i915->drm, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n"
, buffer_size, spare_size, min_size)
739 buffer_size, spare_size, min_size)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC error state capture buffer lacks spare size: %d < %d (min = %d)\n"
, buffer_size, spare_size, min_size);
740}
741
742/*
743 * KMD Init time flows:
744 * --------------------
745 * --> alloc A: GuC input capture regs lists (registered to GuC via ADS).
746 * intel_guc_ads acquires the register lists by calling
747 * intel_guc_capture_list_size and intel_guc_capture_list_get 'n' times,
748 * where n = 1 for global-reg-list +
749 * num_engine_classes for class-reg-list +
750 * num_engine_classes for instance-reg-list
751 * (since all instances of the same engine-class type
752 * have an identical engine-instance register-list).
753 * ADS module also calls separately for PF vs VF.
754 *
755 * --> alloc B: GuC output capture buf (registered via guc_init_params(log_param))
756 * Size = #define CAPTURE_BUFFER_SIZE (warns if on too-small)
757 * Note2: 'x 3' to hold multiple capture groups
758 *
759 * GUC Runtime notify capture:
760 * --------------------------
761 * --> G2H STATE_CAPTURE_NOTIFICATION
762 * L--> intel_guc_capture_process
763 * L--> Loop through B (head..tail) and for each engine instance's
764 * err-state-captured register-list we find, we alloc 'C':
765 * --> alloc C: A capture-output-node structure that includes misc capture info along
766 * with 3 register list dumps (global, engine-class and engine-instance)
767 * This node is created from a pre-allocated list of blank nodes in
768 * guc->capture->cachelist and populated with the error-capture
769 * data from GuC and then it's added into guc->capture->outlist linked
770 * list. This list is used for matchup and printout by i915_gpu_coredump
771 * and err_print_gt, (when user invokes the error capture sysfs).
772 *
773 * GUC --> notify context reset:
774 * -----------------------------
775 * --> G2H CONTEXT RESET
776 * L--> guc_handle_context_reset --> i915_capture_error_state
777 * L--> i915_gpu_coredump(..IS_GUC_CAPTURE) --> gt_record_engines
778 * --> capture_engine(..IS_GUC_CAPTURE)
779 * L--> intel_guc_capture_get_matching_node is where
780 * detach C from internal linked list and add it into
781 * intel_engine_coredump struct (if the context and
782 * engine of the event notification matches a node
783 * in the link list).
784 *
785 * User Sysfs / Debugfs
786 * --------------------
787 * --> i915_gpu_coredump_copy_to_buffer->
788 * L--> err_print_to_sgl --> err_print_gt
789 * L--> error_print_guc_captures
790 * L--> intel_guc_capture_print_node prints the
791 * register lists values of the attached node
792 * on the error-engine-dump being reported.
793 * L--> i915_reset_error_state ... -->__i915_gpu_coredump_free
794 * L--> ... cleanup_gt -->
795 * L--> intel_guc_capture_free_node returns the
796 * capture-output-node back to the internal
797 * cachelist for reuse.
798 *
799 */
800
801static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf)
802{
803 if (buf->wr >= buf->rd)
804 return (buf->wr - buf->rd);
805 return (buf->size - buf->rd) + buf->wr;
806}
807
808static int guc_capture_buf_cnt_to_end(struct __guc_capture_bufstate *buf)
809{
810 if (buf->rd > buf->wr)
811 return (buf->size - buf->rd);
812 return (buf->wr - buf->rd);
813}
814
815/*
816 * GuC's error-capture output is a ring buffer populated in a byte-stream fashion:
817 *
818 * The GuC Log buffer region for error-capture is managed like a ring buffer.
819 * The GuC firmware dumps error capture logs into this ring in a byte-stream flow.
820 * Additionally, as per the current and foreseeable future, all packed error-
821 * capture output structures are dword aligned.
822 *
823 * That said, if the GuC firmware is in the midst of writing a structure that is larger
824 * than one dword but the tail end of the err-capture buffer-region has lesser space left,
825 * we would need to extract that structure one dword at a time straddled across the end,
826 * onto the start of the ring.
827 *
828 * Below function, guc_capture_log_remove_dw is a helper for that. All callers of this
829 * function would typically do a straight-up memcpy from the ring contents and will only
830 * call this helper if their structure-extraction is straddling across the end of the
831 * ring. GuC firmware does not add any padding. The reason for the no-padding is to ease
832 * scalability for future expansion of output data types without requiring a redesign
833 * of the flow controls.
834 */
835static int
836guc_capture_log_remove_dw(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
837 u32 *dw)
838{
839 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
840 int tries = 2;
841 int avail = 0;
842 u32 *src_data;
843
844 if (!guc_capture_buf_cnt(buf))
845 return 0;
846
847 while (tries--) {
848 avail = guc_capture_buf_cnt_to_end(buf);
849 if (avail >= sizeof(u32)) {
850 src_data = (u32 *)(buf->data + buf->rd);
851 *dw = *src_data;
852 buf->rd += 4;
853 return 4;
854 }
855 if (avail)
856 drm_dbg(&i915->drm, "GuC-Cap-Logs not dword aligned, skipping.\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC-Cap-Logs not dword aligned, skipping.\n"
);
857 buf->rd = 0;
858 }
859
860 return 0;
861}
862
863static bool_Bool
864guc_capture_data_extracted(struct __guc_capture_bufstate *b,
865 int size, void *dest)
866{
867 if (guc_capture_buf_cnt_to_end(b) >= size) {
868 memcpy(dest, (b->data + b->rd), size)__builtin_memcpy((dest), ((b->data + b->rd)), (size));
869 b->rd += size;
870 return true1;
871 }
872 return false0;
873}
874
875static int
876guc_capture_log_get_group_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
877 struct guc_state_capture_group_header_t *ghdr)
878{
879 int read = 0;
880 int fullsize = sizeof(struct guc_state_capture_group_header_t);
881
882 if (fullsize > guc_capture_buf_cnt(buf))
883 return -1;
884
885 if (guc_capture_data_extracted(buf, fullsize, (void *)ghdr))
886 return 0;
887
888 read += guc_capture_log_remove_dw(guc, buf, &ghdr->owner);
889 read += guc_capture_log_remove_dw(guc, buf, &ghdr->info);
890 if (read != fullsize)
891 return -1;
892
893 return 0;
894}
895
896static int
897guc_capture_log_get_data_hdr(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
898 struct guc_state_capture_header_t *hdr)
899{
900 int read = 0;
901 int fullsize = sizeof(struct guc_state_capture_header_t);
902
903 if (fullsize > guc_capture_buf_cnt(buf))
904 return -1;
905
906 if (guc_capture_data_extracted(buf, fullsize, (void *)hdr))
907 return 0;
908
909 read += guc_capture_log_remove_dw(guc, buf, &hdr->owner);
910 read += guc_capture_log_remove_dw(guc, buf, &hdr->info);
911 read += guc_capture_log_remove_dw(guc, buf, &hdr->lrca);
912 read += guc_capture_log_remove_dw(guc, buf, &hdr->guc_id);
913 read += guc_capture_log_remove_dw(guc, buf, &hdr->num_mmios);
914 if (read != fullsize)
915 return -1;
916
917 return 0;
918}
919
920static int
921guc_capture_log_get_register(struct intel_guc *guc, struct __guc_capture_bufstate *buf,
922 struct guc_mmio_reg *reg)
923{
924 int read = 0;
925 int fullsize = sizeof(struct guc_mmio_reg);
926
927 if (fullsize > guc_capture_buf_cnt(buf))
928 return -1;
929
930 if (guc_capture_data_extracted(buf, fullsize, (void *)reg))
931 return 0;
932
933 read += guc_capture_log_remove_dw(guc, buf, &reg->offset);
934 read += guc_capture_log_remove_dw(guc, buf, &reg->value);
935 read += guc_capture_log_remove_dw(guc, buf, &reg->flags);
936 read += guc_capture_log_remove_dw(guc, buf, &reg->mask);
937 if (read != fullsize)
938 return -1;
939
940 return 0;
941}
942
943static void
944guc_capture_delete_one_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node)
945{
946 int i;
947
948 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i)
949 kfree(node->reginfo[i].regs);
950 list_del(&node->link);
951 kfree(node);
952}
953
954static void
955guc_capture_delete_prealloc_nodes(struct intel_guc *guc)
956{
957 struct __guc_capture_parsed_output *n, *ntmp;
958
959 /*
960 * NOTE: At the end of driver operation, we must assume that we
961 * have prealloc nodes in both the cachelist as well as outlist
962 * if unclaimed error capture events occurred prior to shutdown.
963 */
964 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link)for (n = ({ const __typeof( ((__typeof(*n) *)0)->link ) *__mptr
= ((&guc->capture->outlist)->next); (__typeof(*
n) *)( (char *)__mptr - __builtin_offsetof(__typeof(*n), link
) );}), ntmp = ({ const __typeof( ((__typeof(*n) *)0)->link
) *__mptr = (n->link.next); (__typeof(*n) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*n), link) );}); &n->link
!= (&guc->capture->outlist); n = ntmp, ntmp = ({ const
__typeof( ((__typeof(*ntmp) *)0)->link ) *__mptr = (ntmp->
link.next); (__typeof(*ntmp) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*ntmp), link) );}))
965 guc_capture_delete_one_node(guc, n);
966
967 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link)for (n = ({ const __typeof( ((__typeof(*n) *)0)->link ) *__mptr
= ((&guc->capture->cachelist)->next); (__typeof
(*n) *)( (char *)__mptr - __builtin_offsetof(__typeof(*n), link
) );}), ntmp = ({ const __typeof( ((__typeof(*n) *)0)->link
) *__mptr = (n->link.next); (__typeof(*n) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*n), link) );}); &n->link
!= (&guc->capture->cachelist); n = ntmp, ntmp = ({
const __typeof( ((__typeof(*ntmp) *)0)->link ) *__mptr = (
ntmp->link.next); (__typeof(*ntmp) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*ntmp), link) );}))
968 guc_capture_delete_one_node(guc, n);
969}
970
971static void
972guc_capture_add_node_to_list(struct __guc_capture_parsed_output *node,
973 struct list_head *list)
974{
975 list_add_tail(&node->link, list);
976}
977
978static void
979guc_capture_add_node_to_outlist(struct intel_guc_state_capture *gc,
980 struct __guc_capture_parsed_output *node)
981{
982 guc_capture_add_node_to_list(node, &gc->outlist);
983}
984
985static void
986guc_capture_add_node_to_cachelist(struct intel_guc_state_capture *gc,
987 struct __guc_capture_parsed_output *node)
988{
989 guc_capture_add_node_to_list(node, &gc->cachelist);
990}
991
992static void
993guc_capture_init_node(struct intel_guc *guc, struct __guc_capture_parsed_output *node)
994{
995 struct guc_mmio_reg *tmp[GUC_CAPTURE_LIST_TYPE_MAX];
996 int i;
997
998 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) {
999 tmp[i] = node->reginfo[i].regs;
1000 memset(tmp[i], 0, sizeof(struct guc_mmio_reg) *__builtin_memset((tmp[i]), (0), (sizeof(struct guc_mmio_reg) *
guc->capture->max_mmio_per_node))
1001 guc->capture->max_mmio_per_node)__builtin_memset((tmp[i]), (0), (sizeof(struct guc_mmio_reg) *
guc->capture->max_mmio_per_node));
1002 }
1003 memset(node, 0, sizeof(*node))__builtin_memset((node), (0), (sizeof(*node)));
1004 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i)
1005 node->reginfo[i].regs = tmp[i];
1006
1007 INIT_LIST_HEAD(&node->link);
1008}
1009
1010static struct __guc_capture_parsed_output *
1011guc_capture_get_prealloc_node(struct intel_guc *guc)
1012{
1013 struct __guc_capture_parsed_output *found = NULL((void *)0);
1014
1015 if (!list_empty(&guc->capture->cachelist)) {
1016 struct __guc_capture_parsed_output *n, *ntmp;
1017
1018 /* get first avail node from the cache list */
1019 list_for_each_entry_safe(n, ntmp, &guc->capture->cachelist, link)for (n = ({ const __typeof( ((__typeof(*n) *)0)->link ) *__mptr
= ((&guc->capture->cachelist)->next); (__typeof
(*n) *)( (char *)__mptr - __builtin_offsetof(__typeof(*n), link
) );}), ntmp = ({ const __typeof( ((__typeof(*n) *)0)->link
) *__mptr = (n->link.next); (__typeof(*n) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*n), link) );}); &n->link
!= (&guc->capture->cachelist); n = ntmp, ntmp = ({
const __typeof( ((__typeof(*ntmp) *)0)->link ) *__mptr = (
ntmp->link.next); (__typeof(*ntmp) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*ntmp), link) );})) {
1020 found = n;
1021 list_del(&n->link);
1022 break;
1023 }
1024 } else {
1025 struct __guc_capture_parsed_output *n, *ntmp;
1026
1027 /* traverse down and steal back the oldest node already allocated */
1028 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link)for (n = ({ const __typeof( ((__typeof(*n) *)0)->link ) *__mptr
= ((&guc->capture->outlist)->next); (__typeof(*
n) *)( (char *)__mptr - __builtin_offsetof(__typeof(*n), link
) );}), ntmp = ({ const __typeof( ((__typeof(*n) *)0)->link
) *__mptr = (n->link.next); (__typeof(*n) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*n), link) );}); &n->link
!= (&guc->capture->outlist); n = ntmp, ntmp = ({ const
__typeof( ((__typeof(*ntmp) *)0)->link ) *__mptr = (ntmp->
link.next); (__typeof(*ntmp) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*ntmp), link) );})) {
1029 found = n;
1030 }
1031 if (found)
1032 list_del(&found->link);
1033 }
1034 if (found)
1035 guc_capture_init_node(guc, found);
1036
1037 return found;
1038}
1039
1040static struct __guc_capture_parsed_output *
1041guc_capture_alloc_one_node(struct intel_guc *guc)
1042{
1043 struct __guc_capture_parsed_output *new;
1044 int i;
1045
1046 new = kzalloc(sizeof(*new), GFP_KERNEL(0x0001 | 0x0004));
1047 if (!new)
1048 return NULL((void *)0);
1049
1050 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) {
1051 new->reginfo[i].regs = kcalloc(guc->capture->max_mmio_per_node,
1052 sizeof(struct guc_mmio_reg), GFP_KERNEL(0x0001 | 0x0004));
1053 if (!new->reginfo[i].regs) {
1054 while (i)
1055 kfree(new->reginfo[--i].regs);
1056 kfree(new);
1057 return NULL((void *)0);
1058 }
1059 }
1060 guc_capture_init_node(guc, new);
1061
1062 return new;
1063}
1064
1065static struct __guc_capture_parsed_output *
1066guc_capture_clone_node(struct intel_guc *guc, struct __guc_capture_parsed_output *original,
1067 u32 keep_reglist_mask)
1068{
1069 struct __guc_capture_parsed_output *new;
1070 int i;
1071
1072 new = guc_capture_get_prealloc_node(guc);
1073 if (!new)
1074 return NULL((void *)0);
1075 if (!original)
1076 return new;
1077
1078 new->is_partial = original->is_partial;
1079
1080 /* copy reg-lists that we want to clone */
1081 for (i = 0; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) {
1082 if (keep_reglist_mask & BIT(i)(1UL << (i))) {
1083 GEM_BUG_ON(original->reginfo[i].num_regs >((void)0)
1084 guc->capture->max_mmio_per_node)((void)0);
1085
1086 memcpy(new->reginfo[i].regs, original->reginfo[i].regs,__builtin_memcpy((new->reginfo[i].regs), (original->reginfo
[i].regs), (original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg
)))
1087 original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg))__builtin_memcpy((new->reginfo[i].regs), (original->reginfo
[i].regs), (original->reginfo[i].num_regs * sizeof(struct guc_mmio_reg
)));
1088
1089 new->reginfo[i].num_regs = original->reginfo[i].num_regs;
1090 new->reginfo[i].vfid = original->reginfo[i].vfid;
1091
1092 if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS) {
1093 new->eng_class = original->eng_class;
1094 } else if (i == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) {
1095 new->eng_inst = original->eng_inst;
1096 new->guc_id = original->guc_id;
1097 new->lrca = original->lrca;
1098 }
1099 }
1100 }
1101
1102 return new;
1103}
1104
1105static void
1106__guc_capture_create_prealloc_nodes(struct intel_guc *guc)
1107{
1108 struct __guc_capture_parsed_output *node = NULL((void *)0);
1109 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
1110 int i;
1111
1112 for (i = 0; i < PREALLOC_NODES_MAX_COUNT(3 * 16 * 32); ++i) {
1113 node = guc_capture_alloc_one_node(guc);
1114 if (!node) {
1115 drm_warn(&i915->drm, "GuC Capture pre-alloc-cache failure\n")printf("drm:pid%d:%s *WARNING* " "[drm] " "GuC Capture pre-alloc-cache failure\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1116 /* dont free the priors, use what we got and cleanup at shutdown */
1117 return;
1118 }
1119 guc_capture_add_node_to_cachelist(guc->capture, node);
1120 }
1121}
1122
1123static int
1124guc_get_max_reglist_count(struct intel_guc *guc)
1125{
1126 int i, j, k, tmp, maxregcount = 0;
1127
1128 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) {
1129 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) {
1130 for (k = 0; k < GUC_MAX_ENGINE_CLASSES16; ++k) {
1131 if (j == GUC_CAPTURE_LIST_TYPE_GLOBAL && k > 0)
1132 continue;
1133
1134 tmp = guc_cap_list_num_regs(guc->capture, i, j, k);
1135 if (tmp > maxregcount)
1136 maxregcount = tmp;
1137 }
1138 }
1139 }
1140 if (!maxregcount)
1141 maxregcount = PREALLOC_NODES_DEFAULT_NUMREGS64;
1142
1143 return maxregcount;
1144}
1145
1146static void
1147guc_capture_create_prealloc_nodes(struct intel_guc *guc)
1148{
1149 /* skip if we've already done the pre-alloc */
1150 if (guc->capture->max_mmio_per_node)
1151 return;
1152
1153 guc->capture->max_mmio_per_node = guc_get_max_reglist_count(guc);
1154 __guc_capture_create_prealloc_nodes(guc);
1155}
1156
1157static int
1158guc_capture_extract_reglists(struct intel_guc *guc, struct __guc_capture_bufstate *buf)
1159{
1160 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
1161 struct guc_state_capture_group_header_t ghdr = {0};
1162 struct guc_state_capture_header_t hdr = {0};
1163 struct __guc_capture_parsed_output *node = NULL((void *)0);
1164 struct guc_mmio_reg *regs = NULL((void *)0);
1165 int i, numlists, numregs, ret = 0;
1166 enum guc_capture_type datatype;
1167 struct guc_mmio_reg tmp;
1168 bool_Bool is_partial = false0;
1169
1170 i = guc_capture_buf_cnt(buf);
1171 if (!i)
1172 return -ENODATA91;
1173 if (i % sizeof(u32)) {
1174 drm_warn(&i915->drm, "GuC Capture new entries unaligned\n")printf("drm:pid%d:%s *WARNING* " "[drm] " "GuC Capture new entries unaligned\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1175 ret = -EIO5;
1176 goto bailout;
1177 }
1178
1179 /* first get the capture group header */
1180 if (guc_capture_log_get_group_hdr(guc, buf, &ghdr)) {
1181 ret = -EIO5;
1182 goto bailout;
1183 }
1184 /*
1185 * we would typically expect a layout as below where n would be expected to be
1186 * anywhere between 3 to n where n > 3 if we are seeing multiple dependent engine
1187 * instances being reset together.
1188 * ____________________________________________
1189 * | Capture Group |
1190 * | ________________________________________ |
1191 * | | Capture Group Header: | |
1192 * | | - num_captures = 5 | |
1193 * | |______________________________________| |
1194 * | ________________________________________ |
1195 * | | Capture1: | |
1196 * | | Hdr: GLOBAL, numregs=a | |
1197 * | | ____________________________________ | |
1198 * | | | Reglist | | |
1199 * | | | - reg1, reg2, ... rega | | |
1200 * | | |__________________________________| | |
1201 * | |______________________________________| |
1202 * | ________________________________________ |
1203 * | | Capture2: | |
1204 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=b| |
1205 * | | ____________________________________ | |
1206 * | | | Reglist | | |
1207 * | | | - reg1, reg2, ... regb | | |
1208 * | | |__________________________________| | |
1209 * | |______________________________________| |
1210 * | ________________________________________ |
1211 * | | Capture3: | |
1212 * | | Hdr: INSTANCE=RCS, numregs=c | |
1213 * | | ____________________________________ | |
1214 * | | | Reglist | | |
1215 * | | | - reg1, reg2, ... regc | | |
1216 * | | |__________________________________| | |
1217 * | |______________________________________| |
1218 * | ________________________________________ |
1219 * | | Capture4: | |
1220 * | | Hdr: CLASS=RENDER/COMPUTE, numregs=d| |
1221 * | | ____________________________________ | |
1222 * | | | Reglist | | |
1223 * | | | - reg1, reg2, ... regd | | |
1224 * | | |__________________________________| | |
1225 * | |______________________________________| |
1226 * | ________________________________________ |
1227 * | | Capture5: | |
1228 * | | Hdr: INSTANCE=CCS0, numregs=e | |
1229 * | | ____________________________________ | |
1230 * | | | Reglist | | |
1231 * | | | - reg1, reg2, ... rege | | |
1232 * | | |__________________________________| | |
1233 * | |______________________________________| |
1234 * |__________________________________________|
1235 */
1236 is_partial = FIELD_GET(CAP_GRP_HDR_CAPTURE_TYPE, ghdr.info)((typeof((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(8)))))(((ghdr.info) & ((((~0UL) >> (64 - (15) - 1
)) & ((~0UL) << (8))))) >> (__builtin_ffsll((
((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (8))
)) - 1)));
1237 numlists = FIELD_GET(CAP_GRP_HDR_NUM_CAPTURES, ghdr.info)((typeof((((~0UL) >> (64 - (7) - 1)) & ((~0UL) <<
(0)))))(((ghdr.info) & ((((~0UL) >> (64 - (7) - 1)
) & ((~0UL) << (0))))) >> (__builtin_ffsll(((
(~0UL) >> (64 - (7) - 1)) & ((~0UL) << (0))))
- 1)));
1238
1239 while (numlists--) {
1240 if (guc_capture_log_get_data_hdr(guc, buf, &hdr)) {
1241 ret = -EIO5;
1242 break;
1243 }
1244
1245 datatype = FIELD_GET(CAP_HDR_CAPTURE_TYPE, hdr.info)((typeof((((~0UL) >> (64 - (3) - 1)) & ((~0UL) <<
(0)))))(((hdr.info) & ((((~0UL) >> (64 - (3) - 1))
& ((~0UL) << (0))))) >> (__builtin_ffsll((((
~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0)))) -
1)));
1246 if (datatype > GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE) {
1247 /* unknown capture type - skip over to next capture set */
1248 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios)((typeof((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0)))))(((hdr.num_mmios) & ((((~0UL) >> (64 - (9) -
1)) & ((~0UL) << (0))))) >> (__builtin_ffsll
((((~0UL) >> (64 - (9) - 1)) & ((~0UL) << (0)
))) - 1)));
1249 while (numregs--) {
1250 if (guc_capture_log_get_register(guc, buf, &tmp)) {
1251 ret = -EIO5;
1252 break;
1253 }
1254 }
1255 continue;
1256 } else if (node) {
1257 /*
1258 * Based on the current capture type and what we have so far,
1259 * decide if we should add the current node into the internal
1260 * linked list for match-up when i915_gpu_coredump calls later
1261 * (and alloc a blank node for the next set of reglists)
1262 * or continue with the same node or clone the current node
1263 * but only retain the global or class registers (such as the
1264 * case of dependent engine resets).
1265 */
1266 if (datatype == GUC_CAPTURE_LIST_TYPE_GLOBAL) {
1267 guc_capture_add_node_to_outlist(guc->capture, node);
1268 node = NULL((void *)0);
1269 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS &&
1270 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS].num_regs) {
1271 /* Add to list, clone node and duplicate global list */
1272 guc_capture_add_node_to_outlist(guc->capture, node);
1273 node = guc_capture_clone_node(guc, node,
1274 GCAP_PARSED_REGLIST_INDEX_GLOBAL(1UL << (GUC_CAPTURE_LIST_TYPE_GLOBAL)));
1275 } else if (datatype == GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE &&
1276 node->reginfo[GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE].num_regs) {
1277 /* Add to list, clone node and duplicate global + class lists */
1278 guc_capture_add_node_to_outlist(guc->capture, node);
1279 node = guc_capture_clone_node(guc, node,
1280 (GCAP_PARSED_REGLIST_INDEX_GLOBAL(1UL << (GUC_CAPTURE_LIST_TYPE_GLOBAL)) |
1281 GCAP_PARSED_REGLIST_INDEX_ENGCLASS(1UL << (GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS))));
1282 }
1283 }
1284
1285 if (!node) {
1286 node = guc_capture_get_prealloc_node(guc);
1287 if (!node) {
1288 ret = -ENOMEM12;
1289 break;
1290 }
1291 if (datatype != GUC_CAPTURE_LIST_TYPE_GLOBAL)
1292 drm_dbg(&i915->drm, "GuC Capture missing global dump: %08x!\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC Capture missing global dump: %08x!\n"
, datatype)
1293 datatype)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC Capture missing global dump: %08x!\n"
, datatype);
1294 }
1295 node->is_partial = is_partial;
1296 node->reginfo[datatype].vfid = FIELD_GET(CAP_HDR_CAPTURE_VFID, hdr.owner)((typeof((((~0UL) >> (64 - (7) - 1)) & ((~0UL) <<
(0)))))(((hdr.owner) & ((((~0UL) >> (64 - (7) - 1)
) & ((~0UL) << (0))))) >> (__builtin_ffsll(((
(~0UL) >> (64 - (7) - 1)) & ((~0UL) << (0))))
- 1)));
1297 switch (datatype) {
1298 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE:
1299 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info)((typeof((((~0UL) >> (64 - (7) - 1)) & ((~0UL) <<
(4)))))(((hdr.info) & ((((~0UL) >> (64 - (7) - 1))
& ((~0UL) << (4))))) >> (__builtin_ffsll((((
~0UL) >> (64 - (7) - 1)) & ((~0UL) << (4)))) -
1)));
1300 node->eng_inst = FIELD_GET(CAP_HDR_ENGINE_INSTANCE, hdr.info)((typeof((((~0UL) >> (64 - (11) - 1)) & ((~0UL) <<
(8)))))(((hdr.info) & ((((~0UL) >> (64 - (11) - 1)
) & ((~0UL) << (8))))) >> (__builtin_ffsll(((
(~0UL) >> (64 - (11) - 1)) & ((~0UL) << (8)))
) - 1)));
1301 node->lrca = hdr.lrca;
1302 node->guc_id = hdr.guc_id;
1303 break;
1304 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS:
1305 node->eng_class = FIELD_GET(CAP_HDR_ENGINE_CLASS, hdr.info)((typeof((((~0UL) >> (64 - (7) - 1)) & ((~0UL) <<
(4)))))(((hdr.info) & ((((~0UL) >> (64 - (7) - 1))
& ((~0UL) << (4))))) >> (__builtin_ffsll((((
~0UL) >> (64 - (7) - 1)) & ((~0UL) << (4)))) -
1)));
1306 break;
1307 default:
1308 break;
1309 }
1310
1311 numregs = FIELD_GET(CAP_HDR_NUM_MMIOS, hdr.num_mmios)((typeof((((~0UL) >> (64 - (9) - 1)) & ((~0UL) <<
(0)))))(((hdr.num_mmios) & ((((~0UL) >> (64 - (9) -
1)) & ((~0UL) << (0))))) >> (__builtin_ffsll
((((~0UL) >> (64 - (9) - 1)) & ((~0UL) << (0)
))) - 1)));
1312 if (numregs > guc->capture->max_mmio_per_node) {
1313 drm_dbg(&i915->drm, "GuC Capture list extraction clipped by prealloc!\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC Capture list extraction clipped by prealloc!\n"
);
1314 numregs = guc->capture->max_mmio_per_node;
1315 }
1316 node->reginfo[datatype].num_regs = numregs;
1317 regs = node->reginfo[datatype].regs;
1318 i = 0;
1319 while (numregs--) {
1320 if (guc_capture_log_get_register(guc, buf, &regs[i++])) {
1321 ret = -EIO5;
1322 break;
1323 }
1324 }
1325 }
1326
1327bailout:
1328 if (node) {
1329 /* If we have data, add to linked list for match-up when i915_gpu_coredump calls */
1330 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) {
1331 if (node->reginfo[i].regs) {
1332 guc_capture_add_node_to_outlist(guc->capture, node);
1333 node = NULL((void *)0);
1334 break;
1335 }
1336 }
1337 if (node) /* else return it back to cache list */
1338 guc_capture_add_node_to_cachelist(guc->capture, node);
1339 }
1340 return ret;
1341}
1342
1343static int __guc_capture_flushlog_complete(struct intel_guc *guc)
1344{
1345 u32 action[] = {
1346 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE,
1347 GUC_CAPTURE_LOG_BUFFER
1348 };
1349
1350 return intel_guc_send_nb(guc, action, ARRAY_SIZE(action)(sizeof((action)) / sizeof((action)[0])), 0);
1351
1352}
1353
1354static void __guc_capture_process_output(struct intel_guc *guc)
1355{
1356 unsigned int buffer_size, read_offset, write_offset, full_count;
1357 struct intel_uc *uc = container_of(guc, typeof(*uc), guc)({ const __typeof( ((typeof(*uc) *)0)->guc ) *__mptr = (guc
); (typeof(*uc) *)( (char *)__mptr - __builtin_offsetof(typeof
(*uc), guc) );});
1358 struct drm_i915_privateinteldrm_softc *i915 = guc_to_gt(guc)->i915;
1359 struct guc_log_buffer_state log_buf_state_local;
1360 struct guc_log_buffer_state *log_buf_state;
1361 struct __guc_capture_bufstate buf;
1362 void *src_data = NULL((void *)0);
1363 bool_Bool new_overflow;
1364 int ret;
1365
1366 log_buf_state = guc->log.buf_addr +
1367 (sizeof(struct guc_log_buffer_state) * GUC_CAPTURE_LOG_BUFFER);
1368 src_data = guc->log.buf_addr +
1369 intel_guc_get_log_buffer_offset(&guc->log, GUC_CAPTURE_LOG_BUFFER);
1370
1371 /*
1372 * Make a copy of the state structure, inside GuC log buffer
1373 * (which is uncached mapped), on the stack to avoid reading
1374 * from it multiple times.
1375 */
1376 memcpy(&log_buf_state_local, log_buf_state, sizeof(struct guc_log_buffer_state))__builtin_memcpy((&log_buf_state_local), (log_buf_state),
(sizeof(struct guc_log_buffer_state)));
1377 buffer_size = intel_guc_get_log_buffer_size(&guc->log, GUC_CAPTURE_LOG_BUFFER);
1378 read_offset = log_buf_state_local.read_ptr;
1379 write_offset = log_buf_state_local.sampled_write_ptr;
1380 full_count = log_buf_state_local.buffer_full_cnt;
1381
1382 /* Bookkeeping stuff */
1383 guc->log.stats[GUC_CAPTURE_LOG_BUFFER].flush += log_buf_state_local.flush_to_file;
1384 new_overflow = intel_guc_check_log_buf_overflow(&guc->log, GUC_CAPTURE_LOG_BUFFER,
1385 full_count);
1386
1387 /* Now copy the actual logs. */
1388 if (unlikely(new_overflow)__builtin_expect(!!(new_overflow), 0)) {
1389 /* copy the whole buffer in case of overflow */
1390 read_offset = 0;
1391 write_offset = buffer_size;
1392 } else if (unlikely((read_offset > buffer_size) ||__builtin_expect(!!((read_offset > buffer_size) || (write_offset
> buffer_size)), 0)
1393 (write_offset > buffer_size))__builtin_expect(!!((read_offset > buffer_size) || (write_offset
> buffer_size)), 0)) {
1394 drm_err(&i915->drm, "invalid GuC log capture buffer state!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "invalid GuC log capture buffer state!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
1395 /* copy whole buffer as offsets are unreliable */
1396 read_offset = 0;
1397 write_offset = buffer_size;
1398 }
1399
1400 buf.size = buffer_size;
1401 buf.rd = read_offset;
1402 buf.wr = write_offset;
1403 buf.data = src_data;
1404
1405 if (!uc->reset_in_progress) {
1406 do {
1407 ret = guc_capture_extract_reglists(guc, &buf);
1408 } while (ret >= 0);
1409 }
1410
1411 /* Update the state of log buffer err-cap state */
1412 log_buf_state->read_ptr = write_offset;
1413 log_buf_state->flush_to_file = 0;
1414 __guc_capture_flushlog_complete(guc);
1415}
1416
1417#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)1
1418
1419static const char *
1420guc_capture_reg_to_str(const struct intel_guc *guc, u32 owner, u32 type,
1421 u32 class, u32 id, u32 offset, u32 *is_ext)
1422{
1423 const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists;
1424 struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists;
1425 const struct __guc_mmio_reg_descr_group *match;
1426 struct __guc_mmio_reg_descr_group *matchext;
1427 int j;
1428
1429 *is_ext = 0;
1430 if (!reglists)
1431 return NULL((void *)0);
1432
1433 match = guc_capture_get_one_list(reglists, owner, type, id);
1434 if (!match)
1435 return NULL((void *)0);
1436
1437 for (j = 0; j < match->num_regs; ++j) {
1438 if (offset == match->list[j].reg.reg)
1439 return match->list[j].regname;
1440 }
1441 if (extlists) {
1442 matchext = guc_capture_get_one_ext_list(extlists, owner, type, id);
1443 if (!matchext)
1444 return NULL((void *)0);
1445 for (j = 0; j < matchext->num_regs; ++j) {
1446 if (offset == matchext->extlist[j].reg.reg) {
1447 *is_ext = 1;
1448 return matchext->extlist[j].regname;
1449 }
1450 }
1451 }
1452
1453 return NULL((void *)0);
1454}
1455
1456#define GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng)do { i915_error_printf(ebuf, " i915-Eng-Name: %s command stream\n"
, (eng)->name); i915_error_printf(ebuf, " i915-Eng-Inst-Class: 0x%02x\n"
, (eng)->class); i915_error_printf(ebuf, " i915-Eng-Inst-Id: 0x%02x\n"
, (eng)->instance); i915_error_printf(ebuf, " i915-Eng-LogicalMask: 0x%08x\n"
, (eng)->logical_mask); } while (0) \
1457 do { \
1458 i915_error_printf(ebuf, " i915-Eng-Name: %s command stream\n", \
1459 (eng)->name); \
1460 i915_error_printf(ebuf, " i915-Eng-Inst-Class: 0x%02x\n", (eng)->class); \
1461 i915_error_printf(ebuf, " i915-Eng-Inst-Id: 0x%02x\n", (eng)->instance); \
1462 i915_error_printf(ebuf, " i915-Eng-LogicalMask: 0x%08x\n", \
1463 (eng)->logical_mask); \
1464 } while (0)
1465
1466#define GCAP_PRINT_GUC_INST_INFO(ebuf, node)do { i915_error_printf(ebuf, " GuC-Engine-Inst-Id: 0x%08x\n"
, (node)->eng_inst); i915_error_printf(ebuf, " GuC-Context-Id: 0x%08x\n"
, (node)->guc_id); i915_error_printf(ebuf, " LRCA: 0x%08x\n"
, (node)->lrca); } while (0) \
1467 do { \
1468 i915_error_printf(ebuf, " GuC-Engine-Inst-Id: 0x%08x\n", \
1469 (node)->eng_inst); \
1470 i915_error_printf(ebuf, " GuC-Context-Id: 0x%08x\n", (node)->guc_id); \
1471 i915_error_printf(ebuf, " LRCA: 0x%08x\n", (node)->lrca); \
1472 } while (0)
1473
1474int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf,
1475 const struct intel_engine_coredump *ee)
1476{
1477 const char *grptype[GUC_STATE_CAPTURE_GROUP_TYPE_MAX] = {
1478 "full-capture",
1479 "partial-capture"
1480 };
1481 const char *datatype[GUC_CAPTURE_LIST_TYPE_MAX] = {
1482 "Global",
1483 "Engine-Class",
1484 "Engine-Instance"
1485 };
1486 struct intel_guc_state_capture *cap;
1487 struct __guc_capture_parsed_output *node;
1488 struct intel_engine_cs *eng;
1489 struct guc_mmio_reg *regs;
1490 struct intel_guc *guc;
1491 const char *str;
1492 int numregs, i, j;
1493 u32 is_ext;
1494
1495 if (!ebuf || !ee)
1496 return -EINVAL22;
1497 cap = ee->guc_capture;
1498 if (!cap || !ee->engine)
1499 return -ENODEV19;
1500
1501 guc = &ee->engine->gt->uc.guc;
1502
1503 i915_error_printf(ebuf, "global --- GuC Error Capture on %s command stream:\n",
1504 ee->engine->name);
1505
1506 node = ee->guc_capture_node;
1507 if (!node) {
1508 i915_error_printf(ebuf, " No matching ee-node\n");
1509 return 0;
1510 }
1511
1512 i915_error_printf(ebuf, "Coverage: %s\n", grptype[node->is_partial]);
1513
1514 for (i = GUC_CAPTURE_LIST_TYPE_GLOBAL; i < GUC_CAPTURE_LIST_TYPE_MAX; ++i) {
1515 i915_error_printf(ebuf, " RegListType: %s\n",
1516 datatype[i % GUC_CAPTURE_LIST_TYPE_MAX]);
1517 i915_error_printf(ebuf, " Owner-Id: %d\n", node->reginfo[i].vfid);
1518
1519 switch (i) {
1520 case GUC_CAPTURE_LIST_TYPE_GLOBAL:
1521 default:
1522 break;
1523 case GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS:
1524 i915_error_printf(ebuf, " GuC-Eng-Class: %d\n", node->eng_class);
1525 i915_error_printf(ebuf, " i915-Eng-Class: %d\n",
1526 guc_class_to_engine_class(node->eng_class));
1527 break;
1528 case GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE:
1529 eng = intel_guc_lookup_engine(guc, node->eng_class, node->eng_inst);
1530 if (eng)
1531 GCAP_PRINT_INTEL_ENG_INFO(ebuf, eng)do { i915_error_printf(ebuf, " i915-Eng-Name: %s command stream\n"
, (eng)->name); i915_error_printf(ebuf, " i915-Eng-Inst-Class: 0x%02x\n"
, (eng)->class); i915_error_printf(ebuf, " i915-Eng-Inst-Id: 0x%02x\n"
, (eng)->instance); i915_error_printf(ebuf, " i915-Eng-LogicalMask: 0x%08x\n"
, (eng)->logical_mask); } while (0);
1532 else
1533 i915_error_printf(ebuf, " i915-Eng-Lookup Fail!\n");
1534 GCAP_PRINT_GUC_INST_INFO(ebuf, node)do { i915_error_printf(ebuf, " GuC-Engine-Inst-Id: 0x%08x\n"
, (node)->eng_inst); i915_error_printf(ebuf, " GuC-Context-Id: 0x%08x\n"
, (node)->guc_id); i915_error_printf(ebuf, " LRCA: 0x%08x\n"
, (node)->lrca); } while (0);
1535 break;
1536 }
1537
1538 numregs = node->reginfo[i].num_regs;
1539 i915_error_printf(ebuf, " NumRegs: %d\n", numregs);
1540 j = 0;
1541 while (numregs--) {
1542 regs = node->reginfo[i].regs;
1543 str = guc_capture_reg_to_str(guc, GUC_CAPTURE_LIST_INDEX_PF, i,
1544 node->eng_class, 0, regs[j].offset, &is_ext);
1545 if (!str)
1546 i915_error_printf(ebuf, " REG-0x%08x", regs[j].offset);
1547 else
1548 i915_error_printf(ebuf, " %s", str);
1549 if (is_ext)
1550 i915_error_printf(ebuf, "[%ld][%ld]",
1551 FIELD_GET(GUC_REGSET_STEERING_GROUP, regs[j].flags)((typeof((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(12)))))(((regs[j].flags) & ((((~0UL) >> (64 - (15
) - 1)) & ((~0UL) << (12))))) >> (__builtin_ffsll
((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (12
)))) - 1))),
1552 FIELD_GET(GUC_REGSET_STEERING_INSTANCE, regs[j].flags)((typeof((((~0UL) >> (64 - (23) - 1)) & ((~0UL) <<
(20)))))(((regs[j].flags) & ((((~0UL) >> (64 - (23
) - 1)) & ((~0UL) << (20))))) >> (__builtin_ffsll
((((~0UL) >> (64 - (23) - 1)) & ((~0UL) << (20
)))) - 1))));
1553 i915_error_printf(ebuf, ": 0x%08x\n", regs[j].value);
1554 ++j;
1555 }
1556 }
1557 return 0;
1558}
1559
1560#endif //CONFIG_DRM_I915_CAPTURE_ERROR
1561
1562static void guc_capture_find_ecode(struct intel_engine_coredump *ee)
1563{
1564 struct gcap_reg_list_info *reginfo;
1565 struct guc_mmio_reg *regs;
1566 i915_reg_t reg_ipehr = RING_IPEHR(0)((const i915_reg_t){ .reg = ((0) + 0x68) });
1567 i915_reg_t reg_instdone = RING_INSTDONE(0)((const i915_reg_t){ .reg = ((0) + 0x6c) });
1568 int i;
1569
1570 if (!ee->guc_capture_node)
1571 return;
1572
1573 reginfo = ee->guc_capture_node->reginfo + GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE;
1574 regs = reginfo->regs;
1575 for (i = 0; i < reginfo->num_regs; i++) {
1576 if (regs[i].offset == reg_ipehr.reg)
1577 ee->ipehr = regs[i].value;
1578 else if (regs[i].offset == reg_instdone.reg)
1579 ee->instdone.instdone = regs[i].value;
1580 }
1581}
1582
1583void intel_guc_capture_free_node(struct intel_engine_coredump *ee)
1584{
1585 if (!ee || !ee->guc_capture_node)
1586 return;
1587
1588 guc_capture_add_node_to_cachelist(ee->guc_capture, ee->guc_capture_node);
1589 ee->guc_capture = NULL((void *)0);
1590 ee->guc_capture_node = NULL((void *)0);
1591}
1592
1593void intel_guc_capture_get_matching_node(struct intel_gt *gt,
1594 struct intel_engine_coredump *ee,
1595 struct intel_context *ce)
1596{
1597 struct __guc_capture_parsed_output *n, *ntmp;
1598 struct drm_i915_privateinteldrm_softc *i915;
1599 struct intel_guc *guc;
1600
1601 if (!gt || !ee || !ce)
1602 return;
1603
1604 i915 = gt->i915;
1605 guc = &gt->uc.guc;
1606 if (!guc->capture)
1607 return;
1608
1609 GEM_BUG_ON(ee->guc_capture_node)((void)0);
1610 /*
1611 * Look for a matching GuC reported error capture node from
1612 * the internal output link-list based on lrca, guc-id and engine
1613 * identification.
1614 */
1615 list_for_each_entry_safe(n, ntmp, &guc->capture->outlist, link)for (n = ({ const __typeof( ((__typeof(*n) *)0)->link ) *__mptr
= ((&guc->capture->outlist)->next); (__typeof(*
n) *)( (char *)__mptr - __builtin_offsetof(__typeof(*n), link
) );}), ntmp = ({ const __typeof( ((__typeof(*n) *)0)->link
) *__mptr = (n->link.next); (__typeof(*n) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*n), link) );}); &n->link
!= (&guc->capture->outlist); n = ntmp, ntmp = ({ const
__typeof( ((__typeof(*ntmp) *)0)->link ) *__mptr = (ntmp->
link.next); (__typeof(*ntmp) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*ntmp), link) );})) {
1616 if (n->eng_inst == GUC_ID_TO_ENGINE_INSTANCE(ee->engine->guc_id)(((ee->engine->guc_id) & (0xf << 3)) >>
3) &&
1617 n->eng_class == GUC_ID_TO_ENGINE_CLASS(ee->engine->guc_id)(((ee->engine->guc_id) & (0x7 << 0)) >>
0) &&
1618 n->guc_id && n->guc_id == ce->guc_id.id &&
1619 (n->lrca & CTX_GTT_ADDRESS_MASK(((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (12
)))) && (n->lrca & CTX_GTT_ADDRESS_MASK(((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (12
)))) ==
1620 (ce->lrc.lrca & CTX_GTT_ADDRESS_MASK(((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (12
))))) {
1621 list_del(&n->link);
1622 ee->guc_capture_node = n;
1623 ee->guc_capture = guc->capture;
1624 guc_capture_find_ecode(ee);
1625 return;
1626 }
1627 }
1628 drm_dbg(&i915->drm, "GuC capture can't match ee to node\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_DRIVER, "GuC capture can't match ee to node\n"
);
1629}
1630
1631void intel_guc_capture_process(struct intel_guc *guc)
1632{
1633 if (guc->capture)
1634 __guc_capture_process_output(guc);
1635}
1636
1637static void
1638guc_capture_free_ads_cache(struct intel_guc_state_capture *gc)
1639{
1640 int i, j, k;
1641 struct __guc_capture_ads_cache *cache;
1642
1643 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; ++i) {
1644 for (j = 0; j < GUC_CAPTURE_LIST_TYPE_MAX; ++j) {
1645 for (k = 0; k < GUC_MAX_ENGINE_CLASSES16; ++k) {
1646 cache = &gc->ads_cache[i][j][k];
1647 if (cache->is_valid)
1648 kfree(cache->ptr);
1649 }
1650 }
1651 }
1652 kfree(gc->ads_null_cache);
1653}
1654
1655void intel_guc_capture_destroy(struct intel_guc *guc)
1656{
1657 if (!guc->capture)
1658 return;
1659
1660 guc_capture_free_ads_cache(guc->capture);
1661
1662 guc_capture_delete_prealloc_nodes(guc);
1663
1664 guc_capture_free_extlists(guc->capture->extlists);
1665 kfree(guc->capture->extlists);
1666
1667 kfree(guc->capture);
1668 guc->capture = NULL((void *)0);
1669}
1670
1671int intel_guc_capture_init(struct intel_guc *guc)
1672{
1673 guc->capture = kzalloc(sizeof(*guc->capture), GFP_KERNEL(0x0001 | 0x0004));
1674 if (!guc->capture)
1675 return -ENOMEM12;
1676
1677 guc->capture->reglists = guc_capture_get_device_reglist(guc);
1678
1679 INIT_LIST_HEAD(&guc->capture->outlist);
1680 INIT_LIST_HEAD(&guc->capture->cachelist);
1681
1682 check_guc_capture_size(guc);
1683
1684 return 0;
1685}