File: | dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c |
Warning: | line 1922, column 3 Value stored to 'timing' is never read |
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1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright 2022 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: AMD |
24 | * |
25 | */ |
26 | |
27 | #include "dm_services.h" |
28 | #include "dc.h" |
29 | |
30 | #include "dcn32_init.h" |
31 | |
32 | #include "resource.h" |
33 | #include "include/irq_service_interface.h" |
34 | #include "dcn32_resource.h" |
35 | |
36 | #include "dcn20/dcn20_resource.h" |
37 | #include "dcn30/dcn30_resource.h" |
38 | |
39 | #include "dcn10/dcn10_ipp.h" |
40 | #include "dcn30/dcn30_hubbub.h" |
41 | #include "dcn31/dcn31_hubbub.h" |
42 | #include "dcn32/dcn32_hubbub.h" |
43 | #include "dcn32/dcn32_mpc.h" |
44 | #include "dcn32_hubp.h" |
45 | #include "irq/dcn32/irq_service_dcn32.h" |
46 | #include "dcn32/dcn32_dpp.h" |
47 | #include "dcn32/dcn32_optc.h" |
48 | #include "dcn20/dcn20_hwseq.h" |
49 | #include "dcn30/dcn30_hwseq.h" |
50 | #include "dce110/dce110_hw_sequencer.h" |
51 | #include "dcn30/dcn30_opp.h" |
52 | #include "dcn20/dcn20_dsc.h" |
53 | #include "dcn30/dcn30_vpg.h" |
54 | #include "dcn30/dcn30_afmt.h" |
55 | #include "dcn30/dcn30_dio_stream_encoder.h" |
56 | #include "dcn32/dcn32_dio_stream_encoder.h" |
57 | #include "dcn31/dcn31_hpo_dp_stream_encoder.h" |
58 | #include "dcn31/dcn31_hpo_dp_link_encoder.h" |
59 | #include "dcn32/dcn32_hpo_dp_link_encoder.h" |
60 | #include "dc_link_dp.h" |
61 | #include "dcn31/dcn31_apg.h" |
62 | #include "dcn31/dcn31_dio_link_encoder.h" |
63 | #include "dcn32/dcn32_dio_link_encoder.h" |
64 | #include "dce/dce_clock_source.h" |
65 | #include "dce/dce_audio.h" |
66 | #include "dce/dce_hwseq.h" |
67 | #include "clk_mgr.h" |
68 | #include "virtual/virtual_stream_encoder.h" |
69 | #include "dml/display_mode_vba.h" |
70 | #include "dcn32/dcn32_dccg.h" |
71 | #include "dcn10/dcn10_resource.h" |
72 | #include "dc_link_ddc.h" |
73 | #include "dcn31/dcn31_panel_cntl.h" |
74 | |
75 | #include "dcn30/dcn30_dwb.h" |
76 | #include "dcn32/dcn32_mmhubbub.h" |
77 | |
78 | #include "dcn/dcn_3_2_0_offset.h" |
79 | #include "dcn/dcn_3_2_0_sh_mask.h" |
80 | #include "nbio/nbio_4_3_0_offset.h" |
81 | |
82 | #include "reg_helper.h" |
83 | #include "dce/dmub_abm.h" |
84 | #include "dce/dmub_psr.h" |
85 | #include "dce/dce_aux.h" |
86 | #include "dce/dce_i2c.h" |
87 | |
88 | #include "dml/dcn30/display_mode_vba_30.h" |
89 | #include "vm_helper.h" |
90 | #include "dcn20/dcn20_vmid.h" |
91 | #include "dml/dcn32/dcn32_fpu.h" |
92 | |
93 | #define DC_LOGGER_INIT(logger) |
94 | |
95 | enum dcn32_clk_src_array_id { |
96 | DCN32_CLK_SRC_PLL0, |
97 | DCN32_CLK_SRC_PLL1, |
98 | DCN32_CLK_SRC_PLL2, |
99 | DCN32_CLK_SRC_PLL3, |
100 | DCN32_CLK_SRC_PLL4, |
101 | DCN32_CLK_SRC_TOTAL |
102 | }; |
103 | |
104 | /* begin ********************* |
105 | * macros to expend register list macro defined in HW object header file |
106 | */ |
107 | |
108 | /* DCN */ |
109 | /* TODO awful hack. fixup dcn20_dwb.h */ |
110 | #undef BASE_INNER |
111 | #define BASE_INNER(seg)ctx->dcn_reg_offsets[seg] ctx->dcn_reg_offsets[seg] |
112 | |
113 | #define BASE(seg)ctx->dcn_reg_offsets[seg] BASE_INNER(seg)ctx->dcn_reg_offsets[seg] |
114 | |
115 | #define SR(reg_name)dccg_regs.reg_name = ctx->dcn_reg_offsets[regreg_name_BASE_IDX ] + regreg_name\ |
116 | REG_STRUCTdccg_regs.reg_name = BASE(reg ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + \ |
117 | reg ## reg_name |
118 | #define SR_ARR(reg_name, id)dccg_regs[id].reg_name = ctx->dcn_reg_offsets[regreg_name_BASE_IDX ] + regreg_name \ |
119 | REG_STRUCTdccg_regs[id].reg_name = BASE(reg##reg_name##_BASE_IDX)ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name |
120 | |
121 | #define SR_ARR_INIT(reg_name, id, value)dccg_regs[id].reg_name = value \ |
122 | REG_STRUCTdccg_regs[id].reg_name = value |
123 | |
124 | #define SRI(reg_name, block, id)dccg_regs.reg_name = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
125 | REG_STRUCTdccg_regs.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
126 | reg ## block ## id ## _ ## reg_name |
127 | |
128 | #define SRI_ARR(reg_name, block, id)dccg_regs[id].reg_name = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
129 | REG_STRUCTdccg_regs[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
130 | reg ## block ## id ## _ ## reg_name |
131 | |
132 | #define SR_ARR_I2C(reg_name, id)dccg_regs[id-1].reg_name = ctx->dcn_reg_offsets[regreg_name_BASE_IDX ] + regreg_name \ |
133 | REG_STRUCTdccg_regs[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX)ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name |
134 | |
135 | #define SRI_ARR_I2C(reg_name, block, id)dccg_regs[id-1].reg_name = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
136 | REG_STRUCTdccg_regs[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
137 | reg ## block ## id ## _ ## reg_name |
138 | |
139 | #define SRI_ARR_ALPHABET(reg_name, block, index, id)dccg_regs[index].reg_name = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
140 | REG_STRUCTdccg_regs[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
141 | reg ## block ## id ## _ ## reg_name |
142 | |
143 | #define SRI2(reg_name, block, id).reg_name = ctx->dcn_reg_offsets[regreg_name_BASE_IDX] + regreg_name\ |
144 | .reg_name = BASE(reg ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + \ |
145 | reg ## reg_name |
146 | #define SRI2_ARR(reg_name, block, id)dccg_regs[id].reg_name = ctx->dcn_reg_offsets[regreg_name_BASE_IDX ] + regreg_name\ |
147 | REG_STRUCTdccg_regs[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + \ |
148 | reg ## reg_name |
149 | |
150 | #define SRIR(var_name, reg_name, block, id).var_name = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
151 | .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
152 | reg ## block ## id ## _ ## reg_name |
153 | |
154 | #define SRII(reg_name, block, id)dccg_regs.reg_name[id] = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
155 | REG_STRUCTdccg_regs.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
156 | reg ## block ## id ## _ ## reg_name |
157 | |
158 | #define SRII_ARR_2(reg_name, block, id, inst)dccg_regs[inst].reg_name[id] = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
159 | REG_STRUCTdccg_regs[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
160 | reg ## block ## id ## _ ## reg_name |
161 | |
162 | #define SRII_MPC_RMU(reg_name, block, id).RMU_reg_name[id] = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
163 | .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
164 | reg ## block ## id ## _ ## reg_name |
165 | |
166 | #define SRII_DWB(reg_name, temp_name, block, id)dccg_regs.reg_name[id] = ctx->dcn_reg_offsets[regblockid_temp_name_BASE_IDX ] + regblockid_temp_name\ |
167 | REG_STRUCTdccg_regs.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## temp_name ## _BASE_IDX] + \ |
168 | reg ## block ## id ## _ ## temp_name |
169 | |
170 | #define DCCG_SRII(reg_name, block, id)dccg_regs.block_reg_name[id] = ctx->dcn_reg_offsets[regblockid_reg_name_BASE_IDX ] + regblockid_reg_name\ |
171 | REG_STRUCTdccg_regs.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## block ## id ## _ ## reg_name ## _BASE_IDX] + \ |
172 | reg ## block ## id ## _ ## reg_name |
173 | |
174 | #define VUPDATE_SRII(reg_name, block, id)dccg_regs.reg_name[id] = ctx->dcn_reg_offsets[regreg_name_blockid_BASE_IDX ] + regreg_name_blockid\ |
175 | REG_STRUCTdccg_regs.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## reg_name ## _ ## block ## id ## _BASE_IDX] + \ |
176 | reg ## reg_name ## _ ## block ## id |
177 | |
178 | /* NBIO */ |
179 | #define NBIO_BASE_INNER(seg)ctx->nbio_reg_offsets[seg] ctx->nbio_reg_offsets[seg] |
180 | |
181 | #define NBIO_BASE(seg)ctx->nbio_reg_offsets[seg] \ |
182 | NBIO_BASE_INNER(seg)ctx->nbio_reg_offsets[seg] |
183 | |
184 | #define NBIO_SR(reg_name)dccg_regs.reg_name = ctx->nbio_reg_offsets[regBIF_BX0_reg_name_BASE_IDX ] + regBIF_BX0_reg_name\ |
185 | REG_STRUCTdccg_regs.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX)ctx->nbio_reg_offsets[regBIF_BX0_ ## reg_name ## _BASE_IDX ] + \ |
186 | regBIF_BX0_ ## reg_name |
187 | #define NBIO_SR_ARR(reg_name, id)dccg_regs[id].reg_name = ctx->nbio_reg_offsets[regBIF_BX0_reg_name_BASE_IDX ] + regBIF_BX0_reg_name\ |
188 | REG_STRUCTdccg_regs[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX)ctx->nbio_reg_offsets[regBIF_BX0_ ## reg_name ## _BASE_IDX ] + \ |
189 | regBIF_BX0_ ## reg_name |
190 | |
191 | #undef CTXctx |
192 | #define CTXctx ctx |
193 | #define REG(reg_name)(ctx->dcn_reg_offsets[regreg_name_BASE_IDX] + regreg_name) \ |
194 | (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) |
195 | |
196 | static struct bios_registers bios_regs; |
197 | |
198 | #define bios_regs_init()( dccg_regs.BIOS_SCRATCH_3 = ctx->nbio_reg_offsets[1] + 0x003b , dccg_regs.BIOS_SCRATCH_6 = ctx->nbio_reg_offsets[1] + 0x003e ) \ |
199 | ( \ |
200 | NBIO_SR(BIOS_SCRATCH_3)dccg_regs.BIOS_SCRATCH_3 = ctx->nbio_reg_offsets[1] + 0x003b,\ |
201 | NBIO_SR(BIOS_SCRATCH_6)dccg_regs.BIOS_SCRATCH_6 = ctx->nbio_reg_offsets[1] + 0x003e\ |
202 | ) |
203 | |
204 | #define clk_src_regs_init(index, pllid)( dccg_regs[index].PIXCLK_RESYNC_CNTL = ctx->dcn_reg_offsets [regPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX] + regPHYPLLpllid_PIXCLK_RESYNC_CNTL , dccg_regs[index].PHASE[0] = ctx->dcn_reg_offsets[1] + 0x0081 , dccg_regs[index].PHASE[1] = ctx->dcn_reg_offsets[1] + 0x0085 , dccg_regs[index].PHASE[2] = ctx->dcn_reg_offsets[1] + 0x0089 , dccg_regs[index].PHASE[3] = ctx->dcn_reg_offsets[1] + 0x008d , dccg_regs[index].MODULO[0] = ctx->dcn_reg_offsets[1] + 0x0082 , dccg_regs[index].MODULO[1] = ctx->dcn_reg_offsets[1] + 0x0086 , dccg_regs[index].MODULO[2] = ctx->dcn_reg_offsets[1] + 0x008a , dccg_regs[index].MODULO[3] = ctx->dcn_reg_offsets[1] + 0x008e , dccg_regs[index].PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs[index].PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs[index].PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs[index].PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c )\ |
205 | CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)( dccg_regs[index].PIXCLK_RESYNC_CNTL = ctx->dcn_reg_offsets [regPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX] + regPHYPLLpllid_PIXCLK_RESYNC_CNTL , dccg_regs[index].PHASE[0] = ctx->dcn_reg_offsets[1] + 0x0081 , dccg_regs[index].PHASE[1] = ctx->dcn_reg_offsets[1] + 0x0085 , dccg_regs[index].PHASE[2] = ctx->dcn_reg_offsets[1] + 0x0089 , dccg_regs[index].PHASE[3] = ctx->dcn_reg_offsets[1] + 0x008d , dccg_regs[index].MODULO[0] = ctx->dcn_reg_offsets[1] + 0x0082 , dccg_regs[index].MODULO[1] = ctx->dcn_reg_offsets[1] + 0x0086 , dccg_regs[index].MODULO[2] = ctx->dcn_reg_offsets[1] + 0x008a , dccg_regs[index].MODULO[3] = ctx->dcn_reg_offsets[1] + 0x008e , dccg_regs[index].PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs[index].PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs[index].PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs[index].PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c ) |
206 | |
207 | static struct dce110_clk_src_regs clk_src_regs[5]; |
208 | |
209 | static const struct dce110_clk_src_shift cs_shift = { |
210 | CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT).DP_DTO0_PHASE = 0x0, .DP_DTO0_MODULO = 0x0, .PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x4, .DP_DTO0_ENABLE = 0x4, .PIPE0_DTO_SRC_SEL = 0xc |
211 | }; |
212 | |
213 | static const struct dce110_clk_src_mask cs_mask = { |
214 | CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK).DP_DTO0_PHASE = 0xFFFFFFFFL, .DP_DTO0_MODULO = 0xFFFFFFFFL, . PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x00000030L, .DP_DTO0_ENABLE = 0x00000010L, .PIPE0_DTO_SRC_SEL = 0x00003000L |
215 | }; |
216 | |
217 | #define abm_regs_init(id)( dccg_regs[id].DC_ABM1_HG_SAMPLE_RATE = ctx->dcn_reg_offsets [regABMid_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX] + regABMid_DC_ABM1_HG_SAMPLE_RATE , dccg_regs[id].DC_ABM1_LS_SAMPLE_RATE = ctx->dcn_reg_offsets [regABMid_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX] + regABMid_DC_ABM1_LS_SAMPLE_RATE , dccg_regs[id].BL1_PWM_BL_UPDATE_SAMPLE_RATE = ctx->dcn_reg_offsets [regABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX] + regABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE , dccg_regs[id].DC_ABM1_HG_MISC_CTRL = ctx->dcn_reg_offsets [regABMid_DC_ABM1_HG_MISC_CTRL_BASE_IDX] + regABMid_DC_ABM1_HG_MISC_CTRL , dccg_regs[id].DC_ABM1_IPCSC_COEFF_SEL = ctx->dcn_reg_offsets [regABMid_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX] + regABMid_DC_ABM1_IPCSC_COEFF_SEL , dccg_regs[id].BL1_PWM_CURRENT_ABM_LEVEL = ctx->dcn_reg_offsets [regABMid_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX] + regABMid_BL1_PWM_CURRENT_ABM_LEVEL , dccg_regs[id].BL1_PWM_TARGET_ABM_LEVEL = ctx->dcn_reg_offsets [regABMid_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX] + regABMid_BL1_PWM_TARGET_ABM_LEVEL , dccg_regs[id].BL1_PWM_USER_LEVEL = ctx->dcn_reg_offsets[ regABMid_BL1_PWM_USER_LEVEL_BASE_IDX] + regABMid_BL1_PWM_USER_LEVEL , dccg_regs[id].DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = ctx-> dcn_reg_offsets[regABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX ] + regABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, dccg_regs[ id].DC_ABM1_HGLS_REG_READ_PROGRESS = ctx->dcn_reg_offsets[ regABMid_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX] + regABMid_DC_ABM1_HGLS_REG_READ_PROGRESS , dccg_regs[id].DC_ABM1_ACE_OFFSET_SLOPE_0 = ctx->dcn_reg_offsets [regABMid_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX] + regABMid_DC_ABM1_ACE_OFFSET_SLOPE_0 , dccg_regs[id].DC_ABM1_ACE_THRES_12 = ctx->dcn_reg_offsets [regABMid_DC_ABM1_ACE_THRES_12_BASE_IDX] + regABMid_DC_ABM1_ACE_THRES_12 , dccg_regs[id].BIOS_SCRATCH_2 = ctx->nbio_reg_offsets[1] + 0x003a )\ |
218 | ABM_DCN32_REG_LIST_RI(id)( dccg_regs[id].DC_ABM1_HG_SAMPLE_RATE = ctx->dcn_reg_offsets [regABMid_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX] + regABMid_DC_ABM1_HG_SAMPLE_RATE , dccg_regs[id].DC_ABM1_LS_SAMPLE_RATE = ctx->dcn_reg_offsets [regABMid_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX] + regABMid_DC_ABM1_LS_SAMPLE_RATE , dccg_regs[id].BL1_PWM_BL_UPDATE_SAMPLE_RATE = ctx->dcn_reg_offsets [regABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX] + regABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE , dccg_regs[id].DC_ABM1_HG_MISC_CTRL = ctx->dcn_reg_offsets [regABMid_DC_ABM1_HG_MISC_CTRL_BASE_IDX] + regABMid_DC_ABM1_HG_MISC_CTRL , dccg_regs[id].DC_ABM1_IPCSC_COEFF_SEL = ctx->dcn_reg_offsets [regABMid_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX] + regABMid_DC_ABM1_IPCSC_COEFF_SEL , dccg_regs[id].BL1_PWM_CURRENT_ABM_LEVEL = ctx->dcn_reg_offsets [regABMid_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX] + regABMid_BL1_PWM_CURRENT_ABM_LEVEL , dccg_regs[id].BL1_PWM_TARGET_ABM_LEVEL = ctx->dcn_reg_offsets [regABMid_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX] + regABMid_BL1_PWM_TARGET_ABM_LEVEL , dccg_regs[id].BL1_PWM_USER_LEVEL = ctx->dcn_reg_offsets[ regABMid_BL1_PWM_USER_LEVEL_BASE_IDX] + regABMid_BL1_PWM_USER_LEVEL , dccg_regs[id].DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = ctx-> dcn_reg_offsets[regABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX ] + regABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, dccg_regs[ id].DC_ABM1_HGLS_REG_READ_PROGRESS = ctx->dcn_reg_offsets[ regABMid_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX] + regABMid_DC_ABM1_HGLS_REG_READ_PROGRESS , dccg_regs[id].DC_ABM1_ACE_OFFSET_SLOPE_0 = ctx->dcn_reg_offsets [regABMid_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX] + regABMid_DC_ABM1_ACE_OFFSET_SLOPE_0 , dccg_regs[id].DC_ABM1_ACE_THRES_12 = ctx->dcn_reg_offsets [regABMid_DC_ABM1_ACE_THRES_12_BASE_IDX] + regABMid_DC_ABM1_ACE_THRES_12 , dccg_regs[id].BIOS_SCRATCH_2 = ctx->nbio_reg_offsets[1] + 0x003a ) |
219 | |
220 | static struct dce_abm_registers abm_regs[4]; |
221 | |
222 | static const struct dce_abm_shift abm_shift = { |
223 | ABM_MASK_SH_LIST_DCN32(__SHIFT).ABM1_HG_NUM_OF_BINS_SEL = 0x0, .ABM1_HG_VMAX_SEL = 0x8, .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x10, .ABM1_IPCSC_COEFF_SEL_R = 0x10, .ABM1_IPCSC_COEFF_SEL_G = 0x8, .ABM1_IPCSC_COEFF_SEL_B = 0x0, .BL1_PWM_CURRENT_ABM_LEVEL = 0x0, .BL1_PWM_TARGET_ABM_LEVEL = 0x0, .BL1_PWM_USER_LEVEL = 0x0, .ABM1_LS_MIN_PIXEL_VALUE_THRES = 0x0, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x10, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR = 0x10, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x18, .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR = 0x1f |
224 | }; |
225 | |
226 | static const struct dce_abm_mask abm_mask = { |
227 | ABM_MASK_SH_LIST_DCN32(_MASK).ABM1_HG_NUM_OF_BINS_SEL = 0x00000003L, .ABM1_HG_VMAX_SEL = 0x00000100L , .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x00030000L, .ABM1_IPCSC_COEFF_SEL_R = 0x000F0000L, .ABM1_IPCSC_COEFF_SEL_G = 0x00000F00L, .ABM1_IPCSC_COEFF_SEL_B = 0x0000000FL, .BL1_PWM_CURRENT_ABM_LEVEL = 0x0001FFFFL, .BL1_PWM_TARGET_ABM_LEVEL = 0x0001FFFFL, .BL1_PWM_USER_LEVEL = 0x0001FFFFL, .ABM1_LS_MIN_PIXEL_VALUE_THRES = 0x000003FFL, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x03FF0000L, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR = 0x00010000L, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x01000000L, .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR = 0x80000000L |
228 | }; |
229 | |
230 | #define audio_regs_init(id)( dccg_regs[id].AZALIA_F0_CODEC_ENDPOINT_INDEX = ctx->dcn_reg_offsets [regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX] + regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, dccg_regs[ id].AZALIA_F0_CODEC_ENDPOINT_DATA = ctx->dcn_reg_offsets[regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX ] + regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, dccg_regs [id].AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = ctx-> dcn_reg_offsets[2] + 0x040c, dccg_regs[id].AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = ctx->dcn_reg_offsets[2] + 0x040b, dccg_regs[id].AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = ctx->dcn_reg_offsets[2] + 0x040d, dccg_regs[id].DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs[id].DCCG_AUDIO_DTO0_MODULE = ctx->dcn_reg_offsets[1] + 0x00ad, dccg_regs[id].DCCG_AUDIO_DTO0_PHASE = ctx->dcn_reg_offsets[1] + 0x00ac, dccg_regs[id].DCCG_AUDIO_DTO1_MODULE = ctx->dcn_reg_offsets[1] + 0x00af, dccg_regs[id].DCCG_AUDIO_DTO1_PHASE = ctx->dcn_reg_offsets[1] + 0x00ae )\ |
231 | AUD_COMMON_REG_LIST_RI(id)( dccg_regs[id].AZALIA_F0_CODEC_ENDPOINT_INDEX = ctx->dcn_reg_offsets [regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX] + regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, dccg_regs[ id].AZALIA_F0_CODEC_ENDPOINT_DATA = ctx->dcn_reg_offsets[regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX ] + regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, dccg_regs [id].AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = ctx-> dcn_reg_offsets[2] + 0x040c, dccg_regs[id].AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = ctx->dcn_reg_offsets[2] + 0x040b, dccg_regs[id].AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = ctx->dcn_reg_offsets[2] + 0x040d, dccg_regs[id].DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs[id].DCCG_AUDIO_DTO0_MODULE = ctx->dcn_reg_offsets[1] + 0x00ad, dccg_regs[id].DCCG_AUDIO_DTO0_PHASE = ctx->dcn_reg_offsets[1] + 0x00ac, dccg_regs[id].DCCG_AUDIO_DTO1_MODULE = ctx->dcn_reg_offsets[1] + 0x00af, dccg_regs[id].DCCG_AUDIO_DTO1_PHASE = ctx->dcn_reg_offsets[1] + 0x00ae ) |
232 | |
233 | static struct dce_audio_registers audio_regs[5]; |
234 | |
235 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh , .AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh , .DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh , .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh , .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh , .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh , .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh , .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh , .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh , .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh , .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh\ |
236 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh,\ |
237 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh).AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh,\ |
238 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh).DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh , .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh , .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh , .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh , .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh , .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh , .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh , .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh , .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh |
239 | |
240 | static const struct dce_audio_shift audio_shift = { |
241 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT).AZALIA_ENDPOINT_REG_INDEX = 0x0, .AZALIA_ENDPOINT_REG_DATA = 0x0, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x0, .DCCG_AUDIO_DTO_SEL = 0x4, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x14, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = 0x18, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x1c, .DCCG_AUDIO_DTO0_MODULE = 0x0, .DCCG_AUDIO_DTO0_PHASE = 0x0, .DCCG_AUDIO_DTO1_MODULE = 0x0, .DCCG_AUDIO_DTO1_PHASE = 0x0, .AUDIO_RATE_CAPABILITIES = 0x0, .CLKSTOP = 0x1e, .EPSS = 0x1f |
242 | }; |
243 | |
244 | static const struct dce_audio_mask audio_mask = { |
245 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK).AZALIA_ENDPOINT_REG_INDEX = 0x00003FFFL, .AZALIA_ENDPOINT_REG_DATA = 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x00000007L, .DCCG_AUDIO_DTO_SEL = 0x00000070L, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x00100000L , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = 0x01000000L, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x10000000L, .DCCG_AUDIO_DTO0_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_PHASE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_PHASE = 0xFFFFFFFFL, .AUDIO_RATE_CAPABILITIES = 0x00000FFFL, .CLKSTOP = 0x40000000L, .EPSS = 0x80000000L |
246 | }; |
247 | |
248 | #define vpg_regs_init(id)( dccg_regs[id].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[ regVPGid_VPG_GENERIC_STATUS_BASE_IDX] + regVPGid_VPG_GENERIC_STATUS , dccg_regs[id].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx->dcn_reg_offsets [regVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX] + regVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL , dccg_regs[id].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets [regVPGid_VPG_GENERIC_PACKET_DATA_BASE_IDX] + regVPGid_VPG_GENERIC_PACKET_DATA , dccg_regs[id].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets [regVPGid_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX] + regVPGid_VPG_GSP_FRAME_UPDATE_CTRL , dccg_regs[id].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets [regVPGid_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX] + regVPGid_VPG_GSP_IMMEDIATE_UPDATE_CTRL )\ |
249 | VPG_DCN3_REG_LIST_RI(id)( dccg_regs[id].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[ regVPGid_VPG_GENERIC_STATUS_BASE_IDX] + regVPGid_VPG_GENERIC_STATUS , dccg_regs[id].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx->dcn_reg_offsets [regVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX] + regVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL , dccg_regs[id].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets [regVPGid_VPG_GENERIC_PACKET_DATA_BASE_IDX] + regVPGid_VPG_GENERIC_PACKET_DATA , dccg_regs[id].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets [regVPGid_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX] + regVPGid_VPG_GSP_FRAME_UPDATE_CTRL , dccg_regs[id].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets [regVPGid_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX] + regVPGid_VPG_GSP_IMMEDIATE_UPDATE_CTRL ) |
250 | |
251 | static struct dcn30_vpg_registers vpg_regs[10]; |
252 | |
253 | static const struct dcn30_vpg_shift vpg_shift = { |
254 | DCN3_VPG_MASK_SH_LIST(__SHIFT).VPG_GENERIC_CONFLICT_OCCURED = 0x1, .VPG_GENERIC_CONFLICT_CLR = 0x4, .VPG_GENERIC_DATA_INDEX = 0x0, .VPG_GENERIC_DATA_BYTE0 = 0x0, .VPG_GENERIC_DATA_BYTE1 = 0x8, .VPG_GENERIC_DATA_BYTE2 = 0x10, .VPG_GENERIC_DATA_BYTE3 = 0x18, .VPG_GENERIC0_FRAME_UPDATE = 0x0, .VPG_GENERIC1_FRAME_UPDATE = 0x1, .VPG_GENERIC2_FRAME_UPDATE = 0x2, .VPG_GENERIC3_FRAME_UPDATE = 0x3, .VPG_GENERIC4_FRAME_UPDATE = 0x4, .VPG_GENERIC5_FRAME_UPDATE = 0x5, .VPG_GENERIC6_FRAME_UPDATE = 0x6, .VPG_GENERIC7_FRAME_UPDATE = 0x7, .VPG_GENERIC8_FRAME_UPDATE = 0x8, .VPG_GENERIC9_FRAME_UPDATE = 0x9, .VPG_GENERIC10_FRAME_UPDATE = 0xa, .VPG_GENERIC11_FRAME_UPDATE = 0xb, .VPG_GENERIC12_FRAME_UPDATE = 0xc, .VPG_GENERIC13_FRAME_UPDATE = 0xd, .VPG_GENERIC14_FRAME_UPDATE = 0xe, .VPG_GENERIC0_IMMEDIATE_UPDATE = 0x0, .VPG_GENERIC1_IMMEDIATE_UPDATE = 0x1, .VPG_GENERIC2_IMMEDIATE_UPDATE = 0x2, .VPG_GENERIC3_IMMEDIATE_UPDATE = 0x3, .VPG_GENERIC4_IMMEDIATE_UPDATE = 0x4, .VPG_GENERIC5_IMMEDIATE_UPDATE = 0x5, .VPG_GENERIC6_IMMEDIATE_UPDATE = 0x6, .VPG_GENERIC7_IMMEDIATE_UPDATE = 0x7, .VPG_GENERIC8_IMMEDIATE_UPDATE = 0x8, .VPG_GENERIC9_IMMEDIATE_UPDATE = 0x9, .VPG_GENERIC10_IMMEDIATE_UPDATE = 0xa, .VPG_GENERIC11_IMMEDIATE_UPDATE = 0xb, .VPG_GENERIC12_IMMEDIATE_UPDATE = 0xc, .VPG_GENERIC13_IMMEDIATE_UPDATE = 0xd, .VPG_GENERIC14_IMMEDIATE_UPDATE = 0xe |
255 | }; |
256 | |
257 | static const struct dcn30_vpg_mask vpg_mask = { |
258 | DCN3_VPG_MASK_SH_LIST(_MASK).VPG_GENERIC_CONFLICT_OCCURED = 0x00000002L, .VPG_GENERIC_CONFLICT_CLR = 0x00000010L, .VPG_GENERIC_DATA_INDEX = 0x000000FFL, .VPG_GENERIC_DATA_BYTE0 = 0x000000FFL, .VPG_GENERIC_DATA_BYTE1 = 0x0000FF00L, .VPG_GENERIC_DATA_BYTE2 = 0x00FF0000L, .VPG_GENERIC_DATA_BYTE3 = 0xFF000000L, .VPG_GENERIC0_FRAME_UPDATE = 0x00000001L, .VPG_GENERIC1_FRAME_UPDATE = 0x00000002L, .VPG_GENERIC2_FRAME_UPDATE = 0x00000004L, .VPG_GENERIC3_FRAME_UPDATE = 0x00000008L, .VPG_GENERIC4_FRAME_UPDATE = 0x00000010L, .VPG_GENERIC5_FRAME_UPDATE = 0x00000020L, .VPG_GENERIC6_FRAME_UPDATE = 0x00000040L, .VPG_GENERIC7_FRAME_UPDATE = 0x00000080L, .VPG_GENERIC8_FRAME_UPDATE = 0x00000100L, .VPG_GENERIC9_FRAME_UPDATE = 0x00000200L, .VPG_GENERIC10_FRAME_UPDATE = 0x00000400L, .VPG_GENERIC11_FRAME_UPDATE = 0x00000800L, .VPG_GENERIC12_FRAME_UPDATE = 0x00001000L, .VPG_GENERIC13_FRAME_UPDATE = 0x00002000L, .VPG_GENERIC14_FRAME_UPDATE = 0x00004000L, .VPG_GENERIC0_IMMEDIATE_UPDATE = 0x00000001L, .VPG_GENERIC1_IMMEDIATE_UPDATE = 0x00000002L, .VPG_GENERIC2_IMMEDIATE_UPDATE = 0x00000004L, .VPG_GENERIC3_IMMEDIATE_UPDATE = 0x00000008L, .VPG_GENERIC4_IMMEDIATE_UPDATE = 0x00000010L, .VPG_GENERIC5_IMMEDIATE_UPDATE = 0x00000020L, .VPG_GENERIC6_IMMEDIATE_UPDATE = 0x00000040L, .VPG_GENERIC7_IMMEDIATE_UPDATE = 0x00000080L, .VPG_GENERIC8_IMMEDIATE_UPDATE = 0x00000100L, .VPG_GENERIC9_IMMEDIATE_UPDATE = 0x00000200L, .VPG_GENERIC10_IMMEDIATE_UPDATE = 0x00000400L, .VPG_GENERIC11_IMMEDIATE_UPDATE = 0x00000800L, .VPG_GENERIC12_IMMEDIATE_UPDATE = 0x00001000L , .VPG_GENERIC13_IMMEDIATE_UPDATE = 0x00002000L, .VPG_GENERIC14_IMMEDIATE_UPDATE = 0x00004000L |
259 | }; |
260 | |
261 | #define afmt_regs_init(id)( dccg_regs[id].AFMT_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets [regAFMTid_AFMT_INFOFRAME_CONTROL0_BASE_IDX] + regAFMTid_AFMT_INFOFRAME_CONTROL0 , dccg_regs[id].AFMT_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets [regAFMTid_AFMT_VBI_PACKET_CONTROL_BASE_IDX] + regAFMTid_AFMT_VBI_PACKET_CONTROL , dccg_regs[id].AFMT_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets [regAFMTid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX] + regAFMTid_AFMT_AUDIO_PACKET_CONTROL , dccg_regs[id].AFMT_AUDIO_PACKET_CONTROL2 = ctx->dcn_reg_offsets [regAFMTid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX] + regAFMTid_AFMT_AUDIO_PACKET_CONTROL2 , dccg_regs[id].AFMT_AUDIO_SRC_CONTROL = ctx->dcn_reg_offsets [regAFMTid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX] + regAFMTid_AFMT_AUDIO_SRC_CONTROL , dccg_regs[id].AFMT_60958_0 = ctx->dcn_reg_offsets[regAFMTid_AFMT_60958_0_BASE_IDX ] + regAFMTid_AFMT_60958_0, dccg_regs[id].AFMT_60958_1 = ctx-> dcn_reg_offsets[regAFMTid_AFMT_60958_1_BASE_IDX] + regAFMTid_AFMT_60958_1 , dccg_regs[id].AFMT_60958_2 = ctx->dcn_reg_offsets[regAFMTid_AFMT_60958_2_BASE_IDX ] + regAFMTid_AFMT_60958_2, dccg_regs[id].AFMT_MEM_PWR = ctx-> dcn_reg_offsets[regAFMTid_AFMT_MEM_PWR_BASE_IDX] + regAFMTid_AFMT_MEM_PWR )\ |
262 | AFMT_DCN3_REG_LIST_RI(id)( dccg_regs[id].AFMT_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets [regAFMTid_AFMT_INFOFRAME_CONTROL0_BASE_IDX] + regAFMTid_AFMT_INFOFRAME_CONTROL0 , dccg_regs[id].AFMT_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets [regAFMTid_AFMT_VBI_PACKET_CONTROL_BASE_IDX] + regAFMTid_AFMT_VBI_PACKET_CONTROL , dccg_regs[id].AFMT_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets [regAFMTid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX] + regAFMTid_AFMT_AUDIO_PACKET_CONTROL , dccg_regs[id].AFMT_AUDIO_PACKET_CONTROL2 = ctx->dcn_reg_offsets [regAFMTid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX] + regAFMTid_AFMT_AUDIO_PACKET_CONTROL2 , dccg_regs[id].AFMT_AUDIO_SRC_CONTROL = ctx->dcn_reg_offsets [regAFMTid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX] + regAFMTid_AFMT_AUDIO_SRC_CONTROL , dccg_regs[id].AFMT_60958_0 = ctx->dcn_reg_offsets[regAFMTid_AFMT_60958_0_BASE_IDX ] + regAFMTid_AFMT_60958_0, dccg_regs[id].AFMT_60958_1 = ctx-> dcn_reg_offsets[regAFMTid_AFMT_60958_1_BASE_IDX] + regAFMTid_AFMT_60958_1 , dccg_regs[id].AFMT_60958_2 = ctx->dcn_reg_offsets[regAFMTid_AFMT_60958_2_BASE_IDX ] + regAFMTid_AFMT_60958_2, dccg_regs[id].AFMT_MEM_PWR = ctx-> dcn_reg_offsets[regAFMTid_AFMT_MEM_PWR_BASE_IDX] + regAFMTid_AFMT_MEM_PWR ) |
263 | |
264 | static struct dcn30_afmt_registers afmt_regs[6]; |
265 | |
266 | static const struct dcn30_afmt_shift afmt_shift = { |
267 | DCN3_AFMT_MASK_SH_LIST(__SHIFT).AFMT_AUDIO_INFO_UPDATE = 0x7, .AFMT_AUDIO_SRC_SELECT = 0x0, . AFMT_AUDIO_CHANNEL_ENABLE = 0x8, .AFMT_60958_CS_UPDATE = 0x1a , .AFMT_AUDIO_LAYOUT_OVRD = 0x0, .AFMT_60958_OSF_OVRD = 0x1c, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0x14, .AFMT_60958_CS_CLOCK_ACCURACY = 0x1c, .AFMT_60958_CS_CHANNEL_NUMBER_R = 0x14, .AFMT_60958_CS_CHANNEL_NUMBER_2 = 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x4, .AFMT_60958_CS_CHANNEL_NUMBER_4 = 0x8, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0xc, .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x10, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x14, .AFMT_AUDIO_SAMPLE_SEND = 0x0, .AFMT_MEM_PWR_FORCE = 0x4 |
268 | }; |
269 | |
270 | static const struct dcn30_afmt_mask afmt_mask = { |
271 | DCN3_AFMT_MASK_SH_LIST(_MASK).AFMT_AUDIO_INFO_UPDATE = 0x00000080L, .AFMT_AUDIO_SRC_SELECT = 0x00000007L, .AFMT_AUDIO_CHANNEL_ENABLE = 0x0000FF00L, .AFMT_60958_CS_UPDATE = 0x04000000L, .AFMT_AUDIO_LAYOUT_OVRD = 0x00000001L, .AFMT_60958_OSF_OVRD = 0x10000000L, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0x00F00000L , .AFMT_60958_CS_CLOCK_ACCURACY = 0x30000000L, .AFMT_60958_CS_CHANNEL_NUMBER_R = 0x00F00000L, .AFMT_60958_CS_CHANNEL_NUMBER_2 = 0x0000000FL , .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x000000F0L, .AFMT_60958_CS_CHANNEL_NUMBER_4 = 0x00000F00L, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0x0000F000L , .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x000F0000L, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x00F00000L, .AFMT_AUDIO_SAMPLE_SEND = 0x00000001L, .AFMT_MEM_PWR_FORCE = 0x00000030L |
272 | }; |
273 | |
274 | #define apg_regs_init(id)( dccg_regs[id].APG_CONTROL = ctx->dcn_reg_offsets[regAPGid_APG_CONTROL_BASE_IDX ] + regAPGid_APG_CONTROL, dccg_regs[id].APG_CONTROL2 = ctx-> dcn_reg_offsets[regAPGid_APG_CONTROL2_BASE_IDX] + regAPGid_APG_CONTROL2 , dccg_regs[id].APG_MEM_PWR = ctx->dcn_reg_offsets[regAPGid_APG_MEM_PWR_BASE_IDX ] + regAPGid_APG_MEM_PWR, dccg_regs[id].APG_DBG_GEN_CONTROL = ctx->dcn_reg_offsets[regAPGid_APG_DBG_GEN_CONTROL_BASE_IDX ] + regAPGid_APG_DBG_GEN_CONTROL )\ |
275 | APG_DCN31_REG_LIST_RI(id)( dccg_regs[id].APG_CONTROL = ctx->dcn_reg_offsets[regAPGid_APG_CONTROL_BASE_IDX ] + regAPGid_APG_CONTROL, dccg_regs[id].APG_CONTROL2 = ctx-> dcn_reg_offsets[regAPGid_APG_CONTROL2_BASE_IDX] + regAPGid_APG_CONTROL2 , dccg_regs[id].APG_MEM_PWR = ctx->dcn_reg_offsets[regAPGid_APG_MEM_PWR_BASE_IDX ] + regAPGid_APG_MEM_PWR, dccg_regs[id].APG_DBG_GEN_CONTROL = ctx->dcn_reg_offsets[regAPGid_APG_DBG_GEN_CONTROL_BASE_IDX ] + regAPGid_APG_DBG_GEN_CONTROL ) |
276 | |
277 | static struct dcn31_apg_registers apg_regs[4]; |
278 | |
279 | static const struct dcn31_apg_shift apg_shift = { |
280 | DCN31_APG_MASK_SH_LIST(__SHIFT).APG_RESET = 0x1, .APG_RESET_DONE = 0x2, .APG_ENABLE = 0x0, . APG_DP_AUDIO_STREAM_ID = 0x8, .APG_DBG_AUDIO_CHANNEL_ENABLE = 0x8, .APG_MEM_PWR_FORCE = 0x4 |
281 | }; |
282 | |
283 | static const struct dcn31_apg_mask apg_mask = { |
284 | DCN31_APG_MASK_SH_LIST(_MASK).APG_RESET = 0x00000002L, .APG_RESET_DONE = 0x00000004L, .APG_ENABLE = 0x00000001L, .APG_DP_AUDIO_STREAM_ID = 0x0000FF00L, .APG_DBG_AUDIO_CHANNEL_ENABLE = 0x0000FF00L, .APG_MEM_PWR_FORCE = 0x00000030L |
285 | }; |
286 | |
287 | #define stream_enc_regs_init(id)( dccg_regs[id].AFMT_CNTL = ctx->dcn_reg_offsets[regDIGid_AFMT_CNTL_BASE_IDX ] + regDIGid_AFMT_CNTL, dccg_regs[id].DIG_FE_CNTL = ctx->dcn_reg_offsets [regDIGid_DIG_FE_CNTL_BASE_IDX] + regDIGid_DIG_FE_CNTL, dccg_regs [id].HDMI_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_CONTROL_BASE_IDX ] + regDIGid_HDMI_CONTROL, dccg_regs[id].HDMI_DB_CONTROL = ctx ->dcn_reg_offsets[regDIGid_HDMI_DB_CONTROL_BASE_IDX] + regDIGid_HDMI_DB_CONTROL , dccg_regs[id].HDMI_GC = ctx->dcn_reg_offsets[regDIGid_HDMI_GC_BASE_IDX ] + regDIGid_HDMI_GC, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL0 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL0, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL1 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL1, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL2 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL2, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL3 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL3, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL4 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL4, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL5 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL5, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL6 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL6, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL7 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL7, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL8 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL8, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL9 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL9, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL10 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL10, dccg_regs[id].HDMI_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets[regDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX ] + regDIGid_HDMI_INFOFRAME_CONTROL0, dccg_regs[id].HDMI_INFOFRAME_CONTROL1 = ctx->dcn_reg_offsets[regDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX ] + regDIGid_HDMI_INFOFRAME_CONTROL1, dccg_regs[id].HDMI_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX ] + regDIGid_HDMI_VBI_PACKET_CONTROL, dccg_regs[id].HDMI_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX ] + regDIGid_HDMI_AUDIO_PACKET_CONTROL, dccg_regs[id].HDMI_ACR_PACKET_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX ] + regDIGid_HDMI_ACR_PACKET_CONTROL, dccg_regs[id].HDMI_ACR_32_0 = ctx->dcn_reg_offsets[regDIGid_HDMI_ACR_32_0_BASE_IDX] + regDIGid_HDMI_ACR_32_0, dccg_regs[id].HDMI_ACR_32_1 = ctx-> dcn_reg_offsets[regDIGid_HDMI_ACR_32_1_BASE_IDX] + regDIGid_HDMI_ACR_32_1 , dccg_regs[id].HDMI_ACR_44_0 = ctx->dcn_reg_offsets[regDIGid_HDMI_ACR_44_0_BASE_IDX ] + regDIGid_HDMI_ACR_44_0, dccg_regs[id].HDMI_ACR_44_1 = ctx ->dcn_reg_offsets[regDIGid_HDMI_ACR_44_1_BASE_IDX] + regDIGid_HDMI_ACR_44_1 , dccg_regs[id].HDMI_ACR_48_0 = ctx->dcn_reg_offsets[regDIGid_HDMI_ACR_48_0_BASE_IDX ] + regDIGid_HDMI_ACR_48_0, dccg_regs[id].HDMI_ACR_48_1 = ctx ->dcn_reg_offsets[regDIGid_HDMI_ACR_48_1_BASE_IDX] + regDIGid_HDMI_ACR_48_1 , dccg_regs[id].DP_DB_CNTL = ctx->dcn_reg_offsets[regDPid_DP_DB_CNTL_BASE_IDX ] + regDPid_DP_DB_CNTL, dccg_regs[id].DP_MSA_MISC = ctx->dcn_reg_offsets [regDPid_DP_MSA_MISC_BASE_IDX] + regDPid_DP_MSA_MISC, dccg_regs [id].DP_MSA_VBID_MISC = ctx->dcn_reg_offsets[regDPid_DP_MSA_VBID_MISC_BASE_IDX ] + regDPid_DP_MSA_VBID_MISC, dccg_regs[id].DP_MSA_COLORIMETRY = ctx->dcn_reg_offsets[regDPid_DP_MSA_COLORIMETRY_BASE_IDX ] + regDPid_DP_MSA_COLORIMETRY, dccg_regs[id].DP_MSA_TIMING_PARAM1 = ctx->dcn_reg_offsets[regDPid_DP_MSA_TIMING_PARAM1_BASE_IDX ] + regDPid_DP_MSA_TIMING_PARAM1, dccg_regs[id].DP_MSA_TIMING_PARAM2 = ctx->dcn_reg_offsets[regDPid_DP_MSA_TIMING_PARAM2_BASE_IDX ] + regDPid_DP_MSA_TIMING_PARAM2, dccg_regs[id].DP_MSA_TIMING_PARAM3 = ctx->dcn_reg_offsets[regDPid_DP_MSA_TIMING_PARAM3_BASE_IDX ] + regDPid_DP_MSA_TIMING_PARAM3, dccg_regs[id].DP_MSA_TIMING_PARAM4 = ctx->dcn_reg_offsets[regDPid_DP_MSA_TIMING_PARAM4_BASE_IDX ] + regDPid_DP_MSA_TIMING_PARAM4, dccg_regs[id].DP_MSE_RATE_CNTL = ctx->dcn_reg_offsets[regDPid_DP_MSE_RATE_CNTL_BASE_IDX] + regDPid_DP_MSE_RATE_CNTL, dccg_regs[id].DP_MSE_RATE_UPDATE = ctx->dcn_reg_offsets[regDPid_DP_MSE_RATE_UPDATE_BASE_IDX ] + regDPid_DP_MSE_RATE_UPDATE, dccg_regs[id].DP_PIXEL_FORMAT = ctx->dcn_reg_offsets[regDPid_DP_PIXEL_FORMAT_BASE_IDX] + regDPid_DP_PIXEL_FORMAT, dccg_regs[id].DP_SEC_CNTL = ctx-> dcn_reg_offsets[regDPid_DP_SEC_CNTL_BASE_IDX] + regDPid_DP_SEC_CNTL , dccg_regs[id].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[regDPid_DP_SEC_CNTL1_BASE_IDX ] + regDPid_DP_SEC_CNTL1, dccg_regs[id].DP_SEC_CNTL2 = ctx-> dcn_reg_offsets[regDPid_DP_SEC_CNTL2_BASE_IDX] + regDPid_DP_SEC_CNTL2 , dccg_regs[id].DP_SEC_CNTL5 = ctx->dcn_reg_offsets[regDPid_DP_SEC_CNTL5_BASE_IDX ] + regDPid_DP_SEC_CNTL5, dccg_regs[id].DP_SEC_CNTL6 = ctx-> dcn_reg_offsets[regDPid_DP_SEC_CNTL6_BASE_IDX] + regDPid_DP_SEC_CNTL6 , dccg_regs[id].DP_STEER_FIFO = ctx->dcn_reg_offsets[regDPid_DP_STEER_FIFO_BASE_IDX ] + regDPid_DP_STEER_FIFO, dccg_regs[id].DP_VID_M = ctx->dcn_reg_offsets [regDPid_DP_VID_M_BASE_IDX] + regDPid_DP_VID_M, dccg_regs[id] .DP_VID_N = ctx->dcn_reg_offsets[regDPid_DP_VID_N_BASE_IDX ] + regDPid_DP_VID_N, dccg_regs[id].DP_VID_STREAM_CNTL = ctx-> dcn_reg_offsets[regDPid_DP_VID_STREAM_CNTL_BASE_IDX] + regDPid_DP_VID_STREAM_CNTL , dccg_regs[id].DP_VID_TIMING = ctx->dcn_reg_offsets[regDPid_DP_VID_TIMING_BASE_IDX ] + regDPid_DP_VID_TIMING, dccg_regs[id].DP_SEC_AUD_N = ctx-> dcn_reg_offsets[regDPid_DP_SEC_AUD_N_BASE_IDX] + regDPid_DP_SEC_AUD_N , dccg_regs[id].DP_SEC_TIMESTAMP = ctx->dcn_reg_offsets[regDPid_DP_SEC_TIMESTAMP_BASE_IDX ] + regDPid_DP_SEC_TIMESTAMP, dccg_regs[id].DP_DSC_CNTL = ctx ->dcn_reg_offsets[regDPid_DP_DSC_CNTL_BASE_IDX] + regDPid_DP_DSC_CNTL , dccg_regs[id].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets [regDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX] + regDPid_DP_SEC_METADATA_TRANSMISSION , dccg_regs[id].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets [regDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX] + regDIGid_HDMI_METADATA_PACKET_CONTROL , dccg_regs[id].DP_SEC_FRAMING4 = ctx->dcn_reg_offsets[regDPid_DP_SEC_FRAMING4_BASE_IDX ] + regDPid_DP_SEC_FRAMING4, dccg_regs[id].DP_GSP11_CNTL = ctx ->dcn_reg_offsets[regDPid_DP_GSP11_CNTL_BASE_IDX] + regDPid_DP_GSP11_CNTL , dccg_regs[id].DME_CONTROL = ctx->dcn_reg_offsets[regDMEid_DME_CONTROL_BASE_IDX ] + regDMEid_DME_CONTROL, dccg_regs[id].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[regDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX ] + regDPid_DP_SEC_METADATA_TRANSMISSION, dccg_regs[id].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX ] + regDIGid_HDMI_METADATA_PACKET_CONTROL, dccg_regs[id].DIG_FE_CNTL = ctx->dcn_reg_offsets[regDIGid_DIG_FE_CNTL_BASE_IDX] + regDIGid_DIG_FE_CNTL , dccg_regs[id].DIG_CLOCK_PATTERN = ctx->dcn_reg_offsets[regDIGid_DIG_CLOCK_PATTERN_BASE_IDX ] + regDIGid_DIG_CLOCK_PATTERN, dccg_regs[id].DIG_FIFO_CTRL0 = ctx->dcn_reg_offsets[regDIGid_DIG_FIFO_CTRL0_BASE_IDX] + regDIGid_DIG_FIFO_CTRL0 )\ |
288 | SE_DCN32_REG_LIST_RI(id)( dccg_regs[id].AFMT_CNTL = ctx->dcn_reg_offsets[regDIGid_AFMT_CNTL_BASE_IDX ] + regDIGid_AFMT_CNTL, dccg_regs[id].DIG_FE_CNTL = ctx->dcn_reg_offsets [regDIGid_DIG_FE_CNTL_BASE_IDX] + regDIGid_DIG_FE_CNTL, dccg_regs [id].HDMI_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_CONTROL_BASE_IDX ] + regDIGid_HDMI_CONTROL, dccg_regs[id].HDMI_DB_CONTROL = ctx ->dcn_reg_offsets[regDIGid_HDMI_DB_CONTROL_BASE_IDX] + regDIGid_HDMI_DB_CONTROL , dccg_regs[id].HDMI_GC = ctx->dcn_reg_offsets[regDIGid_HDMI_GC_BASE_IDX ] + regDIGid_HDMI_GC, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL0 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL0, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL1 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL1, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL2 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL2, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL3 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL3, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL4 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL4, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL5 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL5, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL6 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL6, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL7 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL7, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL8 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL8, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL9 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL9, dccg_regs[id].HDMI_GENERIC_PACKET_CONTROL10 = ctx->dcn_reg_offsets[regDIGid_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX ] + regDIGid_HDMI_GENERIC_PACKET_CONTROL10, dccg_regs[id].HDMI_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets[regDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX ] + regDIGid_HDMI_INFOFRAME_CONTROL0, dccg_regs[id].HDMI_INFOFRAME_CONTROL1 = ctx->dcn_reg_offsets[regDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX ] + regDIGid_HDMI_INFOFRAME_CONTROL1, dccg_regs[id].HDMI_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX ] + regDIGid_HDMI_VBI_PACKET_CONTROL, dccg_regs[id].HDMI_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX ] + regDIGid_HDMI_AUDIO_PACKET_CONTROL, dccg_regs[id].HDMI_ACR_PACKET_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX ] + regDIGid_HDMI_ACR_PACKET_CONTROL, dccg_regs[id].HDMI_ACR_32_0 = ctx->dcn_reg_offsets[regDIGid_HDMI_ACR_32_0_BASE_IDX] + regDIGid_HDMI_ACR_32_0, dccg_regs[id].HDMI_ACR_32_1 = ctx-> dcn_reg_offsets[regDIGid_HDMI_ACR_32_1_BASE_IDX] + regDIGid_HDMI_ACR_32_1 , dccg_regs[id].HDMI_ACR_44_0 = ctx->dcn_reg_offsets[regDIGid_HDMI_ACR_44_0_BASE_IDX ] + regDIGid_HDMI_ACR_44_0, dccg_regs[id].HDMI_ACR_44_1 = ctx ->dcn_reg_offsets[regDIGid_HDMI_ACR_44_1_BASE_IDX] + regDIGid_HDMI_ACR_44_1 , dccg_regs[id].HDMI_ACR_48_0 = ctx->dcn_reg_offsets[regDIGid_HDMI_ACR_48_0_BASE_IDX ] + regDIGid_HDMI_ACR_48_0, dccg_regs[id].HDMI_ACR_48_1 = ctx ->dcn_reg_offsets[regDIGid_HDMI_ACR_48_1_BASE_IDX] + regDIGid_HDMI_ACR_48_1 , dccg_regs[id].DP_DB_CNTL = ctx->dcn_reg_offsets[regDPid_DP_DB_CNTL_BASE_IDX ] + regDPid_DP_DB_CNTL, dccg_regs[id].DP_MSA_MISC = ctx->dcn_reg_offsets [regDPid_DP_MSA_MISC_BASE_IDX] + regDPid_DP_MSA_MISC, dccg_regs [id].DP_MSA_VBID_MISC = ctx->dcn_reg_offsets[regDPid_DP_MSA_VBID_MISC_BASE_IDX ] + regDPid_DP_MSA_VBID_MISC, dccg_regs[id].DP_MSA_COLORIMETRY = ctx->dcn_reg_offsets[regDPid_DP_MSA_COLORIMETRY_BASE_IDX ] + regDPid_DP_MSA_COLORIMETRY, dccg_regs[id].DP_MSA_TIMING_PARAM1 = ctx->dcn_reg_offsets[regDPid_DP_MSA_TIMING_PARAM1_BASE_IDX ] + regDPid_DP_MSA_TIMING_PARAM1, dccg_regs[id].DP_MSA_TIMING_PARAM2 = ctx->dcn_reg_offsets[regDPid_DP_MSA_TIMING_PARAM2_BASE_IDX ] + regDPid_DP_MSA_TIMING_PARAM2, dccg_regs[id].DP_MSA_TIMING_PARAM3 = ctx->dcn_reg_offsets[regDPid_DP_MSA_TIMING_PARAM3_BASE_IDX ] + regDPid_DP_MSA_TIMING_PARAM3, dccg_regs[id].DP_MSA_TIMING_PARAM4 = ctx->dcn_reg_offsets[regDPid_DP_MSA_TIMING_PARAM4_BASE_IDX ] + regDPid_DP_MSA_TIMING_PARAM4, dccg_regs[id].DP_MSE_RATE_CNTL = ctx->dcn_reg_offsets[regDPid_DP_MSE_RATE_CNTL_BASE_IDX] + regDPid_DP_MSE_RATE_CNTL, dccg_regs[id].DP_MSE_RATE_UPDATE = ctx->dcn_reg_offsets[regDPid_DP_MSE_RATE_UPDATE_BASE_IDX ] + regDPid_DP_MSE_RATE_UPDATE, dccg_regs[id].DP_PIXEL_FORMAT = ctx->dcn_reg_offsets[regDPid_DP_PIXEL_FORMAT_BASE_IDX] + regDPid_DP_PIXEL_FORMAT, dccg_regs[id].DP_SEC_CNTL = ctx-> dcn_reg_offsets[regDPid_DP_SEC_CNTL_BASE_IDX] + regDPid_DP_SEC_CNTL , dccg_regs[id].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[regDPid_DP_SEC_CNTL1_BASE_IDX ] + regDPid_DP_SEC_CNTL1, dccg_regs[id].DP_SEC_CNTL2 = ctx-> dcn_reg_offsets[regDPid_DP_SEC_CNTL2_BASE_IDX] + regDPid_DP_SEC_CNTL2 , dccg_regs[id].DP_SEC_CNTL5 = ctx->dcn_reg_offsets[regDPid_DP_SEC_CNTL5_BASE_IDX ] + regDPid_DP_SEC_CNTL5, dccg_regs[id].DP_SEC_CNTL6 = ctx-> dcn_reg_offsets[regDPid_DP_SEC_CNTL6_BASE_IDX] + regDPid_DP_SEC_CNTL6 , dccg_regs[id].DP_STEER_FIFO = ctx->dcn_reg_offsets[regDPid_DP_STEER_FIFO_BASE_IDX ] + regDPid_DP_STEER_FIFO, dccg_regs[id].DP_VID_M = ctx->dcn_reg_offsets [regDPid_DP_VID_M_BASE_IDX] + regDPid_DP_VID_M, dccg_regs[id] .DP_VID_N = ctx->dcn_reg_offsets[regDPid_DP_VID_N_BASE_IDX ] + regDPid_DP_VID_N, dccg_regs[id].DP_VID_STREAM_CNTL = ctx-> dcn_reg_offsets[regDPid_DP_VID_STREAM_CNTL_BASE_IDX] + regDPid_DP_VID_STREAM_CNTL , dccg_regs[id].DP_VID_TIMING = ctx->dcn_reg_offsets[regDPid_DP_VID_TIMING_BASE_IDX ] + regDPid_DP_VID_TIMING, dccg_regs[id].DP_SEC_AUD_N = ctx-> dcn_reg_offsets[regDPid_DP_SEC_AUD_N_BASE_IDX] + regDPid_DP_SEC_AUD_N , dccg_regs[id].DP_SEC_TIMESTAMP = ctx->dcn_reg_offsets[regDPid_DP_SEC_TIMESTAMP_BASE_IDX ] + regDPid_DP_SEC_TIMESTAMP, dccg_regs[id].DP_DSC_CNTL = ctx ->dcn_reg_offsets[regDPid_DP_DSC_CNTL_BASE_IDX] + regDPid_DP_DSC_CNTL , dccg_regs[id].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets [regDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX] + regDPid_DP_SEC_METADATA_TRANSMISSION , dccg_regs[id].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets [regDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX] + regDIGid_HDMI_METADATA_PACKET_CONTROL , dccg_regs[id].DP_SEC_FRAMING4 = ctx->dcn_reg_offsets[regDPid_DP_SEC_FRAMING4_BASE_IDX ] + regDPid_DP_SEC_FRAMING4, dccg_regs[id].DP_GSP11_CNTL = ctx ->dcn_reg_offsets[regDPid_DP_GSP11_CNTL_BASE_IDX] + regDPid_DP_GSP11_CNTL , dccg_regs[id].DME_CONTROL = ctx->dcn_reg_offsets[regDMEid_DME_CONTROL_BASE_IDX ] + regDMEid_DME_CONTROL, dccg_regs[id].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[regDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX ] + regDPid_DP_SEC_METADATA_TRANSMISSION, dccg_regs[id].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[regDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX ] + regDIGid_HDMI_METADATA_PACKET_CONTROL, dccg_regs[id].DIG_FE_CNTL = ctx->dcn_reg_offsets[regDIGid_DIG_FE_CNTL_BASE_IDX] + regDIGid_DIG_FE_CNTL , dccg_regs[id].DIG_CLOCK_PATTERN = ctx->dcn_reg_offsets[regDIGid_DIG_CLOCK_PATTERN_BASE_IDX ] + regDIGid_DIG_CLOCK_PATTERN, dccg_regs[id].DIG_FIFO_CTRL0 = ctx->dcn_reg_offsets[regDIGid_DIG_FIFO_CTRL0_BASE_IDX] + regDIGid_DIG_FIFO_CTRL0 ) |
289 | |
290 | static struct dcn10_stream_enc_registers stream_enc_regs[5]; |
291 | |
292 | static const struct dcn10_stream_encoder_shift se_shift = { |
293 | SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT).DP_PIXEL_ENCODING = 0x0, .DP_COMPONENT_DEPTH = 0x18, .DP_PIXEL_PER_CYCLE_PROCESSING_MODE = 0x1e, .HDMI_PACKET_GEN_VERSION = 0x4, .HDMI_KEEPOUT_MODE = 0x0, .HDMI_DEEP_COLOR_ENABLE = 0x18, .HDMI_DEEP_COLOR_DEPTH = 0x1c, .HDMI_DATA_SCRAMBLE_EN = 0x1, .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x3, .HDMI_GC_CONT = 0x5, .HDMI_GC_SEND = 0x4, .HDMI_NULL_SEND = 0x0, .HDMI_ACP_SEND = 0xc, .HDMI_AUDIO_INFO_SEND = 0x4, .HDMI_AUDIO_INFO_LINE = 0x8, .HDMI_GC_AVMUTE = 0x0, .DP_MSE_RATE_X = 0x1a, .DP_MSE_RATE_Y = 0x0, .DP_MSE_RATE_UPDATE_PENDING = 0x0, .DP_SEC_GSP0_ENABLE = 0x14, .DP_SEC_STREAM_ENABLE = 0x0, .DP_SEC_GSP1_ENABLE = 0x15 , .DP_SEC_GSP2_ENABLE = 0x16, .DP_SEC_GSP3_ENABLE = 0x17, .DP_SEC_MPG_ENABLE = 0x1c, .DP_SEC_GSP5_LINE_REFERENCE = 0xd, .DP_SEC_GSP4_SEND = 0xc, .DP_SEC_GSP4_SEND_PENDING = 0xd, .DP_SEC_GSP4_LINE_NUM = 0x10, .DP_SEC_GSP5_LINE_NUM = 0x0, .DP_SEC_GSP4_SEND_ANY_LINE = 0xf, .DP_VID_STREAM_DIS_DEFER = 0x8, .DP_VID_STREAM_ENABLE = 0x0, .DP_VID_STREAM_STATUS = 0x10, .DP_STEER_FIFO_RESET = 0x0 , .DP_VID_M_N_GEN_EN = 0x8, .DP_VID_N = 0x0, .DP_VID_M = 0x0, .HDMI_AUDIO_DELAY_EN = 0x4, .HDMI_ACR_AUTO_SEND = 0xc, .HDMI_ACR_SOURCE = 0x8, .HDMI_ACR_AUDIO_PRIORITY = 0x1f, .HDMI_ACR_CTS_32 = 0xc , .HDMI_ACR_N_32 = 0x0, .HDMI_ACR_CTS_44 = 0xc, .HDMI_ACR_N_44 = 0x0, .HDMI_ACR_CTS_48 = 0xc, .HDMI_ACR_N_48 = 0x0, .DP_SEC_AUD_N = 0x0, .DP_SEC_TIMESTAMP_MODE = 0x0, .DP_SEC_ASP_ENABLE = 0x4 , .DP_SEC_ATP_ENABLE = 0x8, .DP_SEC_AIP_ENABLE = 0xc, .DP_SEC_ACM_ENABLE = 0x10, .AFMT_AUDIO_CLOCK_EN = 0x0, .HDMI_CLOCK_CHANNEL_RATE = 0x2, .TMDS_PIXEL_ENCODING = 0x1c, .TMDS_COLOR_FORMAT = 0x1e , .DIG_STEREOSYNC_SELECT = 0x4, .DIG_STEREOSYNC_GATE_EN = 0x8 , .DP_SEC_GSP4_ENABLE = 0x18, .DP_SEC_GSP5_ENABLE = 0x19, .DP_SEC_GSP6_ENABLE = 0x1a, .DP_SEC_GSP7_ENABLE = 0x1b, .DP_SEC_GSP7_SEND = 0x18 , .DP_SEC_GSP7_LINE_NUM = 0x0, .DP_SEC_GSP11_PPS = 0x1c, .DP_SEC_GSP11_ENABLE = 0x4, .DP_SEC_GSP11_LINE_NUM = 0x10, .DP_DB_DISABLE = 0xc, . DP_MSA_MISC0 = 0x18, .DP_MSA_HTOTAL = 0x10, .DP_MSA_VTOTAL = 0x0 , .DP_MSA_HSTART = 0x10, .DP_MSA_VSTART = 0x0, .DP_MSA_HSYNCWIDTH = 0x10, .DP_MSA_HSYNCPOLARITY = 0x1f, .DP_MSA_VSYNCWIDTH = 0x0 , .DP_MSA_VSYNCPOLARITY = 0xf, .DP_MSA_HWIDTH = 0x10, .DP_MSA_VHEIGHT = 0x0, .HDMI_DB_DISABLE = 0xc, .DP_VID_N_MUL = 0xa, .DIG_SOURCE_SELECT = 0x0, .HDMI_GENERIC0_CONT = 0x1, .HDMI_GENERIC0_SEND = 0x0, .HDMI_GENERIC1_CONT = 0x5, .HDMI_GENERIC1_SEND = 0x4, .HDMI_GENERIC2_CONT = 0x9, .HDMI_GENERIC2_SEND = 0x8, .HDMI_GENERIC3_CONT = 0xd, .HDMI_GENERIC3_SEND = 0xc, .HDMI_GENERIC4_CONT = 0x11, .HDMI_GENERIC4_SEND = 0x10, .HDMI_GENERIC5_CONT = 0x15, .HDMI_GENERIC5_SEND = 0x14 , .HDMI_GENERIC6_CONT = 0x19, .HDMI_GENERIC6_SEND = 0x18, .HDMI_GENERIC7_CONT = 0x1d, .HDMI_GENERIC7_SEND = 0x1c, .HDMI_GENERIC8_CONT = 0x1 , .HDMI_GENERIC8_SEND = 0x0, .HDMI_GENERIC9_CONT = 0x5, .HDMI_GENERIC9_SEND = 0x4, .HDMI_GENERIC10_CONT = 0x9, .HDMI_GENERIC10_SEND = 0x8 , .HDMI_GENERIC11_CONT = 0xd, .HDMI_GENERIC11_SEND = 0xc, .HDMI_GENERIC12_CONT = 0x11, .HDMI_GENERIC12_SEND = 0x10, .HDMI_GENERIC13_CONT = 0x15 , .HDMI_GENERIC13_SEND = 0x14, .HDMI_GENERIC14_CONT = 0x19, . HDMI_GENERIC14_SEND = 0x18, .HDMI_GENERIC0_LINE = 0x0, .HDMI_GENERIC1_LINE = 0x10, .HDMI_GENERIC2_LINE = 0x0, .HDMI_GENERIC3_LINE = 0x10 , .HDMI_GENERIC4_LINE = 0x0, .HDMI_GENERIC5_LINE = 0x10, .HDMI_GENERIC6_LINE = 0x0, .HDMI_GENERIC7_LINE = 0x10, .HDMI_GENERIC8_LINE = 0x0 , .HDMI_GENERIC9_LINE = 0x10, .HDMI_GENERIC10_LINE = 0x0, .HDMI_GENERIC11_LINE = 0x10, .HDMI_GENERIC12_LINE = 0x0, .HDMI_GENERIC13_LINE = 0x10 , .HDMI_GENERIC14_LINE = 0x0, .DP_DSC_MODE = 0x0, .DP_VBID6_LINE_REFERENCE = 0xf, .DP_VBID6_LINE_NUM = 0x10, .METADATA_ENGINE_EN = 0x4, .METADATA_HUBP_REQUESTOR_ID = 0x0, .METADATA_STREAM_TYPE = 0x8 , .DP_SEC_METADATA_PACKET_ENABLE = 0x0, .DP_SEC_METADATA_PACKET_LINE_REFERENCE = 0x1, .DP_SEC_METADATA_PACKET_LINE = 0x10, .HDMI_METADATA_PACKET_ENABLE = 0x0, .HDMI_METADATA_PACKET_LINE_REFERENCE = 0x4, .HDMI_METADATA_PACKET_LINE = 0x10, .DOLBY_VISION_EN = 0x12, .DIG_SYMCLK_FE_ON = 0x18, . DP_SST_SDP_SPLITTING = 0x0, .DIG_CLOCK_PATTERN = 0x0, .DIG_FIFO_READ_START_LEVEL = 0x2, .DIG_FIFO_ENABLE = 0x0, .DIG_FIFO_RESET = 0x1, .DIG_FIFO_RESET_DONE = 0x14, .DIG_FIFO_OUTPUT_PIXEL_MODE = 0x8 |
294 | }; |
295 | |
296 | static const struct dcn10_stream_encoder_mask se_mask = { |
297 | SE_COMMON_MASK_SH_LIST_DCN32(_MASK).DP_PIXEL_ENCODING = 0x00000007L, .DP_COMPONENT_DEPTH = 0x07000000L , .DP_PIXEL_PER_CYCLE_PROCESSING_MODE = 0x40000000L, .HDMI_PACKET_GEN_VERSION = 0x00000010L, .HDMI_KEEPOUT_MODE = 0x00000001L, .HDMI_DEEP_COLOR_ENABLE = 0x01000000L, .HDMI_DEEP_COLOR_DEPTH = 0x30000000L, .HDMI_DATA_SCRAMBLE_EN = 0x00000002L, .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x00000008L , .HDMI_GC_CONT = 0x00000020L, .HDMI_GC_SEND = 0x00000010L, . HDMI_NULL_SEND = 0x00000001L, .HDMI_ACP_SEND = 0x00001000L, . HDMI_AUDIO_INFO_SEND = 0x00000010L, .HDMI_AUDIO_INFO_LINE = 0x00003F00L , .HDMI_GC_AVMUTE = 0x00000001L, .DP_MSE_RATE_X = 0xFC000000L , .DP_MSE_RATE_Y = 0x03FFFFFFL, .DP_MSE_RATE_UPDATE_PENDING = 0x00000001L, .DP_SEC_GSP0_ENABLE = 0x00100000L, .DP_SEC_STREAM_ENABLE = 0x00000001L, .DP_SEC_GSP1_ENABLE = 0x00200000L, .DP_SEC_GSP2_ENABLE = 0x00400000L, .DP_SEC_GSP3_ENABLE = 0x00800000L, .DP_SEC_MPG_ENABLE = 0x10000000L, .DP_SEC_GSP5_LINE_REFERENCE = 0x00002000L, .DP_SEC_GSP4_SEND = 0x00001000L, .DP_SEC_GSP4_SEND_PENDING = 0x00002000L, .DP_SEC_GSP4_LINE_NUM = 0xFFFF0000L, .DP_SEC_GSP5_LINE_NUM = 0x0000FFFFL, .DP_SEC_GSP4_SEND_ANY_LINE = 0x00008000L, .DP_VID_STREAM_DIS_DEFER = 0x00000300L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_VID_STREAM_STATUS = 0x00010000L, .DP_STEER_FIFO_RESET = 0x00000001L, .DP_VID_M_N_GEN_EN = 0x00000100L, .DP_VID_N = 0x00FFFFFFL, .DP_VID_M = 0x00FFFFFFL, .HDMI_AUDIO_DELAY_EN = 0x00000030L, .HDMI_ACR_AUTO_SEND = 0x00001000L, .HDMI_ACR_SOURCE = 0x00000100L, .HDMI_ACR_AUDIO_PRIORITY = 0x80000000L, .HDMI_ACR_CTS_32 = 0xFFFFF000L, .HDMI_ACR_N_32 = 0x000FFFFFL, .HDMI_ACR_CTS_44 = 0xFFFFF000L, .HDMI_ACR_N_44 = 0x000FFFFFL, .HDMI_ACR_CTS_48 = 0xFFFFF000L, .HDMI_ACR_N_48 = 0x000FFFFFL, .DP_SEC_AUD_N = 0x00FFFFFFL, .DP_SEC_TIMESTAMP_MODE = 0x00000001L, .DP_SEC_ASP_ENABLE = 0x00000010L, .DP_SEC_ATP_ENABLE = 0x00000100L, .DP_SEC_AIP_ENABLE = 0x00001000L, .DP_SEC_ACM_ENABLE = 0x00010000L, .AFMT_AUDIO_CLOCK_EN = 0x00000001L, .HDMI_CLOCK_CHANNEL_RATE = 0x00000004L, .TMDS_PIXEL_ENCODING = 0x10000000L, .TMDS_COLOR_FORMAT = 0xC0000000L, .DIG_STEREOSYNC_SELECT = 0x00000070L, .DIG_STEREOSYNC_GATE_EN = 0x00000100L, .DP_SEC_GSP4_ENABLE = 0x01000000L, .DP_SEC_GSP5_ENABLE = 0x02000000L, .DP_SEC_GSP6_ENABLE = 0x04000000L, .DP_SEC_GSP7_ENABLE = 0x08000000L, .DP_SEC_GSP7_SEND = 0x01000000L, .DP_SEC_GSP7_LINE_NUM = 0x0000FFFFL, .DP_SEC_GSP11_PPS = 0x10000000L, .DP_SEC_GSP11_ENABLE = 0x00000010L, .DP_SEC_GSP11_LINE_NUM = 0xFFFF0000L, .DP_DB_DISABLE = 0x00001000L, .DP_MSA_MISC0 = 0xFF000000L, .DP_MSA_HTOTAL = 0xFFFF0000L, .DP_MSA_VTOTAL = 0x0000FFFFL , .DP_MSA_HSTART = 0xFFFF0000L, .DP_MSA_VSTART = 0x0000FFFFL, .DP_MSA_HSYNCWIDTH = 0x7FFF0000L, .DP_MSA_HSYNCPOLARITY = 0x80000000L , .DP_MSA_VSYNCWIDTH = 0x00007FFFL, .DP_MSA_VSYNCPOLARITY = 0x00008000L , .DP_MSA_HWIDTH = 0xFFFF0000L, .DP_MSA_VHEIGHT = 0x0000FFFFL , .HDMI_DB_DISABLE = 0x00001000L, .DP_VID_N_MUL = 0x00000C00L , .DIG_SOURCE_SELECT = 0x00000007L, .HDMI_GENERIC0_CONT = 0x00000002L , .HDMI_GENERIC0_SEND = 0x00000001L, .HDMI_GENERIC1_CONT = 0x00000020L , .HDMI_GENERIC1_SEND = 0x00000010L, .HDMI_GENERIC2_CONT = 0x00000200L , .HDMI_GENERIC2_SEND = 0x00000100L, .HDMI_GENERIC3_CONT = 0x00002000L , .HDMI_GENERIC3_SEND = 0x00001000L, .HDMI_GENERIC4_CONT = 0x00020000L , .HDMI_GENERIC4_SEND = 0x00010000L, .HDMI_GENERIC5_CONT = 0x00200000L , .HDMI_GENERIC5_SEND = 0x00100000L, .HDMI_GENERIC6_CONT = 0x02000000L , .HDMI_GENERIC6_SEND = 0x01000000L, .HDMI_GENERIC7_CONT = 0x20000000L , .HDMI_GENERIC7_SEND = 0x10000000L, .HDMI_GENERIC8_CONT = 0x00000002L , .HDMI_GENERIC8_SEND = 0x00000001L, .HDMI_GENERIC9_CONT = 0x00000020L , .HDMI_GENERIC9_SEND = 0x00000010L, .HDMI_GENERIC10_CONT = 0x00000200L , .HDMI_GENERIC10_SEND = 0x00000100L, .HDMI_GENERIC11_CONT = 0x00002000L , .HDMI_GENERIC11_SEND = 0x00001000L, .HDMI_GENERIC12_CONT = 0x00020000L , .HDMI_GENERIC12_SEND = 0x00010000L, .HDMI_GENERIC13_CONT = 0x00200000L , .HDMI_GENERIC13_SEND = 0x00100000L, .HDMI_GENERIC14_CONT = 0x02000000L , .HDMI_GENERIC14_SEND = 0x01000000L, .HDMI_GENERIC0_LINE = 0x0000FFFFL , .HDMI_GENERIC1_LINE = 0xFFFF0000L, .HDMI_GENERIC2_LINE = 0x0000FFFFL , .HDMI_GENERIC3_LINE = 0xFFFF0000L, .HDMI_GENERIC4_LINE = 0x0000FFFFL , .HDMI_GENERIC5_LINE = 0xFFFF0000L, .HDMI_GENERIC6_LINE = 0x0000FFFFL , .HDMI_GENERIC7_LINE = 0xFFFF0000L, .HDMI_GENERIC8_LINE = 0x0000FFFFL , .HDMI_GENERIC9_LINE = 0xFFFF0000L, .HDMI_GENERIC10_LINE = 0x0000FFFFL , .HDMI_GENERIC11_LINE = 0xFFFF0000L, .HDMI_GENERIC12_LINE = 0x0000FFFFL , .HDMI_GENERIC13_LINE = 0xFFFF0000L, .HDMI_GENERIC14_LINE = 0x0000FFFFL , .DP_DSC_MODE = 0x00000001L, .DP_VBID6_LINE_REFERENCE = 0x00008000L , .DP_VBID6_LINE_NUM = 0xFFFF0000L, .METADATA_ENGINE_EN = 0x00000010L , .METADATA_HUBP_REQUESTOR_ID = 0x00000007L, .METADATA_STREAM_TYPE = 0x00000100L, .DP_SEC_METADATA_PACKET_ENABLE = 0x00000001L, .DP_SEC_METADATA_PACKET_LINE_REFERENCE = 0x00000002L, .DP_SEC_METADATA_PACKET_LINE = 0xFFFF0000L, .HDMI_METADATA_PACKET_ENABLE = 0x00000001L, . HDMI_METADATA_PACKET_LINE_REFERENCE = 0x00000010L, .HDMI_METADATA_PACKET_LINE = 0xFFFF0000L, .DOLBY_VISION_EN = 0x00040000L, .DIG_SYMCLK_FE_ON = 0x01000000L, .DP_SST_SDP_SPLITTING = 0x00000001L, .DIG_CLOCK_PATTERN = 0x000003FFL, .DIG_FIFO_READ_START_LEVEL = 0x0000007CL, .DIG_FIFO_ENABLE = 0x00000001L, .DIG_FIFO_RESET = 0x00000002L, .DIG_FIFO_RESET_DONE = 0x00100000L, .DIG_FIFO_OUTPUT_PIXEL_MODE = 0x00000100L |
298 | }; |
299 | |
300 | |
301 | #define aux_regs_init(id)( ( dccg_regs[id].AUX_CONTROL = ctx->dcn_reg_offsets[regDP_AUXid_AUX_CONTROL_BASE_IDX ] + regDP_AUXid_AUX_CONTROL, dccg_regs[id].AUX_DPHY_RX_CONTROL0 = ctx->dcn_reg_offsets[regDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX ] + regDP_AUXid_AUX_DPHY_RX_CONTROL0, dccg_regs[id].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets[regDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX ] + regDP_AUXid_AUX_DPHY_RX_CONTROL1 ), dccg_regs[id].AUX_DPHY_TX_CONTROL = ctx->dcn_reg_offsets[regDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX ] + regDP_AUXid_AUX_DPHY_TX_CONTROL )\ |
302 | DCN2_AUX_REG_LIST_RI(id)( ( dccg_regs[id].AUX_CONTROL = ctx->dcn_reg_offsets[regDP_AUXid_AUX_CONTROL_BASE_IDX ] + regDP_AUXid_AUX_CONTROL, dccg_regs[id].AUX_DPHY_RX_CONTROL0 = ctx->dcn_reg_offsets[regDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX ] + regDP_AUXid_AUX_DPHY_RX_CONTROL0, dccg_regs[id].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets[regDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX ] + regDP_AUXid_AUX_DPHY_RX_CONTROL1 ), dccg_regs[id].AUX_DPHY_TX_CONTROL = ctx->dcn_reg_offsets[regDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX ] + regDP_AUXid_AUX_DPHY_TX_CONTROL ) |
303 | |
304 | static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; |
305 | |
306 | #define hpd_regs_init(id)dccg_regs[id].DC_HPD_CONTROL = ctx->dcn_reg_offsets[regHPDid_DC_HPD_CONTROL_BASE_IDX ] + regHPDid_DC_HPD_CONTROL\ |
307 | HPD_REG_LIST_RI(id)dccg_regs[id].DC_HPD_CONTROL = ctx->dcn_reg_offsets[regHPDid_DC_HPD_CONTROL_BASE_IDX ] + regHPDid_DC_HPD_CONTROL |
308 | |
309 | static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; |
310 | |
311 | #define link_regs_init(id, phyid)( ( ( dccg_regs[id].DIG_BE_CNTL = ctx->dcn_reg_offsets[regDIGid_DIG_BE_CNTL_BASE_IDX ] + regDIGid_DIG_BE_CNTL, dccg_regs[id].DIG_BE_EN_CNTL = ctx-> dcn_reg_offsets[regDIGid_DIG_BE_EN_CNTL_BASE_IDX] + regDIGid_DIG_BE_EN_CNTL , dccg_regs[id].TMDS_CTL_BITS = ctx->dcn_reg_offsets[regDIGid_TMDS_CTL_BITS_BASE_IDX ] + regDIGid_TMDS_CTL_BITS, dccg_regs[id].TMDS_DCBALANCER_CONTROL = ctx->dcn_reg_offsets[regDIGid_TMDS_DCBALANCER_CONTROL_BASE_IDX ] + regDIGid_TMDS_DCBALANCER_CONTROL, dccg_regs[id].DP_CONFIG = ctx->dcn_reg_offsets[regDPid_DP_CONFIG_BASE_IDX] + regDPid_DP_CONFIG , dccg_regs[id].DP_DPHY_CNTL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_CNTL_BASE_IDX ] + regDPid_DP_DPHY_CNTL, dccg_regs[id].DP_DPHY_PRBS_CNTL = ctx ->dcn_reg_offsets[regDPid_DP_DPHY_PRBS_CNTL_BASE_IDX] + regDPid_DP_DPHY_PRBS_CNTL , dccg_regs[id].DP_DPHY_SCRAM_CNTL = ctx->dcn_reg_offsets[ regDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX] + regDPid_DP_DPHY_SCRAM_CNTL , dccg_regs[id].DP_DPHY_SYM0 = ctx->dcn_reg_offsets[regDPid_DP_DPHY_SYM0_BASE_IDX ] + regDPid_DP_DPHY_SYM0, dccg_regs[id].DP_DPHY_SYM1 = ctx-> dcn_reg_offsets[regDPid_DP_DPHY_SYM1_BASE_IDX] + regDPid_DP_DPHY_SYM1 , dccg_regs[id].DP_DPHY_SYM2 = ctx->dcn_reg_offsets[regDPid_DP_DPHY_SYM2_BASE_IDX ] + regDPid_DP_DPHY_SYM2, dccg_regs[id].DP_DPHY_TRAINING_PATTERN_SEL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX ] + regDPid_DP_DPHY_TRAINING_PATTERN_SEL, dccg_regs[id].DP_LINK_CNTL = ctx->dcn_reg_offsets[regDPid_DP_LINK_CNTL_BASE_IDX] + regDPid_DP_LINK_CNTL , dccg_regs[id].DP_LINK_FRAMING_CNTL = ctx->dcn_reg_offsets [regDPid_DP_LINK_FRAMING_CNTL_BASE_IDX] + regDPid_DP_LINK_FRAMING_CNTL , dccg_regs[id].DP_MSE_SAT0 = ctx->dcn_reg_offsets[regDPid_DP_MSE_SAT0_BASE_IDX ] + regDPid_DP_MSE_SAT0, dccg_regs[id].DP_MSE_SAT1 = ctx-> dcn_reg_offsets[regDPid_DP_MSE_SAT1_BASE_IDX] + regDPid_DP_MSE_SAT1 , dccg_regs[id].DP_MSE_SAT2 = ctx->dcn_reg_offsets[regDPid_DP_MSE_SAT2_BASE_IDX ] + regDPid_DP_MSE_SAT2, dccg_regs[id].DP_MSE_SAT_UPDATE = ctx ->dcn_reg_offsets[regDPid_DP_MSE_SAT_UPDATE_BASE_IDX] + regDPid_DP_MSE_SAT_UPDATE , dccg_regs[id].DP_SEC_CNTL = ctx->dcn_reg_offsets[regDPid_DP_SEC_CNTL_BASE_IDX ] + regDPid_DP_SEC_CNTL, dccg_regs[id].DP_VID_STREAM_CNTL = ctx ->dcn_reg_offsets[regDPid_DP_VID_STREAM_CNTL_BASE_IDX] + regDPid_DP_VID_STREAM_CNTL , dccg_regs[id].DP_DPHY_FAST_TRAINING = ctx->dcn_reg_offsets [regDPid_DP_DPHY_FAST_TRAINING_BASE_IDX] + regDPid_DP_DPHY_FAST_TRAINING , dccg_regs[id].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[regDPid_DP_SEC_CNTL1_BASE_IDX ] + regDPid_DP_SEC_CNTL1, dccg_regs[id].DP_DPHY_BS_SR_SWAP_CNTL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX ] + regDPid_DP_DPHY_BS_SR_SWAP_CNTL, dccg_regs[id].DP_DPHY_HBR2_PATTERN_CONTROL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX ] + regDPid_DP_DPHY_HBR2_PATTERN_CONTROL ), dccg_regs[id].DP_DPHY_INTERNAL_CTRL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX ] + regDPid_DP_DPHY_INTERNAL_CTRL, dccg_regs[id].DIO_LINKA_CNTL = ctx->dcn_reg_offsets[2] + 0x1f04, dccg_regs[id].DIO_LINKB_CNTL = ctx->dcn_reg_offsets[2] + 0x1f05, dccg_regs[id].DIO_LINKC_CNTL = ctx->dcn_reg_offsets[2] + 0x1f06, dccg_regs[id].DIO_LINKD_CNTL = ctx->dcn_reg_offsets[2] + 0x1f07, dccg_regs[id].DIO_LINKE_CNTL = ctx->dcn_reg_offsets[2] + 0x1f08, dccg_regs[id].DIO_LINKF_CNTL = ctx->dcn_reg_offsets[2] + 0x1f09 ), ( dccg_regs[id].CLOCK_ENABLE = ctx->dcn_reg_offsets[regSYMCLKphyid_CLOCK_ENABLE_BASE_IDX ] + regSYMCLKphyid_CLOCK_ENABLE, dccg_regs[id].CHANNEL_XBAR_CNTL = ctx->dcn_reg_offsets[regUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX ] + regUNIPHYphyid_CHANNEL_XBAR_CNTL ) )\ |
312 | ( \ |
313 | LE_DCN31_REG_LIST_RI(id)( ( dccg_regs[id].DIG_BE_CNTL = ctx->dcn_reg_offsets[regDIGid_DIG_BE_CNTL_BASE_IDX ] + regDIGid_DIG_BE_CNTL, dccg_regs[id].DIG_BE_EN_CNTL = ctx-> dcn_reg_offsets[regDIGid_DIG_BE_EN_CNTL_BASE_IDX] + regDIGid_DIG_BE_EN_CNTL , dccg_regs[id].TMDS_CTL_BITS = ctx->dcn_reg_offsets[regDIGid_TMDS_CTL_BITS_BASE_IDX ] + regDIGid_TMDS_CTL_BITS, dccg_regs[id].TMDS_DCBALANCER_CONTROL = ctx->dcn_reg_offsets[regDIGid_TMDS_DCBALANCER_CONTROL_BASE_IDX ] + regDIGid_TMDS_DCBALANCER_CONTROL, dccg_regs[id].DP_CONFIG = ctx->dcn_reg_offsets[regDPid_DP_CONFIG_BASE_IDX] + regDPid_DP_CONFIG , dccg_regs[id].DP_DPHY_CNTL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_CNTL_BASE_IDX ] + regDPid_DP_DPHY_CNTL, dccg_regs[id].DP_DPHY_PRBS_CNTL = ctx ->dcn_reg_offsets[regDPid_DP_DPHY_PRBS_CNTL_BASE_IDX] + regDPid_DP_DPHY_PRBS_CNTL , dccg_regs[id].DP_DPHY_SCRAM_CNTL = ctx->dcn_reg_offsets[ regDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX] + regDPid_DP_DPHY_SCRAM_CNTL , dccg_regs[id].DP_DPHY_SYM0 = ctx->dcn_reg_offsets[regDPid_DP_DPHY_SYM0_BASE_IDX ] + regDPid_DP_DPHY_SYM0, dccg_regs[id].DP_DPHY_SYM1 = ctx-> dcn_reg_offsets[regDPid_DP_DPHY_SYM1_BASE_IDX] + regDPid_DP_DPHY_SYM1 , dccg_regs[id].DP_DPHY_SYM2 = ctx->dcn_reg_offsets[regDPid_DP_DPHY_SYM2_BASE_IDX ] + regDPid_DP_DPHY_SYM2, dccg_regs[id].DP_DPHY_TRAINING_PATTERN_SEL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX ] + regDPid_DP_DPHY_TRAINING_PATTERN_SEL, dccg_regs[id].DP_LINK_CNTL = ctx->dcn_reg_offsets[regDPid_DP_LINK_CNTL_BASE_IDX] + regDPid_DP_LINK_CNTL , dccg_regs[id].DP_LINK_FRAMING_CNTL = ctx->dcn_reg_offsets [regDPid_DP_LINK_FRAMING_CNTL_BASE_IDX] + regDPid_DP_LINK_FRAMING_CNTL , dccg_regs[id].DP_MSE_SAT0 = ctx->dcn_reg_offsets[regDPid_DP_MSE_SAT0_BASE_IDX ] + regDPid_DP_MSE_SAT0, dccg_regs[id].DP_MSE_SAT1 = ctx-> dcn_reg_offsets[regDPid_DP_MSE_SAT1_BASE_IDX] + regDPid_DP_MSE_SAT1 , dccg_regs[id].DP_MSE_SAT2 = ctx->dcn_reg_offsets[regDPid_DP_MSE_SAT2_BASE_IDX ] + regDPid_DP_MSE_SAT2, dccg_regs[id].DP_MSE_SAT_UPDATE = ctx ->dcn_reg_offsets[regDPid_DP_MSE_SAT_UPDATE_BASE_IDX] + regDPid_DP_MSE_SAT_UPDATE , dccg_regs[id].DP_SEC_CNTL = ctx->dcn_reg_offsets[regDPid_DP_SEC_CNTL_BASE_IDX ] + regDPid_DP_SEC_CNTL, dccg_regs[id].DP_VID_STREAM_CNTL = ctx ->dcn_reg_offsets[regDPid_DP_VID_STREAM_CNTL_BASE_IDX] + regDPid_DP_VID_STREAM_CNTL , dccg_regs[id].DP_DPHY_FAST_TRAINING = ctx->dcn_reg_offsets [regDPid_DP_DPHY_FAST_TRAINING_BASE_IDX] + regDPid_DP_DPHY_FAST_TRAINING , dccg_regs[id].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[regDPid_DP_SEC_CNTL1_BASE_IDX ] + regDPid_DP_SEC_CNTL1, dccg_regs[id].DP_DPHY_BS_SR_SWAP_CNTL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX ] + regDPid_DP_DPHY_BS_SR_SWAP_CNTL, dccg_regs[id].DP_DPHY_HBR2_PATTERN_CONTROL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX ] + regDPid_DP_DPHY_HBR2_PATTERN_CONTROL ), dccg_regs[id].DP_DPHY_INTERNAL_CTRL = ctx->dcn_reg_offsets[regDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX ] + regDPid_DP_DPHY_INTERNAL_CTRL, dccg_regs[id].DIO_LINKA_CNTL = ctx->dcn_reg_offsets[2] + 0x1f04, dccg_regs[id].DIO_LINKB_CNTL = ctx->dcn_reg_offsets[2] + 0x1f05, dccg_regs[id].DIO_LINKC_CNTL = ctx->dcn_reg_offsets[2] + 0x1f06, dccg_regs[id].DIO_LINKD_CNTL = ctx->dcn_reg_offsets[2] + 0x1f07, dccg_regs[id].DIO_LINKE_CNTL = ctx->dcn_reg_offsets[2] + 0x1f08, dccg_regs[id].DIO_LINKF_CNTL = ctx->dcn_reg_offsets[2] + 0x1f09 ), \ |
314 | UNIPHY_DCN2_REG_LIST_RI(id, phyid)( dccg_regs[id].CLOCK_ENABLE = ctx->dcn_reg_offsets[regSYMCLKphyid_CLOCK_ENABLE_BASE_IDX ] + regSYMCLKphyid_CLOCK_ENABLE, dccg_regs[id].CHANNEL_XBAR_CNTL = ctx->dcn_reg_offsets[regUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX ] + regUNIPHYphyid_CHANNEL_XBAR_CNTL )\ |
315 | ) |
316 | /*DPCS_DCN31_REG_LIST(id),*/ \ |
317 | |
318 | static struct dcn10_link_enc_registers link_enc_regs[5]; |
319 | |
320 | static const struct dcn10_link_enc_shift le_shift = { |
321 | LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT).DIG_ENABLE = 0x0, .DIG_HPD_SELECT = 0x1c, .DIG_MODE = 0x10, . DIG_FE_SOURCE_SELECT = 0x8, .DIG_CLOCK_PATTERN = 0x0, .TMDS_CTL0 = 0x0, .DPHY_BYPASS = 0x10, .DPHY_ATEST_SEL_LANE0 = 0x0, .DPHY_ATEST_SEL_LANE1 = 0x1, .DPHY_ATEST_SEL_LANE2 = 0x2, .DPHY_ATEST_SEL_LANE3 = 0x3 , .DPHY_PRBS_EN = 0x0, .DPHY_PRBS_SEL = 0x4, .DPHY_SYM1 = 0x0 , .DPHY_SYM2 = 0xa, .DPHY_SYM3 = 0x14, .DPHY_SYM4 = 0x0, .DPHY_SYM5 = 0xa, .DPHY_SYM6 = 0x14, .DPHY_SYM7 = 0x0, .DPHY_SYM8 = 0xa , .DPHY_SCRAMBLER_BS_COUNT = 0x8, .DPHY_SCRAMBLER_ADVANCE = 0x4 , .DPHY_RX_FAST_TRAINING_CAPABLE = 0x0, .DPHY_LOAD_BS_COUNT = 0x0, .DPHY_TRAINING_PATTERN_SEL = 0x0, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x0, .DP_LINK_TRAINING_COMPLETE = 0x4, .DP_IDLE_BS_INTERVAL = 0x0, .DP_VBID_DISABLE = 0x18, .DP_VID_ENHANCED_FRAME_MODE = 0x1c, .DP_VID_STREAM_ENABLE = 0x0, .DP_UDI_LANES = 0x0, .DP_SEC_GSP0_LINE_NUM = 0x10, .DP_SEC_GSP0_PRIORITY = 0x4, .DP_MSE_SAT_SRC0 = 0x0, .DP_MSE_SAT_SRC1 = 0x10, .DP_MSE_SAT_SLOT_COUNT0 = 0x8, .DP_MSE_SAT_SLOT_COUNT1 = 0x18, .DP_MSE_SAT_SRC2 = 0x0, .DP_MSE_SAT_SRC3 = 0x10, .DP_MSE_SAT_SLOT_COUNT2 = 0x8, .DP_MSE_SAT_SLOT_COUNT3 = 0x18, .DP_MSE_SAT_UPDATE = 0x0 , .DP_MSE_16_MTP_KEEPOUT = 0x8, .AUX_HPD_SEL = 0x14, .AUX_LS_READ_EN = 0x8, .AUX_RX_RECEIVE_WINDOW = 0x8, .DC_HPD_EN = 0x1c, .DPHY_FEC_EN = 0x4, .DPHY_FEC_READY_SHADOW = 0x5, .DPHY_FEC_ACTIVE_STATUS = 0x6, .TMDS_CTL0 = 0x0, .AUX_RX_START_WINDOW = 0x4, .AUX_RX_HALF_SYM_DETECT_LEN = 0xc, .AUX_RX_TRANSITION_FILTER_EN = 0x10, .AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x11, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = 0x12, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = 0x13, .AUX_RX_PHASE_DETECT_LEN = 0x14, .AUX_RX_DETECTION_THRESHOLD = 0x1c, .AUX_TX_PRECHARGE_LEN = 0x0, .AUX_TX_PRECHARGE_SYMBOLS = 0x8, .AUX_MODE_DET_CHECK_DELAY = 0x10, .AUX_RX_PRECHARGE_SKIP = 0x0, .AUX_RX_TIMEOUT_LEN = 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf , .ENC_TYPE_SEL = 0x0, .HPO_DP_ENC_SEL = 0x8, .HPO_HDMI_ENC_SEL = 0x4, \ |
322 | //DPCS_DCN31_MASK_SH_LIST(__SHIFT) |
323 | }; |
324 | |
325 | static const struct dcn10_link_enc_mask le_mask = { |
326 | LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK).DIG_ENABLE = 0x00000001L, .DIG_HPD_SELECT = 0x70000000L, .DIG_MODE = 0x00070000L, .DIG_FE_SOURCE_SELECT = 0x00007F00L, .DIG_CLOCK_PATTERN = 0x000003FFL, .TMDS_CTL0 = 0x00000001L, .DPHY_BYPASS = 0x00010000L , .DPHY_ATEST_SEL_LANE0 = 0x00000001L, .DPHY_ATEST_SEL_LANE1 = 0x00000002L, .DPHY_ATEST_SEL_LANE2 = 0x00000004L, .DPHY_ATEST_SEL_LANE3 = 0x00000008L, .DPHY_PRBS_EN = 0x00000001L, .DPHY_PRBS_SEL = 0x00000030L, .DPHY_SYM1 = 0x000003FFL, .DPHY_SYM2 = 0x000FFC00L , .DPHY_SYM3 = 0x3FF00000L, .DPHY_SYM4 = 0x000003FFL, .DPHY_SYM5 = 0x000FFC00L, .DPHY_SYM6 = 0x3FF00000L, .DPHY_SYM7 = 0x000003FFL , .DPHY_SYM8 = 0x000FFC00L, .DPHY_SCRAMBLER_BS_COUNT = 0x0003FF00L , .DPHY_SCRAMBLER_ADVANCE = 0x00000010L, .DPHY_RX_FAST_TRAINING_CAPABLE = 0x00000001L, .DPHY_LOAD_BS_COUNT = 0x000003FFL, .DPHY_TRAINING_PATTERN_SEL = 0x00000003L, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x00000007L, . DP_LINK_TRAINING_COMPLETE = 0x00000010L, .DP_IDLE_BS_INTERVAL = 0x0003FFFFL, .DP_VBID_DISABLE = 0x01000000L, .DP_VID_ENHANCED_FRAME_MODE = 0x10000000L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_UDI_LANES = 0x00000003L, .DP_SEC_GSP0_LINE_NUM = 0xFFFF0000L, .DP_SEC_GSP0_PRIORITY = 0x00000010L, .DP_MSE_SAT_SRC0 = 0x00000007L, .DP_MSE_SAT_SRC1 = 0x00070000L, .DP_MSE_SAT_SLOT_COUNT0 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT1 = 0x3F000000L, .DP_MSE_SAT_SRC2 = 0x00000007L, .DP_MSE_SAT_SRC3 = 0x00070000L, .DP_MSE_SAT_SLOT_COUNT2 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT3 = 0x3F000000L, .DP_MSE_SAT_UPDATE = 0x00000003L, .DP_MSE_16_MTP_KEEPOUT = 0x00000100L, .AUX_HPD_SEL = 0x00700000L, .AUX_LS_READ_EN = 0x00000100L, .AUX_RX_RECEIVE_WINDOW = 0x00000700L, .DC_HPD_EN = 0x10000000L, .DPHY_FEC_EN = 0x00000010L, .DPHY_FEC_READY_SHADOW = 0x00000020L, .DPHY_FEC_ACTIVE_STATUS = 0x00000040L, .TMDS_CTL0 = 0x00000001L, .AUX_RX_START_WINDOW = 0x00000070L, .AUX_RX_HALF_SYM_DETECT_LEN = 0x00003000L, .AUX_RX_TRANSITION_FILTER_EN = 0x00010000L, . AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00020000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = 0x00040000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = 0x00080000L , .AUX_RX_PHASE_DETECT_LEN = 0x00300000L, .AUX_RX_DETECTION_THRESHOLD = 0x70000000L, .AUX_TX_PRECHARGE_LEN = 0x0000000FL, .AUX_TX_PRECHARGE_SYMBOLS = 0x00003F00L, .AUX_MODE_DET_CHECK_DELAY = 0x00070000L, .AUX_RX_PRECHARGE_SKIP = 0x000000FFL, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL = 0x00018000L, .ENC_TYPE_SEL = 0x00000003L, .HPO_DP_ENC_SEL = 0x00000700L, .HPO_HDMI_ENC_SEL = 0x00000070L, \ |
327 | |
328 | //DPCS_DCN31_MASK_SH_LIST(_MASK) |
329 | }; |
330 | |
331 | #define hpo_dp_stream_encoder_reg_init(id)( dccg_regs[id].DP_STREAM_MAPPER_CONTROL0 = ctx->dcn_reg_offsets [3] + 0x0e56, dccg_regs[id].DP_STREAM_MAPPER_CONTROL1 = ctx-> dcn_reg_offsets[3] + 0x0e57, dccg_regs[id].DP_STREAM_MAPPER_CONTROL2 = ctx->dcn_reg_offsets[3] + 0x0e58, dccg_regs[id].DP_STREAM_MAPPER_CONTROL3 = ctx->dcn_reg_offsets[3] + 0x0e59, dccg_regs[id].DP_STREAM_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets[regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX ] + regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_CONTROL, dccg_regs [id].DP_STREAM_ENC_INPUT_MUX_CONTROL = ctx->dcn_reg_offsets [regDP_STREAM_ENCid_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX] + regDP_STREAM_ENCid_DP_STREAM_ENC_INPUT_MUX_CONTROL, dccg_regs [id].DP_STREAM_ENC_AUDIO_CONTROL = ctx->dcn_reg_offsets[regDP_STREAM_ENCid_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX ] + regDP_STREAM_ENCid_DP_STREAM_ENC_AUDIO_CONTROL, dccg_regs [id].DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = ctx->dcn_reg_offsets[regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX ] + regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 , dccg_regs[id].DP_SYM32_ENC_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_PIXEL_FORMAT = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT , dccg_regs[id].DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_MSA0 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA0_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA0 , dccg_regs[id].DP_SYM32_ENC_VID_MSA1 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA1_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA1 , dccg_regs[id].DP_SYM32_ENC_VID_MSA2 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA2_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA2 , dccg_regs[id].DP_SYM32_ENC_VID_MSA3 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA3_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA3 , dccg_regs[id].DP_SYM32_ENC_VID_MSA4 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA4_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA4 , dccg_regs[id].DP_SYM32_ENC_VID_MSA5 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA5_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA5 , dccg_regs[id].DP_SYM32_ENC_VID_MSA6 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA6_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA6 , dccg_regs[id].DP_SYM32_ENC_VID_MSA7 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA7_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA7 , dccg_regs[id].DP_SYM32_ENC_VID_MSA8 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA8_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA8 , dccg_regs[id].DP_SYM32_ENC_VID_MSA_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = ctx ->dcn_reg_offsets[regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_FIFO_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_FIFO_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_STREAM_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_STREAM_CONTROL, dccg_regs [id].DP_SYM32_ENC_VID_VBID_CONTROL = ctx->dcn_reg_offsets[ regDP_SYM32_ENCid_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_VBID_CONTROL , dccg_regs[id].DP_SYM32_ENC_SDP_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_CONTROL , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL0 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL0 , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL2 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL2 , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL3 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL3 , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL5 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL5 , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL11 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL11, dccg_regs[ id].DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL , dccg_regs[id].DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, dccg_regs [id].DP_SYM32_ENC_VID_CRC_CONTROL = ctx->dcn_reg_offsets[regDP_SYM32_ENCid_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_CRC_CONTROL, dccg_regs [id].DP_SYM32_ENC_HBLANK_CONTROL = ctx->dcn_reg_offsets[regDP_SYM32_ENCid_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_HBLANK_CONTROL )\ |
332 | DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)( dccg_regs[id].DP_STREAM_MAPPER_CONTROL0 = ctx->dcn_reg_offsets [3] + 0x0e56, dccg_regs[id].DP_STREAM_MAPPER_CONTROL1 = ctx-> dcn_reg_offsets[3] + 0x0e57, dccg_regs[id].DP_STREAM_MAPPER_CONTROL2 = ctx->dcn_reg_offsets[3] + 0x0e58, dccg_regs[id].DP_STREAM_MAPPER_CONTROL3 = ctx->dcn_reg_offsets[3] + 0x0e59, dccg_regs[id].DP_STREAM_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets[regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX ] + regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_CONTROL, dccg_regs [id].DP_STREAM_ENC_INPUT_MUX_CONTROL = ctx->dcn_reg_offsets [regDP_STREAM_ENCid_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX] + regDP_STREAM_ENCid_DP_STREAM_ENC_INPUT_MUX_CONTROL, dccg_regs [id].DP_STREAM_ENC_AUDIO_CONTROL = ctx->dcn_reg_offsets[regDP_STREAM_ENCid_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX ] + regDP_STREAM_ENCid_DP_STREAM_ENC_AUDIO_CONTROL, dccg_regs [id].DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = ctx->dcn_reg_offsets[regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX ] + regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 , dccg_regs[id].DP_SYM32_ENC_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_PIXEL_FORMAT = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT , dccg_regs[id].DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_MSA0 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA0_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA0 , dccg_regs[id].DP_SYM32_ENC_VID_MSA1 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA1_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA1 , dccg_regs[id].DP_SYM32_ENC_VID_MSA2 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA2_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA2 , dccg_regs[id].DP_SYM32_ENC_VID_MSA3 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA3_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA3 , dccg_regs[id].DP_SYM32_ENC_VID_MSA4 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA4_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA4 , dccg_regs[id].DP_SYM32_ENC_VID_MSA5 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA5_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA5 , dccg_regs[id].DP_SYM32_ENC_VID_MSA6 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA6_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA6 , dccg_regs[id].DP_SYM32_ENC_VID_MSA7 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA7_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA7 , dccg_regs[id].DP_SYM32_ENC_VID_MSA8 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA8_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA8 , dccg_regs[id].DP_SYM32_ENC_VID_MSA_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = ctx ->dcn_reg_offsets[regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_FIFO_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_FIFO_CONTROL , dccg_regs[id].DP_SYM32_ENC_VID_STREAM_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_STREAM_CONTROL, dccg_regs [id].DP_SYM32_ENC_VID_VBID_CONTROL = ctx->dcn_reg_offsets[ regDP_SYM32_ENCid_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_VBID_CONTROL , dccg_regs[id].DP_SYM32_ENC_SDP_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_CONTROL , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL0 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL0 , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL2 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL2 , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL3 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL3 , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL5 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL5 , dccg_regs[id].DP_SYM32_ENC_SDP_GSP_CONTROL11 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL11, dccg_regs[ id].DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL , dccg_regs[id].DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = ctx->dcn_reg_offsets [regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX] + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, dccg_regs [id].DP_SYM32_ENC_VID_CRC_CONTROL = ctx->dcn_reg_offsets[regDP_SYM32_ENCid_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_CRC_CONTROL, dccg_regs [id].DP_SYM32_ENC_HBLANK_CONTROL = ctx->dcn_reg_offsets[regDP_SYM32_ENCid_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX ] + regDP_SYM32_ENCid_DP_SYM32_ENC_HBLANK_CONTROL ) |
333 | |
334 | static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; |
335 | |
336 | static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { |
337 | DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT).DP_STREAM_LINK_TARGET = 0x0, .DP_STREAM_ENC_CLOCK_EN = 0x0, . DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL = 0x0, .DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL = 0x0, .FIFO_RESET = 0x4, .FIFO_RESET_DONE = 0x14, .FIFO_ENABLE = 0x0, .DP_SYM32_ENC_RESET = 0x4, .DP_SYM32_ENC_RESET_DONE = 0x8, .DP_SYM32_ENC_ENABLE = 0x0, .PIXEL_ENCODING_TYPE = 0x0, .UNCOMPRESSED_PIXEL_ENCODING = 0x4, .UNCOMPRESSED_COMPONENT_DEPTH = 0x8, .PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE = 0x0, .MSA_DOUBLE_BUFFER_ENABLE = 0x0, .MSA_DATA_LANE_0 = 0x0, .MSA_DATA_LANE_1 = 0x8, .MSA_DATA_LANE_2 = 0x10, .MSA_DATA_LANE_3 = 0x18, .PIXEL_TO_SYMBOL_FIFO_RESET = 0x4, .PIXEL_TO_SYMBOL_FIFO_RESET_DONE = 0x8, .PIXEL_TO_SYMBOL_FIFO_ENABLE = 0x0, .VID_STREAM_ENABLE = 0x0, .VID_STREAM_STATUS = 0x8, . VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE = 0x0, .VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER = 0x10, .SDP_STREAM_ENABLE = 0x0, .GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE = 0x0, .GSP_PAYLOAD_SIZE = 0x5, .GSP_TRANSMISSION_LINE_NUMBER = 0x10, .GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE = 0x0, .GSP_TRANSMISSION_LINE_NUMBER = 0x10, .GSP_SOF_REFERENCE = 0x7, .METADATA_PACKET_ENABLE = 0x0 , .AUDIO_MUTE = 0x1c, .ASP_ENABLE = 0x0, .ATP_ENABLE = 0x1, . AIP_ENABLE = 0x2, .ACM_ENABLE = 0x3, .CRC_ENABLE = 0x0, .CRC_CONT_MODE_ENABLE = 0x4, .HBLANK_MINIMUM_SYMBOL_WIDTH = 0x0 |
338 | }; |
339 | |
340 | static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { |
341 | DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK).DP_STREAM_LINK_TARGET = 0x00000007L, .DP_STREAM_ENC_CLOCK_EN = 0x00000001L, .DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL = 0x00000007L, .DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL = 0x00000007L, .FIFO_RESET = 0x00000010L, .FIFO_RESET_DONE = 0x00100000L, .FIFO_ENABLE = 0x00000001L, .DP_SYM32_ENC_RESET = 0x00000010L, .DP_SYM32_ENC_RESET_DONE = 0x00000100L, .DP_SYM32_ENC_ENABLE = 0x00000001L, .PIXEL_ENCODING_TYPE = 0x00000001L, .UNCOMPRESSED_PIXEL_ENCODING = 0x00000030L, .UNCOMPRESSED_COMPONENT_DEPTH = 0x00000300L, . PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE = 0x00000001L, .MSA_DOUBLE_BUFFER_ENABLE = 0x00000001L, .MSA_DATA_LANE_0 = 0x000000FFL, .MSA_DATA_LANE_1 = 0x0000FF00L, .MSA_DATA_LANE_2 = 0x00FF0000L, .MSA_DATA_LANE_3 = 0xFF000000L, .PIXEL_TO_SYMBOL_FIFO_RESET = 0x00000010L, .PIXEL_TO_SYMBOL_FIFO_RESET_DONE = 0x00000100L, .PIXEL_TO_SYMBOL_FIFO_ENABLE = 0x00000001L, . VID_STREAM_ENABLE = 0x00000001L, .VID_STREAM_STATUS = 0x00000100L , .VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE = 0x00000001L, . VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER = 0xFFFF0000L, .SDP_STREAM_ENABLE = 0x00000001L, .GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE = 0x00000001L , .GSP_PAYLOAD_SIZE = 0x00000060L, .GSP_TRANSMISSION_LINE_NUMBER = 0xFFFF0000L, .GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE = 0x00000001L , .GSP_TRANSMISSION_LINE_NUMBER = 0xFFFF0000L, .GSP_SOF_REFERENCE = 0x00000080L, .METADATA_PACKET_ENABLE = 0x00000001L, .AUDIO_MUTE = 0x10000000L, .ASP_ENABLE = 0x00000001L, .ATP_ENABLE = 0x00000002L , .AIP_ENABLE = 0x00000004L, .ACM_ENABLE = 0x00000008L, .CRC_ENABLE = 0x00000001L, .CRC_CONT_MODE_ENABLE = 0x00000010L, .HBLANK_MINIMUM_SYMBOL_WIDTH = 0x0000FFFFL |
342 | }; |
343 | |
344 | |
345 | #define hpo_dp_link_encoder_reg_init(id)( dccg_regs[id].DP_LINK_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets [regDP_LINK_ENCid_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX] + regDP_LINK_ENCid_DP_LINK_ENC_CLOCK_CONTROL , dccg_regs[id].DP_DPHY_SYM32_CONTROL = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_CONTROL_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_CONTROL , dccg_regs[id].DP_DPHY_SYM32_STATUS = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_STATUS_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_STATUS , dccg_regs[id].DP_DPHY_SYM32_TP_CONFIG = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CONFIG , dccg_regs[id].DP_DPHY_SYM32_TP_PRBS_SEED0 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED0 , dccg_regs[id].DP_DPHY_SYM32_TP_PRBS_SEED1 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED1 , dccg_regs[id].DP_DPHY_SYM32_TP_PRBS_SEED2 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED2 , dccg_regs[id].DP_DPHY_SYM32_TP_PRBS_SEED3 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED3 , dccg_regs[id].DP_DPHY_SYM32_TP_SQ_PULSE = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_SQ_PULSE , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM0 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM0 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM1 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM1 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM2 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM2 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM3 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM3 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM4 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM4 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM5 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM5 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM6 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM6 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM7 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM7 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM8 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM8 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM9 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM9 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM10 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM10 , dccg_regs[id].DP_DPHY_SYM32_SAT_VC0 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC0_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC0 , dccg_regs[id].DP_DPHY_SYM32_SAT_VC1 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC1_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC1 , dccg_regs[id].DP_DPHY_SYM32_SAT_VC2 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC2_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC2 , dccg_regs[id].DP_DPHY_SYM32_SAT_VC3 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC3_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC3 , dccg_regs[id].DP_DPHY_SYM32_VC_RATE_CNTL0 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL0 , dccg_regs[id].DP_DPHY_SYM32_VC_RATE_CNTL1 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL1 , dccg_regs[id].DP_DPHY_SYM32_VC_RATE_CNTL2 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL2 , dccg_regs[id].DP_DPHY_SYM32_VC_RATE_CNTL3 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL3 , dccg_regs[id].DP_DPHY_SYM32_SAT_UPDATE = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_UPDATE )\ |
346 | DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)( dccg_regs[id].DP_LINK_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets [regDP_LINK_ENCid_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX] + regDP_LINK_ENCid_DP_LINK_ENC_CLOCK_CONTROL , dccg_regs[id].DP_DPHY_SYM32_CONTROL = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_CONTROL_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_CONTROL , dccg_regs[id].DP_DPHY_SYM32_STATUS = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_STATUS_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_STATUS , dccg_regs[id].DP_DPHY_SYM32_TP_CONFIG = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CONFIG , dccg_regs[id].DP_DPHY_SYM32_TP_PRBS_SEED0 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED0 , dccg_regs[id].DP_DPHY_SYM32_TP_PRBS_SEED1 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED1 , dccg_regs[id].DP_DPHY_SYM32_TP_PRBS_SEED2 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED2 , dccg_regs[id].DP_DPHY_SYM32_TP_PRBS_SEED3 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED3 , dccg_regs[id].DP_DPHY_SYM32_TP_SQ_PULSE = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_SQ_PULSE , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM0 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM0 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM1 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM1 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM2 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM2 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM3 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM3 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM4 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM4 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM5 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM5 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM6 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM6 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM7 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM7 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM8 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM8 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM9 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM9 , dccg_regs[id].DP_DPHY_SYM32_TP_CUSTOM10 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM10 , dccg_regs[id].DP_DPHY_SYM32_SAT_VC0 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC0_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC0 , dccg_regs[id].DP_DPHY_SYM32_SAT_VC1 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC1_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC1 , dccg_regs[id].DP_DPHY_SYM32_SAT_VC2 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC2_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC2 , dccg_regs[id].DP_DPHY_SYM32_SAT_VC3 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC3_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC3 , dccg_regs[id].DP_DPHY_SYM32_VC_RATE_CNTL0 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL0 , dccg_regs[id].DP_DPHY_SYM32_VC_RATE_CNTL1 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL1 , dccg_regs[id].DP_DPHY_SYM32_VC_RATE_CNTL2 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL2 , dccg_regs[id].DP_DPHY_SYM32_VC_RATE_CNTL3 = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL3 , dccg_regs[id].DP_DPHY_SYM32_SAT_UPDATE = ctx->dcn_reg_offsets [regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX] + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_UPDATE ) |
347 | /*DCN3_1_RDPCSTX_REG_LIST(0),*/ |
348 | /*DCN3_1_RDPCSTX_REG_LIST(1),*/ |
349 | /*DCN3_1_RDPCSTX_REG_LIST(2),*/ |
350 | /*DCN3_1_RDPCSTX_REG_LIST(3),*/ |
351 | |
352 | static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2]; |
353 | |
354 | static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { |
355 | DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT).DP_LINK_ENC_CLOCK_EN = 0x0, .DPHY_RESET = 0x1, .DPHY_ENABLE = 0x0, .PRECODER_ENABLE = 0x2, .MODE = 0x4, .NUM_LANES = 0x8, . STATUS = 0x0, .SAT_UPDATE_PENDING = 0x10, .RATE_UPDATE_PENDING = 0xc, .TP_CUSTOM = 0x0, .TP_SELECT0 = 0x0, .TP_SELECT1 = 0x8 , .TP_SELECT2 = 0x10, .TP_SELECT3 = 0x18, .TP_PRBS_SEL0 = 0x4 , .TP_PRBS_SEL1 = 0xc, .TP_PRBS_SEL2 = 0x14, .TP_PRBS_SEL3 = 0x1c , .TP_SQ_PULSE_WIDTH = 0x0, .SAT_STREAM_SOURCE = 0x0, .SAT_SLOT_COUNT = 0x8, .STREAM_VC_RATE_X = 0x19, .STREAM_VC_RATE_Y = 0x0, .SAT_UPDATE = 0x0 |
356 | }; |
357 | |
358 | static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { |
359 | DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK).DP_LINK_ENC_CLOCK_EN = 0x00000001L, .DPHY_RESET = 0x00000002L , .DPHY_ENABLE = 0x00000001L, .PRECODER_ENABLE = 0x00000004L, .MODE = 0x00000030L, .NUM_LANES = 0x00000300L, .STATUS = 0x00000001L , .SAT_UPDATE_PENDING = 0x00030000L, .RATE_UPDATE_PENDING = 0x00001000L , .TP_CUSTOM = 0x00FFFFFFL, .TP_SELECT0 = 0x00000007L, .TP_SELECT1 = 0x00000700L, .TP_SELECT2 = 0x00070000L, .TP_SELECT3 = 0x07000000L , .TP_PRBS_SEL0 = 0x00000070L, .TP_PRBS_SEL1 = 0x00007000L, . TP_PRBS_SEL2 = 0x00700000L, .TP_PRBS_SEL3 = 0x70000000L, .TP_SQ_PULSE_WIDTH = 0x000000FFL, .SAT_STREAM_SOURCE = 0x00000007L, .SAT_SLOT_COUNT = 0x00007F00L, .STREAM_VC_RATE_X = 0xFE000000L, .STREAM_VC_RATE_Y = 0x01FFFFFFL, .SAT_UPDATE = 0x00000003L |
360 | }; |
361 | |
362 | #define dpp_regs_init(id)( dccg_regs[id].CM_DEALPHA = ctx->dcn_reg_offsets[regCMid_CM_DEALPHA_BASE_IDX ] + regCMid_CM_DEALPHA, dccg_regs[id].CM_MEM_PWR_STATUS = ctx ->dcn_reg_offsets[regCMid_CM_MEM_PWR_STATUS_BASE_IDX] + regCMid_CM_MEM_PWR_STATUS , dccg_regs[id].CM_BIAS_CR_R = ctx->dcn_reg_offsets[regCMid_CM_BIAS_CR_R_BASE_IDX ] + regCMid_CM_BIAS_CR_R, dccg_regs[id].CM_BIAS_Y_G_CB_B = ctx ->dcn_reg_offsets[regCMid_CM_BIAS_Y_G_CB_B_BASE_IDX] + regCMid_CM_BIAS_Y_G_CB_B , dccg_regs[id].PRE_DEGAM = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_DEGAM_BASE_IDX ] + regCNVC_CFGid_PRE_DEGAM, dccg_regs[id].CM_GAMCOR_CONTROL = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_CONTROL_BASE_IDX] + regCMid_CM_GAMCOR_CONTROL, dccg_regs[id].CM_GAMCOR_LUT_CONTROL = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_LUT_CONTROL_BASE_IDX ] + regCMid_CM_GAMCOR_LUT_CONTROL, dccg_regs[id].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX ] + regCMid_CM_GAMCOR_LUT_INDEX, dccg_regs[id].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX ] + regCMid_CM_GAMCOR_LUT_INDEX, dccg_regs[id].CM_GAMCOR_LUT_DATA = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_LUT_DATA_BASE_IDX ] + regCMid_CM_GAMCOR_LUT_DATA, dccg_regs[id].CM_GAMCOR_RAMB_START_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_CNTL_B, dccg_regs[id].CM_GAMCOR_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_CNTL_G, dccg_regs[id].CM_GAMCOR_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_CNTL_R, dccg_regs[id].CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, dccg_regs[id]. CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, dccg_regs[id]. CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, dccg_regs[id]. CM_GAMCOR_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL1_B, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL2_B, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL1_G, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL2_G, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL1_R, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL2_R, dccg_regs[id].CM_GAMCOR_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_REGION_0_1, dccg_regs[id].CM_GAMCOR_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_REGION_32_33, dccg_regs[id].CM_GAMCOR_RAMB_OFFSET_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_OFFSET_B, dccg_regs[id].CM_GAMCOR_RAMB_OFFSET_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_OFFSET_G, dccg_regs[id].CM_GAMCOR_RAMB_OFFSET_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_OFFSET_R, dccg_regs[id].CM_GAMCOR_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B, dccg_regs[id].CM_GAMCOR_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G, dccg_regs[id].CM_GAMCOR_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R, dccg_regs[id].CM_GAMCOR_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_CNTL_B, dccg_regs[id].CM_GAMCOR_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_CNTL_G, dccg_regs[id].CM_GAMCOR_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_CNTL_R, dccg_regs[id].CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, dccg_regs[id]. CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, dccg_regs[id]. CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, dccg_regs[id]. CM_GAMCOR_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL1_B, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL2_B, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL1_G, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL2_G, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL1_R, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL2_R, dccg_regs[id].CM_GAMCOR_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_REGION_0_1, dccg_regs[id].CM_GAMCOR_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_REGION_32_33, dccg_regs[id].CM_GAMCOR_RAMA_OFFSET_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_OFFSET_B, dccg_regs[id].CM_GAMCOR_RAMA_OFFSET_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_OFFSET_G, dccg_regs[id].CM_GAMCOR_RAMA_OFFSET_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_OFFSET_R, dccg_regs[id].CM_GAMCOR_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B, dccg_regs[id].CM_GAMCOR_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G, dccg_regs[id].CM_GAMCOR_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R, dccg_regs[id].CM_GAMUT_REMAP_CONTROL = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_CONTROL, dccg_regs[id].CM_GAMUT_REMAP_C11_C12 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C11_C12, dccg_regs[id].CM_GAMUT_REMAP_C13_C14 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C13_C14, dccg_regs[id].CM_GAMUT_REMAP_C21_C22 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C21_C22, dccg_regs[id].CM_GAMUT_REMAP_C23_C24 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C23_C24, dccg_regs[id].CM_GAMUT_REMAP_C31_C32 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C31_C32, dccg_regs[id].CM_GAMUT_REMAP_C33_C34 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C33_C34, dccg_regs[id].CM_GAMUT_REMAP_B_C11_C12 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C11_C12, dccg_regs[id].CM_GAMUT_REMAP_B_C13_C14 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C13_C14, dccg_regs[id].CM_GAMUT_REMAP_B_C21_C22 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C21_C22, dccg_regs[id].CM_GAMUT_REMAP_B_C23_C24 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C23_C24, dccg_regs[id].CM_GAMUT_REMAP_B_C31_C32 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C31_C32, dccg_regs[id].CM_GAMUT_REMAP_B_C33_C34 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C33_C34, dccg_regs[id].DSCL_EXT_OVERSCAN_LEFT_RIGHT = ctx->dcn_reg_offsets[regDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX ] + regDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, dccg_regs[id].DSCL_EXT_OVERSCAN_TOP_BOTTOM = ctx->dcn_reg_offsets[regDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX ] + regDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, dccg_regs[id].OTG_H_BLANK = ctx->dcn_reg_offsets[regDSCLid_OTG_H_BLANK_BASE_IDX] + regDSCLid_OTG_H_BLANK , dccg_regs[id].OTG_V_BLANK = ctx->dcn_reg_offsets[regDSCLid_OTG_V_BLANK_BASE_IDX ] + regDSCLid_OTG_V_BLANK, dccg_regs[id].SCL_MODE = ctx->dcn_reg_offsets [regDSCLid_SCL_MODE_BASE_IDX] + regDSCLid_SCL_MODE, dccg_regs [id].LB_DATA_FORMAT = ctx->dcn_reg_offsets[regDSCLid_LB_DATA_FORMAT_BASE_IDX ] + regDSCLid_LB_DATA_FORMAT, dccg_regs[id].LB_MEMORY_CTRL = ctx ->dcn_reg_offsets[regDSCLid_LB_MEMORY_CTRL_BASE_IDX] + regDSCLid_LB_MEMORY_CTRL , dccg_regs[id].DSCL_AUTOCAL = ctx->dcn_reg_offsets[regDSCLid_DSCL_AUTOCAL_BASE_IDX ] + regDSCLid_DSCL_AUTOCAL, dccg_regs[id].SCL_TAP_CONTROL = ctx ->dcn_reg_offsets[regDSCLid_SCL_TAP_CONTROL_BASE_IDX] + regDSCLid_SCL_TAP_CONTROL , dccg_regs[id].SCL_COEF_RAM_TAP_SELECT = ctx->dcn_reg_offsets [regDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX] + regDSCLid_SCL_COEF_RAM_TAP_SELECT , dccg_regs[id].SCL_COEF_RAM_TAP_DATA = ctx->dcn_reg_offsets [regDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX] + regDSCLid_SCL_COEF_RAM_TAP_DATA , dccg_regs[id].DSCL_2TAP_CONTROL = ctx->dcn_reg_offsets[regDSCLid_DSCL_2TAP_CONTROL_BASE_IDX ] + regDSCLid_DSCL_2TAP_CONTROL, dccg_regs[id].MPC_SIZE = ctx ->dcn_reg_offsets[regDSCLid_MPC_SIZE_BASE_IDX] + regDSCLid_MPC_SIZE , dccg_regs[id].SCL_HORZ_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets [regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX] + regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO , dccg_regs[id].SCL_VERT_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets [regDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX] + regDSCLid_SCL_VERT_FILTER_SCALE_RATIO , dccg_regs[id].SCL_HORZ_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets [regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX] + regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C , dccg_regs[id].SCL_VERT_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets [regDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX] + regDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C , dccg_regs[id].SCL_HORZ_FILTER_INIT = ctx->dcn_reg_offsets [regDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX] + regDSCLid_SCL_HORZ_FILTER_INIT , dccg_regs[id].SCL_HORZ_FILTER_INIT_C = ctx->dcn_reg_offsets [regDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX] + regDSCLid_SCL_HORZ_FILTER_INIT_C , dccg_regs[id].SCL_VERT_FILTER_INIT = ctx->dcn_reg_offsets [regDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX] + regDSCLid_SCL_VERT_FILTER_INIT , dccg_regs[id].SCL_VERT_FILTER_INIT_C = ctx->dcn_reg_offsets [regDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX] + regDSCLid_SCL_VERT_FILTER_INIT_C , dccg_regs[id].RECOUT_START = ctx->dcn_reg_offsets[regDSCLid_RECOUT_START_BASE_IDX ] + regDSCLid_RECOUT_START, dccg_regs[id].RECOUT_SIZE = ctx-> dcn_reg_offsets[regDSCLid_RECOUT_SIZE_BASE_IDX] + regDSCLid_RECOUT_SIZE , dccg_regs[id].PRE_DEALPHA = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_DEALPHA_BASE_IDX ] + regCNVC_CFGid_PRE_DEALPHA, dccg_regs[id].PRE_REALPHA = ctx ->dcn_reg_offsets[regCNVC_CFGid_PRE_REALPHA_BASE_IDX] + regCNVC_CFGid_PRE_REALPHA , dccg_regs[id].PRE_CSC_MODE = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_MODE_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_MODE, dccg_regs[id].PRE_CSC_C11_C12 = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_C11_C12_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_C11_C12, dccg_regs[id].PRE_CSC_C33_C34 = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_C33_C34_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_C33_C34, dccg_regs[id].PRE_CSC_B_C11_C12 = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_B_C11_C12_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_B_C11_C12, dccg_regs[id].PRE_CSC_B_C33_C34 = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_B_C33_C34_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_B_C33_C34, dccg_regs[id].CM_POST_CSC_CONTROL = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_CONTROL_BASE_IDX ] + regCMid_CM_POST_CSC_CONTROL, dccg_regs[id].CM_POST_CSC_C11_C12 = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_C11_C12_BASE_IDX ] + regCMid_CM_POST_CSC_C11_C12, dccg_regs[id].CM_POST_CSC_C33_C34 = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_C33_C34_BASE_IDX ] + regCMid_CM_POST_CSC_C33_C34, dccg_regs[id].CM_POST_CSC_B_C11_C12 = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_B_C11_C12_BASE_IDX ] + regCMid_CM_POST_CSC_B_C11_C12, dccg_regs[id].CM_POST_CSC_B_C33_C34 = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_B_C33_C34_BASE_IDX ] + regCMid_CM_POST_CSC_B_C33_C34, dccg_regs[id].CM_MEM_PWR_CTRL = ctx->dcn_reg_offsets[regCMid_CM_MEM_PWR_CTRL_BASE_IDX] + regCMid_CM_MEM_PWR_CTRL, dccg_regs[id].CM_CONTROL = ctx-> dcn_reg_offsets[regCMid_CM_CONTROL_BASE_IDX] + regCMid_CM_CONTROL , dccg_regs[id].FORMAT_CONTROL = ctx->dcn_reg_offsets[regCNVC_CFGid_FORMAT_CONTROL_BASE_IDX ] + regCNVC_CFGid_FORMAT_CONTROL, dccg_regs[id].CNVC_SURFACE_PIXEL_FORMAT = ctx->dcn_reg_offsets[regCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX ] + regCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, dccg_regs[id].CURSOR0_CONTROL = ctx->dcn_reg_offsets[regCNVC_CURid_CURSOR0_CONTROL_BASE_IDX ] + regCNVC_CURid_CURSOR0_CONTROL, dccg_regs[id].CURSOR0_COLOR0 = ctx->dcn_reg_offsets[regCNVC_CURid_CURSOR0_COLOR0_BASE_IDX ] + regCNVC_CURid_CURSOR0_COLOR0, dccg_regs[id].CURSOR0_COLOR1 = ctx->dcn_reg_offsets[regCNVC_CURid_CURSOR0_COLOR1_BASE_IDX ] + regCNVC_CURid_CURSOR0_COLOR1, dccg_regs[id].CURSOR0_FP_SCALE_BIAS = ctx->dcn_reg_offsets[regCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX ] + regCNVC_CURid_CURSOR0_FP_SCALE_BIAS, dccg_regs[id].DPP_CONTROL = ctx->dcn_reg_offsets[regDPP_TOPid_DPP_CONTROL_BASE_IDX] + regDPP_TOPid_DPP_CONTROL, dccg_regs[id].CM_HDR_MULT_COEF = ctx->dcn_reg_offsets[regCMid_CM_HDR_MULT_COEF_BASE_IDX] + regCMid_CM_HDR_MULT_COEF, dccg_regs[id].CURSOR_CONTROL = ctx ->dcn_reg_offsets[regCURSOR0_id_CURSOR_CONTROL_BASE_IDX] + regCURSOR0_id_CURSOR_CONTROL, dccg_regs[id].ALPHA_2BIT_LUT = ctx->dcn_reg_offsets[regCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX ] + regCNVC_CFGid_ALPHA_2BIT_LUT, dccg_regs[id].FCNV_FP_BIAS_R = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_BIAS_R, dccg_regs[id].FCNV_FP_BIAS_G = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_BIAS_G, dccg_regs[id].FCNV_FP_BIAS_B = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_BIAS_B, dccg_regs[id].FCNV_FP_SCALE_R = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_SCALE_R, dccg_regs[id].FCNV_FP_SCALE_G = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_SCALE_G, dccg_regs[id].FCNV_FP_SCALE_B = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_SCALE_B, dccg_regs[id].COLOR_KEYER_CONTROL = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_CONTROL, dccg_regs[id].COLOR_KEYER_ALPHA = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_ALPHA, dccg_regs[id].COLOR_KEYER_RED = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_RED, dccg_regs[id].COLOR_KEYER_GREEN = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_GREEN, dccg_regs[id].COLOR_KEYER_BLUE = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_BLUE, dccg_regs[id].CURSOR_CONTROL = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_CONTROL_BASE_IDX ] + regCURSOR0_id_CURSOR_CONTROL, dccg_regs[id].OBUF_MEM_PWR_CTRL = ctx->dcn_reg_offsets[regDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX ] + regDSCLid_OBUF_MEM_PWR_CTRL, dccg_regs[id].DSCL_MEM_PWR_STATUS = ctx->dcn_reg_offsets[regDSCLid_DSCL_MEM_PWR_STATUS_BASE_IDX ] + regDSCLid_DSCL_MEM_PWR_STATUS, dccg_regs[id].DSCL_MEM_PWR_CTRL = ctx->dcn_reg_offsets[regDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX ] + regDSCLid_DSCL_MEM_PWR_CTRL )\ |
363 | DPP_REG_LIST_DCN30_COMMON_RI(id)( dccg_regs[id].CM_DEALPHA = ctx->dcn_reg_offsets[regCMid_CM_DEALPHA_BASE_IDX ] + regCMid_CM_DEALPHA, dccg_regs[id].CM_MEM_PWR_STATUS = ctx ->dcn_reg_offsets[regCMid_CM_MEM_PWR_STATUS_BASE_IDX] + regCMid_CM_MEM_PWR_STATUS , dccg_regs[id].CM_BIAS_CR_R = ctx->dcn_reg_offsets[regCMid_CM_BIAS_CR_R_BASE_IDX ] + regCMid_CM_BIAS_CR_R, dccg_regs[id].CM_BIAS_Y_G_CB_B = ctx ->dcn_reg_offsets[regCMid_CM_BIAS_Y_G_CB_B_BASE_IDX] + regCMid_CM_BIAS_Y_G_CB_B , dccg_regs[id].PRE_DEGAM = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_DEGAM_BASE_IDX ] + regCNVC_CFGid_PRE_DEGAM, dccg_regs[id].CM_GAMCOR_CONTROL = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_CONTROL_BASE_IDX] + regCMid_CM_GAMCOR_CONTROL, dccg_regs[id].CM_GAMCOR_LUT_CONTROL = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_LUT_CONTROL_BASE_IDX ] + regCMid_CM_GAMCOR_LUT_CONTROL, dccg_regs[id].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX ] + regCMid_CM_GAMCOR_LUT_INDEX, dccg_regs[id].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX ] + regCMid_CM_GAMCOR_LUT_INDEX, dccg_regs[id].CM_GAMCOR_LUT_DATA = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_LUT_DATA_BASE_IDX ] + regCMid_CM_GAMCOR_LUT_DATA, dccg_regs[id].CM_GAMCOR_RAMB_START_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_CNTL_B, dccg_regs[id].CM_GAMCOR_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_CNTL_G, dccg_regs[id].CM_GAMCOR_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_CNTL_R, dccg_regs[id].CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, dccg_regs[id]. CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, dccg_regs[id]. CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, dccg_regs[id]. CM_GAMCOR_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL1_B, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL2_B, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL1_G, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL2_G, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL1_R, dccg_regs[id].CM_GAMCOR_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_END_CNTL2_R, dccg_regs[id].CM_GAMCOR_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_REGION_0_1, dccg_regs[id].CM_GAMCOR_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_REGION_32_33, dccg_regs[id].CM_GAMCOR_RAMB_OFFSET_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_OFFSET_B, dccg_regs[id].CM_GAMCOR_RAMB_OFFSET_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_OFFSET_G, dccg_regs[id].CM_GAMCOR_RAMB_OFFSET_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_OFFSET_R, dccg_regs[id].CM_GAMCOR_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B, dccg_regs[id].CM_GAMCOR_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G, dccg_regs[id].CM_GAMCOR_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R, dccg_regs[id].CM_GAMCOR_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_CNTL_B, dccg_regs[id].CM_GAMCOR_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_CNTL_G, dccg_regs[id].CM_GAMCOR_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_CNTL_R, dccg_regs[id].CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, dccg_regs[id]. CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, dccg_regs[id]. CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, dccg_regs[id]. CM_GAMCOR_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL1_B, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL2_B, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL1_G, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL2_G, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL1_R, dccg_regs[id].CM_GAMCOR_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_END_CNTL2_R, dccg_regs[id].CM_GAMCOR_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_REGION_0_1, dccg_regs[id].CM_GAMCOR_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_REGION_32_33, dccg_regs[id].CM_GAMCOR_RAMA_OFFSET_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_OFFSET_B, dccg_regs[id].CM_GAMCOR_RAMA_OFFSET_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_OFFSET_G, dccg_regs[id].CM_GAMCOR_RAMA_OFFSET_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_OFFSET_R, dccg_regs[id].CM_GAMCOR_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B, dccg_regs[id].CM_GAMCOR_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G, dccg_regs[id].CM_GAMCOR_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX ] + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R, dccg_regs[id].CM_GAMUT_REMAP_CONTROL = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_CONTROL, dccg_regs[id].CM_GAMUT_REMAP_C11_C12 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C11_C12, dccg_regs[id].CM_GAMUT_REMAP_C13_C14 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C13_C14, dccg_regs[id].CM_GAMUT_REMAP_C21_C22 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C21_C22, dccg_regs[id].CM_GAMUT_REMAP_C23_C24 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C23_C24, dccg_regs[id].CM_GAMUT_REMAP_C31_C32 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C31_C32, dccg_regs[id].CM_GAMUT_REMAP_C33_C34 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_C33_C34, dccg_regs[id].CM_GAMUT_REMAP_B_C11_C12 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C11_C12, dccg_regs[id].CM_GAMUT_REMAP_B_C13_C14 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C13_C14, dccg_regs[id].CM_GAMUT_REMAP_B_C21_C22 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C21_C22, dccg_regs[id].CM_GAMUT_REMAP_B_C23_C24 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C23_C24, dccg_regs[id].CM_GAMUT_REMAP_B_C31_C32 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C31_C32, dccg_regs[id].CM_GAMUT_REMAP_B_C33_C34 = ctx->dcn_reg_offsets[regCMid_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX ] + regCMid_CM_GAMUT_REMAP_B_C33_C34, dccg_regs[id].DSCL_EXT_OVERSCAN_LEFT_RIGHT = ctx->dcn_reg_offsets[regDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX ] + regDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, dccg_regs[id].DSCL_EXT_OVERSCAN_TOP_BOTTOM = ctx->dcn_reg_offsets[regDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX ] + regDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, dccg_regs[id].OTG_H_BLANK = ctx->dcn_reg_offsets[regDSCLid_OTG_H_BLANK_BASE_IDX] + regDSCLid_OTG_H_BLANK , dccg_regs[id].OTG_V_BLANK = ctx->dcn_reg_offsets[regDSCLid_OTG_V_BLANK_BASE_IDX ] + regDSCLid_OTG_V_BLANK, dccg_regs[id].SCL_MODE = ctx->dcn_reg_offsets [regDSCLid_SCL_MODE_BASE_IDX] + regDSCLid_SCL_MODE, dccg_regs [id].LB_DATA_FORMAT = ctx->dcn_reg_offsets[regDSCLid_LB_DATA_FORMAT_BASE_IDX ] + regDSCLid_LB_DATA_FORMAT, dccg_regs[id].LB_MEMORY_CTRL = ctx ->dcn_reg_offsets[regDSCLid_LB_MEMORY_CTRL_BASE_IDX] + regDSCLid_LB_MEMORY_CTRL , dccg_regs[id].DSCL_AUTOCAL = ctx->dcn_reg_offsets[regDSCLid_DSCL_AUTOCAL_BASE_IDX ] + regDSCLid_DSCL_AUTOCAL, dccg_regs[id].SCL_TAP_CONTROL = ctx ->dcn_reg_offsets[regDSCLid_SCL_TAP_CONTROL_BASE_IDX] + regDSCLid_SCL_TAP_CONTROL , dccg_regs[id].SCL_COEF_RAM_TAP_SELECT = ctx->dcn_reg_offsets [regDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX] + regDSCLid_SCL_COEF_RAM_TAP_SELECT , dccg_regs[id].SCL_COEF_RAM_TAP_DATA = ctx->dcn_reg_offsets [regDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX] + regDSCLid_SCL_COEF_RAM_TAP_DATA , dccg_regs[id].DSCL_2TAP_CONTROL = ctx->dcn_reg_offsets[regDSCLid_DSCL_2TAP_CONTROL_BASE_IDX ] + regDSCLid_DSCL_2TAP_CONTROL, dccg_regs[id].MPC_SIZE = ctx ->dcn_reg_offsets[regDSCLid_MPC_SIZE_BASE_IDX] + regDSCLid_MPC_SIZE , dccg_regs[id].SCL_HORZ_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets [regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX] + regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO , dccg_regs[id].SCL_VERT_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets [regDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX] + regDSCLid_SCL_VERT_FILTER_SCALE_RATIO , dccg_regs[id].SCL_HORZ_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets [regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX] + regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C , dccg_regs[id].SCL_VERT_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets [regDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX] + regDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C , dccg_regs[id].SCL_HORZ_FILTER_INIT = ctx->dcn_reg_offsets [regDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX] + regDSCLid_SCL_HORZ_FILTER_INIT , dccg_regs[id].SCL_HORZ_FILTER_INIT_C = ctx->dcn_reg_offsets [regDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX] + regDSCLid_SCL_HORZ_FILTER_INIT_C , dccg_regs[id].SCL_VERT_FILTER_INIT = ctx->dcn_reg_offsets [regDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX] + regDSCLid_SCL_VERT_FILTER_INIT , dccg_regs[id].SCL_VERT_FILTER_INIT_C = ctx->dcn_reg_offsets [regDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX] + regDSCLid_SCL_VERT_FILTER_INIT_C , dccg_regs[id].RECOUT_START = ctx->dcn_reg_offsets[regDSCLid_RECOUT_START_BASE_IDX ] + regDSCLid_RECOUT_START, dccg_regs[id].RECOUT_SIZE = ctx-> dcn_reg_offsets[regDSCLid_RECOUT_SIZE_BASE_IDX] + regDSCLid_RECOUT_SIZE , dccg_regs[id].PRE_DEALPHA = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_DEALPHA_BASE_IDX ] + regCNVC_CFGid_PRE_DEALPHA, dccg_regs[id].PRE_REALPHA = ctx ->dcn_reg_offsets[regCNVC_CFGid_PRE_REALPHA_BASE_IDX] + regCNVC_CFGid_PRE_REALPHA , dccg_regs[id].PRE_CSC_MODE = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_MODE_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_MODE, dccg_regs[id].PRE_CSC_C11_C12 = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_C11_C12_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_C11_C12, dccg_regs[id].PRE_CSC_C33_C34 = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_C33_C34_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_C33_C34, dccg_regs[id].PRE_CSC_B_C11_C12 = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_B_C11_C12_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_B_C11_C12, dccg_regs[id].PRE_CSC_B_C33_C34 = ctx->dcn_reg_offsets[regCNVC_CFGid_PRE_CSC_B_C33_C34_BASE_IDX ] + regCNVC_CFGid_PRE_CSC_B_C33_C34, dccg_regs[id].CM_POST_CSC_CONTROL = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_CONTROL_BASE_IDX ] + regCMid_CM_POST_CSC_CONTROL, dccg_regs[id].CM_POST_CSC_C11_C12 = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_C11_C12_BASE_IDX ] + regCMid_CM_POST_CSC_C11_C12, dccg_regs[id].CM_POST_CSC_C33_C34 = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_C33_C34_BASE_IDX ] + regCMid_CM_POST_CSC_C33_C34, dccg_regs[id].CM_POST_CSC_B_C11_C12 = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_B_C11_C12_BASE_IDX ] + regCMid_CM_POST_CSC_B_C11_C12, dccg_regs[id].CM_POST_CSC_B_C33_C34 = ctx->dcn_reg_offsets[regCMid_CM_POST_CSC_B_C33_C34_BASE_IDX ] + regCMid_CM_POST_CSC_B_C33_C34, dccg_regs[id].CM_MEM_PWR_CTRL = ctx->dcn_reg_offsets[regCMid_CM_MEM_PWR_CTRL_BASE_IDX] + regCMid_CM_MEM_PWR_CTRL, dccg_regs[id].CM_CONTROL = ctx-> dcn_reg_offsets[regCMid_CM_CONTROL_BASE_IDX] + regCMid_CM_CONTROL , dccg_regs[id].FORMAT_CONTROL = ctx->dcn_reg_offsets[regCNVC_CFGid_FORMAT_CONTROL_BASE_IDX ] + regCNVC_CFGid_FORMAT_CONTROL, dccg_regs[id].CNVC_SURFACE_PIXEL_FORMAT = ctx->dcn_reg_offsets[regCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX ] + regCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, dccg_regs[id].CURSOR0_CONTROL = ctx->dcn_reg_offsets[regCNVC_CURid_CURSOR0_CONTROL_BASE_IDX ] + regCNVC_CURid_CURSOR0_CONTROL, dccg_regs[id].CURSOR0_COLOR0 = ctx->dcn_reg_offsets[regCNVC_CURid_CURSOR0_COLOR0_BASE_IDX ] + regCNVC_CURid_CURSOR0_COLOR0, dccg_regs[id].CURSOR0_COLOR1 = ctx->dcn_reg_offsets[regCNVC_CURid_CURSOR0_COLOR1_BASE_IDX ] + regCNVC_CURid_CURSOR0_COLOR1, dccg_regs[id].CURSOR0_FP_SCALE_BIAS = ctx->dcn_reg_offsets[regCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX ] + regCNVC_CURid_CURSOR0_FP_SCALE_BIAS, dccg_regs[id].DPP_CONTROL = ctx->dcn_reg_offsets[regDPP_TOPid_DPP_CONTROL_BASE_IDX] + regDPP_TOPid_DPP_CONTROL, dccg_regs[id].CM_HDR_MULT_COEF = ctx->dcn_reg_offsets[regCMid_CM_HDR_MULT_COEF_BASE_IDX] + regCMid_CM_HDR_MULT_COEF, dccg_regs[id].CURSOR_CONTROL = ctx ->dcn_reg_offsets[regCURSOR0_id_CURSOR_CONTROL_BASE_IDX] + regCURSOR0_id_CURSOR_CONTROL, dccg_regs[id].ALPHA_2BIT_LUT = ctx->dcn_reg_offsets[regCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX ] + regCNVC_CFGid_ALPHA_2BIT_LUT, dccg_regs[id].FCNV_FP_BIAS_R = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_BIAS_R, dccg_regs[id].FCNV_FP_BIAS_G = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_BIAS_G, dccg_regs[id].FCNV_FP_BIAS_B = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_BIAS_B, dccg_regs[id].FCNV_FP_SCALE_R = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_SCALE_R, dccg_regs[id].FCNV_FP_SCALE_G = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_SCALE_G, dccg_regs[id].FCNV_FP_SCALE_B = ctx->dcn_reg_offsets[regCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX ] + regCNVC_CFGid_FCNV_FP_SCALE_B, dccg_regs[id].COLOR_KEYER_CONTROL = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_CONTROL, dccg_regs[id].COLOR_KEYER_ALPHA = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_ALPHA, dccg_regs[id].COLOR_KEYER_RED = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_RED, dccg_regs[id].COLOR_KEYER_GREEN = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_GREEN, dccg_regs[id].COLOR_KEYER_BLUE = ctx->dcn_reg_offsets[regCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX ] + regCNVC_CFGid_COLOR_KEYER_BLUE, dccg_regs[id].CURSOR_CONTROL = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_CONTROL_BASE_IDX ] + regCURSOR0_id_CURSOR_CONTROL, dccg_regs[id].OBUF_MEM_PWR_CTRL = ctx->dcn_reg_offsets[regDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX ] + regDSCLid_OBUF_MEM_PWR_CTRL, dccg_regs[id].DSCL_MEM_PWR_STATUS = ctx->dcn_reg_offsets[regDSCLid_DSCL_MEM_PWR_STATUS_BASE_IDX ] + regDSCLid_DSCL_MEM_PWR_STATUS, dccg_regs[id].DSCL_MEM_PWR_CTRL = ctx->dcn_reg_offsets[regDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX ] + regDSCLid_DSCL_MEM_PWR_CTRL ) |
364 | |
365 | static struct dcn3_dpp_registers dpp_regs[4]; |
366 | |
367 | static const struct dcn3_dpp_shift tf_shift = { |
368 | DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT).GAMCOR_MEM_PWR_STATE = 0x0, .CM_DEALPHA_EN = 0x0, .CM_DEALPHA_ABLND = 0x1, .CM_BIAS_CR_R = 0x0, .CM_BIAS_Y_G = 0x0, .CM_BIAS_CB_B = 0x10, .GAMCOR_MEM_PWR_DIS = 0x2, .GAMCOR_MEM_PWR_FORCE = 0x0 , .PRE_DEGAM_MODE = 0x0, .PRE_DEGAM_SELECT = 0x4, .CM_GAMCOR_MODE = 0x0, .CM_GAMCOR_SELECT = 0x2, .CM_GAMCOR_PWL_DISABLE = 0x3 , .CM_GAMCOR_MODE_CURRENT = 0x4, .CM_GAMCOR_SELECT_CURRENT = 0x6 , .CM_GAMCOR_LUT_INDEX = 0x0, .CM_GAMCOR_LUT_DATA = 0x0, .CM_GAMCOR_LUT_WRITE_COLOR_MASK = 0x0, .CM_GAMCOR_LUT_READ_COLOR_SEL = 0x3, .CM_GAMCOR_LUT_READ_DBG = 0x5, .CM_GAMCOR_LUT_HOST_SEL = 0x6, .CM_GAMCOR_LUT_CONFIG_MODE = 0x7, .CM_GAMCOR_RAMA_EXP_REGION_START_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .CM_GAMCOR_RAMA_OFFSET_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_GAMUT_REMAP_MODE = 0x0, .CM_GAMUT_REMAP_MODE_CURRENT = 0x2, .CM_GAMUT_REMAP_C11 = 0x0, .CM_GAMUT_REMAP_C12 = 0x10 , .CM_GAMUT_REMAP_C13 = 0x0, .CM_GAMUT_REMAP_C14 = 0x10, .CM_GAMUT_REMAP_C21 = 0x0, .CM_GAMUT_REMAP_C22 = 0x10, .CM_GAMUT_REMAP_C23 = 0x0 , .CM_GAMUT_REMAP_C24 = 0x10, .CM_GAMUT_REMAP_C31 = 0x0, .CM_GAMUT_REMAP_C32 = 0x10, .CM_GAMUT_REMAP_C33 = 0x0, .CM_GAMUT_REMAP_C34 = 0x10 , .EXT_OVERSCAN_LEFT = 0x10, .EXT_OVERSCAN_RIGHT = 0x0, .EXT_OVERSCAN_BOTTOM = 0x0, .EXT_OVERSCAN_TOP = 0x10, .OTG_H_BLANK_START = 0x0, . OTG_H_BLANK_END = 0x10, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END = 0x10, .INTERLEAVE_EN = 0x0, .LB_DATA_FORMAT__ALPHA_EN = 0x4 , .MEMORY_CONFIG = 0x0, .LB_MAX_PARTITIONS = 0x8, .AUTOCAL_MODE = 0x0, .AUTOCAL_NUM_PIPE = 0x8, .AUTOCAL_PIPE_ID = 0xc, .SCL_V_NUM_TAPS = 0x0, .SCL_H_NUM_TAPS = 0x4, .SCL_V_NUM_TAPS_C = 0x8, .SCL_H_NUM_TAPS_C = 0xc, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x0, .SCL_COEF_RAM_PHASE = 0x8, .SCL_COEF_RAM_FILTER_TYPE = 0x10, .SCL_COEF_RAM_EVEN_TAP_COEF = 0x0, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0xf, .SCL_COEF_RAM_ODD_TAP_COEF = 0x10, .SCL_COEF_RAM_ODD_TAP_COEF_EN = 0x1f, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x0, .SCL_H_2TAP_SHARP_EN = 0x4, .SCL_H_2TAP_SHARP_FACTOR = 0x8, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x10, .SCL_V_2TAP_SHARP_EN = 0x14, .SCL_V_2TAP_SHARP_FACTOR = 0x18, .SCL_COEF_RAM_SELECT = 0x8, .DSCL_MODE = 0x0, .RECOUT_START_X = 0x0, .RECOUT_START_Y = 0x10, .RECOUT_WIDTH = 0x0, .RECOUT_HEIGHT = 0x10, .MPC_WIDTH = 0x0, .MPC_HEIGHT = 0x10, .SCL_H_SCALE_RATIO = 0x0, .SCL_V_SCALE_RATIO = 0x0, .SCL_H_SCALE_RATIO_C = 0x0, .SCL_V_SCALE_RATIO_C = 0x0 , .SCL_H_INIT_FRAC = 0x0, .SCL_H_INIT_INT = 0x18, .SCL_H_INIT_FRAC_C = 0x0, .SCL_H_INIT_INT_C = 0x18, .SCL_V_INIT_FRAC = 0x0, .SCL_V_INIT_INT = 0x18, .SCL_V_INIT_FRAC_C = 0x0, .SCL_V_INIT_INT_C = 0x18, . SCL_CHROMA_COEF_MODE = 0x10, .SCL_COEF_RAM_SELECT_CURRENT = 0xc , .PRE_DEALPHA_EN = 0x0, .PRE_DEALPHA_ABLND_EN = 0x4, .PRE_REALPHA_EN = 0x0, .PRE_REALPHA_ABLND_EN = 0x4, .PRE_CSC_MODE = 0x0, .PRE_CSC_MODE_CURRENT = 0x2, .PRE_CSC_C11 = 0x0, .PRE_CSC_C12 = 0x10, .PRE_CSC_C33 = 0x0, .PRE_CSC_C34 = 0x10, .CM_POST_CSC_MODE = 0x0, .CM_POST_CSC_MODE_CURRENT = 0x2, .CM_POST_CSC_C11 = 0x0, .CM_POST_CSC_C12 = 0x10, .CM_POST_CSC_C33 = 0x0, .CM_POST_CSC_C34 = 0x10, .CNVC_BYPASS = 0xc, .FORMAT_CONTROL__ALPHA_EN = 0x8, .FORMAT_EXPANSION_MODE = 0x0, .CNVC_SURFACE_PIXEL_FORMAT = 0x0, .CNVC_ALPHA_PLANE_ENABLE = 0x8, .CUR0_MODE = 0x4, .CUR0_EXPANSION_MODE = 0x1, .CUR0_ENABLE = 0x0, .CUR0_COLOR0 = 0x0, .CUR0_COLOR1 = 0x0, .CUR0_FP_BIAS = 0x10, .CUR0_FP_SCALE = 0x0, .DPP_CLOCK_ENABLE = 0x4, .CM_HDR_MULT_COEF = 0x0, .CM_BYPASS = 0x0, .CURSOR_MODE = 0x8, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK = 0x18, .CURSOR_ENABLE = 0x0, .FORMAT_CNV16 = 0x4, .CNVC_BYPASS_MSB_ALIGN = 0xd, .CLAMP_POSITIVE = 0x10, .CLAMP_POSITIVE_C = 0x11, .FORMAT_CROSSBAR_R = 0x18, .FORMAT_CROSSBAR_G = 0x1a, .FORMAT_CROSSBAR_B = 0x1c , .ALPHA_2BIT_LUT0 = 0x0, .ALPHA_2BIT_LUT1 = 0x8, .ALPHA_2BIT_LUT2 = 0x10, .ALPHA_2BIT_LUT3 = 0x18, .FCNV_FP_BIAS_R = 0x0, .FCNV_FP_BIAS_G = 0x0, .FCNV_FP_BIAS_B = 0x0, .FCNV_FP_SCALE_R = 0x0, .FCNV_FP_SCALE_G = 0x0, .FCNV_FP_SCALE_B = 0x0, .COLOR_KEYER_EN = 0x0, .COLOR_KEYER_MODE = 0x4, .COLOR_KEYER_ALPHA_LOW = 0x0, .COLOR_KEYER_ALPHA_HIGH = 0x10, .COLOR_KEYER_RED_LOW = 0x0, .COLOR_KEYER_RED_HIGH = 0x10 , .COLOR_KEYER_GREEN_LOW = 0x0, .COLOR_KEYER_GREEN_HIGH = 0x10 , .COLOR_KEYER_BLUE_LOW = 0x0, .COLOR_KEYER_BLUE_HIGH = 0x10, .CUR0_PIX_INV_MODE = 0x2, .CUR0_PIXEL_ALPHA_MOD_EN = 0x7, .CUR0_ROM_EN = 0x3, .OBUF_MEM_PWR_FORCE = 0x0, .LUT_MEM_PWR_FORCE = 0x0, . LUT_MEM_PWR_STATE = 0x0 |
369 | }; |
370 | |
371 | static const struct dcn3_dpp_mask tf_mask = { |
372 | DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK).GAMCOR_MEM_PWR_STATE = 0x00000003L, .CM_DEALPHA_EN = 0x00000001L , .CM_DEALPHA_ABLND = 0x00000002L, .CM_BIAS_CR_R = 0x0000FFFFL , .CM_BIAS_Y_G = 0x0000FFFFL, .CM_BIAS_CB_B = 0xFFFF0000L, .GAMCOR_MEM_PWR_DIS = 0x00000004L, .GAMCOR_MEM_PWR_FORCE = 0x00000003L, .PRE_DEGAM_MODE = 0x00000003L, .PRE_DEGAM_SELECT = 0x00000070L, .CM_GAMCOR_MODE = 0x00000003L, .CM_GAMCOR_SELECT = 0x00000004L, .CM_GAMCOR_PWL_DISABLE = 0x00000008L, .CM_GAMCOR_MODE_CURRENT = 0x00000030L, .CM_GAMCOR_SELECT_CURRENT = 0x00000040L, .CM_GAMCOR_LUT_INDEX = 0x000001FFL, .CM_GAMCOR_LUT_DATA = 0x0003FFFFL, .CM_GAMCOR_LUT_WRITE_COLOR_MASK = 0x00000007L , .CM_GAMCOR_LUT_READ_COLOR_SEL = 0x00000018L, .CM_GAMCOR_LUT_READ_DBG = 0x00000020L, .CM_GAMCOR_LUT_HOST_SEL = 0x00000040L, .CM_GAMCOR_LUT_CONFIG_MODE = 0x00000080L, .CM_GAMCOR_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL , .CM_GAMCOR_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .CM_GAMCOR_RAMA_OFFSET_B = 0x0007FFFFL, .CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L , .CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_GAMUT_REMAP_MODE = 0x00000003L, .CM_GAMUT_REMAP_MODE_CURRENT = 0x0000000CL, .CM_GAMUT_REMAP_C11 = 0x0000FFFFL, .CM_GAMUT_REMAP_C12 = 0xFFFF0000L, .CM_GAMUT_REMAP_C13 = 0x0000FFFFL, .CM_GAMUT_REMAP_C14 = 0xFFFF0000L, .CM_GAMUT_REMAP_C21 = 0x0000FFFFL, .CM_GAMUT_REMAP_C22 = 0xFFFF0000L, .CM_GAMUT_REMAP_C23 = 0x0000FFFFL, .CM_GAMUT_REMAP_C24 = 0xFFFF0000L, .CM_GAMUT_REMAP_C31 = 0x0000FFFFL, .CM_GAMUT_REMAP_C32 = 0xFFFF0000L, .CM_GAMUT_REMAP_C33 = 0x0000FFFFL, .CM_GAMUT_REMAP_C34 = 0xFFFF0000L, .EXT_OVERSCAN_LEFT = 0x1FFF0000L, .EXT_OVERSCAN_RIGHT = 0x00001FFFL, .EXT_OVERSCAN_BOTTOM = 0x00001FFFL, .EXT_OVERSCAN_TOP = 0x1FFF0000L, .OTG_H_BLANK_START = 0x00003FFFL, .OTG_H_BLANK_END = 0x3FFF0000L, .OTG_V_BLANK_START = 0x00003FFFL, .OTG_V_BLANK_END = 0x3FFF0000L, .INTERLEAVE_EN = 0x00000001L, .LB_DATA_FORMAT__ALPHA_EN = 0x00000010L, .MEMORY_CONFIG = 0x00000003L, .LB_MAX_PARTITIONS = 0x00003F00L, .AUTOCAL_MODE = 0x00000003L, .AUTOCAL_NUM_PIPE = 0x00000300L, .AUTOCAL_PIPE_ID = 0x00003000L, .SCL_V_NUM_TAPS = 0x00000007L, .SCL_H_NUM_TAPS = 0x00000070L, .SCL_V_NUM_TAPS_C = 0x00000700L, .SCL_H_NUM_TAPS_C = 0x00007000L, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x00000003L, .SCL_COEF_RAM_PHASE = 0x00003F00L, .SCL_COEF_RAM_FILTER_TYPE = 0x00030000L, .SCL_COEF_RAM_EVEN_TAP_COEF = 0x00003FFFL, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0x00008000L, .SCL_COEF_RAM_ODD_TAP_COEF = 0x3FFF0000L, .SCL_COEF_RAM_ODD_TAP_COEF_EN = 0x80000000L, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x00000001L, . SCL_H_2TAP_SHARP_EN = 0x00000010L, .SCL_H_2TAP_SHARP_FACTOR = 0x00000700L, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x00010000L, .SCL_V_2TAP_SHARP_EN = 0x00100000L, .SCL_V_2TAP_SHARP_FACTOR = 0x07000000L, .SCL_COEF_RAM_SELECT = 0x00000100L, .DSCL_MODE = 0x00000007L, .RECOUT_START_X = 0x00001FFFL , .RECOUT_START_Y = 0x1FFF0000L, .RECOUT_WIDTH = 0x00003FFFL, .RECOUT_HEIGHT = 0x3FFF0000L, .MPC_WIDTH = 0x00003FFFL, .MPC_HEIGHT = 0x3FFF0000L, .SCL_H_SCALE_RATIO = 0x07FFFFFFL, .SCL_V_SCALE_RATIO = 0x07FFFFFFL, .SCL_H_SCALE_RATIO_C = 0x07FFFFFFL, .SCL_V_SCALE_RATIO_C = 0x07FFFFFFL, .SCL_H_INIT_FRAC = 0x00FFFFFFL, .SCL_H_INIT_INT = 0x0F000000L, .SCL_H_INIT_FRAC_C = 0x00FFFFFFL, .SCL_H_INIT_INT_C = 0x0F000000L, .SCL_V_INIT_FRAC = 0x00FFFFFFL, .SCL_V_INIT_INT = 0x0F000000L, .SCL_V_INIT_FRAC_C = 0x00FFFFFFL, .SCL_V_INIT_INT_C = 0x0F000000L, .SCL_CHROMA_COEF_MODE = 0x00010000L, .SCL_COEF_RAM_SELECT_CURRENT = 0x00001000L, .PRE_DEALPHA_EN = 0x00000001L, .PRE_DEALPHA_ABLND_EN = 0x00000010L, .PRE_REALPHA_EN = 0x00000001L, .PRE_REALPHA_ABLND_EN = 0x00000010L, .PRE_CSC_MODE = 0x00000003L, .PRE_CSC_MODE_CURRENT = 0x0000000CL, .PRE_CSC_C11 = 0x0000FFFFL, .PRE_CSC_C12 = 0xFFFF0000L , .PRE_CSC_C33 = 0x0000FFFFL, .PRE_CSC_C34 = 0xFFFF0000L, .CM_POST_CSC_MODE = 0x00000003L, .CM_POST_CSC_MODE_CURRENT = 0x0000000CL, .CM_POST_CSC_C11 = 0x0000FFFFL, .CM_POST_CSC_C12 = 0xFFFF0000L, .CM_POST_CSC_C33 = 0x0000FFFFL, .CM_POST_CSC_C34 = 0xFFFF0000L, .CNVC_BYPASS = 0x00001000L, .FORMAT_CONTROL__ALPHA_EN = 0x00000100L, .FORMAT_EXPANSION_MODE = 0x00000001L, .CNVC_SURFACE_PIXEL_FORMAT = 0x0000007FL, .CNVC_ALPHA_PLANE_ENABLE = 0x00000100L, .CUR0_MODE = 0x00000070L, .CUR0_EXPANSION_MODE = 0x00000002L, .CUR0_ENABLE = 0x00000001L, .CUR0_COLOR0 = 0x00FFFFFFL , .CUR0_COLOR1 = 0x00FFFFFFL, .CUR0_FP_BIAS = 0xFFFF0000L, .CUR0_FP_SCALE = 0x0000FFFFL, .DPP_CLOCK_ENABLE = 0x00000010L, .CM_HDR_MULT_COEF = 0x0007FFFFL, .CM_BYPASS = 0x00000001L, .CURSOR_MODE = 0x00000700L , .CURSOR_PITCH = 0x00030000L, .CURSOR_LINES_PER_CHUNK = 0x1F000000L , .CURSOR_ENABLE = 0x00000001L, .FORMAT_CNV16 = 0x00000010L, . CNVC_BYPASS_MSB_ALIGN = 0x00002000L, .CLAMP_POSITIVE = 0x00010000L , .CLAMP_POSITIVE_C = 0x00020000L, .FORMAT_CROSSBAR_R = 0x03000000L , .FORMAT_CROSSBAR_G = 0x0C000000L, .FORMAT_CROSSBAR_B = 0x30000000L , .ALPHA_2BIT_LUT0 = 0x000000FFL, .ALPHA_2BIT_LUT1 = 0x0000FF00L , .ALPHA_2BIT_LUT2 = 0x00FF0000L, .ALPHA_2BIT_LUT3 = 0xFF000000L , .FCNV_FP_BIAS_R = 0x0007FFFFL, .FCNV_FP_BIAS_G = 0x0007FFFFL , .FCNV_FP_BIAS_B = 0x0007FFFFL, .FCNV_FP_SCALE_R = 0x0007FFFFL , .FCNV_FP_SCALE_G = 0x0007FFFFL, .FCNV_FP_SCALE_B = 0x0007FFFFL , .COLOR_KEYER_EN = 0x00000001L, .COLOR_KEYER_MODE = 0x00000030L , .COLOR_KEYER_ALPHA_LOW = 0x0000FFFFL, .COLOR_KEYER_ALPHA_HIGH = 0xFFFF0000L, .COLOR_KEYER_RED_LOW = 0x0000FFFFL, .COLOR_KEYER_RED_HIGH = 0xFFFF0000L, .COLOR_KEYER_GREEN_LOW = 0x0000FFFFL, .COLOR_KEYER_GREEN_HIGH = 0xFFFF0000L, .COLOR_KEYER_BLUE_LOW = 0x0000FFFFL, .COLOR_KEYER_BLUE_HIGH = 0xFFFF0000L, .CUR0_PIX_INV_MODE = 0x00000004L, .CUR0_PIXEL_ALPHA_MOD_EN = 0x00000080L, .CUR0_ROM_EN = 0x00000008L, .OBUF_MEM_PWR_FORCE = 0x00000003L, .LUT_MEM_PWR_FORCE = 0x00000003L, .LUT_MEM_PWR_STATE = 0x00000003L |
373 | }; |
374 | |
375 | |
376 | #define opp_regs_init(id)( ( dccg_regs[id].FMT_BIT_DEPTH_CONTROL = ctx->dcn_reg_offsets [regFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX] + regFMTid_FMT_BIT_DEPTH_CONTROL , dccg_regs[id].FMT_CONTROL = ctx->dcn_reg_offsets[regFMTid_FMT_CONTROL_BASE_IDX ] + regFMTid_FMT_CONTROL, dccg_regs[id].FMT_DITHER_RAND_R_SEED = ctx->dcn_reg_offsets[regFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX ] + regFMTid_FMT_DITHER_RAND_R_SEED, dccg_regs[id].FMT_DITHER_RAND_G_SEED = ctx->dcn_reg_offsets[regFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX ] + regFMTid_FMT_DITHER_RAND_G_SEED, dccg_regs[id].FMT_DITHER_RAND_B_SEED = ctx->dcn_reg_offsets[regFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX ] + regFMTid_FMT_DITHER_RAND_B_SEED, dccg_regs[id].FMT_CLAMP_CNTL = ctx->dcn_reg_offsets[regFMTid_FMT_CLAMP_CNTL_BASE_IDX] + regFMTid_FMT_CLAMP_CNTL, dccg_regs[id].FMT_DYNAMIC_EXP_CNTL = ctx->dcn_reg_offsets[regFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX ] + regFMTid_FMT_DYNAMIC_EXP_CNTL, dccg_regs[id].FMT_MAP420_MEMORY_CONTROL = ctx->dcn_reg_offsets[regFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX ] + regFMTid_FMT_MAP420_MEMORY_CONTROL, dccg_regs[id].OPPBUF_CONTROL = ctx->dcn_reg_offsets[regOPPBUFid_OPPBUF_CONTROL_BASE_IDX ] + regOPPBUFid_OPPBUF_CONTROL, dccg_regs[id].OPPBUF_3D_PARAMETERS_0 = ctx->dcn_reg_offsets[regOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX ] + regOPPBUFid_OPPBUF_3D_PARAMETERS_0, dccg_regs[id].OPPBUF_3D_PARAMETERS_1 = ctx->dcn_reg_offsets[regOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX ] + regOPPBUFid_OPPBUF_3D_PARAMETERS_1, dccg_regs[id].OPP_PIPE_CONTROL = ctx->dcn_reg_offsets[regOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX ] + regOPP_PIPEid_OPP_PIPE_CONTROL ), ( dccg_regs[id].DPG_CONTROL = ctx->dcn_reg_offsets[regDPGid_DPG_CONTROL_BASE_IDX] + regDPGid_DPG_CONTROL , dccg_regs[id].DPG_DIMENSIONS = ctx->dcn_reg_offsets[regDPGid_DPG_DIMENSIONS_BASE_IDX ] + regDPGid_DPG_DIMENSIONS, dccg_regs[id].DPG_OFFSET_SEGMENT = ctx->dcn_reg_offsets[regDPGid_DPG_OFFSET_SEGMENT_BASE_IDX ] + regDPGid_DPG_OFFSET_SEGMENT, dccg_regs[id].DPG_COLOUR_B_CB = ctx->dcn_reg_offsets[regDPGid_DPG_COLOUR_B_CB_BASE_IDX] + regDPGid_DPG_COLOUR_B_CB, dccg_regs[id].DPG_COLOUR_G_Y = ctx ->dcn_reg_offsets[regDPGid_DPG_COLOUR_G_Y_BASE_IDX] + regDPGid_DPG_COLOUR_G_Y , dccg_regs[id].DPG_COLOUR_R_CR = ctx->dcn_reg_offsets[regDPGid_DPG_COLOUR_R_CR_BASE_IDX ] + regDPGid_DPG_COLOUR_R_CR, dccg_regs[id].DPG_RAMP_CONTROL = ctx->dcn_reg_offsets[regDPGid_DPG_RAMP_CONTROL_BASE_IDX] + regDPGid_DPG_RAMP_CONTROL, dccg_regs[id].DPG_STATUS = ctx-> dcn_reg_offsets[regDPGid_DPG_STATUS_BASE_IDX] + regDPGid_DPG_STATUS ), dccg_regs[id].FMT_422_CONTROL = ctx->dcn_reg_offsets[regFMTid_FMT_422_CONTROL_BASE_IDX ] + regFMTid_FMT_422_CONTROL )\ |
377 | OPP_REG_LIST_DCN30_RI(id)( ( dccg_regs[id].FMT_BIT_DEPTH_CONTROL = ctx->dcn_reg_offsets [regFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX] + regFMTid_FMT_BIT_DEPTH_CONTROL , dccg_regs[id].FMT_CONTROL = ctx->dcn_reg_offsets[regFMTid_FMT_CONTROL_BASE_IDX ] + regFMTid_FMT_CONTROL, dccg_regs[id].FMT_DITHER_RAND_R_SEED = ctx->dcn_reg_offsets[regFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX ] + regFMTid_FMT_DITHER_RAND_R_SEED, dccg_regs[id].FMT_DITHER_RAND_G_SEED = ctx->dcn_reg_offsets[regFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX ] + regFMTid_FMT_DITHER_RAND_G_SEED, dccg_regs[id].FMT_DITHER_RAND_B_SEED = ctx->dcn_reg_offsets[regFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX ] + regFMTid_FMT_DITHER_RAND_B_SEED, dccg_regs[id].FMT_CLAMP_CNTL = ctx->dcn_reg_offsets[regFMTid_FMT_CLAMP_CNTL_BASE_IDX] + regFMTid_FMT_CLAMP_CNTL, dccg_regs[id].FMT_DYNAMIC_EXP_CNTL = ctx->dcn_reg_offsets[regFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX ] + regFMTid_FMT_DYNAMIC_EXP_CNTL, dccg_regs[id].FMT_MAP420_MEMORY_CONTROL = ctx->dcn_reg_offsets[regFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX ] + regFMTid_FMT_MAP420_MEMORY_CONTROL, dccg_regs[id].OPPBUF_CONTROL = ctx->dcn_reg_offsets[regOPPBUFid_OPPBUF_CONTROL_BASE_IDX ] + regOPPBUFid_OPPBUF_CONTROL, dccg_regs[id].OPPBUF_3D_PARAMETERS_0 = ctx->dcn_reg_offsets[regOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX ] + regOPPBUFid_OPPBUF_3D_PARAMETERS_0, dccg_regs[id].OPPBUF_3D_PARAMETERS_1 = ctx->dcn_reg_offsets[regOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX ] + regOPPBUFid_OPPBUF_3D_PARAMETERS_1, dccg_regs[id].OPP_PIPE_CONTROL = ctx->dcn_reg_offsets[regOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX ] + regOPP_PIPEid_OPP_PIPE_CONTROL ), ( dccg_regs[id].DPG_CONTROL = ctx->dcn_reg_offsets[regDPGid_DPG_CONTROL_BASE_IDX] + regDPGid_DPG_CONTROL , dccg_regs[id].DPG_DIMENSIONS = ctx->dcn_reg_offsets[regDPGid_DPG_DIMENSIONS_BASE_IDX ] + regDPGid_DPG_DIMENSIONS, dccg_regs[id].DPG_OFFSET_SEGMENT = ctx->dcn_reg_offsets[regDPGid_DPG_OFFSET_SEGMENT_BASE_IDX ] + regDPGid_DPG_OFFSET_SEGMENT, dccg_regs[id].DPG_COLOUR_B_CB = ctx->dcn_reg_offsets[regDPGid_DPG_COLOUR_B_CB_BASE_IDX] + regDPGid_DPG_COLOUR_B_CB, dccg_regs[id].DPG_COLOUR_G_Y = ctx ->dcn_reg_offsets[regDPGid_DPG_COLOUR_G_Y_BASE_IDX] + regDPGid_DPG_COLOUR_G_Y , dccg_regs[id].DPG_COLOUR_R_CR = ctx->dcn_reg_offsets[regDPGid_DPG_COLOUR_R_CR_BASE_IDX ] + regDPGid_DPG_COLOUR_R_CR, dccg_regs[id].DPG_RAMP_CONTROL = ctx->dcn_reg_offsets[regDPGid_DPG_RAMP_CONTROL_BASE_IDX] + regDPGid_DPG_RAMP_CONTROL, dccg_regs[id].DPG_STATUS = ctx-> dcn_reg_offsets[regDPGid_DPG_STATUS_BASE_IDX] + regDPGid_DPG_STATUS ), dccg_regs[id].FMT_422_CONTROL = ctx->dcn_reg_offsets[regFMTid_FMT_422_CONTROL_BASE_IDX ] + regFMTid_FMT_422_CONTROL ) |
378 | |
379 | static struct dcn20_opp_registers opp_regs[4]; |
380 | |
381 | static const struct dcn20_opp_shift opp_shift = { |
382 | OPP_MASK_SH_LIST_DCN20(__SHIFT).FMT_TRUNCATE_EN = 0x0, .FMT_TRUNCATE_DEPTH = 0x4, .FMT_TRUNCATE_MODE = 0x1, .FMT_SPATIAL_DITHER_EN = 0x8, .FMT_SPATIAL_DITHER_MODE = 0x9, .FMT_SPATIAL_DITHER_DEPTH = 0xb, .FMT_TEMPORAL_DITHER_EN = 0x10, .FMT_HIGHPASS_RANDOM_ENABLE = 0xf, .FMT_FRAME_RANDOM_ENABLE = 0xd, .FMT_RGB_RANDOM_ENABLE = 0xe, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0x8, .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0xc, .FMT_PIXEL_ENCODING = 0x10, .FMT_STEREOSYNC_OVERRIDE = 0x0, .FMT_RAND_R_SEED = 0x0 , .FMT_RAND_G_SEED = 0x0, .FMT_RAND_B_SEED = 0x0, .FMT_CLAMP_DATA_EN = 0x0, .FMT_CLAMP_COLOR_FORMAT = 0x10, .FMT_DYNAMIC_EXP_EN = 0x0, .FMT_DYNAMIC_EXP_MODE = 0x4, .FMT_MAP420MEM_PWR_FORCE = 0x0, .OPPBUF_ACTIVE_WIDTH = 0x0, .OPPBUF_PIXEL_REPETITION = 0x18 , .OPPBUF_3D_VACT_SPACE1_SIZE = 0x0, .OPPBUF_3D_VACT_SPACE2_SIZE = 0xa, .OPP_PIPE_CLOCK_EN = 0x0, .DPG_EN = 0x0, .DPG_MODE = 0x4 , .DPG_DYNAMIC_RANGE = 0x8, .DPG_BIT_DEPTH = 0xc, .DPG_VRES = 0x10, .DPG_HRES = 0x14, .DPG_ACTIVE_WIDTH = 0x10, .DPG_ACTIVE_HEIGHT = 0x0, .DPG_X_OFFSET = 0x0, .DPG_SEGMENT_WIDTH = 0x10, .DPG_COLOUR0_R_CR = 0x0, .DPG_COLOUR1_R_CR = 0x10, .DPG_COLOUR0_B_CB = 0x0, .DPG_COLOUR1_B_CB = 0x10, .DPG_COLOUR0_G_Y = 0x0, .DPG_COLOUR1_G_Y = 0x10, .DPG_RAMP0_OFFSET = 0x0, .DPG_INC0 = 0x18, .DPG_INC1 = 0x1c, .DPG_DOUBLE_BUFFER_PENDING = 0x0, .OPPBUF_DISPLAY_SEGMENTATION = 0x10, .OPPBUF_OVERLAP_PIXEL_NUM = 0x14, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x0 |
383 | }; |
384 | |
385 | static const struct dcn20_opp_mask opp_mask = { |
386 | OPP_MASK_SH_LIST_DCN20(_MASK).FMT_TRUNCATE_EN = 0x00000001L, .FMT_TRUNCATE_DEPTH = 0x00000030L , .FMT_TRUNCATE_MODE = 0x00000002L, .FMT_SPATIAL_DITHER_EN = 0x00000100L , .FMT_SPATIAL_DITHER_MODE = 0x00000600L, .FMT_SPATIAL_DITHER_DEPTH = 0x00001800L, .FMT_TEMPORAL_DITHER_EN = 0x00010000L, .FMT_HIGHPASS_RANDOM_ENABLE = 0x00008000L, .FMT_FRAME_RANDOM_ENABLE = 0x00002000L, .FMT_RGB_RANDOM_ENABLE = 0x00004000L, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0x00000F00L , .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0x00003000L, . FMT_PIXEL_ENCODING = 0x00030000L, .FMT_STEREOSYNC_OVERRIDE = 0x00000001L , .FMT_RAND_R_SEED = 0x000000FFL, .FMT_RAND_G_SEED = 0x000000FFL , .FMT_RAND_B_SEED = 0x000000FFL, .FMT_CLAMP_DATA_EN = 0x00000001L , .FMT_CLAMP_COLOR_FORMAT = 0x00070000L, .FMT_DYNAMIC_EXP_EN = 0x00000001L, .FMT_DYNAMIC_EXP_MODE = 0x00000010L, .FMT_MAP420MEM_PWR_FORCE = 0x00000003L, .OPPBUF_ACTIVE_WIDTH = 0x00003FFFL, .OPPBUF_PIXEL_REPETITION = 0x0F000000L, .OPPBUF_3D_VACT_SPACE1_SIZE = 0x000003FFL, .OPPBUF_3D_VACT_SPACE2_SIZE = 0x000FFC00L, .OPP_PIPE_CLOCK_EN = 0x00000001L, .DPG_EN = 0x00000001L , .DPG_MODE = 0x00000070L, .DPG_DYNAMIC_RANGE = 0x00000100L, . DPG_BIT_DEPTH = 0x00003000L, .DPG_VRES = 0x000F0000L, .DPG_HRES = 0x00F00000L, .DPG_ACTIVE_WIDTH = 0x3FFF0000L, .DPG_ACTIVE_HEIGHT = 0x00003FFFL, .DPG_X_OFFSET = 0x00003FFFL, .DPG_SEGMENT_WIDTH = 0x3FFF0000L, .DPG_COLOUR0_R_CR = 0x0000FFFFL, .DPG_COLOUR1_R_CR = 0xFFFF0000L, .DPG_COLOUR0_B_CB = 0x0000FFFFL, .DPG_COLOUR1_B_CB = 0xFFFF0000L, .DPG_COLOUR0_G_Y = 0x0000FFFFL, .DPG_COLOUR1_G_Y = 0xFFFF0000L, .DPG_RAMP0_OFFSET = 0x0000FFFFL, .DPG_INC0 = 0x0F000000L , .DPG_INC1 = 0xF0000000L, .DPG_DOUBLE_BUFFER_PENDING = 0x00000001L , .OPPBUF_DISPLAY_SEGMENTATION = 0x00070000L, .OPPBUF_OVERLAP_PIXEL_NUM = 0x00F00000L, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x00000001L |
387 | }; |
388 | |
389 | #define aux_engine_regs_init(id)( ( dccg_regs[id].AUX_CONTROL = ctx->dcn_reg_offsets[regDP_AUXid_AUX_CONTROL_BASE_IDX ] + regDP_AUXid_AUX_CONTROL, dccg_regs[id].AUX_ARB_CONTROL = ctx ->dcn_reg_offsets[regDP_AUXid_AUX_ARB_CONTROL_BASE_IDX] + regDP_AUXid_AUX_ARB_CONTROL , dccg_regs[id].AUX_SW_DATA = ctx->dcn_reg_offsets[regDP_AUXid_AUX_SW_DATA_BASE_IDX ] + regDP_AUXid_AUX_SW_DATA, dccg_regs[id].AUX_SW_CONTROL = ctx ->dcn_reg_offsets[regDP_AUXid_AUX_SW_CONTROL_BASE_IDX] + regDP_AUXid_AUX_SW_CONTROL , dccg_regs[id].AUX_INTERRUPT_CONTROL = ctx->dcn_reg_offsets [regDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX] + regDP_AUXid_AUX_INTERRUPT_CONTROL , dccg_regs[id].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [regDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX] + regDP_AUXid_AUX_DPHY_RX_CONTROL1 , dccg_regs[id].AUX_SW_STATUS = ctx->dcn_reg_offsets[regDP_AUXid_AUX_SW_STATUS_BASE_IDX ] + regDP_AUXid_AUX_SW_STATUS ), dccg_regs[id].AUXN_IMPCAL = 0 , dccg_regs[id].AUXP_IMPCAL = 0, dccg_regs[id].AUX_RESET_MASK = 0x00000010L, dccg_regs[id].AUX_RESET_MASK = 0x00000010L )\ |
390 | ( \ |
391 | AUX_COMMON_REG_LIST0_RI(id)( dccg_regs[id].AUX_CONTROL = ctx->dcn_reg_offsets[regDP_AUXid_AUX_CONTROL_BASE_IDX ] + regDP_AUXid_AUX_CONTROL, dccg_regs[id].AUX_ARB_CONTROL = ctx ->dcn_reg_offsets[regDP_AUXid_AUX_ARB_CONTROL_BASE_IDX] + regDP_AUXid_AUX_ARB_CONTROL , dccg_regs[id].AUX_SW_DATA = ctx->dcn_reg_offsets[regDP_AUXid_AUX_SW_DATA_BASE_IDX ] + regDP_AUXid_AUX_SW_DATA, dccg_regs[id].AUX_SW_CONTROL = ctx ->dcn_reg_offsets[regDP_AUXid_AUX_SW_CONTROL_BASE_IDX] + regDP_AUXid_AUX_SW_CONTROL , dccg_regs[id].AUX_INTERRUPT_CONTROL = ctx->dcn_reg_offsets [regDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX] + regDP_AUXid_AUX_INTERRUPT_CONTROL , dccg_regs[id].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [regDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX] + regDP_AUXid_AUX_DPHY_RX_CONTROL1 , dccg_regs[id].AUX_SW_STATUS = ctx->dcn_reg_offsets[regDP_AUXid_AUX_SW_STATUS_BASE_IDX ] + regDP_AUXid_AUX_SW_STATUS ), \ |
392 | SR_ARR_INIT(AUXN_IMPCAL, id, 0)dccg_regs[id].AUXN_IMPCAL = 0, \ |
393 | SR_ARR_INIT(AUXP_IMPCAL, id, 0)dccg_regs[id].AUXP_IMPCAL = 0, \ |
394 | SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)dccg_regs[id].AUX_RESET_MASK = 0x00000010L, \ |
395 | SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)dccg_regs[id].AUX_RESET_MASK = 0x00000010L\ |
396 | ) |
397 | |
398 | static struct dce110_aux_registers aux_engine_regs[5]; |
399 | |
400 | static const struct dce110_aux_registers_shift aux_shift = { |
401 | DCN_AUX_MASK_SH_LIST(__SHIFT).AUX_EN = 0x0, .AUX_RESET = 0x4, .AUX_RESET_DONE = 0x5, .AUX_REG_RW_CNTL_STATUS = 0x2, .AUX_SW_USE_AUX_REG_REQ = 0x10, .AUX_SW_DONE_USING_AUX_REG = 0x11, .AUX_SW_START_DELAY = 0x4, .AUX_SW_WR_BYTES = 0x10, . AUX_SW_GO = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_DATA_RW = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_INDEX = 0x10, .AUX_SW_DATA = 0x8, .AUX_SW_REPLY_BYTE_COUNT = 0x18, . AUX_SW_DONE = 0x0, .AUX_SW_DONE_ACK = 0x1, .AUX_RX_TIMEOUT_LEN = 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf |
402 | }; |
403 | |
404 | static const struct dce110_aux_registers_mask aux_mask = { |
405 | DCN_AUX_MASK_SH_LIST(_MASK).AUX_EN = 0x00000001L, .AUX_RESET = 0x00000010L, .AUX_RESET_DONE = 0x00000020L, .AUX_REG_RW_CNTL_STATUS = 0x0000000CL, .AUX_SW_USE_AUX_REG_REQ = 0x00010000L, .AUX_SW_DONE_USING_AUX_REG = 0x00020000L, .AUX_SW_START_DELAY = 0x000000F0L, .AUX_SW_WR_BYTES = 0x001F0000L, .AUX_SW_GO = 0x00000001L , .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, .AUX_SW_DATA_RW = 0x00000001L, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, . AUX_SW_INDEX = 0x001F0000L, .AUX_SW_DATA = 0x0000FF00L, .AUX_SW_REPLY_BYTE_COUNT = 0x1F000000L, .AUX_SW_DONE = 0x00000001L, .AUX_SW_DONE_ACK = 0x00000002L, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL = 0x00018000L |
406 | }; |
407 | |
408 | #define dwbc_regs_dcn3_init(id)( dccg_regs[id].DWB_ENABLE_CLK_CTRL = ctx->dcn_reg_offsets [2] + 0x3228, dccg_regs[id].DWB_MEM_PWR_CTRL = ctx->dcn_reg_offsets [2] + 0x3229, dccg_regs[id].FC_MODE_CTRL = ctx->dcn_reg_offsets [2] + 0x322a, dccg_regs[id].FC_FLOW_CTRL = ctx->dcn_reg_offsets [2] + 0x322b, dccg_regs[id].FC_WINDOW_START = ctx->dcn_reg_offsets [2] + 0x322c, dccg_regs[id].FC_WINDOW_SIZE = ctx->dcn_reg_offsets [2] + 0x322d, dccg_regs[id].FC_SOURCE_SIZE = ctx->dcn_reg_offsets [2] + 0x322e, dccg_regs[id].DWB_UPDATE_CTRL = ctx->dcn_reg_offsets [2] + 0x322f, dccg_regs[id].DWB_CRC_CTRL = ctx->dcn_reg_offsets [2] + 0x3230, dccg_regs[id].DWB_CRC_MASK_R_G = ctx->dcn_reg_offsets [2] + 0x3231, dccg_regs[id].DWB_CRC_MASK_B_A = ctx->dcn_reg_offsets [2] + 0x3232, dccg_regs[id].DWB_CRC_VAL_R_G = ctx->dcn_reg_offsets [2] + 0x3233, dccg_regs[id].DWB_CRC_VAL_B_A = ctx->dcn_reg_offsets [2] + 0x3234, dccg_regs[id].DWB_OUT_CTRL = ctx->dcn_reg_offsets [2] + 0x3235, dccg_regs[id].DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = ctx->dcn_reg_offsets[2] + 0x3236, dccg_regs[id].DWB_MMHUBBUB_BACKPRESSURE_CNT = ctx->dcn_reg_offsets[2] + 0x3237, dccg_regs[id].DWB_HOST_READ_CONTROL = ctx->dcn_reg_offsets[2] + 0x3238, dccg_regs[id].DWB_SOFT_RESET = ctx->dcn_reg_offsets[2] + 0x323b, dccg_regs[id].DWB_HDR_MULT_COEF = ctx->dcn_reg_offsets[2] + 0x3294, dccg_regs[id].DWB_GAMUT_REMAP_MODE = ctx->dcn_reg_offsets[2] + 0x3295, dccg_regs[id].DWB_GAMUT_REMAP_COEF_FORMAT = ctx->dcn_reg_offsets[2] + 0x3296, dccg_regs[id].DWB_GAMUT_REMAPA_C11_C12 = ctx->dcn_reg_offsets[2] + 0x3297, dccg_regs[id].DWB_GAMUT_REMAPA_C13_C14 = ctx->dcn_reg_offsets[2] + 0x3298, dccg_regs[id].DWB_GAMUT_REMAPA_C21_C22 = ctx->dcn_reg_offsets[2] + 0x3299, dccg_regs[id].DWB_GAMUT_REMAPA_C23_C24 = ctx->dcn_reg_offsets[2] + 0x329a, dccg_regs[id].DWB_GAMUT_REMAPA_C31_C32 = ctx->dcn_reg_offsets[2] + 0x329b, dccg_regs[id].DWB_GAMUT_REMAPA_C33_C34 = ctx->dcn_reg_offsets[2] + 0x329c, dccg_regs[id].DWB_GAMUT_REMAPB_C11_C12 = ctx->dcn_reg_offsets[2] + 0x329d, dccg_regs[id].DWB_GAMUT_REMAPB_C13_C14 = ctx->dcn_reg_offsets[2] + 0x329e, dccg_regs[id].DWB_GAMUT_REMAPB_C21_C22 = ctx->dcn_reg_offsets[2] + 0x329f, dccg_regs[id].DWB_GAMUT_REMAPB_C23_C24 = ctx->dcn_reg_offsets[2] + 0x32a0, dccg_regs[id].DWB_GAMUT_REMAPB_C31_C32 = ctx->dcn_reg_offsets[2] + 0x32a1, dccg_regs[id].DWB_GAMUT_REMAPB_C33_C34 = ctx->dcn_reg_offsets[2] + 0x32a2, dccg_regs[id].DWB_OGAM_CONTROL = ctx->dcn_reg_offsets[2] + 0x32a3, dccg_regs[id].DWB_OGAM_LUT_INDEX = ctx->dcn_reg_offsets[2] + 0x32a4, dccg_regs[id].DWB_OGAM_LUT_DATA = ctx->dcn_reg_offsets[2] + 0x32a5, dccg_regs[id].DWB_OGAM_LUT_CONTROL = ctx->dcn_reg_offsets[2] + 0x32a6, dccg_regs[id].DWB_OGAM_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32a7, dccg_regs[id].DWB_OGAM_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32a8, dccg_regs[id].DWB_OGAM_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32a9, dccg_regs[id].DWB_OGAM_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32aa, dccg_regs[id].DWB_OGAM_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ab, dccg_regs[id].DWB_OGAM_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32ac, dccg_regs[id].DWB_OGAM_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32ad, dccg_regs[id].DWB_OGAM_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32ae, dccg_regs[id].DWB_OGAM_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32af, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x32b0, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x32b1, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x32b2, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x32b3, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x32b4, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x32b5, dccg_regs[id].DWB_OGAM_RAMA_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x32b6, dccg_regs[id].DWB_OGAM_RAMA_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x32b7, dccg_regs[id].DWB_OGAM_RAMA_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x32b8, dccg_regs[id].DWB_OGAM_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x32b9, dccg_regs[id].DWB_OGAM_RAMA_REGION_2_3 = ctx->dcn_reg_offsets[2] + 0x32ba, dccg_regs[id].DWB_OGAM_RAMA_REGION_4_5 = ctx->dcn_reg_offsets[2] + 0x32bb, dccg_regs[id].DWB_OGAM_RAMA_REGION_6_7 = ctx->dcn_reg_offsets[2] + 0x32bc, dccg_regs[id].DWB_OGAM_RAMA_REGION_8_9 = ctx->dcn_reg_offsets[2] + 0x32bd, dccg_regs[id].DWB_OGAM_RAMA_REGION_10_11 = ctx->dcn_reg_offsets[2] + 0x32be, dccg_regs[id].DWB_OGAM_RAMA_REGION_12_13 = ctx->dcn_reg_offsets[2] + 0x32bf, dccg_regs[id].DWB_OGAM_RAMA_REGION_14_15 = ctx->dcn_reg_offsets[2] + 0x32c0, dccg_regs[id].DWB_OGAM_RAMA_REGION_16_17 = ctx->dcn_reg_offsets[2] + 0x32c1, dccg_regs[id].DWB_OGAM_RAMA_REGION_18_19 = ctx->dcn_reg_offsets[2] + 0x32c2, dccg_regs[id].DWB_OGAM_RAMA_REGION_20_21 = ctx->dcn_reg_offsets[2] + 0x32c3, dccg_regs[id].DWB_OGAM_RAMA_REGION_22_23 = ctx->dcn_reg_offsets[2] + 0x32c4, dccg_regs[id].DWB_OGAM_RAMA_REGION_24_25 = ctx->dcn_reg_offsets[2] + 0x32c5, dccg_regs[id].DWB_OGAM_RAMA_REGION_26_27 = ctx->dcn_reg_offsets[2] + 0x32c6, dccg_regs[id].DWB_OGAM_RAMA_REGION_28_29 = ctx->dcn_reg_offsets[2] + 0x32c7, dccg_regs[id].DWB_OGAM_RAMA_REGION_30_31 = ctx->dcn_reg_offsets[2] + 0x32c8, dccg_regs[id].DWB_OGAM_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x32c9, dccg_regs[id].DWB_OGAM_RAMB_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ca, dccg_regs[id].DWB_OGAM_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32cb, dccg_regs[id].DWB_OGAM_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32cc, dccg_regs[id].DWB_OGAM_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32cd, dccg_regs[id].DWB_OGAM_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ce, dccg_regs[id].DWB_OGAM_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32cf, dccg_regs[id].DWB_OGAM_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32d0, dccg_regs[id].DWB_OGAM_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32d1, dccg_regs[id].DWB_OGAM_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32d2, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x32d3, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x32d4, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x32d5, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x32d6, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x32d7, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x32d8, dccg_regs[id].DWB_OGAM_RAMB_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x32d9, dccg_regs[id].DWB_OGAM_RAMB_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x32da, dccg_regs[id].DWB_OGAM_RAMB_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x32db, dccg_regs[id].DWB_OGAM_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x32dc, dccg_regs[id].DWB_OGAM_RAMB_REGION_2_3 = ctx->dcn_reg_offsets[2] + 0x32dd, dccg_regs[id].DWB_OGAM_RAMB_REGION_4_5 = ctx->dcn_reg_offsets[2] + 0x32de, dccg_regs[id].DWB_OGAM_RAMB_REGION_6_7 = ctx->dcn_reg_offsets[2] + 0x32df, dccg_regs[id].DWB_OGAM_RAMB_REGION_8_9 = ctx->dcn_reg_offsets[2] + 0x32e0, dccg_regs[id].DWB_OGAM_RAMB_REGION_10_11 = ctx->dcn_reg_offsets[2] + 0x32e1, dccg_regs[id].DWB_OGAM_RAMB_REGION_12_13 = ctx->dcn_reg_offsets[2] + 0x32e2, dccg_regs[id].DWB_OGAM_RAMB_REGION_14_15 = ctx->dcn_reg_offsets[2] + 0x32e3, dccg_regs[id].DWB_OGAM_RAMB_REGION_16_17 = ctx->dcn_reg_offsets[2] + 0x32e4, dccg_regs[id].DWB_OGAM_RAMB_REGION_18_19 = ctx->dcn_reg_offsets[2] + 0x32e5, dccg_regs[id].DWB_OGAM_RAMB_REGION_20_21 = ctx->dcn_reg_offsets[2] + 0x32e6, dccg_regs[id].DWB_OGAM_RAMB_REGION_22_23 = ctx->dcn_reg_offsets[2] + 0x32e7, dccg_regs[id].DWB_OGAM_RAMB_REGION_24_25 = ctx->dcn_reg_offsets[2] + 0x32e8, dccg_regs[id].DWB_OGAM_RAMB_REGION_26_27 = ctx->dcn_reg_offsets[2] + 0x32e9, dccg_regs[id].DWB_OGAM_RAMB_REGION_28_29 = ctx->dcn_reg_offsets[2] + 0x32ea, dccg_regs[id].DWB_OGAM_RAMB_REGION_30_31 = ctx->dcn_reg_offsets[2] + 0x32eb, dccg_regs[id].DWB_OGAM_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x32ec )\ |
409 | DWBC_COMMON_REG_LIST_DCN30_RI(id)( dccg_regs[id].DWB_ENABLE_CLK_CTRL = ctx->dcn_reg_offsets [2] + 0x3228, dccg_regs[id].DWB_MEM_PWR_CTRL = ctx->dcn_reg_offsets [2] + 0x3229, dccg_regs[id].FC_MODE_CTRL = ctx->dcn_reg_offsets [2] + 0x322a, dccg_regs[id].FC_FLOW_CTRL = ctx->dcn_reg_offsets [2] + 0x322b, dccg_regs[id].FC_WINDOW_START = ctx->dcn_reg_offsets [2] + 0x322c, dccg_regs[id].FC_WINDOW_SIZE = ctx->dcn_reg_offsets [2] + 0x322d, dccg_regs[id].FC_SOURCE_SIZE = ctx->dcn_reg_offsets [2] + 0x322e, dccg_regs[id].DWB_UPDATE_CTRL = ctx->dcn_reg_offsets [2] + 0x322f, dccg_regs[id].DWB_CRC_CTRL = ctx->dcn_reg_offsets [2] + 0x3230, dccg_regs[id].DWB_CRC_MASK_R_G = ctx->dcn_reg_offsets [2] + 0x3231, dccg_regs[id].DWB_CRC_MASK_B_A = ctx->dcn_reg_offsets [2] + 0x3232, dccg_regs[id].DWB_CRC_VAL_R_G = ctx->dcn_reg_offsets [2] + 0x3233, dccg_regs[id].DWB_CRC_VAL_B_A = ctx->dcn_reg_offsets [2] + 0x3234, dccg_regs[id].DWB_OUT_CTRL = ctx->dcn_reg_offsets [2] + 0x3235, dccg_regs[id].DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = ctx->dcn_reg_offsets[2] + 0x3236, dccg_regs[id].DWB_MMHUBBUB_BACKPRESSURE_CNT = ctx->dcn_reg_offsets[2] + 0x3237, dccg_regs[id].DWB_HOST_READ_CONTROL = ctx->dcn_reg_offsets[2] + 0x3238, dccg_regs[id].DWB_SOFT_RESET = ctx->dcn_reg_offsets[2] + 0x323b, dccg_regs[id].DWB_HDR_MULT_COEF = ctx->dcn_reg_offsets[2] + 0x3294, dccg_regs[id].DWB_GAMUT_REMAP_MODE = ctx->dcn_reg_offsets[2] + 0x3295, dccg_regs[id].DWB_GAMUT_REMAP_COEF_FORMAT = ctx->dcn_reg_offsets[2] + 0x3296, dccg_regs[id].DWB_GAMUT_REMAPA_C11_C12 = ctx->dcn_reg_offsets[2] + 0x3297, dccg_regs[id].DWB_GAMUT_REMAPA_C13_C14 = ctx->dcn_reg_offsets[2] + 0x3298, dccg_regs[id].DWB_GAMUT_REMAPA_C21_C22 = ctx->dcn_reg_offsets[2] + 0x3299, dccg_regs[id].DWB_GAMUT_REMAPA_C23_C24 = ctx->dcn_reg_offsets[2] + 0x329a, dccg_regs[id].DWB_GAMUT_REMAPA_C31_C32 = ctx->dcn_reg_offsets[2] + 0x329b, dccg_regs[id].DWB_GAMUT_REMAPA_C33_C34 = ctx->dcn_reg_offsets[2] + 0x329c, dccg_regs[id].DWB_GAMUT_REMAPB_C11_C12 = ctx->dcn_reg_offsets[2] + 0x329d, dccg_regs[id].DWB_GAMUT_REMAPB_C13_C14 = ctx->dcn_reg_offsets[2] + 0x329e, dccg_regs[id].DWB_GAMUT_REMAPB_C21_C22 = ctx->dcn_reg_offsets[2] + 0x329f, dccg_regs[id].DWB_GAMUT_REMAPB_C23_C24 = ctx->dcn_reg_offsets[2] + 0x32a0, dccg_regs[id].DWB_GAMUT_REMAPB_C31_C32 = ctx->dcn_reg_offsets[2] + 0x32a1, dccg_regs[id].DWB_GAMUT_REMAPB_C33_C34 = ctx->dcn_reg_offsets[2] + 0x32a2, dccg_regs[id].DWB_OGAM_CONTROL = ctx->dcn_reg_offsets[2] + 0x32a3, dccg_regs[id].DWB_OGAM_LUT_INDEX = ctx->dcn_reg_offsets[2] + 0x32a4, dccg_regs[id].DWB_OGAM_LUT_DATA = ctx->dcn_reg_offsets[2] + 0x32a5, dccg_regs[id].DWB_OGAM_LUT_CONTROL = ctx->dcn_reg_offsets[2] + 0x32a6, dccg_regs[id].DWB_OGAM_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32a7, dccg_regs[id].DWB_OGAM_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32a8, dccg_regs[id].DWB_OGAM_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32a9, dccg_regs[id].DWB_OGAM_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32aa, dccg_regs[id].DWB_OGAM_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ab, dccg_regs[id].DWB_OGAM_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32ac, dccg_regs[id].DWB_OGAM_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32ad, dccg_regs[id].DWB_OGAM_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32ae, dccg_regs[id].DWB_OGAM_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32af, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x32b0, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x32b1, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x32b2, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x32b3, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x32b4, dccg_regs[id].DWB_OGAM_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x32b5, dccg_regs[id].DWB_OGAM_RAMA_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x32b6, dccg_regs[id].DWB_OGAM_RAMA_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x32b7, dccg_regs[id].DWB_OGAM_RAMA_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x32b8, dccg_regs[id].DWB_OGAM_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x32b9, dccg_regs[id].DWB_OGAM_RAMA_REGION_2_3 = ctx->dcn_reg_offsets[2] + 0x32ba, dccg_regs[id].DWB_OGAM_RAMA_REGION_4_5 = ctx->dcn_reg_offsets[2] + 0x32bb, dccg_regs[id].DWB_OGAM_RAMA_REGION_6_7 = ctx->dcn_reg_offsets[2] + 0x32bc, dccg_regs[id].DWB_OGAM_RAMA_REGION_8_9 = ctx->dcn_reg_offsets[2] + 0x32bd, dccg_regs[id].DWB_OGAM_RAMA_REGION_10_11 = ctx->dcn_reg_offsets[2] + 0x32be, dccg_regs[id].DWB_OGAM_RAMA_REGION_12_13 = ctx->dcn_reg_offsets[2] + 0x32bf, dccg_regs[id].DWB_OGAM_RAMA_REGION_14_15 = ctx->dcn_reg_offsets[2] + 0x32c0, dccg_regs[id].DWB_OGAM_RAMA_REGION_16_17 = ctx->dcn_reg_offsets[2] + 0x32c1, dccg_regs[id].DWB_OGAM_RAMA_REGION_18_19 = ctx->dcn_reg_offsets[2] + 0x32c2, dccg_regs[id].DWB_OGAM_RAMA_REGION_20_21 = ctx->dcn_reg_offsets[2] + 0x32c3, dccg_regs[id].DWB_OGAM_RAMA_REGION_22_23 = ctx->dcn_reg_offsets[2] + 0x32c4, dccg_regs[id].DWB_OGAM_RAMA_REGION_24_25 = ctx->dcn_reg_offsets[2] + 0x32c5, dccg_regs[id].DWB_OGAM_RAMA_REGION_26_27 = ctx->dcn_reg_offsets[2] + 0x32c6, dccg_regs[id].DWB_OGAM_RAMA_REGION_28_29 = ctx->dcn_reg_offsets[2] + 0x32c7, dccg_regs[id].DWB_OGAM_RAMA_REGION_30_31 = ctx->dcn_reg_offsets[2] + 0x32c8, dccg_regs[id].DWB_OGAM_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x32c9, dccg_regs[id].DWB_OGAM_RAMB_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ca, dccg_regs[id].DWB_OGAM_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32cb, dccg_regs[id].DWB_OGAM_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32cc, dccg_regs[id].DWB_OGAM_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32cd, dccg_regs[id].DWB_OGAM_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ce, dccg_regs[id].DWB_OGAM_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32cf, dccg_regs[id].DWB_OGAM_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32d0, dccg_regs[id].DWB_OGAM_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32d1, dccg_regs[id].DWB_OGAM_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32d2, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x32d3, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x32d4, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x32d5, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x32d6, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x32d7, dccg_regs[id].DWB_OGAM_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x32d8, dccg_regs[id].DWB_OGAM_RAMB_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x32d9, dccg_regs[id].DWB_OGAM_RAMB_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x32da, dccg_regs[id].DWB_OGAM_RAMB_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x32db, dccg_regs[id].DWB_OGAM_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x32dc, dccg_regs[id].DWB_OGAM_RAMB_REGION_2_3 = ctx->dcn_reg_offsets[2] + 0x32dd, dccg_regs[id].DWB_OGAM_RAMB_REGION_4_5 = ctx->dcn_reg_offsets[2] + 0x32de, dccg_regs[id].DWB_OGAM_RAMB_REGION_6_7 = ctx->dcn_reg_offsets[2] + 0x32df, dccg_regs[id].DWB_OGAM_RAMB_REGION_8_9 = ctx->dcn_reg_offsets[2] + 0x32e0, dccg_regs[id].DWB_OGAM_RAMB_REGION_10_11 = ctx->dcn_reg_offsets[2] + 0x32e1, dccg_regs[id].DWB_OGAM_RAMB_REGION_12_13 = ctx->dcn_reg_offsets[2] + 0x32e2, dccg_regs[id].DWB_OGAM_RAMB_REGION_14_15 = ctx->dcn_reg_offsets[2] + 0x32e3, dccg_regs[id].DWB_OGAM_RAMB_REGION_16_17 = ctx->dcn_reg_offsets[2] + 0x32e4, dccg_regs[id].DWB_OGAM_RAMB_REGION_18_19 = ctx->dcn_reg_offsets[2] + 0x32e5, dccg_regs[id].DWB_OGAM_RAMB_REGION_20_21 = ctx->dcn_reg_offsets[2] + 0x32e6, dccg_regs[id].DWB_OGAM_RAMB_REGION_22_23 = ctx->dcn_reg_offsets[2] + 0x32e7, dccg_regs[id].DWB_OGAM_RAMB_REGION_24_25 = ctx->dcn_reg_offsets[2] + 0x32e8, dccg_regs[id].DWB_OGAM_RAMB_REGION_26_27 = ctx->dcn_reg_offsets[2] + 0x32e9, dccg_regs[id].DWB_OGAM_RAMB_REGION_28_29 = ctx->dcn_reg_offsets[2] + 0x32ea, dccg_regs[id].DWB_OGAM_RAMB_REGION_30_31 = ctx->dcn_reg_offsets[2] + 0x32eb, dccg_regs[id].DWB_OGAM_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x32ec ) |
410 | |
411 | static struct dcn30_dwbc_registers dwbc30_regs[1]; |
412 | |
413 | static const struct dcn30_dwbc_shift dwbc30_shift = { |
414 | DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT).DWB_ENABLE = 0x0, .DISPCLK_R_DWB_GATE_DIS = 0x4, .DISPCLK_G_DWB_GATE_DIS = 0x8, .DWB_TEST_CLK_SEL = 0xc, .DWB_OGAM_LUT_MEM_PWR_FORCE = 0x10, .DWB_OGAM_LUT_MEM_PWR_DIS = 0x12, .DWB_OGAM_LUT_MEM_PWR_STATE = 0x14, .FC_FRAME_CAPTURE_EN = 0x0, .FC_FRAME_CAPTURE_RATE = 0x4, .FC_WINDOW_CROP_EN = 0x8, .FC_EYE_SELECTION = 0xc, .FC_STEREO_EYE_POLARITY = 0x10, .FC_NEW_CONTENT = 0x14, .FC_FRAME_CAPTURE_EN_CURRENT = 0x1f, .FC_FIRST_PIXEL_DELAY_COUNT = 0x0, .FC_WINDOW_START_X = 0x0, .FC_WINDOW_START_Y = 0x10, .FC_WINDOW_WIDTH = 0x0, .FC_WINDOW_HEIGHT = 0x10, .FC_SOURCE_WIDTH = 0x0, .FC_SOURCE_HEIGHT = 0x10, .DWB_UPDATE_LOCK = 0x0, .DWB_UPDATE_PENDING = 0x4, .DWB_CRC_EN = 0x0, .DWB_CRC_CONT_EN = 0x4, .DWB_CRC_SRC_SEL = 0x8, .DWB_CRC_RED_MASK = 0x0, .DWB_CRC_GREEN_MASK = 0x10, .DWB_CRC_BLUE_MASK = 0x0, .DWB_CRC_A_MASK = 0x10, .DWB_CRC_SIG_RED = 0x0, .DWB_CRC_SIG_GREEN = 0x10, .DWB_CRC_SIG_BLUE = 0x0, . DWB_CRC_SIG_A = 0x10, .OUT_FORMAT = 0x0, .OUT_DENORM = 0x4, . OUT_MAX = 0x8, .OUT_MIN = 0x14, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = 0x0, .DWB_MMHUBBUB_MAX_BACKPRESSURE = 0x0, .DWB_HOST_READ_RATE_CONTROL = 0x0, .DWB_SOFT_RESET = 0x0, .DWB_HDR_MULT_COEF = 0x0, .DWB_GAMUT_REMAP_MODE = 0x0, .DWB_GAMUT_REMAP_MODE_CURRENT = 0x18, .DWB_GAMUT_REMAP_COEF_FORMAT = 0x0, .DWB_GAMUT_REMAPA_C11 = 0x0, .DWB_GAMUT_REMAPA_C12 = 0x10 , .DWB_GAMUT_REMAPA_C13 = 0x0, .DWB_GAMUT_REMAPA_C14 = 0x10, . DWB_GAMUT_REMAPA_C21 = 0x0, .DWB_GAMUT_REMAPA_C22 = 0x10, .DWB_GAMUT_REMAPA_C23 = 0x0, .DWB_GAMUT_REMAPA_C24 = 0x10, .DWB_GAMUT_REMAPA_C31 = 0x0, .DWB_GAMUT_REMAPA_C32 = 0x10, .DWB_GAMUT_REMAPA_C33 = 0x0 , .DWB_GAMUT_REMAPA_C34 = 0x10, .DWB_GAMUT_REMAPB_C11 = 0x0, . DWB_GAMUT_REMAPB_C12 = 0x10, .DWB_GAMUT_REMAPB_C13 = 0x0, .DWB_GAMUT_REMAPB_C14 = 0x10, .DWB_GAMUT_REMAPB_C21 = 0x0, .DWB_GAMUT_REMAPB_C22 = 0x10, .DWB_GAMUT_REMAPB_C23 = 0x0, .DWB_GAMUT_REMAPB_C24 = 0x10 , .DWB_GAMUT_REMAPB_C31 = 0x0, .DWB_GAMUT_REMAPB_C32 = 0x10, . DWB_GAMUT_REMAPB_C33 = 0x0, .DWB_GAMUT_REMAPB_C34 = 0x10, .DWB_OGAM_MODE = 0x0, .DWB_OGAM_SELECT = 0x4, .DWB_OGAM_PWL_DISABLE = 0x8, . DWB_OGAM_MODE_CURRENT = 0x18, .DWB_OGAM_SELECT_CURRENT = 0x1c , .DWB_OGAM_LUT_INDEX = 0x0, .DWB_OGAM_LUT_DATA = 0x0, .DWB_OGAM_LUT_WRITE_COLOR_MASK = 0x0, .DWB_OGAM_LUT_READ_COLOR_SEL = 0x4, .DWB_OGAM_LUT_READ_DBG = 0x8, .DWB_OGAM_LUT_HOST_SEL = 0xc, .DWB_OGAM_LUT_CONFIG_MODE = 0x10, .DWB_OGAM_RAMA_EXP_REGION_START_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G = 0x10, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x10, .DWB_OGAM_RAMA_OFFSET_B = 0x0, .DWB_OGAM_RAMA_OFFSET_G = 0x0, .DWB_OGAM_RAMA_OFFSET_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION_START_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x10, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x10, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x10, .DWB_OGAM_RAMB_OFFSET_B = 0x0, .DWB_OGAM_RAMB_OFFSET_G = 0x0, .DWB_OGAM_RAMB_OFFSET_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x1c |
415 | }; |
416 | |
417 | static const struct dcn30_dwbc_mask dwbc30_mask = { |
418 | DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK).DWB_ENABLE = 0x00000001L, .DISPCLK_R_DWB_GATE_DIS = 0x00000010L , .DISPCLK_G_DWB_GATE_DIS = 0x00000100L, .DWB_TEST_CLK_SEL = 0x00003000L , .DWB_OGAM_LUT_MEM_PWR_FORCE = 0x00030000L, .DWB_OGAM_LUT_MEM_PWR_DIS = 0x00040000L, .DWB_OGAM_LUT_MEM_PWR_STATE = 0x00300000L, .FC_FRAME_CAPTURE_EN = 0x00000001L, .FC_FRAME_CAPTURE_RATE = 0x00000030L, .FC_WINDOW_CROP_EN = 0x00000100L, .FC_EYE_SELECTION = 0x00003000L, .FC_STEREO_EYE_POLARITY = 0x00010000L, .FC_NEW_CONTENT = 0x00100000L, .FC_FRAME_CAPTURE_EN_CURRENT = 0x80000000L, .FC_FIRST_PIXEL_DELAY_COUNT = 0x00000FFFL, .FC_WINDOW_START_X = 0x00001FFFL, .FC_WINDOW_START_Y = 0x1FFF0000L, .FC_WINDOW_WIDTH = 0x00000FFFL, .FC_WINDOW_HEIGHT = 0x0FFF0000L, .FC_SOURCE_WIDTH = 0x00007FFFL, .FC_SOURCE_HEIGHT = 0x7FFF0000L, .DWB_UPDATE_LOCK = 0x00000001L, .DWB_UPDATE_PENDING = 0x00000010L, .DWB_CRC_EN = 0x00000001L, .DWB_CRC_CONT_EN = 0x00000010L, .DWB_CRC_SRC_SEL = 0x00000300L, .DWB_CRC_RED_MASK = 0x0000FFFFL, .DWB_CRC_GREEN_MASK = 0xFFFF0000L, .DWB_CRC_BLUE_MASK = 0x0000FFFFL, .DWB_CRC_A_MASK = 0xFFFF0000L, .DWB_CRC_SIG_RED = 0x0000FFFFL, .DWB_CRC_SIG_GREEN = 0xFFFF0000L, .DWB_CRC_SIG_BLUE = 0x0000FFFFL, .DWB_CRC_SIG_A = 0xFFFF0000L, .OUT_FORMAT = 0x00000003L, .OUT_DENORM = 0x00000030L , .OUT_MAX = 0x0003FF00L, .OUT_MIN = 0x3FF00000L, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = 0x00000001L, .DWB_MMHUBBUB_MAX_BACKPRESSURE = 0x0000FFFFL, .DWB_HOST_READ_RATE_CONTROL = 0x000000FFL, .DWB_SOFT_RESET = 0x00000001L, .DWB_HDR_MULT_COEF = 0x0007FFFFL, .DWB_GAMUT_REMAP_MODE = 0x00000003L, .DWB_GAMUT_REMAP_MODE_CURRENT = 0x03000000L, . DWB_GAMUT_REMAP_COEF_FORMAT = 0x00000001L, .DWB_GAMUT_REMAPA_C11 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C12 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C13 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C14 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C21 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C22 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C23 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C24 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C31 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C32 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C33 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C34 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C11 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C12 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C13 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C14 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C21 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C22 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C23 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C24 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C31 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C32 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C33 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C34 = 0xFFFF0000L, .DWB_OGAM_MODE = 0x00000003L, .DWB_OGAM_SELECT = 0x00000010L, .DWB_OGAM_PWL_DISABLE = 0x00000100L, .DWB_OGAM_MODE_CURRENT = 0x03000000L, .DWB_OGAM_SELECT_CURRENT = 0x10000000L, .DWB_OGAM_LUT_INDEX = 0x000001FFL, .DWB_OGAM_LUT_DATA = 0x0003FFFFL, .DWB_OGAM_LUT_WRITE_COLOR_MASK = 0x00000007L, .DWB_OGAM_LUT_READ_COLOR_SEL = 0x00000030L, .DWB_OGAM_LUT_READ_DBG = 0x00000100L, .DWB_OGAM_LUT_HOST_SEL = 0x00001000L, .DWB_OGAM_LUT_CONFIG_MODE = 0x00010000L, .DWB_OGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .DWB_OGAM_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x07F00000L , .DWB_OGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_G = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_START_BASE_R = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_G = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_END_G = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G = 0xFFFF0000L, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_R = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R = 0xFFFF0000L, .DWB_OGAM_RAMA_OFFSET_B = 0x0007FFFFL, .DWB_OGAM_RAMA_OFFSET_G = 0x0007FFFFL, .DWB_OGAM_RAMA_OFFSET_R = 0x0007FFFFL, .DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .DWB_OGAM_RAMB_EXP_REGION_START_G = 0x0003FFFFL , .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .DWB_OGAM_RAMB_EXP_REGION_START_R = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L , .DWB_OGAM_RAMB_EXP_REGION_START_BASE_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_G = 0x0003FFFFL , .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_R = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0003FFFFL , .DWB_OGAM_RAMB_EXP_REGION_END_BASE_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B = 0xFFFF0000L , .DWB_OGAM_RAMB_EXP_REGION_END_BASE_G = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_G = 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G = 0xFFFF0000L , .DWB_OGAM_RAMB_EXP_REGION_END_BASE_R = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_R = 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R = 0xFFFF0000L , .DWB_OGAM_RAMB_OFFSET_B = 0x0007FFFFL, .DWB_OGAM_RAMB_OFFSET_G = 0x0007FFFFL, .DWB_OGAM_RAMB_OFFSET_R = 0x0007FFFFL, .DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x70000000L |
419 | }; |
420 | |
421 | #define mcif_wb_regs_dcn3_init(id)( dccg_regs[id].MCIF_WB_BUFMGR_SW_CONTROL = ctx->dcn_reg_offsets [2] + 0x0272, dccg_regs[id].MCIF_WB_BUFMGR_STATUS = ctx->dcn_reg_offsets [2] + 0x0274, dccg_regs[id].MCIF_WB_BUF_PITCH = ctx->dcn_reg_offsets [2] + 0x0275, dccg_regs[id].MCIF_WB_BUF_1_STATUS = ctx->dcn_reg_offsets [2] + 0x0276, dccg_regs[id].MCIF_WB_BUF_1_STATUS2 = ctx->dcn_reg_offsets [2] + 0x0277, dccg_regs[id].MCIF_WB_BUF_2_STATUS = ctx->dcn_reg_offsets [2] + 0x0278, dccg_regs[id].MCIF_WB_BUF_2_STATUS2 = ctx->dcn_reg_offsets [2] + 0x0279, dccg_regs[id].MCIF_WB_BUF_3_STATUS = ctx->dcn_reg_offsets [2] + 0x027a, dccg_regs[id].MCIF_WB_BUF_3_STATUS2 = ctx->dcn_reg_offsets [2] + 0x027b, dccg_regs[id].MCIF_WB_BUF_4_STATUS = ctx->dcn_reg_offsets [2] + 0x027c, dccg_regs[id].MCIF_WB_BUF_4_STATUS2 = ctx->dcn_reg_offsets [2] + 0x027d, dccg_regs[id].MCIF_WB_ARBITRATION_CONTROL = ctx ->dcn_reg_offsets[2] + 0x027e, dccg_regs[id].MCIF_WB_SCLK_CHANGE = ctx->dcn_reg_offsets[2] + 0x027f, dccg_regs[id].MCIF_WB_TEST_DEBUG_INDEX = ctx->dcn_reg_offsets[2] + 0x0280, dccg_regs[id].MCIF_WB_TEST_DEBUG_DATA = ctx->dcn_reg_offsets[2] + 0x0281, dccg_regs[id].MCIF_WB_BUF_1_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x0282, dccg_regs[id].MCIF_WB_BUF_1_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0284, dccg_regs[id].MCIF_WB_BUF_2_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x0286, dccg_regs[id].MCIF_WB_BUF_2_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0288, dccg_regs[id].MCIF_WB_BUF_3_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x028a, dccg_regs[id].MCIF_WB_BUF_3_ADDR_C = ctx->dcn_reg_offsets[2] + 0x028c, dccg_regs[id].MCIF_WB_BUF_4_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x028e, dccg_regs[id].MCIF_WB_BUF_4_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0290, dccg_regs[id].MCIF_WB_BUFMGR_VCE_CONTROL = ctx->dcn_reg_offsets[2] + 0x0292, dccg_regs[id].MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = ctx->dcn_reg_offsets[2] + 0x02aa, dccg_regs[id].MCIF_WB_NB_PSTATE_CONTROL = ctx->dcn_reg_offsets[2] + 0x0293, dccg_regs[id].MCIF_WB_WATERMARK = ctx->dcn_reg_offsets[2] + 0x02ab, dccg_regs[id].MCIF_WB_CLOCK_GATER_CONTROL = ctx->dcn_reg_offsets[2] + 0x0294, dccg_regs[id].MCIF_WB_SELF_REFRESH_CONTROL = ctx->dcn_reg_offsets[2] + 0x0296, dccg_regs[id].MULTI_LEVEL_QOS_CTRL = ctx->dcn_reg_offsets[2] + 0x0297, dccg_regs[id].MCIF_WB_SECURITY_LEVEL = ctx->dcn_reg_offsets[2] + 0x0298, dccg_regs[id].MCIF_WB_BUF_LUMA_SIZE = ctx->dcn_reg_offsets[2] + 0x0299, dccg_regs[id].MCIF_WB_BUF_CHROMA_SIZE = ctx->dcn_reg_offsets[2] + 0x029a, dccg_regs[id].MCIF_WB_BUF_1_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029b, dccg_regs[id].MCIF_WB_BUF_1_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x029c, dccg_regs[id].MCIF_WB_BUF_2_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029d, dccg_regs[id].MCIF_WB_BUF_2_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x029e, dccg_regs[id].MCIF_WB_BUF_3_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029f, dccg_regs[id].MCIF_WB_BUF_3_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x02a0, dccg_regs[id].MCIF_WB_BUF_4_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x02a1, dccg_regs[id].MCIF_WB_BUF_4_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x02a2, dccg_regs[id].MCIF_WB_BUF_1_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a3, dccg_regs[id].MCIF_WB_BUF_2_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a4, dccg_regs[id].MCIF_WB_BUF_3_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a5, dccg_regs[id].MCIF_WB_BUF_4_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a6, dccg_regs[id].MMHUBBUB_MEM_PWR_CNTL = ctx->dcn_reg_offsets[2] + 0x0340, dccg_regs[id].MMHUBBUB_WARMUP_ADDR_REGION = ctx->dcn_reg_offsets[2] + 0x02b0, dccg_regs[id].MMHUBBUB_WARMUP_BASE_ADDR_HIGH = ctx->dcn_reg_offsets[2] + 0x02af, dccg_regs[id].MMHUBBUB_WARMUP_BASE_ADDR_LOW = ctx->dcn_reg_offsets[2] + 0x02ae, dccg_regs[id].MMHUBBUB_WARMUP_CONTROL_STATUS = ctx->dcn_reg_offsets[2] + 0x02ad )\ |
422 | MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)( dccg_regs[id].MCIF_WB_BUFMGR_SW_CONTROL = ctx->dcn_reg_offsets [2] + 0x0272, dccg_regs[id].MCIF_WB_BUFMGR_STATUS = ctx->dcn_reg_offsets [2] + 0x0274, dccg_regs[id].MCIF_WB_BUF_PITCH = ctx->dcn_reg_offsets [2] + 0x0275, dccg_regs[id].MCIF_WB_BUF_1_STATUS = ctx->dcn_reg_offsets [2] + 0x0276, dccg_regs[id].MCIF_WB_BUF_1_STATUS2 = ctx->dcn_reg_offsets [2] + 0x0277, dccg_regs[id].MCIF_WB_BUF_2_STATUS = ctx->dcn_reg_offsets [2] + 0x0278, dccg_regs[id].MCIF_WB_BUF_2_STATUS2 = ctx->dcn_reg_offsets [2] + 0x0279, dccg_regs[id].MCIF_WB_BUF_3_STATUS = ctx->dcn_reg_offsets [2] + 0x027a, dccg_regs[id].MCIF_WB_BUF_3_STATUS2 = ctx->dcn_reg_offsets [2] + 0x027b, dccg_regs[id].MCIF_WB_BUF_4_STATUS = ctx->dcn_reg_offsets [2] + 0x027c, dccg_regs[id].MCIF_WB_BUF_4_STATUS2 = ctx->dcn_reg_offsets [2] + 0x027d, dccg_regs[id].MCIF_WB_ARBITRATION_CONTROL = ctx ->dcn_reg_offsets[2] + 0x027e, dccg_regs[id].MCIF_WB_SCLK_CHANGE = ctx->dcn_reg_offsets[2] + 0x027f, dccg_regs[id].MCIF_WB_TEST_DEBUG_INDEX = ctx->dcn_reg_offsets[2] + 0x0280, dccg_regs[id].MCIF_WB_TEST_DEBUG_DATA = ctx->dcn_reg_offsets[2] + 0x0281, dccg_regs[id].MCIF_WB_BUF_1_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x0282, dccg_regs[id].MCIF_WB_BUF_1_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0284, dccg_regs[id].MCIF_WB_BUF_2_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x0286, dccg_regs[id].MCIF_WB_BUF_2_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0288, dccg_regs[id].MCIF_WB_BUF_3_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x028a, dccg_regs[id].MCIF_WB_BUF_3_ADDR_C = ctx->dcn_reg_offsets[2] + 0x028c, dccg_regs[id].MCIF_WB_BUF_4_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x028e, dccg_regs[id].MCIF_WB_BUF_4_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0290, dccg_regs[id].MCIF_WB_BUFMGR_VCE_CONTROL = ctx->dcn_reg_offsets[2] + 0x0292, dccg_regs[id].MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = ctx->dcn_reg_offsets[2] + 0x02aa, dccg_regs[id].MCIF_WB_NB_PSTATE_CONTROL = ctx->dcn_reg_offsets[2] + 0x0293, dccg_regs[id].MCIF_WB_WATERMARK = ctx->dcn_reg_offsets[2] + 0x02ab, dccg_regs[id].MCIF_WB_CLOCK_GATER_CONTROL = ctx->dcn_reg_offsets[2] + 0x0294, dccg_regs[id].MCIF_WB_SELF_REFRESH_CONTROL = ctx->dcn_reg_offsets[2] + 0x0296, dccg_regs[id].MULTI_LEVEL_QOS_CTRL = ctx->dcn_reg_offsets[2] + 0x0297, dccg_regs[id].MCIF_WB_SECURITY_LEVEL = ctx->dcn_reg_offsets[2] + 0x0298, dccg_regs[id].MCIF_WB_BUF_LUMA_SIZE = ctx->dcn_reg_offsets[2] + 0x0299, dccg_regs[id].MCIF_WB_BUF_CHROMA_SIZE = ctx->dcn_reg_offsets[2] + 0x029a, dccg_regs[id].MCIF_WB_BUF_1_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029b, dccg_regs[id].MCIF_WB_BUF_1_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x029c, dccg_regs[id].MCIF_WB_BUF_2_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029d, dccg_regs[id].MCIF_WB_BUF_2_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x029e, dccg_regs[id].MCIF_WB_BUF_3_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029f, dccg_regs[id].MCIF_WB_BUF_3_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x02a0, dccg_regs[id].MCIF_WB_BUF_4_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x02a1, dccg_regs[id].MCIF_WB_BUF_4_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x02a2, dccg_regs[id].MCIF_WB_BUF_1_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a3, dccg_regs[id].MCIF_WB_BUF_2_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a4, dccg_regs[id].MCIF_WB_BUF_3_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a5, dccg_regs[id].MCIF_WB_BUF_4_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a6, dccg_regs[id].MMHUBBUB_MEM_PWR_CNTL = ctx->dcn_reg_offsets[2] + 0x0340, dccg_regs[id].MMHUBBUB_WARMUP_ADDR_REGION = ctx->dcn_reg_offsets[2] + 0x02b0, dccg_regs[id].MMHUBBUB_WARMUP_BASE_ADDR_HIGH = ctx->dcn_reg_offsets[2] + 0x02af, dccg_regs[id].MMHUBBUB_WARMUP_BASE_ADDR_LOW = ctx->dcn_reg_offsets[2] + 0x02ae, dccg_regs[id].MMHUBBUB_WARMUP_CONTROL_STATUS = ctx->dcn_reg_offsets[2] + 0x02ad ) |
423 | |
424 | static struct dcn30_mmhubbub_registers mcif_wb30_regs[1]; |
425 | |
426 | static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { |
427 | MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT).MCIF_WB_BUFMGR_ENABLE = 0x0, .MCIF_WB_BUFMGR_SW_INT_EN = 0x4 , .MCIF_WB_BUFMGR_SW_INT_ACK = 0x5, .MCIF_WB_BUFMGR_SW_SLICE_INT_EN = 0x6, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN = 0x7, .MCIF_WB_BUFMGR_SW_LOCK = 0x8, .MCIF_WB_BUF_ADDR_FENCE_EN = 0x18, .MCIF_WB_BUFMGR_SW_INT_STATUS = 0x1, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS = 0x2, .MCIF_WB_BUFMGR_CUR_BUF = 0x4, .MCIF_WB_BUFMGR_BUFTAG = 0x8, .MCIF_WB_BUFMGR_CUR_LINE_L = 0xc, .MCIF_WB_BUFMGR_NEXT_BUF = 0x1c, .MCIF_WB_BUF_LUMA_PITCH = 0x8, .MCIF_WB_BUF_CHROMA_PITCH = 0x18, .MCIF_WB_BUF_1_ACTIVE = 0x0, .MCIF_WB_BUF_1_SW_LOCKED = 0x1, .MCIF_WB_BUF_1_OVERFLOW = 0x3, .MCIF_WB_BUF_1_DISABLE = 0x4, .MCIF_WB_BUF_1_MODE = 0x5 , .MCIF_WB_BUF_1_BUFTAG = 0x8, .MCIF_WB_BUF_1_NXT_BUF = 0xc, . MCIF_WB_BUF_1_CUR_LINE_L = 0x10, .MCIF_WB_BUF_1_NEW_CONTENT = 0xd, .MCIF_WB_BUF_1_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_1_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_1_TMZ = 0x10, .MCIF_WB_BUF_1_Y_OVERRUN = 0x11, .MCIF_WB_BUF_1_C_OVERRUN = 0x12, .MCIF_WB_BUF_2_ACTIVE = 0x0, .MCIF_WB_BUF_2_SW_LOCKED = 0x1, .MCIF_WB_BUF_2_OVERFLOW = 0x3, .MCIF_WB_BUF_2_DISABLE = 0x4, .MCIF_WB_BUF_2_MODE = 0x5 , .MCIF_WB_BUF_2_BUFTAG = 0x8, .MCIF_WB_BUF_2_NXT_BUF = 0xc, . MCIF_WB_BUF_2_CUR_LINE_L = 0x10, .MCIF_WB_BUF_2_NEW_CONTENT = 0xd, .MCIF_WB_BUF_2_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_2_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_2_TMZ = 0x10, .MCIF_WB_BUF_2_Y_OVERRUN = 0x11, .MCIF_WB_BUF_2_C_OVERRUN = 0x12, .MCIF_WB_BUF_3_ACTIVE = 0x0, .MCIF_WB_BUF_3_SW_LOCKED = 0x1, .MCIF_WB_BUF_3_OVERFLOW = 0x3, .MCIF_WB_BUF_3_DISABLE = 0x4, .MCIF_WB_BUF_3_MODE = 0x5 , .MCIF_WB_BUF_3_BUFTAG = 0x8, .MCIF_WB_BUF_3_NXT_BUF = 0xc, . MCIF_WB_BUF_3_CUR_LINE_L = 0x10, .MCIF_WB_BUF_3_NEW_CONTENT = 0xd, .MCIF_WB_BUF_3_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_3_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_3_TMZ = 0x10, .MCIF_WB_BUF_3_Y_OVERRUN = 0x11, .MCIF_WB_BUF_3_C_OVERRUN = 0x12, .MCIF_WB_BUF_4_ACTIVE = 0x0, .MCIF_WB_BUF_4_SW_LOCKED = 0x1, .MCIF_WB_BUF_4_OVERFLOW = 0x3, .MCIF_WB_BUF_4_DISABLE = 0x4, .MCIF_WB_BUF_4_MODE = 0x5 , .MCIF_WB_BUF_4_BUFTAG = 0x8, .MCIF_WB_BUF_4_NXT_BUF = 0xc, . MCIF_WB_BUF_4_CUR_LINE_L = 0x10, .MCIF_WB_BUF_4_NEW_CONTENT = 0xd, .MCIF_WB_BUF_4_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_4_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_4_TMZ = 0x10, .MCIF_WB_BUF_4_Y_OVERRUN = 0x11, .MCIF_WB_BUF_4_C_OVERRUN = 0x12, .MCIF_WB_CLIENT_ARBITRATION_SLICE = 0x0, .MCIF_WB_TIME_PER_PIXEL = 0x14, .WM_CHANGE_ACK_FORCE_ON = 0x0, .MCIF_WB_TEST_DEBUG_INDEX = 0x0, .MCIF_WB_TEST_DEBUG_DATA = 0x0, .MCIF_WB_BUF_1_ADDR_Y = 0x0, .MCIF_WB_BUF_1_ADDR_C = 0x0 , .MCIF_WB_BUF_2_ADDR_Y = 0x0, .MCIF_WB_BUF_2_ADDR_C = 0x0, . MCIF_WB_BUF_3_ADDR_Y = 0x0, .MCIF_WB_BUF_3_ADDR_C = 0x0, .MCIF_WB_BUF_4_ADDR_Y = 0x0, .MCIF_WB_BUF_4_ADDR_C = 0x0, .MCIF_WB_BUFMGR_SLICE_SIZE = 0x10, .NB_PSTATE_CHANGE_REFRESH_WATERMARK = 0x0, .NB_PSTATE_CHANGE_WATERMARK_MASK = 0x18, .NB_PSTATE_CHANGE_FORCE_ON = 0x1, .MCIF_WB_CLI_WATERMARK = 0x0, .MCIF_WB_CLI_WATERMARK_MASK = 0x18, .MCIF_WB_CLI_CLOCK_GATER_OVERRIDE = 0x0, .PERFRAME_SELF_REFRESH = 0x1, .MAX_SCALED_TIME_TO_URGENT = 0x0, .MCIF_WB_SECURITY_LEVEL = 0x0, .MCIF_WB_BUF_LUMA_SIZE = 0x0, .MCIF_WB_BUF_CHROMA_SIZE = 0x0, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_1_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_1_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_2_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_2_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_3_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_3_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_4_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_4_RESOLUTION_HEIGHT = 0x10, .MMHUBBUB_WARMUP_ADDR_REGION = 0x0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x0, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0x0, .MMHUBBUB_WARMUP_EN = 0x0, .MMHUBBUB_WARMUP_SW_INT_EN = 0x4, .MMHUBBUB_WARMUP_SW_INT_STATUS = 0x5, .MMHUBBUB_WARMUP_SW_INT_ACK = 0x6, .MMHUBBUB_WARMUP_INC_ADDR = 0x8 |
428 | }; |
429 | |
430 | static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { |
431 | MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK).MCIF_WB_BUFMGR_ENABLE = 0x00000001L, .MCIF_WB_BUFMGR_SW_INT_EN = 0x00000010L, .MCIF_WB_BUFMGR_SW_INT_ACK = 0x00000020L, .MCIF_WB_BUFMGR_SW_SLICE_INT_EN = 0x00000040L, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN = 0x00000080L , .MCIF_WB_BUFMGR_SW_LOCK = 0x00000F00L, .MCIF_WB_BUF_ADDR_FENCE_EN = 0x01000000L, .MCIF_WB_BUFMGR_SW_INT_STATUS = 0x00000002L, . MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS = 0x00000004L, .MCIF_WB_BUFMGR_CUR_BUF = 0x00000070L, .MCIF_WB_BUFMGR_BUFTAG = 0x00000F00L, .MCIF_WB_BUFMGR_CUR_LINE_L = 0x01FFF000L, .MCIF_WB_BUFMGR_NEXT_BUF = 0x70000000L, .MCIF_WB_BUF_LUMA_PITCH = 0x0000FF00L, .MCIF_WB_BUF_CHROMA_PITCH = 0xFF000000L, .MCIF_WB_BUF_1_ACTIVE = 0x00000001L, .MCIF_WB_BUF_1_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_1_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_1_DISABLE = 0x00000010L, .MCIF_WB_BUF_1_MODE = 0x000000E0L, .MCIF_WB_BUF_1_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_1_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_1_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_1_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_1_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_1_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_1_TMZ = 0x00010000L, .MCIF_WB_BUF_1_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_1_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_2_ACTIVE = 0x00000001L, .MCIF_WB_BUF_2_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_2_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_2_DISABLE = 0x00000010L, .MCIF_WB_BUF_2_MODE = 0x000000E0L, .MCIF_WB_BUF_2_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_2_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_2_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_2_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_2_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_2_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_2_TMZ = 0x00010000L, .MCIF_WB_BUF_2_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_2_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_3_ACTIVE = 0x00000001L, .MCIF_WB_BUF_3_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_3_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_3_DISABLE = 0x00000010L, .MCIF_WB_BUF_3_MODE = 0x000000E0L, .MCIF_WB_BUF_3_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_3_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_3_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_3_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_3_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_3_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_3_TMZ = 0x00010000L, .MCIF_WB_BUF_3_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_3_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_4_ACTIVE = 0x00000001L, .MCIF_WB_BUF_4_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_4_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_4_DISABLE = 0x00000010L, .MCIF_WB_BUF_4_MODE = 0x000000E0L, .MCIF_WB_BUF_4_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_4_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_4_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_4_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_4_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_4_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_4_TMZ = 0x00010000L, .MCIF_WB_BUF_4_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_4_C_OVERRUN = 0x00040000L, .MCIF_WB_CLIENT_ARBITRATION_SLICE = 0x00000003L, .MCIF_WB_TIME_PER_PIXEL = 0xFFF00000L, .WM_CHANGE_ACK_FORCE_ON = 0x00000001L, .MCIF_WB_TEST_DEBUG_INDEX = 0x000000FFL, .MCIF_WB_TEST_DEBUG_DATA = 0xFFFFFFFFL, .MCIF_WB_BUF_1_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_1_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_2_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_2_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_3_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_3_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_4_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_4_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUFMGR_SLICE_SIZE = 0x1FFF0000L, .NB_PSTATE_CHANGE_REFRESH_WATERMARK = 0x001FFFFFL, .NB_PSTATE_CHANGE_WATERMARK_MASK = 0x07000000L , .NB_PSTATE_CHANGE_FORCE_ON = 0x00000002L, .MCIF_WB_CLI_WATERMARK = 0x001FFFFFL, .MCIF_WB_CLI_WATERMARK_MASK = 0x07000000L, .MCIF_WB_CLI_CLOCK_GATER_OVERRIDE = 0x00000001L, .PERFRAME_SELF_REFRESH = 0x00000002L, .MAX_SCALED_TIME_TO_URGENT = 0x003FFFFFL, .MCIF_WB_SECURITY_LEVEL = 0x00000007L, .MCIF_WB_BUF_LUMA_SIZE = 0x000FFFFFL, .MCIF_WB_BUF_CHROMA_SIZE = 0x000FFFFFL, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_1_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_1_RESOLUTION_HEIGHT = 0x1FFF0000L , .MCIF_WB_BUF_2_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_2_RESOLUTION_HEIGHT = 0x1FFF0000L, .MCIF_WB_BUF_3_RESOLUTION_WIDTH = 0x00001FFFL , .MCIF_WB_BUF_3_RESOLUTION_HEIGHT = 0x1FFF0000L, .MCIF_WB_BUF_4_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_4_RESOLUTION_HEIGHT = 0x1FFF0000L , .MMHUBBUB_WARMUP_ADDR_REGION = 0x07FFFFFFL, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x000007FFL, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0xFFFFFFFFL, .MMHUBBUB_WARMUP_EN = 0x00000001L, .MMHUBBUB_WARMUP_SW_INT_EN = 0x00000010L, .MMHUBBUB_WARMUP_SW_INT_STATUS = 0x00000020L, .MMHUBBUB_WARMUP_SW_INT_ACK = 0x00000040L, .MMHUBBUB_WARMUP_INC_ADDR = 0x03FFFF00L |
432 | }; |
433 | |
434 | #define dsc_regsDCN20_init(id)( dccg_regs[id].DSC_TOP_CONTROL = ctx->dcn_reg_offsets[regDSC_TOPid_DSC_TOP_CONTROL_BASE_IDX ] + regDSC_TOPid_DSC_TOP_CONTROL, dccg_regs[id].DSC_DEBUG_CONTROL = ctx->dcn_reg_offsets[regDSC_TOPid_DSC_DEBUG_CONTROL_BASE_IDX ] + regDSC_TOPid_DSC_DEBUG_CONTROL, dccg_regs[id].DSCC_CONFIG0 = ctx->dcn_reg_offsets[regDSCCid_DSCC_CONFIG0_BASE_IDX] + regDSCCid_DSCC_CONFIG0, dccg_regs[id].DSCC_CONFIG1 = ctx-> dcn_reg_offsets[regDSCCid_DSCC_CONFIG1_BASE_IDX] + regDSCCid_DSCC_CONFIG1 , dccg_regs[id].DSCC_STATUS = ctx->dcn_reg_offsets[regDSCCid_DSCC_STATUS_BASE_IDX ] + regDSCCid_DSCC_STATUS, dccg_regs[id].DSCC_INTERRUPT_CONTROL_STATUS = ctx->dcn_reg_offsets[regDSCCid_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX ] + regDSCCid_DSCC_INTERRUPT_CONTROL_STATUS, dccg_regs[id].DSCC_PPS_CONFIG0 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG0_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG0, dccg_regs[id].DSCC_PPS_CONFIG1 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG1_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG1, dccg_regs[id].DSCC_PPS_CONFIG2 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG2_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG2, dccg_regs[id].DSCC_PPS_CONFIG3 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG3_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG3, dccg_regs[id].DSCC_PPS_CONFIG4 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG4_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG4, dccg_regs[id].DSCC_PPS_CONFIG5 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG5_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG5, dccg_regs[id].DSCC_PPS_CONFIG6 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG6_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG6, dccg_regs[id].DSCC_PPS_CONFIG7 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG7_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG7, dccg_regs[id].DSCC_PPS_CONFIG8 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG8_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG8, dccg_regs[id].DSCC_PPS_CONFIG9 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG9_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG9, dccg_regs[id].DSCC_PPS_CONFIG10 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG10_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG10, dccg_regs[id].DSCC_PPS_CONFIG11 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG11_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG11, dccg_regs[id].DSCC_PPS_CONFIG12 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG12_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG12, dccg_regs[id].DSCC_PPS_CONFIG13 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG13_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG13, dccg_regs[id].DSCC_PPS_CONFIG14 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG14_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG14, dccg_regs[id].DSCC_PPS_CONFIG15 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG15_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG15, dccg_regs[id].DSCC_PPS_CONFIG16 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG16_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG16, dccg_regs[id].DSCC_PPS_CONFIG17 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG17_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG17, dccg_regs[id].DSCC_PPS_CONFIG18 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG18_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG18, dccg_regs[id].DSCC_PPS_CONFIG19 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG19_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG19, dccg_regs[id].DSCC_PPS_CONFIG20 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG20_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG20, dccg_regs[id].DSCC_PPS_CONFIG21 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG21_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG21, dccg_regs[id].DSCC_PPS_CONFIG22 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG22_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG22, dccg_regs[id].DSCC_MEM_POWER_CONTROL = ctx->dcn_reg_offsets[regDSCCid_DSCC_MEM_POWER_CONTROL_BASE_IDX ] + regDSCCid_DSCC_MEM_POWER_CONTROL, dccg_regs[id].DSCC_R_Y_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[regDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX ] + regDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER, dccg_regs[id].DSCC_R_Y_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[regDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX ] + regDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER, dccg_regs[id].DSCC_G_CB_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[regDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX ] + regDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER, dccg_regs[id].DSCC_G_CB_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[regDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX ] + regDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER, dccg_regs[id].DSCC_B_CR_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[regDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX ] + regDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER, dccg_regs[id].DSCC_B_CR_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[regDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX ] + regDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER, dccg_regs[id].DSCC_MAX_ABS_ERROR0 = ctx->dcn_reg_offsets[regDSCCid_DSCC_MAX_ABS_ERROR0_BASE_IDX ] + regDSCCid_DSCC_MAX_ABS_ERROR0, dccg_regs[id].DSCC_MAX_ABS_ERROR1 = ctx->dcn_reg_offsets[regDSCCid_DSCC_MAX_ABS_ERROR1_BASE_IDX ] + regDSCCid_DSCC_MAX_ABS_ERROR1, dccg_regs[id].DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[regDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX] + regDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL , dccg_regs[id].DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = ctx-> dcn_reg_offsets[regDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX] + regDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL , dccg_regs[id].DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[regDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCCIF_CONFIG0 = ctx->dcn_reg_offsets[regDSCCIFid_DSCCIF_CONFIG0_BASE_IDX ] + regDSCCIFid_DSCCIF_CONFIG0, dccg_regs[id].DSCCIF_CONFIG1 = ctx->dcn_reg_offsets[regDSCCIFid_DSCCIF_CONFIG1_BASE_IDX] + regDSCCIFid_DSCCIF_CONFIG1, dccg_regs[id].DSCRM_DSC_FORWARD_CONFIG = ctx->dcn_reg_offsets[regDSCRMid_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX ] + regDSCRMid_DSCRM_DSC_FORWARD_CONFIG )\ |
435 | DSC_REG_LIST_DCN20_RI(id)( dccg_regs[id].DSC_TOP_CONTROL = ctx->dcn_reg_offsets[regDSC_TOPid_DSC_TOP_CONTROL_BASE_IDX ] + regDSC_TOPid_DSC_TOP_CONTROL, dccg_regs[id].DSC_DEBUG_CONTROL = ctx->dcn_reg_offsets[regDSC_TOPid_DSC_DEBUG_CONTROL_BASE_IDX ] + regDSC_TOPid_DSC_DEBUG_CONTROL, dccg_regs[id].DSCC_CONFIG0 = ctx->dcn_reg_offsets[regDSCCid_DSCC_CONFIG0_BASE_IDX] + regDSCCid_DSCC_CONFIG0, dccg_regs[id].DSCC_CONFIG1 = ctx-> dcn_reg_offsets[regDSCCid_DSCC_CONFIG1_BASE_IDX] + regDSCCid_DSCC_CONFIG1 , dccg_regs[id].DSCC_STATUS = ctx->dcn_reg_offsets[regDSCCid_DSCC_STATUS_BASE_IDX ] + regDSCCid_DSCC_STATUS, dccg_regs[id].DSCC_INTERRUPT_CONTROL_STATUS = ctx->dcn_reg_offsets[regDSCCid_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX ] + regDSCCid_DSCC_INTERRUPT_CONTROL_STATUS, dccg_regs[id].DSCC_PPS_CONFIG0 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG0_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG0, dccg_regs[id].DSCC_PPS_CONFIG1 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG1_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG1, dccg_regs[id].DSCC_PPS_CONFIG2 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG2_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG2, dccg_regs[id].DSCC_PPS_CONFIG3 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG3_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG3, dccg_regs[id].DSCC_PPS_CONFIG4 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG4_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG4, dccg_regs[id].DSCC_PPS_CONFIG5 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG5_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG5, dccg_regs[id].DSCC_PPS_CONFIG6 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG6_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG6, dccg_regs[id].DSCC_PPS_CONFIG7 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG7_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG7, dccg_regs[id].DSCC_PPS_CONFIG8 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG8_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG8, dccg_regs[id].DSCC_PPS_CONFIG9 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG9_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG9, dccg_regs[id].DSCC_PPS_CONFIG10 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG10_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG10, dccg_regs[id].DSCC_PPS_CONFIG11 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG11_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG11, dccg_regs[id].DSCC_PPS_CONFIG12 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG12_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG12, dccg_regs[id].DSCC_PPS_CONFIG13 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG13_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG13, dccg_regs[id].DSCC_PPS_CONFIG14 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG14_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG14, dccg_regs[id].DSCC_PPS_CONFIG15 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG15_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG15, dccg_regs[id].DSCC_PPS_CONFIG16 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG16_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG16, dccg_regs[id].DSCC_PPS_CONFIG17 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG17_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG17, dccg_regs[id].DSCC_PPS_CONFIG18 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG18_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG18, dccg_regs[id].DSCC_PPS_CONFIG19 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG19_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG19, dccg_regs[id].DSCC_PPS_CONFIG20 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG20_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG20, dccg_regs[id].DSCC_PPS_CONFIG21 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG21_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG21, dccg_regs[id].DSCC_PPS_CONFIG22 = ctx->dcn_reg_offsets[regDSCCid_DSCC_PPS_CONFIG22_BASE_IDX ] + regDSCCid_DSCC_PPS_CONFIG22, dccg_regs[id].DSCC_MEM_POWER_CONTROL = ctx->dcn_reg_offsets[regDSCCid_DSCC_MEM_POWER_CONTROL_BASE_IDX ] + regDSCCid_DSCC_MEM_POWER_CONTROL, dccg_regs[id].DSCC_R_Y_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[regDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX ] + regDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER, dccg_regs[id].DSCC_R_Y_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[regDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX ] + regDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER, dccg_regs[id].DSCC_G_CB_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[regDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX ] + regDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER, dccg_regs[id].DSCC_G_CB_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[regDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX ] + regDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER, dccg_regs[id].DSCC_B_CR_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[regDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX ] + regDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER, dccg_regs[id].DSCC_B_CR_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[regDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX ] + regDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER, dccg_regs[id].DSCC_MAX_ABS_ERROR0 = ctx->dcn_reg_offsets[regDSCCid_DSCC_MAX_ABS_ERROR0_BASE_IDX ] + regDSCCid_DSCC_MAX_ABS_ERROR0, dccg_regs[id].DSCC_MAX_ABS_ERROR1 = ctx->dcn_reg_offsets[regDSCCid_DSCC_MAX_ABS_ERROR1_BASE_IDX ] + regDSCCid_DSCC_MAX_ABS_ERROR1, dccg_regs[id].DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[regDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX] + regDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL , dccg_regs[id].DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = ctx-> dcn_reg_offsets[regDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX] + regDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL , dccg_regs[id].DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[regDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets [regDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX ] + regDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, dccg_regs [id].DSCCIF_CONFIG0 = ctx->dcn_reg_offsets[regDSCCIFid_DSCCIF_CONFIG0_BASE_IDX ] + regDSCCIFid_DSCCIF_CONFIG0, dccg_regs[id].DSCCIF_CONFIG1 = ctx->dcn_reg_offsets[regDSCCIFid_DSCCIF_CONFIG1_BASE_IDX] + regDSCCIFid_DSCCIF_CONFIG1, dccg_regs[id].DSCRM_DSC_FORWARD_CONFIG = ctx->dcn_reg_offsets[regDSCRMid_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX ] + regDSCRMid_DSCRM_DSC_FORWARD_CONFIG ) |
436 | |
437 | static struct dcn20_dsc_registers dsc_regs[4]; |
438 | |
439 | static const struct dcn20_dsc_shift dsc_shift = { |
440 | DSC_REG_LIST_SH_MASK_DCN20(__SHIFT).DSC_CLOCK_EN = 0x0, .DSC_DISPCLK_R_GATE_DIS = 0x4, .DSC_DSCCLK_R_GATE_DIS = 0x8, .DSC_DBG_EN = 0x0, .ICH_RESET_AT_END_OF_LINE = 0x0, . NUMBER_OF_SLICES_PER_LINE = 0x4, .ALTERNATE_ICH_ENCODING_EN = 0x8, .NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION = 0x10, .DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE = 0x0, .DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x0, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED = 0x0, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED = 0x1, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED = 0x2, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED = 0x3, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED = 0x4, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED = 0x5, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED = 0x6, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED = 0x7, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED = 0x8, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED = 0x9 , .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED = 0xa, . DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED = 0xb, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN = 0x10, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN = 0x11, . DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN = 0x12, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN = 0x13, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN = 0x14, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN = 0x15, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN = 0x16, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN = 0x17, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN = 0x18 , .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN = 0x19, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN = 0x1a, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN = 0x1b, .DSC_VERSION_MINOR = 0x0, .DSC_VERSION_MAJOR = 0x4, . PPS_IDENTIFIER = 0x8, .LINEBUF_DEPTH = 0x18, .DSCC_PPS_CONFIG0__BITS_PER_COMPONENT = 0x1c, .BITS_PER_PIXEL = 0x0, .VBR_ENABLE = 0xa, .SIMPLE_422 = 0xb, .CONVERT_RGB = 0xc, .BLOCK_PRED_ENABLE = 0xd, .NATIVE_422 = 0xe, .NATIVE_420 = 0xf, .CHUNK_SIZE = 0x10, .PIC_WIDTH = 0x0 , .PIC_HEIGHT = 0x10, .SLICE_WIDTH = 0x0, .SLICE_HEIGHT = 0x10 , .INITIAL_XMIT_DELAY = 0x0, .INITIAL_DEC_DELAY = 0x10, .INITIAL_SCALE_VALUE = 0x0, .SCALE_INCREMENT_INTERVAL = 0x10, .SCALE_DECREMENT_INTERVAL = 0x0, .FIRST_LINE_BPG_OFFSET = 0x10, .SECOND_LINE_BPG_OFFSET = 0x18, .NFL_BPG_OFFSET = 0x0, .SLICE_BPG_OFFSET = 0x10, .NSL_BPG_OFFSET = 0x0, .SECOND_LINE_OFFSET_ADJ = 0x10, .INITIAL_OFFSET = 0x0 , .FINAL_OFFSET = 0x10, .FLATNESS_MIN_QP = 0x0, .FLATNESS_MAX_QP = 0x8, .RC_MODEL_SIZE = 0x10, .RC_EDGE_FACTOR = 0x0, .RC_QUANT_INCR_LIMIT0 = 0x8, .RC_QUANT_INCR_LIMIT1 = 0x10, .RC_TGT_OFFSET_LO = 0x18 , .RC_TGT_OFFSET_HI = 0x1c, .RC_BUF_THRESH0 = 0x0, .RC_BUF_THRESH1 = 0x8, .RC_BUF_THRESH2 = 0x10, .RC_BUF_THRESH3 = 0x18, .RC_BUF_THRESH4 = 0x0, .RC_BUF_THRESH5 = 0x8, .RC_BUF_THRESH6 = 0x10, .RC_BUF_THRESH7 = 0x18, .RC_BUF_THRESH8 = 0x0, .RC_BUF_THRESH9 = 0x8, .RC_BUF_THRESH10 = 0x10, .RC_BUF_THRESH11 = 0x18, .RC_BUF_THRESH12 = 0x0, .RC_BUF_THRESH13 = 0x8, .RANGE_MIN_QP0 = 0x10, .RANGE_MAX_QP0 = 0x15, .RANGE_BPG_OFFSET0 = 0x1a, .RANGE_MIN_QP1 = 0x0, .RANGE_MAX_QP1 = 0x5, .RANGE_BPG_OFFSET1 = 0xa, .RANGE_MIN_QP2 = 0x10, .RANGE_MAX_QP2 = 0x15, .RANGE_BPG_OFFSET2 = 0x1a, .RANGE_MIN_QP3 = 0x0, .RANGE_MAX_QP3 = 0x5, .RANGE_BPG_OFFSET3 = 0xa, .RANGE_MIN_QP4 = 0x10, .RANGE_MAX_QP4 = 0x15, .RANGE_BPG_OFFSET4 = 0x1a, .RANGE_MIN_QP5 = 0x0, .RANGE_MAX_QP5 = 0x5, .RANGE_BPG_OFFSET5 = 0xa, .RANGE_MIN_QP6 = 0x10, .RANGE_MAX_QP6 = 0x15, .RANGE_BPG_OFFSET6 = 0x1a, .RANGE_MIN_QP7 = 0x0, .RANGE_MAX_QP7 = 0x5, .RANGE_BPG_OFFSET7 = 0xa, .RANGE_MIN_QP8 = 0x10, .RANGE_MAX_QP8 = 0x15, .RANGE_BPG_OFFSET8 = 0x1a, .RANGE_MIN_QP9 = 0x0, .RANGE_MAX_QP9 = 0x5, .RANGE_BPG_OFFSET9 = 0xa, .RANGE_MIN_QP10 = 0x10, .RANGE_MAX_QP10 = 0x15, .RANGE_BPG_OFFSET10 = 0x1a, .RANGE_MIN_QP11 = 0x0, .RANGE_MAX_QP11 = 0x5, .RANGE_BPG_OFFSET11 = 0xa, .RANGE_MIN_QP12 = 0x10, .RANGE_MAX_QP12 = 0x15, .RANGE_BPG_OFFSET12 = 0x1a, .RANGE_MIN_QP13 = 0x0, .RANGE_MAX_QP13 = 0x5, .RANGE_BPG_OFFSET13 = 0xa, .RANGE_MIN_QP14 = 0x10, .RANGE_MAX_QP14 = 0x15, .RANGE_BPG_OFFSET14 = 0x1a, .DSCC_DEFAULT_MEM_LOW_POWER_STATE = 0x0, .DSCC_MEM_PWR_FORCE = 0x4, .DSCC_MEM_PWR_DIS = 0x8, .DSCC_MEM_PWR_STATE = 0x10, . DSCC_NATIVE_422_MEM_PWR_FORCE = 0x14, .DSCC_NATIVE_422_MEM_PWR_DIS = 0x18, .DSCC_NATIVE_422_MEM_PWR_STATE = 0x1c, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x0, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x0, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x0, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x0, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x0, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x0, .DSCC_R_Y_MAX_ABS_ERROR = 0x0, .DSCC_G_CB_MAX_ABS_ERROR = 0x10, .DSCC_B_CR_MAX_ABS_ERROR = 0x0, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x0, . DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x0, . INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN = 0x0, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN = 0x4, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS = 0x8, .INPUT_PIXEL_FORMAT = 0xc, .DSCCIF_CONFIG0__BITS_PER_COMPONENT = 0x10, .DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x18, .PIC_WIDTH = 0x0, .PIC_HEIGHT = 0x10, .DSCRM_DSC_FORWARD_EN = 0x0, .DSCRM_DSC_OPP_PIPE_SOURCE = 0x4 |
441 | }; |
442 | |
443 | static const struct dcn20_dsc_mask dsc_mask = { |
444 | DSC_REG_LIST_SH_MASK_DCN20(_MASK).DSC_CLOCK_EN = 0x00000001L, .DSC_DISPCLK_R_GATE_DIS = 0x00000010L , .DSC_DSCCLK_R_GATE_DIS = 0x00000100L, .DSC_DBG_EN = 0x00000001L , .ICH_RESET_AT_END_OF_LINE = 0x0000000FL, .NUMBER_OF_SLICES_PER_LINE = 0x00000030L, .ALTERNATE_ICH_ENCODING_EN = 0x00000100L, .NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION = 0xFFFF0000L, .DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE = 0x0003FFFFL , .DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x00000001L, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED = 0x00000001L, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED = 0x00000002L , .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED = 0x00000004L, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED = 0x00000008L, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED = 0x00000010L , .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED = 0x00000020L, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED = 0x00000040L, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED = 0x00000080L , .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED = 0x00000100L , .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED = 0x00000200L , .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED = 0x00000400L , .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED = 0x00000800L , .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN = 0x00010000L, . DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN = 0x00020000L, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN = 0x00040000L, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN = 0x00080000L, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN = 0x00100000L , .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN = 0x00200000L, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN = 0x00400000L, . DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN = 0x00800000L, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN = 0x01000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN = 0x02000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN = 0x04000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN = 0x08000000L, .DSC_VERSION_MINOR = 0x0000000FL, .DSC_VERSION_MAJOR = 0x000000F0L, .PPS_IDENTIFIER = 0x0000FF00L, .LINEBUF_DEPTH = 0x0F000000L, .DSCC_PPS_CONFIG0__BITS_PER_COMPONENT = 0xF0000000L , .BITS_PER_PIXEL = 0x000003FFL, .VBR_ENABLE = 0x00000400L, . SIMPLE_422 = 0x00000800L, .CONVERT_RGB = 0x00001000L, .BLOCK_PRED_ENABLE = 0x00002000L, .NATIVE_422 = 0x00004000L, .NATIVE_420 = 0x00008000L , .CHUNK_SIZE = 0xFFFF0000L, .PIC_WIDTH = 0x0000FFFFL, .PIC_HEIGHT = 0xFFFF0000L, .SLICE_WIDTH = 0x0000FFFFL, .SLICE_HEIGHT = 0xFFFF0000L , .INITIAL_XMIT_DELAY = 0x000003FFL, .INITIAL_DEC_DELAY = 0xFFFF0000L , .INITIAL_SCALE_VALUE = 0x0000003FL, .SCALE_INCREMENT_INTERVAL = 0xFFFF0000L, .SCALE_DECREMENT_INTERVAL = 0x00000FFFL, .FIRST_LINE_BPG_OFFSET = 0x001F0000L, .SECOND_LINE_BPG_OFFSET = 0x1F000000L, .NFL_BPG_OFFSET = 0x0000FFFFL, .SLICE_BPG_OFFSET = 0xFFFF0000L, .NSL_BPG_OFFSET = 0x0000FFFFL, .SECOND_LINE_OFFSET_ADJ = 0xFFFF0000L, .INITIAL_OFFSET = 0x0000FFFFL, .FINAL_OFFSET = 0xFFFF0000L, .FLATNESS_MIN_QP = 0x0000001FL, .FLATNESS_MAX_QP = 0x00001F00L, .RC_MODEL_SIZE = 0xFFFF0000L, .RC_EDGE_FACTOR = 0x0000000FL, .RC_QUANT_INCR_LIMIT0 = 0x00001F00L, .RC_QUANT_INCR_LIMIT1 = 0x001F0000L, .RC_TGT_OFFSET_LO = 0x0F000000L, .RC_TGT_OFFSET_HI = 0xF0000000L, .RC_BUF_THRESH0 = 0x000000FFL, .RC_BUF_THRESH1 = 0x0000FF00L, .RC_BUF_THRESH2 = 0x00FF0000L, .RC_BUF_THRESH3 = 0xFF000000L, .RC_BUF_THRESH4 = 0x000000FFL, .RC_BUF_THRESH5 = 0x0000FF00L, .RC_BUF_THRESH6 = 0x00FF0000L, .RC_BUF_THRESH7 = 0xFF000000L, .RC_BUF_THRESH8 = 0x000000FFL, .RC_BUF_THRESH9 = 0x0000FF00L, .RC_BUF_THRESH10 = 0x00FF0000L, .RC_BUF_THRESH11 = 0xFF000000L, .RC_BUF_THRESH12 = 0x000000FFL, .RC_BUF_THRESH13 = 0x0000FF00L, .RANGE_MIN_QP0 = 0x001F0000L, .RANGE_MAX_QP0 = 0x03E00000L, .RANGE_BPG_OFFSET0 = 0xFC000000L, .RANGE_MIN_QP1 = 0x0000001FL, .RANGE_MAX_QP1 = 0x000003E0L, .RANGE_BPG_OFFSET1 = 0x0000FC00L, .RANGE_MIN_QP2 = 0x001F0000L, .RANGE_MAX_QP2 = 0x03E00000L, .RANGE_BPG_OFFSET2 = 0xFC000000L, .RANGE_MIN_QP3 = 0x0000001FL, .RANGE_MAX_QP3 = 0x000003E0L, .RANGE_BPG_OFFSET3 = 0x0000FC00L, .RANGE_MIN_QP4 = 0x001F0000L, .RANGE_MAX_QP4 = 0x03E00000L, .RANGE_BPG_OFFSET4 = 0xFC000000L, .RANGE_MIN_QP5 = 0x0000001FL, .RANGE_MAX_QP5 = 0x000003E0L, .RANGE_BPG_OFFSET5 = 0x0000FC00L, .RANGE_MIN_QP6 = 0x001F0000L, .RANGE_MAX_QP6 = 0x03E00000L, .RANGE_BPG_OFFSET6 = 0xFC000000L, .RANGE_MIN_QP7 = 0x0000001FL, .RANGE_MAX_QP7 = 0x000003E0L, .RANGE_BPG_OFFSET7 = 0x0000FC00L, .RANGE_MIN_QP8 = 0x001F0000L, .RANGE_MAX_QP8 = 0x03E00000L, .RANGE_BPG_OFFSET8 = 0xFC000000L, .RANGE_MIN_QP9 = 0x0000001FL, .RANGE_MAX_QP9 = 0x000003E0L, .RANGE_BPG_OFFSET9 = 0x0000FC00L, .RANGE_MIN_QP10 = 0x001F0000L, .RANGE_MAX_QP10 = 0x03E00000L, .RANGE_BPG_OFFSET10 = 0xFC000000L, .RANGE_MIN_QP11 = 0x0000001FL, .RANGE_MAX_QP11 = 0x000003E0L, .RANGE_BPG_OFFSET11 = 0x0000FC00L, .RANGE_MIN_QP12 = 0x001F0000L, .RANGE_MAX_QP12 = 0x03E00000L, .RANGE_BPG_OFFSET12 = 0xFC000000L, .RANGE_MIN_QP13 = 0x0000001FL, .RANGE_MAX_QP13 = 0x000003E0L, .RANGE_BPG_OFFSET13 = 0x0000FC00L, .RANGE_MIN_QP14 = 0x001F0000L, .RANGE_MAX_QP14 = 0x03E00000L, .RANGE_BPG_OFFSET14 = 0xFC000000L, .DSCC_DEFAULT_MEM_LOW_POWER_STATE = 0x00000003L , .DSCC_MEM_PWR_FORCE = 0x00000030L, .DSCC_MEM_PWR_DIS = 0x00000100L , .DSCC_MEM_PWR_STATE = 0x00030000L, .DSCC_NATIVE_422_MEM_PWR_FORCE = 0x00300000L, .DSCC_NATIVE_422_MEM_PWR_DIS = 0x01000000L, . DSCC_NATIVE_422_MEM_PWR_STATE = 0x30000000L, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, . DSCC_G_CB_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, .DSCC_R_Y_MAX_ABS_ERROR = 0x0000FFFFL, .DSCC_G_CB_MAX_ABS_ERROR = 0xFFFF0000L, .DSCC_B_CR_MAX_ABS_ERROR = 0x0000FFFFL, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x0003FFFFL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x0003FFFFL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN = 0x00000001L, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN = 0x00000010L, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS = 0x00000100L , .INPUT_PIXEL_FORMAT = 0x00007000L, .DSCCIF_CONFIG0__BITS_PER_COMPONENT = 0x000F0000L, .DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x01000000L , .PIC_WIDTH = 0x0000FFFFL, .PIC_HEIGHT = 0xFFFF0000L, .DSCRM_DSC_FORWARD_EN = 0x00000001L, .DSCRM_DSC_OPP_PIPE_SOURCE = 0x00000070L |
445 | }; |
446 | |
447 | static struct dcn30_mpc_registers mpc_regs; |
448 | |
449 | #define dcn_mpc_regs_init()( ( dccg_regs.MPCC_TOP_SEL[0] = ctx->dcn_reg_offsets[3] + 0x0000 , dccg_regs.MPCC_BOT_SEL[0] = ctx->dcn_reg_offsets[3] + 0x0001 , dccg_regs.MPCC_CONTROL[0] = ctx->dcn_reg_offsets[3] + 0x0003 , dccg_regs.MPCC_STATUS[0] = ctx->dcn_reg_offsets[3] + 0x000e , dccg_regs.MPCC_OPP_ID[0] = ctx->dcn_reg_offsets[3] + 0x0002 , dccg_regs.MPCC_BG_G_Y[0] = ctx->dcn_reg_offsets[3] + 0x000b , dccg_regs.MPCC_BG_R_CR[0] = ctx->dcn_reg_offsets[3] + 0x000a , dccg_regs.MPCC_BG_B_CB[0] = ctx->dcn_reg_offsets[3] + 0x000c , dccg_regs.MPCC_SM_CONTROL[0] = ctx->dcn_reg_offsets[3] + 0x0004, dccg_regs.MPCC_UPDATE_LOCK_SEL[0] = ctx->dcn_reg_offsets [3] + 0x0005 ), dccg_regs.MPCC_TOP_GAIN[0] = ctx->dcn_reg_offsets [3] + 0x0006, dccg_regs.MPCC_BOT_GAIN_INSIDE[0] = ctx->dcn_reg_offsets [3] + 0x0007, dccg_regs.MPCC_BOT_GAIN_OUTSIDE[0] = ctx->dcn_reg_offsets [3] + 0x0008, dccg_regs.MPCC_MEM_PWR_CTRL[0] = ctx->dcn_reg_offsets [3] + 0x000d, dccg_regs.MPCC_OGAM_LUT_INDEX[0] = ctx->dcn_reg_offsets [3] + 0x00a9, dccg_regs.MPCC_OGAM_LUT_DATA[0] = ctx->dcn_reg_offsets [3] + 0x00aa, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT[0] = ctx ->dcn_reg_offsets[3] + 0x00f2, dccg_regs.MPCC_GAMUT_REMAP_MODE [0] = ctx->dcn_reg_offsets[3] + 0x00f3, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [0] = ctx->dcn_reg_offsets[3] + 0x00f4, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [0] = ctx->dcn_reg_offsets[3] + 0x00f9, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [0] = ctx->dcn_reg_offsets[3] + 0x00fa, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [0] = ctx->dcn_reg_offsets[3] + 0x00ff, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00ac, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00ad, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00ae, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00af, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00b0, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00b1, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x00b5, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x00b6, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x00b7, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x00b8, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x00b9, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x00ba, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x00be, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x00ce, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x00bb, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x00bc, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x00bd, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00b2, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00b3, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00b4, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00cf, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d0, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d1, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00d2, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d3, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d4, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x00d8, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x00d9, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x00da, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x00db, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x00dc, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x00dd, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x00e1, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x00f1, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x00de, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x00df, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x00e0, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00d5, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d6, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d7, dccg_regs.MPCC_OGAM_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x00a8, dccg_regs.MPCC_OGAM_LUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x00ab ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0009, dccg_regs.MPCC_MCM_SHAPER_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0453, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x0454, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x0455, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x0456, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [0] = ctx->dcn_reg_offsets[3] + 0x0457, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [0] = ctx->dcn_reg_offsets[3] + 0x0458, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x0459, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x045a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [0] = ctx->dcn_reg_offsets[3] + 0x045b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x045c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x045d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x045e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x045f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0460, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0461, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x0462, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x0463, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x0464, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x0465, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x0466, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x0467, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x0468, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x0469, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x046a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x046b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x046c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x046d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x046e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x046f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x0470, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x0471, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x0472, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0473, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0474, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0475, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0476, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0477, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0478, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x0479, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x047a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x047b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x047c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x047d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x047e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x047f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x0480, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x0481, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x0482, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x0483, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x0484, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x0485, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x0486, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x0487, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x0488, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x0489, dccg_regs.MPCC_MCM_3DLUT_MODE [0] = ctx->dcn_reg_offsets[3] + 0x048a, dccg_regs.MPCC_MCM_3DLUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x048b, dccg_regs.MPCC_MCM_3DLUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x048c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [0] = ctx->dcn_reg_offsets[3] + 0x048d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x048e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [0] = ctx->dcn_reg_offsets[3] + 0x048f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x0490, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x0491, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x0492, dccg_regs.MPCC_MCM_1DLUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0493, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x0494, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x0495, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0496, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0497, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0498, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0499, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x049a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x049b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x049c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x049d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x049e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x049f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x04a0, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x04a1, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x04a2, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x04a3, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x04a4, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x04a5, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x04a6, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x04a7, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x04a8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x04a9, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x04aa, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x04ab, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x04ac, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x04ad, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x04ae, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x04af, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x04b0, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x04b1, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x04b2, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x04b3, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x04b4, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x04b5, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x04b6, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x04b7, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x04b8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x04b9, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04ba, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04bb, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04bc, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04bd, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04be, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04bf, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04c0, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04c1, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04c2, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x04c3, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x04c4, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x04c5, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x04c6, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x04c7, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x04c8, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x04c9, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x04ca, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x04cb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x04cc, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x04cd, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x04ce, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x04cf, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x04d0, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x04d1, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x04d2, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x04d3, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x04d4, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x04d5, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x04d6, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x04d7, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x04d8, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x04d9, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x04da, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x04db, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x04dc, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [0] = ctx->dcn_reg_offsets[3] + 0x04dd, ( ( dccg_regs.MPCC_TOP_SEL [1] = ctx->dcn_reg_offsets[3] + 0x0015, dccg_regs.MPCC_BOT_SEL [1] = ctx->dcn_reg_offsets[3] + 0x0016, dccg_regs.MPCC_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0018, dccg_regs.MPCC_STATUS [1] = ctx->dcn_reg_offsets[3] + 0x0023, dccg_regs.MPCC_OPP_ID [1] = ctx->dcn_reg_offsets[3] + 0x0017, dccg_regs.MPCC_BG_G_Y [1] = ctx->dcn_reg_offsets[3] + 0x0020, dccg_regs.MPCC_BG_R_CR [1] = ctx->dcn_reg_offsets[3] + 0x001f, dccg_regs.MPCC_BG_B_CB [1] = ctx->dcn_reg_offsets[3] + 0x0021, dccg_regs.MPCC_SM_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0019, dccg_regs.MPCC_UPDATE_LOCK_SEL [1] = ctx->dcn_reg_offsets[3] + 0x001a ), dccg_regs.MPCC_TOP_GAIN [1] = ctx->dcn_reg_offsets[3] + 0x001b, dccg_regs.MPCC_BOT_GAIN_INSIDE [1] = ctx->dcn_reg_offsets[3] + 0x001c, dccg_regs.MPCC_BOT_GAIN_OUTSIDE [1] = ctx->dcn_reg_offsets[3] + 0x001d, dccg_regs.MPCC_MEM_PWR_CTRL [1] = ctx->dcn_reg_offsets[3] + 0x0022, dccg_regs.MPCC_OGAM_LUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x0107, dccg_regs.MPCC_OGAM_LUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x0108, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT [1] = ctx->dcn_reg_offsets[3] + 0x0150, dccg_regs.MPCC_GAMUT_REMAP_MODE [1] = ctx->dcn_reg_offsets[3] + 0x0151, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [1] = ctx->dcn_reg_offsets[3] + 0x0152, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [1] = ctx->dcn_reg_offsets[3] + 0x0157, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [1] = ctx->dcn_reg_offsets[3] + 0x0158, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [1] = ctx->dcn_reg_offsets[3] + 0x015d, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x010a, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x010b, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x010c, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x010d, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x010e, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x010f, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0113, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0114, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0115, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0116, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0117, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0118, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x011c, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x012c, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0119, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x011a, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x011b, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0110, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0111, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0112, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x012d, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x012e, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x012f, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0130, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0131, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0132, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0136, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0137, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0138, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0139, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x013a, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x013b, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x013f, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x014f, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x013c, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x013d, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x013e, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0133, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0134, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0135, dccg_regs.MPCC_OGAM_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0106, dccg_regs.MPCC_OGAM_LUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0109 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x001e, dccg_regs.MPCC_MCM_SHAPER_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x04e3, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x04e4, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x04e5, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x04e6, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [1] = ctx->dcn_reg_offsets[3] + 0x04e7, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [1] = ctx->dcn_reg_offsets[3] + 0x04e8, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x04e9, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x04ea, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [1] = ctx->dcn_reg_offsets[3] + 0x04eb, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x04ec, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x04ed, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x04ee, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x04ef, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x04f0, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x04f1, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x04f2, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x04f3, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x04f4, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x04f5, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x04f6, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x04f7, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x04f8, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x04f9, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x04fa, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x04fb, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x04fc, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x04fd, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x04fe, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x04ff, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0500, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0501, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0502, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0503, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0504, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0505, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0506, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0507, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0508, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x0509, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x050a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x050b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x050c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x050d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x050e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x050f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0510, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0511, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0512, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0513, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0514, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0515, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0516, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0517, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0518, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0519, dccg_regs.MPCC_MCM_3DLUT_MODE [1] = ctx->dcn_reg_offsets[3] + 0x051a, dccg_regs.MPCC_MCM_3DLUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x051b, dccg_regs.MPCC_MCM_3DLUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x051c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [1] = ctx->dcn_reg_offsets[3] + 0x051d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x051e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [1] = ctx->dcn_reg_offsets[3] + 0x051f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x0520, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x0521, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0522, dccg_regs.MPCC_MCM_1DLUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0523, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x0524, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x0525, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0526, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0527, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0528, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0529, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x052a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x052b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x052c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x052d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x052e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x052f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0530, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0531, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0532, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0533, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0534, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0535, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0536, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x0537, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x0538, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x0539, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x053a, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x053b, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x053c, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x053d, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x053e, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x053f, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0540, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0541, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0542, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0543, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0544, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0545, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0546, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0547, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0548, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0549, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x054a, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x054b, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x054c, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x054d, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x054e, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x054f, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0550, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0551, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0552, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0553, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0554, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0555, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0556, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0557, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0558, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0559, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x055a, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x055b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x055c, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x055d, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x055e, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x055f, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x0560, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x0561, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x0562, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0563, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0564, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0565, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0566, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0567, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0568, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0569, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x056a, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x056b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x056c, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [1] = ctx->dcn_reg_offsets[3] + 0x056d, ( ( dccg_regs.MPCC_TOP_SEL [2] = ctx->dcn_reg_offsets[3] + 0x002a, dccg_regs.MPCC_BOT_SEL [2] = ctx->dcn_reg_offsets[3] + 0x002b, dccg_regs.MPCC_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x002d, dccg_regs.MPCC_STATUS [2] = ctx->dcn_reg_offsets[3] + 0x0038, dccg_regs.MPCC_OPP_ID [2] = ctx->dcn_reg_offsets[3] + 0x002c, dccg_regs.MPCC_BG_G_Y [2] = ctx->dcn_reg_offsets[3] + 0x0035, dccg_regs.MPCC_BG_R_CR [2] = ctx->dcn_reg_offsets[3] + 0x0034, dccg_regs.MPCC_BG_B_CB [2] = ctx->dcn_reg_offsets[3] + 0x0036, dccg_regs.MPCC_SM_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x002e, dccg_regs.MPCC_UPDATE_LOCK_SEL [2] = ctx->dcn_reg_offsets[3] + 0x002f ), dccg_regs.MPCC_TOP_GAIN [2] = ctx->dcn_reg_offsets[3] + 0x0030, dccg_regs.MPCC_BOT_GAIN_INSIDE [2] = ctx->dcn_reg_offsets[3] + 0x0031, dccg_regs.MPCC_BOT_GAIN_OUTSIDE [2] = ctx->dcn_reg_offsets[3] + 0x0032, dccg_regs.MPCC_MEM_PWR_CTRL [2] = ctx->dcn_reg_offsets[3] + 0x0037, dccg_regs.MPCC_OGAM_LUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x0165, dccg_regs.MPCC_OGAM_LUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x0166, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT [2] = ctx->dcn_reg_offsets[3] + 0x01ae, dccg_regs.MPCC_GAMUT_REMAP_MODE [2] = ctx->dcn_reg_offsets[3] + 0x01af, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [2] = ctx->dcn_reg_offsets[3] + 0x01b0, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [2] = ctx->dcn_reg_offsets[3] + 0x01b5, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [2] = ctx->dcn_reg_offsets[3] + 0x01b6, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [2] = ctx->dcn_reg_offsets[3] + 0x01bb, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0168, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0169, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x016a, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x016b, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x016c, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x016d, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x0171, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x0172, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x0173, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x0174, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x0175, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x0176, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x017a, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x018a, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x0177, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x0178, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x0179, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x016e, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x016f, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0170, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x018b, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x018c, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x018d, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x018e, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x018f, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0190, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x0194, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x0195, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x0196, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x0197, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x0198, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x0199, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x019d, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x01ad, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x019a, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x019b, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x019c, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0191, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0192, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0193, dccg_regs.MPCC_OGAM_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0164, dccg_regs.MPCC_OGAM_LUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0167 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0033, dccg_regs.MPCC_MCM_SHAPER_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0573, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x0574, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x0575, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x0576, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [2] = ctx->dcn_reg_offsets[3] + 0x0577, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [2] = ctx->dcn_reg_offsets[3] + 0x0578, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x0579, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x057a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [2] = ctx->dcn_reg_offsets[3] + 0x057b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x057c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x057d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x057e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x057f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0580, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0581, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x0582, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x0583, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x0584, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x0585, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x0586, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x0587, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x0588, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x0589, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x058a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x058b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x058c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x058d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x058e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x058f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x0590, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x0591, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x0592, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0593, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0594, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0595, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0596, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0597, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0598, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x0599, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x059a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x059b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x059c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x059d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x059e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x059f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05a0, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05a1, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05a2, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05a3, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05a4, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05a5, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05a6, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05a7, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05a8, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05a9, dccg_regs.MPCC_MCM_3DLUT_MODE [2] = ctx->dcn_reg_offsets[3] + 0x05aa, dccg_regs.MPCC_MCM_3DLUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x05ab, dccg_regs.MPCC_MCM_3DLUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x05ac, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [2] = ctx->dcn_reg_offsets[3] + 0x05ad, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05ae, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [2] = ctx->dcn_reg_offsets[3] + 0x05af, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05b0, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05b1, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05b2, dccg_regs.MPCC_MCM_1DLUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05b3, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x05b4, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x05b5, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05b6, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05b7, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05b8, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05b9, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05ba, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05bb, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05bc, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05bd, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05be, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05bf, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x05c0, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x05c1, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x05c2, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x05c3, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x05c4, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x05c5, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05c6, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05c7, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05c8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x05c9, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x05ca, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x05cb, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x05cc, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x05cd, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x05ce, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x05cf, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05d0, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05d1, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05d2, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05d3, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05d4, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05d5, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05d6, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05d7, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05d8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05d9, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05da, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05db, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05dc, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05dd, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05de, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05df, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05e0, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05e1, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05e2, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x05e3, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x05e4, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x05e5, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x05e6, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x05e7, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x05e8, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05e9, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05ea, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05eb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x05ec, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x05ed, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x05ee, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x05ef, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x05f0, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x05f1, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x05f2, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05f3, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05f4, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05f5, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05f6, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05f7, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05f8, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05f9, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05fa, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05fb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05fc, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [2] = ctx->dcn_reg_offsets[3] + 0x05fd, ( ( dccg_regs.MPCC_TOP_SEL [3] = ctx->dcn_reg_offsets[3] + 0x003f, dccg_regs.MPCC_BOT_SEL [3] = ctx->dcn_reg_offsets[3] + 0x0040, dccg_regs.MPCC_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0042, dccg_regs.MPCC_STATUS [3] = ctx->dcn_reg_offsets[3] + 0x004d, dccg_regs.MPCC_OPP_ID [3] = ctx->dcn_reg_offsets[3] + 0x0041, dccg_regs.MPCC_BG_G_Y [3] = ctx->dcn_reg_offsets[3] + 0x004a, dccg_regs.MPCC_BG_R_CR [3] = ctx->dcn_reg_offsets[3] + 0x0049, dccg_regs.MPCC_BG_B_CB [3] = ctx->dcn_reg_offsets[3] + 0x004b, dccg_regs.MPCC_SM_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0043, dccg_regs.MPCC_UPDATE_LOCK_SEL [3] = ctx->dcn_reg_offsets[3] + 0x0044 ), dccg_regs.MPCC_TOP_GAIN [3] = ctx->dcn_reg_offsets[3] + 0x0045, dccg_regs.MPCC_BOT_GAIN_INSIDE [3] = ctx->dcn_reg_offsets[3] + 0x0046, dccg_regs.MPCC_BOT_GAIN_OUTSIDE [3] = ctx->dcn_reg_offsets[3] + 0x0047, dccg_regs.MPCC_MEM_PWR_CTRL [3] = ctx->dcn_reg_offsets[3] + 0x004c, dccg_regs.MPCC_OGAM_LUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x01c3, dccg_regs.MPCC_OGAM_LUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x01c4, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT [3] = ctx->dcn_reg_offsets[3] + 0x020c, dccg_regs.MPCC_GAMUT_REMAP_MODE [3] = ctx->dcn_reg_offsets[3] + 0x020d, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [3] = ctx->dcn_reg_offsets[3] + 0x020e, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [3] = ctx->dcn_reg_offsets[3] + 0x0213, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [3] = ctx->dcn_reg_offsets[3] + 0x0214, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [3] = ctx->dcn_reg_offsets[3] + 0x0219, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01c6, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01c7, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01c8, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01c9, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ca, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01cb, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x01cf, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x01d0, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x01d1, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x01d2, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x01d3, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x01d4, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x01d8, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x01e8, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x01d5, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x01d6, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x01d7, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01cc, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01cd, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01ce, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01e9, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ea, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01eb, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01ec, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ed, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01ee, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x01f2, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x01f3, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x01f4, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x01f5, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x01f6, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x01f7, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x01fb, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x020b, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x01f8, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x01f9, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x01fa, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01ef, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01f0, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01f1, dccg_regs.MPCC_OGAM_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x01c2, dccg_regs.MPCC_OGAM_LUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x01c5 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0048, dccg_regs.MPCC_MCM_SHAPER_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0603, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0604, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0605, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0606, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [3] = ctx->dcn_reg_offsets[3] + 0x0607, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [3] = ctx->dcn_reg_offsets[3] + 0x0608, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x0609, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x060a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [3] = ctx->dcn_reg_offsets[3] + 0x060b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x060c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x060d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x060e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x060f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0610, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0611, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0612, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x0613, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x0614, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x0615, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x0616, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x0617, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x0618, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0619, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x061a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x061b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x061c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x061d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x061e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x061f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0620, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0621, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0622, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0623, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0624, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0625, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0626, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0627, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0628, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0629, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x062a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x062b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x062c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x062d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x062e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x062f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0630, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0631, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0632, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0633, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0634, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0635, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0636, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0637, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0638, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0639, dccg_regs.MPCC_MCM_3DLUT_MODE [3] = ctx->dcn_reg_offsets[3] + 0x063a, dccg_regs.MPCC_MCM_3DLUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x063b, dccg_regs.MPCC_MCM_3DLUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x063c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [3] = ctx->dcn_reg_offsets[3] + 0x063d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x063e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [3] = ctx->dcn_reg_offsets[3] + 0x063f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0640, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0641, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0642, dccg_regs.MPCC_MCM_1DLUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0643, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x0644, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x0645, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0646, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0647, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0648, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0649, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x064a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x064b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x064c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x064d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x064e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x064f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x0650, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x0651, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x0652, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x0653, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x0654, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x0655, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0656, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0657, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0658, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0659, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x065a, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x065b, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x065c, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x065d, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x065e, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x065f, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0660, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0661, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0662, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0663, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0664, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0665, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0666, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0667, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0668, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0669, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x066a, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x066b, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x066c, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x066d, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x066e, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x066f, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0670, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0671, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0672, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x0673, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x0674, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x0675, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x0676, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x0677, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x0678, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0679, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x067a, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x067b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x067c, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x067d, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x067e, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x067f, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x0680, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x0681, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x0682, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0683, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0684, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0685, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0686, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0687, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0688, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0689, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x068a, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x068b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x068c, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [3] = ctx->dcn_reg_offsets[3] + 0x068d, ( ( dccg_regs.MUX[ 0] = ctx->dcn_reg_offsets[3] + 0x03d8, dccg_regs.CUR[0] = ctx ->dcn_reg_offsets[3] + 0x03ab ), dccg_regs.CSC_MODE[0] = ctx ->dcn_reg_offsets[3] + 0x03f1, dccg_regs.CSC_C11_C12_A[0] = ctx->dcn_reg_offsets[3] + 0x03f2, dccg_regs.CSC_C33_C34_A [0] = ctx->dcn_reg_offsets[3] + 0x03f7, dccg_regs.CSC_C11_C12_B [0] = ctx->dcn_reg_offsets[3] + 0x03f8, dccg_regs.CSC_C33_C34_B [0] = ctx->dcn_reg_offsets[3] + 0x03fd, dccg_regs.DENORM_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x03d9, dccg_regs.DENORM_CLAMP_G_Y [0] = ctx->dcn_reg_offsets[3] + 0x03da, dccg_regs.DENORM_CLAMP_B_CB [0] = ctx->dcn_reg_offsets[3] + 0x03db, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ), ( ( dccg_regs.MUX[1 ] = ctx->dcn_reg_offsets[3] + 0x03dc, dccg_regs.CUR[1] = ctx ->dcn_reg_offsets[3] + 0x03b0 ), dccg_regs.CSC_MODE[1] = ctx ->dcn_reg_offsets[3] + 0x03fe, dccg_regs.CSC_C11_C12_A[1] = ctx->dcn_reg_offsets[3] + 0x03ff, dccg_regs.CSC_C33_C34_A [1] = ctx->dcn_reg_offsets[3] + 0x0404, dccg_regs.CSC_C11_C12_B [1] = ctx->dcn_reg_offsets[3] + 0x0405, dccg_regs.CSC_C33_C34_B [1] = ctx->dcn_reg_offsets[3] + 0x040a, dccg_regs.DENORM_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x03dd, dccg_regs.DENORM_CLAMP_G_Y [1] = ctx->dcn_reg_offsets[3] + 0x03de, dccg_regs.DENORM_CLAMP_B_CB [1] = ctx->dcn_reg_offsets[3] + 0x03df, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ), ( ( dccg_regs.MUX[2 ] = ctx->dcn_reg_offsets[3] + 0x03e0, dccg_regs.CUR[2] = ctx ->dcn_reg_offsets[3] + 0x03b5 ), dccg_regs.CSC_MODE[2] = ctx ->dcn_reg_offsets[3] + 0x040b, dccg_regs.CSC_C11_C12_A[2] = ctx->dcn_reg_offsets[3] + 0x040c, dccg_regs.CSC_C33_C34_A [2] = ctx->dcn_reg_offsets[3] + 0x0411, dccg_regs.CSC_C11_C12_B [2] = ctx->dcn_reg_offsets[3] + 0x0412, dccg_regs.CSC_C33_C34_B [2] = ctx->dcn_reg_offsets[3] + 0x0417, dccg_regs.DENORM_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x03e1, dccg_regs.DENORM_CLAMP_G_Y [2] = ctx->dcn_reg_offsets[3] + 0x03e2, dccg_regs.DENORM_CLAMP_B_CB [2] = ctx->dcn_reg_offsets[3] + 0x03e3, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ), ( ( dccg_regs.MUX[3 ] = ctx->dcn_reg_offsets[3] + 0x03e4, dccg_regs.CUR[3] = ctx ->dcn_reg_offsets[3] + 0x03ba ), dccg_regs.CSC_MODE[3] = ctx ->dcn_reg_offsets[3] + 0x0418, dccg_regs.CSC_C11_C12_A[3] = ctx->dcn_reg_offsets[3] + 0x0419, dccg_regs.CSC_C33_C34_A [3] = ctx->dcn_reg_offsets[3] + 0x041e, dccg_regs.CSC_C11_C12_B [3] = ctx->dcn_reg_offsets[3] + 0x041f, dccg_regs.CSC_C33_C34_B [3] = ctx->dcn_reg_offsets[3] + 0x0424, dccg_regs.DENORM_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x03e5, dccg_regs.DENORM_CLAMP_G_Y [3] = ctx->dcn_reg_offsets[3] + 0x03e6, dccg_regs.DENORM_CLAMP_B_CB [3] = ctx->dcn_reg_offsets[3] + 0x03e7, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ), dccg_regs.DWB_MUX[0 ] = ctx->dcn_reg_offsets[3] + 0x03c6 \ |
450 | MPC_REG_LIST_DCN3_2_RI(0)( ( dccg_regs.MPCC_TOP_SEL[0] = ctx->dcn_reg_offsets[3] + 0x0000 , dccg_regs.MPCC_BOT_SEL[0] = ctx->dcn_reg_offsets[3] + 0x0001 , dccg_regs.MPCC_CONTROL[0] = ctx->dcn_reg_offsets[3] + 0x0003 , dccg_regs.MPCC_STATUS[0] = ctx->dcn_reg_offsets[3] + 0x000e , dccg_regs.MPCC_OPP_ID[0] = ctx->dcn_reg_offsets[3] + 0x0002 , dccg_regs.MPCC_BG_G_Y[0] = ctx->dcn_reg_offsets[3] + 0x000b , dccg_regs.MPCC_BG_R_CR[0] = ctx->dcn_reg_offsets[3] + 0x000a , dccg_regs.MPCC_BG_B_CB[0] = ctx->dcn_reg_offsets[3] + 0x000c , dccg_regs.MPCC_SM_CONTROL[0] = ctx->dcn_reg_offsets[3] + 0x0004, dccg_regs.MPCC_UPDATE_LOCK_SEL[0] = ctx->dcn_reg_offsets [3] + 0x0005 ), dccg_regs.MPCC_TOP_GAIN[0] = ctx->dcn_reg_offsets [3] + 0x0006, dccg_regs.MPCC_BOT_GAIN_INSIDE[0] = ctx->dcn_reg_offsets [3] + 0x0007, dccg_regs.MPCC_BOT_GAIN_OUTSIDE[0] = ctx->dcn_reg_offsets [3] + 0x0008, dccg_regs.MPCC_MEM_PWR_CTRL[0] = ctx->dcn_reg_offsets [3] + 0x000d, dccg_regs.MPCC_OGAM_LUT_INDEX[0] = ctx->dcn_reg_offsets [3] + 0x00a9, dccg_regs.MPCC_OGAM_LUT_DATA[0] = ctx->dcn_reg_offsets [3] + 0x00aa, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT[0] = ctx ->dcn_reg_offsets[3] + 0x00f2, dccg_regs.MPCC_GAMUT_REMAP_MODE [0] = ctx->dcn_reg_offsets[3] + 0x00f3, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [0] = ctx->dcn_reg_offsets[3] + 0x00f4, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [0] = ctx->dcn_reg_offsets[3] + 0x00f9, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [0] = ctx->dcn_reg_offsets[3] + 0x00fa, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [0] = ctx->dcn_reg_offsets[3] + 0x00ff, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00ac, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00ad, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00ae, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00af, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00b0, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00b1, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x00b5, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x00b6, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x00b7, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x00b8, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x00b9, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x00ba, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x00be, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x00ce, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x00bb, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x00bc, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x00bd, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00b2, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00b3, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00b4, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00cf, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d0, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d1, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00d2, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d3, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d4, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x00d8, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x00d9, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x00da, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x00db, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x00dc, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x00dd, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x00e1, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x00f1, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x00de, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x00df, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x00e0, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00d5, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d6, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d7, dccg_regs.MPCC_OGAM_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x00a8, dccg_regs.MPCC_OGAM_LUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x00ab ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0009, dccg_regs.MPCC_MCM_SHAPER_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0453, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x0454, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x0455, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x0456, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [0] = ctx->dcn_reg_offsets[3] + 0x0457, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [0] = ctx->dcn_reg_offsets[3] + 0x0458, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x0459, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x045a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [0] = ctx->dcn_reg_offsets[3] + 0x045b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x045c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x045d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x045e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x045f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0460, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0461, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x0462, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x0463, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x0464, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x0465, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x0466, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x0467, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x0468, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x0469, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x046a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x046b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x046c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x046d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x046e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x046f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x0470, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x0471, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x0472, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0473, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0474, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0475, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0476, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0477, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0478, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x0479, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x047a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x047b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x047c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x047d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x047e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x047f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x0480, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x0481, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x0482, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x0483, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x0484, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x0485, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x0486, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x0487, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x0488, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x0489, dccg_regs.MPCC_MCM_3DLUT_MODE [0] = ctx->dcn_reg_offsets[3] + 0x048a, dccg_regs.MPCC_MCM_3DLUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x048b, dccg_regs.MPCC_MCM_3DLUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x048c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [0] = ctx->dcn_reg_offsets[3] + 0x048d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x048e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [0] = ctx->dcn_reg_offsets[3] + 0x048f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x0490, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x0491, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x0492, dccg_regs.MPCC_MCM_1DLUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0493, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x0494, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x0495, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0496, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0497, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0498, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0499, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x049a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x049b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x049c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x049d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x049e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x049f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x04a0, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x04a1, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x04a2, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x04a3, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x04a4, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x04a5, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x04a6, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x04a7, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x04a8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x04a9, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x04aa, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x04ab, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x04ac, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x04ad, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x04ae, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x04af, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x04b0, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x04b1, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x04b2, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x04b3, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x04b4, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x04b5, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x04b6, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x04b7, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x04b8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x04b9, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04ba, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04bb, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04bc, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04bd, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04be, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04bf, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04c0, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04c1, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04c2, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x04c3, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x04c4, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x04c5, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x04c6, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x04c7, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x04c8, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x04c9, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x04ca, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x04cb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x04cc, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x04cd, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x04ce, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x04cf, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x04d0, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x04d1, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x04d2, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x04d3, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x04d4, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x04d5, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x04d6, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x04d7, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x04d8, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x04d9, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x04da, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x04db, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x04dc, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [0] = ctx->dcn_reg_offsets[3] + 0x04dd,\ |
451 | MPC_REG_LIST_DCN3_2_RI(1)( ( dccg_regs.MPCC_TOP_SEL[1] = ctx->dcn_reg_offsets[3] + 0x0015 , dccg_regs.MPCC_BOT_SEL[1] = ctx->dcn_reg_offsets[3] + 0x0016 , dccg_regs.MPCC_CONTROL[1] = ctx->dcn_reg_offsets[3] + 0x0018 , dccg_regs.MPCC_STATUS[1] = ctx->dcn_reg_offsets[3] + 0x0023 , dccg_regs.MPCC_OPP_ID[1] = ctx->dcn_reg_offsets[3] + 0x0017 , dccg_regs.MPCC_BG_G_Y[1] = ctx->dcn_reg_offsets[3] + 0x0020 , dccg_regs.MPCC_BG_R_CR[1] = ctx->dcn_reg_offsets[3] + 0x001f , dccg_regs.MPCC_BG_B_CB[1] = ctx->dcn_reg_offsets[3] + 0x0021 , dccg_regs.MPCC_SM_CONTROL[1] = ctx->dcn_reg_offsets[3] + 0x0019, dccg_regs.MPCC_UPDATE_LOCK_SEL[1] = ctx->dcn_reg_offsets [3] + 0x001a ), dccg_regs.MPCC_TOP_GAIN[1] = ctx->dcn_reg_offsets [3] + 0x001b, dccg_regs.MPCC_BOT_GAIN_INSIDE[1] = ctx->dcn_reg_offsets [3] + 0x001c, dccg_regs.MPCC_BOT_GAIN_OUTSIDE[1] = ctx->dcn_reg_offsets [3] + 0x001d, dccg_regs.MPCC_MEM_PWR_CTRL[1] = ctx->dcn_reg_offsets [3] + 0x0022, dccg_regs.MPCC_OGAM_LUT_INDEX[1] = ctx->dcn_reg_offsets [3] + 0x0107, dccg_regs.MPCC_OGAM_LUT_DATA[1] = ctx->dcn_reg_offsets [3] + 0x0108, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT[1] = ctx ->dcn_reg_offsets[3] + 0x0150, dccg_regs.MPCC_GAMUT_REMAP_MODE [1] = ctx->dcn_reg_offsets[3] + 0x0151, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [1] = ctx->dcn_reg_offsets[3] + 0x0152, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [1] = ctx->dcn_reg_offsets[3] + 0x0157, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [1] = ctx->dcn_reg_offsets[3] + 0x0158, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [1] = ctx->dcn_reg_offsets[3] + 0x015d, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x010a, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x010b, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x010c, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x010d, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x010e, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x010f, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0113, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0114, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0115, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0116, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0117, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0118, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x011c, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x012c, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0119, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x011a, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x011b, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0110, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0111, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0112, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x012d, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x012e, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x012f, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0130, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0131, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0132, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0136, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0137, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0138, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0139, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x013a, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x013b, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x013f, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x014f, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x013c, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x013d, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x013e, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0133, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0134, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0135, dccg_regs.MPCC_OGAM_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0106, dccg_regs.MPCC_OGAM_LUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0109 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x001e, dccg_regs.MPCC_MCM_SHAPER_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x04e3, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x04e4, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x04e5, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x04e6, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [1] = ctx->dcn_reg_offsets[3] + 0x04e7, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [1] = ctx->dcn_reg_offsets[3] + 0x04e8, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x04e9, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x04ea, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [1] = ctx->dcn_reg_offsets[3] + 0x04eb, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x04ec, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x04ed, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x04ee, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x04ef, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x04f0, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x04f1, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x04f2, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x04f3, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x04f4, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x04f5, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x04f6, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x04f7, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x04f8, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x04f9, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x04fa, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x04fb, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x04fc, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x04fd, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x04fe, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x04ff, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0500, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0501, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0502, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0503, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0504, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0505, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0506, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0507, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0508, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x0509, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x050a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x050b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x050c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x050d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x050e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x050f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0510, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0511, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0512, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0513, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0514, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0515, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0516, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0517, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0518, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0519, dccg_regs.MPCC_MCM_3DLUT_MODE [1] = ctx->dcn_reg_offsets[3] + 0x051a, dccg_regs.MPCC_MCM_3DLUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x051b, dccg_regs.MPCC_MCM_3DLUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x051c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [1] = ctx->dcn_reg_offsets[3] + 0x051d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x051e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [1] = ctx->dcn_reg_offsets[3] + 0x051f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x0520, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x0521, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0522, dccg_regs.MPCC_MCM_1DLUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0523, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x0524, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x0525, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0526, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0527, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0528, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0529, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x052a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x052b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x052c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x052d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x052e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x052f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0530, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0531, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0532, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0533, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0534, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0535, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0536, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x0537, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x0538, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x0539, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x053a, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x053b, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x053c, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x053d, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x053e, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x053f, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0540, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0541, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0542, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0543, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0544, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0545, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0546, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0547, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0548, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0549, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x054a, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x054b, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x054c, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x054d, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x054e, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x054f, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0550, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0551, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0552, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0553, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0554, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0555, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0556, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0557, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0558, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0559, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x055a, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x055b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x055c, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x055d, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x055e, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x055f, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x0560, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x0561, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x0562, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0563, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0564, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0565, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0566, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0567, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0568, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0569, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x056a, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x056b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x056c, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [1] = ctx->dcn_reg_offsets[3] + 0x056d,\ |
452 | MPC_REG_LIST_DCN3_2_RI(2)( ( dccg_regs.MPCC_TOP_SEL[2] = ctx->dcn_reg_offsets[3] + 0x002a , dccg_regs.MPCC_BOT_SEL[2] = ctx->dcn_reg_offsets[3] + 0x002b , dccg_regs.MPCC_CONTROL[2] = ctx->dcn_reg_offsets[3] + 0x002d , dccg_regs.MPCC_STATUS[2] = ctx->dcn_reg_offsets[3] + 0x0038 , dccg_regs.MPCC_OPP_ID[2] = ctx->dcn_reg_offsets[3] + 0x002c , dccg_regs.MPCC_BG_G_Y[2] = ctx->dcn_reg_offsets[3] + 0x0035 , dccg_regs.MPCC_BG_R_CR[2] = ctx->dcn_reg_offsets[3] + 0x0034 , dccg_regs.MPCC_BG_B_CB[2] = ctx->dcn_reg_offsets[3] + 0x0036 , dccg_regs.MPCC_SM_CONTROL[2] = ctx->dcn_reg_offsets[3] + 0x002e, dccg_regs.MPCC_UPDATE_LOCK_SEL[2] = ctx->dcn_reg_offsets [3] + 0x002f ), dccg_regs.MPCC_TOP_GAIN[2] = ctx->dcn_reg_offsets [3] + 0x0030, dccg_regs.MPCC_BOT_GAIN_INSIDE[2] = ctx->dcn_reg_offsets [3] + 0x0031, dccg_regs.MPCC_BOT_GAIN_OUTSIDE[2] = ctx->dcn_reg_offsets [3] + 0x0032, dccg_regs.MPCC_MEM_PWR_CTRL[2] = ctx->dcn_reg_offsets [3] + 0x0037, dccg_regs.MPCC_OGAM_LUT_INDEX[2] = ctx->dcn_reg_offsets [3] + 0x0165, dccg_regs.MPCC_OGAM_LUT_DATA[2] = ctx->dcn_reg_offsets [3] + 0x0166, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT[2] = ctx ->dcn_reg_offsets[3] + 0x01ae, dccg_regs.MPCC_GAMUT_REMAP_MODE [2] = ctx->dcn_reg_offsets[3] + 0x01af, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [2] = ctx->dcn_reg_offsets[3] + 0x01b0, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [2] = ctx->dcn_reg_offsets[3] + 0x01b5, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [2] = ctx->dcn_reg_offsets[3] + 0x01b6, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [2] = ctx->dcn_reg_offsets[3] + 0x01bb, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0168, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0169, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x016a, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x016b, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x016c, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x016d, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x0171, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x0172, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x0173, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x0174, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x0175, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x0176, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x017a, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x018a, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x0177, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x0178, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x0179, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x016e, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x016f, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0170, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x018b, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x018c, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x018d, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x018e, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x018f, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0190, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x0194, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x0195, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x0196, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x0197, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x0198, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x0199, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x019d, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x01ad, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x019a, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x019b, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x019c, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0191, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0192, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0193, dccg_regs.MPCC_OGAM_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0164, dccg_regs.MPCC_OGAM_LUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0167 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0033, dccg_regs.MPCC_MCM_SHAPER_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0573, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x0574, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x0575, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x0576, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [2] = ctx->dcn_reg_offsets[3] + 0x0577, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [2] = ctx->dcn_reg_offsets[3] + 0x0578, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x0579, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x057a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [2] = ctx->dcn_reg_offsets[3] + 0x057b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x057c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x057d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x057e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x057f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0580, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0581, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x0582, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x0583, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x0584, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x0585, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x0586, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x0587, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x0588, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x0589, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x058a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x058b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x058c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x058d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x058e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x058f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x0590, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x0591, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x0592, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0593, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0594, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0595, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0596, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0597, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0598, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x0599, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x059a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x059b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x059c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x059d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x059e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x059f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05a0, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05a1, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05a2, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05a3, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05a4, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05a5, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05a6, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05a7, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05a8, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05a9, dccg_regs.MPCC_MCM_3DLUT_MODE [2] = ctx->dcn_reg_offsets[3] + 0x05aa, dccg_regs.MPCC_MCM_3DLUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x05ab, dccg_regs.MPCC_MCM_3DLUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x05ac, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [2] = ctx->dcn_reg_offsets[3] + 0x05ad, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05ae, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [2] = ctx->dcn_reg_offsets[3] + 0x05af, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05b0, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05b1, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05b2, dccg_regs.MPCC_MCM_1DLUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05b3, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x05b4, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x05b5, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05b6, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05b7, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05b8, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05b9, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05ba, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05bb, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05bc, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05bd, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05be, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05bf, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x05c0, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x05c1, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x05c2, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x05c3, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x05c4, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x05c5, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05c6, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05c7, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05c8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x05c9, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x05ca, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x05cb, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x05cc, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x05cd, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x05ce, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x05cf, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05d0, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05d1, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05d2, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05d3, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05d4, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05d5, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05d6, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05d7, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05d8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05d9, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05da, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05db, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05dc, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05dd, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05de, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05df, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05e0, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05e1, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05e2, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x05e3, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x05e4, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x05e5, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x05e6, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x05e7, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x05e8, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05e9, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05ea, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05eb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x05ec, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x05ed, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x05ee, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x05ef, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x05f0, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x05f1, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x05f2, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05f3, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05f4, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05f5, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05f6, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05f7, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05f8, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05f9, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05fa, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05fb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05fc, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [2] = ctx->dcn_reg_offsets[3] + 0x05fd,\ |
453 | MPC_REG_LIST_DCN3_2_RI(3)( ( dccg_regs.MPCC_TOP_SEL[3] = ctx->dcn_reg_offsets[3] + 0x003f , dccg_regs.MPCC_BOT_SEL[3] = ctx->dcn_reg_offsets[3] + 0x0040 , dccg_regs.MPCC_CONTROL[3] = ctx->dcn_reg_offsets[3] + 0x0042 , dccg_regs.MPCC_STATUS[3] = ctx->dcn_reg_offsets[3] + 0x004d , dccg_regs.MPCC_OPP_ID[3] = ctx->dcn_reg_offsets[3] + 0x0041 , dccg_regs.MPCC_BG_G_Y[3] = ctx->dcn_reg_offsets[3] + 0x004a , dccg_regs.MPCC_BG_R_CR[3] = ctx->dcn_reg_offsets[3] + 0x0049 , dccg_regs.MPCC_BG_B_CB[3] = ctx->dcn_reg_offsets[3] + 0x004b , dccg_regs.MPCC_SM_CONTROL[3] = ctx->dcn_reg_offsets[3] + 0x0043, dccg_regs.MPCC_UPDATE_LOCK_SEL[3] = ctx->dcn_reg_offsets [3] + 0x0044 ), dccg_regs.MPCC_TOP_GAIN[3] = ctx->dcn_reg_offsets [3] + 0x0045, dccg_regs.MPCC_BOT_GAIN_INSIDE[3] = ctx->dcn_reg_offsets [3] + 0x0046, dccg_regs.MPCC_BOT_GAIN_OUTSIDE[3] = ctx->dcn_reg_offsets [3] + 0x0047, dccg_regs.MPCC_MEM_PWR_CTRL[3] = ctx->dcn_reg_offsets [3] + 0x004c, dccg_regs.MPCC_OGAM_LUT_INDEX[3] = ctx->dcn_reg_offsets [3] + 0x01c3, dccg_regs.MPCC_OGAM_LUT_DATA[3] = ctx->dcn_reg_offsets [3] + 0x01c4, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT[3] = ctx ->dcn_reg_offsets[3] + 0x020c, dccg_regs.MPCC_GAMUT_REMAP_MODE [3] = ctx->dcn_reg_offsets[3] + 0x020d, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [3] = ctx->dcn_reg_offsets[3] + 0x020e, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [3] = ctx->dcn_reg_offsets[3] + 0x0213, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [3] = ctx->dcn_reg_offsets[3] + 0x0214, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [3] = ctx->dcn_reg_offsets[3] + 0x0219, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01c6, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01c7, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01c8, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01c9, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ca, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01cb, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x01cf, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x01d0, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x01d1, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x01d2, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x01d3, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x01d4, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x01d8, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x01e8, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x01d5, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x01d6, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x01d7, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01cc, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01cd, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01ce, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01e9, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ea, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01eb, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01ec, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ed, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01ee, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x01f2, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x01f3, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x01f4, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x01f5, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x01f6, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x01f7, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x01fb, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x020b, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x01f8, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x01f9, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x01fa, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01ef, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01f0, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01f1, dccg_regs.MPCC_OGAM_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x01c2, dccg_regs.MPCC_OGAM_LUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x01c5 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0048, dccg_regs.MPCC_MCM_SHAPER_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0603, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0604, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0605, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0606, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [3] = ctx->dcn_reg_offsets[3] + 0x0607, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [3] = ctx->dcn_reg_offsets[3] + 0x0608, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x0609, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x060a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [3] = ctx->dcn_reg_offsets[3] + 0x060b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x060c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x060d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x060e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x060f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0610, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0611, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0612, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x0613, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x0614, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x0615, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x0616, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x0617, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x0618, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0619, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x061a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x061b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x061c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x061d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x061e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x061f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0620, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0621, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0622, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0623, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0624, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0625, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0626, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0627, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0628, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0629, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x062a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x062b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x062c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x062d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x062e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x062f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0630, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0631, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0632, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0633, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0634, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0635, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0636, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0637, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0638, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0639, dccg_regs.MPCC_MCM_3DLUT_MODE [3] = ctx->dcn_reg_offsets[3] + 0x063a, dccg_regs.MPCC_MCM_3DLUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x063b, dccg_regs.MPCC_MCM_3DLUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x063c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [3] = ctx->dcn_reg_offsets[3] + 0x063d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x063e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [3] = ctx->dcn_reg_offsets[3] + 0x063f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0640, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0641, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0642, dccg_regs.MPCC_MCM_1DLUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0643, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x0644, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x0645, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0646, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0647, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0648, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0649, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x064a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x064b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x064c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x064d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x064e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x064f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x0650, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x0651, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x0652, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x0653, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x0654, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x0655, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0656, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0657, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0658, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0659, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x065a, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x065b, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x065c, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x065d, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x065e, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x065f, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0660, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0661, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0662, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0663, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0664, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0665, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0666, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0667, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0668, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0669, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x066a, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x066b, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x066c, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x066d, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x066e, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x066f, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0670, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0671, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0672, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x0673, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x0674, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x0675, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x0676, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x0677, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x0678, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0679, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x067a, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x067b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x067c, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x067d, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x067e, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x067f, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x0680, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x0681, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x0682, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0683, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0684, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0685, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0686, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0687, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0688, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0689, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x068a, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x068b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x068c, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [3] = ctx->dcn_reg_offsets[3] + 0x068d,\ |
454 | MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0)( ( dccg_regs.MUX[0] = ctx->dcn_reg_offsets[3] + 0x03d8, dccg_regs .CUR[0] = ctx->dcn_reg_offsets[3] + 0x03ab ), dccg_regs.CSC_MODE [0] = ctx->dcn_reg_offsets[3] + 0x03f1, dccg_regs.CSC_C11_C12_A [0] = ctx->dcn_reg_offsets[3] + 0x03f2, dccg_regs.CSC_C33_C34_A [0] = ctx->dcn_reg_offsets[3] + 0x03f7, dccg_regs.CSC_C11_C12_B [0] = ctx->dcn_reg_offsets[3] + 0x03f8, dccg_regs.CSC_C33_C34_B [0] = ctx->dcn_reg_offsets[3] + 0x03fd, dccg_regs.DENORM_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x03d9, dccg_regs.DENORM_CLAMP_G_Y [0] = ctx->dcn_reg_offsets[3] + 0x03da, dccg_regs.DENORM_CLAMP_B_CB [0] = ctx->dcn_reg_offsets[3] + 0x03db, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ),\ |
455 | MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1)( ( dccg_regs.MUX[1] = ctx->dcn_reg_offsets[3] + 0x03dc, dccg_regs .CUR[1] = ctx->dcn_reg_offsets[3] + 0x03b0 ), dccg_regs.CSC_MODE [1] = ctx->dcn_reg_offsets[3] + 0x03fe, dccg_regs.CSC_C11_C12_A [1] = ctx->dcn_reg_offsets[3] + 0x03ff, dccg_regs.CSC_C33_C34_A [1] = ctx->dcn_reg_offsets[3] + 0x0404, dccg_regs.CSC_C11_C12_B [1] = ctx->dcn_reg_offsets[3] + 0x0405, dccg_regs.CSC_C33_C34_B [1] = ctx->dcn_reg_offsets[3] + 0x040a, dccg_regs.DENORM_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x03dd, dccg_regs.DENORM_CLAMP_G_Y [1] = ctx->dcn_reg_offsets[3] + 0x03de, dccg_regs.DENORM_CLAMP_B_CB [1] = ctx->dcn_reg_offsets[3] + 0x03df, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ),\ |
456 | MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2)( ( dccg_regs.MUX[2] = ctx->dcn_reg_offsets[3] + 0x03e0, dccg_regs .CUR[2] = ctx->dcn_reg_offsets[3] + 0x03b5 ), dccg_regs.CSC_MODE [2] = ctx->dcn_reg_offsets[3] + 0x040b, dccg_regs.CSC_C11_C12_A [2] = ctx->dcn_reg_offsets[3] + 0x040c, dccg_regs.CSC_C33_C34_A [2] = ctx->dcn_reg_offsets[3] + 0x0411, dccg_regs.CSC_C11_C12_B [2] = ctx->dcn_reg_offsets[3] + 0x0412, dccg_regs.CSC_C33_C34_B [2] = ctx->dcn_reg_offsets[3] + 0x0417, dccg_regs.DENORM_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x03e1, dccg_regs.DENORM_CLAMP_G_Y [2] = ctx->dcn_reg_offsets[3] + 0x03e2, dccg_regs.DENORM_CLAMP_B_CB [2] = ctx->dcn_reg_offsets[3] + 0x03e3, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ),\ |
457 | MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3)( ( dccg_regs.MUX[3] = ctx->dcn_reg_offsets[3] + 0x03e4, dccg_regs .CUR[3] = ctx->dcn_reg_offsets[3] + 0x03ba ), dccg_regs.CSC_MODE [3] = ctx->dcn_reg_offsets[3] + 0x0418, dccg_regs.CSC_C11_C12_A [3] = ctx->dcn_reg_offsets[3] + 0x0419, dccg_regs.CSC_C33_C34_A [3] = ctx->dcn_reg_offsets[3] + 0x041e, dccg_regs.CSC_C11_C12_B [3] = ctx->dcn_reg_offsets[3] + 0x041f, dccg_regs.CSC_C33_C34_B [3] = ctx->dcn_reg_offsets[3] + 0x0424, dccg_regs.DENORM_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x03e5, dccg_regs.DENORM_CLAMP_G_Y [3] = ctx->dcn_reg_offsets[3] + 0x03e6, dccg_regs.DENORM_CLAMP_B_CB [3] = ctx->dcn_reg_offsets[3] + 0x03e7, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ),\ |
458 | MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)dccg_regs.DWB_MUX[0] = ctx->dcn_reg_offsets[3] + 0x03c6 |
459 | |
460 | static const struct dcn30_mpc_shift mpc_shift = { |
461 | MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT).MPCC_TOP_SEL = 0x0, .MPCC_BOT_SEL = 0x0, .MPCC_MODE = 0x0, . MPCC_ALPHA_BLND_MODE = 0x4, .MPCC_ALPHA_MULTIPLIED_MODE = 0x6 , .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x7, .MPCC_GLOBAL_ALPHA = 0x10 , .MPCC_GLOBAL_GAIN = 0x18, .MPCC_IDLE = 0x0, .MPCC_BUSY = 0x1 , .MPCC_OPP_ID = 0x0, .MPCC_BG_G_Y = 0x0, .MPCC_BG_R_CR = 0x0 , .MPCC_BG_B_CB = 0x0, .MPCC_SM_EN = 0x0, .MPCC_SM_MODE = 0x1 , .MPCC_SM_FRAME_ALT = 0x4, .MPCC_SM_FIELD_ALT = 0x5, .MPCC_SM_FORCE_NEXT_FRAME_POL = 0x8, .MPCC_SM_FORCE_NEXT_TOP_POL = 0x10, .MPC_OUT_MUX = 0x0 , .MPCC_UPDATE_LOCK_SEL = 0x0, .MPCC_BG_BPC = 0x8, .MPCC_BOT_GAIN_MODE = 0xb, .MPCC_TOP_GAIN = 0x0, .MPCC_BOT_GAIN_INSIDE = 0x0, .MPCC_BOT_GAIN_OUTSIDE = 0x0, .MPCC_MOVABLE_CM_LOCATION_CNTL = 0x0, .MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT = 0x4, .MPC_OCSC_MODE = 0x0, .MPC_OCSC_C11_A = 0x0, .MPC_OCSC_C12_A = 0x10, .MPCC_DISABLED = 0x2, .MPCC_OGAM_MEM_PWR_FORCE = 0x0 , .MPCC_OGAM_MEM_PWR_DIS = 0x2, .MPCC_OGAM_MEM_LOW_PWR_MODE = 0x4, .MPCC_OGAM_MEM_PWR_STATE = 0x8, .MPC_OUT_DENORM_MODE = 0x18 , .MPC_OUT_DENORM_CLAMP_MAX_R_CR = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_R_CR = 0x0, .MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_G_Y = 0x0, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_B_CB = 0x0, .MPCC_GAMUT_REMAP_MODE = 0x0, .MPCC_GAMUT_REMAP_MODE_CURRENT = 0x7, .MPCC_GAMUT_REMAP_COEF_FORMAT = 0x0, .MPCC_GAMUT_REMAP_C11_A = 0x0, .MPCC_GAMUT_REMAP_C12_A = 0x10, .MPC_DWB0_MUX = 0x0, . MPC_DWB0_MUX_STATUS = 0x4, .MPC_OUT_RATE_CONTROL = 0x9, .MPC_OUT_RATE_CONTROL_DISABLE = 0x8, .MPC_OUT_FLOW_CONTROL_MODE = 0xa, .MPC_OUT_FLOW_CONTROL_COUNT = 0xb, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .MPCC_OGAM_RAMA_OFFSET_B = 0x0, .MPCC_OGAM_RAMA_OFFSET_G = 0x0, .MPCC_OGAM_RAMA_OFFSET_R = 0x0, .MPCC_OGAM_LUT_INDEX = 0x0, .MPCC_OGAM_MODE = 0x0, .MPCC_OGAM_SELECT = 0x2, .MPCC_OGAM_PWL_DISABLE = 0x3, .MPCC_OGAM_MODE_CURRENT = 0x7, .MPCC_OGAM_SELECT_CURRENT = 0x9, .MPCC_OGAM_LUT_WRITE_COLOR_MASK = 0x0, .MPCC_OGAM_LUT_READ_COLOR_SEL = 0x3, .MPCC_OGAM_LUT_READ_DBG = 0x5, .MPCC_OGAM_LUT_HOST_SEL = 0x6, .MPCC_OGAM_LUT_CONFIG_MODE = 0x7, .MPCC_OGAM_LUT_DATA = 0x0, .MPCC_MCM_3DLUT_MODE = 0x0 , .MPCC_MCM_3DLUT_SIZE = 0x4, .MPCC_MCM_3DLUT_MODE_CURRENT = 0x8 , .MPCC_MCM_3DLUT_WRITE_EN_MASK = 0x0, .MPCC_MCM_3DLUT_RAM_SEL = 0x4, .MPCC_MCM_3DLUT_30BIT_EN = 0x8, .MPCC_MCM_3DLUT_READ_SEL = 0x10, .MPCC_MCM_3DLUT_INDEX = 0x0, .MPCC_MCM_3DLUT_DATA0 = 0x0, .MPCC_MCM_3DLUT_DATA1 = 0x10, .MPCC_MCM_3DLUT_DATA_30BIT = 0x2, .MPCC_MCM_SHAPER_LUT_MODE = 0x0, .MPCC_MCM_SHAPER_MODE_CURRENT = 0x2, .MPCC_MCM_SHAPER_OFFSET_R = 0x0, .MPCC_MCM_SHAPER_OFFSET_G = 0x0, .MPCC_MCM_SHAPER_OFFSET_B = 0x0, .MPCC_MCM_SHAPER_SCALE_R = 0x0, .MPCC_MCM_SHAPER_SCALE_G = 0x0, .MPCC_MCM_SHAPER_SCALE_B = 0x10, .MPCC_MCM_SHAPER_LUT_INDEX = 0x0, .MPCC_MCM_SHAPER_LUT_DATA = 0x0, .MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK = 0x0, .MPCC_MCM_SHAPER_LUT_WRITE_SEL = 0x4, .MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B = 0x0, .MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B = 0x0, .MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x10, .MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, . MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c , .MPCC_MCM_1DLUT_MODE = 0x0, .MPCC_MCM_1DLUT_SELECT = 0x2, . MPCC_MCM_1DLUT_PWL_DISABLE = 0x3, .MPCC_MCM_1DLUT_MODE_CURRENT = 0x4, .MPCC_MCM_1DLUT_SELECT_CURRENT = 0x6, .MPCC_MCM_1DLUT_LUT_INDEX = 0x0, .MPCC_MCM_1DLUT_LUT_DATA = 0x0, .MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK = 0x0, .MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL = 0x3, .MPCC_MCM_1DLUT_LUT_READ_DBG = 0x5, .MPCC_MCM_1DLUT_LUT_HOST_SEL = 0x6, .MPCC_MCM_1DLUT_LUT_CONFIG_MODE = 0x7, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B = 0x0, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B = 0x0, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B = 0x0, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B = 0x0, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .MPCC_MCM_1DLUT_RAMA_OFFSET_B = 0x0, .MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, . MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .MPCC_MCM_SHAPER_MEM_PWR_FORCE = 0x0, .MPCC_MCM_SHAPER_MEM_PWR_DIS = 0x2, .MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE = 0x4, .MPCC_MCM_3DLUT_MEM_PWR_FORCE = 0x8, .MPCC_MCM_3DLUT_MEM_PWR_DIS = 0xa, .MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE = 0xc, .MPCC_MCM_1DLUT_MEM_PWR_FORCE = 0x10, .MPCC_MCM_1DLUT_MEM_PWR_DIS = 0x12, .MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE = 0x14, .MPCC_MCM_SHAPER_MEM_PWR_STATE = 0x18, .MPCC_MCM_3DLUT_MEM_PWR_STATE = 0x1a, .MPCC_MCM_1DLUT_MEM_PWR_STATE = 0x1c, .CUR_VUPDATE_LOCK_SET = 0x0 |
462 | }; |
463 | |
464 | static const struct dcn30_mpc_mask mpc_mask = { |
465 | MPC_COMMON_MASK_SH_LIST_DCN32(_MASK).MPCC_TOP_SEL = 0x0000000FL, .MPCC_BOT_SEL = 0x0000000FL, .MPCC_MODE = 0x00000003L, .MPCC_ALPHA_BLND_MODE = 0x00000030L, .MPCC_ALPHA_MULTIPLIED_MODE = 0x00000040L, .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x00000080L, .MPCC_GLOBAL_ALPHA = 0x00FF0000L, .MPCC_GLOBAL_GAIN = 0xFF000000L , .MPCC_IDLE = 0x00000001L, .MPCC_BUSY = 0x00000002L, .MPCC_OPP_ID = 0x0000000FL, .MPCC_BG_G_Y = 0x00000FFFL, .MPCC_BG_R_CR = 0x00000FFFL , .MPCC_BG_B_CB = 0x00000FFFL, .MPCC_SM_EN = 0x00000001L, .MPCC_SM_MODE = 0x0000000EL, .MPCC_SM_FRAME_ALT = 0x00000010L, .MPCC_SM_FIELD_ALT = 0x00000020L, .MPCC_SM_FORCE_NEXT_FRAME_POL = 0x00000300L, . MPCC_SM_FORCE_NEXT_TOP_POL = 0x00030000L, .MPC_OUT_MUX = 0x0000000FL , .MPCC_UPDATE_LOCK_SEL = 0x0000000FL, .MPCC_BG_BPC = 0x00000700L , .MPCC_BOT_GAIN_MODE = 0x00000800L, .MPCC_TOP_GAIN = 0x0007FFFFL , .MPCC_BOT_GAIN_INSIDE = 0x0007FFFFL, .MPCC_BOT_GAIN_OUTSIDE = 0x0007FFFFL, .MPCC_MOVABLE_CM_LOCATION_CNTL = 0x00000001L, .MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT = 0x00000010L, .MPC_OCSC_MODE = 0x00000003L, .MPC_OCSC_C11_A = 0x0000FFFFL, .MPC_OCSC_C12_A = 0xFFFF0000L, .MPCC_DISABLED = 0x00000004L, .MPCC_OGAM_MEM_PWR_FORCE = 0x00000003L, .MPCC_OGAM_MEM_PWR_DIS = 0x00000004L, .MPCC_OGAM_MEM_LOW_PWR_MODE = 0x00000030L, .MPCC_OGAM_MEM_PWR_STATE = 0x00000300L, .MPC_OUT_DENORM_MODE = 0x07000000L, .MPC_OUT_DENORM_CLAMP_MAX_R_CR = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_R_CR = 0x00000FFFL, .MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_G_Y = 0x00000FFFL, . MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_B_CB = 0x00000FFFL, .MPCC_GAMUT_REMAP_MODE = 0x00000003L, .MPCC_GAMUT_REMAP_MODE_CURRENT = 0x00000180L, .MPCC_GAMUT_REMAP_COEF_FORMAT = 0x00000001L, . MPCC_GAMUT_REMAP_C11_A = 0x0000FFFFL, .MPCC_GAMUT_REMAP_C12_A = 0xFFFF0000L, .MPC_DWB0_MUX = 0x0000000FL, .MPC_DWB0_MUX_STATUS = 0x000000F0L, .MPC_OUT_RATE_CONTROL = 0x00000200L, .MPC_OUT_RATE_CONTROL_DISABLE = 0x00000100L, .MPC_OUT_FLOW_CONTROL_MODE = 0x00000400L, .MPC_OUT_FLOW_CONTROL_COUNT = 0x007FF800L, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL , .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L , .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL , .MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . MPCC_OGAM_RAMA_OFFSET_B = 0x0007FFFFL, .MPCC_OGAM_RAMA_OFFSET_G = 0x0007FFFFL, .MPCC_OGAM_RAMA_OFFSET_R = 0x0007FFFFL, .MPCC_OGAM_LUT_INDEX = 0x000001FFL, .MPCC_OGAM_MODE = 0x00000003L, .MPCC_OGAM_SELECT = 0x00000004L, .MPCC_OGAM_PWL_DISABLE = 0x00000008L, .MPCC_OGAM_MODE_CURRENT = 0x00000180L, .MPCC_OGAM_SELECT_CURRENT = 0x00000200L, .MPCC_OGAM_LUT_WRITE_COLOR_MASK = 0x00000007L, .MPCC_OGAM_LUT_READ_COLOR_SEL = 0x00000018L, . MPCC_OGAM_LUT_READ_DBG = 0x00000020L, .MPCC_OGAM_LUT_HOST_SEL = 0x00000040L, .MPCC_OGAM_LUT_CONFIG_MODE = 0x00000080L, .MPCC_OGAM_LUT_DATA = 0x0003FFFFL, .MPCC_MCM_3DLUT_MODE = 0x00000003L, .MPCC_MCM_3DLUT_SIZE = 0x00000010L, .MPCC_MCM_3DLUT_MODE_CURRENT = 0x00000300L, . MPCC_MCM_3DLUT_WRITE_EN_MASK = 0x0000000FL, .MPCC_MCM_3DLUT_RAM_SEL = 0x00000010L, .MPCC_MCM_3DLUT_30BIT_EN = 0x00000100L, .MPCC_MCM_3DLUT_READ_SEL = 0x00030000L, .MPCC_MCM_3DLUT_INDEX = 0x000007FFL, .MPCC_MCM_3DLUT_DATA0 = 0x0000FFFFL, .MPCC_MCM_3DLUT_DATA1 = 0xFFFF0000L, .MPCC_MCM_3DLUT_DATA_30BIT = 0xFFFFFFFCL, .MPCC_MCM_SHAPER_LUT_MODE = 0x00000003L, .MPCC_MCM_SHAPER_MODE_CURRENT = 0x0000000CL, .MPCC_MCM_SHAPER_OFFSET_R = 0x0007FFFFL, .MPCC_MCM_SHAPER_OFFSET_G = 0x0007FFFFL, .MPCC_MCM_SHAPER_OFFSET_B = 0x0007FFFFL, .MPCC_MCM_SHAPER_SCALE_R = 0x0000FFFFL, .MPCC_MCM_SHAPER_SCALE_G = 0x0000FFFFL, .MPCC_MCM_SHAPER_SCALE_B = 0xFFFF0000L, .MPCC_MCM_SHAPER_LUT_INDEX = 0x000000FFL, .MPCC_MCM_SHAPER_LUT_DATA = 0x00FFFFFFL, .MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK = 0x00000007L , .MPCC_MCM_SHAPER_LUT_WRITE_SEL = 0x00000010L, .MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B = 0x0003FFFFL, .MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B = 0x0000FFFFL , .MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x3FFF0000L, . MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .MPCC_MCM_1DLUT_MODE = 0x00000003L, .MPCC_MCM_1DLUT_SELECT = 0x00000004L, .MPCC_MCM_1DLUT_PWL_DISABLE = 0x00000008L, .MPCC_MCM_1DLUT_MODE_CURRENT = 0x00000030L, .MPCC_MCM_1DLUT_SELECT_CURRENT = 0x00000040L, .MPCC_MCM_1DLUT_LUT_INDEX = 0x000001FFL, .MPCC_MCM_1DLUT_LUT_DATA = 0x0003FFFFL, .MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK = 0x00000007L , .MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL = 0x00000018L, .MPCC_MCM_1DLUT_LUT_READ_DBG = 0x00000020L, .MPCC_MCM_1DLUT_LUT_HOST_SEL = 0x00000040L, . MPCC_MCM_1DLUT_LUT_CONFIG_MODE = 0x00000080L, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B = 0x0003FFFFL, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL , .MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .MPCC_MCM_1DLUT_RAMA_OFFSET_B = 0x0007FFFFL, . MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .MPCC_MCM_SHAPER_MEM_PWR_FORCE = 0x00000003L, . MPCC_MCM_SHAPER_MEM_PWR_DIS = 0x00000004L, .MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE = 0x00000030L, .MPCC_MCM_3DLUT_MEM_PWR_FORCE = 0x00000300L, . MPCC_MCM_3DLUT_MEM_PWR_DIS = 0x00000400L, .MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE = 0x00003000L, .MPCC_MCM_1DLUT_MEM_PWR_FORCE = 0x00030000L, . MPCC_MCM_1DLUT_MEM_PWR_DIS = 0x00040000L, .MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE = 0x00300000L, .MPCC_MCM_SHAPER_MEM_PWR_STATE = 0x03000000L, .MPCC_MCM_3DLUT_MEM_PWR_STATE = 0x0C000000L, .MPCC_MCM_1DLUT_MEM_PWR_STATE = 0x30000000L, .CUR_VUPDATE_LOCK_SET = 0x00000001L |
466 | }; |
467 | |
468 | #define optc_regs_init(id)( dccg_regs[id].OTG_VSTARTUP_PARAM = ctx->dcn_reg_offsets[ regOTGid_OTG_VSTARTUP_PARAM_BASE_IDX] + regOTGid_OTG_VSTARTUP_PARAM , dccg_regs[id].OTG_VUPDATE_PARAM = ctx->dcn_reg_offsets[regOTGid_OTG_VUPDATE_PARAM_BASE_IDX ] + regOTGid_OTG_VUPDATE_PARAM, dccg_regs[id].OTG_VREADY_PARAM = ctx->dcn_reg_offsets[regOTGid_OTG_VREADY_PARAM_BASE_IDX ] + regOTGid_OTG_VREADY_PARAM, dccg_regs[id].OTG_MASTER_UPDATE_LOCK = ctx->dcn_reg_offsets[regOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX ] + regOTGid_OTG_MASTER_UPDATE_LOCK, dccg_regs[id].OTG_GLOBAL_CONTROL0 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL0, dccg_regs[id].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL1, dccg_regs[id].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL2, dccg_regs[id].OTG_GLOBAL_CONTROL4 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL4_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL4, dccg_regs[id].OTG_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX ] + regOTGid_OTG_DOUBLE_BUFFER_CONTROL, dccg_regs[id].OTG_H_TOTAL = ctx->dcn_reg_offsets[regOTGid_OTG_H_TOTAL_BASE_IDX] + regOTGid_OTG_H_TOTAL , dccg_regs[id].OTG_H_BLANK_START_END = ctx->dcn_reg_offsets [regOTGid_OTG_H_BLANK_START_END_BASE_IDX] + regOTGid_OTG_H_BLANK_START_END , dccg_regs[id].OTG_H_SYNC_A = ctx->dcn_reg_offsets[regOTGid_OTG_H_SYNC_A_BASE_IDX ] + regOTGid_OTG_H_SYNC_A, dccg_regs[id].OTG_H_SYNC_A_CNTL = ctx ->dcn_reg_offsets[regOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX] + regOTGid_OTG_H_SYNC_A_CNTL , dccg_regs[id].OTG_H_TIMING_CNTL = ctx->dcn_reg_offsets[regOTGid_OTG_H_TIMING_CNTL_BASE_IDX ] + regOTGid_OTG_H_TIMING_CNTL, dccg_regs[id].OTG_V_TOTAL = ctx ->dcn_reg_offsets[regOTGid_OTG_V_TOTAL_BASE_IDX] + regOTGid_OTG_V_TOTAL , dccg_regs[id].OTG_V_BLANK_START_END = ctx->dcn_reg_offsets [regOTGid_OTG_V_BLANK_START_END_BASE_IDX] + regOTGid_OTG_V_BLANK_START_END , dccg_regs[id].OTG_V_SYNC_A = ctx->dcn_reg_offsets[regOTGid_OTG_V_SYNC_A_BASE_IDX ] + regOTGid_OTG_V_SYNC_A, dccg_regs[id].OTG_V_SYNC_A_CNTL = ctx ->dcn_reg_offsets[regOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX] + regOTGid_OTG_V_SYNC_A_CNTL , dccg_regs[id].OTG_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CONTROL_BASE_IDX ] + regOTGid_OTG_CONTROL, dccg_regs[id].OTG_STEREO_CONTROL = ctx ->dcn_reg_offsets[regOTGid_OTG_STEREO_CONTROL_BASE_IDX] + regOTGid_OTG_STEREO_CONTROL , dccg_regs[id].OTG_3D_STRUCTURE_CONTROL = ctx->dcn_reg_offsets [regOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX] + regOTGid_OTG_3D_STRUCTURE_CONTROL , dccg_regs[id].OTG_STEREO_STATUS = ctx->dcn_reg_offsets[regOTGid_OTG_STEREO_STATUS_BASE_IDX ] + regOTGid_OTG_STEREO_STATUS, dccg_regs[id].OTG_V_TOTAL_MAX = ctx->dcn_reg_offsets[regOTGid_OTG_V_TOTAL_MAX_BASE_IDX] + regOTGid_OTG_V_TOTAL_MAX, dccg_regs[id].OTG_V_TOTAL_MIN = ctx ->dcn_reg_offsets[regOTGid_OTG_V_TOTAL_MIN_BASE_IDX] + regOTGid_OTG_V_TOTAL_MIN , dccg_regs[id].OTG_V_TOTAL_CONTROL = ctx->dcn_reg_offsets [regOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX] + regOTGid_OTG_V_TOTAL_CONTROL , dccg_regs[id].OTG_TRIGA_CNTL = ctx->dcn_reg_offsets[regOTGid_OTG_TRIGA_CNTL_BASE_IDX ] + regOTGid_OTG_TRIGA_CNTL, dccg_regs[id].OTG_FORCE_COUNT_NOW_CNTL = ctx->dcn_reg_offsets[regOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX ] + regOTGid_OTG_FORCE_COUNT_NOW_CNTL, dccg_regs[id].OTG_STATIC_SCREEN_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX ] + regOTGid_OTG_STATIC_SCREEN_CONTROL, dccg_regs[id].OTG_STATUS_FRAME_COUNT = ctx->dcn_reg_offsets[regOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX ] + regOTGid_OTG_STATUS_FRAME_COUNT, dccg_regs[id].OTG_STATUS = ctx->dcn_reg_offsets[regOTGid_OTG_STATUS_BASE_IDX] + regOTGid_OTG_STATUS , dccg_regs[id].OTG_STATUS_POSITION = ctx->dcn_reg_offsets [regOTGid_OTG_STATUS_POSITION_BASE_IDX] + regOTGid_OTG_STATUS_POSITION , dccg_regs[id].OTG_NOM_VERT_POSITION = ctx->dcn_reg_offsets [regOTGid_OTG_NOM_VERT_POSITION_BASE_IDX] + regOTGid_OTG_NOM_VERT_POSITION , dccg_regs[id].OTG_M_CONST_DTO0 = ctx->dcn_reg_offsets[regOTGid_OTG_M_CONST_DTO0_BASE_IDX ] + regOTGid_OTG_M_CONST_DTO0, dccg_regs[id].OTG_M_CONST_DTO1 = ctx->dcn_reg_offsets[regOTGid_OTG_M_CONST_DTO1_BASE_IDX ] + regOTGid_OTG_M_CONST_DTO1, dccg_regs[id].OTG_CLOCK_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CLOCK_CONTROL_BASE_IDX ] + regOTGid_OTG_CLOCK_CONTROL, dccg_regs[id].OTG_VERTICAL_INTERRUPT0_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, dccg_regs[id].OTG_VERTICAL_INTERRUPT0_POSITION = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, dccg_regs[id]. OTG_VERTICAL_INTERRUPT1_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, dccg_regs[id].OTG_VERTICAL_INTERRUPT1_POSITION = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, dccg_regs[id]. OTG_VERTICAL_INTERRUPT2_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, dccg_regs[id].OTG_VERTICAL_INTERRUPT2_POSITION = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, dccg_regs[id]. OPTC_INPUT_CLOCK_CONTROL = ctx->dcn_reg_offsets[regODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX ] + regODMid_OPTC_INPUT_CLOCK_CONTROL, dccg_regs[id].OPTC_DATA_SOURCE_SELECT = ctx->dcn_reg_offsets[regODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX ] + regODMid_OPTC_DATA_SOURCE_SELECT, dccg_regs[id].OPTC_INPUT_GLOBAL_CONTROL = ctx->dcn_reg_offsets[regODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX ] + regODMid_OPTC_INPUT_GLOBAL_CONTROL, dccg_regs[id].CONTROL = ctx->dcn_reg_offsets[regVTGid_CONTROL_BASE_IDX] + regVTGid_CONTROL , dccg_regs[id].OTG_VERT_SYNC_CONTROL = ctx->dcn_reg_offsets [regOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX] + regOTGid_OTG_VERT_SYNC_CONTROL , dccg_regs[id].OTG_GSL_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_GSL_CONTROL_BASE_IDX ] + regOTGid_OTG_GSL_CONTROL, dccg_regs[id].OTG_CRC_CNTL = ctx ->dcn_reg_offsets[regOTGid_OTG_CRC_CNTL_BASE_IDX] + regOTGid_OTG_CRC_CNTL , dccg_regs[id].OTG_CRC0_DATA_RG = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_DATA_RG_BASE_IDX ] + regOTGid_OTG_CRC0_DATA_RG, dccg_regs[id].OTG_CRC0_DATA_B = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_DATA_B_BASE_IDX] + regOTGid_OTG_CRC0_DATA_B, dccg_regs[id].OTG_CRC0_WINDOWA_X_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX ] + regOTGid_OTG_CRC0_WINDOWA_X_CONTROL, dccg_regs[id].OTG_CRC0_WINDOWA_Y_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX ] + regOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, dccg_regs[id].OTG_CRC0_WINDOWB_X_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX ] + regOTGid_OTG_CRC0_WINDOWB_X_CONTROL, dccg_regs[id].OTG_CRC0_WINDOWB_Y_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX ] + regOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, dccg_regs[id].GSL_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1e2b, dccg_regs[id].OTG_TRIGA_MANUAL_TRIG = ctx->dcn_reg_offsets[regOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX ] + regOTGid_OTG_TRIGA_MANUAL_TRIG, dccg_regs[id].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL1, dccg_regs[id].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL2, dccg_regs[id].OTG_GSL_WINDOW_X = ctx->dcn_reg_offsets[regOTGid_OTG_GSL_WINDOW_X_BASE_IDX ] + regOTGid_OTG_GSL_WINDOW_X, dccg_regs[id].OTG_GSL_WINDOW_Y = ctx->dcn_reg_offsets[regOTGid_OTG_GSL_WINDOW_Y_BASE_IDX ] + regOTGid_OTG_GSL_WINDOW_Y, dccg_regs[id].OTG_VUPDATE_KEEPOUT = ctx->dcn_reg_offsets[regOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX ] + regOTGid_OTG_VUPDATE_KEEPOUT, dccg_regs[id].OTG_DSC_START_POSITION = ctx->dcn_reg_offsets[regOTGid_OTG_DSC_START_POSITION_BASE_IDX ] + regOTGid_OTG_DSC_START_POSITION, dccg_regs[id].OTG_DRR_TRIGGER_WINDOW = ctx->dcn_reg_offsets[regOTGid_OTG_DRR_TRIGGER_WINDOW_BASE_IDX ] + regOTGid_OTG_DRR_TRIGGER_WINDOW, dccg_regs[id].OTG_DRR_V_TOTAL_CHANGE = ctx->dcn_reg_offsets[regOTGid_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX ] + regOTGid_OTG_DRR_V_TOTAL_CHANGE, dccg_regs[id].OPTC_DATA_FORMAT_CONTROL = ctx->dcn_reg_offsets[regODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX ] + regODMid_OPTC_DATA_FORMAT_CONTROL, dccg_regs[id].OPTC_BYTES_PER_PIXEL = ctx->dcn_reg_offsets[regODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX ] + regODMid_OPTC_BYTES_PER_PIXEL, dccg_regs[id].OPTC_WIDTH_CONTROL = ctx->dcn_reg_offsets[regODMid_OPTC_WIDTH_CONTROL_BASE_IDX ] + regODMid_OPTC_WIDTH_CONTROL, dccg_regs[id].OPTC_MEMORY_CONFIG = ctx->dcn_reg_offsets[regODMid_OPTC_MEMORY_CONFIG_BASE_IDX ] + regODMid_OPTC_MEMORY_CONFIG, dccg_regs[id].OTG_DRR_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_DRR_CONTROL_BASE_IDX] + regOTGid_OTG_DRR_CONTROL )\ |
469 | OPTC_COMMON_REG_LIST_DCN3_2_RI(id)( dccg_regs[id].OTG_VSTARTUP_PARAM = ctx->dcn_reg_offsets[ regOTGid_OTG_VSTARTUP_PARAM_BASE_IDX] + regOTGid_OTG_VSTARTUP_PARAM , dccg_regs[id].OTG_VUPDATE_PARAM = ctx->dcn_reg_offsets[regOTGid_OTG_VUPDATE_PARAM_BASE_IDX ] + regOTGid_OTG_VUPDATE_PARAM, dccg_regs[id].OTG_VREADY_PARAM = ctx->dcn_reg_offsets[regOTGid_OTG_VREADY_PARAM_BASE_IDX ] + regOTGid_OTG_VREADY_PARAM, dccg_regs[id].OTG_MASTER_UPDATE_LOCK = ctx->dcn_reg_offsets[regOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX ] + regOTGid_OTG_MASTER_UPDATE_LOCK, dccg_regs[id].OTG_GLOBAL_CONTROL0 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL0, dccg_regs[id].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL1, dccg_regs[id].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL2, dccg_regs[id].OTG_GLOBAL_CONTROL4 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL4_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL4, dccg_regs[id].OTG_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX ] + regOTGid_OTG_DOUBLE_BUFFER_CONTROL, dccg_regs[id].OTG_H_TOTAL = ctx->dcn_reg_offsets[regOTGid_OTG_H_TOTAL_BASE_IDX] + regOTGid_OTG_H_TOTAL , dccg_regs[id].OTG_H_BLANK_START_END = ctx->dcn_reg_offsets [regOTGid_OTG_H_BLANK_START_END_BASE_IDX] + regOTGid_OTG_H_BLANK_START_END , dccg_regs[id].OTG_H_SYNC_A = ctx->dcn_reg_offsets[regOTGid_OTG_H_SYNC_A_BASE_IDX ] + regOTGid_OTG_H_SYNC_A, dccg_regs[id].OTG_H_SYNC_A_CNTL = ctx ->dcn_reg_offsets[regOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX] + regOTGid_OTG_H_SYNC_A_CNTL , dccg_regs[id].OTG_H_TIMING_CNTL = ctx->dcn_reg_offsets[regOTGid_OTG_H_TIMING_CNTL_BASE_IDX ] + regOTGid_OTG_H_TIMING_CNTL, dccg_regs[id].OTG_V_TOTAL = ctx ->dcn_reg_offsets[regOTGid_OTG_V_TOTAL_BASE_IDX] + regOTGid_OTG_V_TOTAL , dccg_regs[id].OTG_V_BLANK_START_END = ctx->dcn_reg_offsets [regOTGid_OTG_V_BLANK_START_END_BASE_IDX] + regOTGid_OTG_V_BLANK_START_END , dccg_regs[id].OTG_V_SYNC_A = ctx->dcn_reg_offsets[regOTGid_OTG_V_SYNC_A_BASE_IDX ] + regOTGid_OTG_V_SYNC_A, dccg_regs[id].OTG_V_SYNC_A_CNTL = ctx ->dcn_reg_offsets[regOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX] + regOTGid_OTG_V_SYNC_A_CNTL , dccg_regs[id].OTG_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CONTROL_BASE_IDX ] + regOTGid_OTG_CONTROL, dccg_regs[id].OTG_STEREO_CONTROL = ctx ->dcn_reg_offsets[regOTGid_OTG_STEREO_CONTROL_BASE_IDX] + regOTGid_OTG_STEREO_CONTROL , dccg_regs[id].OTG_3D_STRUCTURE_CONTROL = ctx->dcn_reg_offsets [regOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX] + regOTGid_OTG_3D_STRUCTURE_CONTROL , dccg_regs[id].OTG_STEREO_STATUS = ctx->dcn_reg_offsets[regOTGid_OTG_STEREO_STATUS_BASE_IDX ] + regOTGid_OTG_STEREO_STATUS, dccg_regs[id].OTG_V_TOTAL_MAX = ctx->dcn_reg_offsets[regOTGid_OTG_V_TOTAL_MAX_BASE_IDX] + regOTGid_OTG_V_TOTAL_MAX, dccg_regs[id].OTG_V_TOTAL_MIN = ctx ->dcn_reg_offsets[regOTGid_OTG_V_TOTAL_MIN_BASE_IDX] + regOTGid_OTG_V_TOTAL_MIN , dccg_regs[id].OTG_V_TOTAL_CONTROL = ctx->dcn_reg_offsets [regOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX] + regOTGid_OTG_V_TOTAL_CONTROL , dccg_regs[id].OTG_TRIGA_CNTL = ctx->dcn_reg_offsets[regOTGid_OTG_TRIGA_CNTL_BASE_IDX ] + regOTGid_OTG_TRIGA_CNTL, dccg_regs[id].OTG_FORCE_COUNT_NOW_CNTL = ctx->dcn_reg_offsets[regOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX ] + regOTGid_OTG_FORCE_COUNT_NOW_CNTL, dccg_regs[id].OTG_STATIC_SCREEN_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX ] + regOTGid_OTG_STATIC_SCREEN_CONTROL, dccg_regs[id].OTG_STATUS_FRAME_COUNT = ctx->dcn_reg_offsets[regOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX ] + regOTGid_OTG_STATUS_FRAME_COUNT, dccg_regs[id].OTG_STATUS = ctx->dcn_reg_offsets[regOTGid_OTG_STATUS_BASE_IDX] + regOTGid_OTG_STATUS , dccg_regs[id].OTG_STATUS_POSITION = ctx->dcn_reg_offsets [regOTGid_OTG_STATUS_POSITION_BASE_IDX] + regOTGid_OTG_STATUS_POSITION , dccg_regs[id].OTG_NOM_VERT_POSITION = ctx->dcn_reg_offsets [regOTGid_OTG_NOM_VERT_POSITION_BASE_IDX] + regOTGid_OTG_NOM_VERT_POSITION , dccg_regs[id].OTG_M_CONST_DTO0 = ctx->dcn_reg_offsets[regOTGid_OTG_M_CONST_DTO0_BASE_IDX ] + regOTGid_OTG_M_CONST_DTO0, dccg_regs[id].OTG_M_CONST_DTO1 = ctx->dcn_reg_offsets[regOTGid_OTG_M_CONST_DTO1_BASE_IDX ] + regOTGid_OTG_M_CONST_DTO1, dccg_regs[id].OTG_CLOCK_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CLOCK_CONTROL_BASE_IDX ] + regOTGid_OTG_CLOCK_CONTROL, dccg_regs[id].OTG_VERTICAL_INTERRUPT0_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, dccg_regs[id].OTG_VERTICAL_INTERRUPT0_POSITION = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, dccg_regs[id]. OTG_VERTICAL_INTERRUPT1_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, dccg_regs[id].OTG_VERTICAL_INTERRUPT1_POSITION = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, dccg_regs[id]. OTG_VERTICAL_INTERRUPT2_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, dccg_regs[id].OTG_VERTICAL_INTERRUPT2_POSITION = ctx->dcn_reg_offsets[regOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX ] + regOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, dccg_regs[id]. OPTC_INPUT_CLOCK_CONTROL = ctx->dcn_reg_offsets[regODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX ] + regODMid_OPTC_INPUT_CLOCK_CONTROL, dccg_regs[id].OPTC_DATA_SOURCE_SELECT = ctx->dcn_reg_offsets[regODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX ] + regODMid_OPTC_DATA_SOURCE_SELECT, dccg_regs[id].OPTC_INPUT_GLOBAL_CONTROL = ctx->dcn_reg_offsets[regODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX ] + regODMid_OPTC_INPUT_GLOBAL_CONTROL, dccg_regs[id].CONTROL = ctx->dcn_reg_offsets[regVTGid_CONTROL_BASE_IDX] + regVTGid_CONTROL , dccg_regs[id].OTG_VERT_SYNC_CONTROL = ctx->dcn_reg_offsets [regOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX] + regOTGid_OTG_VERT_SYNC_CONTROL , dccg_regs[id].OTG_GSL_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_GSL_CONTROL_BASE_IDX ] + regOTGid_OTG_GSL_CONTROL, dccg_regs[id].OTG_CRC_CNTL = ctx ->dcn_reg_offsets[regOTGid_OTG_CRC_CNTL_BASE_IDX] + regOTGid_OTG_CRC_CNTL , dccg_regs[id].OTG_CRC0_DATA_RG = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_DATA_RG_BASE_IDX ] + regOTGid_OTG_CRC0_DATA_RG, dccg_regs[id].OTG_CRC0_DATA_B = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_DATA_B_BASE_IDX] + regOTGid_OTG_CRC0_DATA_B, dccg_regs[id].OTG_CRC0_WINDOWA_X_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX ] + regOTGid_OTG_CRC0_WINDOWA_X_CONTROL, dccg_regs[id].OTG_CRC0_WINDOWA_Y_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX ] + regOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, dccg_regs[id].OTG_CRC0_WINDOWB_X_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX ] + regOTGid_OTG_CRC0_WINDOWB_X_CONTROL, dccg_regs[id].OTG_CRC0_WINDOWB_Y_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX ] + regOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, dccg_regs[id].GSL_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1e2b, dccg_regs[id].OTG_TRIGA_MANUAL_TRIG = ctx->dcn_reg_offsets[regOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX ] + regOTGid_OTG_TRIGA_MANUAL_TRIG, dccg_regs[id].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL1, dccg_regs[id].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets[regOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX ] + regOTGid_OTG_GLOBAL_CONTROL2, dccg_regs[id].OTG_GSL_WINDOW_X = ctx->dcn_reg_offsets[regOTGid_OTG_GSL_WINDOW_X_BASE_IDX ] + regOTGid_OTG_GSL_WINDOW_X, dccg_regs[id].OTG_GSL_WINDOW_Y = ctx->dcn_reg_offsets[regOTGid_OTG_GSL_WINDOW_Y_BASE_IDX ] + regOTGid_OTG_GSL_WINDOW_Y, dccg_regs[id].OTG_VUPDATE_KEEPOUT = ctx->dcn_reg_offsets[regOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX ] + regOTGid_OTG_VUPDATE_KEEPOUT, dccg_regs[id].OTG_DSC_START_POSITION = ctx->dcn_reg_offsets[regOTGid_OTG_DSC_START_POSITION_BASE_IDX ] + regOTGid_OTG_DSC_START_POSITION, dccg_regs[id].OTG_DRR_TRIGGER_WINDOW = ctx->dcn_reg_offsets[regOTGid_OTG_DRR_TRIGGER_WINDOW_BASE_IDX ] + regOTGid_OTG_DRR_TRIGGER_WINDOW, dccg_regs[id].OTG_DRR_V_TOTAL_CHANGE = ctx->dcn_reg_offsets[regOTGid_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX ] + regOTGid_OTG_DRR_V_TOTAL_CHANGE, dccg_regs[id].OPTC_DATA_FORMAT_CONTROL = ctx->dcn_reg_offsets[regODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX ] + regODMid_OPTC_DATA_FORMAT_CONTROL, dccg_regs[id].OPTC_BYTES_PER_PIXEL = ctx->dcn_reg_offsets[regODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX ] + regODMid_OPTC_BYTES_PER_PIXEL, dccg_regs[id].OPTC_WIDTH_CONTROL = ctx->dcn_reg_offsets[regODMid_OPTC_WIDTH_CONTROL_BASE_IDX ] + regODMid_OPTC_WIDTH_CONTROL, dccg_regs[id].OPTC_MEMORY_CONFIG = ctx->dcn_reg_offsets[regODMid_OPTC_MEMORY_CONFIG_BASE_IDX ] + regODMid_OPTC_MEMORY_CONFIG, dccg_regs[id].OTG_DRR_CONTROL = ctx->dcn_reg_offsets[regOTGid_OTG_DRR_CONTROL_BASE_IDX] + regOTGid_OTG_DRR_CONTROL ) |
470 | |
471 | static struct dcn_optc_registers optc_regs[4]; |
472 | |
473 | static const struct dcn_optc_shift optc_shift = { |
474 | OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT).VSTARTUP_START = 0x0, .VUPDATE_OFFSET = 0x0, .VUPDATE_WIDTH = 0x10, .VREADY_OFFSET = 0x0, .OTG_MASTER_UPDATE_LOCK = 0x0, . UPDATE_LOCK_STATUS = 0x8, .MASTER_UPDATE_LOCK_DB_START_X = 0x0 , .MASTER_UPDATE_LOCK_DB_END_X = 0x10, .MASTER_UPDATE_LOCK_DB_EN = 0x1f, .MASTER_UPDATE_LOCK_DB_START_Y = 0x0, .MASTER_UPDATE_LOCK_DB_END_Y = 0x10, .OTG_MASTER_UPDATE_LOCK_SEL = 0x19, .DIG_UPDATE_POSITION_X = 0x0, .DIG_UPDATE_POSITION_Y = 0x10, .OTG_UPDATE_PENDING = 0x0 , .OTG_H_TOTAL = 0x0, .OTG_H_BLANK_START = 0x0, .OTG_H_BLANK_END = 0x10, .OTG_H_SYNC_A_START = 0x0, .OTG_H_SYNC_A_END = 0x10, .OTG_H_SYNC_A_POL = 0x0, .OTG_V_TOTAL = 0x0, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END = 0x10, .OTG_V_SYNC_A_START = 0x0, . OTG_V_SYNC_A_END = 0x10, .OTG_V_SYNC_A_POL = 0x0, .OTG_V_SYNC_MODE = 0x8, .OTG_MASTER_EN = 0x0, .OTG_START_POINT_CNTL = 0xc, .OTG_DISABLE_POINT_CNTL = 0x8, .OTG_FIELD_NUMBER_CNTL = 0xd, .OTG_OUT_MUX = 0x14, .OTG_STEREO_EN = 0x18, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM = 0x0, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0xf, .OTG_STEREO_EYE_FLAG_POLARITY = 0x11, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x12, .OTG_STEREO_CURRENT_EYE = 0x0, .OTG_3D_STRUCTURE_EN = 0x0, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x8, .OTG_3D_STRUCTURE_STEREO_SEL_OVR = 0xc, .OTG_V_TOTAL_MAX = 0x0, .OTG_V_TOTAL_MIN = 0x0, .OTG_V_TOTAL_MIN_SEL = 0x0, .OTG_V_TOTAL_MAX_SEL = 0x1, .OTG_FORCE_LOCK_ON_EVENT = 0x4, .OTG_SET_V_TOTAL_MIN_MASK = 0x10, .OTG_VTOTAL_MID_REPLACING_MIN_EN = 0x3, .OTG_VTOTAL_MID_REPLACING_MAX_EN = 0x2, .OTG_FORCE_COUNT_NOW_CLEAR = 0x18, .OTG_FORCE_COUNT_NOW_MODE = 0x0, .OTG_FORCE_COUNT_NOW_OCCURRED = 0x10, .OTG_TRIGA_SOURCE_SELECT = 0x0, .OTG_TRIGA_SOURCE_PIPE_SELECT = 0x5, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x10, .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x12, .OTG_TRIGA_POLARITY_SELECT = 0x8, .OTG_TRIGA_FREQUENCY_SELECT = 0x14, .OTG_TRIGA_DELAY = 0x18, .OTG_TRIGA_CLEAR = 0x1f, .OTG_STATIC_SCREEN_EVENT_MASK = 0x0, .OTG_STATIC_SCREEN_FRAME_COUNT = 0x10, .OTG_FRAME_COUNT = 0x0, .OTG_V_BLANK = 0x0, .OTG_V_ACTIVE_DISP = 0x1, .OTG_HORZ_COUNT = 0x10, .OTG_VERT_COUNT = 0x0, .OTG_VERT_COUNT_NOM = 0x0, .OTG_M_CONST_DTO_PHASE = 0x0, .OTG_M_CONST_DTO_MODULO = 0x0, .OTG_BUSY = 0x10, .OTG_CLOCK_EN = 0x0, .OTG_CLOCK_ON = 0x8, .OTG_CLOCK_GATE_DIS = 0x1, .OTG_VERTICAL_INTERRUPT0_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT0_LINE_START = 0x0, .OTG_VERTICAL_INTERRUPT0_LINE_END = 0x10, .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT1_LINE_START = 0x0, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT2_LINE_START = 0x0, .OPTC_INPUT_CLK_EN = 0x1, .OPTC_INPUT_CLK_ON = 0x2, . OPTC_INPUT_CLK_GATE_DIS = 0x0, .OPTC_UNDERFLOW_OCCURRED_STATUS = 0xa, .OPTC_UNDERFLOW_CLEAR = 0xc, .VTG0_ENABLE = 0x1f, .VTG0_FP2 = 0x0, .VTG0_VCOUNT_INIT = 0x10, .OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED = 0x0, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = 0x8, .OTG_AUTO_FORCE_VSYNC_MODE = 0x10, .OTG_GSL0_EN = 0x0, .OTG_GSL1_EN = 0x1, .OTG_GSL2_EN = 0x2, .OTG_GSL_MASTER_EN = 0x3, .OTG_GSL_FORCE_DELAY = 0x10 , .OTG_GSL_CHECK_ALL_FIELDS = 0x1c, .OTG_CRC_CONT_EN = 0x4, . OTG_CRC0_SELECT = 0x14, .OTG_CRC_EN = 0x0, .CRC0_R_CR = 0x0, . CRC0_G_Y = 0x10, .CRC0_B_CB = 0x0, .OTG_CRC0_WINDOWA_X_START = 0x0, .OTG_CRC0_WINDOWA_X_END = 0x10, .OTG_CRC0_WINDOWA_Y_START = 0x0, .OTG_CRC0_WINDOWA_Y_END = 0x10, .OTG_CRC0_WINDOWB_X_START = 0x0, .OTG_CRC0_WINDOWB_X_END = 0x10, .OTG_CRC0_WINDOWB_Y_START = 0x0, .OTG_CRC0_WINDOWB_Y_END = 0x10, .OTG_TRIGA_MANUAL_TRIG = 0x0, .GSL0_READY_SOURCE_SEL = 0x0, .GSL1_READY_SOURCE_SEL = 0x4, .GSL2_READY_SOURCE_SEL = 0x8, .MANUAL_FLOW_CONTROL_SEL = 0x10, .GLOBAL_UPDATE_LOCK_EN = 0xa, .OTG_GSL_WINDOW_START_X = 0x0, .OTG_GSL_WINDOW_END_X = 0x10, .OTG_GSL_WINDOW_START_Y = 0x0, .OTG_GSL_WINDOW_END_Y = 0x10, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x1f, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0 , .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x10, .OTG_GSL_MASTER_MODE = 0x4, .OTG_MASTER_UPDATE_LOCK_GSL_EN = 0x1f, .OTG_DSC_START_POSITION_X = 0x0, .OTG_DSC_START_POSITION_LINE_NUM = 0x10, .OPTC_SEG0_SRC_SEL = 0x10, .OPTC_SEG1_SRC_SEL = 0x14, .OPTC_SEG2_SRC_SEL = 0x18 , .OPTC_SEG3_SRC_SEL = 0x1c, .OPTC_NUM_OF_INPUT_SEGMENT = 0x0 , .OPTC_MEM_SEL = 0x0, .OPTC_DATA_FORMAT = 0x0, .OPTC_DSC_MODE = 0x4, .OPTC_DSC_BYTES_PER_PIXEL = 0x0, .OPTC_DSC_SLICE_WIDTH = 0x10, .OPTC_SEGMENT_WIDTH = 0x0, .OTG_DRR_TRIGGER_WINDOW_START_X = 0x0, .OTG_DRR_TRIGGER_WINDOW_END_X = 0x10, .OTG_DRR_V_TOTAL_CHANGE_LIMIT = 0x0, .OTG_H_TIMING_DIV_MODE = 0x0, .OTG_H_TIMING_DIV_MODE_MANUAL = 0x8, .OTG_DRR_TIMING_DBUF_UPDATE_MODE = 0x18, .OTG_V_TOTAL_LAST_USED_BY_DRR = 0x10 |
475 | }; |
476 | |
477 | static const struct dcn_optc_mask optc_mask = { |
478 | OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK).VSTARTUP_START = 0x000003FFL, .VUPDATE_OFFSET = 0x0000FFFFL, .VUPDATE_WIDTH = 0x03FF0000L, .VREADY_OFFSET = 0x0000FFFFL, . OTG_MASTER_UPDATE_LOCK = 0x00000001L, .UPDATE_LOCK_STATUS = 0x00000100L , .MASTER_UPDATE_LOCK_DB_START_X = 0x00007FFFL, .MASTER_UPDATE_LOCK_DB_END_X = 0x7FFF0000L, .MASTER_UPDATE_LOCK_DB_EN = 0x80000000L, .MASTER_UPDATE_LOCK_DB_START_Y = 0x00007FFFL, .MASTER_UPDATE_LOCK_DB_END_Y = 0x7FFF0000L, . OTG_MASTER_UPDATE_LOCK_SEL = 0x0E000000L, .DIG_UPDATE_POSITION_X = 0x00007FFFL, .DIG_UPDATE_POSITION_Y = 0x7FFF0000L, .OTG_UPDATE_PENDING = 0x00000001L, .OTG_H_TOTAL = 0x00007FFFL, .OTG_H_BLANK_START = 0x00007FFFL, .OTG_H_BLANK_END = 0x7FFF0000L, .OTG_H_SYNC_A_START = 0x00007FFFL, .OTG_H_SYNC_A_END = 0x7FFF0000L, .OTG_H_SYNC_A_POL = 0x00000001L, .OTG_V_TOTAL = 0x00007FFFL, .OTG_V_BLANK_START = 0x00007FFFL, .OTG_V_BLANK_END = 0x7FFF0000L, .OTG_V_SYNC_A_START = 0x00007FFFL, .OTG_V_SYNC_A_END = 0x7FFF0000L, .OTG_V_SYNC_A_POL = 0x00000001L, .OTG_V_SYNC_MODE = 0x00000100L, .OTG_MASTER_EN = 0x00000001L, .OTG_START_POINT_CNTL = 0x00001000L, .OTG_DISABLE_POINT_CNTL = 0x00000300L, .OTG_FIELD_NUMBER_CNTL = 0x00002000L, .OTG_OUT_MUX = 0x00300000L, .OTG_STEREO_EN = 0x01000000L, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM = 0x00007FFFL, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0x00008000L , .OTG_STEREO_EYE_FLAG_POLARITY = 0x00020000L, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x00040000L, .OTG_STEREO_CURRENT_EYE = 0x00000001L, .OTG_3D_STRUCTURE_EN = 0x00000001L, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x00000300L , .OTG_3D_STRUCTURE_STEREO_SEL_OVR = 0x00001000L, .OTG_V_TOTAL_MAX = 0x00007FFFL, .OTG_V_TOTAL_MIN = 0x00007FFFL, .OTG_V_TOTAL_MIN_SEL = 0x00000001L, .OTG_V_TOTAL_MAX_SEL = 0x00000002L, .OTG_FORCE_LOCK_ON_EVENT = 0x00000010L, .OTG_SET_V_TOTAL_MIN_MASK = 0xFFFF0000L, .OTG_VTOTAL_MID_REPLACING_MIN_EN = 0x00000008L, .OTG_VTOTAL_MID_REPLACING_MAX_EN = 0x00000004L , .OTG_FORCE_COUNT_NOW_CLEAR = 0x01000000L, .OTG_FORCE_COUNT_NOW_MODE = 0x00000003L, .OTG_FORCE_COUNT_NOW_OCCURRED = 0x00010000L, . OTG_TRIGA_SOURCE_SELECT = 0x0000001FL, .OTG_TRIGA_SOURCE_PIPE_SELECT = 0x000000E0L, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x00030000L , .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x000C0000L, .OTG_TRIGA_POLARITY_SELECT = 0x00000700L, .OTG_TRIGA_FREQUENCY_SELECT = 0x00300000L, .OTG_TRIGA_DELAY = 0x1F000000L, .OTG_TRIGA_CLEAR = 0x80000000L, .OTG_STATIC_SCREEN_EVENT_MASK = 0x0000FFFFL, .OTG_STATIC_SCREEN_FRAME_COUNT = 0x00FF0000L, .OTG_FRAME_COUNT = 0x00FFFFFFL, .OTG_V_BLANK = 0x00000001L, . OTG_V_ACTIVE_DISP = 0x00000002L, .OTG_HORZ_COUNT = 0x7FFF0000L , .OTG_VERT_COUNT = 0x00007FFFL, .OTG_VERT_COUNT_NOM = 0x00007FFFL , .OTG_M_CONST_DTO_PHASE = 0xFFFFFFFFL, .OTG_M_CONST_DTO_MODULO = 0xFFFFFFFFL, .OTG_BUSY = 0x00010000L, .OTG_CLOCK_EN = 0x00000001L , .OTG_CLOCK_ON = 0x00000100L, .OTG_CLOCK_GATE_DIS = 0x00000002L , .OTG_VERTICAL_INTERRUPT0_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT0_LINE_START = 0x00007FFFL, .OTG_VERTICAL_INTERRUPT0_LINE_END = 0x7FFF0000L , .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT1_LINE_START = 0x00007FFFL, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x00000100L , .OTG_VERTICAL_INTERRUPT2_LINE_START = 0x00007FFFL, .OPTC_INPUT_CLK_EN = 0x00000002L, .OPTC_INPUT_CLK_ON = 0x00000004L, .OPTC_INPUT_CLK_GATE_DIS = 0x00000001L, .OPTC_UNDERFLOW_OCCURRED_STATUS = 0x00000400L , .OPTC_UNDERFLOW_CLEAR = 0x00001000L, .VTG0_ENABLE = 0x80000000L , .VTG0_FP2 = 0x00007FFFL, .VTG0_VCOUNT_INIT = 0x7FFF0000L, . OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED = 0x00000001L, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = 0x00000100L, .OTG_AUTO_FORCE_VSYNC_MODE = 0x00030000L, .OTG_GSL0_EN = 0x00000001L, .OTG_GSL1_EN = 0x00000002L, .OTG_GSL2_EN = 0x00000004L , .OTG_GSL_MASTER_EN = 0x00000008L, .OTG_GSL_FORCE_DELAY = 0x001F0000L , .OTG_GSL_CHECK_ALL_FIELDS = 0x10000000L, .OTG_CRC_CONT_EN = 0x00000010L, .OTG_CRC0_SELECT = 0x00700000L, .OTG_CRC_EN = 0x00000001L , .CRC0_R_CR = 0x0000FFFFL, .CRC0_G_Y = 0xFFFF0000L, .CRC0_B_CB = 0x0000FFFFL, .OTG_CRC0_WINDOWA_X_START = 0x00007FFFL, .OTG_CRC0_WINDOWA_X_END = 0x7FFF0000L, .OTG_CRC0_WINDOWA_Y_START = 0x00007FFFL, .OTG_CRC0_WINDOWA_Y_END = 0x7FFF0000L, .OTG_CRC0_WINDOWB_X_START = 0x00007FFFL, .OTG_CRC0_WINDOWB_X_END = 0x7FFF0000L, .OTG_CRC0_WINDOWB_Y_START = 0x00007FFFL, .OTG_CRC0_WINDOWB_Y_END = 0x7FFF0000L, .OTG_TRIGA_MANUAL_TRIG = 0x00000001L, .GSL0_READY_SOURCE_SEL = 0x00000007L, .GSL1_READY_SOURCE_SEL = 0x00000070L, .GSL2_READY_SOURCE_SEL = 0x00000700L, .MANUAL_FLOW_CONTROL_SEL = 0x00070000L, .GLOBAL_UPDATE_LOCK_EN = 0x00000400L, .OTG_GSL_WINDOW_START_X = 0x00007FFFL, .OTG_GSL_WINDOW_END_X = 0x7FFF0000L, .OTG_GSL_WINDOW_START_Y = 0x00007FFFL, .OTG_GSL_WINDOW_END_Y = 0x7FFF0000L, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x80000000L , .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0000FFFFL , .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x03FF0000L , .OTG_GSL_MASTER_MODE = 0x00000030L, .OTG_MASTER_UPDATE_LOCK_GSL_EN = 0x80000000L, .OTG_DSC_START_POSITION_X = 0x00007FFFL, .OTG_DSC_START_POSITION_LINE_NUM = 0x03FF0000L, .OPTC_SEG0_SRC_SEL = 0x000F0000L, .OPTC_SEG1_SRC_SEL = 0x00F00000L, .OPTC_SEG2_SRC_SEL = 0x0F000000L, .OPTC_SEG3_SRC_SEL = 0xF0000000L, .OPTC_NUM_OF_INPUT_SEGMENT = 0x00000003L, .OPTC_MEM_SEL = 0x0000FFFFL, .OPTC_DATA_FORMAT = 0x00000003L, .OPTC_DSC_MODE = 0x00000030L, .OPTC_DSC_BYTES_PER_PIXEL = 0x7FFFFFFFL, .OPTC_DSC_SLICE_WIDTH = 0x1FFF0000L, .OPTC_SEGMENT_WIDTH = 0x00001FFFL, .OTG_DRR_TRIGGER_WINDOW_START_X = 0x00007FFFL, .OTG_DRR_TRIGGER_WINDOW_END_X = 0x7FFF0000L, . OTG_DRR_V_TOTAL_CHANGE_LIMIT = 0x00007FFFL, .OTG_H_TIMING_DIV_MODE = 0x00000003L, .OTG_H_TIMING_DIV_MODE_MANUAL = 0x00000100L, . OTG_DRR_TIMING_DBUF_UPDATE_MODE = 0x03000000L, .OTG_V_TOTAL_LAST_USED_BY_DRR = 0x7FFF0000L |
479 | }; |
480 | |
481 | #define hubp_regs_init(id)( ( ( ( ( dccg_regs[id].DCHUBP_CNTL = ctx->dcn_reg_offsets [regHUBPid_DCHUBP_CNTL_BASE_IDX] + regHUBPid_DCHUBP_CNTL, dccg_regs [id].HUBPREQ_DEBUG_DB = ctx->dcn_reg_offsets[regHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX ] + regHUBPid_HUBPREQ_DEBUG_DB, dccg_regs[id].HUBPREQ_DEBUG = ctx->dcn_reg_offsets[regHUBPid_HUBPREQ_DEBUG_BASE_IDX] + regHUBPid_HUBPREQ_DEBUG , dccg_regs[id].DCSURF_ADDR_CONFIG = ctx->dcn_reg_offsets[ regHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX] + regHUBPid_DCSURF_ADDR_CONFIG , dccg_regs[id].DCSURF_TILING_CONFIG = ctx->dcn_reg_offsets [regHUBPid_DCSURF_TILING_CONFIG_BASE_IDX] + regHUBPid_DCSURF_TILING_CONFIG , dccg_regs[id].DCSURF_SURFACE_PITCH = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX] + regHUBPREQid_DCSURF_SURFACE_PITCH , dccg_regs[id].DCSURF_SURFACE_PITCH_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX] + regHUBPREQid_DCSURF_SURFACE_PITCH_C , dccg_regs[id].DCSURF_SURFACE_CONFIG = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX] + regHUBPid_DCSURF_SURFACE_CONFIG , dccg_regs[id].DCSURF_FLIP_CONTROL = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX] + regHUBPREQid_DCSURF_FLIP_CONTROL , dccg_regs[id].DCSURF_PRI_VIEWPORT_DIMENSION = ctx->dcn_reg_offsets [regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX] + regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION , dccg_regs[id].DCSURF_PRI_VIEWPORT_START = ctx->dcn_reg_offsets [regHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX] + regHUBPid_DCSURF_PRI_VIEWPORT_START , dccg_regs[id].DCSURF_SEC_VIEWPORT_DIMENSION = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX] + regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION , dccg_regs[id].DCSURF_SEC_VIEWPORT_START = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX] + regHUBPid_DCSURF_SEC_VIEWPORT_START , dccg_regs[id].DCSURF_PRI_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets [regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX] + regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C , dccg_regs[id].DCSURF_PRI_VIEWPORT_START_C = ctx->dcn_reg_offsets [regHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX] + regHUBPid_DCSURF_PRI_VIEWPORT_START_C , dccg_regs[id].DCSURF_SEC_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX] + regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C , dccg_regs[id].DCSURF_SEC_VIEWPORT_START_C = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX] + regHUBPid_DCSURF_SEC_VIEWPORT_START_C , dccg_regs[id].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = ctx-> dcn_reg_offsets[regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, dccg_regs [id].DCSURF_PRIMARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS , dccg_regs[id].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = ctx-> dcn_reg_offsets[regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, dccg_regs [id].DCSURF_SECONDARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX] + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS , dccg_regs[id].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = ctx ->dcn_reg_offsets[regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, dccg_regs [id].DCSURF_PRIMARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, dccg_regs[ id].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, dccg_regs [id].DCSURF_SECONDARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX] + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, dccg_regs [id].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, dccg_regs [id].DCSURF_PRIMARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C , dccg_regs[id].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = ctx ->dcn_reg_offsets[regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, dccg_regs [id].DCSURF_SECONDARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX] + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C , dccg_regs[id].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = ctx ->dcn_reg_offsets[regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, dccg_regs [id].DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, dccg_regs [id].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C , dccg_regs[id].DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = ctx ->dcn_reg_offsets[regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, dccg_regs [id].DCSURF_SURFACE_INUSE = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_INUSE, dccg_regs[id].DCSURF_SURFACE_INUSE_HIGH = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, dccg_regs[id].DCSURF_SURFACE_INUSE_C = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_INUSE_C, dccg_regs[id].DCSURF_SURFACE_INUSE_HIGH_C = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, dccg_regs[id].DCSURF_SURFACE_EARLIEST_INUSE = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, dccg_regs[id] .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX] + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH , dccg_regs[id].DCSURF_SURFACE_EARLIEST_INUSE_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX] + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C , dccg_regs[id].DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = ctx-> dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, dccg_regs [id].DCSURF_SURFACE_CONTROL = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_CONTROL, dccg_regs[id].DCSURF_SURFACE_FLIP_INTERRUPT = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT, dccg_regs[id] .HUBPRET_CONTROL = ctx->dcn_reg_offsets[regHUBPRETid_HUBPRET_CONTROL_BASE_IDX ] + regHUBPRETid_HUBPRET_CONTROL, dccg_regs[id].HUBPRET_READ_LINE_STATUS = ctx->dcn_reg_offsets[regHUBPRETid_HUBPRET_READ_LINE_STATUS_BASE_IDX ] + regHUBPRETid_HUBPRET_READ_LINE_STATUS, dccg_regs[id].DCN_EXPANSION_MODE = ctx->dcn_reg_offsets[regHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX ] + regHUBPREQid_DCN_EXPANSION_MODE, dccg_regs[id].DCHUBP_REQ_SIZE_CONFIG = ctx->dcn_reg_offsets[regHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX ] + regHUBPid_DCHUBP_REQ_SIZE_CONFIG, dccg_regs[id].DCHUBP_REQ_SIZE_CONFIG_C = ctx->dcn_reg_offsets[regHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX ] + regHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, dccg_regs[id].BLANK_OFFSET_0 = ctx->dcn_reg_offsets[regHUBPREQid_BLANK_OFFSET_0_BASE_IDX ] + regHUBPREQid_BLANK_OFFSET_0, dccg_regs[id].BLANK_OFFSET_1 = ctx->dcn_reg_offsets[regHUBPREQid_BLANK_OFFSET_1_BASE_IDX ] + regHUBPREQid_BLANK_OFFSET_1, dccg_regs[id].DST_DIMENSIONS = ctx->dcn_reg_offsets[regHUBPREQid_DST_DIMENSIONS_BASE_IDX ] + regHUBPREQid_DST_DIMENSIONS, dccg_regs[id].DST_AFTER_SCALER = ctx->dcn_reg_offsets[regHUBPREQid_DST_AFTER_SCALER_BASE_IDX ] + regHUBPREQid_DST_AFTER_SCALER, dccg_regs[id].VBLANK_PARAMETERS_0 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_0, dccg_regs[id].REF_FREQ_TO_PIX_FREQ = ctx->dcn_reg_offsets[regHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX ] + regHUBPREQid_REF_FREQ_TO_PIX_FREQ, dccg_regs[id].VBLANK_PARAMETERS_1 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_1, dccg_regs[id].VBLANK_PARAMETERS_3 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_3, dccg_regs[id].NOM_PARAMETERS_4 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_4_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_4, dccg_regs[id].NOM_PARAMETERS_5 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_5_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_5, dccg_regs[id].PER_LINE_DELIVERY_PRE = ctx->dcn_reg_offsets[regHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX ] + regHUBPREQid_PER_LINE_DELIVERY_PRE, dccg_regs[id].PER_LINE_DELIVERY = ctx->dcn_reg_offsets[regHUBPREQid_PER_LINE_DELIVERY_BASE_IDX ] + regHUBPREQid_PER_LINE_DELIVERY, dccg_regs[id].VBLANK_PARAMETERS_2 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_2, dccg_regs[id].VBLANK_PARAMETERS_4 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_4, dccg_regs[id].NOM_PARAMETERS_6 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_6_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_6, dccg_regs[id].NOM_PARAMETERS_7 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_7_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_7, dccg_regs[id].DCN_TTU_QOS_WM = ctx->dcn_reg_offsets[regHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX ] + regHUBPREQid_DCN_TTU_QOS_WM, dccg_regs[id].DCN_GLOBAL_TTU_CNTL = ctx->dcn_reg_offsets[regHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX ] + regHUBPREQid_DCN_GLOBAL_TTU_CNTL, dccg_regs[id].DCN_SURF0_TTU_CNTL0 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX ] + regHUBPREQid_DCN_SURF0_TTU_CNTL0, dccg_regs[id].DCN_SURF0_TTU_CNTL1 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX ] + regHUBPREQid_DCN_SURF0_TTU_CNTL1, dccg_regs[id].DCN_SURF1_TTU_CNTL0 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX ] + regHUBPREQid_DCN_SURF1_TTU_CNTL0, dccg_regs[id].DCN_SURF1_TTU_CNTL1 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX ] + regHUBPREQid_DCN_SURF1_TTU_CNTL1, dccg_regs[id].DCN_CUR0_TTU_CNTL0 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX ] + regHUBPREQid_DCN_CUR0_TTU_CNTL0, dccg_regs[id].DCN_CUR0_TTU_CNTL1 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX ] + regHUBPREQid_DCN_CUR0_TTU_CNTL1, dccg_regs[id].HUBP_CLK_CNTL = ctx->dcn_reg_offsets[regHUBPid_HUBP_CLK_CNTL_BASE_IDX] + regHUBPid_HUBP_CLK_CNTL ), ( dccg_regs[id].NOM_PARAMETERS_0 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_0_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_0, dccg_regs[id].NOM_PARAMETERS_1 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_1_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_1, dccg_regs[id].NOM_PARAMETERS_2 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_2_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_2, dccg_regs[id].NOM_PARAMETERS_3 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_3_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_3, dccg_regs[id].DCN_VM_MX_L1_TLB_CNTL = ctx->dcn_reg_offsets[regHUBPREQid_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX ] + regHUBPREQid_DCN_VM_MX_L1_TLB_CNTL ), dccg_regs[id].PREFETCH_SETTINGS = ctx->dcn_reg_offsets[regHUBPREQid_PREFETCH_SETTINGS_BASE_IDX ] + regHUBPREQid_PREFETCH_SETTINGS, dccg_regs[id].PREFETCH_SETTINGS_C = ctx->dcn_reg_offsets[regHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX ] + regHUBPREQid_PREFETCH_SETTINGS_C, dccg_regs[id].DCN_VM_SYSTEM_APERTURE_LOW_ADDR = ctx->dcn_reg_offsets[regHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX ] + regHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, dccg_regs[id ].DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = ctx->dcn_reg_offsets[ regHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX] + regHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR , dccg_regs[id].CURSOR_SETTINGS = ctx->dcn_reg_offsets[regHUBPREQid_CURSOR_SETTINGS_BASE_IDX ] + regHUBPREQid_CURSOR_SETTINGS, dccg_regs[id].CURSOR_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, dccg_regs[id]. CURSOR_SURFACE_ADDRESS = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX ] + regCURSOR0_id_CURSOR_SURFACE_ADDRESS, dccg_regs[id].CURSOR_SIZE = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_SIZE_BASE_IDX ] + regCURSOR0_id_CURSOR_SIZE, dccg_regs[id].CURSOR_CONTROL = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_CONTROL_BASE_IDX ] + regCURSOR0_id_CURSOR_CONTROL, dccg_regs[id].CURSOR_POSITION = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_POSITION_BASE_IDX ] + regCURSOR0_id_CURSOR_POSITION, dccg_regs[id].CURSOR_HOT_SPOT = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX ] + regCURSOR0_id_CURSOR_HOT_SPOT, dccg_regs[id].CURSOR_DST_OFFSET = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX ] + regCURSOR0_id_CURSOR_DST_OFFSET, dccg_regs[id].DMDATA_ADDRESS_HIGH = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX ] + regCURSOR0_id_DMDATA_ADDRESS_HIGH, dccg_regs[id].DMDATA_ADDRESS_LOW = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX ] + regCURSOR0_id_DMDATA_ADDRESS_LOW, dccg_regs[id].DMDATA_CNTL = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_CNTL_BASE_IDX ] + regCURSOR0_id_DMDATA_CNTL, dccg_regs[id].DMDATA_SW_CNTL = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX ] + regCURSOR0_id_DMDATA_SW_CNTL, dccg_regs[id].DMDATA_QOS_CNTL = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX ] + regCURSOR0_id_DMDATA_QOS_CNTL, dccg_regs[id].DMDATA_SW_DATA = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_SW_DATA_BASE_IDX ] + regCURSOR0_id_DMDATA_SW_DATA, dccg_regs[id].DMDATA_STATUS = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_STATUS_BASE_IDX ] + regCURSOR0_id_DMDATA_STATUS, dccg_regs[id].FLIP_PARAMETERS_0 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_0, dccg_regs[id].FLIP_PARAMETERS_1 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_1_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_1, dccg_regs[id].FLIP_PARAMETERS_2 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_2, dccg_regs[id].DCN_CUR1_TTU_CNTL0 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_CUR1_TTU_CNTL0_BASE_IDX ] + regHUBPREQid_DCN_CUR1_TTU_CNTL0, dccg_regs[id].DCN_CUR1_TTU_CNTL1 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_CUR1_TTU_CNTL1_BASE_IDX ] + regHUBPREQid_DCN_CUR1_TTU_CNTL1, dccg_regs[id].DCSURF_FLIP_CONTROL2 = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX ] + regHUBPREQid_DCSURF_FLIP_CONTROL2, dccg_regs[id].VMID_SETTINGS_0 = ctx->dcn_reg_offsets[regHUBPREQid_VMID_SETTINGS_0_BASE_IDX ] + regHUBPREQid_VMID_SETTINGS_0 ), dccg_regs[id].FLIP_PARAMETERS_3 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_3_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_3, dccg_regs[id].FLIP_PARAMETERS_4 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_4_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_4, dccg_regs[id].FLIP_PARAMETERS_5 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_5_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_5, dccg_regs[id].FLIP_PARAMETERS_6 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_6_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_6, dccg_regs[id].VBLANK_PARAMETERS_5 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_5_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_5, dccg_regs[id].VBLANK_PARAMETERS_6 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_6_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_6 ), dccg_regs[id].DCN_DMDATA_VM_CNTL = ctx->dcn_reg_offsets[regHUBPREQid_DCN_DMDATA_VM_CNTL_BASE_IDX ] + regHUBPREQid_DCN_DMDATA_VM_CNTL ), dccg_regs[id].DCHUBP_MALL_CONFIG = ctx->dcn_reg_offsets[regHUBPid_DCHUBP_MALL_CONFIG_BASE_IDX ] + regHUBPid_DCHUBP_MALL_CONFIG, dccg_regs[id].DCHUBP_VMPG_CONFIG = ctx->dcn_reg_offsets[regHUBPid_DCHUBP_VMPG_CONFIG_BASE_IDX ] + regHUBPid_DCHUBP_VMPG_CONFIG, dccg_regs[id].UCLK_PSTATE_FORCE = ctx->dcn_reg_offsets[regHUBPREQid_UCLK_PSTATE_FORCE_BASE_IDX ] + regHUBPREQid_UCLK_PSTATE_FORCE )\ |
482 | HUBP_REG_LIST_DCN32_RI(id)( ( ( ( ( dccg_regs[id].DCHUBP_CNTL = ctx->dcn_reg_offsets [regHUBPid_DCHUBP_CNTL_BASE_IDX] + regHUBPid_DCHUBP_CNTL, dccg_regs [id].HUBPREQ_DEBUG_DB = ctx->dcn_reg_offsets[regHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX ] + regHUBPid_HUBPREQ_DEBUG_DB, dccg_regs[id].HUBPREQ_DEBUG = ctx->dcn_reg_offsets[regHUBPid_HUBPREQ_DEBUG_BASE_IDX] + regHUBPid_HUBPREQ_DEBUG , dccg_regs[id].DCSURF_ADDR_CONFIG = ctx->dcn_reg_offsets[ regHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX] + regHUBPid_DCSURF_ADDR_CONFIG , dccg_regs[id].DCSURF_TILING_CONFIG = ctx->dcn_reg_offsets [regHUBPid_DCSURF_TILING_CONFIG_BASE_IDX] + regHUBPid_DCSURF_TILING_CONFIG , dccg_regs[id].DCSURF_SURFACE_PITCH = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX] + regHUBPREQid_DCSURF_SURFACE_PITCH , dccg_regs[id].DCSURF_SURFACE_PITCH_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX] + regHUBPREQid_DCSURF_SURFACE_PITCH_C , dccg_regs[id].DCSURF_SURFACE_CONFIG = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX] + regHUBPid_DCSURF_SURFACE_CONFIG , dccg_regs[id].DCSURF_FLIP_CONTROL = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX] + regHUBPREQid_DCSURF_FLIP_CONTROL , dccg_regs[id].DCSURF_PRI_VIEWPORT_DIMENSION = ctx->dcn_reg_offsets [regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX] + regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION , dccg_regs[id].DCSURF_PRI_VIEWPORT_START = ctx->dcn_reg_offsets [regHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX] + regHUBPid_DCSURF_PRI_VIEWPORT_START , dccg_regs[id].DCSURF_SEC_VIEWPORT_DIMENSION = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX] + regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION , dccg_regs[id].DCSURF_SEC_VIEWPORT_START = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX] + regHUBPid_DCSURF_SEC_VIEWPORT_START , dccg_regs[id].DCSURF_PRI_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets [regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX] + regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C , dccg_regs[id].DCSURF_PRI_VIEWPORT_START_C = ctx->dcn_reg_offsets [regHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX] + regHUBPid_DCSURF_PRI_VIEWPORT_START_C , dccg_regs[id].DCSURF_SEC_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX] + regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C , dccg_regs[id].DCSURF_SEC_VIEWPORT_START_C = ctx->dcn_reg_offsets [regHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX] + regHUBPid_DCSURF_SEC_VIEWPORT_START_C , dccg_regs[id].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = ctx-> dcn_reg_offsets[regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, dccg_regs [id].DCSURF_PRIMARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS , dccg_regs[id].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = ctx-> dcn_reg_offsets[regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, dccg_regs [id].DCSURF_SECONDARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX] + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS , dccg_regs[id].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = ctx ->dcn_reg_offsets[regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, dccg_regs [id].DCSURF_PRIMARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, dccg_regs[ id].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, dccg_regs [id].DCSURF_SECONDARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX] + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, dccg_regs [id].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, dccg_regs [id].DCSURF_PRIMARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C , dccg_regs[id].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = ctx ->dcn_reg_offsets[regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, dccg_regs [id].DCSURF_SECONDARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX] + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C , dccg_regs[id].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = ctx ->dcn_reg_offsets[regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, dccg_regs [id].DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX] + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, dccg_regs [id].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C , dccg_regs[id].DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = ctx ->dcn_reg_offsets[regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX ] + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, dccg_regs [id].DCSURF_SURFACE_INUSE = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_INUSE, dccg_regs[id].DCSURF_SURFACE_INUSE_HIGH = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, dccg_regs[id].DCSURF_SURFACE_INUSE_C = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_INUSE_C, dccg_regs[id].DCSURF_SURFACE_INUSE_HIGH_C = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, dccg_regs[id].DCSURF_SURFACE_EARLIEST_INUSE = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, dccg_regs[id] .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX] + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH , dccg_regs[id].DCSURF_SURFACE_EARLIEST_INUSE_C = ctx->dcn_reg_offsets [regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX] + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C , dccg_regs[id].DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = ctx-> dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, dccg_regs [id].DCSURF_SURFACE_CONTROL = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_CONTROL, dccg_regs[id].DCSURF_SURFACE_FLIP_INTERRUPT = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX ] + regHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT, dccg_regs[id] .HUBPRET_CONTROL = ctx->dcn_reg_offsets[regHUBPRETid_HUBPRET_CONTROL_BASE_IDX ] + regHUBPRETid_HUBPRET_CONTROL, dccg_regs[id].HUBPRET_READ_LINE_STATUS = ctx->dcn_reg_offsets[regHUBPRETid_HUBPRET_READ_LINE_STATUS_BASE_IDX ] + regHUBPRETid_HUBPRET_READ_LINE_STATUS, dccg_regs[id].DCN_EXPANSION_MODE = ctx->dcn_reg_offsets[regHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX ] + regHUBPREQid_DCN_EXPANSION_MODE, dccg_regs[id].DCHUBP_REQ_SIZE_CONFIG = ctx->dcn_reg_offsets[regHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX ] + regHUBPid_DCHUBP_REQ_SIZE_CONFIG, dccg_regs[id].DCHUBP_REQ_SIZE_CONFIG_C = ctx->dcn_reg_offsets[regHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX ] + regHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, dccg_regs[id].BLANK_OFFSET_0 = ctx->dcn_reg_offsets[regHUBPREQid_BLANK_OFFSET_0_BASE_IDX ] + regHUBPREQid_BLANK_OFFSET_0, dccg_regs[id].BLANK_OFFSET_1 = ctx->dcn_reg_offsets[regHUBPREQid_BLANK_OFFSET_1_BASE_IDX ] + regHUBPREQid_BLANK_OFFSET_1, dccg_regs[id].DST_DIMENSIONS = ctx->dcn_reg_offsets[regHUBPREQid_DST_DIMENSIONS_BASE_IDX ] + regHUBPREQid_DST_DIMENSIONS, dccg_regs[id].DST_AFTER_SCALER = ctx->dcn_reg_offsets[regHUBPREQid_DST_AFTER_SCALER_BASE_IDX ] + regHUBPREQid_DST_AFTER_SCALER, dccg_regs[id].VBLANK_PARAMETERS_0 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_0, dccg_regs[id].REF_FREQ_TO_PIX_FREQ = ctx->dcn_reg_offsets[regHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX ] + regHUBPREQid_REF_FREQ_TO_PIX_FREQ, dccg_regs[id].VBLANK_PARAMETERS_1 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_1, dccg_regs[id].VBLANK_PARAMETERS_3 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_3, dccg_regs[id].NOM_PARAMETERS_4 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_4_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_4, dccg_regs[id].NOM_PARAMETERS_5 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_5_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_5, dccg_regs[id].PER_LINE_DELIVERY_PRE = ctx->dcn_reg_offsets[regHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX ] + regHUBPREQid_PER_LINE_DELIVERY_PRE, dccg_regs[id].PER_LINE_DELIVERY = ctx->dcn_reg_offsets[regHUBPREQid_PER_LINE_DELIVERY_BASE_IDX ] + regHUBPREQid_PER_LINE_DELIVERY, dccg_regs[id].VBLANK_PARAMETERS_2 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_2, dccg_regs[id].VBLANK_PARAMETERS_4 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_4, dccg_regs[id].NOM_PARAMETERS_6 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_6_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_6, dccg_regs[id].NOM_PARAMETERS_7 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_7_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_7, dccg_regs[id].DCN_TTU_QOS_WM = ctx->dcn_reg_offsets[regHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX ] + regHUBPREQid_DCN_TTU_QOS_WM, dccg_regs[id].DCN_GLOBAL_TTU_CNTL = ctx->dcn_reg_offsets[regHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX ] + regHUBPREQid_DCN_GLOBAL_TTU_CNTL, dccg_regs[id].DCN_SURF0_TTU_CNTL0 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX ] + regHUBPREQid_DCN_SURF0_TTU_CNTL0, dccg_regs[id].DCN_SURF0_TTU_CNTL1 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX ] + regHUBPREQid_DCN_SURF0_TTU_CNTL1, dccg_regs[id].DCN_SURF1_TTU_CNTL0 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX ] + regHUBPREQid_DCN_SURF1_TTU_CNTL0, dccg_regs[id].DCN_SURF1_TTU_CNTL1 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX ] + regHUBPREQid_DCN_SURF1_TTU_CNTL1, dccg_regs[id].DCN_CUR0_TTU_CNTL0 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX ] + regHUBPREQid_DCN_CUR0_TTU_CNTL0, dccg_regs[id].DCN_CUR0_TTU_CNTL1 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX ] + regHUBPREQid_DCN_CUR0_TTU_CNTL1, dccg_regs[id].HUBP_CLK_CNTL = ctx->dcn_reg_offsets[regHUBPid_HUBP_CLK_CNTL_BASE_IDX] + regHUBPid_HUBP_CLK_CNTL ), ( dccg_regs[id].NOM_PARAMETERS_0 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_0_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_0, dccg_regs[id].NOM_PARAMETERS_1 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_1_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_1, dccg_regs[id].NOM_PARAMETERS_2 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_2_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_2, dccg_regs[id].NOM_PARAMETERS_3 = ctx->dcn_reg_offsets[regHUBPREQid_NOM_PARAMETERS_3_BASE_IDX ] + regHUBPREQid_NOM_PARAMETERS_3, dccg_regs[id].DCN_VM_MX_L1_TLB_CNTL = ctx->dcn_reg_offsets[regHUBPREQid_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX ] + regHUBPREQid_DCN_VM_MX_L1_TLB_CNTL ), dccg_regs[id].PREFETCH_SETTINGS = ctx->dcn_reg_offsets[regHUBPREQid_PREFETCH_SETTINGS_BASE_IDX ] + regHUBPREQid_PREFETCH_SETTINGS, dccg_regs[id].PREFETCH_SETTINGS_C = ctx->dcn_reg_offsets[regHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX ] + regHUBPREQid_PREFETCH_SETTINGS_C, dccg_regs[id].DCN_VM_SYSTEM_APERTURE_LOW_ADDR = ctx->dcn_reg_offsets[regHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX ] + regHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, dccg_regs[id ].DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = ctx->dcn_reg_offsets[ regHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX] + regHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR , dccg_regs[id].CURSOR_SETTINGS = ctx->dcn_reg_offsets[regHUBPREQid_CURSOR_SETTINGS_BASE_IDX ] + regHUBPREQid_CURSOR_SETTINGS, dccg_regs[id].CURSOR_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX ] + regCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, dccg_regs[id]. CURSOR_SURFACE_ADDRESS = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX ] + regCURSOR0_id_CURSOR_SURFACE_ADDRESS, dccg_regs[id].CURSOR_SIZE = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_SIZE_BASE_IDX ] + regCURSOR0_id_CURSOR_SIZE, dccg_regs[id].CURSOR_CONTROL = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_CONTROL_BASE_IDX ] + regCURSOR0_id_CURSOR_CONTROL, dccg_regs[id].CURSOR_POSITION = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_POSITION_BASE_IDX ] + regCURSOR0_id_CURSOR_POSITION, dccg_regs[id].CURSOR_HOT_SPOT = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX ] + regCURSOR0_id_CURSOR_HOT_SPOT, dccg_regs[id].CURSOR_DST_OFFSET = ctx->dcn_reg_offsets[regCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX ] + regCURSOR0_id_CURSOR_DST_OFFSET, dccg_regs[id].DMDATA_ADDRESS_HIGH = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX ] + regCURSOR0_id_DMDATA_ADDRESS_HIGH, dccg_regs[id].DMDATA_ADDRESS_LOW = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX ] + regCURSOR0_id_DMDATA_ADDRESS_LOW, dccg_regs[id].DMDATA_CNTL = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_CNTL_BASE_IDX ] + regCURSOR0_id_DMDATA_CNTL, dccg_regs[id].DMDATA_SW_CNTL = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX ] + regCURSOR0_id_DMDATA_SW_CNTL, dccg_regs[id].DMDATA_QOS_CNTL = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX ] + regCURSOR0_id_DMDATA_QOS_CNTL, dccg_regs[id].DMDATA_SW_DATA = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_SW_DATA_BASE_IDX ] + regCURSOR0_id_DMDATA_SW_DATA, dccg_regs[id].DMDATA_STATUS = ctx->dcn_reg_offsets[regCURSOR0_id_DMDATA_STATUS_BASE_IDX ] + regCURSOR0_id_DMDATA_STATUS, dccg_regs[id].FLIP_PARAMETERS_0 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_0, dccg_regs[id].FLIP_PARAMETERS_1 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_1_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_1, dccg_regs[id].FLIP_PARAMETERS_2 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_2, dccg_regs[id].DCN_CUR1_TTU_CNTL0 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_CUR1_TTU_CNTL0_BASE_IDX ] + regHUBPREQid_DCN_CUR1_TTU_CNTL0, dccg_regs[id].DCN_CUR1_TTU_CNTL1 = ctx->dcn_reg_offsets[regHUBPREQid_DCN_CUR1_TTU_CNTL1_BASE_IDX ] + regHUBPREQid_DCN_CUR1_TTU_CNTL1, dccg_regs[id].DCSURF_FLIP_CONTROL2 = ctx->dcn_reg_offsets[regHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX ] + regHUBPREQid_DCSURF_FLIP_CONTROL2, dccg_regs[id].VMID_SETTINGS_0 = ctx->dcn_reg_offsets[regHUBPREQid_VMID_SETTINGS_0_BASE_IDX ] + regHUBPREQid_VMID_SETTINGS_0 ), dccg_regs[id].FLIP_PARAMETERS_3 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_3_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_3, dccg_regs[id].FLIP_PARAMETERS_4 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_4_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_4, dccg_regs[id].FLIP_PARAMETERS_5 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_5_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_5, dccg_regs[id].FLIP_PARAMETERS_6 = ctx->dcn_reg_offsets[regHUBPREQid_FLIP_PARAMETERS_6_BASE_IDX ] + regHUBPREQid_FLIP_PARAMETERS_6, dccg_regs[id].VBLANK_PARAMETERS_5 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_5_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_5, dccg_regs[id].VBLANK_PARAMETERS_6 = ctx->dcn_reg_offsets[regHUBPREQid_VBLANK_PARAMETERS_6_BASE_IDX ] + regHUBPREQid_VBLANK_PARAMETERS_6 ), dccg_regs[id].DCN_DMDATA_VM_CNTL = ctx->dcn_reg_offsets[regHUBPREQid_DCN_DMDATA_VM_CNTL_BASE_IDX ] + regHUBPREQid_DCN_DMDATA_VM_CNTL ), dccg_regs[id].DCHUBP_MALL_CONFIG = ctx->dcn_reg_offsets[regHUBPid_DCHUBP_MALL_CONFIG_BASE_IDX ] + regHUBPid_DCHUBP_MALL_CONFIG, dccg_regs[id].DCHUBP_VMPG_CONFIG = ctx->dcn_reg_offsets[regHUBPid_DCHUBP_VMPG_CONFIG_BASE_IDX ] + regHUBPid_DCHUBP_VMPG_CONFIG, dccg_regs[id].UCLK_PSTATE_FORCE = ctx->dcn_reg_offsets[regHUBPREQid_UCLK_PSTATE_FORCE_BASE_IDX ] + regHUBPREQid_UCLK_PSTATE_FORCE ) |
483 | |
484 | static struct dcn_hubp2_registers hubp_regs[4]; |
485 | |
486 | |
487 | static const struct dcn_hubp2_shift hubp_shift = { |
488 | HUBP_MASK_SH_LIST_DCN32(__SHIFT).REFCYC_PER_VM_DMDATA = 0x0, .DMDATA_VM_FAULT_STATUS = 0x10, . DMDATA_VM_FAULT_STATUS_CLEAR = 0x14, .DMDATA_VM_UNDERFLOW_STATUS = 0x18, .DMDATA_VM_LATE_STATUS = 0x19, .DMDATA_VM_UNDERFLOW_STATUS_CLEAR = 0x1a, .DMDATA_VM_DONE = 0x1f, .HUBP_BLANK_EN = 0x0, .HUBP_TTU_DISABLE = 0xc, .HUBP_UNDERFLOW_STATUS = 0x1c, .HUBP_UNDERFLOW_CLEAR = 0x1f, .HUBP_NO_OUTSTANDING_REQ = 0x1, .HUBP_VTG_SEL = 0x4, . HUBP_UNBOUNDED_REQ_MODE = 0xa, .HUBP_IN_BLANK = 0x3, .HUBP_SOFT_RESET = 0x2, .NUM_PIPES = 0x0, .PIPE_INTERLEAVE = 0x6, .MAX_COMPRESSED_FRAGS = 0xc, .NUM_PKRS = 0x10, .SW_MODE = 0x0, .META_LINEAR = 0x9, .PIPE_ALIGNED = 0xb, .PITCH = 0x0, .META_PITCH = 0x10, .PITCH_C = 0x0, .META_PITCH_C = 0x10, .SURFACE_PIXEL_FORMAT = 0x0, .SURFACE_FLIP_TYPE = 0x1, .SURFACE_FLIP_MODE_FOR_STEREOSYNC = 0xc, .SURFACE_FLIP_IN_STEREOSYNC = 0x10, .SURFACE_FLIP_PENDING = 0x8, .SURFACE_UPDATE_LOCK = 0x0 , .PRI_VIEWPORT_WIDTH = 0x0, .PRI_VIEWPORT_HEIGHT = 0x10, .PRI_VIEWPORT_X_START = 0x0, .PRI_VIEWPORT_Y_START = 0x10, .SEC_VIEWPORT_WIDTH = 0x0 , .SEC_VIEWPORT_HEIGHT = 0x10, .SEC_VIEWPORT_X_START = 0x0, . SEC_VIEWPORT_Y_START = 0x10, .PRI_VIEWPORT_WIDTH_C = 0x0, .PRI_VIEWPORT_HEIGHT_C = 0x10, .PRI_VIEWPORT_X_START_C = 0x0, .PRI_VIEWPORT_Y_START_C = 0x10, .SEC_VIEWPORT_WIDTH_C = 0x0, .SEC_VIEWPORT_HEIGHT_C = 0x10, .SEC_VIEWPORT_X_START_C = 0x0, .SEC_VIEWPORT_Y_START_C = 0x10, .PRIMARY_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_SURFACE_ADDRESS = 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_SURFACE_ADDRESS = 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_META_SURFACE_ADDRESS = 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_META_SURFACE_ADDRESS = 0x0, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_SURFACE_ADDRESS_C = 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_SURFACE_ADDRESS_C = 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_META_SURFACE_ADDRESS_C = 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_META_SURFACE_ADDRESS_C = 0x0, .SURFACE_INUSE_ADDRESS = 0x0, .SURFACE_INUSE_ADDRESS_HIGH = 0x0, .SURFACE_INUSE_ADDRESS_C = 0x0, .SURFACE_INUSE_ADDRESS_HIGH_C = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C = 0x0, .PRIMARY_SURFACE_TMZ = 0x0, .PRIMARY_SURFACE_TMZ_C = 0x4 , .PRIMARY_META_SURFACE_TMZ = 0x10, .PRIMARY_META_SURFACE_TMZ_C = 0x11, .PRIMARY_SURFACE_DCC_EN = 0x1, .PRIMARY_SURFACE_DCC_IND_BLK = 0x2, .PRIMARY_SURFACE_DCC_IND_BLK_C = 0x5, .SECONDARY_SURFACE_TMZ = 0x8, .SECONDARY_SURFACE_TMZ_C = 0xc, .SECONDARY_META_SURFACE_TMZ = 0x12, .SECONDARY_META_SURFACE_TMZ_C = 0x13, .SECONDARY_SURFACE_DCC_EN = 0x9, .SECONDARY_SURFACE_DCC_IND_BLK = 0xa, .SECONDARY_SURFACE_DCC_IND_BLK_C = 0xd, .SURFACE_FLIP_INT_MASK = 0x0, .DET_BUF_PLANE1_BASE_ADDRESS = 0x4, .CROSSBAR_SRC_CB_B = 0x14, .CROSSBAR_SRC_CR_R = 0x16, .CROSSBAR_SRC_Y_G = 0x12, .CROSSBAR_SRC_ALPHA = 0x10, .PACK_3TO2_ELEMENT_DISABLE = 0xf, .DRQ_EXPANSION_MODE = 0x0, .PRQ_EXPANSION_MODE = 0x6, .MRQ_EXPANSION_MODE = 0x4, .CRQ_EXPANSION_MODE = 0x2, .CHUNK_SIZE = 0x8, .MIN_CHUNK_SIZE = 0xb, .META_CHUNK_SIZE = 0x10, .MIN_META_CHUNK_SIZE = 0x12, .DPTE_GROUP_SIZE = 0x14, .SWATH_HEIGHT = 0x0, .PTE_ROW_HEIGHT_LINEAR = 0x4, .CHUNK_SIZE_C = 0x8, .MIN_CHUNK_SIZE_C = 0xb, .META_CHUNK_SIZE_C = 0x10, .MIN_META_CHUNK_SIZE_C = 0x12, .DPTE_GROUP_SIZE_C = 0x14 , .SWATH_HEIGHT_C = 0x0, .PTE_ROW_HEIGHT_LINEAR_C = 0x4, .REFCYC_H_BLANK_END = 0x0, .DLG_V_BLANK_END = 0x10, .MIN_DST_Y_NEXT_START = 0x0, .REFCYC_PER_HTOTAL = 0x0, .REFCYC_X_AFTER_SCALER = 0x0, .DST_Y_AFTER_SCALER = 0x10, .DST_Y_PER_VM_VBLANK = 0x0, .DST_Y_PER_ROW_VBLANK = 0x8 , .REF_FREQ_TO_PIX_FREQ = 0x0, .REFCYC_PER_PTE_GROUP_VBLANK_L = 0x0, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x0, .DST_Y_PER_META_ROW_NOM_L = 0x0, .REFCYC_PER_META_CHUNK_NOM_L = 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_L = 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x10, .REFCYC_PER_LINE_DELIVERY_L = 0x0, .REFCYC_PER_LINE_DELIVERY_C = 0x10, .REFCYC_PER_PTE_GROUP_VBLANK_C = 0x0, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x0, .DST_Y_PER_META_ROW_NOM_C = 0x0, .REFCYC_PER_META_CHUNK_NOM_C = 0x0, .QoS_LEVEL_LOW_WM = 0x0, .QoS_LEVEL_HIGH_WM = 0x10, .MIN_TTU_VBLANK = 0x0, .QoS_LEVEL_FLIP = 0x1c, .ROW_TTU_MODE = 0x1b, .REFCYC_PER_REQ_DELIVERY = 0x0 , .QoS_LEVEL_FIXED = 0x18, .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE = 0x0, .HUBP_CLOCK_ENABLE = 0x0, .DST_Y_PER_PTE_ROW_NOM_L = 0x0 , .REFCYC_PER_PTE_GROUP_NOM_L = 0x0, .DST_Y_PER_PTE_ROW_NOM_C = 0x0, .REFCYC_PER_PTE_GROUP_NOM_C = 0x0, .ENABLE_L1_TLB = 0x0 , .SYSTEM_ACCESS_MODE = 0x3, .REFCYC_PER_REQ_DELIVERY = 0x0, . QoS_LEVEL_FIXED = 0x18, .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE = 0x0, .ROTATION_ANGLE = 0x8, .H_MIRROR_EN = 0xa, .ALPHA_PLANE_EN = 0xb, .DST_Y_PREFETCH = 0x18, .VRATIO_PREFETCH = 0x0, .VRATIO_PREFETCH_C = 0x0, .MC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x0, .MC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x0, .CURSOR0_DST_Y_OFFSET = 0x0, .CURSOR0_CHUNK_HDL_ADJUST = 0x8, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0, .CURSOR_SURFACE_ADDRESS = 0x0, .CURSOR_WIDTH = 0x10, .CURSOR_HEIGHT = 0x0, .CURSOR_MODE = 0x8, .CURSOR_REQ_MODE = 0x2, .CURSOR_2X_MAGNIFY = 0x4, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK = 0x18, .CURSOR_ENABLE = 0x0 , .CURSOR_X_POSITION = 0x10, .CURSOR_Y_POSITION = 0x0, .CURSOR_HOT_SPOT_X = 0x10, .CURSOR_HOT_SPOT_Y = 0x0, .CURSOR_DST_X_OFFSET = 0x0 , .DMDATA_ADDRESS_HIGH = 0x0, .DMDATA_MODE = 0x2, .DMDATA_UPDATED = 0x0, .DMDATA_REPEAT = 0x1, .DMDATA_SIZE = 0x10, .DMDATA_SW_UPDATED = 0x0, .DMDATA_SW_REPEAT = 0x1, .DMDATA_SW_SIZE = 0x10, .DMDATA_QOS_MODE = 0x0, .DMDATA_QOS_LEVEL = 0x4, .DMDATA_DL_DELTA = 0x10, .DMDATA_DONE = 0x0, .DST_Y_PER_VM_FLIP = 0x0, .DST_Y_PER_ROW_FLIP = 0x8, . REFCYC_PER_PTE_GROUP_FLIP_L = 0x0, .REFCYC_PER_META_CHUNK_FLIP_L = 0x0, .HUBP_VREADY_AT_OR_AFTER_VSYNC = 0x8, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x9, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS = 0x9, .SURFACE_GSL_ENABLE = 0x8, .SURFACE_TRIPLE_BUFFER_ENABLE = 0xa, .VMID = 0x0, .REFCYC_PER_VM_GROUP_FLIP = 0x0, .REFCYC_PER_VM_REQ_FLIP = 0x0, .REFCYC_PER_PTE_GROUP_FLIP_C = 0x0, .REFCYC_PER_META_CHUNK_FLIP_C = 0x0, .REFCYC_PER_VM_GROUP_VBLANK = 0x0, .REFCYC_PER_VM_REQ_VBLANK = 0x0, .VM_GROUP_SIZE = 0x18 , .USE_MALL_SEL = 0x0, .USE_MALL_FOR_CURSOR = 0x2, .VMPG_SIZE = 0x0, .PTE_BUFFER_MODE = 0x1, .BIGK_FRAGMENT_SIZE = 0x2, .FORCE_ONE_ROW_FOR_FRAME = 0x7, .DATA_UCLK_PSTATE_FORCE_EN = 0x0, .DATA_UCLK_PSTATE_FORCE_VALUE = 0x1, .CURSOR_UCLK_PSTATE_FORCE_EN = 0x2, .CURSOR_UCLK_PSTATE_FORCE_VALUE = 0x3 |
489 | }; |
490 | |
491 | static const struct dcn_hubp2_mask hubp_mask = { |
492 | HUBP_MASK_SH_LIST_DCN32(_MASK).REFCYC_PER_VM_DMDATA = 0x0000FFFFL, .DMDATA_VM_FAULT_STATUS = 0x000F0000L, .DMDATA_VM_FAULT_STATUS_CLEAR = 0x00100000L, .DMDATA_VM_UNDERFLOW_STATUS = 0x01000000L, .DMDATA_VM_LATE_STATUS = 0x02000000L, .DMDATA_VM_UNDERFLOW_STATUS_CLEAR = 0x04000000L, .DMDATA_VM_DONE = 0x80000000L, .HUBP_BLANK_EN = 0x00000001L, .HUBP_TTU_DISABLE = 0x00001000L, .HUBP_UNDERFLOW_STATUS = 0x70000000L, .HUBP_UNDERFLOW_CLEAR = 0x80000000L, .HUBP_NO_OUTSTANDING_REQ = 0x00000002L, .HUBP_VTG_SEL = 0x000000F0L, .HUBP_UNBOUNDED_REQ_MODE = 0x00000400L, .HUBP_IN_BLANK = 0x00000008L, .HUBP_SOFT_RESET = 0x00000004L, .NUM_PIPES = 0x00000007L, .PIPE_INTERLEAVE = 0x000000C0L , .MAX_COMPRESSED_FRAGS = 0x00003000L, .NUM_PKRS = 0x00070000L , .SW_MODE = 0x0000001FL, .META_LINEAR = 0x00000200L, .PIPE_ALIGNED = 0x00000800L, .PITCH = 0x00003FFFL, .META_PITCH = 0x3FFF0000L , .PITCH_C = 0x00003FFFL, .META_PITCH_C = 0x3FFF0000L, .SURFACE_PIXEL_FORMAT = 0x0000007FL, .SURFACE_FLIP_TYPE = 0x00000002L, .SURFACE_FLIP_MODE_FOR_STEREOSYNC = 0x00003000L, .SURFACE_FLIP_IN_STEREOSYNC = 0x00010000L, .SURFACE_FLIP_PENDING = 0x00000100L, .SURFACE_UPDATE_LOCK = 0x00000001L, .PRI_VIEWPORT_WIDTH = 0x00003FFFL, .PRI_VIEWPORT_HEIGHT = 0x3FFF0000L, .PRI_VIEWPORT_X_START = 0x00003FFFL, .PRI_VIEWPORT_Y_START = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH = 0x00003FFFL, .SEC_VIEWPORT_HEIGHT = 0x3FFF0000L, .SEC_VIEWPORT_X_START = 0x00003FFFL, .SEC_VIEWPORT_Y_START = 0x3FFF0000L, .PRI_VIEWPORT_WIDTH_C = 0x00003FFFL, .PRI_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .PRI_VIEWPORT_X_START_C = 0x00003FFFL, .PRI_VIEWPORT_Y_START_C = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH_C = 0x00003FFFL, .SEC_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .SEC_VIEWPORT_X_START_C = 0x00003FFFL, .SEC_VIEWPORT_Y_START_C = 0x3FFF0000L, .PRIMARY_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .PRIMARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS = 0xFFFFFFFFL, . SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .SECONDARY_META_SURFACE_ADDRESS = 0xFFFFFFFFL, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL , .PRIMARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, . PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL , .SECONDARY_META_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH = 0x0000FFFFL, .SURFACE_INUSE_ADDRESS_C = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, . SURFACE_EARLIEST_INUSE_ADDRESS = 0xFFFFFFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH = 0x0000FFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0xFFFFFFFFL , .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_SURFACE_TMZ = 0x00000001L, .PRIMARY_SURFACE_TMZ_C = 0x00000010L, .PRIMARY_META_SURFACE_TMZ = 0x00010000L, .PRIMARY_META_SURFACE_TMZ_C = 0x00020000L, .PRIMARY_SURFACE_DCC_EN = 0x00000002L, .PRIMARY_SURFACE_DCC_IND_BLK = 0x0000000CL, . PRIMARY_SURFACE_DCC_IND_BLK_C = 0x00000060L, .SECONDARY_SURFACE_TMZ = 0x00000100L, .SECONDARY_SURFACE_TMZ_C = 0x00001000L, .SECONDARY_META_SURFACE_TMZ = 0x00040000L, .SECONDARY_META_SURFACE_TMZ_C = 0x00080000L, . SECONDARY_SURFACE_DCC_EN = 0x00000200L, .SECONDARY_SURFACE_DCC_IND_BLK = 0x00000C00L, .SECONDARY_SURFACE_DCC_IND_BLK_C = 0x00006000L , .SURFACE_FLIP_INT_MASK = 0x00000001L, .DET_BUF_PLANE1_BASE_ADDRESS = 0x00007FF0L, .CROSSBAR_SRC_CB_B = 0x00300000L, .CROSSBAR_SRC_CR_R = 0x00C00000L, .CROSSBAR_SRC_Y_G = 0x000C0000L, .CROSSBAR_SRC_ALPHA = 0x00030000L, .PACK_3TO2_ELEMENT_DISABLE = 0x00008000L, .DRQ_EXPANSION_MODE = 0x00000003L, .PRQ_EXPANSION_MODE = 0x000000C0L, .MRQ_EXPANSION_MODE = 0x00000030L, .CRQ_EXPANSION_MODE = 0x0000000CL, .CHUNK_SIZE = 0x00000700L, .MIN_CHUNK_SIZE = 0x00001800L, .META_CHUNK_SIZE = 0x00030000L, .MIN_META_CHUNK_SIZE = 0x000C0000L, .DPTE_GROUP_SIZE = 0x00700000L, .SWATH_HEIGHT = 0x00000007L, .PTE_ROW_HEIGHT_LINEAR = 0x00000070L, .CHUNK_SIZE_C = 0x00000700L, .MIN_CHUNK_SIZE_C = 0x00001800L, .META_CHUNK_SIZE_C = 0x00030000L, .MIN_META_CHUNK_SIZE_C = 0x000C0000L, .DPTE_GROUP_SIZE_C = 0x00700000L, .SWATH_HEIGHT_C = 0x00000007L, .PTE_ROW_HEIGHT_LINEAR_C = 0x00000070L, .REFCYC_H_BLANK_END = 0x00001FFFL, .DLG_V_BLANK_END = 0x7FFF0000L, .MIN_DST_Y_NEXT_START = 0x0003FFFFL, .REFCYC_PER_HTOTAL = 0x001FFFFFL, .REFCYC_X_AFTER_SCALER = 0x00001FFFL, .DST_Y_AFTER_SCALER = 0x00070000L, .DST_Y_PER_VM_VBLANK = 0x0000007FL, .DST_Y_PER_ROW_VBLANK = 0x00003F00L, .REF_FREQ_TO_PIX_FREQ = 0x001FFFFFL, .REFCYC_PER_PTE_GROUP_VBLANK_L = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x007FFFFFL, .DST_Y_PER_META_ROW_NOM_L = 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_L = 0x007FFFFFL, . REFCYC_PER_LINE_DELIVERY_PRE_L = 0x00001FFFL, .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x1FFF0000L, .REFCYC_PER_LINE_DELIVERY_L = 0x00001FFFL, .REFCYC_PER_LINE_DELIVERY_C = 0x1FFF0000L, .REFCYC_PER_PTE_GROUP_VBLANK_C = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x007FFFFFL, .DST_Y_PER_META_ROW_NOM_C = 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_C = 0x007FFFFFL, . QoS_LEVEL_LOW_WM = 0x00003FFFL, .QoS_LEVEL_HIGH_WM = 0x3FFF0000L , .MIN_TTU_VBLANK = 0x00FFFFFFL, .QoS_LEVEL_FLIP = 0xF0000000L , .ROW_TTU_MODE = 0x08000000L, .REFCYC_PER_REQ_DELIVERY = 0x007FFFFFL , .QoS_LEVEL_FIXED = 0x0F000000L, .QoS_RAMP_DISABLE = 0x10000000L , .REFCYC_PER_REQ_DELIVERY_PRE = 0x007FFFFFL, .HUBP_CLOCK_ENABLE = 0x00000001L, .DST_Y_PER_PTE_ROW_NOM_L = 0x0001FFFFL, .REFCYC_PER_PTE_GROUP_NOM_L = 0x007FFFFFL, .DST_Y_PER_PTE_ROW_NOM_C = 0x0001FFFFL, .REFCYC_PER_PTE_GROUP_NOM_C = 0x007FFFFFL, .ENABLE_L1_TLB = 0x00000001L, .SYSTEM_ACCESS_MODE = 0x00000018L, .REFCYC_PER_REQ_DELIVERY = 0x007FFFFFL, .QoS_LEVEL_FIXED = 0x0F000000L, .QoS_RAMP_DISABLE = 0x10000000L, .REFCYC_PER_REQ_DELIVERY_PRE = 0x007FFFFFL, .ROTATION_ANGLE = 0x00000300L, .H_MIRROR_EN = 0x00000400L, .ALPHA_PLANE_EN = 0x00000800L, .DST_Y_PREFETCH = 0xFF000000L, .VRATIO_PREFETCH = 0x003FFFFFL, .VRATIO_PREFETCH_C = 0x003FFFFFL, .MC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x3FFFFFFFL , .MC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x3FFFFFFFL, .CURSOR0_DST_Y_OFFSET = 0x000000FFL, .CURSOR0_CHUNK_HDL_ADJUST = 0x00000300L, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .CURSOR_SURFACE_ADDRESS = 0xFFFFFFFFL, .CURSOR_WIDTH = 0x01FF0000L, .CURSOR_HEIGHT = 0x000001FFL, .CURSOR_MODE = 0x00000700L , .CURSOR_REQ_MODE = 0x00000004L, .CURSOR_2X_MAGNIFY = 0x00000010L , .CURSOR_PITCH = 0x00030000L, .CURSOR_LINES_PER_CHUNK = 0x1F000000L , .CURSOR_ENABLE = 0x00000001L, .CURSOR_X_POSITION = 0x3FFF0000L , .CURSOR_Y_POSITION = 0x00003FFFL, .CURSOR_HOT_SPOT_X = 0x00FF0000L , .CURSOR_HOT_SPOT_Y = 0x000000FFL, .CURSOR_DST_X_OFFSET = 0x00001FFFL , .DMDATA_ADDRESS_HIGH = 0x0000FFFFL, .DMDATA_MODE = 0x00000004L , .DMDATA_UPDATED = 0x00000001L, .DMDATA_REPEAT = 0x00000002L , .DMDATA_SIZE = 0x0FFF0000L, .DMDATA_SW_UPDATED = 0x00000001L , .DMDATA_SW_REPEAT = 0x00000002L, .DMDATA_SW_SIZE = 0x0FFF0000L , .DMDATA_QOS_MODE = 0x00000001L, .DMDATA_QOS_LEVEL = 0x000000F0L , .DMDATA_DL_DELTA = 0xFFFF0000L, .DMDATA_DONE = 0x00000001L, .DST_Y_PER_VM_FLIP = 0x0000007FL, .DST_Y_PER_ROW_FLIP = 0x00003F00L , .REFCYC_PER_PTE_GROUP_FLIP_L = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_FLIP_L = 0x007FFFFFL, .HUBP_VREADY_AT_OR_AFTER_VSYNC = 0x00000100L, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x00000200L, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS = 0x00000200L, .SURFACE_GSL_ENABLE = 0x00000100L, .SURFACE_TRIPLE_BUFFER_ENABLE = 0x00000400L, .VMID = 0x0000000FL, .REFCYC_PER_VM_GROUP_FLIP = 0x007FFFFFL, .REFCYC_PER_VM_REQ_FLIP = 0x007FFFFFL, .REFCYC_PER_PTE_GROUP_FLIP_C = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_FLIP_C = 0x007FFFFFL, . REFCYC_PER_VM_GROUP_VBLANK = 0x007FFFFFL, .REFCYC_PER_VM_REQ_VBLANK = 0x007FFFFFL, .VM_GROUP_SIZE = 0x07000000L, .USE_MALL_SEL = 0x00000003L, .USE_MALL_FOR_CURSOR = 0x00000004L, .VMPG_SIZE = 0x00000001L, .PTE_BUFFER_MODE = 0x00000002L, .BIGK_FRAGMENT_SIZE = 0x0000007CL, .FORCE_ONE_ROW_FOR_FRAME = 0x00000080L, .DATA_UCLK_PSTATE_FORCE_EN = 0x00000001L, .DATA_UCLK_PSTATE_FORCE_VALUE = 0x00000002L, . CURSOR_UCLK_PSTATE_FORCE_EN = 0x00000004L, .CURSOR_UCLK_PSTATE_FORCE_VALUE = 0x00000008L |
493 | }; |
494 | |
495 | static struct dcn_hubbub_registers hubbub_reg; |
496 | #define hubbub_reg_init()( dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = ctx->dcn_reg_offsets [2] + 0x04fe, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x0507, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0510, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x0519, dccg_regs.DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL = ctx->dcn_reg_offsets[2] + 0x0522, dccg_regs.DCHUBBUB_ARB_DRAM_STATE_CNTL = ctx->dcn_reg_offsets[2] + 0x04fc, dccg_regs.DCHUBBUB_ARB_SAT_LEVEL = ctx->dcn_reg_offsets[2] + 0x04fa, dccg_regs.DCHUBBUB_ARB_DF_REQ_OUTSTAND = ctx->dcn_reg_offsets[2] + 0x04f9, dccg_regs.DCHUBBUB_GLOBAL_TIMER_CNTL = ctx->dcn_reg_offsets[2] + 0x0525, dccg_regs.DCHUBBUB_SOFT_RESET = ctx->dcn_reg_offsets[2] + 0x0532, dccg_regs.DCHUBBUB_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x04b1, dccg_regs.DCN_VM_FB_LOCATION_BASE = ctx->dcn_reg_offsets[2] + 0x0475, dccg_regs.DCN_VM_FB_LOCATION_TOP = ctx->dcn_reg_offsets[2] + 0x0476, dccg_regs.DCN_VM_FB_OFFSET = ctx->dcn_reg_offsets[2] + 0x0477, dccg_regs.DCN_VM_AGP_BOT = ctx->dcn_reg_offsets[2] + 0x0478, dccg_regs.DCN_VM_AGP_TOP = ctx->dcn_reg_offsets[2] + 0x0479, dccg_regs.DCN_VM_AGP_BASE = ctx->dcn_reg_offsets[2] + 0x047a, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0501, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0502, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050a, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050b, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0513, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0514, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051c, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051d, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = ctx->dcn_reg_offsets[2] + 0x0505, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = ctx->dcn_reg_offsets[2] + 0x050e, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = ctx->dcn_reg_offsets[2] + 0x0517, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = ctx->dcn_reg_offsets[2] + 0x0520, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = ctx->dcn_reg_offsets[2] + 0x0506, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = ctx->dcn_reg_offsets[2] + 0x050f, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = ctx->dcn_reg_offsets[2] + 0x0518, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = ctx->dcn_reg_offsets[2] + 0x0521, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = ctx->dcn_reg_offsets[2] + 0x0500, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = ctx->dcn_reg_offsets[2] + 0x0509, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = ctx->dcn_reg_offsets[2] + 0x0512, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D = ctx->dcn_reg_offsets[2] + 0x051b, dccg_regs.DCHUBBUB_DET0_CTRL = ctx->dcn_reg_offsets[2] + 0x04bb, dccg_regs.DCHUBBUB_DET1_CTRL = ctx->dcn_reg_offsets[2] + 0x04bc, dccg_regs.DCHUBBUB_DET2_CTRL = ctx->dcn_reg_offsets[2] + 0x04bd, dccg_regs.DCHUBBUB_DET3_CTRL = ctx->dcn_reg_offsets[2] + 0x04be, dccg_regs.DCHUBBUB_COMPBUF_CTRL = ctx->dcn_reg_offsets[2] + 0x04ba, dccg_regs.COMPBUF_RESERVED_SPACE = ctx->dcn_reg_offsets[2] + 0x04c4, dccg_regs.DCHUBBUB_DEBUG_CTRL_0 = ctx->dcn_reg_offsets[2] + 0x04c5, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_CNTL = ctx->dcn_reg_offsets[2] + 0x04fd, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x04ff, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x0508, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0511, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051a, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0503, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050c, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0515, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051e, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0504, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050d, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0516, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051f, dccg_regs.DCN_VM_FAULT_ADDR_MSB = ctx->dcn_reg_offsets[2] + 0x05cd, dccg_regs.DCN_VM_FAULT_ADDR_LSB = ctx->dcn_reg_offsets[2] + 0x05ce, dccg_regs.DCN_VM_FAULT_CNTL = ctx->dcn_reg_offsets[2] + 0x05cb, dccg_regs.DCN_VM_FAULT_STATUS = ctx->dcn_reg_offsets[2] + 0x05cc )\ |
497 | HUBBUB_REG_LIST_DCN32_RI(0)( dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = ctx->dcn_reg_offsets [2] + 0x04fe, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x0507, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0510, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x0519, dccg_regs.DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL = ctx->dcn_reg_offsets[2] + 0x0522, dccg_regs.DCHUBBUB_ARB_DRAM_STATE_CNTL = ctx->dcn_reg_offsets[2] + 0x04fc, dccg_regs.DCHUBBUB_ARB_SAT_LEVEL = ctx->dcn_reg_offsets[2] + 0x04fa, dccg_regs.DCHUBBUB_ARB_DF_REQ_OUTSTAND = ctx->dcn_reg_offsets[2] + 0x04f9, dccg_regs.DCHUBBUB_GLOBAL_TIMER_CNTL = ctx->dcn_reg_offsets[2] + 0x0525, dccg_regs.DCHUBBUB_SOFT_RESET = ctx->dcn_reg_offsets[2] + 0x0532, dccg_regs.DCHUBBUB_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x04b1, dccg_regs.DCN_VM_FB_LOCATION_BASE = ctx->dcn_reg_offsets[2] + 0x0475, dccg_regs.DCN_VM_FB_LOCATION_TOP = ctx->dcn_reg_offsets[2] + 0x0476, dccg_regs.DCN_VM_FB_OFFSET = ctx->dcn_reg_offsets[2] + 0x0477, dccg_regs.DCN_VM_AGP_BOT = ctx->dcn_reg_offsets[2] + 0x0478, dccg_regs.DCN_VM_AGP_TOP = ctx->dcn_reg_offsets[2] + 0x0479, dccg_regs.DCN_VM_AGP_BASE = ctx->dcn_reg_offsets[2] + 0x047a, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0501, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0502, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050a, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050b, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0513, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0514, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051c, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051d, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = ctx->dcn_reg_offsets[2] + 0x0505, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = ctx->dcn_reg_offsets[2] + 0x050e, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = ctx->dcn_reg_offsets[2] + 0x0517, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = ctx->dcn_reg_offsets[2] + 0x0520, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = ctx->dcn_reg_offsets[2] + 0x0506, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = ctx->dcn_reg_offsets[2] + 0x050f, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = ctx->dcn_reg_offsets[2] + 0x0518, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = ctx->dcn_reg_offsets[2] + 0x0521, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = ctx->dcn_reg_offsets[2] + 0x0500, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = ctx->dcn_reg_offsets[2] + 0x0509, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = ctx->dcn_reg_offsets[2] + 0x0512, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D = ctx->dcn_reg_offsets[2] + 0x051b, dccg_regs.DCHUBBUB_DET0_CTRL = ctx->dcn_reg_offsets[2] + 0x04bb, dccg_regs.DCHUBBUB_DET1_CTRL = ctx->dcn_reg_offsets[2] + 0x04bc, dccg_regs.DCHUBBUB_DET2_CTRL = ctx->dcn_reg_offsets[2] + 0x04bd, dccg_regs.DCHUBBUB_DET3_CTRL = ctx->dcn_reg_offsets[2] + 0x04be, dccg_regs.DCHUBBUB_COMPBUF_CTRL = ctx->dcn_reg_offsets[2] + 0x04ba, dccg_regs.COMPBUF_RESERVED_SPACE = ctx->dcn_reg_offsets[2] + 0x04c4, dccg_regs.DCHUBBUB_DEBUG_CTRL_0 = ctx->dcn_reg_offsets[2] + 0x04c5, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_CNTL = ctx->dcn_reg_offsets[2] + 0x04fd, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x04ff, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x0508, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0511, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051a, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0503, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050c, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0515, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051e, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0504, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050d, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0516, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051f, dccg_regs.DCN_VM_FAULT_ADDR_MSB = ctx->dcn_reg_offsets[2] + 0x05cd, dccg_regs.DCN_VM_FAULT_ADDR_LSB = ctx->dcn_reg_offsets[2] + 0x05ce, dccg_regs.DCN_VM_FAULT_CNTL = ctx->dcn_reg_offsets[2] + 0x05cb, dccg_regs.DCN_VM_FAULT_STATUS = ctx->dcn_reg_offsets[2] + 0x05cc ) |
498 | |
499 | static const struct dcn_hubbub_shift hubbub_shift = { |
500 | HUBBUB_MASK_SH_LIST_DCN32(__SHIFT).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCHUBBUB_GLOBAL_SOFT_RESET = 0x0, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x8, .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE = 0x4, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x0, . DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x1, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE = 0x4, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x5, .DCHUBBUB_ARB_SAT_LEVEL = 0x0, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND = 0xa, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0, .FB_BASE = 0x0, . FB_TOP = 0x0, .FB_OFFSET = 0x0, .AGP_BOT = 0x0, .AGP_TOP = 0x0 , .AGP_BASE = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D = 0x0, .DET_DEPTH = 0x10, .DET0_SIZE = 0x0, .DET0_SIZE_CURRENT = 0x8, .DET1_SIZE = 0x0, .DET1_SIZE_CURRENT = 0x8, .DET2_SIZE = 0x0, .DET2_SIZE_CURRENT = 0x8, .DET3_SIZE = 0x0, .DET3_SIZE_CURRENT = 0x8, .COMPBUF_SIZE = 0x0, .COMPBUF_SIZE_CURRENT = 0x8, .COMPBUF_RESERVED_SPACE_64B = 0x0, .COMPBUF_RESERVED_SPACE_ZS = 0x10, .DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE = 0x8, .DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE = 0x9 , .DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST = 0xa, .DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE = 0xb, .DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A = 0x0, .DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B = 0x0, .DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C = 0x0, .DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D = 0x0, .DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A = 0x0, . DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B = 0x0, .DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C = 0x0, .DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D = 0x0, . DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A = 0x0, .DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B = 0x0, .DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C = 0x0, . DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D = 0x0, .DCN_VM_FAULT_ADDR_MSB = 0x0, .DCN_VM_FAULT_ADDR_LSB = 0x0, .DCN_VM_ERROR_STATUS_CLEAR = 0x0, .DCN_VM_ERROR_STATUS_MODE = 0x1, .DCN_VM_ERROR_INTERRUPT_ENABLE = 0x2, .DCN_VM_RANGE_FAULT_DISABLE = 0x8, .DCN_VM_PRQ_FAULT_DISABLE = 0x9, .DCN_VM_ERROR_STATUS = 0x0, .DCN_VM_ERROR_VMID = 0x10 , .DCN_VM_ERROR_TABLE_LEVEL = 0x18, .DCN_VM_ERROR_PIPE = 0x1a , .DCN_VM_ERROR_INTERRUPT_STATUS = 0x1f |
501 | }; |
502 | |
503 | static const struct dcn_hubbub_mask hubbub_mask = { |
504 | HUBBUB_MASK_SH_LIST_DCN32(_MASK).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0x00001000L, .DCHUBBUB_GLOBAL_SOFT_RESET = 0x00000001L, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x00000100L , .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE = 0x00000010L , .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x00000001L, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x00000002L, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE = 0x00000010L, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x00000020L , .DCHUBBUB_ARB_SAT_LEVEL = 0xFFFFFFFFL, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND = 0x000FFC00L, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x00003FFFL , .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x00003FFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x00003FFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x00003FFFL , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x0000FFFFL , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x0000FFFFL , .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = 0x0000FFFFL, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, . FB_BASE = 0x00FFFFFFL, .FB_TOP = 0x00FFFFFFL, .FB_OFFSET = 0x00FFFFFFL , .AGP_BOT = 0x00FFFFFFL, .AGP_TOP = 0x00FFFFFFL, .AGP_BASE = 0x00FFFFFFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = 0x000003FFL , .DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = 0x000003FFL , .DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = 0x000003FFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = 0x00003FFFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = 0x00003FFFL , .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = 0x00003FFFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D = 0x00003FFFL, .DET_DEPTH = 0x07FF0000L, .DET0_SIZE = 0x0000001FL , .DET0_SIZE_CURRENT = 0x00001F00L, .DET1_SIZE = 0x0000001FL, .DET1_SIZE_CURRENT = 0x00001F00L, .DET2_SIZE = 0x0000001FL, . DET2_SIZE_CURRENT = 0x00001F00L, .DET3_SIZE = 0x0000001FL, .DET3_SIZE_CURRENT = 0x00001F00L, .COMPBUF_SIZE = 0x0000001FL, .COMPBUF_SIZE_CURRENT = 0x00001F00L, .COMPBUF_RESERVED_SPACE_64B = 0x00000FFFL, .COMPBUF_RESERVED_SPACE_ZS = 0x0FFF0000L, .DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE = 0x00000100L, .DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE = 0x00000200L, .DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST = 0x00000400L, .DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE = 0x00000800L, .DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A = 0x00003FFFL , .DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B = 0x00003FFFL, .DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C = 0x00003FFFL, .DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D = 0x00003FFFL , .DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A = 0x0000FFFFL, .DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B = 0x0000FFFFL, . DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C = 0x0000FFFFL, .DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D = 0x0000FFFFL, .DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A = 0x0000FFFFL, .DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B = 0x0000FFFFL , .DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C = 0x0000FFFFL, .DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D = 0x0000FFFFL, . DCN_VM_FAULT_ADDR_MSB = 0x0000000FL, .DCN_VM_FAULT_ADDR_LSB = 0xFFFFFFFFL, .DCN_VM_ERROR_STATUS_CLEAR = 0x00000001L, .DCN_VM_ERROR_STATUS_MODE = 0x00000002L, .DCN_VM_ERROR_INTERRUPT_ENABLE = 0x00000004L, .DCN_VM_RANGE_FAULT_DISABLE = 0x00000100L, .DCN_VM_PRQ_FAULT_DISABLE = 0x00000200L, .DCN_VM_ERROR_STATUS = 0x0000FFFFL, .DCN_VM_ERROR_VMID = 0x000F0000L, .DCN_VM_ERROR_TABLE_LEVEL = 0x03000000L, .DCN_VM_ERROR_PIPE = 0x3C000000L, .DCN_VM_ERROR_INTERRUPT_STATUS = 0x80000000L |
505 | }; |
506 | |
507 | static struct dccg_registers dccg_regs; |
508 | |
509 | #define dccg_regs_init()( dccg_regs.DPPCLK_DTO_CTRL = ctx->dcn_reg_offsets[1] + 0x00b6 , dccg_regs.DPPCLK_DTO_PARAM[0] = ctx->dcn_reg_offsets[1] + 0x0099, dccg_regs.DPPCLK_DTO_PARAM[1] = ctx->dcn_reg_offsets [1] + 0x009a, dccg_regs.DPPCLK_DTO_PARAM[2] = ctx->dcn_reg_offsets [1] + 0x009b, dccg_regs.DPPCLK_DTO_PARAM[3] = ctx->dcn_reg_offsets [1] + 0x009c, dccg_regs.HDMICHARCLK_CLOCK_CNTL[0] = ctx->dcn_reg_offsets [2] + 0x004a, dccg_regs.PHYASYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0052, dccg_regs.PHYBSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0053, dccg_regs.PHYCSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0054, dccg_regs.PHYDSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0055, dccg_regs.PHYESYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0056, dccg_regs.DPSTREAMCLK_CNTL = ctx->dcn_reg_offsets [1] + 0x004a, dccg_regs.HDMISTREAMCLK_CNTL = ctx->dcn_reg_offsets [2] + 0x0059, dccg_regs.SYMCLK32_SE_CNTL = ctx->dcn_reg_offsets [1] + 0x0065, dccg_regs.SYMCLK32_LE_CNTL = ctx->dcn_reg_offsets [1] + 0x0066, dccg_regs.OTG_PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs.OTG_PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs.OTG_PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs.OTG_PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c, dccg_regs.DTBCLK_DTO_MODULO[0] = ctx->dcn_reg_offsets [2] + 0x001f, dccg_regs.DTBCLK_DTO_MODULO[1] = ctx->dcn_reg_offsets [2] + 0x0020, dccg_regs.DTBCLK_DTO_MODULO[2] = ctx->dcn_reg_offsets [2] + 0x0021, dccg_regs.DTBCLK_DTO_MODULO[3] = ctx->dcn_reg_offsets [2] + 0x0022, dccg_regs.DTBCLK_DTO_PHASE[0] = ctx->dcn_reg_offsets [2] + 0x0018, dccg_regs.DTBCLK_DTO_PHASE[1] = ctx->dcn_reg_offsets [2] + 0x0019, dccg_regs.DTBCLK_DTO_PHASE[2] = ctx->dcn_reg_offsets [2] + 0x001a, dccg_regs.DTBCLK_DTO_PHASE[3] = ctx->dcn_reg_offsets [2] + 0x001b, dccg_regs.DCCG_AUDIO_DTBCLK_DTO_MODULO = ctx-> dcn_reg_offsets[2] + 0x0062, dccg_regs.DCCG_AUDIO_DTBCLK_DTO_PHASE = ctx->dcn_reg_offsets[2] + 0x0061, dccg_regs.OTG_PIXEL_RATE_DIV = ctx->dcn_reg_offsets[1] + 0x006f, dccg_regs.DTBCLK_P_CNTL = ctx->dcn_reg_offsets[1] + 0x0068, dccg_regs.DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs.DENTIST_DISPCLK_CNTL = ctx->dcn_reg_offsets[1] + 0x0064 )\ |
510 | DCCG_REG_LIST_DCN32_RI()( dccg_regs.DPPCLK_DTO_CTRL = ctx->dcn_reg_offsets[1] + 0x00b6 , dccg_regs.DPPCLK_DTO_PARAM[0] = ctx->dcn_reg_offsets[1] + 0x0099, dccg_regs.DPPCLK_DTO_PARAM[1] = ctx->dcn_reg_offsets [1] + 0x009a, dccg_regs.DPPCLK_DTO_PARAM[2] = ctx->dcn_reg_offsets [1] + 0x009b, dccg_regs.DPPCLK_DTO_PARAM[3] = ctx->dcn_reg_offsets [1] + 0x009c, dccg_regs.HDMICHARCLK_CLOCK_CNTL[0] = ctx->dcn_reg_offsets [2] + 0x004a, dccg_regs.PHYASYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0052, dccg_regs.PHYBSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0053, dccg_regs.PHYCSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0054, dccg_regs.PHYDSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0055, dccg_regs.PHYESYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0056, dccg_regs.DPSTREAMCLK_CNTL = ctx->dcn_reg_offsets [1] + 0x004a, dccg_regs.HDMISTREAMCLK_CNTL = ctx->dcn_reg_offsets [2] + 0x0059, dccg_regs.SYMCLK32_SE_CNTL = ctx->dcn_reg_offsets [1] + 0x0065, dccg_regs.SYMCLK32_LE_CNTL = ctx->dcn_reg_offsets [1] + 0x0066, dccg_regs.OTG_PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs.OTG_PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs.OTG_PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs.OTG_PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c, dccg_regs.DTBCLK_DTO_MODULO[0] = ctx->dcn_reg_offsets [2] + 0x001f, dccg_regs.DTBCLK_DTO_MODULO[1] = ctx->dcn_reg_offsets [2] + 0x0020, dccg_regs.DTBCLK_DTO_MODULO[2] = ctx->dcn_reg_offsets [2] + 0x0021, dccg_regs.DTBCLK_DTO_MODULO[3] = ctx->dcn_reg_offsets [2] + 0x0022, dccg_regs.DTBCLK_DTO_PHASE[0] = ctx->dcn_reg_offsets [2] + 0x0018, dccg_regs.DTBCLK_DTO_PHASE[1] = ctx->dcn_reg_offsets [2] + 0x0019, dccg_regs.DTBCLK_DTO_PHASE[2] = ctx->dcn_reg_offsets [2] + 0x001a, dccg_regs.DTBCLK_DTO_PHASE[3] = ctx->dcn_reg_offsets [2] + 0x001b, dccg_regs.DCCG_AUDIO_DTBCLK_DTO_MODULO = ctx-> dcn_reg_offsets[2] + 0x0062, dccg_regs.DCCG_AUDIO_DTBCLK_DTO_PHASE = ctx->dcn_reg_offsets[2] + 0x0061, dccg_regs.OTG_PIXEL_RATE_DIV = ctx->dcn_reg_offsets[1] + 0x006f, dccg_regs.DTBCLK_P_CNTL = ctx->dcn_reg_offsets[1] + 0x0068, dccg_regs.DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs.DENTIST_DISPCLK_CNTL = ctx->dcn_reg_offsets[1] + 0x0064 ) |
511 | |
512 | static const struct dccg_shift dccg_shift = { |
513 | DCCG_MASK_SH_LIST_DCN32(__SHIFT).DPPCLK_DTO_ENABLE[0] = 0x0, .DPPCLK_DTO_DB_EN[0] = 0x1, .DPPCLK_DTO_ENABLE [1] = 0x4, .DPPCLK_DTO_DB_EN[1] = 0x5, .DPPCLK_DTO_ENABLE[2] = 0x8, .DPPCLK_DTO_DB_EN[2] = 0x9, .DPPCLK_DTO_ENABLE[3] = 0xc , .DPPCLK_DTO_DB_EN[3] = 0xd, .DPPCLK0_DTO_PHASE = 0x0, .DPPCLK0_DTO_MODULO = 0x10, .HDMICHARCLK0_EN = 0x0, .HDMICHARCLK0_SRC_SEL = 0x4, .PHYASYMCLK_FORCE_EN = 0x0, .PHYASYMCLK_FORCE_SRC_SEL = 0x4, .PHYBSYMCLK_FORCE_EN = 0x0, .PHYBSYMCLK_FORCE_SRC_SEL = 0x4, .PHYCSYMCLK_FORCE_EN = 0x0, .PHYCSYMCLK_FORCE_SRC_SEL = 0x4, .PHYDSYMCLK_FORCE_EN = 0x0, .PHYDSYMCLK_FORCE_SRC_SEL = 0x4, .PHYESYMCLK_FORCE_EN = 0x0, .PHYESYMCLK_FORCE_SRC_SEL = 0x4, .DPSTREAMCLK0_EN = 0x3, .DPSTREAMCLK1_EN = 0x7, .DPSTREAMCLK2_EN = 0xb, .DPSTREAMCLK3_EN = 0xf, .DPSTREAMCLK0_SRC_SEL = 0x0, . DPSTREAMCLK1_SRC_SEL = 0x4, .DPSTREAMCLK2_SRC_SEL = 0x8, .DPSTREAMCLK3_SRC_SEL = 0xc, .HDMISTREAMCLK0_EN = 0x3, .HDMISTREAMCLK0_DTO_FORCE_DIS = 0x4, .HDMISTREAMCLK0_SRC_SEL = 0x0, .SYMCLK32_SE0_SRC_SEL = 0x0, .SYMCLK32_SE1_SRC_SEL = 0x4, .SYMCLK32_SE2_SRC_SEL = 0x8 , .SYMCLK32_SE3_SRC_SEL = 0xc, .SYMCLK32_SE0_EN = 0x3, .SYMCLK32_SE1_EN = 0x7, .SYMCLK32_SE2_EN = 0xb, .SYMCLK32_SE3_EN = 0xf, .SYMCLK32_LE0_SRC_SEL = 0x0, .SYMCLK32_LE1_SRC_SEL = 0x4, .SYMCLK32_LE0_EN = 0x3, . SYMCLK32_LE1_EN = 0x7, .DTBCLK_DTO_ENABLE[0] = 0x3, .DTBCLK_DTO_ENABLE [1] = 0x3, .DTBCLK_DTO_ENABLE[2] = 0x3, .DTBCLK_DTO_ENABLE[3] = 0x3, .DTBCLKDTO_ENABLE_STATUS[0] = 0x6, .DTBCLKDTO_ENABLE_STATUS [1] = 0x6, .DTBCLKDTO_ENABLE_STATUS[2] = 0x6, .DTBCLKDTO_ENABLE_STATUS [3] = 0x6, .PIPE_DTO_SRC_SEL[0] = 0xc, .PIPE_DTO_SRC_SEL[1] = 0xc, .PIPE_DTO_SRC_SEL[2] = 0xc, .PIPE_DTO_SRC_SEL[3] = 0xc, .OTG_ADD_PIXEL[0] = 0x8, .OTG_ADD_PIXEL[1] = 0x8, .OTG_ADD_PIXEL [2] = 0x8, .OTG_ADD_PIXEL[3] = 0x8, .OTG0_PIXEL_RATE_DIVK1 = 0x0 , .OTG0_PIXEL_RATE_DIVK2 = 0x1, .OTG1_PIXEL_RATE_DIVK1 = 0x3, .OTG1_PIXEL_RATE_DIVK2 = 0x4, .OTG2_PIXEL_RATE_DIVK1 = 0x6, . OTG2_PIXEL_RATE_DIVK2 = 0x7, .OTG3_PIXEL_RATE_DIVK1 = 0x9, .OTG3_PIXEL_RATE_DIVK2 = 0xa, .OTG3_PIXEL_RATE_DIVK2 = 0xa, .DTBCLK_P0_SRC_SEL = 0x0 , .DTBCLK_P0_EN = 0x2, .DTBCLK_P1_SRC_SEL = 0x3, .DTBCLK_P1_EN = 0x5, .DTBCLK_P2_SRC_SEL = 0x6, .DTBCLK_P2_EN = 0x8, .DTBCLK_P3_SRC_SEL = 0x9, .DTBCLK_P3_EN = 0xb, .DCCG_AUDIO_DTO_SEL = 0x4, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x0, .DENTIST_DISPCLK_CHG_DONE = 0x13 |
514 | }; |
515 | |
516 | static const struct dccg_mask dccg_mask = { |
517 | DCCG_MASK_SH_LIST_DCN32(_MASK).DPPCLK_DTO_ENABLE[0] = 0x00000001L, .DPPCLK_DTO_DB_EN[0] = 0x00000002L , .DPPCLK_DTO_ENABLE[1] = 0x00000010L, .DPPCLK_DTO_DB_EN[1] = 0x00000020L, .DPPCLK_DTO_ENABLE[2] = 0x00000100L, .DPPCLK_DTO_DB_EN [2] = 0x00000200L, .DPPCLK_DTO_ENABLE[3] = 0x00001000L, .DPPCLK_DTO_DB_EN [3] = 0x00002000L, .DPPCLK0_DTO_PHASE = 0x000000FFL, .DPPCLK0_DTO_MODULO = 0x00FF0000L, .HDMICHARCLK0_EN = 0x00000001L, .HDMICHARCLK0_SRC_SEL = 0x00000070L, .PHYASYMCLK_FORCE_EN = 0x00000001L, .PHYASYMCLK_FORCE_SRC_SEL = 0x00000030L, .PHYBSYMCLK_FORCE_EN = 0x00000001L, .PHYBSYMCLK_FORCE_SRC_SEL = 0x00000030L, .PHYCSYMCLK_FORCE_EN = 0x00000001L, .PHYCSYMCLK_FORCE_SRC_SEL = 0x00000030L, .PHYDSYMCLK_FORCE_EN = 0x00000001L, .PHYDSYMCLK_FORCE_SRC_SEL = 0x00000030L, .PHYESYMCLK_FORCE_EN = 0x00000001L, .PHYESYMCLK_FORCE_SRC_SEL = 0x00000030L, .DPSTREAMCLK0_EN = 0x00000008L, .DPSTREAMCLK1_EN = 0x00000080L, .DPSTREAMCLK2_EN = 0x00000800L, .DPSTREAMCLK3_EN = 0x00008000L, .DPSTREAMCLK0_SRC_SEL = 0x00000007L, .DPSTREAMCLK1_SRC_SEL = 0x00000070L, .DPSTREAMCLK2_SRC_SEL = 0x00000700L, .DPSTREAMCLK3_SRC_SEL = 0x00007000L, .HDMISTREAMCLK0_EN = 0x00000008L, .HDMISTREAMCLK0_DTO_FORCE_DIS = 0x00000010L, .HDMISTREAMCLK0_SRC_SEL = 0x00000007L, .SYMCLK32_SE0_SRC_SEL = 0x00000007L, .SYMCLK32_SE1_SRC_SEL = 0x00000070L, .SYMCLK32_SE2_SRC_SEL = 0x00000700L, .SYMCLK32_SE3_SRC_SEL = 0x00007000L, .SYMCLK32_SE0_EN = 0x00000008L, .SYMCLK32_SE1_EN = 0x00000080L, .SYMCLK32_SE2_EN = 0x00000800L, .SYMCLK32_SE3_EN = 0x00008000L, .SYMCLK32_LE0_SRC_SEL = 0x00000007L, .SYMCLK32_LE1_SRC_SEL = 0x00000070L, .SYMCLK32_LE0_EN = 0x00000008L, .SYMCLK32_LE1_EN = 0x00000080L, .DTBCLK_DTO_ENABLE [0] = 0x00000008L, .DTBCLK_DTO_ENABLE[1] = 0x00000008L, .DTBCLK_DTO_ENABLE [2] = 0x00000008L, .DTBCLK_DTO_ENABLE[3] = 0x00000008L, .DTBCLKDTO_ENABLE_STATUS [0] = 0x00000040L, .DTBCLKDTO_ENABLE_STATUS[1] = 0x00000040L, .DTBCLKDTO_ENABLE_STATUS[2] = 0x00000040L, .DTBCLKDTO_ENABLE_STATUS [3] = 0x00000040L, .PIPE_DTO_SRC_SEL[0] = 0x00003000L, .PIPE_DTO_SRC_SEL [1] = 0x00003000L, .PIPE_DTO_SRC_SEL[2] = 0x00003000L, .PIPE_DTO_SRC_SEL [3] = 0x00003000L, .OTG_ADD_PIXEL[0] = 0x00000100L, .OTG_ADD_PIXEL [1] = 0x00000100L, .OTG_ADD_PIXEL[2] = 0x00000100L, .OTG_ADD_PIXEL [3] = 0x00000100L, .OTG0_PIXEL_RATE_DIVK1 = 0x00000001L, .OTG0_PIXEL_RATE_DIVK2 = 0x00000006L, .OTG1_PIXEL_RATE_DIVK1 = 0x00000008L, .OTG1_PIXEL_RATE_DIVK2 = 0x00000030L, .OTG2_PIXEL_RATE_DIVK1 = 0x00000040L, .OTG2_PIXEL_RATE_DIVK2 = 0x00000180L, .OTG3_PIXEL_RATE_DIVK1 = 0x00000200L, .OTG3_PIXEL_RATE_DIVK2 = 0x00000C00L, .OTG3_PIXEL_RATE_DIVK2 = 0x00000C00L, .DTBCLK_P0_SRC_SEL = 0x00000003L, .DTBCLK_P0_EN = 0x00000004L, .DTBCLK_P1_SRC_SEL = 0x00000018L, .DTBCLK_P1_EN = 0x00000020L, .DTBCLK_P2_SRC_SEL = 0x000000C0L, .DTBCLK_P2_EN = 0x00000100L, .DTBCLK_P3_SRC_SEL = 0x00000600L, .DTBCLK_P3_EN = 0x00000800L, .DCCG_AUDIO_DTO_SEL = 0x00000070L, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x00000007L, .DENTIST_DISPCLK_CHG_DONE = 0x00080000L |
518 | }; |
519 | |
520 | |
521 | #define SRII2(reg_name_pre, reg_name_post, id).reg_name_pre_reg_name_post[id] = ctx->dcn_reg_offsets[regreg_name_preid_reg_name_post_BASE_IDX ] + regreg_name_preid_reg_name_post\ |
522 | .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ctx->dcn_reg_offsets[reg ## reg_name_pre ## id ## _ ## reg_name_post ## _BASE_IDX] |
523 | ## id ## _ ## reg_name_post ## _BASE_IDX)ctx->dcn_reg_offsets[reg ## reg_name_pre ## id ## _ ## reg_name_post ## _BASE_IDX] + \ |
524 | reg ## reg_name_pre ## id ## _ ## reg_name_post |
525 | |
526 | |
527 | #define HWSEQ_DCN32_REG_LIST()dccg_regs.DCHUBBUB_GLOBAL_TIMER_CNTL = ctx->dcn_reg_offsets [2] + 0x0525, dccg_regs.DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets [2] + 0x1ede, dccg_regs.ODM_MEM_PWR_CTRL3 = ctx->dcn_reg_offsets [2] + 0x1e2f, dccg_regs.MMHUBBUB_MEM_PWR_CNTL = ctx->dcn_reg_offsets [2] + 0x0340, dccg_regs.DCCG_GATE_DISABLE_CNTL = ctx->dcn_reg_offsets [1] + 0x0074, dccg_regs.DCCG_GATE_DISABLE_CNTL2 = ctx->dcn_reg_offsets [1] + 0x007c, dccg_regs.DCFCLK_CNTL = ctx->dcn_reg_offsets [2] + 0x0534, dccg_regs.DC_MEM_GLOBAL_PWR_REQ_CNTL = ctx-> dcn_reg_offsets[1] + 0x0072, dccg_regs.PIXEL_RATE_CNTL[0] = ctx ->dcn_reg_offsets[1] + 0x0080, dccg_regs.PIXEL_RATE_CNTL[1 ] = ctx->dcn_reg_offsets[1] + 0x0084, dccg_regs.PIXEL_RATE_CNTL [2] = ctx->dcn_reg_offsets[1] + 0x0088, dccg_regs.PIXEL_RATE_CNTL [3] = ctx->dcn_reg_offsets[1] + 0x008c, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [0] = ctx->dcn_reg_offsets[1] + 0x0083, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [1] = ctx->dcn_reg_offsets[1] + 0x0087, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [2] = ctx->dcn_reg_offsets[1] + 0x008b, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [3] = ctx->dcn_reg_offsets[1] + 0x008f, dccg_regs.MICROSECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x007b, dccg_regs.MILLISECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x0070, dccg_regs.DISPCLK_FREQ_CHANGE_CNTL = ctx->dcn_reg_offsets[1] + 0x0071, dccg_regs.RBBMIF_TIMEOUT_DIS = ctx->dcn_reg_offsets[2] + 0x0183, dccg_regs.RBBMIF_TIMEOUT_DIS_2 = ctx->dcn_reg_offsets[2] + 0x0184, dccg_regs.DCHUBBUB_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x04b1, dccg_regs.DPP_TOP0_DPP_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x0cc9, dccg_regs.DPP_TOP0_DPP_CRC_VAL_B_A = ctx->dcn_reg_offsets[2] + 0x0cc8, dccg_regs.DPP_TOP0_DPP_CRC_VAL_R_G = ctx->dcn_reg_offsets[2] + 0x0cc7, dccg_regs.MPC_CRC_CTRL = ctx->dcn_reg_offsets[3] + 0x039a, dccg_regs.MPC_CRC_RESULT_GB = ctx->dcn_reg_offsets[3] + 0x039d, dccg_regs.MPC_CRC_RESULT_C = ctx->dcn_reg_offsets[3] + 0x039e, dccg_regs.MPC_CRC_RESULT_AR = ctx->dcn_reg_offsets[3] + 0x039c, dccg_regs.DOMAIN0_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0080, dccg_regs.DOMAIN1_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0082, dccg_regs.DOMAIN2_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0084, dccg_regs.DOMAIN3_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0086, dccg_regs.DOMAIN16_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0089, dccg_regs.DOMAIN17_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008b, dccg_regs.DOMAIN18_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008d, dccg_regs.DOMAIN19_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008f, dccg_regs.DOMAIN0_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0081, dccg_regs.DOMAIN1_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0083, dccg_regs.DOMAIN2_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0085, dccg_regs.DOMAIN3_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0087, dccg_regs.DOMAIN16_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008a, dccg_regs.DOMAIN17_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008c, dccg_regs.DOMAIN18_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008e, dccg_regs.DOMAIN19_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0090, dccg_regs.D1VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000c, dccg_regs.D2VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000e, dccg_regs.D3VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0038, dccg_regs.D4VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0039, dccg_regs.D5VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003a, dccg_regs.D6VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003b, dccg_regs.DC_IP_REQUEST_CNTL = ctx->dcn_reg_offsets[2] + 0x0095, dccg_regs.AZALIA_AUDIO_DTO = ctx->dcn_reg_offsets[2] + 0x03c3, dccg_regs.AZALIA_CONTROLLER_CLOCK_GATING = ctx->dcn_reg_offsets[2] + 0x03c2\ |
528 | SR(DCHUBBUB_GLOBAL_TIMER_CNTL)dccg_regs.DCHUBBUB_GLOBAL_TIMER_CNTL = ctx->dcn_reg_offsets [2] + 0x0525, \ |
529 | SR(DIO_MEM_PWR_CTRL)dccg_regs.DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1ede, \ |
530 | SR(ODM_MEM_PWR_CTRL3)dccg_regs.ODM_MEM_PWR_CTRL3 = ctx->dcn_reg_offsets[2] + 0x1e2f, \ |
531 | SR(MMHUBBUB_MEM_PWR_CNTL)dccg_regs.MMHUBBUB_MEM_PWR_CNTL = ctx->dcn_reg_offsets[2] + 0x0340, \ |
532 | SR(DCCG_GATE_DISABLE_CNTL)dccg_regs.DCCG_GATE_DISABLE_CNTL = ctx->dcn_reg_offsets[1] + 0x0074, \ |
533 | SR(DCCG_GATE_DISABLE_CNTL2)dccg_regs.DCCG_GATE_DISABLE_CNTL2 = ctx->dcn_reg_offsets[1 ] + 0x007c, \ |
534 | SR(DCFCLK_CNTL)dccg_regs.DCFCLK_CNTL = ctx->dcn_reg_offsets[2] + 0x0534,\ |
535 | SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)dccg_regs.DC_MEM_GLOBAL_PWR_REQ_CNTL = ctx->dcn_reg_offsets [1] + 0x0072, \ |
536 | SRII(PIXEL_RATE_CNTL, OTG, 0)dccg_regs.PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets[1] + 0x0080, \ |
537 | SRII(PIXEL_RATE_CNTL, OTG, 1)dccg_regs.PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets[1] + 0x0084,\ |
538 | SRII(PIXEL_RATE_CNTL, OTG, 2)dccg_regs.PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets[1] + 0x0088,\ |
539 | SRII(PIXEL_RATE_CNTL, OTG, 3)dccg_regs.PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets[1] + 0x008c,\ |
540 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0)dccg_regs.PHYPLL_PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0083,\ |
541 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1)dccg_regs.PHYPLL_PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0087,\ |
542 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2)dccg_regs.PHYPLL_PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x008b,\ |
543 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3)dccg_regs.PHYPLL_PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008f,\ |
544 | SR(MICROSECOND_TIME_BASE_DIV)dccg_regs.MICROSECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets [1] + 0x007b, \ |
545 | SR(MILLISECOND_TIME_BASE_DIV)dccg_regs.MILLISECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets [1] + 0x0070, \ |
546 | SR(DISPCLK_FREQ_CHANGE_CNTL)dccg_regs.DISPCLK_FREQ_CHANGE_CNTL = ctx->dcn_reg_offsets[ 1] + 0x0071, \ |
547 | SR(RBBMIF_TIMEOUT_DIS)dccg_regs.RBBMIF_TIMEOUT_DIS = ctx->dcn_reg_offsets[2] + 0x0183, \ |
548 | SR(RBBMIF_TIMEOUT_DIS_2)dccg_regs.RBBMIF_TIMEOUT_DIS_2 = ctx->dcn_reg_offsets[2] + 0x0184, \ |
549 | SR(DCHUBBUB_CRC_CTRL)dccg_regs.DCHUBBUB_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x04b1, \ |
550 | SR(DPP_TOP0_DPP_CRC_CTRL)dccg_regs.DPP_TOP0_DPP_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x0cc9, \ |
551 | SR(DPP_TOP0_DPP_CRC_VAL_B_A)dccg_regs.DPP_TOP0_DPP_CRC_VAL_B_A = ctx->dcn_reg_offsets[ 2] + 0x0cc8, \ |
552 | SR(DPP_TOP0_DPP_CRC_VAL_R_G)dccg_regs.DPP_TOP0_DPP_CRC_VAL_R_G = ctx->dcn_reg_offsets[ 2] + 0x0cc7, \ |
553 | SR(MPC_CRC_CTRL)dccg_regs.MPC_CRC_CTRL = ctx->dcn_reg_offsets[3] + 0x039a, \ |
554 | SR(MPC_CRC_RESULT_GB)dccg_regs.MPC_CRC_RESULT_GB = ctx->dcn_reg_offsets[3] + 0x039d, \ |
555 | SR(MPC_CRC_RESULT_C)dccg_regs.MPC_CRC_RESULT_C = ctx->dcn_reg_offsets[3] + 0x039e, \ |
556 | SR(MPC_CRC_RESULT_AR)dccg_regs.MPC_CRC_RESULT_AR = ctx->dcn_reg_offsets[3] + 0x039c, \ |
557 | SR(DOMAIN0_PG_CONFIG)dccg_regs.DOMAIN0_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0080, \ |
558 | SR(DOMAIN1_PG_CONFIG)dccg_regs.DOMAIN1_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0082, \ |
559 | SR(DOMAIN2_PG_CONFIG)dccg_regs.DOMAIN2_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0084, \ |
560 | SR(DOMAIN3_PG_CONFIG)dccg_regs.DOMAIN3_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0086, \ |
561 | SR(DOMAIN16_PG_CONFIG)dccg_regs.DOMAIN16_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0089, \ |
562 | SR(DOMAIN17_PG_CONFIG)dccg_regs.DOMAIN17_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008b, \ |
563 | SR(DOMAIN18_PG_CONFIG)dccg_regs.DOMAIN18_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008d, \ |
564 | SR(DOMAIN19_PG_CONFIG)dccg_regs.DOMAIN19_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008f, \ |
565 | SR(DOMAIN0_PG_STATUS)dccg_regs.DOMAIN0_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0081, \ |
566 | SR(DOMAIN1_PG_STATUS)dccg_regs.DOMAIN1_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0083, \ |
567 | SR(DOMAIN2_PG_STATUS)dccg_regs.DOMAIN2_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0085, \ |
568 | SR(DOMAIN3_PG_STATUS)dccg_regs.DOMAIN3_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0087, \ |
569 | SR(DOMAIN16_PG_STATUS)dccg_regs.DOMAIN16_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008a, \ |
570 | SR(DOMAIN17_PG_STATUS)dccg_regs.DOMAIN17_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008c, \ |
571 | SR(DOMAIN18_PG_STATUS)dccg_regs.DOMAIN18_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008e, \ |
572 | SR(DOMAIN19_PG_STATUS)dccg_regs.DOMAIN19_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0090, \ |
573 | SR(D1VGA_CONTROL)dccg_regs.D1VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000c, \ |
574 | SR(D2VGA_CONTROL)dccg_regs.D2VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000e, \ |
575 | SR(D3VGA_CONTROL)dccg_regs.D3VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0038, \ |
576 | SR(D4VGA_CONTROL)dccg_regs.D4VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0039, \ |
577 | SR(D5VGA_CONTROL)dccg_regs.D5VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003a, \ |
578 | SR(D6VGA_CONTROL)dccg_regs.D6VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003b, \ |
579 | SR(DC_IP_REQUEST_CNTL)dccg_regs.DC_IP_REQUEST_CNTL = ctx->dcn_reg_offsets[2] + 0x0095, \ |
580 | SR(AZALIA_AUDIO_DTO)dccg_regs.AZALIA_AUDIO_DTO = ctx->dcn_reg_offsets[2] + 0x03c3, \ |
581 | SR(AZALIA_CONTROLLER_CLOCK_GATING)dccg_regs.AZALIA_CONTROLLER_CLOCK_GATING = ctx->dcn_reg_offsets [2] + 0x03c2 |
582 | |
583 | static struct dce_hwseq_registers hwseq_reg; |
584 | |
585 | #define hwseq_reg_init()dccg_regs.DCHUBBUB_GLOBAL_TIMER_CNTL = ctx->dcn_reg_offsets [2] + 0x0525, dccg_regs.DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets [2] + 0x1ede, dccg_regs.ODM_MEM_PWR_CTRL3 = ctx->dcn_reg_offsets [2] + 0x1e2f, dccg_regs.MMHUBBUB_MEM_PWR_CNTL = ctx->dcn_reg_offsets [2] + 0x0340, dccg_regs.DCCG_GATE_DISABLE_CNTL = ctx->dcn_reg_offsets [1] + 0x0074, dccg_regs.DCCG_GATE_DISABLE_CNTL2 = ctx->dcn_reg_offsets [1] + 0x007c, dccg_regs.DCFCLK_CNTL = ctx->dcn_reg_offsets [2] + 0x0534, dccg_regs.DC_MEM_GLOBAL_PWR_REQ_CNTL = ctx-> dcn_reg_offsets[1] + 0x0072, dccg_regs.PIXEL_RATE_CNTL[0] = ctx ->dcn_reg_offsets[1] + 0x0080, dccg_regs.PIXEL_RATE_CNTL[1 ] = ctx->dcn_reg_offsets[1] + 0x0084, dccg_regs.PIXEL_RATE_CNTL [2] = ctx->dcn_reg_offsets[1] + 0x0088, dccg_regs.PIXEL_RATE_CNTL [3] = ctx->dcn_reg_offsets[1] + 0x008c, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [0] = ctx->dcn_reg_offsets[1] + 0x0083, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [1] = ctx->dcn_reg_offsets[1] + 0x0087, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [2] = ctx->dcn_reg_offsets[1] + 0x008b, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [3] = ctx->dcn_reg_offsets[1] + 0x008f, dccg_regs.MICROSECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x007b, dccg_regs.MILLISECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x0070, dccg_regs.DISPCLK_FREQ_CHANGE_CNTL = ctx->dcn_reg_offsets[1] + 0x0071, dccg_regs.RBBMIF_TIMEOUT_DIS = ctx->dcn_reg_offsets[2] + 0x0183, dccg_regs.RBBMIF_TIMEOUT_DIS_2 = ctx->dcn_reg_offsets[2] + 0x0184, dccg_regs.DCHUBBUB_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x04b1, dccg_regs.DPP_TOP0_DPP_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x0cc9, dccg_regs.DPP_TOP0_DPP_CRC_VAL_B_A = ctx->dcn_reg_offsets[2] + 0x0cc8, dccg_regs.DPP_TOP0_DPP_CRC_VAL_R_G = ctx->dcn_reg_offsets[2] + 0x0cc7, dccg_regs.MPC_CRC_CTRL = ctx->dcn_reg_offsets[3] + 0x039a, dccg_regs.MPC_CRC_RESULT_GB = ctx->dcn_reg_offsets[3] + 0x039d, dccg_regs.MPC_CRC_RESULT_C = ctx->dcn_reg_offsets[3] + 0x039e, dccg_regs.MPC_CRC_RESULT_AR = ctx->dcn_reg_offsets[3] + 0x039c, dccg_regs.DOMAIN0_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0080, dccg_regs.DOMAIN1_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0082, dccg_regs.DOMAIN2_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0084, dccg_regs.DOMAIN3_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0086, dccg_regs.DOMAIN16_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0089, dccg_regs.DOMAIN17_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008b, dccg_regs.DOMAIN18_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008d, dccg_regs.DOMAIN19_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008f, dccg_regs.DOMAIN0_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0081, dccg_regs.DOMAIN1_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0083, dccg_regs.DOMAIN2_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0085, dccg_regs.DOMAIN3_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0087, dccg_regs.DOMAIN16_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008a, dccg_regs.DOMAIN17_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008c, dccg_regs.DOMAIN18_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008e, dccg_regs.DOMAIN19_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0090, dccg_regs.D1VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000c, dccg_regs.D2VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000e, dccg_regs.D3VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0038, dccg_regs.D4VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0039, dccg_regs.D5VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003a, dccg_regs.D6VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003b, dccg_regs.DC_IP_REQUEST_CNTL = ctx->dcn_reg_offsets[2] + 0x0095, dccg_regs.AZALIA_AUDIO_DTO = ctx->dcn_reg_offsets[2] + 0x03c3, dccg_regs.AZALIA_CONTROLLER_CLOCK_GATING = ctx->dcn_reg_offsets[2] + 0x03c2\ |
586 | HWSEQ_DCN32_REG_LIST()dccg_regs.DCHUBBUB_GLOBAL_TIMER_CNTL = ctx->dcn_reg_offsets [2] + 0x0525, dccg_regs.DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets [2] + 0x1ede, dccg_regs.ODM_MEM_PWR_CTRL3 = ctx->dcn_reg_offsets [2] + 0x1e2f, dccg_regs.MMHUBBUB_MEM_PWR_CNTL = ctx->dcn_reg_offsets [2] + 0x0340, dccg_regs.DCCG_GATE_DISABLE_CNTL = ctx->dcn_reg_offsets [1] + 0x0074, dccg_regs.DCCG_GATE_DISABLE_CNTL2 = ctx->dcn_reg_offsets [1] + 0x007c, dccg_regs.DCFCLK_CNTL = ctx->dcn_reg_offsets [2] + 0x0534, dccg_regs.DC_MEM_GLOBAL_PWR_REQ_CNTL = ctx-> dcn_reg_offsets[1] + 0x0072, dccg_regs.PIXEL_RATE_CNTL[0] = ctx ->dcn_reg_offsets[1] + 0x0080, dccg_regs.PIXEL_RATE_CNTL[1 ] = ctx->dcn_reg_offsets[1] + 0x0084, dccg_regs.PIXEL_RATE_CNTL [2] = ctx->dcn_reg_offsets[1] + 0x0088, dccg_regs.PIXEL_RATE_CNTL [3] = ctx->dcn_reg_offsets[1] + 0x008c, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [0] = ctx->dcn_reg_offsets[1] + 0x0083, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [1] = ctx->dcn_reg_offsets[1] + 0x0087, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [2] = ctx->dcn_reg_offsets[1] + 0x008b, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [3] = ctx->dcn_reg_offsets[1] + 0x008f, dccg_regs.MICROSECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x007b, dccg_regs.MILLISECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x0070, dccg_regs.DISPCLK_FREQ_CHANGE_CNTL = ctx->dcn_reg_offsets[1] + 0x0071, dccg_regs.RBBMIF_TIMEOUT_DIS = ctx->dcn_reg_offsets[2] + 0x0183, dccg_regs.RBBMIF_TIMEOUT_DIS_2 = ctx->dcn_reg_offsets[2] + 0x0184, dccg_regs.DCHUBBUB_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x04b1, dccg_regs.DPP_TOP0_DPP_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x0cc9, dccg_regs.DPP_TOP0_DPP_CRC_VAL_B_A = ctx->dcn_reg_offsets[2] + 0x0cc8, dccg_regs.DPP_TOP0_DPP_CRC_VAL_R_G = ctx->dcn_reg_offsets[2] + 0x0cc7, dccg_regs.MPC_CRC_CTRL = ctx->dcn_reg_offsets[3] + 0x039a, dccg_regs.MPC_CRC_RESULT_GB = ctx->dcn_reg_offsets[3] + 0x039d, dccg_regs.MPC_CRC_RESULT_C = ctx->dcn_reg_offsets[3] + 0x039e, dccg_regs.MPC_CRC_RESULT_AR = ctx->dcn_reg_offsets[3] + 0x039c, dccg_regs.DOMAIN0_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0080, dccg_regs.DOMAIN1_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0082, dccg_regs.DOMAIN2_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0084, dccg_regs.DOMAIN3_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0086, dccg_regs.DOMAIN16_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0089, dccg_regs.DOMAIN17_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008b, dccg_regs.DOMAIN18_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008d, dccg_regs.DOMAIN19_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008f, dccg_regs.DOMAIN0_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0081, dccg_regs.DOMAIN1_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0083, dccg_regs.DOMAIN2_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0085, dccg_regs.DOMAIN3_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0087, dccg_regs.DOMAIN16_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008a, dccg_regs.DOMAIN17_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008c, dccg_regs.DOMAIN18_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008e, dccg_regs.DOMAIN19_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0090, dccg_regs.D1VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000c, dccg_regs.D2VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000e, dccg_regs.D3VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0038, dccg_regs.D4VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0039, dccg_regs.D5VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003a, dccg_regs.D6VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003b, dccg_regs.DC_IP_REQUEST_CNTL = ctx->dcn_reg_offsets[2] + 0x0095, dccg_regs.AZALIA_AUDIO_DTO = ctx->dcn_reg_offsets[2] + 0x03c3, dccg_regs.AZALIA_CONTROLLER_CLOCK_GATING = ctx->dcn_reg_offsets[2] + 0x03c2 |
587 | |
588 | #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh).PIXEL_RATE_SOURCE = OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCEmask_sh , .DP_DTO0_ENABLE = OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLEmask_sh , .PHYPLL_PIXEL_RATE_SOURCE = OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCEmask_sh , .DCHUBBUB_GLOBAL_TIMER_ENABLE = DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLEmask_sh , .DCFCLK_GATE_DIS = DCFCLK_CNTL__DCFCLK_GATE_DISmask_sh, .DC_MEM_GLOBAL_PWR_REQ_DIS = DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DISmask_sh , .DCHUBBUB_GLOBAL_TIMER_REFDIV = DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIVmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .IP_REQUEST_EN = DC_IP_REQUEST_CNTL__IP_REQUEST_ENmask_sh, . AZALIA_AUDIO_DTO_MODULE = AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULEmask_sh , .HPO_HDMISTREAMCLK_G_GATE_DIS = HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DISmask_sh , .ODM_MEM_UNASSIGNED_PWR_MODE = ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODEmask_sh , .ODM_MEM_VBLANK_PWR_MODE = ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODEmask_sh , .VGA_MEM_PWR_FORCE = MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCEmask_sh\ |
589 | HWSEQ_DCN_MASK_SH_LIST(mask_sh).PIXEL_RATE_SOURCE = OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCEmask_sh , .DP_DTO0_ENABLE = OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLEmask_sh , .PHYPLL_PIXEL_RATE_SOURCE = OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCEmask_sh , .DCHUBBUB_GLOBAL_TIMER_ENABLE = DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLEmask_sh , .DCFCLK_GATE_DIS = DCFCLK_CNTL__DCFCLK_GATE_DISmask_sh, .DC_MEM_GLOBAL_PWR_REQ_DIS = DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DISmask_sh, \ |
590 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh).DCHUBBUB_GLOBAL_TIMER_REFDIV = DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIVmask_sh, \ |
591 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ |
592 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ |
593 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ |
594 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ |
595 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ |
596 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ |
597 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ |
598 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ |
599 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ |
600 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ |
601 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ |
602 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ |
603 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ |
604 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ |
605 | HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ |
606 | HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ |
607 | HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ |
608 | HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ |
609 | HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ |
610 | HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ |
611 | HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ |
612 | HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ |
613 | HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ |
614 | HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ |
615 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh).IP_REQUEST_EN = DC_IP_REQUEST_CNTL__IP_REQUEST_ENmask_sh, \ |
616 | HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh).AZALIA_AUDIO_DTO_MODULE = AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULEmask_sh, \ |
617 | HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh).HPO_HDMISTREAMCLK_G_GATE_DIS = HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DISmask_sh, \ |
618 | HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh).ODM_MEM_UNASSIGNED_PWR_MODE = ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODEmask_sh, \ |
619 | HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh).ODM_MEM_VBLANK_PWR_MODE = ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODEmask_sh, \ |
620 | HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh).VGA_MEM_PWR_FORCE = MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCEmask_sh |
621 | |
622 | static const struct dce_hwseq_shift hwseq_shift = { |
623 | HWSEQ_DCN32_MASK_SH_LIST(__SHIFT).PIXEL_RATE_SOURCE = 0x0, .DP_DTO0_ENABLE = 0x4, .PHYPLL_PIXEL_RATE_SOURCE = 0x0, .DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCFCLK_GATE_DIS = 0x1f, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8 , .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0 , .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8 , .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_PGFSM_PWR_STATUS = 0x1e , .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .IP_REQUEST_EN = 0x0 , .AZALIA_AUDIO_DTO_MODULE = 0x10, .HPO_HDMISTREAMCLK_G_GATE_DIS = 0x9, .ODM_MEM_UNASSIGNED_PWR_MODE = 0x0, .ODM_MEM_VBLANK_PWR_MODE = 0x2, .VGA_MEM_PWR_FORCE = 0x0 |
624 | }; |
625 | |
626 | static const struct dce_hwseq_mask hwseq_mask = { |
627 | HWSEQ_DCN32_MASK_SH_LIST(_MASK).PIXEL_RATE_SOURCE = 0x00000003L, .DP_DTO0_ENABLE = 0x00000010L , .PHYPLL_PIXEL_RATE_SOURCE = 0x00000007L, .DCHUBBUB_GLOBAL_TIMER_ENABLE = 0x00001000L, .DCFCLK_GATE_DIS = 0x80000000L, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x00000001L, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, . DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L , .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L , .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L , .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L , .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L , .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L , .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L , .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L , .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .IP_REQUEST_EN = 0x00000001L, .AZALIA_AUDIO_DTO_MODULE = 0xFFFF0000L, .HPO_HDMISTREAMCLK_G_GATE_DIS = 0x00000200L, . ODM_MEM_UNASSIGNED_PWR_MODE = 0x00000003L, .ODM_MEM_VBLANK_PWR_MODE = 0x0000000CL, .VGA_MEM_PWR_FORCE = 0x00000001L |
628 | }; |
629 | #define vmid_regs_init(id)( dccg_regs[id].CNTL = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_CNTL_BASE_IDX ] + regDCN_VM_CONTEXTid_CNTL, dccg_regs[id].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32, dccg_regs[ id].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32, dccg_regs[ id].PAGE_TABLE_START_ADDR_HI32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32, dccg_regs [id].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32, dccg_regs [id].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32, dccg_regs[id ].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32 )\ |
630 | DCN20_VMID_REG_LIST_RI(id)( dccg_regs[id].CNTL = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_CNTL_BASE_IDX ] + regDCN_VM_CONTEXTid_CNTL, dccg_regs[id].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32, dccg_regs[ id].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32, dccg_regs[ id].PAGE_TABLE_START_ADDR_HI32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32, dccg_regs [id].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32, dccg_regs [id].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32, dccg_regs[id ].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32_BASE_IDX ] + regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32 ) |
631 | |
632 | static struct dcn_vmid_registers vmid_regs[16]; |
633 | |
634 | static const struct dcn20_vmid_shift vmid_shifts = { |
635 | DCN20_VMID_MASK_SH_LIST(__SHIFT).VM_CONTEXT0_PAGE_TABLE_DEPTH = 0x1, .VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE = 0x3, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 = 0x0, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 = 0x0, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 = 0x0, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 = 0x0, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 = 0x0, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 = 0x0 |
636 | }; |
637 | |
638 | static const struct dcn20_vmid_mask vmid_masks = { |
639 | DCN20_VMID_MASK_SH_LIST(_MASK).VM_CONTEXT0_PAGE_TABLE_DEPTH = 0x00000006L, .VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE = 0x00000078L, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 = 0xFFFFFFFFL , .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 = 0xFFFFFFFFL, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 = 0x0000000FL, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 = 0xFFFFFFFFL, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 = 0x0000000FL , .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 = 0xFFFFFFFFL |
640 | }; |
641 | |
642 | static const struct resource_caps res_cap_dcn32 = { |
643 | .num_timing_generator = 4, |
644 | .num_opp = 4, |
645 | .num_video_plane = 4, |
646 | .num_audio = 5, |
647 | .num_stream_encoder = 5, |
648 | .num_hpo_dp_stream_encoder = 4, |
649 | .num_hpo_dp_link_encoder = 2, |
650 | .num_pll = 5, |
651 | .num_dwb = 1, |
652 | .num_ddc = 5, |
653 | .num_vmid = 16, |
654 | .num_mpc_3dlut = 4, |
655 | .num_dsc = 4, |
656 | }; |
657 | |
658 | static const struct dc_plane_cap plane_cap = { |
659 | .type = DC_PLANE_TYPE_DCN_UNIVERSAL, |
660 | .blends_with_above = true1, |
661 | .blends_with_below = true1, |
662 | .per_pixel_alpha = true1, |
663 | |
664 | .pixel_format_support = { |
665 | .argb8888 = true1, |
666 | .nv12 = true1, |
667 | .fp16 = true1, |
668 | .p010 = true1, |
669 | .ayuv = false0, |
670 | }, |
671 | |
672 | .max_upscale_factor = { |
673 | .argb8888 = 16000, |
674 | .nv12 = 16000, |
675 | .fp16 = 16000 |
676 | }, |
677 | |
678 | // 6:1 downscaling ratio: 1000/6 = 166.666 |
679 | .max_downscale_factor = { |
680 | .argb8888 = 167, |
681 | .nv12 = 167, |
682 | .fp16 = 167 |
683 | }, |
684 | 64, |
685 | 64 |
686 | }; |
687 | |
688 | static const struct dc_debug_options debug_defaults_drv = { |
689 | .disable_dmcu = true1, |
690 | .force_abm_enable = false0, |
691 | .timing_trace = false0, |
692 | .clock_trace = true1, |
693 | .disable_pplib_clock_request = false0, |
694 | .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore |
695 | .force_single_disp_pipe_split = false0, |
696 | .disable_dcc = DCC_ENABLE, |
697 | .vsr_support = true1, |
698 | .performance_trace = false0, |
699 | .max_downscale_src_width = 7680,/*upto 8K*/ |
700 | .disable_pplib_wm_range = false0, |
701 | .scl_reset_length10 = true1, |
702 | .sanity_checks = false0, |
703 | .underflow_assert_delay_us = 0xFFFFFFFF, |
704 | .dwb_fi_phase = -1, // -1 = disable, |
705 | .dmub_command_table = true1, |
706 | .enable_mem_low_power = { |
707 | .bits = { |
708 | .vga = false0, |
709 | .i2c = false0, |
710 | .dmcu = false0, // This is previously known to cause hang on S3 cycles if enabled |
711 | .dscl = false0, |
712 | .cm = false0, |
713 | .mpc = false0, |
714 | .optc = true1, |
715 | } |
716 | }, |
717 | .use_max_lb = true1, |
718 | .force_disable_subvp = false0, |
719 | .exit_idle_opt_for_cursor_updates = true1, |
720 | .enable_single_display_2to1_odm_policy = true1, |
721 | |
722 | /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/ |
723 | .enable_double_buffered_dsc_pg_support = true1, |
724 | .enable_dp_dig_pixel_rate_div_policy = 1, |
725 | .allow_sw_cursor_fallback = false0, |
726 | .alloc_extra_way_for_cursor = true1, |
727 | .min_prefetch_in_strobe_ns = 60000, // 60us |
728 | }; |
729 | |
730 | static const struct dc_debug_options debug_defaults_diags = { |
731 | .disable_dmcu = true1, |
732 | .force_abm_enable = false0, |
733 | .timing_trace = true1, |
734 | .clock_trace = true1, |
735 | .disable_dpp_power_gate = true1, |
736 | .disable_hubp_power_gate = true1, |
737 | .disable_dsc_power_gate = true1, |
738 | .disable_clock_gate = true1, |
739 | .disable_pplib_clock_request = true1, |
740 | .disable_pplib_wm_range = true1, |
741 | .disable_stutter = false0, |
742 | .scl_reset_length10 = true1, |
743 | .dwb_fi_phase = -1, // -1 = disable |
744 | .dmub_command_table = true1, |
745 | .enable_tri_buf = true1, |
746 | .use_max_lb = true1, |
747 | .force_disable_subvp = true1 |
748 | }; |
749 | |
750 | static struct dce_aux *dcn32_aux_engine_create( |
751 | struct dc_context *ctx, |
752 | uint32_t inst) |
753 | { |
754 | struct aux_engine_dce110 *aux_engine = |
755 | kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL(0x0001 | 0x0004)); |
756 | |
757 | if (!aux_engine) |
758 | return NULL((void *)0); |
759 | |
760 | #undef REG_STRUCTdccg_regs |
761 | #define REG_STRUCTdccg_regs aux_engine_regs |
762 | aux_engine_regs_init(0)( ( dccg_regs[0].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f50 , dccg_regs[0].AUX_ARB_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f52, dccg_regs[0].AUX_SW_DATA = ctx->dcn_reg_offsets[2 ] + 0x1f56, dccg_regs[0].AUX_SW_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f51, dccg_regs[0].AUX_INTERRUPT_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f53, dccg_regs[0].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1f5b, dccg_regs[0].AUX_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1f54 ), dccg_regs[0].AUXN_IMPCAL = 0, dccg_regs[0].AUXP_IMPCAL = 0, dccg_regs[0].AUX_RESET_MASK = 0x00000010L, dccg_regs[0] .AUX_RESET_MASK = 0x00000010L ), |
763 | aux_engine_regs_init(1)( ( dccg_regs[1].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f6c , dccg_regs[1].AUX_ARB_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f6e, dccg_regs[1].AUX_SW_DATA = ctx->dcn_reg_offsets[2 ] + 0x1f72, dccg_regs[1].AUX_SW_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f6d, dccg_regs[1].AUX_INTERRUPT_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f6f, dccg_regs[1].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1f77, dccg_regs[1].AUX_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1f70 ), dccg_regs[1].AUXN_IMPCAL = 0, dccg_regs[1].AUXP_IMPCAL = 0, dccg_regs[1].AUX_RESET_MASK = 0x00000010L, dccg_regs[1] .AUX_RESET_MASK = 0x00000010L ), |
764 | aux_engine_regs_init(2)( ( dccg_regs[2].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f88 , dccg_regs[2].AUX_ARB_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f8a, dccg_regs[2].AUX_SW_DATA = ctx->dcn_reg_offsets[2 ] + 0x1f8e, dccg_regs[2].AUX_SW_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f89, dccg_regs[2].AUX_INTERRUPT_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f8b, dccg_regs[2].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1f93, dccg_regs[2].AUX_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1f8c ), dccg_regs[2].AUXN_IMPCAL = 0, dccg_regs[2].AUXP_IMPCAL = 0, dccg_regs[2].AUX_RESET_MASK = 0x00000010L, dccg_regs[2] .AUX_RESET_MASK = 0x00000010L ), |
765 | aux_engine_regs_init(3)( ( dccg_regs[3].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1fa4 , dccg_regs[3].AUX_ARB_CONTROL = ctx->dcn_reg_offsets[2] + 0x1fa6, dccg_regs[3].AUX_SW_DATA = ctx->dcn_reg_offsets[2 ] + 0x1faa, dccg_regs[3].AUX_SW_CONTROL = ctx->dcn_reg_offsets [2] + 0x1fa5, dccg_regs[3].AUX_INTERRUPT_CONTROL = ctx->dcn_reg_offsets [2] + 0x1fa7, dccg_regs[3].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1faf, dccg_regs[3].AUX_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1fa8 ), dccg_regs[3].AUXN_IMPCAL = 0, dccg_regs[3].AUXP_IMPCAL = 0, dccg_regs[3].AUX_RESET_MASK = 0x00000010L, dccg_regs[3] .AUX_RESET_MASK = 0x00000010L ), |
766 | aux_engine_regs_init(4)( ( dccg_regs[4].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1fc0 , dccg_regs[4].AUX_ARB_CONTROL = ctx->dcn_reg_offsets[2] + 0x1fc2, dccg_regs[4].AUX_SW_DATA = ctx->dcn_reg_offsets[2 ] + 0x1fc6, dccg_regs[4].AUX_SW_CONTROL = ctx->dcn_reg_offsets [2] + 0x1fc1, dccg_regs[4].AUX_INTERRUPT_CONTROL = ctx->dcn_reg_offsets [2] + 0x1fc3, dccg_regs[4].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1fcb, dccg_regs[4].AUX_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1fc4 ), dccg_regs[4].AUXN_IMPCAL = 0, dccg_regs[4].AUXP_IMPCAL = 0, dccg_regs[4].AUX_RESET_MASK = 0x00000010L, dccg_regs[4] .AUX_RESET_MASK = 0x00000010L ); |
767 | |
768 | dce110_aux_engine_construct(aux_engine, ctx, inst, |
769 | SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, |
770 | &aux_engine_regs[inst], |
771 | &aux_mask, |
772 | &aux_shift, |
773 | ctx->dc->caps.extended_aux_timeout_support); |
774 | |
775 | return &aux_engine->base; |
776 | } |
777 | #define i2c_inst_regs_init(id)( ( dccg_regs[id-1].SETUP = ctx->dcn_reg_offsets[regDC_I2C_DDCid_SETUP_BASE_IDX ] + regDC_I2C_DDCid_SETUP, dccg_regs[id-1].SPEED = ctx->dcn_reg_offsets [regDC_I2C_DDCid_SPEED_BASE_IDX] + regDC_I2C_DDCid_SPEED, dccg_regs [id-1].HW_STATUS = ctx->dcn_reg_offsets[regDC_I2C_DDCid_HW_STATUS_BASE_IDX ] + regDC_I2C_DDCid_HW_STATUS, dccg_regs[id-1].DC_I2C_ARBITRATION = ctx->dcn_reg_offsets[2] + 0x1e99, dccg_regs[id-1].DC_I2C_CONTROL = ctx->dcn_reg_offsets[2] + 0x1e98, dccg_regs[id-1].DC_I2C_SW_STATUS = ctx->dcn_reg_offsets[2] + 0x1e9b, dccg_regs[id-1].DC_I2C_TRANSACTION0 = ctx->dcn_reg_offsets[2] + 0x1eae, dccg_regs[id-1].DC_I2C_TRANSACTION1 = ctx->dcn_reg_offsets[2] + 0x1eaf, dccg_regs[id-1].DC_I2C_TRANSACTION2 = ctx->dcn_reg_offsets[2] + 0x1eb0, dccg_regs[id-1].DC_I2C_TRANSACTION3 = ctx->dcn_reg_offsets[2] + 0x1eb1, dccg_regs[id-1].DC_I2C_DATA = ctx->dcn_reg_offsets[2] + 0x1eb2, dccg_regs[id-1].MICROSECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x007b ), dccg_regs[id-1].DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1ede, dccg_regs[id-1].DIO_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x1edd )\ |
778 | I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)( ( dccg_regs[id-1].SETUP = ctx->dcn_reg_offsets[regDC_I2C_DDCid_SETUP_BASE_IDX ] + regDC_I2C_DDCid_SETUP, dccg_regs[id-1].SPEED = ctx->dcn_reg_offsets [regDC_I2C_DDCid_SPEED_BASE_IDX] + regDC_I2C_DDCid_SPEED, dccg_regs [id-1].HW_STATUS = ctx->dcn_reg_offsets[regDC_I2C_DDCid_HW_STATUS_BASE_IDX ] + regDC_I2C_DDCid_HW_STATUS, dccg_regs[id-1].DC_I2C_ARBITRATION = ctx->dcn_reg_offsets[2] + 0x1e99, dccg_regs[id-1].DC_I2C_CONTROL = ctx->dcn_reg_offsets[2] + 0x1e98, dccg_regs[id-1].DC_I2C_SW_STATUS = ctx->dcn_reg_offsets[2] + 0x1e9b, dccg_regs[id-1].DC_I2C_TRANSACTION0 = ctx->dcn_reg_offsets[2] + 0x1eae, dccg_regs[id-1].DC_I2C_TRANSACTION1 = ctx->dcn_reg_offsets[2] + 0x1eaf, dccg_regs[id-1].DC_I2C_TRANSACTION2 = ctx->dcn_reg_offsets[2] + 0x1eb0, dccg_regs[id-1].DC_I2C_TRANSACTION3 = ctx->dcn_reg_offsets[2] + 0x1eb1, dccg_regs[id-1].DC_I2C_DATA = ctx->dcn_reg_offsets[2] + 0x1eb2, dccg_regs[id-1].MICROSECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x007b ), dccg_regs[id-1].DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1ede, dccg_regs[id-1].DIO_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x1edd ) |
779 | |
780 | static struct dce_i2c_registers i2c_hw_regs[5]; |
781 | |
782 | static const struct dce_i2c_shift i2c_shifts = { |
783 | I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT).DC_I2C_DDC1_ENABLE = 0x6, .DC_I2C_DDC1_TIME_LIMIT = 0x18, .DC_I2C_DDC1_DATA_DRIVE_EN = 0x0, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x7, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x1, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x10, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0x8, .DC_I2C_DDC1_HW_STATUS = 0x0, .DC_I2C_SW_USE_I2C_REG_REQ = 0x14, .DC_I2C_SW_DONE_USING_I2C_REG = 0x15, .DC_I2C_NO_QUEUED_SW_GO = 0x4, .DC_I2C_SW_PRIORITY = 0x0, .DC_I2C_SOFT_RESET = 0x1, . DC_I2C_SW_STATUS_RESET = 0x3, .DC_I2C_GO = 0x0, .DC_I2C_SEND_RESET = 0x2, .DC_I2C_TRANSACTION_COUNT = 0x14, .DC_I2C_DDC_SELECT = 0x8, .DC_I2C_DDC1_PRESCALE = 0x10, .DC_I2C_DDC1_THRESHOLD = 0x0 , .DC_I2C_SW_STOPPED_ON_NACK = 0x8, .DC_I2C_SW_TIMEOUT = 0x5, .DC_I2C_SW_ABORTED = 0x4, .DC_I2C_SW_DONE = 0x2, .DC_I2C_SW_STATUS = 0x0, .DC_I2C_STOP_ON_NACK0 = 0x8, .DC_I2C_START0 = 0xc, .DC_I2C_RW0 = 0x0, .DC_I2C_STOP0 = 0xd, .DC_I2C_COUNT0 = 0x10, .DC_I2C_DATA_RW = 0x0, .DC_I2C_DATA = 0x8, .DC_I2C_INDEX = 0x10, .DC_I2C_INDEX_WRITE = 0x1f, .XTAL_REF_DIV = 0x8, .MICROSECOND_TIME_BASE_DIV = 0x0 , .DC_I2C_REG_RW_CNTL_STATUS = 0x2, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x8, .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x2, .I2C_LIGHT_SLEEP_FORCE = 0x0, .I2C_MEM_PWR_STATE = 0x0 |
784 | }; |
785 | |
786 | static const struct dce_i2c_mask i2c_masks = { |
787 | I2C_COMMON_MASK_SH_LIST_DCN30(_MASK).DC_I2C_DDC1_ENABLE = 0x00000040L, .DC_I2C_DDC1_TIME_LIMIT = 0xFF000000L , .DC_I2C_DDC1_DATA_DRIVE_EN = 0x00000001L, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x00000080L, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x00000002L, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x00FF0000L, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0x0000FF00L, . DC_I2C_DDC1_HW_STATUS = 0x00000003L, .DC_I2C_SW_USE_I2C_REG_REQ = 0x00100000L, .DC_I2C_SW_DONE_USING_I2C_REG = 0x00200000L, . DC_I2C_NO_QUEUED_SW_GO = 0x00000010L, .DC_I2C_SW_PRIORITY = 0x00000003L , .DC_I2C_SOFT_RESET = 0x00000002L, .DC_I2C_SW_STATUS_RESET = 0x00000008L, .DC_I2C_GO = 0x00000001L, .DC_I2C_SEND_RESET = 0x00000004L , .DC_I2C_TRANSACTION_COUNT = 0x00300000L, .DC_I2C_DDC_SELECT = 0x00000700L, .DC_I2C_DDC1_PRESCALE = 0xFFFF0000L, .DC_I2C_DDC1_THRESHOLD = 0x00000003L, .DC_I2C_SW_STOPPED_ON_NACK = 0x00000100L, .DC_I2C_SW_TIMEOUT = 0x00000020L, .DC_I2C_SW_ABORTED = 0x00000010L, .DC_I2C_SW_DONE = 0x00000004L, .DC_I2C_SW_STATUS = 0x00000003L, .DC_I2C_STOP_ON_NACK0 = 0x00000100L, .DC_I2C_START0 = 0x00001000L, .DC_I2C_RW0 = 0x00000001L , .DC_I2C_STOP0 = 0x00002000L, .DC_I2C_COUNT0 = 0x03FF0000L, . DC_I2C_DATA_RW = 0x00000001L, .DC_I2C_DATA = 0x0000FF00L, .DC_I2C_INDEX = 0x03FF0000L, .DC_I2C_INDEX_WRITE = 0x80000000L, .XTAL_REF_DIV = 0x00007F00L, .MICROSECOND_TIME_BASE_DIV = 0x0000007FL, .DC_I2C_REG_RW_CNTL_STATUS = 0x0000000CL, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x00000300L , .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x00000004L, .I2C_LIGHT_SLEEP_FORCE = 0x00000001L, .I2C_MEM_PWR_STATE = 0x00000001L |
788 | }; |
789 | |
790 | static struct dce_i2c_hw *dcn32_i2c_hw_create( |
791 | struct dc_context *ctx, |
792 | uint32_t inst) |
793 | { |
794 | struct dce_i2c_hw *dce_i2c_hw = |
795 | kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL(0x0001 | 0x0004)); |
796 | |
797 | if (!dce_i2c_hw) |
798 | return NULL((void *)0); |
799 | |
800 | #undef REG_STRUCTdccg_regs |
801 | #define REG_STRUCTdccg_regs i2c_hw_regs |
802 | i2c_inst_regs_init(1)( ( dccg_regs[1 -1].SETUP = ctx->dcn_reg_offsets[2] + 0x1ea3 , dccg_regs[1 -1].SPEED = ctx->dcn_reg_offsets[2] + 0x1ea2 , dccg_regs[1 -1].HW_STATUS = ctx->dcn_reg_offsets[2] + 0x1e9c , dccg_regs[1 -1].DC_I2C_ARBITRATION = ctx->dcn_reg_offsets [2] + 0x1e99, dccg_regs[1 -1].DC_I2C_CONTROL = ctx->dcn_reg_offsets [2] + 0x1e98, dccg_regs[1 -1].DC_I2C_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1e9b, dccg_regs[1 -1].DC_I2C_TRANSACTION0 = ctx->dcn_reg_offsets [2] + 0x1eae, dccg_regs[1 -1].DC_I2C_TRANSACTION1 = ctx->dcn_reg_offsets [2] + 0x1eaf, dccg_regs[1 -1].DC_I2C_TRANSACTION2 = ctx->dcn_reg_offsets [2] + 0x1eb0, dccg_regs[1 -1].DC_I2C_TRANSACTION3 = ctx->dcn_reg_offsets [2] + 0x1eb1, dccg_regs[1 -1].DC_I2C_DATA = ctx->dcn_reg_offsets [2] + 0x1eb2, dccg_regs[1 -1].MICROSECOND_TIME_BASE_DIV = ctx ->dcn_reg_offsets[1] + 0x007b ), dccg_regs[1 -1].DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1ede, dccg_regs[1 -1].DIO_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x1edd ), |
803 | i2c_inst_regs_init(2)( ( dccg_regs[2 -1].SETUP = ctx->dcn_reg_offsets[2] + 0x1ea5 , dccg_regs[2 -1].SPEED = ctx->dcn_reg_offsets[2] + 0x1ea4 , dccg_regs[2 -1].HW_STATUS = ctx->dcn_reg_offsets[2] + 0x1e9d , dccg_regs[2 -1].DC_I2C_ARBITRATION = ctx->dcn_reg_offsets [2] + 0x1e99, dccg_regs[2 -1].DC_I2C_CONTROL = ctx->dcn_reg_offsets [2] + 0x1e98, dccg_regs[2 -1].DC_I2C_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1e9b, dccg_regs[2 -1].DC_I2C_TRANSACTION0 = ctx->dcn_reg_offsets [2] + 0x1eae, dccg_regs[2 -1].DC_I2C_TRANSACTION1 = ctx->dcn_reg_offsets [2] + 0x1eaf, dccg_regs[2 -1].DC_I2C_TRANSACTION2 = ctx->dcn_reg_offsets [2] + 0x1eb0, dccg_regs[2 -1].DC_I2C_TRANSACTION3 = ctx->dcn_reg_offsets [2] + 0x1eb1, dccg_regs[2 -1].DC_I2C_DATA = ctx->dcn_reg_offsets [2] + 0x1eb2, dccg_regs[2 -1].MICROSECOND_TIME_BASE_DIV = ctx ->dcn_reg_offsets[1] + 0x007b ), dccg_regs[2 -1].DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1ede, dccg_regs[2 -1].DIO_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x1edd ), |
804 | i2c_inst_regs_init(3)( ( dccg_regs[3 -1].SETUP = ctx->dcn_reg_offsets[2] + 0x1ea7 , dccg_regs[3 -1].SPEED = ctx->dcn_reg_offsets[2] + 0x1ea6 , dccg_regs[3 -1].HW_STATUS = ctx->dcn_reg_offsets[2] + 0x1e9e , dccg_regs[3 -1].DC_I2C_ARBITRATION = ctx->dcn_reg_offsets [2] + 0x1e99, dccg_regs[3 -1].DC_I2C_CONTROL = ctx->dcn_reg_offsets [2] + 0x1e98, dccg_regs[3 -1].DC_I2C_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1e9b, dccg_regs[3 -1].DC_I2C_TRANSACTION0 = ctx->dcn_reg_offsets [2] + 0x1eae, dccg_regs[3 -1].DC_I2C_TRANSACTION1 = ctx->dcn_reg_offsets [2] + 0x1eaf, dccg_regs[3 -1].DC_I2C_TRANSACTION2 = ctx->dcn_reg_offsets [2] + 0x1eb0, dccg_regs[3 -1].DC_I2C_TRANSACTION3 = ctx->dcn_reg_offsets [2] + 0x1eb1, dccg_regs[3 -1].DC_I2C_DATA = ctx->dcn_reg_offsets [2] + 0x1eb2, dccg_regs[3 -1].MICROSECOND_TIME_BASE_DIV = ctx ->dcn_reg_offsets[1] + 0x007b ), dccg_regs[3 -1].DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1ede, dccg_regs[3 -1].DIO_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x1edd ), |
805 | i2c_inst_regs_init(4)( ( dccg_regs[4 -1].SETUP = ctx->dcn_reg_offsets[2] + 0x1ea9 , dccg_regs[4 -1].SPEED = ctx->dcn_reg_offsets[2] + 0x1ea8 , dccg_regs[4 -1].HW_STATUS = ctx->dcn_reg_offsets[2] + 0x1e9f , dccg_regs[4 -1].DC_I2C_ARBITRATION = ctx->dcn_reg_offsets [2] + 0x1e99, dccg_regs[4 -1].DC_I2C_CONTROL = ctx->dcn_reg_offsets [2] + 0x1e98, dccg_regs[4 -1].DC_I2C_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1e9b, dccg_regs[4 -1].DC_I2C_TRANSACTION0 = ctx->dcn_reg_offsets [2] + 0x1eae, dccg_regs[4 -1].DC_I2C_TRANSACTION1 = ctx->dcn_reg_offsets [2] + 0x1eaf, dccg_regs[4 -1].DC_I2C_TRANSACTION2 = ctx->dcn_reg_offsets [2] + 0x1eb0, dccg_regs[4 -1].DC_I2C_TRANSACTION3 = ctx->dcn_reg_offsets [2] + 0x1eb1, dccg_regs[4 -1].DC_I2C_DATA = ctx->dcn_reg_offsets [2] + 0x1eb2, dccg_regs[4 -1].MICROSECOND_TIME_BASE_DIV = ctx ->dcn_reg_offsets[1] + 0x007b ), dccg_regs[4 -1].DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1ede, dccg_regs[4 -1].DIO_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x1edd ), |
806 | i2c_inst_regs_init(5)( ( dccg_regs[5 -1].SETUP = ctx->dcn_reg_offsets[2] + 0x1eab , dccg_regs[5 -1].SPEED = ctx->dcn_reg_offsets[2] + 0x1eaa , dccg_regs[5 -1].HW_STATUS = ctx->dcn_reg_offsets[2] + 0x1ea0 , dccg_regs[5 -1].DC_I2C_ARBITRATION = ctx->dcn_reg_offsets [2] + 0x1e99, dccg_regs[5 -1].DC_I2C_CONTROL = ctx->dcn_reg_offsets [2] + 0x1e98, dccg_regs[5 -1].DC_I2C_SW_STATUS = ctx->dcn_reg_offsets [2] + 0x1e9b, dccg_regs[5 -1].DC_I2C_TRANSACTION0 = ctx->dcn_reg_offsets [2] + 0x1eae, dccg_regs[5 -1].DC_I2C_TRANSACTION1 = ctx->dcn_reg_offsets [2] + 0x1eaf, dccg_regs[5 -1].DC_I2C_TRANSACTION2 = ctx->dcn_reg_offsets [2] + 0x1eb0, dccg_regs[5 -1].DC_I2C_TRANSACTION3 = ctx->dcn_reg_offsets [2] + 0x1eb1, dccg_regs[5 -1].DC_I2C_DATA = ctx->dcn_reg_offsets [2] + 0x1eb2, dccg_regs[5 -1].MICROSECOND_TIME_BASE_DIV = ctx ->dcn_reg_offsets[1] + 0x007b ), dccg_regs[5 -1].DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1ede, dccg_regs[5 -1].DIO_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x1edd ); |
807 | |
808 | dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, |
809 | &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); |
810 | |
811 | return dce_i2c_hw; |
812 | } |
813 | |
814 | static struct clock_source *dcn32_clock_source_create( |
815 | struct dc_context *ctx, |
816 | struct dc_bios *bios, |
817 | enum clock_source_id id, |
818 | const struct dce110_clk_src_regs *regs, |
819 | bool_Bool dp_clk_src) |
820 | { |
821 | struct dce110_clk_src *clk_src = |
822 | kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL(0x0001 | 0x0004)); |
823 | |
824 | if (!clk_src) |
825 | return NULL((void *)0); |
826 | |
827 | if (dcn31_clk_src_construct(clk_src, ctx, bios, id, |
828 | regs, &cs_shift, &cs_mask)) { |
829 | clk_src->base.dp_clk_src = dp_clk_src; |
830 | return &clk_src->base; |
831 | } |
832 | |
833 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 833); do {} while (0); } while (0); |
834 | return NULL((void *)0); |
835 | } |
836 | |
837 | static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx) |
838 | { |
839 | int i; |
840 | |
841 | struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub), |
842 | GFP_KERNEL(0x0001 | 0x0004)); |
843 | |
844 | if (!hubbub2) |
845 | return NULL((void *)0); |
846 | |
847 | #undef REG_STRUCTdccg_regs |
848 | #define REG_STRUCTdccg_regs hubbub_reg |
849 | hubbub_reg_init()( dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = ctx->dcn_reg_offsets [2] + 0x04fe, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x0507, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0510, dccg_regs.DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x0519, dccg_regs.DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL = ctx->dcn_reg_offsets[2] + 0x0522, dccg_regs.DCHUBBUB_ARB_DRAM_STATE_CNTL = ctx->dcn_reg_offsets[2] + 0x04fc, dccg_regs.DCHUBBUB_ARB_SAT_LEVEL = ctx->dcn_reg_offsets[2] + 0x04fa, dccg_regs.DCHUBBUB_ARB_DF_REQ_OUTSTAND = ctx->dcn_reg_offsets[2] + 0x04f9, dccg_regs.DCHUBBUB_GLOBAL_TIMER_CNTL = ctx->dcn_reg_offsets[2] + 0x0525, dccg_regs.DCHUBBUB_SOFT_RESET = ctx->dcn_reg_offsets[2] + 0x0532, dccg_regs.DCHUBBUB_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x04b1, dccg_regs.DCN_VM_FB_LOCATION_BASE = ctx->dcn_reg_offsets[2] + 0x0475, dccg_regs.DCN_VM_FB_LOCATION_TOP = ctx->dcn_reg_offsets[2] + 0x0476, dccg_regs.DCN_VM_FB_OFFSET = ctx->dcn_reg_offsets[2] + 0x0477, dccg_regs.DCN_VM_AGP_BOT = ctx->dcn_reg_offsets[2] + 0x0478, dccg_regs.DCN_VM_AGP_TOP = ctx->dcn_reg_offsets[2] + 0x0479, dccg_regs.DCN_VM_AGP_BASE = ctx->dcn_reg_offsets[2] + 0x047a, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0501, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0502, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050a, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050b, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0513, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0514, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051c, dccg_regs.DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051d, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = ctx->dcn_reg_offsets[2] + 0x0505, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = ctx->dcn_reg_offsets[2] + 0x050e, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = ctx->dcn_reg_offsets[2] + 0x0517, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = ctx->dcn_reg_offsets[2] + 0x0520, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = ctx->dcn_reg_offsets[2] + 0x0506, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = ctx->dcn_reg_offsets[2] + 0x050f, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = ctx->dcn_reg_offsets[2] + 0x0518, dccg_regs.DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = ctx->dcn_reg_offsets[2] + 0x0521, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = ctx->dcn_reg_offsets[2] + 0x0500, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = ctx->dcn_reg_offsets[2] + 0x0509, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = ctx->dcn_reg_offsets[2] + 0x0512, dccg_regs.DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D = ctx->dcn_reg_offsets[2] + 0x051b, dccg_regs.DCHUBBUB_DET0_CTRL = ctx->dcn_reg_offsets[2] + 0x04bb, dccg_regs.DCHUBBUB_DET1_CTRL = ctx->dcn_reg_offsets[2] + 0x04bc, dccg_regs.DCHUBBUB_DET2_CTRL = ctx->dcn_reg_offsets[2] + 0x04bd, dccg_regs.DCHUBBUB_DET3_CTRL = ctx->dcn_reg_offsets[2] + 0x04be, dccg_regs.DCHUBBUB_COMPBUF_CTRL = ctx->dcn_reg_offsets[2] + 0x04ba, dccg_regs.COMPBUF_RESERVED_SPACE = ctx->dcn_reg_offsets[2] + 0x04c4, dccg_regs.DCHUBBUB_DEBUG_CTRL_0 = ctx->dcn_reg_offsets[2] + 0x04c5, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_CNTL = ctx->dcn_reg_offsets[2] + 0x04fd, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x04ff, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x0508, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0511, dccg_regs.DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051a, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0503, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050c, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0515, dccg_regs.DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051e, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A = ctx->dcn_reg_offsets[2] + 0x0504, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B = ctx->dcn_reg_offsets[2] + 0x050d, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C = ctx->dcn_reg_offsets[2] + 0x0516, dccg_regs.DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D = ctx->dcn_reg_offsets[2] + 0x051f, dccg_regs.DCN_VM_FAULT_ADDR_MSB = ctx->dcn_reg_offsets[2] + 0x05cd, dccg_regs.DCN_VM_FAULT_ADDR_LSB = ctx->dcn_reg_offsets[2] + 0x05ce, dccg_regs.DCN_VM_FAULT_CNTL = ctx->dcn_reg_offsets[2] + 0x05cb, dccg_regs.DCN_VM_FAULT_STATUS = ctx->dcn_reg_offsets[2] + 0x05cc ); |
850 | |
851 | #undef REG_STRUCTdccg_regs |
852 | #define REG_STRUCTdccg_regs vmid_regs |
853 | vmid_regs_init(0)( dccg_regs[0].CNTL = ctx->dcn_reg_offsets[2] + 0x0559, dccg_regs [0].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x055a , dccg_regs[0].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x055b, dccg_regs[0].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x055c, dccg_regs[0].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x055d, dccg_regs[0].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x055e, dccg_regs[0].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x055f ), |
854 | vmid_regs_init(1)( dccg_regs[1].CNTL = ctx->dcn_reg_offsets[2] + 0x0560, dccg_regs [1].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0561 , dccg_regs[1].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x0562, dccg_regs[1].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x0563, dccg_regs[1].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0564, dccg_regs[1].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0565, dccg_regs[1].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0566 ), |
855 | vmid_regs_init(2)( dccg_regs[2].CNTL = ctx->dcn_reg_offsets[2] + 0x0567, dccg_regs [2].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0568 , dccg_regs[2].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x0569, dccg_regs[2].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x056a, dccg_regs[2].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x056b, dccg_regs[2].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x056c, dccg_regs[2].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x056d ), |
856 | vmid_regs_init(3)( dccg_regs[3].CNTL = ctx->dcn_reg_offsets[2] + 0x056e, dccg_regs [3].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x056f , dccg_regs[3].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x0570, dccg_regs[3].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x0571, dccg_regs[3].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0572, dccg_regs[3].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0573, dccg_regs[3].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0574 ), |
857 | vmid_regs_init(4)( dccg_regs[4].CNTL = ctx->dcn_reg_offsets[2] + 0x0575, dccg_regs [4].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0576 , dccg_regs[4].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x0577, dccg_regs[4].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x0578, dccg_regs[4].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0579, dccg_regs[4].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x057a, dccg_regs[4].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x057b ), |
858 | vmid_regs_init(5)( dccg_regs[5].CNTL = ctx->dcn_reg_offsets[2] + 0x057c, dccg_regs [5].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x057d , dccg_regs[5].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x057e, dccg_regs[5].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x057f, dccg_regs[5].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0580, dccg_regs[5].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0581, dccg_regs[5].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0582 ), |
859 | vmid_regs_init(6)( dccg_regs[6].CNTL = ctx->dcn_reg_offsets[2] + 0x0583, dccg_regs [6].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0584 , dccg_regs[6].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x0585, dccg_regs[6].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x0586, dccg_regs[6].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0587, dccg_regs[6].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0588, dccg_regs[6].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0589 ), |
860 | vmid_regs_init(7)( dccg_regs[7].CNTL = ctx->dcn_reg_offsets[2] + 0x058a, dccg_regs [7].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x058b , dccg_regs[7].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x058c, dccg_regs[7].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x058d, dccg_regs[7].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x058e, dccg_regs[7].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x058f, dccg_regs[7].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0590 ), |
861 | vmid_regs_init(8)( dccg_regs[8].CNTL = ctx->dcn_reg_offsets[2] + 0x0591, dccg_regs [8].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0592 , dccg_regs[8].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x0593, dccg_regs[8].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x0594, dccg_regs[8].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0595, dccg_regs[8].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0596, dccg_regs[8].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x0597 ), |
862 | vmid_regs_init(9)( dccg_regs[9].CNTL = ctx->dcn_reg_offsets[2] + 0x0598, dccg_regs [9].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x0599 , dccg_regs[9].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x059a, dccg_regs[9].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x059b, dccg_regs[9].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x059c, dccg_regs[9].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x059d, dccg_regs[9].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x059e ), |
863 | vmid_regs_init(10)( dccg_regs[10].CNTL = ctx->dcn_reg_offsets[2] + 0x059f, dccg_regs [10].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05a0, dccg_regs[10].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x05a1, dccg_regs[10].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x05a2, dccg_regs[10].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05a3, dccg_regs[10].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05a4, dccg_regs[10].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05a5 ), |
864 | vmid_regs_init(11)( dccg_regs[11].CNTL = ctx->dcn_reg_offsets[2] + 0x05a6, dccg_regs [11].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05a7, dccg_regs[11].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x05a8, dccg_regs[11].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x05a9, dccg_regs[11].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05aa, dccg_regs[11].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05ab, dccg_regs[11].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05ac ), |
865 | vmid_regs_init(12)( dccg_regs[12].CNTL = ctx->dcn_reg_offsets[2] + 0x05ad, dccg_regs [12].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05ae, dccg_regs[12].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x05af, dccg_regs[12].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x05b0, dccg_regs[12].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05b1, dccg_regs[12].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05b2, dccg_regs[12].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05b3 ), |
866 | vmid_regs_init(13)( dccg_regs[13].CNTL = ctx->dcn_reg_offsets[2] + 0x05b4, dccg_regs [13].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05b5, dccg_regs[13].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x05b6, dccg_regs[13].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x05b7, dccg_regs[13].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05b8, dccg_regs[13].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05b9, dccg_regs[13].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05ba ), |
867 | vmid_regs_init(14)( dccg_regs[14].CNTL = ctx->dcn_reg_offsets[2] + 0x05bb, dccg_regs [14].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05bc, dccg_regs[14].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x05bd, dccg_regs[14].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x05be, dccg_regs[14].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05bf, dccg_regs[14].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05c0, dccg_regs[14].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05c1 ), |
868 | vmid_regs_init(15)( dccg_regs[15].CNTL = ctx->dcn_reg_offsets[2] + 0x05c2, dccg_regs [15].PAGE_TABLE_BASE_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05c3, dccg_regs[15].PAGE_TABLE_BASE_ADDR_LO32 = ctx->dcn_reg_offsets [2] + 0x05c4, dccg_regs[15].PAGE_TABLE_START_ADDR_HI32 = ctx-> dcn_reg_offsets[2] + 0x05c5, dccg_regs[15].PAGE_TABLE_START_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05c6, dccg_regs[15].PAGE_TABLE_END_ADDR_HI32 = ctx->dcn_reg_offsets[2] + 0x05c7, dccg_regs[15].PAGE_TABLE_END_ADDR_LO32 = ctx->dcn_reg_offsets[2] + 0x05c8 ); |
869 | |
870 | hubbub32_construct(hubbub2, ctx, |
871 | &hubbub_reg, |
872 | &hubbub_shift, |
873 | &hubbub_mask, |
874 | ctx->dc->dml.ip.det_buffer_size_kbytes, |
875 | ctx->dc->dml.ip.pixel_chunk_size_kbytes, |
876 | ctx->dc->dml.ip.config_return_buffer_size_in_kbytes); |
877 | |
878 | |
879 | for (i = 0; i < res_cap_dcn32.num_vmid; i++) { |
880 | struct dcn20_vmid *vmid = &hubbub2->vmid[i]; |
881 | |
882 | vmid->ctx = ctx; |
883 | |
884 | vmid->regs = &vmid_regs[i]; |
885 | vmid->shifts = &vmid_shifts; |
886 | vmid->masks = &vmid_masks; |
887 | } |
888 | |
889 | return &hubbub2->base; |
890 | } |
891 | |
892 | static struct hubp *dcn32_hubp_create( |
893 | struct dc_context *ctx, |
894 | uint32_t inst) |
895 | { |
896 | struct dcn20_hubp *hubp2 = |
897 | kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL(0x0001 | 0x0004)); |
898 | |
899 | if (!hubp2) |
900 | return NULL((void *)0); |
901 | |
902 | #undef REG_STRUCTdccg_regs |
903 | #define REG_STRUCTdccg_regs hubp_regs |
904 | hubp_regs_init(0)( ( ( ( ( dccg_regs[0].DCHUBP_CNTL = ctx->dcn_reg_offsets[ 2] + 0x05f3, dccg_regs[0].HUBPREQ_DEBUG_DB = ctx->dcn_reg_offsets [2] + 0x05f8, dccg_regs[0].HUBPREQ_DEBUG = ctx->dcn_reg_offsets [2] + 0x05f9, dccg_regs[0].DCSURF_ADDR_CONFIG = ctx->dcn_reg_offsets [2] + 0x05e6, dccg_regs[0].DCSURF_TILING_CONFIG = ctx->dcn_reg_offsets [2] + 0x05e7, dccg_regs[0].DCSURF_SURFACE_PITCH = ctx->dcn_reg_offsets [2] + 0x0607, dccg_regs[0].DCSURF_SURFACE_PITCH_C = ctx->dcn_reg_offsets [2] + 0x0608, dccg_regs[0].DCSURF_SURFACE_CONFIG = ctx->dcn_reg_offsets [2] + 0x05e5, dccg_regs[0].DCSURF_FLIP_CONTROL = ctx->dcn_reg_offsets [2] + 0x061b, dccg_regs[0].DCSURF_PRI_VIEWPORT_DIMENSION = ctx ->dcn_reg_offsets[2] + 0x05ea, dccg_regs[0].DCSURF_PRI_VIEWPORT_START = ctx->dcn_reg_offsets[2] + 0x05e9, dccg_regs[0].DCSURF_SEC_VIEWPORT_DIMENSION = ctx->dcn_reg_offsets[2] + 0x05ee, dccg_regs[0].DCSURF_SEC_VIEWPORT_START = ctx->dcn_reg_offsets[2] + 0x05ed, dccg_regs[0].DCSURF_PRI_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets[2] + 0x05ec, dccg_regs[0].DCSURF_PRI_VIEWPORT_START_C = ctx->dcn_reg_offsets[2] + 0x05eb, dccg_regs[0].DCSURF_SEC_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets[2] + 0x05f0, dccg_regs[0].DCSURF_SEC_VIEWPORT_START_C = ctx->dcn_reg_offsets[2] + 0x05ef, dccg_regs[0].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x060b, dccg_regs[0].DCSURF_PRIMARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x060a, dccg_regs[0].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x060f, dccg_regs[0].DCSURF_SECONDARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x060e, dccg_regs[0].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x0613, dccg_regs[0].DCSURF_PRIMARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x0612, dccg_regs[0].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x0617, dccg_regs[0].DCSURF_SECONDARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x0616, dccg_regs[0].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x060d, dccg_regs[0].DCSURF_PRIMARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x060c, dccg_regs[0].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x0611, dccg_regs[0].DCSURF_SECONDARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x0610, dccg_regs[0].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x0615, dccg_regs[0].DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x0614, dccg_regs[0].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x0619, dccg_regs[0].DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x0618, dccg_regs[0].DCSURF_SURFACE_INUSE = ctx->dcn_reg_offsets[2] + 0x0620, dccg_regs[0].DCSURF_SURFACE_INUSE_HIGH = ctx->dcn_reg_offsets[2] + 0x0621, dccg_regs[0].DCSURF_SURFACE_INUSE_C = ctx->dcn_reg_offsets[2] + 0x0622, dccg_regs[0].DCSURF_SURFACE_INUSE_HIGH_C = ctx->dcn_reg_offsets[2] + 0x0623, dccg_regs[0].DCSURF_SURFACE_EARLIEST_INUSE = ctx->dcn_reg_offsets[2] + 0x0624, dccg_regs[0].DCSURF_SURFACE_EARLIEST_INUSE_HIGH = ctx->dcn_reg_offsets[2] + 0x0625, dccg_regs[0].DCSURF_SURFACE_EARLIEST_INUSE_C = ctx->dcn_reg_offsets[2] + 0x0626, dccg_regs[0].DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = ctx->dcn_reg_offsets[2] + 0x0627, dccg_regs[0].DCSURF_SURFACE_CONTROL = ctx->dcn_reg_offsets[2] + 0x061a, dccg_regs[0].DCSURF_SURFACE_FLIP_INTERRUPT = ctx->dcn_reg_offsets[2] + 0x061f, dccg_regs[0].HUBPRET_CONTROL = ctx->dcn_reg_offsets[2] + 0x066c, dccg_regs[0].HUBPRET_READ_LINE_STATUS = ctx->dcn_reg_offsets[2] + 0x0675, dccg_regs[0].DCN_EXPANSION_MODE = ctx->dcn_reg_offsets[2] + 0x0628, dccg_regs[0].DCHUBP_REQ_SIZE_CONFIG = ctx->dcn_reg_offsets[2] + 0x05f1, dccg_regs[0].DCHUBP_REQ_SIZE_CONFIG_C = ctx->dcn_reg_offsets[2] + 0x05f2, dccg_regs[0].BLANK_OFFSET_0 = ctx->dcn_reg_offsets[2] + 0x0643, dccg_regs[0].BLANK_OFFSET_1 = ctx->dcn_reg_offsets[2] + 0x0644, dccg_regs[0].DST_DIMENSIONS = ctx->dcn_reg_offsets[2] + 0x0645, dccg_regs[0].DST_AFTER_SCALER = ctx->dcn_reg_offsets[2] + 0x0646, dccg_regs[0].VBLANK_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x0649, dccg_regs[0].REF_FREQ_TO_PIX_FREQ = ctx->dcn_reg_offsets[2] + 0x065c, dccg_regs[0].VBLANK_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x064a, dccg_regs[0].VBLANK_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x064c, dccg_regs[0].NOM_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x0655, dccg_regs[0].NOM_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x0656, dccg_regs[0].PER_LINE_DELIVERY_PRE = ctx->dcn_reg_offsets[2] + 0x0659, dccg_regs[0].PER_LINE_DELIVERY = ctx->dcn_reg_offsets[2] + 0x065a, dccg_regs[0].VBLANK_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x064b, dccg_regs[0].VBLANK_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x064d, dccg_regs[0].NOM_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x0657, dccg_regs[0].NOM_PARAMETERS_7 = ctx->dcn_reg_offsets[2] + 0x0658, dccg_regs[0].DCN_TTU_QOS_WM = ctx->dcn_reg_offsets[2] + 0x0629, dccg_regs[0].DCN_GLOBAL_TTU_CNTL = ctx->dcn_reg_offsets[2] + 0x062a, dccg_regs[0].DCN_SURF0_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x062b, dccg_regs[0].DCN_SURF0_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x062c, dccg_regs[0].DCN_SURF1_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x062d, dccg_regs[0].DCN_SURF1_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x062e, dccg_regs[0].DCN_CUR0_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x062f, dccg_regs[0].DCN_CUR0_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x0630, dccg_regs[0].HUBP_CLK_CNTL = ctx->dcn_reg_offsets[2] + 0x05f4 ), ( dccg_regs[0].NOM_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x0651, dccg_regs[0].NOM_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x0652, dccg_regs[0].NOM_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x0653, dccg_regs[0].NOM_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x0654, dccg_regs[0].DCN_VM_MX_L1_TLB_CNTL = ctx->dcn_reg_offsets[2] + 0x0642 ), dccg_regs[0].PREFETCH_SETTINGS = ctx->dcn_reg_offsets[2] + 0x0647, dccg_regs[0].PREFETCH_SETTINGS_C = ctx->dcn_reg_offsets[2] + 0x0648, dccg_regs[0].DCN_VM_SYSTEM_APERTURE_LOW_ADDR = ctx->dcn_reg_offsets[2] + 0x0634, dccg_regs[0].DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = ctx->dcn_reg_offsets[2] + 0x0635, dccg_regs[0].CURSOR_SETTINGS = ctx->dcn_reg_offsets[2] + 0x065b, dccg_regs[0].CURSOR_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x067a, dccg_regs[0].CURSOR_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x0679, dccg_regs[0].CURSOR_SIZE = ctx->dcn_reg_offsets[2] + 0x067b, dccg_regs[0].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0678, dccg_regs[0].CURSOR_POSITION = ctx->dcn_reg_offsets[2] + 0x067c, dccg_regs[0].CURSOR_HOT_SPOT = ctx->dcn_reg_offsets[2] + 0x067d, dccg_regs[0].CURSOR_DST_OFFSET = ctx->dcn_reg_offsets[2] + 0x067f, dccg_regs[0].DMDATA_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x0682, dccg_regs[0].DMDATA_ADDRESS_LOW = ctx->dcn_reg_offsets[2] + 0x0683, dccg_regs[0].DMDATA_CNTL = ctx->dcn_reg_offsets[2] + 0x0684, dccg_regs[0].DMDATA_SW_CNTL = ctx->dcn_reg_offsets[2] + 0x0687, dccg_regs[0].DMDATA_QOS_CNTL = ctx->dcn_reg_offsets[2] + 0x0685, dccg_regs[0].DMDATA_SW_DATA = ctx->dcn_reg_offsets[2] + 0x0688, dccg_regs[0].DMDATA_STATUS = ctx->dcn_reg_offsets[2] + 0x0686, dccg_regs[0].FLIP_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x064e, dccg_regs[0].FLIP_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x064f, dccg_regs[0].FLIP_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x0650, dccg_regs[0].DCN_CUR1_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x0631, dccg_regs[0].DCN_CUR1_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x0632, dccg_regs[0].DCSURF_FLIP_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x061c, dccg_regs[0].VMID_SETTINGS_0 = ctx->dcn_reg_offsets[2] + 0x0609 ), dccg_regs[0].FLIP_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x0664, dccg_regs[0].FLIP_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x0665, dccg_regs[0].FLIP_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x0666, dccg_regs[0].FLIP_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x0667, dccg_regs[0].VBLANK_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x0662, dccg_regs[0].VBLANK_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x0663 ), dccg_regs[0].DCN_DMDATA_VM_CNTL = ctx->dcn_reg_offsets[2] + 0x0633 ), dccg_regs[0].DCHUBP_MALL_CONFIG = ctx->dcn_reg_offsets[2] + 0x05f6, dccg_regs[0].DCHUBP_VMPG_CONFIG = ctx->dcn_reg_offsets[2] + 0x05f5, dccg_regs[0].UCLK_PSTATE_FORCE = ctx->dcn_reg_offsets[2] + 0x0668 ), |
905 | hubp_regs_init(1)( ( ( ( ( dccg_regs[1].DCHUBP_CNTL = ctx->dcn_reg_offsets[ 2] + 0x06cf, dccg_regs[1].HUBPREQ_DEBUG_DB = ctx->dcn_reg_offsets [2] + 0x06d4, dccg_regs[1].HUBPREQ_DEBUG = ctx->dcn_reg_offsets [2] + 0x06d5, dccg_regs[1].DCSURF_ADDR_CONFIG = ctx->dcn_reg_offsets [2] + 0x06c2, dccg_regs[1].DCSURF_TILING_CONFIG = ctx->dcn_reg_offsets [2] + 0x06c3, dccg_regs[1].DCSURF_SURFACE_PITCH = ctx->dcn_reg_offsets [2] + 0x06e3, dccg_regs[1].DCSURF_SURFACE_PITCH_C = ctx->dcn_reg_offsets [2] + 0x06e4, dccg_regs[1].DCSURF_SURFACE_CONFIG = ctx->dcn_reg_offsets [2] + 0x06c1, dccg_regs[1].DCSURF_FLIP_CONTROL = ctx->dcn_reg_offsets [2] + 0x06f7, dccg_regs[1].DCSURF_PRI_VIEWPORT_DIMENSION = ctx ->dcn_reg_offsets[2] + 0x06c6, dccg_regs[1].DCSURF_PRI_VIEWPORT_START = ctx->dcn_reg_offsets[2] + 0x06c5, dccg_regs[1].DCSURF_SEC_VIEWPORT_DIMENSION = ctx->dcn_reg_offsets[2] + 0x06ca, dccg_regs[1].DCSURF_SEC_VIEWPORT_START = ctx->dcn_reg_offsets[2] + 0x06c9, dccg_regs[1].DCSURF_PRI_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets[2] + 0x06c8, dccg_regs[1].DCSURF_PRI_VIEWPORT_START_C = ctx->dcn_reg_offsets[2] + 0x06c7, dccg_regs[1].DCSURF_SEC_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets[2] + 0x06cc, dccg_regs[1].DCSURF_SEC_VIEWPORT_START_C = ctx->dcn_reg_offsets[2] + 0x06cb, dccg_regs[1].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x06e7, dccg_regs[1].DCSURF_PRIMARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x06e6, dccg_regs[1].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x06eb, dccg_regs[1].DCSURF_SECONDARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x06ea, dccg_regs[1].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x06ef, dccg_regs[1].DCSURF_PRIMARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x06ee, dccg_regs[1].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x06f3, dccg_regs[1].DCSURF_SECONDARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x06f2, dccg_regs[1].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x06e9, dccg_regs[1].DCSURF_PRIMARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x06e8, dccg_regs[1].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x06ed, dccg_regs[1].DCSURF_SECONDARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x06ec, dccg_regs[1].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x06f1, dccg_regs[1].DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x06f0, dccg_regs[1].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x06f5, dccg_regs[1].DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x06f4, dccg_regs[1].DCSURF_SURFACE_INUSE = ctx->dcn_reg_offsets[2] + 0x06fc, dccg_regs[1].DCSURF_SURFACE_INUSE_HIGH = ctx->dcn_reg_offsets[2] + 0x06fd, dccg_regs[1].DCSURF_SURFACE_INUSE_C = ctx->dcn_reg_offsets[2] + 0x06fe, dccg_regs[1].DCSURF_SURFACE_INUSE_HIGH_C = ctx->dcn_reg_offsets[2] + 0x06ff, dccg_regs[1].DCSURF_SURFACE_EARLIEST_INUSE = ctx->dcn_reg_offsets[2] + 0x0700, dccg_regs[1].DCSURF_SURFACE_EARLIEST_INUSE_HIGH = ctx->dcn_reg_offsets[2] + 0x0701, dccg_regs[1].DCSURF_SURFACE_EARLIEST_INUSE_C = ctx->dcn_reg_offsets[2] + 0x0702, dccg_regs[1].DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = ctx->dcn_reg_offsets[2] + 0x0703, dccg_regs[1].DCSURF_SURFACE_CONTROL = ctx->dcn_reg_offsets[2] + 0x06f6, dccg_regs[1].DCSURF_SURFACE_FLIP_INTERRUPT = ctx->dcn_reg_offsets[2] + 0x06fb, dccg_regs[1].HUBPRET_CONTROL = ctx->dcn_reg_offsets[2] + 0x0748, dccg_regs[1].HUBPRET_READ_LINE_STATUS = ctx->dcn_reg_offsets[2] + 0x0751, dccg_regs[1].DCN_EXPANSION_MODE = ctx->dcn_reg_offsets[2] + 0x0704, dccg_regs[1].DCHUBP_REQ_SIZE_CONFIG = ctx->dcn_reg_offsets[2] + 0x06cd, dccg_regs[1].DCHUBP_REQ_SIZE_CONFIG_C = ctx->dcn_reg_offsets[2] + 0x06ce, dccg_regs[1].BLANK_OFFSET_0 = ctx->dcn_reg_offsets[2] + 0x071f, dccg_regs[1].BLANK_OFFSET_1 = ctx->dcn_reg_offsets[2] + 0x0720, dccg_regs[1].DST_DIMENSIONS = ctx->dcn_reg_offsets[2] + 0x0721, dccg_regs[1].DST_AFTER_SCALER = ctx->dcn_reg_offsets[2] + 0x0722, dccg_regs[1].VBLANK_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x0725, dccg_regs[1].REF_FREQ_TO_PIX_FREQ = ctx->dcn_reg_offsets[2] + 0x0738, dccg_regs[1].VBLANK_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x0726, dccg_regs[1].VBLANK_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x0728, dccg_regs[1].NOM_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x0731, dccg_regs[1].NOM_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x0732, dccg_regs[1].PER_LINE_DELIVERY_PRE = ctx->dcn_reg_offsets[2] + 0x0735, dccg_regs[1].PER_LINE_DELIVERY = ctx->dcn_reg_offsets[2] + 0x0736, dccg_regs[1].VBLANK_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x0727, dccg_regs[1].VBLANK_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x0729, dccg_regs[1].NOM_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x0733, dccg_regs[1].NOM_PARAMETERS_7 = ctx->dcn_reg_offsets[2] + 0x0734, dccg_regs[1].DCN_TTU_QOS_WM = ctx->dcn_reg_offsets[2] + 0x0705, dccg_regs[1].DCN_GLOBAL_TTU_CNTL = ctx->dcn_reg_offsets[2] + 0x0706, dccg_regs[1].DCN_SURF0_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x0707, dccg_regs[1].DCN_SURF0_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x0708, dccg_regs[1].DCN_SURF1_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x0709, dccg_regs[1].DCN_SURF1_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x070a, dccg_regs[1].DCN_CUR0_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x070b, dccg_regs[1].DCN_CUR0_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x070c, dccg_regs[1].HUBP_CLK_CNTL = ctx->dcn_reg_offsets[2] + 0x06d0 ), ( dccg_regs[1].NOM_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x072d, dccg_regs[1].NOM_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x072e, dccg_regs[1].NOM_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x072f, dccg_regs[1].NOM_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x0730, dccg_regs[1].DCN_VM_MX_L1_TLB_CNTL = ctx->dcn_reg_offsets[2] + 0x071e ), dccg_regs[1].PREFETCH_SETTINGS = ctx->dcn_reg_offsets[2] + 0x0723, dccg_regs[1].PREFETCH_SETTINGS_C = ctx->dcn_reg_offsets[2] + 0x0724, dccg_regs[1].DCN_VM_SYSTEM_APERTURE_LOW_ADDR = ctx->dcn_reg_offsets[2] + 0x0710, dccg_regs[1].DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = ctx->dcn_reg_offsets[2] + 0x0711, dccg_regs[1].CURSOR_SETTINGS = ctx->dcn_reg_offsets[2] + 0x0737, dccg_regs[1].CURSOR_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x0756, dccg_regs[1].CURSOR_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x0755, dccg_regs[1].CURSOR_SIZE = ctx->dcn_reg_offsets[2] + 0x0757, dccg_regs[1].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0754, dccg_regs[1].CURSOR_POSITION = ctx->dcn_reg_offsets[2] + 0x0758, dccg_regs[1].CURSOR_HOT_SPOT = ctx->dcn_reg_offsets[2] + 0x0759, dccg_regs[1].CURSOR_DST_OFFSET = ctx->dcn_reg_offsets[2] + 0x075b, dccg_regs[1].DMDATA_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x075e, dccg_regs[1].DMDATA_ADDRESS_LOW = ctx->dcn_reg_offsets[2] + 0x075f, dccg_regs[1].DMDATA_CNTL = ctx->dcn_reg_offsets[2] + 0x0760, dccg_regs[1].DMDATA_SW_CNTL = ctx->dcn_reg_offsets[2] + 0x0763, dccg_regs[1].DMDATA_QOS_CNTL = ctx->dcn_reg_offsets[2] + 0x0761, dccg_regs[1].DMDATA_SW_DATA = ctx->dcn_reg_offsets[2] + 0x0764, dccg_regs[1].DMDATA_STATUS = ctx->dcn_reg_offsets[2] + 0x0762, dccg_regs[1].FLIP_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x072a, dccg_regs[1].FLIP_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x072b, dccg_regs[1].FLIP_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x072c, dccg_regs[1].DCN_CUR1_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x070d, dccg_regs[1].DCN_CUR1_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x070e, dccg_regs[1].DCSURF_FLIP_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x06f8, dccg_regs[1].VMID_SETTINGS_0 = ctx->dcn_reg_offsets[2] + 0x06e5 ), dccg_regs[1].FLIP_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x0740, dccg_regs[1].FLIP_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x0741, dccg_regs[1].FLIP_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x0742, dccg_regs[1].FLIP_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x0743, dccg_regs[1].VBLANK_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x073e, dccg_regs[1].VBLANK_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x073f ), dccg_regs[1].DCN_DMDATA_VM_CNTL = ctx->dcn_reg_offsets[2] + 0x070f ), dccg_regs[1].DCHUBP_MALL_CONFIG = ctx->dcn_reg_offsets[2] + 0x06d2, dccg_regs[1].DCHUBP_VMPG_CONFIG = ctx->dcn_reg_offsets[2] + 0x06d1, dccg_regs[1].UCLK_PSTATE_FORCE = ctx->dcn_reg_offsets[2] + 0x0744 ), |
906 | hubp_regs_init(2)( ( ( ( ( dccg_regs[2].DCHUBP_CNTL = ctx->dcn_reg_offsets[ 2] + 0x07ab, dccg_regs[2].HUBPREQ_DEBUG_DB = ctx->dcn_reg_offsets [2] + 0x07b0, dccg_regs[2].HUBPREQ_DEBUG = ctx->dcn_reg_offsets [2] + 0x07b1, dccg_regs[2].DCSURF_ADDR_CONFIG = ctx->dcn_reg_offsets [2] + 0x079e, dccg_regs[2].DCSURF_TILING_CONFIG = ctx->dcn_reg_offsets [2] + 0x079f, dccg_regs[2].DCSURF_SURFACE_PITCH = ctx->dcn_reg_offsets [2] + 0x07bf, dccg_regs[2].DCSURF_SURFACE_PITCH_C = ctx->dcn_reg_offsets [2] + 0x07c0, dccg_regs[2].DCSURF_SURFACE_CONFIG = ctx->dcn_reg_offsets [2] + 0x079d, dccg_regs[2].DCSURF_FLIP_CONTROL = ctx->dcn_reg_offsets [2] + 0x07d3, dccg_regs[2].DCSURF_PRI_VIEWPORT_DIMENSION = ctx ->dcn_reg_offsets[2] + 0x07a2, dccg_regs[2].DCSURF_PRI_VIEWPORT_START = ctx->dcn_reg_offsets[2] + 0x07a1, dccg_regs[2].DCSURF_SEC_VIEWPORT_DIMENSION = ctx->dcn_reg_offsets[2] + 0x07a6, dccg_regs[2].DCSURF_SEC_VIEWPORT_START = ctx->dcn_reg_offsets[2] + 0x07a5, dccg_regs[2].DCSURF_PRI_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets[2] + 0x07a4, dccg_regs[2].DCSURF_PRI_VIEWPORT_START_C = ctx->dcn_reg_offsets[2] + 0x07a3, dccg_regs[2].DCSURF_SEC_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets[2] + 0x07a8, dccg_regs[2].DCSURF_SEC_VIEWPORT_START_C = ctx->dcn_reg_offsets[2] + 0x07a7, dccg_regs[2].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x07c3, dccg_regs[2].DCSURF_PRIMARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x07c2, dccg_regs[2].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x07c7, dccg_regs[2].DCSURF_SECONDARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x07c6, dccg_regs[2].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x07cb, dccg_regs[2].DCSURF_PRIMARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x07ca, dccg_regs[2].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x07cf, dccg_regs[2].DCSURF_SECONDARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x07ce, dccg_regs[2].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x07c5, dccg_regs[2].DCSURF_PRIMARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x07c4, dccg_regs[2].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x07c9, dccg_regs[2].DCSURF_SECONDARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x07c8, dccg_regs[2].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x07cd, dccg_regs[2].DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x07cc, dccg_regs[2].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x07d1, dccg_regs[2].DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x07d0, dccg_regs[2].DCSURF_SURFACE_INUSE = ctx->dcn_reg_offsets[2] + 0x07d8, dccg_regs[2].DCSURF_SURFACE_INUSE_HIGH = ctx->dcn_reg_offsets[2] + 0x07d9, dccg_regs[2].DCSURF_SURFACE_INUSE_C = ctx->dcn_reg_offsets[2] + 0x07da, dccg_regs[2].DCSURF_SURFACE_INUSE_HIGH_C = ctx->dcn_reg_offsets[2] + 0x07db, dccg_regs[2].DCSURF_SURFACE_EARLIEST_INUSE = ctx->dcn_reg_offsets[2] + 0x07dc, dccg_regs[2].DCSURF_SURFACE_EARLIEST_INUSE_HIGH = ctx->dcn_reg_offsets[2] + 0x07dd, dccg_regs[2].DCSURF_SURFACE_EARLIEST_INUSE_C = ctx->dcn_reg_offsets[2] + 0x07de, dccg_regs[2].DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = ctx->dcn_reg_offsets[2] + 0x07df, dccg_regs[2].DCSURF_SURFACE_CONTROL = ctx->dcn_reg_offsets[2] + 0x07d2, dccg_regs[2].DCSURF_SURFACE_FLIP_INTERRUPT = ctx->dcn_reg_offsets[2] + 0x07d7, dccg_regs[2].HUBPRET_CONTROL = ctx->dcn_reg_offsets[2] + 0x0824, dccg_regs[2].HUBPRET_READ_LINE_STATUS = ctx->dcn_reg_offsets[2] + 0x082d, dccg_regs[2].DCN_EXPANSION_MODE = ctx->dcn_reg_offsets[2] + 0x07e0, dccg_regs[2].DCHUBP_REQ_SIZE_CONFIG = ctx->dcn_reg_offsets[2] + 0x07a9, dccg_regs[2].DCHUBP_REQ_SIZE_CONFIG_C = ctx->dcn_reg_offsets[2] + 0x07aa, dccg_regs[2].BLANK_OFFSET_0 = ctx->dcn_reg_offsets[2] + 0x07fb, dccg_regs[2].BLANK_OFFSET_1 = ctx->dcn_reg_offsets[2] + 0x07fc, dccg_regs[2].DST_DIMENSIONS = ctx->dcn_reg_offsets[2] + 0x07fd, dccg_regs[2].DST_AFTER_SCALER = ctx->dcn_reg_offsets[2] + 0x07fe, dccg_regs[2].VBLANK_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x0801, dccg_regs[2].REF_FREQ_TO_PIX_FREQ = ctx->dcn_reg_offsets[2] + 0x0814, dccg_regs[2].VBLANK_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x0802, dccg_regs[2].VBLANK_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x0804, dccg_regs[2].NOM_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x080d, dccg_regs[2].NOM_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x080e, dccg_regs[2].PER_LINE_DELIVERY_PRE = ctx->dcn_reg_offsets[2] + 0x0811, dccg_regs[2].PER_LINE_DELIVERY = ctx->dcn_reg_offsets[2] + 0x0812, dccg_regs[2].VBLANK_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x0803, dccg_regs[2].VBLANK_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x0805, dccg_regs[2].NOM_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x080f, dccg_regs[2].NOM_PARAMETERS_7 = ctx->dcn_reg_offsets[2] + 0x0810, dccg_regs[2].DCN_TTU_QOS_WM = ctx->dcn_reg_offsets[2] + 0x07e1, dccg_regs[2].DCN_GLOBAL_TTU_CNTL = ctx->dcn_reg_offsets[2] + 0x07e2, dccg_regs[2].DCN_SURF0_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x07e3, dccg_regs[2].DCN_SURF0_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x07e4, dccg_regs[2].DCN_SURF1_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x07e5, dccg_regs[2].DCN_SURF1_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x07e6, dccg_regs[2].DCN_CUR0_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x07e7, dccg_regs[2].DCN_CUR0_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x07e8, dccg_regs[2].HUBP_CLK_CNTL = ctx->dcn_reg_offsets[2] + 0x07ac ), ( dccg_regs[2].NOM_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x0809, dccg_regs[2].NOM_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x080a, dccg_regs[2].NOM_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x080b, dccg_regs[2].NOM_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x080c, dccg_regs[2].DCN_VM_MX_L1_TLB_CNTL = ctx->dcn_reg_offsets[2] + 0x07fa ), dccg_regs[2].PREFETCH_SETTINGS = ctx->dcn_reg_offsets[2] + 0x07ff, dccg_regs[2].PREFETCH_SETTINGS_C = ctx->dcn_reg_offsets[2] + 0x0800, dccg_regs[2].DCN_VM_SYSTEM_APERTURE_LOW_ADDR = ctx->dcn_reg_offsets[2] + 0x07ec, dccg_regs[2].DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = ctx->dcn_reg_offsets[2] + 0x07ed, dccg_regs[2].CURSOR_SETTINGS = ctx->dcn_reg_offsets[2] + 0x0813, dccg_regs[2].CURSOR_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x0832, dccg_regs[2].CURSOR_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x0831, dccg_regs[2].CURSOR_SIZE = ctx->dcn_reg_offsets[2] + 0x0833, dccg_regs[2].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0830, dccg_regs[2].CURSOR_POSITION = ctx->dcn_reg_offsets[2] + 0x0834, dccg_regs[2].CURSOR_HOT_SPOT = ctx->dcn_reg_offsets[2] + 0x0835, dccg_regs[2].CURSOR_DST_OFFSET = ctx->dcn_reg_offsets[2] + 0x0837, dccg_regs[2].DMDATA_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x083a, dccg_regs[2].DMDATA_ADDRESS_LOW = ctx->dcn_reg_offsets[2] + 0x083b, dccg_regs[2].DMDATA_CNTL = ctx->dcn_reg_offsets[2] + 0x083c, dccg_regs[2].DMDATA_SW_CNTL = ctx->dcn_reg_offsets[2] + 0x083f, dccg_regs[2].DMDATA_QOS_CNTL = ctx->dcn_reg_offsets[2] + 0x083d, dccg_regs[2].DMDATA_SW_DATA = ctx->dcn_reg_offsets[2] + 0x0840, dccg_regs[2].DMDATA_STATUS = ctx->dcn_reg_offsets[2] + 0x083e, dccg_regs[2].FLIP_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x0806, dccg_regs[2].FLIP_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x0807, dccg_regs[2].FLIP_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x0808, dccg_regs[2].DCN_CUR1_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x07e9, dccg_regs[2].DCN_CUR1_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x07ea, dccg_regs[2].DCSURF_FLIP_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x07d4, dccg_regs[2].VMID_SETTINGS_0 = ctx->dcn_reg_offsets[2] + 0x07c1 ), dccg_regs[2].FLIP_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x081c, dccg_regs[2].FLIP_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x081d, dccg_regs[2].FLIP_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x081e, dccg_regs[2].FLIP_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x081f, dccg_regs[2].VBLANK_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x081a, dccg_regs[2].VBLANK_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x081b ), dccg_regs[2].DCN_DMDATA_VM_CNTL = ctx->dcn_reg_offsets[2] + 0x07eb ), dccg_regs[2].DCHUBP_MALL_CONFIG = ctx->dcn_reg_offsets[2] + 0x07ae, dccg_regs[2].DCHUBP_VMPG_CONFIG = ctx->dcn_reg_offsets[2] + 0x07ad, dccg_regs[2].UCLK_PSTATE_FORCE = ctx->dcn_reg_offsets[2] + 0x0820 ), |
907 | hubp_regs_init(3)( ( ( ( ( dccg_regs[3].DCHUBP_CNTL = ctx->dcn_reg_offsets[ 2] + 0x0887, dccg_regs[3].HUBPREQ_DEBUG_DB = ctx->dcn_reg_offsets [2] + 0x088c, dccg_regs[3].HUBPREQ_DEBUG = ctx->dcn_reg_offsets [2] + 0x088d, dccg_regs[3].DCSURF_ADDR_CONFIG = ctx->dcn_reg_offsets [2] + 0x087a, dccg_regs[3].DCSURF_TILING_CONFIG = ctx->dcn_reg_offsets [2] + 0x087b, dccg_regs[3].DCSURF_SURFACE_PITCH = ctx->dcn_reg_offsets [2] + 0x089b, dccg_regs[3].DCSURF_SURFACE_PITCH_C = ctx->dcn_reg_offsets [2] + 0x089c, dccg_regs[3].DCSURF_SURFACE_CONFIG = ctx->dcn_reg_offsets [2] + 0x0879, dccg_regs[3].DCSURF_FLIP_CONTROL = ctx->dcn_reg_offsets [2] + 0x08af, dccg_regs[3].DCSURF_PRI_VIEWPORT_DIMENSION = ctx ->dcn_reg_offsets[2] + 0x087e, dccg_regs[3].DCSURF_PRI_VIEWPORT_START = ctx->dcn_reg_offsets[2] + 0x087d, dccg_regs[3].DCSURF_SEC_VIEWPORT_DIMENSION = ctx->dcn_reg_offsets[2] + 0x0882, dccg_regs[3].DCSURF_SEC_VIEWPORT_START = ctx->dcn_reg_offsets[2] + 0x0881, dccg_regs[3].DCSURF_PRI_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets[2] + 0x0880, dccg_regs[3].DCSURF_PRI_VIEWPORT_START_C = ctx->dcn_reg_offsets[2] + 0x087f, dccg_regs[3].DCSURF_SEC_VIEWPORT_DIMENSION_C = ctx->dcn_reg_offsets[2] + 0x0884, dccg_regs[3].DCSURF_SEC_VIEWPORT_START_C = ctx->dcn_reg_offsets[2] + 0x0883, dccg_regs[3].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x089f, dccg_regs[3].DCSURF_PRIMARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x089e, dccg_regs[3].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x08a3, dccg_regs[3].DCSURF_SECONDARY_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x08a2, dccg_regs[3].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x08a7, dccg_regs[3].DCSURF_PRIMARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x08a6, dccg_regs[3].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x08ab, dccg_regs[3].DCSURF_SECONDARY_META_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x08aa, dccg_regs[3].DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x08a1, dccg_regs[3].DCSURF_PRIMARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x08a0, dccg_regs[3].DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x08a5, dccg_regs[3].DCSURF_SECONDARY_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x08a4, dccg_regs[3].DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x08a9, dccg_regs[3].DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x08a8, dccg_regs[3].DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = ctx->dcn_reg_offsets[2] + 0x08ad, dccg_regs[3].DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = ctx->dcn_reg_offsets[2] + 0x08ac, dccg_regs[3].DCSURF_SURFACE_INUSE = ctx->dcn_reg_offsets[2] + 0x08b4, dccg_regs[3].DCSURF_SURFACE_INUSE_HIGH = ctx->dcn_reg_offsets[2] + 0x08b5, dccg_regs[3].DCSURF_SURFACE_INUSE_C = ctx->dcn_reg_offsets[2] + 0x08b6, dccg_regs[3].DCSURF_SURFACE_INUSE_HIGH_C = ctx->dcn_reg_offsets[2] + 0x08b7, dccg_regs[3].DCSURF_SURFACE_EARLIEST_INUSE = ctx->dcn_reg_offsets[2] + 0x08b8, dccg_regs[3].DCSURF_SURFACE_EARLIEST_INUSE_HIGH = ctx->dcn_reg_offsets[2] + 0x08b9, dccg_regs[3].DCSURF_SURFACE_EARLIEST_INUSE_C = ctx->dcn_reg_offsets[2] + 0x08ba, dccg_regs[3].DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = ctx->dcn_reg_offsets[2] + 0x08bb, dccg_regs[3].DCSURF_SURFACE_CONTROL = ctx->dcn_reg_offsets[2] + 0x08ae, dccg_regs[3].DCSURF_SURFACE_FLIP_INTERRUPT = ctx->dcn_reg_offsets[2] + 0x08b3, dccg_regs[3].HUBPRET_CONTROL = ctx->dcn_reg_offsets[2] + 0x0900, dccg_regs[3].HUBPRET_READ_LINE_STATUS = ctx->dcn_reg_offsets[2] + 0x0909, dccg_regs[3].DCN_EXPANSION_MODE = ctx->dcn_reg_offsets[2] + 0x08bc, dccg_regs[3].DCHUBP_REQ_SIZE_CONFIG = ctx->dcn_reg_offsets[2] + 0x0885, dccg_regs[3].DCHUBP_REQ_SIZE_CONFIG_C = ctx->dcn_reg_offsets[2] + 0x0886, dccg_regs[3].BLANK_OFFSET_0 = ctx->dcn_reg_offsets[2] + 0x08d7, dccg_regs[3].BLANK_OFFSET_1 = ctx->dcn_reg_offsets[2] + 0x08d8, dccg_regs[3].DST_DIMENSIONS = ctx->dcn_reg_offsets[2] + 0x08d9, dccg_regs[3].DST_AFTER_SCALER = ctx->dcn_reg_offsets[2] + 0x08da, dccg_regs[3].VBLANK_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x08dd, dccg_regs[3].REF_FREQ_TO_PIX_FREQ = ctx->dcn_reg_offsets[2] + 0x08f0, dccg_regs[3].VBLANK_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x08de, dccg_regs[3].VBLANK_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x08e0, dccg_regs[3].NOM_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x08e9, dccg_regs[3].NOM_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x08ea, dccg_regs[3].PER_LINE_DELIVERY_PRE = ctx->dcn_reg_offsets[2] + 0x08ed, dccg_regs[3].PER_LINE_DELIVERY = ctx->dcn_reg_offsets[2] + 0x08ee, dccg_regs[3].VBLANK_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x08df, dccg_regs[3].VBLANK_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x08e1, dccg_regs[3].NOM_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x08eb, dccg_regs[3].NOM_PARAMETERS_7 = ctx->dcn_reg_offsets[2] + 0x08ec, dccg_regs[3].DCN_TTU_QOS_WM = ctx->dcn_reg_offsets[2] + 0x08bd, dccg_regs[3].DCN_GLOBAL_TTU_CNTL = ctx->dcn_reg_offsets[2] + 0x08be, dccg_regs[3].DCN_SURF0_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x08bf, dccg_regs[3].DCN_SURF0_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x08c0, dccg_regs[3].DCN_SURF1_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x08c1, dccg_regs[3].DCN_SURF1_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x08c2, dccg_regs[3].DCN_CUR0_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x08c3, dccg_regs[3].DCN_CUR0_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x08c4, dccg_regs[3].HUBP_CLK_CNTL = ctx->dcn_reg_offsets[2] + 0x0888 ), ( dccg_regs[3].NOM_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x08e5, dccg_regs[3].NOM_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x08e6, dccg_regs[3].NOM_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x08e7, dccg_regs[3].NOM_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x08e8, dccg_regs[3].DCN_VM_MX_L1_TLB_CNTL = ctx->dcn_reg_offsets[2] + 0x08d6 ), dccg_regs[3].PREFETCH_SETTINGS = ctx->dcn_reg_offsets[2] + 0x08db, dccg_regs[3].PREFETCH_SETTINGS_C = ctx->dcn_reg_offsets[2] + 0x08dc, dccg_regs[3].DCN_VM_SYSTEM_APERTURE_LOW_ADDR = ctx->dcn_reg_offsets[2] + 0x08c8, dccg_regs[3].DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = ctx->dcn_reg_offsets[2] + 0x08c9, dccg_regs[3].CURSOR_SETTINGS = ctx->dcn_reg_offsets[2] + 0x08ef, dccg_regs[3].CURSOR_SURFACE_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x090e, dccg_regs[3].CURSOR_SURFACE_ADDRESS = ctx->dcn_reg_offsets[2] + 0x090d, dccg_regs[3].CURSOR_SIZE = ctx->dcn_reg_offsets[2] + 0x090f, dccg_regs[3].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x090c, dccg_regs[3].CURSOR_POSITION = ctx->dcn_reg_offsets[2] + 0x0910, dccg_regs[3].CURSOR_HOT_SPOT = ctx->dcn_reg_offsets[2] + 0x0911, dccg_regs[3].CURSOR_DST_OFFSET = ctx->dcn_reg_offsets[2] + 0x0913, dccg_regs[3].DMDATA_ADDRESS_HIGH = ctx->dcn_reg_offsets[2] + 0x0916, dccg_regs[3].DMDATA_ADDRESS_LOW = ctx->dcn_reg_offsets[2] + 0x0917, dccg_regs[3].DMDATA_CNTL = ctx->dcn_reg_offsets[2] + 0x0918, dccg_regs[3].DMDATA_SW_CNTL = ctx->dcn_reg_offsets[2] + 0x091b, dccg_regs[3].DMDATA_QOS_CNTL = ctx->dcn_reg_offsets[2] + 0x0919, dccg_regs[3].DMDATA_SW_DATA = ctx->dcn_reg_offsets[2] + 0x091c, dccg_regs[3].DMDATA_STATUS = ctx->dcn_reg_offsets[2] + 0x091a, dccg_regs[3].FLIP_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x08e2, dccg_regs[3].FLIP_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x08e3, dccg_regs[3].FLIP_PARAMETERS_2 = ctx->dcn_reg_offsets[2] + 0x08e4, dccg_regs[3].DCN_CUR1_TTU_CNTL0 = ctx->dcn_reg_offsets[2] + 0x08c5, dccg_regs[3].DCN_CUR1_TTU_CNTL1 = ctx->dcn_reg_offsets[2] + 0x08c6, dccg_regs[3].DCSURF_FLIP_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x08b0, dccg_regs[3].VMID_SETTINGS_0 = ctx->dcn_reg_offsets[2] + 0x089d ), dccg_regs[3].FLIP_PARAMETERS_3 = ctx->dcn_reg_offsets[2] + 0x08f8, dccg_regs[3].FLIP_PARAMETERS_4 = ctx->dcn_reg_offsets[2] + 0x08f9, dccg_regs[3].FLIP_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x08fa, dccg_regs[3].FLIP_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x08fb, dccg_regs[3].VBLANK_PARAMETERS_5 = ctx->dcn_reg_offsets[2] + 0x08f6, dccg_regs[3].VBLANK_PARAMETERS_6 = ctx->dcn_reg_offsets[2] + 0x08f7 ), dccg_regs[3].DCN_DMDATA_VM_CNTL = ctx->dcn_reg_offsets[2] + 0x08c7 ), dccg_regs[3].DCHUBP_MALL_CONFIG = ctx->dcn_reg_offsets[2] + 0x088a, dccg_regs[3].DCHUBP_VMPG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0889, dccg_regs[3].UCLK_PSTATE_FORCE = ctx->dcn_reg_offsets[2] + 0x08fc ); |
908 | |
909 | if (hubp32_construct(hubp2, ctx, inst, |
910 | &hubp_regs[inst], &hubp_shift, &hubp_mask)) |
911 | return &hubp2->base; |
912 | |
913 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 913); do {} while (0); } while (0); |
914 | kfree(hubp2); |
915 | return NULL((void *)0); |
916 | } |
917 | |
918 | static void dcn32_dpp_destroy(struct dpp **dpp) |
919 | { |
920 | kfree(TO_DCN30_DPP(*dpp)({ const __typeof( ((struct dcn3_dpp *)0)->base ) *__mptr = (*dpp); (struct dcn3_dpp *)( (char *)__mptr - __builtin_offsetof (struct dcn3_dpp, base) );})); |
921 | *dpp = NULL((void *)0); |
922 | } |
923 | |
924 | static struct dpp *dcn32_dpp_create( |
925 | struct dc_context *ctx, |
926 | uint32_t inst) |
927 | { |
928 | struct dcn3_dpp *dpp3 = |
929 | kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL(0x0001 | 0x0004)); |
930 | |
931 | if (!dpp3) |
932 | return NULL((void *)0); |
933 | |
934 | #undef REG_STRUCTdccg_regs |
935 | #define REG_STRUCTdccg_regs dpp_regs |
936 | dpp_regs_init(0)( dccg_regs[0].CM_DEALPHA = ctx->dcn_reg_offsets[2] + 0x0d8b , dccg_regs[0].CM_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x0d89, dccg_regs[0].CM_BIAS_CR_R = ctx->dcn_reg_offsets [2] + 0x0d3b, dccg_regs[0].CM_BIAS_Y_G_CB_B = ctx->dcn_reg_offsets [2] + 0x0d3c, dccg_regs[0].PRE_DEGAM = ctx->dcn_reg_offsets [2] + 0x0ced, dccg_regs[0].CM_GAMCOR_CONTROL = ctx->dcn_reg_offsets [2] + 0x0d3d, dccg_regs[0].CM_GAMCOR_LUT_CONTROL = ctx->dcn_reg_offsets [2] + 0x0d40, dccg_regs[0].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets [2] + 0x0d3e, dccg_regs[0].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets [2] + 0x0d3e, dccg_regs[0].CM_GAMCOR_LUT_DATA = ctx->dcn_reg_offsets [2] + 0x0d3f, dccg_regs[0].CM_GAMCOR_RAMB_START_CNTL_B = ctx-> dcn_reg_offsets[2] + 0x0d64, dccg_regs[0].CM_GAMCOR_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0d65, dccg_regs[0].CM_GAMCOR_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0d66, dccg_regs[0].CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0d67, dccg_regs[0].CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0d68, dccg_regs[0].CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0d69, dccg_regs[0].CM_GAMCOR_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x0d6d, dccg_regs[0].CM_GAMCOR_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x0d6e, dccg_regs[0].CM_GAMCOR_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x0d6f, dccg_regs[0].CM_GAMCOR_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x0d70, dccg_regs[0].CM_GAMCOR_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x0d71, dccg_regs[0].CM_GAMCOR_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x0d72, dccg_regs[0].CM_GAMCOR_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x0d76, dccg_regs[0].CM_GAMCOR_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x0d86, dccg_regs[0].CM_GAMCOR_RAMB_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x0d73, dccg_regs[0].CM_GAMCOR_RAMB_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x0d74, dccg_regs[0].CM_GAMCOR_RAMB_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x0d75, dccg_regs[0].CM_GAMCOR_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0d6a, dccg_regs[0].CM_GAMCOR_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0d6b, dccg_regs[0].CM_GAMCOR_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0d6c, dccg_regs[0].CM_GAMCOR_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0d41, dccg_regs[0].CM_GAMCOR_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0d42, dccg_regs[0].CM_GAMCOR_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0d43, dccg_regs[0].CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0d44, dccg_regs[0].CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0d45, dccg_regs[0].CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0d46, dccg_regs[0].CM_GAMCOR_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x0d4a, dccg_regs[0].CM_GAMCOR_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x0d4b, dccg_regs[0].CM_GAMCOR_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x0d4c, dccg_regs[0].CM_GAMCOR_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x0d4d, dccg_regs[0].CM_GAMCOR_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x0d4e, dccg_regs[0].CM_GAMCOR_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x0d4f, dccg_regs[0].CM_GAMCOR_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x0d53, dccg_regs[0].CM_GAMCOR_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x0d63, dccg_regs[0].CM_GAMCOR_RAMA_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x0d50, dccg_regs[0].CM_GAMCOR_RAMA_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x0d51, dccg_regs[0].CM_GAMCOR_RAMA_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x0d52, dccg_regs[0].CM_GAMCOR_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0d47, dccg_regs[0].CM_GAMCOR_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0d48, dccg_regs[0].CM_GAMCOR_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0d49, dccg_regs[0].CM_GAMUT_REMAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0d2e, dccg_regs[0].CM_GAMUT_REMAP_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0d2f, dccg_regs[0].CM_GAMUT_REMAP_C13_C14 = ctx->dcn_reg_offsets[2] + 0x0d30, dccg_regs[0].CM_GAMUT_REMAP_C21_C22 = ctx->dcn_reg_offsets[2] + 0x0d31, dccg_regs[0].CM_GAMUT_REMAP_C23_C24 = ctx->dcn_reg_offsets[2] + 0x0d32, dccg_regs[0].CM_GAMUT_REMAP_C31_C32 = ctx->dcn_reg_offsets[2] + 0x0d33, dccg_regs[0].CM_GAMUT_REMAP_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0d34, dccg_regs[0].CM_GAMUT_REMAP_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0d35, dccg_regs[0].CM_GAMUT_REMAP_B_C13_C14 = ctx->dcn_reg_offsets[2] + 0x0d36, dccg_regs[0].CM_GAMUT_REMAP_B_C21_C22 = ctx->dcn_reg_offsets[2] + 0x0d37, dccg_regs[0].CM_GAMUT_REMAP_B_C23_C24 = ctx->dcn_reg_offsets[2] + 0x0d38, dccg_regs[0].CM_GAMUT_REMAP_B_C31_C32 = ctx->dcn_reg_offsets[2] + 0x0d39, dccg_regs[0].CM_GAMUT_REMAP_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0d3a, dccg_regs[0].DSCL_EXT_OVERSCAN_LEFT_RIGHT = ctx->dcn_reg_offsets[2] + 0x0d0d, dccg_regs[0].DSCL_EXT_OVERSCAN_TOP_BOTTOM = ctx->dcn_reg_offsets[2] + 0x0d0e, dccg_regs[0].OTG_H_BLANK = ctx->dcn_reg_offsets[2] + 0x0d0f, dccg_regs[0].OTG_V_BLANK = ctx->dcn_reg_offsets[2] + 0x0d10, dccg_regs[0].SCL_MODE = ctx->dcn_reg_offsets[2] + 0x0cfb, dccg_regs[0].LB_DATA_FORMAT = ctx->dcn_reg_offsets[2] + 0x0d14, dccg_regs[0].LB_MEMORY_CTRL = ctx->dcn_reg_offsets[2] + 0x0d15, dccg_regs[0].DSCL_AUTOCAL = ctx->dcn_reg_offsets[2] + 0x0d0c, dccg_regs[0].SCL_TAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0cfc, dccg_regs[0].SCL_COEF_RAM_TAP_SELECT = ctx->dcn_reg_offsets[2] + 0x0cf9, dccg_regs[0].SCL_COEF_RAM_TAP_DATA = ctx->dcn_reg_offsets[2] + 0x0cfa, dccg_regs[0].DSCL_2TAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0cfe, dccg_regs[0].MPC_SIZE = ctx->dcn_reg_offsets[2] + 0x0d13, dccg_regs[0].SCL_HORZ_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets[2] + 0x0d00, dccg_regs[0].SCL_VERT_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets[2] + 0x0d04, dccg_regs[0].SCL_HORZ_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets[2] + 0x0d02, dccg_regs[0].SCL_VERT_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets[2] + 0x0d07, dccg_regs[0].SCL_HORZ_FILTER_INIT = ctx->dcn_reg_offsets[2] + 0x0d01, dccg_regs[0].SCL_HORZ_FILTER_INIT_C = ctx->dcn_reg_offsets[2] + 0x0d03, dccg_regs[0].SCL_VERT_FILTER_INIT = ctx->dcn_reg_offsets[2] + 0x0d05, dccg_regs[0].SCL_VERT_FILTER_INIT_C = ctx->dcn_reg_offsets[2] + 0x0d08, dccg_regs[0].RECOUT_START = ctx->dcn_reg_offsets[2] + 0x0d11, dccg_regs[0].RECOUT_SIZE = ctx->dcn_reg_offsets[2] + 0x0d12, dccg_regs[0].PRE_DEALPHA = ctx->dcn_reg_offsets[2] + 0x0cde, dccg_regs[0].PRE_REALPHA = ctx->dcn_reg_offsets[2] + 0x0cee, dccg_regs[0].PRE_CSC_MODE = ctx->dcn_reg_offsets[2] + 0x0cdf, dccg_regs[0].PRE_CSC_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0ce0, dccg_regs[0].PRE_CSC_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0ce5, dccg_regs[0].PRE_CSC_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0ce6, dccg_regs[0].PRE_CSC_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0ceb, dccg_regs[0].CM_POST_CSC_CONTROL = ctx->dcn_reg_offsets[2] + 0x0d21, dccg_regs[0].CM_POST_CSC_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0d22, dccg_regs[0].CM_POST_CSC_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0d27, dccg_regs[0].CM_POST_CSC_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0d28, dccg_regs[0].CM_POST_CSC_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0d2d, dccg_regs[0].CM_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x0d88, dccg_regs[0].CM_CONTROL = ctx->dcn_reg_offsets[2] + 0x0d20, dccg_regs[0].FORMAT_CONTROL = ctx->dcn_reg_offsets[2] + 0x0cd0, dccg_regs[0].CNVC_SURFACE_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x0ccf, dccg_regs[0].CURSOR0_CONTROL = ctx->dcn_reg_offsets[2] + 0x0cf1, dccg_regs[0].CURSOR0_COLOR0 = ctx->dcn_reg_offsets[2] + 0x0cf2, dccg_regs[0].CURSOR0_COLOR1 = ctx->dcn_reg_offsets[2] + 0x0cf3, dccg_regs[0].CURSOR0_FP_SCALE_BIAS = ctx->dcn_reg_offsets[2] + 0x0cf4, dccg_regs[0].DPP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0cc5, dccg_regs[0].CM_HDR_MULT_COEF = ctx->dcn_reg_offsets[2] + 0x0d87, dccg_regs[0].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0678, dccg_regs[0].ALPHA_2BIT_LUT = ctx->dcn_reg_offsets[2] + 0x0cdd, dccg_regs[0].FCNV_FP_BIAS_R = ctx->dcn_reg_offsets[2] + 0x0cd1, dccg_regs[0].FCNV_FP_BIAS_G = ctx->dcn_reg_offsets[2] + 0x0cd2, dccg_regs[0].FCNV_FP_BIAS_B = ctx->dcn_reg_offsets[2] + 0x0cd3, dccg_regs[0].FCNV_FP_SCALE_R = ctx->dcn_reg_offsets[2] + 0x0cd4, dccg_regs[0].FCNV_FP_SCALE_G = ctx->dcn_reg_offsets[2] + 0x0cd5, dccg_regs[0].FCNV_FP_SCALE_B = ctx->dcn_reg_offsets[2] + 0x0cd6, dccg_regs[0].COLOR_KEYER_CONTROL = ctx->dcn_reg_offsets[2] + 0x0cd7, dccg_regs[0].COLOR_KEYER_ALPHA = ctx->dcn_reg_offsets[2] + 0x0cd8, dccg_regs[0].COLOR_KEYER_RED = ctx->dcn_reg_offsets[2] + 0x0cd9, dccg_regs[0].COLOR_KEYER_GREEN = ctx->dcn_reg_offsets[2] + 0x0cda, dccg_regs[0].COLOR_KEYER_BLUE = ctx->dcn_reg_offsets[2] + 0x0cdb, dccg_regs[0].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0678, dccg_regs[0].OBUF_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x0d1a, dccg_regs[0].DSCL_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x0d18, dccg_regs[0].DSCL_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x0d17 ), |
937 | dpp_regs_init(1)( dccg_regs[1].CM_DEALPHA = ctx->dcn_reg_offsets[2] + 0x0ef6 , dccg_regs[1].CM_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x0ef4, dccg_regs[1].CM_BIAS_CR_R = ctx->dcn_reg_offsets [2] + 0x0ea6, dccg_regs[1].CM_BIAS_Y_G_CB_B = ctx->dcn_reg_offsets [2] + 0x0ea7, dccg_regs[1].PRE_DEGAM = ctx->dcn_reg_offsets [2] + 0x0e58, dccg_regs[1].CM_GAMCOR_CONTROL = ctx->dcn_reg_offsets [2] + 0x0ea8, dccg_regs[1].CM_GAMCOR_LUT_CONTROL = ctx->dcn_reg_offsets [2] + 0x0eab, dccg_regs[1].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets [2] + 0x0ea9, dccg_regs[1].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets [2] + 0x0ea9, dccg_regs[1].CM_GAMCOR_LUT_DATA = ctx->dcn_reg_offsets [2] + 0x0eaa, dccg_regs[1].CM_GAMCOR_RAMB_START_CNTL_B = ctx-> dcn_reg_offsets[2] + 0x0ecf, dccg_regs[1].CM_GAMCOR_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0ed0, dccg_regs[1].CM_GAMCOR_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0ed1, dccg_regs[1].CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0ed2, dccg_regs[1].CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0ed3, dccg_regs[1].CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0ed4, dccg_regs[1].CM_GAMCOR_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x0ed8, dccg_regs[1].CM_GAMCOR_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x0ed9, dccg_regs[1].CM_GAMCOR_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x0eda, dccg_regs[1].CM_GAMCOR_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x0edb, dccg_regs[1].CM_GAMCOR_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x0edc, dccg_regs[1].CM_GAMCOR_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x0edd, dccg_regs[1].CM_GAMCOR_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x0ee1, dccg_regs[1].CM_GAMCOR_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x0ef1, dccg_regs[1].CM_GAMCOR_RAMB_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x0ede, dccg_regs[1].CM_GAMCOR_RAMB_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x0edf, dccg_regs[1].CM_GAMCOR_RAMB_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x0ee0, dccg_regs[1].CM_GAMCOR_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0ed5, dccg_regs[1].CM_GAMCOR_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0ed6, dccg_regs[1].CM_GAMCOR_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0ed7, dccg_regs[1].CM_GAMCOR_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0eac, dccg_regs[1].CM_GAMCOR_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0ead, dccg_regs[1].CM_GAMCOR_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0eae, dccg_regs[1].CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0eaf, dccg_regs[1].CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0eb0, dccg_regs[1].CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0eb1, dccg_regs[1].CM_GAMCOR_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x0eb5, dccg_regs[1].CM_GAMCOR_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x0eb6, dccg_regs[1].CM_GAMCOR_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x0eb7, dccg_regs[1].CM_GAMCOR_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x0eb8, dccg_regs[1].CM_GAMCOR_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x0eb9, dccg_regs[1].CM_GAMCOR_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x0eba, dccg_regs[1].CM_GAMCOR_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x0ebe, dccg_regs[1].CM_GAMCOR_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x0ece, dccg_regs[1].CM_GAMCOR_RAMA_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x0ebb, dccg_regs[1].CM_GAMCOR_RAMA_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x0ebc, dccg_regs[1].CM_GAMCOR_RAMA_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x0ebd, dccg_regs[1].CM_GAMCOR_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x0eb2, dccg_regs[1].CM_GAMCOR_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x0eb3, dccg_regs[1].CM_GAMCOR_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x0eb4, dccg_regs[1].CM_GAMUT_REMAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e99, dccg_regs[1].CM_GAMUT_REMAP_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0e9a, dccg_regs[1].CM_GAMUT_REMAP_C13_C14 = ctx->dcn_reg_offsets[2] + 0x0e9b, dccg_regs[1].CM_GAMUT_REMAP_C21_C22 = ctx->dcn_reg_offsets[2] + 0x0e9c, dccg_regs[1].CM_GAMUT_REMAP_C23_C24 = ctx->dcn_reg_offsets[2] + 0x0e9d, dccg_regs[1].CM_GAMUT_REMAP_C31_C32 = ctx->dcn_reg_offsets[2] + 0x0e9e, dccg_regs[1].CM_GAMUT_REMAP_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0e9f, dccg_regs[1].CM_GAMUT_REMAP_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0ea0, dccg_regs[1].CM_GAMUT_REMAP_B_C13_C14 = ctx->dcn_reg_offsets[2] + 0x0ea1, dccg_regs[1].CM_GAMUT_REMAP_B_C21_C22 = ctx->dcn_reg_offsets[2] + 0x0ea2, dccg_regs[1].CM_GAMUT_REMAP_B_C23_C24 = ctx->dcn_reg_offsets[2] + 0x0ea3, dccg_regs[1].CM_GAMUT_REMAP_B_C31_C32 = ctx->dcn_reg_offsets[2] + 0x0ea4, dccg_regs[1].CM_GAMUT_REMAP_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0ea5, dccg_regs[1].DSCL_EXT_OVERSCAN_LEFT_RIGHT = ctx->dcn_reg_offsets[2] + 0x0e78, dccg_regs[1].DSCL_EXT_OVERSCAN_TOP_BOTTOM = ctx->dcn_reg_offsets[2] + 0x0e79, dccg_regs[1].OTG_H_BLANK = ctx->dcn_reg_offsets[2] + 0x0e7a, dccg_regs[1].OTG_V_BLANK = ctx->dcn_reg_offsets[2] + 0x0e7b, dccg_regs[1].SCL_MODE = ctx->dcn_reg_offsets[2] + 0x0e66, dccg_regs[1].LB_DATA_FORMAT = ctx->dcn_reg_offsets[2] + 0x0e7f, dccg_regs[1].LB_MEMORY_CTRL = ctx->dcn_reg_offsets[2] + 0x0e80, dccg_regs[1].DSCL_AUTOCAL = ctx->dcn_reg_offsets[2] + 0x0e77, dccg_regs[1].SCL_TAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e67, dccg_regs[1].SCL_COEF_RAM_TAP_SELECT = ctx->dcn_reg_offsets[2] + 0x0e64, dccg_regs[1].SCL_COEF_RAM_TAP_DATA = ctx->dcn_reg_offsets[2] + 0x0e65, dccg_regs[1].DSCL_2TAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e69, dccg_regs[1].MPC_SIZE = ctx->dcn_reg_offsets[2] + 0x0e7e, dccg_regs[1].SCL_HORZ_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets[2] + 0x0e6b, dccg_regs[1].SCL_VERT_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets[2] + 0x0e6f, dccg_regs[1].SCL_HORZ_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets[2] + 0x0e6d, dccg_regs[1].SCL_VERT_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets[2] + 0x0e72, dccg_regs[1].SCL_HORZ_FILTER_INIT = ctx->dcn_reg_offsets[2] + 0x0e6c, dccg_regs[1].SCL_HORZ_FILTER_INIT_C = ctx->dcn_reg_offsets[2] + 0x0e6e, dccg_regs[1].SCL_VERT_FILTER_INIT = ctx->dcn_reg_offsets[2] + 0x0e70, dccg_regs[1].SCL_VERT_FILTER_INIT_C = ctx->dcn_reg_offsets[2] + 0x0e73, dccg_regs[1].RECOUT_START = ctx->dcn_reg_offsets[2] + 0x0e7c, dccg_regs[1].RECOUT_SIZE = ctx->dcn_reg_offsets[2] + 0x0e7d, dccg_regs[1].PRE_DEALPHA = ctx->dcn_reg_offsets[2] + 0x0e49, dccg_regs[1].PRE_REALPHA = ctx->dcn_reg_offsets[2] + 0x0e59, dccg_regs[1].PRE_CSC_MODE = ctx->dcn_reg_offsets[2] + 0x0e4a, dccg_regs[1].PRE_CSC_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0e4b, dccg_regs[1].PRE_CSC_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0e50, dccg_regs[1].PRE_CSC_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0e51, dccg_regs[1].PRE_CSC_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0e56, dccg_regs[1].CM_POST_CSC_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e8c, dccg_regs[1].CM_POST_CSC_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0e8d, dccg_regs[1].CM_POST_CSC_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0e92, dccg_regs[1].CM_POST_CSC_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0e93, dccg_regs[1].CM_POST_CSC_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0e98, dccg_regs[1].CM_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x0ef3, dccg_regs[1].CM_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e8b, dccg_regs[1].FORMAT_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e3b, dccg_regs[1].CNVC_SURFACE_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x0e3a, dccg_regs[1].CURSOR0_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e5c, dccg_regs[1].CURSOR0_COLOR0 = ctx->dcn_reg_offsets[2] + 0x0e5d, dccg_regs[1].CURSOR0_COLOR1 = ctx->dcn_reg_offsets[2] + 0x0e5e, dccg_regs[1].CURSOR0_FP_SCALE_BIAS = ctx->dcn_reg_offsets[2] + 0x0e5f, dccg_regs[1].DPP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e30, dccg_regs[1].CM_HDR_MULT_COEF = ctx->dcn_reg_offsets[2] + 0x0ef2, dccg_regs[1].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0754, dccg_regs[1].ALPHA_2BIT_LUT = ctx->dcn_reg_offsets[2] + 0x0e48, dccg_regs[1].FCNV_FP_BIAS_R = ctx->dcn_reg_offsets[2] + 0x0e3c, dccg_regs[1].FCNV_FP_BIAS_G = ctx->dcn_reg_offsets[2] + 0x0e3d, dccg_regs[1].FCNV_FP_BIAS_B = ctx->dcn_reg_offsets[2] + 0x0e3e, dccg_regs[1].FCNV_FP_SCALE_R = ctx->dcn_reg_offsets[2] + 0x0e3f, dccg_regs[1].FCNV_FP_SCALE_G = ctx->dcn_reg_offsets[2] + 0x0e40, dccg_regs[1].FCNV_FP_SCALE_B = ctx->dcn_reg_offsets[2] + 0x0e41, dccg_regs[1].COLOR_KEYER_CONTROL = ctx->dcn_reg_offsets[2] + 0x0e42, dccg_regs[1].COLOR_KEYER_ALPHA = ctx->dcn_reg_offsets[2] + 0x0e43, dccg_regs[1].COLOR_KEYER_RED = ctx->dcn_reg_offsets[2] + 0x0e44, dccg_regs[1].COLOR_KEYER_GREEN = ctx->dcn_reg_offsets[2] + 0x0e45, dccg_regs[1].COLOR_KEYER_BLUE = ctx->dcn_reg_offsets[2] + 0x0e46, dccg_regs[1].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0754, dccg_regs[1].OBUF_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x0e85, dccg_regs[1].DSCL_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x0e83, dccg_regs[1].DSCL_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x0e82 ), |
938 | dpp_regs_init(2)( dccg_regs[2].CM_DEALPHA = ctx->dcn_reg_offsets[2] + 0x1061 , dccg_regs[2].CM_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x105f, dccg_regs[2].CM_BIAS_CR_R = ctx->dcn_reg_offsets [2] + 0x1011, dccg_regs[2].CM_BIAS_Y_G_CB_B = ctx->dcn_reg_offsets [2] + 0x1012, dccg_regs[2].PRE_DEGAM = ctx->dcn_reg_offsets [2] + 0x0fc3, dccg_regs[2].CM_GAMCOR_CONTROL = ctx->dcn_reg_offsets [2] + 0x1013, dccg_regs[2].CM_GAMCOR_LUT_CONTROL = ctx->dcn_reg_offsets [2] + 0x1016, dccg_regs[2].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets [2] + 0x1014, dccg_regs[2].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets [2] + 0x1014, dccg_regs[2].CM_GAMCOR_LUT_DATA = ctx->dcn_reg_offsets [2] + 0x1015, dccg_regs[2].CM_GAMCOR_RAMB_START_CNTL_B = ctx-> dcn_reg_offsets[2] + 0x103a, dccg_regs[2].CM_GAMCOR_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x103b, dccg_regs[2].CM_GAMCOR_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x103c, dccg_regs[2].CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x103d, dccg_regs[2].CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x103e, dccg_regs[2].CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x103f, dccg_regs[2].CM_GAMCOR_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x1043, dccg_regs[2].CM_GAMCOR_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x1044, dccg_regs[2].CM_GAMCOR_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x1045, dccg_regs[2].CM_GAMCOR_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x1046, dccg_regs[2].CM_GAMCOR_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x1047, dccg_regs[2].CM_GAMCOR_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x1048, dccg_regs[2].CM_GAMCOR_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x104c, dccg_regs[2].CM_GAMCOR_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x105c, dccg_regs[2].CM_GAMCOR_RAMB_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x1049, dccg_regs[2].CM_GAMCOR_RAMB_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x104a, dccg_regs[2].CM_GAMCOR_RAMB_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x104b, dccg_regs[2].CM_GAMCOR_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x1040, dccg_regs[2].CM_GAMCOR_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x1041, dccg_regs[2].CM_GAMCOR_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x1042, dccg_regs[2].CM_GAMCOR_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x1017, dccg_regs[2].CM_GAMCOR_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x1018, dccg_regs[2].CM_GAMCOR_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x1019, dccg_regs[2].CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x101a, dccg_regs[2].CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x101b, dccg_regs[2].CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x101c, dccg_regs[2].CM_GAMCOR_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x1020, dccg_regs[2].CM_GAMCOR_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x1021, dccg_regs[2].CM_GAMCOR_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x1022, dccg_regs[2].CM_GAMCOR_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x1023, dccg_regs[2].CM_GAMCOR_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x1024, dccg_regs[2].CM_GAMCOR_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x1025, dccg_regs[2].CM_GAMCOR_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x1029, dccg_regs[2].CM_GAMCOR_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x1039, dccg_regs[2].CM_GAMCOR_RAMA_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x1026, dccg_regs[2].CM_GAMCOR_RAMA_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x1027, dccg_regs[2].CM_GAMCOR_RAMA_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x1028, dccg_regs[2].CM_GAMCOR_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x101d, dccg_regs[2].CM_GAMCOR_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x101e, dccg_regs[2].CM_GAMCOR_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x101f, dccg_regs[2].CM_GAMUT_REMAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x1004, dccg_regs[2].CM_GAMUT_REMAP_C11_C12 = ctx->dcn_reg_offsets[2] + 0x1005, dccg_regs[2].CM_GAMUT_REMAP_C13_C14 = ctx->dcn_reg_offsets[2] + 0x1006, dccg_regs[2].CM_GAMUT_REMAP_C21_C22 = ctx->dcn_reg_offsets[2] + 0x1007, dccg_regs[2].CM_GAMUT_REMAP_C23_C24 = ctx->dcn_reg_offsets[2] + 0x1008, dccg_regs[2].CM_GAMUT_REMAP_C31_C32 = ctx->dcn_reg_offsets[2] + 0x1009, dccg_regs[2].CM_GAMUT_REMAP_C33_C34 = ctx->dcn_reg_offsets[2] + 0x100a, dccg_regs[2].CM_GAMUT_REMAP_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x100b, dccg_regs[2].CM_GAMUT_REMAP_B_C13_C14 = ctx->dcn_reg_offsets[2] + 0x100c, dccg_regs[2].CM_GAMUT_REMAP_B_C21_C22 = ctx->dcn_reg_offsets[2] + 0x100d, dccg_regs[2].CM_GAMUT_REMAP_B_C23_C24 = ctx->dcn_reg_offsets[2] + 0x100e, dccg_regs[2].CM_GAMUT_REMAP_B_C31_C32 = ctx->dcn_reg_offsets[2] + 0x100f, dccg_regs[2].CM_GAMUT_REMAP_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x1010, dccg_regs[2].DSCL_EXT_OVERSCAN_LEFT_RIGHT = ctx->dcn_reg_offsets[2] + 0x0fe3, dccg_regs[2].DSCL_EXT_OVERSCAN_TOP_BOTTOM = ctx->dcn_reg_offsets[2] + 0x0fe4, dccg_regs[2].OTG_H_BLANK = ctx->dcn_reg_offsets[2] + 0x0fe5, dccg_regs[2].OTG_V_BLANK = ctx->dcn_reg_offsets[2] + 0x0fe6, dccg_regs[2].SCL_MODE = ctx->dcn_reg_offsets[2] + 0x0fd1, dccg_regs[2].LB_DATA_FORMAT = ctx->dcn_reg_offsets[2] + 0x0fea, dccg_regs[2].LB_MEMORY_CTRL = ctx->dcn_reg_offsets[2] + 0x0feb, dccg_regs[2].DSCL_AUTOCAL = ctx->dcn_reg_offsets[2] + 0x0fe2, dccg_regs[2].SCL_TAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0fd2, dccg_regs[2].SCL_COEF_RAM_TAP_SELECT = ctx->dcn_reg_offsets[2] + 0x0fcf, dccg_regs[2].SCL_COEF_RAM_TAP_DATA = ctx->dcn_reg_offsets[2] + 0x0fd0, dccg_regs[2].DSCL_2TAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0fd4, dccg_regs[2].MPC_SIZE = ctx->dcn_reg_offsets[2] + 0x0fe9, dccg_regs[2].SCL_HORZ_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets[2] + 0x0fd6, dccg_regs[2].SCL_VERT_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets[2] + 0x0fda, dccg_regs[2].SCL_HORZ_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets[2] + 0x0fd8, dccg_regs[2].SCL_VERT_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets[2] + 0x0fdd, dccg_regs[2].SCL_HORZ_FILTER_INIT = ctx->dcn_reg_offsets[2] + 0x0fd7, dccg_regs[2].SCL_HORZ_FILTER_INIT_C = ctx->dcn_reg_offsets[2] + 0x0fd9, dccg_regs[2].SCL_VERT_FILTER_INIT = ctx->dcn_reg_offsets[2] + 0x0fdb, dccg_regs[2].SCL_VERT_FILTER_INIT_C = ctx->dcn_reg_offsets[2] + 0x0fde, dccg_regs[2].RECOUT_START = ctx->dcn_reg_offsets[2] + 0x0fe7, dccg_regs[2].RECOUT_SIZE = ctx->dcn_reg_offsets[2] + 0x0fe8, dccg_regs[2].PRE_DEALPHA = ctx->dcn_reg_offsets[2] + 0x0fb4, dccg_regs[2].PRE_REALPHA = ctx->dcn_reg_offsets[2] + 0x0fc4, dccg_regs[2].PRE_CSC_MODE = ctx->dcn_reg_offsets[2] + 0x0fb5, dccg_regs[2].PRE_CSC_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0fb6, dccg_regs[2].PRE_CSC_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0fbb, dccg_regs[2].PRE_CSC_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0fbc, dccg_regs[2].PRE_CSC_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0fc1, dccg_regs[2].CM_POST_CSC_CONTROL = ctx->dcn_reg_offsets[2] + 0x0ff7, dccg_regs[2].CM_POST_CSC_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0ff8, dccg_regs[2].CM_POST_CSC_C33_C34 = ctx->dcn_reg_offsets[2] + 0x0ffd, dccg_regs[2].CM_POST_CSC_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x0ffe, dccg_regs[2].CM_POST_CSC_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x1003, dccg_regs[2].CM_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x105e, dccg_regs[2].CM_CONTROL = ctx->dcn_reg_offsets[2] + 0x0ff6, dccg_regs[2].FORMAT_CONTROL = ctx->dcn_reg_offsets[2] + 0x0fa6, dccg_regs[2].CNVC_SURFACE_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x0fa5, dccg_regs[2].CURSOR0_CONTROL = ctx->dcn_reg_offsets[2] + 0x0fc7, dccg_regs[2].CURSOR0_COLOR0 = ctx->dcn_reg_offsets[2] + 0x0fc8, dccg_regs[2].CURSOR0_COLOR1 = ctx->dcn_reg_offsets[2] + 0x0fc9, dccg_regs[2].CURSOR0_FP_SCALE_BIAS = ctx->dcn_reg_offsets[2] + 0x0fca, dccg_regs[2].DPP_CONTROL = ctx->dcn_reg_offsets[2] + 0x0f9b, dccg_regs[2].CM_HDR_MULT_COEF = ctx->dcn_reg_offsets[2] + 0x105d, dccg_regs[2].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0830, dccg_regs[2].ALPHA_2BIT_LUT = ctx->dcn_reg_offsets[2] + 0x0fb3, dccg_regs[2].FCNV_FP_BIAS_R = ctx->dcn_reg_offsets[2] + 0x0fa7, dccg_regs[2].FCNV_FP_BIAS_G = ctx->dcn_reg_offsets[2] + 0x0fa8, dccg_regs[2].FCNV_FP_BIAS_B = ctx->dcn_reg_offsets[2] + 0x0fa9, dccg_regs[2].FCNV_FP_SCALE_R = ctx->dcn_reg_offsets[2] + 0x0faa, dccg_regs[2].FCNV_FP_SCALE_G = ctx->dcn_reg_offsets[2] + 0x0fab, dccg_regs[2].FCNV_FP_SCALE_B = ctx->dcn_reg_offsets[2] + 0x0fac, dccg_regs[2].COLOR_KEYER_CONTROL = ctx->dcn_reg_offsets[2] + 0x0fad, dccg_regs[2].COLOR_KEYER_ALPHA = ctx->dcn_reg_offsets[2] + 0x0fae, dccg_regs[2].COLOR_KEYER_RED = ctx->dcn_reg_offsets[2] + 0x0faf, dccg_regs[2].COLOR_KEYER_GREEN = ctx->dcn_reg_offsets[2] + 0x0fb0, dccg_regs[2].COLOR_KEYER_BLUE = ctx->dcn_reg_offsets[2] + 0x0fb1, dccg_regs[2].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x0830, dccg_regs[2].OBUF_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x0ff0, dccg_regs[2].DSCL_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x0fee, dccg_regs[2].DSCL_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x0fed ), |
939 | dpp_regs_init(3)( dccg_regs[3].CM_DEALPHA = ctx->dcn_reg_offsets[2] + 0x11cc , dccg_regs[3].CM_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x11ca, dccg_regs[3].CM_BIAS_CR_R = ctx->dcn_reg_offsets [2] + 0x117c, dccg_regs[3].CM_BIAS_Y_G_CB_B = ctx->dcn_reg_offsets [2] + 0x117d, dccg_regs[3].PRE_DEGAM = ctx->dcn_reg_offsets [2] + 0x112e, dccg_regs[3].CM_GAMCOR_CONTROL = ctx->dcn_reg_offsets [2] + 0x117e, dccg_regs[3].CM_GAMCOR_LUT_CONTROL = ctx->dcn_reg_offsets [2] + 0x1181, dccg_regs[3].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets [2] + 0x117f, dccg_regs[3].CM_GAMCOR_LUT_INDEX = ctx->dcn_reg_offsets [2] + 0x117f, dccg_regs[3].CM_GAMCOR_LUT_DATA = ctx->dcn_reg_offsets [2] + 0x1180, dccg_regs[3].CM_GAMCOR_RAMB_START_CNTL_B = ctx-> dcn_reg_offsets[2] + 0x11a5, dccg_regs[3].CM_GAMCOR_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x11a6, dccg_regs[3].CM_GAMCOR_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x11a7, dccg_regs[3].CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x11a8, dccg_regs[3].CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x11a9, dccg_regs[3].CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x11aa, dccg_regs[3].CM_GAMCOR_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x11ae, dccg_regs[3].CM_GAMCOR_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x11af, dccg_regs[3].CM_GAMCOR_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x11b0, dccg_regs[3].CM_GAMCOR_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x11b1, dccg_regs[3].CM_GAMCOR_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x11b2, dccg_regs[3].CM_GAMCOR_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x11b3, dccg_regs[3].CM_GAMCOR_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x11b7, dccg_regs[3].CM_GAMCOR_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x11c7, dccg_regs[3].CM_GAMCOR_RAMB_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x11b4, dccg_regs[3].CM_GAMCOR_RAMB_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x11b5, dccg_regs[3].CM_GAMCOR_RAMB_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x11b6, dccg_regs[3].CM_GAMCOR_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x11ab, dccg_regs[3].CM_GAMCOR_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x11ac, dccg_regs[3].CM_GAMCOR_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x11ad, dccg_regs[3].CM_GAMCOR_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x1182, dccg_regs[3].CM_GAMCOR_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x1183, dccg_regs[3].CM_GAMCOR_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x1184, dccg_regs[3].CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x1185, dccg_regs[3].CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x1186, dccg_regs[3].CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x1187, dccg_regs[3].CM_GAMCOR_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x118b, dccg_regs[3].CM_GAMCOR_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x118c, dccg_regs[3].CM_GAMCOR_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x118d, dccg_regs[3].CM_GAMCOR_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x118e, dccg_regs[3].CM_GAMCOR_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x118f, dccg_regs[3].CM_GAMCOR_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x1190, dccg_regs[3].CM_GAMCOR_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x1194, dccg_regs[3].CM_GAMCOR_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x11a4, dccg_regs[3].CM_GAMCOR_RAMA_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x1191, dccg_regs[3].CM_GAMCOR_RAMA_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x1192, dccg_regs[3].CM_GAMCOR_RAMA_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x1193, dccg_regs[3].CM_GAMCOR_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x1188, dccg_regs[3].CM_GAMCOR_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x1189, dccg_regs[3].CM_GAMCOR_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x118a, dccg_regs[3].CM_GAMUT_REMAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x116f, dccg_regs[3].CM_GAMUT_REMAP_C11_C12 = ctx->dcn_reg_offsets[2] + 0x1170, dccg_regs[3].CM_GAMUT_REMAP_C13_C14 = ctx->dcn_reg_offsets[2] + 0x1171, dccg_regs[3].CM_GAMUT_REMAP_C21_C22 = ctx->dcn_reg_offsets[2] + 0x1172, dccg_regs[3].CM_GAMUT_REMAP_C23_C24 = ctx->dcn_reg_offsets[2] + 0x1173, dccg_regs[3].CM_GAMUT_REMAP_C31_C32 = ctx->dcn_reg_offsets[2] + 0x1174, dccg_regs[3].CM_GAMUT_REMAP_C33_C34 = ctx->dcn_reg_offsets[2] + 0x1175, dccg_regs[3].CM_GAMUT_REMAP_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x1176, dccg_regs[3].CM_GAMUT_REMAP_B_C13_C14 = ctx->dcn_reg_offsets[2] + 0x1177, dccg_regs[3].CM_GAMUT_REMAP_B_C21_C22 = ctx->dcn_reg_offsets[2] + 0x1178, dccg_regs[3].CM_GAMUT_REMAP_B_C23_C24 = ctx->dcn_reg_offsets[2] + 0x1179, dccg_regs[3].CM_GAMUT_REMAP_B_C31_C32 = ctx->dcn_reg_offsets[2] + 0x117a, dccg_regs[3].CM_GAMUT_REMAP_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x117b, dccg_regs[3].DSCL_EXT_OVERSCAN_LEFT_RIGHT = ctx->dcn_reg_offsets[2] + 0x114e, dccg_regs[3].DSCL_EXT_OVERSCAN_TOP_BOTTOM = ctx->dcn_reg_offsets[2] + 0x114f, dccg_regs[3].OTG_H_BLANK = ctx->dcn_reg_offsets[2] + 0x1150, dccg_regs[3].OTG_V_BLANK = ctx->dcn_reg_offsets[2] + 0x1151, dccg_regs[3].SCL_MODE = ctx->dcn_reg_offsets[2] + 0x113c, dccg_regs[3].LB_DATA_FORMAT = ctx->dcn_reg_offsets[2] + 0x1155, dccg_regs[3].LB_MEMORY_CTRL = ctx->dcn_reg_offsets[2] + 0x1156, dccg_regs[3].DSCL_AUTOCAL = ctx->dcn_reg_offsets[2] + 0x114d, dccg_regs[3].SCL_TAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x113d, dccg_regs[3].SCL_COEF_RAM_TAP_SELECT = ctx->dcn_reg_offsets[2] + 0x113a, dccg_regs[3].SCL_COEF_RAM_TAP_DATA = ctx->dcn_reg_offsets[2] + 0x113b, dccg_regs[3].DSCL_2TAP_CONTROL = ctx->dcn_reg_offsets[2] + 0x113f, dccg_regs[3].MPC_SIZE = ctx->dcn_reg_offsets[2] + 0x1154, dccg_regs[3].SCL_HORZ_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets[2] + 0x1141, dccg_regs[3].SCL_VERT_FILTER_SCALE_RATIO = ctx->dcn_reg_offsets[2] + 0x1145, dccg_regs[3].SCL_HORZ_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets[2] + 0x1143, dccg_regs[3].SCL_VERT_FILTER_SCALE_RATIO_C = ctx->dcn_reg_offsets[2] + 0x1148, dccg_regs[3].SCL_HORZ_FILTER_INIT = ctx->dcn_reg_offsets[2] + 0x1142, dccg_regs[3].SCL_HORZ_FILTER_INIT_C = ctx->dcn_reg_offsets[2] + 0x1144, dccg_regs[3].SCL_VERT_FILTER_INIT = ctx->dcn_reg_offsets[2] + 0x1146, dccg_regs[3].SCL_VERT_FILTER_INIT_C = ctx->dcn_reg_offsets[2] + 0x1149, dccg_regs[3].RECOUT_START = ctx->dcn_reg_offsets[2] + 0x1152, dccg_regs[3].RECOUT_SIZE = ctx->dcn_reg_offsets[2] + 0x1153, dccg_regs[3].PRE_DEALPHA = ctx->dcn_reg_offsets[2] + 0x111f, dccg_regs[3].PRE_REALPHA = ctx->dcn_reg_offsets[2] + 0x112f, dccg_regs[3].PRE_CSC_MODE = ctx->dcn_reg_offsets[2] + 0x1120, dccg_regs[3].PRE_CSC_C11_C12 = ctx->dcn_reg_offsets[2] + 0x1121, dccg_regs[3].PRE_CSC_C33_C34 = ctx->dcn_reg_offsets[2] + 0x1126, dccg_regs[3].PRE_CSC_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x1127, dccg_regs[3].PRE_CSC_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x112c, dccg_regs[3].CM_POST_CSC_CONTROL = ctx->dcn_reg_offsets[2] + 0x1162, dccg_regs[3].CM_POST_CSC_C11_C12 = ctx->dcn_reg_offsets[2] + 0x1163, dccg_regs[3].CM_POST_CSC_C33_C34 = ctx->dcn_reg_offsets[2] + 0x1168, dccg_regs[3].CM_POST_CSC_B_C11_C12 = ctx->dcn_reg_offsets[2] + 0x1169, dccg_regs[3].CM_POST_CSC_B_C33_C34 = ctx->dcn_reg_offsets[2] + 0x116e, dccg_regs[3].CM_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x11c9, dccg_regs[3].CM_CONTROL = ctx->dcn_reg_offsets[2] + 0x1161, dccg_regs[3].FORMAT_CONTROL = ctx->dcn_reg_offsets[2] + 0x1111, dccg_regs[3].CNVC_SURFACE_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x1110, dccg_regs[3].CURSOR0_CONTROL = ctx->dcn_reg_offsets[2] + 0x1132, dccg_regs[3].CURSOR0_COLOR0 = ctx->dcn_reg_offsets[2] + 0x1133, dccg_regs[3].CURSOR0_COLOR1 = ctx->dcn_reg_offsets[2] + 0x1134, dccg_regs[3].CURSOR0_FP_SCALE_BIAS = ctx->dcn_reg_offsets[2] + 0x1135, dccg_regs[3].DPP_CONTROL = ctx->dcn_reg_offsets[2] + 0x1106, dccg_regs[3].CM_HDR_MULT_COEF = ctx->dcn_reg_offsets[2] + 0x11c8, dccg_regs[3].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x090c, dccg_regs[3].ALPHA_2BIT_LUT = ctx->dcn_reg_offsets[2] + 0x111e, dccg_regs[3].FCNV_FP_BIAS_R = ctx->dcn_reg_offsets[2] + 0x1112, dccg_regs[3].FCNV_FP_BIAS_G = ctx->dcn_reg_offsets[2] + 0x1113, dccg_regs[3].FCNV_FP_BIAS_B = ctx->dcn_reg_offsets[2] + 0x1114, dccg_regs[3].FCNV_FP_SCALE_R = ctx->dcn_reg_offsets[2] + 0x1115, dccg_regs[3].FCNV_FP_SCALE_G = ctx->dcn_reg_offsets[2] + 0x1116, dccg_regs[3].FCNV_FP_SCALE_B = ctx->dcn_reg_offsets[2] + 0x1117, dccg_regs[3].COLOR_KEYER_CONTROL = ctx->dcn_reg_offsets[2] + 0x1118, dccg_regs[3].COLOR_KEYER_ALPHA = ctx->dcn_reg_offsets[2] + 0x1119, dccg_regs[3].COLOR_KEYER_RED = ctx->dcn_reg_offsets[2] + 0x111a, dccg_regs[3].COLOR_KEYER_GREEN = ctx->dcn_reg_offsets[2] + 0x111b, dccg_regs[3].COLOR_KEYER_BLUE = ctx->dcn_reg_offsets[2] + 0x111c, dccg_regs[3].CURSOR_CONTROL = ctx->dcn_reg_offsets[2] + 0x090c, dccg_regs[3].OBUF_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x115b, dccg_regs[3].DSCL_MEM_PWR_STATUS = ctx->dcn_reg_offsets[2] + 0x1159, dccg_regs[3].DSCL_MEM_PWR_CTRL = ctx->dcn_reg_offsets[2] + 0x1158 ); |
940 | |
941 | if (dpp32_construct(dpp3, ctx, inst, |
942 | &dpp_regs[inst], &tf_shift, &tf_mask)) |
943 | return &dpp3->base; |
944 | |
945 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 945); do {} while (0); } while (0); |
946 | kfree(dpp3); |
947 | return NULL((void *)0); |
948 | } |
949 | |
950 | static struct mpc *dcn32_mpc_create( |
951 | struct dc_context *ctx, |
952 | int num_mpcc, |
953 | int num_rmu) |
954 | { |
955 | struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), |
956 | GFP_KERNEL(0x0001 | 0x0004)); |
957 | |
958 | if (!mpc30) |
959 | return NULL((void *)0); |
960 | |
961 | #undef REG_STRUCTdccg_regs |
962 | #define REG_STRUCTdccg_regs mpc_regs |
963 | dcn_mpc_regs_init()( ( dccg_regs.MPCC_TOP_SEL[0] = ctx->dcn_reg_offsets[3] + 0x0000 , dccg_regs.MPCC_BOT_SEL[0] = ctx->dcn_reg_offsets[3] + 0x0001 , dccg_regs.MPCC_CONTROL[0] = ctx->dcn_reg_offsets[3] + 0x0003 , dccg_regs.MPCC_STATUS[0] = ctx->dcn_reg_offsets[3] + 0x000e , dccg_regs.MPCC_OPP_ID[0] = ctx->dcn_reg_offsets[3] + 0x0002 , dccg_regs.MPCC_BG_G_Y[0] = ctx->dcn_reg_offsets[3] + 0x000b , dccg_regs.MPCC_BG_R_CR[0] = ctx->dcn_reg_offsets[3] + 0x000a , dccg_regs.MPCC_BG_B_CB[0] = ctx->dcn_reg_offsets[3] + 0x000c , dccg_regs.MPCC_SM_CONTROL[0] = ctx->dcn_reg_offsets[3] + 0x0004, dccg_regs.MPCC_UPDATE_LOCK_SEL[0] = ctx->dcn_reg_offsets [3] + 0x0005 ), dccg_regs.MPCC_TOP_GAIN[0] = ctx->dcn_reg_offsets [3] + 0x0006, dccg_regs.MPCC_BOT_GAIN_INSIDE[0] = ctx->dcn_reg_offsets [3] + 0x0007, dccg_regs.MPCC_BOT_GAIN_OUTSIDE[0] = ctx->dcn_reg_offsets [3] + 0x0008, dccg_regs.MPCC_MEM_PWR_CTRL[0] = ctx->dcn_reg_offsets [3] + 0x000d, dccg_regs.MPCC_OGAM_LUT_INDEX[0] = ctx->dcn_reg_offsets [3] + 0x00a9, dccg_regs.MPCC_OGAM_LUT_DATA[0] = ctx->dcn_reg_offsets [3] + 0x00aa, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT[0] = ctx ->dcn_reg_offsets[3] + 0x00f2, dccg_regs.MPCC_GAMUT_REMAP_MODE [0] = ctx->dcn_reg_offsets[3] + 0x00f3, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [0] = ctx->dcn_reg_offsets[3] + 0x00f4, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [0] = ctx->dcn_reg_offsets[3] + 0x00f9, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [0] = ctx->dcn_reg_offsets[3] + 0x00fa, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [0] = ctx->dcn_reg_offsets[3] + 0x00ff, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00ac, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00ad, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00ae, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00af, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00b0, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00b1, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x00b5, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x00b6, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x00b7, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x00b8, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x00b9, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x00ba, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x00be, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x00ce, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x00bb, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x00bc, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x00bd, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00b2, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00b3, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00b4, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00cf, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d0, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d1, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00d2, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d3, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d4, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x00d8, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x00d9, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x00da, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x00db, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x00dc, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x00dd, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x00e1, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x00f1, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x00de, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x00df, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x00e0, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x00d5, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x00d6, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x00d7, dccg_regs.MPCC_OGAM_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x00a8, dccg_regs.MPCC_OGAM_LUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x00ab ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0009, dccg_regs.MPCC_MCM_SHAPER_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0453, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x0454, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x0455, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x0456, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [0] = ctx->dcn_reg_offsets[3] + 0x0457, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [0] = ctx->dcn_reg_offsets[3] + 0x0458, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x0459, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x045a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [0] = ctx->dcn_reg_offsets[3] + 0x045b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x045c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x045d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x045e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x045f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0460, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0461, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x0462, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x0463, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x0464, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x0465, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x0466, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x0467, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x0468, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x0469, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x046a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x046b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x046c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x046d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x046e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x046f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x0470, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x0471, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x0472, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0473, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0474, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0475, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0476, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0477, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0478, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x0479, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x047a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x047b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x047c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x047d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x047e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x047f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x0480, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x0481, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x0482, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x0483, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x0484, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x0485, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x0486, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x0487, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x0488, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x0489, dccg_regs.MPCC_MCM_3DLUT_MODE [0] = ctx->dcn_reg_offsets[3] + 0x048a, dccg_regs.MPCC_MCM_3DLUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x048b, dccg_regs.MPCC_MCM_3DLUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x048c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [0] = ctx->dcn_reg_offsets[3] + 0x048d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x048e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [0] = ctx->dcn_reg_offsets[3] + 0x048f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x0490, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x0491, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x0492, dccg_regs.MPCC_MCM_1DLUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0493, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [0] = ctx->dcn_reg_offsets[3] + 0x0494, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [0] = ctx->dcn_reg_offsets[3] + 0x0495, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x0496, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x0497, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x0498, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x0499, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x049a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x049b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x049c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x049d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x049e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x049f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x04a0, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x04a1, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x04a2, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x04a3, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x04a4, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x04a5, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x04a6, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x04a7, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x04a8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x04a9, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x04aa, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x04ab, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x04ac, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x04ad, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x04ae, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x04af, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x04b0, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x04b1, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x04b2, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x04b3, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x04b4, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x04b5, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x04b6, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x04b7, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x04b8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x04b9, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04ba, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04bb, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04bc, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04bd, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04be, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04bf, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [0] = ctx->dcn_reg_offsets[3] + 0x04c0, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [0] = ctx->dcn_reg_offsets[3] + 0x04c1, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [0] = ctx->dcn_reg_offsets[3] + 0x04c2, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [0] = ctx->dcn_reg_offsets[3] + 0x04c3, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [0] = ctx->dcn_reg_offsets[3] + 0x04c4, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [0] = ctx->dcn_reg_offsets[3] + 0x04c5, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [0] = ctx->dcn_reg_offsets[3] + 0x04c6, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [0] = ctx->dcn_reg_offsets[3] + 0x04c7, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [0] = ctx->dcn_reg_offsets[3] + 0x04c8, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [0] = ctx->dcn_reg_offsets[3] + 0x04c9, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [0] = ctx->dcn_reg_offsets[3] + 0x04ca, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [0] = ctx->dcn_reg_offsets[3] + 0x04cb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [0] = ctx->dcn_reg_offsets[3] + 0x04cc, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [0] = ctx->dcn_reg_offsets[3] + 0x04cd, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [0] = ctx->dcn_reg_offsets[3] + 0x04ce, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [0] = ctx->dcn_reg_offsets[3] + 0x04cf, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [0] = ctx->dcn_reg_offsets[3] + 0x04d0, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [0] = ctx->dcn_reg_offsets[3] + 0x04d1, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [0] = ctx->dcn_reg_offsets[3] + 0x04d2, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [0] = ctx->dcn_reg_offsets[3] + 0x04d3, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [0] = ctx->dcn_reg_offsets[3] + 0x04d4, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [0] = ctx->dcn_reg_offsets[3] + 0x04d5, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [0] = ctx->dcn_reg_offsets[3] + 0x04d6, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [0] = ctx->dcn_reg_offsets[3] + 0x04d7, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [0] = ctx->dcn_reg_offsets[3] + 0x04d8, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [0] = ctx->dcn_reg_offsets[3] + 0x04d9, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [0] = ctx->dcn_reg_offsets[3] + 0x04da, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [0] = ctx->dcn_reg_offsets[3] + 0x04db, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [0] = ctx->dcn_reg_offsets[3] + 0x04dc, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [0] = ctx->dcn_reg_offsets[3] + 0x04dd, ( ( dccg_regs.MPCC_TOP_SEL [1] = ctx->dcn_reg_offsets[3] + 0x0015, dccg_regs.MPCC_BOT_SEL [1] = ctx->dcn_reg_offsets[3] + 0x0016, dccg_regs.MPCC_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0018, dccg_regs.MPCC_STATUS [1] = ctx->dcn_reg_offsets[3] + 0x0023, dccg_regs.MPCC_OPP_ID [1] = ctx->dcn_reg_offsets[3] + 0x0017, dccg_regs.MPCC_BG_G_Y [1] = ctx->dcn_reg_offsets[3] + 0x0020, dccg_regs.MPCC_BG_R_CR [1] = ctx->dcn_reg_offsets[3] + 0x001f, dccg_regs.MPCC_BG_B_CB [1] = ctx->dcn_reg_offsets[3] + 0x0021, dccg_regs.MPCC_SM_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0019, dccg_regs.MPCC_UPDATE_LOCK_SEL [1] = ctx->dcn_reg_offsets[3] + 0x001a ), dccg_regs.MPCC_TOP_GAIN [1] = ctx->dcn_reg_offsets[3] + 0x001b, dccg_regs.MPCC_BOT_GAIN_INSIDE [1] = ctx->dcn_reg_offsets[3] + 0x001c, dccg_regs.MPCC_BOT_GAIN_OUTSIDE [1] = ctx->dcn_reg_offsets[3] + 0x001d, dccg_regs.MPCC_MEM_PWR_CTRL [1] = ctx->dcn_reg_offsets[3] + 0x0022, dccg_regs.MPCC_OGAM_LUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x0107, dccg_regs.MPCC_OGAM_LUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x0108, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT [1] = ctx->dcn_reg_offsets[3] + 0x0150, dccg_regs.MPCC_GAMUT_REMAP_MODE [1] = ctx->dcn_reg_offsets[3] + 0x0151, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [1] = ctx->dcn_reg_offsets[3] + 0x0152, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [1] = ctx->dcn_reg_offsets[3] + 0x0157, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [1] = ctx->dcn_reg_offsets[3] + 0x0158, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [1] = ctx->dcn_reg_offsets[3] + 0x015d, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x010a, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x010b, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x010c, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x010d, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x010e, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x010f, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0113, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0114, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0115, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0116, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0117, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0118, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x011c, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x012c, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0119, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x011a, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x011b, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0110, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0111, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0112, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x012d, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x012e, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x012f, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0130, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0131, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0132, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0136, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0137, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0138, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0139, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x013a, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x013b, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x013f, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x014f, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x013c, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x013d, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x013e, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0133, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0134, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0135, dccg_regs.MPCC_OGAM_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0106, dccg_regs.MPCC_OGAM_LUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0109 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x001e, dccg_regs.MPCC_MCM_SHAPER_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x04e3, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x04e4, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x04e5, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x04e6, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [1] = ctx->dcn_reg_offsets[3] + 0x04e7, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [1] = ctx->dcn_reg_offsets[3] + 0x04e8, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x04e9, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x04ea, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [1] = ctx->dcn_reg_offsets[3] + 0x04eb, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x04ec, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x04ed, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x04ee, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x04ef, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x04f0, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x04f1, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x04f2, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x04f3, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x04f4, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x04f5, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x04f6, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x04f7, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x04f8, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x04f9, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x04fa, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x04fb, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x04fc, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x04fd, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x04fe, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x04ff, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0500, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0501, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0502, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0503, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0504, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0505, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0506, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0507, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0508, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x0509, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x050a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x050b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x050c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x050d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x050e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x050f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0510, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0511, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0512, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0513, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0514, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0515, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0516, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0517, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0518, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0519, dccg_regs.MPCC_MCM_3DLUT_MODE [1] = ctx->dcn_reg_offsets[3] + 0x051a, dccg_regs.MPCC_MCM_3DLUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x051b, dccg_regs.MPCC_MCM_3DLUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x051c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [1] = ctx->dcn_reg_offsets[3] + 0x051d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x051e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [1] = ctx->dcn_reg_offsets[3] + 0x051f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x0520, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x0521, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0522, dccg_regs.MPCC_MCM_1DLUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0523, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [1] = ctx->dcn_reg_offsets[3] + 0x0524, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [1] = ctx->dcn_reg_offsets[3] + 0x0525, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x0526, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0527, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0528, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0529, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x052a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x052b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x052c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x052d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x052e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x052f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0530, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0531, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0532, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0533, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0534, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0535, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0536, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x0537, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x0538, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x0539, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x053a, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x053b, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x053c, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x053d, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x053e, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x053f, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0540, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0541, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0542, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0543, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0544, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0545, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0546, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x0547, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x0548, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x0549, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x054a, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x054b, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x054c, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x054d, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x054e, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x054f, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [1] = ctx->dcn_reg_offsets[3] + 0x0550, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [1] = ctx->dcn_reg_offsets[3] + 0x0551, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [1] = ctx->dcn_reg_offsets[3] + 0x0552, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [1] = ctx->dcn_reg_offsets[3] + 0x0553, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [1] = ctx->dcn_reg_offsets[3] + 0x0554, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [1] = ctx->dcn_reg_offsets[3] + 0x0555, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [1] = ctx->dcn_reg_offsets[3] + 0x0556, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [1] = ctx->dcn_reg_offsets[3] + 0x0557, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [1] = ctx->dcn_reg_offsets[3] + 0x0558, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [1] = ctx->dcn_reg_offsets[3] + 0x0559, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [1] = ctx->dcn_reg_offsets[3] + 0x055a, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [1] = ctx->dcn_reg_offsets[3] + 0x055b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [1] = ctx->dcn_reg_offsets[3] + 0x055c, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [1] = ctx->dcn_reg_offsets[3] + 0x055d, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [1] = ctx->dcn_reg_offsets[3] + 0x055e, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [1] = ctx->dcn_reg_offsets[3] + 0x055f, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [1] = ctx->dcn_reg_offsets[3] + 0x0560, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [1] = ctx->dcn_reg_offsets[3] + 0x0561, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [1] = ctx->dcn_reg_offsets[3] + 0x0562, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [1] = ctx->dcn_reg_offsets[3] + 0x0563, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [1] = ctx->dcn_reg_offsets[3] + 0x0564, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [1] = ctx->dcn_reg_offsets[3] + 0x0565, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [1] = ctx->dcn_reg_offsets[3] + 0x0566, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [1] = ctx->dcn_reg_offsets[3] + 0x0567, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [1] = ctx->dcn_reg_offsets[3] + 0x0568, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [1] = ctx->dcn_reg_offsets[3] + 0x0569, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [1] = ctx->dcn_reg_offsets[3] + 0x056a, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [1] = ctx->dcn_reg_offsets[3] + 0x056b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [1] = ctx->dcn_reg_offsets[3] + 0x056c, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [1] = ctx->dcn_reg_offsets[3] + 0x056d, ( ( dccg_regs.MPCC_TOP_SEL [2] = ctx->dcn_reg_offsets[3] + 0x002a, dccg_regs.MPCC_BOT_SEL [2] = ctx->dcn_reg_offsets[3] + 0x002b, dccg_regs.MPCC_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x002d, dccg_regs.MPCC_STATUS [2] = ctx->dcn_reg_offsets[3] + 0x0038, dccg_regs.MPCC_OPP_ID [2] = ctx->dcn_reg_offsets[3] + 0x002c, dccg_regs.MPCC_BG_G_Y [2] = ctx->dcn_reg_offsets[3] + 0x0035, dccg_regs.MPCC_BG_R_CR [2] = ctx->dcn_reg_offsets[3] + 0x0034, dccg_regs.MPCC_BG_B_CB [2] = ctx->dcn_reg_offsets[3] + 0x0036, dccg_regs.MPCC_SM_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x002e, dccg_regs.MPCC_UPDATE_LOCK_SEL [2] = ctx->dcn_reg_offsets[3] + 0x002f ), dccg_regs.MPCC_TOP_GAIN [2] = ctx->dcn_reg_offsets[3] + 0x0030, dccg_regs.MPCC_BOT_GAIN_INSIDE [2] = ctx->dcn_reg_offsets[3] + 0x0031, dccg_regs.MPCC_BOT_GAIN_OUTSIDE [2] = ctx->dcn_reg_offsets[3] + 0x0032, dccg_regs.MPCC_MEM_PWR_CTRL [2] = ctx->dcn_reg_offsets[3] + 0x0037, dccg_regs.MPCC_OGAM_LUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x0165, dccg_regs.MPCC_OGAM_LUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x0166, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT [2] = ctx->dcn_reg_offsets[3] + 0x01ae, dccg_regs.MPCC_GAMUT_REMAP_MODE [2] = ctx->dcn_reg_offsets[3] + 0x01af, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [2] = ctx->dcn_reg_offsets[3] + 0x01b0, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [2] = ctx->dcn_reg_offsets[3] + 0x01b5, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [2] = ctx->dcn_reg_offsets[3] + 0x01b6, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [2] = ctx->dcn_reg_offsets[3] + 0x01bb, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0168, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0169, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x016a, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x016b, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x016c, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x016d, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x0171, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x0172, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x0173, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x0174, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x0175, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x0176, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x017a, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x018a, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x0177, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x0178, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x0179, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x016e, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x016f, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0170, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x018b, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x018c, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x018d, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x018e, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x018f, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0190, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x0194, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x0195, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x0196, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x0197, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x0198, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x0199, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x019d, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x01ad, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x019a, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x019b, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x019c, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0191, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0192, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0193, dccg_regs.MPCC_OGAM_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0164, dccg_regs.MPCC_OGAM_LUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0167 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0033, dccg_regs.MPCC_MCM_SHAPER_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x0573, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x0574, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x0575, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x0576, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [2] = ctx->dcn_reg_offsets[3] + 0x0577, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [2] = ctx->dcn_reg_offsets[3] + 0x0578, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x0579, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x057a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [2] = ctx->dcn_reg_offsets[3] + 0x057b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x057c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x057d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x057e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x057f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0580, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0581, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x0582, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x0583, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x0584, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x0585, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x0586, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x0587, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x0588, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x0589, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x058a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x058b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x058c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x058d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x058e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x058f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x0590, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x0591, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x0592, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0593, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0594, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0595, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x0596, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x0597, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x0598, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x0599, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x059a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x059b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x059c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x059d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x059e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x059f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05a0, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05a1, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05a2, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05a3, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05a4, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05a5, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05a6, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05a7, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05a8, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05a9, dccg_regs.MPCC_MCM_3DLUT_MODE [2] = ctx->dcn_reg_offsets[3] + 0x05aa, dccg_regs.MPCC_MCM_3DLUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x05ab, dccg_regs.MPCC_MCM_3DLUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x05ac, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [2] = ctx->dcn_reg_offsets[3] + 0x05ad, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05ae, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [2] = ctx->dcn_reg_offsets[3] + 0x05af, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05b0, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05b1, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05b2, dccg_regs.MPCC_MCM_1DLUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05b3, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [2] = ctx->dcn_reg_offsets[3] + 0x05b4, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [2] = ctx->dcn_reg_offsets[3] + 0x05b5, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x05b6, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05b7, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05b8, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05b9, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05ba, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05bb, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05bc, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05bd, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05be, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05bf, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x05c0, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x05c1, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x05c2, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x05c3, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x05c4, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x05c5, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05c6, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05c7, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05c8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x05c9, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x05ca, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x05cb, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x05cc, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x05cd, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x05ce, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x05cf, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05d0, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05d1, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05d2, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05d3, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05d4, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05d5, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05d6, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05d7, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05d8, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05d9, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05da, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05db, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05dc, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05dd, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05de, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05df, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [2] = ctx->dcn_reg_offsets[3] + 0x05e0, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [2] = ctx->dcn_reg_offsets[3] + 0x05e1, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [2] = ctx->dcn_reg_offsets[3] + 0x05e2, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [2] = ctx->dcn_reg_offsets[3] + 0x05e3, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [2] = ctx->dcn_reg_offsets[3] + 0x05e4, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [2] = ctx->dcn_reg_offsets[3] + 0x05e5, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [2] = ctx->dcn_reg_offsets[3] + 0x05e6, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [2] = ctx->dcn_reg_offsets[3] + 0x05e7, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [2] = ctx->dcn_reg_offsets[3] + 0x05e8, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [2] = ctx->dcn_reg_offsets[3] + 0x05e9, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [2] = ctx->dcn_reg_offsets[3] + 0x05ea, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [2] = ctx->dcn_reg_offsets[3] + 0x05eb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [2] = ctx->dcn_reg_offsets[3] + 0x05ec, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [2] = ctx->dcn_reg_offsets[3] + 0x05ed, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [2] = ctx->dcn_reg_offsets[3] + 0x05ee, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [2] = ctx->dcn_reg_offsets[3] + 0x05ef, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [2] = ctx->dcn_reg_offsets[3] + 0x05f0, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [2] = ctx->dcn_reg_offsets[3] + 0x05f1, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [2] = ctx->dcn_reg_offsets[3] + 0x05f2, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [2] = ctx->dcn_reg_offsets[3] + 0x05f3, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [2] = ctx->dcn_reg_offsets[3] + 0x05f4, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [2] = ctx->dcn_reg_offsets[3] + 0x05f5, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [2] = ctx->dcn_reg_offsets[3] + 0x05f6, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [2] = ctx->dcn_reg_offsets[3] + 0x05f7, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [2] = ctx->dcn_reg_offsets[3] + 0x05f8, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [2] = ctx->dcn_reg_offsets[3] + 0x05f9, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [2] = ctx->dcn_reg_offsets[3] + 0x05fa, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [2] = ctx->dcn_reg_offsets[3] + 0x05fb, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [2] = ctx->dcn_reg_offsets[3] + 0x05fc, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [2] = ctx->dcn_reg_offsets[3] + 0x05fd, ( ( dccg_regs.MPCC_TOP_SEL [3] = ctx->dcn_reg_offsets[3] + 0x003f, dccg_regs.MPCC_BOT_SEL [3] = ctx->dcn_reg_offsets[3] + 0x0040, dccg_regs.MPCC_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0042, dccg_regs.MPCC_STATUS [3] = ctx->dcn_reg_offsets[3] + 0x004d, dccg_regs.MPCC_OPP_ID [3] = ctx->dcn_reg_offsets[3] + 0x0041, dccg_regs.MPCC_BG_G_Y [3] = ctx->dcn_reg_offsets[3] + 0x004a, dccg_regs.MPCC_BG_R_CR [3] = ctx->dcn_reg_offsets[3] + 0x0049, dccg_regs.MPCC_BG_B_CB [3] = ctx->dcn_reg_offsets[3] + 0x004b, dccg_regs.MPCC_SM_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0043, dccg_regs.MPCC_UPDATE_LOCK_SEL [3] = ctx->dcn_reg_offsets[3] + 0x0044 ), dccg_regs.MPCC_TOP_GAIN [3] = ctx->dcn_reg_offsets[3] + 0x0045, dccg_regs.MPCC_BOT_GAIN_INSIDE [3] = ctx->dcn_reg_offsets[3] + 0x0046, dccg_regs.MPCC_BOT_GAIN_OUTSIDE [3] = ctx->dcn_reg_offsets[3] + 0x0047, dccg_regs.MPCC_MEM_PWR_CTRL [3] = ctx->dcn_reg_offsets[3] + 0x004c, dccg_regs.MPCC_OGAM_LUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x01c3, dccg_regs.MPCC_OGAM_LUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x01c4, dccg_regs.MPCC_GAMUT_REMAP_COEF_FORMAT [3] = ctx->dcn_reg_offsets[3] + 0x020c, dccg_regs.MPCC_GAMUT_REMAP_MODE [3] = ctx->dcn_reg_offsets[3] + 0x020d, dccg_regs.MPC_GAMUT_REMAP_C11_C12_A [3] = ctx->dcn_reg_offsets[3] + 0x020e, dccg_regs.MPC_GAMUT_REMAP_C33_C34_A [3] = ctx->dcn_reg_offsets[3] + 0x0213, dccg_regs.MPC_GAMUT_REMAP_C11_C12_B [3] = ctx->dcn_reg_offsets[3] + 0x0214, dccg_regs.MPC_GAMUT_REMAP_C33_C34_B [3] = ctx->dcn_reg_offsets[3] + 0x0219, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01c6, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01c7, dccg_regs.MPCC_OGAM_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01c8, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01c9, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ca, dccg_regs.MPCC_OGAM_RAMA_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01cb, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x01cf, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x01d0, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x01d1, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x01d2, dccg_regs.MPCC_OGAM_RAMA_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x01d3, dccg_regs.MPCC_OGAM_RAMA_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x01d4, dccg_regs.MPCC_OGAM_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x01d8, dccg_regs.MPCC_OGAM_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x01e8, dccg_regs.MPCC_OGAM_RAMA_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x01d5, dccg_regs.MPCC_OGAM_RAMA_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x01d6, dccg_regs.MPCC_OGAM_RAMA_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x01d7, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01cc, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01cd, dccg_regs.MPCC_OGAM_RAMA_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01ce, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01e9, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ea, dccg_regs.MPCC_OGAM_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01eb, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01ec, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01ed, dccg_regs.MPCC_OGAM_RAMB_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01ee, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x01f2, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x01f3, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x01f4, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x01f5, dccg_regs.MPCC_OGAM_RAMB_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x01f6, dccg_regs.MPCC_OGAM_RAMB_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x01f7, dccg_regs.MPCC_OGAM_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x01fb, dccg_regs.MPCC_OGAM_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x020b, dccg_regs.MPCC_OGAM_RAMB_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x01f8, dccg_regs.MPCC_OGAM_RAMB_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x01f9, dccg_regs.MPCC_OGAM_RAMB_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x01fa, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x01ef, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x01f0, dccg_regs.MPCC_OGAM_RAMB_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x01f1, dccg_regs.MPCC_OGAM_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x01c2, dccg_regs.MPCC_OGAM_LUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x01c5 ), dccg_regs.MPCC_MOVABLE_CM_LOCATION_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0048, dccg_regs.MPCC_MCM_SHAPER_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0603, dccg_regs.MPCC_MCM_SHAPER_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0604, dccg_regs.MPCC_MCM_SHAPER_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0605, dccg_regs.MPCC_MCM_SHAPER_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0606, dccg_regs.MPCC_MCM_SHAPER_SCALE_R [3] = ctx->dcn_reg_offsets[3] + 0x0607, dccg_regs.MPCC_MCM_SHAPER_SCALE_G_B [3] = ctx->dcn_reg_offsets[3] + 0x0608, dccg_regs.MPCC_MCM_SHAPER_LUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x0609, dccg_regs.MPCC_MCM_SHAPER_LUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x060a, dccg_regs.MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK [3] = ctx->dcn_reg_offsets[3] + 0x060b, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x060c, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x060d, dccg_regs.MPCC_MCM_SHAPER_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x060e, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x060f, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0610, dccg_regs.MPCC_MCM_SHAPER_RAMA_END_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0611, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0612, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x0613, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x0614, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x0615, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x0616, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x0617, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x0618, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0619, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x061a, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x061b, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x061c, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x061d, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x061e, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x061f, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0620, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0621, dccg_regs.MPCC_MCM_SHAPER_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0622, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0623, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0624, dccg_regs.MPCC_MCM_SHAPER_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0625, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0626, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0627, dccg_regs.MPCC_MCM_SHAPER_RAMB_END_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0628, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0629, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x062a, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x062b, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x062c, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x062d, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x062e, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x062f, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0630, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0631, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0632, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0633, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0634, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0635, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0636, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0637, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0638, dccg_regs.MPCC_MCM_SHAPER_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0639, dccg_regs.MPCC_MCM_3DLUT_MODE [3] = ctx->dcn_reg_offsets[3] + 0x063a, dccg_regs.MPCC_MCM_3DLUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x063b, dccg_regs.MPCC_MCM_3DLUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x063c, dccg_regs.MPCC_MCM_3DLUT_DATA_30BIT [3] = ctx->dcn_reg_offsets[3] + 0x063d, dccg_regs.MPCC_MCM_3DLUT_READ_WRITE_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x063e, dccg_regs.MPCC_MCM_3DLUT_OUT_NORM_FACTOR [3] = ctx->dcn_reg_offsets[3] + 0x063f, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0640, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0641, dccg_regs.MPCC_MCM_3DLUT_OUT_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0642, dccg_regs.MPCC_MCM_1DLUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0643, dccg_regs.MPCC_MCM_1DLUT_LUT_INDEX [3] = ctx->dcn_reg_offsets[3] + 0x0644, dccg_regs.MPCC_MCM_1DLUT_LUT_DATA [3] = ctx->dcn_reg_offsets[3] + 0x0645, dccg_regs.MPCC_MCM_1DLUT_LUT_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x0646, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0647, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0648, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0649, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x064a, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x064b, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x064c, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x064d, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x064e, dccg_regs.MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x064f, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x0650, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x0651, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x0652, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x0653, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x0654, dccg_regs.MPCC_MCM_1DLUT_RAMA_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x0655, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0656, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x0657, dccg_regs.MPCC_MCM_1DLUT_RAMA_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x0658, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x0659, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x065a, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x065b, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x065c, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x065d, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x065e, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x065f, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0660, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0661, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0662, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0663, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0664, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0665, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0666, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x0667, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x0668, dccg_regs.MPCC_MCM_1DLUT_RAMA_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x0669, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x066a, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x066b, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x066c, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x066d, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x066e, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x066f, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B [3] = ctx->dcn_reg_offsets[3] + 0x0670, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G [3] = ctx->dcn_reg_offsets[3] + 0x0671, dccg_regs.MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R [3] = ctx->dcn_reg_offsets[3] + 0x0672, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_B [3] = ctx->dcn_reg_offsets[3] + 0x0673, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_B [3] = ctx->dcn_reg_offsets[3] + 0x0674, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_G [3] = ctx->dcn_reg_offsets[3] + 0x0675, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_G [3] = ctx->dcn_reg_offsets[3] + 0x0676, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL1_R [3] = ctx->dcn_reg_offsets[3] + 0x0677, dccg_regs.MPCC_MCM_1DLUT_RAMB_END_CNTL2_R [3] = ctx->dcn_reg_offsets[3] + 0x0678, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_B [3] = ctx->dcn_reg_offsets[3] + 0x0679, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_G [3] = ctx->dcn_reg_offsets[3] + 0x067a, dccg_regs.MPCC_MCM_1DLUT_RAMB_OFFSET_R [3] = ctx->dcn_reg_offsets[3] + 0x067b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_0_1 [3] = ctx->dcn_reg_offsets[3] + 0x067c, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_2_3 [3] = ctx->dcn_reg_offsets[3] + 0x067d, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_4_5 [3] = ctx->dcn_reg_offsets[3] + 0x067e, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_6_7 [3] = ctx->dcn_reg_offsets[3] + 0x067f, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_8_9 [3] = ctx->dcn_reg_offsets[3] + 0x0680, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_10_11 [3] = ctx->dcn_reg_offsets[3] + 0x0681, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_12_13 [3] = ctx->dcn_reg_offsets[3] + 0x0682, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_14_15 [3] = ctx->dcn_reg_offsets[3] + 0x0683, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_16_17 [3] = ctx->dcn_reg_offsets[3] + 0x0684, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_18_19 [3] = ctx->dcn_reg_offsets[3] + 0x0685, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_20_21 [3] = ctx->dcn_reg_offsets[3] + 0x0686, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_22_23 [3] = ctx->dcn_reg_offsets[3] + 0x0687, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_24_25 [3] = ctx->dcn_reg_offsets[3] + 0x0688, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_26_27 [3] = ctx->dcn_reg_offsets[3] + 0x0689, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_28_29 [3] = ctx->dcn_reg_offsets[3] + 0x068a, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_30_31 [3] = ctx->dcn_reg_offsets[3] + 0x068b, dccg_regs.MPCC_MCM_1DLUT_RAMB_REGION_32_33 [3] = ctx->dcn_reg_offsets[3] + 0x068c, dccg_regs.MPCC_MCM_MEM_PWR_CTRL [3] = ctx->dcn_reg_offsets[3] + 0x068d, ( ( dccg_regs.MUX[ 0] = ctx->dcn_reg_offsets[3] + 0x03d8, dccg_regs.CUR[0] = ctx ->dcn_reg_offsets[3] + 0x03ab ), dccg_regs.CSC_MODE[0] = ctx ->dcn_reg_offsets[3] + 0x03f1, dccg_regs.CSC_C11_C12_A[0] = ctx->dcn_reg_offsets[3] + 0x03f2, dccg_regs.CSC_C33_C34_A [0] = ctx->dcn_reg_offsets[3] + 0x03f7, dccg_regs.CSC_C11_C12_B [0] = ctx->dcn_reg_offsets[3] + 0x03f8, dccg_regs.CSC_C33_C34_B [0] = ctx->dcn_reg_offsets[3] + 0x03fd, dccg_regs.DENORM_CONTROL [0] = ctx->dcn_reg_offsets[3] + 0x03d9, dccg_regs.DENORM_CLAMP_G_Y [0] = ctx->dcn_reg_offsets[3] + 0x03da, dccg_regs.DENORM_CLAMP_B_CB [0] = ctx->dcn_reg_offsets[3] + 0x03db, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ), ( ( dccg_regs.MUX[1 ] = ctx->dcn_reg_offsets[3] + 0x03dc, dccg_regs.CUR[1] = ctx ->dcn_reg_offsets[3] + 0x03b0 ), dccg_regs.CSC_MODE[1] = ctx ->dcn_reg_offsets[3] + 0x03fe, dccg_regs.CSC_C11_C12_A[1] = ctx->dcn_reg_offsets[3] + 0x03ff, dccg_regs.CSC_C33_C34_A [1] = ctx->dcn_reg_offsets[3] + 0x0404, dccg_regs.CSC_C11_C12_B [1] = ctx->dcn_reg_offsets[3] + 0x0405, dccg_regs.CSC_C33_C34_B [1] = ctx->dcn_reg_offsets[3] + 0x040a, dccg_regs.DENORM_CONTROL [1] = ctx->dcn_reg_offsets[3] + 0x03dd, dccg_regs.DENORM_CLAMP_G_Y [1] = ctx->dcn_reg_offsets[3] + 0x03de, dccg_regs.DENORM_CLAMP_B_CB [1] = ctx->dcn_reg_offsets[3] + 0x03df, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ), ( ( dccg_regs.MUX[2 ] = ctx->dcn_reg_offsets[3] + 0x03e0, dccg_regs.CUR[2] = ctx ->dcn_reg_offsets[3] + 0x03b5 ), dccg_regs.CSC_MODE[2] = ctx ->dcn_reg_offsets[3] + 0x040b, dccg_regs.CSC_C11_C12_A[2] = ctx->dcn_reg_offsets[3] + 0x040c, dccg_regs.CSC_C33_C34_A [2] = ctx->dcn_reg_offsets[3] + 0x0411, dccg_regs.CSC_C11_C12_B [2] = ctx->dcn_reg_offsets[3] + 0x0412, dccg_regs.CSC_C33_C34_B [2] = ctx->dcn_reg_offsets[3] + 0x0417, dccg_regs.DENORM_CONTROL [2] = ctx->dcn_reg_offsets[3] + 0x03e1, dccg_regs.DENORM_CLAMP_G_Y [2] = ctx->dcn_reg_offsets[3] + 0x03e2, dccg_regs.DENORM_CLAMP_B_CB [2] = ctx->dcn_reg_offsets[3] + 0x03e3, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ), ( ( dccg_regs.MUX[3 ] = ctx->dcn_reg_offsets[3] + 0x03e4, dccg_regs.CUR[3] = ctx ->dcn_reg_offsets[3] + 0x03ba ), dccg_regs.CSC_MODE[3] = ctx ->dcn_reg_offsets[3] + 0x0418, dccg_regs.CSC_C11_C12_A[3] = ctx->dcn_reg_offsets[3] + 0x0419, dccg_regs.CSC_C33_C34_A [3] = ctx->dcn_reg_offsets[3] + 0x041e, dccg_regs.CSC_C11_C12_B [3] = ctx->dcn_reg_offsets[3] + 0x041f, dccg_regs.CSC_C33_C34_B [3] = ctx->dcn_reg_offsets[3] + 0x0424, dccg_regs.DENORM_CONTROL [3] = ctx->dcn_reg_offsets[3] + 0x03e5, dccg_regs.DENORM_CLAMP_G_Y [3] = ctx->dcn_reg_offsets[3] + 0x03e6, dccg_regs.DENORM_CLAMP_B_CB [3] = ctx->dcn_reg_offsets[3] + 0x03e7, dccg_regs.MPC_OUT_CSC_COEF_FORMAT = ctx->dcn_reg_offsets[3] + 0x03f0 ), dccg_regs.DWB_MUX[0 ] = ctx->dcn_reg_offsets[3] + 0x03c6; |
964 | |
965 | dcn32_mpc_construct(mpc30, ctx, |
966 | &mpc_regs, |
967 | &mpc_shift, |
968 | &mpc_mask, |
969 | num_mpcc, |
970 | num_rmu); |
971 | |
972 | return &mpc30->base; |
973 | } |
974 | |
975 | static struct output_pixel_processor *dcn32_opp_create( |
976 | struct dc_context *ctx, uint32_t inst) |
977 | { |
978 | struct dcn20_opp *opp2 = |
979 | kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL(0x0001 | 0x0004)); |
980 | |
981 | if (!opp2) { |
982 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 982); do {} while (0); } while (0); |
983 | return NULL((void *)0); |
984 | } |
985 | |
986 | #undef REG_STRUCTdccg_regs |
987 | #define REG_STRUCTdccg_regs opp_regs |
988 | opp_regs_init(0)( ( dccg_regs[0].FMT_BIT_DEPTH_CONTROL = ctx->dcn_reg_offsets [2] + 0x1841, dccg_regs[0].FMT_CONTROL = ctx->dcn_reg_offsets [2] + 0x1840, dccg_regs[0].FMT_DITHER_RAND_R_SEED = ctx->dcn_reg_offsets [2] + 0x1842, dccg_regs[0].FMT_DITHER_RAND_G_SEED = ctx->dcn_reg_offsets [2] + 0x1843, dccg_regs[0].FMT_DITHER_RAND_B_SEED = ctx->dcn_reg_offsets [2] + 0x1844, dccg_regs[0].FMT_CLAMP_CNTL = ctx->dcn_reg_offsets [2] + 0x1845, dccg_regs[0].FMT_DYNAMIC_EXP_CNTL = ctx->dcn_reg_offsets [2] + 0x183f, dccg_regs[0].FMT_MAP420_MEMORY_CONTROL = ctx-> dcn_reg_offsets[2] + 0x1847, dccg_regs[0].OPPBUF_CONTROL = ctx ->dcn_reg_offsets[2] + 0x1884, dccg_regs[0].OPPBUF_3D_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x1885, dccg_regs[0].OPPBUF_3D_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x1886, dccg_regs[0].OPP_PIPE_CONTROL = ctx->dcn_reg_offsets[2] + 0x188c ), ( dccg_regs[0].DPG_CONTROL = ctx->dcn_reg_offsets[2] + 0x1854, dccg_regs[0].DPG_DIMENSIONS = ctx->dcn_reg_offsets[2] + 0x1856, dccg_regs[0].DPG_OFFSET_SEGMENT = ctx->dcn_reg_offsets[2] + 0x185a, dccg_regs[0].DPG_COLOUR_B_CB = ctx->dcn_reg_offsets[2] + 0x1859, dccg_regs[0].DPG_COLOUR_G_Y = ctx->dcn_reg_offsets[2] + 0x1858, dccg_regs[0].DPG_COLOUR_R_CR = ctx->dcn_reg_offsets[2] + 0x1857, dccg_regs[0].DPG_RAMP_CONTROL = ctx->dcn_reg_offsets[2] + 0x1855, dccg_regs[0].DPG_STATUS = ctx->dcn_reg_offsets[2] + 0x185b ), dccg_regs[0].FMT_422_CONTROL = ctx->dcn_reg_offsets[2] + 0x1849 ), |
989 | opp_regs_init(1)( ( dccg_regs[1].FMT_BIT_DEPTH_CONTROL = ctx->dcn_reg_offsets [2] + 0x189b, dccg_regs[1].FMT_CONTROL = ctx->dcn_reg_offsets [2] + 0x189a, dccg_regs[1].FMT_DITHER_RAND_R_SEED = ctx->dcn_reg_offsets [2] + 0x189c, dccg_regs[1].FMT_DITHER_RAND_G_SEED = ctx->dcn_reg_offsets [2] + 0x189d, dccg_regs[1].FMT_DITHER_RAND_B_SEED = ctx->dcn_reg_offsets [2] + 0x189e, dccg_regs[1].FMT_CLAMP_CNTL = ctx->dcn_reg_offsets [2] + 0x189f, dccg_regs[1].FMT_DYNAMIC_EXP_CNTL = ctx->dcn_reg_offsets [2] + 0x1899, dccg_regs[1].FMT_MAP420_MEMORY_CONTROL = ctx-> dcn_reg_offsets[2] + 0x18a1, dccg_regs[1].OPPBUF_CONTROL = ctx ->dcn_reg_offsets[2] + 0x18de, dccg_regs[1].OPPBUF_3D_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x18df, dccg_regs[1].OPPBUF_3D_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x18e0, dccg_regs[1].OPP_PIPE_CONTROL = ctx->dcn_reg_offsets[2] + 0x18e6 ), ( dccg_regs[1].DPG_CONTROL = ctx->dcn_reg_offsets[2] + 0x18ae, dccg_regs[1].DPG_DIMENSIONS = ctx->dcn_reg_offsets[2] + 0x18b0, dccg_regs[1].DPG_OFFSET_SEGMENT = ctx->dcn_reg_offsets[2] + 0x18b4, dccg_regs[1].DPG_COLOUR_B_CB = ctx->dcn_reg_offsets[2] + 0x18b3, dccg_regs[1].DPG_COLOUR_G_Y = ctx->dcn_reg_offsets[2] + 0x18b2, dccg_regs[1].DPG_COLOUR_R_CR = ctx->dcn_reg_offsets[2] + 0x18b1, dccg_regs[1].DPG_RAMP_CONTROL = ctx->dcn_reg_offsets[2] + 0x18af, dccg_regs[1].DPG_STATUS = ctx->dcn_reg_offsets[2] + 0x18b5 ), dccg_regs[1].FMT_422_CONTROL = ctx->dcn_reg_offsets[2] + 0x18a3 ), |
990 | opp_regs_init(2)( ( dccg_regs[2].FMT_BIT_DEPTH_CONTROL = ctx->dcn_reg_offsets [2] + 0x18f5, dccg_regs[2].FMT_CONTROL = ctx->dcn_reg_offsets [2] + 0x18f4, dccg_regs[2].FMT_DITHER_RAND_R_SEED = ctx->dcn_reg_offsets [2] + 0x18f6, dccg_regs[2].FMT_DITHER_RAND_G_SEED = ctx->dcn_reg_offsets [2] + 0x18f7, dccg_regs[2].FMT_DITHER_RAND_B_SEED = ctx->dcn_reg_offsets [2] + 0x18f8, dccg_regs[2].FMT_CLAMP_CNTL = ctx->dcn_reg_offsets [2] + 0x18f9, dccg_regs[2].FMT_DYNAMIC_EXP_CNTL = ctx->dcn_reg_offsets [2] + 0x18f3, dccg_regs[2].FMT_MAP420_MEMORY_CONTROL = ctx-> dcn_reg_offsets[2] + 0x18fb, dccg_regs[2].OPPBUF_CONTROL = ctx ->dcn_reg_offsets[2] + 0x1938, dccg_regs[2].OPPBUF_3D_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x1939, dccg_regs[2].OPPBUF_3D_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x193a, dccg_regs[2].OPP_PIPE_CONTROL = ctx->dcn_reg_offsets[2] + 0x1940 ), ( dccg_regs[2].DPG_CONTROL = ctx->dcn_reg_offsets[2] + 0x1908, dccg_regs[2].DPG_DIMENSIONS = ctx->dcn_reg_offsets[2] + 0x190a, dccg_regs[2].DPG_OFFSET_SEGMENT = ctx->dcn_reg_offsets[2] + 0x190e, dccg_regs[2].DPG_COLOUR_B_CB = ctx->dcn_reg_offsets[2] + 0x190d, dccg_regs[2].DPG_COLOUR_G_Y = ctx->dcn_reg_offsets[2] + 0x190c, dccg_regs[2].DPG_COLOUR_R_CR = ctx->dcn_reg_offsets[2] + 0x190b, dccg_regs[2].DPG_RAMP_CONTROL = ctx->dcn_reg_offsets[2] + 0x1909, dccg_regs[2].DPG_STATUS = ctx->dcn_reg_offsets[2] + 0x190f ), dccg_regs[2].FMT_422_CONTROL = ctx->dcn_reg_offsets[2] + 0x18fd ), |
991 | opp_regs_init(3)( ( dccg_regs[3].FMT_BIT_DEPTH_CONTROL = ctx->dcn_reg_offsets [2] + 0x194f, dccg_regs[3].FMT_CONTROL = ctx->dcn_reg_offsets [2] + 0x194e, dccg_regs[3].FMT_DITHER_RAND_R_SEED = ctx->dcn_reg_offsets [2] + 0x1950, dccg_regs[3].FMT_DITHER_RAND_G_SEED = ctx->dcn_reg_offsets [2] + 0x1951, dccg_regs[3].FMT_DITHER_RAND_B_SEED = ctx->dcn_reg_offsets [2] + 0x1952, dccg_regs[3].FMT_CLAMP_CNTL = ctx->dcn_reg_offsets [2] + 0x1953, dccg_regs[3].FMT_DYNAMIC_EXP_CNTL = ctx->dcn_reg_offsets [2] + 0x194d, dccg_regs[3].FMT_MAP420_MEMORY_CONTROL = ctx-> dcn_reg_offsets[2] + 0x1955, dccg_regs[3].OPPBUF_CONTROL = ctx ->dcn_reg_offsets[2] + 0x1992, dccg_regs[3].OPPBUF_3D_PARAMETERS_0 = ctx->dcn_reg_offsets[2] + 0x1993, dccg_regs[3].OPPBUF_3D_PARAMETERS_1 = ctx->dcn_reg_offsets[2] + 0x1994, dccg_regs[3].OPP_PIPE_CONTROL = ctx->dcn_reg_offsets[2] + 0x199a ), ( dccg_regs[3].DPG_CONTROL = ctx->dcn_reg_offsets[2] + 0x1962, dccg_regs[3].DPG_DIMENSIONS = ctx->dcn_reg_offsets[2] + 0x1964, dccg_regs[3].DPG_OFFSET_SEGMENT = ctx->dcn_reg_offsets[2] + 0x1968, dccg_regs[3].DPG_COLOUR_B_CB = ctx->dcn_reg_offsets[2] + 0x1967, dccg_regs[3].DPG_COLOUR_G_Y = ctx->dcn_reg_offsets[2] + 0x1966, dccg_regs[3].DPG_COLOUR_R_CR = ctx->dcn_reg_offsets[2] + 0x1965, dccg_regs[3].DPG_RAMP_CONTROL = ctx->dcn_reg_offsets[2] + 0x1963, dccg_regs[3].DPG_STATUS = ctx->dcn_reg_offsets[2] + 0x1969 ), dccg_regs[3].FMT_422_CONTROL = ctx->dcn_reg_offsets[2] + 0x1957 ); |
992 | |
993 | dcn20_opp_construct(opp2, ctx, inst, |
994 | &opp_regs[inst], &opp_shift, &opp_mask); |
995 | return &opp2->base; |
996 | } |
997 | |
998 | |
999 | static struct timing_generator *dcn32_timing_generator_create( |
1000 | struct dc_context *ctx, |
1001 | uint32_t instance) |
1002 | { |
1003 | struct optc *tgn10 = |
1004 | kzalloc(sizeof(struct optc), GFP_KERNEL(0x0001 | 0x0004)); |
1005 | |
1006 | if (!tgn10) |
1007 | return NULL((void *)0); |
1008 | |
1009 | #undef REG_STRUCTdccg_regs |
1010 | #define REG_STRUCTdccg_regs optc_regs |
1011 | optc_regs_init(0)( dccg_regs[0].OTG_VSTARTUP_PARAM = ctx->dcn_reg_offsets[2 ] + 0x1b86, dccg_regs[0].OTG_VUPDATE_PARAM = ctx->dcn_reg_offsets [2] + 0x1b87, dccg_regs[0].OTG_VREADY_PARAM = ctx->dcn_reg_offsets [2] + 0x1b88, dccg_regs[0].OTG_MASTER_UPDATE_LOCK = ctx->dcn_reg_offsets [2] + 0x1b8a, dccg_regs[0].OTG_GLOBAL_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1b8f, dccg_regs[0].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1b90, dccg_regs[0].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets [2] + 0x1b91, dccg_regs[0].OTG_GLOBAL_CONTROL4 = ctx->dcn_reg_offsets [2] + 0x1b93, dccg_regs[0].OTG_DOUBLE_BUFFER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x1b5b, dccg_regs[0].OTG_H_TOTAL = ctx-> dcn_reg_offsets[2] + 0x1b2a, dccg_regs[0].OTG_H_BLANK_START_END = ctx->dcn_reg_offsets[2] + 0x1b2b, dccg_regs[0].OTG_H_SYNC_A = ctx->dcn_reg_offsets[2] + 0x1b2c, dccg_regs[0].OTG_H_SYNC_A_CNTL = ctx->dcn_reg_offsets[2] + 0x1b2d, dccg_regs[0].OTG_H_TIMING_CNTL = ctx->dcn_reg_offsets[2] + 0x1b2e, dccg_regs[0].OTG_V_TOTAL = ctx->dcn_reg_offsets[2] + 0x1b2f, dccg_regs[0].OTG_V_BLANK_START_END = ctx->dcn_reg_offsets[2] + 0x1b36, dccg_regs[0].OTG_V_SYNC_A = ctx->dcn_reg_offsets[2] + 0x1b37, dccg_regs[0].OTG_V_SYNC_A_CNTL = ctx->dcn_reg_offsets[2] + 0x1b38, dccg_regs[0].OTG_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b41, dccg_regs[0].OTG_STEREO_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b54, dccg_regs[0].OTG_3D_STRUCTURE_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b82, dccg_regs[0].OTG_STEREO_STATUS = ctx->dcn_reg_offsets[2] + 0x1b53, dccg_regs[0].OTG_V_TOTAL_MAX = ctx->dcn_reg_offsets[2] + 0x1b31, dccg_regs[0].OTG_V_TOTAL_MIN = ctx->dcn_reg_offsets[2] + 0x1b30, dccg_regs[0].OTG_V_TOTAL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b33, dccg_regs[0].OTG_TRIGA_CNTL = ctx->dcn_reg_offsets[2] + 0x1b39, dccg_regs[0].OTG_FORCE_COUNT_NOW_CNTL = ctx->dcn_reg_offsets[2] + 0x1b3d, dccg_regs[0].OTG_STATIC_SCREEN_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b81, dccg_regs[0].OTG_STATUS_FRAME_COUNT = ctx->dcn_reg_offsets[2] + 0x1b4c, dccg_regs[0].OTG_STATUS = ctx->dcn_reg_offsets[2] + 0x1b49, dccg_regs[0].OTG_STATUS_POSITION = ctx->dcn_reg_offsets[2] + 0x1b4a, dccg_regs[0].OTG_NOM_VERT_POSITION = ctx->dcn_reg_offsets[2] + 0x1b4b, dccg_regs[0].OTG_M_CONST_DTO0 = ctx->dcn_reg_offsets[2] + 0x1b9b, dccg_regs[0].OTG_M_CONST_DTO1 = ctx->dcn_reg_offsets[2] + 0x1b9c, dccg_regs[0].OTG_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b85, dccg_regs[0].OTG_VERTICAL_INTERRUPT0_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b63, dccg_regs[0].OTG_VERTICAL_INTERRUPT0_POSITION = ctx->dcn_reg_offsets[2] + 0x1b62, dccg_regs[0].OTG_VERTICAL_INTERRUPT1_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b65, dccg_regs[0].OTG_VERTICAL_INTERRUPT1_POSITION = ctx->dcn_reg_offsets[2] + 0x1b64, dccg_regs[0].OTG_VERTICAL_INTERRUPT2_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b67, dccg_regs[0].OTG_VERTICAL_INTERRUPT2_POSITION = ctx->dcn_reg_offsets[2] + 0x1b66, dccg_regs[0].OPTC_INPUT_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x1acf, dccg_regs[0].OPTC_DATA_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1acb, dccg_regs[0].OPTC_INPUT_GLOBAL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1aca, dccg_regs[0].CONTROL = ctx->dcn_reg_offsets[2] + 0x052e, dccg_regs[0].OTG_VERT_SYNC_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b52, dccg_regs[0].OTG_GSL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b8b, dccg_regs[0].OTG_CRC_CNTL = ctx->dcn_reg_offsets[2] + 0x1b68, dccg_regs[0].OTG_CRC0_DATA_RG = ctx->dcn_reg_offsets[2] + 0x1b6d, dccg_regs[0].OTG_CRC0_DATA_B = ctx->dcn_reg_offsets[2] + 0x1b6e, dccg_regs[0].OTG_CRC0_WINDOWA_X_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b69, dccg_regs[0].OTG_CRC0_WINDOWA_Y_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b6a, dccg_regs[0].OTG_CRC0_WINDOWB_X_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b6b, dccg_regs[0].OTG_CRC0_WINDOWB_Y_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b6c, dccg_regs[0].GSL_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1e2b, dccg_regs[0].OTG_TRIGA_MANUAL_TRIG = ctx->dcn_reg_offsets[2] + 0x1b3a, dccg_regs[0].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x1b90, dccg_regs[0].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x1b91, dccg_regs[0].OTG_GSL_WINDOW_X = ctx->dcn_reg_offsets[2] + 0x1b8c, dccg_regs[0].OTG_GSL_WINDOW_Y = ctx->dcn_reg_offsets[2] + 0x1b8d, dccg_regs[0].OTG_VUPDATE_KEEPOUT = ctx->dcn_reg_offsets[2] + 0x1b8e, dccg_regs[0].OTG_DSC_START_POSITION = ctx->dcn_reg_offsets[2] + 0x1b9e, dccg_regs[0].OTG_DRR_TRIGGER_WINDOW = ctx->dcn_reg_offsets[2] + 0x1b99, dccg_regs[0].OTG_DRR_V_TOTAL_CHANGE = ctx->dcn_reg_offsets[2] + 0x1b98, dccg_regs[0].OPTC_DATA_FORMAT_CONTROL = ctx->dcn_reg_offsets[2] + 0x1acc, dccg_regs[0].OPTC_BYTES_PER_PIXEL = ctx->dcn_reg_offsets[2] + 0x1acd, dccg_regs[0].OPTC_WIDTH_CONTROL = ctx->dcn_reg_offsets[2] + 0x1ace, dccg_regs[0].OPTC_MEMORY_CONFIG = ctx->dcn_reg_offsets[2] + 0x1ad0, dccg_regs[0].OTG_DRR_CONTROL = ctx->dcn_reg_offsets[2] + 0x1b9a ), |
1012 | optc_regs_init(1)( dccg_regs[1].OTG_VSTARTUP_PARAM = ctx->dcn_reg_offsets[2 ] + 0x1c06, dccg_regs[1].OTG_VUPDATE_PARAM = ctx->dcn_reg_offsets [2] + 0x1c07, dccg_regs[1].OTG_VREADY_PARAM = ctx->dcn_reg_offsets [2] + 0x1c08, dccg_regs[1].OTG_MASTER_UPDATE_LOCK = ctx->dcn_reg_offsets [2] + 0x1c0a, dccg_regs[1].OTG_GLOBAL_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1c0f, dccg_regs[1].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1c10, dccg_regs[1].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets [2] + 0x1c11, dccg_regs[1].OTG_GLOBAL_CONTROL4 = ctx->dcn_reg_offsets [2] + 0x1c13, dccg_regs[1].OTG_DOUBLE_BUFFER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x1bdb, dccg_regs[1].OTG_H_TOTAL = ctx-> dcn_reg_offsets[2] + 0x1baa, dccg_regs[1].OTG_H_BLANK_START_END = ctx->dcn_reg_offsets[2] + 0x1bab, dccg_regs[1].OTG_H_SYNC_A = ctx->dcn_reg_offsets[2] + 0x1bac, dccg_regs[1].OTG_H_SYNC_A_CNTL = ctx->dcn_reg_offsets[2] + 0x1bad, dccg_regs[1].OTG_H_TIMING_CNTL = ctx->dcn_reg_offsets[2] + 0x1bae, dccg_regs[1].OTG_V_TOTAL = ctx->dcn_reg_offsets[2] + 0x1baf, dccg_regs[1].OTG_V_BLANK_START_END = ctx->dcn_reg_offsets[2] + 0x1bb6, dccg_regs[1].OTG_V_SYNC_A = ctx->dcn_reg_offsets[2] + 0x1bb7, dccg_regs[1].OTG_V_SYNC_A_CNTL = ctx->dcn_reg_offsets[2] + 0x1bb8, dccg_regs[1].OTG_CONTROL = ctx->dcn_reg_offsets[2] + 0x1bc1, dccg_regs[1].OTG_STEREO_CONTROL = ctx->dcn_reg_offsets[2] + 0x1bd4, dccg_regs[1].OTG_3D_STRUCTURE_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c02, dccg_regs[1].OTG_STEREO_STATUS = ctx->dcn_reg_offsets[2] + 0x1bd3, dccg_regs[1].OTG_V_TOTAL_MAX = ctx->dcn_reg_offsets[2] + 0x1bb1, dccg_regs[1].OTG_V_TOTAL_MIN = ctx->dcn_reg_offsets[2] + 0x1bb0, dccg_regs[1].OTG_V_TOTAL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1bb3, dccg_regs[1].OTG_TRIGA_CNTL = ctx->dcn_reg_offsets[2] + 0x1bb9, dccg_regs[1].OTG_FORCE_COUNT_NOW_CNTL = ctx->dcn_reg_offsets[2] + 0x1bbd, dccg_regs[1].OTG_STATIC_SCREEN_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c01, dccg_regs[1].OTG_STATUS_FRAME_COUNT = ctx->dcn_reg_offsets[2] + 0x1bcc, dccg_regs[1].OTG_STATUS = ctx->dcn_reg_offsets[2] + 0x1bc9, dccg_regs[1].OTG_STATUS_POSITION = ctx->dcn_reg_offsets[2] + 0x1bca, dccg_regs[1].OTG_NOM_VERT_POSITION = ctx->dcn_reg_offsets[2] + 0x1bcb, dccg_regs[1].OTG_M_CONST_DTO0 = ctx->dcn_reg_offsets[2] + 0x1c1b, dccg_regs[1].OTG_M_CONST_DTO1 = ctx->dcn_reg_offsets[2] + 0x1c1c, dccg_regs[1].OTG_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c05, dccg_regs[1].OTG_VERTICAL_INTERRUPT0_CONTROL = ctx->dcn_reg_offsets[2] + 0x1be3, dccg_regs[1].OTG_VERTICAL_INTERRUPT0_POSITION = ctx->dcn_reg_offsets[2] + 0x1be2, dccg_regs[1].OTG_VERTICAL_INTERRUPT1_CONTROL = ctx->dcn_reg_offsets[2] + 0x1be5, dccg_regs[1].OTG_VERTICAL_INTERRUPT1_POSITION = ctx->dcn_reg_offsets[2] + 0x1be4, dccg_regs[1].OTG_VERTICAL_INTERRUPT2_CONTROL = ctx->dcn_reg_offsets[2] + 0x1be7, dccg_regs[1].OTG_VERTICAL_INTERRUPT2_POSITION = ctx->dcn_reg_offsets[2] + 0x1be6, dccg_regs[1].OPTC_INPUT_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x1adf, dccg_regs[1].OPTC_DATA_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1adb, dccg_regs[1].OPTC_INPUT_GLOBAL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1ada, dccg_regs[1].CONTROL = ctx->dcn_reg_offsets[2] + 0x052f, dccg_regs[1].OTG_VERT_SYNC_CONTROL = ctx->dcn_reg_offsets[2] + 0x1bd2, dccg_regs[1].OTG_GSL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c0b, dccg_regs[1].OTG_CRC_CNTL = ctx->dcn_reg_offsets[2] + 0x1be8, dccg_regs[1].OTG_CRC0_DATA_RG = ctx->dcn_reg_offsets[2] + 0x1bed, dccg_regs[1].OTG_CRC0_DATA_B = ctx->dcn_reg_offsets[2] + 0x1bee, dccg_regs[1].OTG_CRC0_WINDOWA_X_CONTROL = ctx->dcn_reg_offsets[2] + 0x1be9, dccg_regs[1].OTG_CRC0_WINDOWA_Y_CONTROL = ctx->dcn_reg_offsets[2] + 0x1bea, dccg_regs[1].OTG_CRC0_WINDOWB_X_CONTROL = ctx->dcn_reg_offsets[2] + 0x1beb, dccg_regs[1].OTG_CRC0_WINDOWB_Y_CONTROL = ctx->dcn_reg_offsets[2] + 0x1bec, dccg_regs[1].GSL_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1e2b, dccg_regs[1].OTG_TRIGA_MANUAL_TRIG = ctx->dcn_reg_offsets[2] + 0x1bba, dccg_regs[1].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x1c10, dccg_regs[1].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x1c11, dccg_regs[1].OTG_GSL_WINDOW_X = ctx->dcn_reg_offsets[2] + 0x1c0c, dccg_regs[1].OTG_GSL_WINDOW_Y = ctx->dcn_reg_offsets[2] + 0x1c0d, dccg_regs[1].OTG_VUPDATE_KEEPOUT = ctx->dcn_reg_offsets[2] + 0x1c0e, dccg_regs[1].OTG_DSC_START_POSITION = ctx->dcn_reg_offsets[2] + 0x1c1e, dccg_regs[1].OTG_DRR_TRIGGER_WINDOW = ctx->dcn_reg_offsets[2] + 0x1c19, dccg_regs[1].OTG_DRR_V_TOTAL_CHANGE = ctx->dcn_reg_offsets[2] + 0x1c18, dccg_regs[1].OPTC_DATA_FORMAT_CONTROL = ctx->dcn_reg_offsets[2] + 0x1adc, dccg_regs[1].OPTC_BYTES_PER_PIXEL = ctx->dcn_reg_offsets[2] + 0x1add, dccg_regs[1].OPTC_WIDTH_CONTROL = ctx->dcn_reg_offsets[2] + 0x1ade, dccg_regs[1].OPTC_MEMORY_CONFIG = ctx->dcn_reg_offsets[2] + 0x1ae0, dccg_regs[1].OTG_DRR_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c1a ), |
1013 | optc_regs_init(2)( dccg_regs[2].OTG_VSTARTUP_PARAM = ctx->dcn_reg_offsets[2 ] + 0x1c86, dccg_regs[2].OTG_VUPDATE_PARAM = ctx->dcn_reg_offsets [2] + 0x1c87, dccg_regs[2].OTG_VREADY_PARAM = ctx->dcn_reg_offsets [2] + 0x1c88, dccg_regs[2].OTG_MASTER_UPDATE_LOCK = ctx->dcn_reg_offsets [2] + 0x1c8a, dccg_regs[2].OTG_GLOBAL_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1c8f, dccg_regs[2].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1c90, dccg_regs[2].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets [2] + 0x1c91, dccg_regs[2].OTG_GLOBAL_CONTROL4 = ctx->dcn_reg_offsets [2] + 0x1c93, dccg_regs[2].OTG_DOUBLE_BUFFER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x1c5b, dccg_regs[2].OTG_H_TOTAL = ctx-> dcn_reg_offsets[2] + 0x1c2a, dccg_regs[2].OTG_H_BLANK_START_END = ctx->dcn_reg_offsets[2] + 0x1c2b, dccg_regs[2].OTG_H_SYNC_A = ctx->dcn_reg_offsets[2] + 0x1c2c, dccg_regs[2].OTG_H_SYNC_A_CNTL = ctx->dcn_reg_offsets[2] + 0x1c2d, dccg_regs[2].OTG_H_TIMING_CNTL = ctx->dcn_reg_offsets[2] + 0x1c2e, dccg_regs[2].OTG_V_TOTAL = ctx->dcn_reg_offsets[2] + 0x1c2f, dccg_regs[2].OTG_V_BLANK_START_END = ctx->dcn_reg_offsets[2] + 0x1c36, dccg_regs[2].OTG_V_SYNC_A = ctx->dcn_reg_offsets[2] + 0x1c37, dccg_regs[2].OTG_V_SYNC_A_CNTL = ctx->dcn_reg_offsets[2] + 0x1c38, dccg_regs[2].OTG_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c41, dccg_regs[2].OTG_STEREO_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c54, dccg_regs[2].OTG_3D_STRUCTURE_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c82, dccg_regs[2].OTG_STEREO_STATUS = ctx->dcn_reg_offsets[2] + 0x1c53, dccg_regs[2].OTG_V_TOTAL_MAX = ctx->dcn_reg_offsets[2] + 0x1c31, dccg_regs[2].OTG_V_TOTAL_MIN = ctx->dcn_reg_offsets[2] + 0x1c30, dccg_regs[2].OTG_V_TOTAL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c33, dccg_regs[2].OTG_TRIGA_CNTL = ctx->dcn_reg_offsets[2] + 0x1c39, dccg_regs[2].OTG_FORCE_COUNT_NOW_CNTL = ctx->dcn_reg_offsets[2] + 0x1c3d, dccg_regs[2].OTG_STATIC_SCREEN_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c81, dccg_regs[2].OTG_STATUS_FRAME_COUNT = ctx->dcn_reg_offsets[2] + 0x1c4c, dccg_regs[2].OTG_STATUS = ctx->dcn_reg_offsets[2] + 0x1c49, dccg_regs[2].OTG_STATUS_POSITION = ctx->dcn_reg_offsets[2] + 0x1c4a, dccg_regs[2].OTG_NOM_VERT_POSITION = ctx->dcn_reg_offsets[2] + 0x1c4b, dccg_regs[2].OTG_M_CONST_DTO0 = ctx->dcn_reg_offsets[2] + 0x1c9b, dccg_regs[2].OTG_M_CONST_DTO1 = ctx->dcn_reg_offsets[2] + 0x1c9c, dccg_regs[2].OTG_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c85, dccg_regs[2].OTG_VERTICAL_INTERRUPT0_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c63, dccg_regs[2].OTG_VERTICAL_INTERRUPT0_POSITION = ctx->dcn_reg_offsets[2] + 0x1c62, dccg_regs[2].OTG_VERTICAL_INTERRUPT1_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c65, dccg_regs[2].OTG_VERTICAL_INTERRUPT1_POSITION = ctx->dcn_reg_offsets[2] + 0x1c64, dccg_regs[2].OTG_VERTICAL_INTERRUPT2_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c67, dccg_regs[2].OTG_VERTICAL_INTERRUPT2_POSITION = ctx->dcn_reg_offsets[2] + 0x1c66, dccg_regs[2].OPTC_INPUT_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x1aef, dccg_regs[2].OPTC_DATA_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1aeb, dccg_regs[2].OPTC_INPUT_GLOBAL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1aea, dccg_regs[2].CONTROL = ctx->dcn_reg_offsets[2] + 0x0530, dccg_regs[2].OTG_VERT_SYNC_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c52, dccg_regs[2].OTG_GSL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c8b, dccg_regs[2].OTG_CRC_CNTL = ctx->dcn_reg_offsets[2] + 0x1c68, dccg_regs[2].OTG_CRC0_DATA_RG = ctx->dcn_reg_offsets[2] + 0x1c6d, dccg_regs[2].OTG_CRC0_DATA_B = ctx->dcn_reg_offsets[2] + 0x1c6e, dccg_regs[2].OTG_CRC0_WINDOWA_X_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c69, dccg_regs[2].OTG_CRC0_WINDOWA_Y_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c6a, dccg_regs[2].OTG_CRC0_WINDOWB_X_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c6b, dccg_regs[2].OTG_CRC0_WINDOWB_Y_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c6c, dccg_regs[2].GSL_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1e2b, dccg_regs[2].OTG_TRIGA_MANUAL_TRIG = ctx->dcn_reg_offsets[2] + 0x1c3a, dccg_regs[2].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x1c90, dccg_regs[2].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x1c91, dccg_regs[2].OTG_GSL_WINDOW_X = ctx->dcn_reg_offsets[2] + 0x1c8c, dccg_regs[2].OTG_GSL_WINDOW_Y = ctx->dcn_reg_offsets[2] + 0x1c8d, dccg_regs[2].OTG_VUPDATE_KEEPOUT = ctx->dcn_reg_offsets[2] + 0x1c8e, dccg_regs[2].OTG_DSC_START_POSITION = ctx->dcn_reg_offsets[2] + 0x1c9e, dccg_regs[2].OTG_DRR_TRIGGER_WINDOW = ctx->dcn_reg_offsets[2] + 0x1c99, dccg_regs[2].OTG_DRR_V_TOTAL_CHANGE = ctx->dcn_reg_offsets[2] + 0x1c98, dccg_regs[2].OPTC_DATA_FORMAT_CONTROL = ctx->dcn_reg_offsets[2] + 0x1aec, dccg_regs[2].OPTC_BYTES_PER_PIXEL = ctx->dcn_reg_offsets[2] + 0x1aed, dccg_regs[2].OPTC_WIDTH_CONTROL = ctx->dcn_reg_offsets[2] + 0x1aee, dccg_regs[2].OPTC_MEMORY_CONFIG = ctx->dcn_reg_offsets[2] + 0x1af0, dccg_regs[2].OTG_DRR_CONTROL = ctx->dcn_reg_offsets[2] + 0x1c9a ), |
1014 | optc_regs_init(3)( dccg_regs[3].OTG_VSTARTUP_PARAM = ctx->dcn_reg_offsets[2 ] + 0x1d06, dccg_regs[3].OTG_VUPDATE_PARAM = ctx->dcn_reg_offsets [2] + 0x1d07, dccg_regs[3].OTG_VREADY_PARAM = ctx->dcn_reg_offsets [2] + 0x1d08, dccg_regs[3].OTG_MASTER_UPDATE_LOCK = ctx->dcn_reg_offsets [2] + 0x1d0a, dccg_regs[3].OTG_GLOBAL_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1d0f, dccg_regs[3].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1d10, dccg_regs[3].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets [2] + 0x1d11, dccg_regs[3].OTG_GLOBAL_CONTROL4 = ctx->dcn_reg_offsets [2] + 0x1d13, dccg_regs[3].OTG_DOUBLE_BUFFER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x1cdb, dccg_regs[3].OTG_H_TOTAL = ctx-> dcn_reg_offsets[2] + 0x1caa, dccg_regs[3].OTG_H_BLANK_START_END = ctx->dcn_reg_offsets[2] + 0x1cab, dccg_regs[3].OTG_H_SYNC_A = ctx->dcn_reg_offsets[2] + 0x1cac, dccg_regs[3].OTG_H_SYNC_A_CNTL = ctx->dcn_reg_offsets[2] + 0x1cad, dccg_regs[3].OTG_H_TIMING_CNTL = ctx->dcn_reg_offsets[2] + 0x1cae, dccg_regs[3].OTG_V_TOTAL = ctx->dcn_reg_offsets[2] + 0x1caf, dccg_regs[3].OTG_V_BLANK_START_END = ctx->dcn_reg_offsets[2] + 0x1cb6, dccg_regs[3].OTG_V_SYNC_A = ctx->dcn_reg_offsets[2] + 0x1cb7, dccg_regs[3].OTG_V_SYNC_A_CNTL = ctx->dcn_reg_offsets[2] + 0x1cb8, dccg_regs[3].OTG_CONTROL = ctx->dcn_reg_offsets[2] + 0x1cc1, dccg_regs[3].OTG_STEREO_CONTROL = ctx->dcn_reg_offsets[2] + 0x1cd4, dccg_regs[3].OTG_3D_STRUCTURE_CONTROL = ctx->dcn_reg_offsets[2] + 0x1d02, dccg_regs[3].OTG_STEREO_STATUS = ctx->dcn_reg_offsets[2] + 0x1cd3, dccg_regs[3].OTG_V_TOTAL_MAX = ctx->dcn_reg_offsets[2] + 0x1cb1, dccg_regs[3].OTG_V_TOTAL_MIN = ctx->dcn_reg_offsets[2] + 0x1cb0, dccg_regs[3].OTG_V_TOTAL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1cb3, dccg_regs[3].OTG_TRIGA_CNTL = ctx->dcn_reg_offsets[2] + 0x1cb9, dccg_regs[3].OTG_FORCE_COUNT_NOW_CNTL = ctx->dcn_reg_offsets[2] + 0x1cbd, dccg_regs[3].OTG_STATIC_SCREEN_CONTROL = ctx->dcn_reg_offsets[2] + 0x1d01, dccg_regs[3].OTG_STATUS_FRAME_COUNT = ctx->dcn_reg_offsets[2] + 0x1ccc, dccg_regs[3].OTG_STATUS = ctx->dcn_reg_offsets[2] + 0x1cc9, dccg_regs[3].OTG_STATUS_POSITION = ctx->dcn_reg_offsets[2] + 0x1cca, dccg_regs[3].OTG_NOM_VERT_POSITION = ctx->dcn_reg_offsets[2] + 0x1ccb, dccg_regs[3].OTG_M_CONST_DTO0 = ctx->dcn_reg_offsets[2] + 0x1d1b, dccg_regs[3].OTG_M_CONST_DTO1 = ctx->dcn_reg_offsets[2] + 0x1d1c, dccg_regs[3].OTG_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x1d05, dccg_regs[3].OTG_VERTICAL_INTERRUPT0_CONTROL = ctx->dcn_reg_offsets[2] + 0x1ce3, dccg_regs[3].OTG_VERTICAL_INTERRUPT0_POSITION = ctx->dcn_reg_offsets[2] + 0x1ce2, dccg_regs[3].OTG_VERTICAL_INTERRUPT1_CONTROL = ctx->dcn_reg_offsets[2] + 0x1ce5, dccg_regs[3].OTG_VERTICAL_INTERRUPT1_POSITION = ctx->dcn_reg_offsets[2] + 0x1ce4, dccg_regs[3].OTG_VERTICAL_INTERRUPT2_CONTROL = ctx->dcn_reg_offsets[2] + 0x1ce7, dccg_regs[3].OTG_VERTICAL_INTERRUPT2_POSITION = ctx->dcn_reg_offsets[2] + 0x1ce6, dccg_regs[3].OPTC_INPUT_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x1aff, dccg_regs[3].OPTC_DATA_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1afb, dccg_regs[3].OPTC_INPUT_GLOBAL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1afa, dccg_regs[3].CONTROL = ctx->dcn_reg_offsets[2] + 0x0531, dccg_regs[3].OTG_VERT_SYNC_CONTROL = ctx->dcn_reg_offsets[2] + 0x1cd2, dccg_regs[3].OTG_GSL_CONTROL = ctx->dcn_reg_offsets[2] + 0x1d0b, dccg_regs[3].OTG_CRC_CNTL = ctx->dcn_reg_offsets[2] + 0x1ce8, dccg_regs[3].OTG_CRC0_DATA_RG = ctx->dcn_reg_offsets[2] + 0x1ced, dccg_regs[3].OTG_CRC0_DATA_B = ctx->dcn_reg_offsets[2] + 0x1cee, dccg_regs[3].OTG_CRC0_WINDOWA_X_CONTROL = ctx->dcn_reg_offsets[2] + 0x1ce9, dccg_regs[3].OTG_CRC0_WINDOWA_Y_CONTROL = ctx->dcn_reg_offsets[2] + 0x1cea, dccg_regs[3].OTG_CRC0_WINDOWB_X_CONTROL = ctx->dcn_reg_offsets[2] + 0x1ceb, dccg_regs[3].OTG_CRC0_WINDOWB_Y_CONTROL = ctx->dcn_reg_offsets[2] + 0x1cec, dccg_regs[3].GSL_SOURCE_SELECT = ctx->dcn_reg_offsets[2] + 0x1e2b, dccg_regs[3].OTG_TRIGA_MANUAL_TRIG = ctx->dcn_reg_offsets[2] + 0x1cba, dccg_regs[3].OTG_GLOBAL_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x1d10, dccg_regs[3].OTG_GLOBAL_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x1d11, dccg_regs[3].OTG_GSL_WINDOW_X = ctx->dcn_reg_offsets[2] + 0x1d0c, dccg_regs[3].OTG_GSL_WINDOW_Y = ctx->dcn_reg_offsets[2] + 0x1d0d, dccg_regs[3].OTG_VUPDATE_KEEPOUT = ctx->dcn_reg_offsets[2] + 0x1d0e, dccg_regs[3].OTG_DSC_START_POSITION = ctx->dcn_reg_offsets[2] + 0x1d1e, dccg_regs[3].OTG_DRR_TRIGGER_WINDOW = ctx->dcn_reg_offsets[2] + 0x1d19, dccg_regs[3].OTG_DRR_V_TOTAL_CHANGE = ctx->dcn_reg_offsets[2] + 0x1d18, dccg_regs[3].OPTC_DATA_FORMAT_CONTROL = ctx->dcn_reg_offsets[2] + 0x1afc, dccg_regs[3].OPTC_BYTES_PER_PIXEL = ctx->dcn_reg_offsets[2] + 0x1afd, dccg_regs[3].OPTC_WIDTH_CONTROL = ctx->dcn_reg_offsets[2] + 0x1afe, dccg_regs[3].OPTC_MEMORY_CONFIG = ctx->dcn_reg_offsets[2] + 0x1b00, dccg_regs[3].OTG_DRR_CONTROL = ctx->dcn_reg_offsets[2] + 0x1d1a ); |
1015 | |
1016 | tgn10->base.inst = instance; |
1017 | tgn10->base.ctx = ctx; |
1018 | |
1019 | tgn10->tg_regs = &optc_regs[instance]; |
1020 | tgn10->tg_shift = &optc_shift; |
1021 | tgn10->tg_mask = &optc_mask; |
1022 | |
1023 | dcn32_timing_generator_init(tgn10); |
1024 | |
1025 | return &tgn10->base; |
1026 | } |
1027 | |
1028 | static const struct encoder_feature_support link_enc_feature = { |
1029 | .max_hdmi_deep_color = COLOR_DEPTH_121212, |
1030 | .max_hdmi_pixel_clock = 600000, |
1031 | .hdmi_ycbcr420_supported = true1, |
1032 | .dp_ycbcr420_supported = true1, |
1033 | .fec_supported = true1, |
1034 | .flags.bits.IS_HBR2_CAPABLE = true1, |
1035 | .flags.bits.IS_HBR3_CAPABLE = true1, |
1036 | .flags.bits.IS_TPS3_CAPABLE = true1, |
1037 | .flags.bits.IS_TPS4_CAPABLE = true1 |
1038 | }; |
1039 | |
1040 | static struct link_encoder *dcn32_link_encoder_create( |
1041 | struct dc_context *ctx, |
1042 | const struct encoder_init_data *enc_init_data) |
1043 | { |
1044 | struct dcn20_link_encoder *enc20 = |
1045 | kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL(0x0001 | 0x0004)); |
1046 | |
1047 | if (!enc20) |
1048 | return NULL((void *)0); |
1049 | |
1050 | #undef REG_STRUCTdccg_regs |
1051 | #define REG_STRUCTdccg_regs link_enc_aux_regs |
1052 | aux_regs_init(0)( ( dccg_regs[0].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f50 , dccg_regs[0].AUX_DPHY_RX_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1f5a, dccg_regs[0].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1f5b ), dccg_regs[0].AUX_DPHY_TX_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f59 ), |
1053 | aux_regs_init(1)( ( dccg_regs[1].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f6c , dccg_regs[1].AUX_DPHY_RX_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1f76, dccg_regs[1].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1f77 ), dccg_regs[1].AUX_DPHY_TX_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f75 ), |
1054 | aux_regs_init(2)( ( dccg_regs[2].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f88 , dccg_regs[2].AUX_DPHY_RX_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1f92, dccg_regs[2].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1f93 ), dccg_regs[2].AUX_DPHY_TX_CONTROL = ctx->dcn_reg_offsets [2] + 0x1f91 ), |
1055 | aux_regs_init(3)( ( dccg_regs[3].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1fa4 , dccg_regs[3].AUX_DPHY_RX_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1fae, dccg_regs[3].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1faf ), dccg_regs[3].AUX_DPHY_TX_CONTROL = ctx->dcn_reg_offsets [2] + 0x1fad ), |
1056 | aux_regs_init(4)( ( dccg_regs[4].AUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x1fc0 , dccg_regs[4].AUX_DPHY_RX_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x1fca, dccg_regs[4].AUX_DPHY_RX_CONTROL1 = ctx->dcn_reg_offsets [2] + 0x1fcb ), dccg_regs[4].AUX_DPHY_TX_CONTROL = ctx->dcn_reg_offsets [2] + 0x1fc9 ); |
1057 | |
1058 | #undef REG_STRUCTdccg_regs |
1059 | #define REG_STRUCTdccg_regs link_enc_hpd_regs |
1060 | hpd_regs_init(0)dccg_regs[0].DC_HPD_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f16, |
1061 | hpd_regs_init(1)dccg_regs[1].DC_HPD_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f1e, |
1062 | hpd_regs_init(2)dccg_regs[2].DC_HPD_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f26, |
1063 | hpd_regs_init(3)dccg_regs[3].DC_HPD_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f2e, |
1064 | hpd_regs_init(4)dccg_regs[4].DC_HPD_CONTROL = ctx->dcn_reg_offsets[2] + 0x1f36; |
1065 | |
1066 | #undef REG_STRUCTdccg_regs |
1067 | #define REG_STRUCTdccg_regs link_enc_regs |
1068 | link_regs_init(0, A)( ( ( dccg_regs[0].DIG_BE_CNTL = ctx->dcn_reg_offsets[2] + 0x20b1, dccg_regs[0].DIG_BE_EN_CNTL = ctx->dcn_reg_offsets [2] + 0x20b2, dccg_regs[0].TMDS_CTL_BITS = ctx->dcn_reg_offsets [2] + 0x20df, dccg_regs[0].TMDS_DCBALANCER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x20e0, dccg_regs[0].DP_CONFIG = ctx-> dcn_reg_offsets[2] + 0x210b, dccg_regs[0].DP_DPHY_CNTL = ctx-> dcn_reg_offsets[2] + 0x2117, dccg_regs[0].DP_DPHY_PRBS_CNTL = ctx->dcn_reg_offsets[2] + 0x211d, dccg_regs[0].DP_DPHY_SCRAM_CNTL = ctx->dcn_reg_offsets[2] + 0x211e, dccg_regs[0].DP_DPHY_SYM0 = ctx->dcn_reg_offsets[2] + 0x2119, dccg_regs[0].DP_DPHY_SYM1 = ctx->dcn_reg_offsets[2] + 0x211a, dccg_regs[0].DP_DPHY_SYM2 = ctx->dcn_reg_offsets[2] + 0x211b, dccg_regs[0].DP_DPHY_TRAINING_PATTERN_SEL = ctx->dcn_reg_offsets[2] + 0x2118, dccg_regs[0].DP_LINK_CNTL = ctx->dcn_reg_offsets[2] + 0x2108, dccg_regs[0].DP_LINK_FRAMING_CNTL = ctx->dcn_reg_offsets[2] + 0x2113, dccg_regs[0].DP_MSE_SAT0 = ctx->dcn_reg_offsets[2] + 0x213a, dccg_regs[0].DP_MSE_SAT1 = ctx->dcn_reg_offsets[2] + 0x213b, dccg_regs[0].DP_MSE_SAT2 = ctx->dcn_reg_offsets[2] + 0x213c, dccg_regs[0].DP_MSE_SAT_UPDATE = ctx->dcn_reg_offsets[2] + 0x213d, dccg_regs[0].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x212b, dccg_regs[0].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x210c, dccg_regs[0].DP_DPHY_FAST_TRAINING = ctx->dcn_reg_offsets[2] + 0x2124, dccg_regs[0].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x212c, dccg_regs[0].DP_DPHY_BS_SR_SWAP_CNTL = ctx->dcn_reg_offsets[2] + 0x2144, dccg_regs[0].DP_DPHY_HBR2_PATTERN_CONTROL = ctx->dcn_reg_offsets[2] + 0x2145 ), dccg_regs[0].DP_DPHY_INTERNAL_CTRL = ctx->dcn_reg_offsets[2] + 0x210f, dccg_regs[0].DIO_LINKA_CNTL = ctx->dcn_reg_offsets[2] + 0x1f04, dccg_regs[0].DIO_LINKB_CNTL = ctx->dcn_reg_offsets[2] + 0x1f05, dccg_regs[0].DIO_LINKC_CNTL = ctx->dcn_reg_offsets[2] + 0x1f06, dccg_regs[0].DIO_LINKD_CNTL = ctx->dcn_reg_offsets[2] + 0x1f07, dccg_regs[0].DIO_LINKE_CNTL = ctx->dcn_reg_offsets[2] + 0x1f08, dccg_regs[0].DIO_LINKF_CNTL = ctx->dcn_reg_offsets[2] + 0x1f09 ), ( dccg_regs[0].CLOCK_ENABLE = ctx->dcn_reg_offsets[1] + 0x00a0, dccg_regs[0].CHANNEL_XBAR_CNTL = ctx->dcn_reg_offsets[2] + 0x286e ) ), |
1069 | link_regs_init(1, B)( ( ( dccg_regs[1].DIG_BE_CNTL = ctx->dcn_reg_offsets[2] + 0x21b1, dccg_regs[1].DIG_BE_EN_CNTL = ctx->dcn_reg_offsets [2] + 0x21b2, dccg_regs[1].TMDS_CTL_BITS = ctx->dcn_reg_offsets [2] + 0x21df, dccg_regs[1].TMDS_DCBALANCER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x21e0, dccg_regs[1].DP_CONFIG = ctx-> dcn_reg_offsets[2] + 0x220b, dccg_regs[1].DP_DPHY_CNTL = ctx-> dcn_reg_offsets[2] + 0x2217, dccg_regs[1].DP_DPHY_PRBS_CNTL = ctx->dcn_reg_offsets[2] + 0x221d, dccg_regs[1].DP_DPHY_SCRAM_CNTL = ctx->dcn_reg_offsets[2] + 0x221e, dccg_regs[1].DP_DPHY_SYM0 = ctx->dcn_reg_offsets[2] + 0x2219, dccg_regs[1].DP_DPHY_SYM1 = ctx->dcn_reg_offsets[2] + 0x221a, dccg_regs[1].DP_DPHY_SYM2 = ctx->dcn_reg_offsets[2] + 0x221b, dccg_regs[1].DP_DPHY_TRAINING_PATTERN_SEL = ctx->dcn_reg_offsets[2] + 0x2218, dccg_regs[1].DP_LINK_CNTL = ctx->dcn_reg_offsets[2] + 0x2208, dccg_regs[1].DP_LINK_FRAMING_CNTL = ctx->dcn_reg_offsets[2] + 0x2213, dccg_regs[1].DP_MSE_SAT0 = ctx->dcn_reg_offsets[2] + 0x223a, dccg_regs[1].DP_MSE_SAT1 = ctx->dcn_reg_offsets[2] + 0x223b, dccg_regs[1].DP_MSE_SAT2 = ctx->dcn_reg_offsets[2] + 0x223c, dccg_regs[1].DP_MSE_SAT_UPDATE = ctx->dcn_reg_offsets[2] + 0x223d, dccg_regs[1].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x222b, dccg_regs[1].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x220c, dccg_regs[1].DP_DPHY_FAST_TRAINING = ctx->dcn_reg_offsets[2] + 0x2224, dccg_regs[1].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x222c, dccg_regs[1].DP_DPHY_BS_SR_SWAP_CNTL = ctx->dcn_reg_offsets[2] + 0x2244, dccg_regs[1].DP_DPHY_HBR2_PATTERN_CONTROL = ctx->dcn_reg_offsets[2] + 0x2245 ), dccg_regs[1].DP_DPHY_INTERNAL_CTRL = ctx->dcn_reg_offsets[2] + 0x220f, dccg_regs[1].DIO_LINKA_CNTL = ctx->dcn_reg_offsets[2] + 0x1f04, dccg_regs[1].DIO_LINKB_CNTL = ctx->dcn_reg_offsets[2] + 0x1f05, dccg_regs[1].DIO_LINKC_CNTL = ctx->dcn_reg_offsets[2] + 0x1f06, dccg_regs[1].DIO_LINKD_CNTL = ctx->dcn_reg_offsets[2] + 0x1f07, dccg_regs[1].DIO_LINKE_CNTL = ctx->dcn_reg_offsets[2] + 0x1f08, dccg_regs[1].DIO_LINKF_CNTL = ctx->dcn_reg_offsets[2] + 0x1f09 ), ( dccg_regs[1].CLOCK_ENABLE = ctx->dcn_reg_offsets[1] + 0x00a1, dccg_regs[1].CHANNEL_XBAR_CNTL = ctx->dcn_reg_offsets[2] + 0x2870 ) ), |
1070 | link_regs_init(2, C)( ( ( dccg_regs[2].DIG_BE_CNTL = ctx->dcn_reg_offsets[2] + 0x22b1, dccg_regs[2].DIG_BE_EN_CNTL = ctx->dcn_reg_offsets [2] + 0x22b2, dccg_regs[2].TMDS_CTL_BITS = ctx->dcn_reg_offsets [2] + 0x22df, dccg_regs[2].TMDS_DCBALANCER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x22e0, dccg_regs[2].DP_CONFIG = ctx-> dcn_reg_offsets[2] + 0x230b, dccg_regs[2].DP_DPHY_CNTL = ctx-> dcn_reg_offsets[2] + 0x2317, dccg_regs[2].DP_DPHY_PRBS_CNTL = ctx->dcn_reg_offsets[2] + 0x231d, dccg_regs[2].DP_DPHY_SCRAM_CNTL = ctx->dcn_reg_offsets[2] + 0x231e, dccg_regs[2].DP_DPHY_SYM0 = ctx->dcn_reg_offsets[2] + 0x2319, dccg_regs[2].DP_DPHY_SYM1 = ctx->dcn_reg_offsets[2] + 0x231a, dccg_regs[2].DP_DPHY_SYM2 = ctx->dcn_reg_offsets[2] + 0x231b, dccg_regs[2].DP_DPHY_TRAINING_PATTERN_SEL = ctx->dcn_reg_offsets[2] + 0x2318, dccg_regs[2].DP_LINK_CNTL = ctx->dcn_reg_offsets[2] + 0x2308, dccg_regs[2].DP_LINK_FRAMING_CNTL = ctx->dcn_reg_offsets[2] + 0x2313, dccg_regs[2].DP_MSE_SAT0 = ctx->dcn_reg_offsets[2] + 0x233a, dccg_regs[2].DP_MSE_SAT1 = ctx->dcn_reg_offsets[2] + 0x233b, dccg_regs[2].DP_MSE_SAT2 = ctx->dcn_reg_offsets[2] + 0x233c, dccg_regs[2].DP_MSE_SAT_UPDATE = ctx->dcn_reg_offsets[2] + 0x233d, dccg_regs[2].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x232b, dccg_regs[2].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x230c, dccg_regs[2].DP_DPHY_FAST_TRAINING = ctx->dcn_reg_offsets[2] + 0x2324, dccg_regs[2].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x232c, dccg_regs[2].DP_DPHY_BS_SR_SWAP_CNTL = ctx->dcn_reg_offsets[2] + 0x2344, dccg_regs[2].DP_DPHY_HBR2_PATTERN_CONTROL = ctx->dcn_reg_offsets[2] + 0x2345 ), dccg_regs[2].DP_DPHY_INTERNAL_CTRL = ctx->dcn_reg_offsets[2] + 0x230f, dccg_regs[2].DIO_LINKA_CNTL = ctx->dcn_reg_offsets[2] + 0x1f04, dccg_regs[2].DIO_LINKB_CNTL = ctx->dcn_reg_offsets[2] + 0x1f05, dccg_regs[2].DIO_LINKC_CNTL = ctx->dcn_reg_offsets[2] + 0x1f06, dccg_regs[2].DIO_LINKD_CNTL = ctx->dcn_reg_offsets[2] + 0x1f07, dccg_regs[2].DIO_LINKE_CNTL = ctx->dcn_reg_offsets[2] + 0x1f08, dccg_regs[2].DIO_LINKF_CNTL = ctx->dcn_reg_offsets[2] + 0x1f09 ), ( dccg_regs[2].CLOCK_ENABLE = ctx->dcn_reg_offsets[1] + 0x00a2, dccg_regs[2].CHANNEL_XBAR_CNTL = ctx->dcn_reg_offsets[2] + 0x2872 ) ), |
1071 | link_regs_init(3, D)( ( ( dccg_regs[3].DIG_BE_CNTL = ctx->dcn_reg_offsets[2] + 0x23b1, dccg_regs[3].DIG_BE_EN_CNTL = ctx->dcn_reg_offsets [2] + 0x23b2, dccg_regs[3].TMDS_CTL_BITS = ctx->dcn_reg_offsets [2] + 0x23df, dccg_regs[3].TMDS_DCBALANCER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x23e0, dccg_regs[3].DP_CONFIG = ctx-> dcn_reg_offsets[2] + 0x240b, dccg_regs[3].DP_DPHY_CNTL = ctx-> dcn_reg_offsets[2] + 0x2417, dccg_regs[3].DP_DPHY_PRBS_CNTL = ctx->dcn_reg_offsets[2] + 0x241d, dccg_regs[3].DP_DPHY_SCRAM_CNTL = ctx->dcn_reg_offsets[2] + 0x241e, dccg_regs[3].DP_DPHY_SYM0 = ctx->dcn_reg_offsets[2] + 0x2419, dccg_regs[3].DP_DPHY_SYM1 = ctx->dcn_reg_offsets[2] + 0x241a, dccg_regs[3].DP_DPHY_SYM2 = ctx->dcn_reg_offsets[2] + 0x241b, dccg_regs[3].DP_DPHY_TRAINING_PATTERN_SEL = ctx->dcn_reg_offsets[2] + 0x2418, dccg_regs[3].DP_LINK_CNTL = ctx->dcn_reg_offsets[2] + 0x2408, dccg_regs[3].DP_LINK_FRAMING_CNTL = ctx->dcn_reg_offsets[2] + 0x2413, dccg_regs[3].DP_MSE_SAT0 = ctx->dcn_reg_offsets[2] + 0x243a, dccg_regs[3].DP_MSE_SAT1 = ctx->dcn_reg_offsets[2] + 0x243b, dccg_regs[3].DP_MSE_SAT2 = ctx->dcn_reg_offsets[2] + 0x243c, dccg_regs[3].DP_MSE_SAT_UPDATE = ctx->dcn_reg_offsets[2] + 0x243d, dccg_regs[3].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x242b, dccg_regs[3].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x240c, dccg_regs[3].DP_DPHY_FAST_TRAINING = ctx->dcn_reg_offsets[2] + 0x2424, dccg_regs[3].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x242c, dccg_regs[3].DP_DPHY_BS_SR_SWAP_CNTL = ctx->dcn_reg_offsets[2] + 0x2444, dccg_regs[3].DP_DPHY_HBR2_PATTERN_CONTROL = ctx->dcn_reg_offsets[2] + 0x2445 ), dccg_regs[3].DP_DPHY_INTERNAL_CTRL = ctx->dcn_reg_offsets[2] + 0x240f, dccg_regs[3].DIO_LINKA_CNTL = ctx->dcn_reg_offsets[2] + 0x1f04, dccg_regs[3].DIO_LINKB_CNTL = ctx->dcn_reg_offsets[2] + 0x1f05, dccg_regs[3].DIO_LINKC_CNTL = ctx->dcn_reg_offsets[2] + 0x1f06, dccg_regs[3].DIO_LINKD_CNTL = ctx->dcn_reg_offsets[2] + 0x1f07, dccg_regs[3].DIO_LINKE_CNTL = ctx->dcn_reg_offsets[2] + 0x1f08, dccg_regs[3].DIO_LINKF_CNTL = ctx->dcn_reg_offsets[2] + 0x1f09 ), ( dccg_regs[3].CLOCK_ENABLE = ctx->dcn_reg_offsets[1] + 0x00a3, dccg_regs[3].CHANNEL_XBAR_CNTL = ctx->dcn_reg_offsets[2] + 0x2874 ) ), |
1072 | link_regs_init(4, E)( ( ( dccg_regs[4].DIG_BE_CNTL = ctx->dcn_reg_offsets[2] + 0x24b1, dccg_regs[4].DIG_BE_EN_CNTL = ctx->dcn_reg_offsets [2] + 0x24b2, dccg_regs[4].TMDS_CTL_BITS = ctx->dcn_reg_offsets [2] + 0x24df, dccg_regs[4].TMDS_DCBALANCER_CONTROL = ctx-> dcn_reg_offsets[2] + 0x24e0, dccg_regs[4].DP_CONFIG = ctx-> dcn_reg_offsets[2] + 0x250b, dccg_regs[4].DP_DPHY_CNTL = ctx-> dcn_reg_offsets[2] + 0x2517, dccg_regs[4].DP_DPHY_PRBS_CNTL = ctx->dcn_reg_offsets[2] + 0x251d, dccg_regs[4].DP_DPHY_SCRAM_CNTL = ctx->dcn_reg_offsets[2] + 0x251e, dccg_regs[4].DP_DPHY_SYM0 = ctx->dcn_reg_offsets[2] + 0x2519, dccg_regs[4].DP_DPHY_SYM1 = ctx->dcn_reg_offsets[2] + 0x251a, dccg_regs[4].DP_DPHY_SYM2 = ctx->dcn_reg_offsets[2] + 0x251b, dccg_regs[4].DP_DPHY_TRAINING_PATTERN_SEL = ctx->dcn_reg_offsets[2] + 0x2518, dccg_regs[4].DP_LINK_CNTL = ctx->dcn_reg_offsets[2] + 0x2508, dccg_regs[4].DP_LINK_FRAMING_CNTL = ctx->dcn_reg_offsets[2] + 0x2513, dccg_regs[4].DP_MSE_SAT0 = ctx->dcn_reg_offsets[2] + 0x253a, dccg_regs[4].DP_MSE_SAT1 = ctx->dcn_reg_offsets[2] + 0x253b, dccg_regs[4].DP_MSE_SAT2 = ctx->dcn_reg_offsets[2] + 0x253c, dccg_regs[4].DP_MSE_SAT_UPDATE = ctx->dcn_reg_offsets[2] + 0x253d, dccg_regs[4].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x252b, dccg_regs[4].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x250c, dccg_regs[4].DP_DPHY_FAST_TRAINING = ctx->dcn_reg_offsets[2] + 0x2524, dccg_regs[4].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x252c, dccg_regs[4].DP_DPHY_BS_SR_SWAP_CNTL = ctx->dcn_reg_offsets[2] + 0x2544, dccg_regs[4].DP_DPHY_HBR2_PATTERN_CONTROL = ctx->dcn_reg_offsets[2] + 0x2545 ), dccg_regs[4].DP_DPHY_INTERNAL_CTRL = ctx->dcn_reg_offsets[2] + 0x250f, dccg_regs[4].DIO_LINKA_CNTL = ctx->dcn_reg_offsets[2] + 0x1f04, dccg_regs[4].DIO_LINKB_CNTL = ctx->dcn_reg_offsets[2] + 0x1f05, dccg_regs[4].DIO_LINKC_CNTL = ctx->dcn_reg_offsets[2] + 0x1f06, dccg_regs[4].DIO_LINKD_CNTL = ctx->dcn_reg_offsets[2] + 0x1f07, dccg_regs[4].DIO_LINKE_CNTL = ctx->dcn_reg_offsets[2] + 0x1f08, dccg_regs[4].DIO_LINKF_CNTL = ctx->dcn_reg_offsets[2] + 0x1f09 ), ( dccg_regs[4].CLOCK_ENABLE = ctx->dcn_reg_offsets[1] + 0x00a4, dccg_regs[4].CHANNEL_XBAR_CNTL = ctx->dcn_reg_offsets[2] + 0x2876 ) ); |
1073 | |
1074 | dcn32_link_encoder_construct(enc20, |
1075 | enc_init_data, |
1076 | &link_enc_feature, |
1077 | &link_enc_regs[enc_init_data->transmitter], |
1078 | &link_enc_aux_regs[enc_init_data->channel - 1], |
1079 | &link_enc_hpd_regs[enc_init_data->hpd_source], |
1080 | &le_shift, |
1081 | &le_mask); |
1082 | |
1083 | return &enc20->enc10.base; |
1084 | } |
1085 | |
1086 | struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data) |
1087 | { |
1088 | struct dcn31_panel_cntl *panel_cntl = |
1089 | kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL(0x0001 | 0x0004)); |
1090 | |
1091 | if (!panel_cntl) |
1092 | return NULL((void *)0); |
1093 | |
1094 | dcn31_panel_cntl_construct(panel_cntl, init_data); |
1095 | |
1096 | return &panel_cntl->base; |
1097 | } |
1098 | |
1099 | static void read_dce_straps( |
1100 | struct dc_context *ctx, |
1101 | struct resource_straps *straps) |
1102 | { |
1103 | generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX2] + regDC_PINSTRAPS0x2880, |
1104 | FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO)0xe, 0x0000C000L, &straps->dc_pinstraps_audio); |
1105 | |
1106 | } |
1107 | |
1108 | static struct audio *dcn32_create_audio( |
1109 | struct dc_context *ctx, unsigned int inst) |
1110 | { |
1111 | |
1112 | #undef REG_STRUCTdccg_regs |
1113 | #define REG_STRUCTdccg_regs audio_regs |
1114 | audio_regs_init(0)( dccg_regs[0].AZALIA_F0_CODEC_ENDPOINT_INDEX = ctx->dcn_reg_offsets [2] + 0x0386, dccg_regs[0].AZALIA_F0_CODEC_ENDPOINT_DATA = ctx ->dcn_reg_offsets[2] + 0x0387, dccg_regs[0].AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = ctx->dcn_reg_offsets[2] + 0x040c, dccg_regs[0].AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = ctx->dcn_reg_offsets[2] + 0x040b, dccg_regs[0].AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = ctx->dcn_reg_offsets[2] + 0x040d, dccg_regs[0].DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs[0].DCCG_AUDIO_DTO0_MODULE = ctx->dcn_reg_offsets[1] + 0x00ad, dccg_regs[0].DCCG_AUDIO_DTO0_PHASE = ctx->dcn_reg_offsets[1] + 0x00ac, dccg_regs[0].DCCG_AUDIO_DTO1_MODULE = ctx->dcn_reg_offsets[1] + 0x00af, dccg_regs[0].DCCG_AUDIO_DTO1_PHASE = ctx->dcn_reg_offsets[1] + 0x00ae ), |
1115 | audio_regs_init(1)( dccg_regs[1].AZALIA_F0_CODEC_ENDPOINT_INDEX = ctx->dcn_reg_offsets [2] + 0x038c, dccg_regs[1].AZALIA_F0_CODEC_ENDPOINT_DATA = ctx ->dcn_reg_offsets[2] + 0x038d, dccg_regs[1].AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = ctx->dcn_reg_offsets[2] + 0x040c, dccg_regs[1].AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = ctx->dcn_reg_offsets[2] + 0x040b, dccg_regs[1].AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = ctx->dcn_reg_offsets[2] + 0x040d, dccg_regs[1].DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs[1].DCCG_AUDIO_DTO0_MODULE = ctx->dcn_reg_offsets[1] + 0x00ad, dccg_regs[1].DCCG_AUDIO_DTO0_PHASE = ctx->dcn_reg_offsets[1] + 0x00ac, dccg_regs[1].DCCG_AUDIO_DTO1_MODULE = ctx->dcn_reg_offsets[1] + 0x00af, dccg_regs[1].DCCG_AUDIO_DTO1_PHASE = ctx->dcn_reg_offsets[1] + 0x00ae ), |
1116 | audio_regs_init(2)( dccg_regs[2].AZALIA_F0_CODEC_ENDPOINT_INDEX = ctx->dcn_reg_offsets [2] + 0x0392, dccg_regs[2].AZALIA_F0_CODEC_ENDPOINT_DATA = ctx ->dcn_reg_offsets[2] + 0x0393, dccg_regs[2].AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = ctx->dcn_reg_offsets[2] + 0x040c, dccg_regs[2].AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = ctx->dcn_reg_offsets[2] + 0x040b, dccg_regs[2].AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = ctx->dcn_reg_offsets[2] + 0x040d, dccg_regs[2].DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs[2].DCCG_AUDIO_DTO0_MODULE = ctx->dcn_reg_offsets[1] + 0x00ad, dccg_regs[2].DCCG_AUDIO_DTO0_PHASE = ctx->dcn_reg_offsets[1] + 0x00ac, dccg_regs[2].DCCG_AUDIO_DTO1_MODULE = ctx->dcn_reg_offsets[1] + 0x00af, dccg_regs[2].DCCG_AUDIO_DTO1_PHASE = ctx->dcn_reg_offsets[1] + 0x00ae ), |
1117 | audio_regs_init(3)( dccg_regs[3].AZALIA_F0_CODEC_ENDPOINT_INDEX = ctx->dcn_reg_offsets [2] + 0x0398, dccg_regs[3].AZALIA_F0_CODEC_ENDPOINT_DATA = ctx ->dcn_reg_offsets[2] + 0x0399, dccg_regs[3].AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = ctx->dcn_reg_offsets[2] + 0x040c, dccg_regs[3].AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = ctx->dcn_reg_offsets[2] + 0x040b, dccg_regs[3].AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = ctx->dcn_reg_offsets[2] + 0x040d, dccg_regs[3].DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs[3].DCCG_AUDIO_DTO0_MODULE = ctx->dcn_reg_offsets[1] + 0x00ad, dccg_regs[3].DCCG_AUDIO_DTO0_PHASE = ctx->dcn_reg_offsets[1] + 0x00ac, dccg_regs[3].DCCG_AUDIO_DTO1_MODULE = ctx->dcn_reg_offsets[1] + 0x00af, dccg_regs[3].DCCG_AUDIO_DTO1_PHASE = ctx->dcn_reg_offsets[1] + 0x00ae ), |
1118 | audio_regs_init(4)( dccg_regs[4].AZALIA_F0_CODEC_ENDPOINT_INDEX = ctx->dcn_reg_offsets [2] + 0x039e, dccg_regs[4].AZALIA_F0_CODEC_ENDPOINT_DATA = ctx ->dcn_reg_offsets[2] + 0x039f, dccg_regs[4].AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = ctx->dcn_reg_offsets[2] + 0x040c, dccg_regs[4].AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = ctx->dcn_reg_offsets[2] + 0x040b, dccg_regs[4].AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = ctx->dcn_reg_offsets[2] + 0x040d, dccg_regs[4].DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs[4].DCCG_AUDIO_DTO0_MODULE = ctx->dcn_reg_offsets[1] + 0x00ad, dccg_regs[4].DCCG_AUDIO_DTO0_PHASE = ctx->dcn_reg_offsets[1] + 0x00ac, dccg_regs[4].DCCG_AUDIO_DTO1_MODULE = ctx->dcn_reg_offsets[1] + 0x00af, dccg_regs[4].DCCG_AUDIO_DTO1_PHASE = ctx->dcn_reg_offsets[1] + 0x00ae ); |
1119 | |
1120 | return dce_audio_create(ctx, inst, |
1121 | &audio_regs[inst], &audio_shift, &audio_mask); |
1122 | } |
1123 | |
1124 | static struct vpg *dcn32_vpg_create( |
1125 | struct dc_context *ctx, |
1126 | uint32_t inst) |
1127 | { |
1128 | struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL(0x0001 | 0x0004)); |
1129 | |
1130 | if (!vpg3) |
1131 | return NULL((void *)0); |
1132 | |
1133 | #undef REG_STRUCTdccg_regs |
1134 | #define REG_STRUCTdccg_regs vpg_regs |
1135 | vpg_regs_init(0)( dccg_regs[0].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x206c, dccg_regs[0].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x2068, dccg_regs[0].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x2069, dccg_regs[0].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x206a, dccg_regs[0].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x206b ), |
1136 | vpg_regs_init(1)( dccg_regs[1].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x216c, dccg_regs[1].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x2168, dccg_regs[1].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x2169, dccg_regs[1].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x216a, dccg_regs[1].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x216b ), |
1137 | vpg_regs_init(2)( dccg_regs[2].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x226c, dccg_regs[2].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x2268, dccg_regs[2].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x2269, dccg_regs[2].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x226a, dccg_regs[2].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x226b ), |
1138 | vpg_regs_init(3)( dccg_regs[3].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x236c, dccg_regs[3].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x2368, dccg_regs[3].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x2369, dccg_regs[3].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x236a, dccg_regs[3].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x236b ), |
1139 | vpg_regs_init(4)( dccg_regs[4].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x246c, dccg_regs[4].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x2468, dccg_regs[4].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x2469, dccg_regs[4].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x246a, dccg_regs[4].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x246b ), |
1140 | vpg_regs_init(5)( dccg_regs[5].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[3 ] + 0x0935, dccg_regs[5].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[3] + 0x0931, dccg_regs[5].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[3] + 0x0932, dccg_regs[5].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[3] + 0x0933, dccg_regs[5].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[3] + 0x0934 ), |
1141 | vpg_regs_init(6)( dccg_regs[6].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x3655, dccg_regs[6].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x3651, dccg_regs[6].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x3652, dccg_regs[6].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x3653, dccg_regs[6].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x3654 ), |
1142 | vpg_regs_init(7)( dccg_regs[7].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x3729, dccg_regs[7].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x3725, dccg_regs[7].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x3726, dccg_regs[7].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x3727, dccg_regs[7].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x3728 ), |
1143 | vpg_regs_init(8)( dccg_regs[8].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x37fd, dccg_regs[8].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x37f9, dccg_regs[8].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x37fa, dccg_regs[8].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x37fb, dccg_regs[8].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x37fc ), |
1144 | vpg_regs_init(9)( dccg_regs[9].VPG_GENERIC_STATUS = ctx->dcn_reg_offsets[2 ] + 0x38d1, dccg_regs[9].VPG_GENERIC_PACKET_ACCESS_CTRL = ctx ->dcn_reg_offsets[2] + 0x38cd, dccg_regs[9].VPG_GENERIC_PACKET_DATA = ctx->dcn_reg_offsets[2] + 0x38ce, dccg_regs[9].VPG_GSP_FRAME_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x38cf, dccg_regs[9].VPG_GSP_IMMEDIATE_UPDATE_CTRL = ctx->dcn_reg_offsets[2] + 0x38d0 ); |
1145 | |
1146 | vpg3_construct(vpg3, ctx, inst, |
1147 | &vpg_regs[inst], |
1148 | &vpg_shift, |
1149 | &vpg_mask); |
1150 | |
1151 | return &vpg3->base; |
1152 | } |
1153 | |
1154 | static struct afmt *dcn32_afmt_create( |
1155 | struct dc_context *ctx, |
1156 | uint32_t inst) |
1157 | { |
1158 | struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL(0x0001 | 0x0004)); |
1159 | |
1160 | if (!afmt3) |
1161 | return NULL((void *)0); |
1162 | |
1163 | #undef REG_STRUCTdccg_regs |
1164 | #define REG_STRUCTdccg_regs afmt_regs |
1165 | afmt_regs_init(0)( dccg_regs[0].AFMT_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x2083, dccg_regs[0].AFMT_VBI_PACKET_CONTROL = ctx-> dcn_reg_offsets[2] + 0x2074, dccg_regs[0].AFMT_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2082, dccg_regs[0].AFMT_AUDIO_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x2075, dccg_regs[0].AFMT_AUDIO_SRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x2085, dccg_regs[0].AFMT_60958_0 = ctx->dcn_reg_offsets[2] + 0x2078, dccg_regs[0].AFMT_60958_1 = ctx->dcn_reg_offsets[2] + 0x2079, dccg_regs[0].AFMT_60958_2 = ctx->dcn_reg_offsets[2] + 0x207f, dccg_regs[0].AFMT_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x2087 ), |
1166 | afmt_regs_init(1)( dccg_regs[1].AFMT_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x2183, dccg_regs[1].AFMT_VBI_PACKET_CONTROL = ctx-> dcn_reg_offsets[2] + 0x2174, dccg_regs[1].AFMT_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2182, dccg_regs[1].AFMT_AUDIO_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x2175, dccg_regs[1].AFMT_AUDIO_SRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x2185, dccg_regs[1].AFMT_60958_0 = ctx->dcn_reg_offsets[2] + 0x2178, dccg_regs[1].AFMT_60958_1 = ctx->dcn_reg_offsets[2] + 0x2179, dccg_regs[1].AFMT_60958_2 = ctx->dcn_reg_offsets[2] + 0x217f, dccg_regs[1].AFMT_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x2187 ), |
1167 | afmt_regs_init(2)( dccg_regs[2].AFMT_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x2283, dccg_regs[2].AFMT_VBI_PACKET_CONTROL = ctx-> dcn_reg_offsets[2] + 0x2274, dccg_regs[2].AFMT_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2282, dccg_regs[2].AFMT_AUDIO_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x2275, dccg_regs[2].AFMT_AUDIO_SRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x2285, dccg_regs[2].AFMT_60958_0 = ctx->dcn_reg_offsets[2] + 0x2278, dccg_regs[2].AFMT_60958_1 = ctx->dcn_reg_offsets[2] + 0x2279, dccg_regs[2].AFMT_60958_2 = ctx->dcn_reg_offsets[2] + 0x227f, dccg_regs[2].AFMT_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x2287 ), |
1168 | afmt_regs_init(3)( dccg_regs[3].AFMT_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x2383, dccg_regs[3].AFMT_VBI_PACKET_CONTROL = ctx-> dcn_reg_offsets[2] + 0x2374, dccg_regs[3].AFMT_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2382, dccg_regs[3].AFMT_AUDIO_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x2375, dccg_regs[3].AFMT_AUDIO_SRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x2385, dccg_regs[3].AFMT_60958_0 = ctx->dcn_reg_offsets[2] + 0x2378, dccg_regs[3].AFMT_60958_1 = ctx->dcn_reg_offsets[2] + 0x2379, dccg_regs[3].AFMT_60958_2 = ctx->dcn_reg_offsets[2] + 0x237f, dccg_regs[3].AFMT_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x2387 ), |
1169 | afmt_regs_init(4)( dccg_regs[4].AFMT_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x2483, dccg_regs[4].AFMT_VBI_PACKET_CONTROL = ctx-> dcn_reg_offsets[2] + 0x2474, dccg_regs[4].AFMT_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2482, dccg_regs[4].AFMT_AUDIO_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x2475, dccg_regs[4].AFMT_AUDIO_SRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x2485, dccg_regs[4].AFMT_60958_0 = ctx->dcn_reg_offsets[2] + 0x2478, dccg_regs[4].AFMT_60958_1 = ctx->dcn_reg_offsets[2] + 0x2479, dccg_regs[4].AFMT_60958_2 = ctx->dcn_reg_offsets[2] + 0x247f, dccg_regs[4].AFMT_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x2487 ), |
1170 | afmt_regs_init(5)( dccg_regs[5].AFMT_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets [3] + 0x092b, dccg_regs[5].AFMT_VBI_PACKET_CONTROL = ctx-> dcn_reg_offsets[3] + 0x091c, dccg_regs[5].AFMT_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[3] + 0x092a, dccg_regs[5].AFMT_AUDIO_PACKET_CONTROL2 = ctx->dcn_reg_offsets[3] + 0x091d, dccg_regs[5].AFMT_AUDIO_SRC_CONTROL = ctx->dcn_reg_offsets[3] + 0x092d, dccg_regs[5].AFMT_60958_0 = ctx->dcn_reg_offsets[3] + 0x0920, dccg_regs[5].AFMT_60958_1 = ctx->dcn_reg_offsets[3] + 0x0921, dccg_regs[5].AFMT_60958_2 = ctx->dcn_reg_offsets[3] + 0x0927, dccg_regs[5].AFMT_MEM_PWR = ctx->dcn_reg_offsets[3] + 0x092f ); |
1171 | |
1172 | afmt3_construct(afmt3, ctx, inst, |
1173 | &afmt_regs[inst], |
1174 | &afmt_shift, |
1175 | &afmt_mask); |
1176 | |
1177 | return &afmt3->base; |
1178 | } |
1179 | |
1180 | static struct apg *dcn31_apg_create( |
1181 | struct dc_context *ctx, |
1182 | uint32_t inst) |
1183 | { |
1184 | struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL(0x0001 | 0x0004)); |
1185 | |
1186 | if (!apg31) |
1187 | return NULL((void *)0); |
1188 | |
1189 | #undef REG_STRUCTdccg_regs |
1190 | #define REG_STRUCTdccg_regs apg_regs |
1191 | apg_regs_init(0)( dccg_regs[0].APG_CONTROL = ctx->dcn_reg_offsets[2] + 0x3630 , dccg_regs[0].APG_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x3631 , dccg_regs[0].APG_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x3644 , dccg_regs[0].APG_DBG_GEN_CONTROL = ctx->dcn_reg_offsets[ 2] + 0x3632 ), |
1192 | apg_regs_init(1)( dccg_regs[1].APG_CONTROL = ctx->dcn_reg_offsets[2] + 0x3704 , dccg_regs[1].APG_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x3705 , dccg_regs[1].APG_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x3718 , dccg_regs[1].APG_DBG_GEN_CONTROL = ctx->dcn_reg_offsets[ 2] + 0x3706 ), |
1193 | apg_regs_init(2)( dccg_regs[2].APG_CONTROL = ctx->dcn_reg_offsets[2] + 0x37d8 , dccg_regs[2].APG_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x37d9 , dccg_regs[2].APG_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x37ec , dccg_regs[2].APG_DBG_GEN_CONTROL = ctx->dcn_reg_offsets[ 2] + 0x37da ), |
1194 | apg_regs_init(3)( dccg_regs[3].APG_CONTROL = ctx->dcn_reg_offsets[2] + 0x38ac , dccg_regs[3].APG_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x38ad , dccg_regs[3].APG_MEM_PWR = ctx->dcn_reg_offsets[2] + 0x38c0 , dccg_regs[3].APG_DBG_GEN_CONTROL = ctx->dcn_reg_offsets[ 2] + 0x38ae ); |
1195 | |
1196 | apg31_construct(apg31, ctx, inst, |
1197 | &apg_regs[inst], |
1198 | &apg_shift, |
1199 | &apg_mask); |
1200 | |
1201 | return &apg31->base; |
1202 | } |
1203 | |
1204 | static struct stream_encoder *dcn32_stream_encoder_create( |
1205 | enum engine_id eng_id, |
1206 | struct dc_context *ctx) |
1207 | { |
1208 | struct dcn10_stream_encoder *enc1; |
1209 | struct vpg *vpg; |
1210 | struct afmt *afmt; |
1211 | int vpg_inst; |
1212 | int afmt_inst; |
1213 | |
1214 | /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ |
1215 | if (eng_id <= ENGINE_ID_DIGF) { |
1216 | vpg_inst = eng_id; |
1217 | afmt_inst = eng_id; |
1218 | } else |
1219 | return NULL((void *)0); |
1220 | |
1221 | enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL(0x0001 | 0x0004)); |
1222 | vpg = dcn32_vpg_create(ctx, vpg_inst); |
1223 | afmt = dcn32_afmt_create(ctx, afmt_inst); |
1224 | |
1225 | if (!enc1 || !vpg || !afmt) { |
1226 | kfree(enc1); |
1227 | kfree(vpg); |
1228 | kfree(afmt); |
1229 | return NULL((void *)0); |
1230 | } |
1231 | |
1232 | #undef REG_STRUCTdccg_regs |
1233 | #define REG_STRUCTdccg_regs stream_enc_regs |
1234 | stream_enc_regs_init(0)( dccg_regs[0].AFMT_CNTL = ctx->dcn_reg_offsets[2] + 0x20b0 , dccg_regs[0].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x208b , dccg_regs[0].HDMI_CONTROL = ctx->dcn_reg_offsets[2] + 0x2094 , dccg_regs[0].HDMI_DB_CONTROL = ctx->dcn_reg_offsets[2] + 0x20a7, dccg_regs[0].HDMI_GC = ctx->dcn_reg_offsets[2] + 0x209e , dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x209b, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL1 = ctx ->dcn_reg_offsets[2] + 0x209f, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x20a0, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x20a1, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL4 = ctx->dcn_reg_offsets[2] + 0x20a2, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x209d, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL6 = ctx->dcn_reg_offsets[2] + 0x209c, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL7 = ctx->dcn_reg_offsets[2] + 0x20a3, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL8 = ctx->dcn_reg_offsets[2] + 0x20a4, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL9 = ctx->dcn_reg_offsets[2] + 0x20a5, dccg_regs[0].HDMI_GENERIC_PACKET_CONTROL10 = ctx->dcn_reg_offsets[2] + 0x20a6, dccg_regs[0].HDMI_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x2099, dccg_regs[0].HDMI_INFOFRAME_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x209a, dccg_regs[0].HDMI_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2098, dccg_regs[0].HDMI_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2096, dccg_regs[0].HDMI_ACR_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2097, dccg_regs[0].HDMI_ACR_32_0 = ctx->dcn_reg_offsets[2] + 0x20a8, dccg_regs[0].HDMI_ACR_32_1 = ctx->dcn_reg_offsets[2] + 0x20a9, dccg_regs[0].HDMI_ACR_44_0 = ctx->dcn_reg_offsets[2] + 0x20aa, dccg_regs[0].HDMI_ACR_44_1 = ctx->dcn_reg_offsets[2] + 0x20ab, dccg_regs[0].HDMI_ACR_48_0 = ctx->dcn_reg_offsets[2] + 0x20ac, dccg_regs[0].HDMI_ACR_48_1 = ctx->dcn_reg_offsets[2] + 0x20ad, dccg_regs[0].DP_DB_CNTL = ctx->dcn_reg_offsets[2] + 0x2159, dccg_regs[0].DP_MSA_MISC = ctx->dcn_reg_offsets[2] + 0x210e, dccg_regs[0].DP_MSA_VBID_MISC = ctx->dcn_reg_offsets[2] + 0x215a, dccg_regs[0].DP_MSA_COLORIMETRY = ctx->dcn_reg_offsets[2] + 0x210a, dccg_regs[0].DP_MSA_TIMING_PARAM1 = ctx->dcn_reg_offsets[2] + 0x214c, dccg_regs[0].DP_MSA_TIMING_PARAM2 = ctx->dcn_reg_offsets[2] + 0x214d, dccg_regs[0].DP_MSA_TIMING_PARAM3 = ctx->dcn_reg_offsets[2] + 0x214e, dccg_regs[0].DP_MSA_TIMING_PARAM4 = ctx->dcn_reg_offsets[2] + 0x214f, dccg_regs[0].DP_MSE_RATE_CNTL = ctx->dcn_reg_offsets[2] + 0x2137, dccg_regs[0].DP_MSE_RATE_UPDATE = ctx->dcn_reg_offsets[2] + 0x2139, dccg_regs[0].DP_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x2109, dccg_regs[0].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x212b, dccg_regs[0].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x212c, dccg_regs[0].DP_SEC_CNTL2 = ctx->dcn_reg_offsets[2] + 0x2153, dccg_regs[0].DP_SEC_CNTL5 = ctx->dcn_reg_offsets[2] + 0x2156, dccg_regs[0].DP_SEC_CNTL6 = ctx->dcn_reg_offsets[2] + 0x2157, dccg_regs[0].DP_STEER_FIFO = ctx->dcn_reg_offsets[2] + 0x210d, dccg_regs[0].DP_VID_M = ctx->dcn_reg_offsets[2] + 0x2112, dccg_regs[0].DP_VID_N = ctx->dcn_reg_offsets[2] + 0x2111, dccg_regs[0].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x210c, dccg_regs[0].DP_VID_TIMING = ctx->dcn_reg_offsets[2] + 0x2110, dccg_regs[0].DP_SEC_AUD_N = ctx->dcn_reg_offsets[2] + 0x2131, dccg_regs[0].DP_SEC_TIMESTAMP = ctx->dcn_reg_offsets[2] + 0x2135, dccg_regs[0].DP_DSC_CNTL = ctx->dcn_reg_offsets[2] + 0x2152, dccg_regs[0].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x215b, dccg_regs[0].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2093, dccg_regs[0].DP_SEC_FRAMING4 = ctx->dcn_reg_offsets[2] + 0x2130, dccg_regs[0].DP_GSP11_CNTL = ctx->dcn_reg_offsets[2] + 0x2161, dccg_regs[0].DME_CONTROL = ctx->dcn_reg_offsets[2] + 0x2089, dccg_regs[0].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x215b, dccg_regs[0].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2093, dccg_regs[0].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x208b, dccg_regs[0].DIG_CLOCK_PATTERN = ctx->dcn_reg_offsets[2] + 0x208e, dccg_regs[0].DIG_FIFO_CTRL0 = ctx->dcn_reg_offsets[2] + 0x2091 ), |
1235 | stream_enc_regs_init(1)( dccg_regs[1].AFMT_CNTL = ctx->dcn_reg_offsets[2] + 0x21b0 , dccg_regs[1].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x218b , dccg_regs[1].HDMI_CONTROL = ctx->dcn_reg_offsets[2] + 0x2194 , dccg_regs[1].HDMI_DB_CONTROL = ctx->dcn_reg_offsets[2] + 0x21a7, dccg_regs[1].HDMI_GC = ctx->dcn_reg_offsets[2] + 0x219e , dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x219b, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL1 = ctx ->dcn_reg_offsets[2] + 0x219f, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x21a0, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x21a1, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL4 = ctx->dcn_reg_offsets[2] + 0x21a2, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x219d, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL6 = ctx->dcn_reg_offsets[2] + 0x219c, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL7 = ctx->dcn_reg_offsets[2] + 0x21a3, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL8 = ctx->dcn_reg_offsets[2] + 0x21a4, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL9 = ctx->dcn_reg_offsets[2] + 0x21a5, dccg_regs[1].HDMI_GENERIC_PACKET_CONTROL10 = ctx->dcn_reg_offsets[2] + 0x21a6, dccg_regs[1].HDMI_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x2199, dccg_regs[1].HDMI_INFOFRAME_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x219a, dccg_regs[1].HDMI_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2198, dccg_regs[1].HDMI_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2196, dccg_regs[1].HDMI_ACR_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2197, dccg_regs[1].HDMI_ACR_32_0 = ctx->dcn_reg_offsets[2] + 0x21a8, dccg_regs[1].HDMI_ACR_32_1 = ctx->dcn_reg_offsets[2] + 0x21a9, dccg_regs[1].HDMI_ACR_44_0 = ctx->dcn_reg_offsets[2] + 0x21aa, dccg_regs[1].HDMI_ACR_44_1 = ctx->dcn_reg_offsets[2] + 0x21ab, dccg_regs[1].HDMI_ACR_48_0 = ctx->dcn_reg_offsets[2] + 0x21ac, dccg_regs[1].HDMI_ACR_48_1 = ctx->dcn_reg_offsets[2] + 0x21ad, dccg_regs[1].DP_DB_CNTL = ctx->dcn_reg_offsets[2] + 0x2259, dccg_regs[1].DP_MSA_MISC = ctx->dcn_reg_offsets[2] + 0x220e, dccg_regs[1].DP_MSA_VBID_MISC = ctx->dcn_reg_offsets[2] + 0x225a, dccg_regs[1].DP_MSA_COLORIMETRY = ctx->dcn_reg_offsets[2] + 0x220a, dccg_regs[1].DP_MSA_TIMING_PARAM1 = ctx->dcn_reg_offsets[2] + 0x224c, dccg_regs[1].DP_MSA_TIMING_PARAM2 = ctx->dcn_reg_offsets[2] + 0x224d, dccg_regs[1].DP_MSA_TIMING_PARAM3 = ctx->dcn_reg_offsets[2] + 0x224e, dccg_regs[1].DP_MSA_TIMING_PARAM4 = ctx->dcn_reg_offsets[2] + 0x224f, dccg_regs[1].DP_MSE_RATE_CNTL = ctx->dcn_reg_offsets[2] + 0x2237, dccg_regs[1].DP_MSE_RATE_UPDATE = ctx->dcn_reg_offsets[2] + 0x2239, dccg_regs[1].DP_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x2209, dccg_regs[1].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x222b, dccg_regs[1].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x222c, dccg_regs[1].DP_SEC_CNTL2 = ctx->dcn_reg_offsets[2] + 0x2253, dccg_regs[1].DP_SEC_CNTL5 = ctx->dcn_reg_offsets[2] + 0x2256, dccg_regs[1].DP_SEC_CNTL6 = ctx->dcn_reg_offsets[2] + 0x2257, dccg_regs[1].DP_STEER_FIFO = ctx->dcn_reg_offsets[2] + 0x220d, dccg_regs[1].DP_VID_M = ctx->dcn_reg_offsets[2] + 0x2212, dccg_regs[1].DP_VID_N = ctx->dcn_reg_offsets[2] + 0x2211, dccg_regs[1].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x220c, dccg_regs[1].DP_VID_TIMING = ctx->dcn_reg_offsets[2] + 0x2210, dccg_regs[1].DP_SEC_AUD_N = ctx->dcn_reg_offsets[2] + 0x2231, dccg_regs[1].DP_SEC_TIMESTAMP = ctx->dcn_reg_offsets[2] + 0x2235, dccg_regs[1].DP_DSC_CNTL = ctx->dcn_reg_offsets[2] + 0x2252, dccg_regs[1].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x225b, dccg_regs[1].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2193, dccg_regs[1].DP_SEC_FRAMING4 = ctx->dcn_reg_offsets[2] + 0x2230, dccg_regs[1].DP_GSP11_CNTL = ctx->dcn_reg_offsets[2] + 0x2261, dccg_regs[1].DME_CONTROL = ctx->dcn_reg_offsets[2] + 0x2189, dccg_regs[1].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x225b, dccg_regs[1].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2193, dccg_regs[1].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x218b, dccg_regs[1].DIG_CLOCK_PATTERN = ctx->dcn_reg_offsets[2] + 0x218e, dccg_regs[1].DIG_FIFO_CTRL0 = ctx->dcn_reg_offsets[2] + 0x2191 ), |
1236 | stream_enc_regs_init(2)( dccg_regs[2].AFMT_CNTL = ctx->dcn_reg_offsets[2] + 0x22b0 , dccg_regs[2].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x228b , dccg_regs[2].HDMI_CONTROL = ctx->dcn_reg_offsets[2] + 0x2294 , dccg_regs[2].HDMI_DB_CONTROL = ctx->dcn_reg_offsets[2] + 0x22a7, dccg_regs[2].HDMI_GC = ctx->dcn_reg_offsets[2] + 0x229e , dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x229b, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL1 = ctx ->dcn_reg_offsets[2] + 0x229f, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x22a0, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x22a1, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL4 = ctx->dcn_reg_offsets[2] + 0x22a2, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x229d, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL6 = ctx->dcn_reg_offsets[2] + 0x229c, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL7 = ctx->dcn_reg_offsets[2] + 0x22a3, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL8 = ctx->dcn_reg_offsets[2] + 0x22a4, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL9 = ctx->dcn_reg_offsets[2] + 0x22a5, dccg_regs[2].HDMI_GENERIC_PACKET_CONTROL10 = ctx->dcn_reg_offsets[2] + 0x22a6, dccg_regs[2].HDMI_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x2299, dccg_regs[2].HDMI_INFOFRAME_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x229a, dccg_regs[2].HDMI_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2298, dccg_regs[2].HDMI_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2296, dccg_regs[2].HDMI_ACR_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2297, dccg_regs[2].HDMI_ACR_32_0 = ctx->dcn_reg_offsets[2] + 0x22a8, dccg_regs[2].HDMI_ACR_32_1 = ctx->dcn_reg_offsets[2] + 0x22a9, dccg_regs[2].HDMI_ACR_44_0 = ctx->dcn_reg_offsets[2] + 0x22aa, dccg_regs[2].HDMI_ACR_44_1 = ctx->dcn_reg_offsets[2] + 0x22ab, dccg_regs[2].HDMI_ACR_48_0 = ctx->dcn_reg_offsets[2] + 0x22ac, dccg_regs[2].HDMI_ACR_48_1 = ctx->dcn_reg_offsets[2] + 0x22ad, dccg_regs[2].DP_DB_CNTL = ctx->dcn_reg_offsets[2] + 0x2359, dccg_regs[2].DP_MSA_MISC = ctx->dcn_reg_offsets[2] + 0x230e, dccg_regs[2].DP_MSA_VBID_MISC = ctx->dcn_reg_offsets[2] + 0x235a, dccg_regs[2].DP_MSA_COLORIMETRY = ctx->dcn_reg_offsets[2] + 0x230a, dccg_regs[2].DP_MSA_TIMING_PARAM1 = ctx->dcn_reg_offsets[2] + 0x234c, dccg_regs[2].DP_MSA_TIMING_PARAM2 = ctx->dcn_reg_offsets[2] + 0x234d, dccg_regs[2].DP_MSA_TIMING_PARAM3 = ctx->dcn_reg_offsets[2] + 0x234e, dccg_regs[2].DP_MSA_TIMING_PARAM4 = ctx->dcn_reg_offsets[2] + 0x234f, dccg_regs[2].DP_MSE_RATE_CNTL = ctx->dcn_reg_offsets[2] + 0x2337, dccg_regs[2].DP_MSE_RATE_UPDATE = ctx->dcn_reg_offsets[2] + 0x2339, dccg_regs[2].DP_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x2309, dccg_regs[2].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x232b, dccg_regs[2].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x232c, dccg_regs[2].DP_SEC_CNTL2 = ctx->dcn_reg_offsets[2] + 0x2353, dccg_regs[2].DP_SEC_CNTL5 = ctx->dcn_reg_offsets[2] + 0x2356, dccg_regs[2].DP_SEC_CNTL6 = ctx->dcn_reg_offsets[2] + 0x2357, dccg_regs[2].DP_STEER_FIFO = ctx->dcn_reg_offsets[2] + 0x230d, dccg_regs[2].DP_VID_M = ctx->dcn_reg_offsets[2] + 0x2312, dccg_regs[2].DP_VID_N = ctx->dcn_reg_offsets[2] + 0x2311, dccg_regs[2].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x230c, dccg_regs[2].DP_VID_TIMING = ctx->dcn_reg_offsets[2] + 0x2310, dccg_regs[2].DP_SEC_AUD_N = ctx->dcn_reg_offsets[2] + 0x2331, dccg_regs[2].DP_SEC_TIMESTAMP = ctx->dcn_reg_offsets[2] + 0x2335, dccg_regs[2].DP_DSC_CNTL = ctx->dcn_reg_offsets[2] + 0x2352, dccg_regs[2].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x235b, dccg_regs[2].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2293, dccg_regs[2].DP_SEC_FRAMING4 = ctx->dcn_reg_offsets[2] + 0x2330, dccg_regs[2].DP_GSP11_CNTL = ctx->dcn_reg_offsets[2] + 0x2361, dccg_regs[2].DME_CONTROL = ctx->dcn_reg_offsets[2] + 0x2289, dccg_regs[2].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x235b, dccg_regs[2].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2293, dccg_regs[2].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x228b, dccg_regs[2].DIG_CLOCK_PATTERN = ctx->dcn_reg_offsets[2] + 0x228e, dccg_regs[2].DIG_FIFO_CTRL0 = ctx->dcn_reg_offsets[2] + 0x2291 ), |
1237 | stream_enc_regs_init(3)( dccg_regs[3].AFMT_CNTL = ctx->dcn_reg_offsets[2] + 0x23b0 , dccg_regs[3].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x238b , dccg_regs[3].HDMI_CONTROL = ctx->dcn_reg_offsets[2] + 0x2394 , dccg_regs[3].HDMI_DB_CONTROL = ctx->dcn_reg_offsets[2] + 0x23a7, dccg_regs[3].HDMI_GC = ctx->dcn_reg_offsets[2] + 0x239e , dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x239b, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL1 = ctx ->dcn_reg_offsets[2] + 0x239f, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x23a0, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x23a1, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL4 = ctx->dcn_reg_offsets[2] + 0x23a2, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x239d, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL6 = ctx->dcn_reg_offsets[2] + 0x239c, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL7 = ctx->dcn_reg_offsets[2] + 0x23a3, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL8 = ctx->dcn_reg_offsets[2] + 0x23a4, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL9 = ctx->dcn_reg_offsets[2] + 0x23a5, dccg_regs[3].HDMI_GENERIC_PACKET_CONTROL10 = ctx->dcn_reg_offsets[2] + 0x23a6, dccg_regs[3].HDMI_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x2399, dccg_regs[3].HDMI_INFOFRAME_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x239a, dccg_regs[3].HDMI_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2398, dccg_regs[3].HDMI_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2396, dccg_regs[3].HDMI_ACR_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2397, dccg_regs[3].HDMI_ACR_32_0 = ctx->dcn_reg_offsets[2] + 0x23a8, dccg_regs[3].HDMI_ACR_32_1 = ctx->dcn_reg_offsets[2] + 0x23a9, dccg_regs[3].HDMI_ACR_44_0 = ctx->dcn_reg_offsets[2] + 0x23aa, dccg_regs[3].HDMI_ACR_44_1 = ctx->dcn_reg_offsets[2] + 0x23ab, dccg_regs[3].HDMI_ACR_48_0 = ctx->dcn_reg_offsets[2] + 0x23ac, dccg_regs[3].HDMI_ACR_48_1 = ctx->dcn_reg_offsets[2] + 0x23ad, dccg_regs[3].DP_DB_CNTL = ctx->dcn_reg_offsets[2] + 0x2459, dccg_regs[3].DP_MSA_MISC = ctx->dcn_reg_offsets[2] + 0x240e, dccg_regs[3].DP_MSA_VBID_MISC = ctx->dcn_reg_offsets[2] + 0x245a, dccg_regs[3].DP_MSA_COLORIMETRY = ctx->dcn_reg_offsets[2] + 0x240a, dccg_regs[3].DP_MSA_TIMING_PARAM1 = ctx->dcn_reg_offsets[2] + 0x244c, dccg_regs[3].DP_MSA_TIMING_PARAM2 = ctx->dcn_reg_offsets[2] + 0x244d, dccg_regs[3].DP_MSA_TIMING_PARAM3 = ctx->dcn_reg_offsets[2] + 0x244e, dccg_regs[3].DP_MSA_TIMING_PARAM4 = ctx->dcn_reg_offsets[2] + 0x244f, dccg_regs[3].DP_MSE_RATE_CNTL = ctx->dcn_reg_offsets[2] + 0x2437, dccg_regs[3].DP_MSE_RATE_UPDATE = ctx->dcn_reg_offsets[2] + 0x2439, dccg_regs[3].DP_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x2409, dccg_regs[3].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x242b, dccg_regs[3].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x242c, dccg_regs[3].DP_SEC_CNTL2 = ctx->dcn_reg_offsets[2] + 0x2453, dccg_regs[3].DP_SEC_CNTL5 = ctx->dcn_reg_offsets[2] + 0x2456, dccg_regs[3].DP_SEC_CNTL6 = ctx->dcn_reg_offsets[2] + 0x2457, dccg_regs[3].DP_STEER_FIFO = ctx->dcn_reg_offsets[2] + 0x240d, dccg_regs[3].DP_VID_M = ctx->dcn_reg_offsets[2] + 0x2412, dccg_regs[3].DP_VID_N = ctx->dcn_reg_offsets[2] + 0x2411, dccg_regs[3].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x240c, dccg_regs[3].DP_VID_TIMING = ctx->dcn_reg_offsets[2] + 0x2410, dccg_regs[3].DP_SEC_AUD_N = ctx->dcn_reg_offsets[2] + 0x2431, dccg_regs[3].DP_SEC_TIMESTAMP = ctx->dcn_reg_offsets[2] + 0x2435, dccg_regs[3].DP_DSC_CNTL = ctx->dcn_reg_offsets[2] + 0x2452, dccg_regs[3].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x245b, dccg_regs[3].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2393, dccg_regs[3].DP_SEC_FRAMING4 = ctx->dcn_reg_offsets[2] + 0x2430, dccg_regs[3].DP_GSP11_CNTL = ctx->dcn_reg_offsets[2] + 0x2461, dccg_regs[3].DME_CONTROL = ctx->dcn_reg_offsets[2] + 0x2389, dccg_regs[3].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x245b, dccg_regs[3].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2393, dccg_regs[3].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x238b, dccg_regs[3].DIG_CLOCK_PATTERN = ctx->dcn_reg_offsets[2] + 0x238e, dccg_regs[3].DIG_FIFO_CTRL0 = ctx->dcn_reg_offsets[2] + 0x2391 ), |
1238 | stream_enc_regs_init(4)( dccg_regs[4].AFMT_CNTL = ctx->dcn_reg_offsets[2] + 0x24b0 , dccg_regs[4].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x248b , dccg_regs[4].HDMI_CONTROL = ctx->dcn_reg_offsets[2] + 0x2494 , dccg_regs[4].HDMI_DB_CONTROL = ctx->dcn_reg_offsets[2] + 0x24a7, dccg_regs[4].HDMI_GC = ctx->dcn_reg_offsets[2] + 0x249e , dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL0 = ctx->dcn_reg_offsets [2] + 0x249b, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL1 = ctx ->dcn_reg_offsets[2] + 0x249f, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x24a0, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x24a1, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL4 = ctx->dcn_reg_offsets[2] + 0x24a2, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x249d, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL6 = ctx->dcn_reg_offsets[2] + 0x249c, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL7 = ctx->dcn_reg_offsets[2] + 0x24a3, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL8 = ctx->dcn_reg_offsets[2] + 0x24a4, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL9 = ctx->dcn_reg_offsets[2] + 0x24a5, dccg_regs[4].HDMI_GENERIC_PACKET_CONTROL10 = ctx->dcn_reg_offsets[2] + 0x24a6, dccg_regs[4].HDMI_INFOFRAME_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x2499, dccg_regs[4].HDMI_INFOFRAME_CONTROL1 = ctx->dcn_reg_offsets[2] + 0x249a, dccg_regs[4].HDMI_VBI_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2498, dccg_regs[4].HDMI_AUDIO_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2496, dccg_regs[4].HDMI_ACR_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2497, dccg_regs[4].HDMI_ACR_32_0 = ctx->dcn_reg_offsets[2] + 0x24a8, dccg_regs[4].HDMI_ACR_32_1 = ctx->dcn_reg_offsets[2] + 0x24a9, dccg_regs[4].HDMI_ACR_44_0 = ctx->dcn_reg_offsets[2] + 0x24aa, dccg_regs[4].HDMI_ACR_44_1 = ctx->dcn_reg_offsets[2] + 0x24ab, dccg_regs[4].HDMI_ACR_48_0 = ctx->dcn_reg_offsets[2] + 0x24ac, dccg_regs[4].HDMI_ACR_48_1 = ctx->dcn_reg_offsets[2] + 0x24ad, dccg_regs[4].DP_DB_CNTL = ctx->dcn_reg_offsets[2] + 0x2559, dccg_regs[4].DP_MSA_MISC = ctx->dcn_reg_offsets[2] + 0x250e, dccg_regs[4].DP_MSA_VBID_MISC = ctx->dcn_reg_offsets[2] + 0x255a, dccg_regs[4].DP_MSA_COLORIMETRY = ctx->dcn_reg_offsets[2] + 0x250a, dccg_regs[4].DP_MSA_TIMING_PARAM1 = ctx->dcn_reg_offsets[2] + 0x254c, dccg_regs[4].DP_MSA_TIMING_PARAM2 = ctx->dcn_reg_offsets[2] + 0x254d, dccg_regs[4].DP_MSA_TIMING_PARAM3 = ctx->dcn_reg_offsets[2] + 0x254e, dccg_regs[4].DP_MSA_TIMING_PARAM4 = ctx->dcn_reg_offsets[2] + 0x254f, dccg_regs[4].DP_MSE_RATE_CNTL = ctx->dcn_reg_offsets[2] + 0x2537, dccg_regs[4].DP_MSE_RATE_UPDATE = ctx->dcn_reg_offsets[2] + 0x2539, dccg_regs[4].DP_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x2509, dccg_regs[4].DP_SEC_CNTL = ctx->dcn_reg_offsets[2] + 0x252b, dccg_regs[4].DP_SEC_CNTL1 = ctx->dcn_reg_offsets[2] + 0x252c, dccg_regs[4].DP_SEC_CNTL2 = ctx->dcn_reg_offsets[2] + 0x2553, dccg_regs[4].DP_SEC_CNTL5 = ctx->dcn_reg_offsets[2] + 0x2556, dccg_regs[4].DP_SEC_CNTL6 = ctx->dcn_reg_offsets[2] + 0x2557, dccg_regs[4].DP_STEER_FIFO = ctx->dcn_reg_offsets[2] + 0x250d, dccg_regs[4].DP_VID_M = ctx->dcn_reg_offsets[2] + 0x2512, dccg_regs[4].DP_VID_N = ctx->dcn_reg_offsets[2] + 0x2511, dccg_regs[4].DP_VID_STREAM_CNTL = ctx->dcn_reg_offsets[2] + 0x250c, dccg_regs[4].DP_VID_TIMING = ctx->dcn_reg_offsets[2] + 0x2510, dccg_regs[4].DP_SEC_AUD_N = ctx->dcn_reg_offsets[2] + 0x2531, dccg_regs[4].DP_SEC_TIMESTAMP = ctx->dcn_reg_offsets[2] + 0x2535, dccg_regs[4].DP_DSC_CNTL = ctx->dcn_reg_offsets[2] + 0x2552, dccg_regs[4].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x255b, dccg_regs[4].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2493, dccg_regs[4].DP_SEC_FRAMING4 = ctx->dcn_reg_offsets[2] + 0x2530, dccg_regs[4].DP_GSP11_CNTL = ctx->dcn_reg_offsets[2] + 0x2561, dccg_regs[4].DME_CONTROL = ctx->dcn_reg_offsets[2] + 0x2489, dccg_regs[4].DP_SEC_METADATA_TRANSMISSION = ctx->dcn_reg_offsets[2] + 0x255b, dccg_regs[4].HDMI_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x2493, dccg_regs[4].DIG_FE_CNTL = ctx->dcn_reg_offsets[2] + 0x248b, dccg_regs[4].DIG_CLOCK_PATTERN = ctx->dcn_reg_offsets[2] + 0x248e, dccg_regs[4].DIG_FIFO_CTRL0 = ctx->dcn_reg_offsets[2] + 0x2491 ); |
1239 | |
1240 | dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, |
1241 | eng_id, vpg, afmt, |
1242 | &stream_enc_regs[eng_id], |
1243 | &se_shift, &se_mask); |
1244 | |
1245 | return &enc1->base; |
1246 | } |
1247 | |
1248 | static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create( |
1249 | enum engine_id eng_id, |
1250 | struct dc_context *ctx) |
1251 | { |
1252 | struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; |
1253 | struct vpg *vpg; |
1254 | struct apg *apg; |
1255 | uint32_t hpo_dp_inst; |
1256 | uint32_t vpg_inst; |
1257 | uint32_t apg_inst; |
1258 | |
1259 | ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3))do { if (({ static int __warned; int __ret = !!(!((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c" , 1259); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1260 | hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; |
1261 | |
1262 | /* Mapping of VPG register blocks to HPO DP block instance: |
1263 | * VPG[6] -> HPO_DP[0] |
1264 | * VPG[7] -> HPO_DP[1] |
1265 | * VPG[8] -> HPO_DP[2] |
1266 | * VPG[9] -> HPO_DP[3] |
1267 | */ |
1268 | vpg_inst = hpo_dp_inst + 6; |
1269 | |
1270 | /* Mapping of APG register blocks to HPO DP block instance: |
1271 | * APG[0] -> HPO_DP[0] |
1272 | * APG[1] -> HPO_DP[1] |
1273 | * APG[2] -> HPO_DP[2] |
1274 | * APG[3] -> HPO_DP[3] |
1275 | */ |
1276 | apg_inst = hpo_dp_inst; |
1277 | |
1278 | /* allocate HPO stream encoder and create VPG sub-block */ |
1279 | hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL(0x0001 | 0x0004)); |
1280 | vpg = dcn32_vpg_create(ctx, vpg_inst); |
1281 | apg = dcn31_apg_create(ctx, apg_inst); |
1282 | |
1283 | if (!hpo_dp_enc31 || !vpg || !apg) { |
1284 | kfree(hpo_dp_enc31); |
1285 | kfree(vpg); |
1286 | kfree(apg); |
1287 | return NULL((void *)0); |
1288 | } |
1289 | |
1290 | #undef REG_STRUCTdccg_regs |
1291 | #define REG_STRUCTdccg_regs hpo_dp_stream_enc_regs |
1292 | hpo_dp_stream_encoder_reg_init(0)( dccg_regs[0].DP_STREAM_MAPPER_CONTROL0 = ctx->dcn_reg_offsets [3] + 0x0e56, dccg_regs[0].DP_STREAM_MAPPER_CONTROL1 = ctx-> dcn_reg_offsets[3] + 0x0e57, dccg_regs[0].DP_STREAM_MAPPER_CONTROL2 = ctx->dcn_reg_offsets[3] + 0x0e58, dccg_regs[0].DP_STREAM_MAPPER_CONTROL3 = ctx->dcn_reg_offsets[3] + 0x0e59, dccg_regs[0].DP_STREAM_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x3623, dccg_regs[0].DP_STREAM_ENC_INPUT_MUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x3624, dccg_regs[0].DP_STREAM_ENC_AUDIO_CONTROL = ctx->dcn_reg_offsets[2] + 0x3625, dccg_regs[0].DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x3626, dccg_regs[0].DP_SYM32_ENC_CONTROL = ctx->dcn_reg_offsets[2] + 0x365d, dccg_regs[0].DP_SYM32_ENC_VID_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x3661, dccg_regs[0].DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[2] + 0x3660, dccg_regs[0].DP_SYM32_ENC_VID_MSA0 = ctx->dcn_reg_offsets[2] + 0x3662, dccg_regs[0].DP_SYM32_ENC_VID_MSA1 = ctx->dcn_reg_offsets[2] + 0x3663, dccg_regs[0].DP_SYM32_ENC_VID_MSA2 = ctx->dcn_reg_offsets[2] + 0x3664, dccg_regs[0].DP_SYM32_ENC_VID_MSA3 = ctx->dcn_reg_offsets[2] + 0x3665, dccg_regs[0].DP_SYM32_ENC_VID_MSA4 = ctx->dcn_reg_offsets[2] + 0x3666, dccg_regs[0].DP_SYM32_ENC_VID_MSA5 = ctx->dcn_reg_offsets[2] + 0x3667, dccg_regs[0].DP_SYM32_ENC_VID_MSA6 = ctx->dcn_reg_offsets[2] + 0x3668, dccg_regs[0].DP_SYM32_ENC_VID_MSA7 = ctx->dcn_reg_offsets[2] + 0x3669, dccg_regs[0].DP_SYM32_ENC_VID_MSA8 = ctx->dcn_reg_offsets[2] + 0x366a, dccg_regs[0].DP_SYM32_ENC_VID_MSA_CONTROL = ctx->dcn_reg_offsets[2] + 0x3683, dccg_regs[0].DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[2] + 0x365f, dccg_regs[0].DP_SYM32_ENC_VID_FIFO_CONTROL = ctx->dcn_reg_offsets[2] + 0x365e, dccg_regs[0].DP_SYM32_ENC_VID_STREAM_CONTROL = ctx->dcn_reg_offsets[2] + 0x3685, dccg_regs[0].DP_SYM32_ENC_VID_VBID_CONTROL = ctx->dcn_reg_offsets[2] + 0x3684, dccg_regs[0].DP_SYM32_ENC_SDP_CONTROL = ctx->dcn_reg_offsets[2] + 0x367b, dccg_regs[0].DP_SYM32_ENC_SDP_GSP_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x366c, dccg_regs[0].DP_SYM32_ENC_SDP_GSP_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x366e, dccg_regs[0].DP_SYM32_ENC_SDP_GSP_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x366f, dccg_regs[0].DP_SYM32_ENC_SDP_GSP_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x3671, dccg_regs[0].DP_SYM32_ENC_SDP_GSP_CONTROL11 = ctx->dcn_reg_offsets[2] + 0x3677, dccg_regs[0].DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x367e, dccg_regs[0].DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x367c, dccg_regs[0].DP_SYM32_ENC_VID_CRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x3687, dccg_regs[0].DP_SYM32_ENC_HBLANK_CONTROL = ctx->dcn_reg_offsets[2] + 0x366b ), |
1293 | hpo_dp_stream_encoder_reg_init(1)( dccg_regs[1].DP_STREAM_MAPPER_CONTROL0 = ctx->dcn_reg_offsets [3] + 0x0e56, dccg_regs[1].DP_STREAM_MAPPER_CONTROL1 = ctx-> dcn_reg_offsets[3] + 0x0e57, dccg_regs[1].DP_STREAM_MAPPER_CONTROL2 = ctx->dcn_reg_offsets[3] + 0x0e58, dccg_regs[1].DP_STREAM_MAPPER_CONTROL3 = ctx->dcn_reg_offsets[3] + 0x0e59, dccg_regs[1].DP_STREAM_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x36f7, dccg_regs[1].DP_STREAM_ENC_INPUT_MUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x36f8, dccg_regs[1].DP_STREAM_ENC_AUDIO_CONTROL = ctx->dcn_reg_offsets[2] + 0x36f9, dccg_regs[1].DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x36fa, dccg_regs[1].DP_SYM32_ENC_CONTROL = ctx->dcn_reg_offsets[2] + 0x3731, dccg_regs[1].DP_SYM32_ENC_VID_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x3735, dccg_regs[1].DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[2] + 0x3734, dccg_regs[1].DP_SYM32_ENC_VID_MSA0 = ctx->dcn_reg_offsets[2] + 0x3736, dccg_regs[1].DP_SYM32_ENC_VID_MSA1 = ctx->dcn_reg_offsets[2] + 0x3737, dccg_regs[1].DP_SYM32_ENC_VID_MSA2 = ctx->dcn_reg_offsets[2] + 0x3738, dccg_regs[1].DP_SYM32_ENC_VID_MSA3 = ctx->dcn_reg_offsets[2] + 0x3739, dccg_regs[1].DP_SYM32_ENC_VID_MSA4 = ctx->dcn_reg_offsets[2] + 0x373a, dccg_regs[1].DP_SYM32_ENC_VID_MSA5 = ctx->dcn_reg_offsets[2] + 0x373b, dccg_regs[1].DP_SYM32_ENC_VID_MSA6 = ctx->dcn_reg_offsets[2] + 0x373c, dccg_regs[1].DP_SYM32_ENC_VID_MSA7 = ctx->dcn_reg_offsets[2] + 0x373d, dccg_regs[1].DP_SYM32_ENC_VID_MSA8 = ctx->dcn_reg_offsets[2] + 0x373e, dccg_regs[1].DP_SYM32_ENC_VID_MSA_CONTROL = ctx->dcn_reg_offsets[2] + 0x3757, dccg_regs[1].DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[2] + 0x3733, dccg_regs[1].DP_SYM32_ENC_VID_FIFO_CONTROL = ctx->dcn_reg_offsets[2] + 0x3732, dccg_regs[1].DP_SYM32_ENC_VID_STREAM_CONTROL = ctx->dcn_reg_offsets[2] + 0x3759, dccg_regs[1].DP_SYM32_ENC_VID_VBID_CONTROL = ctx->dcn_reg_offsets[2] + 0x3758, dccg_regs[1].DP_SYM32_ENC_SDP_CONTROL = ctx->dcn_reg_offsets[2] + 0x374f, dccg_regs[1].DP_SYM32_ENC_SDP_GSP_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x3740, dccg_regs[1].DP_SYM32_ENC_SDP_GSP_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x3742, dccg_regs[1].DP_SYM32_ENC_SDP_GSP_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x3743, dccg_regs[1].DP_SYM32_ENC_SDP_GSP_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x3745, dccg_regs[1].DP_SYM32_ENC_SDP_GSP_CONTROL11 = ctx->dcn_reg_offsets[2] + 0x374b, dccg_regs[1].DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x3752, dccg_regs[1].DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x3750, dccg_regs[1].DP_SYM32_ENC_VID_CRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x375b, dccg_regs[1].DP_SYM32_ENC_HBLANK_CONTROL = ctx->dcn_reg_offsets[2] + 0x373f ), |
1294 | hpo_dp_stream_encoder_reg_init(2)( dccg_regs[2].DP_STREAM_MAPPER_CONTROL0 = ctx->dcn_reg_offsets [3] + 0x0e56, dccg_regs[2].DP_STREAM_MAPPER_CONTROL1 = ctx-> dcn_reg_offsets[3] + 0x0e57, dccg_regs[2].DP_STREAM_MAPPER_CONTROL2 = ctx->dcn_reg_offsets[3] + 0x0e58, dccg_regs[2].DP_STREAM_MAPPER_CONTROL3 = ctx->dcn_reg_offsets[3] + 0x0e59, dccg_regs[2].DP_STREAM_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x37cb, dccg_regs[2].DP_STREAM_ENC_INPUT_MUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x37cc, dccg_regs[2].DP_STREAM_ENC_AUDIO_CONTROL = ctx->dcn_reg_offsets[2] + 0x37cd, dccg_regs[2].DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x37ce, dccg_regs[2].DP_SYM32_ENC_CONTROL = ctx->dcn_reg_offsets[2] + 0x3805, dccg_regs[2].DP_SYM32_ENC_VID_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x3809, dccg_regs[2].DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[2] + 0x3808, dccg_regs[2].DP_SYM32_ENC_VID_MSA0 = ctx->dcn_reg_offsets[2] + 0x380a, dccg_regs[2].DP_SYM32_ENC_VID_MSA1 = ctx->dcn_reg_offsets[2] + 0x380b, dccg_regs[2].DP_SYM32_ENC_VID_MSA2 = ctx->dcn_reg_offsets[2] + 0x380c, dccg_regs[2].DP_SYM32_ENC_VID_MSA3 = ctx->dcn_reg_offsets[2] + 0x380d, dccg_regs[2].DP_SYM32_ENC_VID_MSA4 = ctx->dcn_reg_offsets[2] + 0x380e, dccg_regs[2].DP_SYM32_ENC_VID_MSA5 = ctx->dcn_reg_offsets[2] + 0x380f, dccg_regs[2].DP_SYM32_ENC_VID_MSA6 = ctx->dcn_reg_offsets[2] + 0x3810, dccg_regs[2].DP_SYM32_ENC_VID_MSA7 = ctx->dcn_reg_offsets[2] + 0x3811, dccg_regs[2].DP_SYM32_ENC_VID_MSA8 = ctx->dcn_reg_offsets[2] + 0x3812, dccg_regs[2].DP_SYM32_ENC_VID_MSA_CONTROL = ctx->dcn_reg_offsets[2] + 0x382b, dccg_regs[2].DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[2] + 0x3807, dccg_regs[2].DP_SYM32_ENC_VID_FIFO_CONTROL = ctx->dcn_reg_offsets[2] + 0x3806, dccg_regs[2].DP_SYM32_ENC_VID_STREAM_CONTROL = ctx->dcn_reg_offsets[2] + 0x382d, dccg_regs[2].DP_SYM32_ENC_VID_VBID_CONTROL = ctx->dcn_reg_offsets[2] + 0x382c, dccg_regs[2].DP_SYM32_ENC_SDP_CONTROL = ctx->dcn_reg_offsets[2] + 0x3823, dccg_regs[2].DP_SYM32_ENC_SDP_GSP_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x3814, dccg_regs[2].DP_SYM32_ENC_SDP_GSP_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x3816, dccg_regs[2].DP_SYM32_ENC_SDP_GSP_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x3817, dccg_regs[2].DP_SYM32_ENC_SDP_GSP_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x3819, dccg_regs[2].DP_SYM32_ENC_SDP_GSP_CONTROL11 = ctx->dcn_reg_offsets[2] + 0x381f, dccg_regs[2].DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x3826, dccg_regs[2].DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x3824, dccg_regs[2].DP_SYM32_ENC_VID_CRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x382f, dccg_regs[2].DP_SYM32_ENC_HBLANK_CONTROL = ctx->dcn_reg_offsets[2] + 0x3813 ), |
1295 | hpo_dp_stream_encoder_reg_init(3)( dccg_regs[3].DP_STREAM_MAPPER_CONTROL0 = ctx->dcn_reg_offsets [3] + 0x0e56, dccg_regs[3].DP_STREAM_MAPPER_CONTROL1 = ctx-> dcn_reg_offsets[3] + 0x0e57, dccg_regs[3].DP_STREAM_MAPPER_CONTROL2 = ctx->dcn_reg_offsets[3] + 0x0e58, dccg_regs[3].DP_STREAM_MAPPER_CONTROL3 = ctx->dcn_reg_offsets[3] + 0x0e59, dccg_regs[3].DP_STREAM_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets[2] + 0x389f, dccg_regs[3].DP_STREAM_ENC_INPUT_MUX_CONTROL = ctx->dcn_reg_offsets[2] + 0x38a0, dccg_regs[3].DP_STREAM_ENC_AUDIO_CONTROL = ctx->dcn_reg_offsets[2] + 0x38a1, dccg_regs[3].DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x38a2, dccg_regs[3].DP_SYM32_ENC_CONTROL = ctx->dcn_reg_offsets[2] + 0x38d9, dccg_regs[3].DP_SYM32_ENC_VID_PIXEL_FORMAT = ctx->dcn_reg_offsets[2] + 0x38dd, dccg_regs[3].DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[2] + 0x38dc, dccg_regs[3].DP_SYM32_ENC_VID_MSA0 = ctx->dcn_reg_offsets[2] + 0x38de, dccg_regs[3].DP_SYM32_ENC_VID_MSA1 = ctx->dcn_reg_offsets[2] + 0x38df, dccg_regs[3].DP_SYM32_ENC_VID_MSA2 = ctx->dcn_reg_offsets[2] + 0x38e0, dccg_regs[3].DP_SYM32_ENC_VID_MSA3 = ctx->dcn_reg_offsets[2] + 0x38e1, dccg_regs[3].DP_SYM32_ENC_VID_MSA4 = ctx->dcn_reg_offsets[2] + 0x38e2, dccg_regs[3].DP_SYM32_ENC_VID_MSA5 = ctx->dcn_reg_offsets[2] + 0x38e3, dccg_regs[3].DP_SYM32_ENC_VID_MSA6 = ctx->dcn_reg_offsets[2] + 0x38e4, dccg_regs[3].DP_SYM32_ENC_VID_MSA7 = ctx->dcn_reg_offsets[2] + 0x38e5, dccg_regs[3].DP_SYM32_ENC_VID_MSA8 = ctx->dcn_reg_offsets[2] + 0x38e6, dccg_regs[3].DP_SYM32_ENC_VID_MSA_CONTROL = ctx->dcn_reg_offsets[2] + 0x38ff, dccg_regs[3].DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = ctx->dcn_reg_offsets[2] + 0x38db, dccg_regs[3].DP_SYM32_ENC_VID_FIFO_CONTROL = ctx->dcn_reg_offsets[2] + 0x38da, dccg_regs[3].DP_SYM32_ENC_VID_STREAM_CONTROL = ctx->dcn_reg_offsets[2] + 0x3901, dccg_regs[3].DP_SYM32_ENC_VID_VBID_CONTROL = ctx->dcn_reg_offsets[2] + 0x3900, dccg_regs[3].DP_SYM32_ENC_SDP_CONTROL = ctx->dcn_reg_offsets[2] + 0x38f7, dccg_regs[3].DP_SYM32_ENC_SDP_GSP_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x38e8, dccg_regs[3].DP_SYM32_ENC_SDP_GSP_CONTROL2 = ctx->dcn_reg_offsets[2] + 0x38ea, dccg_regs[3].DP_SYM32_ENC_SDP_GSP_CONTROL3 = ctx->dcn_reg_offsets[2] + 0x38eb, dccg_regs[3].DP_SYM32_ENC_SDP_GSP_CONTROL5 = ctx->dcn_reg_offsets[2] + 0x38ed, dccg_regs[3].DP_SYM32_ENC_SDP_GSP_CONTROL11 = ctx->dcn_reg_offsets[2] + 0x38f3, dccg_regs[3].DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = ctx->dcn_reg_offsets[2] + 0x38fa, dccg_regs[3].DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = ctx->dcn_reg_offsets[2] + 0x38f8, dccg_regs[3].DP_SYM32_ENC_VID_CRC_CONTROL = ctx->dcn_reg_offsets[2] + 0x3903, dccg_regs[3].DP_SYM32_ENC_HBLANK_CONTROL = ctx->dcn_reg_offsets[2] + 0x38e7 ); |
1296 | |
1297 | dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, |
1298 | hpo_dp_inst, eng_id, vpg, apg, |
1299 | &hpo_dp_stream_enc_regs[hpo_dp_inst], |
1300 | &hpo_dp_se_shift, &hpo_dp_se_mask); |
1301 | |
1302 | return &hpo_dp_enc31->base; |
1303 | } |
1304 | |
1305 | static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create( |
1306 | uint8_t inst, |
1307 | struct dc_context *ctx) |
1308 | { |
1309 | struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; |
1310 | |
1311 | /* allocate HPO link encoder */ |
1312 | hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL(0x0001 | 0x0004)); |
1313 | |
1314 | #undef REG_STRUCTdccg_regs |
1315 | #define REG_STRUCTdccg_regs hpo_dp_link_enc_regs |
1316 | hpo_dp_link_encoder_reg_init(0)( dccg_regs[0].DP_LINK_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets [2] + 0x3697, dccg_regs[0].DP_DPHY_SYM32_CONTROL = ctx->dcn_reg_offsets [2] + 0x36c0, dccg_regs[0].DP_DPHY_SYM32_STATUS = ctx->dcn_reg_offsets [2] + 0x36c1, dccg_regs[0].DP_DPHY_SYM32_TP_CONFIG = ctx-> dcn_reg_offsets[2] + 0x36d7, dccg_regs[0].DP_DPHY_SYM32_TP_PRBS_SEED0 = ctx->dcn_reg_offsets[2] + 0x36d8, dccg_regs[0].DP_DPHY_SYM32_TP_PRBS_SEED1 = ctx->dcn_reg_offsets[2] + 0x36d9, dccg_regs[0].DP_DPHY_SYM32_TP_PRBS_SEED2 = ctx->dcn_reg_offsets[2] + 0x36da, dccg_regs[0].DP_DPHY_SYM32_TP_PRBS_SEED3 = ctx->dcn_reg_offsets[2] + 0x36db, dccg_regs[0].DP_DPHY_SYM32_TP_SQ_PULSE = ctx->dcn_reg_offsets[2] + 0x36dc, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM0 = ctx->dcn_reg_offsets[2] + 0x36dd, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM1 = ctx->dcn_reg_offsets[2] + 0x36de, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM2 = ctx->dcn_reg_offsets[2] + 0x36df, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM3 = ctx->dcn_reg_offsets[2] + 0x36e0, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM4 = ctx->dcn_reg_offsets[2] + 0x36e1, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM5 = ctx->dcn_reg_offsets[2] + 0x36e2, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM6 = ctx->dcn_reg_offsets[2] + 0x36e3, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM7 = ctx->dcn_reg_offsets[2] + 0x36e4, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM8 = ctx->dcn_reg_offsets[2] + 0x36e5, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM9 = ctx->dcn_reg_offsets[2] + 0x36e6, dccg_regs[0].DP_DPHY_SYM32_TP_CUSTOM10 = ctx->dcn_reg_offsets[2] + 0x36e7, dccg_regs[0].DP_DPHY_SYM32_SAT_VC0 = ctx->dcn_reg_offsets[2] + 0x36cb, dccg_regs[0].DP_DPHY_SYM32_SAT_VC1 = ctx->dcn_reg_offsets[2] + 0x36cc, dccg_regs[0].DP_DPHY_SYM32_SAT_VC2 = ctx->dcn_reg_offsets[2] + 0x36cd, dccg_regs[0].DP_DPHY_SYM32_SAT_VC3 = ctx->dcn_reg_offsets[2] + 0x36ce, dccg_regs[0].DP_DPHY_SYM32_VC_RATE_CNTL0 = ctx->dcn_reg_offsets[2] + 0x36c5, dccg_regs[0].DP_DPHY_SYM32_VC_RATE_CNTL1 = ctx->dcn_reg_offsets[2] + 0x36c6, dccg_regs[0].DP_DPHY_SYM32_VC_RATE_CNTL2 = ctx->dcn_reg_offsets[2] + 0x36c7, dccg_regs[0].DP_DPHY_SYM32_VC_RATE_CNTL3 = ctx->dcn_reg_offsets[2] + 0x36c8, dccg_regs[0].DP_DPHY_SYM32_SAT_UPDATE = ctx->dcn_reg_offsets[2] + 0x36c4 ), |
1317 | hpo_dp_link_encoder_reg_init(1)( dccg_regs[1].DP_LINK_ENC_CLOCK_CONTROL = ctx->dcn_reg_offsets [2] + 0x376b, dccg_regs[1].DP_DPHY_SYM32_CONTROL = ctx->dcn_reg_offsets [2] + 0x3794, dccg_regs[1].DP_DPHY_SYM32_STATUS = ctx->dcn_reg_offsets [2] + 0x3795, dccg_regs[1].DP_DPHY_SYM32_TP_CONFIG = ctx-> dcn_reg_offsets[2] + 0x37ab, dccg_regs[1].DP_DPHY_SYM32_TP_PRBS_SEED0 = ctx->dcn_reg_offsets[2] + 0x37ac, dccg_regs[1].DP_DPHY_SYM32_TP_PRBS_SEED1 = ctx->dcn_reg_offsets[2] + 0x37ad, dccg_regs[1].DP_DPHY_SYM32_TP_PRBS_SEED2 = ctx->dcn_reg_offsets[2] + 0x37ae, dccg_regs[1].DP_DPHY_SYM32_TP_PRBS_SEED3 = ctx->dcn_reg_offsets[2] + 0x37af, dccg_regs[1].DP_DPHY_SYM32_TP_SQ_PULSE = ctx->dcn_reg_offsets[2] + 0x37b0, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM0 = ctx->dcn_reg_offsets[2] + 0x37b1, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM1 = ctx->dcn_reg_offsets[2] + 0x37b2, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM2 = ctx->dcn_reg_offsets[2] + 0x37b3, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM3 = ctx->dcn_reg_offsets[2] + 0x37b4, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM4 = ctx->dcn_reg_offsets[2] + 0x37b5, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM5 = ctx->dcn_reg_offsets[2] + 0x37b6, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM6 = ctx->dcn_reg_offsets[2] + 0x37b7, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM7 = ctx->dcn_reg_offsets[2] + 0x37b8, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM8 = ctx->dcn_reg_offsets[2] + 0x37b9, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM9 = ctx->dcn_reg_offsets[2] + 0x37ba, dccg_regs[1].DP_DPHY_SYM32_TP_CUSTOM10 = ctx->dcn_reg_offsets[2] + 0x37bb, dccg_regs[1].DP_DPHY_SYM32_SAT_VC0 = ctx->dcn_reg_offsets[2] + 0x379f, dccg_regs[1].DP_DPHY_SYM32_SAT_VC1 = ctx->dcn_reg_offsets[2] + 0x37a0, dccg_regs[1].DP_DPHY_SYM32_SAT_VC2 = ctx->dcn_reg_offsets[2] + 0x37a1, dccg_regs[1].DP_DPHY_SYM32_SAT_VC3 = ctx->dcn_reg_offsets[2] + 0x37a2, dccg_regs[1].DP_DPHY_SYM32_VC_RATE_CNTL0 = ctx->dcn_reg_offsets[2] + 0x3799, dccg_regs[1].DP_DPHY_SYM32_VC_RATE_CNTL1 = ctx->dcn_reg_offsets[2] + 0x379a, dccg_regs[1].DP_DPHY_SYM32_VC_RATE_CNTL2 = ctx->dcn_reg_offsets[2] + 0x379b, dccg_regs[1].DP_DPHY_SYM32_VC_RATE_CNTL3 = ctx->dcn_reg_offsets[2] + 0x379c, dccg_regs[1].DP_DPHY_SYM32_SAT_UPDATE = ctx->dcn_reg_offsets[2] + 0x3798 ); |
1318 | |
1319 | hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst, |
1320 | &hpo_dp_link_enc_regs[inst], |
1321 | &hpo_dp_le_shift, &hpo_dp_le_mask); |
1322 | |
1323 | return &hpo_dp_enc31->base; |
1324 | } |
1325 | |
1326 | static struct dce_hwseq *dcn32_hwseq_create( |
1327 | struct dc_context *ctx) |
1328 | { |
1329 | struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL(0x0001 | 0x0004)); |
1330 | |
1331 | #undef REG_STRUCTdccg_regs |
1332 | #define REG_STRUCTdccg_regs hwseq_reg |
1333 | hwseq_reg_init()dccg_regs.DCHUBBUB_GLOBAL_TIMER_CNTL = ctx->dcn_reg_offsets [2] + 0x0525, dccg_regs.DIO_MEM_PWR_CTRL = ctx->dcn_reg_offsets [2] + 0x1ede, dccg_regs.ODM_MEM_PWR_CTRL3 = ctx->dcn_reg_offsets [2] + 0x1e2f, dccg_regs.MMHUBBUB_MEM_PWR_CNTL = ctx->dcn_reg_offsets [2] + 0x0340, dccg_regs.DCCG_GATE_DISABLE_CNTL = ctx->dcn_reg_offsets [1] + 0x0074, dccg_regs.DCCG_GATE_DISABLE_CNTL2 = ctx->dcn_reg_offsets [1] + 0x007c, dccg_regs.DCFCLK_CNTL = ctx->dcn_reg_offsets [2] + 0x0534, dccg_regs.DC_MEM_GLOBAL_PWR_REQ_CNTL = ctx-> dcn_reg_offsets[1] + 0x0072, dccg_regs.PIXEL_RATE_CNTL[0] = ctx ->dcn_reg_offsets[1] + 0x0080, dccg_regs.PIXEL_RATE_CNTL[1 ] = ctx->dcn_reg_offsets[1] + 0x0084, dccg_regs.PIXEL_RATE_CNTL [2] = ctx->dcn_reg_offsets[1] + 0x0088, dccg_regs.PIXEL_RATE_CNTL [3] = ctx->dcn_reg_offsets[1] + 0x008c, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [0] = ctx->dcn_reg_offsets[1] + 0x0083, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [1] = ctx->dcn_reg_offsets[1] + 0x0087, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [2] = ctx->dcn_reg_offsets[1] + 0x008b, dccg_regs.PHYPLL_PIXEL_RATE_CNTL [3] = ctx->dcn_reg_offsets[1] + 0x008f, dccg_regs.MICROSECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x007b, dccg_regs.MILLISECOND_TIME_BASE_DIV = ctx->dcn_reg_offsets[1] + 0x0070, dccg_regs.DISPCLK_FREQ_CHANGE_CNTL = ctx->dcn_reg_offsets[1] + 0x0071, dccg_regs.RBBMIF_TIMEOUT_DIS = ctx->dcn_reg_offsets[2] + 0x0183, dccg_regs.RBBMIF_TIMEOUT_DIS_2 = ctx->dcn_reg_offsets[2] + 0x0184, dccg_regs.DCHUBBUB_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x04b1, dccg_regs.DPP_TOP0_DPP_CRC_CTRL = ctx->dcn_reg_offsets[2] + 0x0cc9, dccg_regs.DPP_TOP0_DPP_CRC_VAL_B_A = ctx->dcn_reg_offsets[2] + 0x0cc8, dccg_regs.DPP_TOP0_DPP_CRC_VAL_R_G = ctx->dcn_reg_offsets[2] + 0x0cc7, dccg_regs.MPC_CRC_CTRL = ctx->dcn_reg_offsets[3] + 0x039a, dccg_regs.MPC_CRC_RESULT_GB = ctx->dcn_reg_offsets[3] + 0x039d, dccg_regs.MPC_CRC_RESULT_C = ctx->dcn_reg_offsets[3] + 0x039e, dccg_regs.MPC_CRC_RESULT_AR = ctx->dcn_reg_offsets[3] + 0x039c, dccg_regs.DOMAIN0_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0080, dccg_regs.DOMAIN1_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0082, dccg_regs.DOMAIN2_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0084, dccg_regs.DOMAIN3_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0086, dccg_regs.DOMAIN16_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x0089, dccg_regs.DOMAIN17_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008b, dccg_regs.DOMAIN18_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008d, dccg_regs.DOMAIN19_PG_CONFIG = ctx->dcn_reg_offsets[2] + 0x008f, dccg_regs.DOMAIN0_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0081, dccg_regs.DOMAIN1_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0083, dccg_regs.DOMAIN2_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0085, dccg_regs.DOMAIN3_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0087, dccg_regs.DOMAIN16_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008a, dccg_regs.DOMAIN17_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008c, dccg_regs.DOMAIN18_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x008e, dccg_regs.DOMAIN19_PG_STATUS = ctx->dcn_reg_offsets[2] + 0x0090, dccg_regs.D1VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000c, dccg_regs.D2VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x000e, dccg_regs.D3VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0038, dccg_regs.D4VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x0039, dccg_regs.D5VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003a, dccg_regs.D6VGA_CONTROL = ctx->dcn_reg_offsets[1] + 0x003b, dccg_regs.DC_IP_REQUEST_CNTL = ctx->dcn_reg_offsets[2] + 0x0095, dccg_regs.AZALIA_AUDIO_DTO = ctx->dcn_reg_offsets[2] + 0x03c3, dccg_regs.AZALIA_CONTROLLER_CLOCK_GATING = ctx->dcn_reg_offsets[2] + 0x03c2; |
1334 | |
1335 | if (hws) { |
1336 | hws->ctx = ctx; |
1337 | hws->regs = &hwseq_reg; |
1338 | hws->shifts = &hwseq_shift; |
1339 | hws->masks = &hwseq_mask; |
1340 | } |
1341 | return hws; |
1342 | } |
1343 | static const struct resource_create_funcs res_create_funcs = { |
1344 | .read_dce_straps = read_dce_straps, |
1345 | .create_audio = dcn32_create_audio, |
1346 | .create_stream_encoder = dcn32_stream_encoder_create, |
1347 | .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, |
1348 | .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, |
1349 | .create_hwseq = dcn32_hwseq_create, |
1350 | }; |
1351 | |
1352 | static const struct resource_create_funcs res_create_maximus_funcs = { |
1353 | .read_dce_straps = NULL((void *)0), |
1354 | .create_audio = NULL((void *)0), |
1355 | .create_stream_encoder = NULL((void *)0), |
1356 | .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create, |
1357 | .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create, |
1358 | .create_hwseq = dcn32_hwseq_create, |
1359 | }; |
1360 | |
1361 | static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) |
1362 | { |
1363 | unsigned int i; |
1364 | |
1365 | for (i = 0; i < pool->base.stream_enc_count; i++) { |
1366 | if (pool->base.stream_enc[i] != NULL((void *)0)) { |
1367 | if (pool->base.stream_enc[i]->vpg != NULL((void *)0)) { |
1368 | kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)({ const __typeof( ((struct dcn30_vpg *)0)->base ) *__mptr = (pool->base.stream_enc[i]->vpg); (struct dcn30_vpg * )( (char *)__mptr - __builtin_offsetof(struct dcn30_vpg, base ) );})); |
1369 | pool->base.stream_enc[i]->vpg = NULL((void *)0); |
1370 | } |
1371 | if (pool->base.stream_enc[i]->afmt != NULL((void *)0)) { |
1372 | kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)({ const __typeof( ((struct dcn30_afmt *)0)->base ) *__mptr = (pool->base.stream_enc[i]->afmt); (struct dcn30_afmt *)( (char *)__mptr - __builtin_offsetof(struct dcn30_afmt, base ) );})); |
1373 | pool->base.stream_enc[i]->afmt = NULL((void *)0); |
1374 | } |
1375 | kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])({ const __typeof( ((struct dcn10_stream_encoder *)0)->base ) *__mptr = (pool->base.stream_enc[i]); (struct dcn10_stream_encoder *)( (char *)__mptr - __builtin_offsetof(struct dcn10_stream_encoder , base) );})); |
1376 | pool->base.stream_enc[i] = NULL((void *)0); |
1377 | } |
1378 | } |
1379 | |
1380 | for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { |
1381 | if (pool->base.hpo_dp_stream_enc[i] != NULL((void *)0)) { |
1382 | if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL((void *)0)) { |
1383 | kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)({ const __typeof( ((struct dcn30_vpg *)0)->base ) *__mptr = (pool->base.hpo_dp_stream_enc[i]->vpg); (struct dcn30_vpg *)( (char *)__mptr - __builtin_offsetof(struct dcn30_vpg, base ) );})); |
1384 | pool->base.hpo_dp_stream_enc[i]->vpg = NULL((void *)0); |
1385 | } |
1386 | if (pool->base.hpo_dp_stream_enc[i]->apg != NULL((void *)0)) { |
1387 | kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)({ const __typeof( ((struct dcn31_apg *)0)->base ) *__mptr = (pool->base.hpo_dp_stream_enc[i]->apg); (struct dcn31_apg *)( (char *)__mptr - __builtin_offsetof(struct dcn31_apg, base ) );})); |
1388 | pool->base.hpo_dp_stream_enc[i]->apg = NULL((void *)0); |
1389 | } |
1390 | kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])({ const __typeof( ((struct dcn31_hpo_dp_stream_encoder *)0)-> base ) *__mptr = (pool->base.hpo_dp_stream_enc[i]); (struct dcn31_hpo_dp_stream_encoder *)( (char *)__mptr - __builtin_offsetof (struct dcn31_hpo_dp_stream_encoder, base) );})); |
1391 | pool->base.hpo_dp_stream_enc[i] = NULL((void *)0); |
1392 | } |
1393 | } |
1394 | |
1395 | for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { |
1396 | if (pool->base.hpo_dp_link_enc[i] != NULL((void *)0)) { |
1397 | kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])({ const __typeof( ((struct dcn31_hpo_dp_link_encoder *)0)-> base ) *__mptr = (pool->base.hpo_dp_link_enc[i]); (struct dcn31_hpo_dp_link_encoder *)( (char *)__mptr - __builtin_offsetof(struct dcn31_hpo_dp_link_encoder , base) );})); |
1398 | pool->base.hpo_dp_link_enc[i] = NULL((void *)0); |
1399 | } |
1400 | } |
1401 | |
1402 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { |
1403 | if (pool->base.dscs[i] != NULL((void *)0)) |
1404 | dcn20_dsc_destroy(&pool->base.dscs[i]); |
1405 | } |
1406 | |
1407 | if (pool->base.mpc != NULL((void *)0)) { |
1408 | kfree(TO_DCN20_MPC(pool->base.mpc)({ const __typeof( ((struct dcn20_mpc *)0)->base ) *__mptr = (pool->base.mpc); (struct dcn20_mpc *)( (char *)__mptr - __builtin_offsetof(struct dcn20_mpc, base) );})); |
1409 | pool->base.mpc = NULL((void *)0); |
1410 | } |
1411 | if (pool->base.hubbub != NULL((void *)0)) { |
1412 | kfree(TO_DCN20_HUBBUB(pool->base.hubbub)({ const __typeof( ((struct dcn20_hubbub *)0)->base ) *__mptr = (pool->base.hubbub); (struct dcn20_hubbub *)( (char *)__mptr - __builtin_offsetof(struct dcn20_hubbub, base) );})); |
1413 | pool->base.hubbub = NULL((void *)0); |
1414 | } |
1415 | for (i = 0; i < pool->base.pipe_count; i++) { |
1416 | if (pool->base.dpps[i] != NULL((void *)0)) |
1417 | dcn32_dpp_destroy(&pool->base.dpps[i]); |
1418 | |
1419 | if (pool->base.ipps[i] != NULL((void *)0)) |
1420 | pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); |
1421 | |
1422 | if (pool->base.hubps[i] != NULL((void *)0)) { |
1423 | kfree(TO_DCN20_HUBP(pool->base.hubps[i])({ const __typeof( ((struct dcn20_hubp *)0)->base ) *__mptr = (pool->base.hubps[i]); (struct dcn20_hubp *)( (char *)__mptr - __builtin_offsetof(struct dcn20_hubp, base) );})); |
1424 | pool->base.hubps[i] = NULL((void *)0); |
1425 | } |
1426 | |
1427 | if (pool->base.irqs != NULL((void *)0)) { |
1428 | dal_irq_service_destroy(&pool->base.irqs); |
1429 | } |
1430 | } |
1431 | |
1432 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { |
1433 | if (pool->base.engines[i] != NULL((void *)0)) |
1434 | dce110_engine_destroy(&pool->base.engines[i]); |
1435 | if (pool->base.hw_i2cs[i] != NULL((void *)0)) { |
1436 | kfree(pool->base.hw_i2cs[i]); |
1437 | pool->base.hw_i2cs[i] = NULL((void *)0); |
1438 | } |
1439 | if (pool->base.sw_i2cs[i] != NULL((void *)0)) { |
1440 | kfree(pool->base.sw_i2cs[i]); |
1441 | pool->base.sw_i2cs[i] = NULL((void *)0); |
1442 | } |
1443 | } |
1444 | |
1445 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { |
1446 | if (pool->base.opps[i] != NULL((void *)0)) |
1447 | pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); |
1448 | } |
1449 | |
1450 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { |
1451 | if (pool->base.timing_generators[i] != NULL((void *)0)) { |
1452 | kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])({ const __typeof( ((struct optc *)0)->base ) *__mptr = (pool ->base.timing_generators[i]); (struct optc *)( (char *)__mptr - __builtin_offsetof(struct optc, base) );})); |
1453 | pool->base.timing_generators[i] = NULL((void *)0); |
1454 | } |
1455 | } |
1456 | |
1457 | for (i = 0; i < pool->base.res_cap->num_dwb; i++) { |
1458 | if (pool->base.dwbc[i] != NULL((void *)0)) { |
1459 | kfree(TO_DCN30_DWBC(pool->base.dwbc[i])({ const __typeof( ((struct dcn30_dwbc *)0)->base ) *__mptr = (pool->base.dwbc[i]); (struct dcn30_dwbc *)( (char *)__mptr - __builtin_offsetof(struct dcn30_dwbc, base) );})); |
1460 | pool->base.dwbc[i] = NULL((void *)0); |
1461 | } |
1462 | if (pool->base.mcif_wb[i] != NULL((void *)0)) { |
1463 | kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])({ const __typeof( ((struct dcn30_mmhubbub *)0)->base ) *__mptr = (pool->base.mcif_wb[i]); (struct dcn30_mmhubbub *)( (char *)__mptr - __builtin_offsetof(struct dcn30_mmhubbub, base) ) ;})); |
1464 | pool->base.mcif_wb[i] = NULL((void *)0); |
1465 | } |
1466 | } |
1467 | |
1468 | for (i = 0; i < pool->base.audio_count; i++) { |
1469 | if (pool->base.audios[i]) |
1470 | dce_aud_destroy(&pool->base.audios[i]); |
1471 | } |
1472 | |
1473 | for (i = 0; i < pool->base.clk_src_count; i++) { |
1474 | if (pool->base.clock_sources[i] != NULL((void *)0)) { |
1475 | dcn20_clock_source_destroy(&pool->base.clock_sources[i]); |
1476 | pool->base.clock_sources[i] = NULL((void *)0); |
1477 | } |
1478 | } |
1479 | |
1480 | for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { |
1481 | if (pool->base.mpc_lut[i] != NULL((void *)0)) { |
1482 | dc_3dlut_func_release(pool->base.mpc_lut[i]); |
1483 | pool->base.mpc_lut[i] = NULL((void *)0); |
1484 | } |
1485 | if (pool->base.mpc_shaper[i] != NULL((void *)0)) { |
1486 | dc_transfer_func_release(pool->base.mpc_shaper[i]); |
1487 | pool->base.mpc_shaper[i] = NULL((void *)0); |
1488 | } |
1489 | } |
1490 | |
1491 | if (pool->base.dp_clock_source != NULL((void *)0)) { |
1492 | dcn20_clock_source_destroy(&pool->base.dp_clock_source); |
1493 | pool->base.dp_clock_source = NULL((void *)0); |
1494 | } |
1495 | |
1496 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { |
1497 | if (pool->base.multiple_abms[i] != NULL((void *)0)) |
1498 | dce_abm_destroy(&pool->base.multiple_abms[i]); |
1499 | } |
1500 | |
1501 | if (pool->base.psr != NULL((void *)0)) |
1502 | dmub_psr_destroy(&pool->base.psr); |
1503 | |
1504 | if (pool->base.dccg != NULL((void *)0)) |
1505 | dcn_dccg_destroy(&pool->base.dccg); |
1506 | |
1507 | if (pool->base.oem_device != NULL((void *)0)) |
1508 | dal_ddc_service_destroy(&pool->base.oem_device); |
1509 | } |
1510 | |
1511 | |
1512 | static bool_Bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) |
1513 | { |
1514 | int i; |
1515 | uint32_t dwb_count = pool->res_cap->num_dwb; |
1516 | |
1517 | for (i = 0; i < dwb_count; i++) { |
1518 | struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), |
1519 | GFP_KERNEL(0x0001 | 0x0004)); |
1520 | |
1521 | if (!dwbc30) { |
1522 | dm_error("DC: failed to create dwbc30!\n")__drm_err("DC: failed to create dwbc30!\n"); |
1523 | return false0; |
1524 | } |
1525 | |
1526 | #undef REG_STRUCTdccg_regs |
1527 | #define REG_STRUCTdccg_regs dwbc30_regs |
1528 | dwbc_regs_dcn3_init(0)( dccg_regs[0].DWB_ENABLE_CLK_CTRL = ctx->dcn_reg_offsets[ 2] + 0x3228, dccg_regs[0].DWB_MEM_PWR_CTRL = ctx->dcn_reg_offsets [2] + 0x3229, dccg_regs[0].FC_MODE_CTRL = ctx->dcn_reg_offsets [2] + 0x322a, dccg_regs[0].FC_FLOW_CTRL = ctx->dcn_reg_offsets [2] + 0x322b, dccg_regs[0].FC_WINDOW_START = ctx->dcn_reg_offsets [2] + 0x322c, dccg_regs[0].FC_WINDOW_SIZE = ctx->dcn_reg_offsets [2] + 0x322d, dccg_regs[0].FC_SOURCE_SIZE = ctx->dcn_reg_offsets [2] + 0x322e, dccg_regs[0].DWB_UPDATE_CTRL = ctx->dcn_reg_offsets [2] + 0x322f, dccg_regs[0].DWB_CRC_CTRL = ctx->dcn_reg_offsets [2] + 0x3230, dccg_regs[0].DWB_CRC_MASK_R_G = ctx->dcn_reg_offsets [2] + 0x3231, dccg_regs[0].DWB_CRC_MASK_B_A = ctx->dcn_reg_offsets [2] + 0x3232, dccg_regs[0].DWB_CRC_VAL_R_G = ctx->dcn_reg_offsets [2] + 0x3233, dccg_regs[0].DWB_CRC_VAL_B_A = ctx->dcn_reg_offsets [2] + 0x3234, dccg_regs[0].DWB_OUT_CTRL = ctx->dcn_reg_offsets [2] + 0x3235, dccg_regs[0].DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = ctx->dcn_reg_offsets[2] + 0x3236, dccg_regs[0].DWB_MMHUBBUB_BACKPRESSURE_CNT = ctx->dcn_reg_offsets[2] + 0x3237, dccg_regs[0].DWB_HOST_READ_CONTROL = ctx->dcn_reg_offsets[2] + 0x3238, dccg_regs[0].DWB_SOFT_RESET = ctx->dcn_reg_offsets[2] + 0x323b, dccg_regs[0].DWB_HDR_MULT_COEF = ctx->dcn_reg_offsets[2] + 0x3294, dccg_regs[0].DWB_GAMUT_REMAP_MODE = ctx->dcn_reg_offsets[2] + 0x3295, dccg_regs[0].DWB_GAMUT_REMAP_COEF_FORMAT = ctx->dcn_reg_offsets[2] + 0x3296, dccg_regs[0].DWB_GAMUT_REMAPA_C11_C12 = ctx->dcn_reg_offsets[2] + 0x3297, dccg_regs[0].DWB_GAMUT_REMAPA_C13_C14 = ctx->dcn_reg_offsets[2] + 0x3298, dccg_regs[0].DWB_GAMUT_REMAPA_C21_C22 = ctx->dcn_reg_offsets[2] + 0x3299, dccg_regs[0].DWB_GAMUT_REMAPA_C23_C24 = ctx->dcn_reg_offsets[2] + 0x329a, dccg_regs[0].DWB_GAMUT_REMAPA_C31_C32 = ctx->dcn_reg_offsets[2] + 0x329b, dccg_regs[0].DWB_GAMUT_REMAPA_C33_C34 = ctx->dcn_reg_offsets[2] + 0x329c, dccg_regs[0].DWB_GAMUT_REMAPB_C11_C12 = ctx->dcn_reg_offsets[2] + 0x329d, dccg_regs[0].DWB_GAMUT_REMAPB_C13_C14 = ctx->dcn_reg_offsets[2] + 0x329e, dccg_regs[0].DWB_GAMUT_REMAPB_C21_C22 = ctx->dcn_reg_offsets[2] + 0x329f, dccg_regs[0].DWB_GAMUT_REMAPB_C23_C24 = ctx->dcn_reg_offsets[2] + 0x32a0, dccg_regs[0].DWB_GAMUT_REMAPB_C31_C32 = ctx->dcn_reg_offsets[2] + 0x32a1, dccg_regs[0].DWB_GAMUT_REMAPB_C33_C34 = ctx->dcn_reg_offsets[2] + 0x32a2, dccg_regs[0].DWB_OGAM_CONTROL = ctx->dcn_reg_offsets[2] + 0x32a3, dccg_regs[0].DWB_OGAM_LUT_INDEX = ctx->dcn_reg_offsets[2] + 0x32a4, dccg_regs[0].DWB_OGAM_LUT_DATA = ctx->dcn_reg_offsets[2] + 0x32a5, dccg_regs[0].DWB_OGAM_LUT_CONTROL = ctx->dcn_reg_offsets[2] + 0x32a6, dccg_regs[0].DWB_OGAM_RAMA_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32a7, dccg_regs[0].DWB_OGAM_RAMA_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32a8, dccg_regs[0].DWB_OGAM_RAMA_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32a9, dccg_regs[0].DWB_OGAM_RAMA_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32aa, dccg_regs[0].DWB_OGAM_RAMA_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ab, dccg_regs[0].DWB_OGAM_RAMA_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32ac, dccg_regs[0].DWB_OGAM_RAMA_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32ad, dccg_regs[0].DWB_OGAM_RAMA_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32ae, dccg_regs[0].DWB_OGAM_RAMA_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32af, dccg_regs[0].DWB_OGAM_RAMA_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x32b0, dccg_regs[0].DWB_OGAM_RAMA_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x32b1, dccg_regs[0].DWB_OGAM_RAMA_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x32b2, dccg_regs[0].DWB_OGAM_RAMA_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x32b3, dccg_regs[0].DWB_OGAM_RAMA_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x32b4, dccg_regs[0].DWB_OGAM_RAMA_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x32b5, dccg_regs[0].DWB_OGAM_RAMA_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x32b6, dccg_regs[0].DWB_OGAM_RAMA_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x32b7, dccg_regs[0].DWB_OGAM_RAMA_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x32b8, dccg_regs[0].DWB_OGAM_RAMA_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x32b9, dccg_regs[0].DWB_OGAM_RAMA_REGION_2_3 = ctx->dcn_reg_offsets[2] + 0x32ba, dccg_regs[0].DWB_OGAM_RAMA_REGION_4_5 = ctx->dcn_reg_offsets[2] + 0x32bb, dccg_regs[0].DWB_OGAM_RAMA_REGION_6_7 = ctx->dcn_reg_offsets[2] + 0x32bc, dccg_regs[0].DWB_OGAM_RAMA_REGION_8_9 = ctx->dcn_reg_offsets[2] + 0x32bd, dccg_regs[0].DWB_OGAM_RAMA_REGION_10_11 = ctx->dcn_reg_offsets[2] + 0x32be, dccg_regs[0].DWB_OGAM_RAMA_REGION_12_13 = ctx->dcn_reg_offsets[2] + 0x32bf, dccg_regs[0].DWB_OGAM_RAMA_REGION_14_15 = ctx->dcn_reg_offsets[2] + 0x32c0, dccg_regs[0].DWB_OGAM_RAMA_REGION_16_17 = ctx->dcn_reg_offsets[2] + 0x32c1, dccg_regs[0].DWB_OGAM_RAMA_REGION_18_19 = ctx->dcn_reg_offsets[2] + 0x32c2, dccg_regs[0].DWB_OGAM_RAMA_REGION_20_21 = ctx->dcn_reg_offsets[2] + 0x32c3, dccg_regs[0].DWB_OGAM_RAMA_REGION_22_23 = ctx->dcn_reg_offsets[2] + 0x32c4, dccg_regs[0].DWB_OGAM_RAMA_REGION_24_25 = ctx->dcn_reg_offsets[2] + 0x32c5, dccg_regs[0].DWB_OGAM_RAMA_REGION_26_27 = ctx->dcn_reg_offsets[2] + 0x32c6, dccg_regs[0].DWB_OGAM_RAMA_REGION_28_29 = ctx->dcn_reg_offsets[2] + 0x32c7, dccg_regs[0].DWB_OGAM_RAMA_REGION_30_31 = ctx->dcn_reg_offsets[2] + 0x32c8, dccg_regs[0].DWB_OGAM_RAMA_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x32c9, dccg_regs[0].DWB_OGAM_RAMB_START_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ca, dccg_regs[0].DWB_OGAM_RAMB_START_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32cb, dccg_regs[0].DWB_OGAM_RAMB_START_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32cc, dccg_regs[0].DWB_OGAM_RAMB_START_BASE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32cd, dccg_regs[0].DWB_OGAM_RAMB_START_SLOPE_CNTL_B = ctx->dcn_reg_offsets[2] + 0x32ce, dccg_regs[0].DWB_OGAM_RAMB_START_BASE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32cf, dccg_regs[0].DWB_OGAM_RAMB_START_SLOPE_CNTL_G = ctx->dcn_reg_offsets[2] + 0x32d0, dccg_regs[0].DWB_OGAM_RAMB_START_BASE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32d1, dccg_regs[0].DWB_OGAM_RAMB_START_SLOPE_CNTL_R = ctx->dcn_reg_offsets[2] + 0x32d2, dccg_regs[0].DWB_OGAM_RAMB_END_CNTL1_B = ctx->dcn_reg_offsets[2] + 0x32d3, dccg_regs[0].DWB_OGAM_RAMB_END_CNTL2_B = ctx->dcn_reg_offsets[2] + 0x32d4, dccg_regs[0].DWB_OGAM_RAMB_END_CNTL1_G = ctx->dcn_reg_offsets[2] + 0x32d5, dccg_regs[0].DWB_OGAM_RAMB_END_CNTL2_G = ctx->dcn_reg_offsets[2] + 0x32d6, dccg_regs[0].DWB_OGAM_RAMB_END_CNTL1_R = ctx->dcn_reg_offsets[2] + 0x32d7, dccg_regs[0].DWB_OGAM_RAMB_END_CNTL2_R = ctx->dcn_reg_offsets[2] + 0x32d8, dccg_regs[0].DWB_OGAM_RAMB_OFFSET_B = ctx->dcn_reg_offsets[2] + 0x32d9, dccg_regs[0].DWB_OGAM_RAMB_OFFSET_G = ctx->dcn_reg_offsets[2] + 0x32da, dccg_regs[0].DWB_OGAM_RAMB_OFFSET_R = ctx->dcn_reg_offsets[2] + 0x32db, dccg_regs[0].DWB_OGAM_RAMB_REGION_0_1 = ctx->dcn_reg_offsets[2] + 0x32dc, dccg_regs[0].DWB_OGAM_RAMB_REGION_2_3 = ctx->dcn_reg_offsets[2] + 0x32dd, dccg_regs[0].DWB_OGAM_RAMB_REGION_4_5 = ctx->dcn_reg_offsets[2] + 0x32de, dccg_regs[0].DWB_OGAM_RAMB_REGION_6_7 = ctx->dcn_reg_offsets[2] + 0x32df, dccg_regs[0].DWB_OGAM_RAMB_REGION_8_9 = ctx->dcn_reg_offsets[2] + 0x32e0, dccg_regs[0].DWB_OGAM_RAMB_REGION_10_11 = ctx->dcn_reg_offsets[2] + 0x32e1, dccg_regs[0].DWB_OGAM_RAMB_REGION_12_13 = ctx->dcn_reg_offsets[2] + 0x32e2, dccg_regs[0].DWB_OGAM_RAMB_REGION_14_15 = ctx->dcn_reg_offsets[2] + 0x32e3, dccg_regs[0].DWB_OGAM_RAMB_REGION_16_17 = ctx->dcn_reg_offsets[2] + 0x32e4, dccg_regs[0].DWB_OGAM_RAMB_REGION_18_19 = ctx->dcn_reg_offsets[2] + 0x32e5, dccg_regs[0].DWB_OGAM_RAMB_REGION_20_21 = ctx->dcn_reg_offsets[2] + 0x32e6, dccg_regs[0].DWB_OGAM_RAMB_REGION_22_23 = ctx->dcn_reg_offsets[2] + 0x32e7, dccg_regs[0].DWB_OGAM_RAMB_REGION_24_25 = ctx->dcn_reg_offsets[2] + 0x32e8, dccg_regs[0].DWB_OGAM_RAMB_REGION_26_27 = ctx->dcn_reg_offsets[2] + 0x32e9, dccg_regs[0].DWB_OGAM_RAMB_REGION_28_29 = ctx->dcn_reg_offsets[2] + 0x32ea, dccg_regs[0].DWB_OGAM_RAMB_REGION_30_31 = ctx->dcn_reg_offsets[2] + 0x32eb, dccg_regs[0].DWB_OGAM_RAMB_REGION_32_33 = ctx->dcn_reg_offsets[2] + 0x32ec ); |
1529 | |
1530 | dcn30_dwbc_construct(dwbc30, ctx, |
1531 | &dwbc30_regs[i], |
1532 | &dwbc30_shift, |
1533 | &dwbc30_mask, |
1534 | i); |
1535 | |
1536 | pool->dwbc[i] = &dwbc30->base; |
1537 | } |
1538 | return true1; |
1539 | } |
1540 | |
1541 | static bool_Bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) |
1542 | { |
1543 | int i; |
1544 | uint32_t dwb_count = pool->res_cap->num_dwb; |
1545 | |
1546 | for (i = 0; i < dwb_count; i++) { |
1547 | struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), |
1548 | GFP_KERNEL(0x0001 | 0x0004)); |
1549 | |
1550 | if (!mcif_wb30) { |
1551 | dm_error("DC: failed to create mcif_wb30!\n")__drm_err("DC: failed to create mcif_wb30!\n"); |
1552 | return false0; |
1553 | } |
1554 | |
1555 | #undef REG_STRUCTdccg_regs |
1556 | #define REG_STRUCTdccg_regs mcif_wb30_regs |
1557 | mcif_wb_regs_dcn3_init(0)( dccg_regs[0].MCIF_WB_BUFMGR_SW_CONTROL = ctx->dcn_reg_offsets [2] + 0x0272, dccg_regs[0].MCIF_WB_BUFMGR_STATUS = ctx->dcn_reg_offsets [2] + 0x0274, dccg_regs[0].MCIF_WB_BUF_PITCH = ctx->dcn_reg_offsets [2] + 0x0275, dccg_regs[0].MCIF_WB_BUF_1_STATUS = ctx->dcn_reg_offsets [2] + 0x0276, dccg_regs[0].MCIF_WB_BUF_1_STATUS2 = ctx->dcn_reg_offsets [2] + 0x0277, dccg_regs[0].MCIF_WB_BUF_2_STATUS = ctx->dcn_reg_offsets [2] + 0x0278, dccg_regs[0].MCIF_WB_BUF_2_STATUS2 = ctx->dcn_reg_offsets [2] + 0x0279, dccg_regs[0].MCIF_WB_BUF_3_STATUS = ctx->dcn_reg_offsets [2] + 0x027a, dccg_regs[0].MCIF_WB_BUF_3_STATUS2 = ctx->dcn_reg_offsets [2] + 0x027b, dccg_regs[0].MCIF_WB_BUF_4_STATUS = ctx->dcn_reg_offsets [2] + 0x027c, dccg_regs[0].MCIF_WB_BUF_4_STATUS2 = ctx->dcn_reg_offsets [2] + 0x027d, dccg_regs[0].MCIF_WB_ARBITRATION_CONTROL = ctx-> dcn_reg_offsets[2] + 0x027e, dccg_regs[0].MCIF_WB_SCLK_CHANGE = ctx->dcn_reg_offsets[2] + 0x027f, dccg_regs[0].MCIF_WB_TEST_DEBUG_INDEX = ctx->dcn_reg_offsets[2] + 0x0280, dccg_regs[0].MCIF_WB_TEST_DEBUG_DATA = ctx->dcn_reg_offsets[2] + 0x0281, dccg_regs[0].MCIF_WB_BUF_1_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x0282, dccg_regs[0].MCIF_WB_BUF_1_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0284, dccg_regs[0].MCIF_WB_BUF_2_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x0286, dccg_regs[0].MCIF_WB_BUF_2_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0288, dccg_regs[0].MCIF_WB_BUF_3_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x028a, dccg_regs[0].MCIF_WB_BUF_3_ADDR_C = ctx->dcn_reg_offsets[2] + 0x028c, dccg_regs[0].MCIF_WB_BUF_4_ADDR_Y = ctx->dcn_reg_offsets[2] + 0x028e, dccg_regs[0].MCIF_WB_BUF_4_ADDR_C = ctx->dcn_reg_offsets[2] + 0x0290, dccg_regs[0].MCIF_WB_BUFMGR_VCE_CONTROL = ctx->dcn_reg_offsets[2] + 0x0292, dccg_regs[0].MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = ctx->dcn_reg_offsets[2] + 0x02aa, dccg_regs[0].MCIF_WB_NB_PSTATE_CONTROL = ctx->dcn_reg_offsets[2] + 0x0293, dccg_regs[0].MCIF_WB_WATERMARK = ctx->dcn_reg_offsets[2] + 0x02ab, dccg_regs[0].MCIF_WB_CLOCK_GATER_CONTROL = ctx->dcn_reg_offsets[2] + 0x0294, dccg_regs[0].MCIF_WB_SELF_REFRESH_CONTROL = ctx->dcn_reg_offsets[2] + 0x0296, dccg_regs[0].MULTI_LEVEL_QOS_CTRL = ctx->dcn_reg_offsets[2] + 0x0297, dccg_regs[0].MCIF_WB_SECURITY_LEVEL = ctx->dcn_reg_offsets[2] + 0x0298, dccg_regs[0].MCIF_WB_BUF_LUMA_SIZE = ctx->dcn_reg_offsets[2] + 0x0299, dccg_regs[0].MCIF_WB_BUF_CHROMA_SIZE = ctx->dcn_reg_offsets[2] + 0x029a, dccg_regs[0].MCIF_WB_BUF_1_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029b, dccg_regs[0].MCIF_WB_BUF_1_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x029c, dccg_regs[0].MCIF_WB_BUF_2_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029d, dccg_regs[0].MCIF_WB_BUF_2_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x029e, dccg_regs[0].MCIF_WB_BUF_3_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x029f, dccg_regs[0].MCIF_WB_BUF_3_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x02a0, dccg_regs[0].MCIF_WB_BUF_4_ADDR_Y_HIGH = ctx->dcn_reg_offsets[2] + 0x02a1, dccg_regs[0].MCIF_WB_BUF_4_ADDR_C_HIGH = ctx->dcn_reg_offsets[2] + 0x02a2, dccg_regs[0].MCIF_WB_BUF_1_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a3, dccg_regs[0].MCIF_WB_BUF_2_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a4, dccg_regs[0].MCIF_WB_BUF_3_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a5, dccg_regs[0].MCIF_WB_BUF_4_RESOLUTION = ctx->dcn_reg_offsets[2] + 0x02a6, dccg_regs[0].MMHUBBUB_MEM_PWR_CNTL = ctx->dcn_reg_offsets[2] + 0x0340, dccg_regs[0].MMHUBBUB_WARMUP_ADDR_REGION = ctx->dcn_reg_offsets[2] + 0x02b0, dccg_regs[0].MMHUBBUB_WARMUP_BASE_ADDR_HIGH = ctx->dcn_reg_offsets[2] + 0x02af, dccg_regs[0].MMHUBBUB_WARMUP_BASE_ADDR_LOW = ctx->dcn_reg_offsets[2] + 0x02ae, dccg_regs[0].MMHUBBUB_WARMUP_CONTROL_STATUS = ctx->dcn_reg_offsets[2] + 0x02ad ); |
1558 | |
1559 | dcn32_mmhubbub_construct(mcif_wb30, ctx, |
1560 | &mcif_wb30_regs[i], |
1561 | &mcif_wb30_shift, |
1562 | &mcif_wb30_mask, |
1563 | i); |
1564 | |
1565 | pool->mcif_wb[i] = &mcif_wb30->base; |
1566 | } |
1567 | return true1; |
1568 | } |
1569 | |
1570 | static struct display_stream_compressor *dcn32_dsc_create( |
1571 | struct dc_context *ctx, uint32_t inst) |
1572 | { |
1573 | struct dcn20_dsc *dsc = |
1574 | kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL(0x0001 | 0x0004)); |
1575 | |
1576 | if (!dsc) { |
1577 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 1577); do {} while (0); } while (0); |
1578 | return NULL((void *)0); |
1579 | } |
1580 | |
1581 | #undef REG_STRUCTdccg_regs |
1582 | #define REG_STRUCTdccg_regs dsc_regs |
1583 | dsc_regsDCN20_init(0)( dccg_regs[0].DSC_TOP_CONTROL = ctx->dcn_reg_offsets[2] + 0x3000, dccg_regs[0].DSC_DEBUG_CONTROL = ctx->dcn_reg_offsets [2] + 0x3001, dccg_regs[0].DSCC_CONFIG0 = ctx->dcn_reg_offsets [2] + 0x300a, dccg_regs[0].DSCC_CONFIG1 = ctx->dcn_reg_offsets [2] + 0x300b, dccg_regs[0].DSCC_STATUS = ctx->dcn_reg_offsets [2] + 0x300c, dccg_regs[0].DSCC_INTERRUPT_CONTROL_STATUS = ctx ->dcn_reg_offsets[2] + 0x300d, dccg_regs[0].DSCC_PPS_CONFIG0 = ctx->dcn_reg_offsets[2] + 0x300e, dccg_regs[0].DSCC_PPS_CONFIG1 = ctx->dcn_reg_offsets[2] + 0x300f, dccg_regs[0].DSCC_PPS_CONFIG2 = ctx->dcn_reg_offsets[2] + 0x3010, dccg_regs[0].DSCC_PPS_CONFIG3 = ctx->dcn_reg_offsets[2] + 0x3011, dccg_regs[0].DSCC_PPS_CONFIG4 = ctx->dcn_reg_offsets[2] + 0x3012, dccg_regs[0].DSCC_PPS_CONFIG5 = ctx->dcn_reg_offsets[2] + 0x3013, dccg_regs[0].DSCC_PPS_CONFIG6 = ctx->dcn_reg_offsets[2] + 0x3014, dccg_regs[0].DSCC_PPS_CONFIG7 = ctx->dcn_reg_offsets[2] + 0x3015, dccg_regs[0].DSCC_PPS_CONFIG8 = ctx->dcn_reg_offsets[2] + 0x3016, dccg_regs[0].DSCC_PPS_CONFIG9 = ctx->dcn_reg_offsets[2] + 0x3017, dccg_regs[0].DSCC_PPS_CONFIG10 = ctx->dcn_reg_offsets[2] + 0x3018, dccg_regs[0].DSCC_PPS_CONFIG11 = ctx->dcn_reg_offsets[2] + 0x3019, dccg_regs[0].DSCC_PPS_CONFIG12 = ctx->dcn_reg_offsets[2] + 0x301a, dccg_regs[0].DSCC_PPS_CONFIG13 = ctx->dcn_reg_offsets[2] + 0x301b, dccg_regs[0].DSCC_PPS_CONFIG14 = ctx->dcn_reg_offsets[2] + 0x301c, dccg_regs[0].DSCC_PPS_CONFIG15 = ctx->dcn_reg_offsets[2] + 0x301d, dccg_regs[0].DSCC_PPS_CONFIG16 = ctx->dcn_reg_offsets[2] + 0x301e, dccg_regs[0].DSCC_PPS_CONFIG17 = ctx->dcn_reg_offsets[2] + 0x301f, dccg_regs[0].DSCC_PPS_CONFIG18 = ctx->dcn_reg_offsets[2] + 0x3020, dccg_regs[0].DSCC_PPS_CONFIG19 = ctx->dcn_reg_offsets[2] + 0x3021, dccg_regs[0].DSCC_PPS_CONFIG20 = ctx->dcn_reg_offsets[2] + 0x3022, dccg_regs[0].DSCC_PPS_CONFIG21 = ctx->dcn_reg_offsets[2] + 0x3023, dccg_regs[0].DSCC_PPS_CONFIG22 = ctx->dcn_reg_offsets[2] + 0x3024, dccg_regs[0].DSCC_MEM_POWER_CONTROL = ctx->dcn_reg_offsets[2] + 0x3025, dccg_regs[0].DSCC_R_Y_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x3026, dccg_regs[0].DSCC_R_Y_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x3027, dccg_regs[0].DSCC_G_CB_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x3028, dccg_regs[0].DSCC_G_CB_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x3029, dccg_regs[0].DSCC_B_CR_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x302a, dccg_regs[0].DSCC_B_CR_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x302b, dccg_regs[0].DSCC_MAX_ABS_ERROR0 = ctx->dcn_reg_offsets[2] + 0x302c, dccg_regs[0].DSCC_MAX_ABS_ERROR1 = ctx->dcn_reg_offsets[2] + 0x302d, dccg_regs[0].DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x302e, dccg_regs[0].DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x302f, dccg_regs[0].DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3030, dccg_regs[0].DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3031, dccg_regs[0].DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3032, dccg_regs[0].DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3033, dccg_regs[0].DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3034, dccg_regs[0].DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3035, dccg_regs[0].DSCCIF_CONFIG0 = ctx->dcn_reg_offsets[2] + 0x3005, dccg_regs[0].DSCCIF_CONFIG1 = ctx->dcn_reg_offsets[2] + 0x3006, dccg_regs[0].DSCRM_DSC_FORWARD_CONFIG = ctx->dcn_reg_offsets[2] + 0x1a64 ), |
1584 | dsc_regsDCN20_init(1)( dccg_regs[1].DSC_TOP_CONTROL = ctx->dcn_reg_offsets[2] + 0x305c, dccg_regs[1].DSC_DEBUG_CONTROL = ctx->dcn_reg_offsets [2] + 0x305d, dccg_regs[1].DSCC_CONFIG0 = ctx->dcn_reg_offsets [2] + 0x3066, dccg_regs[1].DSCC_CONFIG1 = ctx->dcn_reg_offsets [2] + 0x3067, dccg_regs[1].DSCC_STATUS = ctx->dcn_reg_offsets [2] + 0x3068, dccg_regs[1].DSCC_INTERRUPT_CONTROL_STATUS = ctx ->dcn_reg_offsets[2] + 0x3069, dccg_regs[1].DSCC_PPS_CONFIG0 = ctx->dcn_reg_offsets[2] + 0x306a, dccg_regs[1].DSCC_PPS_CONFIG1 = ctx->dcn_reg_offsets[2] + 0x306b, dccg_regs[1].DSCC_PPS_CONFIG2 = ctx->dcn_reg_offsets[2] + 0x306c, dccg_regs[1].DSCC_PPS_CONFIG3 = ctx->dcn_reg_offsets[2] + 0x306d, dccg_regs[1].DSCC_PPS_CONFIG4 = ctx->dcn_reg_offsets[2] + 0x306e, dccg_regs[1].DSCC_PPS_CONFIG5 = ctx->dcn_reg_offsets[2] + 0x306f, dccg_regs[1].DSCC_PPS_CONFIG6 = ctx->dcn_reg_offsets[2] + 0x3070, dccg_regs[1].DSCC_PPS_CONFIG7 = ctx->dcn_reg_offsets[2] + 0x3071, dccg_regs[1].DSCC_PPS_CONFIG8 = ctx->dcn_reg_offsets[2] + 0x3072, dccg_regs[1].DSCC_PPS_CONFIG9 = ctx->dcn_reg_offsets[2] + 0x3073, dccg_regs[1].DSCC_PPS_CONFIG10 = ctx->dcn_reg_offsets[2] + 0x3074, dccg_regs[1].DSCC_PPS_CONFIG11 = ctx->dcn_reg_offsets[2] + 0x3075, dccg_regs[1].DSCC_PPS_CONFIG12 = ctx->dcn_reg_offsets[2] + 0x3076, dccg_regs[1].DSCC_PPS_CONFIG13 = ctx->dcn_reg_offsets[2] + 0x3077, dccg_regs[1].DSCC_PPS_CONFIG14 = ctx->dcn_reg_offsets[2] + 0x3078, dccg_regs[1].DSCC_PPS_CONFIG15 = ctx->dcn_reg_offsets[2] + 0x3079, dccg_regs[1].DSCC_PPS_CONFIG16 = ctx->dcn_reg_offsets[2] + 0x307a, dccg_regs[1].DSCC_PPS_CONFIG17 = ctx->dcn_reg_offsets[2] + 0x307b, dccg_regs[1].DSCC_PPS_CONFIG18 = ctx->dcn_reg_offsets[2] + 0x307c, dccg_regs[1].DSCC_PPS_CONFIG19 = ctx->dcn_reg_offsets[2] + 0x307d, dccg_regs[1].DSCC_PPS_CONFIG20 = ctx->dcn_reg_offsets[2] + 0x307e, dccg_regs[1].DSCC_PPS_CONFIG21 = ctx->dcn_reg_offsets[2] + 0x307f, dccg_regs[1].DSCC_PPS_CONFIG22 = ctx->dcn_reg_offsets[2] + 0x3080, dccg_regs[1].DSCC_MEM_POWER_CONTROL = ctx->dcn_reg_offsets[2] + 0x3081, dccg_regs[1].DSCC_R_Y_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x3082, dccg_regs[1].DSCC_R_Y_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x3083, dccg_regs[1].DSCC_G_CB_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x3084, dccg_regs[1].DSCC_G_CB_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x3085, dccg_regs[1].DSCC_B_CR_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x3086, dccg_regs[1].DSCC_B_CR_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x3087, dccg_regs[1].DSCC_MAX_ABS_ERROR0 = ctx->dcn_reg_offsets[2] + 0x3088, dccg_regs[1].DSCC_MAX_ABS_ERROR1 = ctx->dcn_reg_offsets[2] + 0x3089, dccg_regs[1].DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x308a, dccg_regs[1].DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x308b, dccg_regs[1].DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x308c, dccg_regs[1].DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x308d, dccg_regs[1].DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x308e, dccg_regs[1].DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x308f, dccg_regs[1].DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3090, dccg_regs[1].DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3091, dccg_regs[1].DSCCIF_CONFIG0 = ctx->dcn_reg_offsets[2] + 0x3061, dccg_regs[1].DSCCIF_CONFIG1 = ctx->dcn_reg_offsets[2] + 0x3062, dccg_regs[1].DSCRM_DSC_FORWARD_CONFIG = ctx->dcn_reg_offsets[2] + 0x1a65 ), |
1585 | dsc_regsDCN20_init(2)( dccg_regs[2].DSC_TOP_CONTROL = ctx->dcn_reg_offsets[2] + 0x30b8, dccg_regs[2].DSC_DEBUG_CONTROL = ctx->dcn_reg_offsets [2] + 0x30b9, dccg_regs[2].DSCC_CONFIG0 = ctx->dcn_reg_offsets [2] + 0x30c2, dccg_regs[2].DSCC_CONFIG1 = ctx->dcn_reg_offsets [2] + 0x30c3, dccg_regs[2].DSCC_STATUS = ctx->dcn_reg_offsets [2] + 0x30c4, dccg_regs[2].DSCC_INTERRUPT_CONTROL_STATUS = ctx ->dcn_reg_offsets[2] + 0x30c5, dccg_regs[2].DSCC_PPS_CONFIG0 = ctx->dcn_reg_offsets[2] + 0x30c6, dccg_regs[2].DSCC_PPS_CONFIG1 = ctx->dcn_reg_offsets[2] + 0x30c7, dccg_regs[2].DSCC_PPS_CONFIG2 = ctx->dcn_reg_offsets[2] + 0x30c8, dccg_regs[2].DSCC_PPS_CONFIG3 = ctx->dcn_reg_offsets[2] + 0x30c9, dccg_regs[2].DSCC_PPS_CONFIG4 = ctx->dcn_reg_offsets[2] + 0x30ca, dccg_regs[2].DSCC_PPS_CONFIG5 = ctx->dcn_reg_offsets[2] + 0x30cb, dccg_regs[2].DSCC_PPS_CONFIG6 = ctx->dcn_reg_offsets[2] + 0x30cc, dccg_regs[2].DSCC_PPS_CONFIG7 = ctx->dcn_reg_offsets[2] + 0x30cd, dccg_regs[2].DSCC_PPS_CONFIG8 = ctx->dcn_reg_offsets[2] + 0x30ce, dccg_regs[2].DSCC_PPS_CONFIG9 = ctx->dcn_reg_offsets[2] + 0x30cf, dccg_regs[2].DSCC_PPS_CONFIG10 = ctx->dcn_reg_offsets[2] + 0x30d0, dccg_regs[2].DSCC_PPS_CONFIG11 = ctx->dcn_reg_offsets[2] + 0x30d1, dccg_regs[2].DSCC_PPS_CONFIG12 = ctx->dcn_reg_offsets[2] + 0x30d2, dccg_regs[2].DSCC_PPS_CONFIG13 = ctx->dcn_reg_offsets[2] + 0x30d3, dccg_regs[2].DSCC_PPS_CONFIG14 = ctx->dcn_reg_offsets[2] + 0x30d4, dccg_regs[2].DSCC_PPS_CONFIG15 = ctx->dcn_reg_offsets[2] + 0x30d5, dccg_regs[2].DSCC_PPS_CONFIG16 = ctx->dcn_reg_offsets[2] + 0x30d6, dccg_regs[2].DSCC_PPS_CONFIG17 = ctx->dcn_reg_offsets[2] + 0x30d7, dccg_regs[2].DSCC_PPS_CONFIG18 = ctx->dcn_reg_offsets[2] + 0x30d8, dccg_regs[2].DSCC_PPS_CONFIG19 = ctx->dcn_reg_offsets[2] + 0x30d9, dccg_regs[2].DSCC_PPS_CONFIG20 = ctx->dcn_reg_offsets[2] + 0x30da, dccg_regs[2].DSCC_PPS_CONFIG21 = ctx->dcn_reg_offsets[2] + 0x30db, dccg_regs[2].DSCC_PPS_CONFIG22 = ctx->dcn_reg_offsets[2] + 0x30dc, dccg_regs[2].DSCC_MEM_POWER_CONTROL = ctx->dcn_reg_offsets[2] + 0x30dd, dccg_regs[2].DSCC_R_Y_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x30de, dccg_regs[2].DSCC_R_Y_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x30df, dccg_regs[2].DSCC_G_CB_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x30e0, dccg_regs[2].DSCC_G_CB_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x30e1, dccg_regs[2].DSCC_B_CR_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x30e2, dccg_regs[2].DSCC_B_CR_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x30e3, dccg_regs[2].DSCC_MAX_ABS_ERROR0 = ctx->dcn_reg_offsets[2] + 0x30e4, dccg_regs[2].DSCC_MAX_ABS_ERROR1 = ctx->dcn_reg_offsets[2] + 0x30e5, dccg_regs[2].DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x30e6, dccg_regs[2].DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x30e7, dccg_regs[2].DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x30e8, dccg_regs[2].DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x30e9, dccg_regs[2].DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x30ea, dccg_regs[2].DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x30eb, dccg_regs[2].DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x30ec, dccg_regs[2].DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x30ed, dccg_regs[2].DSCCIF_CONFIG0 = ctx->dcn_reg_offsets[2] + 0x30bd, dccg_regs[2].DSCCIF_CONFIG1 = ctx->dcn_reg_offsets[2] + 0x30be, dccg_regs[2].DSCRM_DSC_FORWARD_CONFIG = ctx->dcn_reg_offsets[2] + 0x1a66 ), |
1586 | dsc_regsDCN20_init(3)( dccg_regs[3].DSC_TOP_CONTROL = ctx->dcn_reg_offsets[2] + 0x3114, dccg_regs[3].DSC_DEBUG_CONTROL = ctx->dcn_reg_offsets [2] + 0x3115, dccg_regs[3].DSCC_CONFIG0 = ctx->dcn_reg_offsets [2] + 0x311e, dccg_regs[3].DSCC_CONFIG1 = ctx->dcn_reg_offsets [2] + 0x311f, dccg_regs[3].DSCC_STATUS = ctx->dcn_reg_offsets [2] + 0x3120, dccg_regs[3].DSCC_INTERRUPT_CONTROL_STATUS = ctx ->dcn_reg_offsets[2] + 0x3121, dccg_regs[3].DSCC_PPS_CONFIG0 = ctx->dcn_reg_offsets[2] + 0x3122, dccg_regs[3].DSCC_PPS_CONFIG1 = ctx->dcn_reg_offsets[2] + 0x3123, dccg_regs[3].DSCC_PPS_CONFIG2 = ctx->dcn_reg_offsets[2] + 0x3124, dccg_regs[3].DSCC_PPS_CONFIG3 = ctx->dcn_reg_offsets[2] + 0x3125, dccg_regs[3].DSCC_PPS_CONFIG4 = ctx->dcn_reg_offsets[2] + 0x3126, dccg_regs[3].DSCC_PPS_CONFIG5 = ctx->dcn_reg_offsets[2] + 0x3127, dccg_regs[3].DSCC_PPS_CONFIG6 = ctx->dcn_reg_offsets[2] + 0x3128, dccg_regs[3].DSCC_PPS_CONFIG7 = ctx->dcn_reg_offsets[2] + 0x3129, dccg_regs[3].DSCC_PPS_CONFIG8 = ctx->dcn_reg_offsets[2] + 0x312a, dccg_regs[3].DSCC_PPS_CONFIG9 = ctx->dcn_reg_offsets[2] + 0x312b, dccg_regs[3].DSCC_PPS_CONFIG10 = ctx->dcn_reg_offsets[2] + 0x312c, dccg_regs[3].DSCC_PPS_CONFIG11 = ctx->dcn_reg_offsets[2] + 0x312d, dccg_regs[3].DSCC_PPS_CONFIG12 = ctx->dcn_reg_offsets[2] + 0x312e, dccg_regs[3].DSCC_PPS_CONFIG13 = ctx->dcn_reg_offsets[2] + 0x312f, dccg_regs[3].DSCC_PPS_CONFIG14 = ctx->dcn_reg_offsets[2] + 0x3130, dccg_regs[3].DSCC_PPS_CONFIG15 = ctx->dcn_reg_offsets[2] + 0x3131, dccg_regs[3].DSCC_PPS_CONFIG16 = ctx->dcn_reg_offsets[2] + 0x3132, dccg_regs[3].DSCC_PPS_CONFIG17 = ctx->dcn_reg_offsets[2] + 0x3133, dccg_regs[3].DSCC_PPS_CONFIG18 = ctx->dcn_reg_offsets[2] + 0x3134, dccg_regs[3].DSCC_PPS_CONFIG19 = ctx->dcn_reg_offsets[2] + 0x3135, dccg_regs[3].DSCC_PPS_CONFIG20 = ctx->dcn_reg_offsets[2] + 0x3136, dccg_regs[3].DSCC_PPS_CONFIG21 = ctx->dcn_reg_offsets[2] + 0x3137, dccg_regs[3].DSCC_PPS_CONFIG22 = ctx->dcn_reg_offsets[2] + 0x3138, dccg_regs[3].DSCC_MEM_POWER_CONTROL = ctx->dcn_reg_offsets[2] + 0x3139, dccg_regs[3].DSCC_R_Y_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x313a, dccg_regs[3].DSCC_R_Y_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x313b, dccg_regs[3].DSCC_G_CB_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x313c, dccg_regs[3].DSCC_G_CB_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x313d, dccg_regs[3].DSCC_B_CR_SQUARED_ERROR_LOWER = ctx->dcn_reg_offsets[2] + 0x313e, dccg_regs[3].DSCC_B_CR_SQUARED_ERROR_UPPER = ctx->dcn_reg_offsets[2] + 0x313f, dccg_regs[3].DSCC_MAX_ABS_ERROR0 = ctx->dcn_reg_offsets[2] + 0x3140, dccg_regs[3].DSCC_MAX_ABS_ERROR1 = ctx->dcn_reg_offsets[2] + 0x3141, dccg_regs[3].DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3142, dccg_regs[3].DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3143, dccg_regs[3].DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3144, dccg_regs[3].DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3145, dccg_regs[3].DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3146, dccg_regs[3].DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3147, dccg_regs[3].DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3148, dccg_regs[3].DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = ctx->dcn_reg_offsets[2] + 0x3149, dccg_regs[3].DSCCIF_CONFIG0 = ctx->dcn_reg_offsets[2] + 0x3119, dccg_regs[3].DSCCIF_CONFIG1 = ctx->dcn_reg_offsets[2] + 0x311a, dccg_regs[3].DSCRM_DSC_FORWARD_CONFIG = ctx->dcn_reg_offsets[2] + 0x1a67 ); |
1587 | |
1588 | dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); |
1589 | |
1590 | dsc->max_image_width = 6016; |
1591 | |
1592 | return &dsc->base; |
1593 | } |
1594 | |
1595 | static void dcn32_destroy_resource_pool(struct resource_pool **pool) |
1596 | { |
1597 | struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool)({ const __typeof( ((struct dcn32_resource_pool *)0)->base ) *__mptr = (*pool); (struct dcn32_resource_pool *)( (char * )__mptr - __builtin_offsetof(struct dcn32_resource_pool, base ) );}); |
1598 | |
1599 | dcn32_resource_destruct(dcn32_pool); |
1600 | kfree(dcn32_pool); |
1601 | *pool = NULL((void *)0); |
1602 | } |
1603 | |
1604 | bool_Bool dcn32_acquire_post_bldn_3dlut( |
1605 | struct resource_context *res_ctx, |
1606 | const struct resource_pool *pool, |
1607 | int mpcc_id, |
1608 | struct dc_3dlut **lut, |
1609 | struct dc_transfer_func **shaper) |
1610 | { |
1611 | bool_Bool ret = false0; |
1612 | union dc_3dlut_state *state; |
1613 | |
1614 | ASSERT(*lut == NULL && *shaper == NULL)do { if (({ static int __warned; int __ret = !!(!(*lut == ((void *)0) && *shaper == ((void *)0))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(*lut == ((void *)0) && *shaper == ((void *)0))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c" , 1614); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1615 | *lut = NULL((void *)0); |
1616 | *shaper = NULL((void *)0); |
1617 | |
1618 | if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) { |
1619 | *lut = pool->mpc_lut[mpcc_id]; |
1620 | *shaper = pool->mpc_shaper[mpcc_id]; |
1621 | state = &pool->mpc_lut[mpcc_id]->state; |
1622 | res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true1; |
1623 | ret = true1; |
1624 | } |
1625 | return ret; |
1626 | } |
1627 | |
1628 | bool_Bool dcn32_release_post_bldn_3dlut( |
1629 | struct resource_context *res_ctx, |
1630 | const struct resource_pool *pool, |
1631 | struct dc_3dlut **lut, |
1632 | struct dc_transfer_func **shaper) |
1633 | { |
1634 | int i; |
1635 | bool_Bool ret = false0; |
1636 | |
1637 | for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { |
1638 | if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { |
1639 | res_ctx->is_mpc_3dlut_acquired[i] = false0; |
1640 | pool->mpc_lut[i]->state.raw = 0; |
1641 | *lut = NULL((void *)0); |
1642 | *shaper = NULL((void *)0); |
1643 | ret = true1; |
1644 | break; |
1645 | } |
1646 | } |
1647 | return ret; |
1648 | } |
1649 | |
1650 | static void dcn32_enable_phantom_plane(struct dc *dc, |
1651 | struct dc_state *context, |
1652 | struct dc_stream_state *phantom_stream, |
1653 | unsigned int dc_pipe_idx) |
1654 | { |
1655 | struct dc_plane_state *phantom_plane = NULL((void *)0); |
1656 | struct dc_plane_state *prev_phantom_plane = NULL((void *)0); |
1657 | struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; |
1658 | |
1659 | while (curr_pipe) { |
1660 | if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) |
1661 | phantom_plane = prev_phantom_plane; |
1662 | else |
1663 | phantom_plane = dc_create_plane_state(dc); |
1664 | |
1665 | memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address))__builtin_memcpy((&phantom_plane->address), (&curr_pipe ->plane_state->address), (sizeof(phantom_plane->address ))); |
1666 | memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,__builtin_memcpy((&phantom_plane->scaling_quality), (& curr_pipe->plane_state->scaling_quality), (sizeof(phantom_plane ->scaling_quality))) |
1667 | sizeof(phantom_plane->scaling_quality))__builtin_memcpy((&phantom_plane->scaling_quality), (& curr_pipe->plane_state->scaling_quality), (sizeof(phantom_plane ->scaling_quality))); |
1668 | memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect))__builtin_memcpy((&phantom_plane->src_rect), (&curr_pipe ->plane_state->src_rect), (sizeof(phantom_plane->src_rect ))); |
1669 | memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect))__builtin_memcpy((&phantom_plane->dst_rect), (&curr_pipe ->plane_state->dst_rect), (sizeof(phantom_plane->dst_rect ))); |
1670 | memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect))__builtin_memcpy((&phantom_plane->clip_rect), (&curr_pipe ->plane_state->clip_rect), (sizeof(phantom_plane->clip_rect ))); |
1671 | memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,__builtin_memcpy((&phantom_plane->plane_size), (&curr_pipe ->plane_state->plane_size), (sizeof(phantom_plane->plane_size ))) |
1672 | sizeof(phantom_plane->plane_size))__builtin_memcpy((&phantom_plane->plane_size), (&curr_pipe ->plane_state->plane_size), (sizeof(phantom_plane->plane_size ))); |
1673 | memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,__builtin_memcpy((&phantom_plane->tiling_info), (& curr_pipe->plane_state->tiling_info), (sizeof(phantom_plane ->tiling_info))) |
1674 | sizeof(phantom_plane->tiling_info))__builtin_memcpy((&phantom_plane->tiling_info), (& curr_pipe->plane_state->tiling_info), (sizeof(phantom_plane ->tiling_info))); |
1675 | memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc))__builtin_memcpy((&phantom_plane->dcc), (&curr_pipe ->plane_state->dcc), (sizeof(phantom_plane->dcc))); |
1676 | phantom_plane->format = curr_pipe->plane_state->format; |
1677 | phantom_plane->rotation = curr_pipe->plane_state->rotation; |
1678 | phantom_plane->visible = curr_pipe->plane_state->visible; |
1679 | |
1680 | /* Shadow pipe has small viewport. */ |
1681 | phantom_plane->clip_rect.y = 0; |
1682 | phantom_plane->clip_rect.height = phantom_stream->timing.v_addressable; |
1683 | |
1684 | phantom_plane->is_phantom = true1; |
1685 | |
1686 | dc_add_plane_to_context(dc, phantom_stream, phantom_plane, context); |
1687 | |
1688 | curr_pipe = curr_pipe->bottom_pipe; |
1689 | prev_phantom_plane = phantom_plane; |
1690 | } |
1691 | } |
1692 | |
1693 | static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc, |
1694 | struct dc_state *context, |
1695 | display_e2e_pipe_params_st *pipes, |
1696 | unsigned int pipe_cnt, |
1697 | unsigned int dc_pipe_idx) |
1698 | { |
1699 | struct dc_stream_state *phantom_stream = NULL((void *)0); |
1700 | struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx]; |
1701 | |
1702 | phantom_stream = dc_create_stream_for_sink(ref_pipe->stream->sink); |
1703 | phantom_stream->signal = SIGNAL_TYPE_VIRTUAL; |
1704 | phantom_stream->dpms_off = true1; |
1705 | phantom_stream->mall_stream_config.type = SUBVP_PHANTOM; |
1706 | phantom_stream->mall_stream_config.paired_stream = ref_pipe->stream; |
1707 | ref_pipe->stream->mall_stream_config.type = SUBVP_MAIN; |
1708 | ref_pipe->stream->mall_stream_config.paired_stream = phantom_stream; |
1709 | |
1710 | /* stream has limited viewport and small timing */ |
1711 | memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing))__builtin_memcpy((&phantom_stream->timing), (&ref_pipe ->stream->timing), (sizeof(phantom_stream->timing))); |
1712 | memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src))__builtin_memcpy((&phantom_stream->src), (&ref_pipe ->stream->src), (sizeof(phantom_stream->src))); |
1713 | memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst))__builtin_memcpy((&phantom_stream->dst), (&ref_pipe ->stream->dst), (sizeof(phantom_stream->dst))); |
1714 | DC_FP_START()dc_fpu_begin(__func__, 1714); |
1715 | dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx); |
1716 | DC_FP_END()dc_fpu_end(__func__, 1716); |
1717 | |
1718 | dc_add_stream_to_ctx(dc, context, phantom_stream); |
1719 | return phantom_stream; |
1720 | } |
1721 | |
1722 | void dcn32_retain_phantom_pipes(struct dc *dc, struct dc_state *context) |
1723 | { |
1724 | int i; |
1725 | struct dc_plane_state *phantom_plane = NULL((void *)0); |
1726 | struct dc_stream_state *phantom_stream = NULL((void *)0); |
1727 | |
1728 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
1729 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
1730 | |
1731 | if (!pipe->top_pipe && !pipe->prev_odm_pipe && |
1732 | pipe->plane_state && pipe->stream && |
1733 | pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { |
1734 | phantom_plane = pipe->plane_state; |
1735 | phantom_stream = pipe->stream; |
1736 | |
1737 | dc_plane_state_retain(phantom_plane); |
1738 | dc_stream_retain(phantom_stream); |
1739 | } |
1740 | } |
1741 | } |
1742 | |
1743 | // return true if removed piped from ctx, false otherwise |
1744 | bool_Bool dcn32_remove_phantom_pipes(struct dc *dc, struct dc_state *context) |
1745 | { |
1746 | int i; |
1747 | bool_Bool removed_pipe = false0; |
1748 | struct dc_plane_state *phantom_plane = NULL((void *)0); |
1749 | struct dc_stream_state *phantom_stream = NULL((void *)0); |
1750 | |
1751 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
1752 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
1753 | // build scaling params for phantom pipes |
1754 | if (pipe->plane_state && pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { |
1755 | phantom_plane = pipe->plane_state; |
1756 | phantom_stream = pipe->stream; |
1757 | |
1758 | dc_rem_all_planes_for_stream(dc, pipe->stream, context); |
1759 | dc_remove_stream_from_ctx(dc, context, pipe->stream); |
1760 | |
1761 | /* Ref count is incremented on allocation and also when added to the context. |
1762 | * Therefore we must call release for the the phantom plane and stream once |
1763 | * they are removed from the ctx to finally decrement the refcount to 0 to free. |
1764 | */ |
1765 | dc_plane_state_release(phantom_plane); |
1766 | dc_stream_release(phantom_stream); |
1767 | |
1768 | removed_pipe = true1; |
1769 | } |
1770 | |
1771 | // Clear all phantom stream info |
1772 | if (pipe->stream) { |
1773 | pipe->stream->mall_stream_config.type = SUBVP_NONE; |
1774 | pipe->stream->mall_stream_config.paired_stream = NULL((void *)0); |
1775 | } |
1776 | |
1777 | if (pipe->plane_state) { |
1778 | pipe->plane_state->is_phantom = false0; |
1779 | } |
1780 | } |
1781 | return removed_pipe; |
1782 | } |
1783 | |
1784 | /* TODO: Input to this function should indicate which pipe indexes (or streams) |
1785 | * require a phantom pipe / stream |
1786 | */ |
1787 | void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, |
1788 | display_e2e_pipe_params_st *pipes, |
1789 | unsigned int pipe_cnt, |
1790 | unsigned int index) |
1791 | { |
1792 | struct dc_stream_state *phantom_stream = NULL((void *)0); |
1793 | unsigned int i; |
1794 | |
1795 | // The index of the DC pipe passed into this function is guarenteed to |
1796 | // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't |
1797 | // already have phantom pipe assigned, etc.) by previous checks. |
1798 | phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); |
1799 | dcn32_enable_phantom_plane(dc, context, phantom_stream, index); |
1800 | |
1801 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
1802 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
1803 | |
1804 | // Build scaling params for phantom pipes which were newly added. |
1805 | // We determine which phantom pipes were added by comparing with |
1806 | // the phantom stream. |
1807 | if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream && |
1808 | pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { |
1809 | pipe->stream->use_dynamic_meta = false0; |
1810 | pipe->plane_state->flip_immediate = false0; |
1811 | if (!resource_build_scaling_params(pipe)) { |
1812 | // Log / remove phantom pipes since failed to build scaling params |
1813 | } |
1814 | } |
1815 | } |
1816 | } |
1817 | |
1818 | bool_Bool dcn32_validate_bandwidth(struct dc *dc, |
1819 | struct dc_state *context, |
1820 | bool_Bool fast_validate) |
1821 | { |
1822 | bool_Bool out = false0; |
1823 | |
1824 | BW_VAL_TRACE_SETUP()unsigned long long end_tick = 0; unsigned long long voltage_level_tick = 0; unsigned long long watermark_tick = 0; unsigned long long start_tick = dc->debug.bw_val_profile.enable ? dm_get_timestamp (dc->ctx) : 0; |
1825 | |
1826 | int vlevel = 0; |
1827 | int pipe_cnt = 0; |
1828 | display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL(0x0001 | 0x0004)); |
1829 | struct mall_temp_config mall_temp_config; |
1830 | |
1831 | /* To handle Freesync properly, setting FreeSync DML parameters |
1832 | * to its default state for the first stage of validation |
1833 | */ |
1834 | context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false0; |
1835 | context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true1; |
1836 | |
1837 | DC_LOGGER_INIT(dc->ctx->logger); |
1838 | |
1839 | /* For fast validation, there are situations where a shallow copy of |
1840 | * of the dc->current_state is created for the validation. In this case |
1841 | * we want to save and restore the mall config because we always |
1842 | * teardown subvp at the beginning of validation (and don't attempt |
1843 | * to add it back if it's fast validation). If we don't restore the |
1844 | * subvp config in cases of fast validation + shallow copy of the |
1845 | * dc->current_state, the dc->current_state will have a partially |
1846 | * removed subvp state when we did not intend to remove it. |
1847 | */ |
1848 | if (fast_validate) { |
1849 | memset(&mall_temp_config, 0, sizeof(mall_temp_config))__builtin_memset((&mall_temp_config), (0), (sizeof(mall_temp_config ))); |
1850 | dcn32_save_mall_state(dc, context, &mall_temp_config); |
1851 | } |
1852 | |
1853 | BW_VAL_TRACE_COUNT()if (dc->debug.bw_val_profile.enable) dc->debug.bw_val_profile .total_count++; |
1854 | |
1855 | DC_FP_START()dc_fpu_begin(__func__, 1855); |
1856 | out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); |
1857 | DC_FP_END()dc_fpu_end(__func__, 1857); |
1858 | |
1859 | if (fast_validate) |
1860 | dcn32_restore_mall_state(dc, context, &mall_temp_config); |
1861 | |
1862 | if (pipe_cnt == 0) |
1863 | goto validate_out; |
1864 | |
1865 | if (!out) |
1866 | goto validate_fail; |
1867 | |
1868 | BW_VAL_TRACE_END_VOLTAGE_LEVEL()if (dc->debug.bw_val_profile.enable) voltage_level_tick = dm_get_timestamp (dc->ctx); |
1869 | |
1870 | if (fast_validate) { |
1871 | BW_VAL_TRACE_SKIP(fast)if (dc->debug.bw_val_profile.enable) { if (!voltage_level_tick ) voltage_level_tick = dm_get_timestamp(dc->ctx); dc->debug .bw_val_profile.skip_fast_count++; }; |
1872 | goto validate_out; |
1873 | } |
1874 | |
1875 | dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); |
1876 | |
1877 | BW_VAL_TRACE_END_WATERMARKS()if (dc->debug.bw_val_profile.enable) watermark_tick = dm_get_timestamp (dc->ctx); |
1878 | |
1879 | goto validate_out; |
1880 | |
1881 | validate_fail: |
1882 | DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",printk("\0014" "[" "drm" "] " "Mode Validation Warning: %s failed validation.\n" , dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus [context->bw_ctx.dml.vba.soc.num_states])) |
1883 | dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]))printk("\0014" "[" "drm" "] " "Mode Validation Warning: %s failed validation.\n" , dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus [context->bw_ctx.dml.vba.soc.num_states])); |
1884 | |
1885 | BW_VAL_TRACE_SKIP(fail)if (dc->debug.bw_val_profile.enable) { if (!voltage_level_tick ) voltage_level_tick = dm_get_timestamp(dc->ctx); dc->debug .bw_val_profile.skip_fail_count++; }; |
1886 | out = false0; |
1887 | |
1888 | validate_out: |
1889 | kfree(pipes); |
1890 | |
1891 | BW_VAL_TRACE_FINISH()if (dc->debug.bw_val_profile.enable) { end_tick = dm_get_timestamp (dc->ctx); dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; if (watermark_tick) { dc ->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; } }; |
1892 | |
1893 | return out; |
1894 | } |
1895 | |
1896 | int dcn32_populate_dml_pipes_from_context( |
1897 | struct dc *dc, struct dc_state *context, |
1898 | display_e2e_pipe_params_st *pipes, |
1899 | bool_Bool fast_validate) |
1900 | { |
1901 | int i, pipe_cnt; |
1902 | struct resource_context *res_ctx = &context->res_ctx; |
1903 | struct pipe_ctx *pipe; |
1904 | bool_Bool subvp_in_use = false0; |
1905 | uint8_t is_pipe_split_expected[MAX_PIPES6] = {0}; |
1906 | struct dc_crtc_timing *timing; |
1907 | bool_Bool vsr_odm_support = false0; |
1908 | |
1909 | dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); |
1910 | |
1911 | /* Determine whether we will apply ODM 2to1 policy: |
1912 | * Applies to single display and where the number of planes is less than 3. |
1913 | * For 3 plane case ( 2 MPO planes ), we will not set the policy for the MPO pipes. |
1914 | * |
1915 | * Apply pipe split policy first so we can predict the pipe split correctly |
1916 | * (dcn32_predict_pipe_split). |
1917 | */ |
1918 | for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { |
1919 | if (!res_ctx->pipe_ctx[i].stream) |
1920 | continue; |
1921 | pipe = &res_ctx->pipe_ctx[i]; |
1922 | timing = &pipe->stream->timing; |
Value stored to 'timing' is never read | |
1923 | |
1924 | pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; |
1925 | vsr_odm_support = (res_ctx->pipe_ctx[i].stream->src.width >= 5120 && |
1926 | res_ctx->pipe_ctx[i].stream->src.width > res_ctx->pipe_ctx[i].stream->dst.width); |
1927 | if (context->stream_count == 1 && |
1928 | context->stream_status[0].plane_count == 1 && |
1929 | !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && |
1930 | is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && |
1931 | pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ717000000 && |
1932 | dc->debug.enable_single_display_2to1_odm_policy && |
1933 | !vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr |
1934 | pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; |
1935 | } |
1936 | pipe_cnt++; |
1937 | } |
1938 | |
1939 | for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { |
1940 | |
1941 | if (!res_ctx->pipe_ctx[i].stream) |
1942 | continue; |
1943 | pipe = &res_ctx->pipe_ctx[i]; |
1944 | timing = &pipe->stream->timing; |
1945 | |
1946 | pipes[pipe_cnt].pipe.src.gpuvm = true1; |
1947 | DC_FP_START()dc_fpu_begin(__func__, 1947); |
1948 | dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt); |
1949 | DC_FP_END()dc_fpu_end(__func__, 1949); |
1950 | pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; |
1951 | pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet |
1952 | pipes[pipe_cnt].pipe.src.unbounded_req_mode = false0; |
1953 | pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19; |
1954 | |
1955 | switch (pipe->stream->mall_stream_config.type) { |
1956 | case SUBVP_MAIN: |
1957 | pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport; |
1958 | subvp_in_use = true1; |
1959 | break; |
1960 | case SUBVP_PHANTOM: |
1961 | pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe; |
1962 | pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; |
1963 | // Disallow unbounded req for SubVP according to DCHUB programming guide |
1964 | pipes[pipe_cnt].pipe.src.unbounded_req_mode = false0; |
1965 | break; |
1966 | case SUBVP_NONE: |
1967 | pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable; |
1968 | pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable; |
1969 | break; |
1970 | default: |
1971 | break; |
1972 | } |
1973 | |
1974 | pipes[pipe_cnt].dout.dsc_input_bpc = 0; |
1975 | if (pipes[pipe_cnt].dout.dsc_enable) { |
1976 | switch (timing->display_color_depth) { |
1977 | case COLOR_DEPTH_888: |
1978 | pipes[pipe_cnt].dout.dsc_input_bpc = 8; |
1979 | break; |
1980 | case COLOR_DEPTH_101010: |
1981 | pipes[pipe_cnt].dout.dsc_input_bpc = 10; |
1982 | break; |
1983 | case COLOR_DEPTH_121212: |
1984 | pipes[pipe_cnt].dout.dsc_input_bpc = 12; |
1985 | break; |
1986 | default: |
1987 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c" , 1987); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1988 | break; |
1989 | } |
1990 | } |
1991 | |
1992 | DC_FP_START()dc_fpu_begin(__func__, 1992); |
1993 | is_pipe_split_expected[i] = dcn32_predict_pipe_split(context, &pipes[pipe_cnt]); |
1994 | DC_FP_END()dc_fpu_end(__func__, 1994); |
1995 | |
1996 | pipe_cnt++; |
1997 | } |
1998 | |
1999 | /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all |
2000 | * the DET available for each pipe). Use the DET override input to maintain our driver |
2001 | * policy. |
2002 | */ |
2003 | dcn32_set_det_allocations(dc, context, pipes); |
2004 | |
2005 | // In general cases we want to keep the dram clock change requirement |
2006 | // (prefer configs that support MCLK switch). Only override to false |
2007 | // for SubVP |
2008 | if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use) |
2009 | context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false0; |
2010 | else |
2011 | context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true1; |
2012 | |
2013 | return pipe_cnt; |
2014 | } |
2015 | |
2016 | static struct dc_cap_funcs cap_funcs = { |
2017 | .get_dcc_compression_cap = dcn20_get_dcc_compression_cap |
2018 | }; |
2019 | |
2020 | void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, |
2021 | display_e2e_pipe_params_st *pipes, |
2022 | int pipe_cnt, |
2023 | int vlevel) |
2024 | { |
2025 | DC_FP_START()dc_fpu_begin(__func__, 2025); |
2026 | dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel); |
2027 | DC_FP_END()dc_fpu_end(__func__, 2027); |
2028 | } |
2029 | |
2030 | static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) |
2031 | { |
2032 | DC_FP_START()dc_fpu_begin(__func__, 2032); |
2033 | dcn32_update_bw_bounding_box_fpu(dc, bw_params); |
2034 | DC_FP_END()dc_fpu_end(__func__, 2034); |
2035 | } |
2036 | |
2037 | static struct resource_funcs dcn32_res_pool_funcs = { |
2038 | .destroy = dcn32_destroy_resource_pool, |
2039 | .link_enc_create = dcn32_link_encoder_create, |
2040 | .link_enc_create_minimal = NULL((void *)0), |
2041 | .panel_cntl_create = dcn32_panel_cntl_create, |
2042 | .validate_bandwidth = dcn32_validate_bandwidth, |
2043 | .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg, |
2044 | .populate_dml_pipes = dcn32_populate_dml_pipes_from_context, |
2045 | .acquire_idle_pipe_for_head_pipe_in_layer = dcn32_acquire_idle_pipe_for_head_pipe_in_layer, |
2046 | .add_stream_to_ctx = dcn30_add_stream_to_ctx, |
2047 | .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, |
2048 | .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, |
2049 | .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, |
2050 | .set_mcif_arb_params = dcn30_set_mcif_arb_params, |
2051 | .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, |
2052 | .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, |
2053 | .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, |
2054 | .update_bw_bounding_box = dcn32_update_bw_bounding_box, |
2055 | .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, |
2056 | .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, |
2057 | .add_phantom_pipes = dcn32_add_phantom_pipes, |
2058 | .remove_phantom_pipes = dcn32_remove_phantom_pipes, |
2059 | .retain_phantom_pipes = dcn32_retain_phantom_pipes, |
2060 | }; |
2061 | |
2062 | static uint32_t read_pipe_fuses(struct dc_context *ctx) |
2063 | { |
2064 | uint32_t value = REG_READ(CC_DC_PIPE_DIS)dm_read_reg_func(ctx, (ctx->dcn_reg_offsets[2] + 0x00ca), __func__ ); |
2065 | /* DCN32 support max 4 pipes */ |
2066 | value = value & 0xf; |
2067 | return value; |
2068 | } |
2069 | |
2070 | |
2071 | static bool_Bool dcn32_resource_construct( |
2072 | uint8_t num_virtual_links, |
2073 | struct dc *dc, |
2074 | struct dcn32_resource_pool *pool) |
2075 | { |
2076 | int i, j; |
2077 | struct dc_context *ctx = dc->ctx; |
2078 | struct irq_service_init_data init_data; |
2079 | struct ddc_service_init_data ddc_init_data = {0}; |
2080 | uint32_t pipe_fuses = 0; |
2081 | uint32_t num_pipes = 4; |
2082 | |
2083 | #undef REG_STRUCTdccg_regs |
2084 | #define REG_STRUCTdccg_regs bios_regs |
2085 | bios_regs_init()( dccg_regs.BIOS_SCRATCH_3 = ctx->nbio_reg_offsets[1] + 0x003b , dccg_regs.BIOS_SCRATCH_6 = ctx->nbio_reg_offsets[1] + 0x003e ); |
2086 | |
2087 | #undef REG_STRUCTdccg_regs |
2088 | #define REG_STRUCTdccg_regs clk_src_regs |
2089 | clk_src_regs_init(0, A)( dccg_regs[0].PIXCLK_RESYNC_CNTL = ctx->dcn_reg_offsets[1 ] + 0x0040, dccg_regs[0].PHASE[0] = ctx->dcn_reg_offsets[1 ] + 0x0081, dccg_regs[0].PHASE[1] = ctx->dcn_reg_offsets[1 ] + 0x0085, dccg_regs[0].PHASE[2] = ctx->dcn_reg_offsets[1 ] + 0x0089, dccg_regs[0].PHASE[3] = ctx->dcn_reg_offsets[1 ] + 0x008d, dccg_regs[0].MODULO[0] = ctx->dcn_reg_offsets[ 1] + 0x0082, dccg_regs[0].MODULO[1] = ctx->dcn_reg_offsets [1] + 0x0086, dccg_regs[0].MODULO[2] = ctx->dcn_reg_offsets [1] + 0x008a, dccg_regs[0].MODULO[3] = ctx->dcn_reg_offsets [1] + 0x008e, dccg_regs[0].PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs[0].PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs[0].PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs[0].PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c ), |
2090 | clk_src_regs_init(1, B)( dccg_regs[1].PIXCLK_RESYNC_CNTL = ctx->dcn_reg_offsets[1 ] + 0x0041, dccg_regs[1].PHASE[0] = ctx->dcn_reg_offsets[1 ] + 0x0081, dccg_regs[1].PHASE[1] = ctx->dcn_reg_offsets[1 ] + 0x0085, dccg_regs[1].PHASE[2] = ctx->dcn_reg_offsets[1 ] + 0x0089, dccg_regs[1].PHASE[3] = ctx->dcn_reg_offsets[1 ] + 0x008d, dccg_regs[1].MODULO[0] = ctx->dcn_reg_offsets[ 1] + 0x0082, dccg_regs[1].MODULO[1] = ctx->dcn_reg_offsets [1] + 0x0086, dccg_regs[1].MODULO[2] = ctx->dcn_reg_offsets [1] + 0x008a, dccg_regs[1].MODULO[3] = ctx->dcn_reg_offsets [1] + 0x008e, dccg_regs[1].PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs[1].PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs[1].PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs[1].PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c ), |
2091 | clk_src_regs_init(2, C)( dccg_regs[2].PIXCLK_RESYNC_CNTL = ctx->dcn_reg_offsets[1 ] + 0x0042, dccg_regs[2].PHASE[0] = ctx->dcn_reg_offsets[1 ] + 0x0081, dccg_regs[2].PHASE[1] = ctx->dcn_reg_offsets[1 ] + 0x0085, dccg_regs[2].PHASE[2] = ctx->dcn_reg_offsets[1 ] + 0x0089, dccg_regs[2].PHASE[3] = ctx->dcn_reg_offsets[1 ] + 0x008d, dccg_regs[2].MODULO[0] = ctx->dcn_reg_offsets[ 1] + 0x0082, dccg_regs[2].MODULO[1] = ctx->dcn_reg_offsets [1] + 0x0086, dccg_regs[2].MODULO[2] = ctx->dcn_reg_offsets [1] + 0x008a, dccg_regs[2].MODULO[3] = ctx->dcn_reg_offsets [1] + 0x008e, dccg_regs[2].PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs[2].PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs[2].PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs[2].PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c ), |
2092 | clk_src_regs_init(3, D)( dccg_regs[3].PIXCLK_RESYNC_CNTL = ctx->dcn_reg_offsets[1 ] + 0x0043, dccg_regs[3].PHASE[0] = ctx->dcn_reg_offsets[1 ] + 0x0081, dccg_regs[3].PHASE[1] = ctx->dcn_reg_offsets[1 ] + 0x0085, dccg_regs[3].PHASE[2] = ctx->dcn_reg_offsets[1 ] + 0x0089, dccg_regs[3].PHASE[3] = ctx->dcn_reg_offsets[1 ] + 0x008d, dccg_regs[3].MODULO[0] = ctx->dcn_reg_offsets[ 1] + 0x0082, dccg_regs[3].MODULO[1] = ctx->dcn_reg_offsets [1] + 0x0086, dccg_regs[3].MODULO[2] = ctx->dcn_reg_offsets [1] + 0x008a, dccg_regs[3].MODULO[3] = ctx->dcn_reg_offsets [1] + 0x008e, dccg_regs[3].PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs[3].PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs[3].PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs[3].PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c ), |
2093 | clk_src_regs_init(4, E)( dccg_regs[4].PIXCLK_RESYNC_CNTL = ctx->dcn_reg_offsets[1 ] + 0x004c, dccg_regs[4].PHASE[0] = ctx->dcn_reg_offsets[1 ] + 0x0081, dccg_regs[4].PHASE[1] = ctx->dcn_reg_offsets[1 ] + 0x0085, dccg_regs[4].PHASE[2] = ctx->dcn_reg_offsets[1 ] + 0x0089, dccg_regs[4].PHASE[3] = ctx->dcn_reg_offsets[1 ] + 0x008d, dccg_regs[4].MODULO[0] = ctx->dcn_reg_offsets[ 1] + 0x0082, dccg_regs[4].MODULO[1] = ctx->dcn_reg_offsets [1] + 0x0086, dccg_regs[4].MODULO[2] = ctx->dcn_reg_offsets [1] + 0x008a, dccg_regs[4].MODULO[3] = ctx->dcn_reg_offsets [1] + 0x008e, dccg_regs[4].PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs[4].PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs[4].PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs[4].PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c ); |
2094 | #undef REG_STRUCTdccg_regs |
2095 | #define REG_STRUCTdccg_regs abm_regs |
2096 | abm_regs_init(0)( dccg_regs[0].DC_ABM1_HG_SAMPLE_RATE = ctx->dcn_reg_offsets [3] + 0x0e97, dccg_regs[0].DC_ABM1_LS_SAMPLE_RATE = ctx->dcn_reg_offsets [3] + 0x0e98, dccg_regs[0].BL1_PWM_BL_UPDATE_SAMPLE_RATE = ctx ->dcn_reg_offsets[3] + 0x0e81, dccg_regs[0].DC_ABM1_HG_MISC_CTRL = ctx->dcn_reg_offsets[3] + 0x0e8f, dccg_regs[0].DC_ABM1_IPCSC_COEFF_SEL = ctx->dcn_reg_offsets[3] + 0x0e84, dccg_regs[0].BL1_PWM_CURRENT_ABM_LEVEL = ctx->dcn_reg_offsets[3] + 0x0e7d, dccg_regs[0].BL1_PWM_TARGET_ABM_LEVEL = ctx->dcn_reg_offsets[3] + 0x0e7c, dccg_regs[0].BL1_PWM_USER_LEVEL = ctx->dcn_reg_offsets[3] + 0x0e7b, dccg_regs[0].DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = ctx->dcn_reg_offsets[3] + 0x0e94, dccg_regs[0].DC_ABM1_HGLS_REG_READ_PROGRESS = ctx->dcn_reg_offsets[3] + 0x0e8e, dccg_regs[0].DC_ABM1_ACE_OFFSET_SLOPE_0 = ctx->dcn_reg_offsets[3] + 0x0e85, dccg_regs[0].DC_ABM1_ACE_THRES_12 = ctx->dcn_reg_offsets[3] + 0x0e8a, dccg_regs[0].BIOS_SCRATCH_2 = ctx->nbio_reg_offsets[1] + 0x003a ), |
2097 | abm_regs_init(1)( dccg_regs[1].DC_ABM1_HG_SAMPLE_RATE = ctx->dcn_reg_offsets [3] + 0x0ed8, dccg_regs[1].DC_ABM1_LS_SAMPLE_RATE = ctx->dcn_reg_offsets [3] + 0x0ed9, dccg_regs[1].BL1_PWM_BL_UPDATE_SAMPLE_RATE = ctx ->dcn_reg_offsets[3] + 0x0ec2, dccg_regs[1].DC_ABM1_HG_MISC_CTRL = ctx->dcn_reg_offsets[3] + 0x0ed0, dccg_regs[1].DC_ABM1_IPCSC_COEFF_SEL = ctx->dcn_reg_offsets[3] + 0x0ec5, dccg_regs[1].BL1_PWM_CURRENT_ABM_LEVEL = ctx->dcn_reg_offsets[3] + 0x0ebe, dccg_regs[1].BL1_PWM_TARGET_ABM_LEVEL = ctx->dcn_reg_offsets[3] + 0x0ebd, dccg_regs[1].BL1_PWM_USER_LEVEL = ctx->dcn_reg_offsets[3] + 0x0ebc, dccg_regs[1].DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = ctx->dcn_reg_offsets[3] + 0x0ed5, dccg_regs[1].DC_ABM1_HGLS_REG_READ_PROGRESS = ctx->dcn_reg_offsets[3] + 0x0ecf, dccg_regs[1].DC_ABM1_ACE_OFFSET_SLOPE_0 = ctx->dcn_reg_offsets[3] + 0x0ec6, dccg_regs[1].DC_ABM1_ACE_THRES_12 = ctx->dcn_reg_offsets[3] + 0x0ecb, dccg_regs[1].BIOS_SCRATCH_2 = ctx->nbio_reg_offsets[1] + 0x003a ), |
2098 | abm_regs_init(2)( dccg_regs[2].DC_ABM1_HG_SAMPLE_RATE = ctx->dcn_reg_offsets [3] + 0x0f19, dccg_regs[2].DC_ABM1_LS_SAMPLE_RATE = ctx->dcn_reg_offsets [3] + 0x0f1a, dccg_regs[2].BL1_PWM_BL_UPDATE_SAMPLE_RATE = ctx ->dcn_reg_offsets[3] + 0x0f03, dccg_regs[2].DC_ABM1_HG_MISC_CTRL = ctx->dcn_reg_offsets[3] + 0x0f11, dccg_regs[2].DC_ABM1_IPCSC_COEFF_SEL = ctx->dcn_reg_offsets[3] + 0x0f06, dccg_regs[2].BL1_PWM_CURRENT_ABM_LEVEL = ctx->dcn_reg_offsets[3] + 0x0eff, dccg_regs[2].BL1_PWM_TARGET_ABM_LEVEL = ctx->dcn_reg_offsets[3] + 0x0efe, dccg_regs[2].BL1_PWM_USER_LEVEL = ctx->dcn_reg_offsets[3] + 0x0efd, dccg_regs[2].DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = ctx->dcn_reg_offsets[3] + 0x0f16, dccg_regs[2].DC_ABM1_HGLS_REG_READ_PROGRESS = ctx->dcn_reg_offsets[3] + 0x0f10, dccg_regs[2].DC_ABM1_ACE_OFFSET_SLOPE_0 = ctx->dcn_reg_offsets[3] + 0x0f07, dccg_regs[2].DC_ABM1_ACE_THRES_12 = ctx->dcn_reg_offsets[3] + 0x0f0c, dccg_regs[2].BIOS_SCRATCH_2 = ctx->nbio_reg_offsets[1] + 0x003a ), |
2099 | abm_regs_init(3)( dccg_regs[3].DC_ABM1_HG_SAMPLE_RATE = ctx->dcn_reg_offsets [3] + 0x0f5a, dccg_regs[3].DC_ABM1_LS_SAMPLE_RATE = ctx->dcn_reg_offsets [3] + 0x0f5b, dccg_regs[3].BL1_PWM_BL_UPDATE_SAMPLE_RATE = ctx ->dcn_reg_offsets[3] + 0x0f44, dccg_regs[3].DC_ABM1_HG_MISC_CTRL = ctx->dcn_reg_offsets[3] + 0x0f52, dccg_regs[3].DC_ABM1_IPCSC_COEFF_SEL = ctx->dcn_reg_offsets[3] + 0x0f47, dccg_regs[3].BL1_PWM_CURRENT_ABM_LEVEL = ctx->dcn_reg_offsets[3] + 0x0f40, dccg_regs[3].BL1_PWM_TARGET_ABM_LEVEL = ctx->dcn_reg_offsets[3] + 0x0f3f, dccg_regs[3].BL1_PWM_USER_LEVEL = ctx->dcn_reg_offsets[3] + 0x0f3e, dccg_regs[3].DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = ctx->dcn_reg_offsets[3] + 0x0f57, dccg_regs[3].DC_ABM1_HGLS_REG_READ_PROGRESS = ctx->dcn_reg_offsets[3] + 0x0f51, dccg_regs[3].DC_ABM1_ACE_OFFSET_SLOPE_0 = ctx->dcn_reg_offsets[3] + 0x0f48, dccg_regs[3].DC_ABM1_ACE_THRES_12 = ctx->dcn_reg_offsets[3] + 0x0f4d, dccg_regs[3].BIOS_SCRATCH_2 = ctx->nbio_reg_offsets[1] + 0x003a ); |
2100 | |
2101 | #undef REG_STRUCTdccg_regs |
2102 | #define REG_STRUCTdccg_regs dccg_regs |
2103 | dccg_regs_init()( dccg_regs.DPPCLK_DTO_CTRL = ctx->dcn_reg_offsets[1] + 0x00b6 , dccg_regs.DPPCLK_DTO_PARAM[0] = ctx->dcn_reg_offsets[1] + 0x0099, dccg_regs.DPPCLK_DTO_PARAM[1] = ctx->dcn_reg_offsets [1] + 0x009a, dccg_regs.DPPCLK_DTO_PARAM[2] = ctx->dcn_reg_offsets [1] + 0x009b, dccg_regs.DPPCLK_DTO_PARAM[3] = ctx->dcn_reg_offsets [1] + 0x009c, dccg_regs.HDMICHARCLK_CLOCK_CNTL[0] = ctx->dcn_reg_offsets [2] + 0x004a, dccg_regs.PHYASYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0052, dccg_regs.PHYBSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0053, dccg_regs.PHYCSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0054, dccg_regs.PHYDSYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0055, dccg_regs.PHYESYMCLK_CLOCK_CNTL = ctx->dcn_reg_offsets [2] + 0x0056, dccg_regs.DPSTREAMCLK_CNTL = ctx->dcn_reg_offsets [1] + 0x004a, dccg_regs.HDMISTREAMCLK_CNTL = ctx->dcn_reg_offsets [2] + 0x0059, dccg_regs.SYMCLK32_SE_CNTL = ctx->dcn_reg_offsets [1] + 0x0065, dccg_regs.SYMCLK32_LE_CNTL = ctx->dcn_reg_offsets [1] + 0x0066, dccg_regs.OTG_PIXEL_RATE_CNTL[0] = ctx->dcn_reg_offsets [1] + 0x0080, dccg_regs.OTG_PIXEL_RATE_CNTL[1] = ctx->dcn_reg_offsets [1] + 0x0084, dccg_regs.OTG_PIXEL_RATE_CNTL[2] = ctx->dcn_reg_offsets [1] + 0x0088, dccg_regs.OTG_PIXEL_RATE_CNTL[3] = ctx->dcn_reg_offsets [1] + 0x008c, dccg_regs.DTBCLK_DTO_MODULO[0] = ctx->dcn_reg_offsets [2] + 0x001f, dccg_regs.DTBCLK_DTO_MODULO[1] = ctx->dcn_reg_offsets [2] + 0x0020, dccg_regs.DTBCLK_DTO_MODULO[2] = ctx->dcn_reg_offsets [2] + 0x0021, dccg_regs.DTBCLK_DTO_MODULO[3] = ctx->dcn_reg_offsets [2] + 0x0022, dccg_regs.DTBCLK_DTO_PHASE[0] = ctx->dcn_reg_offsets [2] + 0x0018, dccg_regs.DTBCLK_DTO_PHASE[1] = ctx->dcn_reg_offsets [2] + 0x0019, dccg_regs.DTBCLK_DTO_PHASE[2] = ctx->dcn_reg_offsets [2] + 0x001a, dccg_regs.DTBCLK_DTO_PHASE[3] = ctx->dcn_reg_offsets [2] + 0x001b, dccg_regs.DCCG_AUDIO_DTBCLK_DTO_MODULO = ctx-> dcn_reg_offsets[2] + 0x0062, dccg_regs.DCCG_AUDIO_DTBCLK_DTO_PHASE = ctx->dcn_reg_offsets[2] + 0x0061, dccg_regs.OTG_PIXEL_RATE_DIV = ctx->dcn_reg_offsets[1] + 0x006f, dccg_regs.DTBCLK_P_CNTL = ctx->dcn_reg_offsets[1] + 0x0068, dccg_regs.DCCG_AUDIO_DTO_SOURCE = ctx->dcn_reg_offsets[1] + 0x00ab, dccg_regs.DENTIST_DISPCLK_CNTL = ctx->dcn_reg_offsets[1] + 0x0064 ); |
2104 | |
2105 | DC_FP_START()dc_fpu_begin(__func__, 2105); |
2106 | |
2107 | ctx->dc_bios->regs = &bios_regs; |
2108 | |
2109 | pool->base.res_cap = &res_cap_dcn32; |
2110 | /* max number of pipes for ASIC before checking for pipe fuses */ |
2111 | num_pipes = pool->base.res_cap->num_timing_generator; |
2112 | pipe_fuses = read_pipe_fuses(ctx); |
2113 | |
2114 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) |
2115 | if (pipe_fuses & 1 << i) |
2116 | num_pipes--; |
2117 | |
2118 | if (pipe_fuses & 1) |
2119 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c" , 2119); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); //Unexpected - Pipe 0 should always be fully functional! |
2120 | |
2121 | if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK0x00001000L) |
2122 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c" , 2122); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); //Entire DCN is harvested! |
2123 | |
2124 | /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the |
2125 | * value will be changed, update max_num_dpp and max_num_otg for dml. |
2126 | */ |
2127 | dcn3_2_ip.max_num_dpp = num_pipes; |
2128 | dcn3_2_ip.max_num_otg = num_pipes; |
2129 | |
2130 | pool->base.funcs = &dcn32_res_pool_funcs; |
2131 | |
2132 | /************************************************* |
2133 | * Resource + asic cap harcoding * |
2134 | *************************************************/ |
2135 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE-1; |
2136 | pool->base.timing_generator_count = num_pipes; |
2137 | pool->base.pipe_count = num_pipes; |
2138 | pool->base.mpcc_count = num_pipes; |
2139 | dc->caps.max_downscale_ratio = 600; |
2140 | dc->caps.i2c_speed_in_khz = 100; |
2141 | dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ |
2142 | /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/ |
2143 | dc->caps.max_cursor_size = 64; |
2144 | dc->caps.min_horizontal_blanking_period = 80; |
2145 | dc->caps.dmdata_alloc_size = 2048; |
2146 | dc->caps.mall_size_per_mem_channel = 4; |
2147 | dc->caps.mall_size_total = 0; |
2148 | dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; |
2149 | |
2150 | dc->caps.cache_line_size = 64; |
2151 | dc->caps.cache_num_ways = 16; |
2152 | |
2153 | /* Calculate the available MALL space */ |
2154 | dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( |
2155 | dc, dc->ctx->dc_bios->vram_info.num_chans) * |
2156 | dc->caps.mall_size_per_mem_channel * 1024 * 1024; |
2157 | dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; |
2158 | |
2159 | dc->caps.subvp_fw_processing_delay_us = 15; |
2160 | dc->caps.subvp_prefetch_end_to_mall_start_us = 15; |
2161 | dc->caps.subvp_swath_height_margin_lines = 16; |
2162 | dc->caps.subvp_pstate_allow_width_us = 20; |
2163 | dc->caps.subvp_vertical_int_margin_us = 30; |
2164 | |
2165 | dc->caps.max_slave_planes = 2; |
2166 | dc->caps.max_slave_yuv_planes = 2; |
2167 | dc->caps.max_slave_rgb_planes = 2; |
2168 | dc->caps.post_blend_color_processing = true1; |
2169 | dc->caps.force_dp_tps4_for_cp2520 = true1; |
2170 | dc->caps.dp_hpo = true1; |
2171 | dc->caps.dp_hdmi21_pcon_support = true1; |
2172 | dc->caps.edp_dsc_support = true1; |
2173 | dc->caps.extended_aux_timeout_support = true1; |
2174 | dc->caps.dmcub_support = true1; |
2175 | dc->caps.seamless_odm = true1; |
2176 | |
2177 | /* Color pipeline capabilities */ |
2178 | dc->caps.color.dpp.dcn_arch = 1; |
2179 | dc->caps.color.dpp.input_lut_shared = 0; |
2180 | dc->caps.color.dpp.icsc = 1; |
2181 | dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr |
2182 | dc->caps.color.dpp.dgam_rom_caps.srgb = 1; |
2183 | dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; |
2184 | dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; |
2185 | dc->caps.color.dpp.dgam_rom_caps.pq = 1; |
2186 | dc->caps.color.dpp.dgam_rom_caps.hlg = 1; |
2187 | dc->caps.color.dpp.post_csc = 1; |
2188 | dc->caps.color.dpp.gamma_corr = 1; |
2189 | dc->caps.color.dpp.dgam_rom_for_yuv = 0; |
2190 | |
2191 | dc->caps.color.dpp.hw_3d_lut = 1; |
2192 | dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1 |
2193 | // no OGAM ROM on DCN2 and later ASICs |
2194 | dc->caps.color.dpp.ogam_rom_caps.srgb = 0; |
2195 | dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; |
2196 | dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; |
2197 | dc->caps.color.dpp.ogam_rom_caps.pq = 0; |
2198 | dc->caps.color.dpp.ogam_rom_caps.hlg = 0; |
2199 | dc->caps.color.dpp.ocsc = 0; |
2200 | |
2201 | dc->caps.color.mpc.gamut_remap = 1; |
2202 | dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC |
2203 | dc->caps.color.mpc.ogam_ram = 1; |
2204 | dc->caps.color.mpc.ogam_rom_caps.srgb = 0; |
2205 | dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; |
2206 | dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; |
2207 | dc->caps.color.mpc.ogam_rom_caps.pq = 0; |
2208 | dc->caps.color.mpc.ogam_rom_caps.hlg = 0; |
2209 | dc->caps.color.mpc.ocsc = 1; |
2210 | |
2211 | /* Use pipe context based otg sync logic */ |
2212 | dc->config.use_pipe_ctx_sync_logic = true1; |
2213 | |
2214 | /* read VBIOS LTTPR caps */ |
2215 | { |
2216 | if (ctx->dc_bios->funcs->get_lttpr_caps) { |
2217 | enum bp_result bp_query_result; |
2218 | uint8_t is_vbios_lttpr_enable = 0; |
2219 | |
2220 | bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); |
2221 | dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; |
2222 | } |
2223 | |
2224 | /* interop bit is implicit */ |
2225 | { |
2226 | dc->caps.vbios_lttpr_aware = true1; |
2227 | } |
2228 | } |
2229 | |
2230 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) |
2231 | dc->debug = debug_defaults_drv; |
2232 | else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { |
2233 | dc->debug = debug_defaults_diags; |
2234 | } else |
2235 | dc->debug = debug_defaults_diags; |
2236 | // Init the vm_helper |
2237 | if (dc->vm_helper) |
2238 | vm_helper_init(dc->vm_helper, 16); |
2239 | |
2240 | /************************************************* |
2241 | * Create resources * |
2242 | *************************************************/ |
2243 | |
2244 | /* Clock Sources for Pixel Clock*/ |
2245 | pool->base.clock_sources[DCN32_CLK_SRC_PLL0] = |
2246 | dcn32_clock_source_create(ctx, ctx->dc_bios, |
2247 | CLOCK_SOURCE_COMBO_PHY_PLL0, |
2248 | &clk_src_regs[0], false0); |
2249 | pool->base.clock_sources[DCN32_CLK_SRC_PLL1] = |
2250 | dcn32_clock_source_create(ctx, ctx->dc_bios, |
2251 | CLOCK_SOURCE_COMBO_PHY_PLL1, |
2252 | &clk_src_regs[1], false0); |
2253 | pool->base.clock_sources[DCN32_CLK_SRC_PLL2] = |
2254 | dcn32_clock_source_create(ctx, ctx->dc_bios, |
2255 | CLOCK_SOURCE_COMBO_PHY_PLL2, |
2256 | &clk_src_regs[2], false0); |
2257 | pool->base.clock_sources[DCN32_CLK_SRC_PLL3] = |
2258 | dcn32_clock_source_create(ctx, ctx->dc_bios, |
2259 | CLOCK_SOURCE_COMBO_PHY_PLL3, |
2260 | &clk_src_regs[3], false0); |
2261 | pool->base.clock_sources[DCN32_CLK_SRC_PLL4] = |
2262 | dcn32_clock_source_create(ctx, ctx->dc_bios, |
2263 | CLOCK_SOURCE_COMBO_PHY_PLL4, |
2264 | &clk_src_regs[4], false0); |
2265 | |
2266 | pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL; |
2267 | |
2268 | /* todo: not reuse phy_pll registers */ |
2269 | pool->base.dp_clock_source = |
2270 | dcn32_clock_source_create(ctx, ctx->dc_bios, |
2271 | CLOCK_SOURCE_ID_DP_DTO, |
2272 | &clk_src_regs[0], true1); |
2273 | |
2274 | for (i = 0; i < pool->base.clk_src_count; i++) { |
2275 | if (pool->base.clock_sources[i] == NULL((void *)0)) { |
2276 | dm_error("DC: failed to create clock sources!\n")__drm_err("DC: failed to create clock sources!\n"); |
2277 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2277); do {} while (0); } while (0); |
2278 | goto create_fail; |
2279 | } |
2280 | } |
2281 | |
2282 | /* DCCG */ |
2283 | pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); |
2284 | if (pool->base.dccg == NULL((void *)0)) { |
2285 | dm_error("DC: failed to create dccg!\n")__drm_err("DC: failed to create dccg!\n"); |
2286 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2286); do {} while (0); } while (0); |
2287 | goto create_fail; |
2288 | } |
2289 | |
2290 | /* DML */ |
2291 | if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) |
2292 | dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); |
2293 | |
2294 | /* IRQ Service */ |
2295 | init_data.ctx = dc->ctx; |
2296 | pool->base.irqs = dal_irq_service_dcn32_create(&init_data); |
2297 | if (!pool->base.irqs) |
2298 | goto create_fail; |
2299 | |
2300 | /* HUBBUB */ |
2301 | pool->base.hubbub = dcn32_hubbub_create(ctx); |
2302 | if (pool->base.hubbub == NULL((void *)0)) { |
2303 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2303); do {} while (0); } while (0); |
2304 | dm_error("DC: failed to create hubbub!\n")__drm_err("DC: failed to create hubbub!\n"); |
2305 | goto create_fail; |
2306 | } |
2307 | |
2308 | /* HUBPs, DPPs, OPPs, TGs, ABMs */ |
2309 | for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { |
2310 | |
2311 | /* if pipe is disabled, skip instance of HW pipe, |
2312 | * i.e, skip ASIC register instance |
2313 | */ |
2314 | if (pipe_fuses & 1 << i) |
2315 | continue; |
2316 | |
2317 | /* HUBPs */ |
2318 | pool->base.hubps[j] = dcn32_hubp_create(ctx, i); |
2319 | if (pool->base.hubps[j] == NULL((void *)0)) { |
2320 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2320); do {} while (0); } while (0); |
2321 | dm_error(__drm_err("DC: failed to create hubps!\n") |
2322 | "DC: failed to create hubps!\n")__drm_err("DC: failed to create hubps!\n"); |
2323 | goto create_fail; |
2324 | } |
2325 | |
2326 | /* DPPs */ |
2327 | pool->base.dpps[j] = dcn32_dpp_create(ctx, i); |
2328 | if (pool->base.dpps[j] == NULL((void *)0)) { |
2329 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2329); do {} while (0); } while (0); |
2330 | dm_error(__drm_err("DC: failed to create dpps!\n") |
2331 | "DC: failed to create dpps!\n")__drm_err("DC: failed to create dpps!\n"); |
2332 | goto create_fail; |
2333 | } |
2334 | |
2335 | /* OPPs */ |
2336 | pool->base.opps[j] = dcn32_opp_create(ctx, i); |
2337 | if (pool->base.opps[j] == NULL((void *)0)) { |
2338 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2338); do {} while (0); } while (0); |
2339 | dm_error(__drm_err("DC: failed to create output pixel processor!\n") |
2340 | "DC: failed to create output pixel processor!\n")__drm_err("DC: failed to create output pixel processor!\n"); |
2341 | goto create_fail; |
2342 | } |
2343 | |
2344 | /* TGs */ |
2345 | pool->base.timing_generators[j] = dcn32_timing_generator_create( |
2346 | ctx, i); |
2347 | if (pool->base.timing_generators[j] == NULL((void *)0)) { |
2348 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2348); do {} while (0); } while (0); |
2349 | dm_error("DC: failed to create tg!\n")__drm_err("DC: failed to create tg!\n"); |
2350 | goto create_fail; |
2351 | } |
2352 | |
2353 | /* ABMs */ |
2354 | pool->base.multiple_abms[j] = dmub_abm_create(ctx, |
2355 | &abm_regs[i], |
2356 | &abm_shift, |
2357 | &abm_mask); |
2358 | if (pool->base.multiple_abms[j] == NULL((void *)0)) { |
2359 | dm_error("DC: failed to create abm for pipe %d!\n", i)__drm_err("DC: failed to create abm for pipe %d!\n", i); |
2360 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2360); do {} while (0); } while (0); |
2361 | goto create_fail; |
2362 | } |
2363 | |
2364 | /* index for resource pool arrays for next valid pipe */ |
2365 | j++; |
2366 | } |
2367 | |
2368 | /* PSR */ |
2369 | pool->base.psr = dmub_psr_create(ctx); |
2370 | if (pool->base.psr == NULL((void *)0)) { |
2371 | dm_error("DC: failed to create psr obj!\n")__drm_err("DC: failed to create psr obj!\n"); |
2372 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2372); do {} while (0); } while (0); |
2373 | goto create_fail; |
2374 | } |
2375 | |
2376 | /* MPCCs */ |
2377 | pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut); |
2378 | if (pool->base.mpc == NULL((void *)0)) { |
2379 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2379); do {} while (0); } while (0); |
2380 | dm_error("DC: failed to create mpc!\n")__drm_err("DC: failed to create mpc!\n"); |
2381 | goto create_fail; |
2382 | } |
2383 | |
2384 | /* DSCs */ |
2385 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { |
2386 | pool->base.dscs[i] = dcn32_dsc_create(ctx, i); |
2387 | if (pool->base.dscs[i] == NULL((void *)0)) { |
2388 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2388); do {} while (0); } while (0); |
2389 | dm_error("DC: failed to create display stream compressor %d!\n", i)__drm_err("DC: failed to create display stream compressor %d!\n" , i); |
2390 | goto create_fail; |
2391 | } |
2392 | } |
2393 | |
2394 | /* DWB */ |
2395 | if (!dcn32_dwbc_create(ctx, &pool->base)) { |
2396 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2396); do {} while (0); } while (0); |
2397 | dm_error("DC: failed to create dwbc!\n")__drm_err("DC: failed to create dwbc!\n"); |
2398 | goto create_fail; |
2399 | } |
2400 | |
2401 | /* MMHUBBUB */ |
2402 | if (!dcn32_mmhubbub_create(ctx, &pool->base)) { |
2403 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2403); do {} while (0); } while (0); |
2404 | dm_error("DC: failed to create mcif_wb!\n")__drm_err("DC: failed to create mcif_wb!\n"); |
2405 | goto create_fail; |
2406 | } |
2407 | |
2408 | /* AUX and I2C */ |
2409 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { |
2410 | pool->base.engines[i] = dcn32_aux_engine_create(ctx, i); |
2411 | if (pool->base.engines[i] == NULL((void *)0)) { |
2412 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2412); do {} while (0); } while (0); |
2413 | dm_error(__drm_err("DC:failed to create aux engine!!\n") |
2414 | "DC:failed to create aux engine!!\n")__drm_err("DC:failed to create aux engine!!\n"); |
2415 | goto create_fail; |
2416 | } |
2417 | pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i); |
2418 | if (pool->base.hw_i2cs[i] == NULL((void *)0)) { |
2419 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2419); do {} while (0); } while (0); |
2420 | dm_error(__drm_err("DC:failed to create hw i2c!!\n") |
2421 | "DC:failed to create hw i2c!!\n")__drm_err("DC:failed to create hw i2c!!\n"); |
2422 | goto create_fail; |
2423 | } |
2424 | pool->base.sw_i2cs[i] = NULL((void *)0); |
2425 | } |
2426 | |
2427 | /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ |
2428 | if (!resource_construct(num_virtual_links, dc, &pool->base, |
2429 | (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) ? |
2430 | &res_create_funcs : &res_create_maximus_funcs))) |
2431 | goto create_fail; |
2432 | |
2433 | /* HW Sequencer init functions and Plane caps */ |
2434 | dcn32_hw_sequencer_init_functions(dc); |
2435 | |
2436 | dc->caps.max_planes = pool->base.pipe_count; |
2437 | |
2438 | for (i = 0; i < dc->caps.max_planes; ++i) |
2439 | dc->caps.planes[i] = plane_cap; |
2440 | |
2441 | dc->cap_funcs = cap_funcs; |
2442 | |
2443 | if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { |
2444 | ddc_init_data.ctx = dc->ctx; |
2445 | ddc_init_data.link = NULL((void *)0); |
2446 | ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; |
2447 | ddc_init_data.id.enum_id = 0; |
2448 | ddc_init_data.id.type = OBJECT_TYPE_GENERIC; |
2449 | pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); |
2450 | } else { |
2451 | pool->base.oem_device = NULL((void *)0); |
2452 | } |
2453 | |
2454 | DC_FP_END()dc_fpu_end(__func__, 2454); |
2455 | |
2456 | return true1; |
2457 | |
2458 | create_fail: |
2459 | |
2460 | DC_FP_END()dc_fpu_end(__func__, 2460); |
2461 | |
2462 | dcn32_resource_destruct(pool); |
2463 | |
2464 | return false0; |
2465 | } |
2466 | |
2467 | struct resource_pool *dcn32_create_resource_pool( |
2468 | const struct dc_init_data *init_data, |
2469 | struct dc *dc) |
2470 | { |
2471 | struct dcn32_resource_pool *pool = |
2472 | kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL(0x0001 | 0x0004)); |
2473 | |
2474 | if (!pool) |
2475 | return NULL((void *)0); |
2476 | |
2477 | if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool)) |
2478 | return &pool->base; |
2479 | |
2480 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2480); do {} while (0); } while (0); |
2481 | kfree(pool); |
2482 | return NULL((void *)0); |
2483 | } |
2484 | |
2485 | static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( |
2486 | struct resource_context *res_ctx, |
2487 | const struct resource_pool *pool, |
2488 | const struct pipe_ctx *primary_pipe) |
2489 | { |
2490 | int i; |
2491 | struct pipe_ctx *secondary_pipe = NULL((void *)0); |
2492 | struct pipe_ctx *next_odm_mpo_pipe = NULL((void *)0); |
2493 | int primary_index, preferred_pipe_idx; |
2494 | struct pipe_ctx *old_primary_pipe = NULL((void *)0); |
2495 | |
2496 | /* |
2497 | * Modified from find_idle_secondary_pipe |
2498 | * With windowed MPO and ODM, we want to avoid the case where we want a |
2499 | * free pipe for the left side but the free pipe is being used on the |
2500 | * right side. |
2501 | * Add check on current_state if the primary_pipe is the left side, |
2502 | * to check the right side ( primary_pipe->next_odm_pipe ) to see if |
2503 | * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) |
2504 | * - If so, then don't use this pipe |
2505 | * EXCEPTION - 3 plane ( 2 MPO plane ) case |
2506 | * - in this case, the primary pipe has already gotten a free pipe for the |
2507 | * MPO window in the left |
2508 | * - when it tries to get a free pipe for the MPO window on the right, |
2509 | * it will see that it is already assigned to the right side |
2510 | * ( primary_pipe->next_odm_pipe ). But in this case, we want this |
2511 | * free pipe, since it will be for the right side. So add an |
2512 | * additional condition, that skipping the free pipe on the right only |
2513 | * applies if the primary pipe has no bottom pipe currently assigned |
2514 | */ |
2515 | if (primary_pipe) { |
2516 | primary_index = primary_pipe->pipe_idx; |
2517 | old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; |
2518 | if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) |
2519 | && (!primary_pipe->bottom_pipe)) |
2520 | next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; |
2521 | |
2522 | preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; |
2523 | if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL((void *)0)) && |
2524 | !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { |
2525 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; |
2526 | secondary_pipe->pipe_idx = preferred_pipe_idx; |
2527 | } |
2528 | } |
2529 | |
2530 | /* |
2531 | * search backwards for the second pipe to keep pipe |
2532 | * assignment more consistent |
2533 | */ |
2534 | if (!secondary_pipe) |
2535 | for (i = pool->pipe_count - 1; i >= 0; i--) { |
2536 | if ((res_ctx->pipe_ctx[i].stream == NULL((void *)0)) && |
2537 | !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { |
2538 | secondary_pipe = &res_ctx->pipe_ctx[i]; |
2539 | secondary_pipe->pipe_idx = i; |
2540 | break; |
2541 | } |
2542 | } |
2543 | |
2544 | return secondary_pipe; |
2545 | } |
2546 | |
2547 | struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( |
2548 | struct dc_state *state, |
2549 | const struct resource_pool *pool, |
2550 | struct dc_stream_state *stream, |
2551 | struct pipe_ctx *head_pipe) |
2552 | { |
2553 | struct resource_context *res_ctx = &state->res_ctx; |
2554 | struct pipe_ctx *idle_pipe, *pipe; |
2555 | struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; |
2556 | int head_index; |
2557 | |
2558 | if (!head_pipe) |
2559 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_resource.c" , 2559); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
2560 | |
2561 | /* |
2562 | * Modified from dcn20_acquire_idle_pipe_for_layer |
2563 | * Check if head_pipe in old_context already has bottom_pipe allocated. |
2564 | * - If so, check if that pipe is available in the current context. |
2565 | * -- If so, reuse pipe from old_context |
2566 | */ |
2567 | head_index = head_pipe->pipe_idx; |
2568 | pipe = &old_ctx->pipe_ctx[head_index]; |
2569 | if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL((void *)0)) { |
2570 | idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; |
2571 | idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; |
2572 | } else { |
2573 | idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); |
2574 | if (!idle_pipe) |
2575 | return NULL((void *)0); |
2576 | } |
2577 | |
2578 | idle_pipe->stream = head_pipe->stream; |
2579 | idle_pipe->stream_res.tg = head_pipe->stream_res.tg; |
2580 | idle_pipe->stream_res.opp = head_pipe->stream_res.opp; |
2581 | |
2582 | idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; |
2583 | idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; |
2584 | idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; |
2585 | idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; |
2586 | |
2587 | return idle_pipe; |
2588 | } |
2589 | |
2590 | unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans) |
2591 | { |
2592 | /* |
2593 | * DCN32 and DCN321 SKUs may have different sizes for MALL |
2594 | * but we may not be able to access all the MALL space. |
2595 | * If the num_chans is power of 2, then we can access all |
2596 | * of the available MALL space. Otherwise, we can only |
2597 | * access: |
2598 | * |
2599 | * max_cab_size_in_bytes = total_cache_size_in_bytes * |
2600 | * ((2^floor(log2(num_chans)))/num_chans) |
2601 | * |
2602 | * Calculating the MALL sizes for all available SKUs, we |
2603 | * have come up with the follow simplified check. |
2604 | * - we have max_chans which provides the max MALL size. |
2605 | * Each chans supports 4MB of MALL so: |
2606 | * |
2607 | * total_cache_size_in_bytes = max_chans * 4 MB |
2608 | * |
2609 | * - we have avail_chans which shows the number of channels |
2610 | * we can use if we can't access the entire MALL space. |
2611 | * It is generally half of max_chans |
2612 | * - so we use the following checks: |
2613 | * |
2614 | * if (num_chans == max_chans), return max_chans |
2615 | * if (num_chans < max_chans), return avail_chans |
2616 | * |
2617 | * - exception is GC_11_0_0 where we can't access max_chans, |
2618 | * so we define max_avail_chans as the maximum available |
2619 | * MALL space |
2620 | * |
2621 | */ |
2622 | int gc_11_0_0_max_chans = 48; |
2623 | int gc_11_0_0_max_avail_chans = 32; |
2624 | int gc_11_0_0_avail_chans = 16; |
2625 | int gc_11_0_3_max_chans = 16; |
2626 | int gc_11_0_3_avail_chans = 8; |
2627 | int gc_11_0_2_max_chans = 8; |
2628 | int gc_11_0_2_avail_chans = 4; |
2629 | |
2630 | if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)(dc->ctx->asic_id.hw_internal_rev < 0x10)) { |
2631 | return (num_chans == gc_11_0_0_max_chans) ? |
2632 | gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans; |
2633 | } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)(dc->ctx->asic_id.hw_internal_rev >= 0x10 && dc->ctx->asic_id.hw_internal_rev < 0x20)) { |
2634 | return (num_chans == gc_11_0_2_max_chans) ? |
2635 | gc_11_0_2_max_chans : gc_11_0_2_avail_chans; |
2636 | } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) { |
2637 | return (num_chans == gc_11_0_3_max_chans) ? |
2638 | gc_11_0_3_max_chans : gc_11_0_3_avail_chans; |
2639 | } |
2640 | } |