File: | dev/pci/drm/drm_edid.c |
Warning: | line 2209, column 28 Potential leak of memory pointed to by 'override' |
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1 | /* | ||||
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | ||||
3 | * Copyright (c) 2007-2008 Intel Corporation | ||||
4 | * Jesse Barnes <jesse.barnes@intel.com> | ||||
5 | * Copyright 2010 Red Hat, Inc. | ||||
6 | * | ||||
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | ||||
8 | * FB layer. | ||||
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | ||||
10 | * | ||||
11 | * Permission is hereby granted, free of charge, to any person obtaining a | ||||
12 | * copy of this software and associated documentation files (the "Software"), | ||||
13 | * to deal in the Software without restriction, including without limitation | ||||
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | ||||
15 | * and/or sell copies of the Software, and to permit persons to whom the | ||||
16 | * Software is furnished to do so, subject to the following conditions: | ||||
17 | * | ||||
18 | * The above copyright notice and this permission notice (including the | ||||
19 | * next paragraph) shall be included in all copies or substantial portions | ||||
20 | * of the Software. | ||||
21 | * | ||||
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||||
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||||
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||||
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||||
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||||
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||||
28 | * DEALINGS IN THE SOFTWARE. | ||||
29 | */ | ||||
30 | |||||
31 | #include <linux/bitfield.h> | ||||
32 | #include <linux/hdmi.h> | ||||
33 | #include <linux/i2c.h> | ||||
34 | #include <linux/kernel.h> | ||||
35 | #include <linux/module.h> | ||||
36 | #include <linux/pci.h> | ||||
37 | #include <linux/slab.h> | ||||
38 | #include <linux/vga_switcheroo.h> | ||||
39 | |||||
40 | #include <drm/drm_displayid.h> | ||||
41 | #include <drm/drm_drv.h> | ||||
42 | #include <drm/drm_edid.h> | ||||
43 | #include <drm/drm_encoder.h> | ||||
44 | #include <drm/drm_print.h> | ||||
45 | |||||
46 | #include "drm_crtc_internal.h" | ||||
47 | |||||
48 | static int oui(u8 first, u8 second, u8 third) | ||||
49 | { | ||||
50 | return (first << 16) | (second << 8) | third; | ||||
51 | } | ||||
52 | |||||
53 | #define EDID_EST_TIMINGS16 16 | ||||
54 | #define EDID_STD_TIMINGS8 8 | ||||
55 | #define EDID_DETAILED_TIMINGS4 4 | ||||
56 | |||||
57 | /* | ||||
58 | * EDID blocks out in the wild have a variety of bugs, try to collect | ||||
59 | * them here (note that userspace may work around broken monitors first, | ||||
60 | * but fixes should make their way here so that the kernel "just works" | ||||
61 | * on as many displays as possible). | ||||
62 | */ | ||||
63 | |||||
64 | /* First detailed mode wrong, use largest 60Hz mode */ | ||||
65 | #define EDID_QUIRK_PREFER_LARGE_60(1 << 0) (1 << 0) | ||||
66 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | ||||
67 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH(1 << 1) (1 << 1) | ||||
68 | /* Prefer the largest mode at 75 Hz */ | ||||
69 | #define EDID_QUIRK_PREFER_LARGE_75(1 << 2) (1 << 2) | ||||
70 | /* Detail timing is in cm not mm */ | ||||
71 | #define EDID_QUIRK_DETAILED_IN_CM(1 << 3) (1 << 3) | ||||
72 | /* Detailed timing descriptors have bogus size values, so just take the | ||||
73 | * maximum size and use that. | ||||
74 | */ | ||||
75 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE(1 << 4) (1 << 4) | ||||
76 | /* use +hsync +vsync for detailed mode */ | ||||
77 | #define EDID_QUIRK_DETAILED_SYNC_PP(1 << 6) (1 << 6) | ||||
78 | /* Force reduced-blanking timings for detailed modes */ | ||||
79 | #define EDID_QUIRK_FORCE_REDUCED_BLANKING(1 << 7) (1 << 7) | ||||
80 | /* Force 8bpc */ | ||||
81 | #define EDID_QUIRK_FORCE_8BPC(1 << 8) (1 << 8) | ||||
82 | /* Force 12bpc */ | ||||
83 | #define EDID_QUIRK_FORCE_12BPC(1 << 9) (1 << 9) | ||||
84 | /* Force 6bpc */ | ||||
85 | #define EDID_QUIRK_FORCE_6BPC(1 << 10) (1 << 10) | ||||
86 | /* Force 10bpc */ | ||||
87 | #define EDID_QUIRK_FORCE_10BPC(1 << 11) (1 << 11) | ||||
88 | /* Non desktop display (i.e. HMD) */ | ||||
89 | #define EDID_QUIRK_NON_DESKTOP(1 << 12) (1 << 12) | ||||
90 | /* Cap the DSC target bitrate to 15bpp */ | ||||
91 | #define EDID_QUIRK_CAP_DSC_15BPP(1 << 13) (1 << 13) | ||||
92 | |||||
93 | #define MICROSOFT_IEEE_OUI0xca125c 0xca125c | ||||
94 | |||||
95 | struct detailed_mode_closure { | ||||
96 | struct drm_connector *connector; | ||||
97 | const struct drm_edid *drm_edid; | ||||
98 | bool_Bool preferred; | ||||
99 | u32 quirks; | ||||
100 | int modes; | ||||
101 | }; | ||||
102 | |||||
103 | #define LEVEL_DMT0 0 | ||||
104 | #define LEVEL_GTF1 1 | ||||
105 | #define LEVEL_GTF22 2 | ||||
106 | #define LEVEL_CVT3 3 | ||||
107 | |||||
108 | #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks){ .panel_id = ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | (( (u32)(vend_chr_2) - '@') & 0x1f) << 16 | ((product_id ) & 0xffff)), .quirks = _quirks } \ | ||||
109 | { \ | ||||
110 | .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | (((u32) (vend_chr_1) - '@') & 0x1f) << 21 | (((u32)(vend_chr_2 ) - '@') & 0x1f) << 16 | ((product_id) & 0xffff )) | ||||
111 | product_id)((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | (((u32) (vend_chr_1) - '@') & 0x1f) << 21 | (((u32)(vend_chr_2 ) - '@') & 0x1f) << 16 | ((product_id) & 0xffff )), \ | ||||
112 | .quirks = _quirks \ | ||||
113 | } | ||||
114 | |||||
115 | static const struct edid_quirk { | ||||
116 | u32 panel_id; | ||||
117 | u32 quirks; | ||||
118 | } edid_quirk_list[] = { | ||||
119 | /* Acer AL1706 */ | ||||
120 | EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60){ .panel_id = ((((u32)('A') - '@') & 0x1f) << 26 | ( ((u32)('C') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((44358) & 0xffff)), .quirks = (1 << 0) }, | ||||
121 | /* Acer F51 */ | ||||
122 | EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60){ .panel_id = ((((u32)('A') - '@') & 0x1f) << 26 | ( ((u32)('P') - '@') & 0x1f) << 21 | (((u32)('I') - '@' ) & 0x1f) << 16 | ((0x7602) & 0xffff)), .quirks = (1 << 0) }, | ||||
123 | |||||
124 | /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ | ||||
125 | EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC){ .panel_id = ((((u32)('A') - '@') & 0x1f) << 26 | ( ((u32)('E') - '@') & 0x1f) << 21 | (((u32)('O') - '@' ) & 0x1f) << 16 | ((0) & 0xffff)), .quirks = (1 << 10) }, | ||||
126 | |||||
127 | /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ | ||||
128 | EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC){ .panel_id = ((((u32)('B') - '@') & 0x1f) << 26 | ( ((u32)('O') - '@') & 0x1f) << 21 | (((u32)('E') - '@' ) & 0x1f) << 16 | ((0x78b) & 0xffff)), .quirks = (1 << 10) }, | ||||
129 | |||||
130 | /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ | ||||
131 | EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC){ .panel_id = ((((u32)('C') - '@') & 0x1f) << 26 | ( ((u32)('P') - '@') & 0x1f) << 21 | (((u32)('T') - '@' ) & 0x1f) << 16 | ((0x17df) & 0xffff)), .quirks = (1 << 10) }, | ||||
132 | |||||
133 | /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ | ||||
134 | EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('D') - '@') & 0x1f) << 21 | (((u32)('C') - '@' ) & 0x1f) << 16 | ((0x3652) & 0xffff)), .quirks = (1 << 10) }, | ||||
135 | |||||
136 | /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ | ||||
137 | EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC){ .panel_id = ((((u32)('B') - '@') & 0x1f) << 26 | ( ((u32)('O') - '@') & 0x1f) << 21 | (((u32)('E') - '@' ) & 0x1f) << 16 | ((0x0771) & 0xffff)), .quirks = (1 << 10) }, | ||||
138 | |||||
139 | /* Belinea 10 15 55 */ | ||||
140 | EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60){ .panel_id = ((((u32)('M') - '@') & 0x1f) << 26 | ( ((u32)('A') - '@') & 0x1f) << 21 | (((u32)('X') - '@' ) & 0x1f) << 16 | ((1516) & 0xffff)), .quirks = (1 << 0) }, | ||||
141 | EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60){ .panel_id = ((((u32)('M') - '@') & 0x1f) << 26 | ( ((u32)('A') - '@') & 0x1f) << 21 | (((u32)('X') - '@' ) & 0x1f) << 16 | ((0x77e) & 0xffff)), .quirks = (1 << 0) }, | ||||
142 | |||||
143 | /* Envision Peripherals, Inc. EN-7100e */ | ||||
144 | EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH){ .panel_id = ((((u32)('E') - '@') & 0x1f) << 26 | ( ((u32)('P') - '@') & 0x1f) << 21 | (((u32)('I') - '@' ) & 0x1f) << 16 | ((59264) & 0xffff)), .quirks = (1 << 1) }, | ||||
145 | /* Envision EN2028 */ | ||||
146 | EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60){ .panel_id = ((((u32)('E') - '@') & 0x1f) << 26 | ( ((u32)('P') - '@') & 0x1f) << 21 | (((u32)('I') - '@' ) & 0x1f) << 16 | ((8232) & 0xffff)), .quirks = (1 << 0) }, | ||||
147 | |||||
148 | /* Funai Electronics PM36B */ | ||||
149 | EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |{ .panel_id = ((((u32)('F') - '@') & 0x1f) << 26 | ( ((u32)('C') - '@') & 0x1f) << 21 | (((u32)('M') - '@' ) & 0x1f) << 16 | ((13600) & 0xffff)), .quirks = (1 << 2) | (1 << 3) } | ||||
150 | EDID_QUIRK_DETAILED_IN_CM){ .panel_id = ((((u32)('F') - '@') & 0x1f) << 26 | ( ((u32)('C') - '@') & 0x1f) << 21 | (((u32)('M') - '@' ) & 0x1f) << 16 | ((13600) & 0xffff)), .quirks = (1 << 2) | (1 << 3) }, | ||||
151 | |||||
152 | /* LG 27GP950 */ | ||||
153 | EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP){ .panel_id = ((((u32)('G') - '@') & 0x1f) << 26 | ( ((u32)('S') - '@') & 0x1f) << 21 | (((u32)('M') - '@' ) & 0x1f) << 16 | ((0x5bbf) & 0xffff)), .quirks = (1 << 13) }, | ||||
154 | |||||
155 | /* LG 27GN950 */ | ||||
156 | EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP){ .panel_id = ((((u32)('G') - '@') & 0x1f) << 26 | ( ((u32)('S') - '@') & 0x1f) << 21 | (((u32)('M') - '@' ) & 0x1f) << 16 | ((0x5b9a) & 0xffff)), .quirks = (1 << 13) }, | ||||
157 | |||||
158 | /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ | ||||
159 | EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC){ .panel_id = ((((u32)('L') - '@') & 0x1f) << 26 | ( ((u32)('G') - '@') & 0x1f) << 21 | (((u32)('D') - '@' ) & 0x1f) << 16 | ((764) & 0xffff)), .quirks = ( 1 << 11) }, | ||||
160 | |||||
161 | /* LG Philips LCD LP154W01-A5 */ | ||||
162 | EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE){ .panel_id = ((((u32)('L') - '@') & 0x1f) << 26 | ( ((u32)('P') - '@') & 0x1f) << 21 | (((u32)('L') - '@' ) & 0x1f) << 16 | ((0) & 0xffff)), .quirks = (1 << 4) }, | ||||
163 | EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE){ .panel_id = ((((u32)('L') - '@') & 0x1f) << 26 | ( ((u32)('P') - '@') & 0x1f) << 21 | (((u32)('L') - '@' ) & 0x1f) << 16 | ((0x2a00) & 0xffff)), .quirks = (1 << 4) }, | ||||
164 | |||||
165 | /* Samsung SyncMaster 205BW. Note: irony */ | ||||
166 | EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('A') - '@') & 0x1f) << 21 | (((u32)('M') - '@' ) & 0x1f) << 16 | ((541) & 0xffff)), .quirks = ( 1 << 6) }, | ||||
167 | /* Samsung SyncMaster 22[5-6]BW */ | ||||
168 | EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('A') - '@') & 0x1f) << 21 | (((u32)('M') - '@' ) & 0x1f) << 16 | ((596) & 0xffff)), .quirks = ( 1 << 0) }, | ||||
169 | EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('A') - '@') & 0x1f) << 21 | (((u32)('M') - '@' ) & 0x1f) << 16 | ((638) & 0xffff)), .quirks = ( 1 << 0) }, | ||||
170 | |||||
171 | /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ | ||||
172 | EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('N') - '@') & 0x1f) << 21 | (((u32)('Y') - '@' ) & 0x1f) << 16 | ((0x2541) & 0xffff)), .quirks = (1 << 9) }, | ||||
173 | |||||
174 | /* ViewSonic VA2026w */ | ||||
175 | EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('S') - '@') & 0x1f) << 21 | (((u32)('C') - '@' ) & 0x1f) << 16 | ((5020) & 0xffff)), .quirks = (1 << 7) }, | ||||
176 | |||||
177 | /* Medion MD 30217 PG */ | ||||
178 | EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75){ .panel_id = ((((u32)('M') - '@') & 0x1f) << 26 | ( ((u32)('E') - '@') & 0x1f) << 21 | (((u32)('D') - '@' ) & 0x1f) << 16 | ((0x7b8) & 0xffff)), .quirks = (1 << 2) }, | ||||
179 | |||||
180 | /* Lenovo G50 */ | ||||
181 | EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('D') - '@') & 0x1f) << 21 | (((u32)('C') - '@' ) & 0x1f) << 16 | ((18514) & 0xffff)), .quirks = (1 << 10) }, | ||||
182 | |||||
183 | /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ | ||||
184 | EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('E') - '@') & 0x1f) << 21 | (((u32)('C') - '@' ) & 0x1f) << 16 | ((0xd033) & 0xffff)), .quirks = (1 << 8) }, | ||||
185 | |||||
186 | /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ | ||||
187 | EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC){ .panel_id = ((((u32)('E') - '@') & 0x1f) << 26 | ( ((u32)('T') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((13896) & 0xffff)), .quirks = (1 << 8) }, | ||||
188 | |||||
189 | /* Valve Index Headset */ | ||||
190 | EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91a8) & 0xffff)), .quirks = (1 << 12) }, | ||||
191 | EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b0) & 0xffff)), .quirks = (1 << 12) }, | ||||
192 | EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b1) & 0xffff)), .quirks = (1 << 12) }, | ||||
193 | EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b2) & 0xffff)), .quirks = (1 << 12) }, | ||||
194 | EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b3) & 0xffff)), .quirks = (1 << 12) }, | ||||
195 | EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b4) & 0xffff)), .quirks = (1 << 12) }, | ||||
196 | EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b5) & 0xffff)), .quirks = (1 << 12) }, | ||||
197 | EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b6) & 0xffff)), .quirks = (1 << 12) }, | ||||
198 | EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b7) & 0xffff)), .quirks = (1 << 12) }, | ||||
199 | EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b8) & 0xffff)), .quirks = (1 << 12) }, | ||||
200 | EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91b9) & 0xffff)), .quirks = (1 << 12) }, | ||||
201 | EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91ba) & 0xffff)), .quirks = (1 << 12) }, | ||||
202 | EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91bb) & 0xffff)), .quirks = (1 << 12) }, | ||||
203 | EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91bc) & 0xffff)), .quirks = (1 << 12) }, | ||||
204 | EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91bd) & 0xffff)), .quirks = (1 << 12) }, | ||||
205 | EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91be) & 0xffff)), .quirks = (1 << 12) }, | ||||
206 | EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('V') - '@') & 0x1f) << 26 | ( ((u32)('L') - '@') & 0x1f) << 21 | (((u32)('V') - '@' ) & 0x1f) << 16 | ((0x91bf) & 0xffff)), .quirks = (1 << 12) }, | ||||
207 | |||||
208 | /* HTC Vive and Vive Pro VR Headsets */ | ||||
209 | EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('H') - '@') & 0x1f) << 26 | ( ((u32)('V') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((0xaa01) & 0xffff)), .quirks = (1 << 12) }, | ||||
210 | EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('H') - '@') & 0x1f) << 26 | ( ((u32)('V') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((0xaa02) & 0xffff)), .quirks = (1 << 12) }, | ||||
211 | |||||
212 | /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ | ||||
213 | EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('O') - '@') & 0x1f) << 26 | ( ((u32)('V') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((0x0001) & 0xffff)), .quirks = (1 << 12) }, | ||||
214 | EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('O') - '@') & 0x1f) << 26 | ( ((u32)('V') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((0x0003) & 0xffff)), .quirks = (1 << 12) }, | ||||
215 | EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('O') - '@') & 0x1f) << 26 | ( ((u32)('V') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((0x0004) & 0xffff)), .quirks = (1 << 12) }, | ||||
216 | EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('O') - '@') & 0x1f) << 26 | ( ((u32)('V') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((0x0012) & 0xffff)), .quirks = (1 << 12) }, | ||||
217 | |||||
218 | /* Windows Mixed Reality Headsets */ | ||||
219 | EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('A') - '@') & 0x1f) << 26 | ( ((u32)('C') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((0x7fce) & 0xffff)), .quirks = (1 << 12) }, | ||||
220 | EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('L') - '@') & 0x1f) << 26 | ( ((u32)('E') - '@') & 0x1f) << 21 | (((u32)('N') - '@' ) & 0x1f) << 16 | ((0x0408) & 0xffff)), .quirks = (1 << 12) }, | ||||
221 | EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('F') - '@') & 0x1f) << 26 | ( ((u32)('U') - '@') & 0x1f) << 21 | (((u32)('J') - '@' ) & 0x1f) << 16 | ((0x1970) & 0xffff)), .quirks = (1 << 12) }, | ||||
222 | EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('D') - '@') & 0x1f) << 26 | ( ((u32)('E') - '@') & 0x1f) << 21 | (((u32)('L') - '@' ) & 0x1f) << 16 | ((0x7fce) & 0xffff)), .quirks = (1 << 12) }, | ||||
223 | EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('E') - '@') & 0x1f) << 21 | (((u32)('C') - '@' ) & 0x1f) << 16 | ((0x144a) & 0xffff)), .quirks = (1 << 12) }, | ||||
224 | EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('A') - '@') & 0x1f) << 26 | ( ((u32)('U') - '@') & 0x1f) << 21 | (((u32)('S') - '@' ) & 0x1f) << 16 | ((0xc102) & 0xffff)), .quirks = (1 << 12) }, | ||||
225 | |||||
226 | /* Sony PlayStation VR Headset */ | ||||
227 | EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('N') - '@') & 0x1f) << 21 | (((u32)('Y') - '@' ) & 0x1f) << 16 | ((0x0704) & 0xffff)), .quirks = (1 << 12) }, | ||||
228 | |||||
229 | /* Sensics VR Headsets */ | ||||
230 | EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('E') - '@') & 0x1f) << 21 | (((u32)('N') - '@' ) & 0x1f) << 16 | ((0x1019) & 0xffff)), .quirks = (1 << 12) }, | ||||
231 | |||||
232 | /* OSVR HDK and HDK2 VR Headsets */ | ||||
233 | EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('S') - '@') & 0x1f) << 26 | ( ((u32)('V') - '@') & 0x1f) << 21 | (((u32)('R') - '@' ) & 0x1f) << 16 | ((0x1019) & 0xffff)), .quirks = (1 << 12) }, | ||||
234 | EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP){ .panel_id = ((((u32)('A') - '@') & 0x1f) << 26 | ( ((u32)('U') - '@') & 0x1f) << 21 | (((u32)('O') - '@' ) & 0x1f) << 16 | ((0x1111) & 0xffff)), .quirks = (1 << 12) }, | ||||
235 | }; | ||||
236 | |||||
237 | /* | ||||
238 | * Autogenerated from the DMT spec. | ||||
239 | * This table is copied from xfree86/modes/xf86EdidModes.c. | ||||
240 | */ | ||||
241 | static const struct drm_display_mode drm_dmt_modes[] = { | ||||
242 | /* 0x01 - 640x350@85Hz */ | ||||
243 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,.name = "640x350", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (350), . vsync_start = (382), .vsync_end = (385), .vtotal = (445), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
244 | 736, 832, 0, 350, 382, 385, 445, 0,.name = "640x350", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (350), . vsync_start = (382), .vsync_end = (385), .vtotal = (445), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
245 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x350", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (350), . vsync_start = (382), .vsync_end = (385), .vtotal = (445), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
246 | /* 0x02 - 640x400@85Hz */ | ||||
247 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,.name = "640x400", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (445), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
248 | 736, 832, 0, 400, 401, 404, 445, 0,.name = "640x400", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (445), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
249 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "640x400", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (445), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
250 | /* 0x03 - 720x400@85Hz */ | ||||
251 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (756), .hsync_end = (828), .htotal = (936), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (446), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
252 | 828, 936, 0, 400, 401, 404, 446, 0,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (756), .hsync_end = (828), .htotal = (936), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (446), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
253 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (756), .hsync_end = (828), .htotal = (936), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (446), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
254 | /* 0x04 - 640x480@60Hz */ | ||||
255 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
256 | 752, 800, 0, 480, 490, 492, 525, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
257 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
258 | /* 0x05 - 640x480@72Hz */ | ||||
259 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
260 | 704, 832, 0, 480, 489, 492, 520, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
261 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
262 | /* 0x06 - 640x480@75Hz */ | ||||
263 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
264 | 720, 840, 0, 480, 481, 484, 500, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
265 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
266 | /* 0x07 - 640x480@85Hz */ | ||||
267 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (640), .hsync_start = (696), .hsync_end = (752), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (509), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
268 | 752, 832, 0, 480, 481, 484, 509, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (640), .hsync_start = (696), .hsync_end = (752), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (509), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
269 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (640), .hsync_start = (696), .hsync_end = (752), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (509), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
270 | /* 0x08 - 800x600@56Hz */ | ||||
271 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
272 | 896, 1024, 0, 600, 601, 603, 625, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
273 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
274 | /* 0x09 - 800x600@60Hz */ | ||||
275 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
276 | 968, 1056, 0, 600, 601, 605, 628, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
277 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
278 | /* 0x0a - 800x600@72Hz */ | ||||
279 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
280 | 976, 1040, 0, 600, 637, 643, 666, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
281 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
282 | /* 0x0b - 800x600@75Hz */ | ||||
283 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
284 | 896, 1056, 0, 600, 601, 604, 625, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
285 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
286 | /* 0x0c - 800x600@85Hz */ | ||||
287 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (56250), .hdisplay = (800), .hsync_start = (832), .hsync_end = (896), .htotal = (1048), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (631), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
288 | 896, 1048, 0, 600, 601, 604, 631, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (56250), .hdisplay = (800), .hsync_start = (832), .hsync_end = (896), .htotal = (1048), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (631), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
289 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (56250), .hdisplay = (800), .hsync_start = (832), .hsync_end = (896), .htotal = (1048), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (631), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
290 | /* 0x0d - 800x600@120Hz RB */ | ||||
291 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (73250), .hdisplay = (800), .hsync_start = (848), .hsync_end = (880), .htotal = (960), .hskew = (0), .vdisplay = (600), . vsync_start = (603), .vsync_end = (607), .vtotal = (636), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
292 | 880, 960, 0, 600, 603, 607, 636, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (73250), .hdisplay = (800), .hsync_start = (848), .hsync_end = (880), .htotal = (960), .hskew = (0), .vdisplay = (600), . vsync_start = (603), .vsync_end = (607), .vtotal = (636), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
293 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (73250), .hdisplay = (800), .hsync_start = (848), .hsync_end = (880), .htotal = (960), .hskew = (0), .vdisplay = (600), . vsync_start = (603), .vsync_end = (607), .vtotal = (636), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
294 | /* 0x0e - 848x480@60Hz */ | ||||
295 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,.name = "848x480", .status = 0, .type = ((1<<6)), .clock = (33750), .hdisplay = (848), .hsync_start = (864), .hsync_end = (976), .htotal = (1088), .hskew = (0), .vdisplay = (480), . vsync_start = (486), .vsync_end = (494), .vtotal = (517), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
296 | 976, 1088, 0, 480, 486, 494, 517, 0,.name = "848x480", .status = 0, .type = ((1<<6)), .clock = (33750), .hdisplay = (848), .hsync_start = (864), .hsync_end = (976), .htotal = (1088), .hskew = (0), .vdisplay = (480), . vsync_start = (486), .vsync_end = (494), .vtotal = (517), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
297 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "848x480", .status = 0, .type = ((1<<6)), .clock = (33750), .hdisplay = (848), .hsync_start = (864), .hsync_end = (976), .htotal = (1088), .hskew = (0), .vdisplay = (480), . vsync_start = (486), .vsync_end = (494), .vtotal = (517), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
298 | /* 0x0f - 1024x768@43Hz, interlace */ | ||||
299 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
300 | 1208, 1264, 0, 768, 768, 776, 817, 0,.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
301 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
302 | DRM_MODE_FLAG_INTERLACE).name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) }, | ||||
303 | /* 0x10 - 1024x768@60Hz */ | ||||
304 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
305 | 1184, 1344, 0, 768, 771, 777, 806, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
306 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
307 | /* 0x11 - 1024x768@70Hz */ | ||||
308 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
309 | 1184, 1328, 0, 768, 771, 777, 806, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
310 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
311 | /* 0x12 - 1024x768@75Hz */ | ||||
312 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
313 | 1136, 1312, 0, 768, 769, 772, 800, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
314 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
315 | /* 0x13 - 1024x768@85Hz */ | ||||
316 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (94500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1168), .htotal = (1376), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (808), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
317 | 1168, 1376, 0, 768, 769, 772, 808, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (94500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1168), .htotal = (1376), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (808), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
318 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (94500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1168), .htotal = (1376), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (808), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
319 | /* 0x14 - 1024x768@120Hz RB */ | ||||
320 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (115500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1104), .htotal = (1184), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (775), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
321 | 1104, 1184, 0, 768, 771, 775, 813, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (115500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1104), .htotal = (1184), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (775), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
322 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (115500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1104), .htotal = (1184), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (775), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
323 | /* 0x15 - 1152x864@75Hz */ | ||||
324 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,.name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
325 | 1344, 1600, 0, 864, 865, 868, 900, 0,.name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
326 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
327 | /* 0x55 - 1280x720@60Hz */ | ||||
328 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
329 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
330 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
331 | /* 0x16 - 1280x768@60Hz RB */ | ||||
332 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (68250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (790), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
333 | 1360, 1440, 0, 768, 771, 778, 790, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (68250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (790), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
334 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (68250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (790), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
335 | /* 0x17 - 1280x768@60Hz */ | ||||
336 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (79500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1472), .htotal = (1664), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (798), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
337 | 1472, 1664, 0, 768, 771, 778, 798, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (79500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1472), .htotal = (1664), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (798), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
338 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (79500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1472), .htotal = (1664), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (798), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
339 | /* 0x18 - 1280x768@75Hz */ | ||||
340 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (102250), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (805), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
341 | 1488, 1696, 0, 768, 771, 778, 805, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (102250), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (805), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
342 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (102250), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (805), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
343 | /* 0x19 - 1280x768@85Hz */ | ||||
344 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (117500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (809), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
345 | 1496, 1712, 0, 768, 771, 778, 809, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (117500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (809), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
346 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (117500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (809), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
347 | /* 0x1a - 1280x768@120Hz RB */ | ||||
348 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (140250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
349 | 1360, 1440, 0, 768, 771, 778, 813, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (140250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
350 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (140250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
351 | /* 0x1b - 1280x800@60Hz RB */ | ||||
352 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (71000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (823), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
353 | 1360, 1440, 0, 800, 803, 809, 823, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (71000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (823), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
354 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (71000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (823), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
355 | /* 0x1c - 1280x800@60Hz */ | ||||
356 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (83500), .hdisplay = (1280), .hsync_start = (1352), .hsync_end = (1480), .htotal = (1680), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (831), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
357 | 1480, 1680, 0, 800, 803, 809, 831, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (83500), .hdisplay = (1280), .hsync_start = (1352), .hsync_end = (1480), .htotal = (1680), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (831), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
358 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (83500), .hdisplay = (1280), .hsync_start = (1352), .hsync_end = (1480), .htotal = (1680), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (831), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
359 | /* 0x1d - 1280x800@75Hz */ | ||||
360 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (838), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
361 | 1488, 1696, 0, 800, 803, 809, 838, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (838), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
362 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (838), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
363 | /* 0x1e - 1280x800@85Hz */ | ||||
364 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (122500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (843), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
365 | 1496, 1712, 0, 800, 803, 809, 843, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (122500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (843), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
366 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (122500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (843), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
367 | /* 0x1f - 1280x800@120Hz RB */ | ||||
368 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (847), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
369 | 1360, 1440, 0, 800, 803, 809, 847, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (847), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
370 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (847), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
371 | /* 0x20 - 1280x960@60Hz */ | ||||
372 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1376), .hsync_end = (1488), .htotal = (1800), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
373 | 1488, 1800, 0, 960, 961, 964, 1000, 0,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1376), .hsync_end = (1488), .htotal = (1800), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
374 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1376), .hsync_end = (1488), .htotal = (1800), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
375 | /* 0x21 - 1280x960@85Hz */ | ||||
376 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1011), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
377 | 1504, 1728, 0, 960, 961, 964, 1011, 0,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1011), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
378 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1011), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
379 | /* 0x22 - 1280x960@120Hz RB */ | ||||
380 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (960), .vsync_start = (963), .vsync_end = (967), .vtotal = (1017), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
381 | 1360, 1440, 0, 960, 963, 967, 1017, 0,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (960), .vsync_start = (963), .vsync_end = (967), .vtotal = (1017), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
382 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (960), .vsync_start = (963), .vsync_end = (967), .vtotal = (1017), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
383 | /* 0x23 - 1280x1024@60Hz */ | ||||
384 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
385 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
386 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
387 | /* 0x24 - 1280x1024@75Hz */ | ||||
388 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
389 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
390 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
391 | /* 0x25 - 1280x1024@85Hz */ | ||||
392 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (157500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1072 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
393 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (157500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1072 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
394 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (157500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1072 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
395 | /* 0x26 - 1280x1024@120Hz RB */ | ||||
396 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (187250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1027), .vsync_end = (1034), .vtotal = (1084 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
397 | 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (187250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1027), .vsync_end = (1034), .vtotal = (1084 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
398 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (187250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1027), .vsync_end = (1034), .vtotal = (1084 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
399 | /* 0x27 - 1360x768@60Hz */ | ||||
400 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,.name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1360), .hsync_start = (1424), .hsync_end = (1536), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (795), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
401 | 1536, 1792, 0, 768, 771, 777, 795, 0,.name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1360), .hsync_start = (1424), .hsync_end = (1536), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (795), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
402 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1360), .hsync_start = (1424), .hsync_end = (1536), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (795), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
403 | /* 0x28 - 1360x768@120Hz RB */ | ||||
404 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,.name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (148250), .hdisplay = (1360), .hsync_start = (1408), .hsync_end = (1440), .htotal = (1520), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (776), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
405 | 1440, 1520, 0, 768, 771, 776, 813, 0,.name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (148250), .hdisplay = (1360), .hsync_start = (1408), .hsync_end = (1440), .htotal = (1520), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (776), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
406 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (148250), .hdisplay = (1360), .hsync_start = (1408), .hsync_end = (1440), .htotal = (1520), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (776), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
407 | /* 0x51 - 1366x768@60Hz */ | ||||
408 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,.name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1366), .hsync_start = (1436), .hsync_end = (1579), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (774), .vtotal = (798), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
409 | 1579, 1792, 0, 768, 771, 774, 798, 0,.name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1366), .hsync_start = (1436), .hsync_end = (1579), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (774), .vtotal = (798), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
410 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1366), .hsync_start = (1436), .hsync_end = (1579), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (774), .vtotal = (798), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
411 | /* 0x56 - 1366x768@60Hz */ | ||||
412 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,.name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1366), .hsync_start = (1380), .hsync_end = (1436), .htotal = (1500), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
413 | 1436, 1500, 0, 768, 769, 772, 800, 0,.name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1366), .hsync_start = (1380), .hsync_end = (1436), .htotal = (1500), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
414 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1366), .hsync_start = (1380), .hsync_end = (1436), .htotal = (1500), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
415 | /* 0x29 - 1400x1050@60Hz RB */ | ||||
416 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (101000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
417 | 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (101000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
418 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (101000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
419 | /* 0x2a - 1400x1050@60Hz */ | ||||
420 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (121750), .hdisplay = (1400), .hsync_start = (1488), .hsync_end = (1632), .htotal = (1864), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
421 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (121750), .hdisplay = (1400), .hsync_start = (1488), .hsync_end = (1632), .htotal = (1864), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
422 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (121750), .hdisplay = (1400), .hsync_start = (1488), .hsync_end = (1632), .htotal = (1864), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
423 | /* 0x2b - 1400x1050@75Hz */ | ||||
424 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (156000), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1648), .htotal = (1896), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
425 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (156000), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1648), .htotal = (1896), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
426 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (156000), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1648), .htotal = (1896), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
427 | /* 0x2c - 1400x1050@85Hz */ | ||||
428 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (179500), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1656), .htotal = (1912), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
429 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (179500), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1656), .htotal = (1912), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
430 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (179500), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1656), .htotal = (1912), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
431 | /* 0x2d - 1400x1050@120Hz RB */ | ||||
432 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (208000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
433 | 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (208000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
434 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (208000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
435 | /* 0x2e - 1440x900@60Hz RB */ | ||||
436 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (88750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (926), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
437 | 1520, 1600, 0, 900, 903, 909, 926, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (88750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (926), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
438 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (88750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (926), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
439 | /* 0x2f - 1440x900@60Hz */ | ||||
440 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1440), .hsync_start = (1520), .hsync_end = (1672), .htotal = (1904), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (934), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
441 | 1672, 1904, 0, 900, 903, 909, 934, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1440), .hsync_start = (1520), .hsync_end = (1672), .htotal = (1904), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (934), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
442 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1440), .hsync_start = (1520), .hsync_end = (1672), .htotal = (1904), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (934), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
443 | /* 0x30 - 1440x900@75Hz */ | ||||
444 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (136750), .hdisplay = (1440), .hsync_start = (1536), .hsync_end = (1688), .htotal = (1936), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (942), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
445 | 1688, 1936, 0, 900, 903, 909, 942, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (136750), .hdisplay = (1440), .hsync_start = (1536), .hsync_end = (1688), .htotal = (1936), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (942), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
446 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (136750), .hdisplay = (1440), .hsync_start = (1536), .hsync_end = (1688), .htotal = (1936), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (942), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
447 | /* 0x31 - 1440x900@85Hz */ | ||||
448 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (157000), .hdisplay = (1440), .hsync_start = (1544), .hsync_end = (1696), .htotal = (1952), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (948), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
449 | 1696, 1952, 0, 900, 903, 909, 948, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (157000), .hdisplay = (1440), .hsync_start = (1544), .hsync_end = (1696), .htotal = (1952), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (948), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
450 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (157000), .hdisplay = (1440), .hsync_start = (1544), .hsync_end = (1696), .htotal = (1952), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (948), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
451 | /* 0x32 - 1440x900@120Hz RB */ | ||||
452 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (182750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (953), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
453 | 1520, 1600, 0, 900, 903, 909, 953, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (182750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (953), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
454 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (182750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (953), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
455 | /* 0x53 - 1600x900@60Hz */ | ||||
456 | { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,.name = "1600x900", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1600), .hsync_start = (1624), .hsync_end = (1704), .htotal = (1800), .hskew = (0), .vdisplay = (900), .vsync_start = (901), .vsync_end = (904), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
457 | 1704, 1800, 0, 900, 901, 904, 1000, 0,.name = "1600x900", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1600), .hsync_start = (1624), .hsync_end = (1704), .htotal = (1800), .hskew = (0), .vdisplay = (900), .vsync_start = (901), .vsync_end = (904), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
458 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x900", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1600), .hsync_start = (1624), .hsync_end = (1704), .htotal = (1800), .hskew = (0), .vdisplay = (900), .vsync_start = (901), .vsync_end = (904), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
459 | /* 0x33 - 1600x1200@60Hz */ | ||||
460 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
461 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
462 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
463 | /* 0x34 - 1600x1200@65Hz */ | ||||
464 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
465 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
466 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
467 | /* 0x35 - 1600x1200@70Hz */ | ||||
468 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (189000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
469 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (189000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
470 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (189000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
471 | /* 0x36 - 1600x1200@75Hz */ | ||||
472 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (202500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
473 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (202500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
474 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (202500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
475 | /* 0x37 - 1600x1200@85Hz */ | ||||
476 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (229500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
477 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (229500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
478 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (229500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
479 | /* 0x38 - 1600x1200@120Hz RB */ | ||||
480 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (268250), .hdisplay = (1600), .hsync_start = (1648), .hsync_end = (1680), .htotal = (1760), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1207), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
481 | 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (268250), .hdisplay = (1600), .hsync_start = (1648), .hsync_end = (1680), .htotal = (1760), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1207), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
482 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (268250), .hdisplay = (1600), .hsync_start = (1648), .hsync_end = (1680), .htotal = (1760), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1207), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
483 | /* 0x39 - 1680x1050@60Hz RB */ | ||||
484 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (119000), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
485 | 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (119000), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
486 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (119000), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
487 | /* 0x3a - 1680x1050@60Hz */ | ||||
488 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1680), .hsync_start = (1784), .hsync_end = (1960), .htotal = (2240), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
489 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1680), .hsync_start = (1784), .hsync_end = (1960), .htotal = (2240), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
490 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1680), .hsync_start = (1784), .hsync_end = (1960), .htotal = (2240), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
491 | /* 0x3b - 1680x1050@75Hz */ | ||||
492 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (187000), .hdisplay = (1680), .hsync_start = (1800), .hsync_end = (1976), .htotal = (2272), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
493 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (187000), .hdisplay = (1680), .hsync_start = (1800), .hsync_end = (1976), .htotal = (2272), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
494 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (187000), .hdisplay = (1680), .hsync_start = (1800), .hsync_end = (1976), .htotal = (2272), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
495 | /* 0x3c - 1680x1050@85Hz */ | ||||
496 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (214750), .hdisplay = (1680), .hsync_start = (1808), .hsync_end = (1984), .htotal = (2288), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
497 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (214750), .hdisplay = (1680), .hsync_start = (1808), .hsync_end = (1984), .htotal = (2288), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
498 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (214750), .hdisplay = (1680), .hsync_start = (1808), .hsync_end = (1984), .htotal = (2288), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
499 | /* 0x3d - 1680x1050@120Hz RB */ | ||||
500 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (245500), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
501 | 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (245500), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
502 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (245500), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
503 | /* 0x3e - 1792x1344@60Hz */ | ||||
504 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (204750), .hdisplay = (1792), .hsync_start = (1920), .hsync_end = (2120), .htotal = (2448), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1394 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
505 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (204750), .hdisplay = (1792), .hsync_start = (1920), .hsync_end = (2120), .htotal = (2448), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1394 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
506 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (204750), .hdisplay = (1792), .hsync_start = (1920), .hsync_end = (2120), .htotal = (2448), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1394 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
507 | /* 0x3f - 1792x1344@75Hz */ | ||||
508 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (261000), .hdisplay = (1792), .hsync_start = (1888), .hsync_end = (2104), .htotal = (2456), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1417 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
509 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (261000), .hdisplay = (1792), .hsync_start = (1888), .hsync_end = (2104), .htotal = (2456), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1417 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
510 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (261000), .hdisplay = (1792), .hsync_start = (1888), .hsync_end = (2104), .htotal = (2456), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1417 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
511 | /* 0x40 - 1792x1344@120Hz RB */ | ||||
512 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (333250), .hdisplay = (1792), .hsync_start = (1840), .hsync_end = (1872), .htotal = (1952), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1347), .vsync_end = (1351), .vtotal = (1423 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
513 | 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (333250), .hdisplay = (1792), .hsync_start = (1840), .hsync_end = (1872), .htotal = (1952), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1347), .vsync_end = (1351), .vtotal = (1423 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
514 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (333250), .hdisplay = (1792), .hsync_start = (1840), .hsync_end = (1872), .htotal = (1952), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1347), .vsync_end = (1351), .vtotal = (1423 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
515 | /* 0x41 - 1856x1392@60Hz */ | ||||
516 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (218250), .hdisplay = (1856), .hsync_start = (1952), .hsync_end = (2176), .htotal = (2528), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1439 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
517 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (218250), .hdisplay = (1856), .hsync_start = (1952), .hsync_end = (2176), .htotal = (2528), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1439 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
518 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (218250), .hdisplay = (1856), .hsync_start = (1952), .hsync_end = (2176), .htotal = (2528), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1439 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
519 | /* 0x42 - 1856x1392@75Hz */ | ||||
520 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (288000), .hdisplay = (1856), .hsync_start = (1984), .hsync_end = (2208), .htotal = (2560), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
521 | 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (288000), .hdisplay = (1856), .hsync_start = (1984), .hsync_end = (2208), .htotal = (2560), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
522 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (288000), .hdisplay = (1856), .hsync_start = (1984), .hsync_end = (2208), .htotal = (2560), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
523 | /* 0x43 - 1856x1392@120Hz RB */ | ||||
524 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (356500), .hdisplay = (1856), .hsync_start = (1904), .hsync_end = (1936), .htotal = (2016), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1395), .vsync_end = (1399), .vtotal = (1474 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
525 | 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (356500), .hdisplay = (1856), .hsync_start = (1904), .hsync_end = (1936), .htotal = (2016), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1395), .vsync_end = (1399), .vtotal = (1474 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
526 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (356500), .hdisplay = (1856), .hsync_start = (1904), .hsync_end = (1936), .htotal = (2016), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1395), .vsync_end = (1399), .vtotal = (1474 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
527 | /* 0x52 - 1920x1080@60Hz */ | ||||
528 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
529 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
530 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
531 | /* 0x44 - 1920x1200@60Hz RB */ | ||||
532 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (154000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1235 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
533 | 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (154000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1235 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
534 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (154000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1235 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
535 | /* 0x45 - 1920x1200@60Hz */ | ||||
536 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (193250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2256), .htotal = (2592), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1245 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
537 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (193250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2256), .htotal = (2592), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1245 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
538 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (193250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2256), .htotal = (2592), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1245 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
539 | /* 0x46 - 1920x1200@75Hz */ | ||||
540 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (245250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2264), .htotal = (2608), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1255 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
541 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (245250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2264), .htotal = (2608), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1255 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
542 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (245250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2264), .htotal = (2608), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1255 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
543 | /* 0x47 - 1920x1200@85Hz */ | ||||
544 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (281250), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2272), .htotal = (2624), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1262 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
545 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (281250), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2272), .htotal = (2624), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1262 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
546 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (281250), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2272), .htotal = (2624), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1262 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
547 | /* 0x48 - 1920x1200@120Hz RB */ | ||||
548 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (317000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
549 | 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (317000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
550 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (317000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
551 | /* 0x49 - 1920x1440@60Hz */ | ||||
552 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (234000), .hdisplay = (1920), .hsync_start = (2048), .hsync_end = (2256), .htotal = (2600), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
553 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (234000), .hdisplay = (1920), .hsync_start = (2048), .hsync_end = (2256), .htotal = (2600), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
554 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (234000), .hdisplay = (1920), .hsync_start = (2048), .hsync_end = (2256), .htotal = (2600), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
555 | /* 0x4a - 1920x1440@75Hz */ | ||||
556 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2288), .htotal = (2640), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
557 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2288), .htotal = (2640), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
558 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2288), .htotal = (2640), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
559 | /* 0x4b - 1920x1440@120Hz RB */ | ||||
560 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (380500), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1443), .vsync_end = (1447), .vtotal = (1525 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
561 | 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (380500), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1443), .vsync_end = (1447), .vtotal = (1525 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
562 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (380500), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1443), .vsync_end = (1447), .vtotal = (1525 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
563 | /* 0x54 - 2048x1152@60Hz */ | ||||
564 | { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,.name = "2048x1152", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (2048), .hsync_start = (2074), .hsync_end = (2154), .htotal = (2250), .hskew = (0), .vdisplay = (1152) , .vsync_start = (1153), .vsync_end = (1156), .vtotal = (1200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
565 | 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,.name = "2048x1152", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (2048), .hsync_start = (2074), .hsync_end = (2154), .htotal = (2250), .hskew = (0), .vdisplay = (1152) , .vsync_start = (1153), .vsync_end = (1156), .vtotal = (1200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
566 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2048x1152", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (2048), .hsync_start = (2074), .hsync_end = (2154), .htotal = (2250), .hskew = (0), .vdisplay = (1152) , .vsync_start = (1153), .vsync_end = (1156), .vtotal = (1200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
567 | /* 0x4c - 2560x1600@60Hz RB */ | ||||
568 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (268500), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1646 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
569 | 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (268500), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1646 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
570 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (268500), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1646 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
571 | /* 0x4d - 2560x1600@60Hz */ | ||||
572 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (348500), .hdisplay = (2560), .hsync_start = (2752), .hsync_end = (3032), .htotal = (3504), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1658 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
573 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (348500), .hdisplay = (2560), .hsync_start = (2752), .hsync_end = (3032), .htotal = (3504), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1658 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
574 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (348500), .hdisplay = (2560), .hsync_start = (2752), .hsync_end = (3032), .htotal = (3504), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1658 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
575 | /* 0x4e - 2560x1600@75Hz */ | ||||
576 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (443250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1672 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
577 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (443250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1672 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
578 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (443250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1672 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
579 | /* 0x4f - 2560x1600@85Hz */ | ||||
580 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (505250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1682 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
581 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (505250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1682 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
582 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (505250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1682 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
583 | /* 0x50 - 2560x1600@120Hz RB */ | ||||
584 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (552750), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1694 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
585 | 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (552750), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1694 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
586 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (552750), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1694 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
587 | /* 0x57 - 4096x2160@60Hz RB */ | ||||
588 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556744), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
589 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556744), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
590 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556744), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
591 | /* 0x58 - 4096x2160@59.94Hz RB */ | ||||
592 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556188), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
593 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556188), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
594 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556188), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
595 | }; | ||||
596 | |||||
597 | /* | ||||
598 | * These more or less come from the DMT spec. The 720x400 modes are | ||||
599 | * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 | ||||
600 | * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode | ||||
601 | * should be 1152x870, again for the Mac, but instead we use the x864 DMT | ||||
602 | * mode. | ||||
603 | * | ||||
604 | * The DMT modes have been fact-checked; the rest are mild guesses. | ||||
605 | */ | ||||
606 | static const struct drm_display_mode edid_est_modes[] = { | ||||
607 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
608 | 968, 1056, 0, 600, 601, 605, 628, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
609 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 800x600@60Hz */ | ||||
610 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
611 | 896, 1024, 0, 600, 601, 603, 625, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
612 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 800x600@56Hz */ | ||||
613 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
614 | 720, 840, 0, 480, 481, 484, 500, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
615 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 640x480@75Hz */ | ||||
616 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
617 | 704, 832, 0, 480, 489, 492, 520, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
618 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 640x480@72Hz */ | ||||
619 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (30240), .hdisplay = (640), .hsync_start = (704), .hsync_end = (768), .htotal = (864), .hskew = (0), .vdisplay = (480), . vsync_start = (483), .vsync_end = (486), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
620 | 768, 864, 0, 480, 483, 486, 525, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (30240), .hdisplay = (640), .hsync_start = (704), .hsync_end = (768), .htotal = (864), .hskew = (0), .vdisplay = (480), . vsync_start = (483), .vsync_end = (486), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
621 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (30240), .hdisplay = (640), .hsync_start = (704), .hsync_end = (768), .htotal = (864), .hskew = (0), .vdisplay = (480), . vsync_start = (483), .vsync_end = (486), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 640x480@67Hz */ | ||||
622 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
623 | 752, 800, 0, 480, 490, 492, 525, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
624 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 640x480@60Hz */ | ||||
625 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (421), .vsync_end = (423), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
626 | 846, 900, 0, 400, 421, 423, 449, 0,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (421), .vsync_end = (423), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
627 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (421), .vsync_end = (423), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 720x400@88Hz */ | ||||
628 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (28320), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (412), .vsync_end = (414), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
629 | 846, 900, 0, 400, 412, 414, 449, 0,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (28320), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (412), .vsync_end = (414), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
630 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x400", .status = 0, .type = ((1<<6)), .clock = (28320), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (412), .vsync_end = (414), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, /* 720x400@70Hz */ | ||||
631 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
632 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
633 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 1280x1024@75Hz */ | ||||
634 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
635 | 1136, 1312, 0, 768, 769, 772, 800, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
636 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 1024x768@75Hz */ | ||||
637 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
638 | 1184, 1328, 0, 768, 771, 777, 806, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
639 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 1024x768@70Hz */ | ||||
640 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
641 | 1184, 1344, 0, 768, 771, 777, 806, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
642 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 1024x768@60Hz */ | ||||
643 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
644 | 1208, 1264, 0, 768, 768, 776, 817, 0,.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
645 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE).name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) }, /* 1024x768@43Hz */ | ||||
646 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,.name = "832x624", .status = 0, .type = ((1<<6)), .clock = (57284), .hdisplay = (832), .hsync_start = (864), .hsync_end = (928), .htotal = (1152), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (628), .vtotal = (667), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
647 | 928, 1152, 0, 624, 625, 628, 667, 0,.name = "832x624", .status = 0, .type = ((1<<6)), .clock = (57284), .hdisplay = (832), .hsync_start = (864), .hsync_end = (928), .htotal = (1152), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (628), .vtotal = (667), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
648 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "832x624", .status = 0, .type = ((1<<6)), .clock = (57284), .hdisplay = (832), .hsync_start = (864), .hsync_end = (928), .htotal = (1152), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (628), .vtotal = (667), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 832x624@75Hz */ | ||||
649 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
650 | 896, 1056, 0, 600, 601, 604, 625, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
651 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 800x600@75Hz */ | ||||
652 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
653 | 976, 1040, 0, 600, 637, 643, 666, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
654 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 800x600@72Hz */ | ||||
655 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,.name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
656 | 1344, 1600, 0, 864, 865, 868, 900, 0,.name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
657 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 1152x864@75Hz */ | ||||
658 | }; | ||||
659 | |||||
660 | struct minimode { | ||||
661 | short w; | ||||
662 | short h; | ||||
663 | short r; | ||||
664 | short rb; | ||||
665 | }; | ||||
666 | |||||
667 | static const struct minimode est3_modes[] = { | ||||
668 | /* byte 6 */ | ||||
669 | { 640, 350, 85, 0 }, | ||||
670 | { 640, 400, 85, 0 }, | ||||
671 | { 720, 400, 85, 0 }, | ||||
672 | { 640, 480, 85, 0 }, | ||||
673 | { 848, 480, 60, 0 }, | ||||
674 | { 800, 600, 85, 0 }, | ||||
675 | { 1024, 768, 85, 0 }, | ||||
676 | { 1152, 864, 75, 0 }, | ||||
677 | /* byte 7 */ | ||||
678 | { 1280, 768, 60, 1 }, | ||||
679 | { 1280, 768, 60, 0 }, | ||||
680 | { 1280, 768, 75, 0 }, | ||||
681 | { 1280, 768, 85, 0 }, | ||||
682 | { 1280, 960, 60, 0 }, | ||||
683 | { 1280, 960, 85, 0 }, | ||||
684 | { 1280, 1024, 60, 0 }, | ||||
685 | { 1280, 1024, 85, 0 }, | ||||
686 | /* byte 8 */ | ||||
687 | { 1360, 768, 60, 0 }, | ||||
688 | { 1440, 900, 60, 1 }, | ||||
689 | { 1440, 900, 60, 0 }, | ||||
690 | { 1440, 900, 75, 0 }, | ||||
691 | { 1440, 900, 85, 0 }, | ||||
692 | { 1400, 1050, 60, 1 }, | ||||
693 | { 1400, 1050, 60, 0 }, | ||||
694 | { 1400, 1050, 75, 0 }, | ||||
695 | /* byte 9 */ | ||||
696 | { 1400, 1050, 85, 0 }, | ||||
697 | { 1680, 1050, 60, 1 }, | ||||
698 | { 1680, 1050, 60, 0 }, | ||||
699 | { 1680, 1050, 75, 0 }, | ||||
700 | { 1680, 1050, 85, 0 }, | ||||
701 | { 1600, 1200, 60, 0 }, | ||||
702 | { 1600, 1200, 65, 0 }, | ||||
703 | { 1600, 1200, 70, 0 }, | ||||
704 | /* byte 10 */ | ||||
705 | { 1600, 1200, 75, 0 }, | ||||
706 | { 1600, 1200, 85, 0 }, | ||||
707 | { 1792, 1344, 60, 0 }, | ||||
708 | { 1792, 1344, 75, 0 }, | ||||
709 | { 1856, 1392, 60, 0 }, | ||||
710 | { 1856, 1392, 75, 0 }, | ||||
711 | { 1920, 1200, 60, 1 }, | ||||
712 | { 1920, 1200, 60, 0 }, | ||||
713 | /* byte 11 */ | ||||
714 | { 1920, 1200, 75, 0 }, | ||||
715 | { 1920, 1200, 85, 0 }, | ||||
716 | { 1920, 1440, 60, 0 }, | ||||
717 | { 1920, 1440, 75, 0 }, | ||||
718 | }; | ||||
719 | |||||
720 | static const struct minimode extra_modes[] = { | ||||
721 | { 1024, 576, 60, 0 }, | ||||
722 | { 1366, 768, 60, 0 }, | ||||
723 | { 1600, 900, 60, 0 }, | ||||
724 | { 1680, 945, 60, 0 }, | ||||
725 | { 1920, 1080, 60, 0 }, | ||||
726 | { 2048, 1152, 60, 0 }, | ||||
727 | { 2048, 1536, 60, 0 }, | ||||
728 | }; | ||||
729 | |||||
730 | /* | ||||
731 | * From CEA/CTA-861 spec. | ||||
732 | * | ||||
733 | * Do not access directly, instead always use cea_mode_for_vic(). | ||||
734 | */ | ||||
735 | static const struct drm_display_mode edid_cea_modes_1[] = { | ||||
736 | /* 1 - 640x480@60Hz 4:3 */ | ||||
737 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
738 | 752, 800, 0, 480, 490, 492, 525, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
739 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
740 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
741 | /* 2 - 720x480@60Hz 4:3 */ | ||||
742 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
743 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
744 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
745 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
746 | /* 3 - 720x480@60Hz 16:9 */ | ||||
747 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
748 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
749 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
750 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
751 | /* 4 - 1280x720@60Hz 16:9 */ | ||||
752 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
753 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
754 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
755 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
756 | /* 5 - 1920x1080i@60Hz 16:9 */ | ||||
757 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
758 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
759 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
760 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)), | ||||
761 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
762 | /* 6 - 720(1440)x480i@60Hz 4:3 */ | ||||
763 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
764 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
765 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
766 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
767 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
768 | /* 7 - 720(1440)x480i@60Hz 16:9 */ | ||||
769 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
770 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
771 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
772 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
773 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
774 | /* 8 - 720(1440)x240@60Hz 4:3 */ | ||||
775 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
776 | 801, 858, 0, 240, 244, 247, 262, 0,.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
777 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
778 | DRM_MODE_FLAG_DBLCLK).name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ), | ||||
779 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
780 | /* 9 - 720(1440)x240@60Hz 16:9 */ | ||||
781 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
782 | 801, 858, 0, 240, 244, 247, 262, 0,.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
783 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
784 | DRM_MODE_FLAG_DBLCLK).name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ), | ||||
785 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
786 | /* 10 - 2880x480i@60Hz 4:3 */ | ||||
787 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
788 | 3204, 3432, 0, 480, 488, 494, 525, 0,.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
789 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
790 | DRM_MODE_FLAG_INTERLACE).name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)), | ||||
791 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
792 | /* 11 - 2880x480i@60Hz 16:9 */ | ||||
793 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
794 | 3204, 3432, 0, 480, 488, 494, 525, 0,.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
795 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
796 | DRM_MODE_FLAG_INTERLACE).name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)), | ||||
797 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
798 | /* 12 - 2880x240@60Hz 4:3 */ | ||||
799 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,.name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
800 | 3204, 3432, 0, 240, 244, 247, 262, 0,.name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
801 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
802 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
803 | /* 13 - 2880x240@60Hz 16:9 */ | ||||
804 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,.name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
805 | 3204, 3432, 0, 240, 244, 247, 262, 0,.name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
806 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
807 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
808 | /* 14 - 1440x480@60Hz 4:3 */ | ||||
809 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,.name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
810 | 1596, 1716, 0, 480, 489, 495, 525, 0,.name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
811 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
812 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
813 | /* 15 - 1440x480@60Hz 16:9 */ | ||||
814 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,.name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
815 | 1596, 1716, 0, 480, 489, 495, 525, 0,.name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
816 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
817 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
818 | /* 16 - 1920x1080@60Hz 16:9 */ | ||||
819 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
820 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
821 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
822 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
823 | /* 17 - 720x576@50Hz 4:3 */ | ||||
824 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
825 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
826 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
827 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
828 | /* 18 - 720x576@50Hz 16:9 */ | ||||
829 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
830 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
831 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
832 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
833 | /* 19 - 1280x720@50Hz 16:9 */ | ||||
834 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
835 | 1760, 1980, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
836 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
837 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
838 | /* 20 - 1920x1080i@50Hz 16:9 */ | ||||
839 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
840 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
841 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
842 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)), | ||||
843 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
844 | /* 21 - 720(1440)x576i@50Hz 4:3 */ | ||||
845 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
846 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
847 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
848 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
849 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
850 | /* 22 - 720(1440)x576i@50Hz 16:9 */ | ||||
851 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
852 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
853 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
854 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
855 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
856 | /* 23 - 720(1440)x288@50Hz 4:3 */ | ||||
857 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
858 | 795, 864, 0, 288, 290, 293, 312, 0,.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
859 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
860 | DRM_MODE_FLAG_DBLCLK).name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ), | ||||
861 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
862 | /* 24 - 720(1440)x288@50Hz 16:9 */ | ||||
863 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
864 | 795, 864, 0, 288, 290, 293, 312, 0,.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
865 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
866 | DRM_MODE_FLAG_DBLCLK).name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ), | ||||
867 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
868 | /* 25 - 2880x576i@50Hz 4:3 */ | ||||
869 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
870 | 3180, 3456, 0, 576, 580, 586, 625, 0,.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
871 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
872 | DRM_MODE_FLAG_INTERLACE).name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)), | ||||
873 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
874 | /* 26 - 2880x576i@50Hz 16:9 */ | ||||
875 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
876 | 3180, 3456, 0, 576, 580, 586, 625, 0,.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
877 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
878 | DRM_MODE_FLAG_INTERLACE).name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)), | ||||
879 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
880 | /* 27 - 2880x288@50Hz 4:3 */ | ||||
881 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,.name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
882 | 3180, 3456, 0, 288, 290, 293, 312, 0,.name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
883 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
884 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
885 | /* 28 - 2880x288@50Hz 16:9 */ | ||||
886 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,.name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
887 | 3180, 3456, 0, 288, 290, 293, 312, 0,.name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
888 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
889 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
890 | /* 29 - 1440x576@50Hz 4:3 */ | ||||
891 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,.name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
892 | 1592, 1728, 0, 576, 581, 586, 625, 0,.name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
893 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
894 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
895 | /* 30 - 1440x576@50Hz 16:9 */ | ||||
896 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,.name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
897 | 1592, 1728, 0, 576, 581, 586, 625, 0,.name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
898 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
899 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
900 | /* 31 - 1920x1080@50Hz 16:9 */ | ||||
901 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
902 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
903 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
904 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
905 | /* 32 - 1920x1080@24Hz 16:9 */ | ||||
906 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
907 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
908 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
909 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
910 | /* 33 - 1920x1080@25Hz 16:9 */ | ||||
911 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
912 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
913 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
914 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
915 | /* 34 - 1920x1080@30Hz 16:9 */ | ||||
916 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
917 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
918 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
919 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
920 | /* 35 - 2880x480@60Hz 4:3 */ | ||||
921 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,.name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
922 | 3192, 3432, 0, 480, 489, 495, 525, 0,.name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
923 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
924 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
925 | /* 36 - 2880x480@60Hz 16:9 */ | ||||
926 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,.name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
927 | 3192, 3432, 0, 480, 489, 495, 525, 0,.name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
928 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
929 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
930 | /* 37 - 2880x576@50Hz 4:3 */ | ||||
931 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,.name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
932 | 3184, 3456, 0, 576, 581, 586, 625, 0,.name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
933 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
934 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
935 | /* 38 - 2880x576@50Hz 16:9 */ | ||||
936 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,.name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
937 | 3184, 3456, 0, 576, 581, 586, 625, 0,.name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
938 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
939 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
940 | /* 39 - 1920x1080i@50Hz 16:9 */ | ||||
941 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1920), .hsync_start = (1952), .hsync_end = (2120), .htotal = (2304), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1126), .vsync_end = (1136), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<3) | (1<< 4)) | ||||
942 | 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1920), .hsync_start = (1952), .hsync_end = (2120), .htotal = (2304), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1126), .vsync_end = (1136), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<3) | (1<< 4)) | ||||
943 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1920), .hsync_start = (1952), .hsync_end = (2120), .htotal = (2304), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1126), .vsync_end = (1136), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<3) | (1<< 4)) | ||||
944 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1920), .hsync_start = (1952), .hsync_end = (2120), .htotal = (2304), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1126), .vsync_end = (1136), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<3) | (1<< 4)), | ||||
945 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
946 | /* 40 - 1920x1080i@100Hz 16:9 */ | ||||
947 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
948 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
949 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
950 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)), | ||||
951 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
952 | /* 41 - 1280x720@100Hz 16:9 */ | ||||
953 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
954 | 1760, 1980, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
955 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
956 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
957 | /* 42 - 720x576@100Hz 4:3 */ | ||||
958 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
959 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
960 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
961 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
962 | /* 43 - 720x576@100Hz 16:9 */ | ||||
963 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
964 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
965 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
966 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
967 | /* 44 - 720(1440)x576i@100Hz 4:3 */ | ||||
968 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
969 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
970 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
971 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
972 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
973 | /* 45 - 720(1440)x576i@100Hz 16:9 */ | ||||
974 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
975 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
976 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
977 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
978 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
979 | /* 46 - 1920x1080i@120Hz 16:9 */ | ||||
980 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
981 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
982 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
983 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)), | ||||
984 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
985 | /* 47 - 1280x720@120Hz 16:9 */ | ||||
986 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
987 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
988 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
989 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
990 | /* 48 - 720x480@120Hz 4:3 */ | ||||
991 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
992 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
993 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
994 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
995 | /* 49 - 720x480@120Hz 16:9 */ | ||||
996 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
997 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
998 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
999 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1000 | /* 50 - 720(1440)x480i@120Hz 4:3 */ | ||||
1001 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1002 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1003 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1004 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1005 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1006 | /* 51 - 720(1440)x480i@120Hz 16:9 */ | ||||
1007 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1008 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1009 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1010 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1011 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1012 | /* 52 - 720x576@200Hz 4:3 */ | ||||
1013 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1014 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1015 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
1016 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1017 | /* 53 - 720x576@200Hz 16:9 */ | ||||
1018 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1019 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1020 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
1021 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1022 | /* 54 - 720(1440)x576i@200Hz 4:3 */ | ||||
1023 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1024 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1025 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1026 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1027 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1028 | /* 55 - 720(1440)x576i@200Hz 16:9 */ | ||||
1029 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1030 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1031 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1032 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1033 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1034 | /* 56 - 720x480@240Hz 4:3 */ | ||||
1035 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1036 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1037 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
1038 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1039 | /* 57 - 720x480@240Hz 16:9 */ | ||||
1040 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1041 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1042 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
1043 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1044 | /* 58 - 720(1440)x480i@240Hz 4:3 */ | ||||
1045 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1046 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1047 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1048 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1049 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1050 | /* 59 - 720(1440)x480i@240Hz 16:9 */ | ||||
1051 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1052 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1053 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1054 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1055 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1056 | /* 60 - 1280x720@24Hz 16:9 */ | ||||
1057 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1058 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1059 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1060 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1061 | /* 61 - 1280x720@25Hz 16:9 */ | ||||
1062 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1063 | 3740, 3960, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1064 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1065 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1066 | /* 62 - 1280x720@30Hz 16:9 */ | ||||
1067 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1068 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1069 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1070 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1071 | /* 63 - 1920x1080@120Hz 16:9 */ | ||||
1072 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1073 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1074 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1075 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1076 | /* 64 - 1920x1080@100Hz 16:9 */ | ||||
1077 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1078 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1079 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1080 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1081 | /* 65 - 1280x720@24Hz 64:27 */ | ||||
1082 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1083 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1084 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1085 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1086 | /* 66 - 1280x720@25Hz 64:27 */ | ||||
1087 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1088 | 3740, 3960, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1089 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1090 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1091 | /* 67 - 1280x720@30Hz 64:27 */ | ||||
1092 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1093 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1094 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1095 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1096 | /* 68 - 1280x720@50Hz 64:27 */ | ||||
1097 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1098 | 1760, 1980, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1099 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1100 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1101 | /* 69 - 1280x720@60Hz 64:27 */ | ||||
1102 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1103 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1104 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1105 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1106 | /* 70 - 1280x720@100Hz 64:27 */ | ||||
1107 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1108 | 1760, 1980, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1109 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1110 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1111 | /* 71 - 1280x720@120Hz 64:27 */ | ||||
1112 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1113 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1114 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1115 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1116 | /* 72 - 1920x1080@24Hz 64:27 */ | ||||
1117 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1118 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1119 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1120 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1121 | /* 73 - 1920x1080@25Hz 64:27 */ | ||||
1122 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1123 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1124 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1125 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1126 | /* 74 - 1920x1080@30Hz 64:27 */ | ||||
1127 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1128 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1129 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1130 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1131 | /* 75 - 1920x1080@50Hz 64:27 */ | ||||
1132 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1133 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1134 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1135 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1136 | /* 76 - 1920x1080@60Hz 64:27 */ | ||||
1137 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1138 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1139 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1140 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1141 | /* 77 - 1920x1080@100Hz 64:27 */ | ||||
1142 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1143 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1144 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1145 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1146 | /* 78 - 1920x1080@120Hz 64:27 */ | ||||
1147 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1148 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1149 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1150 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1151 | /* 79 - 1680x720@24Hz 64:27 */ | ||||
1152 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1153 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1154 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1155 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1156 | /* 80 - 1680x720@25Hz 64:27 */ | ||||
1157 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2908), .hsync_end = (2948), .htotal = (3168), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1158 | 2948, 3168, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2908), .hsync_end = (2948), .htotal = (3168), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1159 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2908), .hsync_end = (2948), .htotal = (3168), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1160 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1161 | /* 81 - 1680x720@30Hz 64:27 */ | ||||
1162 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2380), .hsync_end = (2420), .htotal = (2640), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1163 | 2420, 2640, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2380), .hsync_end = (2420), .htotal = (2640), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1164 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2380), .hsync_end = (2420), .htotal = (2640), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1165 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1166 | /* 82 - 1680x720@50Hz 64:27 */ | ||||
1167 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (82500), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1168 | 1980, 2200, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (82500), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1169 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (82500), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1170 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1171 | /* 83 - 1680x720@60Hz 64:27 */ | ||||
1172 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1173 | 1980, 2200, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1174 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1175 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1176 | /* 84 - 1680x720@100Hz 64:27 */ | ||||
1177 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (165000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1178 | 1780, 2000, 0, 720, 725, 730, 825, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (165000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1179 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (165000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1180 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1181 | /* 85 - 1680x720@120Hz 64:27 */ | ||||
1182 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1183 | 1780, 2000, 0, 720, 725, 730, 825, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1184 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1185 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1186 | /* 86 - 2560x1080@24Hz 64:27 */ | ||||
1187 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1188 | 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1189 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1190 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1191 | /* 87 - 2560x1080@25Hz 64:27 */ | ||||
1192 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (2560), .hsync_start = (3008), .hsync_end = (3052), .htotal = (3200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1193 | 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (2560), .hsync_start = (3008), .hsync_end = (3052), .htotal = (3200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1194 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (2560), .hsync_start = (3008), .hsync_end = (3052), .htotal = (3200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1195 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1196 | /* 88 - 2560x1080@30Hz 64:27 */ | ||||
1197 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (118800), .hdisplay = (2560), .hsync_start = (3328), .hsync_end = (3372), .htotal = (3520), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1198 | 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (118800), .hdisplay = (2560), .hsync_start = (3328), .hsync_end = (3372), .htotal = (3520), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1199 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (118800), .hdisplay = (2560), .hsync_start = (3328), .hsync_end = (3372), .htotal = (3520), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1200 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1201 | /* 89 - 2560x1080@50Hz 64:27 */ | ||||
1202 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (185625), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1203 | 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (185625), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1204 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (185625), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1205 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1206 | /* 90 - 2560x1080@60Hz 64:27 */ | ||||
1207 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (2808), .hsync_end = (2852), .htotal = (3000), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1208 | 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (2808), .hsync_end = (2852), .htotal = (3000), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1209 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (2808), .hsync_end = (2852), .htotal = (3000), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1210 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1211 | /* 91 - 2560x1080@100Hz 64:27 */ | ||||
1212 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (371250), .hdisplay = (2560), .hsync_start = (2778), .hsync_end = (2822), .htotal = (2970), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1213 | 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (371250), .hdisplay = (2560), .hsync_start = (2778), .hsync_end = (2822), .htotal = (2970), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1214 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (371250), .hdisplay = (2560), .hsync_start = (2778), .hsync_end = (2822), .htotal = (2970), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1215 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1216 | /* 92 - 2560x1080@120Hz 64:27 */ | ||||
1217 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (495000), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1218 | 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (495000), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1219 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (495000), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1220 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1221 | /* 93 - 3840x2160@24Hz 16:9 */ | ||||
1222 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1223 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1224 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1225 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1226 | /* 94 - 3840x2160@25Hz 16:9 */ | ||||
1227 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1228 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1229 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1230 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1231 | /* 95 - 3840x2160@30Hz 16:9 */ | ||||
1232 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1233 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1234 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1235 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1236 | /* 96 - 3840x2160@50Hz 16:9 */ | ||||
1237 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1238 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1239 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1240 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1241 | /* 97 - 3840x2160@60Hz 16:9 */ | ||||
1242 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1243 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1244 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1245 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1246 | /* 98 - 4096x2160@24Hz 256:135 */ | ||||
1247 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1248 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1249 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1250 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1251 | /* 99 - 4096x2160@25Hz 256:135 */ | ||||
1252 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1253 | 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1254 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1255 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1256 | /* 100 - 4096x2160@30Hz 256:135 */ | ||||
1257 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1258 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1259 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1260 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1261 | /* 101 - 4096x2160@50Hz 256:135 */ | ||||
1262 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1263 | 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1264 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1265 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1266 | /* 102 - 4096x2160@60Hz 256:135 */ | ||||
1267 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1268 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1269 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1270 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1271 | /* 103 - 3840x2160@24Hz 64:27 */ | ||||
1272 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1273 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1274 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1275 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1276 | /* 104 - 3840x2160@25Hz 64:27 */ | ||||
1277 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1278 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1279 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1280 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1281 | /* 105 - 3840x2160@30Hz 64:27 */ | ||||
1282 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1283 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1284 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1285 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1286 | /* 106 - 3840x2160@50Hz 64:27 */ | ||||
1287 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1288 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1289 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1290 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1291 | /* 107 - 3840x2160@60Hz 64:27 */ | ||||
1292 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1293 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1294 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1295 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1296 | /* 108 - 1280x720@48Hz 16:9 */ | ||||
1297 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1298 | 2280, 2500, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1299 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1300 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1301 | /* 109 - 1280x720@48Hz 64:27 */ | ||||
1302 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1303 | 2280, 2500, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1304 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1305 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1306 | /* 110 - 1680x720@48Hz 64:27 */ | ||||
1307 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (2490), .hsync_end = (2530), .htotal = (2750), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1308 | 2530, 2750, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (2490), .hsync_end = (2530), .htotal = (2750), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1309 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (2490), .hsync_end = (2530), .htotal = (2750), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1310 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1311 | /* 111 - 1920x1080@48Hz 16:9 */ | ||||
1312 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1313 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1314 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1315 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1316 | /* 112 - 1920x1080@48Hz 64:27 */ | ||||
1317 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1318 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1319 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1320 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1321 | /* 113 - 2560x1080@48Hz 64:27 */ | ||||
1322 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1323 | 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1324 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1325 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1326 | /* 114 - 3840x2160@48Hz 16:9 */ | ||||
1327 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1328 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1329 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1330 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1331 | /* 115 - 4096x2160@48Hz 256:135 */ | ||||
1332 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1333 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1334 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1335 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1336 | /* 116 - 3840x2160@48Hz 64:27 */ | ||||
1337 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1338 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1339 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1340 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1341 | /* 117 - 3840x2160@100Hz 16:9 */ | ||||
1342 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1343 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1344 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1345 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1346 | /* 118 - 3840x2160@120Hz 16:9 */ | ||||
1347 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1348 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1349 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1350 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1351 | /* 119 - 3840x2160@100Hz 64:27 */ | ||||
1352 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1353 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1354 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1355 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1356 | /* 120 - 3840x2160@120Hz 64:27 */ | ||||
1357 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1358 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1359 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1360 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1361 | /* 121 - 5120x2160@24Hz 64:27 */ | ||||
1362 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (7116), .hsync_end = (7204), .htotal = (7500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1363 | 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (7116), .hsync_end = (7204), .htotal = (7500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1364 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (7116), .hsync_end = (7204), .htotal = (7500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1365 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1366 | /* 122 - 5120x2160@25Hz 64:27 */ | ||||
1367 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (6816), .hsync_end = (6904), .htotal = (7200), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1368 | 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (6816), .hsync_end = (6904), .htotal = (7200), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1369 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (6816), .hsync_end = (6904), .htotal = (7200), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1370 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1371 | /* 123 - 5120x2160@30Hz 64:27 */ | ||||
1372 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (5784), .hsync_end = (5872), .htotal = (6000), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1373 | 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (5784), .hsync_end = (5872), .htotal = (6000), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1374 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (5784), .hsync_end = (5872), .htotal = (6000), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1375 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1376 | /* 124 - 5120x2160@48Hz 64:27 */ | ||||
1377 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5866), .hsync_end = (5954), .htotal = (6250), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2475 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1378 | 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5866), .hsync_end = (5954), .htotal = (6250), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2475 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1379 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5866), .hsync_end = (5954), .htotal = (6250), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2475 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1380 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1381 | /* 125 - 5120x2160@50Hz 64:27 */ | ||||
1382 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1383 | 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1384 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1385 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1386 | /* 126 - 5120x2160@60Hz 64:27 */ | ||||
1387 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1388 | 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1389 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1390 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1391 | /* 127 - 5120x2160@100Hz 64:27 */ | ||||
1392 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1393 | 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1394 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1395 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1396 | }; | ||||
1397 | |||||
1398 | /* | ||||
1399 | * From CEA/CTA-861 spec. | ||||
1400 | * | ||||
1401 | * Do not access directly, instead always use cea_mode_for_vic(). | ||||
1402 | */ | ||||
1403 | static const struct drm_display_mode edid_cea_modes_193[] = { | ||||
1404 | /* 193 - 5120x2160@120Hz 64:27 */ | ||||
1405 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1406 | 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1407 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1408 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1409 | /* 194 - 7680x4320@24Hz 16:9 */ | ||||
1410 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1411 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1412 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1413 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1414 | /* 195 - 7680x4320@25Hz 16:9 */ | ||||
1415 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1416 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1417 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1418 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1419 | /* 196 - 7680x4320@30Hz 16:9 */ | ||||
1420 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1421 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1422 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1423 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1424 | /* 197 - 7680x4320@48Hz 16:9 */ | ||||
1425 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1426 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1427 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1428 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1429 | /* 198 - 7680x4320@50Hz 16:9 */ | ||||
1430 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1431 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1432 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1433 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1434 | /* 199 - 7680x4320@60Hz 16:9 */ | ||||
1435 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1436 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1437 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1438 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1439 | /* 200 - 7680x4320@100Hz 16:9 */ | ||||
1440 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1441 | 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1442 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1443 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1444 | /* 201 - 7680x4320@120Hz 16:9 */ | ||||
1445 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1446 | 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1447 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1448 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1449 | /* 202 - 7680x4320@24Hz 64:27 */ | ||||
1450 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1451 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1452 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1453 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1454 | /* 203 - 7680x4320@25Hz 64:27 */ | ||||
1455 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1456 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1457 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1458 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1459 | /* 204 - 7680x4320@30Hz 64:27 */ | ||||
1460 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1461 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1462 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1463 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1464 | /* 205 - 7680x4320@48Hz 64:27 */ | ||||
1465 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1466 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1467 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1468 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1469 | /* 206 - 7680x4320@50Hz 64:27 */ | ||||
1470 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1471 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1472 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1473 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1474 | /* 207 - 7680x4320@60Hz 64:27 */ | ||||
1475 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1476 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1477 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1478 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1479 | /* 208 - 7680x4320@100Hz 64:27 */ | ||||
1480 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1481 | 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1482 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1483 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1484 | /* 209 - 7680x4320@120Hz 64:27 */ | ||||
1485 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1486 | 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1487 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1488 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1489 | /* 210 - 10240x4320@24Hz 64:27 */ | ||||
1490 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1491 | 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1492 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1493 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1494 | /* 211 - 10240x4320@25Hz 64:27 */ | ||||
1495 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1496 | 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1497 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1498 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1499 | /* 212 - 10240x4320@30Hz 64:27 */ | ||||
1500 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1501 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1502 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1503 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1504 | /* 213 - 10240x4320@48Hz 64:27 */ | ||||
1505 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1506 | 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1507 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1508 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1509 | /* 214 - 10240x4320@50Hz 64:27 */ | ||||
1510 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1511 | 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1512 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1513 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1514 | /* 215 - 10240x4320@60Hz 64:27 */ | ||||
1515 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1516 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1517 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1518 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1519 | /* 216 - 10240x4320@100Hz 64:27 */ | ||||
1520 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (12432), .hsync_end = (12608), .htotal = (13200), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1521 | 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (12432), .hsync_end = (12608), .htotal = (13200), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1522 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (12432), .hsync_end = (12608), .htotal = (13200), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1523 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1524 | /* 217 - 10240x4320@120Hz 64:27 */ | ||||
1525 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1526 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1527 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1528 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1529 | /* 218 - 4096x2160@100Hz 256:135 */ | ||||
1530 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1531 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1532 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1533 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1534 | /* 219 - 4096x2160@120Hz 256:135 */ | ||||
1535 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1536 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1537 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1538 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1539 | }; | ||||
1540 | |||||
1541 | /* | ||||
1542 | * HDMI 1.4 4k modes. Index using the VIC. | ||||
1543 | */ | ||||
1544 | static const struct drm_display_mode edid_4k_modes[] = { | ||||
1545 | /* 0 - dummy, VICs start at 1 */ | ||||
1546 | { }, | ||||
1547 | /* 1 - 3840x2160@30Hz */ | ||||
1548 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1549 | 3840, 4016, 4104, 4400, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1550 | 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1551 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1552 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1553 | /* 2 - 3840x2160@25Hz */ | ||||
1554 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1555 | 3840, 4896, 4984, 5280, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1556 | 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1557 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1558 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1559 | /* 3 - 3840x2160@24Hz */ | ||||
1560 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1561 | 3840, 5116, 5204, 5500, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1562 | 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1563 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1564 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1565 | /* 4 - 4096x2160@24Hz (SMPTE) */ | ||||
1566 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1567 | 4096, 5116, 5204, 5500, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1568 | 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1569 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1570 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1571 | }; | ||||
1572 | |||||
1573 | /*** DDC fetch and block validation ***/ | ||||
1574 | |||||
1575 | /* | ||||
1576 | * The opaque EDID type, internal to drm_edid.c. | ||||
1577 | */ | ||||
1578 | struct drm_edid { | ||||
1579 | /* Size allocated for edid */ | ||||
1580 | size_t size; | ||||
1581 | const struct edid *edid; | ||||
1582 | }; | ||||
1583 | |||||
1584 | static bool_Bool version_greater(const struct drm_edid *drm_edid, | ||||
1585 | u8 version, u8 revision) | ||||
1586 | { | ||||
1587 | const struct edid *edid = drm_edid->edid; | ||||
1588 | |||||
1589 | return edid->version > version || | ||||
1590 | (edid->version == version && edid->revision > revision); | ||||
1591 | } | ||||
1592 | |||||
1593 | static int edid_hfeeodb_extension_block_count(const struct edid *edid); | ||||
1594 | |||||
1595 | static int edid_hfeeodb_block_count(const struct edid *edid) | ||||
1596 | { | ||||
1597 | int eeodb = edid_hfeeodb_extension_block_count(edid); | ||||
1598 | |||||
1599 | return eeodb ? eeodb + 1 : 0; | ||||
1600 | } | ||||
1601 | |||||
1602 | static int edid_extension_block_count(const struct edid *edid) | ||||
1603 | { | ||||
1604 | return edid->extensions; | ||||
1605 | } | ||||
1606 | |||||
1607 | static int edid_block_count(const struct edid *edid) | ||||
1608 | { | ||||
1609 | return edid_extension_block_count(edid) + 1; | ||||
1610 | } | ||||
1611 | |||||
1612 | static int edid_size_by_blocks(int num_blocks) | ||||
1613 | { | ||||
1614 | return num_blocks * EDID_LENGTH128; | ||||
1615 | } | ||||
1616 | |||||
1617 | static int edid_size(const struct edid *edid) | ||||
1618 | { | ||||
1619 | return edid_size_by_blocks(edid_block_count(edid)); | ||||
1620 | } | ||||
1621 | |||||
1622 | static const void *edid_block_data(const struct edid *edid, int index) | ||||
1623 | { | ||||
1624 | BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH)extern char _ctassert[(!(sizeof(*edid) != 128)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
1625 | |||||
1626 | return edid + index; | ||||
1627 | } | ||||
1628 | |||||
1629 | static const void *edid_extension_block_data(const struct edid *edid, int index) | ||||
1630 | { | ||||
1631 | return edid_block_data(edid, index + 1); | ||||
1632 | } | ||||
1633 | |||||
1634 | static int drm_edid_block_count(const struct drm_edid *drm_edid) | ||||
1635 | { | ||||
1636 | int num_blocks; | ||||
1637 | |||||
1638 | /* Starting point */ | ||||
1639 | num_blocks = edid_block_count(drm_edid->edid); | ||||
1640 | |||||
1641 | /* HF-EEODB override */ | ||||
1642 | if (drm_edid->size >= edid_size_by_blocks(2)) { | ||||
1643 | int eeodb; | ||||
1644 | |||||
1645 | /* | ||||
1646 | * Note: HF-EEODB may specify a smaller extension count than the | ||||
1647 | * regular one. Unlike in buffer allocation, here we can use it. | ||||
1648 | */ | ||||
1649 | eeodb = edid_hfeeodb_block_count(drm_edid->edid); | ||||
1650 | if (eeodb) | ||||
1651 | num_blocks = eeodb; | ||||
1652 | } | ||||
1653 | |||||
1654 | /* Limit by allocated size */ | ||||
1655 | num_blocks = min(num_blocks, (int)drm_edid->size / EDID_LENGTH)(((num_blocks)<((int)drm_edid->size / 128))?(num_blocks ):((int)drm_edid->size / 128)); | ||||
1656 | |||||
1657 | return num_blocks; | ||||
1658 | } | ||||
1659 | |||||
1660 | static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) | ||||
1661 | { | ||||
1662 | return drm_edid_block_count(drm_edid) - 1; | ||||
1663 | } | ||||
1664 | |||||
1665 | static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) | ||||
1666 | { | ||||
1667 | return edid_block_data(drm_edid->edid, index); | ||||
1668 | } | ||||
1669 | |||||
1670 | static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, | ||||
1671 | int index) | ||||
1672 | { | ||||
1673 | return edid_extension_block_data(drm_edid->edid, index); | ||||
1674 | } | ||||
1675 | |||||
1676 | /* | ||||
1677 | * Initializer helper for legacy interfaces, where we have no choice but to | ||||
1678 | * trust edid size. Not for general purpose use. | ||||
1679 | */ | ||||
1680 | static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, | ||||
1681 | const struct edid *edid) | ||||
1682 | { | ||||
1683 | if (!edid) | ||||
1684 | return NULL((void *)0); | ||||
1685 | |||||
1686 | memset(drm_edid, 0, sizeof(*drm_edid))__builtin_memset((drm_edid), (0), (sizeof(*drm_edid))); | ||||
1687 | |||||
1688 | drm_edid->edid = edid; | ||||
1689 | drm_edid->size = edid_size(edid); | ||||
1690 | |||||
1691 | return drm_edid; | ||||
1692 | } | ||||
1693 | |||||
1694 | /* | ||||
1695 | * EDID base and extension block iterator. | ||||
1696 | * | ||||
1697 | * struct drm_edid_iter iter; | ||||
1698 | * const u8 *block; | ||||
1699 | * | ||||
1700 | * drm_edid_iter_begin(drm_edid, &iter); | ||||
1701 | * drm_edid_iter_for_each(block, &iter) { | ||||
1702 | * // do stuff with block | ||||
1703 | * } | ||||
1704 | * drm_edid_iter_end(&iter); | ||||
1705 | */ | ||||
1706 | struct drm_edid_iter { | ||||
1707 | const struct drm_edid *drm_edid; | ||||
1708 | |||||
1709 | /* Current block index. */ | ||||
1710 | int index; | ||||
1711 | }; | ||||
1712 | |||||
1713 | static void drm_edid_iter_begin(const struct drm_edid *drm_edid, | ||||
1714 | struct drm_edid_iter *iter) | ||||
1715 | { | ||||
1716 | memset(iter, 0, sizeof(*iter))__builtin_memset((iter), (0), (sizeof(*iter))); | ||||
1717 | |||||
1718 | iter->drm_edid = drm_edid; | ||||
1719 | } | ||||
1720 | |||||
1721 | static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) | ||||
1722 | { | ||||
1723 | const void *block = NULL((void *)0); | ||||
1724 | |||||
1725 | if (!iter->drm_edid) | ||||
1726 | return NULL((void *)0); | ||||
1727 | |||||
1728 | if (iter->index < drm_edid_block_count(iter->drm_edid)) | ||||
1729 | block = drm_edid_block_data(iter->drm_edid, iter->index++); | ||||
1730 | |||||
1731 | return block; | ||||
1732 | } | ||||
1733 | |||||
1734 | #define drm_edid_iter_for_each(__block, __iter)while (((__block) = __drm_edid_iter_next(__iter))) \ | ||||
1735 | while (((__block) = __drm_edid_iter_next(__iter))) | ||||
1736 | |||||
1737 | static void drm_edid_iter_end(struct drm_edid_iter *iter) | ||||
1738 | { | ||||
1739 | memset(iter, 0, sizeof(*iter))__builtin_memset((iter), (0), (sizeof(*iter))); | ||||
1740 | } | ||||
1741 | |||||
1742 | static const u8 edid_header[] = { | ||||
1743 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | ||||
1744 | }; | ||||
1745 | |||||
1746 | static void edid_header_fix(void *edid) | ||||
1747 | { | ||||
1748 | memcpy(edid, edid_header, sizeof(edid_header))__builtin_memcpy((edid), (edid_header), (sizeof(edid_header)) ); | ||||
1749 | } | ||||
1750 | |||||
1751 | /** | ||||
1752 | * drm_edid_header_is_valid - sanity check the header of the base EDID block | ||||
1753 | * @_edid: pointer to raw base EDID block | ||||
1754 | * | ||||
1755 | * Sanity check the header of the base EDID block. | ||||
1756 | * | ||||
1757 | * Return: 8 if the header is perfect, down to 0 if it's totally wrong. | ||||
1758 | */ | ||||
1759 | int drm_edid_header_is_valid(const void *_edid) | ||||
1760 | { | ||||
1761 | const struct edid *edid = _edid; | ||||
1762 | int i, score = 0; | ||||
1763 | |||||
1764 | for (i = 0; i < sizeof(edid_header); i++) { | ||||
1765 | if (edid->header[i] == edid_header[i]) | ||||
1766 | score++; | ||||
1767 | } | ||||
1768 | |||||
1769 | return score; | ||||
1770 | } | ||||
1771 | EXPORT_SYMBOL(drm_edid_header_is_valid); | ||||
1772 | |||||
1773 | static int edid_fixup __read_mostly = 6; | ||||
1774 | module_param_named(edid_fixup, edid_fixup, int, 0400); | ||||
1775 | MODULE_PARM_DESC(edid_fixup, | ||||
1776 | "Minimum number of valid EDID header bytes (0-8, default 6)"); | ||||
1777 | |||||
1778 | static int edid_block_compute_checksum(const void *_block) | ||||
1779 | { | ||||
1780 | const u8 *block = _block; | ||||
1781 | int i; | ||||
1782 | u8 csum = 0, crc = 0; | ||||
1783 | |||||
1784 | for (i = 0; i < EDID_LENGTH128 - 1; i++) | ||||
1785 | csum += block[i]; | ||||
1786 | |||||
1787 | crc = 0x100 - csum; | ||||
1788 | |||||
1789 | return crc; | ||||
1790 | } | ||||
1791 | |||||
1792 | static int edid_block_get_checksum(const void *_block) | ||||
1793 | { | ||||
1794 | const struct edid *block = _block; | ||||
1795 | |||||
1796 | return block->checksum; | ||||
1797 | } | ||||
1798 | |||||
1799 | static int edid_block_tag(const void *_block) | ||||
1800 | { | ||||
1801 | const u8 *block = _block; | ||||
1802 | |||||
1803 | return block[0]; | ||||
1804 | } | ||||
1805 | |||||
1806 | static bool_Bool edid_block_is_zero(const void *edid) | ||||
1807 | { | ||||
1808 | return !memchr_inv(edid, 0, EDID_LENGTH128); | ||||
1809 | } | ||||
1810 | |||||
1811 | /** | ||||
1812 | * drm_edid_are_equal - compare two edid blobs. | ||||
1813 | * @edid1: pointer to first blob | ||||
1814 | * @edid2: pointer to second blob | ||||
1815 | * This helper can be used during probing to determine if | ||||
1816 | * edid had changed. | ||||
1817 | */ | ||||
1818 | bool_Bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) | ||||
1819 | { | ||||
1820 | int edid1_len, edid2_len; | ||||
1821 | bool_Bool edid1_present = edid1 != NULL((void *)0); | ||||
1822 | bool_Bool edid2_present = edid2 != NULL((void *)0); | ||||
1823 | |||||
1824 | if (edid1_present != edid2_present) | ||||
1825 | return false0; | ||||
1826 | |||||
1827 | if (edid1) { | ||||
1828 | edid1_len = edid_size(edid1); | ||||
1829 | edid2_len = edid_size(edid2); | ||||
1830 | |||||
1831 | if (edid1_len != edid2_len) | ||||
1832 | return false0; | ||||
1833 | |||||
1834 | if (memcmp(edid1, edid2, edid1_len)__builtin_memcmp((edid1), (edid2), (edid1_len))) | ||||
1835 | return false0; | ||||
1836 | } | ||||
1837 | |||||
1838 | return true1; | ||||
1839 | } | ||||
1840 | EXPORT_SYMBOL(drm_edid_are_equal); | ||||
1841 | |||||
1842 | enum edid_block_status { | ||||
1843 | EDID_BLOCK_OK = 0, | ||||
1844 | EDID_BLOCK_READ_FAIL, | ||||
1845 | EDID_BLOCK_NULL, | ||||
1846 | EDID_BLOCK_ZERO, | ||||
1847 | EDID_BLOCK_HEADER_CORRUPT, | ||||
1848 | EDID_BLOCK_HEADER_REPAIR, | ||||
1849 | EDID_BLOCK_HEADER_FIXED, | ||||
1850 | EDID_BLOCK_CHECKSUM, | ||||
1851 | EDID_BLOCK_VERSION, | ||||
1852 | }; | ||||
1853 | |||||
1854 | static enum edid_block_status edid_block_check(const void *_block, | ||||
1855 | bool_Bool is_base_block) | ||||
1856 | { | ||||
1857 | const struct edid *block = _block; | ||||
1858 | |||||
1859 | if (!block) | ||||
1860 | return EDID_BLOCK_NULL; | ||||
1861 | |||||
1862 | if (is_base_block) { | ||||
1863 | int score = drm_edid_header_is_valid(block); | ||||
1864 | |||||
1865 | if (score < clamp(edid_fixup, 0, 8)({ __typeof(edid_fixup) __min_a = (({ __typeof(edid_fixup) __max_a = (edid_fixup); __typeof(edid_fixup) __max_b = (0); __max_a > __max_b ? __max_a : __max_b; })); __typeof(edid_fixup) __min_b = (8); __min_a < __min_b ? __min_a : __min_b; })) { | ||||
1866 | if (edid_block_is_zero(block)) | ||||
1867 | return EDID_BLOCK_ZERO; | ||||
1868 | else | ||||
1869 | return EDID_BLOCK_HEADER_CORRUPT; | ||||
1870 | } | ||||
1871 | |||||
1872 | if (score < 8) | ||||
1873 | return EDID_BLOCK_HEADER_REPAIR; | ||||
1874 | } | ||||
1875 | |||||
1876 | if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { | ||||
1877 | if (edid_block_is_zero(block)) | ||||
1878 | return EDID_BLOCK_ZERO; | ||||
1879 | else | ||||
1880 | return EDID_BLOCK_CHECKSUM; | ||||
1881 | } | ||||
1882 | |||||
1883 | if (is_base_block) { | ||||
1884 | if (block->version != 1) | ||||
1885 | return EDID_BLOCK_VERSION; | ||||
1886 | } | ||||
1887 | |||||
1888 | return EDID_BLOCK_OK; | ||||
1889 | } | ||||
1890 | |||||
1891 | static bool_Bool edid_block_status_valid(enum edid_block_status status, int tag) | ||||
1892 | { | ||||
1893 | return status == EDID_BLOCK_OK || | ||||
1894 | status == EDID_BLOCK_HEADER_FIXED || | ||||
1895 | (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT0x02); | ||||
1896 | } | ||||
1897 | |||||
1898 | static bool_Bool edid_block_valid(const void *block, bool_Bool base) | ||||
1899 | { | ||||
1900 | return edid_block_status_valid(edid_block_check(block, base), | ||||
1901 | edid_block_tag(block)); | ||||
1902 | } | ||||
1903 | |||||
1904 | static void edid_block_status_print(enum edid_block_status status, | ||||
1905 | const struct edid *block, | ||||
1906 | int block_num) | ||||
1907 | { | ||||
1908 | switch (status) { | ||||
1909 | case EDID_BLOCK_OK: | ||||
1910 | break; | ||||
1911 | case EDID_BLOCK_READ_FAIL: | ||||
1912 | pr_debug("EDID block %d read failed\n", block_num)do { } while(0); | ||||
1913 | break; | ||||
1914 | case EDID_BLOCK_NULL: | ||||
1915 | pr_debug("EDID block %d pointer is NULL\n", block_num)do { } while(0); | ||||
1916 | break; | ||||
1917 | case EDID_BLOCK_ZERO: | ||||
1918 | pr_notice("EDID block %d is all zeroes\n", block_num)printk("\0015" "EDID block %d is all zeroes\n", block_num); | ||||
1919 | break; | ||||
1920 | case EDID_BLOCK_HEADER_CORRUPT: | ||||
1921 | pr_notice("EDID has corrupt header\n")printk("\0015" "EDID has corrupt header\n"); | ||||
1922 | break; | ||||
1923 | case EDID_BLOCK_HEADER_REPAIR: | ||||
1924 | pr_debug("EDID corrupt header needs repair\n")do { } while(0); | ||||
1925 | break; | ||||
1926 | case EDID_BLOCK_HEADER_FIXED: | ||||
1927 | pr_debug("EDID corrupt header fixed\n")do { } while(0); | ||||
1928 | break; | ||||
1929 | case EDID_BLOCK_CHECKSUM: | ||||
1930 | if (edid_block_status_valid(status, edid_block_tag(block))) { | ||||
1931 | pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",do { } while(0) | ||||
1932 | block_num, edid_block_tag(block),do { } while(0) | ||||
1933 | edid_block_compute_checksum(block))do { } while(0); | ||||
1934 | } else { | ||||
1935 | pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",printk("\0015" "EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n" , block_num, edid_block_tag(block), edid_block_compute_checksum (block)) | ||||
1936 | block_num, edid_block_tag(block),printk("\0015" "EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n" , block_num, edid_block_tag(block), edid_block_compute_checksum (block)) | ||||
1937 | edid_block_compute_checksum(block))printk("\0015" "EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n" , block_num, edid_block_tag(block), edid_block_compute_checksum (block)); | ||||
1938 | } | ||||
1939 | break; | ||||
1940 | case EDID_BLOCK_VERSION: | ||||
1941 | pr_notice("EDID has major version %d, instead of 1\n",printk("\0015" "EDID has major version %d, instead of 1\n", block ->version) | ||||
1942 | block->version)printk("\0015" "EDID has major version %d, instead of 1\n", block ->version); | ||||
1943 | break; | ||||
1944 | default: | ||||
1945 | WARN(1, "EDID block %d unknown edid block status code %d\n",({ int __ret = !!(1); if (__ret) printf("EDID block %d unknown edid block status code %d\n" , block_num, status); __builtin_expect(!!(__ret), 0); }) | ||||
1946 | block_num, status)({ int __ret = !!(1); if (__ret) printf("EDID block %d unknown edid block status code %d\n" , block_num, status); __builtin_expect(!!(__ret), 0); }); | ||||
1947 | break; | ||||
1948 | } | ||||
1949 | } | ||||
1950 | |||||
1951 | static void edid_block_dump(const char *level, const void *block, int block_num) | ||||
1952 | { | ||||
1953 | enum edid_block_status status; | ||||
1954 | char prefix[20]; | ||||
1955 | |||||
1956 | status = edid_block_check(block, block_num == 0); | ||||
1957 | if (status == EDID_BLOCK_ZERO) | ||||
1958 | snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", block_num); | ||||
1959 | else if (!edid_block_status_valid(status, edid_block_tag(block))) | ||||
1960 | snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", block_num); | ||||
1961 | else | ||||
1962 | snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", block_num); | ||||
1963 | |||||
1964 | print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, | ||||
1965 | block, EDID_LENGTH128, false0); | ||||
1966 | } | ||||
1967 | |||||
1968 | /** | ||||
1969 | * drm_edid_block_valid - Sanity check the EDID block (base or extension) | ||||
1970 | * @_block: pointer to raw EDID block | ||||
1971 | * @block_num: type of block to validate (0 for base, extension otherwise) | ||||
1972 | * @print_bad_edid: if true, dump bad EDID blocks to the console | ||||
1973 | * @edid_corrupt: if true, the header or checksum is invalid | ||||
1974 | * | ||||
1975 | * Validate a base or extension EDID block and optionally dump bad blocks to | ||||
1976 | * the console. | ||||
1977 | * | ||||
1978 | * Return: True if the block is valid, false otherwise. | ||||
1979 | */ | ||||
1980 | bool_Bool drm_edid_block_valid(u8 *_block, int block_num, bool_Bool print_bad_edid, | ||||
1981 | bool_Bool *edid_corrupt) | ||||
1982 | { | ||||
1983 | struct edid *block = (struct edid *)_block; | ||||
1984 | enum edid_block_status status; | ||||
1985 | bool_Bool is_base_block = block_num == 0; | ||||
1986 | bool_Bool valid; | ||||
1987 | |||||
1988 | if (WARN_ON(!block)({ int __ret = !!(!block); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!block", "/usr/src/sys/dev/pci/drm/drm_edid.c", 1988); __builtin_expect (!!(__ret), 0); })) | ||||
1989 | return false0; | ||||
1990 | |||||
1991 | status = edid_block_check(block, is_base_block); | ||||
1992 | if (status == EDID_BLOCK_HEADER_REPAIR) { | ||||
1993 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n")___drm_dbg(((void *)0), DRM_UT_CORE, "Fixing EDID header, your hardware may be failing\n" ); | ||||
1994 | edid_header_fix(block); | ||||
1995 | |||||
1996 | /* Retry with fixed header, update status if that worked. */ | ||||
1997 | status = edid_block_check(block, is_base_block); | ||||
1998 | if (status == EDID_BLOCK_OK) | ||||
1999 | status = EDID_BLOCK_HEADER_FIXED; | ||||
2000 | } | ||||
2001 | |||||
2002 | if (edid_corrupt) { | ||||
2003 | /* | ||||
2004 | * Unknown major version isn't corrupt but we can't use it. Only | ||||
2005 | * the base block can reset edid_corrupt to false. | ||||
2006 | */ | ||||
2007 | if (is_base_block && | ||||
2008 | (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) | ||||
2009 | *edid_corrupt = false0; | ||||
2010 | else if (status != EDID_BLOCK_OK) | ||||
2011 | *edid_corrupt = true1; | ||||
2012 | } | ||||
2013 | |||||
2014 | edid_block_status_print(status, block, block_num); | ||||
2015 | |||||
2016 | /* Determine whether we can use this block with this status. */ | ||||
2017 | valid = edid_block_status_valid(status, edid_block_tag(block)); | ||||
2018 | |||||
2019 | if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { | ||||
2020 | pr_notice("Raw EDID:\n")printk("\0015" "Raw EDID:\n"); | ||||
2021 | edid_block_dump(KERN_NOTICE"\0015", block, block_num); | ||||
2022 | } | ||||
2023 | |||||
2024 | return valid; | ||||
2025 | } | ||||
2026 | EXPORT_SYMBOL(drm_edid_block_valid); | ||||
2027 | |||||
2028 | /** | ||||
2029 | * drm_edid_is_valid - sanity check EDID data | ||||
2030 | * @edid: EDID data | ||||
2031 | * | ||||
2032 | * Sanity-check an entire EDID record (including extensions) | ||||
2033 | * | ||||
2034 | * Return: True if the EDID data is valid, false otherwise. | ||||
2035 | */ | ||||
2036 | bool_Bool drm_edid_is_valid(struct edid *edid) | ||||
2037 | { | ||||
2038 | int i; | ||||
2039 | |||||
2040 | if (!edid) | ||||
2041 | return false0; | ||||
2042 | |||||
2043 | for (i = 0; i < edid_block_count(edid); i++) { | ||||
2044 | void *block = (void *)edid_block_data(edid, i); | ||||
2045 | |||||
2046 | if (!drm_edid_block_valid(block, i, true1, NULL((void *)0))) | ||||
2047 | return false0; | ||||
2048 | } | ||||
2049 | |||||
2050 | return true1; | ||||
2051 | } | ||||
2052 | EXPORT_SYMBOL(drm_edid_is_valid); | ||||
2053 | |||||
2054 | static struct edid *edid_filter_invalid_blocks(struct edid *edid, | ||||
2055 | size_t *alloc_size) | ||||
2056 | { | ||||
2057 | struct edid *new; | ||||
2058 | int i, valid_blocks = 0; | ||||
2059 | |||||
2060 | /* | ||||
2061 | * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert | ||||
2062 | * back to regular extension count here. We don't want to start | ||||
2063 | * modifying the HF-EEODB extension too. | ||||
2064 | */ | ||||
2065 | for (i = 0; i < edid_block_count(edid); i++) { | ||||
2066 | const void *src_block = edid_block_data(edid, i); | ||||
2067 | |||||
2068 | if (edid_block_valid(src_block, i == 0)) { | ||||
2069 | void *dst_block = (void *)edid_block_data(edid, valid_blocks); | ||||
2070 | |||||
2071 | memmove(dst_block, src_block, EDID_LENGTH)__builtin_memmove((dst_block), (src_block), (128)); | ||||
2072 | valid_blocks++; | ||||
2073 | } | ||||
2074 | } | ||||
2075 | |||||
2076 | /* We already trusted the base block to be valid here... */ | ||||
2077 | if (WARN_ON(!valid_blocks)({ int __ret = !!(!valid_blocks); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!valid_blocks", "/usr/src/sys/dev/pci/drm/drm_edid.c", 2077 ); __builtin_expect(!!(__ret), 0); })) { | ||||
2078 | kfree(edid); | ||||
2079 | return NULL((void *)0); | ||||
2080 | } | ||||
2081 | |||||
2082 | edid->extensions = valid_blocks - 1; | ||||
2083 | edid->checksum = edid_block_compute_checksum(edid); | ||||
2084 | |||||
2085 | *alloc_size = edid_size_by_blocks(valid_blocks); | ||||
2086 | |||||
2087 | #ifdef __linux__ | ||||
2088 | new = krealloc(edid, *alloc_size, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2089 | if (!new) | ||||
2090 | kfree(edid); | ||||
2091 | #else | ||||
2092 | new = kmalloc(*alloc_size, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2093 | if (!new) | ||||
2094 | kfree(edid); | ||||
2095 | memcpy(new, edid, EDID_LENGTH)__builtin_memcpy((new), (edid), (128)); | ||||
2096 | kfree(edid); | ||||
2097 | #endif | ||||
2098 | |||||
2099 | return new; | ||||
2100 | } | ||||
2101 | |||||
2102 | #define DDC_SEGMENT_ADDR0x30 0x30 | ||||
2103 | /** | ||||
2104 | * drm_do_probe_ddc_edid() - get EDID information via I2C | ||||
2105 | * @data: I2C device adapter | ||||
2106 | * @buf: EDID data buffer to be filled | ||||
2107 | * @block: 128 byte EDID block to start fetching from | ||||
2108 | * @len: EDID data buffer length to fetch | ||||
2109 | * | ||||
2110 | * Try to fetch EDID information by calling I2C driver functions. | ||||
2111 | * | ||||
2112 | * Return: 0 on success or -1 on failure. | ||||
2113 | */ | ||||
2114 | static int | ||||
2115 | drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) | ||||
2116 | { | ||||
2117 | struct i2c_adapter *adapter = data; | ||||
2118 | unsigned char start = block * EDID_LENGTH128; | ||||
2119 | unsigned char segment = block >> 1; | ||||
2120 | unsigned char xfers = segment ? 3 : 2; | ||||
2121 | int ret, retries = 5; | ||||
2122 | |||||
2123 | /* | ||||
2124 | * The core I2C driver will automatically retry the transfer if the | ||||
2125 | * adapter reports EAGAIN. However, we find that bit-banging transfers | ||||
2126 | * are susceptible to errors under a heavily loaded machine and | ||||
2127 | * generate spurious NAKs and timeouts. Retrying the transfer | ||||
2128 | * of the individual block a few times seems to overcome this. | ||||
2129 | */ | ||||
2130 | do { | ||||
2131 | struct i2c_msg msgs[] = { | ||||
2132 | { | ||||
2133 | .addr = DDC_SEGMENT_ADDR0x30, | ||||
2134 | .flags = 0, | ||||
2135 | .len = 1, | ||||
2136 | .buf = &segment, | ||||
2137 | }, { | ||||
2138 | .addr = DDC_ADDR0x50, | ||||
2139 | .flags = 0, | ||||
2140 | .len = 1, | ||||
2141 | .buf = &start, | ||||
2142 | }, { | ||||
2143 | .addr = DDC_ADDR0x50, | ||||
2144 | .flags = I2C_M_RD0x0001, | ||||
2145 | .len = len, | ||||
2146 | .buf = buf, | ||||
2147 | } | ||||
2148 | }; | ||||
2149 | |||||
2150 | /* | ||||
2151 | * Avoid sending the segment addr to not upset non-compliant | ||||
2152 | * DDC monitors. | ||||
2153 | */ | ||||
2154 | ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); | ||||
2155 | |||||
2156 | if (ret == -ENXIO6) { | ||||
2157 | DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",___drm_dbg(((void *)0), DRM_UT_KMS, "drm: skipping non-existent adapter %s\n" , adapter->name) | ||||
2158 | adapter->name)___drm_dbg(((void *)0), DRM_UT_KMS, "drm: skipping non-existent adapter %s\n" , adapter->name); | ||||
2159 | break; | ||||
2160 | } | ||||
2161 | } while (ret != xfers && --retries); | ||||
2162 | |||||
2163 | return ret == xfers ? 0 : -1; | ||||
2164 | } | ||||
2165 | |||||
2166 | static void connector_bad_edid(struct drm_connector *connector, | ||||
2167 | const struct edid *edid, int num_blocks) | ||||
2168 | { | ||||
2169 | int i; | ||||
2170 | u8 last_block; | ||||
2171 | |||||
2172 | /* | ||||
2173 | * 0x7e in the EDID is the number of extension blocks. The EDID | ||||
2174 | * is 1 (base block) + num_ext_blocks big. That means we can think | ||||
2175 | * of 0x7e in the EDID of the _index_ of the last block in the | ||||
2176 | * combined chunk of memory. | ||||
2177 | */ | ||||
2178 | last_block = edid->extensions; | ||||
2179 | |||||
2180 | /* Calculate real checksum for the last edid extension block data */ | ||||
2181 | if (last_block < num_blocks) | ||||
2182 | connector->real_edid_checksum = | ||||
2183 | edid_block_compute_checksum(edid + last_block); | ||||
2184 | |||||
2185 | if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)drm_debug_enabled_raw(DRM_UT_KMS)) | ||||
2186 | return; | ||||
2187 | |||||
2188 | drm_dbg_kms(connector->dev, "%s: EDID is invalid:\n", connector->name)__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "%s: EDID is invalid:\n" , connector->name); | ||||
2189 | for (i = 0; i < num_blocks; i++) | ||||
2190 | edid_block_dump(KERN_DEBUG"\0017", edid + i, i); | ||||
2191 | } | ||||
2192 | |||||
2193 | /* Get override or firmware EDID */ | ||||
2194 | static struct edid *drm_get_override_edid(struct drm_connector *connector, | ||||
2195 | size_t *alloc_size) | ||||
2196 | { | ||||
2197 | struct edid *override = NULL((void *)0); | ||||
2198 | |||||
2199 | if (connector->override_edid) | ||||
2200 | override = drm_edid_duplicate(connector->edid_blob_ptr->data); | ||||
2201 | |||||
2202 | if (!override
| ||||
2203 | override = drm_load_edid_firmware(connector); | ||||
2204 | |||||
2205 | /* FIXME: Get alloc size from deeper down the stack */ | ||||
2206 | if (!IS_ERR_OR_NULL(override) && alloc_size) | ||||
2207 | *alloc_size = edid_size(override); | ||||
2208 | |||||
2209 | return IS_ERR(override) ? NULL((void *)0) : override; | ||||
| |||||
2210 | } | ||||
2211 | |||||
2212 | /* For debugfs edid_override implementation */ | ||||
2213 | int drm_edid_override_set(struct drm_connector *connector, const void *edid, | ||||
2214 | size_t size) | ||||
2215 | { | ||||
2216 | int ret; | ||||
2217 | |||||
2218 | if (size < EDID_LENGTH128 || edid_size(edid) > size) | ||||
2219 | return -EINVAL22; | ||||
2220 | |||||
2221 | connector->override_edid = false0; | ||||
2222 | |||||
2223 | ret = drm_connector_update_edid_property(connector, edid); | ||||
2224 | if (!ret) | ||||
2225 | connector->override_edid = true1; | ||||
2226 | |||||
2227 | return ret; | ||||
2228 | } | ||||
2229 | |||||
2230 | /* For debugfs edid_override implementation */ | ||||
2231 | int drm_edid_override_reset(struct drm_connector *connector) | ||||
2232 | { | ||||
2233 | connector->override_edid = false0; | ||||
2234 | |||||
2235 | return drm_connector_update_edid_property(connector, NULL((void *)0)); | ||||
2236 | } | ||||
2237 | |||||
2238 | /** | ||||
2239 | * drm_add_override_edid_modes - add modes from override/firmware EDID | ||||
2240 | * @connector: connector we're probing | ||||
2241 | * | ||||
2242 | * Add modes from the override/firmware EDID, if available. Only to be used from | ||||
2243 | * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe | ||||
2244 | * failed during drm_get_edid() and caused the override/firmware EDID to be | ||||
2245 | * skipped. | ||||
2246 | * | ||||
2247 | * Return: The number of modes added or 0 if we couldn't find any. | ||||
2248 | */ | ||||
2249 | int drm_add_override_edid_modes(struct drm_connector *connector) | ||||
2250 | { | ||||
2251 | struct edid *override; | ||||
2252 | int num_modes = 0; | ||||
2253 | |||||
2254 | override = drm_get_override_edid(connector, NULL((void *)0)); | ||||
| |||||
2255 | if (override) { | ||||
2256 | drm_connector_update_edid_property(connector, override); | ||||
2257 | num_modes = drm_add_edid_modes(connector, override); | ||||
2258 | kfree(override); | ||||
2259 | |||||
2260 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",___drm_dbg(((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n" , connector->base.id, connector->name, num_modes) | ||||
2261 | connector->base.id, connector->name, num_modes)___drm_dbg(((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n" , connector->base.id, connector->name, num_modes); | ||||
2262 | } | ||||
2263 | |||||
2264 | return num_modes; | ||||
2265 | } | ||||
2266 | EXPORT_SYMBOL(drm_add_override_edid_modes); | ||||
2267 | |||||
2268 | typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); | ||||
2269 | |||||
2270 | static enum edid_block_status edid_block_read(void *block, unsigned int block_num, | ||||
2271 | read_block_fn read_block, | ||||
2272 | void *context) | ||||
2273 | { | ||||
2274 | enum edid_block_status status; | ||||
2275 | bool_Bool is_base_block = block_num == 0; | ||||
2276 | int try; | ||||
2277 | |||||
2278 | for (try = 0; try < 4; try++) { | ||||
2279 | if (read_block(context, block, block_num, EDID_LENGTH128)) | ||||
2280 | return EDID_BLOCK_READ_FAIL; | ||||
2281 | |||||
2282 | status = edid_block_check(block, is_base_block); | ||||
2283 | if (status == EDID_BLOCK_HEADER_REPAIR) { | ||||
2284 | edid_header_fix(block); | ||||
2285 | |||||
2286 | /* Retry with fixed header, update status if that worked. */ | ||||
2287 | status = edid_block_check(block, is_base_block); | ||||
2288 | if (status == EDID_BLOCK_OK) | ||||
2289 | status = EDID_BLOCK_HEADER_FIXED; | ||||
2290 | } | ||||
2291 | |||||
2292 | if (edid_block_status_valid(status, edid_block_tag(block))) | ||||
2293 | break; | ||||
2294 | |||||
2295 | /* Fail early for unrepairable base block all zeros. */ | ||||
2296 | if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) | ||||
2297 | break; | ||||
2298 | } | ||||
2299 | |||||
2300 | return status; | ||||
2301 | } | ||||
2302 | |||||
2303 | static struct edid *_drm_do_get_edid(struct drm_connector *connector, | ||||
2304 | read_block_fn read_block, void *context, | ||||
2305 | size_t *size) | ||||
2306 | { | ||||
2307 | enum edid_block_status status; | ||||
2308 | int i, num_blocks, invalid_blocks = 0; | ||||
2309 | struct edid *edid, *new; | ||||
2310 | size_t alloc_size = EDID_LENGTH128; | ||||
2311 | |||||
2312 | edid = drm_get_override_edid(connector, &alloc_size); | ||||
2313 | if (edid) | ||||
2314 | goto ok; | ||||
2315 | |||||
2316 | edid = kmalloc(alloc_size, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2317 | if (!edid) | ||||
2318 | return NULL((void *)0); | ||||
2319 | |||||
2320 | status = edid_block_read(edid, 0, read_block, context); | ||||
2321 | |||||
2322 | edid_block_status_print(status, edid, 0); | ||||
2323 | |||||
2324 | if (status == EDID_BLOCK_READ_FAIL) | ||||
2325 | goto fail; | ||||
2326 | |||||
2327 | /* FIXME: Clarify what a corrupt EDID actually means. */ | ||||
2328 | if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) | ||||
2329 | connector->edid_corrupt = false0; | ||||
2330 | else | ||||
2331 | connector->edid_corrupt = true1; | ||||
2332 | |||||
2333 | if (!edid_block_status_valid(status, edid_block_tag(edid))) { | ||||
2334 | if (status == EDID_BLOCK_ZERO) | ||||
2335 | connector->null_edid_counter++; | ||||
2336 | |||||
2337 | connector_bad_edid(connector, edid, 1); | ||||
2338 | goto fail; | ||||
2339 | } | ||||
2340 | |||||
2341 | if (!edid_extension_block_count(edid)) | ||||
2342 | goto ok; | ||||
2343 | |||||
2344 | alloc_size = edid_size(edid); | ||||
2345 | #ifdef __linux__ | ||||
2346 | new = krealloc(edid, alloc_size, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2347 | if (!new) | ||||
2348 | goto fail; | ||||
2349 | #else | ||||
2350 | new = kmalloc(alloc_size, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2351 | if (!new) | ||||
2352 | goto fail; | ||||
2353 | memcpy(new, edid, EDID_LENGTH)__builtin_memcpy((new), (edid), (128)); | ||||
2354 | kfree(edid); | ||||
2355 | #endif | ||||
2356 | edid = new; | ||||
2357 | |||||
2358 | num_blocks = edid_block_count(edid); | ||||
2359 | for (i = 1; i < num_blocks; i++) { | ||||
2360 | void *block = (void *)edid_block_data(edid, i); | ||||
2361 | |||||
2362 | status = edid_block_read(block, i, read_block, context); | ||||
2363 | |||||
2364 | edid_block_status_print(status, block, i); | ||||
2365 | |||||
2366 | if (!edid_block_status_valid(status, edid_block_tag(block))) { | ||||
2367 | if (status == EDID_BLOCK_READ_FAIL) | ||||
2368 | goto fail; | ||||
2369 | invalid_blocks++; | ||||
2370 | } else if (i == 1) { | ||||
2371 | /* | ||||
2372 | * If the first EDID extension is a CTA extension, and | ||||
2373 | * the first Data Block is HF-EEODB, override the | ||||
2374 | * extension block count. | ||||
2375 | * | ||||
2376 | * Note: HF-EEODB could specify a smaller extension | ||||
2377 | * count too, but we can't risk allocating a smaller | ||||
2378 | * amount. | ||||
2379 | */ | ||||
2380 | int eeodb = edid_hfeeodb_block_count(edid); | ||||
2381 | |||||
2382 | if (eeodb > num_blocks) { | ||||
2383 | num_blocks = eeodb; | ||||
2384 | alloc_size = edid_size_by_blocks(num_blocks); | ||||
2385 | #ifdef __linux__ | ||||
2386 | new = krealloc(edid, alloc_size, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2387 | if (!new) | ||||
2388 | goto fail; | ||||
2389 | #else | ||||
2390 | new = kmalloc(alloc_size, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2391 | if (!new) | ||||
2392 | goto fail; | ||||
2393 | memcpy(new, edid, EDID_LENGTH)__builtin_memcpy((new), (edid), (128)); | ||||
2394 | kfree(edid); | ||||
2395 | #endif | ||||
2396 | edid = new; | ||||
2397 | } | ||||
2398 | } | ||||
2399 | } | ||||
2400 | |||||
2401 | if (invalid_blocks) { | ||||
2402 | connector_bad_edid(connector, edid, num_blocks); | ||||
2403 | |||||
2404 | edid = edid_filter_invalid_blocks(edid, &alloc_size); | ||||
2405 | } | ||||
2406 | |||||
2407 | ok: | ||||
2408 | if (size) | ||||
2409 | *size = alloc_size; | ||||
2410 | |||||
2411 | return edid; | ||||
2412 | |||||
2413 | fail: | ||||
2414 | kfree(edid); | ||||
2415 | return NULL((void *)0); | ||||
2416 | } | ||||
2417 | |||||
2418 | /** | ||||
2419 | * drm_do_get_edid - get EDID data using a custom EDID block read function | ||||
2420 | * @connector: connector we're probing | ||||
2421 | * @read_block: EDID block read function | ||||
2422 | * @context: private data passed to the block read function | ||||
2423 | * | ||||
2424 | * When the I2C adapter connected to the DDC bus is hidden behind a device that | ||||
2425 | * exposes a different interface to read EDID blocks this function can be used | ||||
2426 | * to get EDID data using a custom block read function. | ||||
2427 | * | ||||
2428 | * As in the general case the DDC bus is accessible by the kernel at the I2C | ||||
2429 | * level, drivers must make all reasonable efforts to expose it as an I2C | ||||
2430 | * adapter and use drm_get_edid() instead of abusing this function. | ||||
2431 | * | ||||
2432 | * The EDID may be overridden using debugfs override_edid or firmware EDID | ||||
2433 | * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority | ||||
2434 | * order. Having either of them bypasses actual EDID reads. | ||||
2435 | * | ||||
2436 | * Return: Pointer to valid EDID or NULL if we couldn't find any. | ||||
2437 | */ | ||||
2438 | struct edid *drm_do_get_edid(struct drm_connector *connector, | ||||
2439 | read_block_fn read_block, | ||||
2440 | void *context) | ||||
2441 | { | ||||
2442 | return _drm_do_get_edid(connector, read_block, context, NULL((void *)0)); | ||||
2443 | } | ||||
2444 | EXPORT_SYMBOL_GPL(drm_do_get_edid); | ||||
2445 | |||||
2446 | /** | ||||
2447 | * drm_edid_raw - Get a pointer to the raw EDID data. | ||||
2448 | * @drm_edid: drm_edid container | ||||
2449 | * | ||||
2450 | * Get a pointer to the raw EDID data. | ||||
2451 | * | ||||
2452 | * This is for transition only. Avoid using this like the plague. | ||||
2453 | * | ||||
2454 | * Return: Pointer to raw EDID data. | ||||
2455 | */ | ||||
2456 | const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) | ||||
2457 | { | ||||
2458 | if (!drm_edid || !drm_edid->size) | ||||
2459 | return NULL((void *)0); | ||||
2460 | |||||
2461 | /* | ||||
2462 | * Do not return pointers where relying on EDID extension count would | ||||
2463 | * lead to buffer overflow. | ||||
2464 | */ | ||||
2465 | if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)({ int __ret = !!(edid_size(drm_edid->edid) > drm_edid-> size); if (__ret) printf("WARNING %s failed at %s:%d\n", "edid_size(drm_edid->edid) > drm_edid->size" , "/usr/src/sys/dev/pci/drm/drm_edid.c", 2465); __builtin_expect (!!(__ret), 0); })) | ||||
2466 | return NULL((void *)0); | ||||
2467 | |||||
2468 | return drm_edid->edid; | ||||
2469 | } | ||||
2470 | EXPORT_SYMBOL(drm_edid_raw); | ||||
2471 | |||||
2472 | /* Allocate struct drm_edid container *without* duplicating the edid data */ | ||||
2473 | static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) | ||||
2474 | { | ||||
2475 | struct drm_edid *drm_edid; | ||||
2476 | |||||
2477 | if (!edid || !size || size < EDID_LENGTH128) | ||||
2478 | return NULL((void *)0); | ||||
2479 | |||||
2480 | drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL(0x0001 | 0x0004)); | ||||
2481 | if (drm_edid) { | ||||
2482 | drm_edid->edid = edid; | ||||
2483 | drm_edid->size = size; | ||||
2484 | } | ||||
2485 | |||||
2486 | return drm_edid; | ||||
2487 | } | ||||
2488 | |||||
2489 | /** | ||||
2490 | * drm_edid_alloc - Allocate a new drm_edid container | ||||
2491 | * @edid: Pointer to raw EDID data | ||||
2492 | * @size: Size of memory allocated for EDID | ||||
2493 | * | ||||
2494 | * Allocate a new drm_edid container. Do not calculate edid size from edid, pass | ||||
2495 | * the actual size that has been allocated for the data. There is no validation | ||||
2496 | * of the raw EDID data against the size, but at least the EDID base block must | ||||
2497 | * fit in the buffer. | ||||
2498 | * | ||||
2499 | * The returned pointer must be freed using drm_edid_free(). | ||||
2500 | * | ||||
2501 | * Return: drm_edid container, or NULL on errors | ||||
2502 | */ | ||||
2503 | const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) | ||||
2504 | { | ||||
2505 | const struct drm_edid *drm_edid; | ||||
2506 | |||||
2507 | if (!edid || !size || size < EDID_LENGTH128) | ||||
2508 | return NULL((void *)0); | ||||
2509 | |||||
2510 | edid = kmemdup(edid, size, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2511 | if (!edid) | ||||
2512 | return NULL((void *)0); | ||||
2513 | |||||
2514 | drm_edid = _drm_edid_alloc(edid, size); | ||||
2515 | if (!drm_edid) | ||||
2516 | kfree(edid); | ||||
2517 | |||||
2518 | return drm_edid; | ||||
2519 | } | ||||
2520 | EXPORT_SYMBOL(drm_edid_alloc); | ||||
2521 | |||||
2522 | /** | ||||
2523 | * drm_edid_dup - Duplicate a drm_edid container | ||||
2524 | * @drm_edid: EDID to duplicate | ||||
2525 | * | ||||
2526 | * The returned pointer must be freed using drm_edid_free(). | ||||
2527 | * | ||||
2528 | * Returns: drm_edid container copy, or NULL on errors | ||||
2529 | */ | ||||
2530 | const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) | ||||
2531 | { | ||||
2532 | if (!drm_edid) | ||||
2533 | return NULL((void *)0); | ||||
2534 | |||||
2535 | return drm_edid_alloc(drm_edid->edid, drm_edid->size); | ||||
2536 | } | ||||
2537 | EXPORT_SYMBOL(drm_edid_dup); | ||||
2538 | |||||
2539 | /** | ||||
2540 | * drm_edid_free - Free the drm_edid container | ||||
2541 | * @drm_edid: EDID to free | ||||
2542 | */ | ||||
2543 | void drm_edid_free(const struct drm_edid *drm_edid) | ||||
2544 | { | ||||
2545 | if (!drm_edid) | ||||
2546 | return; | ||||
2547 | |||||
2548 | kfree(drm_edid->edid); | ||||
2549 | kfree(drm_edid); | ||||
2550 | } | ||||
2551 | EXPORT_SYMBOL(drm_edid_free); | ||||
2552 | |||||
2553 | /** | ||||
2554 | * drm_probe_ddc() - probe DDC presence | ||||
2555 | * @adapter: I2C adapter to probe | ||||
2556 | * | ||||
2557 | * Return: True on success, false on failure. | ||||
2558 | */ | ||||
2559 | bool_Bool | ||||
2560 | drm_probe_ddc(struct i2c_adapter *adapter) | ||||
2561 | { | ||||
2562 | unsigned char out; | ||||
2563 | |||||
2564 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | ||||
2565 | } | ||||
2566 | EXPORT_SYMBOL(drm_probe_ddc); | ||||
2567 | |||||
2568 | /** | ||||
2569 | * drm_get_edid - get EDID data, if available | ||||
2570 | * @connector: connector we're probing | ||||
2571 | * @adapter: I2C adapter to use for DDC | ||||
2572 | * | ||||
2573 | * Poke the given I2C channel to grab EDID data if possible. If found, | ||||
2574 | * attach it to the connector. | ||||
2575 | * | ||||
2576 | * Return: Pointer to valid EDID or NULL if we couldn't find any. | ||||
2577 | */ | ||||
2578 | struct edid *drm_get_edid(struct drm_connector *connector, | ||||
2579 | struct i2c_adapter *adapter) | ||||
2580 | { | ||||
2581 | struct edid *edid; | ||||
2582 | |||||
2583 | if (connector->force == DRM_FORCE_OFF) | ||||
2584 | return NULL((void *)0); | ||||
2585 | |||||
2586 | if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) | ||||
2587 | return NULL((void *)0); | ||||
2588 | |||||
2589 | edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL((void *)0)); | ||||
2590 | drm_connector_update_edid_property(connector, edid); | ||||
2591 | return edid; | ||||
2592 | } | ||||
2593 | EXPORT_SYMBOL(drm_get_edid); | ||||
2594 | |||||
2595 | /** | ||||
2596 | * drm_edid_read_custom - Read EDID data using given EDID block read function | ||||
2597 | * @connector: Connector to use | ||||
2598 | * @read_block: EDID block read function | ||||
2599 | * @context: Private data passed to the block read function | ||||
2600 | * | ||||
2601 | * When the I2C adapter connected to the DDC bus is hidden behind a device that | ||||
2602 | * exposes a different interface to read EDID blocks this function can be used | ||||
2603 | * to get EDID data using a custom block read function. | ||||
2604 | * | ||||
2605 | * As in the general case the DDC bus is accessible by the kernel at the I2C | ||||
2606 | * level, drivers must make all reasonable efforts to expose it as an I2C | ||||
2607 | * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing | ||||
2608 | * this function. | ||||
2609 | * | ||||
2610 | * The EDID may be overridden using debugfs override_edid or firmware EDID | ||||
2611 | * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority | ||||
2612 | * order. Having either of them bypasses actual EDID reads. | ||||
2613 | * | ||||
2614 | * The returned pointer must be freed using drm_edid_free(). | ||||
2615 | * | ||||
2616 | * Return: Pointer to EDID, or NULL if probe/read failed. | ||||
2617 | */ | ||||
2618 | const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, | ||||
2619 | read_block_fn read_block, | ||||
2620 | void *context) | ||||
2621 | { | ||||
2622 | const struct drm_edid *drm_edid; | ||||
2623 | struct edid *edid; | ||||
2624 | size_t size = 0; | ||||
2625 | |||||
2626 | edid = _drm_do_get_edid(connector, read_block, context, &size); | ||||
2627 | if (!edid) | ||||
2628 | return NULL((void *)0); | ||||
2629 | |||||
2630 | /* Sanity check for now */ | ||||
2631 | drm_WARN_ON(connector->dev, !size)({ int __ret = !!((!size)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((connector->dev))->dev), "", "drm_WARN_ON(" "!size" ")"); __builtin_expect(!!(__ret), 0); }); | ||||
2632 | |||||
2633 | drm_edid = _drm_edid_alloc(edid, size); | ||||
2634 | if (!drm_edid) | ||||
2635 | kfree(edid); | ||||
2636 | |||||
2637 | return drm_edid; | ||||
2638 | } | ||||
2639 | EXPORT_SYMBOL(drm_edid_read_custom); | ||||
2640 | |||||
2641 | /** | ||||
2642 | * drm_edid_read_ddc - Read EDID data using given I2C adapter | ||||
2643 | * @connector: Connector to use | ||||
2644 | * @adapter: I2C adapter to use for DDC | ||||
2645 | * | ||||
2646 | * Read EDID using the given I2C adapter. | ||||
2647 | * | ||||
2648 | * The EDID may be overridden using debugfs override_edid or firmware EDID | ||||
2649 | * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority | ||||
2650 | * order. Having either of them bypasses actual EDID reads. | ||||
2651 | * | ||||
2652 | * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and | ||||
2653 | * using drm_edid_read() instead of this function. | ||||
2654 | * | ||||
2655 | * The returned pointer must be freed using drm_edid_free(). | ||||
2656 | * | ||||
2657 | * Return: Pointer to EDID, or NULL if probe/read failed. | ||||
2658 | */ | ||||
2659 | const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, | ||||
2660 | struct i2c_adapter *adapter) | ||||
2661 | { | ||||
2662 | const struct drm_edid *drm_edid; | ||||
2663 | |||||
2664 | if (connector->force == DRM_FORCE_OFF) | ||||
2665 | return NULL((void *)0); | ||||
2666 | |||||
2667 | if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) | ||||
2668 | return NULL((void *)0); | ||||
2669 | |||||
2670 | drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); | ||||
2671 | |||||
2672 | /* Note: Do *not* call connector updates here. */ | ||||
2673 | |||||
2674 | return drm_edid; | ||||
2675 | } | ||||
2676 | EXPORT_SYMBOL(drm_edid_read_ddc); | ||||
2677 | |||||
2678 | /** | ||||
2679 | * drm_edid_read - Read EDID data using connector's I2C adapter | ||||
2680 | * @connector: Connector to use | ||||
2681 | * | ||||
2682 | * Read EDID using the connector's I2C adapter. | ||||
2683 | * | ||||
2684 | * The EDID may be overridden using debugfs override_edid or firmware EDID | ||||
2685 | * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority | ||||
2686 | * order. Having either of them bypasses actual EDID reads. | ||||
2687 | * | ||||
2688 | * The returned pointer must be freed using drm_edid_free(). | ||||
2689 | * | ||||
2690 | * Return: Pointer to EDID, or NULL if probe/read failed. | ||||
2691 | */ | ||||
2692 | const struct drm_edid *drm_edid_read(struct drm_connector *connector) | ||||
2693 | { | ||||
2694 | if (drm_WARN_ON(connector->dev, !connector->ddc)({ int __ret = !!((!connector->ddc)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((connector->dev))->dev), "", "drm_WARN_ON(" "!connector->ddc" ")"); __builtin_expect(!!(__ret), 0); } )) | ||||
2695 | return NULL((void *)0); | ||||
2696 | |||||
2697 | return drm_edid_read_ddc(connector, connector->ddc); | ||||
2698 | } | ||||
2699 | EXPORT_SYMBOL(drm_edid_read); | ||||
2700 | |||||
2701 | static u32 edid_extract_panel_id(const struct edid *edid) | ||||
2702 | { | ||||
2703 | /* | ||||
2704 | * We represent the ID as a 32-bit number so it can easily be compared | ||||
2705 | * with "==". | ||||
2706 | * | ||||
2707 | * NOTE that we deal with endianness differently for the top half | ||||
2708 | * of this ID than for the bottom half. The bottom half (the product | ||||
2709 | * id) gets decoded as little endian by the EDID_PRODUCT_ID because | ||||
2710 | * that's how everyone seems to interpret it. The top half (the mfg_id) | ||||
2711 | * gets stored as big endian because that makes | ||||
2712 | * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier | ||||
2713 | * to write (it's easier to extract the ASCII). It doesn't really | ||||
2714 | * matter, though, as long as the number here is unique. | ||||
2715 | */ | ||||
2716 | return (u32)edid->mfg_id[0] << 24 | | ||||
2717 | (u32)edid->mfg_id[1] << 16 | | ||||
2718 | (u32)EDID_PRODUCT_ID(edid)((edid)->prod_code[0] | ((edid)->prod_code[1] << 8 )); | ||||
2719 | } | ||||
2720 | |||||
2721 | /** | ||||
2722 | * drm_edid_get_panel_id - Get a panel's ID through DDC | ||||
2723 | * @adapter: I2C adapter to use for DDC | ||||
2724 | * | ||||
2725 | * This function reads the first block of the EDID of a panel and (assuming | ||||
2726 | * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value | ||||
2727 | * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's | ||||
2728 | * supposed to be different for each different modem of panel. | ||||
2729 | * | ||||
2730 | * This function is intended to be used during early probing on devices where | ||||
2731 | * more than one panel might be present. Because of its intended use it must | ||||
2732 | * assume that the EDID of the panel is correct, at least as far as the ID | ||||
2733 | * is concerned (in other words, we don't process any overrides here). | ||||
2734 | * | ||||
2735 | * NOTE: it's expected that this function and drm_do_get_edid() will both | ||||
2736 | * be read the EDID, but there is no caching between them. Since we're only | ||||
2737 | * reading the first block, hopefully this extra overhead won't be too big. | ||||
2738 | * | ||||
2739 | * Return: A 32-bit ID that should be different for each make/model of panel. | ||||
2740 | * See the functions drm_edid_encode_panel_id() and | ||||
2741 | * drm_edid_decode_panel_id() for some details on the structure of this | ||||
2742 | * ID. | ||||
2743 | */ | ||||
2744 | |||||
2745 | u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) | ||||
2746 | { | ||||
2747 | enum edid_block_status status; | ||||
2748 | void *base_block; | ||||
2749 | u32 panel_id = 0; | ||||
2750 | |||||
2751 | /* | ||||
2752 | * There are no manufacturer IDs of 0, so if there is a problem reading | ||||
2753 | * the EDID then we'll just return 0. | ||||
2754 | */ | ||||
2755 | |||||
2756 | base_block = kmalloc(EDID_LENGTH128, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2757 | if (!base_block) | ||||
2758 | return 0; | ||||
2759 | |||||
2760 | status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); | ||||
2761 | |||||
2762 | edid_block_status_print(status, base_block, 0); | ||||
2763 | |||||
2764 | if (edid_block_status_valid(status, edid_block_tag(base_block))) | ||||
2765 | panel_id = edid_extract_panel_id(base_block); | ||||
2766 | |||||
2767 | kfree(base_block); | ||||
2768 | |||||
2769 | return panel_id; | ||||
2770 | } | ||||
2771 | EXPORT_SYMBOL(drm_edid_get_panel_id); | ||||
2772 | |||||
2773 | /** | ||||
2774 | * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output | ||||
2775 | * @connector: connector we're probing | ||||
2776 | * @adapter: I2C adapter to use for DDC | ||||
2777 | * | ||||
2778 | * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of | ||||
2779 | * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily | ||||
2780 | * switch DDC to the GPU which is retrieving EDID. | ||||
2781 | * | ||||
2782 | * Return: Pointer to valid EDID or %NULL if we couldn't find any. | ||||
2783 | */ | ||||
2784 | struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, | ||||
2785 | struct i2c_adapter *adapter) | ||||
2786 | { | ||||
2787 | STUB()do { printf("%s: stub\n", __func__); } while(0); | ||||
2788 | return NULL((void *)0); | ||||
2789 | #ifdef notyet | ||||
2790 | struct drm_device *dev = connector->dev; | ||||
2791 | struct pci_dev *pdev = to_pci_dev(dev->dev); | ||||
2792 | struct edid *edid; | ||||
2793 | |||||
2794 | if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))({ static int __warned; int __ret = !!((!dev_is_pci(dev->dev ))); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON_ONCE(" "!dev_is_pci(dev->dev)" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) | ||||
2795 | return NULL((void *)0); | ||||
2796 | |||||
2797 | vga_switcheroo_lock_ddc(pdev); | ||||
2798 | edid = drm_get_edid(connector, adapter); | ||||
2799 | vga_switcheroo_unlock_ddc(pdev); | ||||
2800 | |||||
2801 | return edid; | ||||
2802 | #endif | ||||
2803 | } | ||||
2804 | EXPORT_SYMBOL(drm_get_edid_switcheroo); | ||||
2805 | |||||
2806 | /** | ||||
2807 | * drm_edid_duplicate - duplicate an EDID and the extensions | ||||
2808 | * @edid: EDID to duplicate | ||||
2809 | * | ||||
2810 | * Return: Pointer to duplicated EDID or NULL on allocation failure. | ||||
2811 | */ | ||||
2812 | struct edid *drm_edid_duplicate(const struct edid *edid) | ||||
2813 | { | ||||
2814 | return kmemdup(edid, edid_size(edid), GFP_KERNEL(0x0001 | 0x0004)); | ||||
2815 | } | ||||
2816 | EXPORT_SYMBOL(drm_edid_duplicate); | ||||
2817 | |||||
2818 | /*** EDID parsing ***/ | ||||
2819 | |||||
2820 | /** | ||||
2821 | * edid_get_quirks - return quirk flags for a given EDID | ||||
2822 | * @drm_edid: EDID to process | ||||
2823 | * | ||||
2824 | * This tells subsequent routines what fixes they need to apply. | ||||
2825 | */ | ||||
2826 | static u32 edid_get_quirks(const struct drm_edid *drm_edid) | ||||
2827 | { | ||||
2828 | u32 panel_id = edid_extract_panel_id(drm_edid->edid); | ||||
2829 | const struct edid_quirk *quirk; | ||||
2830 | int i; | ||||
2831 | |||||
2832 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list)(sizeof((edid_quirk_list)) / sizeof((edid_quirk_list)[0])); i++) { | ||||
2833 | quirk = &edid_quirk_list[i]; | ||||
2834 | if (quirk->panel_id == panel_id) | ||||
2835 | return quirk->quirks; | ||||
2836 | } | ||||
2837 | |||||
2838 | return 0; | ||||
2839 | } | ||||
2840 | |||||
2841 | #define MODE_SIZE(m)((m)->hdisplay * (m)->vdisplay) ((m)->hdisplay * (m)->vdisplay) | ||||
2842 | #define MODE_REFRESH_DIFF(c,t)(abs((c) - (t))) (abs((c) - (t))) | ||||
2843 | |||||
2844 | /* | ||||
2845 | * Walk the mode list for connector, clearing the preferred status on existing | ||||
2846 | * modes and setting it anew for the right mode ala quirks. | ||||
2847 | */ | ||||
2848 | static void edid_fixup_preferred(struct drm_connector *connector, | ||||
2849 | u32 quirks) | ||||
2850 | { | ||||
2851 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | ||||
2852 | int target_refresh = 0; | ||||
2853 | int cur_vrefresh, preferred_vrefresh; | ||||
2854 | |||||
2855 | if (list_empty(&connector->probed_modes)) | ||||
2856 | return; | ||||
2857 | |||||
2858 | if (quirks & EDID_QUIRK_PREFER_LARGE_60(1 << 0)) | ||||
2859 | target_refresh = 60; | ||||
2860 | if (quirks & EDID_QUIRK_PREFER_LARGE_75(1 << 2)) | ||||
2861 | target_refresh = 75; | ||||
2862 | |||||
2863 | preferred_mode = list_first_entry(&connector->probed_modes,({ const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&connector->probed_modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );}) | ||||
2864 | struct drm_display_mode, head)({ const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&connector->probed_modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );}); | ||||
2865 | |||||
2866 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head)for (cur_mode = ({ const __typeof( ((__typeof(*cur_mode) *)0) ->head ) *__mptr = ((&connector->probed_modes)-> next); (__typeof(*cur_mode) *)( (char *)__mptr - __builtin_offsetof (__typeof(*cur_mode), head) );}), t = ({ const __typeof( ((__typeof (*cur_mode) *)0)->head ) *__mptr = (cur_mode->head.next ); (__typeof(*cur_mode) *)( (char *)__mptr - __builtin_offsetof (__typeof(*cur_mode), head) );}); &cur_mode->head != ( &connector->probed_modes); cur_mode = t, t = ({ const __typeof ( ((__typeof(*t) *)0)->head ) *__mptr = (t->head.next); (__typeof(*t) *)( (char *)__mptr - __builtin_offsetof(__typeof (*t), head) );})) { | ||||
2867 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
2868 | |||||
2869 | if (cur_mode == preferred_mode) | ||||
2870 | continue; | ||||
2871 | |||||
2872 | /* Largest mode is preferred */ | ||||
2873 | if (MODE_SIZE(cur_mode)((cur_mode)->hdisplay * (cur_mode)->vdisplay) > MODE_SIZE(preferred_mode)((preferred_mode)->hdisplay * (preferred_mode)->vdisplay )) | ||||
2874 | preferred_mode = cur_mode; | ||||
2875 | |||||
2876 | cur_vrefresh = drm_mode_vrefresh(cur_mode); | ||||
2877 | preferred_vrefresh = drm_mode_vrefresh(preferred_mode); | ||||
2878 | /* At a given size, try to get closest to target refresh */ | ||||
2879 | if ((MODE_SIZE(cur_mode)((cur_mode)->hdisplay * (cur_mode)->vdisplay) == MODE_SIZE(preferred_mode)((preferred_mode)->hdisplay * (preferred_mode)->vdisplay )) && | ||||
2880 | MODE_REFRESH_DIFF(cur_vrefresh, target_refresh)(abs((cur_vrefresh) - (target_refresh))) < | ||||
2881 | MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)(abs((preferred_vrefresh) - (target_refresh)))) { | ||||
2882 | preferred_mode = cur_mode; | ||||
2883 | } | ||||
2884 | } | ||||
2885 | |||||
2886 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
2887 | } | ||||
2888 | |||||
2889 | static bool_Bool | ||||
2890 | mode_is_rb(const struct drm_display_mode *mode) | ||||
2891 | { | ||||
2892 | return (mode->htotal - mode->hdisplay == 160) && | ||||
2893 | (mode->hsync_end - mode->hdisplay == 80) && | ||||
2894 | (mode->hsync_end - mode->hsync_start == 32) && | ||||
2895 | (mode->vsync_start - mode->vdisplay == 3); | ||||
2896 | } | ||||
2897 | |||||
2898 | /* | ||||
2899 | * drm_mode_find_dmt - Create a copy of a mode if present in DMT | ||||
2900 | * @dev: Device to duplicate against | ||||
2901 | * @hsize: Mode width | ||||
2902 | * @vsize: Mode height | ||||
2903 | * @fresh: Mode refresh rate | ||||
2904 | * @rb: Mode reduced-blanking-ness | ||||
2905 | * | ||||
2906 | * Walk the DMT mode list looking for a match for the given parameters. | ||||
2907 | * | ||||
2908 | * Return: A newly allocated copy of the mode, or NULL if not found. | ||||
2909 | */ | ||||
2910 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, | ||||
2911 | int hsize, int vsize, int fresh, | ||||
2912 | bool_Bool rb) | ||||
2913 | { | ||||
2914 | int i; | ||||
2915 | |||||
2916 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes)(sizeof((drm_dmt_modes)) / sizeof((drm_dmt_modes)[0])); i++) { | ||||
2917 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; | ||||
2918 | |||||
2919 | if (hsize != ptr->hdisplay) | ||||
2920 | continue; | ||||
2921 | if (vsize != ptr->vdisplay) | ||||
2922 | continue; | ||||
2923 | if (fresh != drm_mode_vrefresh(ptr)) | ||||
2924 | continue; | ||||
2925 | if (rb != mode_is_rb(ptr)) | ||||
2926 | continue; | ||||
2927 | |||||
2928 | return drm_mode_duplicate(dev, ptr); | ||||
2929 | } | ||||
2930 | |||||
2931 | return NULL((void *)0); | ||||
2932 | } | ||||
2933 | EXPORT_SYMBOL(drm_mode_find_dmt); | ||||
2934 | |||||
2935 | static bool_Bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) | ||||
2936 | { | ||||
2937 | BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), pixel_clock) != 0)) ? 1 : -1 ] __attribute__((__unused__)); | ||||
2938 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.pad1) != 2)) ? 1 : -1 ] __attribute__((__unused__ )); | ||||
2939 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.type) != 3)) ? 1 : -1 ] __attribute__((__unused__ )); | ||||
2940 | |||||
2941 | return descriptor->pixel_clock == 0 && | ||||
2942 | descriptor->data.other_data.pad1 == 0 && | ||||
2943 | descriptor->data.other_data.type == type; | ||||
2944 | } | ||||
2945 | |||||
2946 | static bool_Bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) | ||||
2947 | { | ||||
2948 | BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), pixel_clock) != 0)) ? 1 : -1 ] __attribute__((__unused__)); | ||||
2949 | |||||
2950 | return descriptor->pixel_clock != 0; | ||||
2951 | } | ||||
2952 | |||||
2953 | typedef void detailed_cb(const struct detailed_timing *timing, void *closure); | ||||
2954 | |||||
2955 | static void | ||||
2956 | cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) | ||||
2957 | { | ||||
2958 | int i, n; | ||||
2959 | u8 d = ext[0x02]; | ||||
2960 | const u8 *det_base = ext + d; | ||||
2961 | |||||
2962 | if (d < 4 || d > 127) | ||||
2963 | return; | ||||
2964 | |||||
2965 | n = (127 - d) / 18; | ||||
2966 | for (i = 0; i < n; i++) | ||||
2967 | cb((const struct detailed_timing *)(det_base + 18 * i), closure); | ||||
2968 | } | ||||
2969 | |||||
2970 | static void | ||||
2971 | vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) | ||||
2972 | { | ||||
2973 | unsigned int i, n = min((int)ext[0x02], 6)((((int)ext[0x02])<(6))?((int)ext[0x02]):(6)); | ||||
2974 | const u8 *det_base = ext + 5; | ||||
2975 | |||||
2976 | if (ext[0x01] != 1) | ||||
2977 | return; /* unknown version */ | ||||
2978 | |||||
2979 | for (i = 0; i < n; i++) | ||||
2980 | cb((const struct detailed_timing *)(det_base + 18 * i), closure); | ||||
2981 | } | ||||
2982 | |||||
2983 | static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, | ||||
2984 | detailed_cb *cb, void *closure) | ||||
2985 | { | ||||
2986 | struct drm_edid_iter edid_iter; | ||||
2987 | const u8 *ext; | ||||
2988 | int i; | ||||
2989 | |||||
2990 | if (!drm_edid) | ||||
2991 | return; | ||||
2992 | |||||
2993 | for (i = 0; i < EDID_DETAILED_TIMINGS4; i++) | ||||
2994 | cb(&drm_edid->edid->detailed_timings[i], closure); | ||||
2995 | |||||
2996 | drm_edid_iter_begin(drm_edid, &edid_iter); | ||||
2997 | drm_edid_iter_for_each(ext, &edid_iter)while (((ext) = __drm_edid_iter_next(&edid_iter))) { | ||||
2998 | switch (*ext) { | ||||
2999 | case CEA_EXT0x02: | ||||
3000 | cea_for_each_detailed_block(ext, cb, closure); | ||||
3001 | break; | ||||
3002 | case VTB_EXT0x10: | ||||
3003 | vtb_for_each_detailed_block(ext, cb, closure); | ||||
3004 | break; | ||||
3005 | default: | ||||
3006 | break; | ||||
3007 | } | ||||
3008 | } | ||||
3009 | drm_edid_iter_end(&edid_iter); | ||||
3010 | } | ||||
3011 | |||||
3012 | static void | ||||
3013 | is_rb(const struct detailed_timing *descriptor, void *data) | ||||
3014 | { | ||||
3015 | bool_Bool *res = data; | ||||
3016 | |||||
3017 | if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE0xfd)) | ||||
3018 | return; | ||||
3019 | |||||
3020 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.data.range.flags) != 10)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
3021 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.data.range.formula.cvt.flags) != 15)) ? 1 : -1 ] __attribute__((__unused__)); | ||||
3022 | |||||
3023 | if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG0x04 && | ||||
3024 | descriptor->data.other_data.data.range.formula.cvt.flags & 0x10) | ||||
3025 | *res = true1; | ||||
3026 | } | ||||
3027 | |||||
3028 | /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ | ||||
3029 | static bool_Bool | ||||
3030 | drm_monitor_supports_rb(const struct drm_edid *drm_edid) | ||||
3031 | { | ||||
3032 | if (drm_edid->edid->revision >= 4) { | ||||
3033 | bool_Bool ret = false0; | ||||
3034 | |||||
3035 | drm_for_each_detailed_block(drm_edid, is_rb, &ret); | ||||
3036 | return ret; | ||||
3037 | } | ||||
3038 | |||||
3039 | return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL(1 << 7)) != 0); | ||||
3040 | } | ||||
3041 | |||||
3042 | static void | ||||
3043 | find_gtf2(const struct detailed_timing *descriptor, void *data) | ||||
3044 | { | ||||
3045 | const struct detailed_timing **res = data; | ||||
3046 | |||||
3047 | if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE0xfd)) | ||||
3048 | return; | ||||
3049 | |||||
3050 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.data.range.flags) != 10)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
3051 | |||||
3052 | if (descriptor->data.other_data.data.range.flags == 0x02) | ||||
3053 | *res = descriptor; | ||||
3054 | } | ||||
3055 | |||||
3056 | /* Secondary GTF curve kicks in above some break frequency */ | ||||
3057 | static int | ||||
3058 | drm_gtf2_hbreak(const struct drm_edid *drm_edid) | ||||
3059 | { | ||||
3060 | const struct detailed_timing *descriptor = NULL((void *)0); | ||||
3061 | |||||
3062 | drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); | ||||
3063 | |||||
3064 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12)) ? 1 : -1 ] __attribute__((__unused__)); | ||||
3065 | |||||
3066 | return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; | ||||
3067 | } | ||||
3068 | |||||
3069 | static int | ||||
3070 | drm_gtf2_2c(const struct drm_edid *drm_edid) | ||||
3071 | { | ||||
3072 | const struct detailed_timing *descriptor = NULL((void *)0); | ||||
3073 | |||||
3074 | drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); | ||||
3075 | |||||
3076 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.data.range.formula.gtf2.c) != 13)) ? 1 : - 1 ] __attribute__((__unused__)); | ||||
3077 | |||||
3078 | return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; | ||||
3079 | } | ||||
3080 | |||||
3081 | static int | ||||
3082 | drm_gtf2_m(const struct drm_edid *drm_edid) | ||||
3083 | { | ||||
3084 | const struct detailed_timing *descriptor = NULL((void *)0); | ||||
3085 | |||||
3086 | drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); | ||||
3087 | |||||
3088 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.data.range.formula.gtf2.m) != 14)) ? 1 : - 1 ] __attribute__((__unused__)); | ||||
3089 | |||||
3090 | return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m)((__uint16_t)(descriptor->data.other_data.data.range.formula .gtf2.m)) : 0; | ||||
3091 | } | ||||
3092 | |||||
3093 | static int | ||||
3094 | drm_gtf2_k(const struct drm_edid *drm_edid) | ||||
3095 | { | ||||
3096 | const struct detailed_timing *descriptor = NULL((void *)0); | ||||
3097 | |||||
3098 | drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); | ||||
3099 | |||||
3100 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.data.range.formula.gtf2.k) != 16)) ? 1 : - 1 ] __attribute__((__unused__)); | ||||
3101 | |||||
3102 | return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; | ||||
3103 | } | ||||
3104 | |||||
3105 | static int | ||||
3106 | drm_gtf2_2j(const struct drm_edid *drm_edid) | ||||
3107 | { | ||||
3108 | const struct detailed_timing *descriptor = NULL((void *)0); | ||||
3109 | |||||
3110 | drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); | ||||
3111 | |||||
3112 | BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17)extern char _ctassert[(!(__builtin_offsetof(typeof(*descriptor ), data.other_data.data.range.formula.gtf2.j) != 17)) ? 1 : - 1 ] __attribute__((__unused__)); | ||||
3113 | |||||
3114 | return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; | ||||
3115 | } | ||||
3116 | |||||
3117 | /* Get standard timing level (CVT/GTF/DMT). */ | ||||
3118 | static int standard_timing_level(const struct drm_edid *drm_edid) | ||||
3119 | { | ||||
3120 | const struct edid *edid = drm_edid->edid; | ||||
3121 | |||||
3122 | if (edid->revision >= 2) { | ||||
3123 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF(1 << 0))) | ||||
3124 | return LEVEL_CVT3; | ||||
3125 | if (drm_gtf2_hbreak(drm_edid)) | ||||
3126 | return LEVEL_GTF22; | ||||
3127 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF(1 << 0)) | ||||
3128 | return LEVEL_GTF1; | ||||
3129 | } | ||||
3130 | return LEVEL_DMT0; | ||||
3131 | } | ||||
3132 | |||||
3133 | /* | ||||
3134 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | ||||
3135 | * monitors fill with ascii space (0x20) instead. | ||||
3136 | */ | ||||
3137 | static int | ||||
3138 | bad_std_timing(u8 a, u8 b) | ||||
3139 | { | ||||
3140 | return (a == 0x00 && b == 0x00) || | ||||
3141 | (a == 0x01 && b == 0x01) || | ||||
3142 | (a == 0x20 && b == 0x20); | ||||
3143 | } | ||||
3144 | |||||
3145 | static int drm_mode_hsync(const struct drm_display_mode *mode) | ||||
3146 | { | ||||
3147 | if (mode->htotal <= 0) | ||||
3148 | return 0; | ||||
3149 | |||||
3150 | return DIV_ROUND_CLOSEST(mode->clock, mode->htotal)(((mode->clock) + ((mode->htotal) / 2)) / (mode->htotal )); | ||||
3151 | } | ||||
3152 | |||||
3153 | /* | ||||
3154 | * Take the standard timing params (in this case width, aspect, and refresh) | ||||
3155 | * and convert them into a real mode using CVT/GTF/DMT. | ||||
3156 | */ | ||||
3157 | static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, | ||||
3158 | const struct drm_edid *drm_edid, | ||||
3159 | const struct std_timing *t) | ||||
3160 | { | ||||
3161 | struct drm_device *dev = connector->dev; | ||||
3162 | struct drm_display_mode *m, *mode = NULL((void *)0); | ||||
3163 | int hsize, vsize; | ||||
3164 | int vrefresh_rate; | ||||
3165 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK(0x3 << 6)) | ||||
3166 | >> EDID_TIMING_ASPECT_SHIFT6; | ||||
3167 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK(0x3f << 0)) | ||||
3168 | >> EDID_TIMING_VFREQ_SHIFT0; | ||||
3169 | int timing_level = standard_timing_level(drm_edid); | ||||
3170 | |||||
3171 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) | ||||
3172 | return NULL((void *)0); | ||||
3173 | |||||
3174 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ | ||||
3175 | hsize = t->hsize * 8 + 248; | ||||
3176 | /* vrefresh_rate = vfreq + 60 */ | ||||
3177 | vrefresh_rate = vfreq + 60; | ||||
3178 | /* the vdisplay is calculated based on the aspect ratio */ | ||||
3179 | if (aspect_ratio == 0) { | ||||
3180 | if (drm_edid->edid->revision < 3) | ||||
3181 | vsize = hsize; | ||||
3182 | else | ||||
3183 | vsize = (hsize * 10) / 16; | ||||
3184 | } else if (aspect_ratio == 1) | ||||
3185 | vsize = (hsize * 3) / 4; | ||||
3186 | else if (aspect_ratio == 2) | ||||
3187 | vsize = (hsize * 4) / 5; | ||||
3188 | else | ||||
3189 | vsize = (hsize * 9) / 16; | ||||
3190 | |||||
3191 | /* HDTV hack, part 1 */ | ||||
3192 | if (vrefresh_rate == 60 && | ||||
3193 | ((hsize == 1360 && vsize == 765) || | ||||
3194 | (hsize == 1368 && vsize == 769))) { | ||||
3195 | hsize = 1366; | ||||
3196 | vsize = 768; | ||||
3197 | } | ||||
3198 | |||||
3199 | /* | ||||
3200 | * If this connector already has a mode for this size and refresh | ||||
3201 | * rate (because it came from detailed or CVT info), use that | ||||
3202 | * instead. This way we don't have to guess at interlace or | ||||
3203 | * reduced blanking. | ||||
3204 | */ | ||||
3205 | list_for_each_entry(m, &connector->probed_modes, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof(*m ) *)( (char *)__mptr - __builtin_offsetof(__typeof(*m), head) );}); &m->head != (&connector->probed_modes); m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = (m->head.next); (__typeof(*m) *)( (char *)__mptr - __builtin_offsetof (__typeof(*m), head) );})) | ||||
3206 | if (m->hdisplay == hsize && m->vdisplay == vsize && | ||||
3207 | drm_mode_vrefresh(m) == vrefresh_rate) | ||||
3208 | return NULL((void *)0); | ||||
3209 | |||||
3210 | /* HDTV hack, part 2 */ | ||||
3211 | if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { | ||||
3212 | mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, | ||||
3213 | false0); | ||||
3214 | if (!mode) | ||||
3215 | return NULL((void *)0); | ||||
3216 | mode->hdisplay = 1366; | ||||
3217 | mode->hsync_start = mode->hsync_start - 1; | ||||
3218 | mode->hsync_end = mode->hsync_end - 1; | ||||
3219 | return mode; | ||||
3220 | } | ||||
3221 | |||||
3222 | /* check whether it can be found in default mode table */ | ||||
3223 | if (drm_monitor_supports_rb(drm_edid)) { | ||||
3224 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, | ||||
3225 | true1); | ||||
3226 | if (mode) | ||||
3227 | return mode; | ||||
3228 | } | ||||
3229 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false0); | ||||
3230 | if (mode) | ||||
3231 | return mode; | ||||
3232 | |||||
3233 | /* okay, generate it */ | ||||
3234 | switch (timing_level) { | ||||
3235 | case LEVEL_DMT0: | ||||
3236 | break; | ||||
3237 | case LEVEL_GTF1: | ||||
3238 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | ||||
3239 | break; | ||||
3240 | case LEVEL_GTF22: | ||||
3241 | /* | ||||
3242 | * This is potentially wrong if there's ever a monitor with | ||||
3243 | * more than one ranges section, each claiming a different | ||||
3244 | * secondary GTF curve. Please don't do that. | ||||
3245 | */ | ||||
3246 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | ||||
3247 | if (!mode) | ||||
3248 | return NULL((void *)0); | ||||
3249 | if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { | ||||
3250 | drm_mode_destroy(dev, mode); | ||||
3251 | mode = drm_gtf_mode_complex(dev, hsize, vsize, | ||||
3252 | vrefresh_rate, 0, 0, | ||||
3253 | drm_gtf2_m(drm_edid), | ||||
3254 | drm_gtf2_2c(drm_edid), | ||||
3255 | drm_gtf2_k(drm_edid), | ||||
3256 | drm_gtf2_2j(drm_edid)); | ||||
3257 | } | ||||
3258 | break; | ||||
3259 | case LEVEL_CVT3: | ||||
3260 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, | ||||
3261 | false0); | ||||
3262 | break; | ||||
3263 | } | ||||
3264 | return mode; | ||||
3265 | } | ||||
3266 | |||||
3267 | /* | ||||
3268 | * EDID is delightfully ambiguous about how interlaced modes are to be | ||||
3269 | * encoded. Our internal representation is of frame height, but some | ||||
3270 | * HDTV detailed timings are encoded as field height. | ||||
3271 | * | ||||
3272 | * The format list here is from CEA, in frame size. Technically we | ||||
3273 | * should be checking refresh rate too. Whatever. | ||||
3274 | */ | ||||
3275 | static void | ||||
3276 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | ||||
3277 | const struct detailed_pixel_timing *pt) | ||||
3278 | { | ||||
3279 | int i; | ||||
3280 | static const struct { | ||||
3281 | int w, h; | ||||
3282 | } cea_interlaced[] = { | ||||
3283 | { 1920, 1080 }, | ||||
3284 | { 720, 480 }, | ||||
3285 | { 1440, 480 }, | ||||
3286 | { 2880, 480 }, | ||||
3287 | { 720, 576 }, | ||||
3288 | { 1440, 576 }, | ||||
3289 | { 2880, 576 }, | ||||
3290 | }; | ||||
3291 | |||||
3292 | if (!(pt->misc & DRM_EDID_PT_INTERLACED(1 << 7))) | ||||
3293 | return; | ||||
3294 | |||||
3295 | for (i = 0; i < ARRAY_SIZE(cea_interlaced)(sizeof((cea_interlaced)) / sizeof((cea_interlaced)[0])); i++) { | ||||
3296 | if ((mode->hdisplay == cea_interlaced[i].w) && | ||||
3297 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | ||||
3298 | mode->vdisplay *= 2; | ||||
3299 | mode->vsync_start *= 2; | ||||
3300 | mode->vsync_end *= 2; | ||||
3301 | mode->vtotal *= 2; | ||||
3302 | mode->vtotal |= 1; | ||||
3303 | } | ||||
3304 | } | ||||
3305 | |||||
3306 | mode->flags |= DRM_MODE_FLAG_INTERLACE(1<<4); | ||||
3307 | } | ||||
3308 | |||||
3309 | /* | ||||
3310 | * Create a new mode from an EDID detailed timing section. An EDID detailed | ||||
3311 | * timing block contains enough info for us to create and return a new struct | ||||
3312 | * drm_display_mode. | ||||
3313 | */ | ||||
3314 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | ||||
3315 | const struct drm_edid *drm_edid, | ||||
3316 | const struct detailed_timing *timing, | ||||
3317 | u32 quirks) | ||||
3318 | { | ||||
3319 | struct drm_display_mode *mode; | ||||
3320 | const struct detailed_pixel_timing *pt = &timing->data.pixel_data; | ||||
3321 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; | ||||
3322 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | ||||
3323 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | ||||
3324 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | ||||
3325 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; | ||||
3326 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | ||||
3327 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; | ||||
3328 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); | ||||
3329 | |||||
3330 | /* ignore tiny modes */ | ||||
3331 | if (hactive < 64 || vactive < 64) | ||||
3332 | return NULL((void *)0); | ||||
3333 | |||||
3334 | if (pt->misc & DRM_EDID_PT_STEREO(1 << 5)) { | ||||
3335 | DRM_DEBUG_KMS("stereo mode not supported\n")___drm_dbg(((void *)0), DRM_UT_KMS, "stereo mode not supported\n" ); | ||||
3336 | return NULL((void *)0); | ||||
3337 | } | ||||
3338 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC(3 << 3))) { | ||||
3339 | DRM_DEBUG_KMS("composite sync not supported\n")___drm_dbg(((void *)0), DRM_UT_KMS, "composite sync not supported\n" ); | ||||
3340 | } | ||||
3341 | |||||
3342 | /* it is incorrect if hsync/vsync width is zero */ | ||||
3343 | if (!hsync_pulse_width || !vsync_pulse_width) { | ||||
3344 | DRM_DEBUG_KMS("Incorrect Detailed timing. "___drm_dbg(((void *)0), DRM_UT_KMS, "Incorrect Detailed timing. " "Wrong Hsync/Vsync pulse width\n") | ||||
3345 | "Wrong Hsync/Vsync pulse width\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Incorrect Detailed timing. " "Wrong Hsync/Vsync pulse width\n"); | ||||
3346 | return NULL((void *)0); | ||||
3347 | } | ||||
3348 | |||||
3349 | if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING(1 << 7)) { | ||||
3350 | mode = drm_cvt_mode(dev, hactive, vactive, 60, true1, false0, false0); | ||||
3351 | if (!mode) | ||||
3352 | return NULL((void *)0); | ||||
3353 | |||||
3354 | goto set_size; | ||||
3355 | } | ||||
3356 | |||||
3357 | mode = drm_mode_create(dev); | ||||
3358 | if (!mode) | ||||
3359 | return NULL((void *)0); | ||||
3360 | |||||
3361 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH(1 << 1)) | ||||
3362 | mode->clock = 1088 * 10; | ||||
3363 | else | ||||
3364 | mode->clock = le16_to_cpu(timing->pixel_clock)((__uint16_t)(timing->pixel_clock)) * 10; | ||||
3365 | |||||
3366 | mode->hdisplay = hactive; | ||||
3367 | mode->hsync_start = mode->hdisplay + hsync_offset; | ||||
3368 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | ||||
3369 | mode->htotal = mode->hdisplay + hblank; | ||||
3370 | |||||
3371 | mode->vdisplay = vactive; | ||||
3372 | mode->vsync_start = mode->vdisplay + vsync_offset; | ||||
3373 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | ||||
3374 | mode->vtotal = mode->vdisplay + vblank; | ||||
3375 | |||||
3376 | /* Some EDIDs have bogus h/vtotal values */ | ||||
3377 | if (mode->hsync_end > mode->htotal) | ||||
3378 | mode->htotal = mode->hsync_end + 1; | ||||
3379 | if (mode->vsync_end > mode->vtotal) | ||||
3380 | mode->vtotal = mode->vsync_end + 1; | ||||
3381 | |||||
3382 | drm_mode_do_interlace_quirk(mode, pt); | ||||
3383 | |||||
3384 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP(1 << 6)) { | ||||
3385 | mode->flags |= DRM_MODE_FLAG_PHSYNC(1<<0) | DRM_MODE_FLAG_PVSYNC(1<<2); | ||||
3386 | } else { | ||||
3387 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE(1 << 1)) ? | ||||
3388 | DRM_MODE_FLAG_PHSYNC(1<<0) : DRM_MODE_FLAG_NHSYNC(1<<1); | ||||
3389 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE(1 << 2)) ? | ||||
3390 | DRM_MODE_FLAG_PVSYNC(1<<2) : DRM_MODE_FLAG_NVSYNC(1<<3); | ||||
3391 | } | ||||
3392 | |||||
3393 | set_size: | ||||
3394 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; | ||||
3395 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | ||||
3396 | |||||
3397 | if (quirks & EDID_QUIRK_DETAILED_IN_CM(1 << 3)) { | ||||
3398 | mode->width_mm *= 10; | ||||
3399 | mode->height_mm *= 10; | ||||
3400 | } | ||||
3401 | |||||
3402 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE(1 << 4)) { | ||||
3403 | mode->width_mm = drm_edid->edid->width_cm * 10; | ||||
3404 | mode->height_mm = drm_edid->edid->height_cm * 10; | ||||
3405 | } | ||||
3406 | |||||
3407 | mode->type = DRM_MODE_TYPE_DRIVER(1<<6); | ||||
3408 | drm_mode_set_name(mode); | ||||
3409 | |||||
3410 | return mode; | ||||
3411 | } | ||||
3412 | |||||
3413 | static bool_Bool | ||||
3414 | mode_in_hsync_range(const struct drm_display_mode *mode, | ||||
3415 | const struct edid *edid, const u8 *t) | ||||
3416 | { | ||||
3417 | int hsync, hmin, hmax; | ||||
3418 | |||||
3419 | hmin = t[7]; | ||||
3420 | if (edid->revision >= 4) | ||||
3421 | hmin += ((t[4] & 0x04) ? 255 : 0); | ||||
3422 | hmax = t[8]; | ||||
3423 | if (edid->revision >= 4) | ||||
3424 | hmax += ((t[4] & 0x08) ? 255 : 0); | ||||
3425 | hsync = drm_mode_hsync(mode); | ||||
3426 | |||||
3427 | return (hsync <= hmax && hsync >= hmin); | ||||
3428 | } | ||||
3429 | |||||
3430 | static bool_Bool | ||||
3431 | mode_in_vsync_range(const struct drm_display_mode *mode, | ||||
3432 | const struct edid *edid, const u8 *t) | ||||
3433 | { | ||||
3434 | int vsync, vmin, vmax; | ||||
3435 | |||||
3436 | vmin = t[5]; | ||||
3437 | if (edid->revision >= 4) | ||||
3438 | vmin += ((t[4] & 0x01) ? 255 : 0); | ||||
3439 | vmax = t[6]; | ||||
3440 | if (edid->revision >= 4) | ||||
3441 | vmax += ((t[4] & 0x02) ? 255 : 0); | ||||
3442 | vsync = drm_mode_vrefresh(mode); | ||||
3443 | |||||
3444 | return (vsync <= vmax && vsync >= vmin); | ||||
3445 | } | ||||
3446 | |||||
3447 | static u32 | ||||
3448 | range_pixel_clock(const struct edid *edid, const u8 *t) | ||||
3449 | { | ||||
3450 | /* unspecified */ | ||||
3451 | if (t[9] == 0 || t[9] == 255) | ||||
3452 | return 0; | ||||
3453 | |||||
3454 | /* 1.4 with CVT support gives us real precision, yay */ | ||||
3455 | if (edid->revision >= 4 && t[10] == 0x04) | ||||
3456 | return (t[9] * 10000) - ((t[12] >> 2) * 250); | ||||
3457 | |||||
3458 | /* 1.3 is pathetic, so fuzz up a bit */ | ||||
3459 | return t[9] * 10000 + 5001; | ||||
3460 | } | ||||
3461 | |||||
3462 | static bool_Bool mode_in_range(const struct drm_display_mode *mode, | ||||
3463 | const struct drm_edid *drm_edid, | ||||
3464 | const struct detailed_timing *timing) | ||||
3465 | { | ||||
3466 | const struct edid *edid = drm_edid->edid; | ||||
3467 | u32 max_clock; | ||||
3468 | const u8 *t = (const u8 *)timing; | ||||
3469 | |||||
3470 | if (!mode_in_hsync_range(mode, edid, t)) | ||||
3471 | return false0; | ||||
3472 | |||||
3473 | if (!mode_in_vsync_range(mode, edid, t)) | ||||
3474 | return false0; | ||||
3475 | |||||
3476 | if ((max_clock = range_pixel_clock(edid, t))) | ||||
3477 | if (mode->clock > max_clock) | ||||
3478 | return false0; | ||||
3479 | |||||
3480 | /* 1.4 max horizontal check */ | ||||
3481 | if (edid->revision >= 4 && t[10] == 0x04) | ||||
3482 | if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) | ||||
3483 | return false0; | ||||
3484 | |||||
3485 | if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) | ||||
3486 | return false0; | ||||
3487 | |||||
3488 | return true1; | ||||
3489 | } | ||||
3490 | |||||
3491 | static bool_Bool valid_inferred_mode(const struct drm_connector *connector, | ||||
3492 | const struct drm_display_mode *mode) | ||||
3493 | { | ||||
3494 | const struct drm_display_mode *m; | ||||
3495 | bool_Bool ok = false0; | ||||
3496 | |||||
3497 | list_for_each_entry(m, &connector->probed_modes, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof(*m ) *)( (char *)__mptr - __builtin_offsetof(__typeof(*m), head) );}); &m->head != (&connector->probed_modes); m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = (m->head.next); (__typeof(*m) *)( (char *)__mptr - __builtin_offsetof (__typeof(*m), head) );})) { | ||||
3498 | if (mode->hdisplay == m->hdisplay && | ||||
3499 | mode->vdisplay == m->vdisplay && | ||||
3500 | drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) | ||||
3501 | return false0; /* duplicated */ | ||||
3502 | if (mode->hdisplay <= m->hdisplay && | ||||
3503 | mode->vdisplay <= m->vdisplay) | ||||
3504 | ok = true1; | ||||
3505 | } | ||||
3506 | return ok; | ||||
3507 | } | ||||
3508 | |||||
3509 | static int drm_dmt_modes_for_range(struct drm_connector *connector, | ||||
3510 | const struct drm_edid *drm_edid, | ||||
3511 | const struct detailed_timing *timing) | ||||
3512 | { | ||||
3513 | int i, modes = 0; | ||||
3514 | struct drm_display_mode *newmode; | ||||
3515 | struct drm_device *dev = connector->dev; | ||||
3516 | |||||
3517 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes)(sizeof((drm_dmt_modes)) / sizeof((drm_dmt_modes)[0])); i++) { | ||||
3518 | if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && | ||||
3519 | valid_inferred_mode(connector, drm_dmt_modes + i)) { | ||||
3520 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); | ||||
3521 | if (newmode) { | ||||
3522 | drm_mode_probed_add(connector, newmode); | ||||
3523 | modes++; | ||||
3524 | } | ||||
3525 | } | ||||
3526 | } | ||||
3527 | |||||
3528 | return modes; | ||||
3529 | } | ||||
3530 | |||||
3531 | /* fix up 1366x768 mode from 1368x768; | ||||
3532 | * GFT/CVT can't express 1366 width which isn't dividable by 8 | ||||
3533 | */ | ||||
3534 | void drm_mode_fixup_1366x768(struct drm_display_mode *mode) | ||||
3535 | { | ||||
3536 | if (mode->hdisplay == 1368 && mode->vdisplay == 768) { | ||||
3537 | mode->hdisplay = 1366; | ||||
3538 | mode->hsync_start--; | ||||
3539 | mode->hsync_end--; | ||||
3540 | drm_mode_set_name(mode); | ||||
3541 | } | ||||
3542 | } | ||||
3543 | |||||
3544 | static int drm_gtf_modes_for_range(struct drm_connector *connector, | ||||
3545 | const struct drm_edid *drm_edid, | ||||
3546 | const struct detailed_timing *timing) | ||||
3547 | { | ||||
3548 | int i, modes = 0; | ||||
3549 | struct drm_display_mode *newmode; | ||||
3550 | struct drm_device *dev = connector->dev; | ||||
3551 | |||||
3552 | for (i = 0; i < ARRAY_SIZE(extra_modes)(sizeof((extra_modes)) / sizeof((extra_modes)[0])); i++) { | ||||
3553 | const struct minimode *m = &extra_modes[i]; | ||||
3554 | |||||
3555 | newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); | ||||
3556 | if (!newmode) | ||||
3557 | return modes; | ||||
3558 | |||||
3559 | drm_mode_fixup_1366x768(newmode); | ||||
3560 | if (!mode_in_range(newmode, drm_edid, timing) || | ||||
3561 | !valid_inferred_mode(connector, newmode)) { | ||||
3562 | drm_mode_destroy(dev, newmode); | ||||
3563 | continue; | ||||
3564 | } | ||||
3565 | |||||
3566 | drm_mode_probed_add(connector, newmode); | ||||
3567 | modes++; | ||||
3568 | } | ||||
3569 | |||||
3570 | return modes; | ||||
3571 | } | ||||
3572 | |||||
3573 | static int drm_cvt_modes_for_range(struct drm_connector *connector, | ||||
3574 | const struct drm_edid *drm_edid, | ||||
3575 | const struct detailed_timing *timing) | ||||
3576 | { | ||||
3577 | int i, modes = 0; | ||||
3578 | struct drm_display_mode *newmode; | ||||
3579 | struct drm_device *dev = connector->dev; | ||||
3580 | bool_Bool rb = drm_monitor_supports_rb(drm_edid); | ||||
3581 | |||||
3582 | for (i = 0; i < ARRAY_SIZE(extra_modes)(sizeof((extra_modes)) / sizeof((extra_modes)[0])); i++) { | ||||
3583 | const struct minimode *m = &extra_modes[i]; | ||||
3584 | |||||
3585 | newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); | ||||
3586 | if (!newmode) | ||||
3587 | return modes; | ||||
3588 | |||||
3589 | drm_mode_fixup_1366x768(newmode); | ||||
3590 | if (!mode_in_range(newmode, drm_edid, timing) || | ||||
3591 | !valid_inferred_mode(connector, newmode)) { | ||||
3592 | drm_mode_destroy(dev, newmode); | ||||
3593 | continue; | ||||
3594 | } | ||||
3595 | |||||
3596 | drm_mode_probed_add(connector, newmode); | ||||
3597 | modes++; | ||||
3598 | } | ||||
3599 | |||||
3600 | return modes; | ||||
3601 | } | ||||
3602 | |||||
3603 | static void | ||||
3604 | do_inferred_modes(const struct detailed_timing *timing, void *c) | ||||
3605 | { | ||||
3606 | struct detailed_mode_closure *closure = c; | ||||
3607 | const struct detailed_non_pixel *data = &timing->data.other_data; | ||||
3608 | const struct detailed_data_monitor_range *range = &data->data.range; | ||||
3609 | |||||
3610 | if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE0xfd)) | ||||
3611 | return; | ||||
3612 | |||||
3613 | closure->modes += drm_dmt_modes_for_range(closure->connector, | ||||
3614 | closure->drm_edid, | ||||
3615 | timing); | ||||
3616 | |||||
3617 | if (!version_greater(closure->drm_edid, 1, 1)) | ||||
3618 | return; /* GTF not defined yet */ | ||||
3619 | |||||
3620 | switch (range->flags) { | ||||
3621 | case 0x02: /* secondary gtf, XXX could do more */ | ||||
3622 | case 0x00: /* default gtf */ | ||||
3623 | closure->modes += drm_gtf_modes_for_range(closure->connector, | ||||
3624 | closure->drm_edid, | ||||
3625 | timing); | ||||
3626 | break; | ||||
3627 | case 0x04: /* cvt, only in 1.4+ */ | ||||
3628 | if (!version_greater(closure->drm_edid, 1, 3)) | ||||
3629 | break; | ||||
3630 | |||||
3631 | closure->modes += drm_cvt_modes_for_range(closure->connector, | ||||
3632 | closure->drm_edid, | ||||
3633 | timing); | ||||
3634 | break; | ||||
3635 | case 0x01: /* just the ranges, no formula */ | ||||
3636 | default: | ||||
3637 | break; | ||||
3638 | } | ||||
3639 | } | ||||
3640 | |||||
3641 | static int add_inferred_modes(struct drm_connector *connector, | ||||
3642 | const struct drm_edid *drm_edid) | ||||
3643 | { | ||||
3644 | struct detailed_mode_closure closure = { | ||||
3645 | .connector = connector, | ||||
3646 | .drm_edid = drm_edid, | ||||
3647 | }; | ||||
3648 | |||||
3649 | if (version_greater(drm_edid, 1, 0)) | ||||
3650 | drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); | ||||
3651 | |||||
3652 | return closure.modes; | ||||
3653 | } | ||||
3654 | |||||
3655 | static int | ||||
3656 | drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) | ||||
3657 | { | ||||
3658 | int i, j, m, modes = 0; | ||||
3659 | struct drm_display_mode *mode; | ||||
3660 | const u8 *est = ((const u8 *)timing) + 6; | ||||
3661 | |||||
3662 | for (i = 0; i < 6; i++) { | ||||
3663 | for (j = 7; j >= 0; j--) { | ||||
3664 | m = (i * 8) + (7 - j); | ||||
3665 | if (m >= ARRAY_SIZE(est3_modes)(sizeof((est3_modes)) / sizeof((est3_modes)[0]))) | ||||
3666 | break; | ||||
3667 | if (est[i] & (1 << j)) { | ||||
3668 | mode = drm_mode_find_dmt(connector->dev, | ||||
3669 | est3_modes[m].w, | ||||
3670 | est3_modes[m].h, | ||||
3671 | est3_modes[m].r, | ||||
3672 | est3_modes[m].rb); | ||||
3673 | if (mode) { | ||||
3674 | drm_mode_probed_add(connector, mode); | ||||
3675 | modes++; | ||||
3676 | } | ||||
3677 | } | ||||
3678 | } | ||||
3679 | } | ||||
3680 | |||||
3681 | return modes; | ||||
3682 | } | ||||
3683 | |||||
3684 | static void | ||||
3685 | do_established_modes(const struct detailed_timing *timing, void *c) | ||||
3686 | { | ||||
3687 | struct detailed_mode_closure *closure = c; | ||||
3688 | |||||
3689 | if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS0xf7)) | ||||
3690 | return; | ||||
3691 | |||||
3692 | closure->modes += drm_est3_modes(closure->connector, timing); | ||||
3693 | } | ||||
3694 | |||||
3695 | /* | ||||
3696 | * Get established modes from EDID and add them. Each EDID block contains a | ||||
3697 | * bitmap of the supported "established modes" list (defined above). Tease them | ||||
3698 | * out and add them to the global modes list. | ||||
3699 | */ | ||||
3700 | static int add_established_modes(struct drm_connector *connector, | ||||
3701 | const struct drm_edid *drm_edid) | ||||
3702 | { | ||||
3703 | struct drm_device *dev = connector->dev; | ||||
3704 | const struct edid *edid = drm_edid->edid; | ||||
3705 | unsigned long est_bits = edid->established_timings.t1 | | ||||
3706 | (edid->established_timings.t2 << 8) | | ||||
3707 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | ||||
3708 | int i, modes = 0; | ||||
3709 | struct detailed_mode_closure closure = { | ||||
3710 | .connector = connector, | ||||
3711 | .drm_edid = drm_edid, | ||||
3712 | }; | ||||
3713 | |||||
3714 | for (i = 0; i <= EDID_EST_TIMINGS16; i++) { | ||||
3715 | if (est_bits & (1<<i)) { | ||||
3716 | struct drm_display_mode *newmode; | ||||
3717 | |||||
3718 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); | ||||
3719 | if (newmode) { | ||||
3720 | drm_mode_probed_add(connector, newmode); | ||||
3721 | modes++; | ||||
3722 | } | ||||
3723 | } | ||||
3724 | } | ||||
3725 | |||||
3726 | if (version_greater(drm_edid, 1, 0)) | ||||
3727 | drm_for_each_detailed_block(drm_edid, do_established_modes, | ||||
3728 | &closure); | ||||
3729 | |||||
3730 | return modes + closure.modes; | ||||
3731 | } | ||||
3732 | |||||
3733 | static void | ||||
3734 | do_standard_modes(const struct detailed_timing *timing, void *c) | ||||
3735 | { | ||||
3736 | struct detailed_mode_closure *closure = c; | ||||
3737 | const struct detailed_non_pixel *data = &timing->data.other_data; | ||||
3738 | struct drm_connector *connector = closure->connector; | ||||
3739 | int i; | ||||
3740 | |||||
3741 | if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES0xfa)) | ||||
3742 | return; | ||||
3743 | |||||
3744 | for (i = 0; i < 6; i++) { | ||||
3745 | const struct std_timing *std = &data->data.timings[i]; | ||||
3746 | struct drm_display_mode *newmode; | ||||
3747 | |||||
3748 | newmode = drm_mode_std(connector, closure->drm_edid, std); | ||||
3749 | if (newmode) { | ||||
3750 | drm_mode_probed_add(connector, newmode); | ||||
3751 | closure->modes++; | ||||
3752 | } | ||||
3753 | } | ||||
3754 | } | ||||
3755 | |||||
3756 | /* | ||||
3757 | * Get standard modes from EDID and add them. Standard modes can be calculated | ||||
3758 | * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and | ||||
3759 | * add them to the list. | ||||
3760 | */ | ||||
3761 | static int add_standard_modes(struct drm_connector *connector, | ||||
3762 | const struct drm_edid *drm_edid) | ||||
3763 | { | ||||
3764 | int i, modes = 0; | ||||
3765 | struct detailed_mode_closure closure = { | ||||
3766 | .connector = connector, | ||||
3767 | .drm_edid = drm_edid, | ||||
3768 | }; | ||||
3769 | |||||
3770 | for (i = 0; i < EDID_STD_TIMINGS8; i++) { | ||||
3771 | struct drm_display_mode *newmode; | ||||
3772 | |||||
3773 | newmode = drm_mode_std(connector, drm_edid, | ||||
3774 | &drm_edid->edid->standard_timings[i]); | ||||
3775 | if (newmode) { | ||||
3776 | drm_mode_probed_add(connector, newmode); | ||||
3777 | modes++; | ||||
3778 | } | ||||
3779 | } | ||||
3780 | |||||
3781 | if (version_greater(drm_edid, 1, 0)) | ||||
3782 | drm_for_each_detailed_block(drm_edid, do_standard_modes, | ||||
3783 | &closure); | ||||
3784 | |||||
3785 | /* XXX should also look for standard codes in VTB blocks */ | ||||
3786 | |||||
3787 | return modes + closure.modes; | ||||
3788 | } | ||||
3789 | |||||
3790 | static int drm_cvt_modes(struct drm_connector *connector, | ||||
3791 | const struct detailed_timing *timing) | ||||
3792 | { | ||||
3793 | int i, j, modes = 0; | ||||
3794 | struct drm_display_mode *newmode; | ||||
3795 | struct drm_device *dev = connector->dev; | ||||
3796 | const struct cvt_timing *cvt; | ||||
3797 | const int rates[] = { 60, 85, 75, 60, 50 }; | ||||
3798 | const u8 empty[3] = { 0, 0, 0 }; | ||||
3799 | |||||
3800 | for (i = 0; i < 4; i++) { | ||||
3801 | int width, height; | ||||
3802 | |||||
3803 | cvt = &(timing->data.other_data.data.cvt[i]); | ||||
3804 | |||||
3805 | if (!memcmp(cvt->code, empty, 3)__builtin_memcmp((cvt->code), (empty), (3))) | ||||
3806 | continue; | ||||
3807 | |||||
3808 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; | ||||
3809 | switch (cvt->code[1] & 0x0c) { | ||||
3810 | /* default - because compiler doesn't see that we've enumerated all cases */ | ||||
3811 | default: | ||||
3812 | case 0x00: | ||||
3813 | width = height * 4 / 3; | ||||
3814 | break; | ||||
3815 | case 0x04: | ||||
3816 | width = height * 16 / 9; | ||||
3817 | break; | ||||
3818 | case 0x08: | ||||
3819 | width = height * 16 / 10; | ||||
3820 | break; | ||||
3821 | case 0x0c: | ||||
3822 | width = height * 15 / 9; | ||||
3823 | break; | ||||
3824 | } | ||||
3825 | |||||
3826 | for (j = 1; j < 5; j++) { | ||||
3827 | if (cvt->code[2] & (1 << j)) { | ||||
3828 | newmode = drm_cvt_mode(dev, width, height, | ||||
3829 | rates[j], j == 0, | ||||
3830 | false0, false0); | ||||
3831 | if (newmode) { | ||||
3832 | drm_mode_probed_add(connector, newmode); | ||||
3833 | modes++; | ||||
3834 | } | ||||
3835 | } | ||||
3836 | } | ||||
3837 | } | ||||
3838 | |||||
3839 | return modes; | ||||
3840 | } | ||||
3841 | |||||
3842 | static void | ||||
3843 | do_cvt_mode(const struct detailed_timing *timing, void *c) | ||||
3844 | { | ||||
3845 | struct detailed_mode_closure *closure = c; | ||||
3846 | |||||
3847 | if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE0xf8)) | ||||
3848 | return; | ||||
3849 | |||||
3850 | closure->modes += drm_cvt_modes(closure->connector, timing); | ||||
3851 | } | ||||
3852 | |||||
3853 | static int | ||||
3854 | add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) | ||||
3855 | { | ||||
3856 | struct detailed_mode_closure closure = { | ||||
3857 | .connector = connector, | ||||
3858 | .drm_edid = drm_edid, | ||||
3859 | }; | ||||
3860 | |||||
3861 | if (version_greater(drm_edid, 1, 2)) | ||||
3862 | drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); | ||||
3863 | |||||
3864 | /* XXX should also look for CVT codes in VTB blocks */ | ||||
3865 | |||||
3866 | return closure.modes; | ||||
3867 | } | ||||
3868 | |||||
3869 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); | ||||
3870 | |||||
3871 | static void | ||||
3872 | do_detailed_mode(const struct detailed_timing *timing, void *c) | ||||
3873 | { | ||||
3874 | struct detailed_mode_closure *closure = c; | ||||
3875 | struct drm_display_mode *newmode; | ||||
3876 | |||||
3877 | if (!is_detailed_timing_descriptor(timing)) | ||||
3878 | return; | ||||
3879 | |||||
3880 | newmode = drm_mode_detailed(closure->connector->dev, | ||||
3881 | closure->drm_edid, timing, | ||||
3882 | closure->quirks); | ||||
3883 | if (!newmode) | ||||
3884 | return; | ||||
3885 | |||||
3886 | if (closure->preferred) | ||||
3887 | newmode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
3888 | |||||
3889 | /* | ||||
3890 | * Detailed modes are limited to 10kHz pixel clock resolution, | ||||
3891 | * so fix up anything that looks like CEA/HDMI mode, but the clock | ||||
3892 | * is just slightly off. | ||||
3893 | */ | ||||
3894 | fixup_detailed_cea_mode_clock(newmode); | ||||
3895 | |||||
3896 | drm_mode_probed_add(closure->connector, newmode); | ||||
3897 | closure->modes++; | ||||
3898 | closure->preferred = false0; | ||||
3899 | } | ||||
3900 | |||||
3901 | /* | ||||
3902 | * add_detailed_modes - Add modes from detailed timings | ||||
3903 | * @connector: attached connector | ||||
3904 | * @drm_edid: EDID block to scan | ||||
3905 | * @quirks: quirks to apply | ||||
3906 | */ | ||||
3907 | static int add_detailed_modes(struct drm_connector *connector, | ||||
3908 | const struct drm_edid *drm_edid, u32 quirks) | ||||
3909 | { | ||||
3910 | struct detailed_mode_closure closure = { | ||||
3911 | .connector = connector, | ||||
3912 | .drm_edid = drm_edid, | ||||
3913 | .preferred = true1, | ||||
3914 | .quirks = quirks, | ||||
3915 | }; | ||||
3916 | |||||
3917 | if (closure.preferred && !version_greater(drm_edid, 1, 3)) | ||||
3918 | closure.preferred = | ||||
3919 | (drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING(1 << 1)); | ||||
3920 | |||||
3921 | drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); | ||||
3922 | |||||
3923 | return closure.modes; | ||||
3924 | } | ||||
3925 | |||||
3926 | /* CTA-861-H Table 60 - CTA Tag Codes */ | ||||
3927 | #define CTA_DB_AUDIO1 1 | ||||
3928 | #define CTA_DB_VIDEO2 2 | ||||
3929 | #define CTA_DB_VENDOR3 3 | ||||
3930 | #define CTA_DB_SPEAKER4 4 | ||||
3931 | #define CTA_DB_EXTENDED_TAG7 7 | ||||
3932 | |||||
3933 | /* CTA-861-H Table 62 - CTA Extended Tag Codes */ | ||||
3934 | #define CTA_EXT_DB_VIDEO_CAP0 0 | ||||
3935 | #define CTA_EXT_DB_VENDOR1 1 | ||||
3936 | #define CTA_EXT_DB_HDR_STATIC_METADATA6 6 | ||||
3937 | #define CTA_EXT_DB_420_VIDEO_DATA14 14 | ||||
3938 | #define CTA_EXT_DB_420_VIDEO_CAP_MAP15 15 | ||||
3939 | #define CTA_EXT_DB_HF_EEODB0x78 0x78 | ||||
3940 | #define CTA_EXT_DB_HF_SCDB0x79 0x79 | ||||
3941 | |||||
3942 | #define EDID_BASIC_AUDIO(1 << 6) (1 << 6) | ||||
3943 | #define EDID_CEA_YCRCB444(1 << 5) (1 << 5) | ||||
3944 | #define EDID_CEA_YCRCB422(1 << 4) (1 << 4) | ||||
3945 | #define EDID_CEA_VCDB_QS(1 << 6) (1 << 6) | ||||
3946 | |||||
3947 | /* | ||||
3948 | * Search EDID for CEA extension block. | ||||
3949 | * | ||||
3950 | * FIXME: Prefer not returning pointers to raw EDID data. | ||||
3951 | */ | ||||
3952 | const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, | ||||
3953 | int ext_id, int *ext_index) | ||||
3954 | { | ||||
3955 | const u8 *edid_ext = NULL((void *)0); | ||||
3956 | int i; | ||||
3957 | |||||
3958 | /* No EDID or EDID extensions */ | ||||
3959 | if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) | ||||
3960 | return NULL((void *)0); | ||||
3961 | |||||
3962 | /* Find CEA extension */ | ||||
3963 | for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { | ||||
3964 | edid_ext = drm_edid_extension_block_data(drm_edid, i); | ||||
3965 | if (edid_block_tag(edid_ext) == ext_id) | ||||
3966 | break; | ||||
3967 | } | ||||
3968 | |||||
3969 | if (i >= drm_edid_extension_block_count(drm_edid)) | ||||
3970 | return NULL((void *)0); | ||||
3971 | |||||
3972 | *ext_index = i + 1; | ||||
3973 | |||||
3974 | return edid_ext; | ||||
3975 | } | ||||
3976 | |||||
3977 | /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ | ||||
3978 | static bool_Bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) | ||||
3979 | { | ||||
3980 | const struct displayid_block *block; | ||||
3981 | struct displayid_iter iter; | ||||
3982 | int ext_index = 0; | ||||
3983 | bool_Bool found = false0; | ||||
3984 | |||||
3985 | /* Look for a top level CEA extension block */ | ||||
3986 | if (drm_find_edid_extension(drm_edid, CEA_EXT0x02, &ext_index)) | ||||
3987 | return true1; | ||||
3988 | |||||
3989 | /* CEA blocks can also be found embedded in a DisplayID block */ | ||||
3990 | displayid_iter_edid_begin(drm_edid, &iter); | ||||
3991 | displayid_iter_for_each(block, &iter)while (((block) = __displayid_iter_next(&iter))) { | ||||
3992 | if (block->tag == DATA_BLOCK_CTA0x81) { | ||||
3993 | found = true1; | ||||
3994 | break; | ||||
3995 | } | ||||
3996 | } | ||||
3997 | displayid_iter_end(&iter); | ||||
3998 | |||||
3999 | return found; | ||||
4000 | } | ||||
4001 | |||||
4002 | static __always_inlineinline __attribute__((__always_inline__)) const struct drm_display_mode *cea_mode_for_vic(u8 vic) | ||||
4003 | { | ||||
4004 | BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127)extern char _ctassert[(!(1 + (sizeof((edid_cea_modes_1)) / sizeof ((edid_cea_modes_1)[0])) - 1 != 127)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
4005 | BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219)extern char _ctassert[(!(193 + (sizeof((edid_cea_modes_193)) / sizeof((edid_cea_modes_193)[0])) - 1 != 219)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
4006 | |||||
4007 | if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)(sizeof((edid_cea_modes_1)) / sizeof((edid_cea_modes_1)[0]))) | ||||
4008 | return &edid_cea_modes_1[vic - 1]; | ||||
4009 | if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)(sizeof((edid_cea_modes_193)) / sizeof((edid_cea_modes_193)[0 ]))) | ||||
4010 | return &edid_cea_modes_193[vic - 193]; | ||||
4011 | return NULL((void *)0); | ||||
4012 | } | ||||
4013 | |||||
4014 | static u8 cea_num_vics(void) | ||||
4015 | { | ||||
4016 | return 193 + ARRAY_SIZE(edid_cea_modes_193)(sizeof((edid_cea_modes_193)) / sizeof((edid_cea_modes_193)[0 ])); | ||||
4017 | } | ||||
4018 | |||||
4019 | static u8 cea_next_vic(u8 vic) | ||||
4020 | { | ||||
4021 | if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)(sizeof((edid_cea_modes_1)) / sizeof((edid_cea_modes_1)[0]))) | ||||
4022 | vic = 193; | ||||
4023 | return vic; | ||||
4024 | } | ||||
4025 | |||||
4026 | /* | ||||
4027 | * Calculate the alternate clock for the CEA mode | ||||
4028 | * (60Hz vs. 59.94Hz etc.) | ||||
4029 | */ | ||||
4030 | static unsigned int | ||||
4031 | cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) | ||||
4032 | { | ||||
4033 | unsigned int clock = cea_mode->clock; | ||||
4034 | |||||
4035 | if (drm_mode_vrefresh(cea_mode) % 6 != 0) | ||||
4036 | return clock; | ||||
4037 | |||||
4038 | /* | ||||
4039 | * edid_cea_modes contains the 59.94Hz | ||||
4040 | * variant for 240 and 480 line modes, | ||||
4041 | * and the 60Hz variant otherwise. | ||||
4042 | */ | ||||
4043 | if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) | ||||
4044 | clock = DIV_ROUND_CLOSEST(clock * 1001, 1000)(((clock * 1001) + ((1000) / 2)) / (1000)); | ||||
4045 | else | ||||
4046 | clock = DIV_ROUND_CLOSEST(clock * 1000, 1001)(((clock * 1000) + ((1001) / 2)) / (1001)); | ||||
4047 | |||||
4048 | return clock; | ||||
4049 | } | ||||
4050 | |||||
4051 | static bool_Bool | ||||
4052 | cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) | ||||
4053 | { | ||||
4054 | /* | ||||
4055 | * For certain VICs the spec allows the vertical | ||||
4056 | * front porch to vary by one or two lines. | ||||
4057 | * | ||||
4058 | * cea_modes[] stores the variant with the shortest | ||||
4059 | * vertical front porch. We can adjust the mode to | ||||
4060 | * get the other variants by simply increasing the | ||||
4061 | * vertical front porch length. | ||||
4062 | */ | ||||
4063 | #ifdef notyet | ||||
4064 | BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
4065 | cea_mode_for_vic(9)->vtotal != 262 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
4066 | cea_mode_for_vic(12)->vtotal != 262 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
4067 | cea_mode_for_vic(13)->vtotal != 262 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
4068 | cea_mode_for_vic(23)->vtotal != 312 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
4069 | cea_mode_for_vic(24)->vtotal != 312 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
4070 | cea_mode_for_vic(27)->vtotal != 312 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
4071 | cea_mode_for_vic(28)->vtotal != 312)extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
4072 | #endif | ||||
4073 | |||||
4074 | if (((vic == 8 || vic == 9 || | ||||
4075 | vic == 12 || vic == 13) && mode->vtotal < 263) || | ||||
4076 | ((vic == 23 || vic == 24 || | ||||
4077 | vic == 27 || vic == 28) && mode->vtotal < 314)) { | ||||
4078 | mode->vsync_start++; | ||||
4079 | mode->vsync_end++; | ||||
4080 | mode->vtotal++; | ||||
4081 | |||||
4082 | return true1; | ||||
4083 | } | ||||
4084 | |||||
4085 | return false0; | ||||
4086 | } | ||||
4087 | |||||
4088 | static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, | ||||
4089 | unsigned int clock_tolerance) | ||||
4090 | { | ||||
4091 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS(1 << 0) | DRM_MODE_MATCH_FLAGS(1 << 2); | ||||
4092 | u8 vic; | ||||
4093 | |||||
4094 | if (!to_match->clock) | ||||
4095 | return 0; | ||||
4096 | |||||
4097 | if (to_match->picture_aspect_ratio) | ||||
4098 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO(1 << 4); | ||||
4099 | |||||
4100 | for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { | ||||
4101 | struct drm_display_mode cea_mode; | ||||
4102 | unsigned int clock1, clock2; | ||||
4103 | |||||
4104 | drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); | ||||
4105 | |||||
4106 | /* Check both 60Hz and 59.94Hz */ | ||||
4107 | clock1 = cea_mode.clock; | ||||
4108 | clock2 = cea_mode_alternate_clock(&cea_mode); | ||||
4109 | |||||
4110 | if (abs(to_match->clock - clock1) > clock_tolerance && | ||||
4111 | abs(to_match->clock - clock2) > clock_tolerance) | ||||
4112 | continue; | ||||
4113 | |||||
4114 | do { | ||||
4115 | if (drm_mode_match(to_match, &cea_mode, match_flags)) | ||||
4116 | return vic; | ||||
4117 | } while (cea_mode_alternate_timings(vic, &cea_mode)); | ||||
4118 | } | ||||
4119 | |||||
4120 | return 0; | ||||
4121 | } | ||||
4122 | |||||
4123 | /** | ||||
4124 | * drm_match_cea_mode - look for a CEA mode matching given mode | ||||
4125 | * @to_match: display mode | ||||
4126 | * | ||||
4127 | * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 | ||||
4128 | * mode. | ||||
4129 | */ | ||||
4130 | u8 drm_match_cea_mode(const struct drm_display_mode *to_match) | ||||
4131 | { | ||||
4132 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS(1 << 0) | DRM_MODE_MATCH_FLAGS(1 << 2); | ||||
4133 | u8 vic; | ||||
4134 | |||||
4135 | if (!to_match->clock) | ||||
4136 | return 0; | ||||
4137 | |||||
4138 | if (to_match->picture_aspect_ratio) | ||||
4139 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO(1 << 4); | ||||
4140 | |||||
4141 | for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { | ||||
4142 | struct drm_display_mode cea_mode; | ||||
4143 | unsigned int clock1, clock2; | ||||
4144 | |||||
4145 | drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); | ||||
4146 | |||||
4147 | /* Check both 60Hz and 59.94Hz */ | ||||
4148 | clock1 = cea_mode.clock; | ||||
4149 | clock2 = cea_mode_alternate_clock(&cea_mode); | ||||
4150 | |||||
4151 | if (KHZ2PICOS(to_match->clock)(1000000000UL/(to_match->clock)) != KHZ2PICOS(clock1)(1000000000UL/(clock1)) && | ||||
4152 | KHZ2PICOS(to_match->clock)(1000000000UL/(to_match->clock)) != KHZ2PICOS(clock2)(1000000000UL/(clock2))) | ||||
4153 | continue; | ||||
4154 | |||||
4155 | do { | ||||
4156 | if (drm_mode_match(to_match, &cea_mode, match_flags)) | ||||
4157 | return vic; | ||||
4158 | } while (cea_mode_alternate_timings(vic, &cea_mode)); | ||||
4159 | } | ||||
4160 | |||||
4161 | return 0; | ||||
4162 | } | ||||
4163 | EXPORT_SYMBOL(drm_match_cea_mode); | ||||
4164 | |||||
4165 | static bool_Bool drm_valid_cea_vic(u8 vic) | ||||
4166 | { | ||||
4167 | return cea_mode_for_vic(vic) != NULL((void *)0); | ||||
4168 | } | ||||
4169 | |||||
4170 | static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) | ||||
4171 | { | ||||
4172 | const struct drm_display_mode *mode = cea_mode_for_vic(video_code); | ||||
4173 | |||||
4174 | if (mode) | ||||
4175 | return mode->picture_aspect_ratio; | ||||
4176 | |||||
4177 | return HDMI_PICTURE_ASPECT_NONE; | ||||
4178 | } | ||||
4179 | |||||
4180 | static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) | ||||
4181 | { | ||||
4182 | return edid_4k_modes[video_code].picture_aspect_ratio; | ||||
4183 | } | ||||
4184 | |||||
4185 | /* | ||||
4186 | * Calculate the alternate clock for HDMI modes (those from the HDMI vendor | ||||
4187 | * specific block). | ||||
4188 | */ | ||||
4189 | static unsigned int | ||||
4190 | hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) | ||||
4191 | { | ||||
4192 | return cea_mode_alternate_clock(hdmi_mode); | ||||
4193 | } | ||||
4194 | |||||
4195 | static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, | ||||
4196 | unsigned int clock_tolerance) | ||||
4197 | { | ||||
4198 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS(1 << 0) | DRM_MODE_MATCH_FLAGS(1 << 2); | ||||
4199 | u8 vic; | ||||
4200 | |||||
4201 | if (!to_match->clock) | ||||
4202 | return 0; | ||||
4203 | |||||
4204 | if (to_match->picture_aspect_ratio) | ||||
4205 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO(1 << 4); | ||||
4206 | |||||
4207 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes)(sizeof((edid_4k_modes)) / sizeof((edid_4k_modes)[0])); vic++) { | ||||
4208 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | ||||
4209 | unsigned int clock1, clock2; | ||||
4210 | |||||
4211 | /* Make sure to also match alternate clocks */ | ||||
4212 | clock1 = hdmi_mode->clock; | ||||
4213 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | ||||
4214 | |||||
4215 | if (abs(to_match->clock - clock1) > clock_tolerance && | ||||
4216 | abs(to_match->clock - clock2) > clock_tolerance) | ||||
4217 | continue; | ||||
4218 | |||||
4219 | if (drm_mode_match(to_match, hdmi_mode, match_flags)) | ||||
4220 | return vic; | ||||
4221 | } | ||||
4222 | |||||
4223 | return 0; | ||||
4224 | } | ||||
4225 | |||||
4226 | /* | ||||
4227 | * drm_match_hdmi_mode - look for a HDMI mode matching given mode | ||||
4228 | * @to_match: display mode | ||||
4229 | * | ||||
4230 | * An HDMI mode is one defined in the HDMI vendor specific block. | ||||
4231 | * | ||||
4232 | * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. | ||||
4233 | */ | ||||
4234 | static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) | ||||
4235 | { | ||||
4236 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS(1 << 0) | DRM_MODE_MATCH_FLAGS(1 << 2); | ||||
4237 | u8 vic; | ||||
4238 | |||||
4239 | if (!to_match->clock) | ||||
4240 | return 0; | ||||
4241 | |||||
4242 | if (to_match->picture_aspect_ratio) | ||||
4243 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO(1 << 4); | ||||
4244 | |||||
4245 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes)(sizeof((edid_4k_modes)) / sizeof((edid_4k_modes)[0])); vic++) { | ||||
4246 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | ||||
4247 | unsigned int clock1, clock2; | ||||
4248 | |||||
4249 | /* Make sure to also match alternate clocks */ | ||||
4250 | clock1 = hdmi_mode->clock; | ||||
4251 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | ||||
4252 | |||||
4253 | if ((KHZ2PICOS(to_match->clock)(1000000000UL/(to_match->clock)) == KHZ2PICOS(clock1)(1000000000UL/(clock1)) || | ||||
4254 | KHZ2PICOS(to_match->clock)(1000000000UL/(to_match->clock)) == KHZ2PICOS(clock2)(1000000000UL/(clock2))) && | ||||
4255 | drm_mode_match(to_match, hdmi_mode, match_flags)) | ||||
4256 | return vic; | ||||
4257 | } | ||||
4258 | return 0; | ||||
4259 | } | ||||
4260 | |||||
4261 | static bool_Bool drm_valid_hdmi_vic(u8 vic) | ||||
4262 | { | ||||
4263 | return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes)(sizeof((edid_4k_modes)) / sizeof((edid_4k_modes)[0])); | ||||
4264 | } | ||||
4265 | |||||
4266 | static int add_alternate_cea_modes(struct drm_connector *connector, | ||||
4267 | const struct drm_edid *drm_edid) | ||||
4268 | { | ||||
4269 | struct drm_device *dev = connector->dev; | ||||
4270 | struct drm_display_mode *mode, *tmp; | ||||
4271 | DRM_LIST_HEAD(list)struct list_head list = { &(list), &(list) }; | ||||
4272 | int modes = 0; | ||||
4273 | |||||
4274 | /* Don't add CTA modes if the CTA extension block is missing */ | ||||
4275 | if (!drm_edid_has_cta_extension(drm_edid)) | ||||
4276 | return 0; | ||||
4277 | |||||
4278 | /* | ||||
4279 | * Go through all probed modes and create a new mode | ||||
4280 | * with the alternate clock for certain CEA modes. | ||||
4281 | */ | ||||
4282 | list_for_each_entry(mode, &connector->probed_modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof (*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode ), head) );}); &mode->head != (&connector->probed_modes ); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char * )__mptr - __builtin_offsetof(__typeof(*mode), head) );})) { | ||||
4283 | const struct drm_display_mode *cea_mode = NULL((void *)0); | ||||
4284 | struct drm_display_mode *newmode; | ||||
4285 | u8 vic = drm_match_cea_mode(mode); | ||||
4286 | unsigned int clock1, clock2; | ||||
4287 | |||||
4288 | if (drm_valid_cea_vic(vic)) { | ||||
4289 | cea_mode = cea_mode_for_vic(vic); | ||||
4290 | clock2 = cea_mode_alternate_clock(cea_mode); | ||||
4291 | } else { | ||||
4292 | vic = drm_match_hdmi_mode(mode); | ||||
4293 | if (drm_valid_hdmi_vic(vic)) { | ||||
4294 | cea_mode = &edid_4k_modes[vic]; | ||||
4295 | clock2 = hdmi_mode_alternate_clock(cea_mode); | ||||
4296 | } | ||||
4297 | } | ||||
4298 | |||||
4299 | if (!cea_mode) | ||||
4300 | continue; | ||||
4301 | |||||
4302 | clock1 = cea_mode->clock; | ||||
4303 | |||||
4304 | if (clock1 == clock2) | ||||
4305 | continue; | ||||
4306 | |||||
4307 | if (mode->clock != clock1 && mode->clock != clock2) | ||||
4308 | continue; | ||||
4309 | |||||
4310 | newmode = drm_mode_duplicate(dev, cea_mode); | ||||
4311 | if (!newmode) | ||||
4312 | continue; | ||||
4313 | |||||
4314 | /* Carry over the stereo flags */ | ||||
4315 | newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK(0x1f<<14); | ||||
4316 | |||||
4317 | /* | ||||
4318 | * The current mode could be either variant. Make | ||||
4319 | * sure to pick the "other" clock for the new mode. | ||||
4320 | */ | ||||
4321 | if (mode->clock != clock1) | ||||
4322 | newmode->clock = clock1; | ||||
4323 | else | ||||
4324 | newmode->clock = clock2; | ||||
4325 | |||||
4326 | list_add_tail(&newmode->head, &list); | ||||
4327 | } | ||||
4328 | |||||
4329 | list_for_each_entry_safe(mode, tmp, &list, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&list)->next); (__typeof(*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode), head) );}), tmp = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode), head) );}); &mode-> head != (&list); mode = tmp, tmp = ({ const __typeof( ((__typeof (*tmp) *)0)->head ) *__mptr = (tmp->head.next); (__typeof (*tmp) *)( (char *)__mptr - __builtin_offsetof(__typeof(*tmp) , head) );})) { | ||||
4330 | list_del(&mode->head); | ||||
4331 | drm_mode_probed_add(connector, mode); | ||||
4332 | modes++; | ||||
4333 | } | ||||
4334 | |||||
4335 | return modes; | ||||
4336 | } | ||||
4337 | |||||
4338 | static u8 svd_to_vic(u8 svd) | ||||
4339 | { | ||||
4340 | /* 0-6 bit vic, 7th bit native mode indicator */ | ||||
4341 | if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) | ||||
4342 | return svd & 127; | ||||
4343 | |||||
4344 | return svd; | ||||
4345 | } | ||||
4346 | |||||
4347 | static struct drm_display_mode * | ||||
4348 | drm_display_mode_from_vic_index(struct drm_connector *connector, | ||||
4349 | const u8 *video_db, u8 video_len, | ||||
4350 | u8 video_index) | ||||
4351 | { | ||||
4352 | struct drm_device *dev = connector->dev; | ||||
4353 | struct drm_display_mode *newmode; | ||||
4354 | u8 vic; | ||||
4355 | |||||
4356 | if (video_db == NULL((void *)0) || video_index >= video_len) | ||||
4357 | return NULL((void *)0); | ||||
4358 | |||||
4359 | /* CEA modes are numbered 1..127 */ | ||||
4360 | vic = svd_to_vic(video_db[video_index]); | ||||
4361 | if (!drm_valid_cea_vic(vic)) | ||||
4362 | return NULL((void *)0); | ||||
4363 | |||||
4364 | newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); | ||||
4365 | if (!newmode) | ||||
4366 | return NULL((void *)0); | ||||
4367 | |||||
4368 | return newmode; | ||||
4369 | } | ||||
4370 | |||||
4371 | /* | ||||
4372 | * do_y420vdb_modes - Parse YCBCR 420 only modes | ||||
4373 | * @connector: connector corresponding to the HDMI sink | ||||
4374 | * @svds: start of the data block of CEA YCBCR 420 VDB | ||||
4375 | * @len: length of the CEA YCBCR 420 VDB | ||||
4376 | * | ||||
4377 | * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) | ||||
4378 | * which contains modes which can be supported in YCBCR 420 | ||||
4379 | * output format only. | ||||
4380 | */ | ||||
4381 | static int do_y420vdb_modes(struct drm_connector *connector, | ||||
4382 | const u8 *svds, u8 svds_len) | ||||
4383 | { | ||||
4384 | int modes = 0, i; | ||||
4385 | struct drm_device *dev = connector->dev; | ||||
4386 | struct drm_display_info *info = &connector->display_info; | ||||
4387 | struct drm_hdmi_info *hdmi = &info->hdmi; | ||||
4388 | |||||
4389 | for (i = 0; i < svds_len; i++) { | ||||
4390 | u8 vic = svd_to_vic(svds[i]); | ||||
4391 | struct drm_display_mode *newmode; | ||||
4392 | |||||
4393 | if (!drm_valid_cea_vic(vic)) | ||||
4394 | continue; | ||||
4395 | |||||
4396 | newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); | ||||
4397 | if (!newmode) | ||||
4398 | break; | ||||
4399 | bitmap_set(hdmi->y420_vdb_modes, vic, 1); | ||||
4400 | drm_mode_probed_add(connector, newmode); | ||||
4401 | modes++; | ||||
4402 | } | ||||
4403 | |||||
4404 | if (modes > 0) | ||||
4405 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR420(1<<3); | ||||
4406 | return modes; | ||||
4407 | } | ||||
4408 | |||||
4409 | /* | ||||
4410 | * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap | ||||
4411 | * @connector: connector corresponding to the HDMI sink | ||||
4412 | * @vic: CEA vic for the video mode to be added in the map | ||||
4413 | * | ||||
4414 | * Makes an entry for a videomode in the YCBCR 420 bitmap | ||||
4415 | */ | ||||
4416 | static void | ||||
4417 | drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) | ||||
4418 | { | ||||
4419 | u8 vic = svd_to_vic(svd); | ||||
4420 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; | ||||
4421 | |||||
4422 | if (!drm_valid_cea_vic(vic)) | ||||
4423 | return; | ||||
4424 | |||||
4425 | bitmap_set(hdmi->y420_cmdb_modes, vic, 1); | ||||
4426 | } | ||||
4427 | |||||
4428 | /** | ||||
4429 | * drm_display_mode_from_cea_vic() - return a mode for CEA VIC | ||||
4430 | * @dev: DRM device | ||||
4431 | * @video_code: CEA VIC of the mode | ||||
4432 | * | ||||
4433 | * Creates a new mode matching the specified CEA VIC. | ||||
4434 | * | ||||
4435 | * Returns: A new drm_display_mode on success or NULL on failure | ||||
4436 | */ | ||||
4437 | struct drm_display_mode * | ||||
4438 | drm_display_mode_from_cea_vic(struct drm_device *dev, | ||||
4439 | u8 video_code) | ||||
4440 | { | ||||
4441 | const struct drm_display_mode *cea_mode; | ||||
4442 | struct drm_display_mode *newmode; | ||||
4443 | |||||
4444 | cea_mode = cea_mode_for_vic(video_code); | ||||
4445 | if (!cea_mode) | ||||
4446 | return NULL((void *)0); | ||||
4447 | |||||
4448 | newmode = drm_mode_duplicate(dev, cea_mode); | ||||
4449 | if (!newmode) | ||||
4450 | return NULL((void *)0); | ||||
4451 | |||||
4452 | return newmode; | ||||
4453 | } | ||||
4454 | EXPORT_SYMBOL(drm_display_mode_from_cea_vic); | ||||
4455 | |||||
4456 | static int | ||||
4457 | do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) | ||||
4458 | { | ||||
4459 | int i, modes = 0; | ||||
4460 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; | ||||
4461 | |||||
4462 | for (i = 0; i < len; i++) { | ||||
4463 | struct drm_display_mode *mode; | ||||
4464 | |||||
4465 | mode = drm_display_mode_from_vic_index(connector, db, len, i); | ||||
4466 | if (mode) { | ||||
4467 | /* | ||||
4468 | * YCBCR420 capability block contains a bitmap which | ||||
4469 | * gives the index of CEA modes from CEA VDB, which | ||||
4470 | * can support YCBCR 420 sampling output also (apart | ||||
4471 | * from RGB/YCBCR444 etc). | ||||
4472 | * For example, if the bit 0 in bitmap is set, | ||||
4473 | * first mode in VDB can support YCBCR420 output too. | ||||
4474 | * Add YCBCR420 modes only if sink is HDMI 2.0 capable. | ||||
4475 | */ | ||||
4476 | if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) | ||||
4477 | drm_add_cmdb_modes(connector, db[i]); | ||||
4478 | |||||
4479 | drm_mode_probed_add(connector, mode); | ||||
4480 | modes++; | ||||
4481 | } | ||||
4482 | } | ||||
4483 | |||||
4484 | return modes; | ||||
4485 | } | ||||
4486 | |||||
4487 | struct stereo_mandatory_mode { | ||||
4488 | int width, height, vrefresh; | ||||
4489 | unsigned int flags; | ||||
4490 | }; | ||||
4491 | |||||
4492 | static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { | ||||
4493 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14) }, | ||||
4494 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14) }, | ||||
4495 | { 1920, 1080, 50, | ||||
4496 | DRM_MODE_FLAG_INTERLACE(1<<4) | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14) }, | ||||
4497 | { 1920, 1080, 60, | ||||
4498 | DRM_MODE_FLAG_INTERLACE(1<<4) | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14) }, | ||||
4499 | { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14) }, | ||||
4500 | { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14) }, | ||||
4501 | { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14) }, | ||||
4502 | { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14) } | ||||
4503 | }; | ||||
4504 | |||||
4505 | static bool_Bool | ||||
4506 | stereo_match_mandatory(const struct drm_display_mode *mode, | ||||
4507 | const struct stereo_mandatory_mode *stereo_mode) | ||||
4508 | { | ||||
4509 | unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4); | ||||
4510 | |||||
4511 | return mode->hdisplay == stereo_mode->width && | ||||
4512 | mode->vdisplay == stereo_mode->height && | ||||
4513 | interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) && | ||||
4514 | drm_mode_vrefresh(mode) == stereo_mode->vrefresh; | ||||
4515 | } | ||||
4516 | |||||
4517 | static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) | ||||
4518 | { | ||||
4519 | struct drm_device *dev = connector->dev; | ||||
4520 | const struct drm_display_mode *mode; | ||||
4521 | struct list_head stereo_modes; | ||||
4522 | int modes = 0, i; | ||||
4523 | |||||
4524 | INIT_LIST_HEAD(&stereo_modes); | ||||
4525 | |||||
4526 | list_for_each_entry(mode, &connector->probed_modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof (*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode ), head) );}); &mode->head != (&connector->probed_modes ); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char * )__mptr - __builtin_offsetof(__typeof(*mode), head) );})) { | ||||
4527 | for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes)(sizeof((stereo_mandatory_modes)) / sizeof((stereo_mandatory_modes )[0])); i++) { | ||||
4528 | const struct stereo_mandatory_mode *mandatory; | ||||
4529 | struct drm_display_mode *new_mode; | ||||
4530 | |||||
4531 | if (!stereo_match_mandatory(mode, | ||||
4532 | &stereo_mandatory_modes[i])) | ||||
4533 | continue; | ||||
4534 | |||||
4535 | mandatory = &stereo_mandatory_modes[i]; | ||||
4536 | new_mode = drm_mode_duplicate(dev, mode); | ||||
4537 | if (!new_mode) | ||||
4538 | continue; | ||||
4539 | |||||
4540 | new_mode->flags |= mandatory->flags; | ||||
4541 | list_add_tail(&new_mode->head, &stereo_modes); | ||||
4542 | modes++; | ||||
4543 | } | ||||
4544 | } | ||||
4545 | |||||
4546 | list_splice_tail(&stereo_modes, &connector->probed_modes); | ||||
4547 | |||||
4548 | return modes; | ||||
4549 | } | ||||
4550 | |||||
4551 | static int add_hdmi_mode(struct drm_connector *connector, u8 vic) | ||||
4552 | { | ||||
4553 | struct drm_device *dev = connector->dev; | ||||
4554 | struct drm_display_mode *newmode; | ||||
4555 | |||||
4556 | if (!drm_valid_hdmi_vic(vic)) { | ||||
4557 | DRM_ERROR("Unknown HDMI VIC: %d\n", vic)__drm_err("Unknown HDMI VIC: %d\n", vic); | ||||
4558 | return 0; | ||||
4559 | } | ||||
4560 | |||||
4561 | newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); | ||||
4562 | if (!newmode) | ||||
4563 | return 0; | ||||
4564 | |||||
4565 | drm_mode_probed_add(connector, newmode); | ||||
4566 | |||||
4567 | return 1; | ||||
4568 | } | ||||
4569 | |||||
4570 | static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, | ||||
4571 | const u8 *video_db, u8 video_len, u8 video_index) | ||||
4572 | { | ||||
4573 | struct drm_display_mode *newmode; | ||||
4574 | int modes = 0; | ||||
4575 | |||||
4576 | if (structure & (1 << 0)) { | ||||
4577 | newmode = drm_display_mode_from_vic_index(connector, video_db, | ||||
4578 | video_len, | ||||
4579 | video_index); | ||||
4580 | if (newmode) { | ||||
4581 | newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14); | ||||
4582 | drm_mode_probed_add(connector, newmode); | ||||
4583 | modes++; | ||||
4584 | } | ||||
4585 | } | ||||
4586 | if (structure & (1 << 6)) { | ||||
4587 | newmode = drm_display_mode_from_vic_index(connector, video_db, | ||||
4588 | video_len, | ||||
4589 | video_index); | ||||
4590 | if (newmode) { | ||||
4591 | newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14); | ||||
4592 | drm_mode_probed_add(connector, newmode); | ||||
4593 | modes++; | ||||
4594 | } | ||||
4595 | } | ||||
4596 | if (structure & (1 << 8)) { | ||||
4597 | newmode = drm_display_mode_from_vic_index(connector, video_db, | ||||
4598 | video_len, | ||||
4599 | video_index); | ||||
4600 | if (newmode) { | ||||
4601 | newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14); | ||||
4602 | drm_mode_probed_add(connector, newmode); | ||||
4603 | modes++; | ||||
4604 | } | ||||
4605 | } | ||||
4606 | |||||
4607 | return modes; | ||||
4608 | } | ||||
4609 | |||||
4610 | /* | ||||
4611 | * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block | ||||
4612 | * @connector: connector corresponding to the HDMI sink | ||||
4613 | * @db: start of the CEA vendor specific block | ||||
4614 | * @len: length of the CEA block payload, ie. one can access up to db[len] | ||||
4615 | * | ||||
4616 | * Parses the HDMI VSDB looking for modes to add to @connector. This function | ||||
4617 | * also adds the stereo 3d modes when applicable. | ||||
4618 | */ | ||||
4619 | static int | ||||
4620 | do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, | ||||
4621 | const u8 *video_db, u8 video_len) | ||||
4622 | { | ||||
4623 | struct drm_display_info *info = &connector->display_info; | ||||
4624 | int modes = 0, offset = 0, i, multi_present = 0, multi_len; | ||||
4625 | u8 vic_len, hdmi_3d_len = 0; | ||||
4626 | u16 mask; | ||||
4627 | u16 structure_all; | ||||
4628 | |||||
4629 | if (len < 8) | ||||
4630 | goto out; | ||||
4631 | |||||
4632 | /* no HDMI_Video_Present */ | ||||
4633 | if (!(db[8] & (1 << 5))) | ||||
4634 | goto out; | ||||
4635 | |||||
4636 | /* Latency_Fields_Present */ | ||||
4637 | if (db[8] & (1 << 7)) | ||||
4638 | offset += 2; | ||||
4639 | |||||
4640 | /* I_Latency_Fields_Present */ | ||||
4641 | if (db[8] & (1 << 6)) | ||||
4642 | offset += 2; | ||||
4643 | |||||
4644 | /* the declared length is not long enough for the 2 first bytes | ||||
4645 | * of additional video format capabilities */ | ||||
4646 | if (len < (8 + offset + 2)) | ||||
4647 | goto out; | ||||
4648 | |||||
4649 | /* 3D_Present */ | ||||
4650 | offset++; | ||||
4651 | if (db[8 + offset] & (1 << 7)) { | ||||
4652 | modes += add_hdmi_mandatory_stereo_modes(connector); | ||||
4653 | |||||
4654 | /* 3D_Multi_present */ | ||||
4655 | multi_present = (db[8 + offset] & 0x60) >> 5; | ||||
4656 | } | ||||
4657 | |||||
4658 | offset++; | ||||
4659 | vic_len = db[8 + offset] >> 5; | ||||
4660 | hdmi_3d_len = db[8 + offset] & 0x1f; | ||||
4661 | |||||
4662 | for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { | ||||
4663 | u8 vic; | ||||
4664 | |||||
4665 | vic = db[9 + offset + i]; | ||||
4666 | modes += add_hdmi_mode(connector, vic); | ||||
4667 | } | ||||
4668 | offset += 1 + vic_len; | ||||
4669 | |||||
4670 | if (multi_present == 1) | ||||
4671 | multi_len = 2; | ||||
4672 | else if (multi_present == 2) | ||||
4673 | multi_len = 4; | ||||
4674 | else | ||||
4675 | multi_len = 0; | ||||
4676 | |||||
4677 | if (len < (8 + offset + hdmi_3d_len - 1)) | ||||
4678 | goto out; | ||||
4679 | |||||
4680 | if (hdmi_3d_len < multi_len) | ||||
4681 | goto out; | ||||
4682 | |||||
4683 | if (multi_present == 1 || multi_present == 2) { | ||||
4684 | /* 3D_Structure_ALL */ | ||||
4685 | structure_all = (db[8 + offset] << 8) | db[9 + offset]; | ||||
4686 | |||||
4687 | /* check if 3D_MASK is present */ | ||||
4688 | if (multi_present == 2) | ||||
4689 | mask = (db[10 + offset] << 8) | db[11 + offset]; | ||||
4690 | else | ||||
4691 | mask = 0xffff; | ||||
4692 | |||||
4693 | for (i = 0; i < 16; i++) { | ||||
4694 | if (mask & (1 << i)) | ||||
4695 | modes += add_3d_struct_modes(connector, | ||||
4696 | structure_all, | ||||
4697 | video_db, | ||||
4698 | video_len, i); | ||||
4699 | } | ||||
4700 | } | ||||
4701 | |||||
4702 | offset += multi_len; | ||||
4703 | |||||
4704 | for (i = 0; i < (hdmi_3d_len - multi_len); i++) { | ||||
4705 | int vic_index; | ||||
4706 | struct drm_display_mode *newmode = NULL((void *)0); | ||||
4707 | unsigned int newflag = 0; | ||||
4708 | bool_Bool detail_present; | ||||
4709 | |||||
4710 | detail_present = ((db[8 + offset + i] & 0x0f) > 7); | ||||
4711 | |||||
4712 | if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) | ||||
4713 | break; | ||||
4714 | |||||
4715 | /* 2D_VIC_order_X */ | ||||
4716 | vic_index = db[8 + offset + i] >> 4; | ||||
4717 | |||||
4718 | /* 3D_Structure_X */ | ||||
4719 | switch (db[8 + offset + i] & 0x0f) { | ||||
4720 | case 0: | ||||
4721 | newflag = DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14); | ||||
4722 | break; | ||||
4723 | case 6: | ||||
4724 | newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14); | ||||
4725 | break; | ||||
4726 | case 8: | ||||
4727 | /* 3D_Detail_X */ | ||||
4728 | if ((db[9 + offset + i] >> 4) == 1) | ||||
4729 | newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14); | ||||
4730 | break; | ||||
4731 | } | ||||
4732 | |||||
4733 | if (newflag != 0) { | ||||
4734 | newmode = drm_display_mode_from_vic_index(connector, | ||||
4735 | video_db, | ||||
4736 | video_len, | ||||
4737 | vic_index); | ||||
4738 | |||||
4739 | if (newmode) { | ||||
4740 | newmode->flags |= newflag; | ||||
4741 | drm_mode_probed_add(connector, newmode); | ||||
4742 | modes++; | ||||
4743 | } | ||||
4744 | } | ||||
4745 | |||||
4746 | if (detail_present) | ||||
4747 | i++; | ||||
4748 | } | ||||
4749 | |||||
4750 | out: | ||||
4751 | if (modes > 0) | ||||
4752 | info->has_hdmi_infoframe = true1; | ||||
4753 | return modes; | ||||
4754 | } | ||||
4755 | |||||
4756 | static int | ||||
4757 | cea_revision(const u8 *cea) | ||||
4758 | { | ||||
4759 | /* | ||||
4760 | * FIXME is this correct for the DispID variant? | ||||
4761 | * The DispID spec doesn't really specify whether | ||||
4762 | * this is the revision of the CEA extension or | ||||
4763 | * the DispID CEA data block. And the only value | ||||
4764 | * given as an example is 0. | ||||
4765 | */ | ||||
4766 | return cea[1]; | ||||
4767 | } | ||||
4768 | |||||
4769 | /* | ||||
4770 | * CTA Data Block iterator. | ||||
4771 | * | ||||
4772 | * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID | ||||
4773 | * CTA Data Blocks. | ||||
4774 | * | ||||
4775 | * struct cea_db *db: | ||||
4776 | * struct cea_db_iter iter; | ||||
4777 | * | ||||
4778 | * cea_db_iter_edid_begin(edid, &iter); | ||||
4779 | * cea_db_iter_for_each(db, &iter) { | ||||
4780 | * // do stuff with db | ||||
4781 | * } | ||||
4782 | * cea_db_iter_end(&iter); | ||||
4783 | */ | ||||
4784 | struct cea_db_iter { | ||||
4785 | struct drm_edid_iter edid_iter; | ||||
4786 | struct displayid_iter displayid_iter; | ||||
4787 | |||||
4788 | /* Current Data Block Collection. */ | ||||
4789 | const u8 *collection; | ||||
4790 | |||||
4791 | /* Current Data Block index in current collection. */ | ||||
4792 | int index; | ||||
4793 | |||||
4794 | /* End index in current collection. */ | ||||
4795 | int end; | ||||
4796 | }; | ||||
4797 | |||||
4798 | /* CTA-861-H section 7.4 CTA Data BLock Collection */ | ||||
4799 | struct cea_db { | ||||
4800 | u8 tag_length; | ||||
4801 | u8 data[]; | ||||
4802 | } __packed__attribute__((__packed__)); | ||||
4803 | |||||
4804 | static int cea_db_tag(const struct cea_db *db) | ||||
4805 | { | ||||
4806 | return db->tag_length >> 5; | ||||
4807 | } | ||||
4808 | |||||
4809 | static int cea_db_payload_len(const void *_db) | ||||
4810 | { | ||||
4811 | /* FIXME: Transition to passing struct cea_db * everywhere. */ | ||||
4812 | const struct cea_db *db = _db; | ||||
4813 | |||||
4814 | return db->tag_length & 0x1f; | ||||
4815 | } | ||||
4816 | |||||
4817 | static const void *cea_db_data(const struct cea_db *db) | ||||
4818 | { | ||||
4819 | return db->data; | ||||
4820 | } | ||||
4821 | |||||
4822 | static bool_Bool cea_db_is_extended_tag(const struct cea_db *db, int tag) | ||||
4823 | { | ||||
4824 | return cea_db_tag(db) == CTA_DB_EXTENDED_TAG7 && | ||||
4825 | cea_db_payload_len(db) >= 1 && | ||||
4826 | db->data[0] == tag; | ||||
4827 | } | ||||
4828 | |||||
4829 | static bool_Bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) | ||||
4830 | { | ||||
4831 | const u8 *data = cea_db_data(db); | ||||
4832 | |||||
4833 | return cea_db_tag(db) == CTA_DB_VENDOR3 && | ||||
4834 | cea_db_payload_len(db) >= 3 && | ||||
4835 | oui(data[2], data[1], data[0]) == vendor_oui; | ||||
4836 | } | ||||
4837 | |||||
4838 | static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, | ||||
4839 | struct cea_db_iter *iter) | ||||
4840 | { | ||||
4841 | memset(iter, 0, sizeof(*iter))__builtin_memset((iter), (0), (sizeof(*iter))); | ||||
4842 | |||||
4843 | drm_edid_iter_begin(drm_edid, &iter->edid_iter); | ||||
4844 | displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); | ||||
4845 | } | ||||
4846 | |||||
4847 | static const struct cea_db * | ||||
4848 | __cea_db_iter_current_block(const struct cea_db_iter *iter) | ||||
4849 | { | ||||
4850 | const struct cea_db *db; | ||||
4851 | |||||
4852 | if (!iter->collection) | ||||
4853 | return NULL((void *)0); | ||||
4854 | |||||
4855 | db = (const struct cea_db *)&iter->collection[iter->index]; | ||||
4856 | |||||
4857 | if (iter->index + sizeof(*db) <= iter->end && | ||||
4858 | iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) | ||||
4859 | return db; | ||||
4860 | |||||
4861 | return NULL((void *)0); | ||||
4862 | } | ||||
4863 | |||||
4864 | /* | ||||
4865 | * References: | ||||
4866 | * - CTA-861-H section 7.3.3 CTA Extension Version 3 | ||||
4867 | */ | ||||
4868 | static int cea_db_collection_size(const u8 *cta) | ||||
4869 | { | ||||
4870 | u8 d = cta[2]; | ||||
4871 | |||||
4872 | if (d < 4 || d > 127) | ||||
4873 | return 0; | ||||
4874 | |||||
4875 | return d - 4; | ||||
4876 | } | ||||
4877 | |||||
4878 | /* | ||||
4879 | * References: | ||||
4880 | * - VESA E-EDID v1.4 | ||||
4881 | * - CTA-861-H section 7.3.3 CTA Extension Version 3 | ||||
4882 | */ | ||||
4883 | static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) | ||||
4884 | { | ||||
4885 | const u8 *ext; | ||||
4886 | |||||
4887 | drm_edid_iter_for_each(ext, &iter->edid_iter)while (((ext) = __drm_edid_iter_next(&iter->edid_iter) )) { | ||||
4888 | int size; | ||||
4889 | |||||
4890 | /* Only support CTA Extension revision 3+ */ | ||||
4891 | if (ext[0] != CEA_EXT0x02 || cea_revision(ext) < 3) | ||||
4892 | continue; | ||||
4893 | |||||
4894 | size = cea_db_collection_size(ext); | ||||
4895 | if (!size) | ||||
4896 | continue; | ||||
4897 | |||||
4898 | iter->index = 4; | ||||
4899 | iter->end = iter->index + size; | ||||
4900 | |||||
4901 | return ext; | ||||
4902 | } | ||||
4903 | |||||
4904 | return NULL((void *)0); | ||||
4905 | } | ||||
4906 | |||||
4907 | /* | ||||
4908 | * References: | ||||
4909 | * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block | ||||
4910 | * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block | ||||
4911 | * | ||||
4912 | * Note that the above do not specify any connection between DisplayID Data | ||||
4913 | * Block revision and CTA Extension versions. | ||||
4914 | */ | ||||
4915 | static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) | ||||
4916 | { | ||||
4917 | const struct displayid_block *block; | ||||
4918 | |||||
4919 | displayid_iter_for_each(block, &iter->displayid_iter)while (((block) = __displayid_iter_next(&iter->displayid_iter ))) { | ||||
4920 | if (block->tag != DATA_BLOCK_CTA0x81) | ||||
4921 | continue; | ||||
4922 | |||||
4923 | /* | ||||
4924 | * The displayid iterator has already verified the block bounds | ||||
4925 | * in displayid_iter_block(). | ||||
4926 | */ | ||||
4927 | iter->index = sizeof(*block); | ||||
4928 | iter->end = iter->index + block->num_bytes; | ||||
4929 | |||||
4930 | return block; | ||||
4931 | } | ||||
4932 | |||||
4933 | return NULL((void *)0); | ||||
4934 | } | ||||
4935 | |||||
4936 | static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) | ||||
4937 | { | ||||
4938 | const struct cea_db *db; | ||||
4939 | |||||
4940 | if (iter->collection) { | ||||
4941 | /* Current collection should always be valid. */ | ||||
4942 | db = __cea_db_iter_current_block(iter); | ||||
4943 | if (WARN_ON(!db)({ int __ret = !!(!db); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!db", "/usr/src/sys/dev/pci/drm/drm_edid.c", 4943); __builtin_expect (!!(__ret), 0); })) { | ||||
4944 | iter->collection = NULL((void *)0); | ||||
4945 | return NULL((void *)0); | ||||
4946 | } | ||||
4947 | |||||
4948 | /* Next block in CTA Data Block Collection */ | ||||
4949 | iter->index += sizeof(*db) + cea_db_payload_len(db); | ||||
4950 | |||||
4951 | db = __cea_db_iter_current_block(iter); | ||||
4952 | if (db) | ||||
4953 | return db; | ||||
4954 | } | ||||
4955 | |||||
4956 | for (;;) { | ||||
4957 | /* | ||||
4958 | * Find the next CTA Data Block Collection. First iterate all | ||||
4959 | * the EDID CTA Extensions, then all the DisplayID CTA blocks. | ||||
4960 | * | ||||
4961 | * Per DisplayID v1.3 Appendix B: DisplayID as an EDID | ||||
4962 | * Extension, it's recommended that DisplayID extensions are | ||||
4963 | * exposed after all of the CTA Extensions. | ||||
4964 | */ | ||||
4965 | iter->collection = __cea_db_iter_edid_next(iter); | ||||
4966 | if (!iter->collection) | ||||
4967 | iter->collection = __cea_db_iter_displayid_next(iter); | ||||
4968 | |||||
4969 | if (!iter->collection) | ||||
4970 | return NULL((void *)0); | ||||
4971 | |||||
4972 | db = __cea_db_iter_current_block(iter); | ||||
4973 | if (db) | ||||
4974 | return db; | ||||
4975 | } | ||||
4976 | } | ||||
4977 | |||||
4978 | #define cea_db_iter_for_each(__db, __iter)while (((__db) = __cea_db_iter_next(__iter))) \ | ||||
4979 | while (((__db) = __cea_db_iter_next(__iter))) | ||||
4980 | |||||
4981 | static void cea_db_iter_end(struct cea_db_iter *iter) | ||||
4982 | { | ||||
4983 | displayid_iter_end(&iter->displayid_iter); | ||||
4984 | drm_edid_iter_end(&iter->edid_iter); | ||||
4985 | |||||
4986 | memset(iter, 0, sizeof(*iter))__builtin_memset((iter), (0), (sizeof(*iter))); | ||||
4987 | } | ||||
4988 | |||||
4989 | static bool_Bool cea_db_is_hdmi_vsdb(const struct cea_db *db) | ||||
4990 | { | ||||
4991 | return cea_db_is_vendor(db, HDMI_IEEE_OUI0x000c03) && | ||||
4992 | cea_db_payload_len(db) >= 5; | ||||
4993 | } | ||||
4994 | |||||
4995 | static bool_Bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) | ||||
4996 | { | ||||
4997 | return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI0xc45dd8) && | ||||
4998 | cea_db_payload_len(db) >= 7; | ||||
4999 | } | ||||
5000 | |||||
5001 | static bool_Bool cea_db_is_hdmi_forum_eeodb(const void *db) | ||||
5002 | { | ||||
5003 | return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB0x78) && | ||||
5004 | cea_db_payload_len(db) >= 2; | ||||
5005 | } | ||||
5006 | |||||
5007 | static bool_Bool cea_db_is_microsoft_vsdb(const struct cea_db *db) | ||||
5008 | { | ||||
5009 | return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI0xca125c) && | ||||
5010 | cea_db_payload_len(db) == 21; | ||||
5011 | } | ||||
5012 | |||||
5013 | static bool_Bool cea_db_is_vcdb(const struct cea_db *db) | ||||
5014 | { | ||||
5015 | return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP0) && | ||||
5016 | cea_db_payload_len(db) == 2; | ||||
5017 | } | ||||
5018 | |||||
5019 | static bool_Bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) | ||||
5020 | { | ||||
5021 | return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB0x79) && | ||||
5022 | cea_db_payload_len(db) >= 7; | ||||
5023 | } | ||||
5024 | |||||
5025 | static bool_Bool cea_db_is_y420cmdb(const struct cea_db *db) | ||||
5026 | { | ||||
5027 | return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP15); | ||||
5028 | } | ||||
5029 | |||||
5030 | static bool_Bool cea_db_is_y420vdb(const struct cea_db *db) | ||||
5031 | { | ||||
5032 | return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA14); | ||||
5033 | } | ||||
5034 | |||||
5035 | static bool_Bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) | ||||
5036 | { | ||||
5037 | return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA6) && | ||||
5038 | cea_db_payload_len(db) >= 3; | ||||
5039 | } | ||||
5040 | |||||
5041 | /* | ||||
5042 | * Get the HF-EEODB override extension block count from EDID. | ||||
5043 | * | ||||
5044 | * The passed in EDID may be partially read, as long as it has at least two | ||||
5045 | * blocks (base block and one extension block) if EDID extension count is > 0. | ||||
5046 | * | ||||
5047 | * Note that this is *not* how you should parse CTA Data Blocks in general; this | ||||
5048 | * is only to handle partially read EDIDs. Normally, use the CTA Data Block | ||||
5049 | * iterators instead. | ||||
5050 | * | ||||
5051 | * References: | ||||
5052 | * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block | ||||
5053 | */ | ||||
5054 | static int edid_hfeeodb_extension_block_count(const struct edid *edid) | ||||
5055 | { | ||||
5056 | const u8 *cta; | ||||
5057 | |||||
5058 | /* No extensions according to base block, no HF-EEODB. */ | ||||
5059 | if (!edid_extension_block_count(edid)) | ||||
5060 | return 0; | ||||
5061 | |||||
5062 | /* HF-EEODB is always in the first EDID extension block only */ | ||||
5063 | cta = edid_extension_block_data(edid, 0); | ||||
5064 | if (edid_block_tag(cta) != CEA_EXT0x02 || cea_revision(cta) < 3) | ||||
5065 | return 0; | ||||
5066 | |||||
5067 | /* Need to have the data block collection, and at least 3 bytes. */ | ||||
5068 | if (cea_db_collection_size(cta) < 3) | ||||
5069 | return 0; | ||||
5070 | |||||
5071 | /* | ||||
5072 | * Sinks that include the HF-EEODB in their E-EDID shall include one and | ||||
5073 | * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 | ||||
5074 | * through 6 of Block 1 of the E-EDID. | ||||
5075 | */ | ||||
5076 | if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) | ||||
5077 | return 0; | ||||
5078 | |||||
5079 | return cta[4 + 2]; | ||||
5080 | } | ||||
5081 | |||||
5082 | static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, | ||||
5083 | const u8 *db) | ||||
5084 | { | ||||
5085 | struct drm_display_info *info = &connector->display_info; | ||||
5086 | struct drm_hdmi_info *hdmi = &info->hdmi; | ||||
5087 | u8 map_len = cea_db_payload_len(db) - 1; | ||||
5088 | u8 count; | ||||
5089 | u64 map = 0; | ||||
5090 | |||||
5091 | if (map_len == 0) { | ||||
5092 | /* All CEA modes support ycbcr420 sampling also.*/ | ||||
5093 | hdmi->y420_cmdb_map = U64_MAX0xffffffffffffffffULL; | ||||
5094 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR420(1<<3); | ||||
5095 | return; | ||||
5096 | } | ||||
5097 | |||||
5098 | /* | ||||
5099 | * This map indicates which of the existing CEA block modes | ||||
5100 | * from VDB can support YCBCR420 output too. So if bit=0 is | ||||
5101 | * set, first mode from VDB can support YCBCR420 output too. | ||||
5102 | * We will parse and keep this map, before parsing VDB itself | ||||
5103 | * to avoid going through the same block again and again. | ||||
5104 | * | ||||
5105 | * Spec is not clear about max possible size of this block. | ||||
5106 | * Clamping max bitmap block size at 8 bytes. Every byte can | ||||
5107 | * address 8 CEA modes, in this way this map can address | ||||
5108 | * 8*8 = first 64 SVDs. | ||||
5109 | */ | ||||
5110 | if (WARN_ON_ONCE(map_len > 8)({ static int __warned; int __ret = !!(map_len > 8); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "map_len > 8", "/usr/src/sys/dev/pci/drm/drm_edid.c", 5110 ); __warned = 1; } __builtin_expect(!!(__ret), 0); })) | ||||
5111 | map_len = 8; | ||||
5112 | |||||
5113 | for (count = 0; count < map_len; count++) | ||||
5114 | map |= (u64)db[2 + count] << (8 * count); | ||||
5115 | |||||
5116 | if (map) | ||||
5117 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR420(1<<3); | ||||
5118 | |||||
5119 | hdmi->y420_cmdb_map = map; | ||||
5120 | } | ||||
5121 | |||||
5122 | static int add_cea_modes(struct drm_connector *connector, | ||||
5123 | const struct drm_edid *drm_edid) | ||||
5124 | { | ||||
5125 | const struct cea_db *db; | ||||
5126 | struct cea_db_iter iter; | ||||
5127 | const u8 *hdmi = NULL((void *)0), *video = NULL((void *)0); | ||||
5128 | u8 hdmi_len = 0, video_len = 0; | ||||
5129 | int modes = 0; | ||||
5130 | |||||
5131 | cea_db_iter_edid_begin(drm_edid, &iter); | ||||
5132 | cea_db_iter_for_each(db, &iter)while (((db) = __cea_db_iter_next(&iter))) { | ||||
5133 | if (cea_db_tag(db) == CTA_DB_VIDEO2) { | ||||
5134 | video = cea_db_data(db); | ||||
5135 | video_len = cea_db_payload_len(db); | ||||
5136 | modes += do_cea_modes(connector, video, video_len); | ||||
5137 | } else if (cea_db_is_hdmi_vsdb(db)) { | ||||
5138 | /* FIXME: Switch to use cea_db_data() */ | ||||
5139 | hdmi = (const u8 *)db; | ||||
5140 | hdmi_len = cea_db_payload_len(db); | ||||
5141 | } else if (cea_db_is_y420vdb(db)) { | ||||
5142 | const u8 *vdb420 = cea_db_data(db) + 1; | ||||
5143 | |||||
5144 | /* Add 4:2:0(only) modes present in EDID */ | ||||
5145 | modes += do_y420vdb_modes(connector, vdb420, | ||||
5146 | cea_db_payload_len(db) - 1); | ||||
5147 | } | ||||
5148 | } | ||||
5149 | cea_db_iter_end(&iter); | ||||
5150 | |||||
5151 | /* | ||||
5152 | * We parse the HDMI VSDB after having added the cea modes as we will be | ||||
5153 | * patching their flags when the sink supports stereo 3D. | ||||
5154 | */ | ||||
5155 | if (hdmi) | ||||
5156 | modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, | ||||
5157 | video, video_len); | ||||
5158 | |||||
5159 | return modes; | ||||
5160 | } | ||||
5161 | |||||
5162 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) | ||||
5163 | { | ||||
5164 | const struct drm_display_mode *cea_mode; | ||||
5165 | int clock1, clock2, clock; | ||||
5166 | u8 vic; | ||||
5167 | const char *type; | ||||
5168 | |||||
5169 | /* | ||||
5170 | * allow 5kHz clock difference either way to account for | ||||
5171 | * the 10kHz clock resolution limit of detailed timings. | ||||
5172 | */ | ||||
5173 | vic = drm_match_cea_mode_clock_tolerance(mode, 5); | ||||
5174 | if (drm_valid_cea_vic(vic)) { | ||||
5175 | type = "CEA"; | ||||
5176 | cea_mode = cea_mode_for_vic(vic); | ||||
5177 | clock1 = cea_mode->clock; | ||||
5178 | clock2 = cea_mode_alternate_clock(cea_mode); | ||||
5179 | } else { | ||||
5180 | vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); | ||||
5181 | if (drm_valid_hdmi_vic(vic)) { | ||||
5182 | type = "HDMI"; | ||||
5183 | cea_mode = &edid_4k_modes[vic]; | ||||
5184 | clock1 = cea_mode->clock; | ||||
5185 | clock2 = hdmi_mode_alternate_clock(cea_mode); | ||||
5186 | } else { | ||||
5187 | return; | ||||
5188 | } | ||||
5189 | } | ||||
5190 | |||||
5191 | /* pick whichever is closest */ | ||||
5192 | if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) | ||||
5193 | clock = clock1; | ||||
5194 | else | ||||
5195 | clock = clock2; | ||||
5196 | |||||
5197 | if (mode->clock == clock) | ||||
5198 | return; | ||||
5199 | |||||
5200 | DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",___drm_dbg(((void *)0), DRM_UT_CORE, "detailed mode matches %s VIC %d, adjusting clock %d -> %d\n" , type, vic, mode->clock, clock) | ||||
5201 | type, vic, mode->clock, clock)___drm_dbg(((void *)0), DRM_UT_CORE, "detailed mode matches %s VIC %d, adjusting clock %d -> %d\n" , type, vic, mode->clock, clock); | ||||
5202 | mode->clock = clock; | ||||
5203 | } | ||||
5204 | |||||
5205 | static void drm_calculate_luminance_range(struct drm_connector *connector) | ||||
5206 | { | ||||
5207 | struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; | ||||
5208 | struct drm_luminance_range_info *luminance_range = | ||||
5209 | &connector->display_info.luminance_range; | ||||
5210 | static const u8 pre_computed_values[] = { | ||||
5211 | 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, | ||||
5212 | 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 | ||||
5213 | }; | ||||
5214 | u32 max_avg, min_cll, max, min, q, r; | ||||
5215 | |||||
5216 | if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)(1UL << (HDMI_STATIC_METADATA_TYPE1)))) | ||||
5217 | return; | ||||
5218 | |||||
5219 | max_avg = hdr_metadata->max_fall; | ||||
5220 | min_cll = hdr_metadata->min_cll; | ||||
5221 | |||||
5222 | /* | ||||
5223 | * From the specification (CTA-861-G), for calculating the maximum | ||||
5224 | * luminance we need to use: | ||||
5225 | * Luminance = 50*2**(CV/32) | ||||
5226 | * Where CV is a one-byte value. | ||||
5227 | * For calculating this expression we may need float point precision; | ||||
5228 | * to avoid this complexity level, we take advantage that CV is divided | ||||
5229 | * by a constant. From the Euclids division algorithm, we know that CV | ||||
5230 | * can be written as: CV = 32*q + r. Next, we replace CV in the | ||||
5231 | * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just | ||||
5232 | * need to pre-compute the value of r/32. For pre-computing the values | ||||
5233 | * We just used the following Ruby line: | ||||
5234 | * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} | ||||
5235 | * The results of the above expressions can be verified at | ||||
5236 | * pre_computed_values. | ||||
5237 | */ | ||||
5238 | q = max_avg >> 5; | ||||
5239 | r = max_avg % 32; | ||||
5240 | max = (1 << q) * pre_computed_values[r]; | ||||
5241 | |||||
5242 | /* min luminance: maxLum * (CV/255)^2 / 100 */ | ||||
5243 | q = DIV_ROUND_CLOSEST(min_cll, 255)(((min_cll) + ((255) / 2)) / (255)); | ||||
5244 | min = max * DIV_ROUND_CLOSEST((q * q), 100)((((q * q)) + ((100) / 2)) / (100)); | ||||
5245 | |||||
5246 | luminance_range->min_luminance = min; | ||||
5247 | luminance_range->max_luminance = max; | ||||
5248 | } | ||||
5249 | |||||
5250 | static uint8_t eotf_supported(const u8 *edid_ext) | ||||
5251 | { | ||||
5252 | return edid_ext[2] & | ||||
5253 | (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR)(1UL << (HDMI_EOTF_TRADITIONAL_GAMMA_SDR)) | | ||||
5254 | BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR)(1UL << (HDMI_EOTF_TRADITIONAL_GAMMA_HDR)) | | ||||
5255 | BIT(HDMI_EOTF_SMPTE_ST2084)(1UL << (HDMI_EOTF_SMPTE_ST2084)) | | ||||
5256 | BIT(HDMI_EOTF_BT_2100_HLG)(1UL << (HDMI_EOTF_BT_2100_HLG))); | ||||
5257 | } | ||||
5258 | |||||
5259 | static uint8_t hdr_metadata_type(const u8 *edid_ext) | ||||
5260 | { | ||||
5261 | return edid_ext[3] & | ||||
5262 | BIT(HDMI_STATIC_METADATA_TYPE1)(1UL << (HDMI_STATIC_METADATA_TYPE1)); | ||||
5263 | } | ||||
5264 | |||||
5265 | static void | ||||
5266 | drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) | ||||
5267 | { | ||||
5268 | u16 len; | ||||
5269 | |||||
5270 | len = cea_db_payload_len(db); | ||||
5271 | |||||
5272 | connector->hdr_sink_metadata.hdmi_type1.eotf = | ||||
5273 | eotf_supported(db); | ||||
5274 | connector->hdr_sink_metadata.hdmi_type1.metadata_type = | ||||
5275 | hdr_metadata_type(db); | ||||
5276 | |||||
5277 | if (len >= 4) | ||||
5278 | connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; | ||||
5279 | if (len >= 5) | ||||
5280 | connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; | ||||
5281 | if (len >= 6) { | ||||
5282 | connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; | ||||
5283 | |||||
5284 | /* Calculate only when all values are available */ | ||||
5285 | drm_calculate_luminance_range(connector); | ||||
5286 | } | ||||
5287 | } | ||||
5288 | |||||
5289 | static void | ||||
5290 | drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) | ||||
5291 | { | ||||
5292 | u8 len = cea_db_payload_len(db); | ||||
5293 | |||||
5294 | if (len >= 6 && (db[6] & (1 << 7))) | ||||
5295 | connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE5] |= DRM_ELD_SUPPORTS_AI(1 << 1); | ||||
5296 | if (len >= 8) { | ||||
5297 | connector->latency_present[0] = db[8] >> 7; | ||||
5298 | connector->latency_present[1] = (db[8] >> 6) & 1; | ||||
5299 | } | ||||
5300 | if (len >= 9) | ||||
5301 | connector->video_latency[0] = db[9]; | ||||
5302 | if (len >= 10) | ||||
5303 | connector->audio_latency[0] = db[10]; | ||||
5304 | if (len >= 11) | ||||
5305 | connector->video_latency[1] = db[11]; | ||||
5306 | if (len >= 12) | ||||
5307 | connector->audio_latency[1] = db[12]; | ||||
5308 | |||||
5309 | DRM_DEBUG_KMS("HDMI: latency present %d %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]) | ||||
5310 | "video latency %d %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]) | ||||
5311 | "audio latency %d %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]) | ||||
5312 | connector->latency_present[0],___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]) | ||||
5313 | connector->latency_present[1],___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]) | ||||
5314 | connector->video_latency[0],___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]) | ||||
5315 | connector->video_latency[1],___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]) | ||||
5316 | connector->audio_latency[0],___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]) | ||||
5317 | connector->audio_latency[1])___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector-> latency_present[0], connector->latency_present[1], connector ->video_latency[0], connector->video_latency[1], connector ->audio_latency[0], connector->audio_latency[1]); | ||||
5318 | } | ||||
5319 | |||||
5320 | static void | ||||
5321 | monitor_name(const struct detailed_timing *timing, void *data) | ||||
5322 | { | ||||
5323 | const char **res = data; | ||||
5324 | |||||
5325 | if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME0xfc)) | ||||
5326 | return; | ||||
5327 | |||||
5328 | *res = timing->data.other_data.data.str.str; | ||||
5329 | } | ||||
5330 | |||||
5331 | static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) | ||||
5332 | { | ||||
5333 | const char *edid_name = NULL((void *)0); | ||||
5334 | int mnl; | ||||
5335 | |||||
5336 | if (!drm_edid || !name) | ||||
5337 | return 0; | ||||
5338 | |||||
5339 | drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); | ||||
5340 | for (mnl = 0; edid_name && mnl < 13; mnl++) { | ||||
5341 | if (edid_name[mnl] == 0x0a) | ||||
5342 | break; | ||||
5343 | |||||
5344 | name[mnl] = edid_name[mnl]; | ||||
5345 | } | ||||
5346 | |||||
5347 | return mnl; | ||||
5348 | } | ||||
5349 | |||||
5350 | /** | ||||
5351 | * drm_edid_get_monitor_name - fetch the monitor name from the edid | ||||
5352 | * @edid: monitor EDID information | ||||
5353 | * @name: pointer to a character array to hold the name of the monitor | ||||
5354 | * @bufsize: The size of the name buffer (should be at least 14 chars.) | ||||
5355 | * | ||||
5356 | */ | ||||
5357 | void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) | ||||
5358 | { | ||||
5359 | int name_length = 0; | ||||
5360 | |||||
5361 | if (bufsize <= 0) | ||||
5362 | return; | ||||
5363 | |||||
5364 | if (edid) { | ||||
5365 | char buf[13]; | ||||
5366 | struct drm_edid drm_edid = { | ||||
5367 | .edid = edid, | ||||
5368 | .size = edid_size(edid), | ||||
5369 | }; | ||||
5370 | |||||
5371 | name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1)(((get_monitor_name(&drm_edid, buf))<(bufsize - 1))?(get_monitor_name (&drm_edid, buf)):(bufsize - 1)); | ||||
5372 | memcpy(name, buf, name_length)__builtin_memcpy((name), (buf), (name_length)); | ||||
5373 | } | ||||
5374 | |||||
5375 | name[name_length] = '\0'; | ||||
5376 | } | ||||
5377 | EXPORT_SYMBOL(drm_edid_get_monitor_name); | ||||
5378 | |||||
5379 | static void clear_eld(struct drm_connector *connector) | ||||
5380 | { | ||||
5381 | memset(connector->eld, 0, sizeof(connector->eld))__builtin_memset((connector->eld), (0), (sizeof(connector-> eld))); | ||||
5382 | |||||
5383 | connector->latency_present[0] = false0; | ||||
5384 | connector->latency_present[1] = false0; | ||||
5385 | connector->video_latency[0] = 0; | ||||
5386 | connector->audio_latency[0] = 0; | ||||
5387 | connector->video_latency[1] = 0; | ||||
5388 | connector->audio_latency[1] = 0; | ||||
5389 | } | ||||
5390 | |||||
5391 | /* | ||||
5392 | * drm_edid_to_eld - build ELD from EDID | ||||
5393 | * @connector: connector corresponding to the HDMI/DP sink | ||||
5394 | * @drm_edid: EDID to parse | ||||
5395 | * | ||||
5396 | * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The | ||||
5397 | * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. | ||||
5398 | */ | ||||
5399 | static void drm_edid_to_eld(struct drm_connector *connector, | ||||
5400 | const struct drm_edid *drm_edid) | ||||
5401 | { | ||||
5402 | const struct drm_display_info *info = &connector->display_info; | ||||
5403 | const struct cea_db *db; | ||||
5404 | struct cea_db_iter iter; | ||||
5405 | uint8_t *eld = connector->eld; | ||||
5406 | int total_sad_count = 0; | ||||
5407 | int mnl; | ||||
5408 | |||||
5409 | clear_eld(connector); | ||||
5410 | |||||
5411 | if (!drm_edid) | ||||
5412 | return; | ||||
5413 | |||||
5414 | mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING20]); | ||||
5415 | DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING])___drm_dbg(((void *)0), DRM_UT_KMS, "ELD monitor %s\n", & eld[20]); | ||||
5416 | |||||
5417 | eld[DRM_ELD_CEA_EDID_VER_MNL4] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT5; | ||||
5418 | eld[DRM_ELD_CEA_EDID_VER_MNL4] |= mnl; | ||||
5419 | |||||
5420 | eld[DRM_ELD_VER0] = DRM_ELD_VER_CEA861D(2 << 3); | ||||
5421 | |||||
5422 | eld[DRM_ELD_MANUFACTURER_NAME016] = drm_edid->edid->mfg_id[0]; | ||||
5423 | eld[DRM_ELD_MANUFACTURER_NAME117] = drm_edid->edid->mfg_id[1]; | ||||
5424 | eld[DRM_ELD_PRODUCT_CODE018] = drm_edid->edid->prod_code[0]; | ||||
5425 | eld[DRM_ELD_PRODUCT_CODE119] = drm_edid->edid->prod_code[1]; | ||||
5426 | |||||
5427 | cea_db_iter_edid_begin(drm_edid, &iter); | ||||
5428 | cea_db_iter_for_each(db, &iter)while (((db) = __cea_db_iter_next(&iter))) { | ||||
5429 | const u8 *data = cea_db_data(db); | ||||
5430 | int len = cea_db_payload_len(db); | ||||
5431 | int sad_count; | ||||
5432 | |||||
5433 | switch (cea_db_tag(db)) { | ||||
5434 | case CTA_DB_AUDIO1: | ||||
5435 | /* Audio Data Block, contains SADs */ | ||||
5436 | sad_count = min(len / 3, 15 - total_sad_count)(((len / 3)<(15 - total_sad_count))?(len / 3):(15 - total_sad_count )); | ||||
5437 | if (sad_count >= 1) | ||||
5438 | memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],__builtin_memcpy((&eld[(20 + (mnl) + 3 * (total_sad_count ))]), (data), (sad_count * 3)) | ||||
5439 | data, sad_count * 3)__builtin_memcpy((&eld[(20 + (mnl) + 3 * (total_sad_count ))]), (data), (sad_count * 3)); | ||||
5440 | total_sad_count += sad_count; | ||||
5441 | break; | ||||
5442 | case CTA_DB_SPEAKER4: | ||||
5443 | /* Speaker Allocation Data Block */ | ||||
5444 | if (len >= 1) | ||||
5445 | eld[DRM_ELD_SPEAKER7] = data[0]; | ||||
5446 | break; | ||||
5447 | case CTA_DB_VENDOR3: | ||||
5448 | /* HDMI Vendor-Specific Data Block */ | ||||
5449 | if (cea_db_is_hdmi_vsdb(db)) | ||||
5450 | drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); | ||||
5451 | break; | ||||
5452 | default: | ||||
5453 | break; | ||||
5454 | } | ||||
5455 | } | ||||
5456 | cea_db_iter_end(&iter); | ||||
5457 | |||||
5458 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE5] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT4; | ||||
5459 | |||||
5460 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort10 || | ||||
5461 | connector->connector_type == DRM_MODE_CONNECTOR_eDP14) | ||||
5462 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE5] |= DRM_ELD_CONN_TYPE_DP(1 << 2); | ||||
5463 | else | ||||
5464 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE5] |= DRM_ELD_CONN_TYPE_HDMI(0 << 2); | ||||
5465 | |||||
5466 | eld[DRM_ELD_BASELINE_ELD_LEN2] = | ||||
5467 | DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4)(((drm_eld_calc_baseline_block_size(eld)) + ((4) - 1)) / (4)); | ||||
5468 | |||||
5469 | DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "ELD size %d, SAD count %d\n" , drm_eld_size(eld), total_sad_count) | ||||
5470 | drm_eld_size(eld), total_sad_count)___drm_dbg(((void *)0), DRM_UT_KMS, "ELD size %d, SAD count %d\n" , drm_eld_size(eld), total_sad_count); | ||||
5471 | } | ||||
5472 | |||||
5473 | static int _drm_edid_to_sad(const struct drm_edid *drm_edid, | ||||
5474 | struct cea_sad **sads) | ||||
5475 | { | ||||
5476 | const struct cea_db *db; | ||||
5477 | struct cea_db_iter iter; | ||||
5478 | int count = 0; | ||||
5479 | |||||
5480 | cea_db_iter_edid_begin(drm_edid, &iter); | ||||
5481 | cea_db_iter_for_each(db, &iter)while (((db) = __cea_db_iter_next(&iter))) { | ||||
5482 | if (cea_db_tag(db) == CTA_DB_AUDIO1) { | ||||
5483 | int j; | ||||
5484 | |||||
5485 | count = cea_db_payload_len(db) / 3; /* SAD is 3B */ | ||||
5486 | *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL(0x0001 | 0x0004)); | ||||
5487 | if (!*sads) | ||||
5488 | return -ENOMEM12; | ||||
5489 | for (j = 0; j < count; j++) { | ||||
5490 | const u8 *sad = &db->data[j * 3]; | ||||
5491 | |||||
5492 | (*sads)[j].format = (sad[0] & 0x78) >> 3; | ||||
5493 | (*sads)[j].channels = sad[0] & 0x7; | ||||
5494 | (*sads)[j].freq = sad[1] & 0x7F; | ||||
5495 | (*sads)[j].byte2 = sad[2]; | ||||
5496 | } | ||||
5497 | break; | ||||
5498 | } | ||||
5499 | } | ||||
5500 | cea_db_iter_end(&iter); | ||||
5501 | |||||
5502 | DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count)___drm_dbg(((void *)0), DRM_UT_KMS, "Found %d Short Audio Descriptors\n" , count); | ||||
5503 | |||||
5504 | return count; | ||||
5505 | } | ||||
5506 | |||||
5507 | /** | ||||
5508 | * drm_edid_to_sad - extracts SADs from EDID | ||||
5509 | * @edid: EDID to parse | ||||
5510 | * @sads: pointer that will be set to the extracted SADs | ||||
5511 | * | ||||
5512 | * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. | ||||
5513 | * | ||||
5514 | * Note: The returned pointer needs to be freed using kfree(). | ||||
5515 | * | ||||
5516 | * Return: The number of found SADs or negative number on error. | ||||
5517 | */ | ||||
5518 | int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) | ||||
5519 | { | ||||
5520 | struct drm_edid drm_edid; | ||||
5521 | |||||
5522 | return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); | ||||
5523 | } | ||||
5524 | EXPORT_SYMBOL(drm_edid_to_sad); | ||||
5525 | |||||
5526 | static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, | ||||
5527 | u8 **sadb) | ||||
5528 | { | ||||
5529 | const struct cea_db *db; | ||||
5530 | struct cea_db_iter iter; | ||||
5531 | int count = 0; | ||||
5532 | |||||
5533 | cea_db_iter_edid_begin(drm_edid, &iter); | ||||
5534 | cea_db_iter_for_each(db, &iter)while (((db) = __cea_db_iter_next(&iter))) { | ||||
5535 | if (cea_db_tag(db) == CTA_DB_SPEAKER4 && | ||||
5536 | cea_db_payload_len(db) == 3) { | ||||
5537 | *sadb = kmemdup(db->data, cea_db_payload_len(db), | ||||
5538 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
5539 | if (!*sadb) | ||||
5540 | return -ENOMEM12; | ||||
5541 | count = cea_db_payload_len(db); | ||||
5542 | break; | ||||
5543 | } | ||||
5544 | } | ||||
5545 | cea_db_iter_end(&iter); | ||||
5546 | |||||
5547 | DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count)___drm_dbg(((void *)0), DRM_UT_KMS, "Found %d Speaker Allocation Data Blocks\n" , count); | ||||
5548 | |||||
5549 | return count; | ||||
5550 | } | ||||
5551 | |||||
5552 | /** | ||||
5553 | * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID | ||||
5554 | * @edid: EDID to parse | ||||
5555 | * @sadb: pointer to the speaker block | ||||
5556 | * | ||||
5557 | * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. | ||||
5558 | * | ||||
5559 | * Note: The returned pointer needs to be freed using kfree(). | ||||
5560 | * | ||||
5561 | * Return: The number of found Speaker Allocation Blocks or negative number on | ||||
5562 | * error. | ||||
5563 | */ | ||||
5564 | int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) | ||||
5565 | { | ||||
5566 | struct drm_edid drm_edid; | ||||
5567 | |||||
5568 | return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), | ||||
5569 | sadb); | ||||
5570 | } | ||||
5571 | EXPORT_SYMBOL(drm_edid_to_speaker_allocation); | ||||
5572 | |||||
5573 | /** | ||||
5574 | * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay | ||||
5575 | * @connector: connector associated with the HDMI/DP sink | ||||
5576 | * @mode: the display mode | ||||
5577 | * | ||||
5578 | * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if | ||||
5579 | * the sink doesn't support audio or video. | ||||
5580 | */ | ||||
5581 | int drm_av_sync_delay(struct drm_connector *connector, | ||||
5582 | const struct drm_display_mode *mode) | ||||
5583 | { | ||||
5584 | int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)); | ||||
5585 | int a, v; | ||||
5586 | |||||
5587 | if (!connector->latency_present[0]) | ||||
5588 | return 0; | ||||
5589 | if (!connector->latency_present[1]) | ||||
5590 | i = 0; | ||||
5591 | |||||
5592 | a = connector->audio_latency[i]; | ||||
5593 | v = connector->video_latency[i]; | ||||
5594 | |||||
5595 | /* | ||||
5596 | * HDMI/DP sink doesn't support audio or video? | ||||
5597 | */ | ||||
5598 | if (a == 255 || v == 255) | ||||
5599 | return 0; | ||||
5600 | |||||
5601 | /* | ||||
5602 | * Convert raw EDID values to millisecond. | ||||
5603 | * Treat unknown latency as 0ms. | ||||
5604 | */ | ||||
5605 | if (a) | ||||
5606 | a = min(2 * (a - 1), 500)(((2 * (a - 1))<(500))?(2 * (a - 1)):(500)); | ||||
5607 | if (v) | ||||
5608 | v = min(2 * (v - 1), 500)(((2 * (v - 1))<(500))?(2 * (v - 1)):(500)); | ||||
5609 | |||||
5610 | return max(v - a, 0)(((v - a)>(0))?(v - a):(0)); | ||||
5611 | } | ||||
5612 | EXPORT_SYMBOL(drm_av_sync_delay); | ||||
5613 | |||||
5614 | static bool_Bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) | ||||
5615 | { | ||||
5616 | const struct cea_db *db; | ||||
5617 | struct cea_db_iter iter; | ||||
5618 | bool_Bool hdmi = false0; | ||||
5619 | |||||
5620 | /* | ||||
5621 | * Because HDMI identifier is in Vendor Specific Block, | ||||
5622 | * search it from all data blocks of CEA extension. | ||||
5623 | */ | ||||
5624 | cea_db_iter_edid_begin(drm_edid, &iter); | ||||
5625 | cea_db_iter_for_each(db, &iter)while (((db) = __cea_db_iter_next(&iter))) { | ||||
5626 | if (cea_db_is_hdmi_vsdb(db)) { | ||||
5627 | hdmi = true1; | ||||
5628 | break; | ||||
5629 | } | ||||
5630 | } | ||||
5631 | cea_db_iter_end(&iter); | ||||
5632 | |||||
5633 | return hdmi; | ||||
5634 | } | ||||
5635 | |||||
5636 | /** | ||||
5637 | * drm_detect_hdmi_monitor - detect whether monitor is HDMI | ||||
5638 | * @edid: monitor EDID information | ||||
5639 | * | ||||
5640 | * Parse the CEA extension according to CEA-861-B. | ||||
5641 | * | ||||
5642 | * Drivers that have added the modes parsed from EDID to drm_display_info | ||||
5643 | * should use &drm_display_info.is_hdmi instead of calling this function. | ||||
5644 | * | ||||
5645 | * Return: True if the monitor is HDMI, false if not or unknown. | ||||
5646 | */ | ||||
5647 | bool_Bool drm_detect_hdmi_monitor(const struct edid *edid) | ||||
5648 | { | ||||
5649 | struct drm_edid drm_edid; | ||||
5650 | |||||
5651 | return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); | ||||
5652 | } | ||||
5653 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | ||||
5654 | |||||
5655 | static bool_Bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) | ||||
5656 | { | ||||
5657 | struct drm_edid_iter edid_iter; | ||||
5658 | const struct cea_db *db; | ||||
5659 | struct cea_db_iter iter; | ||||
5660 | const u8 *edid_ext; | ||||
5661 | bool_Bool has_audio = false0; | ||||
5662 | |||||
5663 | drm_edid_iter_begin(drm_edid, &edid_iter); | ||||
5664 | drm_edid_iter_for_each(edid_ext, &edid_iter)while (((edid_ext) = __drm_edid_iter_next(&edid_iter))) { | ||||
5665 | if (edid_ext[0] == CEA_EXT0x02) { | ||||
5666 | has_audio = edid_ext[3] & EDID_BASIC_AUDIO(1 << 6); | ||||
5667 | if (has_audio) | ||||
5668 | break; | ||||
5669 | } | ||||
5670 | } | ||||
5671 | drm_edid_iter_end(&edid_iter); | ||||
5672 | |||||
5673 | if (has_audio) { | ||||
5674 | DRM_DEBUG_KMS("Monitor has basic audio support\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Monitor has basic audio support\n" ); | ||||
5675 | goto end; | ||||
5676 | } | ||||
5677 | |||||
5678 | cea_db_iter_edid_begin(drm_edid, &iter); | ||||
5679 | cea_db_iter_for_each(db, &iter)while (((db) = __cea_db_iter_next(&iter))) { | ||||
5680 | if (cea_db_tag(db) == CTA_DB_AUDIO1) { | ||||
5681 | const u8 *data = cea_db_data(db); | ||||
5682 | int i; | ||||
5683 | |||||
5684 | for (i = 0; i < cea_db_payload_len(db); i += 3) | ||||
5685 | DRM_DEBUG_KMS("CEA audio format %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "CEA audio format %d\n", ( data[i] >> 3) & 0xf) | ||||
5686 | (data[i] >> 3) & 0xf)___drm_dbg(((void *)0), DRM_UT_KMS, "CEA audio format %d\n", ( data[i] >> 3) & 0xf); | ||||
5687 | has_audio = true1; | ||||
5688 | break; | ||||
5689 | } | ||||
5690 | } | ||||
5691 | cea_db_iter_end(&iter); | ||||
5692 | |||||
5693 | end: | ||||
5694 | return has_audio; | ||||
5695 | } | ||||
5696 | |||||
5697 | /** | ||||
5698 | * drm_detect_monitor_audio - check monitor audio capability | ||||
5699 | * @edid: EDID block to scan | ||||
5700 | * | ||||
5701 | * Monitor should have CEA extension block. | ||||
5702 | * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic | ||||
5703 | * audio' only. If there is any audio extension block and supported | ||||
5704 | * audio format, assume at least 'basic audio' support, even if 'basic | ||||
5705 | * audio' is not defined in EDID. | ||||
5706 | * | ||||
5707 | * Return: True if the monitor supports audio, false otherwise. | ||||
5708 | */ | ||||
5709 | bool_Bool drm_detect_monitor_audio(const struct edid *edid) | ||||
5710 | { | ||||
5711 | struct drm_edid drm_edid; | ||||
5712 | |||||
5713 | return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); | ||||
5714 | } | ||||
5715 | EXPORT_SYMBOL(drm_detect_monitor_audio); | ||||
5716 | |||||
5717 | |||||
5718 | /** | ||||
5719 | * drm_default_rgb_quant_range - default RGB quantization range | ||||
5720 | * @mode: display mode | ||||
5721 | * | ||||
5722 | * Determine the default RGB quantization range for the mode, | ||||
5723 | * as specified in CEA-861. | ||||
5724 | * | ||||
5725 | * Return: The default RGB quantization range for the mode | ||||
5726 | */ | ||||
5727 | enum hdmi_quantization_range | ||||
5728 | drm_default_rgb_quant_range(const struct drm_display_mode *mode) | ||||
5729 | { | ||||
5730 | /* All CEA modes other than VIC 1 use limited quantization range. */ | ||||
5731 | return drm_match_cea_mode(mode) > 1 ? | ||||
5732 | HDMI_QUANTIZATION_RANGE_LIMITED : | ||||
5733 | HDMI_QUANTIZATION_RANGE_FULL; | ||||
5734 | } | ||||
5735 | EXPORT_SYMBOL(drm_default_rgb_quant_range); | ||||
5736 | |||||
5737 | static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) | ||||
5738 | { | ||||
5739 | struct drm_display_info *info = &connector->display_info; | ||||
5740 | |||||
5741 | DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2])___drm_dbg(((void *)0), DRM_UT_KMS, "CEA VCDB 0x%02x\n", db[2 ]); | ||||
5742 | |||||
5743 | if (db[2] & EDID_CEA_VCDB_QS(1 << 6)) | ||||
5744 | info->rgb_quant_range_selectable = true1; | ||||
5745 | } | ||||
5746 | |||||
5747 | static | ||||
5748 | void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) | ||||
5749 | { | ||||
5750 | switch (max_frl_rate) { | ||||
5751 | case 1: | ||||
5752 | *max_lanes = 3; | ||||
5753 | *max_rate_per_lane = 3; | ||||
5754 | break; | ||||
5755 | case 2: | ||||
5756 | *max_lanes = 3; | ||||
5757 | *max_rate_per_lane = 6; | ||||
5758 | break; | ||||
5759 | case 3: | ||||
5760 | *max_lanes = 4; | ||||
5761 | *max_rate_per_lane = 6; | ||||
5762 | break; | ||||
5763 | case 4: | ||||
5764 | *max_lanes = 4; | ||||
5765 | *max_rate_per_lane = 8; | ||||
5766 | break; | ||||
5767 | case 5: | ||||
5768 | *max_lanes = 4; | ||||
5769 | *max_rate_per_lane = 10; | ||||
5770 | break; | ||||
5771 | case 6: | ||||
5772 | *max_lanes = 4; | ||||
5773 | *max_rate_per_lane = 12; | ||||
5774 | break; | ||||
5775 | case 0: | ||||
5776 | default: | ||||
5777 | *max_lanes = 0; | ||||
5778 | *max_rate_per_lane = 0; | ||||
5779 | } | ||||
5780 | } | ||||
5781 | |||||
5782 | static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, | ||||
5783 | const u8 *db) | ||||
5784 | { | ||||
5785 | u8 dc_mask; | ||||
5786 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; | ||||
5787 | |||||
5788 | dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK((1 << 2) | (1 << 1) | (1 << 0)); | ||||
5789 | hdmi->y420_dc_modes = dc_mask; | ||||
5790 | } | ||||
5791 | |||||
5792 | /* Sink Capability Data Structure */ | ||||
5793 | static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, | ||||
5794 | const u8 *hf_scds) | ||||
5795 | { | ||||
5796 | struct drm_display_info *display = &connector->display_info; | ||||
5797 | struct drm_hdmi_info *hdmi = &display->hdmi; | ||||
5798 | |||||
5799 | display->has_hdmi_infoframe = true1; | ||||
5800 | |||||
5801 | if (hf_scds[6] & 0x80) { | ||||
5802 | hdmi->scdc.supported = true1; | ||||
5803 | if (hf_scds[6] & 0x40) | ||||
5804 | hdmi->scdc.read_request = true1; | ||||
5805 | } | ||||
5806 | |||||
5807 | /* | ||||
5808 | * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. | ||||
5809 | * And as per the spec, three factors confirm this: | ||||
5810 | * * Availability of a HF-VSDB block in EDID (check) | ||||
5811 | * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) | ||||
5812 | * * SCDC support available (let's check) | ||||
5813 | * Lets check it out. | ||||
5814 | */ | ||||
5815 | |||||
5816 | if (hf_scds[5]) { | ||||
5817 | /* max clock is 5000 KHz times block value */ | ||||
5818 | u32 max_tmds_clock = hf_scds[5] * 5000; | ||||
5819 | struct drm_scdc *scdc = &hdmi->scdc; | ||||
5820 | |||||
5821 | if (max_tmds_clock > 340000) { | ||||
5822 | display->max_tmds_clock = max_tmds_clock; | ||||
5823 | DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",___drm_dbg(((void *)0), DRM_UT_KMS, "HF-VSDB: max TMDS clock %d kHz\n" , display->max_tmds_clock) | ||||
5824 | display->max_tmds_clock)___drm_dbg(((void *)0), DRM_UT_KMS, "HF-VSDB: max TMDS clock %d kHz\n" , display->max_tmds_clock); | ||||
5825 | } | ||||
5826 | |||||
5827 | if (scdc->supported) { | ||||
5828 | scdc->scrambling.supported = true1; | ||||
5829 | |||||
5830 | /* Few sinks support scrambling for clocks < 340M */ | ||||
5831 | if ((hf_scds[6] & 0x8)) | ||||
5832 | scdc->scrambling.low_rates = true1; | ||||
5833 | } | ||||
5834 | } | ||||
5835 | |||||
5836 | if (hf_scds[7]) { | ||||
5837 | u8 max_frl_rate; | ||||
5838 | u8 dsc_max_frl_rate; | ||||
5839 | u8 dsc_max_slices; | ||||
5840 | struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; | ||||
5841 | |||||
5842 | DRM_DEBUG_KMS("hdmi_21 sink detected. parsing edid\n")___drm_dbg(((void *)0), DRM_UT_KMS, "hdmi_21 sink detected. parsing edid\n" ); | ||||
5843 | max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK0xf0) >> 4; | ||||
5844 | drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, | ||||
5845 | &hdmi->max_frl_rate_per_lane); | ||||
5846 | hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2(1 << 7); | ||||
5847 | |||||
5848 | if (hdmi_dsc->v_1p2) { | ||||
5849 | hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420(1 << 6); | ||||
5850 | hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP(1 << 3); | ||||
5851 | |||||
5852 | if (hf_scds[11] & DRM_EDID_DSC_16BPC(1 << 2)) | ||||
5853 | hdmi_dsc->bpc_supported = 16; | ||||
5854 | else if (hf_scds[11] & DRM_EDID_DSC_12BPC(1 << 1)) | ||||
5855 | hdmi_dsc->bpc_supported = 12; | ||||
5856 | else if (hf_scds[11] & DRM_EDID_DSC_10BPC(1 << 0)) | ||||
5857 | hdmi_dsc->bpc_supported = 10; | ||||
5858 | else | ||||
5859 | /* Supports min 8 BPC if DSC 1.2 is supported*/ | ||||
5860 | hdmi_dsc->bpc_supported = 8; | ||||
5861 | |||||
5862 | dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK0xf0) >> 4; | ||||
5863 | drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, | ||||
5864 | &hdmi_dsc->max_frl_rate_per_lane); | ||||
5865 | hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES0x3f; | ||||
5866 | |||||
5867 | dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES0xf; | ||||
5868 | switch (dsc_max_slices) { | ||||
5869 | case 1: | ||||
5870 | hdmi_dsc->max_slices = 1; | ||||
5871 | hdmi_dsc->clk_per_slice = 340; | ||||
5872 | break; | ||||
5873 | case 2: | ||||
5874 | hdmi_dsc->max_slices = 2; | ||||
5875 | hdmi_dsc->clk_per_slice = 340; | ||||
5876 | break; | ||||
5877 | case 3: | ||||
5878 | hdmi_dsc->max_slices = 4; | ||||
5879 | hdmi_dsc->clk_per_slice = 340; | ||||
5880 | break; | ||||
5881 | case 4: | ||||
5882 | hdmi_dsc->max_slices = 8; | ||||
5883 | hdmi_dsc->clk_per_slice = 340; | ||||
5884 | break; | ||||
5885 | case 5: | ||||
5886 | hdmi_dsc->max_slices = 8; | ||||
5887 | hdmi_dsc->clk_per_slice = 400; | ||||
5888 | break; | ||||
5889 | case 6: | ||||
5890 | hdmi_dsc->max_slices = 12; | ||||
5891 | hdmi_dsc->clk_per_slice = 400; | ||||
5892 | break; | ||||
5893 | case 7: | ||||
5894 | hdmi_dsc->max_slices = 16; | ||||
5895 | hdmi_dsc->clk_per_slice = 400; | ||||
5896 | break; | ||||
5897 | case 0: | ||||
5898 | default: | ||||
5899 | hdmi_dsc->max_slices = 0; | ||||
5900 | hdmi_dsc->clk_per_slice = 0; | ||||
5901 | } | ||||
5902 | } | ||||
5903 | } | ||||
5904 | |||||
5905 | drm_parse_ycbcr420_deep_color_info(connector, hf_scds); | ||||
5906 | } | ||||
5907 | |||||
5908 | static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, | ||||
5909 | const u8 *hdmi) | ||||
5910 | { | ||||
5911 | struct drm_display_info *info = &connector->display_info; | ||||
5912 | unsigned int dc_bpc = 0; | ||||
5913 | |||||
5914 | /* HDMI supports at least 8 bpc */ | ||||
5915 | info->bpc = 8; | ||||
5916 | |||||
5917 | if (cea_db_payload_len(hdmi) < 6) | ||||
5918 | return; | ||||
5919 | |||||
5920 | if (hdmi[6] & DRM_EDID_HDMI_DC_30(1 << 4)) { | ||||
5921 | dc_bpc = 10; | ||||
5922 | info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30(1 << 4); | ||||
5923 | DRM_DEBUG("%s: HDMI sink does deep color 30.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink does deep color 30.\n" , connector->name) | ||||
5924 | connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink does deep color 30.\n" , connector->name); | ||||
5925 | } | ||||
5926 | |||||
5927 | if (hdmi[6] & DRM_EDID_HDMI_DC_36(1 << 5)) { | ||||
5928 | dc_bpc = 12; | ||||
5929 | info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36(1 << 5); | ||||
5930 | DRM_DEBUG("%s: HDMI sink does deep color 36.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink does deep color 36.\n" , connector->name) | ||||
5931 | connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink does deep color 36.\n" , connector->name); | ||||
5932 | } | ||||
5933 | |||||
5934 | if (hdmi[6] & DRM_EDID_HDMI_DC_48(1 << 6)) { | ||||
5935 | dc_bpc = 16; | ||||
5936 | info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48(1 << 6); | ||||
5937 | DRM_DEBUG("%s: HDMI sink does deep color 48.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink does deep color 48.\n" , connector->name) | ||||
5938 | connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink does deep color 48.\n" , connector->name); | ||||
5939 | } | ||||
5940 | |||||
5941 | if (dc_bpc == 0) { | ||||
5942 | DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: No deep color support on this HDMI sink.\n" , connector->name) | ||||
5943 | connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: No deep color support on this HDMI sink.\n" , connector->name); | ||||
5944 | return; | ||||
5945 | } | ||||
5946 | |||||
5947 | DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Assigning HDMI sink color depth as %d bpc.\n" , connector->name, dc_bpc) | ||||
5948 | connector->name, dc_bpc)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Assigning HDMI sink color depth as %d bpc.\n" , connector->name, dc_bpc); | ||||
5949 | info->bpc = dc_bpc; | ||||
5950 | |||||
5951 | /* YCRCB444 is optional according to spec. */ | ||||
5952 | if (hdmi[6] & DRM_EDID_HDMI_DC_Y444(1 << 3)) { | ||||
5953 | info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; | ||||
5954 | DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink does YCRCB444 in deep color.\n" , connector->name) | ||||
5955 | connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink does YCRCB444 in deep color.\n" , connector->name); | ||||
5956 | } | ||||
5957 | |||||
5958 | /* | ||||
5959 | * Spec says that if any deep color mode is supported at all, | ||||
5960 | * then deep color 36 bit must be supported. | ||||
5961 | */ | ||||
5962 | if (!(hdmi[6] & DRM_EDID_HDMI_DC_36(1 << 5))) { | ||||
5963 | DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink should do DC_36, but does not!\n" , connector->name) | ||||
5964 | connector->name)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: HDMI sink should do DC_36, but does not!\n" , connector->name); | ||||
5965 | } | ||||
5966 | } | ||||
5967 | |||||
5968 | static void | ||||
5969 | drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) | ||||
5970 | { | ||||
5971 | struct drm_display_info *info = &connector->display_info; | ||||
5972 | u8 len = cea_db_payload_len(db); | ||||
5973 | |||||
5974 | info->is_hdmi = true1; | ||||
5975 | |||||
5976 | if (len >= 6) | ||||
5977 | info->dvi_dual = db[6] & 1; | ||||
5978 | if (len >= 7) | ||||
5979 | info->max_tmds_clock = db[7] * 5000; | ||||
5980 | |||||
5981 | DRM_DEBUG_KMS("HDMI: DVI dual %d, "___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: DVI dual %d, " "max TMDS clock %d kHz\n" , info->dvi_dual, info->max_tmds_clock) | ||||
5982 | "max TMDS clock %d kHz\n",___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: DVI dual %d, " "max TMDS clock %d kHz\n" , info->dvi_dual, info->max_tmds_clock) | ||||
5983 | info->dvi_dual,___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: DVI dual %d, " "max TMDS clock %d kHz\n" , info->dvi_dual, info->max_tmds_clock) | ||||
5984 | info->max_tmds_clock)___drm_dbg(((void *)0), DRM_UT_KMS, "HDMI: DVI dual %d, " "max TMDS clock %d kHz\n" , info->dvi_dual, info->max_tmds_clock); | ||||
5985 | |||||
5986 | drm_parse_hdmi_deep_color_info(connector, db); | ||||
5987 | } | ||||
5988 | |||||
5989 | /* | ||||
5990 | * See EDID extension for head-mounted and specialized monitors, specified at: | ||||
5991 | * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension | ||||
5992 | */ | ||||
5993 | static void drm_parse_microsoft_vsdb(struct drm_connector *connector, | ||||
5994 | const u8 *db) | ||||
5995 | { | ||||
5996 | struct drm_display_info *info = &connector->display_info; | ||||
5997 | u8 version = db[4]; | ||||
5998 | bool_Bool desktop_usage = db[5] & BIT(6)(1UL << (6)); | ||||
5999 | |||||
6000 | /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ | ||||
6001 | if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) | ||||
6002 | info->non_desktop = true1; | ||||
6003 | |||||
6004 | drm_dbg_kms(connector->dev, "HMD or specialized display VSDB version %u: 0x%02x\n",__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "HMD or specialized display VSDB version %u: 0x%02x\n" , version, db[5]) | ||||
6005 | version, db[5])__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "HMD or specialized display VSDB version %u: 0x%02x\n" , version, db[5]); | ||||
6006 | } | ||||
6007 | |||||
6008 | static void drm_parse_cea_ext(struct drm_connector *connector, | ||||
6009 | const struct drm_edid *drm_edid) | ||||
6010 | { | ||||
6011 | struct drm_display_info *info = &connector->display_info; | ||||
6012 | struct drm_edid_iter edid_iter; | ||||
6013 | const struct cea_db *db; | ||||
6014 | struct cea_db_iter iter; | ||||
6015 | const u8 *edid_ext; | ||||
6016 | |||||
6017 | drm_edid_iter_begin(drm_edid, &edid_iter); | ||||
6018 | drm_edid_iter_for_each(edid_ext, &edid_iter)while (((edid_ext) = __drm_edid_iter_next(&edid_iter))) { | ||||
6019 | if (edid_ext[0] != CEA_EXT0x02) | ||||
6020 | continue; | ||||
6021 | |||||
6022 | if (!info->cea_rev) | ||||
6023 | info->cea_rev = edid_ext[1]; | ||||
6024 | |||||
6025 | if (info->cea_rev != edid_ext[1]) | ||||
6026 | DRM_DEBUG_KMS("CEA extension version mismatch %u != %u\n",___drm_dbg(((void *)0), DRM_UT_KMS, "CEA extension version mismatch %u != %u\n" , info->cea_rev, edid_ext[1]) | ||||
6027 | info->cea_rev, edid_ext[1])___drm_dbg(((void *)0), DRM_UT_KMS, "CEA extension version mismatch %u != %u\n" , info->cea_rev, edid_ext[1]); | ||||
6028 | |||||
6029 | /* The existence of a CTA extension should imply RGB support */ | ||||
6030 | info->color_formats = DRM_COLOR_FORMAT_RGB444(1<<0); | ||||
6031 | if (edid_ext[3] & EDID_CEA_YCRCB444(1 << 5)) | ||||
6032 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR444(1<<1); | ||||
6033 | if (edid_ext[3] & EDID_CEA_YCRCB422(1 << 4)) | ||||
6034 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR422(1<<2); | ||||
6035 | } | ||||
6036 | drm_edid_iter_end(&edid_iter); | ||||
6037 | |||||
6038 | cea_db_iter_edid_begin(drm_edid, &iter); | ||||
6039 | cea_db_iter_for_each(db, &iter)while (((db) = __cea_db_iter_next(&iter))) { | ||||
6040 | /* FIXME: convert parsers to use struct cea_db */ | ||||
6041 | const u8 *data = (const u8 *)db; | ||||
6042 | |||||
6043 | if (cea_db_is_hdmi_vsdb(db)) | ||||
6044 | drm_parse_hdmi_vsdb_video(connector, data); | ||||
6045 | else if (cea_db_is_hdmi_forum_vsdb(db) || | ||||
6046 | cea_db_is_hdmi_forum_scdb(db)) | ||||
6047 | drm_parse_hdmi_forum_scds(connector, data); | ||||
6048 | else if (cea_db_is_microsoft_vsdb(db)) | ||||
6049 | drm_parse_microsoft_vsdb(connector, data); | ||||
6050 | else if (cea_db_is_y420cmdb(db)) | ||||
6051 | drm_parse_y420cmdb_bitmap(connector, data); | ||||
6052 | else if (cea_db_is_vcdb(db)) | ||||
6053 | drm_parse_vcdb(connector, data); | ||||
6054 | else if (cea_db_is_hdmi_hdr_metadata_block(db)) | ||||
6055 | drm_parse_hdr_metadata_block(connector, data); | ||||
6056 | } | ||||
6057 | cea_db_iter_end(&iter); | ||||
6058 | } | ||||
6059 | |||||
6060 | static | ||||
6061 | void get_monitor_range(const struct detailed_timing *timing, void *c) | ||||
6062 | { | ||||
6063 | struct detailed_mode_closure *closure = c; | ||||
6064 | struct drm_display_info *info = &closure->connector->display_info; | ||||
6065 | struct drm_monitor_range_info *monitor_range = &info->monitor_range; | ||||
6066 | const struct detailed_non_pixel *data = &timing->data.other_data; | ||||
6067 | const struct detailed_data_monitor_range *range = &data->data.range; | ||||
6068 | const struct edid *edid = closure->drm_edid->edid; | ||||
6069 | |||||
6070 | if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE0xfd)) | ||||
6071 | return; | ||||
6072 | |||||
6073 | /* | ||||
6074 | * Check for flag range limits only. If flag == 1 then | ||||
6075 | * no additional timing information provided. | ||||
6076 | * Default GTF, GTF Secondary curve and CVT are not | ||||
6077 | * supported | ||||
6078 | */ | ||||
6079 | if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG0x01) | ||||
6080 | return; | ||||
6081 | |||||
6082 | monitor_range->min_vfreq = range->min_vfreq; | ||||
6083 | monitor_range->max_vfreq = range->max_vfreq; | ||||
6084 | |||||
6085 | if (edid->revision >= 4) { | ||||
6086 | if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ(1 << 0)) | ||||
6087 | monitor_range->min_vfreq += 255; | ||||
6088 | if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ(1 << 1)) | ||||
6089 | monitor_range->max_vfreq += 255; | ||||
6090 | } | ||||
6091 | } | ||||
6092 | |||||
6093 | static void drm_get_monitor_range(struct drm_connector *connector, | ||||
6094 | const struct drm_edid *drm_edid) | ||||
6095 | { | ||||
6096 | const struct drm_display_info *info = &connector->display_info; | ||||
6097 | struct detailed_mode_closure closure = { | ||||
6098 | .connector = connector, | ||||
6099 | .drm_edid = drm_edid, | ||||
6100 | }; | ||||
6101 | |||||
6102 | if (!version_greater(drm_edid, 1, 1)) | ||||
6103 | return; | ||||
6104 | |||||
6105 | drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); | ||||
6106 | |||||
6107 | DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Supported Monitor Refresh rate range is %d Hz - %d Hz\n" , info->monitor_range.min_vfreq, info->monitor_range.max_vfreq ) | ||||
6108 | info->monitor_range.min_vfreq,___drm_dbg(((void *)0), DRM_UT_KMS, "Supported Monitor Refresh rate range is %d Hz - %d Hz\n" , info->monitor_range.min_vfreq, info->monitor_range.max_vfreq ) | ||||
6109 | info->monitor_range.max_vfreq)___drm_dbg(((void *)0), DRM_UT_KMS, "Supported Monitor Refresh rate range is %d Hz - %d Hz\n" , info->monitor_range.min_vfreq, info->monitor_range.max_vfreq ); | ||||
6110 | } | ||||
6111 | |||||
6112 | static void drm_parse_vesa_mso_data(struct drm_connector *connector, | ||||
6113 | const struct displayid_block *block) | ||||
6114 | { | ||||
6115 | struct displayid_vesa_vendor_specific_block *vesa = | ||||
6116 | (struct displayid_vesa_vendor_specific_block *)block; | ||||
6117 | struct drm_display_info *info = &connector->display_info; | ||||
6118 | |||||
6119 | if (block->num_bytes < 3) { | ||||
6120 | drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "Unexpected vendor block size %u\n" , block->num_bytes) | ||||
6121 | block->num_bytes)__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "Unexpected vendor block size %u\n" , block->num_bytes); | ||||
6122 | return; | ||||
6123 | } | ||||
6124 | |||||
6125 | if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI0x3a0292) | ||||
6126 | return; | ||||
6127 | |||||
6128 | if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { | ||||
6129 | drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n")__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "Unexpected VESA vendor block size\n" ); | ||||
6130 | return; | ||||
6131 | } | ||||
6132 | |||||
6133 | switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)((typeof((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5)))))(((vesa->mso) & ((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))))) >> (__builtin_ffsll ((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5) ))) - 1)))) { | ||||
6134 | default: | ||||
6135 | drm_dbg_kms(connector->dev, "Reserved MSO mode value\n")__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "Reserved MSO mode value\n" ); | ||||
6136 | fallthroughdo {} while (0); | ||||
6137 | case 0: | ||||
6138 | info->mso_stream_count = 0; | ||||
6139 | break; | ||||
6140 | case 1: | ||||
6141 | info->mso_stream_count = 2; /* 2 or 4 links */ | ||||
6142 | break; | ||||
6143 | case 2: | ||||
6144 | info->mso_stream_count = 4; /* 4 links */ | ||||
6145 | break; | ||||
6146 | } | ||||
6147 | |||||
6148 | if (!info->mso_stream_count) { | ||||
6149 | info->mso_pixel_overlap = 0; | ||||
6150 | return; | ||||
6151 | } | ||||
6152 | |||||
6153 | info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso)((typeof((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0)))))(((vesa->mso) & ((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))))) >> (__builtin_ffsll ((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0) ))) - 1))); | ||||
6154 | if (info->mso_pixel_overlap > 8) { | ||||
6155 | drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "Reserved MSO pixel overlap value %u\n" , info->mso_pixel_overlap) | ||||
6156 | info->mso_pixel_overlap)__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "Reserved MSO pixel overlap value %u\n" , info->mso_pixel_overlap); | ||||
6157 | info->mso_pixel_overlap = 8; | ||||
6158 | } | ||||
6159 | |||||
6160 | drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "MSO stream count %u, pixel overlap %u\n" , info->mso_stream_count, info->mso_pixel_overlap) | ||||
6161 | info->mso_stream_count, info->mso_pixel_overlap)__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "MSO stream count %u, pixel overlap %u\n" , info->mso_stream_count, info->mso_pixel_overlap); | ||||
6162 | } | ||||
6163 | |||||
6164 | static void drm_update_mso(struct drm_connector *connector, | ||||
6165 | const struct drm_edid *drm_edid) | ||||
6166 | { | ||||
6167 | const struct displayid_block *block; | ||||
6168 | struct displayid_iter iter; | ||||
6169 | |||||
6170 | displayid_iter_edid_begin(drm_edid, &iter); | ||||
6171 | displayid_iter_for_each(block, &iter)while (((block) = __displayid_iter_next(&iter))) { | ||||
6172 | if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC0x7e) | ||||
6173 | drm_parse_vesa_mso_data(connector, block); | ||||
6174 | } | ||||
6175 | displayid_iter_end(&iter); | ||||
6176 | } | ||||
6177 | |||||
6178 | /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset | ||||
6179 | * all of the values which would have been set from EDID | ||||
6180 | */ | ||||
6181 | static void drm_reset_display_info(struct drm_connector *connector) | ||||
6182 | { | ||||
6183 | struct drm_display_info *info = &connector->display_info; | ||||
6184 | |||||
6185 | info->width_mm = 0; | ||||
6186 | info->height_mm = 0; | ||||
6187 | |||||
6188 | info->bpc = 0; | ||||
6189 | info->color_formats = 0; | ||||
6190 | info->cea_rev = 0; | ||||
6191 | info->max_tmds_clock = 0; | ||||
6192 | info->dvi_dual = false0; | ||||
6193 | info->is_hdmi = false0; | ||||
6194 | info->has_hdmi_infoframe = false0; | ||||
6195 | info->rgb_quant_range_selectable = false0; | ||||
6196 | memset(&info->hdmi, 0, sizeof(info->hdmi))__builtin_memset((&info->hdmi), (0), (sizeof(info-> hdmi))); | ||||
6197 | |||||
6198 | info->edid_hdmi_rgb444_dc_modes = 0; | ||||
6199 | info->edid_hdmi_ycbcr444_dc_modes = 0; | ||||
6200 | |||||
6201 | info->non_desktop = 0; | ||||
6202 | memset(&info->monitor_range, 0, sizeof(info->monitor_range))__builtin_memset((&info->monitor_range), (0), (sizeof( info->monitor_range))); | ||||
6203 | memset(&info->luminance_range, 0, sizeof(info->luminance_range))__builtin_memset((&info->luminance_range), (0), (sizeof (info->luminance_range))); | ||||
6204 | |||||
6205 | info->mso_stream_count = 0; | ||||
6206 | info->mso_pixel_overlap = 0; | ||||
6207 | info->max_dsc_bpp = 0; | ||||
6208 | } | ||||
6209 | |||||
6210 | static u32 update_display_info(struct drm_connector *connector, | ||||
6211 | const struct drm_edid *drm_edid) | ||||
6212 | { | ||||
6213 | struct drm_display_info *info = &connector->display_info; | ||||
6214 | const struct edid *edid = drm_edid->edid; | ||||
6215 | |||||
6216 | u32 quirks = edid_get_quirks(drm_edid); | ||||
6217 | |||||
6218 | drm_reset_display_info(connector); | ||||
6219 | |||||
6220 | info->width_mm = edid->width_cm * 10; | ||||
6221 | info->height_mm = edid->height_cm * 10; | ||||
6222 | |||||
6223 | drm_get_monitor_range(connector, drm_edid); | ||||
6224 | |||||
6225 | if (edid->revision < 3) | ||||
6226 | goto out; | ||||
6227 | |||||
6228 | if (!(edid->input & DRM_EDID_INPUT_DIGITAL(1 << 7))) | ||||
6229 | goto out; | ||||
6230 | |||||
6231 | info->color_formats |= DRM_COLOR_FORMAT_RGB444(1<<0); | ||||
6232 | drm_parse_cea_ext(connector, drm_edid); | ||||
6233 | |||||
6234 | /* | ||||
6235 | * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? | ||||
6236 | * | ||||
6237 | * For such displays, the DFP spec 1.0, section 3.10 "EDID support" | ||||
6238 | * tells us to assume 8 bpc color depth if the EDID doesn't have | ||||
6239 | * extensions which tell otherwise. | ||||
6240 | */ | ||||
6241 | if (info->bpc == 0 && edid->revision == 3 && | ||||
6242 | edid->input & DRM_EDID_DIGITAL_DFP_1_X(1 << 0)) { | ||||
6243 | info->bpc = 8; | ||||
6244 | DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Assigning DFP sink color depth as %d bpc.\n" , connector->name, info->bpc) | ||||
6245 | connector->name, info->bpc)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Assigning DFP sink color depth as %d bpc.\n" , connector->name, info->bpc); | ||||
6246 | } | ||||
6247 | |||||
6248 | /* Only defined for 1.4 with digital displays */ | ||||
6249 | if (edid->revision < 4) | ||||
6250 | goto out; | ||||
6251 | |||||
6252 | switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK(7 << 4)) { | ||||
6253 | case DRM_EDID_DIGITAL_DEPTH_6(1 << 4): | ||||
6254 | info->bpc = 6; | ||||
6255 | break; | ||||
6256 | case DRM_EDID_DIGITAL_DEPTH_8(2 << 4): | ||||
6257 | info->bpc = 8; | ||||
6258 | break; | ||||
6259 | case DRM_EDID_DIGITAL_DEPTH_10(3 << 4): | ||||
6260 | info->bpc = 10; | ||||
6261 | break; | ||||
6262 | case DRM_EDID_DIGITAL_DEPTH_12(4 << 4): | ||||
6263 | info->bpc = 12; | ||||
6264 | break; | ||||
6265 | case DRM_EDID_DIGITAL_DEPTH_14(5 << 4): | ||||
6266 | info->bpc = 14; | ||||
6267 | break; | ||||
6268 | case DRM_EDID_DIGITAL_DEPTH_16(6 << 4): | ||||
6269 | info->bpc = 16; | ||||
6270 | break; | ||||
6271 | case DRM_EDID_DIGITAL_DEPTH_UNDEF(0 << 4): | ||||
6272 | default: | ||||
6273 | info->bpc = 0; | ||||
6274 | break; | ||||
6275 | } | ||||
6276 | |||||
6277 | DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n" , connector->name, info->bpc) | ||||
6278 | connector->name, info->bpc)___drm_dbg(((void *)0), DRM_UT_CORE, "%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n" , connector->name, info->bpc); | ||||
6279 | |||||
6280 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444(1 << 3)) | ||||
6281 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR444(1<<1); | ||||
6282 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422(2 << 3)) | ||||
6283 | info->color_formats |= DRM_COLOR_FORMAT_YCBCR422(1<<2); | ||||
6284 | |||||
6285 | drm_update_mso(connector, drm_edid); | ||||
6286 | |||||
6287 | out: | ||||
6288 | if (quirks & EDID_QUIRK_NON_DESKTOP(1 << 12)) { | ||||
6289 | drm_dbg_kms(connector->dev, "Non-desktop display%s\n",__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "Non-desktop display%s\n" , info->non_desktop ? " (redundant quirk)" : "") | ||||
6290 | info->non_desktop ? " (redundant quirk)" : "")__drm_dev_dbg(((void *)0), (connector->dev) ? (connector-> dev)->dev : ((void *)0), DRM_UT_KMS, "Non-desktop display%s\n" , info->non_desktop ? " (redundant quirk)" : ""); | ||||
6291 | info->non_desktop = true1; | ||||
6292 | } | ||||
6293 | |||||
6294 | if (quirks & EDID_QUIRK_CAP_DSC_15BPP(1 << 13)) | ||||
6295 | info->max_dsc_bpp = 15; | ||||
6296 | |||||
6297 | return quirks; | ||||
6298 | } | ||||
6299 | |||||
6300 | static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, | ||||
6301 | struct displayid_detailed_timings_1 *timings, | ||||
6302 | bool_Bool type_7) | ||||
6303 | { | ||||
6304 | struct drm_display_mode *mode; | ||||
6305 | unsigned pixel_clock = (timings->pixel_clock[0] | | ||||
6306 | (timings->pixel_clock[1] << 8) | | ||||
6307 | (timings->pixel_clock[2] << 16)) + 1; | ||||
6308 | unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; | ||||
6309 | unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; | ||||
6310 | unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; | ||||
6311 | unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; | ||||
6312 | unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; | ||||
6313 | unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; | ||||
6314 | unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; | ||||
6315 | unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; | ||||
6316 | bool_Bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; | ||||
6317 | bool_Bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; | ||||
6318 | |||||
6319 | mode = drm_mode_create(dev); | ||||
6320 | if (!mode) | ||||
6321 | return NULL((void *)0); | ||||
6322 | |||||
6323 | /* resolution is kHz for type VII, and 10 kHz for type I */ | ||||
6324 | mode->clock = type_7 ? pixel_clock : pixel_clock * 10; | ||||
6325 | mode->hdisplay = hactive; | ||||
6326 | mode->hsync_start = mode->hdisplay + hsync; | ||||
6327 | mode->hsync_end = mode->hsync_start + hsync_width; | ||||
6328 | mode->htotal = mode->hdisplay + hblank; | ||||
6329 | |||||
6330 | mode->vdisplay = vactive; | ||||
6331 | mode->vsync_start = mode->vdisplay + vsync; | ||||
6332 | mode->vsync_end = mode->vsync_start + vsync_width; | ||||
6333 | mode->vtotal = mode->vdisplay + vblank; | ||||
6334 | |||||
6335 | mode->flags = 0; | ||||
6336 | mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC(1<<0) : DRM_MODE_FLAG_NHSYNC(1<<1); | ||||
6337 | mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC(1<<2) : DRM_MODE_FLAG_NVSYNC(1<<3); | ||||
6338 | mode->type = DRM_MODE_TYPE_DRIVER(1<<6); | ||||
6339 | |||||
6340 | if (timings->flags & 0x80) | ||||
6341 | mode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
6342 | drm_mode_set_name(mode); | ||||
6343 | |||||
6344 | return mode; | ||||
6345 | } | ||||
6346 | |||||
6347 | static int add_displayid_detailed_1_modes(struct drm_connector *connector, | ||||
6348 | const struct displayid_block *block) | ||||
6349 | { | ||||
6350 | struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; | ||||
6351 | int i; | ||||
6352 | int num_timings; | ||||
6353 | struct drm_display_mode *newmode; | ||||
6354 | int num_modes = 0; | ||||
6355 | bool_Bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING0x22; | ||||
6356 | /* blocks must be multiple of 20 bytes length */ | ||||
6357 | if (block->num_bytes % 20) | ||||
6358 | return 0; | ||||
6359 | |||||
6360 | num_timings = block->num_bytes / 20; | ||||
6361 | for (i = 0; i < num_timings; i++) { | ||||
6362 | struct displayid_detailed_timings_1 *timings = &det->timings[i]; | ||||
6363 | |||||
6364 | newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); | ||||
6365 | if (!newmode) | ||||
6366 | continue; | ||||
6367 | |||||
6368 | drm_mode_probed_add(connector, newmode); | ||||
6369 | num_modes++; | ||||
6370 | } | ||||
6371 | return num_modes; | ||||
6372 | } | ||||
6373 | |||||
6374 | static int add_displayid_detailed_modes(struct drm_connector *connector, | ||||
6375 | const struct drm_edid *drm_edid) | ||||
6376 | { | ||||
6377 | const struct displayid_block *block; | ||||
6378 | struct displayid_iter iter; | ||||
6379 | int num_modes = 0; | ||||
6380 | |||||
6381 | displayid_iter_edid_begin(drm_edid, &iter); | ||||
6382 | displayid_iter_for_each(block, &iter)while (((block) = __displayid_iter_next(&iter))) { | ||||
6383 | if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING0x03 || | ||||
6384 | block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING0x22) | ||||
6385 | num_modes += add_displayid_detailed_1_modes(connector, block); | ||||
6386 | } | ||||
6387 | displayid_iter_end(&iter); | ||||
6388 | |||||
6389 | return num_modes; | ||||
6390 | } | ||||
6391 | |||||
6392 | static int _drm_edid_connector_update(struct drm_connector *connector, | ||||
6393 | const struct drm_edid *drm_edid) | ||||
6394 | { | ||||
6395 | int num_modes = 0; | ||||
6396 | u32 quirks; | ||||
6397 | |||||
6398 | if (!drm_edid) { | ||||
6399 | drm_reset_display_info(connector); | ||||
6400 | clear_eld(connector); | ||||
6401 | return 0; | ||||
6402 | } | ||||
6403 | |||||
6404 | /* | ||||
6405 | * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. | ||||
6406 | * To avoid multiple parsing of same block, lets parse that map | ||||
6407 | * from sink info, before parsing CEA modes. | ||||
6408 | */ | ||||
6409 | quirks = update_display_info(connector, drm_edid); | ||||
6410 | |||||
6411 | /* Depends on info->cea_rev set by update_display_info() above */ | ||||
6412 | drm_edid_to_eld(connector, drm_edid); | ||||
6413 | |||||
6414 | /* | ||||
6415 | * EDID spec says modes should be preferred in this order: | ||||
6416 | * - preferred detailed mode | ||||
6417 | * - other detailed modes from base block | ||||
6418 | * - detailed modes from extension blocks | ||||
6419 | * - CVT 3-byte code modes | ||||
6420 | * - standard timing codes | ||||
6421 | * - established timing codes | ||||
6422 | * - modes inferred from GTF or CVT range information | ||||
6423 | * | ||||
6424 | * We get this pretty much right. | ||||
6425 | * | ||||
6426 | * XXX order for additional mode types in extension blocks? | ||||
6427 | */ | ||||
6428 | num_modes += add_detailed_modes(connector, drm_edid, quirks); | ||||
6429 | num_modes += add_cvt_modes(connector, drm_edid); | ||||
6430 | num_modes += add_standard_modes(connector, drm_edid); | ||||
6431 | num_modes += add_established_modes(connector, drm_edid); | ||||
6432 | num_modes += add_cea_modes(connector, drm_edid); | ||||
6433 | num_modes += add_alternate_cea_modes(connector, drm_edid); | ||||
6434 | num_modes += add_displayid_detailed_modes(connector, drm_edid); | ||||
6435 | if (drm_edid->edid->features & DRM_EDID_FEATURE_DEFAULT_GTF(1 << 0)) | ||||
6436 | num_modes += add_inferred_modes(connector, drm_edid); | ||||
6437 | |||||
6438 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60(1 << 0) | EDID_QUIRK_PREFER_LARGE_75(1 << 2))) | ||||
6439 | edid_fixup_preferred(connector, quirks); | ||||
6440 | |||||
6441 | if (quirks & EDID_QUIRK_FORCE_6BPC(1 << 10)) | ||||
6442 | connector->display_info.bpc = 6; | ||||
6443 | |||||
6444 | if (quirks & EDID_QUIRK_FORCE_8BPC(1 << 8)) | ||||
6445 | connector->display_info.bpc = 8; | ||||
6446 | |||||
6447 | if (quirks & EDID_QUIRK_FORCE_10BPC(1 << 11)) | ||||
6448 | connector->display_info.bpc = 10; | ||||
6449 | |||||
6450 | if (quirks & EDID_QUIRK_FORCE_12BPC(1 << 9)) | ||||
6451 | connector->display_info.bpc = 12; | ||||
6452 | |||||
6453 | return num_modes; | ||||
6454 | } | ||||
6455 | |||||
6456 | static void _drm_update_tile_info(struct drm_connector *connector, | ||||
6457 | const struct drm_edid *drm_edid); | ||||
6458 | |||||
6459 | static int _drm_edid_connector_property_update(struct drm_connector *connector, | ||||
6460 | const struct drm_edid *drm_edid) | ||||
6461 | { | ||||
6462 | struct drm_device *dev = connector->dev; | ||||
6463 | int ret; | ||||
6464 | |||||
6465 | if (connector->edid_blob_ptr) { | ||||
6466 | const struct edid *old_edid = connector->edid_blob_ptr->data; | ||||
6467 | |||||
6468 | if (old_edid) { | ||||
6469 | if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL((void *)0), old_edid)) { | ||||
6470 | connector->epoch_counter++; | ||||
6471 | drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n" , connector->base.id, connector->name, connector->epoch_counter ) | ||||
6472 | connector->base.id, connector->name,__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n" , connector->base.id, connector->name, connector->epoch_counter ) | ||||
6473 | connector->epoch_counter)__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n" , connector->base.id, connector->name, connector->epoch_counter ); | ||||
6474 | } | ||||
6475 | } | ||||
6476 | } | ||||
6477 | |||||
6478 | ret = drm_property_replace_global_blob(dev, | ||||
6479 | &connector->edid_blob_ptr, | ||||
6480 | drm_edid ? drm_edid->size : 0, | ||||
6481 | drm_edid ? drm_edid->edid : NULL((void *)0), | ||||
6482 | &connector->base, | ||||
6483 | dev->mode_config.edid_property); | ||||
6484 | if (ret) { | ||||
6485 | drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n" , connector->base.id, connector->name, ret) | ||||
6486 | connector->base.id, connector->name, ret)__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n" , connector->base.id, connector->name, ret); | ||||
6487 | goto out; | ||||
6488 | } | ||||
6489 | |||||
6490 | ret = drm_object_property_set_value(&connector->base, | ||||
6491 | dev->mode_config.non_desktop_property, | ||||
6492 | connector->display_info.non_desktop); | ||||
6493 | if (ret) { | ||||
6494 | drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n" , connector->base.id, connector->name, ret) | ||||
6495 | connector->base.id, connector->name, ret)__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n" , connector->base.id, connector->name, ret); | ||||
6496 | goto out; | ||||
6497 | } | ||||
6498 | |||||
6499 | ret = drm_connector_set_tile_property(connector); | ||||
6500 | if (ret) { | ||||
6501 | drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n" , connector->base.id, connector->name, ret) | ||||
6502 | connector->base.id, connector->name, ret)__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0 ), DRM_UT_KMS, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n" , connector->base.id, connector->name, ret); | ||||
6503 | goto out; | ||||
6504 | } | ||||
6505 | |||||
6506 | out: | ||||
6507 | return ret; | ||||
6508 | } | ||||
6509 | |||||
6510 | /** | ||||
6511 | * drm_edid_connector_update - Update connector information from EDID | ||||
6512 | * @connector: Connector | ||||
6513 | * @drm_edid: EDID | ||||
6514 | * | ||||
6515 | * Update the connector mode list, display info, ELD, HDR metadata, relevant | ||||
6516 | * properties, etc. from the passed in EDID. | ||||
6517 | * | ||||
6518 | * If EDID is NULL, reset the information. | ||||
6519 | * | ||||
6520 | * Return: The number of modes added or 0 if we couldn't find any. | ||||
6521 | */ | ||||
6522 | int drm_edid_connector_update(struct drm_connector *connector, | ||||
6523 | const struct drm_edid *drm_edid) | ||||
6524 | { | ||||
6525 | int count; | ||||
6526 | |||||
6527 | /* | ||||
6528 | * FIXME: Reconcile the differences in override_edid handling between | ||||
6529 | * this and drm_connector_update_edid_property(). | ||||
6530 | * | ||||
6531 | * If override_edid is set, and the EDID passed in here originates from | ||||
6532 | * drm_edid_read() and friends, it will be the override EDID, and there | ||||
6533 | * are no issues. drm_connector_update_edid_property() ignoring requests | ||||
6534 | * to set the EDID dates back to a time when override EDID was not | ||||
6535 | * handled at the low level EDID read. | ||||
6536 | * | ||||
6537 | * The only way the EDID passed in here can be different from the | ||||
6538 | * override EDID is when a driver passes in an EDID that does *not* | ||||
6539 | * originate from drm_edid_read() and friends, or passes in a stale | ||||
6540 | * cached version. This, in turn, is a question of when an override EDID | ||||
6541 | * set via debugfs should take effect. | ||||
6542 | */ | ||||
6543 | |||||
6544 | count = _drm_edid_connector_update(connector, drm_edid); | ||||
6545 | |||||
6546 | _drm_update_tile_info(connector, drm_edid); | ||||
6547 | |||||
6548 | /* Note: Ignore errors for now. */ | ||||
6549 | _drm_edid_connector_property_update(connector, drm_edid); | ||||
6550 | |||||
6551 | return count; | ||||
6552 | } | ||||
6553 | EXPORT_SYMBOL(drm_edid_connector_update); | ||||
6554 | |||||
6555 | static int _drm_connector_update_edid_property(struct drm_connector *connector, | ||||
6556 | const struct drm_edid *drm_edid) | ||||
6557 | { | ||||
6558 | /* ignore requests to set edid when overridden */ | ||||
6559 | if (connector->override_edid) | ||||
6560 | return 0; | ||||
6561 | |||||
6562 | /* | ||||
6563 | * Set the display info, using edid if available, otherwise resetting | ||||
6564 | * the values to defaults. This duplicates the work done in | ||||
6565 | * drm_add_edid_modes, but that function is not consistently called | ||||
6566 | * before this one in all drivers and the computation is cheap enough | ||||
6567 | * that it seems better to duplicate it rather than attempt to ensure | ||||
6568 | * some arbitrary ordering of calls. | ||||
6569 | */ | ||||
6570 | if (drm_edid) | ||||
6571 | update_display_info(connector, drm_edid); | ||||
6572 | else | ||||
6573 | drm_reset_display_info(connector); | ||||
6574 | |||||
6575 | _drm_update_tile_info(connector, drm_edid); | ||||
6576 | |||||
6577 | return _drm_edid_connector_property_update(connector, drm_edid); | ||||
6578 | } | ||||
6579 | |||||
6580 | /** | ||||
6581 | * drm_connector_update_edid_property - update the edid property of a connector | ||||
6582 | * @connector: drm connector | ||||
6583 | * @edid: new value of the edid property | ||||
6584 | * | ||||
6585 | * This function creates a new blob modeset object and assigns its id to the | ||||
6586 | * connector's edid property. | ||||
6587 | * Since we also parse tile information from EDID's displayID block, we also | ||||
6588 | * set the connector's tile property here. See drm_connector_set_tile_property() | ||||
6589 | * for more details. | ||||
6590 | * | ||||
6591 | * This function is deprecated. Use drm_edid_connector_update() instead. | ||||
6592 | * | ||||
6593 | * Returns: | ||||
6594 | * Zero on success, negative errno on failure. | ||||
6595 | */ | ||||
6596 | int drm_connector_update_edid_property(struct drm_connector *connector, | ||||
6597 | const struct edid *edid) | ||||
6598 | { | ||||
6599 | struct drm_edid drm_edid; | ||||
6600 | |||||
6601 | return _drm_connector_update_edid_property(connector, | ||||
6602 | drm_edid_legacy_init(&drm_edid, edid)); | ||||
6603 | } | ||||
6604 | EXPORT_SYMBOL(drm_connector_update_edid_property); | ||||
6605 | |||||
6606 | /** | ||||
6607 | * drm_add_edid_modes - add modes from EDID data, if available | ||||
6608 | * @connector: connector we're probing | ||||
6609 | * @edid: EDID data | ||||
6610 | * | ||||
6611 | * Add the specified modes to the connector's mode list. Also fills out the | ||||
6612 | * &drm_display_info structure and ELD in @connector with any information which | ||||
6613 | * can be derived from the edid. | ||||
6614 | * | ||||
6615 | * This function is deprecated. Use drm_edid_connector_update() instead. | ||||
6616 | * | ||||
6617 | * Return: The number of modes added or 0 if we couldn't find any. | ||||
6618 | */ | ||||
6619 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | ||||
6620 | { | ||||
6621 | struct drm_edid drm_edid; | ||||
6622 | |||||
6623 | if (edid && !drm_edid_is_valid(edid)) { | ||||
6624 | drm_warn(connector->dev, "%s: EDID invalid.\n",printf("drm:pid%d:%s *WARNING* " "[drm] " "%s: EDID invalid.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , connector ->name) | ||||
6625 | connector->name)printf("drm:pid%d:%s *WARNING* " "[drm] " "%s: EDID invalid.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , connector ->name); | ||||
6626 | edid = NULL((void *)0); | ||||
6627 | } | ||||
6628 | |||||
6629 | return _drm_edid_connector_update(connector, | ||||
6630 | drm_edid_legacy_init(&drm_edid, edid)); | ||||
6631 | } | ||||
6632 | EXPORT_SYMBOL(drm_add_edid_modes); | ||||
6633 | |||||
6634 | /** | ||||
6635 | * drm_add_modes_noedid - add modes for the connectors without EDID | ||||
6636 | * @connector: connector we're probing | ||||
6637 | * @hdisplay: the horizontal display limit | ||||
6638 | * @vdisplay: the vertical display limit | ||||
6639 | * | ||||
6640 | * Add the specified modes to the connector's mode list. Only when the | ||||
6641 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | ||||
6642 | * | ||||
6643 | * Return: The number of modes added or 0 if we couldn't find any. | ||||
6644 | */ | ||||
6645 | int drm_add_modes_noedid(struct drm_connector *connector, | ||||
6646 | int hdisplay, int vdisplay) | ||||
6647 | { | ||||
6648 | int i, count, num_modes = 0; | ||||
6649 | struct drm_display_mode *mode; | ||||
6650 | struct drm_device *dev = connector->dev; | ||||
6651 | |||||
6652 | count = ARRAY_SIZE(drm_dmt_modes)(sizeof((drm_dmt_modes)) / sizeof((drm_dmt_modes)[0])); | ||||
6653 | if (hdisplay < 0) | ||||
6654 | hdisplay = 0; | ||||
6655 | if (vdisplay < 0) | ||||
6656 | vdisplay = 0; | ||||
6657 | |||||
6658 | for (i = 0; i < count; i++) { | ||||
6659 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; | ||||
6660 | |||||
6661 | if (hdisplay && vdisplay) { | ||||
6662 | /* | ||||
6663 | * Only when two are valid, they will be used to check | ||||
6664 | * whether the mode should be added to the mode list of | ||||
6665 | * the connector. | ||||
6666 | */ | ||||
6667 | if (ptr->hdisplay > hdisplay || | ||||
6668 | ptr->vdisplay > vdisplay) | ||||
6669 | continue; | ||||
6670 | } | ||||
6671 | if (drm_mode_vrefresh(ptr) > 61) | ||||
6672 | continue; | ||||
6673 | mode = drm_mode_duplicate(dev, ptr); | ||||
6674 | if (mode) { | ||||
6675 | drm_mode_probed_add(connector, mode); | ||||
6676 | num_modes++; | ||||
6677 | } | ||||
6678 | } | ||||
6679 | return num_modes; | ||||
6680 | } | ||||
6681 | EXPORT_SYMBOL(drm_add_modes_noedid); | ||||
6682 | |||||
6683 | /** | ||||
6684 | * drm_set_preferred_mode - Sets the preferred mode of a connector | ||||
6685 | * @connector: connector whose mode list should be processed | ||||
6686 | * @hpref: horizontal resolution of preferred mode | ||||
6687 | * @vpref: vertical resolution of preferred mode | ||||
6688 | * | ||||
6689 | * Marks a mode as preferred if it matches the resolution specified by @hpref | ||||
6690 | * and @vpref. | ||||
6691 | */ | ||||
6692 | void drm_set_preferred_mode(struct drm_connector *connector, | ||||
6693 | int hpref, int vpref) | ||||
6694 | { | ||||
6695 | struct drm_display_mode *mode; | ||||
6696 | |||||
6697 | list_for_each_entry(mode, &connector->probed_modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof (*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode ), head) );}); &mode->head != (&connector->probed_modes ); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char * )__mptr - __builtin_offsetof(__typeof(*mode), head) );})) { | ||||
6698 | if (mode->hdisplay == hpref && | ||||
6699 | mode->vdisplay == vpref) | ||||
6700 | mode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
6701 | } | ||||
6702 | } | ||||
6703 | EXPORT_SYMBOL(drm_set_preferred_mode); | ||||
6704 | |||||
6705 | static bool_Bool is_hdmi2_sink(const struct drm_connector *connector) | ||||
6706 | { | ||||
6707 | /* | ||||
6708 | * FIXME: sil-sii8620 doesn't have a connector around when | ||||
6709 | * we need one, so we have to be prepared for a NULL connector. | ||||
6710 | */ | ||||
6711 | if (!connector) | ||||
6712 | return true1; | ||||
6713 | |||||
6714 | return connector->display_info.hdmi.scdc.supported || | ||||
6715 | connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420(1<<3); | ||||
6716 | } | ||||
6717 | |||||
6718 | static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, | ||||
6719 | const struct drm_display_mode *mode) | ||||
6720 | { | ||||
6721 | bool_Bool has_hdmi_infoframe = connector ? | ||||
6722 | connector->display_info.has_hdmi_infoframe : false0; | ||||
6723 | |||||
6724 | if (!has_hdmi_infoframe) | ||||
6725 | return 0; | ||||
6726 | |||||
6727 | /* No HDMI VIC when signalling 3D video format */ | ||||
6728 | if (mode->flags & DRM_MODE_FLAG_3D_MASK(0x1f<<14)) | ||||
6729 | return 0; | ||||
6730 | |||||
6731 | return drm_match_hdmi_mode(mode); | ||||
6732 | } | ||||
6733 | |||||
6734 | static u8 drm_mode_cea_vic(const struct drm_connector *connector, | ||||
6735 | const struct drm_display_mode *mode) | ||||
6736 | { | ||||
6737 | /* | ||||
6738 | * HDMI spec says if a mode is found in HDMI 1.4b 4K modes | ||||
6739 | * we should send its VIC in vendor infoframes, else send the | ||||
6740 | * VIC in AVI infoframes. Lets check if this mode is present in | ||||
6741 | * HDMI 1.4b 4K modes | ||||
6742 | */ | ||||
6743 | if (drm_mode_hdmi_vic(connector, mode)) | ||||
6744 | return 0; | ||||
6745 | |||||
6746 | return drm_match_cea_mode(mode); | ||||
6747 | } | ||||
6748 | |||||
6749 | /* | ||||
6750 | * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that | ||||
6751 | * conform to HDMI 1.4. | ||||
6752 | * | ||||
6753 | * HDMI 1.4 (CTA-861-D) VIC range: [1..64] | ||||
6754 | * HDMI 2.0 (CTA-861-F) VIC range: [1..107] | ||||
6755 | */ | ||||
6756 | static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) | ||||
6757 | { | ||||
6758 | if (!is_hdmi2_sink(connector) && vic > 64) | ||||
6759 | return 0; | ||||
6760 | |||||
6761 | return vic; | ||||
6762 | } | ||||
6763 | |||||
6764 | /** | ||||
6765 | * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with | ||||
6766 | * data from a DRM display mode | ||||
6767 | * @frame: HDMI AVI infoframe | ||||
6768 | * @connector: the connector | ||||
6769 | * @mode: DRM display mode | ||||
6770 | * | ||||
6771 | * Return: 0 on success or a negative error code on failure. | ||||
6772 | */ | ||||
6773 | int | ||||
6774 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, | ||||
6775 | const struct drm_connector *connector, | ||||
6776 | const struct drm_display_mode *mode) | ||||
6777 | { | ||||
6778 | enum hdmi_picture_aspect picture_aspect; | ||||
6779 | u8 vic, hdmi_vic; | ||||
6780 | |||||
6781 | if (!frame || !mode) | ||||
6782 | return -EINVAL22; | ||||
6783 | |||||
6784 | hdmi_avi_infoframe_init(frame); | ||||
6785 | |||||
6786 | if (mode->flags & DRM_MODE_FLAG_DBLCLK(1<<12)) | ||||
6787 | frame->pixel_repeat = 1; | ||||
6788 | |||||
6789 | vic = drm_mode_cea_vic(connector, mode); | ||||
6790 | hdmi_vic = drm_mode_hdmi_vic(connector, mode); | ||||
6791 | |||||
6792 | frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; | ||||
6793 | |||||
6794 | /* | ||||
6795 | * As some drivers don't support atomic, we can't use connector state. | ||||
6796 | * So just initialize the frame with default values, just the same way | ||||
6797 | * as it's done with other properties here. | ||||
6798 | */ | ||||
6799 | frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; | ||||
6800 | frame->itc = 0; | ||||
6801 | |||||
6802 | /* | ||||
6803 | * Populate picture aspect ratio from either | ||||
6804 | * user input (if specified) or from the CEA/HDMI mode lists. | ||||
6805 | */ | ||||
6806 | picture_aspect = mode->picture_aspect_ratio; | ||||
6807 | if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { | ||||
6808 | if (vic) | ||||
6809 | picture_aspect = drm_get_cea_aspect_ratio(vic); | ||||
6810 | else if (hdmi_vic) | ||||
6811 | picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); | ||||
6812 | } | ||||
6813 | |||||
6814 | /* | ||||
6815 | * The infoframe can't convey anything but none, 4:3 | ||||
6816 | * and 16:9, so if the user has asked for anything else | ||||
6817 | * we can only satisfy it by specifying the right VIC. | ||||
6818 | */ | ||||
6819 | if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { | ||||
6820 | if (vic) { | ||||
6821 | if (picture_aspect != drm_get_cea_aspect_ratio(vic)) | ||||
6822 | return -EINVAL22; | ||||
6823 | } else if (hdmi_vic) { | ||||
6824 | if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) | ||||
6825 | return -EINVAL22; | ||||
6826 | } else { | ||||
6827 | return -EINVAL22; | ||||
6828 | } | ||||
6829 | |||||
6830 | picture_aspect = HDMI_PICTURE_ASPECT_NONE; | ||||
6831 | } | ||||
6832 | |||||
6833 | frame->video_code = vic_for_avi_infoframe(connector, vic); | ||||
6834 | frame->picture_aspect = picture_aspect; | ||||
6835 | frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; | ||||
6836 | frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; | ||||
6837 | |||||
6838 | return 0; | ||||
6839 | } | ||||
6840 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); | ||||
6841 | |||||
6842 | /** | ||||
6843 | * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe | ||||
6844 | * quantization range information | ||||
6845 | * @frame: HDMI AVI infoframe | ||||
6846 | * @connector: the connector | ||||
6847 | * @mode: DRM display mode | ||||
6848 | * @rgb_quant_range: RGB quantization range (Q) | ||||
6849 | */ | ||||
6850 | void | ||||
6851 | drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, | ||||
6852 | const struct drm_connector *connector, | ||||
6853 | const struct drm_display_mode *mode, | ||||
6854 | enum hdmi_quantization_range rgb_quant_range) | ||||
6855 | { | ||||
6856 | const struct drm_display_info *info = &connector->display_info; | ||||
6857 | |||||
6858 | /* | ||||
6859 | * CEA-861: | ||||
6860 | * "A Source shall not send a non-zero Q value that does not correspond | ||||
6861 | * to the default RGB Quantization Range for the transmitted Picture | ||||
6862 | * unless the Sink indicates support for the Q bit in a Video | ||||
6863 | * Capabilities Data Block." | ||||
6864 | * | ||||
6865 | * HDMI 2.0 recommends sending non-zero Q when it does match the | ||||
6866 | * default RGB quantization range for the mode, even when QS=0. | ||||
6867 | */ | ||||
6868 | if (info->rgb_quant_range_selectable || | ||||
6869 | rgb_quant_range == drm_default_rgb_quant_range(mode)) | ||||
6870 | frame->quantization_range = rgb_quant_range; | ||||
6871 | else | ||||
6872 | frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; | ||||
6873 | |||||
6874 | /* | ||||
6875 | * CEA-861-F: | ||||
6876 | * "When transmitting any RGB colorimetry, the Source should set the | ||||
6877 | * YQ-field to match the RGB Quantization Range being transmitted | ||||
6878 | * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, | ||||
6879 | * set YQ=1) and the Sink shall ignore the YQ-field." | ||||
6880 | * | ||||
6881 | * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused | ||||
6882 | * by non-zero YQ when receiving RGB. There doesn't seem to be any | ||||
6883 | * good way to tell which version of CEA-861 the sink supports, so | ||||
6884 | * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based | ||||
6885 | * on on CEA-861-F. | ||||
6886 | */ | ||||
6887 | if (!is_hdmi2_sink(connector) || | ||||
6888 | rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) | ||||
6889 | frame->ycc_quantization_range = | ||||
6890 | HDMI_YCC_QUANTIZATION_RANGE_LIMITED; | ||||
6891 | else | ||||
6892 | frame->ycc_quantization_range = | ||||
6893 | HDMI_YCC_QUANTIZATION_RANGE_FULL; | ||||
6894 | } | ||||
6895 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); | ||||
6896 | |||||
6897 | static enum hdmi_3d_structure | ||||
6898 | s3d_structure_from_display_mode(const struct drm_display_mode *mode) | ||||
6899 | { | ||||
6900 | u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK(0x1f<<14); | ||||
6901 | |||||
6902 | switch (layout) { | ||||
6903 | case DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14): | ||||
6904 | return HDMI_3D_STRUCTURE_FRAME_PACKING; | ||||
6905 | case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE(2<<14): | ||||
6906 | return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; | ||||
6907 | case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE(3<<14): | ||||
6908 | return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; | ||||
6909 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL(4<<14): | ||||
6910 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; | ||||
6911 | case DRM_MODE_FLAG_3D_L_DEPTH(5<<14): | ||||
6912 | return HDMI_3D_STRUCTURE_L_DEPTH; | ||||
6913 | case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH(6<<14): | ||||
6914 | return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; | ||||
6915 | case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14): | ||||
6916 | return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; | ||||
6917 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14): | ||||
6918 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; | ||||
6919 | default: | ||||
6920 | return HDMI_3D_STRUCTURE_INVALID; | ||||
6921 | } | ||||
6922 | } | ||||
6923 | |||||
6924 | /** | ||||
6925 | * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with | ||||
6926 | * data from a DRM display mode | ||||
6927 | * @frame: HDMI vendor infoframe | ||||
6928 | * @connector: the connector | ||||
6929 | * @mode: DRM display mode | ||||
6930 | * | ||||
6931 | * Note that there's is a need to send HDMI vendor infoframes only when using a | ||||
6932 | * 4k or stereoscopic 3D mode. So when giving any other mode as input this | ||||
6933 | * function will return -EINVAL, error that can be safely ignored. | ||||
6934 | * | ||||
6935 | * Return: 0 on success or a negative error code on failure. | ||||
6936 | */ | ||||
6937 | int | ||||
6938 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, | ||||
6939 | const struct drm_connector *connector, | ||||
6940 | const struct drm_display_mode *mode) | ||||
6941 | { | ||||
6942 | /* | ||||
6943 | * FIXME: sil-sii8620 doesn't have a connector around when | ||||
6944 | * we need one, so we have to be prepared for a NULL connector. | ||||
6945 | */ | ||||
6946 | bool_Bool has_hdmi_infoframe = connector ? | ||||
6947 | connector->display_info.has_hdmi_infoframe : false0; | ||||
6948 | int err; | ||||
6949 | |||||
6950 | if (!frame || !mode) | ||||
6951 | return -EINVAL22; | ||||
6952 | |||||
6953 | if (!has_hdmi_infoframe) | ||||
6954 | return -EINVAL22; | ||||
6955 | |||||
6956 | err = hdmi_vendor_infoframe_init(frame); | ||||
6957 | if (err < 0) | ||||
6958 | return err; | ||||
6959 | |||||
6960 | /* | ||||
6961 | * Even if it's not absolutely necessary to send the infoframe | ||||
6962 | * (ie.vic==0 and s3d_struct==0) we will still send it if we | ||||
6963 | * know that the sink can handle it. This is based on a | ||||
6964 | * suggestion in HDMI 2.0 Appendix F. Apparently some sinks | ||||
6965 | * have trouble realizing that they should switch from 3D to 2D | ||||
6966 | * mode if the source simply stops sending the infoframe when | ||||
6967 | * it wants to switch from 3D to 2D. | ||||
6968 | */ | ||||
6969 | frame->vic = drm_mode_hdmi_vic(connector, mode); | ||||
6970 | frame->s3d_struct = s3d_structure_from_display_mode(mode); | ||||
6971 | |||||
6972 | return 0; | ||||
6973 | } | ||||
6974 | EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); | ||||
6975 | |||||
6976 | static void drm_parse_tiled_block(struct drm_connector *connector, | ||||
6977 | const struct displayid_block *block) | ||||
6978 | { | ||||
6979 | const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; | ||||
6980 | u16 w, h; | ||||
6981 | u8 tile_v_loc, tile_h_loc; | ||||
6982 | u8 num_v_tile, num_h_tile; | ||||
6983 | struct drm_tile_group *tg; | ||||
6984 | |||||
6985 | w = tile->tile_size[0] | tile->tile_size[1] << 8; | ||||
6986 | h = tile->tile_size[2] | tile->tile_size[3] << 8; | ||||
6987 | |||||
6988 | num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); | ||||
6989 | num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); | ||||
6990 | tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); | ||||
6991 | tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); | ||||
6992 | |||||
6993 | connector->has_tile = true1; | ||||
6994 | if (tile->tile_cap & 0x80) | ||||
6995 | connector->tile_is_single_monitor = true1; | ||||
6996 | |||||
6997 | connector->num_h_tile = num_h_tile + 1; | ||||
6998 | connector->num_v_tile = num_v_tile + 1; | ||||
6999 | connector->tile_h_loc = tile_h_loc; | ||||
7000 | connector->tile_v_loc = tile_v_loc; | ||||
7001 | connector->tile_h_size = w + 1; | ||||
7002 | connector->tile_v_size = h + 1; | ||||
7003 | |||||
7004 | DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap)___drm_dbg(((void *)0), DRM_UT_KMS, "tile cap 0x%x\n", tile-> tile_cap); | ||||
7005 | DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1)___drm_dbg(((void *)0), DRM_UT_KMS, "tile_size %d x %d\n", w + 1, h + 1); | ||||
7006 | DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "topo num tiles %dx%d, location %dx%d\n" , num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc) | ||||
7007 | num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc)___drm_dbg(((void *)0), DRM_UT_KMS, "topo num tiles %dx%d, location %dx%d\n" , num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); | ||||
7008 | DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2])___drm_dbg(((void *)0), DRM_UT_KMS, "vend %c%c%c\n", tile-> topology_id[0], tile->topology_id[1], tile->topology_id [2]); | ||||
7009 | |||||
7010 | tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); | ||||
7011 | if (!tg) | ||||
7012 | tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); | ||||
7013 | if (!tg) | ||||
7014 | return; | ||||
7015 | |||||
7016 | if (connector->tile_group != tg) { | ||||
7017 | /* if we haven't got a pointer, | ||||
7018 | take the reference, drop ref to old tile group */ | ||||
7019 | if (connector->tile_group) | ||||
7020 | drm_mode_put_tile_group(connector->dev, connector->tile_group); | ||||
7021 | connector->tile_group = tg; | ||||
7022 | } else { | ||||
7023 | /* if same tile group, then release the ref we just took. */ | ||||
7024 | drm_mode_put_tile_group(connector->dev, tg); | ||||
7025 | } | ||||
7026 | } | ||||
7027 | |||||
7028 | static void _drm_update_tile_info(struct drm_connector *connector, | ||||
7029 | const struct drm_edid *drm_edid) | ||||
7030 | { | ||||
7031 | const struct displayid_block *block; | ||||
7032 | struct displayid_iter iter; | ||||
7033 | |||||
7034 | connector->has_tile = false0; | ||||
7035 | |||||
7036 | displayid_iter_edid_begin(drm_edid, &iter); | ||||
7037 | displayid_iter_for_each(block, &iter)while (((block) = __displayid_iter_next(&iter))) { | ||||
7038 | if (block->tag == DATA_BLOCK_TILED_DISPLAY0x12) | ||||
7039 | drm_parse_tiled_block(connector, block); | ||||
7040 | } | ||||
7041 | displayid_iter_end(&iter); | ||||
7042 | |||||
7043 | if (!connector->has_tile && connector->tile_group) { | ||||
7044 | drm_mode_put_tile_group(connector->dev, connector->tile_group); | ||||
7045 | connector->tile_group = NULL((void *)0); | ||||
7046 | } | ||||
7047 | } |
1 | /* Public domain. */ |
2 | |
3 | #ifndef _LINUX_STRING_H |
4 | #define _LINUX_STRING_H |
5 | |
6 | #include <sys/types.h> |
7 | #include <sys/systm.h> |
8 | #include <sys/malloc.h> |
9 | #include <sys/stdint.h> |
10 | #include <sys/errno.h> |
11 | |
12 | #include <linux/compiler.h> |
13 | |
14 | void *memchr_inv(const void *, int, size_t); |
15 | |
16 | static inline void * |
17 | memset32(uint32_t *b, uint32_t c, size_t len) |
18 | { |
19 | uint32_t *dst = b; |
20 | while (len--) |
21 | *dst++ = c; |
22 | return b; |
23 | } |
24 | |
25 | static inline void * |
26 | memset64(uint64_t *b, uint64_t c, size_t len) |
27 | { |
28 | uint64_t *dst = b; |
29 | while (len--) |
30 | *dst++ = c; |
31 | return b; |
32 | } |
33 | |
34 | static inline void * |
35 | memset_p(void **p, void *v, size_t n) |
36 | { |
37 | #ifdef __LP64__1 |
38 | return memset64((uint64_t *)p, (uintptr_t)v, n); |
39 | #else |
40 | return memset32((uint32_t *)p, (uintptr_t)v, n); |
41 | #endif |
42 | } |
43 | |
44 | static inline void * |
45 | kmemdup(const void *src, size_t len, int flags) |
46 | { |
47 | void *p = malloc(len, M_DRM145, flags); |
48 | if (p) |
49 | memcpy(p, src, len)__builtin_memcpy((p), (src), (len)); |
50 | return (p); |
51 | } |
52 | |
53 | static inline void * |
54 | kstrdup(const char *str, int flags) |
55 | { |
56 | size_t len; |
57 | char *p; |
58 | |
59 | if (str == NULL((void *)0)) |
60 | return NULL((void *)0); |
61 | |
62 | len = strlen(str) + 1; |
63 | p = malloc(len, M_DRM145, flags); |
64 | if (p) |
65 | memcpy(p, str, len)__builtin_memcpy((p), (str), (len)); |
66 | return (p); |
67 | } |
68 | |
69 | static inline int |
70 | match_string(const char * const *array, size_t n, const char *str) |
71 | { |
72 | int i; |
73 | |
74 | for (i = 0; i < n; i++) { |
75 | if (array[i] == NULL((void *)0)) |
76 | break; |
77 | if (!strcmp(array[i], str)) |
78 | return i; |
79 | } |
80 | |
81 | return -EINVAL22; |
82 | } |
83 | |
84 | static inline ssize_t |
85 | strscpy(char *dst, const char *src, size_t dstsize) |
86 | { |
87 | ssize_t r; |
88 | r = strlcpy(dst, src, dstsize); |
89 | if (dstsize == 0 || r >= dstsize) |
90 | return -E2BIG7; |
91 | return r; |
92 | } |
93 | |
94 | static inline ssize_t |
95 | strscpy_pad(char *dst, const char *src, size_t dstsize) |
96 | { |
97 | memset(dst, 0, dstsize)__builtin_memset((dst), (0), (dstsize)); |
98 | return strscpy(dst, src, dstsize); |
99 | } |
100 | |
101 | #endif |