File: | dev/pci/drm/radeon/radeon_combios.c |
Warning: | line 2912, column 3 Value stored to 'rev' is never read |
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1 | /* |
2 | * Copyright 2004 ATI Technologies Inc., Markham, Ontario |
3 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
4 | * Copyright 2008 Red Hat Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
26 | */ |
27 | |
28 | #include <linux/pci.h> |
29 | |
30 | #include <drm/drm_device.h> |
31 | #include <drm/radeon_drm.h> |
32 | |
33 | #include "radeon.h" |
34 | #include "radeon_legacy_encoders.h" |
35 | #include "atom.h" |
36 | |
37 | #if defined(CONFIG_PPC_PMAC) && defined(__linux__) |
38 | /* not sure which of these are needed */ |
39 | #include <asm/machdep.h> |
40 | #include <asm/pmac_feature.h> |
41 | #include <asm/prom.h> |
42 | #elif defined(CONFIG_PPC_PMAC) |
43 | #include <linux/of.h> |
44 | #endif /* CONFIG_PPC_PMAC */ |
45 | |
46 | /* old legacy ATI BIOS routines */ |
47 | |
48 | /* COMBIOS table offsets */ |
49 | enum radeon_combios_table_offset { |
50 | /* absolute offset tables */ |
51 | COMBIOS_ASIC_INIT_1_TABLE, |
52 | COMBIOS_BIOS_SUPPORT_TABLE, |
53 | COMBIOS_DAC_PROGRAMMING_TABLE, |
54 | COMBIOS_MAX_COLOR_DEPTH_TABLE, |
55 | COMBIOS_CRTC_INFO_TABLE, |
56 | COMBIOS_PLL_INFO_TABLE, |
57 | COMBIOS_TV_INFO_TABLE, |
58 | COMBIOS_DFP_INFO_TABLE, |
59 | COMBIOS_HW_CONFIG_INFO_TABLE, |
60 | COMBIOS_MULTIMEDIA_INFO_TABLE, |
61 | COMBIOS_TV_STD_PATCH_TABLE, |
62 | COMBIOS_LCD_INFO_TABLE, |
63 | COMBIOS_MOBILE_INFO_TABLE, |
64 | COMBIOS_PLL_INIT_TABLE, |
65 | COMBIOS_MEM_CONFIG_TABLE, |
66 | COMBIOS_SAVE_MASK_TABLE, |
67 | COMBIOS_HARDCODED_EDID_TABLE, |
68 | COMBIOS_ASIC_INIT_2_TABLE, |
69 | COMBIOS_CONNECTOR_INFO_TABLE, |
70 | COMBIOS_DYN_CLK_1_TABLE, |
71 | COMBIOS_RESERVED_MEM_TABLE, |
72 | COMBIOS_EXT_TMDS_INFO_TABLE, |
73 | COMBIOS_MEM_CLK_INFO_TABLE, |
74 | COMBIOS_EXT_DAC_INFO_TABLE, |
75 | COMBIOS_MISC_INFO_TABLE, |
76 | COMBIOS_CRT_INFO_TABLE, |
77 | COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, |
78 | COMBIOS_COMPONENT_VIDEO_INFO_TABLE, |
79 | COMBIOS_FAN_SPEED_INFO_TABLE, |
80 | COMBIOS_OVERDRIVE_INFO_TABLE, |
81 | COMBIOS_OEM_INFO_TABLE, |
82 | COMBIOS_DYN_CLK_2_TABLE, |
83 | COMBIOS_POWER_CONNECTOR_INFO_TABLE, |
84 | COMBIOS_I2C_INFO_TABLE, |
85 | /* relative offset tables */ |
86 | COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ |
87 | COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ |
88 | COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ |
89 | COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ |
90 | COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ |
91 | COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ |
92 | COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ |
93 | COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ |
94 | COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ |
95 | COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ |
96 | COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ |
97 | }; |
98 | |
99 | enum radeon_combios_ddc { |
100 | DDC_NONE_DETECTED, |
101 | DDC_MONID, |
102 | DDC_DVI, |
103 | DDC_VGA, |
104 | DDC_CRT2, |
105 | DDC_LCD, |
106 | DDC_GPIO, |
107 | }; |
108 | |
109 | enum radeon_combios_connector { |
110 | CONNECTOR_NONE_LEGACY, |
111 | CONNECTOR_PROPRIETARY_LEGACY, |
112 | CONNECTOR_CRT_LEGACY, |
113 | CONNECTOR_DVI_I_LEGACY, |
114 | CONNECTOR_DVI_D_LEGACY, |
115 | CONNECTOR_CTV_LEGACY, |
116 | CONNECTOR_STV_LEGACY, |
117 | CONNECTOR_UNSUPPORTED_LEGACY |
118 | }; |
119 | |
120 | static const int legacy_connector_convert[] = { |
121 | DRM_MODE_CONNECTOR_Unknown0, |
122 | DRM_MODE_CONNECTOR_DVID3, |
123 | DRM_MODE_CONNECTOR_VGA1, |
124 | DRM_MODE_CONNECTOR_DVII2, |
125 | DRM_MODE_CONNECTOR_DVID3, |
126 | DRM_MODE_CONNECTOR_Composite5, |
127 | DRM_MODE_CONNECTOR_SVIDEO6, |
128 | DRM_MODE_CONNECTOR_Unknown0, |
129 | }; |
130 | |
131 | static uint16_t combios_get_table_offset(struct drm_device *dev, |
132 | enum radeon_combios_table_offset table) |
133 | { |
134 | struct radeon_device *rdev = dev->dev_private; |
135 | int rev, size; |
136 | uint16_t offset = 0, check_offset; |
137 | |
138 | if (!rdev->bios) |
139 | return 0; |
140 | |
141 | switch (table) { |
142 | /* absolute offset tables */ |
143 | case COMBIOS_ASIC_INIT_1_TABLE: |
144 | check_offset = 0xc; |
145 | break; |
146 | case COMBIOS_BIOS_SUPPORT_TABLE: |
147 | check_offset = 0x14; |
148 | break; |
149 | case COMBIOS_DAC_PROGRAMMING_TABLE: |
150 | check_offset = 0x2a; |
151 | break; |
152 | case COMBIOS_MAX_COLOR_DEPTH_TABLE: |
153 | check_offset = 0x2c; |
154 | break; |
155 | case COMBIOS_CRTC_INFO_TABLE: |
156 | check_offset = 0x2e; |
157 | break; |
158 | case COMBIOS_PLL_INFO_TABLE: |
159 | check_offset = 0x30; |
160 | break; |
161 | case COMBIOS_TV_INFO_TABLE: |
162 | check_offset = 0x32; |
163 | break; |
164 | case COMBIOS_DFP_INFO_TABLE: |
165 | check_offset = 0x34; |
166 | break; |
167 | case COMBIOS_HW_CONFIG_INFO_TABLE: |
168 | check_offset = 0x36; |
169 | break; |
170 | case COMBIOS_MULTIMEDIA_INFO_TABLE: |
171 | check_offset = 0x38; |
172 | break; |
173 | case COMBIOS_TV_STD_PATCH_TABLE: |
174 | check_offset = 0x3e; |
175 | break; |
176 | case COMBIOS_LCD_INFO_TABLE: |
177 | check_offset = 0x40; |
178 | break; |
179 | case COMBIOS_MOBILE_INFO_TABLE: |
180 | check_offset = 0x42; |
181 | break; |
182 | case COMBIOS_PLL_INIT_TABLE: |
183 | check_offset = 0x46; |
184 | break; |
185 | case COMBIOS_MEM_CONFIG_TABLE: |
186 | check_offset = 0x48; |
187 | break; |
188 | case COMBIOS_SAVE_MASK_TABLE: |
189 | check_offset = 0x4a; |
190 | break; |
191 | case COMBIOS_HARDCODED_EDID_TABLE: |
192 | check_offset = 0x4c; |
193 | break; |
194 | case COMBIOS_ASIC_INIT_2_TABLE: |
195 | check_offset = 0x4e; |
196 | break; |
197 | case COMBIOS_CONNECTOR_INFO_TABLE: |
198 | check_offset = 0x50; |
199 | break; |
200 | case COMBIOS_DYN_CLK_1_TABLE: |
201 | check_offset = 0x52; |
202 | break; |
203 | case COMBIOS_RESERVED_MEM_TABLE: |
204 | check_offset = 0x54; |
205 | break; |
206 | case COMBIOS_EXT_TMDS_INFO_TABLE: |
207 | check_offset = 0x58; |
208 | break; |
209 | case COMBIOS_MEM_CLK_INFO_TABLE: |
210 | check_offset = 0x5a; |
211 | break; |
212 | case COMBIOS_EXT_DAC_INFO_TABLE: |
213 | check_offset = 0x5c; |
214 | break; |
215 | case COMBIOS_MISC_INFO_TABLE: |
216 | check_offset = 0x5e; |
217 | break; |
218 | case COMBIOS_CRT_INFO_TABLE: |
219 | check_offset = 0x60; |
220 | break; |
221 | case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: |
222 | check_offset = 0x62; |
223 | break; |
224 | case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: |
225 | check_offset = 0x64; |
226 | break; |
227 | case COMBIOS_FAN_SPEED_INFO_TABLE: |
228 | check_offset = 0x66; |
229 | break; |
230 | case COMBIOS_OVERDRIVE_INFO_TABLE: |
231 | check_offset = 0x68; |
232 | break; |
233 | case COMBIOS_OEM_INFO_TABLE: |
234 | check_offset = 0x6a; |
235 | break; |
236 | case COMBIOS_DYN_CLK_2_TABLE: |
237 | check_offset = 0x6c; |
238 | break; |
239 | case COMBIOS_POWER_CONNECTOR_INFO_TABLE: |
240 | check_offset = 0x6e; |
241 | break; |
242 | case COMBIOS_I2C_INFO_TABLE: |
243 | check_offset = 0x70; |
244 | break; |
245 | /* relative offset tables */ |
246 | case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ |
247 | check_offset = |
248 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
249 | if (check_offset) { |
250 | rev = RBIOS8(check_offset)(rdev->bios[check_offset]); |
251 | if (rev > 0) { |
252 | check_offset = RBIOS16(check_offset + 0x3)((rdev->bios[check_offset + 0x3]) | ((rdev->bios[(check_offset + 0x3)+1]) << 8)); |
253 | if (check_offset) |
254 | offset = check_offset; |
255 | } |
256 | } |
257 | break; |
258 | case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ |
259 | check_offset = |
260 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
261 | if (check_offset) { |
262 | rev = RBIOS8(check_offset)(rdev->bios[check_offset]); |
263 | if (rev > 0) { |
264 | check_offset = RBIOS16(check_offset + 0x5)((rdev->bios[check_offset + 0x5]) | ((rdev->bios[(check_offset + 0x5)+1]) << 8)); |
265 | if (check_offset) |
266 | offset = check_offset; |
267 | } |
268 | } |
269 | break; |
270 | case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ |
271 | check_offset = |
272 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
273 | if (check_offset) { |
274 | rev = RBIOS8(check_offset)(rdev->bios[check_offset]); |
275 | if (rev > 0) { |
276 | check_offset = RBIOS16(check_offset + 0x7)((rdev->bios[check_offset + 0x7]) | ((rdev->bios[(check_offset + 0x7)+1]) << 8)); |
277 | if (check_offset) |
278 | offset = check_offset; |
279 | } |
280 | } |
281 | break; |
282 | case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ |
283 | check_offset = |
284 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); |
285 | if (check_offset) { |
286 | rev = RBIOS8(check_offset)(rdev->bios[check_offset]); |
287 | if (rev == 2) { |
288 | check_offset = RBIOS16(check_offset + 0x9)((rdev->bios[check_offset + 0x9]) | ((rdev->bios[(check_offset + 0x9)+1]) << 8)); |
289 | if (check_offset) |
290 | offset = check_offset; |
291 | } |
292 | } |
293 | break; |
294 | case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ |
295 | check_offset = |
296 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
297 | if (check_offset) { |
298 | while (RBIOS8(check_offset++)(rdev->bios[check_offset++])); |
299 | check_offset += 2; |
300 | if (check_offset) |
301 | offset = check_offset; |
302 | } |
303 | break; |
304 | case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ |
305 | check_offset = |
306 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
307 | if (check_offset) { |
308 | check_offset = RBIOS16(check_offset + 0x11)((rdev->bios[check_offset + 0x11]) | ((rdev->bios[(check_offset + 0x11)+1]) << 8)); |
309 | if (check_offset) |
310 | offset = check_offset; |
311 | } |
312 | break; |
313 | case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ |
314 | check_offset = |
315 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
316 | if (check_offset) { |
317 | check_offset = RBIOS16(check_offset + 0x13)((rdev->bios[check_offset + 0x13]) | ((rdev->bios[(check_offset + 0x13)+1]) << 8)); |
318 | if (check_offset) |
319 | offset = check_offset; |
320 | } |
321 | break; |
322 | case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ |
323 | check_offset = |
324 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
325 | if (check_offset) { |
326 | check_offset = RBIOS16(check_offset + 0x15)((rdev->bios[check_offset + 0x15]) | ((rdev->bios[(check_offset + 0x15)+1]) << 8)); |
327 | if (check_offset) |
328 | offset = check_offset; |
329 | } |
330 | break; |
331 | case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ |
332 | check_offset = |
333 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); |
334 | if (check_offset) { |
335 | check_offset = RBIOS16(check_offset + 0x17)((rdev->bios[check_offset + 0x17]) | ((rdev->bios[(check_offset + 0x17)+1]) << 8)); |
336 | if (check_offset) |
337 | offset = check_offset; |
338 | } |
339 | break; |
340 | case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ |
341 | check_offset = |
342 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); |
343 | if (check_offset) { |
344 | check_offset = RBIOS16(check_offset + 0x2)((rdev->bios[check_offset + 0x2]) | ((rdev->bios[(check_offset + 0x2)+1]) << 8)); |
345 | if (check_offset) |
346 | offset = check_offset; |
347 | } |
348 | break; |
349 | case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ |
350 | check_offset = |
351 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); |
352 | if (check_offset) { |
353 | check_offset = RBIOS16(check_offset + 0x4)((rdev->bios[check_offset + 0x4]) | ((rdev->bios[(check_offset + 0x4)+1]) << 8)); |
354 | if (check_offset) |
355 | offset = check_offset; |
356 | } |
357 | break; |
358 | default: |
359 | check_offset = 0; |
360 | break; |
361 | } |
362 | |
363 | size = RBIOS8(rdev->bios_header_start + 0x6)(rdev->bios[rdev->bios_header_start + 0x6]); |
364 | /* check absolute offset tables */ |
365 | if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) |
366 | offset = RBIOS16(rdev->bios_header_start + check_offset)((rdev->bios[rdev->bios_header_start + check_offset]) | ((rdev->bios[(rdev->bios_header_start + check_offset)+ 1]) << 8)); |
367 | |
368 | return offset; |
369 | } |
370 | |
371 | bool_Bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) |
372 | { |
373 | int edid_info, size; |
374 | struct edid *edid; |
375 | unsigned char *raw; |
376 | edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); |
377 | if (!edid_info) |
378 | return false0; |
379 | |
380 | raw = rdev->bios + edid_info; |
381 | size = EDID_LENGTH128 * (raw[0x7e] + 1); |
382 | edid = kmalloc(size, GFP_KERNEL(0x0001 | 0x0004)); |
383 | if (edid == NULL((void *)0)) |
384 | return false0; |
385 | |
386 | memcpy((unsigned char *)edid, raw, size)__builtin_memcpy(((unsigned char *)edid), (raw), (size)); |
387 | |
388 | if (!drm_edid_is_valid(edid)) { |
389 | kfree(edid); |
390 | return false0; |
391 | } |
392 | |
393 | rdev->mode_info.bios_hardcoded_edid = edid; |
394 | rdev->mode_info.bios_hardcoded_edid_size = size; |
395 | return true1; |
396 | } |
397 | |
398 | /* this is used for atom LCDs as well */ |
399 | struct edid * |
400 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) |
401 | { |
402 | struct edid *edid; |
403 | |
404 | if (rdev->mode_info.bios_hardcoded_edid) { |
405 | edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL(0x0001 | 0x0004)); |
406 | if (edid) { |
407 | memcpy((unsigned char *)edid,__builtin_memcpy(((unsigned char *)edid), ((unsigned char *)rdev ->mode_info.bios_hardcoded_edid), (rdev->mode_info.bios_hardcoded_edid_size )) |
408 | (unsigned char *)rdev->mode_info.bios_hardcoded_edid,__builtin_memcpy(((unsigned char *)edid), ((unsigned char *)rdev ->mode_info.bios_hardcoded_edid), (rdev->mode_info.bios_hardcoded_edid_size )) |
409 | rdev->mode_info.bios_hardcoded_edid_size)__builtin_memcpy(((unsigned char *)edid), ((unsigned char *)rdev ->mode_info.bios_hardcoded_edid), (rdev->mode_info.bios_hardcoded_edid_size )); |
410 | return edid; |
411 | } |
412 | } |
413 | return NULL((void *)0); |
414 | } |
415 | |
416 | #ifdef __clang__1 |
417 | static inline struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, |
418 | enum radeon_combios_ddc ddc, |
419 | u32 clk_mask, |
420 | u32 data_mask) |
421 | #else |
422 | static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, |
423 | enum radeon_combios_ddc ddc, |
424 | u32 clk_mask, |
425 | u32 data_mask) |
426 | #endif |
427 | { |
428 | struct radeon_i2c_bus_rec i2c; |
429 | int ddc_line = 0; |
430 | |
431 | /* ddc id = mask reg |
432 | * DDC_NONE_DETECTED = none |
433 | * DDC_DVI = RADEON_GPIO_DVI_DDC |
434 | * DDC_VGA = RADEON_GPIO_VGA_DDC |
435 | * DDC_LCD = RADEON_GPIOPAD_MASK |
436 | * DDC_GPIO = RADEON_MDGPIO_MASK |
437 | * r1xx |
438 | * DDC_MONID = RADEON_GPIO_MONID |
439 | * DDC_CRT2 = RADEON_GPIO_CRT2_DDC |
440 | * r200 |
441 | * DDC_MONID = RADEON_GPIO_MONID |
442 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
443 | * r300/r350 |
444 | * DDC_MONID = RADEON_GPIO_DVI_DDC |
445 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC |
446 | * rv2xx/rv3xx |
447 | * DDC_MONID = RADEON_GPIO_MONID |
448 | * DDC_CRT2 = RADEON_GPIO_MONID |
449 | * rs3xx/rs4xx |
450 | * DDC_MONID = RADEON_GPIOPAD_MASK |
451 | * DDC_CRT2 = RADEON_GPIO_MONID |
452 | */ |
453 | switch (ddc) { |
454 | case DDC_NONE_DETECTED: |
455 | default: |
456 | ddc_line = 0; |
457 | break; |
458 | case DDC_DVI: |
459 | ddc_line = RADEON_GPIO_DVI_DDC0x0064; |
460 | break; |
461 | case DDC_VGA: |
462 | ddc_line = RADEON_GPIO_VGA_DDC0x0060; |
463 | break; |
464 | case DDC_LCD: |
465 | ddc_line = RADEON_GPIOPAD_MASK0x0198; |
466 | break; |
467 | case DDC_GPIO: |
468 | ddc_line = RADEON_MDGPIO_MASK0x01a8; |
469 | break; |
470 | case DDC_MONID: |
471 | if (rdev->family == CHIP_RS300 || |
472 | rdev->family == CHIP_RS400 || |
473 | rdev->family == CHIP_RS480) |
474 | ddc_line = RADEON_GPIOPAD_MASK0x0198; |
475 | else if (rdev->family == CHIP_R300 || |
476 | rdev->family == CHIP_R350) { |
477 | ddc_line = RADEON_GPIO_DVI_DDC0x0064; |
478 | ddc = DDC_DVI; |
479 | } else |
480 | ddc_line = RADEON_GPIO_MONID0x0068; |
481 | break; |
482 | case DDC_CRT2: |
483 | if (rdev->family == CHIP_R200 || |
484 | rdev->family == CHIP_R300 || |
485 | rdev->family == CHIP_R350) { |
486 | ddc_line = RADEON_GPIO_DVI_DDC0x0064; |
487 | ddc = DDC_DVI; |
488 | } else if (rdev->family == CHIP_RS300 || |
489 | rdev->family == CHIP_RS400 || |
490 | rdev->family == CHIP_RS480) |
491 | ddc_line = RADEON_GPIO_MONID0x0068; |
492 | else if (rdev->family >= CHIP_RV350) { |
493 | ddc_line = RADEON_GPIO_MONID0x0068; |
494 | ddc = DDC_MONID; |
495 | } else |
496 | ddc_line = RADEON_GPIO_CRT2_DDC0x006c; |
497 | break; |
498 | } |
499 | |
500 | if (ddc_line == RADEON_GPIOPAD_MASK0x0198) { |
501 | i2c.mask_clk_reg = RADEON_GPIOPAD_MASK0x0198; |
502 | i2c.mask_data_reg = RADEON_GPIOPAD_MASK0x0198; |
503 | i2c.a_clk_reg = RADEON_GPIOPAD_A0x019c; |
504 | i2c.a_data_reg = RADEON_GPIOPAD_A0x019c; |
505 | i2c.en_clk_reg = RADEON_GPIOPAD_EN0x01a0; |
506 | i2c.en_data_reg = RADEON_GPIOPAD_EN0x01a0; |
507 | i2c.y_clk_reg = RADEON_GPIOPAD_Y0x01a4; |
508 | i2c.y_data_reg = RADEON_GPIOPAD_Y0x01a4; |
509 | } else if (ddc_line == RADEON_MDGPIO_MASK0x01a8) { |
510 | i2c.mask_clk_reg = RADEON_MDGPIO_MASK0x01a8; |
511 | i2c.mask_data_reg = RADEON_MDGPIO_MASK0x01a8; |
512 | i2c.a_clk_reg = RADEON_MDGPIO_A0x01ac; |
513 | i2c.a_data_reg = RADEON_MDGPIO_A0x01ac; |
514 | i2c.en_clk_reg = RADEON_MDGPIO_EN0x01b0; |
515 | i2c.en_data_reg = RADEON_MDGPIO_EN0x01b0; |
516 | i2c.y_clk_reg = RADEON_MDGPIO_Y0x01b4; |
517 | i2c.y_data_reg = RADEON_MDGPIO_Y0x01b4; |
518 | } else { |
519 | i2c.mask_clk_reg = ddc_line; |
520 | i2c.mask_data_reg = ddc_line; |
521 | i2c.a_clk_reg = ddc_line; |
522 | i2c.a_data_reg = ddc_line; |
523 | i2c.en_clk_reg = ddc_line; |
524 | i2c.en_data_reg = ddc_line; |
525 | i2c.y_clk_reg = ddc_line; |
526 | i2c.y_data_reg = ddc_line; |
527 | } |
528 | |
529 | if (clk_mask && data_mask) { |
530 | /* system specific masks */ |
531 | i2c.mask_clk_mask = clk_mask; |
532 | i2c.mask_data_mask = data_mask; |
533 | i2c.a_clk_mask = clk_mask; |
534 | i2c.a_data_mask = data_mask; |
535 | i2c.en_clk_mask = clk_mask; |
536 | i2c.en_data_mask = data_mask; |
537 | i2c.y_clk_mask = clk_mask; |
538 | i2c.y_data_mask = data_mask; |
539 | } else if ((ddc_line == RADEON_GPIOPAD_MASK0x0198) || |
540 | (ddc_line == RADEON_MDGPIO_MASK0x01a8)) { |
541 | /* default gpiopad masks */ |
542 | i2c.mask_clk_mask = (0x20 << 8); |
543 | i2c.mask_data_mask = 0x80; |
544 | i2c.a_clk_mask = (0x20 << 8); |
545 | i2c.a_data_mask = 0x80; |
546 | i2c.en_clk_mask = (0x20 << 8); |
547 | i2c.en_data_mask = 0x80; |
548 | i2c.y_clk_mask = (0x20 << 8); |
549 | i2c.y_data_mask = 0x80; |
550 | } else { |
551 | /* default masks for ddc pads */ |
552 | i2c.mask_clk_mask = RADEON_GPIO_MASK_1(1 << 25); |
553 | i2c.mask_data_mask = RADEON_GPIO_MASK_0(1 << 24); |
554 | i2c.a_clk_mask = RADEON_GPIO_A_1(1 << 1); |
555 | i2c.a_data_mask = RADEON_GPIO_A_0(1 << 0); |
556 | i2c.en_clk_mask = RADEON_GPIO_EN_1(1 << 17); |
557 | i2c.en_data_mask = RADEON_GPIO_EN_0(1 << 16); |
558 | i2c.y_clk_mask = RADEON_GPIO_Y_1(1 << 9); |
559 | i2c.y_data_mask = RADEON_GPIO_Y_0(1 << 8); |
560 | } |
561 | |
562 | switch (rdev->family) { |
563 | case CHIP_R100: |
564 | case CHIP_RV100: |
565 | case CHIP_RS100: |
566 | case CHIP_RV200: |
567 | case CHIP_RS200: |
568 | case CHIP_RS300: |
569 | switch (ddc_line) { |
570 | case RADEON_GPIO_DVI_DDC0x0064: |
571 | i2c.hw_capable = true1; |
572 | break; |
573 | default: |
574 | i2c.hw_capable = false0; |
575 | break; |
576 | } |
577 | break; |
578 | case CHIP_R200: |
579 | switch (ddc_line) { |
580 | case RADEON_GPIO_DVI_DDC0x0064: |
581 | case RADEON_GPIO_MONID0x0068: |
582 | i2c.hw_capable = true1; |
583 | break; |
584 | default: |
585 | i2c.hw_capable = false0; |
586 | break; |
587 | } |
588 | break; |
589 | case CHIP_RV250: |
590 | case CHIP_RV280: |
591 | switch (ddc_line) { |
592 | case RADEON_GPIO_VGA_DDC0x0060: |
593 | case RADEON_GPIO_DVI_DDC0x0064: |
594 | case RADEON_GPIO_CRT2_DDC0x006c: |
595 | i2c.hw_capable = true1; |
596 | break; |
597 | default: |
598 | i2c.hw_capable = false0; |
599 | break; |
600 | } |
601 | break; |
602 | case CHIP_R300: |
603 | case CHIP_R350: |
604 | switch (ddc_line) { |
605 | case RADEON_GPIO_VGA_DDC0x0060: |
606 | case RADEON_GPIO_DVI_DDC0x0064: |
607 | i2c.hw_capable = true1; |
608 | break; |
609 | default: |
610 | i2c.hw_capable = false0; |
611 | break; |
612 | } |
613 | break; |
614 | case CHIP_RV350: |
615 | case CHIP_RV380: |
616 | case CHIP_RS400: |
617 | case CHIP_RS480: |
618 | switch (ddc_line) { |
619 | case RADEON_GPIO_VGA_DDC0x0060: |
620 | case RADEON_GPIO_DVI_DDC0x0064: |
621 | i2c.hw_capable = true1; |
622 | break; |
623 | case RADEON_GPIO_MONID0x0068: |
624 | /* hw i2c on RADEON_GPIO_MONID doesn't seem to work |
625 | * reliably on some pre-r4xx hardware; not sure why. |
626 | */ |
627 | i2c.hw_capable = false0; |
628 | break; |
629 | default: |
630 | i2c.hw_capable = false0; |
631 | break; |
632 | } |
633 | break; |
634 | default: |
635 | i2c.hw_capable = false0; |
636 | break; |
637 | } |
638 | i2c.mm_i2c = false0; |
639 | |
640 | i2c.i2c_id = ddc; |
641 | i2c.hpd = RADEON_HPD_NONE; |
642 | |
643 | if (ddc_line) |
644 | i2c.valid = true1; |
645 | else |
646 | i2c.valid = false0; |
647 | |
648 | return i2c; |
649 | } |
650 | |
651 | static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) |
652 | { |
653 | struct drm_device *dev = rdev->ddev; |
654 | struct radeon_i2c_bus_rec i2c; |
655 | u16 offset; |
656 | u8 id, blocks, clk, data; |
657 | int i; |
658 | |
659 | i2c.valid = false0; |
660 | |
661 | offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); |
662 | if (offset) { |
663 | blocks = RBIOS8(offset + 2)(rdev->bios[offset + 2]); |
664 | for (i = 0; i < blocks; i++) { |
665 | id = RBIOS8(offset + 3 + (i * 5) + 0)(rdev->bios[offset + 3 + (i * 5) + 0]); |
666 | if (id == 136) { |
667 | clk = RBIOS8(offset + 3 + (i * 5) + 3)(rdev->bios[offset + 3 + (i * 5) + 3]); |
668 | data = RBIOS8(offset + 3 + (i * 5) + 4)(rdev->bios[offset + 3 + (i * 5) + 4]); |
669 | /* gpiopad */ |
670 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, |
671 | (1 << clk), (1 << data)); |
672 | break; |
673 | } |
674 | } |
675 | } |
676 | return i2c; |
677 | } |
678 | |
679 | void radeon_combios_i2c_init(struct radeon_device *rdev) |
680 | { |
681 | struct drm_device *dev = rdev->ddev; |
682 | struct radeon_i2c_bus_rec i2c; |
683 | |
684 | /* actual hw pads |
685 | * r1xx/rs2xx/rs3xx |
686 | * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm |
687 | * r200 |
688 | * 0x60, 0x64, 0x68, mm |
689 | * r300/r350 |
690 | * 0x60, 0x64, mm |
691 | * rv2xx/rv3xx/rs4xx |
692 | * 0x60, 0x64, 0x68, gpiopads, mm |
693 | */ |
694 | |
695 | /* 0x60 */ |
696 | i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
697 | rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); |
698 | /* 0x64 */ |
699 | i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
700 | rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); |
701 | |
702 | /* mm i2c */ |
703 | i2c.valid = true1; |
704 | i2c.hw_capable = true1; |
705 | i2c.mm_i2c = true1; |
706 | i2c.i2c_id = 0xa0; |
707 | rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); |
708 | |
709 | if (rdev->family == CHIP_R300 || |
710 | rdev->family == CHIP_R350) { |
711 | /* only 2 sw i2c pads */ |
712 | } else if (rdev->family == CHIP_RS300 || |
713 | rdev->family == CHIP_RS400 || |
714 | rdev->family == CHIP_RS480) { |
715 | /* 0x68 */ |
716 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
717 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
718 | |
719 | /* gpiopad */ |
720 | i2c = radeon_combios_get_i2c_info_from_table(rdev); |
721 | if (i2c.valid) |
722 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); |
723 | } else if ((rdev->family == CHIP_R200) || |
724 | (rdev->family >= CHIP_R300)) { |
725 | /* 0x68 */ |
726 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
727 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
728 | } else { |
729 | /* 0x68 */ |
730 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
731 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
732 | /* 0x6c */ |
733 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
734 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); |
735 | } |
736 | } |
737 | |
738 | bool_Bool radeon_combios_get_clock_info(struct drm_device *dev) |
739 | { |
740 | struct radeon_device *rdev = dev->dev_private; |
741 | uint16_t pll_info; |
742 | struct radeon_pll *p1pll = &rdev->clock.p1pll; |
743 | struct radeon_pll *p2pll = &rdev->clock.p2pll; |
744 | struct radeon_pll *spll = &rdev->clock.spll; |
745 | struct radeon_pll *mpll = &rdev->clock.mpll; |
746 | int8_t rev; |
747 | uint16_t sclk, mclk; |
748 | |
749 | pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); |
750 | if (pll_info) { |
751 | rev = RBIOS8(pll_info)(rdev->bios[pll_info]); |
752 | |
753 | /* pixel clocks */ |
754 | p1pll->reference_freq = RBIOS16(pll_info + 0xe)((rdev->bios[pll_info + 0xe]) | ((rdev->bios[(pll_info + 0xe)+1]) << 8)); |
755 | p1pll->reference_div = RBIOS16(pll_info + 0x10)((rdev->bios[pll_info + 0x10]) | ((rdev->bios[(pll_info + 0x10)+1]) << 8)); |
756 | p1pll->pll_out_min = RBIOS32(pll_info + 0x12)((((rdev->bios[pll_info + 0x12]) | ((rdev->bios[(pll_info + 0x12)+1]) << 8))) | (((rdev->bios[(pll_info + 0x12 )+2]) | ((rdev->bios[((pll_info + 0x12)+2)+1]) << 8) ) << 16)); |
757 | p1pll->pll_out_max = RBIOS32(pll_info + 0x16)((((rdev->bios[pll_info + 0x16]) | ((rdev->bios[(pll_info + 0x16)+1]) << 8))) | (((rdev->bios[(pll_info + 0x16 )+2]) | ((rdev->bios[((pll_info + 0x16)+2)+1]) << 8) ) << 16)); |
758 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
759 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
760 | |
761 | if (rev > 9) { |
762 | p1pll->pll_in_min = RBIOS32(pll_info + 0x36)((((rdev->bios[pll_info + 0x36]) | ((rdev->bios[(pll_info + 0x36)+1]) << 8))) | (((rdev->bios[(pll_info + 0x36 )+2]) | ((rdev->bios[((pll_info + 0x36)+2)+1]) << 8) ) << 16)); |
763 | p1pll->pll_in_max = RBIOS32(pll_info + 0x3a)((((rdev->bios[pll_info + 0x3a]) | ((rdev->bios[(pll_info + 0x3a)+1]) << 8))) | (((rdev->bios[(pll_info + 0x3a )+2]) | ((rdev->bios[((pll_info + 0x3a)+2)+1]) << 8) ) << 16)); |
764 | } else { |
765 | p1pll->pll_in_min = 40; |
766 | p1pll->pll_in_max = 500; |
767 | } |
768 | *p2pll = *p1pll; |
769 | |
770 | /* system clock */ |
771 | spll->reference_freq = RBIOS16(pll_info + 0x1a)((rdev->bios[pll_info + 0x1a]) | ((rdev->bios[(pll_info + 0x1a)+1]) << 8)); |
772 | spll->reference_div = RBIOS16(pll_info + 0x1c)((rdev->bios[pll_info + 0x1c]) | ((rdev->bios[(pll_info + 0x1c)+1]) << 8)); |
773 | spll->pll_out_min = RBIOS32(pll_info + 0x1e)((((rdev->bios[pll_info + 0x1e]) | ((rdev->bios[(pll_info + 0x1e)+1]) << 8))) | (((rdev->bios[(pll_info + 0x1e )+2]) | ((rdev->bios[((pll_info + 0x1e)+2)+1]) << 8) ) << 16)); |
774 | spll->pll_out_max = RBIOS32(pll_info + 0x22)((((rdev->bios[pll_info + 0x22]) | ((rdev->bios[(pll_info + 0x22)+1]) << 8))) | (((rdev->bios[(pll_info + 0x22 )+2]) | ((rdev->bios[((pll_info + 0x22)+2)+1]) << 8) ) << 16)); |
775 | |
776 | if (rev > 10) { |
777 | spll->pll_in_min = RBIOS32(pll_info + 0x48)((((rdev->bios[pll_info + 0x48]) | ((rdev->bios[(pll_info + 0x48)+1]) << 8))) | (((rdev->bios[(pll_info + 0x48 )+2]) | ((rdev->bios[((pll_info + 0x48)+2)+1]) << 8) ) << 16)); |
778 | spll->pll_in_max = RBIOS32(pll_info + 0x4c)((((rdev->bios[pll_info + 0x4c]) | ((rdev->bios[(pll_info + 0x4c)+1]) << 8))) | (((rdev->bios[(pll_info + 0x4c )+2]) | ((rdev->bios[((pll_info + 0x4c)+2)+1]) << 8) ) << 16)); |
779 | } else { |
780 | /* ??? */ |
781 | spll->pll_in_min = 40; |
782 | spll->pll_in_max = 500; |
783 | } |
784 | |
785 | /* memory clock */ |
786 | mpll->reference_freq = RBIOS16(pll_info + 0x26)((rdev->bios[pll_info + 0x26]) | ((rdev->bios[(pll_info + 0x26)+1]) << 8)); |
787 | mpll->reference_div = RBIOS16(pll_info + 0x28)((rdev->bios[pll_info + 0x28]) | ((rdev->bios[(pll_info + 0x28)+1]) << 8)); |
788 | mpll->pll_out_min = RBIOS32(pll_info + 0x2a)((((rdev->bios[pll_info + 0x2a]) | ((rdev->bios[(pll_info + 0x2a)+1]) << 8))) | (((rdev->bios[(pll_info + 0x2a )+2]) | ((rdev->bios[((pll_info + 0x2a)+2)+1]) << 8) ) << 16)); |
789 | mpll->pll_out_max = RBIOS32(pll_info + 0x2e)((((rdev->bios[pll_info + 0x2e]) | ((rdev->bios[(pll_info + 0x2e)+1]) << 8))) | (((rdev->bios[(pll_info + 0x2e )+2]) | ((rdev->bios[((pll_info + 0x2e)+2)+1]) << 8) ) << 16)); |
790 | |
791 | if (rev > 10) { |
792 | mpll->pll_in_min = RBIOS32(pll_info + 0x5a)((((rdev->bios[pll_info + 0x5a]) | ((rdev->bios[(pll_info + 0x5a)+1]) << 8))) | (((rdev->bios[(pll_info + 0x5a )+2]) | ((rdev->bios[((pll_info + 0x5a)+2)+1]) << 8) ) << 16)); |
793 | mpll->pll_in_max = RBIOS32(pll_info + 0x5e)((((rdev->bios[pll_info + 0x5e]) | ((rdev->bios[(pll_info + 0x5e)+1]) << 8))) | (((rdev->bios[(pll_info + 0x5e )+2]) | ((rdev->bios[((pll_info + 0x5e)+2)+1]) << 8) ) << 16)); |
794 | } else { |
795 | /* ??? */ |
796 | mpll->pll_in_min = 40; |
797 | mpll->pll_in_max = 500; |
798 | } |
799 | |
800 | /* default sclk/mclk */ |
801 | sclk = RBIOS16(pll_info + 0xa)((rdev->bios[pll_info + 0xa]) | ((rdev->bios[(pll_info + 0xa)+1]) << 8)); |
802 | mclk = RBIOS16(pll_info + 0x8)((rdev->bios[pll_info + 0x8]) | ((rdev->bios[(pll_info + 0x8)+1]) << 8)); |
803 | if (sclk == 0) |
804 | sclk = 200 * 100; |
805 | if (mclk == 0) |
806 | mclk = 200 * 100; |
807 | |
808 | rdev->clock.default_sclk = sclk; |
809 | rdev->clock.default_mclk = mclk; |
810 | |
811 | if (RBIOS32(pll_info + 0x16)((((rdev->bios[pll_info + 0x16]) | ((rdev->bios[(pll_info + 0x16)+1]) << 8))) | (((rdev->bios[(pll_info + 0x16 )+2]) | ((rdev->bios[((pll_info + 0x16)+2)+1]) << 8) ) << 16))) |
812 | rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16)((((rdev->bios[pll_info + 0x16]) | ((rdev->bios[(pll_info + 0x16)+1]) << 8))) | (((rdev->bios[(pll_info + 0x16 )+2]) | ((rdev->bios[((pll_info + 0x16)+2)+1]) << 8) ) << 16)); |
813 | else |
814 | rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ |
815 | |
816 | return true1; |
817 | } |
818 | return false0; |
819 | } |
820 | |
821 | bool_Bool radeon_combios_sideport_present(struct radeon_device *rdev) |
822 | { |
823 | struct drm_device *dev = rdev->ddev; |
824 | u16 igp_info; |
825 | |
826 | /* sideport is AMD only */ |
827 | if (rdev->family == CHIP_RS400) |
828 | return false0; |
829 | |
830 | igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); |
831 | |
832 | if (igp_info) { |
833 | if (RBIOS16(igp_info + 0x4)((rdev->bios[igp_info + 0x4]) | ((rdev->bios[(igp_info + 0x4)+1]) << 8))) |
834 | return true1; |
835 | } |
836 | return false0; |
837 | } |
838 | |
839 | static const uint32_t default_primarydac_adj[CHIP_LAST] = { |
840 | 0x00000808, /* r100 */ |
841 | 0x00000808, /* rv100 */ |
842 | 0x00000808, /* rs100 */ |
843 | 0x00000808, /* rv200 */ |
844 | 0x00000808, /* rs200 */ |
845 | 0x00000808, /* r200 */ |
846 | 0x00000808, /* rv250 */ |
847 | 0x00000000, /* rs300 */ |
848 | 0x00000808, /* rv280 */ |
849 | 0x00000808, /* r300 */ |
850 | 0x00000808, /* r350 */ |
851 | 0x00000808, /* rv350 */ |
852 | 0x00000808, /* rv380 */ |
853 | 0x00000808, /* r420 */ |
854 | 0x00000808, /* r423 */ |
855 | 0x00000808, /* rv410 */ |
856 | 0x00000000, /* rs400 */ |
857 | 0x00000000, /* rs480 */ |
858 | }; |
859 | |
860 | static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, |
861 | struct radeon_encoder_primary_dac *p_dac) |
862 | { |
863 | p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; |
864 | return; |
865 | } |
866 | |
867 | struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct |
868 | radeon_encoder |
869 | *encoder) |
870 | { |
871 | struct drm_device *dev = encoder->base.dev; |
872 | struct radeon_device *rdev = dev->dev_private; |
873 | uint16_t dac_info; |
874 | uint8_t rev, bg, dac; |
875 | struct radeon_encoder_primary_dac *p_dac = NULL((void *)0); |
876 | int found = 0; |
877 | |
878 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), |
879 | GFP_KERNEL(0x0001 | 0x0004)); |
880 | |
881 | if (!p_dac) |
882 | return NULL((void *)0); |
883 | |
884 | /* check CRT table */ |
885 | dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
886 | if (dac_info) { |
887 | rev = RBIOS8(dac_info)(rdev->bios[dac_info]) & 0x3; |
888 | if (rev < 2) { |
889 | bg = RBIOS8(dac_info + 0x2)(rdev->bios[dac_info + 0x2]) & 0xf; |
890 | dac = (RBIOS8(dac_info + 0x2)(rdev->bios[dac_info + 0x2]) >> 4) & 0xf; |
891 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
892 | } else { |
893 | bg = RBIOS8(dac_info + 0x2)(rdev->bios[dac_info + 0x2]) & 0xf; |
894 | dac = RBIOS8(dac_info + 0x3)(rdev->bios[dac_info + 0x3]) & 0xf; |
895 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
896 | } |
897 | /* if the values are zeros, use the table */ |
898 | if ((dac == 0) || (bg == 0)) |
899 | found = 0; |
900 | else |
901 | found = 1; |
902 | } |
903 | |
904 | /* quirks */ |
905 | /* Radeon 7000 (RV100) */ |
906 | if (((rdev->pdev->device == 0x5159) && |
907 | (rdev->pdev->subsystem_vendor == 0x174B) && |
908 | (rdev->pdev->subsystem_device == 0x7c28)) || |
909 | /* Radeon 9100 (R200) */ |
910 | ((rdev->pdev->device == 0x514D) && |
911 | (rdev->pdev->subsystem_vendor == 0x174B) && |
912 | (rdev->pdev->subsystem_device == 0x7149))) { |
913 | /* vbios value is bad, use the default */ |
914 | found = 0; |
915 | } |
916 | |
917 | if (!found) /* fallback to defaults */ |
918 | radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); |
919 | |
920 | return p_dac; |
921 | } |
922 | |
923 | enum radeon_tv_std |
924 | radeon_combios_get_tv_info(struct radeon_device *rdev) |
925 | { |
926 | struct drm_device *dev = rdev->ddev; |
927 | uint16_t tv_info; |
928 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
929 | |
930 | tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
931 | if (tv_info) { |
932 | if (RBIOS8(tv_info + 6)(rdev->bios[tv_info + 6]) == 'T') { |
933 | switch (RBIOS8(tv_info + 7)(rdev->bios[tv_info + 7]) & 0xf) { |
934 | case 1: |
935 | tv_std = TV_STD_NTSC; |
936 | DRM_DEBUG_KMS("Default TV standard: NTSC\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Default TV standard: NTSC\n" ); |
937 | break; |
938 | case 2: |
939 | tv_std = TV_STD_PAL; |
940 | DRM_DEBUG_KMS("Default TV standard: PAL\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Default TV standard: PAL\n" ); |
941 | break; |
942 | case 3: |
943 | tv_std = TV_STD_PAL_M; |
944 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Default TV standard: PAL-M\n" ); |
945 | break; |
946 | case 4: |
947 | tv_std = TV_STD_PAL_60; |
948 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Default TV standard: PAL-60\n" ); |
949 | break; |
950 | case 5: |
951 | tv_std = TV_STD_NTSC_J; |
952 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Default TV standard: NTSC-J\n" ); |
953 | break; |
954 | case 6: |
955 | tv_std = TV_STD_SCART_PAL; |
956 | DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Default TV standard: SCART-PAL\n" ); |
957 | break; |
958 | default: |
959 | tv_std = TV_STD_NTSC; |
960 | DRM_DEBUG_KMS___drm_dbg(((void *)0), DRM_UT_KMS, "Unknown TV standard; defaulting to NTSC\n" ) |
961 | ("Unknown TV standard; defaulting to NTSC\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Unknown TV standard; defaulting to NTSC\n" ); |
962 | break; |
963 | } |
964 | |
965 | switch ((RBIOS8(tv_info + 9)(rdev->bios[tv_info + 9]) >> 2) & 0x3) { |
966 | case 0: |
967 | DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n")___drm_dbg(((void *)0), DRM_UT_KMS, "29.498928713 MHz TV ref clk\n" ); |
968 | break; |
969 | case 1: |
970 | DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n")___drm_dbg(((void *)0), DRM_UT_KMS, "28.636360000 MHz TV ref clk\n" ); |
971 | break; |
972 | case 2: |
973 | DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n")___drm_dbg(((void *)0), DRM_UT_KMS, "14.318180000 MHz TV ref clk\n" ); |
974 | break; |
975 | case 3: |
976 | DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n")___drm_dbg(((void *)0), DRM_UT_KMS, "27.000000000 MHz TV ref clk\n" ); |
977 | break; |
978 | default: |
979 | break; |
980 | } |
981 | } |
982 | } |
983 | return tv_std; |
984 | } |
985 | |
986 | static const uint32_t default_tvdac_adj[CHIP_LAST] = { |
987 | 0x00000000, /* r100 */ |
988 | 0x00280000, /* rv100 */ |
989 | 0x00000000, /* rs100 */ |
990 | 0x00880000, /* rv200 */ |
991 | 0x00000000, /* rs200 */ |
992 | 0x00000000, /* r200 */ |
993 | 0x00770000, /* rv250 */ |
994 | 0x00290000, /* rs300 */ |
995 | 0x00560000, /* rv280 */ |
996 | 0x00780000, /* r300 */ |
997 | 0x00770000, /* r350 */ |
998 | 0x00780000, /* rv350 */ |
999 | 0x00780000, /* rv380 */ |
1000 | 0x01080000, /* r420 */ |
1001 | 0x01080000, /* r423 */ |
1002 | 0x01080000, /* rv410 */ |
1003 | 0x00780000, /* rs400 */ |
1004 | 0x00780000, /* rs480 */ |
1005 | }; |
1006 | |
1007 | static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, |
1008 | struct radeon_encoder_tv_dac *tv_dac) |
1009 | { |
1010 | tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; |
1011 | if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) |
1012 | tv_dac->ps2_tvdac_adj = 0x00880000; |
1013 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1014 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1015 | return; |
1016 | } |
1017 | |
1018 | struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct |
1019 | radeon_encoder |
1020 | *encoder) |
1021 | { |
1022 | struct drm_device *dev = encoder->base.dev; |
1023 | struct radeon_device *rdev = dev->dev_private; |
1024 | uint16_t dac_info; |
1025 | uint8_t rev, bg, dac; |
1026 | struct radeon_encoder_tv_dac *tv_dac = NULL((void *)0); |
1027 | int found = 0; |
1028 | |
1029 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL(0x0001 | 0x0004)); |
1030 | if (!tv_dac) |
1031 | return NULL((void *)0); |
1032 | |
1033 | /* first check TV table */ |
1034 | dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
1035 | if (dac_info) { |
1036 | rev = RBIOS8(dac_info + 0x3)(rdev->bios[dac_info + 0x3]); |
1037 | if (rev > 4) { |
1038 | bg = RBIOS8(dac_info + 0xc)(rdev->bios[dac_info + 0xc]) & 0xf; |
1039 | dac = RBIOS8(dac_info + 0xd)(rdev->bios[dac_info + 0xd]) & 0xf; |
1040 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
1041 | |
1042 | bg = RBIOS8(dac_info + 0xe)(rdev->bios[dac_info + 0xe]) & 0xf; |
1043 | dac = RBIOS8(dac_info + 0xf)(rdev->bios[dac_info + 0xf]) & 0xf; |
1044 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
1045 | |
1046 | bg = RBIOS8(dac_info + 0x10)(rdev->bios[dac_info + 0x10]) & 0xf; |
1047 | dac = RBIOS8(dac_info + 0x11)(rdev->bios[dac_info + 0x11]) & 0xf; |
1048 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
1049 | /* if the values are all zeros, use the table */ |
1050 | if (tv_dac->ps2_tvdac_adj) |
1051 | found = 1; |
1052 | } else if (rev > 1) { |
1053 | bg = RBIOS8(dac_info + 0xc)(rdev->bios[dac_info + 0xc]) & 0xf; |
1054 | dac = (RBIOS8(dac_info + 0xc)(rdev->bios[dac_info + 0xc]) >> 4) & 0xf; |
1055 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
1056 | |
1057 | bg = RBIOS8(dac_info + 0xd)(rdev->bios[dac_info + 0xd]) & 0xf; |
1058 | dac = (RBIOS8(dac_info + 0xd)(rdev->bios[dac_info + 0xd]) >> 4) & 0xf; |
1059 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
1060 | |
1061 | bg = RBIOS8(dac_info + 0xe)(rdev->bios[dac_info + 0xe]) & 0xf; |
1062 | dac = (RBIOS8(dac_info + 0xe)(rdev->bios[dac_info + 0xe]) >> 4) & 0xf; |
1063 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
1064 | /* if the values are all zeros, use the table */ |
1065 | if (tv_dac->ps2_tvdac_adj) |
1066 | found = 1; |
1067 | } |
1068 | tv_dac->tv_std = radeon_combios_get_tv_info(rdev); |
1069 | } |
1070 | if (!found) { |
1071 | /* then check CRT table */ |
1072 | dac_info = |
1073 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
1074 | if (dac_info) { |
1075 | rev = RBIOS8(dac_info)(rdev->bios[dac_info]) & 0x3; |
1076 | if (rev < 2) { |
1077 | bg = RBIOS8(dac_info + 0x3)(rdev->bios[dac_info + 0x3]) & 0xf; |
1078 | dac = (RBIOS8(dac_info + 0x3)(rdev->bios[dac_info + 0x3]) >> 4) & 0xf; |
1079 | tv_dac->ps2_tvdac_adj = |
1080 | (bg << 16) | (dac << 20); |
1081 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1082 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1083 | /* if the values are all zeros, use the table */ |
1084 | if (tv_dac->ps2_tvdac_adj) |
1085 | found = 1; |
1086 | } else { |
1087 | bg = RBIOS8(dac_info + 0x4)(rdev->bios[dac_info + 0x4]) & 0xf; |
1088 | dac = RBIOS8(dac_info + 0x5)(rdev->bios[dac_info + 0x5]) & 0xf; |
1089 | tv_dac->ps2_tvdac_adj = |
1090 | (bg << 16) | (dac << 20); |
1091 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1092 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
1093 | /* if the values are all zeros, use the table */ |
1094 | if (tv_dac->ps2_tvdac_adj) |
1095 | found = 1; |
1096 | } |
1097 | } else { |
1098 | DRM_INFO("No TV DAC info found in BIOS\n")printk("\0016" "[" "drm" "] " "No TV DAC info found in BIOS\n" ); |
1099 | } |
1100 | } |
1101 | |
1102 | if (!found) /* fallback to defaults */ |
1103 | radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); |
1104 | |
1105 | return tv_dac; |
1106 | } |
1107 | |
1108 | static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct |
1109 | radeon_device |
1110 | *rdev) |
1111 | { |
1112 | struct radeon_encoder_lvds *lvds = NULL((void *)0); |
1113 | uint32_t fp_vert_stretch, fp_horz_stretch; |
1114 | uint32_t ppll_div_sel, ppll_val; |
1115 | uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL)r100_mm_rreg(rdev, (0x02ec), 0); |
1116 | |
1117 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL(0x0001 | 0x0004)); |
1118 | |
1119 | if (!lvds) |
1120 | return NULL((void *)0); |
1121 | |
1122 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH)r100_mm_rreg(rdev, (0x0290), 0); |
1123 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH)r100_mm_rreg(rdev, (0x028c), 0); |
1124 | |
1125 | /* These should be fail-safe defaults, fingers crossed */ |
1126 | lvds->panel_pwr_delay = 200; |
1127 | lvds->panel_vcc_delay = 2000; |
1128 | |
1129 | lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL)r100_mm_rreg(rdev, (0x02d0), 0); |
1130 | lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT16) & 0xf; |
1131 | lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT20) & 0xf; |
1132 | |
1133 | if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE(1 << 25)) |
1134 | lvds->native_mode.vdisplay = |
1135 | ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE(0xfff << 12)) >> |
1136 | RADEON_VERT_PANEL_SHIFT12) + 1; |
1137 | else |
1138 | lvds->native_mode.vdisplay = |
1139 | (RREG32(RADEON_CRTC_V_TOTAL_DISP)r100_mm_rreg(rdev, (0x0208), 0) >> 16) + 1; |
1140 | |
1141 | if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE(1 << 25)) |
1142 | lvds->native_mode.hdisplay = |
1143 | (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE(0x1ff << 16)) >> |
1144 | RADEON_HORZ_PANEL_SHIFT16) + 1) * 8; |
1145 | else |
1146 | lvds->native_mode.hdisplay = |
1147 | ((RREG32(RADEON_CRTC_H_TOTAL_DISP)r100_mm_rreg(rdev, (0x0200), 0) >> 16) + 1) * 8; |
1148 | |
1149 | if ((lvds->native_mode.hdisplay < 640) || |
1150 | (lvds->native_mode.vdisplay < 480)) { |
1151 | lvds->native_mode.hdisplay = 640; |
1152 | lvds->native_mode.vdisplay = 480; |
1153 | } |
1154 | |
1155 | ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1)ioread8((rdev->rmmio) + (0x0008 + 1)) & 0x3; |
1156 | ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel)rdev->pll_rreg(rdev, (0x0004 + ppll_div_sel)); |
1157 | if ((ppll_val & 0x000707ff) == 0x1bb) |
1158 | lvds->use_bios_dividers = false0; |
1159 | else { |
1160 | lvds->panel_ref_divider = |
1161 | RREG32_PLL(RADEON_PPLL_REF_DIV)rdev->pll_rreg(rdev, (0x0003)) & 0x3ff; |
1162 | lvds->panel_post_divider = (ppll_val >> 16) & 0x7; |
1163 | lvds->panel_fb_divider = ppll_val & 0x7ff; |
1164 | |
1165 | if ((lvds->panel_ref_divider != 0) && |
1166 | (lvds->panel_fb_divider > 3)) |
1167 | lvds->use_bios_dividers = true1; |
1168 | } |
1169 | lvds->panel_vcc_delay = 200; |
1170 | |
1171 | DRM_INFO("Panel info derived from registers\n")printk("\0016" "[" "drm" "] " "Panel info derived from registers\n" ); |
1172 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,printk("\0016" "[" "drm" "] " "Panel Size %dx%d\n", lvds-> native_mode.hdisplay, lvds->native_mode.vdisplay) |
1173 | lvds->native_mode.vdisplay)printk("\0016" "[" "drm" "] " "Panel Size %dx%d\n", lvds-> native_mode.hdisplay, lvds->native_mode.vdisplay); |
1174 | |
1175 | return lvds; |
1176 | } |
1177 | |
1178 | struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder |
1179 | *encoder) |
1180 | { |
1181 | struct drm_device *dev = encoder->base.dev; |
1182 | struct radeon_device *rdev = dev->dev_private; |
1183 | uint16_t lcd_info; |
1184 | uint32_t panel_setup; |
1185 | char stmp[30]; |
1186 | int tmp, i; |
1187 | struct radeon_encoder_lvds *lvds = NULL((void *)0); |
1188 | |
1189 | lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
1190 | |
1191 | if (lcd_info) { |
1192 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL(0x0001 | 0x0004)); |
1193 | |
1194 | if (!lvds) |
1195 | return NULL((void *)0); |
1196 | |
1197 | for (i = 0; i < 24; i++) |
1198 | stmp[i] = RBIOS8(lcd_info + i + 1)(rdev->bios[lcd_info + i + 1]); |
1199 | stmp[24] = 0; |
1200 | |
1201 | DRM_INFO("Panel ID String: %s\n", stmp)printk("\0016" "[" "drm" "] " "Panel ID String: %s\n", stmp); |
1202 | |
1203 | lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19)((rdev->bios[lcd_info + 0x19]) | ((rdev->bios[(lcd_info + 0x19)+1]) << 8)); |
1204 | lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b)((rdev->bios[lcd_info + 0x1b]) | ((rdev->bios[(lcd_info + 0x1b)+1]) << 8)); |
1205 | |
1206 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,printk("\0016" "[" "drm" "] " "Panel Size %dx%d\n", lvds-> native_mode.hdisplay, lvds->native_mode.vdisplay) |
1207 | lvds->native_mode.vdisplay)printk("\0016" "[" "drm" "] " "Panel Size %dx%d\n", lvds-> native_mode.hdisplay, lvds->native_mode.vdisplay); |
1208 | |
1209 | lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c)((rdev->bios[lcd_info + 0x2c]) | ((rdev->bios[(lcd_info + 0x2c)+1]) << 8)); |
1210 | lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000)({ u16 __min_a = (lvds->panel_vcc_delay); u16 __min_b = (2000 ); __min_a < __min_b ? __min_a : __min_b; }); |
1211 | |
1212 | lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24)(rdev->bios[lcd_info + 0x24]); |
1213 | lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38)((rdev->bios[lcd_info + 0x38]) | ((rdev->bios[(lcd_info + 0x38)+1]) << 8)) & 0xf; |
1214 | lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38)((rdev->bios[lcd_info + 0x38]) | ((rdev->bios[(lcd_info + 0x38)+1]) << 8)) >> 4) & 0xf; |
1215 | |
1216 | lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e)((rdev->bios[lcd_info + 0x2e]) | ((rdev->bios[(lcd_info + 0x2e)+1]) << 8)); |
1217 | lvds->panel_post_divider = RBIOS8(lcd_info + 0x30)(rdev->bios[lcd_info + 0x30]); |
1218 | lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31)((rdev->bios[lcd_info + 0x31]) | ((rdev->bios[(lcd_info + 0x31)+1]) << 8)); |
1219 | if ((lvds->panel_ref_divider != 0) && |
1220 | (lvds->panel_fb_divider > 3)) |
1221 | lvds->use_bios_dividers = true1; |
1222 | |
1223 | panel_setup = RBIOS32(lcd_info + 0x39)((((rdev->bios[lcd_info + 0x39]) | ((rdev->bios[(lcd_info + 0x39)+1]) << 8))) | (((rdev->bios[(lcd_info + 0x39 )+2]) | ((rdev->bios[((lcd_info + 0x39)+2)+1]) << 8) ) << 16)); |
1224 | lvds->lvds_gen_cntl = 0xff00; |
1225 | if (panel_setup & 0x1) |
1226 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT(1 << 3); |
1227 | |
1228 | if ((panel_setup >> 4) & 0x1) |
1229 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE(1 << 2); |
1230 | |
1231 | switch ((panel_setup >> 8) & 0x7) { |
1232 | case 0: |
1233 | lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM(0 << 4); |
1234 | break; |
1235 | case 1: |
1236 | lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY(1 << 4); |
1237 | break; |
1238 | case 2: |
1239 | lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY(2 << 4); |
1240 | break; |
1241 | default: |
1242 | break; |
1243 | } |
1244 | |
1245 | if ((panel_setup >> 16) & 0x1) |
1246 | lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW(1 << 20); |
1247 | |
1248 | if ((panel_setup >> 17) & 0x1) |
1249 | lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW(1 << 21); |
1250 | |
1251 | if ((panel_setup >> 18) & 0x1) |
1252 | lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW(1 << 22); |
1253 | |
1254 | if ((panel_setup >> 23) & 0x1) |
1255 | lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL(1 << 17); |
1256 | |
1257 | lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); |
1258 | |
1259 | for (i = 0; i < 32; i++) { |
1260 | tmp = RBIOS16(lcd_info + 64 + i * 2)((rdev->bios[lcd_info + 64 + i * 2]) | ((rdev->bios[(lcd_info + 64 + i * 2)+1]) << 8)); |
1261 | if (tmp == 0) |
1262 | break; |
1263 | |
1264 | if ((RBIOS16(tmp)((rdev->bios[tmp]) | ((rdev->bios[(tmp)+1]) << 8) ) == lvds->native_mode.hdisplay) && |
1265 | (RBIOS16(tmp + 2)((rdev->bios[tmp + 2]) | ((rdev->bios[(tmp + 2)+1]) << 8)) == lvds->native_mode.vdisplay)) { |
1266 | u32 hss = (RBIOS16(tmp + 21)((rdev->bios[tmp + 21]) | ((rdev->bios[(tmp + 21)+1]) << 8)) - RBIOS16(tmp + 19)((rdev->bios[tmp + 19]) | ((rdev->bios[(tmp + 19)+1]) << 8)) - 1) * 8; |
1267 | |
1268 | if (hss > lvds->native_mode.hdisplay) |
1269 | hss = (10 - 1) * 8; |
1270 | |
1271 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
1272 | (RBIOS16(tmp + 17)((rdev->bios[tmp + 17]) | ((rdev->bios[(tmp + 17)+1]) << 8)) - RBIOS16(tmp + 19)((rdev->bios[tmp + 19]) | ((rdev->bios[(tmp + 19)+1]) << 8))) * 8; |
1273 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
1274 | hss; |
1275 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
1276 | (RBIOS8(tmp + 23)(rdev->bios[tmp + 23]) * 8); |
1277 | |
1278 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
1279 | (RBIOS16(tmp + 24)((rdev->bios[tmp + 24]) | ((rdev->bios[(tmp + 24)+1]) << 8)) - RBIOS16(tmp + 26)((rdev->bios[tmp + 26]) | ((rdev->bios[(tmp + 26)+1]) << 8))); |
1280 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
1281 | ((RBIOS16(tmp + 28)((rdev->bios[tmp + 28]) | ((rdev->bios[(tmp + 28)+1]) << 8)) & 0x7ff) - RBIOS16(tmp + 26)((rdev->bios[tmp + 26]) | ((rdev->bios[(tmp + 26)+1]) << 8))); |
1282 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
1283 | ((RBIOS16(tmp + 28)((rdev->bios[tmp + 28]) | ((rdev->bios[(tmp + 28)+1]) << 8)) & 0xf800) >> 11); |
1284 | |
1285 | lvds->native_mode.clock = RBIOS16(tmp + 9)((rdev->bios[tmp + 9]) | ((rdev->bios[(tmp + 9)+1]) << 8)) * 10; |
1286 | lvds->native_mode.flags = 0; |
1287 | /* set crtc values */ |
1288 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V(1 << 0)); |
1289 | |
1290 | } |
1291 | } |
1292 | } else { |
1293 | DRM_INFO("No panel info found in BIOS\n")printk("\0016" "[" "drm" "] " "No panel info found in BIOS\n" ); |
1294 | lvds = radeon_legacy_get_lvds_info_from_regs(rdev); |
1295 | } |
1296 | |
1297 | if (lvds) |
1298 | encoder->native_mode = lvds->native_mode; |
1299 | return lvds; |
1300 | } |
1301 | |
1302 | static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { |
1303 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ |
1304 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ |
1305 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ |
1306 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ |
1307 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ |
1308 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ |
1309 | {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ |
1310 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ |
1311 | {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ |
1312 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ |
1313 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ |
1314 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ |
1315 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ |
1316 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ |
1317 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ |
1318 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ |
1319 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ |
1320 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ |
1321 | }; |
1322 | |
1323 | bool_Bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
1324 | struct radeon_encoder_int_tmds *tmds) |
1325 | { |
1326 | struct drm_device *dev = encoder->base.dev; |
1327 | struct radeon_device *rdev = dev->dev_private; |
1328 | int i; |
1329 | |
1330 | for (i = 0; i < 4; i++) { |
1331 | tmds->tmds_pll[i].value = |
1332 | default_tmds_pll[rdev->family][i].value; |
1333 | tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; |
1334 | } |
1335 | |
1336 | return true1; |
1337 | } |
1338 | |
1339 | bool_Bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
1340 | struct radeon_encoder_int_tmds *tmds) |
1341 | { |
1342 | struct drm_device *dev = encoder->base.dev; |
1343 | struct radeon_device *rdev = dev->dev_private; |
1344 | uint16_t tmds_info; |
1345 | int i, n; |
1346 | uint8_t ver; |
1347 | |
1348 | tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
1349 | |
1350 | if (tmds_info) { |
1351 | ver = RBIOS8(tmds_info)(rdev->bios[tmds_info]); |
1352 | DRM_DEBUG_KMS("DFP table revision: %d\n", ver)___drm_dbg(((void *)0), DRM_UT_KMS, "DFP table revision: %d\n" , ver); |
1353 | if (ver == 3) { |
1354 | n = RBIOS8(tmds_info + 5)(rdev->bios[tmds_info + 5]) + 1; |
1355 | if (n > 4) |
1356 | n = 4; |
1357 | for (i = 0; i < n; i++) { |
1358 | tmds->tmds_pll[i].value = |
1359 | RBIOS32(tmds_info + i * 10 + 0x08)((((rdev->bios[tmds_info + i * 10 + 0x08]) | ((rdev->bios [(tmds_info + i * 10 + 0x08)+1]) << 8))) | (((rdev-> bios[(tmds_info + i * 10 + 0x08)+2]) | ((rdev->bios[((tmds_info + i * 10 + 0x08)+2)+1]) << 8)) << 16)); |
1360 | tmds->tmds_pll[i].freq = |
1361 | RBIOS16(tmds_info + i * 10 + 0x10)((rdev->bios[tmds_info + i * 10 + 0x10]) | ((rdev->bios [(tmds_info + i * 10 + 0x10)+1]) << 8)); |
1362 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",___drm_dbg(((void *)0), DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n" , tmds->tmds_pll[i].freq, tmds->tmds_pll[i].value) |
1363 | tmds->tmds_pll[i].freq,___drm_dbg(((void *)0), DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n" , tmds->tmds_pll[i].freq, tmds->tmds_pll[i].value) |
1364 | tmds->tmds_pll[i].value)___drm_dbg(((void *)0), DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n" , tmds->tmds_pll[i].freq, tmds->tmds_pll[i].value); |
1365 | } |
1366 | } else if (ver == 4) { |
1367 | int stride = 0; |
1368 | n = RBIOS8(tmds_info + 5)(rdev->bios[tmds_info + 5]) + 1; |
1369 | if (n > 4) |
1370 | n = 4; |
1371 | for (i = 0; i < n; i++) { |
1372 | tmds->tmds_pll[i].value = |
1373 | RBIOS32(tmds_info + stride + 0x08)((((rdev->bios[tmds_info + stride + 0x08]) | ((rdev->bios [(tmds_info + stride + 0x08)+1]) << 8))) | (((rdev-> bios[(tmds_info + stride + 0x08)+2]) | ((rdev->bios[((tmds_info + stride + 0x08)+2)+1]) << 8)) << 16)); |
1374 | tmds->tmds_pll[i].freq = |
1375 | RBIOS16(tmds_info + stride + 0x10)((rdev->bios[tmds_info + stride + 0x10]) | ((rdev->bios [(tmds_info + stride + 0x10)+1]) << 8)); |
1376 | if (i == 0) |
1377 | stride += 10; |
1378 | else |
1379 | stride += 6; |
1380 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",___drm_dbg(((void *)0), DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n" , tmds->tmds_pll[i].freq, tmds->tmds_pll[i].value) |
1381 | tmds->tmds_pll[i].freq,___drm_dbg(((void *)0), DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n" , tmds->tmds_pll[i].freq, tmds->tmds_pll[i].value) |
1382 | tmds->tmds_pll[i].value)___drm_dbg(((void *)0), DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n" , tmds->tmds_pll[i].freq, tmds->tmds_pll[i].value); |
1383 | } |
1384 | } |
1385 | } else { |
1386 | DRM_INFO("No TMDS info found in BIOS\n")printk("\0016" "[" "drm" "] " "No TMDS info found in BIOS\n"); |
1387 | return false0; |
1388 | } |
1389 | return true1; |
1390 | } |
1391 | |
1392 | bool_Bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
1393 | struct radeon_encoder_ext_tmds *tmds) |
1394 | { |
1395 | struct drm_device *dev = encoder->base.dev; |
1396 | struct radeon_device *rdev = dev->dev_private; |
1397 | struct radeon_i2c_bus_rec i2c_bus; |
1398 | |
1399 | /* default for macs */ |
1400 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1401 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1402 | |
1403 | /* XXX some macs have duallink chips */ |
1404 | switch (rdev->mode_info.connector_table) { |
1405 | case CT_POWERBOOK_EXTERNAL: |
1406 | case CT_MINI_EXTERNAL: |
1407 | default: |
1408 | tmds->dvo_chip = DVO_SIL164; |
1409 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
1410 | break; |
1411 | } |
1412 | |
1413 | return true1; |
1414 | } |
1415 | |
1416 | bool_Bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
1417 | struct radeon_encoder_ext_tmds *tmds) |
1418 | { |
1419 | struct drm_device *dev = encoder->base.dev; |
1420 | struct radeon_device *rdev = dev->dev_private; |
1421 | uint16_t offset; |
1422 | uint8_t ver; |
1423 | enum radeon_combios_ddc gpio; |
1424 | struct radeon_i2c_bus_rec i2c_bus; |
1425 | |
1426 | tmds->i2c_bus = NULL((void *)0); |
1427 | if (rdev->flags & RADEON_IS_IGP) { |
1428 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1429 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1430 | tmds->dvo_chip = DVO_SIL164; |
1431 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
1432 | } else { |
1433 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
1434 | if (offset) { |
1435 | ver = RBIOS8(offset)(rdev->bios[offset]); |
1436 | DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver)___drm_dbg(((void *)0), DRM_UT_KMS, "External TMDS Table revision: %d\n" , ver); |
1437 | tmds->slave_addr = RBIOS8(offset + 4 + 2)(rdev->bios[offset + 4 + 2]); |
1438 | tmds->slave_addr >>= 1; /* 7 bit addressing */ |
1439 | gpio = RBIOS8(offset + 4 + 3)(rdev->bios[offset + 4 + 3]); |
1440 | if (gpio == DDC_LCD) { |
1441 | /* MM i2c */ |
1442 | i2c_bus.valid = true1; |
1443 | i2c_bus.hw_capable = true1; |
1444 | i2c_bus.mm_i2c = true1; |
1445 | i2c_bus.i2c_id = 0xa0; |
1446 | } else |
1447 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
1448 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
1449 | } |
1450 | } |
1451 | |
1452 | if (!tmds->i2c_bus) { |
1453 | DRM_INFO("No valid Ext TMDS info found in BIOS\n")printk("\0016" "[" "drm" "] " "No valid Ext TMDS info found in BIOS\n" ); |
1454 | return false0; |
1455 | } |
1456 | |
1457 | return true1; |
1458 | } |
1459 | |
1460 | bool_Bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) |
1461 | { |
1462 | struct radeon_device *rdev = dev->dev_private; |
1463 | struct radeon_i2c_bus_rec ddc_i2c; |
1464 | struct radeon_hpd hpd; |
1465 | |
1466 | rdev->mode_info.connector_table = radeon_connector_table; |
1467 | if (rdev->mode_info.connector_table == CT_NONE) { |
1468 | #ifdef CONFIG_PPC_PMAC |
1469 | if (of_machine_is_compatible("PowerBook3,3")) { |
1470 | /* powerbook with VGA */ |
1471 | rdev->mode_info.connector_table = CT_POWERBOOK_VGA; |
1472 | } else if (of_machine_is_compatible("PowerBook3,4") || |
1473 | of_machine_is_compatible("PowerBook3,5")) { |
1474 | /* powerbook with internal tmds */ |
1475 | rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; |
1476 | } else if (of_machine_is_compatible("PowerBook5,1") || |
1477 | of_machine_is_compatible("PowerBook5,2") || |
1478 | of_machine_is_compatible("PowerBook5,3") || |
1479 | of_machine_is_compatible("PowerBook5,4") || |
1480 | of_machine_is_compatible("PowerBook5,5")) { |
1481 | /* powerbook with external single link tmds (sil164) */ |
1482 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1483 | } else if (of_machine_is_compatible("PowerBook5,6")) { |
1484 | /* powerbook with external dual or single link tmds */ |
1485 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1486 | } else if (of_machine_is_compatible("PowerBook5,7") || |
1487 | of_machine_is_compatible("PowerBook5,8") || |
1488 | of_machine_is_compatible("PowerBook5,9")) { |
1489 | /* PowerBook6,2 ? */ |
1490 | /* powerbook with external dual link tmds (sil1178?) */ |
1491 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; |
1492 | } else if (of_machine_is_compatible("PowerBook4,1") || |
1493 | of_machine_is_compatible("PowerBook4,2") || |
1494 | of_machine_is_compatible("PowerBook4,3") || |
1495 | of_machine_is_compatible("PowerBook6,3") || |
1496 | of_machine_is_compatible("PowerBook6,5") || |
1497 | of_machine_is_compatible("PowerBook6,7")) { |
1498 | /* ibook */ |
1499 | rdev->mode_info.connector_table = CT_IBOOK; |
1500 | } else if (of_machine_is_compatible("PowerMac3,5")) { |
1501 | /* PowerMac G4 Silver radeon 7500 */ |
1502 | rdev->mode_info.connector_table = CT_MAC_G4_SILVER; |
1503 | } else if (of_machine_is_compatible("PowerMac4,4")) { |
1504 | /* emac */ |
1505 | rdev->mode_info.connector_table = CT_EMAC; |
1506 | } else if (of_machine_is_compatible("PowerMac10,1")) { |
1507 | /* mini with internal tmds */ |
1508 | rdev->mode_info.connector_table = CT_MINI_INTERNAL; |
1509 | } else if (of_machine_is_compatible("PowerMac10,2")) { |
1510 | /* mini with external tmds */ |
1511 | rdev->mode_info.connector_table = CT_MINI_EXTERNAL; |
1512 | } else if (of_machine_is_compatible("PowerMac12,1")) { |
1513 | /* PowerMac8,1 ? */ |
1514 | /* imac g5 isight */ |
1515 | rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; |
1516 | } else if ((rdev->pdev->device == 0x4a48) && |
1517 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1518 | (rdev->pdev->subsystem_device == 0x4a48)) { |
1519 | /* Mac X800 */ |
1520 | rdev->mode_info.connector_table = CT_MAC_X800; |
1521 | } else if ((of_machine_is_compatible("PowerMac7,2") || |
1522 | of_machine_is_compatible("PowerMac7,3")) && |
1523 | (rdev->pdev->device == 0x4150) && |
1524 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1525 | (rdev->pdev->subsystem_device == 0x4150)) { |
1526 | /* Mac G5 tower 9600 */ |
1527 | rdev->mode_info.connector_table = CT_MAC_G5_9600; |
1528 | } else if ((rdev->pdev->device == 0x4c66) && |
1529 | (rdev->pdev->subsystem_vendor == 0x1002) && |
1530 | (rdev->pdev->subsystem_device == 0x4c66)) { |
1531 | /* SAM440ep RV250 embedded board */ |
1532 | rdev->mode_info.connector_table = CT_SAM440EP; |
1533 | } else |
1534 | #endif /* CONFIG_PPC_PMAC */ |
1535 | #ifdef CONFIG_PPC64 |
1536 | if (ASIC_IS_RN50(rdev)((rdev->pdev->device == 0x515e) || (rdev->pdev->device == 0x5969))) |
1537 | rdev->mode_info.connector_table = CT_RN50_POWER; |
1538 | else |
1539 | #endif |
1540 | rdev->mode_info.connector_table = CT_GENERIC; |
1541 | } |
1542 | |
1543 | switch (rdev->mode_info.connector_table) { |
1544 | case CT_GENERIC: |
1545 | DRM_INFO("Connector Table: %d (generic)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (generic)\n" , rdev->mode_info.connector_table) |
1546 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (generic)\n" , rdev->mode_info.connector_table); |
1547 | /* these are the most common settings */ |
1548 | if (rdev->flags & RADEON_SINGLE_CRTC) { |
1549 | /* VGA - primary dac */ |
1550 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1551 | hpd.hpd = RADEON_HPD_NONE; |
1552 | radeon_add_legacy_encoder(dev, |
1553 | radeon_get_encoder_enum(dev, |
1554 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1555 | 1), |
1556 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
1557 | radeon_add_legacy_connector(dev, 0, |
1558 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1559 | DRM_MODE_CONNECTOR_VGA1, |
1560 | &ddc_i2c, |
1561 | CONNECTOR_OBJECT_ID_VGA0x05, |
1562 | &hpd); |
1563 | } else if (rdev->flags & RADEON_IS_MOBILITY) { |
1564 | /* LVDS */ |
1565 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
1566 | hpd.hpd = RADEON_HPD_NONE; |
1567 | radeon_add_legacy_encoder(dev, |
1568 | radeon_get_encoder_enum(dev, |
1569 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1570 | 0), |
1571 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )); |
1572 | radeon_add_legacy_connector(dev, 0, |
1573 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1574 | DRM_MODE_CONNECTOR_LVDS7, |
1575 | &ddc_i2c, |
1576 | CONNECTOR_OBJECT_ID_LVDS0x0E, |
1577 | &hpd); |
1578 | |
1579 | /* VGA - primary dac */ |
1580 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1581 | hpd.hpd = RADEON_HPD_NONE; |
1582 | radeon_add_legacy_encoder(dev, |
1583 | radeon_get_encoder_enum(dev, |
1584 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1585 | 1), |
1586 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
1587 | radeon_add_legacy_connector(dev, 1, |
1588 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1589 | DRM_MODE_CONNECTOR_VGA1, |
1590 | &ddc_i2c, |
1591 | CONNECTOR_OBJECT_ID_VGA0x05, |
1592 | &hpd); |
1593 | } else { |
1594 | /* DVI-I - tv dac, int tmds */ |
1595 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1596 | hpd.hpd = RADEON_HPD_1; |
1597 | radeon_add_legacy_encoder(dev, |
1598 | radeon_get_encoder_enum(dev, |
1599 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
1600 | 0), |
1601 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
1602 | radeon_add_legacy_encoder(dev, |
1603 | radeon_get_encoder_enum(dev, |
1604 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1605 | 2), |
1606 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
1607 | radeon_add_legacy_connector(dev, 0, |
1608 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) | |
1609 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1610 | DRM_MODE_CONNECTOR_DVII2, |
1611 | &ddc_i2c, |
1612 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
1613 | &hpd); |
1614 | |
1615 | /* VGA - primary dac */ |
1616 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1617 | hpd.hpd = RADEON_HPD_NONE; |
1618 | radeon_add_legacy_encoder(dev, |
1619 | radeon_get_encoder_enum(dev, |
1620 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1621 | 1), |
1622 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
1623 | radeon_add_legacy_connector(dev, 1, |
1624 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1625 | DRM_MODE_CONNECTOR_VGA1, |
1626 | &ddc_i2c, |
1627 | CONNECTOR_OBJECT_ID_VGA0x05, |
1628 | &hpd); |
1629 | } |
1630 | |
1631 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
1632 | /* TV - tv dac */ |
1633 | ddc_i2c.valid = false0; |
1634 | hpd.hpd = RADEON_HPD_NONE; |
1635 | radeon_add_legacy_encoder(dev, |
1636 | radeon_get_encoder_enum(dev, |
1637 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1638 | 2), |
1639 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1640 | radeon_add_legacy_connector(dev, 2, |
1641 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1642 | DRM_MODE_CONNECTOR_SVIDEO6, |
1643 | &ddc_i2c, |
1644 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1645 | &hpd); |
1646 | } |
1647 | break; |
1648 | case CT_IBOOK: |
1649 | DRM_INFO("Connector Table: %d (ibook)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (ibook)\n" , rdev->mode_info.connector_table) |
1650 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (ibook)\n" , rdev->mode_info.connector_table); |
1651 | /* LVDS */ |
1652 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1653 | hpd.hpd = RADEON_HPD_NONE; |
1654 | radeon_add_legacy_encoder(dev, |
1655 | radeon_get_encoder_enum(dev, |
1656 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1657 | 0), |
1658 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )); |
1659 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1660 | DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c, |
1661 | CONNECTOR_OBJECT_ID_LVDS0x0E, |
1662 | &hpd); |
1663 | /* VGA - TV DAC */ |
1664 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1665 | hpd.hpd = RADEON_HPD_NONE; |
1666 | radeon_add_legacy_encoder(dev, |
1667 | radeon_get_encoder_enum(dev, |
1668 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1669 | 2), |
1670 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
1671 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1672 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
1673 | CONNECTOR_OBJECT_ID_VGA0x05, |
1674 | &hpd); |
1675 | /* TV - TV DAC */ |
1676 | ddc_i2c.valid = false0; |
1677 | hpd.hpd = RADEON_HPD_NONE; |
1678 | radeon_add_legacy_encoder(dev, |
1679 | radeon_get_encoder_enum(dev, |
1680 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1681 | 2), |
1682 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1683 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1684 | DRM_MODE_CONNECTOR_SVIDEO6, |
1685 | &ddc_i2c, |
1686 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1687 | &hpd); |
1688 | break; |
1689 | case CT_POWERBOOK_EXTERNAL: |
1690 | DRM_INFO("Connector Table: %d (powerbook external tmds)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook external tmds)\n" , rdev->mode_info.connector_table) |
1691 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook external tmds)\n" , rdev->mode_info.connector_table); |
1692 | /* LVDS */ |
1693 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1694 | hpd.hpd = RADEON_HPD_NONE; |
1695 | radeon_add_legacy_encoder(dev, |
1696 | radeon_get_encoder_enum(dev, |
1697 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1698 | 0), |
1699 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )); |
1700 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1701 | DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c, |
1702 | CONNECTOR_OBJECT_ID_LVDS0x0E, |
1703 | &hpd); |
1704 | /* DVI-I - primary dac, ext tmds */ |
1705 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1706 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1707 | radeon_add_legacy_encoder(dev, |
1708 | radeon_get_encoder_enum(dev, |
1709 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ), |
1710 | 0), |
1711 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )); |
1712 | radeon_add_legacy_encoder(dev, |
1713 | radeon_get_encoder_enum(dev, |
1714 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1715 | 1), |
1716 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
1717 | /* XXX some are SL */ |
1718 | radeon_add_legacy_connector(dev, 1, |
1719 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ) | |
1720 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1721 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
1722 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I0x02, |
1723 | &hpd); |
1724 | /* TV - TV DAC */ |
1725 | ddc_i2c.valid = false0; |
1726 | hpd.hpd = RADEON_HPD_NONE; |
1727 | radeon_add_legacy_encoder(dev, |
1728 | radeon_get_encoder_enum(dev, |
1729 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1730 | 2), |
1731 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1732 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1733 | DRM_MODE_CONNECTOR_SVIDEO6, |
1734 | &ddc_i2c, |
1735 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1736 | &hpd); |
1737 | break; |
1738 | case CT_POWERBOOK_INTERNAL: |
1739 | DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook internal tmds)\n" , rdev->mode_info.connector_table) |
1740 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook internal tmds)\n" , rdev->mode_info.connector_table); |
1741 | /* LVDS */ |
1742 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1743 | hpd.hpd = RADEON_HPD_NONE; |
1744 | radeon_add_legacy_encoder(dev, |
1745 | radeon_get_encoder_enum(dev, |
1746 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1747 | 0), |
1748 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )); |
1749 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1750 | DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c, |
1751 | CONNECTOR_OBJECT_ID_LVDS0x0E, |
1752 | &hpd); |
1753 | /* DVI-I - primary dac, int tmds */ |
1754 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1755 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1756 | radeon_add_legacy_encoder(dev, |
1757 | radeon_get_encoder_enum(dev, |
1758 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
1759 | 0), |
1760 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
1761 | radeon_add_legacy_encoder(dev, |
1762 | radeon_get_encoder_enum(dev, |
1763 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1764 | 1), |
1765 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
1766 | radeon_add_legacy_connector(dev, 1, |
1767 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) | |
1768 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1769 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
1770 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
1771 | &hpd); |
1772 | /* TV - TV DAC */ |
1773 | ddc_i2c.valid = false0; |
1774 | hpd.hpd = RADEON_HPD_NONE; |
1775 | radeon_add_legacy_encoder(dev, |
1776 | radeon_get_encoder_enum(dev, |
1777 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1778 | 2), |
1779 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1780 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1781 | DRM_MODE_CONNECTOR_SVIDEO6, |
1782 | &ddc_i2c, |
1783 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1784 | &hpd); |
1785 | break; |
1786 | case CT_POWERBOOK_VGA: |
1787 | DRM_INFO("Connector Table: %d (powerbook vga)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook vga)\n" , rdev->mode_info.connector_table) |
1788 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook vga)\n" , rdev->mode_info.connector_table); |
1789 | /* LVDS */ |
1790 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1791 | hpd.hpd = RADEON_HPD_NONE; |
1792 | radeon_add_legacy_encoder(dev, |
1793 | radeon_get_encoder_enum(dev, |
1794 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1795 | 0), |
1796 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )); |
1797 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
1798 | DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c, |
1799 | CONNECTOR_OBJECT_ID_LVDS0x0E, |
1800 | &hpd); |
1801 | /* VGA - primary dac */ |
1802 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1803 | hpd.hpd = RADEON_HPD_NONE; |
1804 | radeon_add_legacy_encoder(dev, |
1805 | radeon_get_encoder_enum(dev, |
1806 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1807 | 1), |
1808 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
1809 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1810 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
1811 | CONNECTOR_OBJECT_ID_VGA0x05, |
1812 | &hpd); |
1813 | /* TV - TV DAC */ |
1814 | ddc_i2c.valid = false0; |
1815 | hpd.hpd = RADEON_HPD_NONE; |
1816 | radeon_add_legacy_encoder(dev, |
1817 | radeon_get_encoder_enum(dev, |
1818 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1819 | 2), |
1820 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1821 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1822 | DRM_MODE_CONNECTOR_SVIDEO6, |
1823 | &ddc_i2c, |
1824 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1825 | &hpd); |
1826 | break; |
1827 | case CT_MINI_EXTERNAL: |
1828 | DRM_INFO("Connector Table: %d (mini external tmds)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mini external tmds)\n" , rdev->mode_info.connector_table) |
1829 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mini external tmds)\n" , rdev->mode_info.connector_table); |
1830 | /* DVI-I - tv dac, ext tmds */ |
1831 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1832 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
1833 | radeon_add_legacy_encoder(dev, |
1834 | radeon_get_encoder_enum(dev, |
1835 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ), |
1836 | 0), |
1837 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )); |
1838 | radeon_add_legacy_encoder(dev, |
1839 | radeon_get_encoder_enum(dev, |
1840 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1841 | 2), |
1842 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
1843 | /* XXX are any DL? */ |
1844 | radeon_add_legacy_connector(dev, 0, |
1845 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ) | |
1846 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1847 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
1848 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
1849 | &hpd); |
1850 | /* TV - TV DAC */ |
1851 | ddc_i2c.valid = false0; |
1852 | hpd.hpd = RADEON_HPD_NONE; |
1853 | radeon_add_legacy_encoder(dev, |
1854 | radeon_get_encoder_enum(dev, |
1855 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1856 | 2), |
1857 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1858 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1859 | DRM_MODE_CONNECTOR_SVIDEO6, |
1860 | &ddc_i2c, |
1861 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1862 | &hpd); |
1863 | break; |
1864 | case CT_MINI_INTERNAL: |
1865 | DRM_INFO("Connector Table: %d (mini internal tmds)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mini internal tmds)\n" , rdev->mode_info.connector_table) |
1866 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mini internal tmds)\n" , rdev->mode_info.connector_table); |
1867 | /* DVI-I - tv dac, int tmds */ |
1868 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1869 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1870 | radeon_add_legacy_encoder(dev, |
1871 | radeon_get_encoder_enum(dev, |
1872 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
1873 | 0), |
1874 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
1875 | radeon_add_legacy_encoder(dev, |
1876 | radeon_get_encoder_enum(dev, |
1877 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1878 | 2), |
1879 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
1880 | radeon_add_legacy_connector(dev, 0, |
1881 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) | |
1882 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1883 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
1884 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
1885 | &hpd); |
1886 | /* TV - TV DAC */ |
1887 | ddc_i2c.valid = false0; |
1888 | hpd.hpd = RADEON_HPD_NONE; |
1889 | radeon_add_legacy_encoder(dev, |
1890 | radeon_get_encoder_enum(dev, |
1891 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1892 | 2), |
1893 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1894 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1895 | DRM_MODE_CONNECTOR_SVIDEO6, |
1896 | &ddc_i2c, |
1897 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1898 | &hpd); |
1899 | break; |
1900 | case CT_IMAC_G5_ISIGHT: |
1901 | DRM_INFO("Connector Table: %d (imac g5 isight)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (imac g5 isight)\n" , rdev->mode_info.connector_table) |
1902 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (imac g5 isight)\n" , rdev->mode_info.connector_table); |
1903 | /* DVI-D - int tmds */ |
1904 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1905 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
1906 | radeon_add_legacy_encoder(dev, |
1907 | radeon_get_encoder_enum(dev, |
1908 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
1909 | 0), |
1910 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
1911 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
1912 | DRM_MODE_CONNECTOR_DVID3, &ddc_i2c, |
1913 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D0x03, |
1914 | &hpd); |
1915 | /* VGA - tv dac */ |
1916 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
1917 | hpd.hpd = RADEON_HPD_NONE; |
1918 | radeon_add_legacy_encoder(dev, |
1919 | radeon_get_encoder_enum(dev, |
1920 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1921 | 2), |
1922 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
1923 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1924 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
1925 | CONNECTOR_OBJECT_ID_VGA0x05, |
1926 | &hpd); |
1927 | /* TV - TV DAC */ |
1928 | ddc_i2c.valid = false0; |
1929 | hpd.hpd = RADEON_HPD_NONE; |
1930 | radeon_add_legacy_encoder(dev, |
1931 | radeon_get_encoder_enum(dev, |
1932 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1933 | 2), |
1934 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1935 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1936 | DRM_MODE_CONNECTOR_SVIDEO6, |
1937 | &ddc_i2c, |
1938 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1939 | &hpd); |
1940 | break; |
1941 | case CT_EMAC: |
1942 | DRM_INFO("Connector Table: %d (emac)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (emac)\n", rdev->mode_info.connector_table) |
1943 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (emac)\n", rdev->mode_info.connector_table); |
1944 | /* VGA - primary dac */ |
1945 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1946 | hpd.hpd = RADEON_HPD_NONE; |
1947 | radeon_add_legacy_encoder(dev, |
1948 | radeon_get_encoder_enum(dev, |
1949 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1950 | 1), |
1951 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
1952 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1953 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
1954 | CONNECTOR_OBJECT_ID_VGA0x05, |
1955 | &hpd); |
1956 | /* VGA - tv dac */ |
1957 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1958 | hpd.hpd = RADEON_HPD_NONE; |
1959 | radeon_add_legacy_encoder(dev, |
1960 | radeon_get_encoder_enum(dev, |
1961 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1962 | 2), |
1963 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
1964 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
1965 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
1966 | CONNECTOR_OBJECT_ID_VGA0x05, |
1967 | &hpd); |
1968 | /* TV - TV DAC */ |
1969 | ddc_i2c.valid = false0; |
1970 | hpd.hpd = RADEON_HPD_NONE; |
1971 | radeon_add_legacy_encoder(dev, |
1972 | radeon_get_encoder_enum(dev, |
1973 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1974 | 2), |
1975 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
1976 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
1977 | DRM_MODE_CONNECTOR_SVIDEO6, |
1978 | &ddc_i2c, |
1979 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
1980 | &hpd); |
1981 | break; |
1982 | case CT_RN50_POWER: |
1983 | DRM_INFO("Connector Table: %d (rn50-power)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (rn50-power)\n" , rdev->mode_info.connector_table) |
1984 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (rn50-power)\n" , rdev->mode_info.connector_table); |
1985 | /* VGA - primary dac */ |
1986 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
1987 | hpd.hpd = RADEON_HPD_NONE; |
1988 | radeon_add_legacy_encoder(dev, |
1989 | radeon_get_encoder_enum(dev, |
1990 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1991 | 1), |
1992 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
1993 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
1994 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
1995 | CONNECTOR_OBJECT_ID_VGA0x05, |
1996 | &hpd); |
1997 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
1998 | hpd.hpd = RADEON_HPD_NONE; |
1999 | radeon_add_legacy_encoder(dev, |
2000 | radeon_get_encoder_enum(dev, |
2001 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2002 | 2), |
2003 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
2004 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2005 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
2006 | CONNECTOR_OBJECT_ID_VGA0x05, |
2007 | &hpd); |
2008 | break; |
2009 | case CT_MAC_X800: |
2010 | DRM_INFO("Connector Table: %d (mac x800)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mac x800)\n" , rdev->mode_info.connector_table) |
2011 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mac x800)\n" , rdev->mode_info.connector_table); |
2012 | /* DVI - primary dac, internal tmds */ |
2013 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2014 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2015 | radeon_add_legacy_encoder(dev, |
2016 | radeon_get_encoder_enum(dev, |
2017 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
2018 | 0), |
2019 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
2020 | radeon_add_legacy_encoder(dev, |
2021 | radeon_get_encoder_enum(dev, |
2022 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2023 | 1), |
2024 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
2025 | radeon_add_legacy_connector(dev, 0, |
2026 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) | |
2027 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2028 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
2029 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
2030 | &hpd); |
2031 | /* DVI - tv dac, dvo */ |
2032 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
2033 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
2034 | radeon_add_legacy_encoder(dev, |
2035 | radeon_get_encoder_enum(dev, |
2036 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ), |
2037 | 0), |
2038 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )); |
2039 | radeon_add_legacy_encoder(dev, |
2040 | radeon_get_encoder_enum(dev, |
2041 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2042 | 2), |
2043 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
2044 | radeon_add_legacy_connector(dev, 1, |
2045 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ) | |
2046 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2047 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
2048 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I0x02, |
2049 | &hpd); |
2050 | break; |
2051 | case CT_MAC_G5_9600: |
2052 | DRM_INFO("Connector Table: %d (mac g5 9600)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mac g5 9600)\n" , rdev->mode_info.connector_table) |
2053 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mac g5 9600)\n" , rdev->mode_info.connector_table); |
2054 | /* DVI - tv dac, dvo */ |
2055 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2056 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2057 | radeon_add_legacy_encoder(dev, |
2058 | radeon_get_encoder_enum(dev, |
2059 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ), |
2060 | 0), |
2061 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )); |
2062 | radeon_add_legacy_encoder(dev, |
2063 | radeon_get_encoder_enum(dev, |
2064 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2065 | 2), |
2066 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
2067 | radeon_add_legacy_connector(dev, 0, |
2068 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ) | |
2069 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2070 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
2071 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
2072 | &hpd); |
2073 | /* ADC - primary dac, internal tmds */ |
2074 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2075 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
2076 | radeon_add_legacy_encoder(dev, |
2077 | radeon_get_encoder_enum(dev, |
2078 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
2079 | 0), |
2080 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
2081 | radeon_add_legacy_encoder(dev, |
2082 | radeon_get_encoder_enum(dev, |
2083 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2084 | 1), |
2085 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
2086 | radeon_add_legacy_connector(dev, 1, |
2087 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) | |
2088 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2089 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
2090 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
2091 | &hpd); |
2092 | /* TV - TV DAC */ |
2093 | ddc_i2c.valid = false0; |
2094 | hpd.hpd = RADEON_HPD_NONE; |
2095 | radeon_add_legacy_encoder(dev, |
2096 | radeon_get_encoder_enum(dev, |
2097 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2098 | 2), |
2099 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
2100 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2101 | DRM_MODE_CONNECTOR_SVIDEO6, |
2102 | &ddc_i2c, |
2103 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
2104 | &hpd); |
2105 | break; |
2106 | case CT_SAM440EP: |
2107 | DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (SAM440ep embedded board)\n" , rdev->mode_info.connector_table) |
2108 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (SAM440ep embedded board)\n" , rdev->mode_info.connector_table); |
2109 | /* LVDS */ |
2110 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
2111 | hpd.hpd = RADEON_HPD_NONE; |
2112 | radeon_add_legacy_encoder(dev, |
2113 | radeon_get_encoder_enum(dev, |
2114 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
2115 | 0), |
2116 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )); |
2117 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
2118 | DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c, |
2119 | CONNECTOR_OBJECT_ID_LVDS0x0E, |
2120 | &hpd); |
2121 | /* DVI-I - secondary dac, int tmds */ |
2122 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2123 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2124 | radeon_add_legacy_encoder(dev, |
2125 | radeon_get_encoder_enum(dev, |
2126 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
2127 | 0), |
2128 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
2129 | radeon_add_legacy_encoder(dev, |
2130 | radeon_get_encoder_enum(dev, |
2131 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2132 | 2), |
2133 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
2134 | radeon_add_legacy_connector(dev, 1, |
2135 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) | |
2136 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2137 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
2138 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
2139 | &hpd); |
2140 | /* VGA - primary dac */ |
2141 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2142 | hpd.hpd = RADEON_HPD_NONE; |
2143 | radeon_add_legacy_encoder(dev, |
2144 | radeon_get_encoder_enum(dev, |
2145 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2146 | 1), |
2147 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
2148 | radeon_add_legacy_connector(dev, 2, |
2149 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2150 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
2151 | CONNECTOR_OBJECT_ID_VGA0x05, |
2152 | &hpd); |
2153 | /* TV - TV DAC */ |
2154 | ddc_i2c.valid = false0; |
2155 | hpd.hpd = RADEON_HPD_NONE; |
2156 | radeon_add_legacy_encoder(dev, |
2157 | radeon_get_encoder_enum(dev, |
2158 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2159 | 2), |
2160 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
2161 | radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2162 | DRM_MODE_CONNECTOR_SVIDEO6, |
2163 | &ddc_i2c, |
2164 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
2165 | &hpd); |
2166 | break; |
2167 | case CT_MAC_G4_SILVER: |
2168 | DRM_INFO("Connector Table: %d (mac g4 silver)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mac g4 silver)\n" , rdev->mode_info.connector_table) |
2169 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mac g4 silver)\n" , rdev->mode_info.connector_table); |
2170 | /* DVI-I - tv dac, int tmds */ |
2171 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2172 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
2173 | radeon_add_legacy_encoder(dev, |
2174 | radeon_get_encoder_enum(dev, |
2175 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
2176 | 0), |
2177 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
2178 | radeon_add_legacy_encoder(dev, |
2179 | radeon_get_encoder_enum(dev, |
2180 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2181 | 2), |
2182 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
2183 | radeon_add_legacy_connector(dev, 0, |
2184 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) | |
2185 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2186 | DRM_MODE_CONNECTOR_DVII2, &ddc_i2c, |
2187 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
2188 | &hpd); |
2189 | /* VGA - primary dac */ |
2190 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2191 | hpd.hpd = RADEON_HPD_NONE; |
2192 | radeon_add_legacy_encoder(dev, |
2193 | radeon_get_encoder_enum(dev, |
2194 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2195 | 1), |
2196 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
2197 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2198 | DRM_MODE_CONNECTOR_VGA1, &ddc_i2c, |
2199 | CONNECTOR_OBJECT_ID_VGA0x05, |
2200 | &hpd); |
2201 | /* TV - TV DAC */ |
2202 | ddc_i2c.valid = false0; |
2203 | hpd.hpd = RADEON_HPD_NONE; |
2204 | radeon_add_legacy_encoder(dev, |
2205 | radeon_get_encoder_enum(dev, |
2206 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2207 | 2), |
2208 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
2209 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2210 | DRM_MODE_CONNECTOR_SVIDEO6, |
2211 | &ddc_i2c, |
2212 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
2213 | &hpd); |
2214 | break; |
2215 | default: |
2216 | DRM_INFO("Connector table: %d (invalid)\n",printk("\0016" "[" "drm" "] " "Connector table: %d (invalid)\n" , rdev->mode_info.connector_table) |
2217 | rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector table: %d (invalid)\n" , rdev->mode_info.connector_table); |
2218 | return false0; |
2219 | } |
2220 | |
2221 | radeon_link_encoder_connector(dev); |
2222 | |
2223 | return true1; |
2224 | } |
2225 | |
2226 | static bool_Bool radeon_apply_legacy_quirks(struct drm_device *dev, |
2227 | int bios_index, |
2228 | enum radeon_combios_connector |
2229 | *legacy_connector, |
2230 | struct radeon_i2c_bus_rec *ddc_i2c, |
2231 | struct radeon_hpd *hpd) |
2232 | { |
2233 | struct radeon_device *rdev = dev->dev_private; |
2234 | |
2235 | /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, |
2236 | one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ |
2237 | if (rdev->pdev->device == 0x515e && |
2238 | rdev->pdev->subsystem_vendor == 0x1014) { |
2239 | if (*legacy_connector == CONNECTOR_CRT_LEGACY && |
2240 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC0x006c) |
2241 | return false0; |
2242 | } |
2243 | |
2244 | /* X300 card with extra non-existent DVI port */ |
2245 | if (rdev->pdev->device == 0x5B60 && |
2246 | rdev->pdev->subsystem_vendor == 0x17af && |
2247 | rdev->pdev->subsystem_device == 0x201e && bios_index == 2) { |
2248 | if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) |
2249 | return false0; |
2250 | } |
2251 | |
2252 | return true1; |
2253 | } |
2254 | |
2255 | static bool_Bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) |
2256 | { |
2257 | struct radeon_device *rdev = dev->dev_private; |
2258 | |
2259 | /* Acer 5102 has non-existent TV port */ |
2260 | if (rdev->pdev->device == 0x5975 && |
2261 | rdev->pdev->subsystem_vendor == 0x1025 && |
2262 | rdev->pdev->subsystem_device == 0x009f) |
2263 | return false0; |
2264 | |
2265 | /* HP dc5750 has non-existent TV port */ |
2266 | if (rdev->pdev->device == 0x5974 && |
2267 | rdev->pdev->subsystem_vendor == 0x103c && |
2268 | rdev->pdev->subsystem_device == 0x280a) |
2269 | return false0; |
2270 | |
2271 | /* MSI S270 has non-existent TV port */ |
2272 | if (rdev->pdev->device == 0x5955 && |
2273 | rdev->pdev->subsystem_vendor == 0x1462 && |
2274 | rdev->pdev->subsystem_device == 0x0131) |
2275 | return false0; |
2276 | |
2277 | return true1; |
2278 | } |
2279 | |
2280 | static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) |
2281 | { |
2282 | struct radeon_device *rdev = dev->dev_private; |
2283 | uint32_t ext_tmds_info; |
2284 | |
2285 | if (rdev->flags & RADEON_IS_IGP) { |
2286 | if (is_dvi_d) |
2287 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D0x03; |
2288 | else |
2289 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01; |
2290 | } |
2291 | ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
2292 | if (ext_tmds_info) { |
2293 | uint8_t rev = RBIOS8(ext_tmds_info)(rdev->bios[ext_tmds_info]); |
2294 | uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5)(rdev->bios[ext_tmds_info + 4 + 5]); |
2295 | if (rev >= 3) { |
2296 | if (is_dvi_d) |
2297 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D0x04; |
2298 | else |
2299 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I0x02; |
2300 | } else { |
2301 | if (flags & 1) { |
2302 | if (is_dvi_d) |
2303 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D0x04; |
2304 | else |
2305 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I0x02; |
2306 | } |
2307 | } |
2308 | } |
2309 | if (is_dvi_d) |
2310 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D0x03; |
2311 | else |
2312 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01; |
2313 | } |
2314 | |
2315 | bool_Bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) |
2316 | { |
2317 | struct radeon_device *rdev = dev->dev_private; |
2318 | uint32_t conn_info, entry, devices; |
2319 | uint16_t tmp, connector_object_id; |
2320 | enum radeon_combios_ddc ddc_type; |
2321 | enum radeon_combios_connector connector; |
2322 | int i = 0; |
2323 | struct radeon_i2c_bus_rec ddc_i2c; |
2324 | struct radeon_hpd hpd; |
2325 | |
2326 | conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); |
2327 | if (conn_info) { |
2328 | for (i = 0; i < 4; i++) { |
2329 | entry = conn_info + 2 + i * 2; |
2330 | |
2331 | if (!RBIOS16(entry)((rdev->bios[entry]) | ((rdev->bios[(entry)+1]) << 8))) |
2332 | break; |
2333 | |
2334 | tmp = RBIOS16(entry)((rdev->bios[entry]) | ((rdev->bios[(entry)+1]) << 8)); |
2335 | |
2336 | connector = (tmp >> 12) & 0xf; |
2337 | |
2338 | ddc_type = (tmp >> 8) & 0xf; |
2339 | if (ddc_type == 5) |
2340 | ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); |
2341 | else |
2342 | ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
2343 | |
2344 | switch (connector) { |
2345 | case CONNECTOR_PROPRIETARY_LEGACY: |
2346 | case CONNECTOR_DVI_I_LEGACY: |
2347 | case CONNECTOR_DVI_D_LEGACY: |
2348 | if ((tmp >> 4) & 0x1) |
2349 | hpd.hpd = RADEON_HPD_2; |
2350 | else |
2351 | hpd.hpd = RADEON_HPD_1; |
2352 | break; |
2353 | default: |
2354 | hpd.hpd = RADEON_HPD_NONE; |
2355 | break; |
2356 | } |
2357 | |
2358 | if (!radeon_apply_legacy_quirks(dev, i, &connector, |
2359 | &ddc_i2c, &hpd)) |
2360 | continue; |
2361 | |
2362 | switch (connector) { |
2363 | case CONNECTOR_PROPRIETARY_LEGACY: |
2364 | if ((tmp >> 4) & 0x1) |
2365 | devices = ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ); |
2366 | else |
2367 | devices = ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ); |
2368 | radeon_add_legacy_encoder(dev, |
2369 | radeon_get_encoder_enum |
2370 | (dev, devices, 0), |
2371 | devices); |
2372 | radeon_add_legacy_connector(dev, i, devices, |
2373 | legacy_connector_convert |
2374 | [connector], |
2375 | &ddc_i2c, |
2376 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D0x03, |
2377 | &hpd); |
2378 | break; |
2379 | case CONNECTOR_CRT_LEGACY: |
2380 | if (tmp & 0x1) { |
2381 | devices = ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ); |
2382 | radeon_add_legacy_encoder(dev, |
2383 | radeon_get_encoder_enum |
2384 | (dev, |
2385 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2386 | 2), |
2387 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
2388 | } else { |
2389 | devices = ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ); |
2390 | radeon_add_legacy_encoder(dev, |
2391 | radeon_get_encoder_enum |
2392 | (dev, |
2393 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2394 | 1), |
2395 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
2396 | } |
2397 | radeon_add_legacy_connector(dev, |
2398 | i, |
2399 | devices, |
2400 | legacy_connector_convert |
2401 | [connector], |
2402 | &ddc_i2c, |
2403 | CONNECTOR_OBJECT_ID_VGA0x05, |
2404 | &hpd); |
2405 | break; |
2406 | case CONNECTOR_DVI_I_LEGACY: |
2407 | devices = 0; |
2408 | if (tmp & 0x1) { |
2409 | devices |= ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ); |
2410 | radeon_add_legacy_encoder(dev, |
2411 | radeon_get_encoder_enum |
2412 | (dev, |
2413 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ), |
2414 | 2), |
2415 | ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )); |
2416 | } else { |
2417 | devices |= ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ); |
2418 | radeon_add_legacy_encoder(dev, |
2419 | radeon_get_encoder_enum |
2420 | (dev, |
2421 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2422 | 1), |
2423 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
2424 | } |
2425 | /* RV100 board with external TDMS bit mis-set. |
2426 | * Actually uses internal TMDS, clear the bit. |
2427 | */ |
2428 | if (rdev->pdev->device == 0x5159 && |
2429 | rdev->pdev->subsystem_vendor == 0x1014 && |
2430 | rdev->pdev->subsystem_device == 0x029A) { |
2431 | tmp &= ~(1 << 4); |
2432 | } |
2433 | if ((tmp >> 4) & 0x1) { |
2434 | devices |= ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ); |
2435 | radeon_add_legacy_encoder(dev, |
2436 | radeon_get_encoder_enum |
2437 | (dev, |
2438 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ), |
2439 | 0), |
2440 | ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )); |
2441 | connector_object_id = combios_check_dl_dvi(dev, 0); |
2442 | } else { |
2443 | devices |= ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ); |
2444 | radeon_add_legacy_encoder(dev, |
2445 | radeon_get_encoder_enum |
2446 | (dev, |
2447 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
2448 | 0), |
2449 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
2450 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01; |
2451 | } |
2452 | radeon_add_legacy_connector(dev, |
2453 | i, |
2454 | devices, |
2455 | legacy_connector_convert |
2456 | [connector], |
2457 | &ddc_i2c, |
2458 | connector_object_id, |
2459 | &hpd); |
2460 | break; |
2461 | case CONNECTOR_DVI_D_LEGACY: |
2462 | if ((tmp >> 4) & 0x1) { |
2463 | devices = ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ); |
2464 | connector_object_id = combios_check_dl_dvi(dev, 1); |
2465 | } else { |
2466 | devices = ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ); |
2467 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01; |
2468 | } |
2469 | radeon_add_legacy_encoder(dev, |
2470 | radeon_get_encoder_enum |
2471 | (dev, devices, 0), |
2472 | devices); |
2473 | radeon_add_legacy_connector(dev, i, devices, |
2474 | legacy_connector_convert |
2475 | [connector], |
2476 | &ddc_i2c, |
2477 | connector_object_id, |
2478 | &hpd); |
2479 | break; |
2480 | case CONNECTOR_CTV_LEGACY: |
2481 | case CONNECTOR_STV_LEGACY: |
2482 | radeon_add_legacy_encoder(dev, |
2483 | radeon_get_encoder_enum |
2484 | (dev, |
2485 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2486 | 2), |
2487 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
2488 | radeon_add_legacy_connector(dev, i, |
2489 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2490 | legacy_connector_convert |
2491 | [connector], |
2492 | &ddc_i2c, |
2493 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
2494 | &hpd); |
2495 | break; |
2496 | default: |
2497 | DRM_ERROR("Unknown connector type: %d\n",__drm_err("Unknown connector type: %d\n", connector) |
2498 | connector)__drm_err("Unknown connector type: %d\n", connector); |
2499 | continue; |
2500 | } |
2501 | |
2502 | } |
2503 | } else { |
2504 | uint16_t tmds_info = |
2505 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
2506 | if (tmds_info) { |
2507 | DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Found DFP table, assuming DVI connector\n" ); |
2508 | |
2509 | radeon_add_legacy_encoder(dev, |
2510 | radeon_get_encoder_enum(dev, |
2511 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2512 | 1), |
2513 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
2514 | radeon_add_legacy_encoder(dev, |
2515 | radeon_get_encoder_enum(dev, |
2516 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
2517 | 0), |
2518 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )); |
2519 | |
2520 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
2521 | hpd.hpd = RADEON_HPD_1; |
2522 | radeon_add_legacy_connector(dev, |
2523 | 0, |
2524 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ) | |
2525 | ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ), |
2526 | DRM_MODE_CONNECTOR_DVII2, |
2527 | &ddc_i2c, |
2528 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01, |
2529 | &hpd); |
2530 | } else { |
2531 | uint16_t crt_info = |
2532 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
2533 | DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Found CRT table, assuming VGA connector\n" ); |
2534 | if (crt_info) { |
2535 | radeon_add_legacy_encoder(dev, |
2536 | radeon_get_encoder_enum(dev, |
2537 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2538 | 1), |
2539 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )); |
2540 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
2541 | hpd.hpd = RADEON_HPD_NONE; |
2542 | radeon_add_legacy_connector(dev, |
2543 | 0, |
2544 | ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ), |
2545 | DRM_MODE_CONNECTOR_VGA1, |
2546 | &ddc_i2c, |
2547 | CONNECTOR_OBJECT_ID_VGA0x05, |
2548 | &hpd); |
2549 | } else { |
2550 | DRM_DEBUG_KMS("No connector info found\n")___drm_dbg(((void *)0), DRM_UT_KMS, "No connector info found\n" ); |
2551 | return false0; |
2552 | } |
2553 | } |
2554 | } |
2555 | |
2556 | if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { |
2557 | uint16_t lcd_info = |
2558 | combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
2559 | if (lcd_info) { |
2560 | uint16_t lcd_ddc_info = |
2561 | combios_get_table_offset(dev, |
2562 | COMBIOS_LCD_DDC_INFO_TABLE); |
2563 | |
2564 | radeon_add_legacy_encoder(dev, |
2565 | radeon_get_encoder_enum(dev, |
2566 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
2567 | 0), |
2568 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )); |
2569 | |
2570 | if (lcd_ddc_info) { |
2571 | ddc_type = RBIOS8(lcd_ddc_info + 2)(rdev->bios[lcd_ddc_info + 2]); |
2572 | switch (ddc_type) { |
2573 | case DDC_LCD: |
2574 | ddc_i2c = |
2575 | combios_setup_i2c_bus(rdev, |
2576 | DDC_LCD, |
2577 | RBIOS32(lcd_ddc_info + 3)((((rdev->bios[lcd_ddc_info + 3]) | ((rdev->bios[(lcd_ddc_info + 3)+1]) << 8))) | (((rdev->bios[(lcd_ddc_info + 3) +2]) | ((rdev->bios[((lcd_ddc_info + 3)+2)+1]) << 8) ) << 16)), |
2578 | RBIOS32(lcd_ddc_info + 7)((((rdev->bios[lcd_ddc_info + 7]) | ((rdev->bios[(lcd_ddc_info + 7)+1]) << 8))) | (((rdev->bios[(lcd_ddc_info + 7) +2]) | ((rdev->bios[((lcd_ddc_info + 7)+2)+1]) << 8) ) << 16))); |
2579 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
2580 | break; |
2581 | case DDC_GPIO: |
2582 | ddc_i2c = |
2583 | combios_setup_i2c_bus(rdev, |
2584 | DDC_GPIO, |
2585 | RBIOS32(lcd_ddc_info + 3)((((rdev->bios[lcd_ddc_info + 3]) | ((rdev->bios[(lcd_ddc_info + 3)+1]) << 8))) | (((rdev->bios[(lcd_ddc_info + 3) +2]) | ((rdev->bios[((lcd_ddc_info + 3)+2)+1]) << 8) ) << 16)), |
2586 | RBIOS32(lcd_ddc_info + 7)((((rdev->bios[lcd_ddc_info + 7]) | ((rdev->bios[(lcd_ddc_info + 7)+1]) << 8))) | (((rdev->bios[(lcd_ddc_info + 7) +2]) | ((rdev->bios[((lcd_ddc_info + 7)+2)+1]) << 8) ) << 16))); |
2587 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
2588 | break; |
2589 | default: |
2590 | ddc_i2c = |
2591 | combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
2592 | break; |
2593 | } |
2594 | DRM_DEBUG_KMS("LCD DDC Info Table found!\n")___drm_dbg(((void *)0), DRM_UT_KMS, "LCD DDC Info Table found!\n" ); |
2595 | } else |
2596 | ddc_i2c.valid = false0; |
2597 | |
2598 | hpd.hpd = RADEON_HPD_NONE; |
2599 | radeon_add_legacy_connector(dev, |
2600 | 5, |
2601 | ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ), |
2602 | DRM_MODE_CONNECTOR_LVDS7, |
2603 | &ddc_i2c, |
2604 | CONNECTOR_OBJECT_ID_LVDS0x0E, |
2605 | &hpd); |
2606 | } |
2607 | } |
2608 | |
2609 | /* check TV table */ |
2610 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { |
2611 | uint32_t tv_info = |
2612 | combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); |
2613 | if (tv_info) { |
2614 | if (RBIOS8(tv_info + 6)(rdev->bios[tv_info + 6]) == 'T') { |
2615 | if (radeon_apply_legacy_tv_quirks(dev)) { |
2616 | hpd.hpd = RADEON_HPD_NONE; |
2617 | ddc_i2c.valid = false0; |
2618 | radeon_add_legacy_encoder(dev, |
2619 | radeon_get_encoder_enum |
2620 | (dev, |
2621 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2622 | 2), |
2623 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )); |
2624 | radeon_add_legacy_connector(dev, 6, |
2625 | ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ), |
2626 | DRM_MODE_CONNECTOR_SVIDEO6, |
2627 | &ddc_i2c, |
2628 | CONNECTOR_OBJECT_ID_SVIDEO0x07, |
2629 | &hpd); |
2630 | } |
2631 | } |
2632 | } |
2633 | } |
2634 | |
2635 | radeon_link_encoder_connector(dev); |
2636 | |
2637 | return true1; |
2638 | } |
2639 | |
2640 | static const char *thermal_controller_names[] = { |
2641 | "NONE", |
2642 | "lm63", |
2643 | "adm1032", |
2644 | }; |
2645 | |
2646 | void radeon_combios_get_power_modes(struct radeon_device *rdev) |
2647 | { |
2648 | struct drm_device *dev = rdev->ddev; |
2649 | u16 offset, misc, misc2 = 0; |
2650 | u8 rev, tmp; |
2651 | int state_index = 0; |
2652 | struct radeon_i2c_bus_rec i2c_bus; |
2653 | |
2654 | rdev->pm.default_power_state_index = -1; |
2655 | |
2656 | /* allocate 2 power states */ |
2657 | rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state), |
2658 | GFP_KERNEL(0x0001 | 0x0004)); |
2659 | if (rdev->pm.power_state) { |
2660 | /* allocate 1 clock mode per state */ |
2661 | rdev->pm.power_state[0].clock_info = |
2662 | kcalloc(1, sizeof(struct radeon_pm_clock_info), |
2663 | GFP_KERNEL(0x0001 | 0x0004)); |
2664 | rdev->pm.power_state[1].clock_info = |
2665 | kcalloc(1, sizeof(struct radeon_pm_clock_info), |
2666 | GFP_KERNEL(0x0001 | 0x0004)); |
2667 | if (!rdev->pm.power_state[0].clock_info || |
2668 | !rdev->pm.power_state[1].clock_info) |
2669 | goto pm_failed; |
2670 | } else |
2671 | goto pm_failed; |
2672 | |
2673 | /* check for a thermal chip */ |
2674 | offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); |
2675 | if (offset) { |
2676 | u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; |
2677 | |
2678 | rev = RBIOS8(offset)(rdev->bios[offset]); |
2679 | |
2680 | if (rev == 0) { |
2681 | thermal_controller = RBIOS8(offset + 3)(rdev->bios[offset + 3]); |
2682 | gpio = RBIOS8(offset + 4)(rdev->bios[offset + 4]) & 0x3f; |
2683 | i2c_addr = RBIOS8(offset + 5)(rdev->bios[offset + 5]); |
2684 | } else if (rev == 1) { |
2685 | thermal_controller = RBIOS8(offset + 4)(rdev->bios[offset + 4]); |
2686 | gpio = RBIOS8(offset + 5)(rdev->bios[offset + 5]) & 0x3f; |
2687 | i2c_addr = RBIOS8(offset + 6)(rdev->bios[offset + 6]); |
2688 | } else if (rev == 2) { |
2689 | thermal_controller = RBIOS8(offset + 4)(rdev->bios[offset + 4]); |
2690 | gpio = RBIOS8(offset + 5)(rdev->bios[offset + 5]) & 0x3f; |
2691 | i2c_addr = RBIOS8(offset + 6)(rdev->bios[offset + 6]); |
2692 | clk_bit = RBIOS8(offset + 0xa)(rdev->bios[offset + 0xa]); |
2693 | data_bit = RBIOS8(offset + 0xb)(rdev->bios[offset + 0xb]); |
2694 | } |
2695 | if ((thermal_controller > 0) && (thermal_controller < 3)) { |
2696 | DRM_INFO("Possible %s thermal controller at 0x%02x\n",printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n" , thermal_controller_names[thermal_controller], i2c_addr >> 1) |
2697 | thermal_controller_names[thermal_controller],printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n" , thermal_controller_names[thermal_controller], i2c_addr >> 1) |
2698 | i2c_addr >> 1)printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n" , thermal_controller_names[thermal_controller], i2c_addr >> 1); |
2699 | if (gpio == DDC_LCD) { |
2700 | /* MM i2c */ |
2701 | i2c_bus.valid = true1; |
2702 | i2c_bus.hw_capable = true1; |
2703 | i2c_bus.mm_i2c = true1; |
2704 | i2c_bus.i2c_id = 0xa0; |
2705 | } else if (gpio == DDC_GPIO) |
2706 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); |
2707 | else |
2708 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
2709 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
2710 | #ifdef notyet |
2711 | if (rdev->pm.i2c_bus) { |
2712 | struct i2c_board_info info = { }; |
2713 | const char *name = thermal_controller_names[thermal_controller]; |
2714 | info.addr = i2c_addr >> 1; |
2715 | strlcpy(info.type, name, sizeof(info.type)); |
2716 | i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); |
2717 | } |
2718 | #endif |
2719 | } |
2720 | } else { |
2721 | /* boards with a thermal chip, but no overdrive table */ |
2722 | |
2723 | /* Asus 9600xt has an f75375 on the monid bus */ |
2724 | if ((rdev->pdev->device == 0x4152) && |
2725 | (rdev->pdev->subsystem_vendor == 0x1043) && |
2726 | (rdev->pdev->subsystem_device == 0xc002)) { |
2727 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
2728 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
2729 | #ifdef notyet |
2730 | if (rdev->pm.i2c_bus) { |
2731 | struct i2c_board_info info = { }; |
2732 | const char *name = "f75375"; |
2733 | info.addr = 0x28; |
2734 | strlcpy(info.type, name, sizeof(info.type)); |
2735 | i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); |
2736 | DRM_INFO("Possible %s thermal controller at 0x%02x\n",printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n" , name, info.addr) |
2737 | name, info.addr)printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n" , name, info.addr); |
2738 | } |
2739 | #endif |
2740 | } |
2741 | } |
2742 | |
2743 | if (rdev->flags & RADEON_IS_MOBILITY) { |
2744 | offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); |
2745 | if (offset) { |
2746 | rev = RBIOS8(offset)(rdev->bios[offset]); |
2747 | /* power mode 0 tends to be the only valid one */ |
2748 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2749 | rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2)((((rdev->bios[offset + 0x5 + 0x2]) | ((rdev->bios[(offset + 0x5 + 0x2)+1]) << 8))) | (((rdev->bios[(offset + 0x5 + 0x2)+2]) | ((rdev->bios[((offset + 0x5 + 0x2)+2)+1]) << 8)) << 16)); |
2750 | rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6)((((rdev->bios[offset + 0x5 + 0x6]) | ((rdev->bios[(offset + 0x5 + 0x6)+1]) << 8))) | (((rdev->bios[(offset + 0x5 + 0x6)+2]) | ((rdev->bios[((offset + 0x5 + 0x6)+2)+1]) << 8)) << 16)); |
2751 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
2752 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
2753 | goto default_mode; |
2754 | rdev->pm.power_state[state_index].type = |
2755 | POWER_STATE_TYPE_BATTERY; |
2756 | misc = RBIOS16(offset + 0x5 + 0x0)((rdev->bios[offset + 0x5 + 0x0]) | ((rdev->bios[(offset + 0x5 + 0x0)+1]) << 8)); |
2757 | if (rev > 4) |
2758 | misc2 = RBIOS16(offset + 0x5 + 0xe)((rdev->bios[offset + 0x5 + 0xe]) | ((rdev->bios[(offset + 0x5 + 0xe)+1]) << 8)); |
2759 | rdev->pm.power_state[state_index].misc = misc; |
2760 | rdev->pm.power_state[state_index].misc2 = misc2; |
2761 | if (misc & 0x4) { |
2762 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; |
2763 | if (misc & 0x8) |
2764 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
2765 | true1; |
2766 | else |
2767 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = |
2768 | false0; |
2769 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true1; |
2770 | if (rev < 6) { |
2771 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = |
2772 | RBIOS16(offset + 0x5 + 0xb)((rdev->bios[offset + 0x5 + 0xb]) | ((rdev->bios[(offset + 0x5 + 0xb)+1]) << 8)) * 4; |
2773 | tmp = RBIOS8(offset + 0x5 + 0xd)(rdev->bios[offset + 0x5 + 0xd]); |
2774 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); |
2775 | } else { |
2776 | u8 entries = RBIOS8(offset + 0x5 + 0xb)(rdev->bios[offset + 0x5 + 0xb]); |
2777 | u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc)((rdev->bios[offset + 0x5 + 0xc]) | ((rdev->bios[(offset + 0x5 + 0xc)+1]) << 8)); |
2778 | if (entries && voltage_table_offset) { |
2779 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = |
2780 | RBIOS16(voltage_table_offset)((rdev->bios[voltage_table_offset]) | ((rdev->bios[(voltage_table_offset )+1]) << 8)) * 4; |
2781 | tmp = RBIOS8(voltage_table_offset + 0x2)(rdev->bios[voltage_table_offset + 0x2]); |
2782 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); |
2783 | } else |
2784 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false0; |
2785 | } |
2786 | switch ((misc2 & 0x700) >> 8) { |
2787 | case 0: |
2788 | default: |
2789 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; |
2790 | break; |
2791 | case 1: |
2792 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; |
2793 | break; |
2794 | case 2: |
2795 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; |
2796 | break; |
2797 | case 3: |
2798 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; |
2799 | break; |
2800 | case 4: |
2801 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; |
2802 | break; |
2803 | } |
2804 | } else |
2805 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2806 | if (rev > 6) |
2807 | rdev->pm.power_state[state_index].pcie_lanes = |
2808 | RBIOS8(offset + 0x5 + 0x10)(rdev->bios[offset + 0x5 + 0x10]); |
2809 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY(1 << 0); |
2810 | state_index++; |
2811 | } else { |
2812 | /* XXX figure out some good default low power mode for mobility cards w/out power tables */ |
2813 | } |
2814 | } else { |
2815 | /* XXX figure out some good default low power mode for desktop cards */ |
2816 | } |
2817 | |
2818 | default_mode: |
2819 | /* add the default mode */ |
2820 | rdev->pm.power_state[state_index].type = |
2821 | POWER_STATE_TYPE_DEFAULT; |
2822 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2823 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
2824 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
2825 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; |
2826 | if ((state_index > 0) && |
2827 | (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) |
2828 | rdev->pm.power_state[state_index].clock_info[0].voltage = |
2829 | rdev->pm.power_state[0].clock_info[0].voltage; |
2830 | else |
2831 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
2832 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
2833 | rdev->pm.power_state[state_index].flags = 0; |
2834 | rdev->pm.default_power_state_index = state_index; |
2835 | rdev->pm.num_power_states = state_index + 1; |
2836 | |
2837 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2838 | rdev->pm.current_clock_mode_index = 0; |
2839 | return; |
2840 | |
2841 | pm_failed: |
2842 | rdev->pm.default_power_state_index = state_index; |
2843 | rdev->pm.num_power_states = 0; |
2844 | |
2845 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2846 | rdev->pm.current_clock_mode_index = 0; |
2847 | } |
2848 | |
2849 | void radeon_external_tmds_setup(struct drm_encoder *encoder) |
2850 | { |
2851 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof (struct radeon_encoder, base) );}); |
2852 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
2853 | |
2854 | if (!tmds) |
2855 | return; |
2856 | |
2857 | switch (tmds->dvo_chip) { |
2858 | case DVO_SIL164: |
2859 | /* sil 164 */ |
2860 | radeon_i2c_put_byte(tmds->i2c_bus, |
2861 | tmds->slave_addr, |
2862 | 0x08, 0x30); |
2863 | radeon_i2c_put_byte(tmds->i2c_bus, |
2864 | tmds->slave_addr, |
2865 | 0x09, 0x00); |
2866 | radeon_i2c_put_byte(tmds->i2c_bus, |
2867 | tmds->slave_addr, |
2868 | 0x0a, 0x90); |
2869 | radeon_i2c_put_byte(tmds->i2c_bus, |
2870 | tmds->slave_addr, |
2871 | 0x0c, 0x89); |
2872 | radeon_i2c_put_byte(tmds->i2c_bus, |
2873 | tmds->slave_addr, |
2874 | 0x08, 0x3b); |
2875 | break; |
2876 | case DVO_SIL1178: |
2877 | /* sil 1178 - untested */ |
2878 | /* |
2879 | * 0x0f, 0x44 |
2880 | * 0x0f, 0x4c |
2881 | * 0x0e, 0x01 |
2882 | * 0x0a, 0x80 |
2883 | * 0x09, 0x30 |
2884 | * 0x0c, 0xc9 |
2885 | * 0x0d, 0x70 |
2886 | * 0x08, 0x32 |
2887 | * 0x08, 0x33 |
2888 | */ |
2889 | break; |
2890 | default: |
2891 | break; |
2892 | } |
2893 | |
2894 | } |
2895 | |
2896 | bool_Bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) |
2897 | { |
2898 | struct drm_device *dev = encoder->dev; |
2899 | struct radeon_device *rdev = dev->dev_private; |
2900 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof (struct radeon_encoder, base) );}); |
2901 | uint16_t offset; |
2902 | uint8_t blocks, slave_addr, rev; |
2903 | uint32_t index, id; |
2904 | uint32_t reg, val, and_mask, or_mask; |
2905 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
2906 | |
2907 | if (!tmds) |
2908 | return false0; |
2909 | |
2910 | if (rdev->flags & RADEON_IS_IGP) { |
2911 | offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); |
2912 | rev = RBIOS8(offset)(rdev->bios[offset]); |
Value stored to 'rev' is never read | |
2913 | if (offset) { |
2914 | rev = RBIOS8(offset)(rdev->bios[offset]); |
2915 | if (rev > 1) { |
2916 | blocks = RBIOS8(offset + 3)(rdev->bios[offset + 3]); |
2917 | index = offset + 4; |
2918 | while (blocks > 0) { |
2919 | id = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8)); |
2920 | index += 2; |
2921 | switch (id >> 13) { |
2922 | case 0: |
2923 | reg = (id & 0x1fff) * 4; |
2924 | val = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index )+2)+1]) << 8)) << 16)); |
2925 | index += 4; |
2926 | WREG32(reg, val)r100_mm_wreg(rdev, (reg), (val), 0); |
2927 | break; |
2928 | case 2: |
2929 | reg = (id & 0x1fff) * 4; |
2930 | and_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index )+2)+1]) << 8)) << 16)); |
2931 | index += 4; |
2932 | or_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index )+2)+1]) << 8)) << 16)); |
2933 | index += 4; |
2934 | val = RREG32(reg)r100_mm_rreg(rdev, (reg), 0); |
2935 | val = (val & and_mask) | or_mask; |
2936 | WREG32(reg, val)r100_mm_wreg(rdev, (reg), (val), 0); |
2937 | break; |
2938 | case 3: |
2939 | val = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8)); |
2940 | index += 2; |
2941 | udelay(val); |
2942 | break; |
2943 | case 4: |
2944 | val = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8)); |
2945 | index += 2; |
2946 | mdelay(val); |
2947 | break; |
2948 | case 6: |
2949 | slave_addr = id & 0xff; |
2950 | slave_addr >>= 1; /* 7 bit addressing */ |
2951 | index++; |
2952 | reg = RBIOS8(index)(rdev->bios[index]); |
2953 | index++; |
2954 | val = RBIOS8(index)(rdev->bios[index]); |
2955 | index++; |
2956 | radeon_i2c_put_byte(tmds->i2c_bus, |
2957 | slave_addr, |
2958 | reg, val); |
2959 | break; |
2960 | default: |
2961 | DRM_ERROR("Unknown id %d\n", id >> 13)__drm_err("Unknown id %d\n", id >> 13); |
2962 | break; |
2963 | } |
2964 | blocks--; |
2965 | } |
2966 | return true1; |
2967 | } |
2968 | } |
2969 | } else { |
2970 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
2971 | if (offset) { |
2972 | index = offset + 10; |
2973 | id = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8)); |
2974 | while (id != 0xffff) { |
2975 | index += 2; |
2976 | switch (id >> 13) { |
2977 | case 0: |
2978 | reg = (id & 0x1fff) * 4; |
2979 | val = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index )+2)+1]) << 8)) << 16)); |
2980 | WREG32(reg, val)r100_mm_wreg(rdev, (reg), (val), 0); |
2981 | break; |
2982 | case 2: |
2983 | reg = (id & 0x1fff) * 4; |
2984 | and_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index )+2)+1]) << 8)) << 16)); |
2985 | index += 4; |
2986 | or_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index )+2)+1]) << 8)) << 16)); |
2987 | index += 4; |
2988 | val = RREG32(reg)r100_mm_rreg(rdev, (reg), 0); |
2989 | val = (val & and_mask) | or_mask; |
2990 | WREG32(reg, val)r100_mm_wreg(rdev, (reg), (val), 0); |
2991 | break; |
2992 | case 4: |
2993 | val = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8)); |
2994 | index += 2; |
2995 | udelay(val); |
2996 | break; |
2997 | case 5: |
2998 | reg = id & 0x1fff; |
2999 | and_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index )+2)+1]) << 8)) << 16)); |
3000 | index += 4; |
3001 | or_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index )+2)+1]) << 8)) << 16)); |
3002 | index += 4; |
3003 | val = RREG32_PLL(reg)rdev->pll_rreg(rdev, (reg)); |
3004 | val = (val & and_mask) | or_mask; |
3005 | WREG32_PLL(reg, val)rdev->pll_wreg(rdev, (reg), (val)); |
3006 | break; |
3007 | case 6: |
3008 | reg = id & 0x1fff; |
3009 | val = RBIOS8(index)(rdev->bios[index]); |
3010 | index += 1; |
3011 | radeon_i2c_put_byte(tmds->i2c_bus, |
3012 | tmds->slave_addr, |
3013 | reg, val); |
3014 | break; |
3015 | default: |
3016 | DRM_ERROR("Unknown id %d\n", id >> 13)__drm_err("Unknown id %d\n", id >> 13); |
3017 | break; |
3018 | } |
3019 | id = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) << 8)); |
3020 | } |
3021 | return true1; |
3022 | } |
3023 | } |
3024 | return false0; |
3025 | } |
3026 | |
3027 | static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) |
3028 | { |
3029 | struct radeon_device *rdev = dev->dev_private; |
3030 | |
3031 | if (offset) { |
3032 | while (RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8))) { |
3033 | uint16_t cmd = ((RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8)) & 0xe000) >> 13); |
3034 | uint32_t addr = (RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8)) & 0x1fff); |
3035 | uint32_t val, and_mask, or_mask; |
3036 | uint32_t tmp; |
3037 | |
3038 | offset += 2; |
3039 | switch (cmd) { |
3040 | case 0: |
3041 | val = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset )+2)+1]) << 8)) << 16)); |
3042 | offset += 4; |
3043 | WREG32(addr, val)r100_mm_wreg(rdev, (addr), (val), 0); |
3044 | break; |
3045 | case 1: |
3046 | val = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset )+2)+1]) << 8)) << 16)); |
3047 | offset += 4; |
3048 | WREG32(addr, val)r100_mm_wreg(rdev, (addr), (val), 0); |
3049 | break; |
3050 | case 2: |
3051 | and_mask = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset )+2)+1]) << 8)) << 16)); |
3052 | offset += 4; |
3053 | or_mask = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset )+2)+1]) << 8)) << 16)); |
3054 | offset += 4; |
3055 | tmp = RREG32(addr)r100_mm_rreg(rdev, (addr), 0); |
3056 | tmp &= and_mask; |
3057 | tmp |= or_mask; |
3058 | WREG32(addr, tmp)r100_mm_wreg(rdev, (addr), (tmp), 0); |
3059 | break; |
3060 | case 3: |
3061 | and_mask = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset )+2)+1]) << 8)) << 16)); |
3062 | offset += 4; |
3063 | or_mask = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset )+2)+1]) << 8)) << 16)); |
3064 | offset += 4; |
3065 | tmp = RREG32(addr)r100_mm_rreg(rdev, (addr), 0); |
3066 | tmp &= and_mask; |
3067 | tmp |= or_mask; |
3068 | WREG32(addr, tmp)r100_mm_wreg(rdev, (addr), (tmp), 0); |
3069 | break; |
3070 | case 4: |
3071 | val = RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8)); |
3072 | offset += 2; |
3073 | udelay(val); |
3074 | break; |
3075 | case 5: |
3076 | val = RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8)); |
3077 | offset += 2; |
3078 | switch (addr) { |
3079 | case 8: |
3080 | while (val--) { |
3081 | if (! |
3082 | (RREG32_PLLrdev->pll_rreg(rdev, (0x0014)) |
3083 | (RADEON_CLK_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0014)) & |
3084 | RADEON_MC_BUSY(1 << 16))) |
3085 | break; |
3086 | } |
3087 | break; |
3088 | case 9: |
3089 | while (val--) { |
3090 | if ((RREG32(RADEON_MC_STATUS)r100_mm_rreg(rdev, (0x0150), 0) & |
3091 | RADEON_MC_IDLE(1 << 2))) |
3092 | break; |
3093 | } |
3094 | break; |
3095 | default: |
3096 | break; |
3097 | } |
3098 | break; |
3099 | default: |
3100 | break; |
3101 | } |
3102 | } |
3103 | } |
3104 | } |
3105 | |
3106 | static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) |
3107 | { |
3108 | struct radeon_device *rdev = dev->dev_private; |
3109 | |
3110 | if (offset) { |
3111 | while (RBIOS8(offset)(rdev->bios[offset])) { |
3112 | uint8_t cmd = ((RBIOS8(offset)(rdev->bios[offset]) & 0xc0) >> 6); |
3113 | uint8_t addr = (RBIOS8(offset)(rdev->bios[offset]) & 0x3f); |
3114 | uint32_t val, shift, tmp; |
3115 | uint32_t and_mask, or_mask; |
3116 | |
3117 | offset++; |
3118 | switch (cmd) { |
3119 | case 0: |
3120 | val = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset )+2)+1]) << 8)) << 16)); |
3121 | offset += 4; |
3122 | WREG32_PLL(addr, val)rdev->pll_wreg(rdev, (addr), (val)); |
3123 | break; |
3124 | case 1: |
3125 | shift = RBIOS8(offset)(rdev->bios[offset]) * 8; |
3126 | offset++; |
3127 | and_mask = RBIOS8(offset)(rdev->bios[offset]) << shift; |
3128 | and_mask |= ~(0xff << shift); |
3129 | offset++; |
3130 | or_mask = RBIOS8(offset)(rdev->bios[offset]) << shift; |
3131 | offset++; |
3132 | tmp = RREG32_PLL(addr)rdev->pll_rreg(rdev, (addr)); |
3133 | tmp &= and_mask; |
3134 | tmp |= or_mask; |
3135 | WREG32_PLL(addr, tmp)rdev->pll_wreg(rdev, (addr), (tmp)); |
3136 | break; |
3137 | case 2: |
3138 | case 3: |
3139 | tmp = 1000; |
3140 | switch (addr) { |
3141 | case 1: |
3142 | udelay(150); |
3143 | break; |
3144 | case 2: |
3145 | mdelay(1); |
3146 | break; |
3147 | case 3: |
3148 | while (tmp--) { |
3149 | if (! |
3150 | (RREG32_PLLrdev->pll_rreg(rdev, (0x0014)) |
3151 | (RADEON_CLK_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0014)) & |
3152 | RADEON_MC_BUSY(1 << 16))) |
3153 | break; |
3154 | } |
3155 | break; |
3156 | case 4: |
3157 | while (tmp--) { |
3158 | if (RREG32_PLLrdev->pll_rreg(rdev, (0x0014)) |
3159 | (RADEON_CLK_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0014)) & |
3160 | RADEON_DLL_READY(1 << 19)) |
3161 | break; |
3162 | } |
3163 | break; |
3164 | case 5: |
3165 | tmp = |
3166 | RREG32_PLL(RADEON_CLK_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0014)); |
3167 | if (tmp & RADEON_CG_NO1_DEBUG_0(1 << 24)) { |
3168 | #if 0 |
3169 | uint32_t mclk_cntl = |
3170 | RREG32_PLLrdev->pll_rreg(rdev, (0x0012)) |
3171 | (RADEON_MCLK_CNTL)rdev->pll_rreg(rdev, (0x0012)); |
3172 | mclk_cntl &= 0xffff0000; |
3173 | /*mclk_cntl |= 0x00001111;*//* ??? */ |
3174 | WREG32_PLL(RADEON_MCLK_CNTL,rdev->pll_wreg(rdev, (0x0012), (mclk_cntl)) |
3175 | mclk_cntl)rdev->pll_wreg(rdev, (0x0012), (mclk_cntl)); |
3176 | mdelay(10); |
3177 | #endif |
3178 | WREG32_PLLrdev->pll_wreg(rdev, (0x0014), (tmp & ~(1 << 24) )) |
3179 | (RADEON_CLK_PWRMGT_CNTL,rdev->pll_wreg(rdev, (0x0014), (tmp & ~(1 << 24) )) |
3180 | tmp &rdev->pll_wreg(rdev, (0x0014), (tmp & ~(1 << 24) )) |
3181 | ~RADEON_CG_NO1_DEBUG_0)rdev->pll_wreg(rdev, (0x0014), (tmp & ~(1 << 24) )); |
3182 | mdelay(10); |
3183 | } |
3184 | break; |
3185 | default: |
3186 | break; |
3187 | } |
3188 | break; |
3189 | default: |
3190 | break; |
3191 | } |
3192 | } |
3193 | } |
3194 | } |
3195 | |
3196 | static void combios_parse_ram_reset_table(struct drm_device *dev, |
3197 | uint16_t offset) |
3198 | { |
3199 | struct radeon_device *rdev = dev->dev_private; |
3200 | uint32_t tmp; |
3201 | |
3202 | if (offset) { |
3203 | uint8_t val = RBIOS8(offset)(rdev->bios[offset]); |
3204 | while (val != 0xff) { |
3205 | offset++; |
3206 | |
3207 | if (val == 0x0f) { |
3208 | uint32_t channel_complete_mask; |
3209 | |
3210 | if (ASIC_IS_R300(rdev)((rdev->family == CHIP_R300) || (rdev->family == CHIP_RV350 ) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV380 ) || (rdev->family == CHIP_R420) || (rdev->family == CHIP_R423 ) || (rdev->family == CHIP_RV410) || (rdev->family == CHIP_RS400 ) || (rdev->family == CHIP_RS480))) |
3211 | channel_complete_mask = |
3212 | R300_MEM_PWRUP_COMPLETE0x0f; |
3213 | else |
3214 | channel_complete_mask = |
3215 | RADEON_MEM_PWRUP_COMPLETE0x03; |
3216 | tmp = 20000; |
3217 | while (tmp--) { |
3218 | if ((RREG32(RADEON_MEM_STR_CNTL)r100_mm_rreg(rdev, (0x0150), 0) & |
3219 | channel_complete_mask) == |
3220 | channel_complete_mask) |
3221 | break; |
3222 | } |
3223 | } else { |
3224 | uint32_t or_mask = RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) << 8)); |
3225 | offset += 2; |
3226 | |
3227 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG)r100_mm_rreg(rdev, (0x0158), 0); |
3228 | tmp &= RADEON_SDRAM_MODE_MASK0xffff0000; |
3229 | tmp |= or_mask; |
3230 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp)r100_mm_wreg(rdev, (0x0158), (tmp), 0); |
3231 | |
3232 | or_mask = val << 24; |
3233 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG)r100_mm_rreg(rdev, (0x0158), 0); |
3234 | tmp &= RADEON_B3MEM_RESET_MASK0x6fffffff; |
3235 | tmp |= or_mask; |
3236 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp)r100_mm_wreg(rdev, (0x0158), (tmp), 0); |
3237 | } |
3238 | val = RBIOS8(offset)(rdev->bios[offset]); |
3239 | } |
3240 | } |
3241 | } |
3242 | |
3243 | static uint32_t combios_detect_ram(struct drm_device *dev, int ram, |
3244 | int mem_addr_mapping) |
3245 | { |
3246 | struct radeon_device *rdev = dev->dev_private; |
3247 | uint32_t mem_cntl; |
3248 | uint32_t mem_size; |
3249 | uint32_t addr = 0; |
3250 | |
3251 | mem_cntl = RREG32(RADEON_MEM_CNTL)r100_mm_rreg(rdev, (0x0140), 0); |
3252 | if (mem_cntl & RV100_HALF_MODE(1 << 3)) |
3253 | ram /= 2; |
3254 | mem_size = ram; |
3255 | mem_cntl &= ~(0xff << 8); |
3256 | mem_cntl |= (mem_addr_mapping & 0xff) << 8; |
3257 | WREG32(RADEON_MEM_CNTL, mem_cntl)r100_mm_wreg(rdev, (0x0140), (mem_cntl), 0); |
3258 | RREG32(RADEON_MEM_CNTL)r100_mm_rreg(rdev, (0x0140), 0); |
3259 | |
3260 | /* sdram reset ? */ |
3261 | |
3262 | /* something like this???? */ |
3263 | while (ram--) { |
3264 | addr = ram * 1024 * 1024; |
3265 | /* write to each page */ |
3266 | WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef)r100_mm_wreg(rdev, ((addr) | (1 << 31)), (0xdeadbeef), 1 ); |
3267 | /* read back and verify */ |
3268 | if (RREG32_IDX((addr) | RADEON_MM_APER)r100_mm_rreg(rdev, ((addr) | (1 << 31)), 1) != 0xdeadbeef) |
3269 | return 0; |
3270 | } |
3271 | |
3272 | return mem_size; |
3273 | } |
3274 | |
3275 | static void combios_write_ram_size(struct drm_device *dev) |
3276 | { |
3277 | struct radeon_device *rdev = dev->dev_private; |
3278 | uint8_t rev; |
3279 | uint16_t offset; |
3280 | uint32_t mem_size = 0; |
3281 | uint32_t mem_cntl = 0; |
3282 | |
3283 | /* should do something smarter here I guess... */ |
3284 | if (rdev->flags & RADEON_IS_IGP) |
3285 | return; |
3286 | |
3287 | /* first check detected mem table */ |
3288 | offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); |
3289 | if (offset) { |
3290 | rev = RBIOS8(offset)(rdev->bios[offset]); |
3291 | if (rev < 3) { |
3292 | mem_cntl = RBIOS32(offset + 1)((((rdev->bios[offset + 1]) | ((rdev->bios[(offset + 1) +1]) << 8))) | (((rdev->bios[(offset + 1)+2]) | ((rdev ->bios[((offset + 1)+2)+1]) << 8)) << 16)); |
3293 | mem_size = RBIOS16(offset + 5)((rdev->bios[offset + 5]) | ((rdev->bios[(offset + 5)+1 ]) << 8)); |
3294 | if ((rdev->family < CHIP_R200) && |
3295 | !ASIC_IS_RN50(rdev)((rdev->pdev->device == 0x515e) || (rdev->pdev->device == 0x5969))) |
3296 | WREG32(RADEON_MEM_CNTL, mem_cntl)r100_mm_wreg(rdev, (0x0140), (mem_cntl), 0); |
3297 | } |
3298 | } |
3299 | |
3300 | if (!mem_size) { |
3301 | offset = |
3302 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); |
3303 | if (offset) { |
3304 | rev = RBIOS8(offset - 1)(rdev->bios[offset - 1]); |
3305 | if (rev < 1) { |
3306 | if ((rdev->family < CHIP_R200) |
3307 | && !ASIC_IS_RN50(rdev)((rdev->pdev->device == 0x515e) || (rdev->pdev->device == 0x5969))) { |
3308 | int ram = 0; |
3309 | int mem_addr_mapping = 0; |
3310 | |
3311 | while (RBIOS8(offset)(rdev->bios[offset])) { |
3312 | ram = RBIOS8(offset)(rdev->bios[offset]); |
3313 | mem_addr_mapping = |
3314 | RBIOS8(offset + 1)(rdev->bios[offset + 1]); |
3315 | if (mem_addr_mapping != 0x25) |
3316 | ram *= 2; |
3317 | mem_size = |
3318 | combios_detect_ram(dev, ram, |
3319 | mem_addr_mapping); |
3320 | if (mem_size) |
3321 | break; |
3322 | offset += 2; |
3323 | } |
3324 | } else |
3325 | mem_size = RBIOS8(offset)(rdev->bios[offset]); |
3326 | } else { |
3327 | mem_size = RBIOS8(offset)(rdev->bios[offset]); |
3328 | mem_size *= 2; /* convert to MB */ |
3329 | } |
3330 | } |
3331 | } |
3332 | |
3333 | mem_size *= (1024 * 1024); /* convert to bytes */ |
3334 | WREG32(RADEON_CONFIG_MEMSIZE, mem_size)r100_mm_wreg(rdev, (0x00f8), (mem_size), 0); |
3335 | } |
3336 | |
3337 | void radeon_combios_asic_init(struct drm_device *dev) |
3338 | { |
3339 | struct radeon_device *rdev = dev->dev_private; |
3340 | uint16_t table; |
3341 | |
3342 | /* port hardcoded mac stuff from radeonfb */ |
3343 | if (rdev->bios == NULL((void *)0)) |
3344 | return; |
3345 | |
3346 | /* ASIC INIT 1 */ |
3347 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); |
3348 | if (table) |
3349 | combios_parse_mmio_table(dev, table); |
3350 | |
3351 | /* PLL INIT */ |
3352 | table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); |
3353 | if (table) |
3354 | combios_parse_pll_table(dev, table); |
3355 | |
3356 | /* ASIC INIT 2 */ |
3357 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); |
3358 | if (table) |
3359 | combios_parse_mmio_table(dev, table); |
3360 | |
3361 | if (!(rdev->flags & RADEON_IS_IGP)) { |
3362 | /* ASIC INIT 4 */ |
3363 | table = |
3364 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); |
3365 | if (table) |
3366 | combios_parse_mmio_table(dev, table); |
3367 | |
3368 | /* RAM RESET */ |
3369 | table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); |
3370 | if (table) |
3371 | combios_parse_ram_reset_table(dev, table); |
3372 | |
3373 | /* ASIC INIT 3 */ |
3374 | table = |
3375 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); |
3376 | if (table) |
3377 | combios_parse_mmio_table(dev, table); |
3378 | |
3379 | /* write CONFIG_MEMSIZE */ |
3380 | combios_write_ram_size(dev); |
3381 | } |
3382 | |
3383 | /* quirk for rs4xx HP nx6125 laptop to make it resume |
3384 | * - it hangs on resume inside the dynclk 1 table. |
3385 | */ |
3386 | if (rdev->family == CHIP_RS480 && |
3387 | rdev->pdev->subsystem_vendor == 0x103c && |
3388 | rdev->pdev->subsystem_device == 0x308b) |
3389 | return; |
3390 | |
3391 | /* quirk for rs4xx HP dv5000 laptop to make it resume |
3392 | * - it hangs on resume inside the dynclk 1 table. |
3393 | */ |
3394 | if (rdev->family == CHIP_RS480 && |
3395 | rdev->pdev->subsystem_vendor == 0x103c && |
3396 | rdev->pdev->subsystem_device == 0x30a4) |
3397 | return; |
3398 | |
3399 | /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume |
3400 | * - it hangs on resume inside the dynclk 1 table. |
3401 | */ |
3402 | if (rdev->family == CHIP_RS480 && |
3403 | rdev->pdev->subsystem_vendor == 0x103c && |
3404 | rdev->pdev->subsystem_device == 0x30ae) |
3405 | return; |
3406 | |
3407 | /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume |
3408 | * - it hangs on resume inside the dynclk 1 table. |
3409 | */ |
3410 | if (rdev->family == CHIP_RS480 && |
3411 | rdev->pdev->subsystem_vendor == 0x103c && |
3412 | rdev->pdev->subsystem_device == 0x280a) |
3413 | return; |
3414 | /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume |
3415 | * - it hangs on resume inside the dynclk 1 table. |
3416 | */ |
3417 | if (rdev->family == CHIP_RS400 && |
3418 | rdev->pdev->subsystem_vendor == 0x1179 && |
3419 | rdev->pdev->subsystem_device == 0xff31) |
3420 | return; |
3421 | |
3422 | /* DYN CLK 1 */ |
3423 | table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); |
3424 | if (table) |
3425 | combios_parse_pll_table(dev, table); |
3426 | |
3427 | } |
3428 | |
3429 | void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) |
3430 | { |
3431 | struct radeon_device *rdev = dev->dev_private; |
3432 | uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; |
3433 | |
3434 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH)r100_mm_rreg(rdev, (0x0010), 0); |
3435 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0); |
3436 | bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH)r100_mm_rreg(rdev, (0x002c), 0); |
3437 | |
3438 | /* let the bios control the backlight */ |
3439 | bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN(1 << 26); |
3440 | |
3441 | /* tell the bios not to handle mode switching */ |
3442 | bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS(1 << 30) | |
3443 | RADEON_ACC_MODE_CHANGE(1 << 2)); |
3444 | |
3445 | /* tell the bios a driver is loaded */ |
3446 | bios_7_scratch |= RADEON_DRV_LOADED(1 << 12); |
3447 | |
3448 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch)r100_mm_wreg(rdev, (0x0010), (bios_0_scratch), 0); |
3449 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch)r100_mm_wreg(rdev, (0x0028), (bios_6_scratch), 0); |
3450 | WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch)r100_mm_wreg(rdev, (0x002c), (bios_7_scratch), 0); |
3451 | } |
3452 | |
3453 | void radeon_combios_output_lock(struct drm_encoder *encoder, bool_Bool lock) |
3454 | { |
3455 | struct drm_device *dev = encoder->dev; |
3456 | struct radeon_device *rdev = dev->dev_private; |
3457 | uint32_t bios_6_scratch; |
3458 | |
3459 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0); |
3460 | |
3461 | if (lock) |
3462 | bios_6_scratch |= RADEON_DRIVER_CRITICAL(1 << 27); |
3463 | else |
3464 | bios_6_scratch &= ~RADEON_DRIVER_CRITICAL(1 << 27); |
3465 | |
3466 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch)r100_mm_wreg(rdev, (0x0028), (bios_6_scratch), 0); |
3467 | } |
3468 | |
3469 | void |
3470 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, |
3471 | struct drm_encoder *encoder, |
3472 | bool_Bool connected) |
3473 | { |
3474 | struct drm_device *dev = connector->dev; |
3475 | struct radeon_device *rdev = dev->dev_private; |
3476 | struct radeon_connector *radeon_connector = |
3477 | to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) * __mptr = (connector); (struct radeon_connector *)( (char *)__mptr - __builtin_offsetof(struct radeon_connector, base) );}); |
3478 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof (struct radeon_encoder, base) );}); |
3479 | uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH)r100_mm_rreg(rdev, (0x0020), 0); |
3480 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH)r100_mm_rreg(rdev, (0x0024), 0); |
3481 | |
3482 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )) && |
3483 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ))) { |
3484 | if (connected) { |
3485 | DRM_DEBUG_KMS("TV1 connected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "TV1 connected\n"); |
3486 | /* fix me */ |
3487 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO(2 << 4); |
3488 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ |
3489 | bios_5_scratch |= RADEON_TV1_ON(1 << 2); |
3490 | bios_5_scratch |= RADEON_ACC_REQ_TV1(1 << 18); |
3491 | } else { |
3492 | DRM_DEBUG_KMS("TV1 disconnected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "TV1 disconnected\n"); |
3493 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK(3 << 4); |
3494 | bios_5_scratch &= ~RADEON_TV1_ON(1 << 2); |
3495 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1(1 << 18); |
3496 | } |
3497 | } |
3498 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )) && |
3499 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ))) { |
3500 | if (connected) { |
3501 | DRM_DEBUG_KMS("LCD1 connected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "LCD1 connected\n"); |
3502 | bios_4_scratch |= RADEON_LCD1_ATTACHED(1 << 2); |
3503 | bios_5_scratch |= RADEON_LCD1_ON(1 << 0); |
3504 | bios_5_scratch |= RADEON_ACC_REQ_LCD1(1 << 16); |
3505 | } else { |
3506 | DRM_DEBUG_KMS("LCD1 disconnected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "LCD1 disconnected\n"); |
3507 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED(1 << 2); |
3508 | bios_5_scratch &= ~RADEON_LCD1_ON(1 << 0); |
3509 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1(1 << 16); |
3510 | } |
3511 | } |
3512 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )) && |
3513 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ))) { |
3514 | if (connected) { |
3515 | DRM_DEBUG_KMS("CRT1 connected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "CRT1 connected\n"); |
3516 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR(2 << 0); |
3517 | bios_5_scratch |= RADEON_CRT1_ON(1 << 1); |
3518 | bios_5_scratch |= RADEON_ACC_REQ_CRT1(1 << 17); |
3519 | } else { |
3520 | DRM_DEBUG_KMS("CRT1 disconnected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "CRT1 disconnected\n"); |
3521 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK(3 << 0); |
3522 | bios_5_scratch &= ~RADEON_CRT1_ON(1 << 1); |
3523 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1(1 << 17); |
3524 | } |
3525 | } |
3526 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )) && |
3527 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ))) { |
3528 | if (connected) { |
3529 | DRM_DEBUG_KMS("CRT2 connected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "CRT2 connected\n"); |
3530 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR(2 << 8); |
3531 | bios_5_scratch |= RADEON_CRT2_ON(1 << 5); |
3532 | bios_5_scratch |= RADEON_ACC_REQ_CRT2(1 << 21); |
3533 | } else { |
3534 | DRM_DEBUG_KMS("CRT2 disconnected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "CRT2 disconnected\n"); |
3535 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK(3 << 8); |
3536 | bios_5_scratch &= ~RADEON_CRT2_ON(1 << 5); |
3537 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2(1 << 21); |
3538 | } |
3539 | } |
3540 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )) && |
3541 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ))) { |
3542 | if (connected) { |
3543 | DRM_DEBUG_KMS("DFP1 connected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "DFP1 connected\n"); |
3544 | bios_4_scratch |= RADEON_DFP1_ATTACHED(1 << 3); |
3545 | bios_5_scratch |= RADEON_DFP1_ON(1 << 3); |
3546 | bios_5_scratch |= RADEON_ACC_REQ_DFP1(1 << 19); |
3547 | } else { |
3548 | DRM_DEBUG_KMS("DFP1 disconnected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "DFP1 disconnected\n"); |
3549 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED(1 << 3); |
3550 | bios_5_scratch &= ~RADEON_DFP1_ON(1 << 3); |
3551 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1(1 << 19); |
3552 | } |
3553 | } |
3554 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )) && |
3555 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ))) { |
3556 | if (connected) { |
3557 | DRM_DEBUG_KMS("DFP2 connected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "DFP2 connected\n"); |
3558 | bios_4_scratch |= RADEON_DFP2_ATTACHED(1 << 11); |
3559 | bios_5_scratch |= RADEON_DFP2_ON(1 << 7); |
3560 | bios_5_scratch |= RADEON_ACC_REQ_DFP2(1 << 23); |
3561 | } else { |
3562 | DRM_DEBUG_KMS("DFP2 disconnected\n")___drm_dbg(((void *)0), DRM_UT_KMS, "DFP2 disconnected\n"); |
3563 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED(1 << 11); |
3564 | bios_5_scratch &= ~RADEON_DFP2_ON(1 << 7); |
3565 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2(1 << 23); |
3566 | } |
3567 | } |
3568 | WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch)r100_mm_wreg(rdev, (0x0020), (bios_4_scratch), 0); |
3569 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch)r100_mm_wreg(rdev, (0x0024), (bios_5_scratch), 0); |
3570 | } |
3571 | |
3572 | void |
3573 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
3574 | { |
3575 | struct drm_device *dev = encoder->dev; |
3576 | struct radeon_device *rdev = dev->dev_private; |
3577 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof (struct radeon_encoder, base) );}); |
3578 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH)r100_mm_rreg(rdev, (0x0024), 0); |
3579 | |
3580 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )) { |
3581 | bios_5_scratch &= ~RADEON_TV1_CRTC_MASK(1 << 10); |
3582 | bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT10); |
3583 | } |
3584 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )) { |
3585 | bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK(1 << 9); |
3586 | bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT9); |
3587 | } |
3588 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )) { |
3589 | bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK(1 << 12); |
3590 | bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT12); |
3591 | } |
3592 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )) { |
3593 | bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK(1 << 8); |
3594 | bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT8); |
3595 | } |
3596 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )) { |
3597 | bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK(1 << 11); |
3598 | bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT11); |
3599 | } |
3600 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )) { |
3601 | bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK(1 << 14); |
3602 | bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT14); |
3603 | } |
3604 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch)r100_mm_wreg(rdev, (0x0024), (bios_5_scratch), 0); |
3605 | } |
3606 | |
3607 | void |
3608 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool_Bool on) |
3609 | { |
3610 | struct drm_device *dev = encoder->dev; |
3611 | struct radeon_device *rdev = dev->dev_private; |
3612 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr = (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof (struct radeon_encoder, base) );}); |
3613 | uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0); |
3614 | |
3615 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 )))) { |
3616 | if (on) |
3617 | bios_6_scratch |= RADEON_TV_DPMS_ON(1 << 22); |
3618 | else |
3619 | bios_6_scratch &= ~RADEON_TV_DPMS_ON(1 << 22); |
3620 | } |
3621 | if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 )))) { |
3622 | if (on) |
3623 | bios_6_scratch |= RADEON_CRT_DPMS_ON(1 << 21); |
3624 | else |
3625 | bios_6_scratch &= ~RADEON_CRT_DPMS_ON(1 << 21); |
3626 | } |
3627 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) { |
3628 | if (on) |
3629 | bios_6_scratch |= RADEON_LCD_DPMS_ON(1 << 20); |
3630 | else |
3631 | bios_6_scratch &= ~RADEON_LCD_DPMS_ON(1 << 20); |
3632 | } |
3633 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | ( 0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L << 0x0000000B ) | (0x1L << 0x00000006 )))) { |
3634 | if (on) |
3635 | bios_6_scratch |= RADEON_DFP_DPMS_ON(1 << 23); |
3636 | else |
3637 | bios_6_scratch &= ~RADEON_DFP_DPMS_ON(1 << 23); |
3638 | } |
3639 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch)r100_mm_wreg(rdev, (0x0028), (bios_6_scratch), 0); |
3640 | } |