File: | dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c |
Warning: | line 819, column 18 Access to field 'stream' results in a dereference of an undefined pointer value |
Press '?' to see keyboard shortcuts
Keyboard shortcuts:
1 | // SPDX-License-Identifier: MIT | |||
2 | /* | |||
3 | * Copyright 2022 Advanced Micro Devices, Inc. | |||
4 | * | |||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
6 | * copy of this software and associated documentation files (the "Software"), | |||
7 | * to deal in the Software without restriction, including without limitation | |||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
9 | * and/or sell copies of the Software, and to permit persons to whom the | |||
10 | * Software is furnished to do so, subject to the following conditions: | |||
11 | * | |||
12 | * The above copyright notice and this permission notice shall be included in | |||
13 | * all copies or substantial portions of the Software. | |||
14 | * | |||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
21 | * OTHER DEALINGS IN THE SOFTWARE. | |||
22 | * | |||
23 | * Authors: AMD | |||
24 | * | |||
25 | */ | |||
26 | #include "dcn32_fpu.h" | |||
27 | #include "dc_link_dp.h" | |||
28 | #include "dcn32/dcn32_resource.h" | |||
29 | #include "dcn20/dcn20_resource.h" | |||
30 | #include "display_mode_vba_util_32.h" | |||
31 | // We need this includes for WATERMARKS_* defines | |||
32 | #include "clk_mgr/dcn32/dcn32_smu13_driver_if.h" | |||
33 | #include "dcn30/dcn30_resource.h" | |||
34 | ||||
35 | #define DC_LOGGER_INIT(logger) | |||
36 | ||||
37 | struct _vcs_dpi_ip_params_st dcn3_2_ip = { | |||
38 | .gpuvm_enable = 0, | |||
39 | .gpuvm_max_page_table_levels = 4, | |||
40 | .hostvm_enable = 0, | |||
41 | .rob_buffer_size_kbytes = 128, | |||
42 | .det_buffer_size_kbytes = DCN3_2_DEFAULT_DET_SIZE256, | |||
43 | .config_return_buffer_size_in_kbytes = 1280, | |||
44 | .compressed_buffer_segment_size_in_kbytes = 64, | |||
45 | .meta_fifo_size_in_kentries = 22, | |||
46 | .zero_size_buffer_entries = 512, | |||
47 | .compbuf_reserved_space_64b = 256, | |||
48 | .compbuf_reserved_space_zs = 64, | |||
49 | .dpp_output_buffer_pixels = 2560, | |||
50 | .opp_output_buffer_lines = 1, | |||
51 | .pixel_chunk_size_kbytes = 8, | |||
52 | .alpha_pixel_chunk_size_kbytes = 4, | |||
53 | .min_pixel_chunk_size_bytes = 1024, | |||
54 | .dcc_meta_buffer_size_bytes = 6272, | |||
55 | .meta_chunk_size_kbytes = 2, | |||
56 | .min_meta_chunk_size_bytes = 256, | |||
57 | .writeback_chunk_size_kbytes = 8, | |||
58 | .ptoi_supported = false0, | |||
59 | .num_dsc = 4, | |||
60 | .maximum_dsc_bits_per_component = 12, | |||
61 | .maximum_pixels_per_line_per_dsc_unit = 6016, | |||
62 | .dsc422_native_support = true1, | |||
63 | .is_line_buffer_bpp_fixed = true1, | |||
64 | .line_buffer_fixed_bpp = 57, | |||
65 | .line_buffer_size_bits = 1171920, | |||
66 | .max_line_buffer_lines = 32, | |||
67 | .writeback_interface_buffer_size_kbytes = 90, | |||
68 | .max_num_dpp = 4, | |||
69 | .max_num_otg = 4, | |||
70 | .max_num_hdmi_frl_outputs = 1, | |||
71 | .max_num_wb = 1, | |||
72 | .max_dchub_pscl_bw_pix_per_clk = 4, | |||
73 | .max_pscl_lb_bw_pix_per_clk = 2, | |||
74 | .max_lb_vscl_bw_pix_per_clk = 4, | |||
75 | .max_vscl_hscl_bw_pix_per_clk = 4, | |||
76 | .max_hscl_ratio = 6, | |||
77 | .max_vscl_ratio = 6, | |||
78 | .max_hscl_taps = 8, | |||
79 | .max_vscl_taps = 8, | |||
80 | .dpte_buffer_size_in_pte_reqs_luma = 64, | |||
81 | .dpte_buffer_size_in_pte_reqs_chroma = 34, | |||
82 | .dispclk_ramp_margin_percent = 1, | |||
83 | .max_inter_dcn_tile_repeaters = 8, | |||
84 | .cursor_buffer_size = 16, | |||
85 | .cursor_chunk_size = 2, | |||
86 | .writeback_line_buffer_buffer_size = 0, | |||
87 | .writeback_min_hscl_ratio = 1, | |||
88 | .writeback_min_vscl_ratio = 1, | |||
89 | .writeback_max_hscl_ratio = 1, | |||
90 | .writeback_max_vscl_ratio = 1, | |||
91 | .writeback_max_hscl_taps = 1, | |||
92 | .writeback_max_vscl_taps = 1, | |||
93 | .dppclk_delay_subtotal = 47, | |||
94 | .dppclk_delay_scl = 50, | |||
95 | .dppclk_delay_scl_lb_only = 16, | |||
96 | .dppclk_delay_cnvc_formatter = 28, | |||
97 | .dppclk_delay_cnvc_cursor = 6, | |||
98 | .dispclk_delay_subtotal = 125, | |||
99 | .dynamic_metadata_vm_enabled = false0, | |||
100 | .odm_combine_4to1_supported = false0, | |||
101 | .dcc_supported = true1, | |||
102 | .max_num_dp2p0_outputs = 2, | |||
103 | .max_num_dp2p0_streams = 4, | |||
104 | }; | |||
105 | ||||
106 | struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = { | |||
107 | .clock_limits = { | |||
108 | { | |||
109 | .state = 0, | |||
110 | .dcfclk_mhz = 1564.0, | |||
111 | .fabricclk_mhz = 400.0, | |||
112 | .dispclk_mhz = 2150.0, | |||
113 | .dppclk_mhz = 2150.0, | |||
114 | .phyclk_mhz = 810.0, | |||
115 | .phyclk_d18_mhz = 667.0, | |||
116 | .phyclk_d32_mhz = 625.0, | |||
117 | .socclk_mhz = 1200.0, | |||
118 | .dscclk_mhz = 716.667, | |||
119 | .dram_speed_mts = 16000.0, | |||
120 | .dtbclk_mhz = 1564.0, | |||
121 | }, | |||
122 | }, | |||
123 | .num_states = 1, | |||
124 | .sr_exit_time_us = 42.97, | |||
125 | .sr_enter_plus_exit_time_us = 49.94, | |||
126 | .sr_exit_z8_time_us = 285.0, | |||
127 | .sr_enter_plus_exit_z8_time_us = 320, | |||
128 | .writeback_latency_us = 12.0, | |||
129 | .round_trip_ping_latency_dcfclk_cycles = 263, | |||
130 | .urgent_latency_pixel_data_only_us = 4.0, | |||
131 | .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, | |||
132 | .urgent_latency_vm_data_only_us = 4.0, | |||
133 | .fclk_change_latency_us = 20, | |||
134 | .usr_retraining_latency_us = 2, | |||
135 | .smn_latency_us = 2, | |||
136 | .mall_allocated_for_dcn_mbytes = 64, | |||
137 | .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, | |||
138 | .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, | |||
139 | .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, | |||
140 | .pct_ideal_sdp_bw_after_urgent = 90.0, | |||
141 | .pct_ideal_fabric_bw_after_urgent = 67.0, | |||
142 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 20.0, | |||
143 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, // N/A, for now keep as is until DML implemented | |||
144 | .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0, // N/A, for now keep as is until DML implemented | |||
145 | .pct_ideal_dram_bw_after_urgent_strobe = 67.0, | |||
146 | .max_avg_sdp_bw_use_normal_percent = 80.0, | |||
147 | .max_avg_fabric_bw_use_normal_percent = 60.0, | |||
148 | .max_avg_dram_bw_use_normal_strobe_percent = 50.0, | |||
149 | .max_avg_dram_bw_use_normal_percent = 15.0, | |||
150 | .num_chans = 8, | |||
151 | .dram_channel_width_bytes = 2, | |||
152 | .fabric_datapath_to_dcn_data_return_bytes = 64, | |||
153 | .return_bus_width_bytes = 64, | |||
154 | .downspread_percent = 0.38, | |||
155 | .dcn_downspread_percent = 0.5, | |||
156 | .dram_clock_change_latency_us = 400, | |||
157 | .dispclk_dppclk_vco_speed_mhz = 4300.0, | |||
158 | .do_urgent_latency_adjustment = true1, | |||
159 | .urgent_latency_adjustment_fabric_clock_component_us = 1.0, | |||
160 | .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000, | |||
161 | }; | |||
162 | ||||
163 | void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr) | |||
164 | { | |||
165 | /* defaults */ | |||
166 | double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; | |||
167 | double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us; | |||
168 | double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; | |||
169 | double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; | |||
170 | /* For min clocks use as reported by PM FW and report those as min */ | |||
171 | uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; | |||
172 | uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; | |||
173 | uint16_t setb_min_uclk_mhz = min_uclk_mhz; | |||
174 | uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; | |||
175 | ||||
176 | dc_assert_fp_enabled(); | |||
177 | ||||
178 | /* For Set B ranges use min clocks state 2 when available, and report those to PM FW */ | |||
179 | if (dcfclk_mhz_for_the_second_state) | |||
180 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state; | |||
181 | else | |||
182 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; | |||
183 | ||||
184 | if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) | |||
185 | setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; | |||
186 | ||||
187 | /* Set A - Normal - default values */ | |||
188 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].valid = true1; | |||
189 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].dml_input.pstate_latency_us = pstate_latency_us; | |||
190 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].dml_input.fclk_change_latency_us = fclk_change_latency_us; | |||
191 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].dml_input.sr_exit_time_us = sr_exit_time_us; | |||
192 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; | |||
193 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; | |||
194 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; | |||
195 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].pmfw_breakdown.max_dcfclk = 0xFFFF; | |||
196 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].pmfw_breakdown.min_uclk = min_uclk_mhz; | |||
197 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_A0].pmfw_breakdown.max_uclk = 0xFFFF; | |||
198 | ||||
199 | /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */ | |||
200 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].valid = true1; | |||
201 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].dml_input.pstate_latency_us = pstate_latency_us; | |||
202 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].dml_input.fclk_change_latency_us = fclk_change_latency_us; | |||
203 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].dml_input.sr_exit_time_us = sr_exit_time_us; | |||
204 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; | |||
205 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; | |||
206 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].pmfw_breakdown.max_dcfclk = 0xFFFF; | |||
207 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].pmfw_breakdown.min_uclk = setb_min_uclk_mhz; | |||
208 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_B1].pmfw_breakdown.max_uclk = 0xFFFF; | |||
209 | ||||
210 | /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ | |||
211 | /* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */ | |||
212 | if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) { | |||
213 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].valid = true1; | |||
214 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].dml_input.pstate_latency_us = 50; | |||
215 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].dml_input.fclk_change_latency_us = fclk_change_latency_us; | |||
216 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].dml_input.sr_exit_time_us = sr_exit_time_us; | |||
217 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; | |||
218 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; | |||
219 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; | |||
220 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].pmfw_breakdown.max_dcfclk = 0xFFFF; | |||
221 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].pmfw_breakdown.min_uclk = min_uclk_mhz; | |||
222 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_C2].pmfw_breakdown.max_uclk = 0xFFFF; | |||
223 | clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; | |||
224 | clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; | |||
225 | clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; | |||
226 | clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; | |||
227 | clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; | |||
228 | clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; | |||
229 | clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; | |||
230 | clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; | |||
231 | } | |||
232 | /* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */ | |||
233 | /* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */ | |||
234 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].valid = true1; | |||
235 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us; | |||
236 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].dml_input.fclk_change_latency_us = fclk_change_latency_us; | |||
237 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD | |||
238 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD | |||
239 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].pmfw_breakdown.wm_type = WATERMARKS_MALL; | |||
240 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; | |||
241 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].pmfw_breakdown.max_dcfclk = 0xFFFF; | |||
242 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].pmfw_breakdown.min_uclk = min_uclk_mhz; | |||
243 | clk_mgr->base.bw_params->wm_table.nv_entries[WM_D3].pmfw_breakdown.max_uclk = 0xFFFF; | |||
244 | } | |||
245 | ||||
246 | /* | |||
247 | * Finds dummy_latency_index when MCLK switching using firmware based | |||
248 | * vblank stretch is enabled. This function will iterate through the | |||
249 | * table of dummy pstate latencies until the lowest value that allows | |||
250 | * dm_allow_self_refresh_and_mclk_switch to happen is found | |||
251 | */ | |||
252 | int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, | |||
253 | struct dc_state *context, | |||
254 | display_e2e_pipe_params_st *pipes, | |||
255 | int pipe_cnt, | |||
256 | int vlevel) | |||
257 | { | |||
258 | const int max_latency_table_entries = 4; | |||
259 | const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; | |||
260 | int dummy_latency_index = 0; | |||
261 | ||||
262 | dc_assert_fp_enabled(); | |||
263 | ||||
264 | while (dummy_latency_index < max_latency_table_entries) { | |||
265 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = | |||
266 | dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; | |||
267 | dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false0); | |||
268 | ||||
269 | if (vlevel < context->bw_ctx.dml.vba.soc.num_states && | |||
270 | vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported) | |||
271 | break; | |||
272 | ||||
273 | dummy_latency_index++; | |||
274 | } | |||
275 | ||||
276 | if (dummy_latency_index == max_latency_table_entries) { | |||
277 | ASSERT(dummy_latency_index != max_latency_table_entries)do { if (({ static int __warned; int __ret = !!(!(dummy_latency_index != max_latency_table_entries)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dummy_latency_index != max_latency_table_entries)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 277); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
278 | /* If the execution gets here, it means dummy p_states are | |||
279 | * not possible. This should never happen and would mean | |||
280 | * something is severely wrong. | |||
281 | * Here we reset dummy_latency_index to 3, because it is | |||
282 | * better to have underflows than system crashes. | |||
283 | */ | |||
284 | dummy_latency_index = max_latency_table_entries - 1; | |||
285 | } | |||
286 | ||||
287 | return dummy_latency_index; | |||
288 | } | |||
289 | ||||
290 | /** | |||
291 | * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes | |||
292 | * and populate pipe_ctx with those params. | |||
293 | * @dc: [in] current dc state | |||
294 | * @context: [in] new dc state | |||
295 | * @pipes: [in] DML pipe params array | |||
296 | * @pipe_cnt: [in] DML pipe count | |||
297 | * | |||
298 | * This function must be called AFTER the phantom pipes are added to context | |||
299 | * and run through DML (so that the DLG params for the phantom pipes can be | |||
300 | * populated), and BEFORE we program the timing for the phantom pipes. | |||
301 | */ | |||
302 | void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, | |||
303 | struct dc_state *context, | |||
304 | display_e2e_pipe_params_st *pipes, | |||
305 | int pipe_cnt) | |||
306 | { | |||
307 | uint32_t i, pipe_idx; | |||
308 | ||||
309 | dc_assert_fp_enabled(); | |||
310 | ||||
311 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
312 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
313 | ||||
314 | if (!pipe->stream) | |||
315 | continue; | |||
316 | ||||
317 | if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { | |||
318 | pipes[pipe_idx].pipe.dest.vstartup_start = | |||
319 | get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
320 | pipes[pipe_idx].pipe.dest.vupdate_offset = | |||
321 | get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
322 | pipes[pipe_idx].pipe.dest.vupdate_width = | |||
323 | get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
324 | pipes[pipe_idx].pipe.dest.vready_offset = | |||
325 | get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
326 | pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; | |||
327 | } | |||
328 | pipe_idx++; | |||
329 | } | |||
330 | } | |||
331 | ||||
332 | /** | |||
333 | * dcn32_predict_pipe_split - Predict if pipe split will occur for a given DML pipe | |||
334 | * @context: [in] New DC state to be programmed | |||
335 | * @pipe_e2e: [in] DML pipe end to end context | |||
336 | * | |||
337 | * This function takes in a DML pipe (pipe_e2e) and predicts if pipe split is required (both | |||
338 | * ODM and MPC). For pipe split, ODM combine is determined by the ODM mode, and MPC combine is | |||
339 | * determined by DPPClk requirements | |||
340 | * | |||
341 | * This function follows the same policy as DML: | |||
342 | * - Check for ODM combine requirements / policy first | |||
343 | * - MPC combine is only chosen if there is no ODM combine requirements / policy in place, and | |||
344 | * MPC is required | |||
345 | * | |||
346 | * Return: Number of splits expected (1 for 2:1 split, 3 for 4:1 split, 0 for no splits). | |||
347 | */ | |||
348 | uint8_t dcn32_predict_pipe_split(struct dc_state *context, | |||
349 | display_e2e_pipe_params_st *pipe_e2e) | |||
350 | { | |||
351 | double pscl_throughput; | |||
352 | double pscl_throughput_chroma; | |||
353 | double dpp_clk_single_dpp, clock; | |||
354 | double clk_frequency = 0.0; | |||
355 | double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz; | |||
356 | bool_Bool total_available_pipes_support = false0; | |||
357 | uint32_t number_of_dpp = 0; | |||
358 | enum odm_combine_mode odm_mode = dm_odm_combine_mode_disabled; | |||
359 | double req_dispclk_per_surface = 0; | |||
360 | uint8_t num_splits = 0; | |||
361 | ||||
362 | dc_assert_fp_enabled(); | |||
363 | ||||
364 | dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit, | |||
365 | pipe_e2e->pipe.dest.hactive, | |||
366 | pipe_e2e->dout.output_format, | |||
367 | pipe_e2e->dout.output_type, | |||
368 | pipe_e2e->pipe.dest.odm_combine_policy, | |||
369 | context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, | |||
370 | context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, | |||
371 | pipe_e2e->dout.dsc_enable != 0, | |||
372 | 0, /* TotalNumberOfActiveDPP can be 0 since we're predicting pipe split requirement */ | |||
373 | context->bw_ctx.dml.ip.max_num_dpp, | |||
374 | pipe_e2e->pipe.dest.pixel_rate_mhz, | |||
375 | context->bw_ctx.dml.soc.dcn_downspread_percent, | |||
376 | context->bw_ctx.dml.ip.dispclk_ramp_margin_percent, | |||
377 | context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz, | |||
378 | pipe_e2e->dout.dsc_slices, | |||
379 | /* Output */ | |||
380 | &total_available_pipes_support, | |||
381 | &number_of_dpp, | |||
382 | &odm_mode, | |||
383 | &req_dispclk_per_surface); | |||
384 | ||||
385 | dml32_CalculateSinglePipeDPPCLKAndSCLThroughput(pipe_e2e->pipe.scale_ratio_depth.hscl_ratio, | |||
386 | pipe_e2e->pipe.scale_ratio_depth.hscl_ratio_c, | |||
387 | pipe_e2e->pipe.scale_ratio_depth.vscl_ratio, | |||
388 | pipe_e2e->pipe.scale_ratio_depth.vscl_ratio_c, | |||
389 | context->bw_ctx.dml.ip.max_dchub_pscl_bw_pix_per_clk, | |||
390 | context->bw_ctx.dml.ip.max_pscl_lb_bw_pix_per_clk, | |||
391 | pipe_e2e->pipe.dest.pixel_rate_mhz, | |||
392 | pipe_e2e->pipe.src.source_format, | |||
393 | pipe_e2e->pipe.scale_taps.htaps, | |||
394 | pipe_e2e->pipe.scale_taps.htaps_c, | |||
395 | pipe_e2e->pipe.scale_taps.vtaps, | |||
396 | pipe_e2e->pipe.scale_taps.vtaps_c, | |||
397 | /* Output */ | |||
398 | &pscl_throughput, &pscl_throughput_chroma, | |||
399 | &dpp_clk_single_dpp); | |||
400 | ||||
401 | clock = dpp_clk_single_dpp * (1 + context->bw_ctx.dml.soc.dcn_downspread_percent / 100); | |||
402 | ||||
403 | if (clock > 0) | |||
404 | clk_frequency = vco_speed * 4.0 / ((int)(vco_speed * 4.0) / clock); | |||
405 | ||||
406 | if (odm_mode == dm_odm_combine_mode_2to1) | |||
407 | num_splits = 1; | |||
408 | else if (odm_mode == dm_odm_combine_mode_4to1) | |||
409 | num_splits = 3; | |||
410 | else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dppclk_mhz) | |||
411 | num_splits = 1; | |||
412 | ||||
413 | return num_splits; | |||
414 | } | |||
415 | ||||
416 | static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) | |||
417 | { | |||
418 | float memory_bw_kbytes_sec; | |||
419 | float fabric_bw_kbytes_sec; | |||
420 | float sdp_bw_kbytes_sec; | |||
421 | float limiting_bw_kbytes_sec; | |||
422 | ||||
423 | memory_bw_kbytes_sec = entry->dram_speed_mts * | |||
424 | dcn3_2_soc.num_chans * | |||
425 | dcn3_2_soc.dram_channel_width_bytes * | |||
426 | ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); | |||
427 | ||||
428 | fabric_bw_kbytes_sec = entry->fabricclk_mhz * | |||
429 | dcn3_2_soc.return_bus_width_bytes * | |||
430 | ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); | |||
431 | ||||
432 | sdp_bw_kbytes_sec = entry->dcfclk_mhz * | |||
433 | dcn3_2_soc.return_bus_width_bytes * | |||
434 | ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); | |||
435 | ||||
436 | limiting_bw_kbytes_sec = memory_bw_kbytes_sec; | |||
437 | ||||
438 | if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec) | |||
439 | limiting_bw_kbytes_sec = fabric_bw_kbytes_sec; | |||
440 | ||||
441 | if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec) | |||
442 | limiting_bw_kbytes_sec = sdp_bw_kbytes_sec; | |||
443 | ||||
444 | return limiting_bw_kbytes_sec; | |||
445 | } | |||
446 | ||||
447 | static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) | |||
448 | { | |||
449 | if (entry->dcfclk_mhz > 0) { | |||
450 | float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100); | |||
451 | ||||
452 | entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); | |||
453 | entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * | |||
454 | dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); | |||
455 | } else if (entry->fabricclk_mhz > 0) { | |||
456 | float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100); | |||
457 | ||||
458 | entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); | |||
459 | entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * | |||
460 | dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); | |||
461 | } else if (entry->dram_speed_mts > 0) { | |||
462 | float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * | |||
463 | dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100); | |||
464 | ||||
465 | entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100)); | |||
466 | entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100)); | |||
467 | } | |||
468 | } | |||
469 | ||||
470 | void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, | |||
471 | unsigned int *num_entries, | |||
472 | struct _vcs_dpi_voltage_scaling_st *entry) | |||
473 | { | |||
474 | int i = 0; | |||
475 | int index = 0; | |||
476 | float net_bw_of_new_state = 0; | |||
477 | ||||
478 | dc_assert_fp_enabled(); | |||
479 | ||||
480 | get_optimal_ntuple(entry); | |||
481 | ||||
482 | if (*num_entries == 0) { | |||
483 | table[0] = *entry; | |||
484 | (*num_entries)++; | |||
485 | } else { | |||
486 | net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry); | |||
487 | while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) { | |||
488 | index++; | |||
489 | if (index >= *num_entries) | |||
490 | break; | |||
491 | } | |||
492 | ||||
493 | for (i = *num_entries; i > index; i--) | |||
494 | table[i] = table[i - 1]; | |||
495 | ||||
496 | table[index] = *entry; | |||
497 | (*num_entries)++; | |||
498 | } | |||
499 | } | |||
500 | ||||
501 | /** | |||
502 | * dcn32_set_phantom_stream_timing - Set timing params for the phantom stream | |||
503 | * @dc: current dc state | |||
504 | * @context: new dc state | |||
505 | * @ref_pipe: Main pipe for the phantom stream | |||
506 | * @phantom_stream: target phantom stream state | |||
507 | * @pipes: DML pipe params | |||
508 | * @pipe_cnt: number of DML pipes | |||
509 | * @dc_pipe_idx: DC pipe index for the main pipe (i.e. ref_pipe) | |||
510 | * | |||
511 | * Set timing params of the phantom stream based on calculated output from DML. | |||
512 | * This function first gets the DML pipe index using the DC pipe index, then | |||
513 | * calls into DML (get_subviewport_lines_needed_in_mall) to get the number of | |||
514 | * lines required for SubVP MCLK switching and assigns to the phantom stream | |||
515 | * accordingly. | |||
516 | * | |||
517 | * - The number of SubVP lines calculated in DML does not take into account | |||
518 | * FW processing delays and required pstate allow width, so we must include | |||
519 | * that separately. | |||
520 | * | |||
521 | * - Set phantom backporch = vstartup of main pipe | |||
522 | */ | |||
523 | void dcn32_set_phantom_stream_timing(struct dc *dc, | |||
524 | struct dc_state *context, | |||
525 | struct pipe_ctx *ref_pipe, | |||
526 | struct dc_stream_state *phantom_stream, | |||
527 | display_e2e_pipe_params_st *pipes, | |||
528 | unsigned int pipe_cnt, | |||
529 | unsigned int dc_pipe_idx) | |||
530 | { | |||
531 | unsigned int i, pipe_idx; | |||
532 | struct pipe_ctx *pipe; | |||
533 | uint32_t phantom_vactive, phantom_bp, pstate_width_fw_delay_lines; | |||
534 | unsigned int num_dpp; | |||
535 | unsigned int vlevel = context->bw_ctx.dml.vba.VoltageLevel; | |||
536 | unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; | |||
537 | unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; | |||
538 | struct vba_vars_st *vba = &context->bw_ctx.dml.vba; | |||
539 | ||||
540 | dc_assert_fp_enabled(); | |||
541 | ||||
542 | // Find DML pipe index (pipe_idx) using dc_pipe_idx | |||
543 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
544 | pipe = &context->res_ctx.pipe_ctx[i]; | |||
545 | ||||
546 | if (!pipe->stream) | |||
547 | continue; | |||
548 | ||||
549 | if (i == dc_pipe_idx) | |||
550 | break; | |||
551 | ||||
552 | pipe_idx++; | |||
553 | } | |||
554 | ||||
555 | // Calculate lines required for pstate allow width and FW processing delays | |||
556 | pstate_width_fw_delay_lines = ((double)(dc->caps.subvp_fw_processing_delay_us + | |||
557 | dc->caps.subvp_pstate_allow_width_us) / 1000000) * | |||
558 | (ref_pipe->stream->timing.pix_clk_100hz * 100) / | |||
559 | (double)ref_pipe->stream->timing.h_total; | |||
560 | ||||
561 | // Update clks_cfg for calling into recalculate | |||
562 | pipes[0].clks_cfg.voltage = vlevel; | |||
563 | pipes[0].clks_cfg.dcfclk_mhz = dcfclk; | |||
564 | pipes[0].clks_cfg.socclk_mhz = socclk; | |||
565 | ||||
566 | // DML calculation for MALL region doesn't take into account FW delay | |||
567 | // and required pstate allow width for multi-display cases | |||
568 | /* Add 16 lines margin to the MALL REGION because SUB_VP_START_LINE must be aligned | |||
569 | * to 2 swaths (i.e. 16 lines) | |||
570 | */ | |||
571 | phantom_vactive = get_subviewport_lines_needed_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx) + | |||
572 | pstate_width_fw_delay_lines + dc->caps.subvp_swath_height_margin_lines; | |||
573 | ||||
574 | // W/A for DCC corruption with certain high resolution timings. | |||
575 | // Determing if pipesplit is used. If so, add meta_row_height to the phantom vactive. | |||
576 | num_dpp = vba->NoOfDPP[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]]; | |||
577 | phantom_vactive += num_dpp > 1 ? vba->meta_row_height[vba->pipe_plane[pipe_idx]] : 0; | |||
578 | ||||
579 | // For backporch of phantom pipe, use vstartup of the main pipe | |||
580 | phantom_bp = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
581 | ||||
582 | phantom_stream->dst.y = 0; | |||
583 | phantom_stream->dst.height = phantom_vactive; | |||
584 | phantom_stream->src.y = 0; | |||
585 | phantom_stream->src.height = phantom_vactive; | |||
586 | ||||
587 | phantom_stream->timing.v_addressable = phantom_vactive; | |||
588 | phantom_stream->timing.v_front_porch = 1; | |||
589 | phantom_stream->timing.v_total = phantom_stream->timing.v_addressable + | |||
590 | phantom_stream->timing.v_front_porch + | |||
591 | phantom_stream->timing.v_sync_width + | |||
592 | phantom_bp; | |||
593 | phantom_stream->timing.flags.DSC = 0; // Don't need DSC for phantom timing | |||
594 | } | |||
595 | ||||
596 | /** | |||
597 | * dcn32_get_num_free_pipes - Calculate number of free pipes | |||
598 | * @dc: current dc state | |||
599 | * @context: new dc state | |||
600 | * | |||
601 | * This function assumes that a "used" pipe is a pipe that has | |||
602 | * both a stream and a plane assigned to it. | |||
603 | * | |||
604 | * Return: Number of free pipes available in the context | |||
605 | */ | |||
606 | static unsigned int dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context) | |||
607 | { | |||
608 | unsigned int i; | |||
609 | unsigned int free_pipes = 0; | |||
610 | unsigned int num_pipes = 0; | |||
611 | ||||
612 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
613 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
614 | ||||
615 | if (pipe->stream && !pipe->top_pipe) { | |||
616 | while (pipe) { | |||
617 | num_pipes++; | |||
618 | pipe = pipe->bottom_pipe; | |||
619 | } | |||
620 | } | |||
621 | } | |||
622 | ||||
623 | free_pipes = dc->res_pool->pipe_count - num_pipes; | |||
624 | return free_pipes; | |||
625 | } | |||
626 | ||||
627 | /** | |||
628 | * dcn32_assign_subvp_pipe - Function to decide which pipe will use Sub-VP. | |||
629 | * @dc: current dc state | |||
630 | * @context: new dc state | |||
631 | * @index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned | |||
632 | * | |||
633 | * We enter this function if we are Sub-VP capable (i.e. enough pipes available) | |||
634 | * and regular P-State switching (i.e. VACTIVE/VBLANK) is not supported, or if | |||
635 | * we are forcing SubVP P-State switching on the current config. | |||
636 | * | |||
637 | * The number of pipes used for the chosen surface must be less than or equal to the | |||
638 | * number of free pipes available. | |||
639 | * | |||
640 | * In general we choose surfaces with the longest frame time first (better for SubVP + VBLANK). | |||
641 | * For multi-display cases the ActiveDRAMClockChangeMargin doesn't provide enough info on its own | |||
642 | * for determining which should be the SubVP pipe (need a way to determine if a pipe / plane doesn't | |||
643 | * support MCLK switching naturally [i.e. ACTIVE or VBLANK]). | |||
644 | * | |||
645 | * Return: True if a valid pipe assignment was found for Sub-VP. Otherwise false. | |||
646 | */ | |||
647 | static bool_Bool dcn32_assign_subvp_pipe(struct dc *dc, | |||
648 | struct dc_state *context, | |||
649 | unsigned int *index) | |||
650 | { | |||
651 | unsigned int i, pipe_idx; | |||
652 | unsigned int max_frame_time = 0; | |||
653 | bool_Bool valid_assignment_found = false0; | |||
654 | unsigned int free_pipes = dcn32_get_num_free_pipes(dc, context); | |||
655 | bool_Bool current_assignment_freesync = false0; | |||
656 | struct vba_vars_st *vba = &context->bw_ctx.dml.vba; | |||
657 | ||||
658 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
659 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
660 | unsigned int num_pipes = 0; | |||
661 | unsigned int refresh_rate = 0; | |||
662 | ||||
663 | if (!pipe->stream) | |||
664 | continue; | |||
665 | ||||
666 | // Round up | |||
667 | refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + | |||
668 | pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) | |||
669 | / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); | |||
670 | /* SubVP pipe candidate requirements: | |||
671 | * - Refresh rate < 120hz | |||
672 | * - Not able to switch in vactive naturally (switching in active means the | |||
673 | * DET provides enough buffer to hide the P-State switch latency -- trying | |||
674 | * to combine this with SubVP can cause issues with the scheduling). | |||
675 | * - Not TMZ surface | |||
676 | */ | |||
677 | if (pipe->plane_state && !pipe->top_pipe && | |||
678 | pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface && | |||
679 | (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 || | |||
680 | (vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 && | |||
681 | dcn32_allow_subvp_with_active_margin(pipe)))) { | |||
682 | while (pipe) { | |||
683 | num_pipes++; | |||
684 | pipe = pipe->bottom_pipe; | |||
685 | } | |||
686 | ||||
687 | pipe = &context->res_ctx.pipe_ctx[i]; | |||
688 | if (num_pipes <= free_pipes) { | |||
689 | struct dc_stream_state *stream = pipe->stream; | |||
690 | unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total / | |||
691 | (double)(stream->timing.pix_clk_100hz * 100)) * 1000000; | |||
692 | if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) { | |||
693 | *index = i; | |||
694 | max_frame_time = frame_us; | |||
695 | valid_assignment_found = true1; | |||
696 | current_assignment_freesync = false0; | |||
697 | /* For the 2-Freesync display case, still choose the one with the | |||
698 | * longest frame time | |||
699 | */ | |||
700 | } else if (stream->ignore_msa_timing_param && (!valid_assignment_found || | |||
701 | (current_assignment_freesync && frame_us > max_frame_time))) { | |||
702 | *index = i; | |||
703 | valid_assignment_found = true1; | |||
704 | current_assignment_freesync = true1; | |||
705 | } | |||
706 | } | |||
707 | } | |||
708 | pipe_idx++; | |||
709 | } | |||
710 | return valid_assignment_found; | |||
711 | } | |||
712 | ||||
713 | /** | |||
714 | * dcn32_enough_pipes_for_subvp - Function to check if there are "enough" pipes for SubVP. | |||
715 | * @dc: current dc state | |||
716 | * @context: new dc state | |||
717 | * | |||
718 | * This function returns true if there are enough free pipes | |||
719 | * to create the required phantom pipes for any given stream | |||
720 | * (that does not already have phantom pipe assigned). | |||
721 | * | |||
722 | * e.g. For a 2 stream config where the first stream uses one | |||
723 | * pipe and the second stream uses 2 pipes (i.e. pipe split), | |||
724 | * this function will return true because there is 1 remaining | |||
725 | * pipe which can be used as the phantom pipe for the non pipe | |||
726 | * split pipe. | |||
727 | * | |||
728 | * Return: | |||
729 | * True if there are enough free pipes to assign phantom pipes to at least one | |||
730 | * stream that does not already have phantom pipes assigned. Otherwise false. | |||
731 | */ | |||
732 | static bool_Bool dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context) | |||
733 | { | |||
734 | unsigned int i, split_cnt, free_pipes; | |||
735 | unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 | |||
736 | bool_Bool subvp_possible = false0; | |||
737 | ||||
738 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
739 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
740 | ||||
741 | // Find the minimum pipe split count for non SubVP pipes | |||
742 | if (pipe->stream && !pipe->top_pipe && | |||
743 | pipe->stream->mall_stream_config.type == SUBVP_NONE) { | |||
744 | split_cnt = 0; | |||
745 | while (pipe) { | |||
746 | split_cnt++; | |||
747 | pipe = pipe->bottom_pipe; | |||
748 | } | |||
749 | ||||
750 | if (split_cnt < min_pipe_split) | |||
751 | min_pipe_split = split_cnt; | |||
752 | } | |||
753 | } | |||
754 | ||||
755 | free_pipes = dcn32_get_num_free_pipes(dc, context); | |||
756 | ||||
757 | // SubVP only possible if at least one pipe is being used (i.e. free_pipes | |||
758 | // should not equal to the pipe_count) | |||
759 | if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) | |||
760 | subvp_possible = true1; | |||
761 | ||||
762 | return subvp_possible; | |||
763 | } | |||
764 | ||||
765 | /** | |||
766 | * subvp_subvp_schedulable - Determine if SubVP + SubVP config is schedulable | |||
767 | * @dc: current dc state | |||
768 | * @context: new dc state | |||
769 | * | |||
770 | * High level algorithm: | |||
771 | * 1. Find longest microschedule length (in us) between the two SubVP pipes | |||
772 | * 2. Check if the worst case overlap (VBLANK in middle of ACTIVE) for both | |||
773 | * pipes still allows for the maximum microschedule to fit in the active | |||
774 | * region for both pipes. | |||
775 | * | |||
776 | * Return: True if the SubVP + SubVP config is schedulable, false otherwise | |||
777 | */ | |||
778 | static bool_Bool subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) | |||
779 | { | |||
780 | struct pipe_ctx *subvp_pipes[2]; | |||
781 | struct dc_stream_state *phantom = NULL((void *)0); | |||
782 | uint32_t microschedule_lines = 0; | |||
783 | uint32_t index = 0; | |||
784 | uint32_t i; | |||
785 | uint32_t max_microschedule_us = 0; | |||
786 | int32_t vactive1_us, vactive2_us, vblank1_us, vblank2_us; | |||
787 | ||||
788 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
| ||||
789 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
790 | uint32_t time_us = 0; | |||
791 | ||||
792 | /* Loop to calculate the maximum microschedule time between the two SubVP pipes, | |||
793 | * and also to store the two main SubVP pipe pointers in subvp_pipes[2]. | |||
794 | */ | |||
795 | if (pipe->stream && pipe->plane_state && !pipe->top_pipe && | |||
796 | pipe->stream->mall_stream_config.type == SUBVP_MAIN) { | |||
797 | phantom = pipe->stream->mall_stream_config.paired_stream; | |||
798 | microschedule_lines = (phantom->timing.v_total - phantom->timing.v_front_porch) + | |||
799 | phantom->timing.v_addressable; | |||
800 | ||||
801 | // Round up when calculating microschedule time (+ 1 at the end) | |||
802 | time_us = (microschedule_lines * phantom->timing.h_total) / | |||
803 | (double)(phantom->timing.pix_clk_100hz * 100) * 1000000 + | |||
804 | dc->caps.subvp_prefetch_end_to_mall_start_us + | |||
805 | dc->caps.subvp_fw_processing_delay_us + 1; | |||
806 | if (time_us > max_microschedule_us) | |||
807 | max_microschedule_us = time_us; | |||
808 | ||||
809 | subvp_pipes[index] = pipe; | |||
810 | index++; | |||
811 | ||||
812 | // Maximum 2 SubVP pipes | |||
813 | if (index
| |||
814 | break; | |||
815 | } | |||
816 | } | |||
817 | vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / | |||
818 | (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; | |||
819 | vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / | |||
| ||||
820 | (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; | |||
821 | vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) * | |||
822 | subvp_pipes[0]->stream->timing.h_total) / | |||
823 | (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; | |||
824 | vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) * | |||
825 | subvp_pipes[1]->stream->timing.h_total) / | |||
826 | (double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000; | |||
827 | ||||
828 | if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us && | |||
829 | (vactive2_us - vblank1_us) / 2 > max_microschedule_us) | |||
830 | return true1; | |||
831 | ||||
832 | return false0; | |||
833 | } | |||
834 | ||||
835 | /** | |||
836 | * subvp_drr_schedulable - Determine if SubVP + DRR config is schedulable | |||
837 | * @dc: current dc state | |||
838 | * @context: new dc state | |||
839 | * @drr_pipe: DRR pipe_ctx for the SubVP + DRR config | |||
840 | * | |||
841 | * High level algorithm: | |||
842 | * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe | |||
843 | * 2. Determine the frame time for the DRR display when adding required margin for MCLK switching | |||
844 | * (the margin is equal to the MALL region + DRR margin (500us)) | |||
845 | * 3.If (SubVP Active - Prefetch > Stretched DRR frame + max(MALL region, Stretched DRR frame)) | |||
846 | * then report the configuration as supported | |||
847 | * | |||
848 | * Return: True if the SubVP + DRR config is schedulable, false otherwise | |||
849 | */ | |||
850 | static bool_Bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struct pipe_ctx *drr_pipe) | |||
851 | { | |||
852 | bool_Bool schedulable = false0; | |||
853 | uint32_t i; | |||
854 | struct pipe_ctx *pipe = NULL((void *)0); | |||
855 | struct dc_crtc_timing *main_timing = NULL((void *)0); | |||
856 | struct dc_crtc_timing *phantom_timing = NULL((void *)0); | |||
857 | struct dc_crtc_timing *drr_timing = NULL((void *)0); | |||
858 | int16_t prefetch_us = 0; | |||
859 | int16_t mall_region_us = 0; | |||
860 | int16_t drr_frame_us = 0; // nominal frame time | |||
861 | int16_t subvp_active_us = 0; | |||
862 | int16_t stretched_drr_us = 0; | |||
863 | int16_t drr_stretched_vblank_us = 0; | |||
864 | int16_t max_vblank_mallregion = 0; | |||
865 | ||||
866 | // Find SubVP pipe | |||
867 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
868 | pipe = &context->res_ctx.pipe_ctx[i]; | |||
869 | ||||
870 | // We check for master pipe, but it shouldn't matter since we only need | |||
871 | // the pipe for timing info (stream should be same for any pipe splits) | |||
872 | if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) | |||
873 | continue; | |||
874 | ||||
875 | // Find the SubVP pipe | |||
876 | if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) | |||
877 | break; | |||
878 | } | |||
879 | ||||
880 | main_timing = &pipe->stream->timing; | |||
881 | phantom_timing = &pipe->stream->mall_stream_config.paired_stream->timing; | |||
882 | drr_timing = &drr_pipe->stream->timing; | |||
883 | prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / | |||
884 | (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + | |||
885 | dc->caps.subvp_prefetch_end_to_mall_start_us; | |||
886 | subvp_active_us = main_timing->v_addressable * main_timing->h_total / | |||
887 | (double)(main_timing->pix_clk_100hz * 100) * 1000000; | |||
888 | drr_frame_us = drr_timing->v_total * drr_timing->h_total / | |||
889 | (double)(drr_timing->pix_clk_100hz * 100) * 1000000; | |||
890 | // P-State allow width and FW delays already included phantom_timing->v_addressable | |||
891 | mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / | |||
892 | (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; | |||
893 | stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US500; | |||
894 | drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / | |||
895 | (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); | |||
896 | max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us; | |||
897 | ||||
898 | /* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the | |||
899 | * highest refresh rate + margin that can support UCLK P-State switch) passes the static analysis | |||
900 | * for VBLANK: (VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, | |||
901 | * and the max of (VBLANK blanking time, MALL region)). | |||
902 | */ | |||
903 | if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 && | |||
904 | subvp_active_us - prefetch_us - stretched_drr_us - max_vblank_mallregion > 0) | |||
905 | schedulable = true1; | |||
906 | ||||
907 | return schedulable; | |||
908 | } | |||
909 | ||||
910 | ||||
911 | /** | |||
912 | * subvp_vblank_schedulable - Determine if SubVP + VBLANK config is schedulable | |||
913 | * @dc: current dc state | |||
914 | * @context: new dc state | |||
915 | * | |||
916 | * High level algorithm: | |||
917 | * 1. Get timing for SubVP pipe, phantom pipe, and VBLANK pipe | |||
918 | * 2. If (SubVP Active - Prefetch > Vblank Frame Time + max(MALL region, Vblank blanking time)) | |||
919 | * then report the configuration as supported | |||
920 | * 3. If the VBLANK display is DRR, then take the DRR static schedulability path | |||
921 | * | |||
922 | * Return: True if the SubVP + VBLANK/DRR config is schedulable, false otherwise | |||
923 | */ | |||
924 | static bool_Bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) | |||
925 | { | |||
926 | struct pipe_ctx *pipe = NULL((void *)0); | |||
927 | struct pipe_ctx *subvp_pipe = NULL((void *)0); | |||
928 | bool_Bool found = false0; | |||
929 | bool_Bool schedulable = false0; | |||
930 | uint32_t i = 0; | |||
931 | uint8_t vblank_index = 0; | |||
932 | uint16_t prefetch_us = 0; | |||
933 | uint16_t mall_region_us = 0; | |||
934 | uint16_t vblank_frame_us = 0; | |||
935 | uint16_t subvp_active_us = 0; | |||
936 | uint16_t vblank_blank_us = 0; | |||
937 | uint16_t max_vblank_mallregion = 0; | |||
938 | struct dc_crtc_timing *main_timing = NULL((void *)0); | |||
939 | struct dc_crtc_timing *phantom_timing = NULL((void *)0); | |||
940 | struct dc_crtc_timing *vblank_timing = NULL((void *)0); | |||
941 | ||||
942 | /* For SubVP + VBLANK/DRR cases, we assume there can only be | |||
943 | * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK | |||
944 | * is supported, it is either a single VBLANK case or two VBLANK | |||
945 | * displays which are synchronized (in which case they have identical | |||
946 | * timings). | |||
947 | */ | |||
948 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
949 | pipe = &context->res_ctx.pipe_ctx[i]; | |||
950 | ||||
951 | // We check for master pipe, but it shouldn't matter since we only need | |||
952 | // the pipe for timing info (stream should be same for any pipe splits) | |||
953 | if (!pipe->stream || !pipe->plane_state || pipe->top_pipe || pipe->prev_odm_pipe) | |||
954 | continue; | |||
955 | ||||
956 | if (!found && pipe->stream->mall_stream_config.type == SUBVP_NONE) { | |||
957 | // Found pipe which is not SubVP or Phantom (i.e. the VBLANK pipe). | |||
958 | vblank_index = i; | |||
959 | found = true1; | |||
960 | } | |||
961 | ||||
962 | if (!subvp_pipe && pipe->stream->mall_stream_config.type == SUBVP_MAIN) | |||
963 | subvp_pipe = pipe; | |||
964 | } | |||
965 | // Use ignore_msa_timing_param flag to identify as DRR | |||
966 | if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) { | |||
967 | // SUBVP + DRR case | |||
968 | schedulable = subvp_drr_schedulable(dc, context, &context->res_ctx.pipe_ctx[vblank_index]); | |||
969 | } else if (found) { | |||
970 | main_timing = &subvp_pipe->stream->timing; | |||
971 | phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; | |||
972 | vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing; | |||
973 | // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe | |||
974 | // Also include the prefetch end to mallstart delay time | |||
975 | prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total / | |||
976 | (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 + | |||
977 | dc->caps.subvp_prefetch_end_to_mall_start_us; | |||
978 | // P-State allow width and FW delays already included phantom_timing->v_addressable | |||
979 | mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total / | |||
980 | (double)(phantom_timing->pix_clk_100hz * 100) * 1000000; | |||
981 | vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total / | |||
982 | (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; | |||
983 | vblank_blank_us = (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total / | |||
984 | (double)(vblank_timing->pix_clk_100hz * 100) * 1000000; | |||
985 | subvp_active_us = main_timing->v_addressable * main_timing->h_total / | |||
986 | (double)(main_timing->pix_clk_100hz * 100) * 1000000; | |||
987 | max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us; | |||
988 | ||||
989 | // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time, | |||
990 | // and the max of (VBLANK blanking time, MALL region) | |||
991 | // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0) | |||
992 | if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0) | |||
993 | schedulable = true1; | |||
994 | } | |||
995 | return schedulable; | |||
996 | } | |||
997 | ||||
998 | /** | |||
999 | * subvp_validate_static_schedulability - Check which SubVP case is calculated | |||
1000 | * and handle static analysis based on the case. | |||
1001 | * @dc: current dc state | |||
1002 | * @context: new dc state | |||
1003 | * @vlevel: Voltage level calculated by DML | |||
1004 | * | |||
1005 | * Three cases: | |||
1006 | * 1. SubVP + SubVP | |||
1007 | * 2. SubVP + VBLANK (DRR checked internally) | |||
1008 | * 3. SubVP + VACTIVE (currently unsupported) | |||
1009 | * | |||
1010 | * Return: True if statically schedulable, false otherwise | |||
1011 | */ | |||
1012 | static bool_Bool subvp_validate_static_schedulability(struct dc *dc, | |||
1013 | struct dc_state *context, | |||
1014 | int vlevel) | |||
1015 | { | |||
1016 | bool_Bool schedulable = true1; // true by default for single display case | |||
1017 | struct vba_vars_st *vba = &context->bw_ctx.dml.vba; | |||
1018 | uint32_t i, pipe_idx; | |||
1019 | uint8_t subvp_count = 0; | |||
1020 | uint8_t vactive_count = 0; | |||
1021 | ||||
1022 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
1023 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
1024 | ||||
1025 | if (!pipe->stream) | |||
1026 | continue; | |||
1027 | ||||
1028 | if (pipe->plane_state && !pipe->top_pipe && | |||
1029 | pipe->stream->mall_stream_config.type == SUBVP_MAIN) | |||
1030 | subvp_count++; | |||
1031 | ||||
1032 | // Count how many planes that aren't SubVP/phantom are capable of VACTIVE | |||
1033 | // switching (SubVP + VACTIVE unsupported). In situations where we force | |||
1034 | // SubVP for a VACTIVE plane, we don't want to increment the vactive_count. | |||
1035 | if (vba->ActiveDRAMClockChangeLatencyMargin[vba->pipe_plane[pipe_idx]] > 0 && | |||
1036 | pipe->stream->mall_stream_config.type == SUBVP_NONE) { | |||
1037 | vactive_count++; | |||
1038 | } | |||
1039 | pipe_idx++; | |||
1040 | } | |||
1041 | ||||
1042 | if (subvp_count == 2) { | |||
1043 | // Static schedulability check for SubVP + SubVP case | |||
1044 | schedulable = subvp_subvp_schedulable(dc, context); | |||
1045 | } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vblank_w_mall_sub_vp) { | |||
1046 | // Static schedulability check for SubVP + VBLANK case. Also handle the case where | |||
1047 | // DML outputs SubVP + VBLANK + VACTIVE (DML will report as SubVP + VBLANK) | |||
1048 | if (vactive_count > 0) | |||
1049 | schedulable = false0; | |||
1050 | else | |||
1051 | schedulable = subvp_vblank_schedulable(dc, context); | |||
1052 | } else if (vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_vactive_w_mall_sub_vp && | |||
1053 | vactive_count > 0) { | |||
1054 | // For single display SubVP cases, DML will output dm_dram_clock_change_vactive_w_mall_sub_vp by default. | |||
1055 | // We tell the difference between SubVP vs. SubVP + VACTIVE by checking the vactive_count. | |||
1056 | // SubVP + VACTIVE currently unsupported | |||
1057 | schedulable = false0; | |||
1058 | } | |||
1059 | return schedulable; | |||
1060 | } | |||
1061 | ||||
1062 | static void dcn32_full_validate_bw_helper(struct dc *dc, | |||
1063 | struct dc_state *context, | |||
1064 | display_e2e_pipe_params_st *pipes, | |||
1065 | int *vlevel, | |||
1066 | int *split, | |||
1067 | bool_Bool *merge, | |||
1068 | int *pipe_cnt) | |||
1069 | { | |||
1070 | struct vba_vars_st *vba = &context->bw_ctx.dml.vba; | |||
1071 | unsigned int dc_pipe_idx = 0; | |||
1072 | bool_Bool found_supported_config = false0; | |||
1073 | struct pipe_ctx *pipe = NULL((void *)0); | |||
1074 | uint32_t non_subvp_pipes = 0; | |||
1075 | bool_Bool drr_pipe_found = false0; | |||
1076 | uint32_t drr_pipe_index = 0; | |||
1077 | uint32_t i = 0; | |||
1078 | ||||
1079 | dc_assert_fp_enabled(); | |||
1080 | ||||
1081 | /* | |||
1082 | * DML favors voltage over p-state, but we're more interested in | |||
1083 | * supporting p-state over voltage. We can't support p-state in | |||
1084 | * prefetch mode > 0 so try capping the prefetch mode to start. | |||
1085 | * Override present for testing. | |||
1086 | */ | |||
1087 | if (dc->debug.dml_disallow_alternate_prefetch_modes) | |||
1088 | context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = | |||
1089 | dm_prefetch_support_uclk_fclk_and_stutter; | |||
1090 | else | |||
1091 | context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = | |||
1092 | dm_prefetch_support_uclk_fclk_and_stutter_if_possible; | |||
1093 | ||||
1094 | *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); | |||
1095 | /* This may adjust vlevel and maxMpcComb */ | |||
1096 | if (*vlevel < context->bw_ctx.dml.soc.num_states) { | |||
1097 | *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); | |||
1098 | vba->VoltageLevel = *vlevel; | |||
1099 | } | |||
1100 | ||||
1101 | /* Conditions for setting up phantom pipes for SubVP: | |||
1102 | * 1. Not force disable SubVP | |||
1103 | * 2. Full update (i.e. !fast_validate) | |||
1104 | * 3. Enough pipes are available to support SubVP (TODO: Which pipes will use VACTIVE / VBLANK / SUBVP?) | |||
1105 | * 4. Display configuration passes validation | |||
1106 | * 5. (Config doesn't support MCLK in VACTIVE/VBLANK || dc->debug.force_subvp_mclk_switch) | |||
1107 | */ | |||
1108 | if (!dc->debug.force_disable_subvp && dcn32_all_pipes_have_stream_and_plane(dc, context) && | |||
1109 | !dcn32_mpo_in_use(context) && !dcn32_any_surfaces_rotated(dc, context) && | |||
1110 | (*vlevel == context->bw_ctx.dml.soc.num_states || | |||
1111 | vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported || | |||
1112 | dc->debug.force_subvp_mclk_switch)) { | |||
1113 | ||||
1114 | dcn32_merge_pipes_for_subvp(dc, context); | |||
1115 | memset(merge, 0, MAX_PIPES * sizeof(bool))__builtin_memset((merge), (0), (6 * sizeof(_Bool))); | |||
1116 | ||||
1117 | /* to re-initialize viewport after the pipe merge */ | |||
1118 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
1119 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; | |||
1120 | ||||
1121 | if (!pipe_ctx->plane_state || !pipe_ctx->stream) | |||
1122 | continue; | |||
1123 | ||||
1124 | resource_build_scaling_params(pipe_ctx); | |||
1125 | } | |||
1126 | ||||
1127 | while (!found_supported_config && dcn32_enough_pipes_for_subvp(dc, context) && | |||
1128 | dcn32_assign_subvp_pipe(dc, context, &dc_pipe_idx)) { | |||
1129 | /* For the case where *vlevel = num_states, bandwidth validation has failed for this config. | |||
1130 | * Adding phantom pipes won't change the validation result, so change the DML input param | |||
1131 | * for P-State support before adding phantom pipes and recalculating the DML result. | |||
1132 | * However, this case is only applicable for SubVP + DRR cases because the prefetch mode | |||
1133 | * will not allow for switch in VBLANK. The DRR display must have it's VBLANK stretched | |||
1134 | * enough to support MCLK switching. | |||
1135 | */ | |||
1136 | if (*vlevel == context->bw_ctx.dml.soc.num_states && | |||
1137 | context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final == | |||
1138 | dm_prefetch_support_uclk_fclk_and_stutter) { | |||
1139 | context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = | |||
1140 | dm_prefetch_support_stutter; | |||
1141 | /* There are params (such as FabricClock) that need to be recalculated | |||
1142 | * after validation fails (otherwise it will be 0). Calculation for | |||
1143 | * phantom vactive requires call into DML, so we must ensure all the | |||
1144 | * vba params are valid otherwise we'll get incorrect phantom vactive. | |||
1145 | */ | |||
1146 | *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); | |||
1147 | } | |||
1148 | ||||
1149 | dc->res_pool->funcs->add_phantom_pipes(dc, context, pipes, *pipe_cnt, dc_pipe_idx); | |||
1150 | ||||
1151 | *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false0); | |||
1152 | // Populate dppclk to trigger a recalculate in dml_get_voltage_level | |||
1153 | // so the phantom pipe DLG params can be assigned correctly. | |||
1154 | pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0); | |||
1155 | *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); | |||
1156 | ||||
1157 | if (*vlevel < context->bw_ctx.dml.soc.num_states && | |||
1158 | vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] != dm_dram_clock_change_unsupported | |||
1159 | && subvp_validate_static_schedulability(dc, context, *vlevel)) { | |||
1160 | found_supported_config = true1; | |||
1161 | } else if (*vlevel < context->bw_ctx.dml.soc.num_states && | |||
1162 | vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { | |||
1163 | /* Case where 1 SubVP is added, and DML reports MCLK unsupported. This handles | |||
1164 | * the case for SubVP + DRR, where the DRR display does not support MCLK switch | |||
1165 | * at it's native refresh rate / timing. | |||
1166 | */ | |||
1167 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
1168 | pipe = &context->res_ctx.pipe_ctx[i]; | |||
1169 | if (pipe->stream && pipe->plane_state && !pipe->top_pipe && | |||
1170 | pipe->stream->mall_stream_config.type == SUBVP_NONE) { | |||
1171 | non_subvp_pipes++; | |||
1172 | // Use ignore_msa_timing_param flag to identify as DRR | |||
1173 | if (pipe->stream->ignore_msa_timing_param) { | |||
1174 | drr_pipe_found = true1; | |||
1175 | drr_pipe_index = i; | |||
1176 | } | |||
1177 | } | |||
1178 | } | |||
1179 | // If there is only 1 remaining non SubVP pipe that is DRR, check static | |||
1180 | // schedulability for SubVP + DRR. | |||
1181 | if (non_subvp_pipes == 1 && drr_pipe_found) { | |||
1182 | found_supported_config = subvp_drr_schedulable(dc, context, | |||
1183 | &context->res_ctx.pipe_ctx[drr_pipe_index]); | |||
1184 | } | |||
1185 | } | |||
1186 | } | |||
1187 | ||||
1188 | // If SubVP pipe config is unsupported (or cannot be used for UCLK switching) | |||
1189 | // remove phantom pipes and repopulate dml pipes | |||
1190 | if (!found_supported_config) { | |||
1191 | dc->res_pool->funcs->remove_phantom_pipes(dc, context); | |||
1192 | vba->DRAMClockChangeSupport[*vlevel][vba->maxMpcComb] = dm_dram_clock_change_unsupported; | |||
1193 | *pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, false0); | |||
1194 | ||||
1195 | *vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, *pipe_cnt); | |||
1196 | /* This may adjust vlevel and maxMpcComb */ | |||
1197 | if (*vlevel < context->bw_ctx.dml.soc.num_states) { | |||
1198 | *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); | |||
1199 | vba->VoltageLevel = *vlevel; | |||
1200 | } | |||
1201 | } else { | |||
1202 | // Most populate phantom DLG params before programming hardware / timing for phantom pipe | |||
1203 | dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt); | |||
1204 | ||||
1205 | /* Call validate_apply_pipe_split flags after calling DML getters for | |||
1206 | * phantom dlg params, or some of the VBA params indicating pipe split | |||
1207 | * can be overwritten by the getters. | |||
1208 | * | |||
1209 | * When setting up SubVP config, all pipes are merged before attempting to | |||
1210 | * add phantom pipes. If pipe split (ODM / MPC) is required, both the main | |||
1211 | * and phantom pipes will be split in the regular pipe splitting sequence. | |||
1212 | */ | |||
1213 | memset(split, 0, MAX_PIPES * sizeof(int))__builtin_memset((split), (0), (6 * sizeof(int))); | |||
1214 | memset(merge, 0, MAX_PIPES * sizeof(bool))__builtin_memset((merge), (0), (6 * sizeof(_Bool))); | |||
1215 | *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); | |||
1216 | vba->VoltageLevel = *vlevel; | |||
1217 | // Note: We can't apply the phantom pipes to hardware at this time. We have to wait | |||
1218 | // until driver has acquired the DMCUB lock to do it safely. | |||
1219 | } | |||
1220 | } | |||
1221 | } | |||
1222 | ||||
1223 | static bool_Bool is_dtbclk_required(struct dc *dc, struct dc_state *context) | |||
1224 | { | |||
1225 | int i; | |||
1226 | ||||
1227 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
1228 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
1229 | continue; | |||
1230 | if (is_dp_128b_132b_signal(&context->res_ctx.pipe_ctx[i])) | |||
1231 | return true1; | |||
1232 | } | |||
1233 | return false0; | |||
1234 | } | |||
1235 | ||||
1236 | static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, | |||
1237 | display_e2e_pipe_params_st *pipes, | |||
1238 | int pipe_cnt, int vlevel) | |||
1239 | { | |||
1240 | int i, pipe_idx, active_hubp_count = 0; | |||
1241 | bool_Bool usr_retraining_support = false0; | |||
1242 | bool_Bool unbounded_req_enabled = false0; | |||
1243 | ||||
1244 | dc_assert_fp_enabled(); | |||
1245 | ||||
1246 | /* Writeback MCIF_WB arbitration parameters */ | |||
1247 | dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); | |||
1248 | ||||
1249 | context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; | |||
1250 | context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; | |||
1251 | context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; | |||
1252 | context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; | |||
1253 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; | |||
1254 | context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; | |||
1255 | context->bw_ctx.bw.dcn.clk.p_state_change_support = | |||
1256 | context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] | |||
1257 | != dm_dram_clock_change_unsupported; | |||
1258 | context->bw_ctx.bw.dcn.clk.num_ways = dcn32_helper_calculate_num_ways_for_subvp(dc, context); | |||
1259 | ||||
1260 | context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; | |||
1261 | context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); | |||
1262 | context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = context->bw_ctx.dml.vba.DTBCLKPerState[vlevel] * 1000; | |||
1263 | if (context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_fclock_change_unsupported) | |||
1264 | context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false0; | |||
1265 | else | |||
1266 | context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true1; | |||
1267 | ||||
1268 | usr_retraining_support = context->bw_ctx.dml.vba.USRRetrainingSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; | |||
1269 | ASSERT(usr_retraining_support)do { if (({ static int __warned; int __ret = !!(!(usr_retraining_support )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(usr_retraining_support)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1269); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1270 | ||||
1271 | if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) | |||
1272 | context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; | |||
1273 | ||||
1274 | unbounded_req_enabled = get_unbounded_request_enabled(&context->bw_ctx.dml, pipes, pipe_cnt); | |||
1275 | ||||
1276 | if (unbounded_req_enabled && pipe_cnt > 1) { | |||
1277 | // Unbounded requesting should not ever be used when more than 1 pipe is enabled. | |||
1278 | ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1278); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1279 | unbounded_req_enabled = false0; | |||
1280 | } | |||
1281 | ||||
1282 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
1283 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
1284 | continue; | |||
1285 | if (context->res_ctx.pipe_ctx[i].plane_state) | |||
1286 | active_hubp_count++; | |||
1287 | pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, | |||
1288 | pipe_idx); | |||
1289 | pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, | |||
1290 | pipe_idx); | |||
1291 | pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, | |||
1292 | pipe_idx); | |||
1293 | pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, | |||
1294 | pipe_idx); | |||
1295 | ||||
1296 | if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type == SUBVP_PHANTOM) { | |||
1297 | // Phantom pipe requires that DET_SIZE = 0 and no unbounded requests | |||
1298 | context->res_ctx.pipe_ctx[i].det_buffer_size_kb = 0; | |||
1299 | context->res_ctx.pipe_ctx[i].unbounded_req = false0; | |||
1300 | } else { | |||
1301 | context->res_ctx.pipe_ctx[i].det_buffer_size_kb = get_det_buffer_size_kbytes(&context->bw_ctx.dml, pipes, pipe_cnt, | |||
1302 | pipe_idx); | |||
1303 | context->res_ctx.pipe_ctx[i].unbounded_req = unbounded_req_enabled; | |||
1304 | } | |||
1305 | ||||
1306 | if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) | |||
1307 | context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; | |||
1308 | if (context->res_ctx.pipe_ctx[i].plane_state) | |||
1309 | context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; | |||
1310 | else | |||
1311 | context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; | |||
1312 | context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; | |||
1313 | pipe_idx++; | |||
1314 | } | |||
1315 | /* If DCN isn't making memory requests we can allow pstate change and lower clocks */ | |||
1316 | if (!active_hubp_count) { | |||
1317 | context->bw_ctx.bw.dcn.clk.socclk_khz = 0; | |||
1318 | context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; | |||
1319 | context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; | |||
1320 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; | |||
1321 | context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; | |||
1322 | context->bw_ctx.bw.dcn.clk.fclk_khz = 0; | |||
1323 | context->bw_ctx.bw.dcn.clk.p_state_change_support = true1; | |||
1324 | } | |||
1325 | /*save a original dppclock copy*/ | |||
1326 | context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; | |||
1327 | context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; | |||
1328 | context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz | |||
1329 | * 1000; | |||
1330 | context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz | |||
1331 | * 1000; | |||
1332 | ||||
1333 | context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes; | |||
1334 | ||||
1335 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
1336 | if (context->res_ctx.pipe_ctx[i].stream) | |||
1337 | context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[i].det_buffer_size_kb; | |||
1338 | } | |||
1339 | ||||
1340 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
1341 | ||||
1342 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
1343 | continue; | |||
1344 | ||||
1345 | context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg_v2(&context->bw_ctx.dml, | |||
1346 | &context->res_ctx.pipe_ctx[i].dlg_regs, &context->res_ctx.pipe_ctx[i].ttu_regs, pipes, | |||
1347 | pipe_cnt, pipe_idx); | |||
1348 | ||||
1349 | context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg_v2(&context->res_ctx.pipe_ctx[i].rq_regs, | |||
1350 | &context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
1351 | pipe_idx++; | |||
1352 | } | |||
1353 | } | |||
1354 | ||||
1355 | static struct pipe_ctx *dcn32_find_split_pipe( | |||
1356 | struct dc *dc, | |||
1357 | struct dc_state *context, | |||
1358 | int old_index) | |||
1359 | { | |||
1360 | struct pipe_ctx *pipe = NULL((void *)0); | |||
1361 | int i; | |||
1362 | ||||
1363 | if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL((void *)0)) { | |||
1364 | pipe = &context->res_ctx.pipe_ctx[old_index]; | |||
1365 | pipe->pipe_idx = old_index; | |||
1366 | } | |||
1367 | ||||
1368 | if (!pipe) | |||
1369 | for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { | |||
1370 | if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL((void *)0) | |||
1371 | && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL((void *)0)) { | |||
1372 | if (context->res_ctx.pipe_ctx[i].stream == NULL((void *)0)) { | |||
1373 | pipe = &context->res_ctx.pipe_ctx[i]; | |||
1374 | pipe->pipe_idx = i; | |||
1375 | break; | |||
1376 | } | |||
1377 | } | |||
1378 | } | |||
1379 | ||||
1380 | /* | |||
1381 | * May need to fix pipes getting tossed from 1 opp to another on flip | |||
1382 | * Add for debugging transient underflow during topology updates: | |||
1383 | * ASSERT(pipe); | |||
1384 | */ | |||
1385 | if (!pipe) | |||
1386 | for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { | |||
1387 | if (context->res_ctx.pipe_ctx[i].stream == NULL((void *)0)) { | |||
1388 | pipe = &context->res_ctx.pipe_ctx[i]; | |||
1389 | pipe->pipe_idx = i; | |||
1390 | break; | |||
1391 | } | |||
1392 | } | |||
1393 | ||||
1394 | return pipe; | |||
1395 | } | |||
1396 | ||||
1397 | static bool_Bool dcn32_split_stream_for_mpc_or_odm( | |||
1398 | const struct dc *dc, | |||
1399 | struct resource_context *res_ctx, | |||
1400 | struct pipe_ctx *pri_pipe, | |||
1401 | struct pipe_ctx *sec_pipe, | |||
1402 | bool_Bool odm) | |||
1403 | { | |||
1404 | int pipe_idx = sec_pipe->pipe_idx; | |||
1405 | const struct resource_pool *pool = dc->res_pool; | |||
1406 | ||||
1407 | DC_LOGGER_INIT(dc->ctx->logger); | |||
1408 | ||||
1409 | if (odm && pri_pipe->plane_state) { | |||
1410 | /* ODM + window MPO, where MPO window is on left half only */ | |||
1411 | if (pri_pipe->plane_state->clip_rect.x + pri_pipe->plane_state->clip_rect.width <= | |||
1412 | pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { | |||
1413 | ||||
1414 | DC_LOG_SCALER("%s - ODM + window MPO(left). pri_pipe:%d\n",do { } while(0) | |||
1415 | __func__,do { } while(0) | |||
1416 | pri_pipe->pipe_idx)do { } while(0); | |||
1417 | return true1; | |||
1418 | } | |||
1419 | ||||
1420 | /* ODM + window MPO, where MPO window is on right half only */ | |||
1421 | if (pri_pipe->plane_state->clip_rect.x >= pri_pipe->stream->src.x + pri_pipe->stream->src.width/2) { | |||
1422 | ||||
1423 | DC_LOG_SCALER("%s - ODM + window MPO(right). pri_pipe:%d\n",do { } while(0) | |||
1424 | __func__,do { } while(0) | |||
1425 | pri_pipe->pipe_idx)do { } while(0); | |||
1426 | return true1; | |||
1427 | } | |||
1428 | } | |||
1429 | ||||
1430 | *sec_pipe = *pri_pipe; | |||
1431 | ||||
1432 | sec_pipe->pipe_idx = pipe_idx; | |||
1433 | sec_pipe->plane_res.mi = pool->mis[pipe_idx]; | |||
1434 | sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; | |||
1435 | sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; | |||
1436 | sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; | |||
1437 | sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; | |||
1438 | sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; | |||
1439 | sec_pipe->stream_res.dsc = NULL((void *)0); | |||
1440 | if (odm) { | |||
1441 | if (pri_pipe->next_odm_pipe) { | |||
1442 | ASSERT(pri_pipe->next_odm_pipe != sec_pipe)do { if (({ static int __warned; int __ret = !!(!(pri_pipe-> next_odm_pipe != sec_pipe)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(pri_pipe->next_odm_pipe != sec_pipe)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1442); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1443 | sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; | |||
1444 | sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; | |||
1445 | } | |||
1446 | if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { | |||
1447 | pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; | |||
1448 | sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; | |||
1449 | } | |||
1450 | if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { | |||
1451 | pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; | |||
1452 | sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; | |||
1453 | } | |||
1454 | pri_pipe->next_odm_pipe = sec_pipe; | |||
1455 | sec_pipe->prev_odm_pipe = pri_pipe; | |||
1456 | ASSERT(sec_pipe->top_pipe == NULL)do { if (({ static int __warned; int __ret = !!(!(sec_pipe-> top_pipe == ((void *)0))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(sec_pipe->top_pipe == ((void *)0))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1456); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1457 | ||||
1458 | if (!sec_pipe->top_pipe) | |||
1459 | sec_pipe->stream_res.opp = pool->opps[pipe_idx]; | |||
1460 | else | |||
1461 | sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; | |||
1462 | if (sec_pipe->stream->timing.flags.DSC == 1) { | |||
1463 | dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); | |||
1464 | ASSERT(sec_pipe->stream_res.dsc)do { if (({ static int __warned; int __ret = !!(!(sec_pipe-> stream_res.dsc)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(sec_pipe->stream_res.dsc)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1464); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1465 | if (sec_pipe->stream_res.dsc == NULL((void *)0)) | |||
1466 | return false0; | |||
1467 | } | |||
1468 | } else { | |||
1469 | if (pri_pipe->bottom_pipe) { | |||
1470 | ASSERT(pri_pipe->bottom_pipe != sec_pipe)do { if (({ static int __warned; int __ret = !!(!(pri_pipe-> bottom_pipe != sec_pipe)); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(pri_pipe->bottom_pipe != sec_pipe)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1470); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1471 | sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; | |||
1472 | sec_pipe->bottom_pipe->top_pipe = sec_pipe; | |||
1473 | } | |||
1474 | pri_pipe->bottom_pipe = sec_pipe; | |||
1475 | sec_pipe->top_pipe = pri_pipe; | |||
1476 | ||||
1477 | ASSERT(pri_pipe->plane_state)do { if (({ static int __warned; int __ret = !!(!(pri_pipe-> plane_state)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pri_pipe->plane_state)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1477); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1478 | } | |||
1479 | ||||
1480 | return true1; | |||
1481 | } | |||
1482 | ||||
1483 | bool_Bool dcn32_internal_validate_bw(struct dc *dc, | |||
1484 | struct dc_state *context, | |||
1485 | display_e2e_pipe_params_st *pipes, | |||
1486 | int *pipe_cnt_out, | |||
1487 | int *vlevel_out, | |||
1488 | bool_Bool fast_validate) | |||
1489 | { | |||
1490 | bool_Bool out = false0; | |||
1491 | bool_Bool repopulate_pipes = false0; | |||
1492 | int split[MAX_PIPES6] = { 0 }; | |||
1493 | bool_Bool merge[MAX_PIPES6] = { false0 }; | |||
1494 | bool_Bool newly_split[MAX_PIPES6] = { false0 }; | |||
1495 | int pipe_cnt, i, pipe_idx; | |||
1496 | int vlevel = context->bw_ctx.dml.soc.num_states; | |||
1497 | struct vba_vars_st *vba = &context->bw_ctx.dml.vba; | |||
1498 | ||||
1499 | dc_assert_fp_enabled(); | |||
1500 | ||||
1501 | ASSERT(pipes)do { if (({ static int __warned; int __ret = !!(!(pipes)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipes)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1501); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1502 | if (!pipes) | |||
1503 | return false0; | |||
1504 | ||||
1505 | // For each full update, remove all existing phantom pipes first | |||
1506 | dc->res_pool->funcs->remove_phantom_pipes(dc, context); | |||
1507 | ||||
1508 | dc->res_pool->funcs->update_soc_for_wm_a(dc, context); | |||
1509 | ||||
1510 | pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); | |||
1511 | ||||
1512 | if (!pipe_cnt) { | |||
1513 | out = true1; | |||
1514 | goto validate_out; | |||
1515 | } | |||
1516 | ||||
1517 | dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); | |||
1518 | ||||
1519 | if (!fast_validate) | |||
1520 | dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt); | |||
1521 | ||||
1522 | if (fast_validate || | |||
1523 | (dc->debug.dml_disallow_alternate_prefetch_modes && | |||
1524 | (vlevel == context->bw_ctx.dml.soc.num_states || | |||
1525 | vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported))) { | |||
1526 | /* | |||
1527 | * If dml_disallow_alternate_prefetch_modes is false, then we have already | |||
1528 | * tried alternate prefetch modes during full validation. | |||
1529 | * | |||
1530 | * If mode is unsupported or there is no p-state support, then | |||
1531 | * fall back to favouring voltage. | |||
1532 | * | |||
1533 | * If Prefetch mode 0 failed for this config, or passed with Max UCLK, then try | |||
1534 | * to support with Prefetch mode 1 (dm_prefetch_support_fclk_and_stutter == 2) | |||
1535 | */ | |||
1536 | context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = | |||
1537 | dm_prefetch_support_fclk_and_stutter; | |||
1538 | ||||
1539 | vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); | |||
1540 | ||||
1541 | /* Last attempt with Prefetch mode 2 (dm_prefetch_support_stutter == 3) */ | |||
1542 | if (vlevel == context->bw_ctx.dml.soc.num_states) { | |||
1543 | context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = | |||
1544 | dm_prefetch_support_stutter; | |||
1545 | vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); | |||
1546 | } | |||
1547 | ||||
1548 | if (vlevel < context->bw_ctx.dml.soc.num_states) { | |||
1549 | memset(split, 0, sizeof(split))__builtin_memset((split), (0), (sizeof(split))); | |||
1550 | memset(merge, 0, sizeof(merge))__builtin_memset((merge), (0), (sizeof(merge))); | |||
1551 | vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); | |||
1552 | // dcn20_validate_apply_pipe_split_flags can modify voltage level outside of DML | |||
1553 | vba->VoltageLevel = vlevel; | |||
1554 | } | |||
1555 | } | |||
1556 | ||||
1557 | dml_log_mode_support_params(&context->bw_ctx.dml); | |||
1558 | ||||
1559 | if (vlevel == context->bw_ctx.dml.soc.num_states) | |||
1560 | goto validate_fail; | |||
1561 | ||||
1562 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
1563 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
1564 | struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; | |||
1565 | ||||
1566 | if (!pipe->stream) | |||
1567 | continue; | |||
1568 | ||||
1569 | if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled | |||
1570 | && !dc->config.enable_windowed_mpo_odm | |||
1571 | && pipe->plane_state && mpo_pipe | |||
1572 | && memcmp(&mpo_pipe->plane_res.scl_data.recout,__builtin_memcmp((&mpo_pipe->plane_res.scl_data.recout ), (&pipe->plane_res.scl_data.recout), (sizeof(struct rect ))) | |||
1573 | &pipe->plane_res.scl_data.recout,__builtin_memcmp((&mpo_pipe->plane_res.scl_data.recout ), (&pipe->plane_res.scl_data.recout), (sizeof(struct rect ))) | |||
1574 | sizeof(struct rect))__builtin_memcmp((&mpo_pipe->plane_res.scl_data.recout ), (&pipe->plane_res.scl_data.recout), (sizeof(struct rect ))) != 0) { | |||
1575 | ASSERT(mpo_pipe->plane_state != pipe->plane_state)do { if (({ static int __warned; int __ret = !!(!(mpo_pipe-> plane_state != pipe->plane_state)); if (__ret && ! __warned) { printf("WARNING %s failed at %s:%d\n", "!(mpo_pipe->plane_state != pipe->plane_state)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1575); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1576 | goto validate_fail; | |||
1577 | } | |||
1578 | pipe_idx++; | |||
1579 | } | |||
1580 | ||||
1581 | /* merge pipes if necessary */ | |||
1582 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
1583 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
1584 | ||||
1585 | /*skip pipes that don't need merging*/ | |||
1586 | if (!merge[i]) | |||
1587 | continue; | |||
1588 | ||||
1589 | /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ | |||
1590 | if (pipe->prev_odm_pipe) { | |||
1591 | /*split off odm pipe*/ | |||
1592 | pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; | |||
1593 | if (pipe->next_odm_pipe) | |||
1594 | pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; | |||
1595 | ||||
1596 | /*2:1ODM+MPC Split MPO to Single Pipe + MPC Split MPO*/ | |||
1597 | if (pipe->bottom_pipe) { | |||
1598 | if (pipe->bottom_pipe->prev_odm_pipe || pipe->bottom_pipe->next_odm_pipe) { | |||
1599 | /*MPC split rules will handle this case*/ | |||
1600 | pipe->bottom_pipe->top_pipe = NULL((void *)0); | |||
1601 | } else { | |||
1602 | /* when merging an ODM pipes, the bottom MPC pipe must now point to | |||
1603 | * the previous ODM pipe and its associated stream assets | |||
1604 | */ | |||
1605 | if (pipe->prev_odm_pipe->bottom_pipe) { | |||
1606 | /* 3 plane MPO*/ | |||
1607 | pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe->bottom_pipe; | |||
1608 | pipe->prev_odm_pipe->bottom_pipe->bottom_pipe = pipe->bottom_pipe; | |||
1609 | } else { | |||
1610 | /* 2 plane MPO*/ | |||
1611 | pipe->bottom_pipe->top_pipe = pipe->prev_odm_pipe; | |||
1612 | pipe->prev_odm_pipe->bottom_pipe = pipe->bottom_pipe; | |||
1613 | } | |||
1614 | ||||
1615 | memcpy(&pipe->bottom_pipe->stream_res, &pipe->bottom_pipe->top_pipe->stream_res, sizeof(struct stream_resource))__builtin_memcpy((&pipe->bottom_pipe->stream_res), ( &pipe->bottom_pipe->top_pipe->stream_res), (sizeof (struct stream_resource))); | |||
1616 | } | |||
1617 | } | |||
1618 | ||||
1619 | if (pipe->top_pipe) { | |||
1620 | pipe->top_pipe->bottom_pipe = NULL((void *)0); | |||
1621 | } | |||
1622 | ||||
1623 | pipe->bottom_pipe = NULL((void *)0); | |||
1624 | pipe->next_odm_pipe = NULL((void *)0); | |||
1625 | pipe->plane_state = NULL((void *)0); | |||
1626 | pipe->stream = NULL((void *)0); | |||
1627 | pipe->top_pipe = NULL((void *)0); | |||
1628 | pipe->prev_odm_pipe = NULL((void *)0); | |||
1629 | if (pipe->stream_res.dsc) | |||
1630 | dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); | |||
1631 | memset(&pipe->plane_res, 0, sizeof(pipe->plane_res))__builtin_memset((&pipe->plane_res), (0), (sizeof(pipe ->plane_res))); | |||
1632 | memset(&pipe->stream_res, 0, sizeof(pipe->stream_res))__builtin_memset((&pipe->stream_res), (0), (sizeof(pipe ->stream_res))); | |||
1633 | repopulate_pipes = true1; | |||
1634 | } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { | |||
1635 | struct pipe_ctx *top_pipe = pipe->top_pipe; | |||
1636 | struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; | |||
1637 | ||||
1638 | top_pipe->bottom_pipe = bottom_pipe; | |||
1639 | if (bottom_pipe) | |||
1640 | bottom_pipe->top_pipe = top_pipe; | |||
1641 | ||||
1642 | pipe->top_pipe = NULL((void *)0); | |||
1643 | pipe->bottom_pipe = NULL((void *)0); | |||
1644 | pipe->plane_state = NULL((void *)0); | |||
1645 | pipe->stream = NULL((void *)0); | |||
1646 | memset(&pipe->plane_res, 0, sizeof(pipe->plane_res))__builtin_memset((&pipe->plane_res), (0), (sizeof(pipe ->plane_res))); | |||
1647 | memset(&pipe->stream_res, 0, sizeof(pipe->stream_res))__builtin_memset((&pipe->stream_res), (0), (sizeof(pipe ->stream_res))); | |||
1648 | repopulate_pipes = true1; | |||
1649 | } else | |||
1650 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1650); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* Should never try to merge master pipe */ | |||
1651 | ||||
1652 | } | |||
1653 | ||||
1654 | for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { | |||
1655 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
1656 | struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | |||
1657 | struct pipe_ctx *hsplit_pipe = NULL((void *)0); | |||
1658 | bool_Bool odm; | |||
1659 | int old_index = -1; | |||
1660 | ||||
1661 | if (!pipe->stream || newly_split[i]) | |||
1662 | continue; | |||
1663 | ||||
1664 | pipe_idx++; | |||
1665 | odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; | |||
1666 | ||||
1667 | if (!pipe->plane_state && !odm) | |||
1668 | continue; | |||
1669 | ||||
1670 | if (split[i]) { | |||
1671 | if (odm) { | |||
1672 | if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe) | |||
1673 | old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; | |||
1674 | else if (old_pipe->next_odm_pipe) | |||
1675 | old_index = old_pipe->next_odm_pipe->pipe_idx; | |||
1676 | } else { | |||
1677 | if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && | |||
1678 | old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) | |||
1679 | old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; | |||
1680 | else if (old_pipe->bottom_pipe && | |||
1681 | old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) | |||
1682 | old_index = old_pipe->bottom_pipe->pipe_idx; | |||
1683 | } | |||
1684 | hsplit_pipe = dcn32_find_split_pipe(dc, context, old_index); | |||
1685 | ASSERT(hsplit_pipe)do { if (({ static int __warned; int __ret = !!(!(hsplit_pipe )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(hsplit_pipe)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1685); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1686 | if (!hsplit_pipe) | |||
1687 | goto validate_fail; | |||
1688 | ||||
1689 | if (!dcn32_split_stream_for_mpc_or_odm( | |||
1690 | dc, &context->res_ctx, | |||
1691 | pipe, hsplit_pipe, odm)) | |||
1692 | goto validate_fail; | |||
1693 | ||||
1694 | newly_split[hsplit_pipe->pipe_idx] = true1; | |||
1695 | repopulate_pipes = true1; | |||
1696 | } | |||
1697 | if (split[i] == 4) { | |||
1698 | struct pipe_ctx *pipe_4to1; | |||
1699 | ||||
1700 | if (odm && old_pipe->next_odm_pipe) | |||
1701 | old_index = old_pipe->next_odm_pipe->pipe_idx; | |||
1702 | else if (!odm && old_pipe->bottom_pipe && | |||
1703 | old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) | |||
1704 | old_index = old_pipe->bottom_pipe->pipe_idx; | |||
1705 | else | |||
1706 | old_index = -1; | |||
1707 | pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); | |||
1708 | ASSERT(pipe_4to1)do { if (({ static int __warned; int __ret = !!(!(pipe_4to1)) ; if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipe_4to1)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1708); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1709 | if (!pipe_4to1) | |||
1710 | goto validate_fail; | |||
1711 | if (!dcn32_split_stream_for_mpc_or_odm( | |||
1712 | dc, &context->res_ctx, | |||
1713 | pipe, pipe_4to1, odm)) | |||
1714 | goto validate_fail; | |||
1715 | newly_split[pipe_4to1->pipe_idx] = true1; | |||
1716 | ||||
1717 | if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe | |||
1718 | && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe) | |||
1719 | old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; | |||
1720 | else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && | |||
1721 | old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && | |||
1722 | old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) | |||
1723 | old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx; | |||
1724 | else | |||
1725 | old_index = -1; | |||
1726 | pipe_4to1 = dcn32_find_split_pipe(dc, context, old_index); | |||
1727 | ASSERT(pipe_4to1)do { if (({ static int __warned; int __ret = !!(!(pipe_4to1)) ; if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipe_4to1)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c" , 1727); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1728 | if (!pipe_4to1) | |||
1729 | goto validate_fail; | |||
1730 | if (!dcn32_split_stream_for_mpc_or_odm( | |||
1731 | dc, &context->res_ctx, | |||
1732 | hsplit_pipe, pipe_4to1, odm)) | |||
1733 | goto validate_fail; | |||
1734 | newly_split[pipe_4to1->pipe_idx] = true1; | |||
1735 | } | |||
1736 | if (odm) | |||
1737 | dcn20_build_mapped_resource(dc, context, pipe->stream); | |||
1738 | } | |||
1739 | ||||
1740 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
1741 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
1742 | ||||
1743 | if (pipe->plane_state) { | |||
1744 | if (!resource_build_scaling_params(pipe)) | |||
1745 | goto validate_fail; | |||
1746 | } | |||
1747 | } | |||
1748 | ||||
1749 | /* Actual dsc count per stream dsc validation*/ | |||
1750 | if (!dcn20_validate_dsc(dc, context)) { | |||
1751 | vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; | |||
1752 | goto validate_fail; | |||
1753 | } | |||
1754 | ||||
1755 | if (repopulate_pipes) { | |||
1756 | pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); | |||
1757 | ||||
1758 | /* repopulate_pipes = 1 means the pipes were either split or merged. In this case | |||
1759 | * we have to re-calculate the DET allocation and run through DML once more to | |||
1760 | * ensure all the params are calculated correctly. We do not need to run the | |||
1761 | * pipe split check again after this call (pipes are already split / merged). | |||
1762 | * */ | |||
1763 | if (!fast_validate) { | |||
1764 | context->bw_ctx.dml.soc.allow_for_pstate_or_stutter_in_vblank_final = | |||
1765 | dm_prefetch_support_uclk_fclk_and_stutter_if_possible; | |||
1766 | vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); | |||
1767 | } | |||
1768 | } | |||
1769 | *vlevel_out = vlevel; | |||
1770 | *pipe_cnt_out = pipe_cnt; | |||
1771 | ||||
1772 | out = true1; | |||
1773 | goto validate_out; | |||
1774 | ||||
1775 | validate_fail: | |||
1776 | out = false0; | |||
1777 | ||||
1778 | validate_out: | |||
1779 | return out; | |||
1780 | } | |||
1781 | ||||
1782 | ||||
1783 | void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, | |||
1784 | display_e2e_pipe_params_st *pipes, | |||
1785 | int pipe_cnt, | |||
1786 | int vlevel) | |||
1787 | { | |||
1788 | int i, pipe_idx, vlevel_temp = 0; | |||
1789 | double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; | |||
1790 | double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; | |||
1791 | double dram_speed_from_validation = context->bw_ctx.dml.vba.DRAMSpeed; | |||
1792 | double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation; | |||
1793 | bool_Bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != | |||
1794 | dm_dram_clock_change_unsupported; | |||
1795 | unsigned int dummy_latency_index = 0; | |||
1796 | int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; | |||
1797 | unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed; | |||
1798 | unsigned int min_dram_speed_mts_margin; | |||
1799 | ||||
1800 | dc_assert_fp_enabled(); | |||
1801 | ||||
1802 | // Override DRAMClockChangeSupport for SubVP + DRR case where the DRR cannot switch without stretching it's VBLANK | |||
1803 | if (!pstate_en && dcn32_subvp_in_use(dc, context)) { | |||
1804 | context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = dm_dram_clock_change_vblank_w_mall_sub_vp; | |||
1805 | pstate_en = true1; | |||
1806 | } | |||
1807 | ||||
1808 | context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false0; | |||
1809 | ||||
1810 | if (!pstate_en) { | |||
1811 | /* only when the mclk switch can not be natural, is the fw based vblank stretch attempted */ | |||
1812 | context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = | |||
1813 | dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(dc, context); | |||
1814 | ||||
1815 | if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { | |||
1816 | dummy_latency_index = dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(dc, | |||
1817 | context, pipes, pipe_cnt, vlevel); | |||
1818 | ||||
1819 | /* After calling dcn30_find_dummy_latency_index_for_fw_based_mclk_switch | |||
1820 | * we reinstate the original dram_clock_change_latency_us on the context | |||
1821 | * and all variables that may have changed up to this point, except the | |||
1822 | * newly found dummy_latency_index | |||
1823 | */ | |||
1824 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = | |||
1825 | dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A0].dml_input.pstate_latency_us; | |||
1826 | /* For DCN32/321 need to validate with fclk pstate change latency equal to dummy so | |||
1827 | * prefetch is scheduled correctly to account for dummy pstate. | |||
1828 | */ | |||
1829 | if (dummy_latency_index == 0) | |||
1830 | context->bw_ctx.dml.soc.fclk_change_latency_us = | |||
1831 | dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; | |||
1832 | dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false0); | |||
1833 | maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; | |||
1834 | dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; | |||
1835 | pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != | |||
1836 | dm_dram_clock_change_unsupported; | |||
1837 | } | |||
1838 | } | |||
1839 | ||||
1840 | /* Set B: | |||
1841 | * For Set B calculations use clocks from clock_limits[2] when available i.e. when SMU is present, | |||
1842 | * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark | |||
1843 | * calculations to cover bootup clocks. | |||
1844 | * DCFCLK: soc.clock_limits[2] when available | |||
1845 | * UCLK: soc.clock_limits[2] when available | |||
1846 | */ | |||
1847 | if (dcn3_2_soc.num_states > 2) { | |||
1848 | vlevel_temp = 2; | |||
1849 | dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; | |||
1850 | } else | |||
1851 | dcfclk = 615; //DCFCLK Vmin_lv | |||
1852 | ||||
1853 | pipes[0].clks_cfg.voltage = vlevel_temp; | |||
1854 | pipes[0].clks_cfg.dcfclk_mhz = dcfclk; | |||
1855 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; | |||
1856 | ||||
1857 | if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].valid) { | |||
1858 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].dml_input.pstate_latency_us; | |||
1859 | context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].dml_input.fclk_change_latency_us; | |||
1860 | context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].dml_input.sr_enter_plus_exit_time_us; | |||
1861 | context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B1].dml_input.sr_exit_time_us; | |||
1862 | } | |||
1863 | context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1864 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1865 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1866 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1867 | context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1868 | context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1869 | context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1870 | context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1871 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1872 | context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1873 | ||||
1874 | /* Set D: | |||
1875 | * All clocks min. | |||
1876 | * DCFCLK: Min, as reported by PM FW when available | |||
1877 | * UCLK : Min, as reported by PM FW when available | |||
1878 | * sr_enter_exit/sr_exit should be lower than used for DRAM (TBD after bringup or later, use as decided in Clk Mgr) | |||
1879 | */ | |||
1880 | ||||
1881 | if (dcn3_2_soc.num_states > 2) { | |||
1882 | vlevel_temp = 0; | |||
1883 | dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; | |||
1884 | } else | |||
1885 | dcfclk = 615; //DCFCLK Vmin_lv | |||
1886 | ||||
1887 | pipes[0].clks_cfg.voltage = vlevel_temp; | |||
1888 | pipes[0].clks_cfg.dcfclk_mhz = dcfclk; | |||
1889 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; | |||
1890 | ||||
1891 | if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D3].valid) { | |||
1892 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D3].dml_input.pstate_latency_us; | |||
1893 | context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D3].dml_input.fclk_change_latency_us; | |||
1894 | context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D3].dml_input.sr_enter_plus_exit_time_us; | |||
1895 | context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D3].dml_input.sr_exit_time_us; | |||
1896 | } | |||
1897 | context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1898 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1899 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1900 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1901 | context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1902 | context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1903 | context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1904 | context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1905 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1906 | context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1907 | ||||
1908 | /* Set C, for Dummy P-State: | |||
1909 | * All clocks min. | |||
1910 | * DCFCLK: Min, as reported by PM FW, when available | |||
1911 | * UCLK : Min, as reported by PM FW, when available | |||
1912 | * pstate latency as per UCLK state dummy pstate latency | |||
1913 | */ | |||
1914 | ||||
1915 | // For Set A and Set C use values from validation | |||
1916 | pipes[0].clks_cfg.voltage = vlevel; | |||
1917 | pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation; | |||
1918 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; | |||
1919 | ||||
1920 | if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { | |||
1921 | pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching; | |||
1922 | } | |||
1923 | ||||
1924 | if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C2].valid) { | |||
1925 | min_dram_speed_mts = dram_speed_from_validation; | |||
1926 | min_dram_speed_mts_margin = 160; | |||
1927 | ||||
1928 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = | |||
1929 | dc->clk_mgr->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us; | |||
1930 | ||||
1931 | if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] == | |||
1932 | dm_dram_clock_change_unsupported) { | |||
1933 | int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1; | |||
1934 | ||||
1935 | min_dram_speed_mts = | |||
1936 | dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; | |||
1937 | } | |||
1938 | ||||
1939 | if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { | |||
1940 | /* find largest table entry that is lower than dram speed, | |||
1941 | * but lower than DPM0 still uses DPM0 | |||
1942 | */ | |||
1943 | for (dummy_latency_index = 3; dummy_latency_index > 0; dummy_latency_index--) | |||
1944 | if (min_dram_speed_mts + min_dram_speed_mts_margin > | |||
1945 | dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts) | |||
1946 | break; | |||
1947 | } | |||
1948 | ||||
1949 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = | |||
1950 | dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; | |||
1951 | ||||
1952 | context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C2].dml_input.fclk_change_latency_us; | |||
1953 | context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C2].dml_input.sr_enter_plus_exit_time_us; | |||
1954 | context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C2].dml_input.sr_exit_time_us; | |||
1955 | } | |||
1956 | ||||
1957 | context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1958 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1959 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1960 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1961 | context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1962 | context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1963 | context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1964 | context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1965 | /* On DCN32/321, PMFW will set PSTATE_CHANGE_TYPE = 1 (FCLK) for UCLK dummy p-state. | |||
1966 | * In this case we must program FCLK WM Set C to use the UCLK dummy p-state WM | |||
1967 | * value. | |||
1968 | */ | |||
1969 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1970 | context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1971 | ||||
1972 | if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C2].valid)) { | |||
1973 | /* The only difference between A and C is p-state latency, if p-state is not supported | |||
1974 | * with full p-state latency we want to calculate DLG based on dummy p-state latency, | |||
1975 | * Set A p-state watermark set to 0 on DCN30, when p-state unsupported, for now keep as DCN30. | |||
1976 | */ | |||
1977 | context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; | |||
1978 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; | |||
1979 | /* Calculate FCLK p-state change watermark based on FCLK pstate change latency in case | |||
1980 | * UCLK p-state is not supported, to avoid underflow in case FCLK pstate is supported | |||
1981 | */ | |||
1982 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1983 | } else { | |||
1984 | /* Set A: | |||
1985 | * All clocks min. | |||
1986 | * DCFCLK: Min, as reported by PM FW, when available | |||
1987 | * UCLK: Min, as reported by PM FW, when available | |||
1988 | */ | |||
1989 | dc->res_pool->funcs->update_soc_for_wm_a(dc, context); | |||
1990 | context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1991 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1992 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1993 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1994 | context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1995 | context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1996 | context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1997 | context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1998 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
1999 | context->bw_ctx.bw.dcn.watermarks.a.usr_retraining_ns = get_usr_retraining_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
2000 | } | |||
2001 | ||||
2002 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
2003 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
2004 | continue; | |||
2005 | ||||
2006 | pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); | |||
2007 | pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
2008 | ||||
2009 | if (dc->config.forced_clocks) { | |||
2010 | pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; | |||
2011 | pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; | |||
2012 | } | |||
2013 | if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) | |||
2014 | pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; | |||
2015 | if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) | |||
2016 | pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; | |||
2017 | ||||
2018 | pipe_idx++; | |||
2019 | } | |||
2020 | ||||
2021 | context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod; | |||
2022 | ||||
2023 | if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && dummy_latency_index == 0) | |||
2024 | context->bw_ctx.dml.soc.fclk_change_latency_us = | |||
2025 | dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; | |||
2026 | ||||
2027 | dcn32_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); | |||
2028 | ||||
2029 | if (!pstate_en) | |||
2030 | /* Restore full p-state latency */ | |||
2031 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = | |||
2032 | dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A0].dml_input.pstate_latency_us; | |||
2033 | ||||
2034 | if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { | |||
2035 | dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(dc, context); | |||
2036 | if (dummy_latency_index == 0) | |||
2037 | context->bw_ctx.dml.soc.fclk_change_latency_us = | |||
2038 | dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A0].dml_input.fclk_change_latency_us; | |||
2039 | } | |||
2040 | } | |||
2041 | ||||
2042 | static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, | |||
2043 | unsigned int *optimal_dcfclk, | |||
2044 | unsigned int *optimal_fclk) | |||
2045 | { | |||
2046 | double bw_from_dram, bw_from_dram1, bw_from_dram2; | |||
2047 | ||||
2048 | bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans * | |||
2049 | dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); | |||
2050 | bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans * | |||
2051 | dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); | |||
2052 | ||||
2053 | bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; | |||
2054 | ||||
2055 | if (optimal_fclk) | |||
2056 | *optimal_fclk = bw_from_dram / | |||
2057 | (dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); | |||
2058 | ||||
2059 | if (optimal_dcfclk) | |||
2060 | *optimal_dcfclk = bw_from_dram / | |||
2061 | (dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100)); | |||
2062 | } | |||
2063 | ||||
2064 | static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, | |||
2065 | unsigned int index) | |||
2066 | { | |||
2067 | int i; | |||
2068 | ||||
2069 | if (*num_entries == 0) | |||
2070 | return; | |||
2071 | ||||
2072 | for (i = index; i < *num_entries - 1; i++) { | |||
2073 | table[i] = table[i + 1]; | |||
2074 | } | |||
2075 | memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st))__builtin_memset((&table[--(*num_entries)]), (0), (sizeof (struct _vcs_dpi_voltage_scaling_st))); | |||
2076 | } | |||
2077 | ||||
2078 | void dcn32_patch_dpm_table(struct clk_bw_params *bw_params) | |||
2079 | { | |||
2080 | int i; | |||
2081 | unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, | |||
2082 | max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; | |||
2083 | ||||
2084 | for (i = 0; i < MAX_NUM_DPM_LVL8; i++) { | |||
2085 | if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) | |||
2086 | max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; | |||
2087 | if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) | |||
2088 | max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; | |||
2089 | if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) | |||
2090 | max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; | |||
2091 | if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) | |||
2092 | max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; | |||
2093 | if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) | |||
2094 | max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; | |||
2095 | if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) | |||
2096 | max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; | |||
2097 | if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) | |||
2098 | max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; | |||
2099 | } | |||
2100 | ||||
2101 | /* Scan through clock values we currently have and if they are 0, | |||
2102 | * then populate it with dcn3_2_soc.clock_limits[] value. | |||
2103 | * | |||
2104 | * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being | |||
2105 | * 0, will cause it to skip building the clock table. | |||
2106 | */ | |||
2107 | if (max_dcfclk_mhz == 0) | |||
2108 | bw_params->clk_table.entries[0].dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; | |||
2109 | if (max_dispclk_mhz == 0) | |||
2110 | bw_params->clk_table.entries[0].dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; | |||
2111 | if (max_dtbclk_mhz == 0) | |||
2112 | bw_params->clk_table.entries[0].dtbclk_mhz = dcn3_2_soc.clock_limits[0].dtbclk_mhz; | |||
2113 | if (max_uclk_mhz == 0) | |||
2114 | bw_params->clk_table.entries[0].memclk_mhz = dcn3_2_soc.clock_limits[0].dram_speed_mts / 16; | |||
2115 | } | |||
2116 | ||||
2117 | static int build_synthetic_soc_states(struct clk_bw_params *bw_params, | |||
2118 | struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) | |||
2119 | { | |||
2120 | int i, j; | |||
2121 | struct _vcs_dpi_voltage_scaling_st entry = {0}; | |||
2122 | ||||
2123 | unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, | |||
2124 | max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0; | |||
2125 | ||||
2126 | unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; | |||
2127 | ||||
2128 | static const unsigned int num_dcfclk_stas = 5; | |||
2129 | unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES20] = {199, 615, 906, 1324, 1564}; | |||
2130 | ||||
2131 | unsigned int num_uclk_dpms = 0; | |||
2132 | unsigned int num_fclk_dpms = 0; | |||
2133 | unsigned int num_dcfclk_dpms = 0; | |||
2134 | ||||
2135 | for (i = 0; i < MAX_NUM_DPM_LVL8; i++) { | |||
2136 | if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) | |||
2137 | max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; | |||
2138 | if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) | |||
2139 | max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; | |||
2140 | if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) | |||
2141 | max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; | |||
2142 | if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) | |||
2143 | max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; | |||
2144 | if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) | |||
2145 | max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; | |||
2146 | if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) | |||
2147 | max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; | |||
2148 | if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz) | |||
2149 | max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; | |||
2150 | ||||
2151 | if (bw_params->clk_table.entries[i].memclk_mhz > 0) | |||
2152 | num_uclk_dpms++; | |||
2153 | if (bw_params->clk_table.entries[i].fclk_mhz > 0) | |||
2154 | num_fclk_dpms++; | |||
2155 | if (bw_params->clk_table.entries[i].dcfclk_mhz > 0) | |||
2156 | num_dcfclk_dpms++; | |||
2157 | } | |||
2158 | ||||
2159 | if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz) | |||
2160 | return -1; | |||
2161 | ||||
2162 | if (max_dppclk_mhz == 0) | |||
2163 | max_dppclk_mhz = max_dispclk_mhz; | |||
2164 | ||||
2165 | if (max_fclk_mhz == 0) | |||
2166 | max_fclk_mhz = max_dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / dcn3_2_soc.pct_ideal_fabric_bw_after_urgent; | |||
2167 | ||||
2168 | if (max_phyclk_mhz == 0) | |||
2169 | max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; | |||
2170 | ||||
2171 | *num_entries = 0; | |||
2172 | entry.dispclk_mhz = max_dispclk_mhz; | |||
2173 | entry.dscclk_mhz = max_dispclk_mhz / 3; | |||
2174 | entry.dppclk_mhz = max_dppclk_mhz; | |||
2175 | entry.dtbclk_mhz = max_dtbclk_mhz; | |||
2176 | entry.phyclk_mhz = max_phyclk_mhz; | |||
2177 | entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; | |||
2178 | entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; | |||
2179 | ||||
2180 | // Insert all the DCFCLK STAs | |||
2181 | for (i = 0; i < num_dcfclk_stas; i++) { | |||
2182 | entry.dcfclk_mhz = dcfclk_sta_targets[i]; | |||
2183 | entry.fabricclk_mhz = 0; | |||
2184 | entry.dram_speed_mts = 0; | |||
2185 | ||||
2186 | insert_entry_into_table_sorted(table, num_entries, &entry); | |||
2187 | } | |||
2188 | ||||
2189 | // Insert the max DCFCLK | |||
2190 | entry.dcfclk_mhz = max_dcfclk_mhz; | |||
2191 | entry.fabricclk_mhz = 0; | |||
2192 | entry.dram_speed_mts = 0; | |||
2193 | ||||
2194 | insert_entry_into_table_sorted(table, num_entries, &entry); | |||
2195 | ||||
2196 | // Insert the UCLK DPMS | |||
2197 | for (i = 0; i < num_uclk_dpms; i++) { | |||
2198 | entry.dcfclk_mhz = 0; | |||
2199 | entry.fabricclk_mhz = 0; | |||
2200 | entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; | |||
2201 | ||||
2202 | insert_entry_into_table_sorted(table, num_entries, &entry); | |||
2203 | } | |||
2204 | ||||
2205 | // If FCLK is coarse grained, insert individual DPMs. | |||
2206 | if (num_fclk_dpms > 2) { | |||
2207 | for (i = 0; i < num_fclk_dpms; i++) { | |||
2208 | entry.dcfclk_mhz = 0; | |||
2209 | entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; | |||
2210 | entry.dram_speed_mts = 0; | |||
2211 | ||||
2212 | insert_entry_into_table_sorted(table, num_entries, &entry); | |||
2213 | } | |||
2214 | } | |||
2215 | // If FCLK fine grained, only insert max | |||
2216 | else { | |||
2217 | entry.dcfclk_mhz = 0; | |||
2218 | entry.fabricclk_mhz = max_fclk_mhz; | |||
2219 | entry.dram_speed_mts = 0; | |||
2220 | ||||
2221 | insert_entry_into_table_sorted(table, num_entries, &entry); | |||
2222 | } | |||
2223 | ||||
2224 | // At this point, the table contains all "points of interest" based on | |||
2225 | // DPMs from PMFW, and STAs. Table is sorted by BW, and all clock | |||
2226 | // ratios (by derate, are exact). | |||
2227 | ||||
2228 | // Remove states that require higher clocks than are supported | |||
2229 | for (i = *num_entries - 1; i >= 0 ; i--) { | |||
2230 | if (table[i].dcfclk_mhz > max_dcfclk_mhz || | |||
2231 | table[i].fabricclk_mhz > max_fclk_mhz || | |||
2232 | table[i].dram_speed_mts > max_uclk_mhz * 16) | |||
2233 | remove_entry_from_table_at_index(table, num_entries, i); | |||
2234 | } | |||
2235 | ||||
2236 | // At this point, the table only contains supported points of interest | |||
2237 | // it could be used as is, but some states may be redundant due to | |||
2238 | // coarse grained nature of some clocks, so we want to round up to | |||
2239 | // coarse grained DPMs and remove duplicates. | |||
2240 | ||||
2241 | // Round up UCLKs | |||
2242 | for (i = *num_entries - 1; i >= 0 ; i--) { | |||
2243 | for (j = 0; j < num_uclk_dpms; j++) { | |||
2244 | if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { | |||
2245 | table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; | |||
2246 | break; | |||
2247 | } | |||
2248 | } | |||
2249 | } | |||
2250 | ||||
2251 | // If FCLK is coarse grained, round up to next DPMs | |||
2252 | if (num_fclk_dpms > 2) { | |||
2253 | for (i = *num_entries - 1; i >= 0 ; i--) { | |||
2254 | for (j = 0; j < num_fclk_dpms; j++) { | |||
2255 | if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) { | |||
2256 | table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz; | |||
2257 | break; | |||
2258 | } | |||
2259 | } | |||
2260 | } | |||
2261 | } | |||
2262 | // Otherwise, round up to minimum. | |||
2263 | else { | |||
2264 | for (i = *num_entries - 1; i >= 0 ; i--) { | |||
2265 | if (table[i].fabricclk_mhz < min_fclk_mhz) { | |||
2266 | table[i].fabricclk_mhz = min_fclk_mhz; | |||
2267 | break; | |||
2268 | } | |||
2269 | } | |||
2270 | } | |||
2271 | ||||
2272 | // Round DCFCLKs up to minimum | |||
2273 | for (i = *num_entries - 1; i >= 0 ; i--) { | |||
2274 | if (table[i].dcfclk_mhz < min_dcfclk_mhz) { | |||
2275 | table[i].dcfclk_mhz = min_dcfclk_mhz; | |||
2276 | break; | |||
2277 | } | |||
2278 | } | |||
2279 | ||||
2280 | // Remove duplicate states, note duplicate states are always neighbouring since table is sorted. | |||
2281 | i = 0; | |||
2282 | while (i < *num_entries - 1) { | |||
2283 | if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz && | |||
2284 | table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz && | |||
2285 | table[i].dram_speed_mts == table[i + 1].dram_speed_mts) | |||
2286 | remove_entry_from_table_at_index(table, num_entries, i + 1); | |||
2287 | else | |||
2288 | i++; | |||
2289 | } | |||
2290 | ||||
2291 | // Fix up the state indicies | |||
2292 | for (i = *num_entries - 1; i >= 0 ; i--) { | |||
2293 | table[i].state = i; | |||
2294 | } | |||
2295 | ||||
2296 | return 0; | |||
2297 | } | |||
2298 | ||||
2299 | /* | |||
2300 | * dcn32_update_bw_bounding_box | |||
2301 | * | |||
2302 | * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from | |||
2303 | * spreadsheet with actual values as per dGPU SKU: | |||
2304 | * - with passed few options from dc->config | |||
2305 | * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might | |||
2306 | * need to get it from PM FW) | |||
2307 | * - with passed latency values (passed in ns units) in dc-> bb override for | |||
2308 | * debugging purposes | |||
2309 | * - with passed latencies from VBIOS (in 100_ns units) if available for | |||
2310 | * certain dGPU SKU | |||
2311 | * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU | |||
2312 | * of the same ASIC) | |||
2313 | * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM | |||
2314 | * FW for different clocks (which might differ for certain dGPU SKU of the | |||
2315 | * same ASIC) | |||
2316 | */ | |||
2317 | void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) | |||
2318 | { | |||
2319 | dc_assert_fp_enabled(); | |||
2320 | ||||
2321 | if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) { | |||
2322 | /* Overrides from dc->config options */ | |||
2323 | dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk; | |||
2324 | ||||
2325 | /* Override from passed dc->bb_overrides if available*/ | |||
2326 | if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns | |||
2327 | && dc->bb_overrides.sr_exit_time_ns) { | |||
2328 | dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; | |||
2329 | } | |||
2330 | ||||
2331 | if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000) | |||
2332 | != dc->bb_overrides.sr_enter_plus_exit_time_ns | |||
2333 | && dc->bb_overrides.sr_enter_plus_exit_time_ns) { | |||
2334 | dcn3_2_soc.sr_enter_plus_exit_time_us = | |||
2335 | dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; | |||
2336 | } | |||
2337 | ||||
2338 | if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns | |||
2339 | && dc->bb_overrides.urgent_latency_ns) { | |||
2340 | dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; | |||
2341 | dcn3_2_soc.urgent_latency_pixel_data_only_us = dc->bb_overrides.urgent_latency_ns / 1000.0; | |||
2342 | } | |||
2343 | ||||
2344 | if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) | |||
2345 | != dc->bb_overrides.dram_clock_change_latency_ns | |||
2346 | && dc->bb_overrides.dram_clock_change_latency_ns) { | |||
2347 | dcn3_2_soc.dram_clock_change_latency_us = | |||
2348 | dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; | |||
2349 | } | |||
2350 | ||||
2351 | if ((int)(dcn3_2_soc.fclk_change_latency_us * 1000) | |||
2352 | != dc->bb_overrides.fclk_clock_change_latency_ns | |||
2353 | && dc->bb_overrides.fclk_clock_change_latency_ns) { | |||
2354 | dcn3_2_soc.fclk_change_latency_us = | |||
2355 | dc->bb_overrides.fclk_clock_change_latency_ns / 1000; | |||
2356 | } | |||
2357 | ||||
2358 | if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000) | |||
2359 | != dc->bb_overrides.dummy_clock_change_latency_ns | |||
2360 | && dc->bb_overrides.dummy_clock_change_latency_ns) { | |||
2361 | dcn3_2_soc.dummy_pstate_latency_us = | |||
2362 | dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; | |||
2363 | } | |||
2364 | ||||
2365 | /* Override from VBIOS if VBIOS bb_info available */ | |||
2366 | if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { | |||
2367 | struct bp_soc_bb_info bb_info = {0}; | |||
2368 | ||||
2369 | if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { | |||
2370 | if (bb_info.dram_clock_change_latency_100ns > 0) | |||
2371 | dcn3_2_soc.dram_clock_change_latency_us = | |||
2372 | bb_info.dram_clock_change_latency_100ns * 10; | |||
2373 | ||||
2374 | if (bb_info.dram_sr_enter_exit_latency_100ns > 0) | |||
2375 | dcn3_2_soc.sr_enter_plus_exit_time_us = | |||
2376 | bb_info.dram_sr_enter_exit_latency_100ns * 10; | |||
2377 | ||||
2378 | if (bb_info.dram_sr_exit_latency_100ns > 0) | |||
2379 | dcn3_2_soc.sr_exit_time_us = | |||
2380 | bb_info.dram_sr_exit_latency_100ns * 10; | |||
2381 | } | |||
2382 | } | |||
2383 | ||||
2384 | /* Override from VBIOS for num_chan */ | |||
2385 | if (dc->ctx->dc_bios->vram_info.num_chans) { | |||
2386 | dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; | |||
2387 | dcn3_2_soc.mall_allocated_for_dcn_mbytes = (double)(dcn32_calc_num_avail_chans_for_mall(dc, | |||
2388 | dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel); | |||
2389 | } | |||
2390 | ||||
2391 | if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) | |||
2392 | dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; | |||
2393 | } | |||
2394 | ||||
2395 | /* DML DSC delay factor workaround */ | |||
2396 | dcn3_2_ip.dsc_delay_factor_wa = dc->debug.dsc_delay_factor_wa_x1000 / 1000.0; | |||
2397 | ||||
2398 | dcn3_2_ip.min_prefetch_in_strobe_us = dc->debug.min_prefetch_in_strobe_ns / 1000.0; | |||
2399 | ||||
2400 | /* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */ | |||
2401 | dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; | |||
2402 | dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; | |||
2403 | ||||
2404 | /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ | |||
2405 | if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) && (bw_params->clk_table.entries[0].memclk_mhz)) { | |||
2406 | if (dc->debug.use_legacy_soc_bb_mechanism) { | |||
2407 | unsigned int i = 0, j = 0, num_states = 0; | |||
2408 | ||||
2409 | unsigned int dcfclk_mhz[DC__VOLTAGE_STATES20] = {0}; | |||
2410 | unsigned int dram_speed_mts[DC__VOLTAGE_STATES20] = {0}; | |||
2411 | unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES20] = {0}; | |||
2412 | unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES20] = {0}; | |||
2413 | unsigned int min_dcfclk = UINT_MAX0xffffffffU; | |||
2414 | /* Set 199 as first value in STA target array to have a minimum DCFCLK value. | |||
2415 | * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */ | |||
2416 | unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES20] = {199, 615, 906, 1324, 1564}; | |||
2417 | unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; | |||
2418 | unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; | |||
2419 | ||||
2420 | for (i = 0; i < MAX_NUM_DPM_LVL8; i++) { | |||
2421 | if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) | |||
2422 | max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; | |||
2423 | if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 && | |||
2424 | bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk) | |||
2425 | min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz; | |||
2426 | if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) | |||
2427 | max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; | |||
2428 | if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) | |||
2429 | max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; | |||
2430 | if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) | |||
2431 | max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; | |||
2432 | } | |||
2433 | if (min_dcfclk > dcfclk_sta_targets[0]) | |||
2434 | dcfclk_sta_targets[0] = min_dcfclk; | |||
2435 | if (!max_dcfclk_mhz) | |||
2436 | max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; | |||
2437 | if (!max_dispclk_mhz) | |||
2438 | max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; | |||
2439 | if (!max_dppclk_mhz) | |||
2440 | max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; | |||
2441 | if (!max_phyclk_mhz) | |||
2442 | max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; | |||
2443 | ||||
2444 | if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { | |||
2445 | // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array | |||
2446 | dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; | |||
2447 | num_dcfclk_sta_targets++; | |||
2448 | } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { | |||
2449 | // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates | |||
2450 | for (i = 0; i < num_dcfclk_sta_targets; i++) { | |||
2451 | if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { | |||
2452 | dcfclk_sta_targets[i] = max_dcfclk_mhz; | |||
2453 | break; | |||
2454 | } | |||
2455 | } | |||
2456 | // Update size of array since we "removed" duplicates | |||
2457 | num_dcfclk_sta_targets = i + 1; | |||
2458 | } | |||
2459 | ||||
2460 | num_uclk_states = bw_params->clk_table.num_entries; | |||
2461 | ||||
2462 | // Calculate optimal dcfclk for each uclk | |||
2463 | for (i = 0; i < num_uclk_states; i++) { | |||
2464 | dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, | |||
2465 | &optimal_dcfclk_for_uclk[i], NULL((void *)0)); | |||
2466 | if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { | |||
2467 | optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; | |||
2468 | } | |||
2469 | } | |||
2470 | ||||
2471 | // Calculate optimal uclk for each dcfclk sta target | |||
2472 | for (i = 0; i < num_dcfclk_sta_targets; i++) { | |||
2473 | for (j = 0; j < num_uclk_states; j++) { | |||
2474 | if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { | |||
2475 | optimal_uclk_for_dcfclk_sta_targets[i] = | |||
2476 | bw_params->clk_table.entries[j].memclk_mhz * 16; | |||
2477 | break; | |||
2478 | } | |||
2479 | } | |||
2480 | } | |||
2481 | ||||
2482 | i = 0; | |||
2483 | j = 0; | |||
2484 | // create the final dcfclk and uclk table | |||
2485 | while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES20) { | |||
2486 | if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { | |||
2487 | dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; | |||
2488 | dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; | |||
2489 | } else { | |||
2490 | if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { | |||
2491 | dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; | |||
2492 | dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; | |||
2493 | } else { | |||
2494 | j = num_uclk_states; | |||
2495 | } | |||
2496 | } | |||
2497 | } | |||
2498 | ||||
2499 | while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES20) { | |||
2500 | dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; | |||
2501 | dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; | |||
2502 | } | |||
2503 | ||||
2504 | while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES20 && | |||
2505 | optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { | |||
2506 | dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; | |||
2507 | dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; | |||
2508 | } | |||
2509 | ||||
2510 | dcn3_2_soc.num_states = num_states; | |||
2511 | for (i = 0; i < dcn3_2_soc.num_states; i++) { | |||
2512 | dcn3_2_soc.clock_limits[i].state = i; | |||
2513 | dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; | |||
2514 | dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; | |||
2515 | ||||
2516 | /* Fill all states with max values of all these clocks */ | |||
2517 | dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; | |||
2518 | dcn3_2_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; | |||
2519 | dcn3_2_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; | |||
2520 | dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; | |||
2521 | ||||
2522 | /* Populate from bw_params for DTBCLK, SOCCLK */ | |||
2523 | if (i > 0) { | |||
2524 | if (!bw_params->clk_table.entries[i].dtbclk_mhz) { | |||
2525 | dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; | |||
2526 | } else { | |||
2527 | dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; | |||
2528 | } | |||
2529 | } else if (bw_params->clk_table.entries[i].dtbclk_mhz) { | |||
2530 | dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; | |||
2531 | } | |||
2532 | ||||
2533 | if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) | |||
2534 | dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; | |||
2535 | else | |||
2536 | dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; | |||
2537 | ||||
2538 | if (!dram_speed_mts[i] && i > 0) | |||
2539 | dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; | |||
2540 | else | |||
2541 | dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; | |||
2542 | ||||
2543 | /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */ | |||
2544 | /* PHYCLK_D18, PHYCLK_D32 */ | |||
2545 | dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; | |||
2546 | dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; | |||
2547 | } | |||
2548 | } else { | |||
2549 | build_synthetic_soc_states(bw_params, dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states); | |||
2550 | } | |||
2551 | ||||
2552 | /* Re-init DML with updated bb */ | |||
2553 | dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); | |||
2554 | if (dc->current_state) | |||
2555 | dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32); | |||
2556 | } | |||
2557 | } | |||
2558 | ||||
2559 | void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, | |||
2560 | int pipe_cnt) | |||
2561 | { | |||
2562 | dc_assert_fp_enabled(); | |||
2563 | ||||
2564 | pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; | |||
2565 | pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; | |||
2566 | } | |||
2567 | ||||
2568 | bool_Bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe) | |||
2569 | { | |||
2570 | bool_Bool allow = false0; | |||
2571 | uint32_t refresh_rate = 0; | |||
2572 | ||||
2573 | /* Allow subvp on displays that have active margin for 2560x1440@60hz displays | |||
2574 | * only for now. There must be no scaling as well. | |||
2575 | * | |||
2576 | * For now we only enable on 2560x1440@60hz displays to enable 4K60 + 1440p60 configs | |||
2577 | * for p-state switching. | |||
2578 | */ | |||
2579 | if (pipe->stream && pipe->plane_state) { | |||
2580 | refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 + | |||
2581 | pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1) | |||
2582 | / (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total); | |||
2583 | if (pipe->stream->timing.v_addressable == 1440 && | |||
2584 | pipe->stream->timing.h_addressable == 2560 && | |||
2585 | refresh_rate >= 55 && refresh_rate <= 65 && | |||
2586 | pipe->plane_state->src_rect.height == 1440 && | |||
2587 | pipe->plane_state->src_rect.width == 2560 && | |||
2588 | pipe->plane_state->dst_rect.height == 1440 && | |||
2589 | pipe->plane_state->dst_rect.width == 2560) | |||
2590 | allow = true1; | |||
2591 | } | |||
2592 | return allow; | |||
2593 | } |