| File: | dev/pci/drm/amd/display/dc/dcn315/dcn315_resource.c |
| Warning: | line 1810, column 8 Dereference of null pointer |
Press '?' to see keyboard shortcuts
Keyboard shortcuts:
| 1 | /* | ||||
| 2 | * Copyright 2021 Advanced Micro Devices, Inc. | ||||
| 3 | * | ||||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||||
| 6 | * to deal in the Software without restriction, including without limitation | ||||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||||
| 10 | * | ||||
| 11 | * The above copyright notice and this permission notice shall be included in | ||||
| 12 | * all copies or substantial portions of the Software. | ||||
| 13 | * | ||||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||||
| 21 | * | ||||
| 22 | * Authors: AMD | ||||
| 23 | * | ||||
| 24 | */ | ||||
| 25 | |||||
| 26 | |||||
| 27 | #include "dm_services.h" | ||||
| 28 | #include "dc.h" | ||||
| 29 | |||||
| 30 | #include "dcn31/dcn31_init.h" | ||||
| 31 | |||||
| 32 | #include "resource.h" | ||||
| 33 | #include "include/irq_service_interface.h" | ||||
| 34 | #include "dcn315_resource.h" | ||||
| 35 | |||||
| 36 | #include "dcn20/dcn20_resource.h" | ||||
| 37 | #include "dcn30/dcn30_resource.h" | ||||
| 38 | #include "dcn31/dcn31_resource.h" | ||||
| 39 | |||||
| 40 | #include "dcn10/dcn10_ipp.h" | ||||
| 41 | #include "dcn30/dcn30_hubbub.h" | ||||
| 42 | #include "dcn31/dcn31_hubbub.h" | ||||
| 43 | #include "dcn30/dcn30_mpc.h" | ||||
| 44 | #include "dcn31/dcn31_hubp.h" | ||||
| 45 | #include "irq/dcn315/irq_service_dcn315.h" | ||||
| 46 | #include "dcn30/dcn30_dpp.h" | ||||
| 47 | #include "dcn31/dcn31_optc.h" | ||||
| 48 | #include "dcn20/dcn20_hwseq.h" | ||||
| 49 | #include "dcn30/dcn30_hwseq.h" | ||||
| 50 | #include "dce110/dce110_hw_sequencer.h" | ||||
| 51 | #include "dcn30/dcn30_opp.h" | ||||
| 52 | #include "dcn20/dcn20_dsc.h" | ||||
| 53 | #include "dcn30/dcn30_vpg.h" | ||||
| 54 | #include "dcn30/dcn30_afmt.h" | ||||
| 55 | #include "dcn30/dcn30_dio_stream_encoder.h" | ||||
| 56 | #include "dcn31/dcn31_hpo_dp_stream_encoder.h" | ||||
| 57 | #include "dcn31/dcn31_hpo_dp_link_encoder.h" | ||||
| 58 | #include "dcn31/dcn31_apg.h" | ||||
| 59 | #include "dcn31/dcn31_dio_link_encoder.h" | ||||
| 60 | #include "dcn31/dcn31_vpg.h" | ||||
| 61 | #include "dcn31/dcn31_afmt.h" | ||||
| 62 | #include "dce/dce_clock_source.h" | ||||
| 63 | #include "dce/dce_audio.h" | ||||
| 64 | #include "dce/dce_hwseq.h" | ||||
| 65 | #include "clk_mgr.h" | ||||
| 66 | #include "virtual/virtual_stream_encoder.h" | ||||
| 67 | #include "dce110/dce110_resource.h" | ||||
| 68 | #include "dml/display_mode_vba.h" | ||||
| 69 | #include "dml/dcn31/dcn31_fpu.h" | ||||
| 70 | #include "dcn31/dcn31_dccg.h" | ||||
| 71 | #include "dcn10/dcn10_resource.h" | ||||
| 72 | #include "dcn31/dcn31_panel_cntl.h" | ||||
| 73 | |||||
| 74 | #include "dcn30/dcn30_dwb.h" | ||||
| 75 | #include "dcn30/dcn30_mmhubbub.h" | ||||
| 76 | |||||
| 77 | #include "dcn/dcn_3_1_5_offset.h" | ||||
| 78 | #include "dcn/dcn_3_1_5_sh_mask.h" | ||||
| 79 | #include "dpcs/dpcs_4_2_2_offset.h" | ||||
| 80 | #include "dpcs/dpcs_4_2_2_sh_mask.h" | ||||
| 81 | |||||
| 82 | #define NBIO_BASE__INST0_SEG00x00000000 0x00000000 | ||||
| 83 | #define NBIO_BASE__INST0_SEG10x00000014 0x00000014 | ||||
| 84 | #define NBIO_BASE__INST0_SEG20x00000D20 0x00000D20 | ||||
| 85 | #define NBIO_BASE__INST0_SEG30x00010400 0x00010400 | ||||
| 86 | #define NBIO_BASE__INST0_SEG40x0241B000 0x0241B000 | ||||
| 87 | #define NBIO_BASE__INST0_SEG50x04040000 0x04040000 | ||||
| 88 | |||||
| 89 | #define DPCS_BASE__INST0_SEG00x00000012 0x00000012 | ||||
| 90 | #define DPCS_BASE__INST0_SEG10x000000C0 0x000000C0 | ||||
| 91 | #define DPCS_BASE__INST0_SEG20x000034C0 0x000034C0 | ||||
| 92 | #define DPCS_BASE__INST0_SEG30x00009000 0x00009000 | ||||
| 93 | #define DPCS_BASE__INST0_SEG40x02403C00 0x02403C00 | ||||
| 94 | #define DPCS_BASE__INST0_SEG50 0 | ||||
| 95 | |||||
| 96 | #define DCN_BASE__INST0_SEG00x00000012 0x00000012 | ||||
| 97 | #define DCN_BASE__INST0_SEG10x000000C0 0x000000C0 | ||||
| 98 | #define DCN_BASE__INST0_SEG20x000034C0 0x000034C0 | ||||
| 99 | #define DCN_BASE__INST0_SEG30x00009000 0x00009000 | ||||
| 100 | #define DCN_BASE__INST0_SEG40x02403C00 0x02403C00 | ||||
| 101 | #define DCN_BASE__INST0_SEG50 0 | ||||
| 102 | |||||
| 103 | #define regBIF_BX_PF2_RSMU_INDEX0x0000 0x0000 | ||||
| 104 | #define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX1 1 | ||||
| 105 | #define regBIF_BX_PF2_RSMU_DATA0x0001 0x0001 | ||||
| 106 | #define regBIF_BX_PF2_RSMU_DATA_BASE_IDX1 1 | ||||
| 107 | #define regBIF_BX2_BIOS_SCRATCH_60x003e 0x003e | ||||
| 108 | #define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX1 1 | ||||
| 109 | #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT0x0 0x0 | ||||
| 110 | #define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK0xFFFFFFFFL 0xFFFFFFFFL | ||||
| 111 | #define regBIF_BX2_BIOS_SCRATCH_20x003a 0x003a | ||||
| 112 | #define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX1 1 | ||||
| 113 | #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT0x0 0x0 | ||||
| 114 | #define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK0xFFFFFFFFL 0xFFFFFFFFL | ||||
| 115 | #define regBIF_BX2_BIOS_SCRATCH_30x003b 0x003b | ||||
| 116 | #define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX1 1 | ||||
| 117 | #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT0x0 0x0 | ||||
| 118 | #define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK0xFFFFFFFFL 0xFFFFFFFFL | ||||
| 119 | |||||
| 120 | #define regDCHUBBUB_DEBUG_CTRL_00x04d6 0x04d6 | ||||
| 121 | #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX2 2 | ||||
| 122 | #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT0x10 0x10 | ||||
| 123 | #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK0x01FF0000L 0x01FF0000L | ||||
| 124 | |||||
| 125 | #include "reg_helper.h" | ||||
| 126 | #include "dce/dmub_abm.h" | ||||
| 127 | #include "dce/dmub_psr.h" | ||||
| 128 | #include "dce/dce_aux.h" | ||||
| 129 | #include "dce/dce_i2c.h" | ||||
| 130 | |||||
| 131 | #include "dml/dcn30/display_mode_vba_30.h" | ||||
| 132 | #include "vm_helper.h" | ||||
| 133 | #include "dcn20/dcn20_vmid.h" | ||||
| 134 | |||||
| 135 | #include "link_enc_cfg.h" | ||||
| 136 | |||||
| 137 | #define DCN3_15_MAX_DET_SIZE384 384 | ||||
| 138 | #define DCN3_15_CRB_SEGMENT_SIZE_KB64 64 | ||||
| 139 | #define DCN3_15_MAX_DET_SEGS(384 / 64) (DCN3_15_MAX_DET_SIZE384 / DCN3_15_CRB_SEGMENT_SIZE_KB64) | ||||
| 140 | /* Minimum 2 extra segments need to be in compbuf and claimable to guarantee seamless mpo transitions */ | ||||
| 141 | #define MIN_RESERVED_DET_SEGS2 2 | ||||
| 142 | |||||
| 143 | enum dcn31_clk_src_array_id { | ||||
| 144 | DCN31_CLK_SRC_PLL0, | ||||
| 145 | DCN31_CLK_SRC_PLL1, | ||||
| 146 | DCN31_CLK_SRC_PLL2, | ||||
| 147 | DCN31_CLK_SRC_PLL3, | ||||
| 148 | DCN31_CLK_SRC_PLL4, | ||||
| 149 | DCN30_CLK_SRC_TOTAL | ||||
| 150 | }; | ||||
| 151 | |||||
| 152 | /* begin ********************* | ||||
| 153 | * macros to expend register list macro defined in HW object header file | ||||
| 154 | */ | ||||
| 155 | |||||
| 156 | /* DCN */ | ||||
| 157 | /* TODO awful hack. fixup dcn20_dwb.h */ | ||||
| 158 | #undef BASE_INNER | ||||
| 159 | #define BASE_INNER(seg)DCN_BASE__INST0_SEGseg DCN_BASE__INST0_SEG ## seg | ||||
| 160 | |||||
| 161 | #define BASE(seg)DCN_BASE__INST0_SEGseg BASE_INNER(seg)DCN_BASE__INST0_SEGseg | ||||
| 162 | |||||
| 163 | #define SR(reg_name).reg_name = DCN_BASE__INST0_SEGregreg_name_BASE_IDX + regreg_name\ | ||||
| 164 | .reg_name = BASE(reg ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## reg_name ## _BASE_IDX + \ | ||||
| 165 | reg ## reg_name | ||||
| 166 | |||||
| 167 | #define SRI(reg_name, block, id).reg_name = DCN_BASE__INST0_SEGregblockid_reg_name_BASE_IDX + regblockid_reg_name\ | ||||
| 168 | .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | ||||
| 169 | reg ## block ## id ## _ ## reg_name | ||||
| 170 | |||||
| 171 | #define SRI2(reg_name, block, id).reg_name = DCN_BASE__INST0_SEGregreg_name_BASE_IDX + regreg_name\ | ||||
| 172 | .reg_name = BASE(reg ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## reg_name ## _BASE_IDX + \ | ||||
| 173 | reg ## reg_name | ||||
| 174 | |||||
| 175 | #define SRIR(var_name, reg_name, block, id).var_name = DCN_BASE__INST0_SEGregblockid_reg_name_BASE_IDX + regblockid_reg_name\ | ||||
| 176 | .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | ||||
| 177 | reg ## block ## id ## _ ## reg_name | ||||
| 178 | |||||
| 179 | #define SRII(reg_name, block, id).reg_name[id] = DCN_BASE__INST0_SEGregblockid_reg_name_BASE_IDX + regblockid_reg_name\ | ||||
| 180 | .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | ||||
| 181 | reg ## block ## id ## _ ## reg_name | ||||
| 182 | |||||
| 183 | #define SRII_MPC_RMU(reg_name, block, id).RMU_reg_name[id] = DCN_BASE__INST0_SEGregblockid_reg_name_BASE_IDX + regblockid_reg_name\ | ||||
| 184 | .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | ||||
| 185 | reg ## block ## id ## _ ## reg_name | ||||
| 186 | |||||
| 187 | #define SRII_DWB(reg_name, temp_name, block, id).reg_name[id] = DCN_BASE__INST0_SEGregblockid_temp_name_BASE_IDX + regblockid_temp_name\ | ||||
| 188 | .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## block ## id ## _ ## temp_name ## _BASE_IDX + \ | ||||
| 189 | reg ## block ## id ## _ ## temp_name | ||||
| 190 | |||||
| 191 | #define DCCG_SRII(reg_name, block, id).block_reg_name[id] = DCN_BASE__INST0_SEGregblockid_reg_name_BASE_IDX + regblockid_reg_name\ | ||||
| 192 | .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | ||||
| 193 | reg ## block ## id ## _ ## reg_name | ||||
| 194 | |||||
| 195 | #define VUPDATE_SRII(reg_name, block, id).reg_name[id] = DCN_BASE__INST0_SEGregreg_name_blockid_BASE_IDX + regreg_name_blockid\ | ||||
| 196 | .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## reg_name ## _ ## block ## id ## _BASE_IDX + \ | ||||
| 197 | reg ## reg_name ## _ ## block ## id | ||||
| 198 | |||||
| 199 | /* NBIO */ | ||||
| 200 | #define NBIO_BASE_INNER(seg)NBIO_BASE__INST0_SEGseg \ | ||||
| 201 | NBIO_BASE__INST0_SEG ## seg | ||||
| 202 | |||||
| 203 | #define NBIO_BASE(seg)NBIO_BASE__INST0_SEGseg \ | ||||
| 204 | NBIO_BASE_INNER(seg)NBIO_BASE__INST0_SEGseg | ||||
| 205 | |||||
| 206 | #define NBIO_SR(reg_name).reg_name = NBIO_BASE__INST0_SEGregBIF_BX2_reg_name_BASE_IDX + regBIF_BX2_reg_name\ | ||||
| 207 | .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX)NBIO_BASE__INST0_SEGregBIF_BX2_ ## reg_name ## _BASE_IDX + \ | ||||
| 208 | regBIF_BX2_ ## reg_name | ||||
| 209 | |||||
| 210 | static const struct bios_registers bios_regs = { | ||||
| 211 | NBIO_SR(BIOS_SCRATCH_3).BIOS_SCRATCH_3 = 0x00000014 + 0x003b, | ||||
| 212 | NBIO_SR(BIOS_SCRATCH_6).BIOS_SCRATCH_6 = 0x00000014 + 0x003e | ||||
| 213 | }; | ||||
| 214 | |||||
| 215 | #define clk_src_regs(index, pllid)[index] = { .PIXCLK_RESYNC_CNTL = DCN_BASE__INST0_SEGregPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX + regPHYPLLpllid_PIXCLK_RESYNC_CNTL, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .PIXEL_RATE_CNTL [0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008c,}\ | ||||
| 216 | [index] = {\ | ||||
| 217 | CS_COMMON_REG_LIST_DCN3_0(index, pllid).PIXCLK_RESYNC_CNTL = DCN_BASE__INST0_SEGregPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX + regPHYPLLpllid_PIXCLK_RESYNC_CNTL, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .PIXEL_RATE_CNTL [0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008c,\ | ||||
| 218 | } | ||||
| 219 | |||||
| 220 | static const struct dce110_clk_src_regs clk_src_regs[] = { | ||||
| 221 | clk_src_regs(0, A)[0] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0040, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086 , .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c,}, | ||||
| 222 | clk_src_regs(1, B)[1] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0041, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086 , .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c,}, | ||||
| 223 | clk_src_regs(2, C)[2] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0042, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086 , .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c,}, | ||||
| 224 | clk_src_regs(3, D)[3] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0043, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086 , .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c,}, | ||||
| 225 | clk_src_regs(4, E)[4] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x004c, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086 , .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c,} | ||||
| 226 | }; | ||||
| 227 | |||||
| 228 | static const struct dce110_clk_src_shift cs_shift = { | ||||
| 229 | CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT).DP_DTO0_PHASE = 0x0, .DP_DTO0_MODULO = 0x0, .PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x4, .DP_DTO0_ENABLE = 0x4 | ||||
| 230 | }; | ||||
| 231 | |||||
| 232 | static const struct dce110_clk_src_mask cs_mask = { | ||||
| 233 | CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK).DP_DTO0_PHASE = 0xFFFFFFFFL, .DP_DTO0_MODULO = 0xFFFFFFFFL, . PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x00000030L, .DP_DTO0_ENABLE = 0x00000010L | ||||
| 234 | }; | ||||
| 235 | |||||
| 236 | #define abm_regs(id)[id] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG = 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 + 0x00f9, .DC_ABM1_HG_SAMPLE_RATE = DCN_BASE__INST0_SEGregABMid_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX + regABMid_DC_ABM1_HG_SAMPLE_RATE, .DC_ABM1_LS_SAMPLE_RATE = DCN_BASE__INST0_SEGregABMid_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX + regABMid_DC_ABM1_LS_SAMPLE_RATE, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = DCN_BASE__INST0_SEGregABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX + regABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE, .DC_ABM1_HG_MISC_CTRL = DCN_BASE__INST0_SEGregABMid_DC_ABM1_HG_MISC_CTRL_BASE_IDX + regABMid_DC_ABM1_HG_MISC_CTRL, .DC_ABM1_IPCSC_COEFF_SEL = DCN_BASE__INST0_SEGregABMid_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX + regABMid_DC_ABM1_IPCSC_COEFF_SEL, .BL1_PWM_CURRENT_ABM_LEVEL = DCN_BASE__INST0_SEGregABMid_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX + regABMid_BL1_PWM_CURRENT_ABM_LEVEL, .BL1_PWM_TARGET_ABM_LEVEL = DCN_BASE__INST0_SEGregABMid_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX + regABMid_BL1_PWM_TARGET_ABM_LEVEL, .BL1_PWM_USER_LEVEL = DCN_BASE__INST0_SEGregABMid_BL1_PWM_USER_LEVEL_BASE_IDX + regABMid_BL1_PWM_USER_LEVEL, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = DCN_BASE__INST0_SEGregABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX + regABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, .DC_ABM1_HGLS_REG_READ_PROGRESS = DCN_BASE__INST0_SEGregABMid_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX + regABMid_DC_ABM1_HGLS_REG_READ_PROGRESS, .DC_ABM1_ACE_OFFSET_SLOPE_0 = DCN_BASE__INST0_SEGregABMid_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX + regABMid_DC_ABM1_ACE_OFFSET_SLOPE_0, .DC_ABM1_ACE_THRES_12 = DCN_BASE__INST0_SEGregABMid_DC_ABM1_ACE_THRES_12_BASE_IDX + regABMid_DC_ABM1_ACE_THRES_12, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a}\ | ||||
| 237 | [id] = {\ | ||||
| 238 | ABM_DCN302_REG_LIST(id).MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG = 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 + 0x00f9, .DC_ABM1_HG_SAMPLE_RATE = DCN_BASE__INST0_SEGregABMid_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX + regABMid_DC_ABM1_HG_SAMPLE_RATE, .DC_ABM1_LS_SAMPLE_RATE = DCN_BASE__INST0_SEGregABMid_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX + regABMid_DC_ABM1_LS_SAMPLE_RATE, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = DCN_BASE__INST0_SEGregABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX + regABMid_BL1_PWM_BL_UPDATE_SAMPLE_RATE, .DC_ABM1_HG_MISC_CTRL = DCN_BASE__INST0_SEGregABMid_DC_ABM1_HG_MISC_CTRL_BASE_IDX + regABMid_DC_ABM1_HG_MISC_CTRL, .DC_ABM1_IPCSC_COEFF_SEL = DCN_BASE__INST0_SEGregABMid_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX + regABMid_DC_ABM1_IPCSC_COEFF_SEL, .BL1_PWM_CURRENT_ABM_LEVEL = DCN_BASE__INST0_SEGregABMid_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX + regABMid_BL1_PWM_CURRENT_ABM_LEVEL, .BL1_PWM_TARGET_ABM_LEVEL = DCN_BASE__INST0_SEGregABMid_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX + regABMid_BL1_PWM_TARGET_ABM_LEVEL, .BL1_PWM_USER_LEVEL = DCN_BASE__INST0_SEGregABMid_BL1_PWM_USER_LEVEL_BASE_IDX + regABMid_BL1_PWM_USER_LEVEL, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = DCN_BASE__INST0_SEGregABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX + regABMid_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, .DC_ABM1_HGLS_REG_READ_PROGRESS = DCN_BASE__INST0_SEGregABMid_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX + regABMid_DC_ABM1_HGLS_REG_READ_PROGRESS, .DC_ABM1_ACE_OFFSET_SLOPE_0 = DCN_BASE__INST0_SEGregABMid_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX + regABMid_DC_ABM1_ACE_OFFSET_SLOPE_0, .DC_ABM1_ACE_THRES_12 = DCN_BASE__INST0_SEGregABMid_DC_ABM1_ACE_THRES_12_BASE_IDX + regABMid_DC_ABM1_ACE_THRES_12, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a\ | ||||
| 239 | } | ||||
| 240 | |||||
| 241 | static const struct dce_abm_registers abm_regs[] = { | ||||
| 242 | abm_regs(0)[0] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG = 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 + 0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0e97, .DC_ABM1_LS_SAMPLE_RATE = 0x00009000 + 0x0e98, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000 + 0x0e81, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0e8f, .DC_ABM1_IPCSC_COEFF_SEL = 0x00009000 + 0x0e84, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000 + 0x0e7d, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0e7c, . BL1_PWM_USER_LEVEL = 0x00009000 + 0x0e7b, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = 0x00009000 + 0x0e94, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000 + 0x0e8e, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0e85, .DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0e8a, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a}, | ||||
| 243 | abm_regs(1)[1] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG = 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 + 0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0ed8, .DC_ABM1_LS_SAMPLE_RATE = 0x00009000 + 0x0ed9, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000 + 0x0ec2, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0ed0, .DC_ABM1_IPCSC_COEFF_SEL = 0x00009000 + 0x0ec5, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000 + 0x0ebe, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0ebd, . BL1_PWM_USER_LEVEL = 0x00009000 + 0x0ebc, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = 0x00009000 + 0x0ed5, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000 + 0x0ecf, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0ec6, .DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0ecb, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a}, | ||||
| 244 | abm_regs(2)[2] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG = 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 + 0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0f19, .DC_ABM1_LS_SAMPLE_RATE = 0x00009000 + 0x0f1a, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000 + 0x0f03, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0f11, .DC_ABM1_IPCSC_COEFF_SEL = 0x00009000 + 0x0f06, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000 + 0x0eff, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0efe, . BL1_PWM_USER_LEVEL = 0x00009000 + 0x0efd, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = 0x00009000 + 0x0f16, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000 + 0x0f10, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0f07, .DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0f0c, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a}, | ||||
| 245 | abm_regs(3)[3] = { .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG = 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 + 0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x00009000 + 0x0f5a, .DC_ABM1_LS_SAMPLE_RATE = 0x00009000 + 0x0f5b, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x00009000 + 0x0f44, .DC_ABM1_HG_MISC_CTRL = 0x00009000 + 0x0f52, .DC_ABM1_IPCSC_COEFF_SEL = 0x00009000 + 0x0f47, .BL1_PWM_CURRENT_ABM_LEVEL = 0x00009000 + 0x0f40, .BL1_PWM_TARGET_ABM_LEVEL = 0x00009000 + 0x0f3f, . BL1_PWM_USER_LEVEL = 0x00009000 + 0x0f3e, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = 0x00009000 + 0x0f57, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x00009000 + 0x0f51, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x00009000 + 0x0f48, .DC_ABM1_ACE_THRES_12 = 0x00009000 + 0x0f4d, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a}, | ||||
| 246 | }; | ||||
| 247 | |||||
| 248 | static const struct dce_abm_shift abm_shift = { | ||||
| 249 | ABM_MASK_SH_LIST_DCN30(__SHIFT).MASTER_COMM_INTERRUPT = 0x0, .MASTER_COMM_CMD_REG_BYTE0 = 0x0 , .MASTER_COMM_CMD_REG_BYTE1 = 0x8, .MASTER_COMM_CMD_REG_BYTE2 = 0x10, .ABM1_HG_NUM_OF_BINS_SEL = 0x0, .ABM1_HG_VMAX_SEL = 0x8 , .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x10, .ABM1_IPCSC_COEFF_SEL_R = 0x10, .ABM1_IPCSC_COEFF_SEL_G = 0x8, .ABM1_IPCSC_COEFF_SEL_B = 0x0, .BL1_PWM_CURRENT_ABM_LEVEL = 0x0, .BL1_PWM_TARGET_ABM_LEVEL = 0x0, .BL1_PWM_USER_LEVEL = 0x0, .ABM1_LS_MIN_PIXEL_VALUE_THRES = 0x0, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x10, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR = 0x10, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x18, .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR = 0x1f | ||||
| 250 | }; | ||||
| 251 | |||||
| 252 | static const struct dce_abm_mask abm_mask = { | ||||
| 253 | ABM_MASK_SH_LIST_DCN30(_MASK).MASTER_COMM_INTERRUPT = 0x00000001L, .MASTER_COMM_CMD_REG_BYTE0 = 0x000000FFL, .MASTER_COMM_CMD_REG_BYTE1 = 0x0000FF00L, .MASTER_COMM_CMD_REG_BYTE2 = 0x00FF0000L, .ABM1_HG_NUM_OF_BINS_SEL = 0x00000003L, .ABM1_HG_VMAX_SEL = 0x00000100L, .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x00030000L, .ABM1_IPCSC_COEFF_SEL_R = 0x000F0000L, .ABM1_IPCSC_COEFF_SEL_G = 0x00000F00L, .ABM1_IPCSC_COEFF_SEL_B = 0x0000000FL, .BL1_PWM_CURRENT_ABM_LEVEL = 0x0001FFFFL, .BL1_PWM_TARGET_ABM_LEVEL = 0x0001FFFFL, .BL1_PWM_USER_LEVEL = 0x0001FFFFL, .ABM1_LS_MIN_PIXEL_VALUE_THRES = 0x000003FFL, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x03FF0000L, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR = 0x00010000L, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x01000000L , .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR = 0x80000000L | ||||
| 254 | }; | ||||
| 255 | |||||
| 256 | #define audio_regs(id)[id] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = DCN_BASE__INST0_SEGregAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX + regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, .AZALIA_F0_CODEC_ENDPOINT_DATA = DCN_BASE__INST0_SEGregAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX + regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}\ | ||||
| 257 | [id] = {\ | ||||
| 258 | AUD_COMMON_REG_LIST(id).AZALIA_F0_CODEC_ENDPOINT_INDEX = DCN_BASE__INST0_SEGregAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX + regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, .AZALIA_F0_CODEC_ENDPOINT_DATA = DCN_BASE__INST0_SEGregAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX + regAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae\ | ||||
| 259 | } | ||||
| 260 | |||||
| 261 | static const struct dce_audio_registers audio_regs[] = { | ||||
| 262 | audio_regs(0)[0] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0386 , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0387, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | ||||
| 263 | audio_regs(1)[1] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x038c , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x038d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | ||||
| 264 | audio_regs(2)[2] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0392 , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0393, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | ||||
| 265 | audio_regs(3)[3] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0398 , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0399, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | ||||
| 266 | audio_regs(4)[4] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x039e , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x039f, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | ||||
| 267 | audio_regs(5)[5] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x03a4 , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x03a5, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | ||||
| 268 | audio_regs(6)[6] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x03aa , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x03ab, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae} | ||||
| 269 | }; | ||||
| 270 | |||||
| 271 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh , .AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh , .DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh , .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh , .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh , .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh , .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh , .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh , .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh , .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh , .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh\ | ||||
| 272 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh,\ | ||||
| 273 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh).AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh,\ | ||||
| 274 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh).DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh , .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh , .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh , .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh , .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh , .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh , .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh , .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh , .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh | ||||
| 275 | |||||
| 276 | static const struct dce_audio_shift audio_shift = { | ||||
| 277 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT).AZALIA_ENDPOINT_REG_INDEX = 0x0, .AZALIA_ENDPOINT_REG_DATA = 0x0, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x0, .DCCG_AUDIO_DTO_SEL = 0x4, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x14, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = 0x18, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x1c, .DCCG_AUDIO_DTO0_MODULE = 0x0, .DCCG_AUDIO_DTO0_PHASE = 0x0, .DCCG_AUDIO_DTO1_MODULE = 0x0, .DCCG_AUDIO_DTO1_PHASE = 0x0, .AUDIO_RATE_CAPABILITIES = 0x0, .CLKSTOP = 0x1e, .EPSS = 0x1f | ||||
| 278 | }; | ||||
| 279 | |||||
| 280 | static const struct dce_audio_mask audio_mask = { | ||||
| 281 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK).AZALIA_ENDPOINT_REG_INDEX = 0x00003FFFL, .AZALIA_ENDPOINT_REG_DATA = 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x00000007L, .DCCG_AUDIO_DTO_SEL = 0x00000070L, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x00100000L , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = 0x01000000L, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x10000000L, .DCCG_AUDIO_DTO0_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_PHASE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_PHASE = 0xFFFFFFFFL, .AUDIO_RATE_CAPABILITIES = 0x00000FFFL, .CLKSTOP = 0x40000000L, .EPSS = 0x80000000L | ||||
| 282 | }; | ||||
| 283 | |||||
| 284 | #define vpg_regs(id)[id] = { .VPG_GENERIC_STATUS = DCN_BASE__INST0_SEGregVPGid_VPG_GENERIC_STATUS_BASE_IDX + regVPGid_VPG_GENERIC_STATUS, .VPG_GENERIC_PACKET_ACCESS_CTRL = DCN_BASE__INST0_SEGregVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX + regVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL, .VPG_GENERIC_PACKET_DATA = DCN_BASE__INST0_SEGregVPGid_VPG_GENERIC_PACKET_DATA_BASE_IDX + regVPGid_VPG_GENERIC_PACKET_DATA, .VPG_GSP_FRAME_UPDATE_CTRL = DCN_BASE__INST0_SEGregVPGid_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX + regVPGid_VPG_GSP_FRAME_UPDATE_CTRL, .VPG_GSP_IMMEDIATE_UPDATE_CTRL = DCN_BASE__INST0_SEGregVPGid_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX + regVPGid_VPG_GSP_IMMEDIATE_UPDATE_CTRL, .VPG_MEM_PWR = DCN_BASE__INST0_SEGregVPGid_VPG_MEM_PWR_BASE_IDX + regVPGid_VPG_MEM_PWR}\ | ||||
| 285 | [id] = {\ | ||||
| 286 | VPG_DCN31_REG_LIST(id).VPG_GENERIC_STATUS = DCN_BASE__INST0_SEGregVPGid_VPG_GENERIC_STATUS_BASE_IDX + regVPGid_VPG_GENERIC_STATUS, .VPG_GENERIC_PACKET_ACCESS_CTRL = DCN_BASE__INST0_SEGregVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX + regVPGid_VPG_GENERIC_PACKET_ACCESS_CTRL, .VPG_GENERIC_PACKET_DATA = DCN_BASE__INST0_SEGregVPGid_VPG_GENERIC_PACKET_DATA_BASE_IDX + regVPGid_VPG_GENERIC_PACKET_DATA, .VPG_GSP_FRAME_UPDATE_CTRL = DCN_BASE__INST0_SEGregVPGid_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX + regVPGid_VPG_GSP_FRAME_UPDATE_CTRL, .VPG_GSP_IMMEDIATE_UPDATE_CTRL = DCN_BASE__INST0_SEGregVPGid_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX + regVPGid_VPG_GSP_IMMEDIATE_UPDATE_CTRL, .VPG_MEM_PWR = DCN_BASE__INST0_SEGregVPGid_VPG_MEM_PWR_BASE_IDX + regVPGid_VPG_MEM_PWR\ | ||||
| 287 | } | ||||
| 288 | |||||
| 289 | static const struct dcn31_vpg_registers vpg_regs[] = { | ||||
| 290 | vpg_regs(0)[0] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x206c, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x2068, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x2069, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x206a, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x206b, .VPG_MEM_PWR = 0x000034C0 + 0x206d}, | ||||
| 291 | vpg_regs(1)[1] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x216c, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x2168, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x2169, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x216a, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x216b, .VPG_MEM_PWR = 0x000034C0 + 0x216d}, | ||||
| 292 | vpg_regs(2)[2] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x226c, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x2268, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x2269, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x226a, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x226b, .VPG_MEM_PWR = 0x000034C0 + 0x226d}, | ||||
| 293 | vpg_regs(3)[3] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x236c, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x2368, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x2369, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x236a, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x236b, .VPG_MEM_PWR = 0x000034C0 + 0x236d}, | ||||
| 294 | vpg_regs(4)[4] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x246c, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x2468, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x2469, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x246a, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x246b, .VPG_MEM_PWR = 0x000034C0 + 0x246d}, | ||||
| 295 | vpg_regs(5)[5] = { .VPG_GENERIC_STATUS = 0x00009000 + 0x0935, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x00009000 + 0x0931, .VPG_GENERIC_PACKET_DATA = 0x00009000 + 0x0932, .VPG_GSP_FRAME_UPDATE_CTRL = 0x00009000 + 0x0933, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x00009000 + 0x0934, .VPG_MEM_PWR = 0x00009000 + 0x0936}, | ||||
| 296 | vpg_regs(6)[6] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x3655, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x3651, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x3652, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x3653, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x3654, .VPG_MEM_PWR = 0x000034C0 + 0x3656}, | ||||
| 297 | vpg_regs(7)[7] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x3729, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x3725, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x3726, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x3727, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x3728, .VPG_MEM_PWR = 0x000034C0 + 0x372a}, | ||||
| 298 | vpg_regs(8)[8] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x37fd, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x37f9, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x37fa, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x37fb, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x37fc, .VPG_MEM_PWR = 0x000034C0 + 0x37fe}, | ||||
| 299 | vpg_regs(9)[9] = { .VPG_GENERIC_STATUS = 0x000034C0 + 0x38d1, .VPG_GENERIC_PACKET_ACCESS_CTRL = 0x000034C0 + 0x38cd, .VPG_GENERIC_PACKET_DATA = 0x000034C0 + 0x38ce, .VPG_GSP_FRAME_UPDATE_CTRL = 0x000034C0 + 0x38cf, . VPG_GSP_IMMEDIATE_UPDATE_CTRL = 0x000034C0 + 0x38d0, .VPG_MEM_PWR = 0x000034C0 + 0x38d2}, | ||||
| 300 | }; | ||||
| 301 | |||||
| 302 | static const struct dcn31_vpg_shift vpg_shift = { | ||||
| 303 | DCN31_VPG_MASK_SH_LIST(__SHIFT).VPG_GENERIC_CONFLICT_OCCURED = 0x1, .VPG_GENERIC_CONFLICT_CLR = 0x4, .VPG_GENERIC_DATA_INDEX = 0x0, .VPG_GENERIC_DATA_BYTE0 = 0x0, .VPG_GENERIC_DATA_BYTE1 = 0x8, .VPG_GENERIC_DATA_BYTE2 = 0x10, .VPG_GENERIC_DATA_BYTE3 = 0x18, .VPG_GENERIC0_FRAME_UPDATE = 0x0, .VPG_GENERIC1_FRAME_UPDATE = 0x1, .VPG_GENERIC2_FRAME_UPDATE = 0x2, .VPG_GENERIC3_FRAME_UPDATE = 0x3, .VPG_GENERIC4_FRAME_UPDATE = 0x4, .VPG_GENERIC5_FRAME_UPDATE = 0x5, .VPG_GENERIC6_FRAME_UPDATE = 0x6, .VPG_GENERIC7_FRAME_UPDATE = 0x7, .VPG_GENERIC8_FRAME_UPDATE = 0x8, .VPG_GENERIC9_FRAME_UPDATE = 0x9, .VPG_GENERIC10_FRAME_UPDATE = 0xa, .VPG_GENERIC11_FRAME_UPDATE = 0xb, .VPG_GENERIC12_FRAME_UPDATE = 0xc, .VPG_GENERIC13_FRAME_UPDATE = 0xd, .VPG_GENERIC14_FRAME_UPDATE = 0xe, .VPG_GENERIC0_IMMEDIATE_UPDATE = 0x0, .VPG_GENERIC1_IMMEDIATE_UPDATE = 0x1, .VPG_GENERIC2_IMMEDIATE_UPDATE = 0x2, .VPG_GENERIC3_IMMEDIATE_UPDATE = 0x3, .VPG_GENERIC4_IMMEDIATE_UPDATE = 0x4, .VPG_GENERIC5_IMMEDIATE_UPDATE = 0x5, .VPG_GENERIC6_IMMEDIATE_UPDATE = 0x6, .VPG_GENERIC7_IMMEDIATE_UPDATE = 0x7, .VPG_GENERIC8_IMMEDIATE_UPDATE = 0x8, .VPG_GENERIC9_IMMEDIATE_UPDATE = 0x9, .VPG_GENERIC10_IMMEDIATE_UPDATE = 0xa, .VPG_GENERIC11_IMMEDIATE_UPDATE = 0xb, .VPG_GENERIC12_IMMEDIATE_UPDATE = 0xc, .VPG_GENERIC13_IMMEDIATE_UPDATE = 0xd, .VPG_GENERIC14_IMMEDIATE_UPDATE = 0xe, .VPG_GSP_MEM_LIGHT_SLEEP_DIS = 0x0, .VPG_GSP_LIGHT_SLEEP_FORCE = 0x4, .VPG_GSP_MEM_PWR_STATE = 0x8 | ||||
| 304 | }; | ||||
| 305 | |||||
| 306 | static const struct dcn31_vpg_mask vpg_mask = { | ||||
| 307 | DCN31_VPG_MASK_SH_LIST(_MASK).VPG_GENERIC_CONFLICT_OCCURED = 0x00000002L, .VPG_GENERIC_CONFLICT_CLR = 0x00000010L, .VPG_GENERIC_DATA_INDEX = 0x000000FFL, .VPG_GENERIC_DATA_BYTE0 = 0x000000FFL, .VPG_GENERIC_DATA_BYTE1 = 0x0000FF00L, .VPG_GENERIC_DATA_BYTE2 = 0x00FF0000L, .VPG_GENERIC_DATA_BYTE3 = 0xFF000000L, .VPG_GENERIC0_FRAME_UPDATE = 0x00000001L, .VPG_GENERIC1_FRAME_UPDATE = 0x00000002L, .VPG_GENERIC2_FRAME_UPDATE = 0x00000004L, .VPG_GENERIC3_FRAME_UPDATE = 0x00000008L, .VPG_GENERIC4_FRAME_UPDATE = 0x00000010L, .VPG_GENERIC5_FRAME_UPDATE = 0x00000020L, .VPG_GENERIC6_FRAME_UPDATE = 0x00000040L, .VPG_GENERIC7_FRAME_UPDATE = 0x00000080L, .VPG_GENERIC8_FRAME_UPDATE = 0x00000100L, .VPG_GENERIC9_FRAME_UPDATE = 0x00000200L, .VPG_GENERIC10_FRAME_UPDATE = 0x00000400L, .VPG_GENERIC11_FRAME_UPDATE = 0x00000800L, .VPG_GENERIC12_FRAME_UPDATE = 0x00001000L, .VPG_GENERIC13_FRAME_UPDATE = 0x00002000L, .VPG_GENERIC14_FRAME_UPDATE = 0x00004000L, .VPG_GENERIC0_IMMEDIATE_UPDATE = 0x00000001L, .VPG_GENERIC1_IMMEDIATE_UPDATE = 0x00000002L, .VPG_GENERIC2_IMMEDIATE_UPDATE = 0x00000004L, .VPG_GENERIC3_IMMEDIATE_UPDATE = 0x00000008L, .VPG_GENERIC4_IMMEDIATE_UPDATE = 0x00000010L, .VPG_GENERIC5_IMMEDIATE_UPDATE = 0x00000020L, .VPG_GENERIC6_IMMEDIATE_UPDATE = 0x00000040L, .VPG_GENERIC7_IMMEDIATE_UPDATE = 0x00000080L, .VPG_GENERIC8_IMMEDIATE_UPDATE = 0x00000100L, .VPG_GENERIC9_IMMEDIATE_UPDATE = 0x00000200L, .VPG_GENERIC10_IMMEDIATE_UPDATE = 0x00000400L, .VPG_GENERIC11_IMMEDIATE_UPDATE = 0x00000800L, .VPG_GENERIC12_IMMEDIATE_UPDATE = 0x00001000L , .VPG_GENERIC13_IMMEDIATE_UPDATE = 0x00002000L, .VPG_GENERIC14_IMMEDIATE_UPDATE = 0x00004000L, .VPG_GSP_MEM_LIGHT_SLEEP_DIS = 0x00000001L, . VPG_GSP_LIGHT_SLEEP_FORCE = 0x00000010L, .VPG_GSP_MEM_PWR_STATE = 0x00000100L | ||||
| 308 | }; | ||||
| 309 | |||||
| 310 | #define afmt_regs(id)[id] = { .AFMT_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGregAFMTid_AFMT_INFOFRAME_CONTROL0_BASE_IDX + regAFMTid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGregAFMTid_AFMT_VBI_PACKET_CONTROL_BASE_IDX + regAFMTid_AFMT_VBI_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL = DCN_BASE__INST0_SEGregAFMTid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX + regAFMTid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2 = DCN_BASE__INST0_SEGregAFMTid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX + regAFMTid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL = DCN_BASE__INST0_SEGregAFMTid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX + regAFMTid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = DCN_BASE__INST0_SEGregAFMTid_AFMT_60958_0_BASE_IDX + regAFMTid_AFMT_60958_0, .AFMT_60958_1 = DCN_BASE__INST0_SEGregAFMTid_AFMT_60958_1_BASE_IDX + regAFMTid_AFMT_60958_1, .AFMT_60958_2 = DCN_BASE__INST0_SEGregAFMTid_AFMT_60958_2_BASE_IDX + regAFMTid_AFMT_60958_2, .AFMT_MEM_PWR = DCN_BASE__INST0_SEGregAFMTid_AFMT_MEM_PWR_BASE_IDX + regAFMTid_AFMT_MEM_PWR}\ | ||||
| 311 | [id] = {\ | ||||
| 312 | AFMT_DCN31_REG_LIST(id).AFMT_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGregAFMTid_AFMT_INFOFRAME_CONTROL0_BASE_IDX + regAFMTid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGregAFMTid_AFMT_VBI_PACKET_CONTROL_BASE_IDX + regAFMTid_AFMT_VBI_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL = DCN_BASE__INST0_SEGregAFMTid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX + regAFMTid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2 = DCN_BASE__INST0_SEGregAFMTid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX + regAFMTid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL = DCN_BASE__INST0_SEGregAFMTid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX + regAFMTid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = DCN_BASE__INST0_SEGregAFMTid_AFMT_60958_0_BASE_IDX + regAFMTid_AFMT_60958_0, .AFMT_60958_1 = DCN_BASE__INST0_SEGregAFMTid_AFMT_60958_1_BASE_IDX + regAFMTid_AFMT_60958_1, .AFMT_60958_2 = DCN_BASE__INST0_SEGregAFMTid_AFMT_60958_2_BASE_IDX + regAFMTid_AFMT_60958_2, .AFMT_MEM_PWR = DCN_BASE__INST0_SEGregAFMTid_AFMT_MEM_PWR_BASE_IDX + regAFMTid_AFMT_MEM_PWR\ | ||||
| 313 | } | ||||
| 314 | |||||
| 315 | static const struct dcn31_afmt_registers afmt_regs[] = { | ||||
| 316 | afmt_regs(0)[0] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2083, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x2074, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2082, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2075, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2085, .AFMT_60958_0 = 0x000034C0 + 0x2078, .AFMT_60958_1 = 0x000034C0 + 0x2079, . AFMT_60958_2 = 0x000034C0 + 0x207f, .AFMT_MEM_PWR = 0x000034C0 + 0x2087}, | ||||
| 317 | afmt_regs(1)[1] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2183, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x2174, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2182, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2175, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2185, .AFMT_60958_0 = 0x000034C0 + 0x2178, .AFMT_60958_1 = 0x000034C0 + 0x2179, . AFMT_60958_2 = 0x000034C0 + 0x217f, .AFMT_MEM_PWR = 0x000034C0 + 0x2187}, | ||||
| 318 | afmt_regs(2)[2] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2283, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x2274, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2282, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2275, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2285, .AFMT_60958_0 = 0x000034C0 + 0x2278, .AFMT_60958_1 = 0x000034C0 + 0x2279, . AFMT_60958_2 = 0x000034C0 + 0x227f, .AFMT_MEM_PWR = 0x000034C0 + 0x2287}, | ||||
| 319 | afmt_regs(3)[3] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2383, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x2374, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2382, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2375, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2385, .AFMT_60958_0 = 0x000034C0 + 0x2378, .AFMT_60958_1 = 0x000034C0 + 0x2379, . AFMT_60958_2 = 0x000034C0 + 0x237f, .AFMT_MEM_PWR = 0x000034C0 + 0x2387}, | ||||
| 320 | afmt_regs(4)[4] = { .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2483, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x2474, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2482, .AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x2475, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x2485, .AFMT_60958_0 = 0x000034C0 + 0x2478, .AFMT_60958_1 = 0x000034C0 + 0x2479, . AFMT_60958_2 = 0x000034C0 + 0x247f, .AFMT_MEM_PWR = 0x000034C0 + 0x2487}, | ||||
| 321 | afmt_regs(5)[5] = { .AFMT_INFOFRAME_CONTROL0 = 0x00009000 + 0x092b, .AFMT_VBI_PACKET_CONTROL = 0x00009000 + 0x091c, .AFMT_AUDIO_PACKET_CONTROL = 0x00009000 + 0x092a, .AFMT_AUDIO_PACKET_CONTROL2 = 0x00009000 + 0x091d, .AFMT_AUDIO_SRC_CONTROL = 0x00009000 + 0x092d, .AFMT_60958_0 = 0x00009000 + 0x0920, .AFMT_60958_1 = 0x00009000 + 0x0921, . AFMT_60958_2 = 0x00009000 + 0x0927, .AFMT_MEM_PWR = 0x00009000 + 0x092f} | ||||
| 322 | }; | ||||
| 323 | |||||
| 324 | static const struct dcn31_afmt_shift afmt_shift = { | ||||
| 325 | DCN31_AFMT_MASK_SH_LIST(__SHIFT).AFMT_AUDIO_INFO_UPDATE = 0x7, .AFMT_AUDIO_SRC_SELECT = 0x0, . AFMT_AUDIO_CHANNEL_ENABLE = 0x8, .AFMT_60958_CS_UPDATE = 0x1a , .AFMT_AUDIO_LAYOUT_OVRD = 0x0, .AFMT_60958_OSF_OVRD = 0x1c, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0x14, .AFMT_60958_CS_CLOCK_ACCURACY = 0x1c, .AFMT_60958_CS_CHANNEL_NUMBER_R = 0x14, .AFMT_60958_CS_CHANNEL_NUMBER_2 = 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x4, .AFMT_60958_CS_CHANNEL_NUMBER_4 = 0x8, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0xc, .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x10, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x14, .AFMT_AUDIO_SAMPLE_SEND = 0x0, .AFMT_MEM_PWR_FORCE = 0x4, .AFMT_MEM_PWR_DIS = 0x0, . AFMT_MEM_PWR_STATE = 0x8 | ||||
| 326 | }; | ||||
| 327 | |||||
| 328 | static const struct dcn31_afmt_mask afmt_mask = { | ||||
| 329 | DCN31_AFMT_MASK_SH_LIST(_MASK).AFMT_AUDIO_INFO_UPDATE = 0x00000080L, .AFMT_AUDIO_SRC_SELECT = 0x00000007L, .AFMT_AUDIO_CHANNEL_ENABLE = 0x0000FF00L, .AFMT_60958_CS_UPDATE = 0x04000000L, .AFMT_AUDIO_LAYOUT_OVRD = 0x00000001L, .AFMT_60958_OSF_OVRD = 0x10000000L, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0x00F00000L , .AFMT_60958_CS_CLOCK_ACCURACY = 0x30000000L, .AFMT_60958_CS_CHANNEL_NUMBER_R = 0x00F00000L, .AFMT_60958_CS_CHANNEL_NUMBER_2 = 0x0000000FL , .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x000000F0L, .AFMT_60958_CS_CHANNEL_NUMBER_4 = 0x00000F00L, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0x0000F000L , .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x000F0000L, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x00F00000L, .AFMT_AUDIO_SAMPLE_SEND = 0x00000001L, .AFMT_MEM_PWR_FORCE = 0x00000030L, .AFMT_MEM_PWR_DIS = 0x00000001L, .AFMT_MEM_PWR_STATE = 0x00000300L | ||||
| 330 | }; | ||||
| 331 | |||||
| 332 | #define apg_regs(id)[id] = { .APG_CONTROL = DCN_BASE__INST0_SEGregAPGid_APG_CONTROL_BASE_IDX + regAPGid_APG_CONTROL, .APG_CONTROL2 = DCN_BASE__INST0_SEGregAPGid_APG_CONTROL2_BASE_IDX + regAPGid_APG_CONTROL2, .APG_MEM_PWR = DCN_BASE__INST0_SEGregAPGid_APG_MEM_PWR_BASE_IDX + regAPGid_APG_MEM_PWR, .APG_DBG_GEN_CONTROL = DCN_BASE__INST0_SEGregAPGid_APG_DBG_GEN_CONTROL_BASE_IDX + regAPGid_APG_DBG_GEN_CONTROL}\ | ||||
| 333 | [id] = {\ | ||||
| 334 | APG_DCN31_REG_LIST(id).APG_CONTROL = DCN_BASE__INST0_SEGregAPGid_APG_CONTROL_BASE_IDX + regAPGid_APG_CONTROL, .APG_CONTROL2 = DCN_BASE__INST0_SEGregAPGid_APG_CONTROL2_BASE_IDX + regAPGid_APG_CONTROL2, .APG_MEM_PWR = DCN_BASE__INST0_SEGregAPGid_APG_MEM_PWR_BASE_IDX + regAPGid_APG_MEM_PWR, .APG_DBG_GEN_CONTROL = DCN_BASE__INST0_SEGregAPGid_APG_DBG_GEN_CONTROL_BASE_IDX + regAPGid_APG_DBG_GEN_CONTROL\ | ||||
| 335 | } | ||||
| 336 | |||||
| 337 | static const struct dcn31_apg_registers apg_regs[] = { | ||||
| 338 | apg_regs(0)[0] = { .APG_CONTROL = 0x000034C0 + 0x3630, .APG_CONTROL2 = 0x000034C0 + 0x3631, .APG_MEM_PWR = 0x000034C0 + 0x3644, .APG_DBG_GEN_CONTROL = 0x000034C0 + 0x3632}, | ||||
| 339 | apg_regs(1)[1] = { .APG_CONTROL = 0x000034C0 + 0x3704, .APG_CONTROL2 = 0x000034C0 + 0x3705, .APG_MEM_PWR = 0x000034C0 + 0x3718, .APG_DBG_GEN_CONTROL = 0x000034C0 + 0x3706}, | ||||
| 340 | apg_regs(2)[2] = { .APG_CONTROL = 0x000034C0 + 0x37d8, .APG_CONTROL2 = 0x000034C0 + 0x37d9, .APG_MEM_PWR = 0x000034C0 + 0x37ec, .APG_DBG_GEN_CONTROL = 0x000034C0 + 0x37da}, | ||||
| 341 | apg_regs(3)[3] = { .APG_CONTROL = 0x000034C0 + 0x38ac, .APG_CONTROL2 = 0x000034C0 + 0x38ad, .APG_MEM_PWR = 0x000034C0 + 0x38c0, .APG_DBG_GEN_CONTROL = 0x000034C0 + 0x38ae} | ||||
| 342 | }; | ||||
| 343 | |||||
| 344 | static const struct dcn31_apg_shift apg_shift = { | ||||
| 345 | DCN31_APG_MASK_SH_LIST(__SHIFT).APG_RESET = 0x1, .APG_RESET_DONE = 0x2, .APG_ENABLE = 0x0, . APG_DP_AUDIO_STREAM_ID = 0x8, .APG_DBG_AUDIO_CHANNEL_ENABLE = 0x8, .APG_MEM_PWR_FORCE = 0x4 | ||||
| 346 | }; | ||||
| 347 | |||||
| 348 | static const struct dcn31_apg_mask apg_mask = { | ||||
| 349 | DCN31_APG_MASK_SH_LIST(_MASK).APG_RESET = 0x00000002L, .APG_RESET_DONE = 0x00000004L, .APG_ENABLE = 0x00000001L, .APG_DP_AUDIO_STREAM_ID = 0x0000FF00L, .APG_DBG_AUDIO_CHANNEL_ENABLE = 0x0000FF00L, .APG_MEM_PWR_FORCE = 0x00000030L | ||||
| 350 | }; | ||||
| 351 | |||||
| 352 | #define stream_enc_regs(id)[id] = { .AFMT_CNTL = DCN_BASE__INST0_SEGregDIGid_AFMT_CNTL_BASE_IDX + regDIGid_AFMT_CNTL, .DIG_FE_CNTL = DCN_BASE__INST0_SEGregDIGid_DIG_FE_CNTL_BASE_IDX + regDIGid_DIG_FE_CNTL, .HDMI_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_CONTROL_BASE_IDX + regDIGid_HDMI_CONTROL, .HDMI_DB_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_DB_CONTROL_BASE_IDX + regDIGid_HDMI_DB_CONTROL, .HDMI_GC = DCN_BASE__INST0_SEGregDIGid_HDMI_GC_BASE_IDX + regDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_GENERIC_PACKET_CONTROL2 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL2, .HDMI_GENERIC_PACKET_CONTROL3 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL3, .HDMI_GENERIC_PACKET_CONTROL4 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL4, .HDMI_GENERIC_PACKET_CONTROL5 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL5, .HDMI_GENERIC_PACKET_CONTROL6 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL6, .HDMI_GENERIC_PACKET_CONTROL7 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL7, .HDMI_GENERIC_PACKET_CONTROL8 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL8, .HDMI_GENERIC_PACKET_CONTROL9 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL9, .HDMI_GENERIC_PACKET_CONTROL10 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL10, .HDMI_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGregDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX + regDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 = DCN_BASE__INST0_SEGregDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX + regDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_32_0_BASE_IDX + regDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_32_1_BASE_IDX + regDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_44_0_BASE_IDX + regDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_44_1_BASE_IDX + regDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_48_0_BASE_IDX + regDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_48_1_BASE_IDX + regDIGid_HDMI_ACR_48_1, .DP_DB_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DB_CNTL_BASE_IDX + regDPid_DP_DB_CNTL, .DP_MSA_MISC = DCN_BASE__INST0_SEGregDPid_DP_MSA_MISC_BASE_IDX + regDPid_DP_MSA_MISC, .DP_MSA_VBID_MISC = DCN_BASE__INST0_SEGregDPid_DP_MSA_VBID_MISC_BASE_IDX + regDPid_DP_MSA_VBID_MISC, .DP_MSA_COLORIMETRY = DCN_BASE__INST0_SEGregDPid_DP_MSA_COLORIMETRY_BASE_IDX + regDPid_DP_MSA_COLORIMETRY, .DP_MSA_TIMING_PARAM1 = DCN_BASE__INST0_SEGregDPid_DP_MSA_TIMING_PARAM1_BASE_IDX + regDPid_DP_MSA_TIMING_PARAM1, .DP_MSA_TIMING_PARAM2 = DCN_BASE__INST0_SEGregDPid_DP_MSA_TIMING_PARAM2_BASE_IDX + regDPid_DP_MSA_TIMING_PARAM2, .DP_MSA_TIMING_PARAM3 = DCN_BASE__INST0_SEGregDPid_DP_MSA_TIMING_PARAM3_BASE_IDX + regDPid_DP_MSA_TIMING_PARAM3, .DP_MSA_TIMING_PARAM4 = DCN_BASE__INST0_SEGregDPid_DP_MSA_TIMING_PARAM4_BASE_IDX + regDPid_DP_MSA_TIMING_PARAM4, .DP_MSE_RATE_CNTL = DCN_BASE__INST0_SEGregDPid_DP_MSE_RATE_CNTL_BASE_IDX + regDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE = DCN_BASE__INST0_SEGregDPid_DP_MSE_RATE_UPDATE_BASE_IDX + regDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = DCN_BASE__INST0_SEGregDPid_DP_PIXEL_FORMAT_BASE_IDX + regDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL_BASE_IDX + regDPid_DP_SEC_CNTL, .DP_SEC_CNTL1 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL1_BASE_IDX + regDPid_DP_SEC_CNTL1, .DP_SEC_CNTL2 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL2_BASE_IDX + regDPid_DP_SEC_CNTL2, .DP_SEC_CNTL5 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL5_BASE_IDX + regDPid_DP_SEC_CNTL5, .DP_SEC_CNTL6 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL6_BASE_IDX + regDPid_DP_SEC_CNTL6, .DP_STEER_FIFO = DCN_BASE__INST0_SEGregDPid_DP_STEER_FIFO_BASE_IDX + regDPid_DP_STEER_FIFO, .DP_VID_M = DCN_BASE__INST0_SEGregDPid_DP_VID_M_BASE_IDX + regDPid_DP_VID_M, .DP_VID_N = DCN_BASE__INST0_SEGregDPid_DP_VID_N_BASE_IDX + regDPid_DP_VID_N, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGregDPid_DP_VID_STREAM_CNTL_BASE_IDX + regDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING = DCN_BASE__INST0_SEGregDPid_DP_VID_TIMING_BASE_IDX + regDPid_DP_VID_TIMING, .DP_SEC_AUD_N = DCN_BASE__INST0_SEGregDPid_DP_SEC_AUD_N_BASE_IDX + regDPid_DP_SEC_AUD_N, .DP_SEC_AUD_N_READBACK = DCN_BASE__INST0_SEGregDPid_DP_SEC_AUD_N_READBACK_BASE_IDX + regDPid_DP_SEC_AUD_N_READBACK, .DP_SEC_AUD_M_READBACK = DCN_BASE__INST0_SEGregDPid_DP_SEC_AUD_M_READBACK_BASE_IDX + regDPid_DP_SEC_AUD_M_READBACK, .DP_SEC_TIMESTAMP = DCN_BASE__INST0_SEGregDPid_DP_SEC_TIMESTAMP_BASE_IDX + regDPid_DP_SEC_TIMESTAMP, .DP_DSC_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DSC_CNTL_BASE_IDX + regDPid_DP_DSC_CNTL, .DP_DSC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGregDPid_DP_DSC_BYTES_PER_PIXEL_BASE_IDX + regDPid_DP_DSC_BYTES_PER_PIXEL, .DP_SEC_METADATA_TRANSMISSION = DCN_BASE__INST0_SEGregDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX + regDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_METADATA_PACKET_CONTROL, .DP_SEC_FRAMING4 = DCN_BASE__INST0_SEGregDPid_DP_SEC_FRAMING4_BASE_IDX + regDPid_DP_SEC_FRAMING4, .DP_GSP11_CNTL = DCN_BASE__INST0_SEGregDPid_DP_GSP11_CNTL_BASE_IDX + regDPid_DP_GSP11_CNTL, .DME_CONTROL = DCN_BASE__INST0_SEGregDMEid_DME_CONTROL_BASE_IDX + regDMEid_DME_CONTROL, .DP_SEC_METADATA_TRANSMISSION = DCN_BASE__INST0_SEGregDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX + regDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_METADATA_PACKET_CONTROL, .DIG_FE_CNTL = DCN_BASE__INST0_SEGregDIGid_DIG_FE_CNTL_BASE_IDX + regDIGid_DIG_FE_CNTL, .DIG_FIFO_STATUS = DCN_BASE__INST0_SEGregDIGid_DIG_FIFO_STATUS_BASE_IDX + regDIGid_DIG_FIFO_STATUS, .DIG_CLOCK_PATTERN = DCN_BASE__INST0_SEGregDIGid_DIG_CLOCK_PATTERN_BASE_IDX + regDIGid_DIG_CLOCK_PATTERN}\ | ||||
| 353 | [id] = {\ | ||||
| 354 | SE_DCN3_REG_LIST(id).AFMT_CNTL = DCN_BASE__INST0_SEGregDIGid_AFMT_CNTL_BASE_IDX + regDIGid_AFMT_CNTL, .DIG_FE_CNTL = DCN_BASE__INST0_SEGregDIGid_DIG_FE_CNTL_BASE_IDX + regDIGid_DIG_FE_CNTL, .HDMI_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_CONTROL_BASE_IDX + regDIGid_HDMI_CONTROL, .HDMI_DB_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_DB_CONTROL_BASE_IDX + regDIGid_HDMI_DB_CONTROL, .HDMI_GC = DCN_BASE__INST0_SEGregDIGid_HDMI_GC_BASE_IDX + regDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_GENERIC_PACKET_CONTROL2 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL2, .HDMI_GENERIC_PACKET_CONTROL3 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL3, .HDMI_GENERIC_PACKET_CONTROL4 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL4, .HDMI_GENERIC_PACKET_CONTROL5 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL5, .HDMI_GENERIC_PACKET_CONTROL6 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL6, .HDMI_GENERIC_PACKET_CONTROL7 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL7, .HDMI_GENERIC_PACKET_CONTROL8 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL8, .HDMI_GENERIC_PACKET_CONTROL9 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL9, .HDMI_GENERIC_PACKET_CONTROL10 = DCN_BASE__INST0_SEGregDIGid_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX + regDIGid_HDMI_GENERIC_PACKET_CONTROL10, .HDMI_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGregDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX + regDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 = DCN_BASE__INST0_SEGregDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX + regDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_32_0_BASE_IDX + regDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_32_1_BASE_IDX + regDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_44_0_BASE_IDX + regDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_44_1_BASE_IDX + regDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_48_0_BASE_IDX + regDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = DCN_BASE__INST0_SEGregDIGid_HDMI_ACR_48_1_BASE_IDX + regDIGid_HDMI_ACR_48_1, .DP_DB_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DB_CNTL_BASE_IDX + regDPid_DP_DB_CNTL, .DP_MSA_MISC = DCN_BASE__INST0_SEGregDPid_DP_MSA_MISC_BASE_IDX + regDPid_DP_MSA_MISC, .DP_MSA_VBID_MISC = DCN_BASE__INST0_SEGregDPid_DP_MSA_VBID_MISC_BASE_IDX + regDPid_DP_MSA_VBID_MISC, .DP_MSA_COLORIMETRY = DCN_BASE__INST0_SEGregDPid_DP_MSA_COLORIMETRY_BASE_IDX + regDPid_DP_MSA_COLORIMETRY, .DP_MSA_TIMING_PARAM1 = DCN_BASE__INST0_SEGregDPid_DP_MSA_TIMING_PARAM1_BASE_IDX + regDPid_DP_MSA_TIMING_PARAM1, .DP_MSA_TIMING_PARAM2 = DCN_BASE__INST0_SEGregDPid_DP_MSA_TIMING_PARAM2_BASE_IDX + regDPid_DP_MSA_TIMING_PARAM2, .DP_MSA_TIMING_PARAM3 = DCN_BASE__INST0_SEGregDPid_DP_MSA_TIMING_PARAM3_BASE_IDX + regDPid_DP_MSA_TIMING_PARAM3, .DP_MSA_TIMING_PARAM4 = DCN_BASE__INST0_SEGregDPid_DP_MSA_TIMING_PARAM4_BASE_IDX + regDPid_DP_MSA_TIMING_PARAM4, .DP_MSE_RATE_CNTL = DCN_BASE__INST0_SEGregDPid_DP_MSE_RATE_CNTL_BASE_IDX + regDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE = DCN_BASE__INST0_SEGregDPid_DP_MSE_RATE_UPDATE_BASE_IDX + regDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = DCN_BASE__INST0_SEGregDPid_DP_PIXEL_FORMAT_BASE_IDX + regDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL_BASE_IDX + regDPid_DP_SEC_CNTL, .DP_SEC_CNTL1 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL1_BASE_IDX + regDPid_DP_SEC_CNTL1, .DP_SEC_CNTL2 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL2_BASE_IDX + regDPid_DP_SEC_CNTL2, .DP_SEC_CNTL5 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL5_BASE_IDX + regDPid_DP_SEC_CNTL5, .DP_SEC_CNTL6 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL6_BASE_IDX + regDPid_DP_SEC_CNTL6, .DP_STEER_FIFO = DCN_BASE__INST0_SEGregDPid_DP_STEER_FIFO_BASE_IDX + regDPid_DP_STEER_FIFO, .DP_VID_M = DCN_BASE__INST0_SEGregDPid_DP_VID_M_BASE_IDX + regDPid_DP_VID_M, .DP_VID_N = DCN_BASE__INST0_SEGregDPid_DP_VID_N_BASE_IDX + regDPid_DP_VID_N, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGregDPid_DP_VID_STREAM_CNTL_BASE_IDX + regDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING = DCN_BASE__INST0_SEGregDPid_DP_VID_TIMING_BASE_IDX + regDPid_DP_VID_TIMING, .DP_SEC_AUD_N = DCN_BASE__INST0_SEGregDPid_DP_SEC_AUD_N_BASE_IDX + regDPid_DP_SEC_AUD_N, .DP_SEC_AUD_N_READBACK = DCN_BASE__INST0_SEGregDPid_DP_SEC_AUD_N_READBACK_BASE_IDX + regDPid_DP_SEC_AUD_N_READBACK, .DP_SEC_AUD_M_READBACK = DCN_BASE__INST0_SEGregDPid_DP_SEC_AUD_M_READBACK_BASE_IDX + regDPid_DP_SEC_AUD_M_READBACK, .DP_SEC_TIMESTAMP = DCN_BASE__INST0_SEGregDPid_DP_SEC_TIMESTAMP_BASE_IDX + regDPid_DP_SEC_TIMESTAMP, .DP_DSC_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DSC_CNTL_BASE_IDX + regDPid_DP_DSC_CNTL, .DP_DSC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGregDPid_DP_DSC_BYTES_PER_PIXEL_BASE_IDX + regDPid_DP_DSC_BYTES_PER_PIXEL, .DP_SEC_METADATA_TRANSMISSION = DCN_BASE__INST0_SEGregDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX + regDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_METADATA_PACKET_CONTROL, .DP_SEC_FRAMING4 = DCN_BASE__INST0_SEGregDPid_DP_SEC_FRAMING4_BASE_IDX + regDPid_DP_SEC_FRAMING4, .DP_GSP11_CNTL = DCN_BASE__INST0_SEGregDPid_DP_GSP11_CNTL_BASE_IDX + regDPid_DP_GSP11_CNTL, .DME_CONTROL = DCN_BASE__INST0_SEGregDMEid_DME_CONTROL_BASE_IDX + regDMEid_DME_CONTROL, .DP_SEC_METADATA_TRANSMISSION = DCN_BASE__INST0_SEGregDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX + regDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL = DCN_BASE__INST0_SEGregDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX + regDIGid_HDMI_METADATA_PACKET_CONTROL, .DIG_FE_CNTL = DCN_BASE__INST0_SEGregDIGid_DIG_FE_CNTL_BASE_IDX + regDIGid_DIG_FE_CNTL, .DIG_FIFO_STATUS = DCN_BASE__INST0_SEGregDIGid_DIG_FIFO_STATUS_BASE_IDX + regDIGid_DIG_FIFO_STATUS, .DIG_CLOCK_PATTERN = DCN_BASE__INST0_SEGregDIGid_DIG_CLOCK_PATTERN_BASE_IDX + regDIGid_DIG_CLOCK_PATTERN\ | ||||
| 355 | } | ||||
| 356 | |||||
| 357 | static const struct dcn10_stream_enc_registers stream_enc_regs[] = { | ||||
| 358 | stream_enc_regs(0)[0] = { .AFMT_CNTL = 0x000034C0 + 0x20af, .DIG_FE_CNTL = 0x000034C0 + 0x208b, .HDMI_CONTROL = 0x000034C0 + 0x2093, .HDMI_DB_CONTROL = 0x000034C0 + 0x20a6, .HDMI_GC = 0x000034C0 + 0x209d, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x209a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x209e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x209f , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x20a0, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x20a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x209c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x209b , .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x20a2, .HDMI_GENERIC_PACKET_CONTROL8 = 0x000034C0 + 0x20a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0 + 0x20a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x20a5 , .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2098, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2099, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2097, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2095, . HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2096, .HDMI_ACR_32_0 = 0x000034C0 + 0x20a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x20a8, .HDMI_ACR_44_0 = 0x000034C0 + 0x20a9, .HDMI_ACR_44_1 = 0x000034C0 + 0x20aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x20ab, .HDMI_ACR_48_1 = 0x000034C0 + 0x20ac, .DP_DB_CNTL = 0x000034C0 + 0x2159, .DP_MSA_MISC = 0x000034C0 + 0x210e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x215a , .DP_MSA_COLORIMETRY = 0x000034C0 + 0x210a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x214c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x214d , .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x214e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x214f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2137 , .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2139, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2109, .DP_SEC_CNTL = 0x000034C0 + 0x212b, . DP_SEC_CNTL1 = 0x000034C0 + 0x212c, .DP_SEC_CNTL2 = 0x000034C0 + 0x2153, .DP_SEC_CNTL5 = 0x000034C0 + 0x2156, .DP_SEC_CNTL6 = 0x000034C0 + 0x2157, .DP_STEER_FIFO = 0x000034C0 + 0x210d, .DP_VID_M = 0x000034C0 + 0x2112, .DP_VID_N = 0x000034C0 + 0x2111 , .DP_VID_STREAM_CNTL = 0x000034C0 + 0x210c, .DP_VID_TIMING = 0x000034C0 + 0x2110, .DP_SEC_AUD_N = 0x000034C0 + 0x2131, .DP_SEC_AUD_N_READBACK = 0x000034C0 + 0x2132, .DP_SEC_AUD_M_READBACK = 0x000034C0 + 0x2134, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2135, .DP_DSC_CNTL = 0x000034C0 + 0x2152, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x215c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x215b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2092, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2130, .DP_GSP11_CNTL = 0x000034C0 + 0x2161, .DME_CONTROL = 0x000034C0 + 0x2089, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x215b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2092, .DIG_FE_CNTL = 0x000034C0 + 0x208b, .DIG_FIFO_STATUS = 0x000034C0 + 0x2091, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x208e }, | ||||
| 359 | stream_enc_regs(1)[1] = { .AFMT_CNTL = 0x000034C0 + 0x21af, .DIG_FE_CNTL = 0x000034C0 + 0x218b, .HDMI_CONTROL = 0x000034C0 + 0x2193, .HDMI_DB_CONTROL = 0x000034C0 + 0x21a6, .HDMI_GC = 0x000034C0 + 0x219d, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x219a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x219e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x219f , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x21a0, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x21a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x219c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x219b , .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x21a2, .HDMI_GENERIC_PACKET_CONTROL8 = 0x000034C0 + 0x21a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0 + 0x21a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x21a5 , .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2198, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2199, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2197, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2195, . HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2196, .HDMI_ACR_32_0 = 0x000034C0 + 0x21a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x21a8, .HDMI_ACR_44_0 = 0x000034C0 + 0x21a9, .HDMI_ACR_44_1 = 0x000034C0 + 0x21aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x21ab, .HDMI_ACR_48_1 = 0x000034C0 + 0x21ac, .DP_DB_CNTL = 0x000034C0 + 0x2259, .DP_MSA_MISC = 0x000034C0 + 0x220e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x225a , .DP_MSA_COLORIMETRY = 0x000034C0 + 0x220a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x224c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x224d , .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x224e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x224f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2237 , .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2239, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2209, .DP_SEC_CNTL = 0x000034C0 + 0x222b, . DP_SEC_CNTL1 = 0x000034C0 + 0x222c, .DP_SEC_CNTL2 = 0x000034C0 + 0x2253, .DP_SEC_CNTL5 = 0x000034C0 + 0x2256, .DP_SEC_CNTL6 = 0x000034C0 + 0x2257, .DP_STEER_FIFO = 0x000034C0 + 0x220d, .DP_VID_M = 0x000034C0 + 0x2212, .DP_VID_N = 0x000034C0 + 0x2211 , .DP_VID_STREAM_CNTL = 0x000034C0 + 0x220c, .DP_VID_TIMING = 0x000034C0 + 0x2210, .DP_SEC_AUD_N = 0x000034C0 + 0x2231, .DP_SEC_AUD_N_READBACK = 0x000034C0 + 0x2232, .DP_SEC_AUD_M_READBACK = 0x000034C0 + 0x2234, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2235, .DP_DSC_CNTL = 0x000034C0 + 0x2252, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x225c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x225b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2192, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2230, .DP_GSP11_CNTL = 0x000034C0 + 0x2261, .DME_CONTROL = 0x000034C0 + 0x2189, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x225b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2192, .DIG_FE_CNTL = 0x000034C0 + 0x218b, .DIG_FIFO_STATUS = 0x000034C0 + 0x2191, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x218e }, | ||||
| 360 | stream_enc_regs(2)[2] = { .AFMT_CNTL = 0x000034C0 + 0x22af, .DIG_FE_CNTL = 0x000034C0 + 0x228b, .HDMI_CONTROL = 0x000034C0 + 0x2293, .HDMI_DB_CONTROL = 0x000034C0 + 0x22a6, .HDMI_GC = 0x000034C0 + 0x229d, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x229a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x229e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x229f , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x22a0, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x22a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x229c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x229b , .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x22a2, .HDMI_GENERIC_PACKET_CONTROL8 = 0x000034C0 + 0x22a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0 + 0x22a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x22a5 , .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2298, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2299, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2297, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2295, . HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2296, .HDMI_ACR_32_0 = 0x000034C0 + 0x22a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x22a8, .HDMI_ACR_44_0 = 0x000034C0 + 0x22a9, .HDMI_ACR_44_1 = 0x000034C0 + 0x22aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x22ab, .HDMI_ACR_48_1 = 0x000034C0 + 0x22ac, .DP_DB_CNTL = 0x000034C0 + 0x2359, .DP_MSA_MISC = 0x000034C0 + 0x230e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x235a , .DP_MSA_COLORIMETRY = 0x000034C0 + 0x230a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x234c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x234d , .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x234e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x234f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2337 , .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2339, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2309, .DP_SEC_CNTL = 0x000034C0 + 0x232b, . DP_SEC_CNTL1 = 0x000034C0 + 0x232c, .DP_SEC_CNTL2 = 0x000034C0 + 0x2353, .DP_SEC_CNTL5 = 0x000034C0 + 0x2356, .DP_SEC_CNTL6 = 0x000034C0 + 0x2357, .DP_STEER_FIFO = 0x000034C0 + 0x230d, .DP_VID_M = 0x000034C0 + 0x2312, .DP_VID_N = 0x000034C0 + 0x2311 , .DP_VID_STREAM_CNTL = 0x000034C0 + 0x230c, .DP_VID_TIMING = 0x000034C0 + 0x2310, .DP_SEC_AUD_N = 0x000034C0 + 0x2331, .DP_SEC_AUD_N_READBACK = 0x000034C0 + 0x2332, .DP_SEC_AUD_M_READBACK = 0x000034C0 + 0x2334, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2335, .DP_DSC_CNTL = 0x000034C0 + 0x2352, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x235c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x235b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2292, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2330, .DP_GSP11_CNTL = 0x000034C0 + 0x2361, .DME_CONTROL = 0x000034C0 + 0x2289, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x235b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2292, .DIG_FE_CNTL = 0x000034C0 + 0x228b, .DIG_FIFO_STATUS = 0x000034C0 + 0x2291, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x228e }, | ||||
| 361 | stream_enc_regs(3)[3] = { .AFMT_CNTL = 0x000034C0 + 0x23af, .DIG_FE_CNTL = 0x000034C0 + 0x238b, .HDMI_CONTROL = 0x000034C0 + 0x2393, .HDMI_DB_CONTROL = 0x000034C0 + 0x23a6, .HDMI_GC = 0x000034C0 + 0x239d, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x239a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x239e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x239f , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x23a0, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x23a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x239c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x239b , .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x23a2, .HDMI_GENERIC_PACKET_CONTROL8 = 0x000034C0 + 0x23a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0 + 0x23a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x23a5 , .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2398, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2399, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2397, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2395, . HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2396, .HDMI_ACR_32_0 = 0x000034C0 + 0x23a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x23a8, .HDMI_ACR_44_0 = 0x000034C0 + 0x23a9, .HDMI_ACR_44_1 = 0x000034C0 + 0x23aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x23ab, .HDMI_ACR_48_1 = 0x000034C0 + 0x23ac, .DP_DB_CNTL = 0x000034C0 + 0x2459, .DP_MSA_MISC = 0x000034C0 + 0x240e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x245a , .DP_MSA_COLORIMETRY = 0x000034C0 + 0x240a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x244c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x244d , .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x244e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x244f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2437 , .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2439, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2409, .DP_SEC_CNTL = 0x000034C0 + 0x242b, . DP_SEC_CNTL1 = 0x000034C0 + 0x242c, .DP_SEC_CNTL2 = 0x000034C0 + 0x2453, .DP_SEC_CNTL5 = 0x000034C0 + 0x2456, .DP_SEC_CNTL6 = 0x000034C0 + 0x2457, .DP_STEER_FIFO = 0x000034C0 + 0x240d, .DP_VID_M = 0x000034C0 + 0x2412, .DP_VID_N = 0x000034C0 + 0x2411 , .DP_VID_STREAM_CNTL = 0x000034C0 + 0x240c, .DP_VID_TIMING = 0x000034C0 + 0x2410, .DP_SEC_AUD_N = 0x000034C0 + 0x2431, .DP_SEC_AUD_N_READBACK = 0x000034C0 + 0x2432, .DP_SEC_AUD_M_READBACK = 0x000034C0 + 0x2434, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2435, .DP_DSC_CNTL = 0x000034C0 + 0x2452, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x245c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x245b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2392, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2430, .DP_GSP11_CNTL = 0x000034C0 + 0x2461, .DME_CONTROL = 0x000034C0 + 0x2389, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x245b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2392, .DIG_FE_CNTL = 0x000034C0 + 0x238b, .DIG_FIFO_STATUS = 0x000034C0 + 0x2391, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x238e }, | ||||
| 362 | stream_enc_regs(4)[4] = { .AFMT_CNTL = 0x000034C0 + 0x24af, .DIG_FE_CNTL = 0x000034C0 + 0x248b, .HDMI_CONTROL = 0x000034C0 + 0x2493, .HDMI_DB_CONTROL = 0x000034C0 + 0x24a6, .HDMI_GC = 0x000034C0 + 0x249d, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x249a, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x249e, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x249f , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x24a0, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x24a1, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x249c, .HDMI_GENERIC_PACKET_CONTROL6 = 0x000034C0 + 0x249b , .HDMI_GENERIC_PACKET_CONTROL7 = 0x000034C0 + 0x24a2, .HDMI_GENERIC_PACKET_CONTROL8 = 0x000034C0 + 0x24a3, .HDMI_GENERIC_PACKET_CONTROL9 = 0x000034C0 + 0x24a4, .HDMI_GENERIC_PACKET_CONTROL10 = 0x000034C0 + 0x24a5 , .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2498, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2499, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2497, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2495, . HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2496, .HDMI_ACR_32_0 = 0x000034C0 + 0x24a7, .HDMI_ACR_32_1 = 0x000034C0 + 0x24a8, .HDMI_ACR_44_0 = 0x000034C0 + 0x24a9, .HDMI_ACR_44_1 = 0x000034C0 + 0x24aa, .HDMI_ACR_48_0 = 0x000034C0 + 0x24ab, .HDMI_ACR_48_1 = 0x000034C0 + 0x24ac, .DP_DB_CNTL = 0x000034C0 + 0x2559, .DP_MSA_MISC = 0x000034C0 + 0x250e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x255a , .DP_MSA_COLORIMETRY = 0x000034C0 + 0x250a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x254c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x254d , .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x254e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x254f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2537 , .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2539, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2509, .DP_SEC_CNTL = 0x000034C0 + 0x252b, . DP_SEC_CNTL1 = 0x000034C0 + 0x252c, .DP_SEC_CNTL2 = 0x000034C0 + 0x2553, .DP_SEC_CNTL5 = 0x000034C0 + 0x2556, .DP_SEC_CNTL6 = 0x000034C0 + 0x2557, .DP_STEER_FIFO = 0x000034C0 + 0x250d, .DP_VID_M = 0x000034C0 + 0x2512, .DP_VID_N = 0x000034C0 + 0x2511 , .DP_VID_STREAM_CNTL = 0x000034C0 + 0x250c, .DP_VID_TIMING = 0x000034C0 + 0x2510, .DP_SEC_AUD_N = 0x000034C0 + 0x2531, .DP_SEC_AUD_N_READBACK = 0x000034C0 + 0x2532, .DP_SEC_AUD_M_READBACK = 0x000034C0 + 0x2534, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2535, .DP_DSC_CNTL = 0x000034C0 + 0x2552, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x255c, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x255b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2492, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2530, .DP_GSP11_CNTL = 0x000034C0 + 0x2561, .DME_CONTROL = 0x000034C0 + 0x2489, .DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x255b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x2492, .DIG_FE_CNTL = 0x000034C0 + 0x248b, .DIG_FIFO_STATUS = 0x000034C0 + 0x2491, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x248e } | ||||
| 363 | }; | ||||
| 364 | |||||
| 365 | static const struct dcn10_stream_encoder_shift se_shift = { | ||||
| 366 | SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT).DP_PIXEL_ENCODING = 0x0, .DP_COMPONENT_DEPTH = 0x18, .HDMI_PACKET_GEN_VERSION = 0x4, .HDMI_KEEPOUT_MODE = 0x0, .HDMI_DEEP_COLOR_ENABLE = 0x18 , .HDMI_DEEP_COLOR_DEPTH = 0x1c, .HDMI_DATA_SCRAMBLE_EN = 0x1 , .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x3, .HDMI_GC_CONT = 0x5 , .HDMI_GC_SEND = 0x4, .HDMI_NULL_SEND = 0x0, .HDMI_ACP_SEND = 0xc, .HDMI_AUDIO_INFO_SEND = 0x4, .HDMI_AUDIO_INFO_LINE = 0x8 , .HDMI_GC_AVMUTE = 0x0, .DP_MSE_RATE_X = 0x1a, .DP_MSE_RATE_Y = 0x0, .DP_MSE_RATE_UPDATE_PENDING = 0x0, .DP_SEC_GSP0_ENABLE = 0x14, .DP_SEC_STREAM_ENABLE = 0x0, .DP_SEC_GSP1_ENABLE = 0x15 , .DP_SEC_GSP2_ENABLE = 0x16, .DP_SEC_GSP3_ENABLE = 0x17, .DP_SEC_MPG_ENABLE = 0x1c, .DP_SEC_GSP4_SEND = 0xc, .DP_SEC_GSP4_SEND_PENDING = 0xd, .DP_SEC_GSP4_LINE_NUM = 0x10, .DP_SEC_GSP4_SEND_ANY_LINE = 0xf, .DP_VID_STREAM_DIS_DEFER = 0x8, .DP_VID_STREAM_ENABLE = 0x0, .DP_VID_STREAM_STATUS = 0x10, .DP_STEER_FIFO_RESET = 0x0 , .DP_VID_M_N_GEN_EN = 0x8, .DP_VID_N = 0x0, .DP_VID_M = 0x0, .DIG_START = 0xa, .HDMI_AUDIO_DELAY_EN = 0x4, .HDMI_ACR_AUTO_SEND = 0xc, .HDMI_ACR_SOURCE = 0x8, .HDMI_ACR_AUDIO_PRIORITY = 0x1f , .HDMI_ACR_CTS_32 = 0xc, .HDMI_ACR_N_32 = 0x0, .HDMI_ACR_CTS_44 = 0xc, .HDMI_ACR_N_44 = 0x0, .HDMI_ACR_CTS_48 = 0xc, .HDMI_ACR_N_48 = 0x0, .DP_SEC_AUD_N = 0x0, .DP_SEC_AUD_N_READBACK = 0x0, .DP_SEC_AUD_M_READBACK = 0x0, .DP_SEC_TIMESTAMP_MODE = 0x0, .DP_SEC_ASP_ENABLE = 0x4 , .DP_SEC_ATP_ENABLE = 0x8, .DP_SEC_AIP_ENABLE = 0xc, .DP_SEC_ACM_ENABLE = 0x10, .AFMT_AUDIO_CLOCK_EN = 0x0, .HDMI_CLOCK_CHANNEL_RATE = 0x2, .TMDS_PIXEL_ENCODING = 0x1c, .TMDS_COLOR_FORMAT = 0x1e , .DIG_STEREOSYNC_SELECT = 0x4, .DIG_STEREOSYNC_GATE_EN = 0x8 , .DIG_FIFO_LEVEL_ERROR = 0x0, .DIG_FIFO_USE_OVERWRITE_LEVEL = 0x1, .DIG_FIFO_OVERWRITE_LEVEL = 0x2, .DIG_FIFO_ERROR_ACK = 0x8 , .DIG_FIFO_CAL_AVERAGE_LEVEL = 0xa, .DIG_FIFO_MAXIMUM_LEVEL = 0x10, .DIG_FIFO_MINIMUM_LEVEL = 0x16, .DIG_FIFO_READ_CLOCK_SRC = 0x1a, .DIG_FIFO_CALIBRATED = 0x1d, .DIG_FIFO_FORCE_RECAL_AVERAGE = 0x1e, .DIG_FIFO_FORCE_RECOMP_MINMAX = 0x1f, .DP_SEC_GSP4_ENABLE = 0x18, .DP_SEC_GSP5_ENABLE = 0x19, .DP_SEC_GSP6_ENABLE = 0x1a , .DP_SEC_GSP7_ENABLE = 0x1b, .DP_SEC_GSP5_LINE_REFERENCE = 0xd , .DP_SEC_GSP7_SEND = 0x18, .DP_SEC_GSP5_LINE_NUM = 0x0, .DP_SEC_GSP7_LINE_NUM = 0x0, .DP_SEC_GSP11_PPS = 0x1c, .DP_SEC_GSP11_ENABLE = 0x4, .DP_SEC_GSP11_LINE_NUM = 0x10, .DP_DB_DISABLE = 0xc, .DP_MSA_MISC0 = 0x18, .DP_MSA_HTOTAL = 0x10, .DP_MSA_VTOTAL = 0x0, .DP_MSA_HSTART = 0x10, .DP_MSA_VSTART = 0x0, .DP_MSA_HSYNCWIDTH = 0x10, .DP_MSA_HSYNCPOLARITY = 0x1f, .DP_MSA_VSYNCWIDTH = 0x0, .DP_MSA_VSYNCPOLARITY = 0xf , .DP_MSA_HWIDTH = 0x10, .DP_MSA_VHEIGHT = 0x0, .HDMI_DB_DISABLE = 0xc, .DP_VID_N_MUL = 0xa, .DIG_SOURCE_SELECT = 0x0, .HDMI_GENERIC0_CONT = 0x1, .HDMI_GENERIC0_SEND = 0x0, .HDMI_GENERIC1_CONT = 0x5, .HDMI_GENERIC1_SEND = 0x4, .HDMI_GENERIC2_CONT = 0x9, .HDMI_GENERIC2_SEND = 0x8, .HDMI_GENERIC3_CONT = 0xd, .HDMI_GENERIC3_SEND = 0xc, .HDMI_GENERIC4_CONT = 0x11, .HDMI_GENERIC4_SEND = 0x10, .HDMI_GENERIC5_CONT = 0x15, .HDMI_GENERIC5_SEND = 0x14, .HDMI_GENERIC6_CONT = 0x19 , .HDMI_GENERIC6_SEND = 0x18, .HDMI_GENERIC7_CONT = 0x1d, .HDMI_GENERIC7_SEND = 0x1c, .HDMI_GENERIC8_CONT = 0x1, .HDMI_GENERIC8_SEND = 0x0 , .HDMI_GENERIC9_CONT = 0x5, .HDMI_GENERIC9_SEND = 0x4, .HDMI_GENERIC10_CONT = 0x9, .HDMI_GENERIC10_SEND = 0x8, .HDMI_GENERIC11_CONT = 0xd , .HDMI_GENERIC11_SEND = 0xc, .HDMI_GENERIC12_CONT = 0x11, .HDMI_GENERIC12_SEND = 0x10, .HDMI_GENERIC13_CONT = 0x15, .HDMI_GENERIC13_SEND = 0x14 , .HDMI_GENERIC14_CONT = 0x19, .HDMI_GENERIC14_SEND = 0x18, . HDMI_GENERIC0_LINE = 0x0, .HDMI_GENERIC1_LINE = 0x10, .HDMI_GENERIC2_LINE = 0x0, .HDMI_GENERIC3_LINE = 0x10, .HDMI_GENERIC4_LINE = 0x0 , .HDMI_GENERIC5_LINE = 0x10, .HDMI_GENERIC6_LINE = 0x0, .HDMI_GENERIC7_LINE = 0x10, .HDMI_GENERIC8_LINE = 0x0, .HDMI_GENERIC9_LINE = 0x10 , .HDMI_GENERIC10_LINE = 0x0, .HDMI_GENERIC11_LINE = 0x10, .HDMI_GENERIC12_LINE = 0x0, .HDMI_GENERIC13_LINE = 0x10, .HDMI_GENERIC14_LINE = 0x0 , .DP_DSC_MODE = 0x0, .DP_DSC_SLICE_WIDTH = 0x10, .DP_DSC_BYTES_PER_PIXEL = 0x0, .DP_VBID6_LINE_REFERENCE = 0xf, .DP_VBID6_LINE_NUM = 0x10 , .METADATA_ENGINE_EN = 0x4, .METADATA_HUBP_REQUESTOR_ID = 0x0 , .METADATA_STREAM_TYPE = 0x8, .DP_SEC_METADATA_PACKET_ENABLE = 0x0, .DP_SEC_METADATA_PACKET_LINE_REFERENCE = 0x1, .DP_SEC_METADATA_PACKET_LINE = 0x10, .HDMI_METADATA_PACKET_ENABLE = 0x0, .HDMI_METADATA_PACKET_LINE_REFERENCE = 0x4, .HDMI_METADATA_PACKET_LINE = 0x10, .DOLBY_VISION_EN = 0x12, .DP_PIXEL_COMBINE = 0x1c, .DP_SST_SDP_SPLITTING = 0x0, .DIG_CLOCK_PATTERN = 0x0 | ||||
| 367 | }; | ||||
| 368 | |||||
| 369 | static const struct dcn10_stream_encoder_mask se_mask = { | ||||
| 370 | SE_COMMON_MASK_SH_LIST_DCN30(_MASK).DP_PIXEL_ENCODING = 0x00000007L, .DP_COMPONENT_DEPTH = 0x07000000L , .HDMI_PACKET_GEN_VERSION = 0x00000010L, .HDMI_KEEPOUT_MODE = 0x00000001L, .HDMI_DEEP_COLOR_ENABLE = 0x01000000L, .HDMI_DEEP_COLOR_DEPTH = 0x30000000L, .HDMI_DATA_SCRAMBLE_EN = 0x00000002L, .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x00000008L, .HDMI_GC_CONT = 0x00000020L, .HDMI_GC_SEND = 0x00000010L , .HDMI_NULL_SEND = 0x00000001L, .HDMI_ACP_SEND = 0x00001000L , .HDMI_AUDIO_INFO_SEND = 0x00000010L, .HDMI_AUDIO_INFO_LINE = 0x00003F00L, .HDMI_GC_AVMUTE = 0x00000001L, .DP_MSE_RATE_X = 0xFC000000L, .DP_MSE_RATE_Y = 0x03FFFFFFL, .DP_MSE_RATE_UPDATE_PENDING = 0x00000001L, .DP_SEC_GSP0_ENABLE = 0x00100000L, .DP_SEC_STREAM_ENABLE = 0x00000001L, .DP_SEC_GSP1_ENABLE = 0x00200000L, .DP_SEC_GSP2_ENABLE = 0x00400000L, .DP_SEC_GSP3_ENABLE = 0x00800000L, .DP_SEC_MPG_ENABLE = 0x10000000L, .DP_SEC_GSP4_SEND = 0x00001000L, .DP_SEC_GSP4_SEND_PENDING = 0x00002000L, .DP_SEC_GSP4_LINE_NUM = 0xFFFF0000L, .DP_SEC_GSP4_SEND_ANY_LINE = 0x00008000L, .DP_VID_STREAM_DIS_DEFER = 0x00000300L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_VID_STREAM_STATUS = 0x00010000L, .DP_STEER_FIFO_RESET = 0x00000001L, .DP_VID_M_N_GEN_EN = 0x00000100L, .DP_VID_N = 0x00FFFFFFL, .DP_VID_M = 0x00FFFFFFL, .DIG_START = 0x00000400L , .HDMI_AUDIO_DELAY_EN = 0x00000030L, .HDMI_ACR_AUTO_SEND = 0x00001000L , .HDMI_ACR_SOURCE = 0x00000100L, .HDMI_ACR_AUDIO_PRIORITY = 0x80000000L , .HDMI_ACR_CTS_32 = 0xFFFFF000L, .HDMI_ACR_N_32 = 0x000FFFFFL , .HDMI_ACR_CTS_44 = 0xFFFFF000L, .HDMI_ACR_N_44 = 0x000FFFFFL , .HDMI_ACR_CTS_48 = 0xFFFFF000L, .HDMI_ACR_N_48 = 0x000FFFFFL , .DP_SEC_AUD_N = 0x00FFFFFFL, .DP_SEC_AUD_N_READBACK = 0x00FFFFFFL , .DP_SEC_AUD_M_READBACK = 0x00FFFFFFL, .DP_SEC_TIMESTAMP_MODE = 0x00000001L, .DP_SEC_ASP_ENABLE = 0x00000010L, .DP_SEC_ATP_ENABLE = 0x00000100L, .DP_SEC_AIP_ENABLE = 0x00001000L, .DP_SEC_ACM_ENABLE = 0x00010000L, .AFMT_AUDIO_CLOCK_EN = 0x00000001L, .HDMI_CLOCK_CHANNEL_RATE = 0x00000004L, .TMDS_PIXEL_ENCODING = 0x10000000L, .TMDS_COLOR_FORMAT = 0xC0000000L, .DIG_STEREOSYNC_SELECT = 0x00000070L, .DIG_STEREOSYNC_GATE_EN = 0x00000100L, .DIG_FIFO_LEVEL_ERROR = 0x00000001L, .DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000002L, .DIG_FIFO_OVERWRITE_LEVEL = 0x000000FCL, .DIG_FIFO_ERROR_ACK = 0x00000100L, .DIG_FIFO_CAL_AVERAGE_LEVEL = 0x0000FC00L, .DIG_FIFO_MAXIMUM_LEVEL = 0x001F0000L, .DIG_FIFO_MINIMUM_LEVEL = 0x03C00000L, .DIG_FIFO_READ_CLOCK_SRC = 0x04000000L, .DIG_FIFO_CALIBRATED = 0x20000000L, .DIG_FIFO_FORCE_RECAL_AVERAGE = 0x40000000L, .DIG_FIFO_FORCE_RECOMP_MINMAX = 0x80000000L, . DP_SEC_GSP4_ENABLE = 0x01000000L, .DP_SEC_GSP5_ENABLE = 0x02000000L , .DP_SEC_GSP6_ENABLE = 0x04000000L, .DP_SEC_GSP7_ENABLE = 0x08000000L , .DP_SEC_GSP5_LINE_REFERENCE = 0x00002000L, .DP_SEC_GSP7_SEND = 0x01000000L, .DP_SEC_GSP5_LINE_NUM = 0x0000FFFFL, .DP_SEC_GSP7_LINE_NUM = 0x0000FFFFL, .DP_SEC_GSP11_PPS = 0x10000000L, .DP_SEC_GSP11_ENABLE = 0x00000010L, .DP_SEC_GSP11_LINE_NUM = 0xFFFF0000L, .DP_DB_DISABLE = 0x00001000L, .DP_MSA_MISC0 = 0xFF000000L, .DP_MSA_HTOTAL = 0xFFFF0000L, .DP_MSA_VTOTAL = 0x0000FFFFL, .DP_MSA_HSTART = 0xFFFF0000L , .DP_MSA_VSTART = 0x0000FFFFL, .DP_MSA_HSYNCWIDTH = 0x7FFF0000L , .DP_MSA_HSYNCPOLARITY = 0x80000000L, .DP_MSA_VSYNCWIDTH = 0x00007FFFL , .DP_MSA_VSYNCPOLARITY = 0x00008000L, .DP_MSA_HWIDTH = 0xFFFF0000L , .DP_MSA_VHEIGHT = 0x0000FFFFL, .HDMI_DB_DISABLE = 0x00001000L , .DP_VID_N_MUL = 0x00000C00L, .DIG_SOURCE_SELECT = 0x00000007L , .HDMI_GENERIC0_CONT = 0x00000002L, .HDMI_GENERIC0_SEND = 0x00000001L , .HDMI_GENERIC1_CONT = 0x00000020L, .HDMI_GENERIC1_SEND = 0x00000010L , .HDMI_GENERIC2_CONT = 0x00000200L, .HDMI_GENERIC2_SEND = 0x00000100L , .HDMI_GENERIC3_CONT = 0x00002000L, .HDMI_GENERIC3_SEND = 0x00001000L , .HDMI_GENERIC4_CONT = 0x00020000L, .HDMI_GENERIC4_SEND = 0x00010000L , .HDMI_GENERIC5_CONT = 0x00200000L, .HDMI_GENERIC5_SEND = 0x00100000L , .HDMI_GENERIC6_CONT = 0x02000000L, .HDMI_GENERIC6_SEND = 0x01000000L , .HDMI_GENERIC7_CONT = 0x20000000L, .HDMI_GENERIC7_SEND = 0x10000000L , .HDMI_GENERIC8_CONT = 0x00000002L, .HDMI_GENERIC8_SEND = 0x00000001L , .HDMI_GENERIC9_CONT = 0x00000020L, .HDMI_GENERIC9_SEND = 0x00000010L , .HDMI_GENERIC10_CONT = 0x00000200L, .HDMI_GENERIC10_SEND = 0x00000100L , .HDMI_GENERIC11_CONT = 0x00002000L, .HDMI_GENERIC11_SEND = 0x00001000L , .HDMI_GENERIC12_CONT = 0x00020000L, .HDMI_GENERIC12_SEND = 0x00010000L , .HDMI_GENERIC13_CONT = 0x00200000L, .HDMI_GENERIC13_SEND = 0x00100000L , .HDMI_GENERIC14_CONT = 0x02000000L, .HDMI_GENERIC14_SEND = 0x01000000L , .HDMI_GENERIC0_LINE = 0x0000FFFFL, .HDMI_GENERIC1_LINE = 0xFFFF0000L , .HDMI_GENERIC2_LINE = 0x0000FFFFL, .HDMI_GENERIC3_LINE = 0xFFFF0000L , .HDMI_GENERIC4_LINE = 0x0000FFFFL, .HDMI_GENERIC5_LINE = 0xFFFF0000L , .HDMI_GENERIC6_LINE = 0x0000FFFFL, .HDMI_GENERIC7_LINE = 0xFFFF0000L , .HDMI_GENERIC8_LINE = 0x0000FFFFL, .HDMI_GENERIC9_LINE = 0xFFFF0000L , .HDMI_GENERIC10_LINE = 0x0000FFFFL, .HDMI_GENERIC11_LINE = 0xFFFF0000L , .HDMI_GENERIC12_LINE = 0x0000FFFFL, .HDMI_GENERIC13_LINE = 0xFFFF0000L , .HDMI_GENERIC14_LINE = 0x0000FFFFL, .DP_DSC_MODE = 0x00000003L , .DP_DSC_SLICE_WIDTH = 0x1FFF0000L, .DP_DSC_BYTES_PER_PIXEL = 0x7FFFFFFFL, .DP_VBID6_LINE_REFERENCE = 0x00008000L, .DP_VBID6_LINE_NUM = 0xFFFF0000L, .METADATA_ENGINE_EN = 0x00000010L, .METADATA_HUBP_REQUESTOR_ID = 0x00000007L, .METADATA_STREAM_TYPE = 0x00000100L, .DP_SEC_METADATA_PACKET_ENABLE = 0x00000001L, .DP_SEC_METADATA_PACKET_LINE_REFERENCE = 0x00000002L , .DP_SEC_METADATA_PACKET_LINE = 0xFFFF0000L, .HDMI_METADATA_PACKET_ENABLE = 0x00000001L, .HDMI_METADATA_PACKET_LINE_REFERENCE = 0x00000010L , .HDMI_METADATA_PACKET_LINE = 0xFFFF0000L, .DOLBY_VISION_EN = 0x00040000L, .DP_PIXEL_COMBINE = 0x30000000L, .DP_SST_SDP_SPLITTING = 0x00000001L, .DIG_CLOCK_PATTERN = 0x000003FFL | ||||
| 371 | }; | ||||
| 372 | |||||
| 373 | |||||
| 374 | #define aux_regs(id)[id] = { .AUX_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_CONTROL_BASE_IDX + regDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 = DCN_BASE__INST0_SEGregDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX + regDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGregDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX + regDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_DPHY_TX_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX + regDP_AUXid_AUX_DPHY_TX_CONTROL}\ | ||||
| 375 | [id] = {\ | ||||
| 376 | DCN2_AUX_REG_LIST(id).AUX_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_CONTROL_BASE_IDX + regDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 = DCN_BASE__INST0_SEGregDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX + regDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGregDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX + regDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_DPHY_TX_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX + regDP_AUXid_AUX_DPHY_TX_CONTROL\ | ||||
| 377 | } | ||||
| 378 | |||||
| 379 | static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { | ||||
| 380 | aux_regs(0)[0] = { .AUX_CONTROL = 0x000034C0 + 0x1f50, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1f5a, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f5b , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f59}, | ||||
| 381 | aux_regs(1)[1] = { .AUX_CONTROL = 0x000034C0 + 0x1f6c, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1f76, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f77 , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f75}, | ||||
| 382 | aux_regs(2)[2] = { .AUX_CONTROL = 0x000034C0 + 0x1f88, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1f92, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f93 , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f91}, | ||||
| 383 | aux_regs(3)[3] = { .AUX_CONTROL = 0x000034C0 + 0x1fa4, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1fae, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1faf , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1fad}, | ||||
| 384 | aux_regs(4)[4] = { .AUX_CONTROL = 0x000034C0 + 0x1fc0, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1fca, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fcb , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1fc9} | ||||
| 385 | }; | ||||
| 386 | |||||
| 387 | #define hpd_regs(id)[id] = { .DC_HPD_CONTROL = DCN_BASE__INST0_SEGregHPDid_DC_HPD_CONTROL_BASE_IDX + regHPDid_DC_HPD_CONTROL}\ | ||||
| 388 | [id] = {\ | ||||
| 389 | HPD_REG_LIST(id).DC_HPD_CONTROL = DCN_BASE__INST0_SEGregHPDid_DC_HPD_CONTROL_BASE_IDX + regHPDid_DC_HPD_CONTROL\ | ||||
| 390 | } | ||||
| 391 | |||||
| 392 | static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { | ||||
| 393 | hpd_regs(0)[0] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f16}, | ||||
| 394 | hpd_regs(1)[1] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f1e}, | ||||
| 395 | hpd_regs(2)[2] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f26}, | ||||
| 396 | hpd_regs(3)[3] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f2e}, | ||||
| 397 | hpd_regs(4)[4] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f36} | ||||
| 398 | }; | ||||
| 399 | |||||
| 400 | #define link_regs(id, phyid)[id] = { .DIG_BE_CNTL = DCN_BASE__INST0_SEGregDIGid_DIG_BE_CNTL_BASE_IDX + regDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = DCN_BASE__INST0_SEGregDIGid_DIG_BE_EN_CNTL_BASE_IDX + regDIGid_DIG_BE_EN_CNTL, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGregDIGid_TMDS_CTL_BITS_BASE_IDX + regDIGid_TMDS_CTL_BITS, .TMDS_DCBALANCER_CONTROL = DCN_BASE__INST0_SEGregDIGid_TMDS_DCBALANCER_CONTROL_BASE_IDX + regDIGid_TMDS_DCBALANCER_CONTROL, .DP_CONFIG = DCN_BASE__INST0_SEGregDPid_DP_CONFIG_BASE_IDX + regDPid_DP_CONFIG, .DP_DPHY_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_CNTL_BASE_IDX + regDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_PRBS_CNTL_BASE_IDX + regDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX + regDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = DCN_BASE__INST0_SEGregDPid_DP_DPHY_SYM0_BASE_IDX + regDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = DCN_BASE__INST0_SEGregDPid_DP_DPHY_SYM1_BASE_IDX + regDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = DCN_BASE__INST0_SEGregDPid_DP_DPHY_SYM2_BASE_IDX + regDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX + regDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = DCN_BASE__INST0_SEGregDPid_DP_LINK_CNTL_BASE_IDX + regDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL = DCN_BASE__INST0_SEGregDPid_DP_LINK_FRAMING_CNTL_BASE_IDX + regDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = DCN_BASE__INST0_SEGregDPid_DP_MSE_SAT0_BASE_IDX + regDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = DCN_BASE__INST0_SEGregDPid_DP_MSE_SAT1_BASE_IDX + regDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = DCN_BASE__INST0_SEGregDPid_DP_MSE_SAT2_BASE_IDX + regDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = DCN_BASE__INST0_SEGregDPid_DP_MSE_SAT_UPDATE_BASE_IDX + regDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL_BASE_IDX + regDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGregDPid_DP_VID_STREAM_CNTL_BASE_IDX + regDPid_DP_VID_STREAM_CNTL, .DP_DPHY_FAST_TRAINING = DCN_BASE__INST0_SEGregDPid_DP_DPHY_FAST_TRAINING_BASE_IDX + regDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL1_BASE_IDX + regDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX + regDPid_DP_DPHY_BS_SR_SWAP_CNTL, .DP_DPHY_HBR2_PATTERN_CONTROL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX + regDPid_DP_DPHY_HBR2_PATTERN_CONTROL, .DP_DPHY_INTERNAL_CTRL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX + regDPid_DP_DPHY_INTERNAL_CTRL, .DIO_LINKA_CNTL = 0x000034C0 + 0x1f04, .DIO_LINKB_CNTL = 0x000034C0 + 0x1f05, .DIO_LINKC_CNTL = 0x000034C0 + 0x1f06, .DIO_LINKD_CNTL = 0x000034C0 + 0x1f07 , .DIO_LINKE_CNTL = 0x000034C0 + 0x1f08, .DIO_LINKF_CNTL = 0x000034C0 + 0x1f09, .CLOCK_ENABLE = DCN_BASE__INST0_SEGregSYMCLKphyid_CLOCK_ENABLE_BASE_IDX + regSYMCLKphyid_CLOCK_ENABLE, .CHANNEL_XBAR_CNTL = DCN_BASE__INST0_SEGregUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX + regUNIPHYphyid_CHANNEL_XBAR_CNTL, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGregDIGid_TMDS_CTL_BITS_BASE_IDX + regDIGid_TMDS_CTL_BITS, .RDPCSTX_PHY_CNTL3 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL3_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL3, .RDPCSTX_PHY_CNTL4 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL4_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL4, .RDPCSTX_PHY_CNTL5 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL5_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL5, .RDPCSTX_PHY_CNTL6 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL6_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL6, .RDPCSPIPE_PHY_CNTL6 = DCN_BASE__INST0_SEGregRDPCSPIPEid_RDPCSPIPE_PHY_CNTL6_BASE_IDX + regRDPCSPIPEid_RDPCSPIPE_PHY_CNTL6, .RDPCSTX_PHY_CNTL7 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL7_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL7, .RDPCSTX_PHY_CNTL8 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL8_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL8, .RDPCSTX_PHY_CNTL9 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL9_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL9, .RDPCSTX_PHY_CNTL10 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL10_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL10, .RDPCSTX_PHY_CNTL11 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL11_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL11, .RDPCSTX_PHY_CNTL12 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL12_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL12, .RDPCSTX_PHY_CNTL13 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL13_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL13, .RDPCSTX_PHY_CNTL14 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL14_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL14, .RDPCSTX_CNTL = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_CNTL_BASE_IDX + regRDPCSTXid_RDPCSTX_CNTL, .RDPCSTX_CLOCK_CNTL = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_CLOCK_CNTL_BASE_IDX + regRDPCSTXid_RDPCSTX_CLOCK_CNTL, .RDPCSTX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX + regRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL, .RDPCSTX_PHY_CNTL0 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL0_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL0, .RDPCSTX_PHY_CNTL2 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL2_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL2, .RDPCS_TX_CR_ADDR = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCS_TX_CR_ADDR_BASE_IDX + regRDPCSTXid_RDPCS_TX_CR_ADDR, .RDPCS_TX_CR_DATA = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCS_TX_CR_DATA_BASE_IDX + regRDPCSTXid_RDPCS_TX_CR_DATA, .RDPCSTX_PHY_FUSE0 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_FUSE0_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_FUSE0, .RDPCSTX_PHY_FUSE1 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_FUSE1_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_FUSE1, .RDPCSTX_PHY_FUSE2 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_FUSE2_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_FUSE2, .RDPCSTX_PHY_FUSE3 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_FUSE3_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_FUSE3, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX + regRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, }\ | ||||
| 401 | [id] = {\ | ||||
| 402 | LE_DCN31_REG_LIST(id).DIG_BE_CNTL = DCN_BASE__INST0_SEGregDIGid_DIG_BE_CNTL_BASE_IDX + regDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = DCN_BASE__INST0_SEGregDIGid_DIG_BE_EN_CNTL_BASE_IDX + regDIGid_DIG_BE_EN_CNTL, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGregDIGid_TMDS_CTL_BITS_BASE_IDX + regDIGid_TMDS_CTL_BITS, .TMDS_DCBALANCER_CONTROL = DCN_BASE__INST0_SEGregDIGid_TMDS_DCBALANCER_CONTROL_BASE_IDX + regDIGid_TMDS_DCBALANCER_CONTROL, .DP_CONFIG = DCN_BASE__INST0_SEGregDPid_DP_CONFIG_BASE_IDX + regDPid_DP_CONFIG, .DP_DPHY_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_CNTL_BASE_IDX + regDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_PRBS_CNTL_BASE_IDX + regDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX + regDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = DCN_BASE__INST0_SEGregDPid_DP_DPHY_SYM0_BASE_IDX + regDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = DCN_BASE__INST0_SEGregDPid_DP_DPHY_SYM1_BASE_IDX + regDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = DCN_BASE__INST0_SEGregDPid_DP_DPHY_SYM2_BASE_IDX + regDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX + regDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = DCN_BASE__INST0_SEGregDPid_DP_LINK_CNTL_BASE_IDX + regDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL = DCN_BASE__INST0_SEGregDPid_DP_LINK_FRAMING_CNTL_BASE_IDX + regDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = DCN_BASE__INST0_SEGregDPid_DP_MSE_SAT0_BASE_IDX + regDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = DCN_BASE__INST0_SEGregDPid_DP_MSE_SAT1_BASE_IDX + regDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = DCN_BASE__INST0_SEGregDPid_DP_MSE_SAT2_BASE_IDX + regDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = DCN_BASE__INST0_SEGregDPid_DP_MSE_SAT_UPDATE_BASE_IDX + regDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL_BASE_IDX + regDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGregDPid_DP_VID_STREAM_CNTL_BASE_IDX + regDPid_DP_VID_STREAM_CNTL, .DP_DPHY_FAST_TRAINING = DCN_BASE__INST0_SEGregDPid_DP_DPHY_FAST_TRAINING_BASE_IDX + regDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1 = DCN_BASE__INST0_SEGregDPid_DP_SEC_CNTL1_BASE_IDX + regDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX + regDPid_DP_DPHY_BS_SR_SWAP_CNTL, .DP_DPHY_HBR2_PATTERN_CONTROL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX + regDPid_DP_DPHY_HBR2_PATTERN_CONTROL, .DP_DPHY_INTERNAL_CTRL = DCN_BASE__INST0_SEGregDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX + regDPid_DP_DPHY_INTERNAL_CTRL, .DIO_LINKA_CNTL = 0x000034C0 + 0x1f04, .DIO_LINKB_CNTL = 0x000034C0 + 0x1f05, .DIO_LINKC_CNTL = 0x000034C0 + 0x1f06, .DIO_LINKD_CNTL = 0x000034C0 + 0x1f07 , .DIO_LINKE_CNTL = 0x000034C0 + 0x1f08, .DIO_LINKF_CNTL = 0x000034C0 + 0x1f09, \ | ||||
| 403 | UNIPHY_DCN2_REG_LIST(phyid).CLOCK_ENABLE = DCN_BASE__INST0_SEGregSYMCLKphyid_CLOCK_ENABLE_BASE_IDX + regSYMCLKphyid_CLOCK_ENABLE, .CHANNEL_XBAR_CNTL = DCN_BASE__INST0_SEGregUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX + regUNIPHYphyid_CHANNEL_XBAR_CNTL, \ | ||||
| 404 | DPCS_DCN31_REG_LIST(id).TMDS_CTL_BITS = DCN_BASE__INST0_SEGregDIGid_TMDS_CTL_BITS_BASE_IDX + regDIGid_TMDS_CTL_BITS, .RDPCSTX_PHY_CNTL3 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL3_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL3, .RDPCSTX_PHY_CNTL4 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL4_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL4, .RDPCSTX_PHY_CNTL5 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL5_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL5, .RDPCSTX_PHY_CNTL6 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL6_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL6, .RDPCSPIPE_PHY_CNTL6 = DCN_BASE__INST0_SEGregRDPCSPIPEid_RDPCSPIPE_PHY_CNTL6_BASE_IDX + regRDPCSPIPEid_RDPCSPIPE_PHY_CNTL6, .RDPCSTX_PHY_CNTL7 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL7_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL7, .RDPCSTX_PHY_CNTL8 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL8_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL8, .RDPCSTX_PHY_CNTL9 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL9_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL9, .RDPCSTX_PHY_CNTL10 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL10_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL10, .RDPCSTX_PHY_CNTL11 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL11_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL11, .RDPCSTX_PHY_CNTL12 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL12_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL12, .RDPCSTX_PHY_CNTL13 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL13_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL13, .RDPCSTX_PHY_CNTL14 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL14_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL14, .RDPCSTX_CNTL = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_CNTL_BASE_IDX + regRDPCSTXid_RDPCSTX_CNTL, .RDPCSTX_CLOCK_CNTL = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_CLOCK_CNTL_BASE_IDX + regRDPCSTXid_RDPCSTX_CLOCK_CNTL, .RDPCSTX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX + regRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL, .RDPCSTX_PHY_CNTL0 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL0_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL0, .RDPCSTX_PHY_CNTL2 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_CNTL2_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_CNTL2, .RDPCS_TX_CR_ADDR = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCS_TX_CR_ADDR_BASE_IDX + regRDPCSTXid_RDPCS_TX_CR_ADDR, .RDPCS_TX_CR_DATA = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCS_TX_CR_DATA_BASE_IDX + regRDPCSTXid_RDPCS_TX_CR_DATA, .RDPCSTX_PHY_FUSE0 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_FUSE0_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_FUSE0, .RDPCSTX_PHY_FUSE1 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_FUSE1_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_FUSE1, .RDPCSTX_PHY_FUSE2 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_FUSE2_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_FUSE2, .RDPCSTX_PHY_FUSE3 = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_FUSE3_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_FUSE3, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX + regRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = DCN_BASE__INST0_SEGregRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX + regRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, \ | ||||
| 405 | } | ||||
| 406 | |||||
| 407 | static const struct dce110_aux_registers_shift aux_shift = { | ||||
| 408 | DCN_AUX_MASK_SH_LIST(__SHIFT).AUX_EN = 0x0, .AUX_RESET = 0x4, .AUX_RESET_DONE = 0x5, .AUX_REG_RW_CNTL_STATUS = 0x2, .AUX_SW_USE_AUX_REG_REQ = 0x10, .AUX_SW_DONE_USING_AUX_REG = 0x11, .AUX_SW_START_DELAY = 0x4, .AUX_SW_WR_BYTES = 0x10, . AUX_SW_GO = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_DATA_RW = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_INDEX = 0x10, .AUX_SW_DATA = 0x8, .AUX_SW_REPLY_BYTE_COUNT = 0x18, . AUX_SW_DONE = 0x0, .AUX_SW_DONE_ACK = 0x1, .AUX_RX_TIMEOUT_LEN = 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf | ||||
| 409 | }; | ||||
| 410 | |||||
| 411 | static const struct dce110_aux_registers_mask aux_mask = { | ||||
| 412 | DCN_AUX_MASK_SH_LIST(_MASK).AUX_EN = 0x00000001L, .AUX_RESET = 0x00000010L, .AUX_RESET_DONE = 0x00000020L, .AUX_REG_RW_CNTL_STATUS = 0x0000000CL, .AUX_SW_USE_AUX_REG_REQ = 0x00010000L, .AUX_SW_DONE_USING_AUX_REG = 0x00020000L, .AUX_SW_START_DELAY = 0x000000F0L, .AUX_SW_WR_BYTES = 0x001F0000L, .AUX_SW_GO = 0x00000001L , .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, .AUX_SW_DATA_RW = 0x00000001L, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, . AUX_SW_INDEX = 0x001F0000L, .AUX_SW_DATA = 0x0000FF00L, .AUX_SW_REPLY_BYTE_COUNT = 0x1F000000L, .AUX_SW_DONE = 0x00000001L, .AUX_SW_DONE_ACK = 0x00000002L, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL = 0x00018000L | ||||
| 413 | }; | ||||
| 414 | |||||
| 415 | static const struct dcn10_link_enc_registers link_enc_regs[] = { | ||||
| 416 | link_regs(0, A)[0] = { .DIG_BE_CNTL = 0x000034C0 + 0x20b0, .DIG_BE_EN_CNTL = 0x000034C0 + 0x20b1, .TMDS_CTL_BITS = 0x000034C0 + 0x20de, . TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x20df, .DP_CONFIG = 0x000034C0 + 0x210b, .DP_DPHY_CNTL = 0x000034C0 + 0x2117, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x211d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x211e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2119, .DP_DPHY_SYM1 = 0x000034C0 + 0x211a, .DP_DPHY_SYM2 = 0x000034C0 + 0x211b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2118, .DP_LINK_CNTL = 0x000034C0 + 0x2108, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2113, .DP_MSE_SAT0 = 0x000034C0 + 0x213a, .DP_MSE_SAT1 = 0x000034C0 + 0x213b, .DP_MSE_SAT2 = 0x000034C0 + 0x213c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x213d , .DP_SEC_CNTL = 0x000034C0 + 0x212b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x210c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2124, .DP_SEC_CNTL1 = 0x000034C0 + 0x212c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2144, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2145 , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x210f, .DIO_LINKA_CNTL = 0x000034C0 + 0x1f04, .DIO_LINKB_CNTL = 0x000034C0 + 0x1f05 , .DIO_LINKC_CNTL = 0x000034C0 + 0x1f06, .DIO_LINKD_CNTL = 0x000034C0 + 0x1f07, .DIO_LINKE_CNTL = 0x000034C0 + 0x1f08, .DIO_LINKF_CNTL = 0x000034C0 + 0x1f09, .CLOCK_ENABLE = 0x000000C0 + 0x00a0, . CHANNEL_XBAR_CNTL = 0x000034C0 + 0x286e, .TMDS_CTL_BITS = 0x000034C0 + 0x20de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2943, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2944, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2945 , .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2946, .RDPCSPIPE_PHY_CNTL6 = 0x000034C0 + 0x2d73, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2947 , .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2948, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2949, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x294a , .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x294b, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x294c, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x294d , .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x294e, .RDPCSTX_CNTL = 0x000034C0 + 0x2930, .RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2931, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2932, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2940 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2942, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2934, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2935 , .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x294f, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2950, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2951 , .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2952, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2953, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x293c , }, | ||||
| 417 | link_regs(1, B)[1] = { .DIG_BE_CNTL = 0x000034C0 + 0x21b0, .DIG_BE_EN_CNTL = 0x000034C0 + 0x21b1, .TMDS_CTL_BITS = 0x000034C0 + 0x21de, . TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x21df, .DP_CONFIG = 0x000034C0 + 0x220b, .DP_DPHY_CNTL = 0x000034C0 + 0x2217, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x221d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x221e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2219, .DP_DPHY_SYM1 = 0x000034C0 + 0x221a, .DP_DPHY_SYM2 = 0x000034C0 + 0x221b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2218, .DP_LINK_CNTL = 0x000034C0 + 0x2208, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2213, .DP_MSE_SAT0 = 0x000034C0 + 0x223a, .DP_MSE_SAT1 = 0x000034C0 + 0x223b, .DP_MSE_SAT2 = 0x000034C0 + 0x223c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x223d , .DP_SEC_CNTL = 0x000034C0 + 0x222b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x220c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2224, .DP_SEC_CNTL1 = 0x000034C0 + 0x222c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2244, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2245 , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x220f, .DIO_LINKA_CNTL = 0x000034C0 + 0x1f04, .DIO_LINKB_CNTL = 0x000034C0 + 0x1f05 , .DIO_LINKC_CNTL = 0x000034C0 + 0x1f06, .DIO_LINKD_CNTL = 0x000034C0 + 0x1f07, .DIO_LINKE_CNTL = 0x000034C0 + 0x1f08, .DIO_LINKF_CNTL = 0x000034C0 + 0x1f09, .CLOCK_ENABLE = 0x000000C0 + 0x00a1, . CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2870, .TMDS_CTL_BITS = 0x000034C0 + 0x21de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2a1b, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2a1c, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2a1d , .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2a1e, .RDPCSPIPE_PHY_CNTL6 = 0x000034C0 + 0x2e4b, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2a1f , .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2a20, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2a21, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2a22 , .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2a23, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2a24, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2a25 , .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2a26, .RDPCSTX_CNTL = 0x000034C0 + 0x2a08, .RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2a09, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2a0a, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2a18 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2a1a, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2a0c, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2a0d , .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2a27, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2a28, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2a29 , .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2a2a, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2a2b, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2a14 , }, | ||||
| 418 | link_regs(2, C)[2] = { .DIG_BE_CNTL = 0x000034C0 + 0x22b0, .DIG_BE_EN_CNTL = 0x000034C0 + 0x22b1, .TMDS_CTL_BITS = 0x000034C0 + 0x22de, . TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x22df, .DP_CONFIG = 0x000034C0 + 0x230b, .DP_DPHY_CNTL = 0x000034C0 + 0x2317, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x231d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x231e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2319, .DP_DPHY_SYM1 = 0x000034C0 + 0x231a, .DP_DPHY_SYM2 = 0x000034C0 + 0x231b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2318, .DP_LINK_CNTL = 0x000034C0 + 0x2308, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2313, .DP_MSE_SAT0 = 0x000034C0 + 0x233a, .DP_MSE_SAT1 = 0x000034C0 + 0x233b, .DP_MSE_SAT2 = 0x000034C0 + 0x233c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x233d , .DP_SEC_CNTL = 0x000034C0 + 0x232b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x230c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2324, .DP_SEC_CNTL1 = 0x000034C0 + 0x232c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2344, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2345 , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x230f, .DIO_LINKA_CNTL = 0x000034C0 + 0x1f04, .DIO_LINKB_CNTL = 0x000034C0 + 0x1f05 , .DIO_LINKC_CNTL = 0x000034C0 + 0x1f06, .DIO_LINKD_CNTL = 0x000034C0 + 0x1f07, .DIO_LINKE_CNTL = 0x000034C0 + 0x1f08, .DIO_LINKF_CNTL = 0x000034C0 + 0x1f09, .CLOCK_ENABLE = 0x000000C0 + 0x00a2, . CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2872, .TMDS_CTL_BITS = 0x000034C0 + 0x22de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2af3, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2af4, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2af5 , .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2af6, .RDPCSPIPE_PHY_CNTL6 = 0x000034C0 + 0x2d73, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2af7 , .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2af8, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2af9, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2afa , .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2afb, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2afc, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2afd , .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2afe, .RDPCSTX_CNTL = 0x000034C0 + 0x2ae0, .RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2ae1, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2ae2, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2af0 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2af2, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2ae4, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2ae5 , .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2aff, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2b00, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2b01 , .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2b02, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2b03, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2aec , }, | ||||
| 419 | link_regs(3, D)[3] = { .DIG_BE_CNTL = 0x000034C0 + 0x23b0, .DIG_BE_EN_CNTL = 0x000034C0 + 0x23b1, .TMDS_CTL_BITS = 0x000034C0 + 0x23de, . TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x23df, .DP_CONFIG = 0x000034C0 + 0x240b, .DP_DPHY_CNTL = 0x000034C0 + 0x2417, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x241d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x241e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2419, .DP_DPHY_SYM1 = 0x000034C0 + 0x241a, .DP_DPHY_SYM2 = 0x000034C0 + 0x241b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2418, .DP_LINK_CNTL = 0x000034C0 + 0x2408, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2413, .DP_MSE_SAT0 = 0x000034C0 + 0x243a, .DP_MSE_SAT1 = 0x000034C0 + 0x243b, .DP_MSE_SAT2 = 0x000034C0 + 0x243c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x243d , .DP_SEC_CNTL = 0x000034C0 + 0x242b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x240c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2424, .DP_SEC_CNTL1 = 0x000034C0 + 0x242c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2444, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2445 , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x240f, .DIO_LINKA_CNTL = 0x000034C0 + 0x1f04, .DIO_LINKB_CNTL = 0x000034C0 + 0x1f05 , .DIO_LINKC_CNTL = 0x000034C0 + 0x1f06, .DIO_LINKD_CNTL = 0x000034C0 + 0x1f07, .DIO_LINKE_CNTL = 0x000034C0 + 0x1f08, .DIO_LINKF_CNTL = 0x000034C0 + 0x1f09, .CLOCK_ENABLE = 0x000000C0 + 0x00a3, . CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2874, .TMDS_CTL_BITS = 0x000034C0 + 0x23de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2bcb, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2bcc, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2bcd , .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2bce, .RDPCSPIPE_PHY_CNTL6 = 0x000034C0 + 0x2e4b, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2bcf , .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2bd0, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2bd1, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2bd2 , .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2bd3, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2bd4, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2bd5 , .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2bd6, .RDPCSTX_CNTL = 0x000034C0 + 0x2bb8, .RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2bb9, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2bba, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2bc8 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2bca, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2bbc, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2bbd , .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2bd7, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2bd8, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2bd9 , .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2bda, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2bdb, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2bc4 , }, | ||||
| 420 | link_regs(4, E)[4] = { .DIG_BE_CNTL = 0x000034C0 + 0x24b0, .DIG_BE_EN_CNTL = 0x000034C0 + 0x24b1, .TMDS_CTL_BITS = 0x000034C0 + 0x24de, . TMDS_DCBALANCER_CONTROL = 0x000034C0 + 0x24df, .DP_CONFIG = 0x000034C0 + 0x250b, .DP_DPHY_CNTL = 0x000034C0 + 0x2517, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x251d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x251e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2519, .DP_DPHY_SYM1 = 0x000034C0 + 0x251a, .DP_DPHY_SYM2 = 0x000034C0 + 0x251b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2518, .DP_LINK_CNTL = 0x000034C0 + 0x2508, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2513, .DP_MSE_SAT0 = 0x000034C0 + 0x253a, .DP_MSE_SAT1 = 0x000034C0 + 0x253b, .DP_MSE_SAT2 = 0x000034C0 + 0x253c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x253d , .DP_SEC_CNTL = 0x000034C0 + 0x252b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x250c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2524, .DP_SEC_CNTL1 = 0x000034C0 + 0x252c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2544, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2545 , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x250f, .DIO_LINKA_CNTL = 0x000034C0 + 0x1f04, .DIO_LINKB_CNTL = 0x000034C0 + 0x1f05 , .DIO_LINKC_CNTL = 0x000034C0 + 0x1f06, .DIO_LINKD_CNTL = 0x000034C0 + 0x1f07, .DIO_LINKE_CNTL = 0x000034C0 + 0x1f08, .DIO_LINKF_CNTL = 0x000034C0 + 0x1f09, .CLOCK_ENABLE = 0x000000C0 + 0x00a4, . CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2876, .TMDS_CTL_BITS = 0x000034C0 + 0x24de, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2ca3, .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2ca4, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2ca5 , .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2ca6, .RDPCSPIPE_PHY_CNTL6 = 0x000034C0 + 0x2d73, .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2ca7 , .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2ca8, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2ca9, .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2caa , .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2cab, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2cac, .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2cad , .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2cae, .RDPCSTX_CNTL = 0x000034C0 + 0x2c90, .RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2c91, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2c92, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2ca0 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2ca2, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2c94, .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2c95 , .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2caf, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2cb0, .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2cb1 , .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2cb2, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2937, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2cb3, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2c9c , } | ||||
| 421 | }; | ||||
| 422 | |||||
| 423 | static const struct dcn10_link_enc_shift le_shift = { | ||||
| 424 | LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT).DIG_ENABLE = 0x0, .DIG_HPD_SELECT = 0x1c, .DIG_MODE = 0x10, . DIG_FE_SOURCE_SELECT = 0x8, .DIG_CLOCK_PATTERN = 0x0, .TMDS_CTL0 = 0x0, .DPHY_BYPASS = 0x10, .DPHY_ATEST_SEL_LANE0 = 0x0, .DPHY_ATEST_SEL_LANE1 = 0x1, .DPHY_ATEST_SEL_LANE2 = 0x2, .DPHY_ATEST_SEL_LANE3 = 0x3 , .DPHY_PRBS_EN = 0x0, .DPHY_PRBS_SEL = 0x4, .DPHY_SYM1 = 0x0 , .DPHY_SYM2 = 0xa, .DPHY_SYM3 = 0x14, .DPHY_SYM4 = 0x0, .DPHY_SYM5 = 0xa, .DPHY_SYM6 = 0x14, .DPHY_SYM7 = 0x0, .DPHY_SYM8 = 0xa , .DPHY_SCRAMBLER_BS_COUNT = 0x8, .DPHY_SCRAMBLER_ADVANCE = 0x4 , .DPHY_RX_FAST_TRAINING_CAPABLE = 0x0, .DPHY_LOAD_BS_COUNT = 0x0, .DPHY_TRAINING_PATTERN_SEL = 0x0, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x0, .DP_LINK_TRAINING_COMPLETE = 0x4, .DP_IDLE_BS_INTERVAL = 0x0, .DP_VBID_DISABLE = 0x18, .DP_VID_ENHANCED_FRAME_MODE = 0x1c, .DP_VID_STREAM_ENABLE = 0x0, .DP_UDI_LANES = 0x0, .DP_SEC_GSP0_LINE_NUM = 0x10, .DP_SEC_GSP0_PRIORITY = 0x4, .DP_MSE_SAT_SRC0 = 0x0, .DP_MSE_SAT_SRC1 = 0x10, .DP_MSE_SAT_SLOT_COUNT0 = 0x8, .DP_MSE_SAT_SLOT_COUNT1 = 0x18, .DP_MSE_SAT_SRC2 = 0x0, .DP_MSE_SAT_SRC3 = 0x10, .DP_MSE_SAT_SLOT_COUNT2 = 0x8, .DP_MSE_SAT_SLOT_COUNT3 = 0x18, .DP_MSE_SAT_UPDATE = 0x0 , .DP_MSE_16_MTP_KEEPOUT = 0x8, .AUX_HPD_SEL = 0x14, .AUX_LS_READ_EN = 0x8, .AUX_RX_RECEIVE_WINDOW = 0x8, .DC_HPD_EN = 0x1c, .DPHY_FEC_EN = 0x4, .DPHY_FEC_READY_SHADOW = 0x5, .DPHY_FEC_ACTIVE_STATUS = 0x6, .TMDS_CTL0 = 0x0, .AUX_RX_START_WINDOW = 0x4, .AUX_RX_HALF_SYM_DETECT_LEN = 0xc, .AUX_RX_TRANSITION_FILTER_EN = 0x10, .AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x11, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = 0x12, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = 0x13, .AUX_RX_PHASE_DETECT_LEN = 0x14, .AUX_RX_DETECTION_THRESHOLD = 0x1c, .AUX_TX_PRECHARGE_LEN = 0x0, .AUX_TX_PRECHARGE_SYMBOLS = 0x8, .AUX_MODE_DET_CHECK_DELAY = 0x10, .AUX_RX_PRECHARGE_SKIP = 0x0, .AUX_RX_TIMEOUT_LEN = 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf , .ENC_TYPE_SEL = 0x0, .HPO_DP_ENC_SEL = 0x8, .HPO_HDMI_ENC_SEL = 0x4, \ | ||||
| 425 | DPCS_DCN31_MASK_SH_LIST(__SHIFT).RDPCS_PHY_DP_TX0_CLK_RDY = 0x2, .RDPCS_PHY_DP_TX0_DATA_EN = 0x3 , .RDPCS_PHY_DP_TX1_CLK_RDY = 0xa, .RDPCS_PHY_DP_TX1_DATA_EN = 0xb, .RDPCS_PHY_DP_TX2_CLK_RDY = 0x12, .RDPCS_PHY_DP_TX2_DATA_EN = 0x13, .RDPCS_PHY_DP_TX3_CLK_RDY = 0x1a, .RDPCS_PHY_DP_TX3_DATA_EN = 0x1b, .RDPCS_PHY_DP_TX0_TERM_CTRL = 0x0, .RDPCS_PHY_DP_TX1_TERM_CTRL = 0x8, .RDPCS_PHY_DP_TX2_TERM_CTRL = 0x10, .RDPCS_PHY_DP_TX3_TERM_CTRL = 0x18, .RDPCS_PHY_DP_MPLLB_MULTIPLIER = 0x4, .RDPCS_PHY_DP_TX0_WIDTH = 0x4, .RDPCS_PHY_DP_TX0_RATE = 0x1, .RDPCS_PHY_DP_TX1_WIDTH = 0xc, .RDPCS_PHY_DP_TX1_RATE = 0x9, .RDPCS_PHY_DP_TX2_PSTATE = 0x8, .RDPCS_PHY_DP_TX3_PSTATE = 0xc, .RDPCS_PHY_DP_TX2_MPLL_EN = 0xa, .RDPCS_PHY_DP_TX3_MPLL_EN = 0xe, .RDPCS_PHY_DPALT_DP4 = 0x10, .RDPCS_PHY_DPALT_DP4 = 0x10, .RDPCS_PHY_DPALT_DISABLE = 0x11, .RDPCS_PHY_DPALT_DISABLE_ACK = 0x12, .RDPCS_PHY_DP_MPLLB_FRACN_QUOT = 0x10, .RDPCS_PHY_DP_MPLLB_FRACN_DEN = 0x0, .RDPCS_PHY_DP_MPLLB_SSC_PEAK = 0x0, .RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD = 0x18, .RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE = 0x0, .RDPCS_PHY_DP_MPLLB_FRACN_REM = 0x0, .RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = 0x14, .RDPCS_PHY_HDMI_MPLLB_HDMI_DIV = 0x10, .RDPCS_PHY_DP_MPLLB_SSC_EN = 0x8, .RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN = 0x0, .RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x4, .RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN = 0x2, .RDPCS_PHY_DP_MPLLB_STATE = 0x7, .RDPCS_PHY_DP_MPLLB_DIV_CLK_EN = 0x1c, .RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER = 0x14, .RDPCS_PHY_DP_MPLLB_FRACN_EN = 0x18, .RDPCS_PHY_DP_MPLLB_PMIX_EN = 0x1c, .RDPCS_TX_FIFO_LANE0_EN = 0xc, .RDPCS_TX_FIFO_LANE1_EN = 0xd, .RDPCS_TX_FIFO_LANE2_EN = 0xe, .RDPCS_TX_FIFO_LANE3_EN = 0xf, .RDPCS_TX_FIFO_EN = 0x19, .RDPCS_TX_FIFO_RD_START_DELAY = 0x14, .RDPCS_EXT_REFCLK_EN = 0x0, .RDPCS_SRAMCLK_BYPASS = 0x10 , .RDPCS_SRAMCLK_EN = 0xd, .RDPCS_SRAMCLK_CLOCK_ON = 0xe, .RDPCS_SYMCLK_DIV2_CLOCK_ON = 0xa, .RDPCS_SYMCLK_DIV2_GATE_DIS = 0x8, .RDPCS_SYMCLK_DIV2_EN = 0x9, .RDPCS_PHY_DP_TX0_DISABLE = 0x1, .RDPCS_PHY_DP_TX1_DISABLE = 0x9, .RDPCS_PHY_DP_TX2_DISABLE = 0x11, .RDPCS_PHY_DP_TX3_DISABLE = 0x19, .RDPCS_PHY_DP_TX0_REQ = 0x4, .RDPCS_PHY_DP_TX1_REQ = 0xc, .RDPCS_PHY_DP_TX2_REQ = 0x14, .RDPCS_PHY_DP_TX3_REQ = 0x1c , .RDPCS_PHY_DP_TX0_ACK = 0x5, .RDPCS_PHY_DP_TX1_ACK = 0xd, . RDPCS_PHY_DP_TX2_ACK = 0x15, .RDPCS_PHY_DP_TX3_ACK = 0x1d, .RDPCS_PHY_DP_TX0_RESET = 0x0, .RDPCS_PHY_DP_TX1_RESET = 0x8, .RDPCS_PHY_DP_TX2_RESET = 0x10, .RDPCS_PHY_DP_TX3_RESET = 0x18, .RDPCS_PHY_RESET = 0x0 , .RDPCS_PHY_CR_MUX_SEL = 0x15, .RDPCS_PHY_REF_RANGE = 0x9, . RDPCS_SRAM_BYPASS = 0x1f, .RDPCS_SRAM_EXT_LD_DONE = 0x1d, .RDPCS_PHY_HDMIMODE_ENABLE = 0x8, .RDPCS_SRAM_INIT_DONE = 0x1c, .RDPCS_PHY_DP4_POR = 0x3 , .RDPCS_REG_FIFO_ERROR_MASK = 0x10, .RDPCS_TX_FIFO_ERROR_MASK = 0x14, .RDPCS_DPALT_DISABLE_TOGGLE_MASK = 0x11, .RDPCS_DPALT_4LANE_TOGGLE_MASK = 0x12, .RDPCS_TX_CR_ADDR = 0x0, .RDPCS_TX_CR_DATA = 0x0, .RDPCS_PHY_DP_MPLLB_V2I = 0x12, .RDPCS_PHY_DP_TX0_EQ_MAIN = 0x0, .RDPCS_PHY_DP_TX0_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX0_EQ_POST = 0xc, .RDPCS_PHY_DP_MPLLB_FREQ_VCO = 0x14, .RDPCS_PHY_DP_MPLLB_CP_INT = 0x12, .RDPCS_PHY_DP_MPLLB_CP_PROP = 0x19, .RDPCS_PHY_DP_TX1_EQ_MAIN = 0x0, .RDPCS_PHY_DP_TX1_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX1_EQ_POST = 0xc, .RDPCS_PHY_DP_TX2_EQ_MAIN = 0x0, .RDPCS_PHY_DP_TX2_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX2_EQ_POST = 0xc, .RDPCS_PHY_DP_TX3_EQ_MAIN = 0x0, .RDPCS_PHY_DCO_FINETUNE = 0x12, .RDPCS_PHY_DCO_RANGE = 0x18, .RDPCS_PHY_DP_TX3_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX3_EQ_POST = 0xc | ||||
| 426 | }; | ||||
| 427 | |||||
| 428 | static const struct dcn10_link_enc_mask le_mask = { | ||||
| 429 | LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK).DIG_ENABLE = 0x00000001L, .DIG_HPD_SELECT = 0x70000000L, .DIG_MODE = 0x00070000L, .DIG_FE_SOURCE_SELECT = 0x00007F00L, .DIG_CLOCK_PATTERN = 0x000003FFL, .TMDS_CTL0 = 0x00000001L, .DPHY_BYPASS = 0x00010000L , .DPHY_ATEST_SEL_LANE0 = 0x00000001L, .DPHY_ATEST_SEL_LANE1 = 0x00000002L, .DPHY_ATEST_SEL_LANE2 = 0x00000004L, .DPHY_ATEST_SEL_LANE3 = 0x00000008L, .DPHY_PRBS_EN = 0x00000001L, .DPHY_PRBS_SEL = 0x00000030L, .DPHY_SYM1 = 0x000003FFL, .DPHY_SYM2 = 0x000FFC00L , .DPHY_SYM3 = 0x3FF00000L, .DPHY_SYM4 = 0x000003FFL, .DPHY_SYM5 = 0x000FFC00L, .DPHY_SYM6 = 0x3FF00000L, .DPHY_SYM7 = 0x000003FFL , .DPHY_SYM8 = 0x000FFC00L, .DPHY_SCRAMBLER_BS_COUNT = 0x0003FF00L , .DPHY_SCRAMBLER_ADVANCE = 0x00000010L, .DPHY_RX_FAST_TRAINING_CAPABLE = 0x00000001L, .DPHY_LOAD_BS_COUNT = 0x000003FFL, .DPHY_TRAINING_PATTERN_SEL = 0x00000003L, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x00000007L, . DP_LINK_TRAINING_COMPLETE = 0x00000010L, .DP_IDLE_BS_INTERVAL = 0x0003FFFFL, .DP_VBID_DISABLE = 0x01000000L, .DP_VID_ENHANCED_FRAME_MODE = 0x10000000L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_UDI_LANES = 0x00000003L, .DP_SEC_GSP0_LINE_NUM = 0xFFFF0000L, .DP_SEC_GSP0_PRIORITY = 0x00000010L, .DP_MSE_SAT_SRC0 = 0x00000007L, .DP_MSE_SAT_SRC1 = 0x00070000L, .DP_MSE_SAT_SLOT_COUNT0 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT1 = 0x3F000000L, .DP_MSE_SAT_SRC2 = 0x00000007L, .DP_MSE_SAT_SRC3 = 0x00070000L, .DP_MSE_SAT_SLOT_COUNT2 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT3 = 0x3F000000L, .DP_MSE_SAT_UPDATE = 0x00000003L, .DP_MSE_16_MTP_KEEPOUT = 0x00000100L, .AUX_HPD_SEL = 0x00700000L, .AUX_LS_READ_EN = 0x00000100L, .AUX_RX_RECEIVE_WINDOW = 0x00000700L, .DC_HPD_EN = 0x10000000L, .DPHY_FEC_EN = 0x00000010L, .DPHY_FEC_READY_SHADOW = 0x00000020L, .DPHY_FEC_ACTIVE_STATUS = 0x00000040L, .TMDS_CTL0 = 0x00000001L, .AUX_RX_START_WINDOW = 0x00000070L, .AUX_RX_HALF_SYM_DETECT_LEN = 0x00003000L, .AUX_RX_TRANSITION_FILTER_EN = 0x00010000L, . AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00020000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = 0x00040000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = 0x00080000L , .AUX_RX_PHASE_DETECT_LEN = 0x00300000L, .AUX_RX_DETECTION_THRESHOLD = 0x70000000L, .AUX_TX_PRECHARGE_LEN = 0x0000000FL, .AUX_TX_PRECHARGE_SYMBOLS = 0x00003F00L, .AUX_MODE_DET_CHECK_DELAY = 0x00070000L, .AUX_RX_PRECHARGE_SKIP = 0x000000FFL, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL = 0x00018000L, .ENC_TYPE_SEL = 0x00000003L, .HPO_DP_ENC_SEL = 0x00000700L, .HPO_HDMI_ENC_SEL = 0x00000070L, \ | ||||
| 430 | DPCS_DCN31_MASK_SH_LIST(_MASK).RDPCS_PHY_DP_TX0_CLK_RDY = 0x00000004L, .RDPCS_PHY_DP_TX0_DATA_EN = 0x00000008L, .RDPCS_PHY_DP_TX1_CLK_RDY = 0x00000400L, .RDPCS_PHY_DP_TX1_DATA_EN = 0x00000800L, .RDPCS_PHY_DP_TX2_CLK_RDY = 0x00040000L, .RDPCS_PHY_DP_TX2_DATA_EN = 0x00080000L, .RDPCS_PHY_DP_TX3_CLK_RDY = 0x04000000L, .RDPCS_PHY_DP_TX3_DATA_EN = 0x08000000L, .RDPCS_PHY_DP_TX0_TERM_CTRL = 0x00000007L, .RDPCS_PHY_DP_TX1_TERM_CTRL = 0x00000700L, .RDPCS_PHY_DP_TX2_TERM_CTRL = 0x00070000L, .RDPCS_PHY_DP_TX3_TERM_CTRL = 0x07000000L, .RDPCS_PHY_DP_MPLLB_MULTIPLIER = 0x0000FFF0L, .RDPCS_PHY_DP_TX0_WIDTH = 0x00000030L, .RDPCS_PHY_DP_TX0_RATE = 0x0000000EL, .RDPCS_PHY_DP_TX1_WIDTH = 0x00003000L, .RDPCS_PHY_DP_TX1_RATE = 0x00000E00L, .RDPCS_PHY_DP_TX2_PSTATE = 0x00000300L, .RDPCS_PHY_DP_TX3_PSTATE = 0x00003000L, .RDPCS_PHY_DP_TX2_MPLL_EN = 0x00000400L, .RDPCS_PHY_DP_TX3_MPLL_EN = 0x00004000L, .RDPCS_PHY_DPALT_DP4 = 0x00010000L, .RDPCS_PHY_DPALT_DP4 = 0x00010000L, .RDPCS_PHY_DPALT_DISABLE = 0x00020000L, .RDPCS_PHY_DPALT_DISABLE_ACK = 0x00040000L, .RDPCS_PHY_DP_MPLLB_FRACN_QUOT = 0xFFFF0000L, .RDPCS_PHY_DP_MPLLB_FRACN_DEN = 0x0000FFFFL, .RDPCS_PHY_DP_MPLLB_SSC_PEAK = 0x000FFFFFL, .RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD = 0x01000000L , .RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE = 0x001FFFFFL, .RDPCS_PHY_DP_MPLLB_FRACN_REM = 0x0000FFFFL, .RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = 0x00700000L , .RDPCS_PHY_HDMI_MPLLB_HDMI_DIV = 0x00070000L, .RDPCS_PHY_DP_MPLLB_SSC_EN = 0x00000100L, .RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN = 0x00000001L , .RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000070L, .RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN = 0x00000004L, .RDPCS_PHY_DP_MPLLB_STATE = 0x00000080L, .RDPCS_PHY_DP_MPLLB_DIV_CLK_EN = 0x10000000L, .RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER = 0x0FF00000L , .RDPCS_PHY_DP_MPLLB_FRACN_EN = 0x01000000L, .RDPCS_PHY_DP_MPLLB_PMIX_EN = 0x10000000L, .RDPCS_TX_FIFO_LANE0_EN = 0x00001000L, .RDPCS_TX_FIFO_LANE1_EN = 0x00002000L, .RDPCS_TX_FIFO_LANE2_EN = 0x00004000L, .RDPCS_TX_FIFO_LANE3_EN = 0x00008000L, .RDPCS_TX_FIFO_EN = 0x02000000L, .RDPCS_TX_FIFO_RD_START_DELAY = 0x01F00000L, .RDPCS_EXT_REFCLK_EN = 0x00000001L, .RDPCS_SRAMCLK_BYPASS = 0x00010000L, .RDPCS_SRAMCLK_EN = 0x00002000L, .RDPCS_SRAMCLK_CLOCK_ON = 0x00004000L, .RDPCS_SYMCLK_DIV2_CLOCK_ON = 0x00000400L, .RDPCS_SYMCLK_DIV2_GATE_DIS = 0x00000100L, .RDPCS_SYMCLK_DIV2_EN = 0x00000200L, .RDPCS_PHY_DP_TX0_DISABLE = 0x00000002L, .RDPCS_PHY_DP_TX1_DISABLE = 0x00000200L, .RDPCS_PHY_DP_TX2_DISABLE = 0x00020000L, .RDPCS_PHY_DP_TX3_DISABLE = 0x02000000L, .RDPCS_PHY_DP_TX0_REQ = 0x00000010L, .RDPCS_PHY_DP_TX1_REQ = 0x00001000L, .RDPCS_PHY_DP_TX2_REQ = 0x00100000L, .RDPCS_PHY_DP_TX3_REQ = 0x10000000L, .RDPCS_PHY_DP_TX0_ACK = 0x00000020L, .RDPCS_PHY_DP_TX1_ACK = 0x00002000L, .RDPCS_PHY_DP_TX2_ACK = 0x00200000L, .RDPCS_PHY_DP_TX3_ACK = 0x20000000L, .RDPCS_PHY_DP_TX0_RESET = 0x00000001L, .RDPCS_PHY_DP_TX1_RESET = 0x00000100L, .RDPCS_PHY_DP_TX2_RESET = 0x00010000L, .RDPCS_PHY_DP_TX3_RESET = 0x01000000L, .RDPCS_PHY_RESET = 0x00000001L, .RDPCS_PHY_CR_MUX_SEL = 0x00200000L, .RDPCS_PHY_REF_RANGE = 0x00003E00L, .RDPCS_SRAM_BYPASS = 0x80000000L, .RDPCS_SRAM_EXT_LD_DONE = 0x20000000L, .RDPCS_PHY_HDMIMODE_ENABLE = 0x00000100L, .RDPCS_SRAM_INIT_DONE = 0x10000000L, .RDPCS_PHY_DP4_POR = 0x00000008L, .RDPCS_REG_FIFO_ERROR_MASK = 0x00010000L, .RDPCS_TX_FIFO_ERROR_MASK = 0x00100000L, .RDPCS_DPALT_DISABLE_TOGGLE_MASK = 0x00020000L, .RDPCS_DPALT_4LANE_TOGGLE_MASK = 0x00040000L, .RDPCS_TX_CR_ADDR = 0x0000FFFFL, .RDPCS_TX_CR_DATA = 0x0000FFFFL , .RDPCS_PHY_DP_MPLLB_V2I = 0x000C0000L, .RDPCS_PHY_DP_TX0_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DP_TX0_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX0_EQ_POST = 0x0003F000L, .RDPCS_PHY_DP_MPLLB_FREQ_VCO = 0x00300000L, . RDPCS_PHY_DP_MPLLB_CP_INT = 0x01FC0000L, .RDPCS_PHY_DP_MPLLB_CP_PROP = 0xFE000000L, .RDPCS_PHY_DP_TX1_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DP_TX1_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX1_EQ_POST = 0x0003F000L, .RDPCS_PHY_DP_TX2_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DP_TX2_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX2_EQ_POST = 0x0003F000L, .RDPCS_PHY_DP_TX3_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DCO_FINETUNE = 0x00FC0000L, .RDPCS_PHY_DCO_RANGE = 0x03000000L, .RDPCS_PHY_DP_TX3_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX3_EQ_POST = 0x0003F000L | ||||
| 431 | }; | ||||
| 432 | |||||
| 433 | #define hpo_dp_stream_encoder_reg_list(id)[id] = { .DP_STREAM_MAPPER_CONTROL0 = 0x00009000 + 0x0e56, .DP_STREAM_MAPPER_CONTROL1 = 0x00009000 + 0x0e57, .DP_STREAM_MAPPER_CONTROL2 = 0x00009000 + 0x0e58, .DP_STREAM_MAPPER_CONTROL3 = 0x00009000 + 0x0e59, . DP_STREAM_ENC_CLOCK_CONTROL = DCN_BASE__INST0_SEGregDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX + regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_CONTROL, .DP_STREAM_ENC_INPUT_MUX_CONTROL = DCN_BASE__INST0_SEGregDP_STREAM_ENCid_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX + regDP_STREAM_ENCid_DP_STREAM_ENC_INPUT_MUX_CONTROL, .DP_STREAM_ENC_AUDIO_CONTROL = DCN_BASE__INST0_SEGregDP_STREAM_ENCid_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX + regDP_STREAM_ENCid_DP_STREAM_ENC_AUDIO_CONTROL, .DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = DCN_BASE__INST0_SEGregDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX + regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 , .DP_SYM32_ENC_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_CONTROL, .DP_SYM32_ENC_VID_PIXEL_FORMAT = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT, .DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL , .DP_SYM32_ENC_VID_MSA0 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA0_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA0, .DP_SYM32_ENC_VID_MSA1 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA1_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA1, .DP_SYM32_ENC_VID_MSA2 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA2_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA2, .DP_SYM32_ENC_VID_MSA3 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA3_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA3, .DP_SYM32_ENC_VID_MSA4 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA4_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA4, .DP_SYM32_ENC_VID_MSA5 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA5_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA5, .DP_SYM32_ENC_VID_MSA6 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA6_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA6, .DP_SYM32_ENC_VID_MSA7 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA7_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA7, .DP_SYM32_ENC_VID_MSA8 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA8_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA8, .DP_SYM32_ENC_VID_MSA_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_CONTROL, .DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL , .DP_SYM32_ENC_VID_FIFO_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_FIFO_CONTROL, .DP_SYM32_ENC_VID_STREAM_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_STREAM_CONTROL, .DP_SYM32_ENC_VID_VBID_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_VBID_CONTROL, .DP_SYM32_ENC_SDP_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_CONTROL, .DP_SYM32_ENC_SDP_GSP_CONTROL0 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL0, .DP_SYM32_ENC_SDP_GSP_CONTROL2 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL2, .DP_SYM32_ENC_SDP_GSP_CONTROL3 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL3, .DP_SYM32_ENC_SDP_GSP_CONTROL5 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL5, .DP_SYM32_ENC_SDP_GSP_CONTROL11 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL11, .DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL , .DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, .DP_SYM32_ENC_VID_CRC_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_CRC_CONTROL, .DP_SYM32_ENC_HBLANK_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_HBLANK_CONTROL}\ | ||||
| 434 | [id] = {\ | ||||
| 435 | DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id).DP_STREAM_MAPPER_CONTROL0 = 0x00009000 + 0x0e56, .DP_STREAM_MAPPER_CONTROL1 = 0x00009000 + 0x0e57, .DP_STREAM_MAPPER_CONTROL2 = 0x00009000 + 0x0e58, .DP_STREAM_MAPPER_CONTROL3 = 0x00009000 + 0x0e59, . DP_STREAM_ENC_CLOCK_CONTROL = DCN_BASE__INST0_SEGregDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX + regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_CONTROL, .DP_STREAM_ENC_INPUT_MUX_CONTROL = DCN_BASE__INST0_SEGregDP_STREAM_ENCid_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX + regDP_STREAM_ENCid_DP_STREAM_ENC_INPUT_MUX_CONTROL, .DP_STREAM_ENC_AUDIO_CONTROL = DCN_BASE__INST0_SEGregDP_STREAM_ENCid_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX + regDP_STREAM_ENCid_DP_STREAM_ENC_AUDIO_CONTROL, .DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = DCN_BASE__INST0_SEGregDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX + regDP_STREAM_ENCid_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 , .DP_SYM32_ENC_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_CONTROL, .DP_SYM32_ENC_VID_PIXEL_FORMAT = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT, .DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL , .DP_SYM32_ENC_VID_MSA0 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA0_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA0, .DP_SYM32_ENC_VID_MSA1 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA1_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA1, .DP_SYM32_ENC_VID_MSA2 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA2_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA2, .DP_SYM32_ENC_VID_MSA3 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA3_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA3, .DP_SYM32_ENC_VID_MSA4 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA4_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA4, .DP_SYM32_ENC_VID_MSA5 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA5_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA5, .DP_SYM32_ENC_VID_MSA6 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA6_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA6, .DP_SYM32_ENC_VID_MSA7 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA7_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA7, .DP_SYM32_ENC_VID_MSA8 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA8_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA8, .DP_SYM32_ENC_VID_MSA_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_CONTROL, .DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL , .DP_SYM32_ENC_VID_FIFO_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_FIFO_CONTROL, .DP_SYM32_ENC_VID_STREAM_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_STREAM_CONTROL, .DP_SYM32_ENC_VID_VBID_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_VBID_CONTROL, .DP_SYM32_ENC_SDP_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_CONTROL, .DP_SYM32_ENC_SDP_GSP_CONTROL0 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL0, .DP_SYM32_ENC_SDP_GSP_CONTROL2 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL2, .DP_SYM32_ENC_SDP_GSP_CONTROL3 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL3, .DP_SYM32_ENC_SDP_GSP_CONTROL5 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL5, .DP_SYM32_ENC_SDP_GSP_CONTROL11 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_GSP_CONTROL11, .DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL , .DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, .DP_SYM32_ENC_VID_CRC_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_VID_CRC_CONTROL, .DP_SYM32_ENC_HBLANK_CONTROL = DCN_BASE__INST0_SEGregDP_SYM32_ENCid_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX + regDP_SYM32_ENCid_DP_SYM32_ENC_HBLANK_CONTROL\ | ||||
| 436 | } | ||||
| 437 | |||||
| 438 | static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = { | ||||
| 439 | hpo_dp_stream_encoder_reg_list(0)[0] = { .DP_STREAM_MAPPER_CONTROL0 = 0x00009000 + 0x0e56, .DP_STREAM_MAPPER_CONTROL1 = 0x00009000 + 0x0e57, .DP_STREAM_MAPPER_CONTROL2 = 0x00009000 + 0x0e58, .DP_STREAM_MAPPER_CONTROL3 = 0x00009000 + 0x0e59, . DP_STREAM_ENC_CLOCK_CONTROL = 0x000034C0 + 0x3623, .DP_STREAM_ENC_INPUT_MUX_CONTROL = 0x000034C0 + 0x3624, .DP_STREAM_ENC_AUDIO_CONTROL = 0x000034C0 + 0x3625, .DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = 0x000034C0 + 0x3626, .DP_SYM32_ENC_CONTROL = 0x000034C0 + 0x365d , .DP_SYM32_ENC_VID_PIXEL_FORMAT = 0x000034C0 + 0x3661, .DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x3660, .DP_SYM32_ENC_VID_MSA0 = 0x000034C0 + 0x3662, .DP_SYM32_ENC_VID_MSA1 = 0x000034C0 + 0x3663, .DP_SYM32_ENC_VID_MSA2 = 0x000034C0 + 0x3664, .DP_SYM32_ENC_VID_MSA3 = 0x000034C0 + 0x3665, .DP_SYM32_ENC_VID_MSA4 = 0x000034C0 + 0x3666, .DP_SYM32_ENC_VID_MSA5 = 0x000034C0 + 0x3667, .DP_SYM32_ENC_VID_MSA6 = 0x000034C0 + 0x3668, .DP_SYM32_ENC_VID_MSA7 = 0x000034C0 + 0x3669, .DP_SYM32_ENC_VID_MSA8 = 0x000034C0 + 0x366a, .DP_SYM32_ENC_VID_MSA_CONTROL = 0x000034C0 + 0x3683, .DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x365f, .DP_SYM32_ENC_VID_FIFO_CONTROL = 0x000034C0 + 0x365e , .DP_SYM32_ENC_VID_STREAM_CONTROL = 0x000034C0 + 0x3685, .DP_SYM32_ENC_VID_VBID_CONTROL = 0x000034C0 + 0x3684, .DP_SYM32_ENC_SDP_CONTROL = 0x000034C0 + 0x367b, .DP_SYM32_ENC_SDP_GSP_CONTROL0 = 0x000034C0 + 0x366c , .DP_SYM32_ENC_SDP_GSP_CONTROL2 = 0x000034C0 + 0x366e, .DP_SYM32_ENC_SDP_GSP_CONTROL3 = 0x000034C0 + 0x366f, .DP_SYM32_ENC_SDP_GSP_CONTROL5 = 0x000034C0 + 0x3671, .DP_SYM32_ENC_SDP_GSP_CONTROL11 = 0x000034C0 + 0x3677 , .DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = 0x000034C0 + 0x367e , .DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = 0x000034C0 + 0x367c, .DP_SYM32_ENC_VID_CRC_CONTROL = 0x000034C0 + 0x3687, .DP_SYM32_ENC_HBLANK_CONTROL = 0x000034C0 + 0x366b}, | ||||
| 440 | hpo_dp_stream_encoder_reg_list(1)[1] = { .DP_STREAM_MAPPER_CONTROL0 = 0x00009000 + 0x0e56, .DP_STREAM_MAPPER_CONTROL1 = 0x00009000 + 0x0e57, .DP_STREAM_MAPPER_CONTROL2 = 0x00009000 + 0x0e58, .DP_STREAM_MAPPER_CONTROL3 = 0x00009000 + 0x0e59, . DP_STREAM_ENC_CLOCK_CONTROL = 0x000034C0 + 0x36f7, .DP_STREAM_ENC_INPUT_MUX_CONTROL = 0x000034C0 + 0x36f8, .DP_STREAM_ENC_AUDIO_CONTROL = 0x000034C0 + 0x36f9, .DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = 0x000034C0 + 0x36fa, .DP_SYM32_ENC_CONTROL = 0x000034C0 + 0x3731 , .DP_SYM32_ENC_VID_PIXEL_FORMAT = 0x000034C0 + 0x3735, .DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x3734, .DP_SYM32_ENC_VID_MSA0 = 0x000034C0 + 0x3736, .DP_SYM32_ENC_VID_MSA1 = 0x000034C0 + 0x3737, .DP_SYM32_ENC_VID_MSA2 = 0x000034C0 + 0x3738, .DP_SYM32_ENC_VID_MSA3 = 0x000034C0 + 0x3739, .DP_SYM32_ENC_VID_MSA4 = 0x000034C0 + 0x373a, .DP_SYM32_ENC_VID_MSA5 = 0x000034C0 + 0x373b, .DP_SYM32_ENC_VID_MSA6 = 0x000034C0 + 0x373c, .DP_SYM32_ENC_VID_MSA7 = 0x000034C0 + 0x373d, .DP_SYM32_ENC_VID_MSA8 = 0x000034C0 + 0x373e, .DP_SYM32_ENC_VID_MSA_CONTROL = 0x000034C0 + 0x3757, .DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x3733, .DP_SYM32_ENC_VID_FIFO_CONTROL = 0x000034C0 + 0x3732 , .DP_SYM32_ENC_VID_STREAM_CONTROL = 0x000034C0 + 0x3759, .DP_SYM32_ENC_VID_VBID_CONTROL = 0x000034C0 + 0x3758, .DP_SYM32_ENC_SDP_CONTROL = 0x000034C0 + 0x374f, .DP_SYM32_ENC_SDP_GSP_CONTROL0 = 0x000034C0 + 0x3740 , .DP_SYM32_ENC_SDP_GSP_CONTROL2 = 0x000034C0 + 0x3742, .DP_SYM32_ENC_SDP_GSP_CONTROL3 = 0x000034C0 + 0x3743, .DP_SYM32_ENC_SDP_GSP_CONTROL5 = 0x000034C0 + 0x3745, .DP_SYM32_ENC_SDP_GSP_CONTROL11 = 0x000034C0 + 0x374b , .DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = 0x000034C0 + 0x3752 , .DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = 0x000034C0 + 0x3750, .DP_SYM32_ENC_VID_CRC_CONTROL = 0x000034C0 + 0x375b, .DP_SYM32_ENC_HBLANK_CONTROL = 0x000034C0 + 0x373f}, | ||||
| 441 | hpo_dp_stream_encoder_reg_list(2)[2] = { .DP_STREAM_MAPPER_CONTROL0 = 0x00009000 + 0x0e56, .DP_STREAM_MAPPER_CONTROL1 = 0x00009000 + 0x0e57, .DP_STREAM_MAPPER_CONTROL2 = 0x00009000 + 0x0e58, .DP_STREAM_MAPPER_CONTROL3 = 0x00009000 + 0x0e59, . DP_STREAM_ENC_CLOCK_CONTROL = 0x000034C0 + 0x37cb, .DP_STREAM_ENC_INPUT_MUX_CONTROL = 0x000034C0 + 0x37cc, .DP_STREAM_ENC_AUDIO_CONTROL = 0x000034C0 + 0x37cd, .DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = 0x000034C0 + 0x37ce, .DP_SYM32_ENC_CONTROL = 0x000034C0 + 0x3805 , .DP_SYM32_ENC_VID_PIXEL_FORMAT = 0x000034C0 + 0x3809, .DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x3808, .DP_SYM32_ENC_VID_MSA0 = 0x000034C0 + 0x380a, .DP_SYM32_ENC_VID_MSA1 = 0x000034C0 + 0x380b, .DP_SYM32_ENC_VID_MSA2 = 0x000034C0 + 0x380c, .DP_SYM32_ENC_VID_MSA3 = 0x000034C0 + 0x380d, .DP_SYM32_ENC_VID_MSA4 = 0x000034C0 + 0x380e, .DP_SYM32_ENC_VID_MSA5 = 0x000034C0 + 0x380f, .DP_SYM32_ENC_VID_MSA6 = 0x000034C0 + 0x3810, .DP_SYM32_ENC_VID_MSA7 = 0x000034C0 + 0x3811, .DP_SYM32_ENC_VID_MSA8 = 0x000034C0 + 0x3812, .DP_SYM32_ENC_VID_MSA_CONTROL = 0x000034C0 + 0x382b, .DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x3807, .DP_SYM32_ENC_VID_FIFO_CONTROL = 0x000034C0 + 0x3806 , .DP_SYM32_ENC_VID_STREAM_CONTROL = 0x000034C0 + 0x382d, .DP_SYM32_ENC_VID_VBID_CONTROL = 0x000034C0 + 0x382c, .DP_SYM32_ENC_SDP_CONTROL = 0x000034C0 + 0x3823, .DP_SYM32_ENC_SDP_GSP_CONTROL0 = 0x000034C0 + 0x3814 , .DP_SYM32_ENC_SDP_GSP_CONTROL2 = 0x000034C0 + 0x3816, .DP_SYM32_ENC_SDP_GSP_CONTROL3 = 0x000034C0 + 0x3817, .DP_SYM32_ENC_SDP_GSP_CONTROL5 = 0x000034C0 + 0x3819, .DP_SYM32_ENC_SDP_GSP_CONTROL11 = 0x000034C0 + 0x381f , .DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = 0x000034C0 + 0x3826 , .DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = 0x000034C0 + 0x3824, .DP_SYM32_ENC_VID_CRC_CONTROL = 0x000034C0 + 0x382f, .DP_SYM32_ENC_HBLANK_CONTROL = 0x000034C0 + 0x3813}, | ||||
| 442 | hpo_dp_stream_encoder_reg_list(3)[3] = { .DP_STREAM_MAPPER_CONTROL0 = 0x00009000 + 0x0e56, .DP_STREAM_MAPPER_CONTROL1 = 0x00009000 + 0x0e57, .DP_STREAM_MAPPER_CONTROL2 = 0x00009000 + 0x0e58, .DP_STREAM_MAPPER_CONTROL3 = 0x00009000 + 0x0e59, . DP_STREAM_ENC_CLOCK_CONTROL = 0x000034C0 + 0x389f, .DP_STREAM_ENC_INPUT_MUX_CONTROL = 0x000034C0 + 0x38a0, .DP_STREAM_ENC_AUDIO_CONTROL = 0x000034C0 + 0x38a1, .DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 = 0x000034C0 + 0x38a2, .DP_SYM32_ENC_CONTROL = 0x000034C0 + 0x38d9 , .DP_SYM32_ENC_VID_PIXEL_FORMAT = 0x000034C0 + 0x38dd, .DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x38dc, .DP_SYM32_ENC_VID_MSA0 = 0x000034C0 + 0x38de, .DP_SYM32_ENC_VID_MSA1 = 0x000034C0 + 0x38df, .DP_SYM32_ENC_VID_MSA2 = 0x000034C0 + 0x38e0, .DP_SYM32_ENC_VID_MSA3 = 0x000034C0 + 0x38e1, .DP_SYM32_ENC_VID_MSA4 = 0x000034C0 + 0x38e2, .DP_SYM32_ENC_VID_MSA5 = 0x000034C0 + 0x38e3, .DP_SYM32_ENC_VID_MSA6 = 0x000034C0 + 0x38e4, .DP_SYM32_ENC_VID_MSA7 = 0x000034C0 + 0x38e5, .DP_SYM32_ENC_VID_MSA8 = 0x000034C0 + 0x38e6, .DP_SYM32_ENC_VID_MSA_CONTROL = 0x000034C0 + 0x38ff, .DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x38db, .DP_SYM32_ENC_VID_FIFO_CONTROL = 0x000034C0 + 0x38da , .DP_SYM32_ENC_VID_STREAM_CONTROL = 0x000034C0 + 0x3901, .DP_SYM32_ENC_VID_VBID_CONTROL = 0x000034C0 + 0x3900, .DP_SYM32_ENC_SDP_CONTROL = 0x000034C0 + 0x38f7, .DP_SYM32_ENC_SDP_GSP_CONTROL0 = 0x000034C0 + 0x38e8 , .DP_SYM32_ENC_SDP_GSP_CONTROL2 = 0x000034C0 + 0x38ea, .DP_SYM32_ENC_SDP_GSP_CONTROL3 = 0x000034C0 + 0x38eb, .DP_SYM32_ENC_SDP_GSP_CONTROL5 = 0x000034C0 + 0x38ed, .DP_SYM32_ENC_SDP_GSP_CONTROL11 = 0x000034C0 + 0x38f3 , .DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL = 0x000034C0 + 0x38fa , .DP_SYM32_ENC_SDP_AUDIO_CONTROL0 = 0x000034C0 + 0x38f8, .DP_SYM32_ENC_VID_CRC_CONTROL = 0x000034C0 + 0x3903, .DP_SYM32_ENC_HBLANK_CONTROL = 0x000034C0 + 0x38e7}, | ||||
| 443 | }; | ||||
| 444 | |||||
| 445 | static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { | ||||
| 446 | DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT).DP_STREAM_LINK_TARGET = 0x0, .DP_STREAM_ENC_CLOCK_EN = 0x0, . DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL = 0x0, .DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL = 0x0, .FIFO_RESET = 0x4, .FIFO_RESET_DONE = 0x14, .FIFO_ENABLE = 0x0, .DP_SYM32_ENC_RESET = 0x4, .DP_SYM32_ENC_RESET_DONE = 0x8, .DP_SYM32_ENC_ENABLE = 0x0, .PIXEL_ENCODING_TYPE = 0x0, .UNCOMPRESSED_PIXEL_ENCODING = 0x4, .UNCOMPRESSED_COMPONENT_DEPTH = 0x8, .PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE = 0x0, .MSA_DOUBLE_BUFFER_ENABLE = 0x0, .MSA_DATA_LANE_0 = 0x0, .MSA_DATA_LANE_1 = 0x8, .MSA_DATA_LANE_2 = 0x10, .MSA_DATA_LANE_3 = 0x18, .PIXEL_TO_SYMBOL_FIFO_RESET = 0x4, .PIXEL_TO_SYMBOL_FIFO_RESET_DONE = 0x8, .PIXEL_TO_SYMBOL_FIFO_ENABLE = 0x0, .VID_STREAM_ENABLE = 0x0, .VID_STREAM_STATUS = 0x8, . VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE = 0x0, .VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER = 0x10, .SDP_STREAM_ENABLE = 0x0, .GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE = 0x0, .GSP_PAYLOAD_SIZE = 0x5, .GSP_TRANSMISSION_LINE_NUMBER = 0x10, .GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE = 0x0, .GSP_TRANSMISSION_LINE_NUMBER = 0x10, .GSP_SOF_REFERENCE = 0x7, .METADATA_PACKET_ENABLE = 0x0 , .AUDIO_MUTE = 0x1c, .ASP_ENABLE = 0x0, .ATP_ENABLE = 0x1, . AIP_ENABLE = 0x2, .ACM_ENABLE = 0x3, .CRC_ENABLE = 0x0, .CRC_CONT_MODE_ENABLE = 0x4, .HBLANK_MINIMUM_SYMBOL_WIDTH = 0x0 | ||||
| 447 | }; | ||||
| 448 | |||||
| 449 | static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { | ||||
| 450 | DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK).DP_STREAM_LINK_TARGET = 0x00000007L, .DP_STREAM_ENC_CLOCK_EN = 0x00000001L, .DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL = 0x00000007L, .DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL = 0x00000007L, .FIFO_RESET = 0x00000010L, .FIFO_RESET_DONE = 0x00100000L, .FIFO_ENABLE = 0x00000001L, .DP_SYM32_ENC_RESET = 0x00000010L, .DP_SYM32_ENC_RESET_DONE = 0x00000100L, .DP_SYM32_ENC_ENABLE = 0x00000001L, .PIXEL_ENCODING_TYPE = 0x00000001L, .UNCOMPRESSED_PIXEL_ENCODING = 0x00000030L, .UNCOMPRESSED_COMPONENT_DEPTH = 0x00000300L, . PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE = 0x00000001L, .MSA_DOUBLE_BUFFER_ENABLE = 0x00000001L, .MSA_DATA_LANE_0 = 0x000000FFL, .MSA_DATA_LANE_1 = 0x0000FF00L, .MSA_DATA_LANE_2 = 0x00FF0000L, .MSA_DATA_LANE_3 = 0xFF000000L, .PIXEL_TO_SYMBOL_FIFO_RESET = 0x00000010L, .PIXEL_TO_SYMBOL_FIFO_RESET_DONE = 0x00000100L, .PIXEL_TO_SYMBOL_FIFO_ENABLE = 0x00000001L, . VID_STREAM_ENABLE = 0x00000001L, .VID_STREAM_STATUS = 0x00000100L , .VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE = 0x00000001L, . VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER = 0xFFFF0000L, .SDP_STREAM_ENABLE = 0x00000001L, .GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE = 0x00000001L , .GSP_PAYLOAD_SIZE = 0x00000060L, .GSP_TRANSMISSION_LINE_NUMBER = 0xFFFF0000L, .GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE = 0x00000001L , .GSP_TRANSMISSION_LINE_NUMBER = 0xFFFF0000L, .GSP_SOF_REFERENCE = 0x00000080L, .METADATA_PACKET_ENABLE = 0x00000001L, .AUDIO_MUTE = 0x10000000L, .ASP_ENABLE = 0x00000001L, .ATP_ENABLE = 0x00000002L , .AIP_ENABLE = 0x00000004L, .ACM_ENABLE = 0x00000008L, .CRC_ENABLE = 0x00000001L, .CRC_CONT_MODE_ENABLE = 0x00000010L, .HBLANK_MINIMUM_SYMBOL_WIDTH = 0x0000FFFFL | ||||
| 451 | }; | ||||
| 452 | |||||
| 453 | |||||
| 454 | #define hpo_dp_link_encoder_reg_list(id)[id] = { .DP_LINK_ENC_CLOCK_CONTROL = DCN_BASE__INST0_SEGregDP_LINK_ENCid_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX + regDP_LINK_ENCid_DP_LINK_ENC_CLOCK_CONTROL, .DP_DPHY_SYM32_CONTROL = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_CONTROL_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_CONTROL, .DP_DPHY_SYM32_STATUS = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_STATUS_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_STATUS, .DP_DPHY_SYM32_TP_CONFIG = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CONFIG, .DP_DPHY_SYM32_TP_PRBS_SEED0 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED0, .DP_DPHY_SYM32_TP_PRBS_SEED1 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED1, .DP_DPHY_SYM32_TP_PRBS_SEED2 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED2, .DP_DPHY_SYM32_TP_PRBS_SEED3 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED3, .DP_DPHY_SYM32_TP_SQ_PULSE = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_SQ_PULSE, .DP_DPHY_SYM32_TP_CUSTOM0 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM0, .DP_DPHY_SYM32_TP_CUSTOM1 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM1, .DP_DPHY_SYM32_TP_CUSTOM2 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM2, .DP_DPHY_SYM32_TP_CUSTOM3 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM3, .DP_DPHY_SYM32_TP_CUSTOM4 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM4, .DP_DPHY_SYM32_TP_CUSTOM5 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM5, .DP_DPHY_SYM32_TP_CUSTOM6 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM6, .DP_DPHY_SYM32_TP_CUSTOM7 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM7, .DP_DPHY_SYM32_TP_CUSTOM8 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM8, .DP_DPHY_SYM32_TP_CUSTOM9 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM9, .DP_DPHY_SYM32_TP_CUSTOM10 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM10, .DP_DPHY_SYM32_SAT_VC0 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC0_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC0, .DP_DPHY_SYM32_SAT_VC1 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC1_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC1, .DP_DPHY_SYM32_SAT_VC2 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC2_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC2, .DP_DPHY_SYM32_SAT_VC3 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC3_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC3, .DP_DPHY_SYM32_VC_RATE_CNTL0 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL0, .DP_DPHY_SYM32_VC_RATE_CNTL1 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL1, .DP_DPHY_SYM32_VC_RATE_CNTL2 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL2, .DP_DPHY_SYM32_VC_RATE_CNTL3 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL3, .DP_DPHY_SYM32_SAT_UPDATE = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_UPDATE, .RDPCSTX_PHY_CNTL6 [0] = 0x000034C0 + 0x2946, .RDPCSTX_PHY_CNTL6[1] = 0x000034C0 + 0x2a1e, .RDPCSTX_PHY_CNTL6[2] = 0x000034C0 + 0x2af6, .RDPCSTX_PHY_CNTL6 [3] = 0x000034C0 + 0x2bce, .RDPCSTX_PHY_CNTL6[4] = 0x000034C0 + 0x2ca6}\ | ||||
| 455 | [id] = {\ | ||||
| 456 | DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id).DP_LINK_ENC_CLOCK_CONTROL = DCN_BASE__INST0_SEGregDP_LINK_ENCid_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX + regDP_LINK_ENCid_DP_LINK_ENC_CLOCK_CONTROL, .DP_DPHY_SYM32_CONTROL = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_CONTROL_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_CONTROL, .DP_DPHY_SYM32_STATUS = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_STATUS_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_STATUS, .DP_DPHY_SYM32_TP_CONFIG = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CONFIG, .DP_DPHY_SYM32_TP_PRBS_SEED0 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED0, .DP_DPHY_SYM32_TP_PRBS_SEED1 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED1, .DP_DPHY_SYM32_TP_PRBS_SEED2 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED2, .DP_DPHY_SYM32_TP_PRBS_SEED3 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_PRBS_SEED3, .DP_DPHY_SYM32_TP_SQ_PULSE = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_SQ_PULSE, .DP_DPHY_SYM32_TP_CUSTOM0 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM0, .DP_DPHY_SYM32_TP_CUSTOM1 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM1, .DP_DPHY_SYM32_TP_CUSTOM2 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM2, .DP_DPHY_SYM32_TP_CUSTOM3 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM3, .DP_DPHY_SYM32_TP_CUSTOM4 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM4, .DP_DPHY_SYM32_TP_CUSTOM5 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM5, .DP_DPHY_SYM32_TP_CUSTOM6 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM6, .DP_DPHY_SYM32_TP_CUSTOM7 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM7, .DP_DPHY_SYM32_TP_CUSTOM8 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM8, .DP_DPHY_SYM32_TP_CUSTOM9 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM9, .DP_DPHY_SYM32_TP_CUSTOM10 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_TP_CUSTOM10, .DP_DPHY_SYM32_SAT_VC0 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC0_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC0, .DP_DPHY_SYM32_SAT_VC1 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC1_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC1, .DP_DPHY_SYM32_SAT_VC2 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC2_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC2, .DP_DPHY_SYM32_SAT_VC3 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC3_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_VC3, .DP_DPHY_SYM32_VC_RATE_CNTL0 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL0, .DP_DPHY_SYM32_VC_RATE_CNTL1 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL1, .DP_DPHY_SYM32_VC_RATE_CNTL2 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL2, .DP_DPHY_SYM32_VC_RATE_CNTL3 = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_VC_RATE_CNTL3, .DP_DPHY_SYM32_SAT_UPDATE = DCN_BASE__INST0_SEGregDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX + regDP_DPHY_SYM32id_DP_DPHY_SYM32_SAT_UPDATE,\ | ||||
| 457 | DCN3_1_RDPCSTX_REG_LIST(0).RDPCSTX_PHY_CNTL6[0] = 0x000034C0 + 0x2946,\ | ||||
| 458 | DCN3_1_RDPCSTX_REG_LIST(1).RDPCSTX_PHY_CNTL6[1] = 0x000034C0 + 0x2a1e,\ | ||||
| 459 | DCN3_1_RDPCSTX_REG_LIST(2).RDPCSTX_PHY_CNTL6[2] = 0x000034C0 + 0x2af6,\ | ||||
| 460 | DCN3_1_RDPCSTX_REG_LIST(3).RDPCSTX_PHY_CNTL6[3] = 0x000034C0 + 0x2bce,\ | ||||
| 461 | DCN3_1_RDPCSTX_REG_LIST(4).RDPCSTX_PHY_CNTL6[4] = 0x000034C0 + 0x2ca6\ | ||||
| 462 | } | ||||
| 463 | |||||
| 464 | static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = { | ||||
| 465 | hpo_dp_link_encoder_reg_list(0)[0] = { .DP_LINK_ENC_CLOCK_CONTROL = 0x000034C0 + 0x3697, .DP_DPHY_SYM32_CONTROL = 0x000034C0 + 0x36c0, .DP_DPHY_SYM32_STATUS = 0x000034C0 + 0x36c1 , .DP_DPHY_SYM32_TP_CONFIG = 0x000034C0 + 0x36d7, .DP_DPHY_SYM32_TP_PRBS_SEED0 = 0x000034C0 + 0x36d8, .DP_DPHY_SYM32_TP_PRBS_SEED1 = 0x000034C0 + 0x36d9, .DP_DPHY_SYM32_TP_PRBS_SEED2 = 0x000034C0 + 0x36da , .DP_DPHY_SYM32_TP_PRBS_SEED3 = 0x000034C0 + 0x36db, .DP_DPHY_SYM32_TP_SQ_PULSE = 0x000034C0 + 0x36dc, .DP_DPHY_SYM32_TP_CUSTOM0 = 0x000034C0 + 0x36dd, .DP_DPHY_SYM32_TP_CUSTOM1 = 0x000034C0 + 0x36de, . DP_DPHY_SYM32_TP_CUSTOM2 = 0x000034C0 + 0x36df, .DP_DPHY_SYM32_TP_CUSTOM3 = 0x000034C0 + 0x36e0, .DP_DPHY_SYM32_TP_CUSTOM4 = 0x000034C0 + 0x36e1, .DP_DPHY_SYM32_TP_CUSTOM5 = 0x000034C0 + 0x36e2, . DP_DPHY_SYM32_TP_CUSTOM6 = 0x000034C0 + 0x36e3, .DP_DPHY_SYM32_TP_CUSTOM7 = 0x000034C0 + 0x36e4, .DP_DPHY_SYM32_TP_CUSTOM8 = 0x000034C0 + 0x36e5, .DP_DPHY_SYM32_TP_CUSTOM9 = 0x000034C0 + 0x36e6, . DP_DPHY_SYM32_TP_CUSTOM10 = 0x000034C0 + 0x36e7, .DP_DPHY_SYM32_SAT_VC0 = 0x000034C0 + 0x36cb, .DP_DPHY_SYM32_SAT_VC1 = 0x000034C0 + 0x36cc, .DP_DPHY_SYM32_SAT_VC2 = 0x000034C0 + 0x36cd, .DP_DPHY_SYM32_SAT_VC3 = 0x000034C0 + 0x36ce, .DP_DPHY_SYM32_VC_RATE_CNTL0 = 0x000034C0 + 0x36c5, .DP_DPHY_SYM32_VC_RATE_CNTL1 = 0x000034C0 + 0x36c6 , .DP_DPHY_SYM32_VC_RATE_CNTL2 = 0x000034C0 + 0x36c7, .DP_DPHY_SYM32_VC_RATE_CNTL3 = 0x000034C0 + 0x36c8, .DP_DPHY_SYM32_SAT_UPDATE = 0x000034C0 + 0x36c4, .RDPCSTX_PHY_CNTL6[0] = 0x000034C0 + 0x2946, .RDPCSTX_PHY_CNTL6 [1] = 0x000034C0 + 0x2a1e, .RDPCSTX_PHY_CNTL6[2] = 0x000034C0 + 0x2af6, .RDPCSTX_PHY_CNTL6[3] = 0x000034C0 + 0x2bce, .RDPCSTX_PHY_CNTL6 [4] = 0x000034C0 + 0x2ca6}, | ||||
| 466 | hpo_dp_link_encoder_reg_list(1)[1] = { .DP_LINK_ENC_CLOCK_CONTROL = 0x000034C0 + 0x376b, .DP_DPHY_SYM32_CONTROL = 0x000034C0 + 0x3794, .DP_DPHY_SYM32_STATUS = 0x000034C0 + 0x3795 , .DP_DPHY_SYM32_TP_CONFIG = 0x000034C0 + 0x37ab, .DP_DPHY_SYM32_TP_PRBS_SEED0 = 0x000034C0 + 0x37ac, .DP_DPHY_SYM32_TP_PRBS_SEED1 = 0x000034C0 + 0x37ad, .DP_DPHY_SYM32_TP_PRBS_SEED2 = 0x000034C0 + 0x37ae , .DP_DPHY_SYM32_TP_PRBS_SEED3 = 0x000034C0 + 0x37af, .DP_DPHY_SYM32_TP_SQ_PULSE = 0x000034C0 + 0x37b0, .DP_DPHY_SYM32_TP_CUSTOM0 = 0x000034C0 + 0x37b1, .DP_DPHY_SYM32_TP_CUSTOM1 = 0x000034C0 + 0x37b2, . DP_DPHY_SYM32_TP_CUSTOM2 = 0x000034C0 + 0x37b3, .DP_DPHY_SYM32_TP_CUSTOM3 = 0x000034C0 + 0x37b4, .DP_DPHY_SYM32_TP_CUSTOM4 = 0x000034C0 + 0x37b5, .DP_DPHY_SYM32_TP_CUSTOM5 = 0x000034C0 + 0x37b6, . DP_DPHY_SYM32_TP_CUSTOM6 = 0x000034C0 + 0x37b7, .DP_DPHY_SYM32_TP_CUSTOM7 = 0x000034C0 + 0x37b8, .DP_DPHY_SYM32_TP_CUSTOM8 = 0x000034C0 + 0x37b9, .DP_DPHY_SYM32_TP_CUSTOM9 = 0x000034C0 + 0x37ba, . DP_DPHY_SYM32_TP_CUSTOM10 = 0x000034C0 + 0x37bb, .DP_DPHY_SYM32_SAT_VC0 = 0x000034C0 + 0x379f, .DP_DPHY_SYM32_SAT_VC1 = 0x000034C0 + 0x37a0, .DP_DPHY_SYM32_SAT_VC2 = 0x000034C0 + 0x37a1, .DP_DPHY_SYM32_SAT_VC3 = 0x000034C0 + 0x37a2, .DP_DPHY_SYM32_VC_RATE_CNTL0 = 0x000034C0 + 0x3799, .DP_DPHY_SYM32_VC_RATE_CNTL1 = 0x000034C0 + 0x379a , .DP_DPHY_SYM32_VC_RATE_CNTL2 = 0x000034C0 + 0x379b, .DP_DPHY_SYM32_VC_RATE_CNTL3 = 0x000034C0 + 0x379c, .DP_DPHY_SYM32_SAT_UPDATE = 0x000034C0 + 0x3798, .RDPCSTX_PHY_CNTL6[0] = 0x000034C0 + 0x2946, .RDPCSTX_PHY_CNTL6 [1] = 0x000034C0 + 0x2a1e, .RDPCSTX_PHY_CNTL6[2] = 0x000034C0 + 0x2af6, .RDPCSTX_PHY_CNTL6[3] = 0x000034C0 + 0x2bce, .RDPCSTX_PHY_CNTL6 [4] = 0x000034C0 + 0x2ca6}, | ||||
| 467 | }; | ||||
| 468 | |||||
| 469 | static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { | ||||
| 470 | DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT).DP_LINK_ENC_CLOCK_EN = 0x0, .DPHY_RESET = 0x1, .DPHY_ENABLE = 0x0, .PRECODER_ENABLE = 0x2, .MODE = 0x4, .NUM_LANES = 0x8, . STATUS = 0x0, .SAT_UPDATE_PENDING = 0x10, .RATE_UPDATE_PENDING = 0xc, .TP_CUSTOM = 0x0, .TP_SELECT0 = 0x0, .TP_SELECT1 = 0x8 , .TP_SELECT2 = 0x10, .TP_SELECT3 = 0x18, .TP_PRBS_SEL0 = 0x4 , .TP_PRBS_SEL1 = 0xc, .TP_PRBS_SEL2 = 0x14, .TP_PRBS_SEL3 = 0x1c , .TP_SQ_PULSE_WIDTH = 0x0, .SAT_STREAM_SOURCE = 0x0, .SAT_SLOT_COUNT = 0x8, .RDPCS_PHY_DPALT_DISABLE = 0x11, .STREAM_VC_RATE_X = 0x19 , .STREAM_VC_RATE_Y = 0x0, .SAT_UPDATE = 0x0 | ||||
| 471 | }; | ||||
| 472 | |||||
| 473 | static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { | ||||
| 474 | DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK).DP_LINK_ENC_CLOCK_EN = 0x00000001L, .DPHY_RESET = 0x00000002L , .DPHY_ENABLE = 0x00000001L, .PRECODER_ENABLE = 0x00000004L, .MODE = 0x00000030L, .NUM_LANES = 0x00000300L, .STATUS = 0x00000001L , .SAT_UPDATE_PENDING = 0x00030000L, .RATE_UPDATE_PENDING = 0x00001000L , .TP_CUSTOM = 0x00FFFFFFL, .TP_SELECT0 = 0x00000007L, .TP_SELECT1 = 0x00000700L, .TP_SELECT2 = 0x00070000L, .TP_SELECT3 = 0x07000000L , .TP_PRBS_SEL0 = 0x00000070L, .TP_PRBS_SEL1 = 0x00007000L, . TP_PRBS_SEL2 = 0x00700000L, .TP_PRBS_SEL3 = 0x70000000L, .TP_SQ_PULSE_WIDTH = 0x000000FFL, .SAT_STREAM_SOURCE = 0x00000007L, .SAT_SLOT_COUNT = 0x00007F00L, .RDPCS_PHY_DPALT_DISABLE = 0x00020000L, .STREAM_VC_RATE_X = 0xFE000000L, .STREAM_VC_RATE_Y = 0x01FFFFFFL, .SAT_UPDATE = 0x00000003L | ||||
| 475 | }; | ||||
| 476 | |||||
| 477 | #define dpp_regs(id)[id] = { .CM_DEALPHA = DCN_BASE__INST0_SEGregCMid_CM_DEALPHA_BASE_IDX + regCMid_CM_DEALPHA, .CM_MEM_PWR_STATUS = DCN_BASE__INST0_SEGregCMid_CM_MEM_PWR_STATUS_BASE_IDX + regCMid_CM_MEM_PWR_STATUS, .CM_BIAS_CR_R = DCN_BASE__INST0_SEGregCMid_CM_BIAS_CR_R_BASE_IDX + regCMid_CM_BIAS_CR_R, .CM_BIAS_Y_G_CB_B = DCN_BASE__INST0_SEGregCMid_CM_BIAS_Y_G_CB_B_BASE_IDX + regCMid_CM_BIAS_Y_G_CB_B, .PRE_DEGAM = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_DEGAM_BASE_IDX + regCNVC_CFGid_PRE_DEGAM, .CM_GAMCOR_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_CONTROL_BASE_IDX + regCMid_CM_GAMCOR_CONTROL, .CM_GAMCOR_LUT_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_LUT_CONTROL_BASE_IDX + regCMid_CM_GAMCOR_LUT_CONTROL, .CM_GAMCOR_LUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX + regCMid_CM_GAMCOR_LUT_INDEX, .CM_GAMCOR_LUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX + regCMid_CM_GAMCOR_LUT_INDEX, .CM_GAMCOR_LUT_DATA = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_LUT_DATA_BASE_IDX + regCMid_CM_GAMCOR_LUT_DATA, .CM_GAMCOR_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_CNTL_B, .CM_GAMCOR_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_CNTL_G, .CM_GAMCOR_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_CNTL_R, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, .CM_GAMCOR_RAMB_END_CNTL1_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL1_B, .CM_GAMCOR_RAMB_END_CNTL2_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL2_B, .CM_GAMCOR_RAMB_END_CNTL1_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL1_G, .CM_GAMCOR_RAMB_END_CNTL2_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL2_G, .CM_GAMCOR_RAMB_END_CNTL1_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL1_R, .CM_GAMCOR_RAMB_END_CNTL2_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL2_R, .CM_GAMCOR_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX + regCMid_CM_GAMCOR_RAMB_REGION_0_1, .CM_GAMCOR_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX + regCMid_CM_GAMCOR_RAMB_REGION_32_33, .CM_GAMCOR_RAMB_OFFSET_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_OFFSET_B, .CM_GAMCOR_RAMB_OFFSET_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_OFFSET_G, .CM_GAMCOR_RAMB_OFFSET_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_OFFSET_R, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B, .CM_GAMCOR_RAMB_START_BASE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G, .CM_GAMCOR_RAMB_START_BASE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R, .CM_GAMCOR_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_CNTL_B, .CM_GAMCOR_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_CNTL_G, .CM_GAMCOR_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_CNTL_R, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, .CM_GAMCOR_RAMA_END_CNTL1_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL1_B, .CM_GAMCOR_RAMA_END_CNTL2_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL2_B, .CM_GAMCOR_RAMA_END_CNTL1_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL1_G, .CM_GAMCOR_RAMA_END_CNTL2_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL2_G, .CM_GAMCOR_RAMA_END_CNTL1_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL1_R, .CM_GAMCOR_RAMA_END_CNTL2_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL2_R, .CM_GAMCOR_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX + regCMid_CM_GAMCOR_RAMA_REGION_0_1, .CM_GAMCOR_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX + regCMid_CM_GAMCOR_RAMA_REGION_32_33, .CM_GAMCOR_RAMA_OFFSET_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_OFFSET_B, .CM_GAMCOR_RAMA_OFFSET_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_OFFSET_G, .CM_GAMCOR_RAMA_OFFSET_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_OFFSET_R, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B, .CM_GAMCOR_RAMA_START_BASE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G, .CM_GAMCOR_RAMA_START_BASE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R, .CM_GAMUT_REMAP_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX + regCMid_CM_GAMUT_REMAP_CONTROL, .CM_GAMUT_REMAP_C11_C12 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX + regCMid_CM_GAMUT_REMAP_C11_C12, .CM_GAMUT_REMAP_C13_C14 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX + regCMid_CM_GAMUT_REMAP_C13_C14, .CM_GAMUT_REMAP_C21_C22 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX + regCMid_CM_GAMUT_REMAP_C21_C22, .CM_GAMUT_REMAP_C23_C24 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX + regCMid_CM_GAMUT_REMAP_C23_C24, .CM_GAMUT_REMAP_C31_C32 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX + regCMid_CM_GAMUT_REMAP_C31_C32, .CM_GAMUT_REMAP_C33_C34 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX + regCMid_CM_GAMUT_REMAP_C33_C34, .CM_GAMUT_REMAP_B_C11_C12 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C11_C12, .CM_GAMUT_REMAP_B_C13_C14 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C13_C14, .CM_GAMUT_REMAP_B_C21_C22 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C21_C22, .CM_GAMUT_REMAP_B_C23_C24 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C23_C24, .CM_GAMUT_REMAP_B_C31_C32 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C31_C32, .CM_GAMUT_REMAP_B_C33_C34 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C33_C34, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = DCN_BASE__INST0_SEGregDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX + regDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = DCN_BASE__INST0_SEGregDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX + regDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, .OTG_H_BLANK = DCN_BASE__INST0_SEGregDSCLid_OTG_H_BLANK_BASE_IDX + regDSCLid_OTG_H_BLANK, .OTG_V_BLANK = DCN_BASE__INST0_SEGregDSCLid_OTG_V_BLANK_BASE_IDX + regDSCLid_OTG_V_BLANK, .SCL_MODE = DCN_BASE__INST0_SEGregDSCLid_SCL_MODE_BASE_IDX + regDSCLid_SCL_MODE, .LB_DATA_FORMAT = DCN_BASE__INST0_SEGregDSCLid_LB_DATA_FORMAT_BASE_IDX + regDSCLid_LB_DATA_FORMAT, .LB_MEMORY_CTRL = DCN_BASE__INST0_SEGregDSCLid_LB_MEMORY_CTRL_BASE_IDX + regDSCLid_LB_MEMORY_CTRL, .DSCL_AUTOCAL = DCN_BASE__INST0_SEGregDSCLid_DSCL_AUTOCAL_BASE_IDX + regDSCLid_DSCL_AUTOCAL, .SCL_TAP_CONTROL = DCN_BASE__INST0_SEGregDSCLid_SCL_TAP_CONTROL_BASE_IDX + regDSCLid_SCL_TAP_CONTROL, .SCL_COEF_RAM_TAP_SELECT = DCN_BASE__INST0_SEGregDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX + regDSCLid_SCL_COEF_RAM_TAP_SELECT, .SCL_COEF_RAM_TAP_DATA = DCN_BASE__INST0_SEGregDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX + regDSCLid_SCL_COEF_RAM_TAP_DATA, .DSCL_2TAP_CONTROL = DCN_BASE__INST0_SEGregDSCLid_DSCL_2TAP_CONTROL_BASE_IDX + regDSCLid_DSCL_2TAP_CONTROL, .MPC_SIZE = DCN_BASE__INST0_SEGregDSCLid_MPC_SIZE_BASE_IDX + regDSCLid_MPC_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGregDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX + regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGregDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX + regDSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_SCALE_RATIO_C = DCN_BASE__INST0_SEGregDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX + regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C, .SCL_VERT_FILTER_SCALE_RATIO_C = DCN_BASE__INST0_SEGregDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX + regDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C, .SCL_HORZ_FILTER_INIT = DCN_BASE__INST0_SEGregDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX + regDSCLid_SCL_HORZ_FILTER_INIT, .SCL_HORZ_FILTER_INIT_C = DCN_BASE__INST0_SEGregDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX + regDSCLid_SCL_HORZ_FILTER_INIT_C, .SCL_VERT_FILTER_INIT = DCN_BASE__INST0_SEGregDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX + regDSCLid_SCL_VERT_FILTER_INIT, .SCL_VERT_FILTER_INIT_C = DCN_BASE__INST0_SEGregDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX + regDSCLid_SCL_VERT_FILTER_INIT_C, .RECOUT_START = DCN_BASE__INST0_SEGregDSCLid_RECOUT_START_BASE_IDX + regDSCLid_RECOUT_START, .RECOUT_SIZE = DCN_BASE__INST0_SEGregDSCLid_RECOUT_SIZE_BASE_IDX + regDSCLid_RECOUT_SIZE, .PRE_DEALPHA = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_DEALPHA_BASE_IDX + regCNVC_CFGid_PRE_DEALPHA, .PRE_REALPHA = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_REALPHA_BASE_IDX + regCNVC_CFGid_PRE_REALPHA, .PRE_CSC_MODE = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_MODE_BASE_IDX + regCNVC_CFGid_PRE_CSC_MODE, .PRE_CSC_C11_C12 = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_C11_C12_BASE_IDX + regCNVC_CFGid_PRE_CSC_C11_C12, .PRE_CSC_C33_C34 = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_C33_C34_BASE_IDX + regCNVC_CFGid_PRE_CSC_C33_C34, .PRE_CSC_B_C11_C12 = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_B_C11_C12_BASE_IDX + regCNVC_CFGid_PRE_CSC_B_C11_C12, .PRE_CSC_B_C33_C34 = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_B_C33_C34_BASE_IDX + regCNVC_CFGid_PRE_CSC_B_C33_C34, .CM_POST_CSC_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_CONTROL_BASE_IDX + regCMid_CM_POST_CSC_CONTROL, .CM_POST_CSC_C11_C12 = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_C11_C12_BASE_IDX + regCMid_CM_POST_CSC_C11_C12, .CM_POST_CSC_C33_C34 = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_C33_C34_BASE_IDX + regCMid_CM_POST_CSC_C33_C34, .CM_POST_CSC_B_C11_C12 = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_B_C11_C12_BASE_IDX + regCMid_CM_POST_CSC_B_C11_C12, .CM_POST_CSC_B_C33_C34 = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_B_C33_C34_BASE_IDX + regCMid_CM_POST_CSC_B_C33_C34, .CM_MEM_PWR_CTRL = DCN_BASE__INST0_SEGregCMid_CM_MEM_PWR_CTRL_BASE_IDX + regCMid_CM_MEM_PWR_CTRL, .CM_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_CONTROL_BASE_IDX + regCMid_CM_CONTROL, .FORMAT_CONTROL = DCN_BASE__INST0_SEGregCNVC_CFGid_FORMAT_CONTROL_BASE_IDX + regCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DCN_BASE__INST0_SEGregCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX + regCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL = DCN_BASE__INST0_SEGregCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + regCNVC_CURid_CURSOR0_CONTROL , .CURSOR0_COLOR0 = DCN_BASE__INST0_SEGregCNVC_CURid_CURSOR0_COLOR0_BASE_IDX + regCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DCN_BASE__INST0_SEGregCNVC_CURid_CURSOR0_COLOR1_BASE_IDX + regCNVC_CURid_CURSOR0_COLOR1, .CURSOR0_FP_SCALE_BIAS = DCN_BASE__INST0_SEGregCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX + regCNVC_CURid_CURSOR0_FP_SCALE_BIAS, .DPP_CONTROL = DCN_BASE__INST0_SEGregDPP_TOPid_DPP_CONTROL_BASE_IDX + regDPP_TOPid_DPP_CONTROL, .CM_HDR_MULT_COEF = DCN_BASE__INST0_SEGregCMid_CM_HDR_MULT_COEF_BASE_IDX + regCMid_CM_HDR_MULT_COEF, .CURSOR_CONTROL = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_CONTROL_BASE_IDX + regCURSOR0_id_CURSOR_CONTROL, .ALPHA_2BIT_LUT = DCN_BASE__INST0_SEGregCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX + regCNVC_CFGid_ALPHA_2BIT_LUT, .FCNV_FP_BIAS_R = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX + regCNVC_CFGid_FCNV_FP_BIAS_R, .FCNV_FP_BIAS_G = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX + regCNVC_CFGid_FCNV_FP_BIAS_G, .FCNV_FP_BIAS_B = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX + regCNVC_CFGid_FCNV_FP_BIAS_B, .FCNV_FP_SCALE_R = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX + regCNVC_CFGid_FCNV_FP_SCALE_R, .FCNV_FP_SCALE_G = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX + regCNVC_CFGid_FCNV_FP_SCALE_G, .FCNV_FP_SCALE_B = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX + regCNVC_CFGid_FCNV_FP_SCALE_B, .COLOR_KEYER_CONTROL = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_CONTROL, .COLOR_KEYER_ALPHA = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_ALPHA, .COLOR_KEYER_RED = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_RED, .COLOR_KEYER_GREEN = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_GREEN, .COLOR_KEYER_BLUE = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_BLUE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_CONTROL_BASE_IDX + regCURSOR0_id_CURSOR_CONTROL, .OBUF_MEM_PWR_CTRL = DCN_BASE__INST0_SEGregDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX + regDSCLid_OBUF_MEM_PWR_CTRL, .DSCL_MEM_PWR_STATUS = DCN_BASE__INST0_SEGregDSCLid_DSCL_MEM_PWR_STATUS_BASE_IDX + regDSCLid_DSCL_MEM_PWR_STATUS, .DSCL_MEM_PWR_CTRL = DCN_BASE__INST0_SEGregDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX + regDSCLid_DSCL_MEM_PWR_CTRL, .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_CONTROL_BASE_IDX + regCMid_CM_BLNDGAM_CONTROL, .CM_BLNDGAM_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_CNTL_B, .CM_BLNDGAM_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_CNTL_G, .CM_BLNDGAM_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_CNTL_R, .CM_BLNDGAM_RAMB_END_CNTL1_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL1_B, .CM_BLNDGAM_RAMB_END_CNTL2_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL2_B, .CM_BLNDGAM_RAMB_END_CNTL1_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL1_G, .CM_BLNDGAM_RAMB_END_CNTL2_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL2_G, .CM_BLNDGAM_RAMB_END_CNTL1_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL1_R, .CM_BLNDGAM_RAMB_END_CNTL2_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL2_R, .CM_BLNDGAM_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_0_1, .CM_BLNDGAM_RAMB_REGION_2_3 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_2_3, .CM_BLNDGAM_RAMB_REGION_4_5 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_4_5, .CM_BLNDGAM_RAMB_REGION_6_7 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_6_7, .CM_BLNDGAM_RAMB_REGION_8_9 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_8_9, .CM_BLNDGAM_RAMB_REGION_10_11 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_10_11, .CM_BLNDGAM_RAMB_REGION_12_13 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_12_13, .CM_BLNDGAM_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_14_15, .CM_BLNDGAM_RAMB_REGION_16_17 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_16_17, .CM_BLNDGAM_RAMB_REGION_18_19 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_18_19, .CM_BLNDGAM_RAMB_REGION_20_21 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_20_21, .CM_BLNDGAM_RAMB_REGION_22_23 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_22_23, .CM_BLNDGAM_RAMB_REGION_24_25 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_24_25, .CM_BLNDGAM_RAMB_REGION_26_27 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_26_27, .CM_BLNDGAM_RAMB_REGION_28_29 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_28_29, .CM_BLNDGAM_RAMB_REGION_30_31 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_30_31, .CM_BLNDGAM_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_32_33, .CM_BLNDGAM_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_CNTL_B, .CM_BLNDGAM_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_CNTL_G, .CM_BLNDGAM_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_CNTL_R, .CM_BLNDGAM_RAMA_END_CNTL1_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL1_B, .CM_BLNDGAM_RAMA_END_CNTL2_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL2_B, .CM_BLNDGAM_RAMA_END_CNTL1_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL1_G, .CM_BLNDGAM_RAMA_END_CNTL2_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL2_G, .CM_BLNDGAM_RAMA_END_CNTL1_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL1_R, .CM_BLNDGAM_RAMA_END_CNTL2_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL2_R, .CM_BLNDGAM_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_0_1, .CM_BLNDGAM_RAMA_REGION_2_3 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_2_3, .CM_BLNDGAM_RAMA_REGION_4_5 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_4_5, .CM_BLNDGAM_RAMA_REGION_6_7 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_6_7, .CM_BLNDGAM_RAMA_REGION_8_9 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_8_9, .CM_BLNDGAM_RAMA_REGION_10_11 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_10_11, .CM_BLNDGAM_RAMA_REGION_12_13 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_12_13, .CM_BLNDGAM_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_14_15, .CM_BLNDGAM_RAMA_REGION_16_17 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_16_17, .CM_BLNDGAM_RAMA_REGION_18_19 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_18_19, .CM_BLNDGAM_RAMA_REGION_20_21 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_20_21, .CM_BLNDGAM_RAMA_REGION_22_23 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_22_23, .CM_BLNDGAM_RAMA_REGION_24_25 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_24_25, .CM_BLNDGAM_RAMA_REGION_26_27 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_26_27, .CM_BLNDGAM_RAMA_REGION_28_29 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_28_29, .CM_BLNDGAM_RAMA_REGION_30_31 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_30_31, .CM_BLNDGAM_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_32_33, .CM_BLNDGAM_LUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_LUT_INDEX_BASE_IDX + regCMid_CM_BLNDGAM_LUT_INDEX, .CM_BLNDGAM_LUT_DATA = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_LUT_DATA_BASE_IDX + regCMid_CM_BLNDGAM_LUT_DATA, .CM_3DLUT_MODE = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_MODE_BASE_IDX + regCMid_CM_3DLUT_MODE, .CM_3DLUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_INDEX_BASE_IDX + regCMid_CM_3DLUT_INDEX, .CM_3DLUT_DATA = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_DATA_BASE_IDX + regCMid_CM_3DLUT_DATA, .CM_3DLUT_DATA_30BIT = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_DATA_30BIT_BASE_IDX + regCMid_CM_3DLUT_DATA_30BIT, .CM_3DLUT_READ_WRITE_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX + regCMid_CM_3DLUT_READ_WRITE_CONTROL, .CM_SHAPER_LUT_WRITE_EN_MASK = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX + regCMid_CM_SHAPER_LUT_WRITE_EN_MASK, .CM_SHAPER_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_CONTROL_BASE_IDX + regCMid_CM_SHAPER_CONTROL, .CM_SHAPER_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX + regCMid_CM_SHAPER_RAMB_START_CNTL_B, .CM_SHAPER_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX + regCMid_CM_SHAPER_RAMB_START_CNTL_G, .CM_SHAPER_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX + regCMid_CM_SHAPER_RAMB_START_CNTL_R, .CM_SHAPER_RAMB_END_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX + regCMid_CM_SHAPER_RAMB_END_CNTL_B, .CM_SHAPER_RAMB_END_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX + regCMid_CM_SHAPER_RAMB_END_CNTL_G, .CM_SHAPER_RAMB_END_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX + regCMid_CM_SHAPER_RAMB_END_CNTL_R, .CM_SHAPER_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_0_1, .CM_SHAPER_RAMB_REGION_2_3 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_2_3, .CM_SHAPER_RAMB_REGION_4_5 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_4_5, .CM_SHAPER_RAMB_REGION_6_7 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_6_7, .CM_SHAPER_RAMB_REGION_8_9 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_8_9, .CM_SHAPER_RAMB_REGION_10_11 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_10_11, .CM_SHAPER_RAMB_REGION_12_13 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_12_13, .CM_SHAPER_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_14_15, .CM_SHAPER_RAMB_REGION_16_17 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_16_17, .CM_SHAPER_RAMB_REGION_18_19 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_18_19, .CM_SHAPER_RAMB_REGION_20_21 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_20_21, .CM_SHAPER_RAMB_REGION_22_23 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_22_23, .CM_SHAPER_RAMB_REGION_24_25 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_24_25, .CM_SHAPER_RAMB_REGION_26_27 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_26_27, .CM_SHAPER_RAMB_REGION_28_29 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_28_29, .CM_SHAPER_RAMB_REGION_30_31 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_30_31, .CM_SHAPER_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_32_33, .CM_SHAPER_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX + regCMid_CM_SHAPER_RAMA_START_CNTL_B, .CM_SHAPER_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX + regCMid_CM_SHAPER_RAMA_START_CNTL_G, .CM_SHAPER_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX + regCMid_CM_SHAPER_RAMA_START_CNTL_R, .CM_SHAPER_RAMA_END_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX + regCMid_CM_SHAPER_RAMA_END_CNTL_B, .CM_SHAPER_RAMA_END_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX + regCMid_CM_SHAPER_RAMA_END_CNTL_G, .CM_SHAPER_RAMA_END_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX + regCMid_CM_SHAPER_RAMA_END_CNTL_R, .CM_SHAPER_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_0_1, .CM_SHAPER_RAMA_REGION_2_3 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_2_3, .CM_SHAPER_RAMA_REGION_4_5 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_4_5, .CM_SHAPER_RAMA_REGION_6_7 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_6_7, .CM_SHAPER_RAMA_REGION_8_9 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_8_9, .CM_SHAPER_RAMA_REGION_10_11 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_10_11, .CM_SHAPER_RAMA_REGION_12_13 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_12_13, .CM_SHAPER_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_14_15, .CM_SHAPER_RAMA_REGION_16_17 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_16_17, .CM_SHAPER_RAMA_REGION_18_19 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_18_19, .CM_SHAPER_RAMA_REGION_20_21 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_20_21, .CM_SHAPER_RAMA_REGION_22_23 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_22_23, .CM_SHAPER_RAMA_REGION_24_25 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_24_25, .CM_SHAPER_RAMA_REGION_26_27 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_26_27, .CM_SHAPER_RAMA_REGION_28_29 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_28_29, .CM_SHAPER_RAMA_REGION_30_31 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_30_31, .CM_SHAPER_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_32_33, .CM_SHAPER_LUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_LUT_INDEX_BASE_IDX + regCMid_CM_SHAPER_LUT_INDEX , .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_CONTROL_BASE_IDX + regCMid_CM_BLNDGAM_CONTROL, .CM_SHAPER_LUT_DATA = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_LUT_DATA_BASE_IDX + regCMid_CM_SHAPER_LUT_DATA, .CM_MEM_PWR_CTRL2 = DCN_BASE__INST0_SEGregCMid_CM_MEM_PWR_CTRL2_BASE_IDX + regCMid_CM_MEM_PWR_CTRL2, .CM_MEM_PWR_STATUS2 = DCN_BASE__INST0_SEGregCMid_CM_MEM_PWR_STATUS2_BASE_IDX + regCMid_CM_MEM_PWR_STATUS2, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, .CM_BLNDGAM_LUT_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_LUT_CONTROL_BASE_IDX + regCMid_CM_BLNDGAM_LUT_CONTROL,}\ | ||||
| 478 | [id] = {\ | ||||
| 479 | DPP_REG_LIST_DCN30(id).CM_DEALPHA = DCN_BASE__INST0_SEGregCMid_CM_DEALPHA_BASE_IDX + regCMid_CM_DEALPHA, .CM_MEM_PWR_STATUS = DCN_BASE__INST0_SEGregCMid_CM_MEM_PWR_STATUS_BASE_IDX + regCMid_CM_MEM_PWR_STATUS, .CM_BIAS_CR_R = DCN_BASE__INST0_SEGregCMid_CM_BIAS_CR_R_BASE_IDX + regCMid_CM_BIAS_CR_R, .CM_BIAS_Y_G_CB_B = DCN_BASE__INST0_SEGregCMid_CM_BIAS_Y_G_CB_B_BASE_IDX + regCMid_CM_BIAS_Y_G_CB_B, .PRE_DEGAM = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_DEGAM_BASE_IDX + regCNVC_CFGid_PRE_DEGAM, .CM_GAMCOR_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_CONTROL_BASE_IDX + regCMid_CM_GAMCOR_CONTROL, .CM_GAMCOR_LUT_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_LUT_CONTROL_BASE_IDX + regCMid_CM_GAMCOR_LUT_CONTROL, .CM_GAMCOR_LUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX + regCMid_CM_GAMCOR_LUT_INDEX, .CM_GAMCOR_LUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_LUT_INDEX_BASE_IDX + regCMid_CM_GAMCOR_LUT_INDEX, .CM_GAMCOR_LUT_DATA = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_LUT_DATA_BASE_IDX + regCMid_CM_GAMCOR_LUT_DATA, .CM_GAMCOR_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_CNTL_B, .CM_GAMCOR_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_CNTL_G, .CM_GAMCOR_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_CNTL_R, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, .CM_GAMCOR_RAMB_END_CNTL1_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL1_B, .CM_GAMCOR_RAMB_END_CNTL2_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL2_B, .CM_GAMCOR_RAMB_END_CNTL1_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL1_G, .CM_GAMCOR_RAMB_END_CNTL2_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL2_G, .CM_GAMCOR_RAMB_END_CNTL1_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL1_R, .CM_GAMCOR_RAMB_END_CNTL2_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_END_CNTL2_R, .CM_GAMCOR_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX + regCMid_CM_GAMCOR_RAMB_REGION_0_1, .CM_GAMCOR_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX + regCMid_CM_GAMCOR_RAMB_REGION_32_33, .CM_GAMCOR_RAMB_OFFSET_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_OFFSET_B, .CM_GAMCOR_RAMB_OFFSET_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_OFFSET_G, .CM_GAMCOR_RAMB_OFFSET_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_OFFSET_R, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_B, .CM_GAMCOR_RAMB_START_BASE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_G, .CM_GAMCOR_RAMB_START_BASE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMB_START_BASE_CNTL_R, .CM_GAMCOR_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_CNTL_B, .CM_GAMCOR_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_CNTL_G, .CM_GAMCOR_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_CNTL_R, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, .CM_GAMCOR_RAMA_END_CNTL1_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL1_B, .CM_GAMCOR_RAMA_END_CNTL2_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL2_B, .CM_GAMCOR_RAMA_END_CNTL1_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL1_G, .CM_GAMCOR_RAMA_END_CNTL2_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL2_G, .CM_GAMCOR_RAMA_END_CNTL1_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL1_R, .CM_GAMCOR_RAMA_END_CNTL2_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_END_CNTL2_R, .CM_GAMCOR_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX + regCMid_CM_GAMCOR_RAMA_REGION_0_1, .CM_GAMCOR_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX + regCMid_CM_GAMCOR_RAMA_REGION_32_33, .CM_GAMCOR_RAMA_OFFSET_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_OFFSET_B, .CM_GAMCOR_RAMA_OFFSET_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_OFFSET_G, .CM_GAMCOR_RAMA_OFFSET_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_OFFSET_R, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_B, .CM_GAMCOR_RAMA_START_BASE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_G, .CM_GAMCOR_RAMA_START_BASE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX + regCMid_CM_GAMCOR_RAMA_START_BASE_CNTL_R, .CM_GAMUT_REMAP_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX + regCMid_CM_GAMUT_REMAP_CONTROL, .CM_GAMUT_REMAP_C11_C12 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX + regCMid_CM_GAMUT_REMAP_C11_C12, .CM_GAMUT_REMAP_C13_C14 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX + regCMid_CM_GAMUT_REMAP_C13_C14, .CM_GAMUT_REMAP_C21_C22 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX + regCMid_CM_GAMUT_REMAP_C21_C22, .CM_GAMUT_REMAP_C23_C24 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX + regCMid_CM_GAMUT_REMAP_C23_C24, .CM_GAMUT_REMAP_C31_C32 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX + regCMid_CM_GAMUT_REMAP_C31_C32, .CM_GAMUT_REMAP_C33_C34 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX + regCMid_CM_GAMUT_REMAP_C33_C34, .CM_GAMUT_REMAP_B_C11_C12 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C11_C12, .CM_GAMUT_REMAP_B_C13_C14 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C13_C14, .CM_GAMUT_REMAP_B_C21_C22 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C21_C22, .CM_GAMUT_REMAP_B_C23_C24 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C23_C24, .CM_GAMUT_REMAP_B_C31_C32 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C31_C32, .CM_GAMUT_REMAP_B_C33_C34 = DCN_BASE__INST0_SEGregCMid_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX + regCMid_CM_GAMUT_REMAP_B_C33_C34, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = DCN_BASE__INST0_SEGregDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX + regDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = DCN_BASE__INST0_SEGregDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX + regDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, .OTG_H_BLANK = DCN_BASE__INST0_SEGregDSCLid_OTG_H_BLANK_BASE_IDX + regDSCLid_OTG_H_BLANK, .OTG_V_BLANK = DCN_BASE__INST0_SEGregDSCLid_OTG_V_BLANK_BASE_IDX + regDSCLid_OTG_V_BLANK, .SCL_MODE = DCN_BASE__INST0_SEGregDSCLid_SCL_MODE_BASE_IDX + regDSCLid_SCL_MODE, .LB_DATA_FORMAT = DCN_BASE__INST0_SEGregDSCLid_LB_DATA_FORMAT_BASE_IDX + regDSCLid_LB_DATA_FORMAT, .LB_MEMORY_CTRL = DCN_BASE__INST0_SEGregDSCLid_LB_MEMORY_CTRL_BASE_IDX + regDSCLid_LB_MEMORY_CTRL, .DSCL_AUTOCAL = DCN_BASE__INST0_SEGregDSCLid_DSCL_AUTOCAL_BASE_IDX + regDSCLid_DSCL_AUTOCAL, .SCL_TAP_CONTROL = DCN_BASE__INST0_SEGregDSCLid_SCL_TAP_CONTROL_BASE_IDX + regDSCLid_SCL_TAP_CONTROL, .SCL_COEF_RAM_TAP_SELECT = DCN_BASE__INST0_SEGregDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX + regDSCLid_SCL_COEF_RAM_TAP_SELECT, .SCL_COEF_RAM_TAP_DATA = DCN_BASE__INST0_SEGregDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX + regDSCLid_SCL_COEF_RAM_TAP_DATA, .DSCL_2TAP_CONTROL = DCN_BASE__INST0_SEGregDSCLid_DSCL_2TAP_CONTROL_BASE_IDX + regDSCLid_DSCL_2TAP_CONTROL, .MPC_SIZE = DCN_BASE__INST0_SEGregDSCLid_MPC_SIZE_BASE_IDX + regDSCLid_MPC_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGregDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX + regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGregDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX + regDSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_SCALE_RATIO_C = DCN_BASE__INST0_SEGregDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX + regDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C, .SCL_VERT_FILTER_SCALE_RATIO_C = DCN_BASE__INST0_SEGregDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX + regDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C, .SCL_HORZ_FILTER_INIT = DCN_BASE__INST0_SEGregDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX + regDSCLid_SCL_HORZ_FILTER_INIT, .SCL_HORZ_FILTER_INIT_C = DCN_BASE__INST0_SEGregDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX + regDSCLid_SCL_HORZ_FILTER_INIT_C, .SCL_VERT_FILTER_INIT = DCN_BASE__INST0_SEGregDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX + regDSCLid_SCL_VERT_FILTER_INIT, .SCL_VERT_FILTER_INIT_C = DCN_BASE__INST0_SEGregDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX + regDSCLid_SCL_VERT_FILTER_INIT_C, .RECOUT_START = DCN_BASE__INST0_SEGregDSCLid_RECOUT_START_BASE_IDX + regDSCLid_RECOUT_START, .RECOUT_SIZE = DCN_BASE__INST0_SEGregDSCLid_RECOUT_SIZE_BASE_IDX + regDSCLid_RECOUT_SIZE, .PRE_DEALPHA = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_DEALPHA_BASE_IDX + regCNVC_CFGid_PRE_DEALPHA, .PRE_REALPHA = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_REALPHA_BASE_IDX + regCNVC_CFGid_PRE_REALPHA, .PRE_CSC_MODE = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_MODE_BASE_IDX + regCNVC_CFGid_PRE_CSC_MODE, .PRE_CSC_C11_C12 = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_C11_C12_BASE_IDX + regCNVC_CFGid_PRE_CSC_C11_C12, .PRE_CSC_C33_C34 = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_C33_C34_BASE_IDX + regCNVC_CFGid_PRE_CSC_C33_C34, .PRE_CSC_B_C11_C12 = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_B_C11_C12_BASE_IDX + regCNVC_CFGid_PRE_CSC_B_C11_C12, .PRE_CSC_B_C33_C34 = DCN_BASE__INST0_SEGregCNVC_CFGid_PRE_CSC_B_C33_C34_BASE_IDX + regCNVC_CFGid_PRE_CSC_B_C33_C34, .CM_POST_CSC_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_CONTROL_BASE_IDX + regCMid_CM_POST_CSC_CONTROL, .CM_POST_CSC_C11_C12 = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_C11_C12_BASE_IDX + regCMid_CM_POST_CSC_C11_C12, .CM_POST_CSC_C33_C34 = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_C33_C34_BASE_IDX + regCMid_CM_POST_CSC_C33_C34, .CM_POST_CSC_B_C11_C12 = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_B_C11_C12_BASE_IDX + regCMid_CM_POST_CSC_B_C11_C12, .CM_POST_CSC_B_C33_C34 = DCN_BASE__INST0_SEGregCMid_CM_POST_CSC_B_C33_C34_BASE_IDX + regCMid_CM_POST_CSC_B_C33_C34, .CM_MEM_PWR_CTRL = DCN_BASE__INST0_SEGregCMid_CM_MEM_PWR_CTRL_BASE_IDX + regCMid_CM_MEM_PWR_CTRL, .CM_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_CONTROL_BASE_IDX + regCMid_CM_CONTROL, .FORMAT_CONTROL = DCN_BASE__INST0_SEGregCNVC_CFGid_FORMAT_CONTROL_BASE_IDX + regCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DCN_BASE__INST0_SEGregCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX + regCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL = DCN_BASE__INST0_SEGregCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + regCNVC_CURid_CURSOR0_CONTROL , .CURSOR0_COLOR0 = DCN_BASE__INST0_SEGregCNVC_CURid_CURSOR0_COLOR0_BASE_IDX + regCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DCN_BASE__INST0_SEGregCNVC_CURid_CURSOR0_COLOR1_BASE_IDX + regCNVC_CURid_CURSOR0_COLOR1, .CURSOR0_FP_SCALE_BIAS = DCN_BASE__INST0_SEGregCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX + regCNVC_CURid_CURSOR0_FP_SCALE_BIAS, .DPP_CONTROL = DCN_BASE__INST0_SEGregDPP_TOPid_DPP_CONTROL_BASE_IDX + regDPP_TOPid_DPP_CONTROL, .CM_HDR_MULT_COEF = DCN_BASE__INST0_SEGregCMid_CM_HDR_MULT_COEF_BASE_IDX + regCMid_CM_HDR_MULT_COEF, .CURSOR_CONTROL = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_CONTROL_BASE_IDX + regCURSOR0_id_CURSOR_CONTROL, .ALPHA_2BIT_LUT = DCN_BASE__INST0_SEGregCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX + regCNVC_CFGid_ALPHA_2BIT_LUT, .FCNV_FP_BIAS_R = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX + regCNVC_CFGid_FCNV_FP_BIAS_R, .FCNV_FP_BIAS_G = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX + regCNVC_CFGid_FCNV_FP_BIAS_G, .FCNV_FP_BIAS_B = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX + regCNVC_CFGid_FCNV_FP_BIAS_B, .FCNV_FP_SCALE_R = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX + regCNVC_CFGid_FCNV_FP_SCALE_R, .FCNV_FP_SCALE_G = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX + regCNVC_CFGid_FCNV_FP_SCALE_G, .FCNV_FP_SCALE_B = DCN_BASE__INST0_SEGregCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX + regCNVC_CFGid_FCNV_FP_SCALE_B, .COLOR_KEYER_CONTROL = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_CONTROL, .COLOR_KEYER_ALPHA = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_ALPHA, .COLOR_KEYER_RED = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_RED, .COLOR_KEYER_GREEN = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_GREEN, .COLOR_KEYER_BLUE = DCN_BASE__INST0_SEGregCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX + regCNVC_CFGid_COLOR_KEYER_BLUE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_CONTROL_BASE_IDX + regCURSOR0_id_CURSOR_CONTROL, .OBUF_MEM_PWR_CTRL = DCN_BASE__INST0_SEGregDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX + regDSCLid_OBUF_MEM_PWR_CTRL, .DSCL_MEM_PWR_STATUS = DCN_BASE__INST0_SEGregDSCLid_DSCL_MEM_PWR_STATUS_BASE_IDX + regDSCLid_DSCL_MEM_PWR_STATUS, .DSCL_MEM_PWR_CTRL = DCN_BASE__INST0_SEGregDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX + regDSCLid_DSCL_MEM_PWR_CTRL, .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_CONTROL_BASE_IDX + regCMid_CM_BLNDGAM_CONTROL, .CM_BLNDGAM_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_CNTL_B, .CM_BLNDGAM_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_CNTL_G, .CM_BLNDGAM_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_CNTL_R, .CM_BLNDGAM_RAMB_END_CNTL1_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL1_B, .CM_BLNDGAM_RAMB_END_CNTL2_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL2_B, .CM_BLNDGAM_RAMB_END_CNTL1_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL1_G, .CM_BLNDGAM_RAMB_END_CNTL2_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL2_G, .CM_BLNDGAM_RAMB_END_CNTL1_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL1_R, .CM_BLNDGAM_RAMB_END_CNTL2_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_END_CNTL2_R, .CM_BLNDGAM_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_0_1, .CM_BLNDGAM_RAMB_REGION_2_3 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_2_3, .CM_BLNDGAM_RAMB_REGION_4_5 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_4_5, .CM_BLNDGAM_RAMB_REGION_6_7 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_6_7, .CM_BLNDGAM_RAMB_REGION_8_9 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_8_9, .CM_BLNDGAM_RAMB_REGION_10_11 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_10_11, .CM_BLNDGAM_RAMB_REGION_12_13 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_12_13, .CM_BLNDGAM_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_14_15, .CM_BLNDGAM_RAMB_REGION_16_17 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_16_17, .CM_BLNDGAM_RAMB_REGION_18_19 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_18_19, .CM_BLNDGAM_RAMB_REGION_20_21 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_20_21, .CM_BLNDGAM_RAMB_REGION_22_23 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_22_23, .CM_BLNDGAM_RAMB_REGION_24_25 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_24_25, .CM_BLNDGAM_RAMB_REGION_26_27 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_26_27, .CM_BLNDGAM_RAMB_REGION_28_29 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_28_29, .CM_BLNDGAM_RAMB_REGION_30_31 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_30_31, .CM_BLNDGAM_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_REGION_32_33, .CM_BLNDGAM_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_CNTL_B, .CM_BLNDGAM_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_CNTL_G, .CM_BLNDGAM_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_CNTL_R, .CM_BLNDGAM_RAMA_END_CNTL1_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL1_B, .CM_BLNDGAM_RAMA_END_CNTL2_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL2_B, .CM_BLNDGAM_RAMA_END_CNTL1_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL1_G, .CM_BLNDGAM_RAMA_END_CNTL2_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL2_G, .CM_BLNDGAM_RAMA_END_CNTL1_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL1_R, .CM_BLNDGAM_RAMA_END_CNTL2_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_END_CNTL2_R, .CM_BLNDGAM_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_0_1, .CM_BLNDGAM_RAMA_REGION_2_3 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_2_3, .CM_BLNDGAM_RAMA_REGION_4_5 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_4_5, .CM_BLNDGAM_RAMA_REGION_6_7 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_6_7, .CM_BLNDGAM_RAMA_REGION_8_9 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_8_9, .CM_BLNDGAM_RAMA_REGION_10_11 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_10_11, .CM_BLNDGAM_RAMA_REGION_12_13 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_12_13, .CM_BLNDGAM_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_14_15, .CM_BLNDGAM_RAMA_REGION_16_17 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_16_17, .CM_BLNDGAM_RAMA_REGION_18_19 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_18_19, .CM_BLNDGAM_RAMA_REGION_20_21 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_20_21, .CM_BLNDGAM_RAMA_REGION_22_23 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_22_23, .CM_BLNDGAM_RAMA_REGION_24_25 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_24_25, .CM_BLNDGAM_RAMA_REGION_26_27 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_26_27, .CM_BLNDGAM_RAMA_REGION_28_29 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_28_29, .CM_BLNDGAM_RAMA_REGION_30_31 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_30_31, .CM_BLNDGAM_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_REGION_32_33, .CM_BLNDGAM_LUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_LUT_INDEX_BASE_IDX + regCMid_CM_BLNDGAM_LUT_INDEX, .CM_BLNDGAM_LUT_DATA = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_LUT_DATA_BASE_IDX + regCMid_CM_BLNDGAM_LUT_DATA, .CM_3DLUT_MODE = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_MODE_BASE_IDX + regCMid_CM_3DLUT_MODE, .CM_3DLUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_INDEX_BASE_IDX + regCMid_CM_3DLUT_INDEX, .CM_3DLUT_DATA = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_DATA_BASE_IDX + regCMid_CM_3DLUT_DATA, .CM_3DLUT_DATA_30BIT = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_DATA_30BIT_BASE_IDX + regCMid_CM_3DLUT_DATA_30BIT, .CM_3DLUT_READ_WRITE_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX + regCMid_CM_3DLUT_READ_WRITE_CONTROL, .CM_SHAPER_LUT_WRITE_EN_MASK = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX + regCMid_CM_SHAPER_LUT_WRITE_EN_MASK, .CM_SHAPER_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_CONTROL_BASE_IDX + regCMid_CM_SHAPER_CONTROL, .CM_SHAPER_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX + regCMid_CM_SHAPER_RAMB_START_CNTL_B, .CM_SHAPER_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX + regCMid_CM_SHAPER_RAMB_START_CNTL_G, .CM_SHAPER_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX + regCMid_CM_SHAPER_RAMB_START_CNTL_R, .CM_SHAPER_RAMB_END_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX + regCMid_CM_SHAPER_RAMB_END_CNTL_B, .CM_SHAPER_RAMB_END_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX + regCMid_CM_SHAPER_RAMB_END_CNTL_G, .CM_SHAPER_RAMB_END_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX + regCMid_CM_SHAPER_RAMB_END_CNTL_R, .CM_SHAPER_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_0_1, .CM_SHAPER_RAMB_REGION_2_3 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_2_3, .CM_SHAPER_RAMB_REGION_4_5 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_4_5, .CM_SHAPER_RAMB_REGION_6_7 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_6_7, .CM_SHAPER_RAMB_REGION_8_9 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_8_9, .CM_SHAPER_RAMB_REGION_10_11 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_10_11, .CM_SHAPER_RAMB_REGION_12_13 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_12_13, .CM_SHAPER_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_14_15, .CM_SHAPER_RAMB_REGION_16_17 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_16_17, .CM_SHAPER_RAMB_REGION_18_19 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_18_19, .CM_SHAPER_RAMB_REGION_20_21 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_20_21, .CM_SHAPER_RAMB_REGION_22_23 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_22_23, .CM_SHAPER_RAMB_REGION_24_25 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_24_25, .CM_SHAPER_RAMB_REGION_26_27 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_26_27, .CM_SHAPER_RAMB_REGION_28_29 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_28_29, .CM_SHAPER_RAMB_REGION_30_31 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_30_31, .CM_SHAPER_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX + regCMid_CM_SHAPER_RAMB_REGION_32_33, .CM_SHAPER_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX + regCMid_CM_SHAPER_RAMA_START_CNTL_B, .CM_SHAPER_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX + regCMid_CM_SHAPER_RAMA_START_CNTL_G, .CM_SHAPER_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX + regCMid_CM_SHAPER_RAMA_START_CNTL_R, .CM_SHAPER_RAMA_END_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX + regCMid_CM_SHAPER_RAMA_END_CNTL_B, .CM_SHAPER_RAMA_END_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX + regCMid_CM_SHAPER_RAMA_END_CNTL_G, .CM_SHAPER_RAMA_END_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX + regCMid_CM_SHAPER_RAMA_END_CNTL_R, .CM_SHAPER_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_0_1, .CM_SHAPER_RAMA_REGION_2_3 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_2_3, .CM_SHAPER_RAMA_REGION_4_5 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_4_5, .CM_SHAPER_RAMA_REGION_6_7 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_6_7, .CM_SHAPER_RAMA_REGION_8_9 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_8_9, .CM_SHAPER_RAMA_REGION_10_11 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_10_11, .CM_SHAPER_RAMA_REGION_12_13 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_12_13, .CM_SHAPER_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_14_15, .CM_SHAPER_RAMA_REGION_16_17 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_16_17, .CM_SHAPER_RAMA_REGION_18_19 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_18_19, .CM_SHAPER_RAMA_REGION_20_21 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_20_21, .CM_SHAPER_RAMA_REGION_22_23 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_22_23, .CM_SHAPER_RAMA_REGION_24_25 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_24_25, .CM_SHAPER_RAMA_REGION_26_27 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_26_27, .CM_SHAPER_RAMA_REGION_28_29 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_28_29, .CM_SHAPER_RAMA_REGION_30_31 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_30_31, .CM_SHAPER_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX + regCMid_CM_SHAPER_RAMA_REGION_32_33, .CM_SHAPER_LUT_INDEX = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_LUT_INDEX_BASE_IDX + regCMid_CM_SHAPER_LUT_INDEX , .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_CONTROL_BASE_IDX + regCMid_CM_BLNDGAM_CONTROL, .CM_SHAPER_LUT_DATA = DCN_BASE__INST0_SEGregCMid_CM_SHAPER_LUT_DATA_BASE_IDX + regCMid_CM_SHAPER_LUT_DATA, .CM_MEM_PWR_CTRL2 = DCN_BASE__INST0_SEGregCMid_CM_MEM_PWR_CTRL2_BASE_IDX + regCMid_CM_MEM_PWR_CTRL2, .CM_MEM_PWR_STATUS2 = DCN_BASE__INST0_SEGregCMid_CM_MEM_PWR_STATUS2_BASE_IDX + regCMid_CM_MEM_PWR_STATUS2, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX + regCMid_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, .CM_BLNDGAM_LUT_CONTROL = DCN_BASE__INST0_SEGregCMid_CM_BLNDGAM_LUT_CONTROL_BASE_IDX + regCMid_CM_BLNDGAM_LUT_CONTROL,\ | ||||
| 480 | } | ||||
| 481 | |||||
| 482 | static const struct dcn3_dpp_registers dpp_regs[] = { | ||||
| 483 | dpp_regs(0)[0] = { .CM_DEALPHA = 0x000034C0 + 0x0dd5, .CM_MEM_PWR_STATUS = 0x000034C0 + 0x0dd3, .CM_BIAS_CR_R = 0x000034C0 + 0x0d3b, . CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x0d3c, .PRE_DEGAM = 0x000034C0 + 0x0ced, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x0d3d, .CM_GAMCOR_LUT_CONTROL = 0x000034C0 + 0x0d40, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x0d3e , .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x0d3e, .CM_GAMCOR_LUT_DATA = 0x000034C0 + 0x0d3f, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0 + 0x0d64, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x0d65 , .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x0d66, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x0d67, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x0d68, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x0d69 , .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x0d6d, .CM_GAMCOR_RAMB_END_CNTL2_B = 0x000034C0 + 0x0d6e, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0 + 0x0d6f, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x0d70, .CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x0d71, .CM_GAMCOR_RAMB_END_CNTL2_R = 0x000034C0 + 0x0d72, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0 + 0x0d76, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x0d86 , .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x0d73, .CM_GAMCOR_RAMB_OFFSET_G = 0x000034C0 + 0x0d74, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0 + 0x0d75, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x0d6a , .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x0d6b, .CM_GAMCOR_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x0d6c, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0 + 0x0d41, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x0d42 , .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x0d43, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x0d44, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x0d45, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x0d46 , .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x0d4a, .CM_GAMCOR_RAMA_END_CNTL2_B = 0x000034C0 + 0x0d4b, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0 + 0x0d4c, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x0d4d, .CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x0d4e, .CM_GAMCOR_RAMA_END_CNTL2_R = 0x000034C0 + 0x0d4f, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0 + 0x0d53, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x0d63 , .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x0d50, .CM_GAMCOR_RAMA_OFFSET_G = 0x000034C0 + 0x0d51, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0 + 0x0d52, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x0d47 , .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x0d48, .CM_GAMCOR_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x0d49, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x0d2e, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x0d2f, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x0d30, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x0d31, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x0d32, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x0d33, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x0d34, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x0d35, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x0d36, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x0d37, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x0d38, . CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x0d39, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x0d3a, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x0d0d, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0d0e , .OTG_H_BLANK = 0x000034C0 + 0x0d0f, .OTG_V_BLANK = 0x000034C0 + 0x0d10, .SCL_MODE = 0x000034C0 + 0x0cfb, .LB_DATA_FORMAT = 0x000034C0 + 0x0d14, .LB_MEMORY_CTRL = 0x000034C0 + 0x0d15, . DSCL_AUTOCAL = 0x000034C0 + 0x0d0c, .SCL_TAP_CONTROL = 0x000034C0 + 0x0cfc, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0cf9, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x0cfa, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0cfe , .MPC_SIZE = 0x000034C0 + 0x0d13, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x0d00, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0d04, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0d02 , .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0d07, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x0d01, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x0d03, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0d05, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x0d08, .RECOUT_START = 0x000034C0 + 0x0d11, . RECOUT_SIZE = 0x000034C0 + 0x0d12, .PRE_DEALPHA = 0x000034C0 + 0x0cde, .PRE_REALPHA = 0x000034C0 + 0x0cee, .PRE_CSC_MODE = 0x000034C0 + 0x0cdf, .PRE_CSC_C11_C12 = 0x000034C0 + 0x0ce0, .PRE_CSC_C33_C34 = 0x000034C0 + 0x0ce5, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x0ce6 , .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x0ceb, .CM_POST_CSC_CONTROL = 0x000034C0 + 0x0d21, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x0d22 , .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x0d27, .CM_POST_CSC_B_C11_C12 = 0x000034C0 + 0x0d28, .CM_POST_CSC_B_C33_C34 = 0x000034C0 + 0x0d2d, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x0dd2, .CM_CONTROL = 0x000034C0 + 0x0d20, .FORMAT_CONTROL = 0x000034C0 + 0x0cd0, . CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0ccf, .CURSOR0_CONTROL = 0x000034C0 + 0x0cf1, .CURSOR0_COLOR0 = 0x000034C0 + 0x0cf2 , .CURSOR0_COLOR1 = 0x000034C0 + 0x0cf3, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0cf4, .DPP_CONTROL = 0x000034C0 + 0x0cc5, . CM_HDR_MULT_COEF = 0x000034C0 + 0x0dd1, .CURSOR_CONTROL = 0x000034C0 + 0x0678, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0cdd, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0cd1, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0cd2 , .FCNV_FP_BIAS_B = 0x000034C0 + 0x0cd3, .FCNV_FP_SCALE_R = 0x000034C0 + 0x0cd4, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0cd5, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0cd6, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0cd7 , .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0cd8, .COLOR_KEYER_RED = 0x000034C0 + 0x0cd9, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0cda , .COLOR_KEYER_BLUE = 0x000034C0 + 0x0cdb, .CURSOR_CONTROL = 0x000034C0 + 0x0678, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0d1a, .DSCL_MEM_PWR_STATUS = 0x000034C0 + 0x0d18, .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0d17 , .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0d87, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0dae, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x0daf, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x0db0 , .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0db7, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0db8, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x0db9, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x0dba , .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0dbb, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0dbc, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x0dc0, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x0dc1, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x0dc2, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x0dc3, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x0dc4, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x0dc5 , .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x0dc6, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x0dc7, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x0dc8, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x0dc9 , .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x0dca, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x0dcb, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x0dcc, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x0dcd , .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x0dce, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x0dcf, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x0dd0, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x0d8b , .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0d8c, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0d8d, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x0d94, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x0d95 , .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0d96, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0d97, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x0d98, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x0d99 , .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0d9d, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x0d9e, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x0d9f, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x0da0, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x0da1, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x0da2, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x0da3, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0da4 , .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x0da5, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x0da6, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x0da7, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x0da8 , .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x0da9, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x0daa, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x0dab, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x0dac , .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x0dad, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x0d88, .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x0d89 , .CM_3DLUT_MODE = 0x000034C0 + 0x0e10, .CM_3DLUT_INDEX = 0x000034C0 + 0x0e11, .CM_3DLUT_DATA = 0x000034C0 + 0x0e12, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x0e13, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x0e14, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0ddf , .CM_SHAPER_CONTROL = 0x000034C0 + 0x0dd7, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x0df7, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x0df8, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x0df9 , .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x0dfa, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x0dfb, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x0dfc, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x0dfd, . CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x0dfe, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x0dff, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x0e00, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x0e01, . CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x0e02, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x0e03, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x0e04, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x0e05 , .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x0e06, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x0e07, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x0e08, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x0e09 , .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x0e0a, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x0e0b, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x0e0c, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x0e0d , .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x0de0, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x0de1, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x0de2, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x0de3, . CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x0de4, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x0de5, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x0de6, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x0de7, . CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x0de8, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x0de9, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x0dea, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x0deb , .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x0dec, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x0ded, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x0dee, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x0def , .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x0df0, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x0df1, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x0df2, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x0df3 , .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x0df4, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x0df5, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x0df6, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x0ddd, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0d87, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x0dde , .CM_MEM_PWR_CTRL2 = 0x000034C0 + 0x0e0e, .CM_MEM_PWR_STATUS2 = 0x000034C0 + 0x0e0f, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x0d8e, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x0d8f, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x0d90, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x0db1 , .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x0db2, . CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x0db3, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x0d8a,}, | ||||
| 484 | dpp_regs(1)[1] = { .CM_DEALPHA = 0x000034C0 + 0x0f40, .CM_MEM_PWR_STATUS = 0x000034C0 + 0x0f3e, .CM_BIAS_CR_R = 0x000034C0 + 0x0ea6, . CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x0ea7, .PRE_DEGAM = 0x000034C0 + 0x0e58, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x0ea8, .CM_GAMCOR_LUT_CONTROL = 0x000034C0 + 0x0eab, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x0ea9 , .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x0ea9, .CM_GAMCOR_LUT_DATA = 0x000034C0 + 0x0eaa, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0 + 0x0ecf, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x0ed0 , .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x0ed1, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x0ed2, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x0ed3, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x0ed4 , .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x0ed8, .CM_GAMCOR_RAMB_END_CNTL2_B = 0x000034C0 + 0x0ed9, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0 + 0x0eda, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x0edb, .CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x0edc, .CM_GAMCOR_RAMB_END_CNTL2_R = 0x000034C0 + 0x0edd, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0 + 0x0ee1, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x0ef1 , .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x0ede, .CM_GAMCOR_RAMB_OFFSET_G = 0x000034C0 + 0x0edf, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0 + 0x0ee0, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x0ed5 , .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x0ed6, .CM_GAMCOR_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x0ed7, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0 + 0x0eac, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x0ead , .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x0eae, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x0eaf, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x0eb0, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x0eb1 , .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x0eb5, .CM_GAMCOR_RAMA_END_CNTL2_B = 0x000034C0 + 0x0eb6, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0 + 0x0eb7, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x0eb8, .CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x0eb9, .CM_GAMCOR_RAMA_END_CNTL2_R = 0x000034C0 + 0x0eba, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0 + 0x0ebe, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x0ece , .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x0ebb, .CM_GAMCOR_RAMA_OFFSET_G = 0x000034C0 + 0x0ebc, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0 + 0x0ebd, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x0eb2 , .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x0eb3, .CM_GAMCOR_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x0eb4, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x0e99, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x0e9a, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x0e9b, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x0e9c, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x0e9d, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x0e9e, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x0e9f, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x0ea0, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x0ea1, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x0ea2, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x0ea3, . CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x0ea4, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x0ea5, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x0e78, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0e79 , .OTG_H_BLANK = 0x000034C0 + 0x0e7a, .OTG_V_BLANK = 0x000034C0 + 0x0e7b, .SCL_MODE = 0x000034C0 + 0x0e66, .LB_DATA_FORMAT = 0x000034C0 + 0x0e7f, .LB_MEMORY_CTRL = 0x000034C0 + 0x0e80, . DSCL_AUTOCAL = 0x000034C0 + 0x0e77, .SCL_TAP_CONTROL = 0x000034C0 + 0x0e67, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0e64, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x0e65, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0e69 , .MPC_SIZE = 0x000034C0 + 0x0e7e, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x0e6b, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0e6f, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0e6d , .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0e72, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x0e6c, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x0e6e, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0e70, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x0e73, .RECOUT_START = 0x000034C0 + 0x0e7c, . RECOUT_SIZE = 0x000034C0 + 0x0e7d, .PRE_DEALPHA = 0x000034C0 + 0x0e49, .PRE_REALPHA = 0x000034C0 + 0x0e59, .PRE_CSC_MODE = 0x000034C0 + 0x0e4a, .PRE_CSC_C11_C12 = 0x000034C0 + 0x0e4b, .PRE_CSC_C33_C34 = 0x000034C0 + 0x0e50, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x0e51 , .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x0e56, .CM_POST_CSC_CONTROL = 0x000034C0 + 0x0e8c, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x0e8d , .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x0e92, .CM_POST_CSC_B_C11_C12 = 0x000034C0 + 0x0e93, .CM_POST_CSC_B_C33_C34 = 0x000034C0 + 0x0e98, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x0f3d, .CM_CONTROL = 0x000034C0 + 0x0e8b, .FORMAT_CONTROL = 0x000034C0 + 0x0e3b, . CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0e3a, .CURSOR0_CONTROL = 0x000034C0 + 0x0e5c, .CURSOR0_COLOR0 = 0x000034C0 + 0x0e5d , .CURSOR0_COLOR1 = 0x000034C0 + 0x0e5e, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0e5f, .DPP_CONTROL = 0x000034C0 + 0x0e30, . CM_HDR_MULT_COEF = 0x000034C0 + 0x0f3c, .CURSOR_CONTROL = 0x000034C0 + 0x0754, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0e48, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0e3c, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0e3d , .FCNV_FP_BIAS_B = 0x000034C0 + 0x0e3e, .FCNV_FP_SCALE_R = 0x000034C0 + 0x0e3f, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0e40, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0e41, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0e42 , .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0e43, .COLOR_KEYER_RED = 0x000034C0 + 0x0e44, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0e45 , .COLOR_KEYER_BLUE = 0x000034C0 + 0x0e46, .CURSOR_CONTROL = 0x000034C0 + 0x0754, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0e85, .DSCL_MEM_PWR_STATUS = 0x000034C0 + 0x0e83, .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0e82 , .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0ef2, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0f19, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x0f1a, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x0f1b , .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0f22, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0f23, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x0f24, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x0f25 , .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0f26, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0f27, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x0f2b, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x0f2c, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x0f2d, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x0f2e, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x0f2f, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x0f30 , .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x0f31, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x0f32, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x0f33, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x0f34 , .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x0f35, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x0f36, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x0f37, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x0f38 , .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x0f39, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x0f3a, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x0f3b, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x0ef6 , .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0ef7, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0ef8, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x0eff, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x0f00 , .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0f01, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0f02, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x0f03, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x0f04 , .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0f08, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x0f09, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x0f0a, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x0f0b, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x0f0c, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x0f0d, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x0f0e, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0f0f , .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x0f10, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x0f11, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x0f12, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x0f13 , .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x0f14, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x0f15, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x0f16, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x0f17 , .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x0f18, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x0ef3, .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x0ef4 , .CM_3DLUT_MODE = 0x000034C0 + 0x0f7b, .CM_3DLUT_INDEX = 0x000034C0 + 0x0f7c, .CM_3DLUT_DATA = 0x000034C0 + 0x0f7d, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x0f7e, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x0f7f, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0f4a , .CM_SHAPER_CONTROL = 0x000034C0 + 0x0f42, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x0f62, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x0f63, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x0f64 , .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x0f65, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x0f66, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x0f67, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x0f68, . CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x0f69, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x0f6a, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x0f6b, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x0f6c, . CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x0f6d, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x0f6e, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x0f6f, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x0f70 , .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x0f71, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x0f72, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x0f73, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x0f74 , .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x0f75, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x0f76, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x0f77, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x0f78 , .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x0f4b, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x0f4c, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x0f4d, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x0f4e, . CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x0f4f, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x0f50, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x0f51, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x0f52, . CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x0f53, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x0f54, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x0f55, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x0f56 , .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x0f57, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x0f58, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x0f59, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x0f5a , .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x0f5b, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x0f5c, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x0f5d, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x0f5e , .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x0f5f, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x0f60, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x0f61, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x0f48, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0ef2, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x0f49 , .CM_MEM_PWR_CTRL2 = 0x000034C0 + 0x0f79, .CM_MEM_PWR_STATUS2 = 0x000034C0 + 0x0f7a, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x0ef9, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x0efa, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x0efb, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x0f1c , .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x0f1d, . CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x0f1e, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x0ef5,}, | ||||
| 485 | dpp_regs(2)[2] = { .CM_DEALPHA = 0x000034C0 + 0x10ab, .CM_MEM_PWR_STATUS = 0x000034C0 + 0x10a9, .CM_BIAS_CR_R = 0x000034C0 + 0x1011, . CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x1012, .PRE_DEGAM = 0x000034C0 + 0x0fc3, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x1013, .CM_GAMCOR_LUT_CONTROL = 0x000034C0 + 0x1016, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x1014 , .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x1014, .CM_GAMCOR_LUT_DATA = 0x000034C0 + 0x1015, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0 + 0x103a, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x103b , .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x103c, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x103d, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x103e, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x103f , .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x1043, .CM_GAMCOR_RAMB_END_CNTL2_B = 0x000034C0 + 0x1044, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0 + 0x1045, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x1046, .CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x1047, .CM_GAMCOR_RAMB_END_CNTL2_R = 0x000034C0 + 0x1048, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0 + 0x104c, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x105c , .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x1049, .CM_GAMCOR_RAMB_OFFSET_G = 0x000034C0 + 0x104a, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0 + 0x104b, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x1040 , .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x1041, .CM_GAMCOR_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x1042, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0 + 0x1017, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x1018 , .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x1019, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x101a, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x101b, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x101c , .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x1020, .CM_GAMCOR_RAMA_END_CNTL2_B = 0x000034C0 + 0x1021, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0 + 0x1022, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x1023, .CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x1024, .CM_GAMCOR_RAMA_END_CNTL2_R = 0x000034C0 + 0x1025, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0 + 0x1029, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x1039 , .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x1026, .CM_GAMCOR_RAMA_OFFSET_G = 0x000034C0 + 0x1027, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0 + 0x1028, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x101d , .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x101e, .CM_GAMCOR_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x101f, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x1004, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x1005, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x1006, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x1007, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x1008, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x1009, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x100a, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x100b, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x100c, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x100d, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x100e, . CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x100f, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x1010, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x0fe3, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0fe4 , .OTG_H_BLANK = 0x000034C0 + 0x0fe5, .OTG_V_BLANK = 0x000034C0 + 0x0fe6, .SCL_MODE = 0x000034C0 + 0x0fd1, .LB_DATA_FORMAT = 0x000034C0 + 0x0fea, .LB_MEMORY_CTRL = 0x000034C0 + 0x0feb, . DSCL_AUTOCAL = 0x000034C0 + 0x0fe2, .SCL_TAP_CONTROL = 0x000034C0 + 0x0fd2, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0fcf, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x0fd0, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0fd4 , .MPC_SIZE = 0x000034C0 + 0x0fe9, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x0fd6, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0fda, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0fd8 , .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0fdd, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x0fd7, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x0fd9, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0fdb, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x0fde, .RECOUT_START = 0x000034C0 + 0x0fe7, . RECOUT_SIZE = 0x000034C0 + 0x0fe8, .PRE_DEALPHA = 0x000034C0 + 0x0fb4, .PRE_REALPHA = 0x000034C0 + 0x0fc4, .PRE_CSC_MODE = 0x000034C0 + 0x0fb5, .PRE_CSC_C11_C12 = 0x000034C0 + 0x0fb6, .PRE_CSC_C33_C34 = 0x000034C0 + 0x0fbb, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x0fbc , .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x0fc1, .CM_POST_CSC_CONTROL = 0x000034C0 + 0x0ff7, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x0ff8 , .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x0ffd, .CM_POST_CSC_B_C11_C12 = 0x000034C0 + 0x0ffe, .CM_POST_CSC_B_C33_C34 = 0x000034C0 + 0x1003, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x10a8, .CM_CONTROL = 0x000034C0 + 0x0ff6, .FORMAT_CONTROL = 0x000034C0 + 0x0fa6, . CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0fa5, .CURSOR0_CONTROL = 0x000034C0 + 0x0fc7, .CURSOR0_COLOR0 = 0x000034C0 + 0x0fc8 , .CURSOR0_COLOR1 = 0x000034C0 + 0x0fc9, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0fca, .DPP_CONTROL = 0x000034C0 + 0x0f9b, . CM_HDR_MULT_COEF = 0x000034C0 + 0x10a7, .CURSOR_CONTROL = 0x000034C0 + 0x0830, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0fb3, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0fa7, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0fa8 , .FCNV_FP_BIAS_B = 0x000034C0 + 0x0fa9, .FCNV_FP_SCALE_R = 0x000034C0 + 0x0faa, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0fab, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0fac, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0fad , .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0fae, .COLOR_KEYER_RED = 0x000034C0 + 0x0faf, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0fb0 , .COLOR_KEYER_BLUE = 0x000034C0 + 0x0fb1, .CURSOR_CONTROL = 0x000034C0 + 0x0830, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0ff0, .DSCL_MEM_PWR_STATUS = 0x000034C0 + 0x0fee, .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0fed , .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x105d, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x1084, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x1085, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x1086 , .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x108d, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x108e, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x108f, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x1090 , .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x1091, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x1092, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x1096, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x1097, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x1098, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x1099, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x109a, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x109b , .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x109c, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x109d, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x109e, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x109f , .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x10a0, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x10a1, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x10a2, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x10a3 , .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x10a4, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x10a5, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x10a6, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x1061 , .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x1062, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x1063, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x106a, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x106b , .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x106c, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x106d, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x106e, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x106f , .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x1073, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x1074, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x1075, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x1076, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x1077, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x1078, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x1079, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x107a , .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x107b, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x107c, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x107d, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x107e , .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x107f, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x1080, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x1081, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x1082 , .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x1083, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x105e, .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x105f , .CM_3DLUT_MODE = 0x000034C0 + 0x10e6, .CM_3DLUT_INDEX = 0x000034C0 + 0x10e7, .CM_3DLUT_DATA = 0x000034C0 + 0x10e8, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x10e9, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x10ea, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x10b5 , .CM_SHAPER_CONTROL = 0x000034C0 + 0x10ad, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x10cd, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x10ce, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x10cf , .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x10d0, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x10d1, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x10d2, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x10d3, . CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x10d4, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x10d5, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x10d6, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x10d7, . CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x10d8, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x10d9, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x10da, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x10db , .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x10dc, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x10dd, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x10de, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x10df , .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x10e0, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x10e1, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x10e2, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x10e3 , .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x10b6, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x10b7, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x10b8, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x10b9, . CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x10ba, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x10bb, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x10bc, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x10bd, . CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x10be, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x10bf, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x10c0, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x10c1 , .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x10c2, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x10c3, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x10c4, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x10c5 , .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x10c6, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x10c7, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x10c8, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x10c9 , .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x10ca, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x10cb, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x10cc, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x10b3, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x105d, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x10b4 , .CM_MEM_PWR_CTRL2 = 0x000034C0 + 0x10e4, .CM_MEM_PWR_STATUS2 = 0x000034C0 + 0x10e5, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x1064, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x1065, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x1066, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x1087 , .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x1088, . CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x1089, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x1060,}, | ||||
| 486 | dpp_regs(3)[3] = { .CM_DEALPHA = 0x000034C0 + 0x1216, .CM_MEM_PWR_STATUS = 0x000034C0 + 0x1214, .CM_BIAS_CR_R = 0x000034C0 + 0x117c, . CM_BIAS_Y_G_CB_B = 0x000034C0 + 0x117d, .PRE_DEGAM = 0x000034C0 + 0x112e, .CM_GAMCOR_CONTROL = 0x000034C0 + 0x117e, .CM_GAMCOR_LUT_CONTROL = 0x000034C0 + 0x1181, .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x117f , .CM_GAMCOR_LUT_INDEX = 0x000034C0 + 0x117f, .CM_GAMCOR_LUT_DATA = 0x000034C0 + 0x1180, .CM_GAMCOR_RAMB_START_CNTL_B = 0x000034C0 + 0x11a5, .CM_GAMCOR_RAMB_START_CNTL_G = 0x000034C0 + 0x11a6 , .CM_GAMCOR_RAMB_START_CNTL_R = 0x000034C0 + 0x11a7, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x11a8, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x11a9, .CM_GAMCOR_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x11aa , .CM_GAMCOR_RAMB_END_CNTL1_B = 0x000034C0 + 0x11ae, .CM_GAMCOR_RAMB_END_CNTL2_B = 0x000034C0 + 0x11af, .CM_GAMCOR_RAMB_END_CNTL1_G = 0x000034C0 + 0x11b0, .CM_GAMCOR_RAMB_END_CNTL2_G = 0x000034C0 + 0x11b1, .CM_GAMCOR_RAMB_END_CNTL1_R = 0x000034C0 + 0x11b2, .CM_GAMCOR_RAMB_END_CNTL2_R = 0x000034C0 + 0x11b3, .CM_GAMCOR_RAMB_REGION_0_1 = 0x000034C0 + 0x11b7, .CM_GAMCOR_RAMB_REGION_32_33 = 0x000034C0 + 0x11c7 , .CM_GAMCOR_RAMB_OFFSET_B = 0x000034C0 + 0x11b4, .CM_GAMCOR_RAMB_OFFSET_G = 0x000034C0 + 0x11b5, .CM_GAMCOR_RAMB_OFFSET_R = 0x000034C0 + 0x11b6, .CM_GAMCOR_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x11ab , .CM_GAMCOR_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x11ac, .CM_GAMCOR_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x11ad, .CM_GAMCOR_RAMA_START_CNTL_B = 0x000034C0 + 0x1182, .CM_GAMCOR_RAMA_START_CNTL_G = 0x000034C0 + 0x1183 , .CM_GAMCOR_RAMA_START_CNTL_R = 0x000034C0 + 0x1184, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x1185, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x1186, .CM_GAMCOR_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x1187 , .CM_GAMCOR_RAMA_END_CNTL1_B = 0x000034C0 + 0x118b, .CM_GAMCOR_RAMA_END_CNTL2_B = 0x000034C0 + 0x118c, .CM_GAMCOR_RAMA_END_CNTL1_G = 0x000034C0 + 0x118d, .CM_GAMCOR_RAMA_END_CNTL2_G = 0x000034C0 + 0x118e, .CM_GAMCOR_RAMA_END_CNTL1_R = 0x000034C0 + 0x118f, .CM_GAMCOR_RAMA_END_CNTL2_R = 0x000034C0 + 0x1190, .CM_GAMCOR_RAMA_REGION_0_1 = 0x000034C0 + 0x1194, .CM_GAMCOR_RAMA_REGION_32_33 = 0x000034C0 + 0x11a4 , .CM_GAMCOR_RAMA_OFFSET_B = 0x000034C0 + 0x1191, .CM_GAMCOR_RAMA_OFFSET_G = 0x000034C0 + 0x1192, .CM_GAMCOR_RAMA_OFFSET_R = 0x000034C0 + 0x1193, .CM_GAMCOR_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x1188 , .CM_GAMCOR_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x1189, .CM_GAMCOR_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x118a, .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x116f, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x1170, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x1171, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x1172, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x1173, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x1174, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x1175, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x1176, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x1177, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x1178, .CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x1179, . CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x117a, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x117b, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x114e, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x114f , .OTG_H_BLANK = 0x000034C0 + 0x1150, .OTG_V_BLANK = 0x000034C0 + 0x1151, .SCL_MODE = 0x000034C0 + 0x113c, .LB_DATA_FORMAT = 0x000034C0 + 0x1155, .LB_MEMORY_CTRL = 0x000034C0 + 0x1156, . DSCL_AUTOCAL = 0x000034C0 + 0x114d, .SCL_TAP_CONTROL = 0x000034C0 + 0x113d, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x113a, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x113b, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x113f , .MPC_SIZE = 0x000034C0 + 0x1154, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x1141, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x1145, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1143 , .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1148, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x1142, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x1144, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x1146, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x1149, .RECOUT_START = 0x000034C0 + 0x1152, . RECOUT_SIZE = 0x000034C0 + 0x1153, .PRE_DEALPHA = 0x000034C0 + 0x111f, .PRE_REALPHA = 0x000034C0 + 0x112f, .PRE_CSC_MODE = 0x000034C0 + 0x1120, .PRE_CSC_C11_C12 = 0x000034C0 + 0x1121, .PRE_CSC_C33_C34 = 0x000034C0 + 0x1126, .PRE_CSC_B_C11_C12 = 0x000034C0 + 0x1127 , .PRE_CSC_B_C33_C34 = 0x000034C0 + 0x112c, .CM_POST_CSC_CONTROL = 0x000034C0 + 0x1162, .CM_POST_CSC_C11_C12 = 0x000034C0 + 0x1163 , .CM_POST_CSC_C33_C34 = 0x000034C0 + 0x1168, .CM_POST_CSC_B_C11_C12 = 0x000034C0 + 0x1169, .CM_POST_CSC_B_C33_C34 = 0x000034C0 + 0x116e, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x1213, .CM_CONTROL = 0x000034C0 + 0x1161, .FORMAT_CONTROL = 0x000034C0 + 0x1111, . CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x1110, .CURSOR0_CONTROL = 0x000034C0 + 0x1132, .CURSOR0_COLOR0 = 0x000034C0 + 0x1133 , .CURSOR0_COLOR1 = 0x000034C0 + 0x1134, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x1135, .DPP_CONTROL = 0x000034C0 + 0x1106, . CM_HDR_MULT_COEF = 0x000034C0 + 0x1212, .CURSOR_CONTROL = 0x000034C0 + 0x090c, .ALPHA_2BIT_LUT = 0x000034C0 + 0x111e, .FCNV_FP_BIAS_R = 0x000034C0 + 0x1112, .FCNV_FP_BIAS_G = 0x000034C0 + 0x1113 , .FCNV_FP_BIAS_B = 0x000034C0 + 0x1114, .FCNV_FP_SCALE_R = 0x000034C0 + 0x1115, .FCNV_FP_SCALE_G = 0x000034C0 + 0x1116, .FCNV_FP_SCALE_B = 0x000034C0 + 0x1117, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x1118 , .COLOR_KEYER_ALPHA = 0x000034C0 + 0x1119, .COLOR_KEYER_RED = 0x000034C0 + 0x111a, .COLOR_KEYER_GREEN = 0x000034C0 + 0x111b , .COLOR_KEYER_BLUE = 0x000034C0 + 0x111c, .CURSOR_CONTROL = 0x000034C0 + 0x090c, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x115b, .DSCL_MEM_PWR_STATUS = 0x000034C0 + 0x1159, .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x1158 , .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x11c8, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x11ef, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x11f0, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x11f1 , .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x11f8, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x11f9, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x11fa, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x11fb , .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x11fc, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x11fd, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x1201, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x1202, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x1203, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x1204, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x1205, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x1206 , .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x1207, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x1208, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x1209, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x120a , .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x120b, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x120c, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x120d, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x120e , .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x120f, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x1210, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x1211, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x11cc , .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x11cd, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x11ce, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x11d5, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x11d6 , .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x11d7, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x11d8, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x11d9, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x11da , .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x11de, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x11df, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x11e0, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x11e1, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x11e2, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x11e3, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x11e4, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x11e5 , .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x11e6, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x11e7, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x11e8, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x11e9 , .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x11ea, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x11eb, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x11ec, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x11ed , .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x11ee, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x11c9, .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x11ca , .CM_3DLUT_MODE = 0x000034C0 + 0x1251, .CM_3DLUT_INDEX = 0x000034C0 + 0x1252, .CM_3DLUT_DATA = 0x000034C0 + 0x1253, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x1254, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x1255, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x1220 , .CM_SHAPER_CONTROL = 0x000034C0 + 0x1218, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x1238, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x1239, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x123a , .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x123b, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x123c, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x123d, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x123e, . CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x123f, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x1240, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x1241, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x1242, . CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x1243, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x1244, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x1245, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x1246 , .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x1247, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x1248, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x1249, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x124a , .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x124b, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x124c, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x124d, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x124e , .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x1221, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x1222, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x1223, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x1224, . CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x1225, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x1226, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x1227, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x1228, . CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x1229, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x122a, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x122b, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x122c , .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x122d, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x122e, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x122f, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x1230 , .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x1231, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x1232, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x1233, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x1234 , .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x1235, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x1236, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x1237, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x121e, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x11c8, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x121f , .CM_MEM_PWR_CTRL2 = 0x000034C0 + 0x124f, .CM_MEM_PWR_STATUS2 = 0x000034C0 + 0x1250, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x11cf, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x11d0, .CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x11d1, .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x11f2 , .CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x11f3, . CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x11f4, .CM_BLNDGAM_LUT_CONTROL = 0x000034C0 + 0x11cb,} | ||||
| 487 | }; | ||||
| 488 | |||||
| 489 | static const struct dcn3_dpp_shift tf_shift = { | ||||
| 490 | DPP_REG_LIST_SH_MASK_DCN30(__SHIFT).GAMCOR_MEM_PWR_STATE = 0x0, .CM_DEALPHA_EN = 0x0, .CM_DEALPHA_ABLND = 0x1, .CM_BIAS_CR_R = 0x0, .CM_BIAS_Y_G = 0x0, .CM_BIAS_CB_B = 0x10, .GAMCOR_MEM_PWR_DIS = 0x2, .GAMCOR_MEM_PWR_FORCE = 0x0 , .PRE_DEGAM_MODE = 0x0, .PRE_DEGAM_SELECT = 0x4, .CM_GAMCOR_MODE = 0x0, .CM_GAMCOR_SELECT = 0x2, .CM_GAMCOR_PWL_DISABLE = 0x3 , .CM_GAMCOR_MODE_CURRENT = 0x4, .CM_GAMCOR_SELECT_CURRENT = 0x6 , .CM_GAMCOR_LUT_INDEX = 0x0, .CM_GAMCOR_LUT_DATA = 0x0, .CM_GAMCOR_LUT_WRITE_COLOR_MASK = 0x0, .CM_GAMCOR_LUT_READ_COLOR_SEL = 0x3, .CM_GAMCOR_LUT_READ_DBG = 0x5, .CM_GAMCOR_LUT_HOST_SEL = 0x6, .CM_GAMCOR_LUT_CONFIG_MODE = 0x7, .CM_GAMCOR_RAMA_EXP_REGION_START_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .CM_GAMCOR_RAMA_OFFSET_B = 0x0, .CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_GAMUT_REMAP_MODE = 0x0, .CM_GAMUT_REMAP_MODE_CURRENT = 0x2, .CM_GAMUT_REMAP_C11 = 0x0, .CM_GAMUT_REMAP_C12 = 0x10 , .CM_GAMUT_REMAP_C13 = 0x0, .CM_GAMUT_REMAP_C14 = 0x10, .CM_GAMUT_REMAP_C21 = 0x0, .CM_GAMUT_REMAP_C22 = 0x10, .CM_GAMUT_REMAP_C23 = 0x0 , .CM_GAMUT_REMAP_C24 = 0x10, .CM_GAMUT_REMAP_C31 = 0x0, .CM_GAMUT_REMAP_C32 = 0x10, .CM_GAMUT_REMAP_C33 = 0x0, .CM_GAMUT_REMAP_C34 = 0x10 , .EXT_OVERSCAN_LEFT = 0x10, .EXT_OVERSCAN_RIGHT = 0x0, .EXT_OVERSCAN_BOTTOM = 0x0, .EXT_OVERSCAN_TOP = 0x10, .OTG_H_BLANK_START = 0x0, . OTG_H_BLANK_END = 0x10, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END = 0x10, .INTERLEAVE_EN = 0x0, .LB_DATA_FORMAT__ALPHA_EN = 0x4 , .MEMORY_CONFIG = 0x0, .LB_MAX_PARTITIONS = 0x8, .AUTOCAL_MODE = 0x0, .AUTOCAL_NUM_PIPE = 0x8, .AUTOCAL_PIPE_ID = 0xc, .SCL_V_NUM_TAPS = 0x0, .SCL_H_NUM_TAPS = 0x4, .SCL_V_NUM_TAPS_C = 0x8, .SCL_H_NUM_TAPS_C = 0xc, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x0, .SCL_COEF_RAM_PHASE = 0x8, .SCL_COEF_RAM_FILTER_TYPE = 0x10, .SCL_COEF_RAM_EVEN_TAP_COEF = 0x0, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0xf, .SCL_COEF_RAM_ODD_TAP_COEF = 0x10, .SCL_COEF_RAM_ODD_TAP_COEF_EN = 0x1f, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x0, .SCL_H_2TAP_SHARP_EN = 0x4, .SCL_H_2TAP_SHARP_FACTOR = 0x8, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x10, .SCL_V_2TAP_SHARP_EN = 0x14, .SCL_V_2TAP_SHARP_FACTOR = 0x18, .SCL_COEF_RAM_SELECT = 0x8, .DSCL_MODE = 0x0, .RECOUT_START_X = 0x0, .RECOUT_START_Y = 0x10, .RECOUT_WIDTH = 0x0, .RECOUT_HEIGHT = 0x10, .MPC_WIDTH = 0x0, .MPC_HEIGHT = 0x10, .SCL_H_SCALE_RATIO = 0x0, .SCL_V_SCALE_RATIO = 0x0, .SCL_H_SCALE_RATIO_C = 0x0, .SCL_V_SCALE_RATIO_C = 0x0 , .SCL_H_INIT_FRAC = 0x0, .SCL_H_INIT_INT = 0x18, .SCL_H_INIT_FRAC_C = 0x0, .SCL_H_INIT_INT_C = 0x18, .SCL_V_INIT_FRAC = 0x0, .SCL_V_INIT_INT = 0x18, .SCL_V_INIT_FRAC_C = 0x0, .SCL_V_INIT_INT_C = 0x18, . SCL_CHROMA_COEF_MODE = 0x10, .SCL_COEF_RAM_SELECT_CURRENT = 0xc , .PRE_DEALPHA_EN = 0x0, .PRE_DEALPHA_ABLND_EN = 0x4, .PRE_REALPHA_EN = 0x0, .PRE_REALPHA_ABLND_EN = 0x4, .PRE_CSC_MODE = 0x0, .PRE_CSC_MODE_CURRENT = 0x2, .PRE_CSC_C11 = 0x0, .PRE_CSC_C12 = 0x10, .PRE_CSC_C33 = 0x0, .PRE_CSC_C34 = 0x10, .CM_POST_CSC_MODE = 0x0, .CM_POST_CSC_MODE_CURRENT = 0x2, .CM_POST_CSC_C11 = 0x0, .CM_POST_CSC_C12 = 0x10, .CM_POST_CSC_C33 = 0x0, .CM_POST_CSC_C34 = 0x10, .CNVC_BYPASS = 0xc, .FORMAT_CONTROL__ALPHA_EN = 0x8, .FORMAT_EXPANSION_MODE = 0x0, .CNVC_SURFACE_PIXEL_FORMAT = 0x0, .CNVC_ALPHA_PLANE_ENABLE = 0x8, .CUR0_MODE = 0x4, .CUR0_EXPANSION_MODE = 0x1, .CUR0_ENABLE = 0x0, .CUR0_COLOR0 = 0x0, .CUR0_COLOR1 = 0x0, .CUR0_FP_BIAS = 0x10, .CUR0_FP_SCALE = 0x0, .DPP_CLOCK_ENABLE = 0x4, .CM_HDR_MULT_COEF = 0x0, .CM_BYPASS = 0x0, .CURSOR_MODE = 0x8, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK = 0x18, .CURSOR_ENABLE = 0x0, .FORMAT_CNV16 = 0x4, .CNVC_BYPASS_MSB_ALIGN = 0xd, .CLAMP_POSITIVE = 0x10, .CLAMP_POSITIVE_C = 0x11, .FORMAT_CROSSBAR_R = 0x18, .FORMAT_CROSSBAR_G = 0x1a, .FORMAT_CROSSBAR_B = 0x1c , .ALPHA_2BIT_LUT0 = 0x0, .ALPHA_2BIT_LUT1 = 0x8, .ALPHA_2BIT_LUT2 = 0x10, .ALPHA_2BIT_LUT3 = 0x18, .FCNV_FP_BIAS_R = 0x0, .FCNV_FP_BIAS_G = 0x0, .FCNV_FP_BIAS_B = 0x0, .FCNV_FP_SCALE_R = 0x0, .FCNV_FP_SCALE_G = 0x0, .FCNV_FP_SCALE_B = 0x0, .COLOR_KEYER_EN = 0x0, .COLOR_KEYER_MODE = 0x4, .COLOR_KEYER_ALPHA_LOW = 0x0, .COLOR_KEYER_ALPHA_HIGH = 0x10, .COLOR_KEYER_RED_LOW = 0x0, .COLOR_KEYER_RED_HIGH = 0x10 , .COLOR_KEYER_GREEN_LOW = 0x0, .COLOR_KEYER_GREEN_HIGH = 0x10 , .COLOR_KEYER_BLUE_LOW = 0x0, .COLOR_KEYER_BLUE_HIGH = 0x10, .CUR0_PIX_INV_MODE = 0x2, .CUR0_PIXEL_ALPHA_MOD_EN = 0x7, .CUR0_ROM_EN = 0x3, .OBUF_MEM_PWR_FORCE = 0x0, .LUT_MEM_PWR_FORCE = 0x0, . LUT_MEM_PWR_STATE = 0x0, .CM_3DLUT_MODE = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, . CM_BLNDGAM_RAMB_EXP_REGION_START_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .CM_BLNDGAM_RAMB_EXP_REGION_START_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, . CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION_START_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_START_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_START_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, . CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_LUT_INDEX = 0x0, .CM_BLNDGAM_LUT_DATA = 0x0 , .BLNDGAM_MEM_PWR_FORCE = 0x4, .CM_3DLUT_MODE = 0x0, .CM_3DLUT_SIZE = 0x4, .CM_3DLUT_INDEX = 0x0, .CM_3DLUT_DATA0 = 0x0, .CM_3DLUT_DATA1 = 0x10, .CM_3DLUT_DATA_30BIT = 0x2, .CM_3DLUT_WRITE_EN_MASK = 0x0, .CM_3DLUT_RAM_SEL = 0x4, .CM_3DLUT_30BIT_EN = 0x8, .CM_3DLUT_READ_SEL = 0x10, .CM_SHAPER_LUT_MODE = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_B = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .CM_SHAPER_RAMB_EXP_REGION_START_G = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .CM_SHAPER_RAMB_EXP_REGION_START_R = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .CM_SHAPER_RAMB_EXP_REGION_END_B = 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_B = 0x10, .CM_SHAPER_RAMB_EXP_REGION_END_G = 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_G = 0x10, .CM_SHAPER_RAMB_EXP_REGION_END_R = 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_R = 0x10, .CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION_START_B = 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_SHAPER_RAMA_EXP_REGION_START_G = 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .CM_SHAPER_RAMA_EXP_REGION_START_R = 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .CM_SHAPER_RAMA_EXP_REGION_END_B = 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x10, .CM_SHAPER_RAMA_EXP_REGION_END_G = 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_G = 0x10, .CM_SHAPER_RAMA_EXP_REGION_END_R = 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_R = 0x10, .CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x0, .CM_SHAPER_LUT_WRITE_SEL = 0x4, .CM_SHAPER_LUT_INDEX = 0x0, .CM_SHAPER_LUT_DATA = 0x0, .BLNDGAM_MEM_PWR_STATE = 0x2 , .HDR3DLUT_MEM_PWR_FORCE = 0xc, .SHAPER_MEM_PWR_FORCE = 0x8, .HDR3DLUT_MEM_PWR_STATE = 0x6, .SHAPER_MEM_PWR_STATE = 0x4, . CM_BLNDGAM_MODE = 0x0, .CM_BLNDGAM_MODE_CURRENT = 0x4, .CM_BLNDGAM_SELECT_CURRENT = 0x6, .CM_BLNDGAM_SELECT = 0x2, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_R = 0x0, .CM_BLNDGAM_LUT_WRITE_COLOR_MASK = 0x0, .CM_BLNDGAM_LUT_HOST_SEL = 0x6, .CM_BLNDGAM_LUT_CONFIG_MODE = 0x7, .CM_3DLUT_MODE_CURRENT = 0x8, .CM_SHAPER_MODE_CURRENT = 0x2 | ||||
| 491 | }; | ||||
| 492 | |||||
| 493 | static const struct dcn3_dpp_mask tf_mask = { | ||||
| 494 | DPP_REG_LIST_SH_MASK_DCN30(_MASK).GAMCOR_MEM_PWR_STATE = 0x00000003L, .CM_DEALPHA_EN = 0x00000001L , .CM_DEALPHA_ABLND = 0x00000002L, .CM_BIAS_CR_R = 0x0000FFFFL , .CM_BIAS_Y_G = 0x0000FFFFL, .CM_BIAS_CB_B = 0xFFFF0000L, .GAMCOR_MEM_PWR_DIS = 0x00000004L, .GAMCOR_MEM_PWR_FORCE = 0x00000003L, .PRE_DEGAM_MODE = 0x00000003L, .PRE_DEGAM_SELECT = 0x00000070L, .CM_GAMCOR_MODE = 0x00000003L, .CM_GAMCOR_SELECT = 0x00000004L, .CM_GAMCOR_PWL_DISABLE = 0x00000008L, .CM_GAMCOR_MODE_CURRENT = 0x00000030L, .CM_GAMCOR_SELECT_CURRENT = 0x00000040L, .CM_GAMCOR_LUT_INDEX = 0x000001FFL, .CM_GAMCOR_LUT_DATA = 0x0003FFFFL, .CM_GAMCOR_LUT_WRITE_COLOR_MASK = 0x00000007L , .CM_GAMCOR_LUT_READ_COLOR_SEL = 0x00000018L, .CM_GAMCOR_LUT_READ_DBG = 0x00000020L, .CM_GAMCOR_LUT_HOST_SEL = 0x00000040L, .CM_GAMCOR_LUT_CONFIG_MODE = 0x00000080L, .CM_GAMCOR_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL , .CM_GAMCOR_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .CM_GAMCOR_RAMA_OFFSET_B = 0x0007FFFFL, .CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L , .CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_GAMUT_REMAP_MODE = 0x00000003L, .CM_GAMUT_REMAP_MODE_CURRENT = 0x0000000CL, .CM_GAMUT_REMAP_C11 = 0x0000FFFFL, .CM_GAMUT_REMAP_C12 = 0xFFFF0000L, .CM_GAMUT_REMAP_C13 = 0x0000FFFFL, .CM_GAMUT_REMAP_C14 = 0xFFFF0000L, .CM_GAMUT_REMAP_C21 = 0x0000FFFFL, .CM_GAMUT_REMAP_C22 = 0xFFFF0000L, .CM_GAMUT_REMAP_C23 = 0x0000FFFFL, .CM_GAMUT_REMAP_C24 = 0xFFFF0000L, .CM_GAMUT_REMAP_C31 = 0x0000FFFFL, .CM_GAMUT_REMAP_C32 = 0xFFFF0000L, .CM_GAMUT_REMAP_C33 = 0x0000FFFFL, .CM_GAMUT_REMAP_C34 = 0xFFFF0000L, .EXT_OVERSCAN_LEFT = 0x1FFF0000L, .EXT_OVERSCAN_RIGHT = 0x00001FFFL, .EXT_OVERSCAN_BOTTOM = 0x00001FFFL, .EXT_OVERSCAN_TOP = 0x1FFF0000L, .OTG_H_BLANK_START = 0x00003FFFL, .OTG_H_BLANK_END = 0x3FFF0000L, .OTG_V_BLANK_START = 0x00003FFFL, .OTG_V_BLANK_END = 0x3FFF0000L, .INTERLEAVE_EN = 0x00000001L, .LB_DATA_FORMAT__ALPHA_EN = 0x00000010L, .MEMORY_CONFIG = 0x00000003L, .LB_MAX_PARTITIONS = 0x00003F00L, .AUTOCAL_MODE = 0x00000003L, .AUTOCAL_NUM_PIPE = 0x00000300L, .AUTOCAL_PIPE_ID = 0x00003000L, .SCL_V_NUM_TAPS = 0x00000007L, .SCL_H_NUM_TAPS = 0x00000070L, .SCL_V_NUM_TAPS_C = 0x00000700L, .SCL_H_NUM_TAPS_C = 0x00007000L, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x00000003L, .SCL_COEF_RAM_PHASE = 0x00003F00L, .SCL_COEF_RAM_FILTER_TYPE = 0x00070000L, .SCL_COEF_RAM_EVEN_TAP_COEF = 0x00003FFFL, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0x00008000L, .SCL_COEF_RAM_ODD_TAP_COEF = 0x3FFF0000L, .SCL_COEF_RAM_ODD_TAP_COEF_EN = 0x80000000L, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x00000001L, . SCL_H_2TAP_SHARP_EN = 0x00000010L, .SCL_H_2TAP_SHARP_FACTOR = 0x00000700L, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x00010000L, .SCL_V_2TAP_SHARP_EN = 0x00100000L, .SCL_V_2TAP_SHARP_FACTOR = 0x07000000L, .SCL_COEF_RAM_SELECT = 0x00000100L, .DSCL_MODE = 0x00000007L, .RECOUT_START_X = 0x00001FFFL , .RECOUT_START_Y = 0x1FFF0000L, .RECOUT_WIDTH = 0x00003FFFL, .RECOUT_HEIGHT = 0x3FFF0000L, .MPC_WIDTH = 0x00003FFFL, .MPC_HEIGHT = 0x3FFF0000L, .SCL_H_SCALE_RATIO = 0x07FFFFFFL, .SCL_V_SCALE_RATIO = 0x07FFFFFFL, .SCL_H_SCALE_RATIO_C = 0x07FFFFFFL, .SCL_V_SCALE_RATIO_C = 0x07FFFFFFL, .SCL_H_INIT_FRAC = 0x00FFFFFFL, .SCL_H_INIT_INT = 0x0F000000L, .SCL_H_INIT_FRAC_C = 0x00FFFFFFL, .SCL_H_INIT_INT_C = 0x0F000000L, .SCL_V_INIT_FRAC = 0x00FFFFFFL, .SCL_V_INIT_INT = 0x0F000000L, .SCL_V_INIT_FRAC_C = 0x00FFFFFFL, .SCL_V_INIT_INT_C = 0x0F000000L, .SCL_CHROMA_COEF_MODE = 0x00010000L, .SCL_COEF_RAM_SELECT_CURRENT = 0x00001000L, .PRE_DEALPHA_EN = 0x00000001L, .PRE_DEALPHA_ABLND_EN = 0x00000010L, .PRE_REALPHA_EN = 0x00000001L, .PRE_REALPHA_ABLND_EN = 0x00000010L, .PRE_CSC_MODE = 0x00000003L, .PRE_CSC_MODE_CURRENT = 0x0000000CL, .PRE_CSC_C11 = 0x0000FFFFL, .PRE_CSC_C12 = 0xFFFF0000L , .PRE_CSC_C33 = 0x0000FFFFL, .PRE_CSC_C34 = 0xFFFF0000L, .CM_POST_CSC_MODE = 0x00000003L, .CM_POST_CSC_MODE_CURRENT = 0x0000000CL, .CM_POST_CSC_C11 = 0x0000FFFFL, .CM_POST_CSC_C12 = 0xFFFF0000L, .CM_POST_CSC_C33 = 0x0000FFFFL, .CM_POST_CSC_C34 = 0xFFFF0000L, .CNVC_BYPASS = 0x00001000L, .FORMAT_CONTROL__ALPHA_EN = 0x00000100L, .FORMAT_EXPANSION_MODE = 0x00000001L, .CNVC_SURFACE_PIXEL_FORMAT = 0x0000007FL, .CNVC_ALPHA_PLANE_ENABLE = 0x00000100L, .CUR0_MODE = 0x00000070L, .CUR0_EXPANSION_MODE = 0x00000002L, .CUR0_ENABLE = 0x00000001L, .CUR0_COLOR0 = 0x00FFFFFFL , .CUR0_COLOR1 = 0x00FFFFFFL, .CUR0_FP_BIAS = 0xFFFF0000L, .CUR0_FP_SCALE = 0x0000FFFFL, .DPP_CLOCK_ENABLE = 0x00000010L, .CM_HDR_MULT_COEF = 0x0007FFFFL, .CM_BYPASS = 0x00000001L, .CURSOR_MODE = 0x00000700L , .CURSOR_PITCH = 0x00030000L, .CURSOR_LINES_PER_CHUNK = 0x1F000000L , .CURSOR_ENABLE = 0x00000001L, .FORMAT_CNV16 = 0x00000010L, . CNVC_BYPASS_MSB_ALIGN = 0x00002000L, .CLAMP_POSITIVE = 0x00010000L , .CLAMP_POSITIVE_C = 0x00020000L, .FORMAT_CROSSBAR_R = 0x03000000L , .FORMAT_CROSSBAR_G = 0x0C000000L, .FORMAT_CROSSBAR_B = 0x30000000L , .ALPHA_2BIT_LUT0 = 0x000000FFL, .ALPHA_2BIT_LUT1 = 0x0000FF00L , .ALPHA_2BIT_LUT2 = 0x00FF0000L, .ALPHA_2BIT_LUT3 = 0xFF000000L , .FCNV_FP_BIAS_R = 0x0007FFFFL, .FCNV_FP_BIAS_G = 0x0007FFFFL , .FCNV_FP_BIAS_B = 0x0007FFFFL, .FCNV_FP_SCALE_R = 0x0007FFFFL , .FCNV_FP_SCALE_G = 0x0007FFFFL, .FCNV_FP_SCALE_B = 0x0007FFFFL , .COLOR_KEYER_EN = 0x00000001L, .COLOR_KEYER_MODE = 0x00000030L , .COLOR_KEYER_ALPHA_LOW = 0x0000FFFFL, .COLOR_KEYER_ALPHA_HIGH = 0xFFFF0000L, .COLOR_KEYER_RED_LOW = 0x0000FFFFL, .COLOR_KEYER_RED_HIGH = 0xFFFF0000L, .COLOR_KEYER_GREEN_LOW = 0x0000FFFFL, .COLOR_KEYER_GREEN_HIGH = 0xFFFF0000L, .COLOR_KEYER_BLUE_LOW = 0x0000FFFFL, .COLOR_KEYER_BLUE_HIGH = 0xFFFF0000L, .CUR0_PIX_INV_MODE = 0x00000004L, .CUR0_PIXEL_ALPHA_MOD_EN = 0x00000080L, .CUR0_ROM_EN = 0x00000008L, .OBUF_MEM_PWR_FORCE = 0x00000003L, .LUT_MEM_PWR_FORCE = 0x00000003L, .LUT_MEM_PWR_STATE = 0x00000003L, .CM_3DLUT_MODE = 0x00000003L, .CM_BLNDGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .CM_BLNDGAM_RAMB_EXP_REGION_START_G = 0x0003FFFFL , .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L, . CM_BLNDGAM_RAMB_EXP_REGION_START_R = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B = 0xFFFF0000L , .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G = 0xFFFF0000L, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R = 0xFFFF0000L, .CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L , .CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L , .CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L , .CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L , .CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L , .CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L , .CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . CM_BLNDGAM_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .CM_BLNDGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, . CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G = 0xFFFF0000L, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R = 0xFFFF0000L , .CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L , .CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L , .CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L , .CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L , .CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L , .CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_LUT_INDEX = 0x000001FFL, .CM_BLNDGAM_LUT_DATA = 0x0003FFFFL, .BLNDGAM_MEM_PWR_FORCE = 0x00000030L, .CM_3DLUT_MODE = 0x00000003L, .CM_3DLUT_SIZE = 0x00000010L, .CM_3DLUT_INDEX = 0x000007FFL, .CM_3DLUT_DATA0 = 0x0000FFFFL, .CM_3DLUT_DATA1 = 0xFFFF0000L, .CM_3DLUT_DATA_30BIT = 0xFFFFFFFCL, .CM_3DLUT_WRITE_EN_MASK = 0x0000000FL, .CM_3DLUT_RAM_SEL = 0x00000010L, .CM_3DLUT_30BIT_EN = 0x00000100L, .CM_3DLUT_READ_SEL = 0x00030000L, .CM_SHAPER_LUT_MODE = 0x00000003L, .CM_SHAPER_RAMB_EXP_REGION_START_B = 0x0003FFFFL , .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . CM_SHAPER_RAMB_EXP_REGION_START_G = 0x0003FFFFL, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .CM_SHAPER_RAMB_EXP_REGION_START_R = 0x0003FFFFL , .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L, . CM_SHAPER_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_B = 0x3FFF0000L, .CM_SHAPER_RAMB_EXP_REGION_END_G = 0x0000FFFFL , .CM_SHAPER_RAMB_EXP_REGION_END_BASE_G = 0x3FFF0000L, .CM_SHAPER_RAMB_EXP_REGION_END_R = 0x0000FFFFL, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_R = 0x3FFF0000L , .CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . CM_SHAPER_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .CM_SHAPER_RAMA_EXP_REGION_START_R = 0x0003FFFFL , .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, . CM_SHAPER_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x3FFF0000L, .CM_SHAPER_RAMA_EXP_REGION_END_G = 0x0000FFFFL , .CM_SHAPER_RAMA_EXP_REGION_END_BASE_G = 0x3FFF0000L, .CM_SHAPER_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_R = 0x3FFF0000L , .CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x00000007L, . CM_SHAPER_LUT_WRITE_SEL = 0x00000010L, .CM_SHAPER_LUT_INDEX = 0x000000FFL, .CM_SHAPER_LUT_DATA = 0x00FFFFFFL, .BLNDGAM_MEM_PWR_STATE = 0x0000000CL, .HDR3DLUT_MEM_PWR_FORCE = 0x00003000L, .SHAPER_MEM_PWR_FORCE = 0x00000300L, .HDR3DLUT_MEM_PWR_STATE = 0x000000C0L, .SHAPER_MEM_PWR_STATE = 0x00000030L, .CM_BLNDGAM_MODE = 0x00000003L, .CM_BLNDGAM_MODE_CURRENT = 0x00000030L, .CM_BLNDGAM_SELECT_CURRENT = 0x00000040L, .CM_BLNDGAM_SELECT = 0x00000004L, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B = 0x0003FFFFL , .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B = 0x0003FFFFL , .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_END_G = 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .CM_BLNDGAM_LUT_WRITE_COLOR_MASK = 0x00000007L , .CM_BLNDGAM_LUT_HOST_SEL = 0x00000040L, .CM_BLNDGAM_LUT_CONFIG_MODE = 0x00000080L, .CM_3DLUT_MODE_CURRENT = 0x00000300L, .CM_SHAPER_MODE_CURRENT = 0x0000000CL | ||||
| 495 | }; | ||||
| 496 | |||||
| 497 | #define opp_regs(id)[id] = { .FMT_BIT_DEPTH_CONTROL = DCN_BASE__INST0_SEGregFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX + regFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = DCN_BASE__INST0_SEGregFMTid_FMT_CONTROL_BASE_IDX + regFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = DCN_BASE__INST0_SEGregFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX + regFMTid_FMT_DITHER_RAND_R_SEED, .FMT_DITHER_RAND_G_SEED = DCN_BASE__INST0_SEGregFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX + regFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED = DCN_BASE__INST0_SEGregFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX + regFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = DCN_BASE__INST0_SEGregFMTid_FMT_CLAMP_CNTL_BASE_IDX + regFMTid_FMT_CLAMP_CNTL, .FMT_DYNAMIC_EXP_CNTL = DCN_BASE__INST0_SEGregFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX + regFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_MAP420_MEMORY_CONTROL = DCN_BASE__INST0_SEGregFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX + regFMTid_FMT_MAP420_MEMORY_CONTROL, .OPPBUF_CONTROL = DCN_BASE__INST0_SEGregOPPBUFid_OPPBUF_CONTROL_BASE_IDX + regOPPBUFid_OPPBUF_CONTROL, .OPPBUF_3D_PARAMETERS_0 = DCN_BASE__INST0_SEGregOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX + regOPPBUFid_OPPBUF_3D_PARAMETERS_0, .OPPBUF_3D_PARAMETERS_1 = DCN_BASE__INST0_SEGregOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX + regOPPBUFid_OPPBUF_3D_PARAMETERS_1, .OPP_PIPE_CONTROL = DCN_BASE__INST0_SEGregOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX + regOPP_PIPEid_OPP_PIPE_CONTROL, .DPG_CONTROL = DCN_BASE__INST0_SEGregDPGid_DPG_CONTROL_BASE_IDX + regDPGid_DPG_CONTROL, .DPG_DIMENSIONS = DCN_BASE__INST0_SEGregDPGid_DPG_DIMENSIONS_BASE_IDX + regDPGid_DPG_DIMENSIONS, .DPG_OFFSET_SEGMENT = DCN_BASE__INST0_SEGregDPGid_DPG_OFFSET_SEGMENT_BASE_IDX + regDPGid_DPG_OFFSET_SEGMENT, .DPG_COLOUR_B_CB = DCN_BASE__INST0_SEGregDPGid_DPG_COLOUR_B_CB_BASE_IDX + regDPGid_DPG_COLOUR_B_CB, .DPG_COLOUR_G_Y = DCN_BASE__INST0_SEGregDPGid_DPG_COLOUR_G_Y_BASE_IDX + regDPGid_DPG_COLOUR_G_Y, .DPG_COLOUR_R_CR = DCN_BASE__INST0_SEGregDPGid_DPG_COLOUR_R_CR_BASE_IDX + regDPGid_DPG_COLOUR_R_CR, .DPG_RAMP_CONTROL = DCN_BASE__INST0_SEGregDPGid_DPG_RAMP_CONTROL_BASE_IDX + regDPGid_DPG_RAMP_CONTROL, .DPG_STATUS = DCN_BASE__INST0_SEGregDPGid_DPG_STATUS_BASE_IDX + regDPGid_DPG_STATUS, .FMT_422_CONTROL = DCN_BASE__INST0_SEGregFMTid_FMT_422_CONTROL_BASE_IDX + regFMTid_FMT_422_CONTROL,}\ | ||||
| 498 | [id] = {\ | ||||
| 499 | OPP_REG_LIST_DCN30(id).FMT_BIT_DEPTH_CONTROL = DCN_BASE__INST0_SEGregFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX + regFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = DCN_BASE__INST0_SEGregFMTid_FMT_CONTROL_BASE_IDX + regFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = DCN_BASE__INST0_SEGregFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX + regFMTid_FMT_DITHER_RAND_R_SEED, .FMT_DITHER_RAND_G_SEED = DCN_BASE__INST0_SEGregFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX + regFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED = DCN_BASE__INST0_SEGregFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX + regFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = DCN_BASE__INST0_SEGregFMTid_FMT_CLAMP_CNTL_BASE_IDX + regFMTid_FMT_CLAMP_CNTL, .FMT_DYNAMIC_EXP_CNTL = DCN_BASE__INST0_SEGregFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX + regFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_MAP420_MEMORY_CONTROL = DCN_BASE__INST0_SEGregFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX + regFMTid_FMT_MAP420_MEMORY_CONTROL, .OPPBUF_CONTROL = DCN_BASE__INST0_SEGregOPPBUFid_OPPBUF_CONTROL_BASE_IDX + regOPPBUFid_OPPBUF_CONTROL, .OPPBUF_3D_PARAMETERS_0 = DCN_BASE__INST0_SEGregOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX + regOPPBUFid_OPPBUF_3D_PARAMETERS_0, .OPPBUF_3D_PARAMETERS_1 = DCN_BASE__INST0_SEGregOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX + regOPPBUFid_OPPBUF_3D_PARAMETERS_1, .OPP_PIPE_CONTROL = DCN_BASE__INST0_SEGregOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX + regOPP_PIPEid_OPP_PIPE_CONTROL, .DPG_CONTROL = DCN_BASE__INST0_SEGregDPGid_DPG_CONTROL_BASE_IDX + regDPGid_DPG_CONTROL, .DPG_DIMENSIONS = DCN_BASE__INST0_SEGregDPGid_DPG_DIMENSIONS_BASE_IDX + regDPGid_DPG_DIMENSIONS, .DPG_OFFSET_SEGMENT = DCN_BASE__INST0_SEGregDPGid_DPG_OFFSET_SEGMENT_BASE_IDX + regDPGid_DPG_OFFSET_SEGMENT, .DPG_COLOUR_B_CB = DCN_BASE__INST0_SEGregDPGid_DPG_COLOUR_B_CB_BASE_IDX + regDPGid_DPG_COLOUR_B_CB, .DPG_COLOUR_G_Y = DCN_BASE__INST0_SEGregDPGid_DPG_COLOUR_G_Y_BASE_IDX + regDPGid_DPG_COLOUR_G_Y, .DPG_COLOUR_R_CR = DCN_BASE__INST0_SEGregDPGid_DPG_COLOUR_R_CR_BASE_IDX + regDPGid_DPG_COLOUR_R_CR, .DPG_RAMP_CONTROL = DCN_BASE__INST0_SEGregDPGid_DPG_RAMP_CONTROL_BASE_IDX + regDPGid_DPG_RAMP_CONTROL, .DPG_STATUS = DCN_BASE__INST0_SEGregDPGid_DPG_STATUS_BASE_IDX + regDPGid_DPG_STATUS, .FMT_422_CONTROL = DCN_BASE__INST0_SEGregFMTid_FMT_422_CONTROL_BASE_IDX + regFMTid_FMT_422_CONTROL,\ | ||||
| 500 | } | ||||
| 501 | |||||
| 502 | static const struct dcn20_opp_registers opp_regs[] = { | ||||
| 503 | opp_regs(0)[0] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x1841, .FMT_CONTROL = 0x000034C0 + 0x1840, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x1842, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1843, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x1844, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1845 , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x183f, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x1847, .OPPBUF_CONTROL = 0x000034C0 + 0x1884 , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1885, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x1886, .OPP_PIPE_CONTROL = 0x000034C0 + 0x188c , .DPG_CONTROL = 0x000034C0 + 0x1854, .DPG_DIMENSIONS = 0x000034C0 + 0x1856, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x185a, .DPG_COLOUR_B_CB = 0x000034C0 + 0x1859, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1858 , .DPG_COLOUR_R_CR = 0x000034C0 + 0x1857, .DPG_RAMP_CONTROL = 0x000034C0 + 0x1855, .DPG_STATUS = 0x000034C0 + 0x185b, .FMT_422_CONTROL = 0x000034C0 + 0x1849,}, | ||||
| 504 | opp_regs(1)[1] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x189b, .FMT_CONTROL = 0x000034C0 + 0x189a, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x189c, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x189d, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x189e, .FMT_CLAMP_CNTL = 0x000034C0 + 0x189f , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x1899, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x18a1, .OPPBUF_CONTROL = 0x000034C0 + 0x18de , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x18df, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x18e0, .OPP_PIPE_CONTROL = 0x000034C0 + 0x18e6 , .DPG_CONTROL = 0x000034C0 + 0x18ae, .DPG_DIMENSIONS = 0x000034C0 + 0x18b0, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x18b4, .DPG_COLOUR_B_CB = 0x000034C0 + 0x18b3, .DPG_COLOUR_G_Y = 0x000034C0 + 0x18b2 , .DPG_COLOUR_R_CR = 0x000034C0 + 0x18b1, .DPG_RAMP_CONTROL = 0x000034C0 + 0x18af, .DPG_STATUS = 0x000034C0 + 0x18b5, .FMT_422_CONTROL = 0x000034C0 + 0x18a3,}, | ||||
| 505 | opp_regs(2)[2] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x18f5, .FMT_CONTROL = 0x000034C0 + 0x18f4, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x18f6, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x18f7, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x18f8, .FMT_CLAMP_CNTL = 0x000034C0 + 0x18f9 , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x18f3, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x18fb, .OPPBUF_CONTROL = 0x000034C0 + 0x1938 , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1939, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x193a, .OPP_PIPE_CONTROL = 0x000034C0 + 0x1940 , .DPG_CONTROL = 0x000034C0 + 0x1908, .DPG_DIMENSIONS = 0x000034C0 + 0x190a, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x190e, .DPG_COLOUR_B_CB = 0x000034C0 + 0x190d, .DPG_COLOUR_G_Y = 0x000034C0 + 0x190c , .DPG_COLOUR_R_CR = 0x000034C0 + 0x190b, .DPG_RAMP_CONTROL = 0x000034C0 + 0x1909, .DPG_STATUS = 0x000034C0 + 0x190f, .FMT_422_CONTROL = 0x000034C0 + 0x18fd,}, | ||||
| 506 | opp_regs(3)[3] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x194f, .FMT_CONTROL = 0x000034C0 + 0x194e, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x1950, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1951, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x1952, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1953 , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x194d, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x1955, .OPPBUF_CONTROL = 0x000034C0 + 0x1992 , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1993, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x1994, .OPP_PIPE_CONTROL = 0x000034C0 + 0x199a , .DPG_CONTROL = 0x000034C0 + 0x1962, .DPG_DIMENSIONS = 0x000034C0 + 0x1964, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x1968, .DPG_COLOUR_B_CB = 0x000034C0 + 0x1967, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1966 , .DPG_COLOUR_R_CR = 0x000034C0 + 0x1965, .DPG_RAMP_CONTROL = 0x000034C0 + 0x1963, .DPG_STATUS = 0x000034C0 + 0x1969, .FMT_422_CONTROL = 0x000034C0 + 0x1957,} | ||||
| 507 | }; | ||||
| 508 | |||||
| 509 | static const struct dcn20_opp_shift opp_shift = { | ||||
| 510 | OPP_MASK_SH_LIST_DCN20(__SHIFT).FMT_TRUNCATE_EN = 0x0, .FMT_TRUNCATE_DEPTH = 0x4, .FMT_TRUNCATE_MODE = 0x1, .FMT_SPATIAL_DITHER_EN = 0x8, .FMT_SPATIAL_DITHER_MODE = 0x9, .FMT_SPATIAL_DITHER_DEPTH = 0xb, .FMT_TEMPORAL_DITHER_EN = 0x10, .FMT_HIGHPASS_RANDOM_ENABLE = 0xf, .FMT_FRAME_RANDOM_ENABLE = 0xd, .FMT_RGB_RANDOM_ENABLE = 0xe, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0x8, .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0xc, .FMT_PIXEL_ENCODING = 0x10, .FMT_STEREOSYNC_OVERRIDE = 0x0, .FMT_RAND_R_SEED = 0x0 , .FMT_RAND_G_SEED = 0x0, .FMT_RAND_B_SEED = 0x0, .FMT_CLAMP_DATA_EN = 0x0, .FMT_CLAMP_COLOR_FORMAT = 0x10, .FMT_DYNAMIC_EXP_EN = 0x0, .FMT_DYNAMIC_EXP_MODE = 0x4, .FMT_MAP420MEM_PWR_FORCE = 0x0, .OPPBUF_ACTIVE_WIDTH = 0x0, .OPPBUF_PIXEL_REPETITION = 0x18 , .OPPBUF_3D_VACT_SPACE1_SIZE = 0x0, .OPPBUF_3D_VACT_SPACE2_SIZE = 0xa, .OPP_PIPE_CLOCK_EN = 0x0, .DPG_EN = 0x0, .DPG_MODE = 0x4 , .DPG_DYNAMIC_RANGE = 0x8, .DPG_BIT_DEPTH = 0xc, .DPG_VRES = 0x10, .DPG_HRES = 0x14, .DPG_ACTIVE_WIDTH = 0x10, .DPG_ACTIVE_HEIGHT = 0x0, .DPG_X_OFFSET = 0x0, .DPG_SEGMENT_WIDTH = 0x10, .DPG_COLOUR0_R_CR = 0x0, .DPG_COLOUR1_R_CR = 0x10, .DPG_COLOUR0_B_CB = 0x0, .DPG_COLOUR1_B_CB = 0x10, .DPG_COLOUR0_G_Y = 0x0, .DPG_COLOUR1_G_Y = 0x10, .DPG_RAMP0_OFFSET = 0x0, .DPG_INC0 = 0x18, .DPG_INC1 = 0x1c, .DPG_DOUBLE_BUFFER_PENDING = 0x0, .OPPBUF_DISPLAY_SEGMENTATION = 0x10, .OPPBUF_OVERLAP_PIXEL_NUM = 0x14, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x0 | ||||
| 511 | }; | ||||
| 512 | |||||
| 513 | static const struct dcn20_opp_mask opp_mask = { | ||||
| 514 | OPP_MASK_SH_LIST_DCN20(_MASK).FMT_TRUNCATE_EN = 0x00000001L, .FMT_TRUNCATE_DEPTH = 0x00000030L , .FMT_TRUNCATE_MODE = 0x00000002L, .FMT_SPATIAL_DITHER_EN = 0x00000100L , .FMT_SPATIAL_DITHER_MODE = 0x00000600L, .FMT_SPATIAL_DITHER_DEPTH = 0x00001800L, .FMT_TEMPORAL_DITHER_EN = 0x00010000L, .FMT_HIGHPASS_RANDOM_ENABLE = 0x00008000L, .FMT_FRAME_RANDOM_ENABLE = 0x00002000L, .FMT_RGB_RANDOM_ENABLE = 0x00004000L, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0x00000F00L , .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0x00003000L, . FMT_PIXEL_ENCODING = 0x00030000L, .FMT_STEREOSYNC_OVERRIDE = 0x00000001L , .FMT_RAND_R_SEED = 0x000000FFL, .FMT_RAND_G_SEED = 0x000000FFL , .FMT_RAND_B_SEED = 0x000000FFL, .FMT_CLAMP_DATA_EN = 0x00000001L , .FMT_CLAMP_COLOR_FORMAT = 0x00070000L, .FMT_DYNAMIC_EXP_EN = 0x00000001L, .FMT_DYNAMIC_EXP_MODE = 0x00000010L, .FMT_MAP420MEM_PWR_FORCE = 0x00000003L, .OPPBUF_ACTIVE_WIDTH = 0x00003FFFL, .OPPBUF_PIXEL_REPETITION = 0x0F000000L, .OPPBUF_3D_VACT_SPACE1_SIZE = 0x000003FFL, .OPPBUF_3D_VACT_SPACE2_SIZE = 0x000FFC00L, .OPP_PIPE_CLOCK_EN = 0x00000001L, .DPG_EN = 0x00000001L , .DPG_MODE = 0x00000070L, .DPG_DYNAMIC_RANGE = 0x00000100L, . DPG_BIT_DEPTH = 0x00003000L, .DPG_VRES = 0x000F0000L, .DPG_HRES = 0x00F00000L, .DPG_ACTIVE_WIDTH = 0x3FFF0000L, .DPG_ACTIVE_HEIGHT = 0x00003FFFL, .DPG_X_OFFSET = 0x00003FFFL, .DPG_SEGMENT_WIDTH = 0x3FFF0000L, .DPG_COLOUR0_R_CR = 0x0000FFFFL, .DPG_COLOUR1_R_CR = 0xFFFF0000L, .DPG_COLOUR0_B_CB = 0x0000FFFFL, .DPG_COLOUR1_B_CB = 0xFFFF0000L, .DPG_COLOUR0_G_Y = 0x0000FFFFL, .DPG_COLOUR1_G_Y = 0xFFFF0000L, .DPG_RAMP0_OFFSET = 0x0000FFFFL, .DPG_INC0 = 0x0F000000L , .DPG_INC1 = 0xF0000000L, .DPG_DOUBLE_BUFFER_PENDING = 0x00000001L , .OPPBUF_DISPLAY_SEGMENTATION = 0x00070000L, .OPPBUF_OVERLAP_PIXEL_NUM = 0x00F00000L, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x00000001L | ||||
| 515 | }; | ||||
| 516 | |||||
| 517 | #define aux_engine_regs(id)[id] = { .AUX_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_CONTROL_BASE_IDX + regDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_ARB_CONTROL_BASE_IDX + regDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = DCN_BASE__INST0_SEGregDP_AUXid_AUX_SW_DATA_BASE_IDX + regDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_SW_CONTROL_BASE_IDX + regDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX + regDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGregDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX + regDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_SW_STATUS = DCN_BASE__INST0_SEGregDP_AUXid_AUX_SW_STATUS_BASE_IDX + regDP_AUXid_AUX_SW_STATUS, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, .AUX_RESET_MASK = 0x00000010L, }\ | ||||
| 518 | [id] = {\ | ||||
| 519 | AUX_COMMON_REG_LIST0(id).AUX_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_CONTROL_BASE_IDX + regDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_ARB_CONTROL_BASE_IDX + regDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = DCN_BASE__INST0_SEGregDP_AUXid_AUX_SW_DATA_BASE_IDX + regDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_SW_CONTROL_BASE_IDX + regDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGregDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX + regDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGregDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX + regDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_SW_STATUS = DCN_BASE__INST0_SEGregDP_AUXid_AUX_SW_STATUS_BASE_IDX + regDP_AUXid_AUX_SW_STATUS, \ | ||||
| 520 | .AUXN_IMPCAL = 0, \ | ||||
| 521 | .AUXP_IMPCAL = 0, \ | ||||
| 522 | .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK0x00000010L, \ | ||||
| 523 | } | ||||
| 524 | |||||
| 525 | static const struct dce110_aux_registers aux_engine_regs[] = { | ||||
| 526 | aux_engine_regs(0)[0] = { .AUX_CONTROL = 0x000034C0 + 0x1f50, .AUX_ARB_CONTROL = 0x000034C0 + 0x1f52, .AUX_SW_DATA = 0x000034C0 + 0x1f56, .AUX_SW_CONTROL = 0x000034C0 + 0x1f51, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1f53, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f5b, .AUX_SW_STATUS = 0x000034C0 + 0x1f54, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | ||||
| 527 | aux_engine_regs(1)[1] = { .AUX_CONTROL = 0x000034C0 + 0x1f6c, .AUX_ARB_CONTROL = 0x000034C0 + 0x1f6e, .AUX_SW_DATA = 0x000034C0 + 0x1f72, .AUX_SW_CONTROL = 0x000034C0 + 0x1f6d, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1f6f, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f77, .AUX_SW_STATUS = 0x000034C0 + 0x1f70, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | ||||
| 528 | aux_engine_regs(2)[2] = { .AUX_CONTROL = 0x000034C0 + 0x1f88, .AUX_ARB_CONTROL = 0x000034C0 + 0x1f8a, .AUX_SW_DATA = 0x000034C0 + 0x1f8e, .AUX_SW_CONTROL = 0x000034C0 + 0x1f89, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1f8b, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f93, .AUX_SW_STATUS = 0x000034C0 + 0x1f8c, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | ||||
| 529 | aux_engine_regs(3)[3] = { .AUX_CONTROL = 0x000034C0 + 0x1fa4, .AUX_ARB_CONTROL = 0x000034C0 + 0x1fa6, .AUX_SW_DATA = 0x000034C0 + 0x1faa, .AUX_SW_CONTROL = 0x000034C0 + 0x1fa5, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1fa7, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1faf, .AUX_SW_STATUS = 0x000034C0 + 0x1fa8, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | ||||
| 530 | aux_engine_regs(4)[4] = { .AUX_CONTROL = 0x000034C0 + 0x1fc0, .AUX_ARB_CONTROL = 0x000034C0 + 0x1fc2, .AUX_SW_DATA = 0x000034C0 + 0x1fc6, .AUX_SW_CONTROL = 0x000034C0 + 0x1fc1, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1fc3, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fcb, .AUX_SW_STATUS = 0x000034C0 + 0x1fc4, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, } | ||||
| 531 | }; | ||||
| 532 | |||||
| 533 | #define dwbc_regs_dcn3(id)[id] = { .DWB_ENABLE_CLK_CTRL = 0x000034C0 + 0x3228, .DWB_MEM_PWR_CTRL = 0x000034C0 + 0x3229, .FC_MODE_CTRL = 0x000034C0 + 0x322a, . FC_FLOW_CTRL = 0x000034C0 + 0x322b, .FC_WINDOW_START = 0x000034C0 + 0x322c, .FC_WINDOW_SIZE = 0x000034C0 + 0x322d, .FC_SOURCE_SIZE = 0x000034C0 + 0x322e, .DWB_UPDATE_CTRL = 0x000034C0 + 0x322f , .DWB_CRC_CTRL = 0x000034C0 + 0x3230, .DWB_CRC_MASK_R_G = 0x000034C0 + 0x3231, .DWB_CRC_MASK_B_A = 0x000034C0 + 0x3232, .DWB_CRC_VAL_R_G = 0x000034C0 + 0x3233, .DWB_CRC_VAL_B_A = 0x000034C0 + 0x3234 , .DWB_OUT_CTRL = 0x000034C0 + 0x3235, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = 0x000034C0 + 0x3236, .DWB_MMHUBBUB_BACKPRESSURE_CNT = 0x000034C0 + 0x3237, .DWB_HOST_READ_CONTROL = 0x000034C0 + 0x3238, .DWB_SOFT_RESET = 0x000034C0 + 0x323b, .DWB_HDR_MULT_COEF = 0x000034C0 + 0x3294 , .DWB_GAMUT_REMAP_MODE = 0x000034C0 + 0x3295, .DWB_GAMUT_REMAP_COEF_FORMAT = 0x000034C0 + 0x3296, .DWB_GAMUT_REMAPA_C11_C12 = 0x000034C0 + 0x3297, .DWB_GAMUT_REMAPA_C13_C14 = 0x000034C0 + 0x3298, . DWB_GAMUT_REMAPA_C21_C22 = 0x000034C0 + 0x3299, .DWB_GAMUT_REMAPA_C23_C24 = 0x000034C0 + 0x329a, .DWB_GAMUT_REMAPA_C31_C32 = 0x000034C0 + 0x329b, .DWB_GAMUT_REMAPA_C33_C34 = 0x000034C0 + 0x329c, . DWB_GAMUT_REMAPB_C11_C12 = 0x000034C0 + 0x329d, .DWB_GAMUT_REMAPB_C13_C14 = 0x000034C0 + 0x329e, .DWB_GAMUT_REMAPB_C21_C22 = 0x000034C0 + 0x329f, .DWB_GAMUT_REMAPB_C23_C24 = 0x000034C0 + 0x32a0, . DWB_GAMUT_REMAPB_C31_C32 = 0x000034C0 + 0x32a1, .DWB_GAMUT_REMAPB_C33_C34 = 0x000034C0 + 0x32a2, .DWB_OGAM_CONTROL = 0x000034C0 + 0x32a3 , .DWB_OGAM_LUT_INDEX = 0x000034C0 + 0x32a4, .DWB_OGAM_LUT_DATA = 0x000034C0 + 0x32a5, .DWB_OGAM_LUT_CONTROL = 0x000034C0 + 0x32a6 , .DWB_OGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x32a7, .DWB_OGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x32a8, .DWB_OGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x32a9, .DWB_OGAM_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x32aa , .DWB_OGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ab, .DWB_OGAM_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x32ac, .DWB_OGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x32ad, .DWB_OGAM_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x32ae , .DWB_OGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x32af, .DWB_OGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x32b0, .DWB_OGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x32b1, .DWB_OGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x32b2, . DWB_OGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x32b3, .DWB_OGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x32b4, .DWB_OGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x32b5, .DWB_OGAM_RAMA_OFFSET_B = 0x000034C0 + 0x32b6, .DWB_OGAM_RAMA_OFFSET_G = 0x000034C0 + 0x32b7, .DWB_OGAM_RAMA_OFFSET_R = 0x000034C0 + 0x32b8, .DWB_OGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x32b9, .DWB_OGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x32ba, .DWB_OGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x32bb, .DWB_OGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x32bc, . DWB_OGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x32bd, .DWB_OGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x32be, .DWB_OGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x32bf, .DWB_OGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x32c0, .DWB_OGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x32c1, .DWB_OGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x32c2, .DWB_OGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x32c3, .DWB_OGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x32c4, .DWB_OGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x32c5, .DWB_OGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x32c6, .DWB_OGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x32c7, .DWB_OGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x32c8, .DWB_OGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x32c9, .DWB_OGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x32ca, .DWB_OGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x32cb, .DWB_OGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x32cc, .DWB_OGAM_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x32cd, .DWB_OGAM_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ce, .DWB_OGAM_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x32cf, .DWB_OGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x32d0 , .DWB_OGAM_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x32d1, .DWB_OGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x32d2, .DWB_OGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x32d3, .DWB_OGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x32d4, . DWB_OGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x32d5, .DWB_OGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x32d6, .DWB_OGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x32d7, .DWB_OGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x32d8, . DWB_OGAM_RAMB_OFFSET_B = 0x000034C0 + 0x32d9, .DWB_OGAM_RAMB_OFFSET_G = 0x000034C0 + 0x32da, .DWB_OGAM_RAMB_OFFSET_R = 0x000034C0 + 0x32db, .DWB_OGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x32dc, .DWB_OGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x32dd, .DWB_OGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x32de, .DWB_OGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x32df, . DWB_OGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x32e0, .DWB_OGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x32e1, .DWB_OGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x32e2, .DWB_OGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x32e3, .DWB_OGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x32e4, .DWB_OGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x32e5, .DWB_OGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x32e6, .DWB_OGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x32e7, .DWB_OGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x32e8, .DWB_OGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x32e9, .DWB_OGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x32ea, .DWB_OGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x32eb, .DWB_OGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x32ec,}\ | ||||
| 534 | [id] = {\ | ||||
| 535 | DWBC_COMMON_REG_LIST_DCN30(id).DWB_ENABLE_CLK_CTRL = 0x000034C0 + 0x3228, .DWB_MEM_PWR_CTRL = 0x000034C0 + 0x3229, .FC_MODE_CTRL = 0x000034C0 + 0x322a, . FC_FLOW_CTRL = 0x000034C0 + 0x322b, .FC_WINDOW_START = 0x000034C0 + 0x322c, .FC_WINDOW_SIZE = 0x000034C0 + 0x322d, .FC_SOURCE_SIZE = 0x000034C0 + 0x322e, .DWB_UPDATE_CTRL = 0x000034C0 + 0x322f , .DWB_CRC_CTRL = 0x000034C0 + 0x3230, .DWB_CRC_MASK_R_G = 0x000034C0 + 0x3231, .DWB_CRC_MASK_B_A = 0x000034C0 + 0x3232, .DWB_CRC_VAL_R_G = 0x000034C0 + 0x3233, .DWB_CRC_VAL_B_A = 0x000034C0 + 0x3234 , .DWB_OUT_CTRL = 0x000034C0 + 0x3235, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = 0x000034C0 + 0x3236, .DWB_MMHUBBUB_BACKPRESSURE_CNT = 0x000034C0 + 0x3237, .DWB_HOST_READ_CONTROL = 0x000034C0 + 0x3238, .DWB_SOFT_RESET = 0x000034C0 + 0x323b, .DWB_HDR_MULT_COEF = 0x000034C0 + 0x3294 , .DWB_GAMUT_REMAP_MODE = 0x000034C0 + 0x3295, .DWB_GAMUT_REMAP_COEF_FORMAT = 0x000034C0 + 0x3296, .DWB_GAMUT_REMAPA_C11_C12 = 0x000034C0 + 0x3297, .DWB_GAMUT_REMAPA_C13_C14 = 0x000034C0 + 0x3298, . DWB_GAMUT_REMAPA_C21_C22 = 0x000034C0 + 0x3299, .DWB_GAMUT_REMAPA_C23_C24 = 0x000034C0 + 0x329a, .DWB_GAMUT_REMAPA_C31_C32 = 0x000034C0 + 0x329b, .DWB_GAMUT_REMAPA_C33_C34 = 0x000034C0 + 0x329c, . DWB_GAMUT_REMAPB_C11_C12 = 0x000034C0 + 0x329d, .DWB_GAMUT_REMAPB_C13_C14 = 0x000034C0 + 0x329e, .DWB_GAMUT_REMAPB_C21_C22 = 0x000034C0 + 0x329f, .DWB_GAMUT_REMAPB_C23_C24 = 0x000034C0 + 0x32a0, . DWB_GAMUT_REMAPB_C31_C32 = 0x000034C0 + 0x32a1, .DWB_GAMUT_REMAPB_C33_C34 = 0x000034C0 + 0x32a2, .DWB_OGAM_CONTROL = 0x000034C0 + 0x32a3 , .DWB_OGAM_LUT_INDEX = 0x000034C0 + 0x32a4, .DWB_OGAM_LUT_DATA = 0x000034C0 + 0x32a5, .DWB_OGAM_LUT_CONTROL = 0x000034C0 + 0x32a6 , .DWB_OGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x32a7, .DWB_OGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x32a8, .DWB_OGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x32a9, .DWB_OGAM_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x32aa , .DWB_OGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ab, .DWB_OGAM_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x32ac, .DWB_OGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x32ad, .DWB_OGAM_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x32ae , .DWB_OGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x32af, .DWB_OGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x32b0, .DWB_OGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x32b1, .DWB_OGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x32b2, . DWB_OGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x32b3, .DWB_OGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x32b4, .DWB_OGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x32b5, .DWB_OGAM_RAMA_OFFSET_B = 0x000034C0 + 0x32b6, .DWB_OGAM_RAMA_OFFSET_G = 0x000034C0 + 0x32b7, .DWB_OGAM_RAMA_OFFSET_R = 0x000034C0 + 0x32b8, .DWB_OGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x32b9, .DWB_OGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x32ba, .DWB_OGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x32bb, .DWB_OGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x32bc, . DWB_OGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x32bd, .DWB_OGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x32be, .DWB_OGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x32bf, .DWB_OGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x32c0, .DWB_OGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x32c1, .DWB_OGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x32c2, .DWB_OGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x32c3, .DWB_OGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x32c4, .DWB_OGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x32c5, .DWB_OGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x32c6, .DWB_OGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x32c7, .DWB_OGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x32c8, .DWB_OGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x32c9, .DWB_OGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x32ca, .DWB_OGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x32cb, .DWB_OGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x32cc, .DWB_OGAM_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x32cd, .DWB_OGAM_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ce, .DWB_OGAM_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x32cf, .DWB_OGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x32d0 , .DWB_OGAM_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x32d1, .DWB_OGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x32d2, .DWB_OGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x32d3, .DWB_OGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x32d4, . DWB_OGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x32d5, .DWB_OGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x32d6, .DWB_OGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x32d7, .DWB_OGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x32d8, . DWB_OGAM_RAMB_OFFSET_B = 0x000034C0 + 0x32d9, .DWB_OGAM_RAMB_OFFSET_G = 0x000034C0 + 0x32da, .DWB_OGAM_RAMB_OFFSET_R = 0x000034C0 + 0x32db, .DWB_OGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x32dc, .DWB_OGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x32dd, .DWB_OGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x32de, .DWB_OGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x32df, . DWB_OGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x32e0, .DWB_OGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x32e1, .DWB_OGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x32e2, .DWB_OGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x32e3, .DWB_OGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x32e4, .DWB_OGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x32e5, .DWB_OGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x32e6, .DWB_OGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x32e7, .DWB_OGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x32e8, .DWB_OGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x32e9, .DWB_OGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x32ea, .DWB_OGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x32eb, .DWB_OGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x32ec,\ | ||||
| 536 | } | ||||
| 537 | |||||
| 538 | static const struct dcn30_dwbc_registers dwbc30_regs[] = { | ||||
| 539 | dwbc_regs_dcn3(0)[0] = { .DWB_ENABLE_CLK_CTRL = 0x000034C0 + 0x3228, .DWB_MEM_PWR_CTRL = 0x000034C0 + 0x3229, .FC_MODE_CTRL = 0x000034C0 + 0x322a, . FC_FLOW_CTRL = 0x000034C0 + 0x322b, .FC_WINDOW_START = 0x000034C0 + 0x322c, .FC_WINDOW_SIZE = 0x000034C0 + 0x322d, .FC_SOURCE_SIZE = 0x000034C0 + 0x322e, .DWB_UPDATE_CTRL = 0x000034C0 + 0x322f , .DWB_CRC_CTRL = 0x000034C0 + 0x3230, .DWB_CRC_MASK_R_G = 0x000034C0 + 0x3231, .DWB_CRC_MASK_B_A = 0x000034C0 + 0x3232, .DWB_CRC_VAL_R_G = 0x000034C0 + 0x3233, .DWB_CRC_VAL_B_A = 0x000034C0 + 0x3234 , .DWB_OUT_CTRL = 0x000034C0 + 0x3235, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = 0x000034C0 + 0x3236, .DWB_MMHUBBUB_BACKPRESSURE_CNT = 0x000034C0 + 0x3237, .DWB_HOST_READ_CONTROL = 0x000034C0 + 0x3238, .DWB_SOFT_RESET = 0x000034C0 + 0x323b, .DWB_HDR_MULT_COEF = 0x000034C0 + 0x3294 , .DWB_GAMUT_REMAP_MODE = 0x000034C0 + 0x3295, .DWB_GAMUT_REMAP_COEF_FORMAT = 0x000034C0 + 0x3296, .DWB_GAMUT_REMAPA_C11_C12 = 0x000034C0 + 0x3297, .DWB_GAMUT_REMAPA_C13_C14 = 0x000034C0 + 0x3298, . DWB_GAMUT_REMAPA_C21_C22 = 0x000034C0 + 0x3299, .DWB_GAMUT_REMAPA_C23_C24 = 0x000034C0 + 0x329a, .DWB_GAMUT_REMAPA_C31_C32 = 0x000034C0 + 0x329b, .DWB_GAMUT_REMAPA_C33_C34 = 0x000034C0 + 0x329c, . DWB_GAMUT_REMAPB_C11_C12 = 0x000034C0 + 0x329d, .DWB_GAMUT_REMAPB_C13_C14 = 0x000034C0 + 0x329e, .DWB_GAMUT_REMAPB_C21_C22 = 0x000034C0 + 0x329f, .DWB_GAMUT_REMAPB_C23_C24 = 0x000034C0 + 0x32a0, . DWB_GAMUT_REMAPB_C31_C32 = 0x000034C0 + 0x32a1, .DWB_GAMUT_REMAPB_C33_C34 = 0x000034C0 + 0x32a2, .DWB_OGAM_CONTROL = 0x000034C0 + 0x32a3 , .DWB_OGAM_LUT_INDEX = 0x000034C0 + 0x32a4, .DWB_OGAM_LUT_DATA = 0x000034C0 + 0x32a5, .DWB_OGAM_LUT_CONTROL = 0x000034C0 + 0x32a6 , .DWB_OGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x32a7, .DWB_OGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x32a8, .DWB_OGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x32a9, .DWB_OGAM_RAMA_START_BASE_CNTL_B = 0x000034C0 + 0x32aa , .DWB_OGAM_RAMA_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ab, .DWB_OGAM_RAMA_START_BASE_CNTL_G = 0x000034C0 + 0x32ac, .DWB_OGAM_RAMA_START_SLOPE_CNTL_G = 0x000034C0 + 0x32ad, .DWB_OGAM_RAMA_START_BASE_CNTL_R = 0x000034C0 + 0x32ae , .DWB_OGAM_RAMA_START_SLOPE_CNTL_R = 0x000034C0 + 0x32af, .DWB_OGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x32b0, .DWB_OGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x32b1, .DWB_OGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x32b2, . DWB_OGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x32b3, .DWB_OGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x32b4, .DWB_OGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x32b5, .DWB_OGAM_RAMA_OFFSET_B = 0x000034C0 + 0x32b6, .DWB_OGAM_RAMA_OFFSET_G = 0x000034C0 + 0x32b7, .DWB_OGAM_RAMA_OFFSET_R = 0x000034C0 + 0x32b8, .DWB_OGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x32b9, .DWB_OGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x32ba, .DWB_OGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x32bb, .DWB_OGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x32bc, . DWB_OGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x32bd, .DWB_OGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x32be, .DWB_OGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x32bf, .DWB_OGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x32c0, .DWB_OGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x32c1, .DWB_OGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x32c2, .DWB_OGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x32c3, .DWB_OGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x32c4, .DWB_OGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x32c5, .DWB_OGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x32c6, .DWB_OGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x32c7, .DWB_OGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x32c8, .DWB_OGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x32c9, .DWB_OGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x32ca, .DWB_OGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x32cb, .DWB_OGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x32cc, .DWB_OGAM_RAMB_START_BASE_CNTL_B = 0x000034C0 + 0x32cd, .DWB_OGAM_RAMB_START_SLOPE_CNTL_B = 0x000034C0 + 0x32ce, .DWB_OGAM_RAMB_START_BASE_CNTL_G = 0x000034C0 + 0x32cf, .DWB_OGAM_RAMB_START_SLOPE_CNTL_G = 0x000034C0 + 0x32d0 , .DWB_OGAM_RAMB_START_BASE_CNTL_R = 0x000034C0 + 0x32d1, .DWB_OGAM_RAMB_START_SLOPE_CNTL_R = 0x000034C0 + 0x32d2, .DWB_OGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x32d3, .DWB_OGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x32d4, . DWB_OGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x32d5, .DWB_OGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x32d6, .DWB_OGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x32d7, .DWB_OGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x32d8, . DWB_OGAM_RAMB_OFFSET_B = 0x000034C0 + 0x32d9, .DWB_OGAM_RAMB_OFFSET_G = 0x000034C0 + 0x32da, .DWB_OGAM_RAMB_OFFSET_R = 0x000034C0 + 0x32db, .DWB_OGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x32dc, .DWB_OGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x32dd, .DWB_OGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x32de, .DWB_OGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x32df, . DWB_OGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x32e0, .DWB_OGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x32e1, .DWB_OGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x32e2, .DWB_OGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x32e3, .DWB_OGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x32e4, .DWB_OGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x32e5, .DWB_OGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x32e6, .DWB_OGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x32e7, .DWB_OGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x32e8, .DWB_OGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x32e9, .DWB_OGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x32ea, .DWB_OGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x32eb, .DWB_OGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x32ec,}, | ||||
| 540 | }; | ||||
| 541 | |||||
| 542 | static const struct dcn30_dwbc_shift dwbc30_shift = { | ||||
| 543 | DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT).DWB_ENABLE = 0x0, .DISPCLK_R_DWB_GATE_DIS = 0x4, .DISPCLK_G_DWB_GATE_DIS = 0x8, .DWB_TEST_CLK_SEL = 0xc, .DWB_OGAM_LUT_MEM_PWR_FORCE = 0x10, .DWB_OGAM_LUT_MEM_PWR_DIS = 0x12, .DWB_OGAM_LUT_MEM_PWR_STATE = 0x14, .FC_FRAME_CAPTURE_EN = 0x0, .FC_FRAME_CAPTURE_RATE = 0x4, .FC_WINDOW_CROP_EN = 0x8, .FC_EYE_SELECTION = 0xc, .FC_STEREO_EYE_POLARITY = 0x10, .FC_NEW_CONTENT = 0x14, .FC_FRAME_CAPTURE_EN_CURRENT = 0x1f, .FC_FIRST_PIXEL_DELAY_COUNT = 0x0, .FC_WINDOW_START_X = 0x0, .FC_WINDOW_START_Y = 0x10, .FC_WINDOW_WIDTH = 0x0, .FC_WINDOW_HEIGHT = 0x10, .FC_SOURCE_WIDTH = 0x0, .FC_SOURCE_HEIGHT = 0x10, .DWB_UPDATE_LOCK = 0x0, .DWB_UPDATE_PENDING = 0x4, .DWB_CRC_EN = 0x0, .DWB_CRC_CONT_EN = 0x4, .DWB_CRC_SRC_SEL = 0x8, .DWB_CRC_RED_MASK = 0x0, .DWB_CRC_GREEN_MASK = 0x10, .DWB_CRC_BLUE_MASK = 0x0, .DWB_CRC_A_MASK = 0x10, .DWB_CRC_SIG_RED = 0x0, .DWB_CRC_SIG_GREEN = 0x10, .DWB_CRC_SIG_BLUE = 0x0, . DWB_CRC_SIG_A = 0x10, .OUT_FORMAT = 0x0, .OUT_DENORM = 0x4, . OUT_MAX = 0x8, .OUT_MIN = 0x14, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = 0x0, .DWB_MMHUBBUB_MAX_BACKPRESSURE = 0x0, .DWB_HOST_READ_RATE_CONTROL = 0x0, .DWB_SOFT_RESET = 0x0, .DWB_HDR_MULT_COEF = 0x0, .DWB_GAMUT_REMAP_MODE = 0x0, .DWB_GAMUT_REMAP_MODE_CURRENT = 0x18, .DWB_GAMUT_REMAP_COEF_FORMAT = 0x0, .DWB_GAMUT_REMAPA_C11 = 0x0, .DWB_GAMUT_REMAPA_C12 = 0x10 , .DWB_GAMUT_REMAPA_C13 = 0x0, .DWB_GAMUT_REMAPA_C14 = 0x10, . DWB_GAMUT_REMAPA_C21 = 0x0, .DWB_GAMUT_REMAPA_C22 = 0x10, .DWB_GAMUT_REMAPA_C23 = 0x0, .DWB_GAMUT_REMAPA_C24 = 0x10, .DWB_GAMUT_REMAPA_C31 = 0x0, .DWB_GAMUT_REMAPA_C32 = 0x10, .DWB_GAMUT_REMAPA_C33 = 0x0 , .DWB_GAMUT_REMAPA_C34 = 0x10, .DWB_GAMUT_REMAPB_C11 = 0x0, . DWB_GAMUT_REMAPB_C12 = 0x10, .DWB_GAMUT_REMAPB_C13 = 0x0, .DWB_GAMUT_REMAPB_C14 = 0x10, .DWB_GAMUT_REMAPB_C21 = 0x0, .DWB_GAMUT_REMAPB_C22 = 0x10, .DWB_GAMUT_REMAPB_C23 = 0x0, .DWB_GAMUT_REMAPB_C24 = 0x10 , .DWB_GAMUT_REMAPB_C31 = 0x0, .DWB_GAMUT_REMAPB_C32 = 0x10, . DWB_GAMUT_REMAPB_C33 = 0x0, .DWB_GAMUT_REMAPB_C34 = 0x10, .DWB_OGAM_MODE = 0x0, .DWB_OGAM_SELECT = 0x4, .DWB_OGAM_PWL_DISABLE = 0x8, . DWB_OGAM_MODE_CURRENT = 0x18, .DWB_OGAM_SELECT_CURRENT = 0x1c , .DWB_OGAM_LUT_INDEX = 0x0, .DWB_OGAM_LUT_DATA = 0x0, .DWB_OGAM_LUT_WRITE_COLOR_MASK = 0x0, .DWB_OGAM_LUT_READ_COLOR_SEL = 0x4, .DWB_OGAM_LUT_READ_DBG = 0x8, .DWB_OGAM_LUT_HOST_SEL = 0xc, .DWB_OGAM_LUT_CONFIG_MODE = 0x10, .DWB_OGAM_RAMA_EXP_REGION_START_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_B = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_G = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G = 0x10, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x10, .DWB_OGAM_RAMA_OFFSET_B = 0x0, .DWB_OGAM_RAMA_OFFSET_G = 0x0, .DWB_OGAM_RAMA_OFFSET_R = 0x0, .DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION_START_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_B = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x10, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_G = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x10, .DWB_OGAM_RAMB_EXP_REGION_END_BASE_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x10, .DWB_OGAM_RAMB_OFFSET_B = 0x0, .DWB_OGAM_RAMB_OFFSET_G = 0x0, .DWB_OGAM_RAMB_OFFSET_R = 0x0, .DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x1c, .DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0xc, .DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x1c | ||||
| 544 | }; | ||||
| 545 | |||||
| 546 | static const struct dcn30_dwbc_mask dwbc30_mask = { | ||||
| 547 | DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK).DWB_ENABLE = 0x00000001L, .DISPCLK_R_DWB_GATE_DIS = 0x00000010L , .DISPCLK_G_DWB_GATE_DIS = 0x00000100L, .DWB_TEST_CLK_SEL = 0x00003000L , .DWB_OGAM_LUT_MEM_PWR_FORCE = 0x00030000L, .DWB_OGAM_LUT_MEM_PWR_DIS = 0x00040000L, .DWB_OGAM_LUT_MEM_PWR_STATE = 0x00300000L, .FC_FRAME_CAPTURE_EN = 0x00000001L, .FC_FRAME_CAPTURE_RATE = 0x00000030L, .FC_WINDOW_CROP_EN = 0x00000100L, .FC_EYE_SELECTION = 0x00003000L, .FC_STEREO_EYE_POLARITY = 0x00010000L, .FC_NEW_CONTENT = 0x00100000L, .FC_FRAME_CAPTURE_EN_CURRENT = 0x80000000L, .FC_FIRST_PIXEL_DELAY_COUNT = 0x00000FFFL, .FC_WINDOW_START_X = 0x00001FFFL, .FC_WINDOW_START_Y = 0x1FFF0000L, .FC_WINDOW_WIDTH = 0x00000FFFL, .FC_WINDOW_HEIGHT = 0x0FFF0000L, .FC_SOURCE_WIDTH = 0x00007FFFL, .FC_SOURCE_HEIGHT = 0x7FFF0000L, .DWB_UPDATE_LOCK = 0x00000001L, .DWB_UPDATE_PENDING = 0x00000010L, .DWB_CRC_EN = 0x00000001L, .DWB_CRC_CONT_EN = 0x00000010L, .DWB_CRC_SRC_SEL = 0x00000300L, .DWB_CRC_RED_MASK = 0x0000FFFFL, .DWB_CRC_GREEN_MASK = 0xFFFF0000L, .DWB_CRC_BLUE_MASK = 0x0000FFFFL, .DWB_CRC_A_MASK = 0xFFFF0000L, .DWB_CRC_SIG_RED = 0x0000FFFFL, .DWB_CRC_SIG_GREEN = 0xFFFF0000L, .DWB_CRC_SIG_BLUE = 0x0000FFFFL, .DWB_CRC_SIG_A = 0xFFFF0000L, .OUT_FORMAT = 0x00000003L, .OUT_DENORM = 0x00000030L , .OUT_MAX = 0x0003FF00L, .OUT_MIN = 0x3FF00000L, .DWB_MMHUBBUB_BACKPRESSURE_CNT_EN = 0x00000001L, .DWB_MMHUBBUB_MAX_BACKPRESSURE = 0x0000FFFFL, .DWB_HOST_READ_RATE_CONTROL = 0x000000FFL, .DWB_SOFT_RESET = 0x00000001L, .DWB_HDR_MULT_COEF = 0x0007FFFFL, .DWB_GAMUT_REMAP_MODE = 0x00000003L, .DWB_GAMUT_REMAP_MODE_CURRENT = 0x03000000L, . DWB_GAMUT_REMAP_COEF_FORMAT = 0x00000001L, .DWB_GAMUT_REMAPA_C11 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C12 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C13 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C14 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C21 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C22 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C23 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C24 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C31 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C32 = 0xFFFF0000L, .DWB_GAMUT_REMAPA_C33 = 0x0000FFFFL, .DWB_GAMUT_REMAPA_C34 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C11 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C12 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C13 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C14 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C21 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C22 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C23 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C24 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C31 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C32 = 0xFFFF0000L, .DWB_GAMUT_REMAPB_C33 = 0x0000FFFFL, .DWB_GAMUT_REMAPB_C34 = 0xFFFF0000L, .DWB_OGAM_MODE = 0x00000003L, .DWB_OGAM_SELECT = 0x00000010L, .DWB_OGAM_PWL_DISABLE = 0x00000100L, .DWB_OGAM_MODE_CURRENT = 0x03000000L, .DWB_OGAM_SELECT_CURRENT = 0x10000000L, .DWB_OGAM_LUT_INDEX = 0x000001FFL, .DWB_OGAM_LUT_DATA = 0x0003FFFFL, .DWB_OGAM_LUT_WRITE_COLOR_MASK = 0x00000007L, .DWB_OGAM_LUT_READ_COLOR_SEL = 0x00000030L, .DWB_OGAM_LUT_READ_DBG = 0x00000100L, .DWB_OGAM_LUT_HOST_SEL = 0x00001000L, .DWB_OGAM_LUT_CONFIG_MODE = 0x00010000L, .DWB_OGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .DWB_OGAM_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x07F00000L , .DWB_OGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_BASE_G = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_START_BASE_R = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R = 0x0003FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_G = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_END_G = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G = 0xFFFF0000L, .DWB_OGAM_RAMA_EXP_REGION_END_BASE_R = 0x0003FFFFL , .DWB_OGAM_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R = 0xFFFF0000L, .DWB_OGAM_RAMA_OFFSET_B = 0x0007FFFFL, .DWB_OGAM_RAMA_OFFSET_G = 0x0007FFFFL, .DWB_OGAM_RAMA_OFFSET_R = 0x0007FFFFL, .DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .DWB_OGAM_RAMB_EXP_REGION_START_G = 0x0003FFFFL , .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .DWB_OGAM_RAMB_EXP_REGION_START_R = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L , .DWB_OGAM_RAMB_EXP_REGION_START_BASE_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_G = 0x0003FFFFL , .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_BASE_R = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R = 0x0003FFFFL , .DWB_OGAM_RAMB_EXP_REGION_END_BASE_B = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B = 0xFFFF0000L , .DWB_OGAM_RAMB_EXP_REGION_END_BASE_G = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_G = 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G = 0xFFFF0000L , .DWB_OGAM_RAMB_EXP_REGION_END_BASE_R = 0x0003FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_R = 0x0000FFFFL, .DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R = 0xFFFF0000L , .DWB_OGAM_RAMB_OFFSET_B = 0x0007FFFFL, .DWB_OGAM_RAMB_OFFSET_G = 0x0007FFFFL, .DWB_OGAM_RAMB_OFFSET_R = 0x0007FFFFL, .DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x70000000L , .DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L , .DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L , .DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL , .DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x70000000L | ||||
| 548 | }; | ||||
| 549 | |||||
| 550 | #define mcif_wb_regs_dcn3(id)[id] = { .MCIF_WB_BUFMGR_SW_CONTROL = 0x000034C0 + 0x0272, .MCIF_WB_BUFMGR_STATUS = 0x000034C0 + 0x0274, .MCIF_WB_BUF_PITCH = 0x000034C0 + 0x0275 , .MCIF_WB_BUF_1_STATUS = 0x000034C0 + 0x0276, .MCIF_WB_BUF_1_STATUS2 = 0x000034C0 + 0x0277, .MCIF_WB_BUF_2_STATUS = 0x000034C0 + 0x0278 , .MCIF_WB_BUF_2_STATUS2 = 0x000034C0 + 0x0279, .MCIF_WB_BUF_3_STATUS = 0x000034C0 + 0x027a, .MCIF_WB_BUF_3_STATUS2 = 0x000034C0 + 0x027b, .MCIF_WB_BUF_4_STATUS = 0x000034C0 + 0x027c, .MCIF_WB_BUF_4_STATUS2 = 0x000034C0 + 0x027d, .MCIF_WB_ARBITRATION_CONTROL = 0x000034C0 + 0x027e, .MCIF_WB_SCLK_CHANGE = 0x000034C0 + 0x027f, .MCIF_WB_BUF_1_ADDR_Y = 0x000034C0 + 0x0282, .MCIF_WB_BUF_1_ADDR_C = 0x000034C0 + 0x0284 , .MCIF_WB_BUF_2_ADDR_Y = 0x000034C0 + 0x0286, .MCIF_WB_BUF_2_ADDR_C = 0x000034C0 + 0x0288, .MCIF_WB_BUF_3_ADDR_Y = 0x000034C0 + 0x028a , .MCIF_WB_BUF_3_ADDR_C = 0x000034C0 + 0x028c, .MCIF_WB_BUF_4_ADDR_Y = 0x000034C0 + 0x028e, .MCIF_WB_BUF_4_ADDR_C = 0x000034C0 + 0x0290 , .MCIF_WB_BUFMGR_VCE_CONTROL = 0x000034C0 + 0x0292, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = 0x000034C0 + 0x02aa, .MCIF_WB_NB_PSTATE_CONTROL = 0x000034C0 + 0x0293, .MCIF_WB_WATERMARK = 0x000034C0 + 0x02ab, .MCIF_WB_CLOCK_GATER_CONTROL = 0x000034C0 + 0x0294, .MCIF_WB_SELF_REFRESH_CONTROL = 0x000034C0 + 0x0296, .MULTI_LEVEL_QOS_CTRL = 0x000034C0 + 0x0297, .MCIF_WB_BUF_LUMA_SIZE = 0x000034C0 + 0x0299, .MCIF_WB_BUF_CHROMA_SIZE = 0x000034C0 + 0x029a, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000034C0 + 0x029b, . MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000034C0 + 0x029c, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x000034C0 + 0x029d, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000034C0 + 0x029e, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000034C0 + 0x029f, . MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000034C0 + 0x02a0, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x000034C0 + 0x02a1, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000034C0 + 0x02a2, .MCIF_WB_BUF_1_RESOLUTION = 0x000034C0 + 0x02a3, . MCIF_WB_BUF_2_RESOLUTION = 0x000034C0 + 0x02a4, .MCIF_WB_BUF_3_RESOLUTION = 0x000034C0 + 0x02a5, .MCIF_WB_BUF_4_RESOLUTION = 0x000034C0 + 0x02a6, .MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x0340, .MMHUBBUB_WARMUP_ADDR_REGION = 0x000034C0 + 0x02b0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x000034C0 + 0x02af, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0x000034C0 + 0x02ae , .MMHUBBUB_WARMUP_CONTROL_STATUS = 0x000034C0 + 0x02ad, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI = 0x000034C0 + 0x02a7,}\ | ||||
| 551 | [id] = {\ | ||||
| 552 | MCIF_WB_COMMON_REG_LIST_DCN30(id).MCIF_WB_BUFMGR_SW_CONTROL = 0x000034C0 + 0x0272, .MCIF_WB_BUFMGR_STATUS = 0x000034C0 + 0x0274, .MCIF_WB_BUF_PITCH = 0x000034C0 + 0x0275 , .MCIF_WB_BUF_1_STATUS = 0x000034C0 + 0x0276, .MCIF_WB_BUF_1_STATUS2 = 0x000034C0 + 0x0277, .MCIF_WB_BUF_2_STATUS = 0x000034C0 + 0x0278 , .MCIF_WB_BUF_2_STATUS2 = 0x000034C0 + 0x0279, .MCIF_WB_BUF_3_STATUS = 0x000034C0 + 0x027a, .MCIF_WB_BUF_3_STATUS2 = 0x000034C0 + 0x027b, .MCIF_WB_BUF_4_STATUS = 0x000034C0 + 0x027c, .MCIF_WB_BUF_4_STATUS2 = 0x000034C0 + 0x027d, .MCIF_WB_ARBITRATION_CONTROL = 0x000034C0 + 0x027e, .MCIF_WB_SCLK_CHANGE = 0x000034C0 + 0x027f, .MCIF_WB_BUF_1_ADDR_Y = 0x000034C0 + 0x0282, .MCIF_WB_BUF_1_ADDR_C = 0x000034C0 + 0x0284 , .MCIF_WB_BUF_2_ADDR_Y = 0x000034C0 + 0x0286, .MCIF_WB_BUF_2_ADDR_C = 0x000034C0 + 0x0288, .MCIF_WB_BUF_3_ADDR_Y = 0x000034C0 + 0x028a , .MCIF_WB_BUF_3_ADDR_C = 0x000034C0 + 0x028c, .MCIF_WB_BUF_4_ADDR_Y = 0x000034C0 + 0x028e, .MCIF_WB_BUF_4_ADDR_C = 0x000034C0 + 0x0290 , .MCIF_WB_BUFMGR_VCE_CONTROL = 0x000034C0 + 0x0292, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = 0x000034C0 + 0x02aa, .MCIF_WB_NB_PSTATE_CONTROL = 0x000034C0 + 0x0293, .MCIF_WB_WATERMARK = 0x000034C0 + 0x02ab, .MCIF_WB_CLOCK_GATER_CONTROL = 0x000034C0 + 0x0294, .MCIF_WB_SELF_REFRESH_CONTROL = 0x000034C0 + 0x0296, .MULTI_LEVEL_QOS_CTRL = 0x000034C0 + 0x0297, .MCIF_WB_BUF_LUMA_SIZE = 0x000034C0 + 0x0299, .MCIF_WB_BUF_CHROMA_SIZE = 0x000034C0 + 0x029a, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000034C0 + 0x029b, . MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000034C0 + 0x029c, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x000034C0 + 0x029d, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000034C0 + 0x029e, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000034C0 + 0x029f, . MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000034C0 + 0x02a0, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x000034C0 + 0x02a1, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000034C0 + 0x02a2, .MCIF_WB_BUF_1_RESOLUTION = 0x000034C0 + 0x02a3, . MCIF_WB_BUF_2_RESOLUTION = 0x000034C0 + 0x02a4, .MCIF_WB_BUF_3_RESOLUTION = 0x000034C0 + 0x02a5, .MCIF_WB_BUF_4_RESOLUTION = 0x000034C0 + 0x02a6, .MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x0340, .MMHUBBUB_WARMUP_ADDR_REGION = 0x000034C0 + 0x02b0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x000034C0 + 0x02af, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0x000034C0 + 0x02ae , .MMHUBBUB_WARMUP_CONTROL_STATUS = 0x000034C0 + 0x02ad, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI = 0x000034C0 + 0x02a7,\ | ||||
| 553 | } | ||||
| 554 | |||||
| 555 | static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { | ||||
| 556 | mcif_wb_regs_dcn3(0)[0] = { .MCIF_WB_BUFMGR_SW_CONTROL = 0x000034C0 + 0x0272, .MCIF_WB_BUFMGR_STATUS = 0x000034C0 + 0x0274, .MCIF_WB_BUF_PITCH = 0x000034C0 + 0x0275 , .MCIF_WB_BUF_1_STATUS = 0x000034C0 + 0x0276, .MCIF_WB_BUF_1_STATUS2 = 0x000034C0 + 0x0277, .MCIF_WB_BUF_2_STATUS = 0x000034C0 + 0x0278 , .MCIF_WB_BUF_2_STATUS2 = 0x000034C0 + 0x0279, .MCIF_WB_BUF_3_STATUS = 0x000034C0 + 0x027a, .MCIF_WB_BUF_3_STATUS2 = 0x000034C0 + 0x027b, .MCIF_WB_BUF_4_STATUS = 0x000034C0 + 0x027c, .MCIF_WB_BUF_4_STATUS2 = 0x000034C0 + 0x027d, .MCIF_WB_ARBITRATION_CONTROL = 0x000034C0 + 0x027e, .MCIF_WB_SCLK_CHANGE = 0x000034C0 + 0x027f, .MCIF_WB_BUF_1_ADDR_Y = 0x000034C0 + 0x0282, .MCIF_WB_BUF_1_ADDR_C = 0x000034C0 + 0x0284 , .MCIF_WB_BUF_2_ADDR_Y = 0x000034C0 + 0x0286, .MCIF_WB_BUF_2_ADDR_C = 0x000034C0 + 0x0288, .MCIF_WB_BUF_3_ADDR_Y = 0x000034C0 + 0x028a , .MCIF_WB_BUF_3_ADDR_C = 0x000034C0 + 0x028c, .MCIF_WB_BUF_4_ADDR_Y = 0x000034C0 + 0x028e, .MCIF_WB_BUF_4_ADDR_C = 0x000034C0 + 0x0290 , .MCIF_WB_BUFMGR_VCE_CONTROL = 0x000034C0 + 0x0292, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = 0x000034C0 + 0x02aa, .MCIF_WB_NB_PSTATE_CONTROL = 0x000034C0 + 0x0293, .MCIF_WB_WATERMARK = 0x000034C0 + 0x02ab, .MCIF_WB_CLOCK_GATER_CONTROL = 0x000034C0 + 0x0294, .MCIF_WB_SELF_REFRESH_CONTROL = 0x000034C0 + 0x0296, .MULTI_LEVEL_QOS_CTRL = 0x000034C0 + 0x0297, .MCIF_WB_BUF_LUMA_SIZE = 0x000034C0 + 0x0299, .MCIF_WB_BUF_CHROMA_SIZE = 0x000034C0 + 0x029a, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000034C0 + 0x029b, . MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000034C0 + 0x029c, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x000034C0 + 0x029d, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000034C0 + 0x029e, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000034C0 + 0x029f, . MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000034C0 + 0x02a0, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x000034C0 + 0x02a1, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000034C0 + 0x02a2, .MCIF_WB_BUF_1_RESOLUTION = 0x000034C0 + 0x02a3, . MCIF_WB_BUF_2_RESOLUTION = 0x000034C0 + 0x02a4, .MCIF_WB_BUF_3_RESOLUTION = 0x000034C0 + 0x02a5, .MCIF_WB_BUF_4_RESOLUTION = 0x000034C0 + 0x02a6, .MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x0340, .MMHUBBUB_WARMUP_ADDR_REGION = 0x000034C0 + 0x02b0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x000034C0 + 0x02af, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0x000034C0 + 0x02ae , .MMHUBBUB_WARMUP_CONTROL_STATUS = 0x000034C0 + 0x02ad, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI = 0x000034C0 + 0x02a7,} | ||||
| 557 | }; | ||||
| 558 | |||||
| 559 | static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { | ||||
| 560 | MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT).MCIF_WB_BUFMGR_ENABLE = 0x0, .MCIF_WB_BUFMGR_SW_INT_EN = 0x4 , .MCIF_WB_BUFMGR_SW_INT_ACK = 0x5, .MCIF_WB_BUFMGR_SW_SLICE_INT_EN = 0x6, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN = 0x7, .MCIF_WB_BUFMGR_SW_LOCK = 0x8, .MCIF_WB_BUF_ADDR_FENCE_EN = 0x18, .MCIF_WB_BUFMGR_VCE_INT_STATUS = 0x0, .MCIF_WB_BUFMGR_SW_INT_STATUS = 0x1, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS = 0x2, .MCIF_WB_BUFMGR_CUR_BUF = 0x4, .MCIF_WB_BUFMGR_BUFTAG = 0x8, .MCIF_WB_BUFMGR_CUR_LINE_L = 0xc, .MCIF_WB_BUFMGR_NEXT_BUF = 0x1c, .MCIF_WB_BUF_LUMA_PITCH = 0x8, .MCIF_WB_BUF_CHROMA_PITCH = 0x18, .MCIF_WB_BUF_1_ACTIVE = 0x0, .MCIF_WB_BUF_1_SW_LOCKED = 0x1, .MCIF_WB_BUF_1_VCE_LOCKED = 0x2, .MCIF_WB_BUF_1_OVERFLOW = 0x3, .MCIF_WB_BUF_1_DISABLE = 0x4, .MCIF_WB_BUF_1_MODE = 0x5 , .MCIF_WB_BUF_1_BUFTAG = 0x8, .MCIF_WB_BUF_1_NXT_BUF = 0xc, . MCIF_WB_BUF_1_CUR_LINE_L = 0x10, .MCIF_WB_BUF_1_NEW_CONTENT = 0xd, .MCIF_WB_BUF_1_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_1_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_1_TMZ = 0x10, .MCIF_WB_BUF_1_Y_OVERRUN = 0x11, .MCIF_WB_BUF_1_C_OVERRUN = 0x12, .MCIF_WB_BUF_2_ACTIVE = 0x0, .MCIF_WB_BUF_2_SW_LOCKED = 0x1, .MCIF_WB_BUF_2_VCE_LOCKED = 0x2, .MCIF_WB_BUF_2_OVERFLOW = 0x3, .MCIF_WB_BUF_2_DISABLE = 0x4, .MCIF_WB_BUF_2_MODE = 0x5, .MCIF_WB_BUF_2_BUFTAG = 0x8 , .MCIF_WB_BUF_2_NXT_BUF = 0xc, .MCIF_WB_BUF_2_CUR_LINE_L = 0x10 , .MCIF_WB_BUF_2_NEW_CONTENT = 0xd, .MCIF_WB_BUF_2_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_2_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_2_TMZ = 0x10, .MCIF_WB_BUF_2_Y_OVERRUN = 0x11, .MCIF_WB_BUF_2_C_OVERRUN = 0x12, .MCIF_WB_BUF_3_ACTIVE = 0x0, .MCIF_WB_BUF_3_SW_LOCKED = 0x1, .MCIF_WB_BUF_3_VCE_LOCKED = 0x2, .MCIF_WB_BUF_3_OVERFLOW = 0x3, .MCIF_WB_BUF_3_DISABLE = 0x4, .MCIF_WB_BUF_3_MODE = 0x5 , .MCIF_WB_BUF_3_BUFTAG = 0x8, .MCIF_WB_BUF_3_NXT_BUF = 0xc, . MCIF_WB_BUF_3_CUR_LINE_L = 0x10, .MCIF_WB_BUF_3_NEW_CONTENT = 0xd, .MCIF_WB_BUF_3_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_3_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_3_TMZ = 0x10, .MCIF_WB_BUF_3_Y_OVERRUN = 0x11, .MCIF_WB_BUF_3_C_OVERRUN = 0x12, .MCIF_WB_BUF_4_ACTIVE = 0x0, .MCIF_WB_BUF_4_SW_LOCKED = 0x1, .MCIF_WB_BUF_4_VCE_LOCKED = 0x2, .MCIF_WB_BUF_4_OVERFLOW = 0x3, .MCIF_WB_BUF_4_DISABLE = 0x4, .MCIF_WB_BUF_4_MODE = 0x5, .MCIF_WB_BUF_4_BUFTAG = 0x8 , .MCIF_WB_BUF_4_NXT_BUF = 0xc, .MCIF_WB_BUF_4_CUR_LINE_L = 0x10 , .MCIF_WB_BUF_4_NEW_CONTENT = 0xd, .MCIF_WB_BUF_4_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_4_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_4_TMZ = 0x10, .MCIF_WB_BUF_4_Y_OVERRUN = 0x11, .MCIF_WB_BUF_4_C_OVERRUN = 0x12, .MCIF_WB_CLIENT_ARBITRATION_SLICE = 0x0, .MCIF_WB_TIME_PER_PIXEL = 0x14, .WM_CHANGE_ACK_FORCE_ON = 0x0, .MCIF_WB_BUF_1_ADDR_Y = 0x0, .MCIF_WB_BUF_1_ADDR_C = 0x0, .MCIF_WB_BUF_2_ADDR_Y = 0x0 , .MCIF_WB_BUF_2_ADDR_C = 0x0, .MCIF_WB_BUF_3_ADDR_Y = 0x0, . MCIF_WB_BUF_3_ADDR_C = 0x0, .MCIF_WB_BUF_4_ADDR_Y = 0x0, .MCIF_WB_BUF_4_ADDR_C = 0x0, .MCIF_WB_BUFMGR_VCE_SLICE_INT_EN = 0x6, .MCIF_WB_BUFMGR_SLICE_SIZE = 0x10, .NB_PSTATE_CHANGE_REFRESH_WATERMARK = 0x0, .NB_PSTATE_CHANGE_WATERMARK_MASK = 0x18, .NB_PSTATE_CHANGE_URGENT_DURING_REQUEST = 0x0, .NB_PSTATE_CHANGE_FORCE_ON = 0x1, .NB_PSTATE_ALLOW_FOR_URGENT = 0x2, .MCIF_WB_CLI_WATERMARK = 0x0, .MCIF_WB_CLI_WATERMARK_MASK = 0x18, .MCIF_WB_CLI_CLOCK_GATER_OVERRIDE = 0x0, .DIS_REFRESH_UNDER_NBPREQ = 0x0, .PERFRAME_SELF_REFRESH = 0x1, .MAX_SCALED_TIME_TO_URGENT = 0x0, .MCIF_WB_BUF_LUMA_SIZE = 0x0, .MCIF_WB_BUF_CHROMA_SIZE = 0x0, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_1_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_1_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_2_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_2_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_3_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_3_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_4_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_4_RESOLUTION_HEIGHT = 0x10, .MMHUBBUB_WARMUP_ADDR_REGION = 0x0, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x0, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0x0, .MMHUBBUB_WARMUP_EN = 0x0, .MMHUBBUB_WARMUP_SW_INT_EN = 0x4, .MMHUBBUB_WARMUP_SW_INT_STATUS = 0x5, .MMHUBBUB_WARMUP_SW_INT_ACK = 0x6, .MMHUBBUB_WARMUP_INC_ADDR = 0x8, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI = 0x0 | ||||
| 561 | }; | ||||
| 562 | |||||
| 563 | static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { | ||||
| 564 | MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK).MCIF_WB_BUFMGR_ENABLE = 0x00000001L, .MCIF_WB_BUFMGR_SW_INT_EN = 0x00000010L, .MCIF_WB_BUFMGR_SW_INT_ACK = 0x00000020L, .MCIF_WB_BUFMGR_SW_SLICE_INT_EN = 0x00000040L, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN = 0x00000080L , .MCIF_WB_BUFMGR_SW_LOCK = 0x00000F00L, .MCIF_WB_BUF_ADDR_FENCE_EN = 0x01000000L, .MCIF_WB_BUFMGR_VCE_INT_STATUS = 0x00000001L, .MCIF_WB_BUFMGR_SW_INT_STATUS = 0x00000002L, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS = 0x00000004L, .MCIF_WB_BUFMGR_CUR_BUF = 0x00000070L, .MCIF_WB_BUFMGR_BUFTAG = 0x00000F00L, .MCIF_WB_BUFMGR_CUR_LINE_L = 0x01FFF000L, .MCIF_WB_BUFMGR_NEXT_BUF = 0x70000000L, .MCIF_WB_BUF_LUMA_PITCH = 0x0000FF00L, .MCIF_WB_BUF_CHROMA_PITCH = 0xFF000000L, .MCIF_WB_BUF_1_ACTIVE = 0x00000001L, .MCIF_WB_BUF_1_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_1_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_1_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_1_DISABLE = 0x00000010L, .MCIF_WB_BUF_1_MODE = 0x000000E0L, .MCIF_WB_BUF_1_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_1_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_1_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_1_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_1_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_1_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_1_TMZ = 0x00010000L, .MCIF_WB_BUF_1_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_1_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_2_ACTIVE = 0x00000001L, .MCIF_WB_BUF_2_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_2_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_2_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_2_DISABLE = 0x00000010L, .MCIF_WB_BUF_2_MODE = 0x000000E0L, .MCIF_WB_BUF_2_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_2_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_2_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_2_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_2_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_2_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_2_TMZ = 0x00010000L, .MCIF_WB_BUF_2_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_2_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_3_ACTIVE = 0x00000001L, .MCIF_WB_BUF_3_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_3_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_3_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_3_DISABLE = 0x00000010L, .MCIF_WB_BUF_3_MODE = 0x000000E0L, .MCIF_WB_BUF_3_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_3_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_3_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_3_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_3_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_3_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_3_TMZ = 0x00010000L, .MCIF_WB_BUF_3_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_3_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_4_ACTIVE = 0x00000001L, .MCIF_WB_BUF_4_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_4_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_4_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_4_DISABLE = 0x00000010L, .MCIF_WB_BUF_4_MODE = 0x000000E0L, .MCIF_WB_BUF_4_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_4_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_4_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_4_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_4_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_4_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_4_TMZ = 0x00010000L, .MCIF_WB_BUF_4_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_4_C_OVERRUN = 0x00040000L, .MCIF_WB_CLIENT_ARBITRATION_SLICE = 0x00000003L, .MCIF_WB_TIME_PER_PIXEL = 0xFFF00000L, .WM_CHANGE_ACK_FORCE_ON = 0x00000001L, .MCIF_WB_BUF_1_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_1_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_2_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_2_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_3_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_3_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_4_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_4_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUFMGR_VCE_SLICE_INT_EN = 0x00000040L , .MCIF_WB_BUFMGR_SLICE_SIZE = 0x1FFF0000L, .NB_PSTATE_CHANGE_REFRESH_WATERMARK = 0x001FFFFFL, .NB_PSTATE_CHANGE_WATERMARK_MASK = 0x07000000L , .NB_PSTATE_CHANGE_URGENT_DURING_REQUEST = 0x00000001L, .NB_PSTATE_CHANGE_FORCE_ON = 0x00000002L, .NB_PSTATE_ALLOW_FOR_URGENT = 0x00000004L, .MCIF_WB_CLI_WATERMARK = 0x001FFFFFL, .MCIF_WB_CLI_WATERMARK_MASK = 0x07000000L, .MCIF_WB_CLI_CLOCK_GATER_OVERRIDE = 0x00000001L, .DIS_REFRESH_UNDER_NBPREQ = 0x00000001L, .PERFRAME_SELF_REFRESH = 0x00000002L, .MAX_SCALED_TIME_TO_URGENT = 0x003FFFFFL, .MCIF_WB_BUF_LUMA_SIZE = 0x000FFFFFL, .MCIF_WB_BUF_CHROMA_SIZE = 0x000FFFFFL, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_1_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_1_RESOLUTION_HEIGHT = 0x1FFF0000L , .MCIF_WB_BUF_2_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_2_RESOLUTION_HEIGHT = 0x1FFF0000L, .MCIF_WB_BUF_3_RESOLUTION_WIDTH = 0x00001FFFL , .MCIF_WB_BUF_3_RESOLUTION_HEIGHT = 0x1FFF0000L, .MCIF_WB_BUF_4_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_4_RESOLUTION_HEIGHT = 0x1FFF0000L , .MMHUBBUB_WARMUP_ADDR_REGION = 0x07FFFFFFL, .MMHUBBUB_WARMUP_BASE_ADDR_HIGH = 0x000007FFL, .MMHUBBUB_WARMUP_BASE_ADDR_LOW = 0xFFFFFFFFL, .MMHUBBUB_WARMUP_EN = 0x00000001L, .MMHUBBUB_WARMUP_SW_INT_EN = 0x00000010L, .MMHUBBUB_WARMUP_SW_INT_STATUS = 0x00000020L, .MMHUBBUB_WARMUP_SW_INT_ACK = 0x00000040L, .MMHUBBUB_WARMUP_INC_ADDR = 0x03FFFF00L, .MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI = 0x0000FFFFL | ||||
| 565 | }; | ||||
| 566 | |||||
| 567 | #define dsc_regsDCN20(id)[id] = { .DSC_TOP_CONTROL = DCN_BASE__INST0_SEGregDSC_TOPid_DSC_TOP_CONTROL_BASE_IDX + regDSC_TOPid_DSC_TOP_CONTROL, .DSC_DEBUG_CONTROL = DCN_BASE__INST0_SEGregDSC_TOPid_DSC_DEBUG_CONTROL_BASE_IDX + regDSC_TOPid_DSC_DEBUG_CONTROL, .DSCC_CONFIG0 = DCN_BASE__INST0_SEGregDSCCid_DSCC_CONFIG0_BASE_IDX + regDSCCid_DSCC_CONFIG0, .DSCC_CONFIG1 = DCN_BASE__INST0_SEGregDSCCid_DSCC_CONFIG1_BASE_IDX + regDSCCid_DSCC_CONFIG1, .DSCC_STATUS = DCN_BASE__INST0_SEGregDSCCid_DSCC_STATUS_BASE_IDX + regDSCCid_DSCC_STATUS, .DSCC_INTERRUPT_CONTROL_STATUS = DCN_BASE__INST0_SEGregDSCCid_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX + regDSCCid_DSCC_INTERRUPT_CONTROL_STATUS, .DSCC_PPS_CONFIG0 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG0_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG0 , .DSCC_PPS_CONFIG1 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG1_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG1, .DSCC_PPS_CONFIG2 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG2_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG2, .DSCC_PPS_CONFIG3 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG3_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG3, .DSCC_PPS_CONFIG4 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG4_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG4, .DSCC_PPS_CONFIG5 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG5_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG5, .DSCC_PPS_CONFIG6 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG6_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG6, .DSCC_PPS_CONFIG7 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG7_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG7, .DSCC_PPS_CONFIG8 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG8_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG8, .DSCC_PPS_CONFIG9 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG9_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG9, .DSCC_PPS_CONFIG10 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG10_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG10, .DSCC_PPS_CONFIG11 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG11_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG11, .DSCC_PPS_CONFIG12 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG12_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG12, .DSCC_PPS_CONFIG13 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG13_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG13, .DSCC_PPS_CONFIG14 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG14_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG14, .DSCC_PPS_CONFIG15 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG15_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG15, .DSCC_PPS_CONFIG16 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG16_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG16, .DSCC_PPS_CONFIG17 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG17_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG17, .DSCC_PPS_CONFIG18 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG18_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG18, .DSCC_PPS_CONFIG19 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG19_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG19, .DSCC_PPS_CONFIG20 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG20_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG20, .DSCC_PPS_CONFIG21 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG21_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG21, .DSCC_PPS_CONFIG22 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG22_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG22, .DSCC_MEM_POWER_CONTROL = DCN_BASE__INST0_SEGregDSCCid_DSCC_MEM_POWER_CONTROL_BASE_IDX + regDSCCid_DSCC_MEM_POWER_CONTROL, .DSCC_R_Y_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGregDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX + regDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER, .DSCC_R_Y_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGregDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX + regDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER, .DSCC_G_CB_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGregDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX + regDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER, .DSCC_G_CB_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGregDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX + regDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER, .DSCC_B_CR_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGregDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX + regDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER, .DSCC_B_CR_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGregDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX + regDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER, .DSCC_MAX_ABS_ERROR0 = DCN_BASE__INST0_SEGregDSCCid_DSCC_MAX_ABS_ERROR0_BASE_IDX + regDSCCid_DSCC_MAX_ABS_ERROR0, .DSCC_MAX_ABS_ERROR1 = DCN_BASE__INST0_SEGregDSCCid_DSCC_MAX_ABS_ERROR1_BASE_IDX + regDSCCid_DSCC_MAX_ABS_ERROR1, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, .DSCCIF_CONFIG0 = DCN_BASE__INST0_SEGregDSCCIFid_DSCCIF_CONFIG0_BASE_IDX + regDSCCIFid_DSCCIF_CONFIG0 , .DSCCIF_CONFIG1 = DCN_BASE__INST0_SEGregDSCCIFid_DSCCIF_CONFIG1_BASE_IDX + regDSCCIFid_DSCCIF_CONFIG1, .DSCRM_DSC_FORWARD_CONFIG = DCN_BASE__INST0_SEGregDSCRMid_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX + regDSCRMid_DSCRM_DSC_FORWARD_CONFIG}\ | ||||
| 568 | [id] = {\ | ||||
| 569 | DSC_REG_LIST_DCN20(id).DSC_TOP_CONTROL = DCN_BASE__INST0_SEGregDSC_TOPid_DSC_TOP_CONTROL_BASE_IDX + regDSC_TOPid_DSC_TOP_CONTROL, .DSC_DEBUG_CONTROL = DCN_BASE__INST0_SEGregDSC_TOPid_DSC_DEBUG_CONTROL_BASE_IDX + regDSC_TOPid_DSC_DEBUG_CONTROL, .DSCC_CONFIG0 = DCN_BASE__INST0_SEGregDSCCid_DSCC_CONFIG0_BASE_IDX + regDSCCid_DSCC_CONFIG0, .DSCC_CONFIG1 = DCN_BASE__INST0_SEGregDSCCid_DSCC_CONFIG1_BASE_IDX + regDSCCid_DSCC_CONFIG1, .DSCC_STATUS = DCN_BASE__INST0_SEGregDSCCid_DSCC_STATUS_BASE_IDX + regDSCCid_DSCC_STATUS, .DSCC_INTERRUPT_CONTROL_STATUS = DCN_BASE__INST0_SEGregDSCCid_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX + regDSCCid_DSCC_INTERRUPT_CONTROL_STATUS, .DSCC_PPS_CONFIG0 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG0_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG0 , .DSCC_PPS_CONFIG1 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG1_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG1, .DSCC_PPS_CONFIG2 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG2_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG2, .DSCC_PPS_CONFIG3 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG3_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG3, .DSCC_PPS_CONFIG4 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG4_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG4, .DSCC_PPS_CONFIG5 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG5_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG5, .DSCC_PPS_CONFIG6 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG6_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG6, .DSCC_PPS_CONFIG7 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG7_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG7, .DSCC_PPS_CONFIG8 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG8_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG8, .DSCC_PPS_CONFIG9 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG9_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG9, .DSCC_PPS_CONFIG10 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG10_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG10, .DSCC_PPS_CONFIG11 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG11_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG11, .DSCC_PPS_CONFIG12 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG12_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG12, .DSCC_PPS_CONFIG13 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG13_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG13, .DSCC_PPS_CONFIG14 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG14_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG14, .DSCC_PPS_CONFIG15 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG15_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG15, .DSCC_PPS_CONFIG16 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG16_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG16, .DSCC_PPS_CONFIG17 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG17_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG17, .DSCC_PPS_CONFIG18 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG18_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG18, .DSCC_PPS_CONFIG19 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG19_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG19, .DSCC_PPS_CONFIG20 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG20_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG20, .DSCC_PPS_CONFIG21 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG21_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG21, .DSCC_PPS_CONFIG22 = DCN_BASE__INST0_SEGregDSCCid_DSCC_PPS_CONFIG22_BASE_IDX + regDSCCid_DSCC_PPS_CONFIG22, .DSCC_MEM_POWER_CONTROL = DCN_BASE__INST0_SEGregDSCCid_DSCC_MEM_POWER_CONTROL_BASE_IDX + regDSCCid_DSCC_MEM_POWER_CONTROL, .DSCC_R_Y_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGregDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX + regDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER, .DSCC_R_Y_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGregDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX + regDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER, .DSCC_G_CB_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGregDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX + regDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER, .DSCC_G_CB_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGregDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX + regDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER, .DSCC_B_CR_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGregDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX + regDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER, .DSCC_B_CR_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGregDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX + regDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER, .DSCC_MAX_ABS_ERROR0 = DCN_BASE__INST0_SEGregDSCCid_DSCC_MAX_ABS_ERROR0_BASE_IDX + regDSCCid_DSCC_MAX_ABS_ERROR0, .DSCC_MAX_ABS_ERROR1 = DCN_BASE__INST0_SEGregDSCCid_DSCC_MAX_ABS_ERROR1_BASE_IDX + regDSCCid_DSCC_MAX_ABS_ERROR1, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGregDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX + regDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, .DSCCIF_CONFIG0 = DCN_BASE__INST0_SEGregDSCCIFid_DSCCIF_CONFIG0_BASE_IDX + regDSCCIFid_DSCCIF_CONFIG0 , .DSCCIF_CONFIG1 = DCN_BASE__INST0_SEGregDSCCIFid_DSCCIF_CONFIG1_BASE_IDX + regDSCCIFid_DSCCIF_CONFIG1, .DSCRM_DSC_FORWARD_CONFIG = DCN_BASE__INST0_SEGregDSCRMid_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX + regDSCRMid_DSCRM_DSC_FORWARD_CONFIG\ | ||||
| 570 | } | ||||
| 571 | |||||
| 572 | static const struct dcn20_dsc_registers dsc_regs[] = { | ||||
| 573 | dsc_regsDCN20(0)[0] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x3000, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x3001, .DSCC_CONFIG0 = 0x000034C0 + 0x300a, . DSCC_CONFIG1 = 0x000034C0 + 0x300b, .DSCC_STATUS = 0x000034C0 + 0x300c, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x300d , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x300e, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x300f, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x3010 , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x3011, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x3012, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x3013 , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3014, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x3015, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x3016 , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x3017, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x3018, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x3019 , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x301a, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x301b, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x301c , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x301d, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x301e, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x301f , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x3020, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x3021, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x3022 , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x3023, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x3024, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x3025, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3026, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3027, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3028, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3029, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x302a , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x302b, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x302c, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x302d , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x302e , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x302f , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3030 , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3031 , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3032, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3033, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3034, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3035, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3005, .DSCCIF_CONFIG1 = 0x000034C0 + 0x3006, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a64}, | ||||
| 574 | dsc_regsDCN20(1)[1] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x305c, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x305d, .DSCC_CONFIG0 = 0x000034C0 + 0x3066, . DSCC_CONFIG1 = 0x000034C0 + 0x3067, .DSCC_STATUS = 0x000034C0 + 0x3068, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x3069 , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x306a, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x306b, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x306c , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x306d, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x306e, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x306f , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3070, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x3071, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x3072 , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x3073, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x3074, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x3075 , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x3076, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x3077, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x3078 , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x3079, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x307a, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x307b , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x307c, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x307d, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x307e , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x307f, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x3080, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x3081, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3082, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3083, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3084, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3085, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3086 , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3087, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x3088, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x3089 , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308a , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308b , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308c , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308d , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308e, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308f, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3090, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3091, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3061, .DSCCIF_CONFIG1 = 0x000034C0 + 0x3062, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a65}, | ||||
| 575 | dsc_regsDCN20(2)[2] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x30b8, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x30b9, .DSCC_CONFIG0 = 0x000034C0 + 0x30c2, . DSCC_CONFIG1 = 0x000034C0 + 0x30c3, .DSCC_STATUS = 0x000034C0 + 0x30c4, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x30c5 , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x30c6, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x30c7, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x30c8 , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x30c9, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x30ca, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x30cb , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x30cc, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x30cd, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x30ce , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x30cf, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x30d0, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x30d1 , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x30d2, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x30d3, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x30d4 , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x30d5, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x30d6, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x30d7 , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x30d8, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x30d9, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x30da , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x30db, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x30dc, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x30dd, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x30de, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x30df, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x30e0, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x30e1, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x30e2 , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x30e3, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x30e4, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x30e5 , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e6 , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e7 , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e8 , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e9 , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30ea, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30eb, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30ec, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30ed, .DSCCIF_CONFIG0 = 0x000034C0 + 0x30bd, .DSCCIF_CONFIG1 = 0x000034C0 + 0x30be, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a66} | ||||
| 576 | }; | ||||
| 577 | |||||
| 578 | static const struct dcn20_dsc_shift dsc_shift = { | ||||
| 579 | DSC_REG_LIST_SH_MASK_DCN20(__SHIFT).DSC_CLOCK_EN = 0x0, .DSC_DISPCLK_R_GATE_DIS = 0x4, .DSC_DSCCLK_R_GATE_DIS = 0x8, .DSC_DBG_EN = 0x0, .ICH_RESET_AT_END_OF_LINE = 0x0, . NUMBER_OF_SLICES_PER_LINE = 0x4, .ALTERNATE_ICH_ENCODING_EN = 0x8, .NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION = 0x10, .DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE = 0x0, .DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x0, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED = 0x0, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED = 0x1, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED = 0x2, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED = 0x3, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED = 0x4, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED = 0x5, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED = 0x6, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED = 0x7, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED = 0x8, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED = 0x9 , .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED = 0xa, . DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED = 0xb, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN = 0x10, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN = 0x11, . DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN = 0x12, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN = 0x13, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN = 0x14, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN = 0x15, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN = 0x16, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN = 0x17, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN = 0x18 , .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN = 0x19, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN = 0x1a, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN = 0x1b, .DSC_VERSION_MINOR = 0x0, .DSC_VERSION_MAJOR = 0x4, . PPS_IDENTIFIER = 0x8, .LINEBUF_DEPTH = 0x18, .DSCC_PPS_CONFIG0__BITS_PER_COMPONENT = 0x1c, .BITS_PER_PIXEL = 0x0, .VBR_ENABLE = 0xa, .SIMPLE_422 = 0xb, .CONVERT_RGB = 0xc, .BLOCK_PRED_ENABLE = 0xd, .NATIVE_422 = 0xe, .NATIVE_420 = 0xf, .CHUNK_SIZE = 0x10, .PIC_WIDTH = 0x0 , .PIC_HEIGHT = 0x10, .SLICE_WIDTH = 0x0, .SLICE_HEIGHT = 0x10 , .INITIAL_XMIT_DELAY = 0x0, .INITIAL_DEC_DELAY = 0x10, .INITIAL_SCALE_VALUE = 0x0, .SCALE_INCREMENT_INTERVAL = 0x10, .SCALE_DECREMENT_INTERVAL = 0x0, .FIRST_LINE_BPG_OFFSET = 0x10, .SECOND_LINE_BPG_OFFSET = 0x18, .NFL_BPG_OFFSET = 0x0, .SLICE_BPG_OFFSET = 0x10, .NSL_BPG_OFFSET = 0x0, .SECOND_LINE_OFFSET_ADJ = 0x10, .INITIAL_OFFSET = 0x0 , .FINAL_OFFSET = 0x10, .FLATNESS_MIN_QP = 0x0, .FLATNESS_MAX_QP = 0x8, .RC_MODEL_SIZE = 0x10, .RC_EDGE_FACTOR = 0x0, .RC_QUANT_INCR_LIMIT0 = 0x8, .RC_QUANT_INCR_LIMIT1 = 0x10, .RC_TGT_OFFSET_LO = 0x18 , .RC_TGT_OFFSET_HI = 0x1c, .RC_BUF_THRESH0 = 0x0, .RC_BUF_THRESH1 = 0x8, .RC_BUF_THRESH2 = 0x10, .RC_BUF_THRESH3 = 0x18, .RC_BUF_THRESH4 = 0x0, .RC_BUF_THRESH5 = 0x8, .RC_BUF_THRESH6 = 0x10, .RC_BUF_THRESH7 = 0x18, .RC_BUF_THRESH8 = 0x0, .RC_BUF_THRESH9 = 0x8, .RC_BUF_THRESH10 = 0x10, .RC_BUF_THRESH11 = 0x18, .RC_BUF_THRESH12 = 0x0, .RC_BUF_THRESH13 = 0x8, .RANGE_MIN_QP0 = 0x10, .RANGE_MAX_QP0 = 0x15, .RANGE_BPG_OFFSET0 = 0x1a, .RANGE_MIN_QP1 = 0x0, .RANGE_MAX_QP1 = 0x5, .RANGE_BPG_OFFSET1 = 0xa, .RANGE_MIN_QP2 = 0x10, .RANGE_MAX_QP2 = 0x15, .RANGE_BPG_OFFSET2 = 0x1a, .RANGE_MIN_QP3 = 0x0, .RANGE_MAX_QP3 = 0x5, .RANGE_BPG_OFFSET3 = 0xa, .RANGE_MIN_QP4 = 0x10, .RANGE_MAX_QP4 = 0x15, .RANGE_BPG_OFFSET4 = 0x1a, .RANGE_MIN_QP5 = 0x0, .RANGE_MAX_QP5 = 0x5, .RANGE_BPG_OFFSET5 = 0xa, .RANGE_MIN_QP6 = 0x10, .RANGE_MAX_QP6 = 0x15, .RANGE_BPG_OFFSET6 = 0x1a, .RANGE_MIN_QP7 = 0x0, .RANGE_MAX_QP7 = 0x5, .RANGE_BPG_OFFSET7 = 0xa, .RANGE_MIN_QP8 = 0x10, .RANGE_MAX_QP8 = 0x15, .RANGE_BPG_OFFSET8 = 0x1a, .RANGE_MIN_QP9 = 0x0, .RANGE_MAX_QP9 = 0x5, .RANGE_BPG_OFFSET9 = 0xa, .RANGE_MIN_QP10 = 0x10, .RANGE_MAX_QP10 = 0x15, .RANGE_BPG_OFFSET10 = 0x1a, .RANGE_MIN_QP11 = 0x0, .RANGE_MAX_QP11 = 0x5, .RANGE_BPG_OFFSET11 = 0xa, .RANGE_MIN_QP12 = 0x10, .RANGE_MAX_QP12 = 0x15, .RANGE_BPG_OFFSET12 = 0x1a, .RANGE_MIN_QP13 = 0x0, .RANGE_MAX_QP13 = 0x5, .RANGE_BPG_OFFSET13 = 0xa, .RANGE_MIN_QP14 = 0x10, .RANGE_MAX_QP14 = 0x15, .RANGE_BPG_OFFSET14 = 0x1a, .DSCC_DEFAULT_MEM_LOW_POWER_STATE = 0x0, .DSCC_MEM_PWR_FORCE = 0x4, .DSCC_MEM_PWR_DIS = 0x8, .DSCC_MEM_PWR_STATE = 0x10, . DSCC_NATIVE_422_MEM_PWR_FORCE = 0x14, .DSCC_NATIVE_422_MEM_PWR_DIS = 0x18, .DSCC_NATIVE_422_MEM_PWR_STATE = 0x1c, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x0, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x0, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x0, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x0, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x0, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x0, .DSCC_R_Y_MAX_ABS_ERROR = 0x0, .DSCC_G_CB_MAX_ABS_ERROR = 0x10, .DSCC_B_CR_MAX_ABS_ERROR = 0x0, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x0, . DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x0, . INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN = 0x0, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN = 0x4, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS = 0x8, .INPUT_PIXEL_FORMAT = 0xc, .DSCCIF_CONFIG0__BITS_PER_COMPONENT = 0x10, .DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x18, .PIC_WIDTH = 0x0, .PIC_HEIGHT = 0x10, .DSCRM_DSC_FORWARD_EN = 0x0, .DSCRM_DSC_OPP_PIPE_SOURCE = 0x4 | ||||
| 580 | }; | ||||
| 581 | |||||
| 582 | static const struct dcn20_dsc_mask dsc_mask = { | ||||
| 583 | DSC_REG_LIST_SH_MASK_DCN20(_MASK).DSC_CLOCK_EN = 0x00000001L, .DSC_DISPCLK_R_GATE_DIS = 0x00000010L , .DSC_DSCCLK_R_GATE_DIS = 0x00000100L, .DSC_DBG_EN = 0x00000001L , .ICH_RESET_AT_END_OF_LINE = 0x0000000FL, .NUMBER_OF_SLICES_PER_LINE = 0x00000030L, .ALTERNATE_ICH_ENCODING_EN = 0x00000100L, .NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION = 0xFFFF0000L, .DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE = 0x0003FFFFL , .DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x00000001L, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED = 0x00000001L, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED = 0x00000002L , .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED = 0x00000004L, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED = 0x00000008L, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED = 0x00000010L , .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED = 0x00000020L, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED = 0x00000040L, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED = 0x00000080L , .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED = 0x00000100L , .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED = 0x00000200L , .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED = 0x00000400L , .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED = 0x00000800L , .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN = 0x00010000L, . DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN = 0x00020000L, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN = 0x00040000L, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN = 0x00080000L, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN = 0x00100000L , .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN = 0x00200000L, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN = 0x00400000L, . DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN = 0x00800000L, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN = 0x01000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN = 0x02000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN = 0x04000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN = 0x08000000L, .DSC_VERSION_MINOR = 0x0000000FL, .DSC_VERSION_MAJOR = 0x000000F0L, .PPS_IDENTIFIER = 0x0000FF00L, .LINEBUF_DEPTH = 0x0F000000L, .DSCC_PPS_CONFIG0__BITS_PER_COMPONENT = 0xF0000000L , .BITS_PER_PIXEL = 0x000003FFL, .VBR_ENABLE = 0x00000400L, . SIMPLE_422 = 0x00000800L, .CONVERT_RGB = 0x00001000L, .BLOCK_PRED_ENABLE = 0x00002000L, .NATIVE_422 = 0x00004000L, .NATIVE_420 = 0x00008000L , .CHUNK_SIZE = 0xFFFF0000L, .PIC_WIDTH = 0x0000FFFFL, .PIC_HEIGHT = 0xFFFF0000L, .SLICE_WIDTH = 0x0000FFFFL, .SLICE_HEIGHT = 0xFFFF0000L , .INITIAL_XMIT_DELAY = 0x000003FFL, .INITIAL_DEC_DELAY = 0xFFFF0000L , .INITIAL_SCALE_VALUE = 0x0000003FL, .SCALE_INCREMENT_INTERVAL = 0xFFFF0000L, .SCALE_DECREMENT_INTERVAL = 0x00000FFFL, .FIRST_LINE_BPG_OFFSET = 0x001F0000L, .SECOND_LINE_BPG_OFFSET = 0x1F000000L, .NFL_BPG_OFFSET = 0x0000FFFFL, .SLICE_BPG_OFFSET = 0xFFFF0000L, .NSL_BPG_OFFSET = 0x0000FFFFL, .SECOND_LINE_OFFSET_ADJ = 0xFFFF0000L, .INITIAL_OFFSET = 0x0000FFFFL, .FINAL_OFFSET = 0xFFFF0000L, .FLATNESS_MIN_QP = 0x0000001FL, .FLATNESS_MAX_QP = 0x00001F00L, .RC_MODEL_SIZE = 0xFFFF0000L, .RC_EDGE_FACTOR = 0x0000000FL, .RC_QUANT_INCR_LIMIT0 = 0x00001F00L, .RC_QUANT_INCR_LIMIT1 = 0x001F0000L, .RC_TGT_OFFSET_LO = 0x0F000000L, .RC_TGT_OFFSET_HI = 0xF0000000L, .RC_BUF_THRESH0 = 0x000000FFL, .RC_BUF_THRESH1 = 0x0000FF00L, .RC_BUF_THRESH2 = 0x00FF0000L, .RC_BUF_THRESH3 = 0xFF000000L, .RC_BUF_THRESH4 = 0x000000FFL, .RC_BUF_THRESH5 = 0x0000FF00L, .RC_BUF_THRESH6 = 0x00FF0000L, .RC_BUF_THRESH7 = 0xFF000000L, .RC_BUF_THRESH8 = 0x000000FFL, .RC_BUF_THRESH9 = 0x0000FF00L, .RC_BUF_THRESH10 = 0x00FF0000L, .RC_BUF_THRESH11 = 0xFF000000L, .RC_BUF_THRESH12 = 0x000000FFL, .RC_BUF_THRESH13 = 0x0000FF00L, .RANGE_MIN_QP0 = 0x001F0000L, .RANGE_MAX_QP0 = 0x03E00000L, .RANGE_BPG_OFFSET0 = 0xFC000000L, .RANGE_MIN_QP1 = 0x0000001FL, .RANGE_MAX_QP1 = 0x000003E0L, .RANGE_BPG_OFFSET1 = 0x0000FC00L, .RANGE_MIN_QP2 = 0x001F0000L, .RANGE_MAX_QP2 = 0x03E00000L, .RANGE_BPG_OFFSET2 = 0xFC000000L, .RANGE_MIN_QP3 = 0x0000001FL, .RANGE_MAX_QP3 = 0x000003E0L, .RANGE_BPG_OFFSET3 = 0x0000FC00L, .RANGE_MIN_QP4 = 0x001F0000L, .RANGE_MAX_QP4 = 0x03E00000L, .RANGE_BPG_OFFSET4 = 0xFC000000L, .RANGE_MIN_QP5 = 0x0000001FL, .RANGE_MAX_QP5 = 0x000003E0L, .RANGE_BPG_OFFSET5 = 0x0000FC00L, .RANGE_MIN_QP6 = 0x001F0000L, .RANGE_MAX_QP6 = 0x03E00000L, .RANGE_BPG_OFFSET6 = 0xFC000000L, .RANGE_MIN_QP7 = 0x0000001FL, .RANGE_MAX_QP7 = 0x000003E0L, .RANGE_BPG_OFFSET7 = 0x0000FC00L, .RANGE_MIN_QP8 = 0x001F0000L, .RANGE_MAX_QP8 = 0x03E00000L, .RANGE_BPG_OFFSET8 = 0xFC000000L, .RANGE_MIN_QP9 = 0x0000001FL, .RANGE_MAX_QP9 = 0x000003E0L, .RANGE_BPG_OFFSET9 = 0x0000FC00L, .RANGE_MIN_QP10 = 0x001F0000L, .RANGE_MAX_QP10 = 0x03E00000L, .RANGE_BPG_OFFSET10 = 0xFC000000L, .RANGE_MIN_QP11 = 0x0000001FL, .RANGE_MAX_QP11 = 0x000003E0L, .RANGE_BPG_OFFSET11 = 0x0000FC00L, .RANGE_MIN_QP12 = 0x001F0000L, .RANGE_MAX_QP12 = 0x03E00000L, .RANGE_BPG_OFFSET12 = 0xFC000000L, .RANGE_MIN_QP13 = 0x0000001FL, .RANGE_MAX_QP13 = 0x000003E0L, .RANGE_BPG_OFFSET13 = 0x0000FC00L, .RANGE_MIN_QP14 = 0x001F0000L, .RANGE_MAX_QP14 = 0x03E00000L, .RANGE_BPG_OFFSET14 = 0xFC000000L, .DSCC_DEFAULT_MEM_LOW_POWER_STATE = 0x00000003L , .DSCC_MEM_PWR_FORCE = 0x00000030L, .DSCC_MEM_PWR_DIS = 0x00000100L , .DSCC_MEM_PWR_STATE = 0x00030000L, .DSCC_NATIVE_422_MEM_PWR_FORCE = 0x00300000L, .DSCC_NATIVE_422_MEM_PWR_DIS = 0x01000000L, . DSCC_NATIVE_422_MEM_PWR_STATE = 0x30000000L, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, . DSCC_G_CB_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, .DSCC_R_Y_MAX_ABS_ERROR = 0x0000FFFFL, .DSCC_G_CB_MAX_ABS_ERROR = 0xFFFF0000L, .DSCC_B_CR_MAX_ABS_ERROR = 0x0000FFFFL, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x0003FFFFL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x0003FFFFL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN = 0x00000001L, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN = 0x00000010L, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS = 0x00000100L , .INPUT_PIXEL_FORMAT = 0x00007000L, .DSCCIF_CONFIG0__BITS_PER_COMPONENT = 0x000F0000L, .DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x01000000L , .PIC_WIDTH = 0x0000FFFFL, .PIC_HEIGHT = 0xFFFF0000L, .DSCRM_DSC_FORWARD_EN = 0x00000001L, .DSCRM_DSC_OPP_PIPE_SOURCE = 0x00000070L | ||||
| 584 | }; | ||||
| 585 | |||||
| 586 | static const struct dcn30_mpc_registers mpc_regs = { | ||||
| 587 | MPC_REG_LIST_DCN3_0(0).MPCC_TOP_SEL[0] = 0x00009000 + 0x0000, .MPCC_BOT_SEL[0] = 0x00009000 + 0x0001, .MPCC_CONTROL[0] = 0x00009000 + 0x0003, .MPCC_STATUS [0] = 0x00009000 + 0x000d, .MPCC_OPP_ID[0] = 0x00009000 + 0x0002 , .MPCC_BG_G_Y[0] = 0x00009000 + 0x000a, .MPCC_BG_R_CR[0] = 0x00009000 + 0x0009, .MPCC_BG_B_CB[0] = 0x00009000 + 0x000b, .MPCC_SM_CONTROL [0] = 0x00009000 + 0x0004, .MPCC_UPDATE_LOCK_SEL[0] = 0x00009000 + 0x0005, .MPCC_TOP_GAIN[0] = 0x00009000 + 0x0006, .MPCC_BOT_GAIN_INSIDE [0] = 0x00009000 + 0x0007, .MPCC_BOT_GAIN_OUTSIDE[0] = 0x00009000 + 0x0008, .MPCC_MEM_PWR_CTRL[0] = 0x00009000 + 0x000c, .MPCC_OGAM_LUT_INDEX [0] = 0x00009000 + 0x0101, .MPCC_OGAM_LUT_DATA[0] = 0x00009000 + 0x0102, .MPCC_GAMUT_REMAP_COEF_FORMAT[0] = 0x00009000 + 0x014a , .MPCC_GAMUT_REMAP_MODE[0] = 0x00009000 + 0x014b, .MPC_GAMUT_REMAP_C11_C12_A [0] = 0x00009000 + 0x014c, .MPC_GAMUT_REMAP_C33_C34_A[0] = 0x00009000 + 0x0151, .MPC_GAMUT_REMAP_C11_C12_B[0] = 0x00009000 + 0x0152 , .MPC_GAMUT_REMAP_C33_C34_B[0] = 0x00009000 + 0x0157, .MPCC_OGAM_RAMA_START_CNTL_B [0] = 0x00009000 + 0x0104, .MPCC_OGAM_RAMA_START_CNTL_G[0] = 0x00009000 + 0x0105, .MPCC_OGAM_RAMA_START_CNTL_R[0] = 0x00009000 + 0x0106 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[0] = 0x00009000 + 0x0107 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[0] = 0x00009000 + 0x0108 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[0] = 0x00009000 + 0x0109 , .MPCC_OGAM_RAMA_END_CNTL1_B[0] = 0x00009000 + 0x010d, .MPCC_OGAM_RAMA_END_CNTL2_B [0] = 0x00009000 + 0x010e, .MPCC_OGAM_RAMA_END_CNTL1_G[0] = 0x00009000 + 0x010f, .MPCC_OGAM_RAMA_END_CNTL2_G[0] = 0x00009000 + 0x0110 , .MPCC_OGAM_RAMA_END_CNTL1_R[0] = 0x00009000 + 0x0111, .MPCC_OGAM_RAMA_END_CNTL2_R [0] = 0x00009000 + 0x0112, .MPCC_OGAM_RAMA_REGION_0_1[0] = 0x00009000 + 0x0116, .MPCC_OGAM_RAMA_REGION_32_33[0] = 0x00009000 + 0x0126 , .MPCC_OGAM_RAMA_OFFSET_B[0] = 0x00009000 + 0x0113, .MPCC_OGAM_RAMA_OFFSET_G [0] = 0x00009000 + 0x0114, .MPCC_OGAM_RAMA_OFFSET_R[0] = 0x00009000 + 0x0115, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[0] = 0x00009000 + 0x010a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[0] = 0x00009000 + 0x010b , .MPCC_OGAM_RAMA_START_BASE_CNTL_R[0] = 0x00009000 + 0x010c, .MPCC_OGAM_RAMB_START_CNTL_B[0] = 0x00009000 + 0x0127, .MPCC_OGAM_RAMB_START_CNTL_G [0] = 0x00009000 + 0x0128, .MPCC_OGAM_RAMB_START_CNTL_R[0] = 0x00009000 + 0x0129, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[0] = 0x00009000 + 0x012a, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[0] = 0x00009000 + 0x012b, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[0] = 0x00009000 + 0x012c, .MPCC_OGAM_RAMB_END_CNTL1_B[0] = 0x00009000 + 0x0130 , .MPCC_OGAM_RAMB_END_CNTL2_B[0] = 0x00009000 + 0x0131, .MPCC_OGAM_RAMB_END_CNTL1_G [0] = 0x00009000 + 0x0132, .MPCC_OGAM_RAMB_END_CNTL2_G[0] = 0x00009000 + 0x0133, .MPCC_OGAM_RAMB_END_CNTL1_R[0] = 0x00009000 + 0x0134 , .MPCC_OGAM_RAMB_END_CNTL2_R[0] = 0x00009000 + 0x0135, .MPCC_OGAM_RAMB_REGION_0_1 [0] = 0x00009000 + 0x0139, .MPCC_OGAM_RAMB_REGION_32_33[0] = 0x00009000 + 0x0149, .MPCC_OGAM_RAMB_OFFSET_B[0] = 0x00009000 + 0x0136, .MPCC_OGAM_RAMB_OFFSET_G[0] = 0x00009000 + 0x0137, .MPCC_OGAM_RAMB_OFFSET_R [0] = 0x00009000 + 0x0138, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[ 0] = 0x00009000 + 0x012d, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[0 ] = 0x00009000 + 0x012e, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[0] = 0x00009000 + 0x012f, .MPCC_OGAM_CONTROL[0] = 0x00009000 + 0x0100 , .MPCC_OGAM_LUT_CONTROL[0] = 0x00009000 + 0x0103, | ||||
| 588 | MPC_REG_LIST_DCN3_0(1).MPCC_TOP_SEL[1] = 0x00009000 + 0x0020, .MPCC_BOT_SEL[1] = 0x00009000 + 0x0021, .MPCC_CONTROL[1] = 0x00009000 + 0x0023, .MPCC_STATUS [1] = 0x00009000 + 0x002d, .MPCC_OPP_ID[1] = 0x00009000 + 0x0022 , .MPCC_BG_G_Y[1] = 0x00009000 + 0x002a, .MPCC_BG_R_CR[1] = 0x00009000 + 0x0029, .MPCC_BG_B_CB[1] = 0x00009000 + 0x002b, .MPCC_SM_CONTROL [1] = 0x00009000 + 0x0024, .MPCC_UPDATE_LOCK_SEL[1] = 0x00009000 + 0x0025, .MPCC_TOP_GAIN[1] = 0x00009000 + 0x0026, .MPCC_BOT_GAIN_INSIDE [1] = 0x00009000 + 0x0027, .MPCC_BOT_GAIN_OUTSIDE[1] = 0x00009000 + 0x0028, .MPCC_MEM_PWR_CTRL[1] = 0x00009000 + 0x002c, .MPCC_OGAM_LUT_INDEX [1] = 0x00009000 + 0x0181, .MPCC_OGAM_LUT_DATA[1] = 0x00009000 + 0x0182, .MPCC_GAMUT_REMAP_COEF_FORMAT[1] = 0x00009000 + 0x01ca , .MPCC_GAMUT_REMAP_MODE[1] = 0x00009000 + 0x01cb, .MPC_GAMUT_REMAP_C11_C12_A [1] = 0x00009000 + 0x01cc, .MPC_GAMUT_REMAP_C33_C34_A[1] = 0x00009000 + 0x01d1, .MPC_GAMUT_REMAP_C11_C12_B[1] = 0x00009000 + 0x01d2 , .MPC_GAMUT_REMAP_C33_C34_B[1] = 0x00009000 + 0x01d7, .MPCC_OGAM_RAMA_START_CNTL_B [1] = 0x00009000 + 0x0184, .MPCC_OGAM_RAMA_START_CNTL_G[1] = 0x00009000 + 0x0185, .MPCC_OGAM_RAMA_START_CNTL_R[1] = 0x00009000 + 0x0186 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[1] = 0x00009000 + 0x0187 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[1] = 0x00009000 + 0x0188 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[1] = 0x00009000 + 0x0189 , .MPCC_OGAM_RAMA_END_CNTL1_B[1] = 0x00009000 + 0x018d, .MPCC_OGAM_RAMA_END_CNTL2_B [1] = 0x00009000 + 0x018e, .MPCC_OGAM_RAMA_END_CNTL1_G[1] = 0x00009000 + 0x018f, .MPCC_OGAM_RAMA_END_CNTL2_G[1] = 0x00009000 + 0x0190 , .MPCC_OGAM_RAMA_END_CNTL1_R[1] = 0x00009000 + 0x0191, .MPCC_OGAM_RAMA_END_CNTL2_R [1] = 0x00009000 + 0x0192, .MPCC_OGAM_RAMA_REGION_0_1[1] = 0x00009000 + 0x0196, .MPCC_OGAM_RAMA_REGION_32_33[1] = 0x00009000 + 0x01a6 , .MPCC_OGAM_RAMA_OFFSET_B[1] = 0x00009000 + 0x0193, .MPCC_OGAM_RAMA_OFFSET_G [1] = 0x00009000 + 0x0194, .MPCC_OGAM_RAMA_OFFSET_R[1] = 0x00009000 + 0x0195, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[1] = 0x00009000 + 0x018a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[1] = 0x00009000 + 0x018b , .MPCC_OGAM_RAMA_START_BASE_CNTL_R[1] = 0x00009000 + 0x018c, .MPCC_OGAM_RAMB_START_CNTL_B[1] = 0x00009000 + 0x01a7, .MPCC_OGAM_RAMB_START_CNTL_G [1] = 0x00009000 + 0x01a8, .MPCC_OGAM_RAMB_START_CNTL_R[1] = 0x00009000 + 0x01a9, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[1] = 0x00009000 + 0x01aa, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[1] = 0x00009000 + 0x01ab, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[1] = 0x00009000 + 0x01ac, .MPCC_OGAM_RAMB_END_CNTL1_B[1] = 0x00009000 + 0x01b0 , .MPCC_OGAM_RAMB_END_CNTL2_B[1] = 0x00009000 + 0x01b1, .MPCC_OGAM_RAMB_END_CNTL1_G [1] = 0x00009000 + 0x01b2, .MPCC_OGAM_RAMB_END_CNTL2_G[1] = 0x00009000 + 0x01b3, .MPCC_OGAM_RAMB_END_CNTL1_R[1] = 0x00009000 + 0x01b4 , .MPCC_OGAM_RAMB_END_CNTL2_R[1] = 0x00009000 + 0x01b5, .MPCC_OGAM_RAMB_REGION_0_1 [1] = 0x00009000 + 0x01b9, .MPCC_OGAM_RAMB_REGION_32_33[1] = 0x00009000 + 0x01c9, .MPCC_OGAM_RAMB_OFFSET_B[1] = 0x00009000 + 0x01b6, .MPCC_OGAM_RAMB_OFFSET_G[1] = 0x00009000 + 0x01b7, .MPCC_OGAM_RAMB_OFFSET_R [1] = 0x00009000 + 0x01b8, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[ 1] = 0x00009000 + 0x01ad, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[1 ] = 0x00009000 + 0x01ae, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[1] = 0x00009000 + 0x01af, .MPCC_OGAM_CONTROL[1] = 0x00009000 + 0x0180 , .MPCC_OGAM_LUT_CONTROL[1] = 0x00009000 + 0x0183, | ||||
| 589 | MPC_REG_LIST_DCN3_0(2).MPCC_TOP_SEL[2] = 0x00009000 + 0x0040, .MPCC_BOT_SEL[2] = 0x00009000 + 0x0041, .MPCC_CONTROL[2] = 0x00009000 + 0x0043, .MPCC_STATUS [2] = 0x00009000 + 0x004d, .MPCC_OPP_ID[2] = 0x00009000 + 0x0042 , .MPCC_BG_G_Y[2] = 0x00009000 + 0x004a, .MPCC_BG_R_CR[2] = 0x00009000 + 0x0049, .MPCC_BG_B_CB[2] = 0x00009000 + 0x004b, .MPCC_SM_CONTROL [2] = 0x00009000 + 0x0044, .MPCC_UPDATE_LOCK_SEL[2] = 0x00009000 + 0x0045, .MPCC_TOP_GAIN[2] = 0x00009000 + 0x0046, .MPCC_BOT_GAIN_INSIDE [2] = 0x00009000 + 0x0047, .MPCC_BOT_GAIN_OUTSIDE[2] = 0x00009000 + 0x0048, .MPCC_MEM_PWR_CTRL[2] = 0x00009000 + 0x004c, .MPCC_OGAM_LUT_INDEX [2] = 0x00009000 + 0x0201, .MPCC_OGAM_LUT_DATA[2] = 0x00009000 + 0x0202, .MPCC_GAMUT_REMAP_COEF_FORMAT[2] = 0x00009000 + 0x024a , .MPCC_GAMUT_REMAP_MODE[2] = 0x00009000 + 0x024b, .MPC_GAMUT_REMAP_C11_C12_A [2] = 0x00009000 + 0x024c, .MPC_GAMUT_REMAP_C33_C34_A[2] = 0x00009000 + 0x0251, .MPC_GAMUT_REMAP_C11_C12_B[2] = 0x00009000 + 0x0252 , .MPC_GAMUT_REMAP_C33_C34_B[2] = 0x00009000 + 0x0257, .MPCC_OGAM_RAMA_START_CNTL_B [2] = 0x00009000 + 0x0204, .MPCC_OGAM_RAMA_START_CNTL_G[2] = 0x00009000 + 0x0205, .MPCC_OGAM_RAMA_START_CNTL_R[2] = 0x00009000 + 0x0206 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[2] = 0x00009000 + 0x0207 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[2] = 0x00009000 + 0x0208 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[2] = 0x00009000 + 0x0209 , .MPCC_OGAM_RAMA_END_CNTL1_B[2] = 0x00009000 + 0x020d, .MPCC_OGAM_RAMA_END_CNTL2_B [2] = 0x00009000 + 0x020e, .MPCC_OGAM_RAMA_END_CNTL1_G[2] = 0x00009000 + 0x020f, .MPCC_OGAM_RAMA_END_CNTL2_G[2] = 0x00009000 + 0x0210 , .MPCC_OGAM_RAMA_END_CNTL1_R[2] = 0x00009000 + 0x0211, .MPCC_OGAM_RAMA_END_CNTL2_R [2] = 0x00009000 + 0x0212, .MPCC_OGAM_RAMA_REGION_0_1[2] = 0x00009000 + 0x0216, .MPCC_OGAM_RAMA_REGION_32_33[2] = 0x00009000 + 0x0226 , .MPCC_OGAM_RAMA_OFFSET_B[2] = 0x00009000 + 0x0213, .MPCC_OGAM_RAMA_OFFSET_G [2] = 0x00009000 + 0x0214, .MPCC_OGAM_RAMA_OFFSET_R[2] = 0x00009000 + 0x0215, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[2] = 0x00009000 + 0x020a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[2] = 0x00009000 + 0x020b , .MPCC_OGAM_RAMA_START_BASE_CNTL_R[2] = 0x00009000 + 0x020c, .MPCC_OGAM_RAMB_START_CNTL_B[2] = 0x00009000 + 0x0227, .MPCC_OGAM_RAMB_START_CNTL_G [2] = 0x00009000 + 0x0228, .MPCC_OGAM_RAMB_START_CNTL_R[2] = 0x00009000 + 0x0229, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[2] = 0x00009000 + 0x022a, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[2] = 0x00009000 + 0x022b, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[2] = 0x00009000 + 0x022c, .MPCC_OGAM_RAMB_END_CNTL1_B[2] = 0x00009000 + 0x0230 , .MPCC_OGAM_RAMB_END_CNTL2_B[2] = 0x00009000 + 0x0231, .MPCC_OGAM_RAMB_END_CNTL1_G [2] = 0x00009000 + 0x0232, .MPCC_OGAM_RAMB_END_CNTL2_G[2] = 0x00009000 + 0x0233, .MPCC_OGAM_RAMB_END_CNTL1_R[2] = 0x00009000 + 0x0234 , .MPCC_OGAM_RAMB_END_CNTL2_R[2] = 0x00009000 + 0x0235, .MPCC_OGAM_RAMB_REGION_0_1 [2] = 0x00009000 + 0x0239, .MPCC_OGAM_RAMB_REGION_32_33[2] = 0x00009000 + 0x0249, .MPCC_OGAM_RAMB_OFFSET_B[2] = 0x00009000 + 0x0236, .MPCC_OGAM_RAMB_OFFSET_G[2] = 0x00009000 + 0x0237, .MPCC_OGAM_RAMB_OFFSET_R [2] = 0x00009000 + 0x0238, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[ 2] = 0x00009000 + 0x022d, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[2 ] = 0x00009000 + 0x022e, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[2] = 0x00009000 + 0x022f, .MPCC_OGAM_CONTROL[2] = 0x00009000 + 0x0200 , .MPCC_OGAM_LUT_CONTROL[2] = 0x00009000 + 0x0203, | ||||
| 590 | MPC_REG_LIST_DCN3_0(3).MPCC_TOP_SEL[3] = 0x00009000 + 0x0060, .MPCC_BOT_SEL[3] = 0x00009000 + 0x0061, .MPCC_CONTROL[3] = 0x00009000 + 0x0063, .MPCC_STATUS [3] = 0x00009000 + 0x006d, .MPCC_OPP_ID[3] = 0x00009000 + 0x0062 , .MPCC_BG_G_Y[3] = 0x00009000 + 0x006a, .MPCC_BG_R_CR[3] = 0x00009000 + 0x0069, .MPCC_BG_B_CB[3] = 0x00009000 + 0x006b, .MPCC_SM_CONTROL [3] = 0x00009000 + 0x0064, .MPCC_UPDATE_LOCK_SEL[3] = 0x00009000 + 0x0065, .MPCC_TOP_GAIN[3] = 0x00009000 + 0x0066, .MPCC_BOT_GAIN_INSIDE [3] = 0x00009000 + 0x0067, .MPCC_BOT_GAIN_OUTSIDE[3] = 0x00009000 + 0x0068, .MPCC_MEM_PWR_CTRL[3] = 0x00009000 + 0x006c, .MPCC_OGAM_LUT_INDEX [3] = 0x00009000 + 0x0281, .MPCC_OGAM_LUT_DATA[3] = 0x00009000 + 0x0282, .MPCC_GAMUT_REMAP_COEF_FORMAT[3] = 0x00009000 + 0x02ca , .MPCC_GAMUT_REMAP_MODE[3] = 0x00009000 + 0x02cb, .MPC_GAMUT_REMAP_C11_C12_A [3] = 0x00009000 + 0x02cc, .MPC_GAMUT_REMAP_C33_C34_A[3] = 0x00009000 + 0x02d1, .MPC_GAMUT_REMAP_C11_C12_B[3] = 0x00009000 + 0x02d2 , .MPC_GAMUT_REMAP_C33_C34_B[3] = 0x00009000 + 0x02d7, .MPCC_OGAM_RAMA_START_CNTL_B [3] = 0x00009000 + 0x0284, .MPCC_OGAM_RAMA_START_CNTL_G[3] = 0x00009000 + 0x0285, .MPCC_OGAM_RAMA_START_CNTL_R[3] = 0x00009000 + 0x0286 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[3] = 0x00009000 + 0x0287 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[3] = 0x00009000 + 0x0288 , .MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[3] = 0x00009000 + 0x0289 , .MPCC_OGAM_RAMA_END_CNTL1_B[3] = 0x00009000 + 0x028d, .MPCC_OGAM_RAMA_END_CNTL2_B [3] = 0x00009000 + 0x028e, .MPCC_OGAM_RAMA_END_CNTL1_G[3] = 0x00009000 + 0x028f, .MPCC_OGAM_RAMA_END_CNTL2_G[3] = 0x00009000 + 0x0290 , .MPCC_OGAM_RAMA_END_CNTL1_R[3] = 0x00009000 + 0x0291, .MPCC_OGAM_RAMA_END_CNTL2_R [3] = 0x00009000 + 0x0292, .MPCC_OGAM_RAMA_REGION_0_1[3] = 0x00009000 + 0x0296, .MPCC_OGAM_RAMA_REGION_32_33[3] = 0x00009000 + 0x02a6 , .MPCC_OGAM_RAMA_OFFSET_B[3] = 0x00009000 + 0x0293, .MPCC_OGAM_RAMA_OFFSET_G [3] = 0x00009000 + 0x0294, .MPCC_OGAM_RAMA_OFFSET_R[3] = 0x00009000 + 0x0295, .MPCC_OGAM_RAMA_START_BASE_CNTL_B[3] = 0x00009000 + 0x028a, .MPCC_OGAM_RAMA_START_BASE_CNTL_G[3] = 0x00009000 + 0x028b , .MPCC_OGAM_RAMA_START_BASE_CNTL_R[3] = 0x00009000 + 0x028c, .MPCC_OGAM_RAMB_START_CNTL_B[3] = 0x00009000 + 0x02a7, .MPCC_OGAM_RAMB_START_CNTL_G [3] = 0x00009000 + 0x02a8, .MPCC_OGAM_RAMB_START_CNTL_R[3] = 0x00009000 + 0x02a9, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[3] = 0x00009000 + 0x02aa, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[3] = 0x00009000 + 0x02ab, .MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[3] = 0x00009000 + 0x02ac, .MPCC_OGAM_RAMB_END_CNTL1_B[3] = 0x00009000 + 0x02b0 , .MPCC_OGAM_RAMB_END_CNTL2_B[3] = 0x00009000 + 0x02b1, .MPCC_OGAM_RAMB_END_CNTL1_G [3] = 0x00009000 + 0x02b2, .MPCC_OGAM_RAMB_END_CNTL2_G[3] = 0x00009000 + 0x02b3, .MPCC_OGAM_RAMB_END_CNTL1_R[3] = 0x00009000 + 0x02b4 , .MPCC_OGAM_RAMB_END_CNTL2_R[3] = 0x00009000 + 0x02b5, .MPCC_OGAM_RAMB_REGION_0_1 [3] = 0x00009000 + 0x02b9, .MPCC_OGAM_RAMB_REGION_32_33[3] = 0x00009000 + 0x02c9, .MPCC_OGAM_RAMB_OFFSET_B[3] = 0x00009000 + 0x02b6, .MPCC_OGAM_RAMB_OFFSET_G[3] = 0x00009000 + 0x02b7, .MPCC_OGAM_RAMB_OFFSET_R [3] = 0x00009000 + 0x02b8, .MPCC_OGAM_RAMB_START_BASE_CNTL_B[ 3] = 0x00009000 + 0x02ad, .MPCC_OGAM_RAMB_START_BASE_CNTL_G[3 ] = 0x00009000 + 0x02ae, .MPCC_OGAM_RAMB_START_BASE_CNTL_R[3] = 0x00009000 + 0x02af, .MPCC_OGAM_CONTROL[3] = 0x00009000 + 0x0280 , .MPCC_OGAM_LUT_CONTROL[3] = 0x00009000 + 0x0283, | ||||
| 591 | MPC_OUT_MUX_REG_LIST_DCN3_0(0).MUX[0] = 0x00009000 + 0x0580, .CUR[0] = 0x00009000 + 0x0513, .CSC_MODE[0] = 0x00009000 + 0x05a1, .CSC_C11_C12_A[0] = 0x00009000 + 0x05a2, .CSC_C33_C34_A[0] = 0x00009000 + 0x05a7, .CSC_C11_C12_B [0] = 0x00009000 + 0x05a8, .CSC_C33_C34_B[0] = 0x00009000 + 0x05ad , .DENORM_CONTROL[0] = 0x00009000 + 0x0581, .DENORM_CLAMP_G_Y [0] = 0x00009000 + 0x0582, .DENORM_CLAMP_B_CB[0] = 0x00009000 + 0x0583, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x05a0, | ||||
| 592 | MPC_OUT_MUX_REG_LIST_DCN3_0(1).MUX[1] = 0x00009000 + 0x0584, .CUR[1] = 0x00009000 + 0x0518, .CSC_MODE[1] = 0x00009000 + 0x05ae, .CSC_C11_C12_A[1] = 0x00009000 + 0x05af, .CSC_C33_C34_A[1] = 0x00009000 + 0x05b4, .CSC_C11_C12_B [1] = 0x00009000 + 0x05b5, .CSC_C33_C34_B[1] = 0x00009000 + 0x05ba , .DENORM_CONTROL[1] = 0x00009000 + 0x0585, .DENORM_CLAMP_G_Y [1] = 0x00009000 + 0x0586, .DENORM_CLAMP_B_CB[1] = 0x00009000 + 0x0587, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x05a0, | ||||
| 593 | MPC_OUT_MUX_REG_LIST_DCN3_0(2).MUX[2] = 0x00009000 + 0x0588, .CUR[2] = 0x00009000 + 0x051d, .CSC_MODE[2] = 0x00009000 + 0x05bb, .CSC_C11_C12_A[2] = 0x00009000 + 0x05bc, .CSC_C33_C34_A[2] = 0x00009000 + 0x05c1, .CSC_C11_C12_B [2] = 0x00009000 + 0x05c2, .CSC_C33_C34_B[2] = 0x00009000 + 0x05c7 , .DENORM_CONTROL[2] = 0x00009000 + 0x0589, .DENORM_CLAMP_G_Y [2] = 0x00009000 + 0x058a, .DENORM_CLAMP_B_CB[2] = 0x00009000 + 0x058b, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x05a0, | ||||
| 594 | MPC_OUT_MUX_REG_LIST_DCN3_0(3).MUX[3] = 0x00009000 + 0x058c, .CUR[3] = 0x00009000 + 0x0522, .CSC_MODE[3] = 0x00009000 + 0x05c8, .CSC_C11_C12_A[3] = 0x00009000 + 0x05c9, .CSC_C33_C34_A[3] = 0x00009000 + 0x05ce, .CSC_C11_C12_B [3] = 0x00009000 + 0x05cf, .CSC_C33_C34_B[3] = 0x00009000 + 0x05d4 , .DENORM_CONTROL[3] = 0x00009000 + 0x058d, .DENORM_CLAMP_G_Y [3] = 0x00009000 + 0x058e, .DENORM_CLAMP_B_CB[3] = 0x00009000 + 0x058f, .MPC_OUT_CSC_COEF_FORMAT = 0x00009000 + 0x05a0, | ||||
| 595 | MPC_DWB_MUX_REG_LIST_DCN3_0(0).DWB_MUX[0] = 0x00009000 + 0x055c, | ||||
| 596 | }; | ||||
| 597 | |||||
| 598 | static const struct dcn30_mpc_shift mpc_shift = { | ||||
| 599 | MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT).MPCC_TOP_SEL = 0x0, .MPCC_BOT_SEL = 0x0, .MPCC_MODE = 0x0, . MPCC_ALPHA_BLND_MODE = 0x4, .MPCC_ALPHA_MULTIPLIED_MODE = 0x6 , .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x7, .MPCC_GLOBAL_ALPHA = 0x10 , .MPCC_GLOBAL_GAIN = 0x18, .MPCC_IDLE = 0x0, .MPCC_BUSY = 0x1 , .MPCC_OPP_ID = 0x0, .MPCC_BG_G_Y = 0x0, .MPCC_BG_R_CR = 0x0 , .MPCC_BG_B_CB = 0x0, .MPCC_SM_EN = 0x0, .MPCC_SM_MODE = 0x1 , .MPCC_SM_FRAME_ALT = 0x4, .MPCC_SM_FIELD_ALT = 0x5, .MPCC_SM_FORCE_NEXT_FRAME_POL = 0x8, .MPCC_SM_FORCE_NEXT_TOP_POL = 0x10, .MPC_OUT_MUX = 0x0 , .MPCC_UPDATE_LOCK_SEL = 0x0, .MPCC_BG_BPC = 0x8, .MPCC_BOT_GAIN_MODE = 0xb, .MPCC_TOP_GAIN = 0x0, .MPCC_BOT_GAIN_INSIDE = 0x0, .MPCC_BOT_GAIN_OUTSIDE = 0x0, .MPC_OCSC_MODE = 0x0, .MPC_OCSC_C11_A = 0x0, .MPC_OCSC_C12_A = 0x10, .MPCC_DISABLED = 0x2, .MPCC_OGAM_MEM_PWR_FORCE = 0x0 , .MPCC_OGAM_MEM_PWR_DIS = 0x2, .MPCC_OGAM_MEM_LOW_PWR_MODE = 0x4, .MPCC_OGAM_MEM_PWR_STATE = 0x8, .MPC_OUT_DENORM_MODE = 0x18 , .MPC_OUT_DENORM_CLAMP_MAX_R_CR = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_R_CR = 0x0, .MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_G_Y = 0x0, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_B_CB = 0x0, .MPCC_GAMUT_REMAP_MODE = 0x0, .MPCC_GAMUT_REMAP_MODE_CURRENT = 0x7, .MPCC_GAMUT_REMAP_COEF_FORMAT = 0x0, .MPCC_GAMUT_REMAP_C11_A = 0x0, .MPCC_GAMUT_REMAP_C12_A = 0x10, .MPC_DWB0_MUX = 0x0, . MPC_DWB0_MUX_STATUS = 0x4, .MPC_OUT_RATE_CONTROL = 0x9, .MPC_OUT_RATE_CONTROL_DISABLE = 0x8, .MPC_OUT_FLOW_CONTROL_MODE = 0xa, .MPC_OUT_FLOW_CONTROL_COUNT = 0xb, .MPC_RMU0_MUX = 0x0, .MPC_RMU1_MUX = 0x8, .MPC_RMU0_MUX_STATUS = 0x4, .MPC_RMU1_MUX_STATUS = 0xc, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x10, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .MPCC_OGAM_RAMA_OFFSET_B = 0x0, .MPCC_OGAM_RAMA_OFFSET_G = 0x0, .MPCC_OGAM_RAMA_OFFSET_R = 0x0, .MPCC_OGAM_LUT_INDEX = 0x0, .MPCC_OGAM_MODE = 0x0, .MPCC_OGAM_SELECT = 0x2, .MPCC_OGAM_PWL_DISABLE = 0x3, .MPCC_OGAM_MODE_CURRENT = 0x7, .MPCC_OGAM_SELECT_CURRENT = 0x9, .MPCC_OGAM_LUT_WRITE_COLOR_MASK = 0x0, .MPCC_OGAM_LUT_READ_COLOR_SEL = 0x3, .MPCC_OGAM_LUT_READ_DBG = 0x5, .MPCC_OGAM_LUT_HOST_SEL = 0x6, .MPCC_OGAM_LUT_CONFIG_MODE = 0x7, .MPCC_OGAM_LUT_DATA = 0x0, .MPC_RMU_3DLUT_MODE = 0x0, .MPC_RMU_3DLUT_SIZE = 0x4, .MPC_RMU_3DLUT_WRITE_EN_MASK = 0x0, .MPC_RMU_3DLUT_RAM_SEL = 0x4, .MPC_RMU_3DLUT_30BIT_EN = 0x8, .MPC_RMU_3DLUT_READ_SEL = 0x10, .MPC_RMU_3DLUT_INDEX = 0x0, .MPC_RMU_3DLUT_DATA0 = 0x0 , .MPC_RMU_3DLUT_DATA1 = 0x10, .MPC_RMU_3DLUT_DATA_30BIT = 0x2 , .MPC_RMU_SHAPER_LUT_MODE = 0x0, .MPC_RMU_SHAPER_OFFSET_R = 0x0 , .MPC_RMU_SHAPER_OFFSET_G = 0x0, .MPC_RMU_SHAPER_OFFSET_B = 0x0 , .MPC_RMU_SHAPER_SCALE_R = 0x0, .MPC_RMU_SHAPER_SCALE_G = 0x0 , .MPC_RMU_SHAPER_SCALE_B = 0x10, .MPC_RMU_SHAPER_LUT_INDEX = 0x0, .MPC_RMU_SHAPER_LUT_DATA = 0x0, .MPC_RMU_SHAPER_LUT_WRITE_EN_MASK = 0x0, .MPC_RMU_SHAPER_LUT_WRITE_SEL = 0x4, .MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B = 0x0, .MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x14 , .MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B = 0x0, .MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x10, .MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, . MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c , .MPC_RMU0_MEM_PWR_FORCE = 0x0, .MPC_RMU0_MEM_PWR_DIS = 0x2, .MPC_RMU0_SHAPER_MEM_PWR_STATE = 0x4, .MPC_RMU0_3DLUT_MEM_PWR_STATE = 0x6, .MPC_RMU0_MEM_LOW_PWR_MODE = 0x8, .MPC_RMU1_MEM_PWR_FORCE = 0xa, .MPC_RMU1_MEM_PWR_DIS = 0xc, .MPC_RMU1_SHAPER_MEM_PWR_STATE = 0xe, .MPC_RMU1_3DLUT_MEM_PWR_STATE = 0x10, .MPC_RMU1_MEM_LOW_PWR_MODE = 0x12, .MPC_RMU_SHAPER_MODE_CURRENT = 0x8, .CUR_VUPDATE_LOCK_SET = 0x0 | ||||
| 600 | }; | ||||
| 601 | |||||
| 602 | static const struct dcn30_mpc_mask mpc_mask = { | ||||
| 603 | MPC_COMMON_MASK_SH_LIST_DCN30(_MASK).MPCC_TOP_SEL = 0x0000000FL, .MPCC_BOT_SEL = 0x0000000FL, .MPCC_MODE = 0x00000003L, .MPCC_ALPHA_BLND_MODE = 0x00000030L, .MPCC_ALPHA_MULTIPLIED_MODE = 0x00000040L, .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x00000080L, .MPCC_GLOBAL_ALPHA = 0x00FF0000L, .MPCC_GLOBAL_GAIN = 0xFF000000L , .MPCC_IDLE = 0x00000001L, .MPCC_BUSY = 0x00000002L, .MPCC_OPP_ID = 0x0000000FL, .MPCC_BG_G_Y = 0x00000FFFL, .MPCC_BG_R_CR = 0x00000FFFL , .MPCC_BG_B_CB = 0x00000FFFL, .MPCC_SM_EN = 0x00000001L, .MPCC_SM_MODE = 0x0000000EL, .MPCC_SM_FRAME_ALT = 0x00000010L, .MPCC_SM_FIELD_ALT = 0x00000020L, .MPCC_SM_FORCE_NEXT_FRAME_POL = 0x00000300L, . MPCC_SM_FORCE_NEXT_TOP_POL = 0x00030000L, .MPC_OUT_MUX = 0x0000000FL , .MPCC_UPDATE_LOCK_SEL = 0x0000000FL, .MPCC_BG_BPC = 0x00000700L , .MPCC_BOT_GAIN_MODE = 0x00000800L, .MPCC_TOP_GAIN = 0x0007FFFFL , .MPCC_BOT_GAIN_INSIDE = 0x0007FFFFL, .MPCC_BOT_GAIN_OUTSIDE = 0x0007FFFFL, .MPC_OCSC_MODE = 0x00000003L, .MPC_OCSC_C11_A = 0x0000FFFFL, .MPC_OCSC_C12_A = 0xFFFF0000L, .MPCC_DISABLED = 0x00000004L, .MPCC_OGAM_MEM_PWR_FORCE = 0x00000003L, .MPCC_OGAM_MEM_PWR_DIS = 0x00000004L, .MPCC_OGAM_MEM_LOW_PWR_MODE = 0x00000030L, .MPCC_OGAM_MEM_PWR_STATE = 0x00000300L, .MPC_OUT_DENORM_MODE = 0x07000000L, .MPC_OUT_DENORM_CLAMP_MAX_R_CR = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_R_CR = 0x00000FFFL, .MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_G_Y = 0x00000FFFL, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_B_CB = 0x00000FFFL, .MPCC_GAMUT_REMAP_MODE = 0x00000003L, .MPCC_GAMUT_REMAP_MODE_CURRENT = 0x00000180L, .MPCC_GAMUT_REMAP_COEF_FORMAT = 0x00000001L, .MPCC_GAMUT_REMAP_C11_A = 0x0000FFFFL, .MPCC_GAMUT_REMAP_C12_A = 0xFFFF0000L, .MPC_DWB0_MUX = 0x0000000FL, .MPC_DWB0_MUX_STATUS = 0x000000F0L, .MPC_OUT_RATE_CONTROL = 0x00000200L, .MPC_OUT_RATE_CONTROL_DISABLE = 0x00000100L, . MPC_OUT_FLOW_CONTROL_MODE = 0x00000400L, .MPC_OUT_FLOW_CONTROL_COUNT = 0x007FF800L, .MPC_RMU0_MUX = 0x0000000FL, .MPC_RMU1_MUX = 0x00000F00L , .MPC_RMU0_MUX_STATUS = 0x000000F0L, .MPC_RMU1_MUX_STATUS = 0x0000F000L , .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L , .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0xFFFF0000L, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL , .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B = 0x0003FFFFL , .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .MPCC_OGAM_RAMA_OFFSET_B = 0x0007FFFFL, .MPCC_OGAM_RAMA_OFFSET_G = 0x0007FFFFL, .MPCC_OGAM_RAMA_OFFSET_R = 0x0007FFFFL, .MPCC_OGAM_LUT_INDEX = 0x000001FFL, .MPCC_OGAM_MODE = 0x00000003L, .MPCC_OGAM_SELECT = 0x00000004L, .MPCC_OGAM_PWL_DISABLE = 0x00000008L, .MPCC_OGAM_MODE_CURRENT = 0x00000180L, .MPCC_OGAM_SELECT_CURRENT = 0x00000200L, .MPCC_OGAM_LUT_WRITE_COLOR_MASK = 0x00000007L, .MPCC_OGAM_LUT_READ_COLOR_SEL = 0x00000018L, . MPCC_OGAM_LUT_READ_DBG = 0x00000020L, .MPCC_OGAM_LUT_HOST_SEL = 0x00000040L, .MPCC_OGAM_LUT_CONFIG_MODE = 0x00000080L, .MPCC_OGAM_LUT_DATA = 0x0003FFFFL, .MPC_RMU_3DLUT_MODE = 0x00000003L, .MPC_RMU_3DLUT_SIZE = 0x00000010L, .MPC_RMU_3DLUT_WRITE_EN_MASK = 0x0000000FL, . MPC_RMU_3DLUT_RAM_SEL = 0x00000010L, .MPC_RMU_3DLUT_30BIT_EN = 0x00000100L, .MPC_RMU_3DLUT_READ_SEL = 0x00030000L, .MPC_RMU_3DLUT_INDEX = 0x000007FFL, .MPC_RMU_3DLUT_DATA0 = 0x0000FFFFL, .MPC_RMU_3DLUT_DATA1 = 0xFFFF0000L, .MPC_RMU_3DLUT_DATA_30BIT = 0xFFFFFFFCL, .MPC_RMU_SHAPER_LUT_MODE = 0x00000003L, .MPC_RMU_SHAPER_OFFSET_R = 0x0007FFFFL, .MPC_RMU_SHAPER_OFFSET_G = 0x0007FFFFL, .MPC_RMU_SHAPER_OFFSET_B = 0x0007FFFFL, .MPC_RMU_SHAPER_SCALE_R = 0x0000FFFFL, .MPC_RMU_SHAPER_SCALE_G = 0x0000FFFFL, .MPC_RMU_SHAPER_SCALE_B = 0xFFFF0000L, .MPC_RMU_SHAPER_LUT_INDEX = 0x000000FFL, .MPC_RMU_SHAPER_LUT_DATA = 0x00FFFFFFL, .MPC_RMU_SHAPER_LUT_WRITE_EN_MASK = 0x00000007L , .MPC_RMU_SHAPER_LUT_WRITE_SEL = 0x00000010L, .MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B = 0x0003FFFFL, .MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B = 0x0000FFFFL , .MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x3FFF0000L, . MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .MPC_RMU0_MEM_PWR_FORCE = 0x00000003L, .MPC_RMU0_MEM_PWR_DIS = 0x00000004L, .MPC_RMU0_SHAPER_MEM_PWR_STATE = 0x00000030L, .MPC_RMU0_3DLUT_MEM_PWR_STATE = 0x000000C0L, .MPC_RMU0_MEM_LOW_PWR_MODE = 0x00000300L, .MPC_RMU1_MEM_PWR_FORCE = 0x00000C00L, .MPC_RMU1_MEM_PWR_DIS = 0x00001000L, .MPC_RMU1_SHAPER_MEM_PWR_STATE = 0x0000C000L, .MPC_RMU1_3DLUT_MEM_PWR_STATE = 0x00030000L, .MPC_RMU1_MEM_LOW_PWR_MODE = 0x000C0000L, .MPC_RMU_SHAPER_MODE_CURRENT = 0x00000300L, . CUR_VUPDATE_LOCK_SET = 0x00000001L | ||||
| 604 | }; | ||||
| 605 | |||||
| 606 | #define optc_regs(id)[id] = {.OTG_VSTARTUP_PARAM = DCN_BASE__INST0_SEGregOTGid_OTG_VSTARTUP_PARAM_BASE_IDX + regOTGid_OTG_VSTARTUP_PARAM, .OTG_VUPDATE_PARAM = DCN_BASE__INST0_SEGregOTGid_OTG_VUPDATE_PARAM_BASE_IDX + regOTGid_OTG_VUPDATE_PARAM, .OTG_VREADY_PARAM = DCN_BASE__INST0_SEGregOTGid_OTG_VREADY_PARAM_BASE_IDX + regOTGid_OTG_VREADY_PARAM, .OTG_MASTER_UPDATE_LOCK = DCN_BASE__INST0_SEGregOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX + regOTGid_OTG_MASTER_UPDATE_LOCK, .OTG_GLOBAL_CONTROL0 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL0, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL2, .OTG_GLOBAL_CONTROL4 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL4_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL4, .OTG_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX + regOTGid_OTG_DOUBLE_BUFFER_CONTROL, .OTG_H_TOTAL = DCN_BASE__INST0_SEGregOTGid_OTG_H_TOTAL_BASE_IDX + regOTGid_OTG_H_TOTAL, .OTG_H_BLANK_START_END = DCN_BASE__INST0_SEGregOTGid_OTG_H_BLANK_START_END_BASE_IDX + regOTGid_OTG_H_BLANK_START_END, .OTG_H_SYNC_A = DCN_BASE__INST0_SEGregOTGid_OTG_H_SYNC_A_BASE_IDX + regOTGid_OTG_H_SYNC_A, .OTG_H_SYNC_A_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX + regOTGid_OTG_H_SYNC_A_CNTL, .OTG_H_TIMING_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_H_TIMING_CNTL_BASE_IDX + regOTGid_OTG_H_TIMING_CNTL, .OTG_V_TOTAL = DCN_BASE__INST0_SEGregOTGid_OTG_V_TOTAL_BASE_IDX + regOTGid_OTG_V_TOTAL, .OTG_V_BLANK_START_END = DCN_BASE__INST0_SEGregOTGid_OTG_V_BLANK_START_END_BASE_IDX + regOTGid_OTG_V_BLANK_START_END, .OTG_V_SYNC_A = DCN_BASE__INST0_SEGregOTGid_OTG_V_SYNC_A_BASE_IDX + regOTGid_OTG_V_SYNC_A, .OTG_V_SYNC_A_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX + regOTGid_OTG_V_SYNC_A_CNTL, .OTG_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CONTROL_BASE_IDX + regOTGid_OTG_CONTROL, .OTG_STEREO_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_STEREO_CONTROL_BASE_IDX + regOTGid_OTG_STEREO_CONTROL, .OTG_3D_STRUCTURE_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX + regOTGid_OTG_3D_STRUCTURE_CONTROL, .OTG_STEREO_STATUS = DCN_BASE__INST0_SEGregOTGid_OTG_STEREO_STATUS_BASE_IDX + regOTGid_OTG_STEREO_STATUS, .OTG_V_TOTAL_MAX = DCN_BASE__INST0_SEGregOTGid_OTG_V_TOTAL_MAX_BASE_IDX + regOTGid_OTG_V_TOTAL_MAX, .OTG_V_TOTAL_MIN = DCN_BASE__INST0_SEGregOTGid_OTG_V_TOTAL_MIN_BASE_IDX + regOTGid_OTG_V_TOTAL_MIN, .OTG_V_TOTAL_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX + regOTGid_OTG_V_TOTAL_CONTROL, .OTG_TRIGA_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_TRIGA_CNTL_BASE_IDX + regOTGid_OTG_TRIGA_CNTL, .OTG_FORCE_COUNT_NOW_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX + regOTGid_OTG_FORCE_COUNT_NOW_CNTL, .OTG_STATIC_SCREEN_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX + regOTGid_OTG_STATIC_SCREEN_CONTROL, .OTG_STATUS_FRAME_COUNT = DCN_BASE__INST0_SEGregOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX + regOTGid_OTG_STATUS_FRAME_COUNT, .OTG_STATUS = DCN_BASE__INST0_SEGregOTGid_OTG_STATUS_BASE_IDX + regOTGid_OTG_STATUS, .OTG_STATUS_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_STATUS_POSITION_BASE_IDX + regOTGid_OTG_STATUS_POSITION, .OTG_NOM_VERT_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_NOM_VERT_POSITION_BASE_IDX + regOTGid_OTG_NOM_VERT_POSITION, .OTG_M_CONST_DTO0 = DCN_BASE__INST0_SEGregOTGid_OTG_M_CONST_DTO0_BASE_IDX + regOTGid_OTG_M_CONST_DTO0, .OTG_M_CONST_DTO1 = DCN_BASE__INST0_SEGregOTGid_OTG_M_CONST_DTO1_BASE_IDX + regOTGid_OTG_M_CONST_DTO1, .OTG_CLOCK_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CLOCK_CONTROL_BASE_IDX + regOTGid_OTG_CLOCK_CONTROL, .OTG_VERTICAL_INTERRUPT0_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, .OTG_VERTICAL_INTERRUPT0_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, .OTG_VERTICAL_INTERRUPT1_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, .OTG_VERTICAL_INTERRUPT1_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, .OTG_VERTICAL_INTERRUPT2_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, .OTG_VERTICAL_INTERRUPT2_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, .OPTC_INPUT_CLOCK_CONTROL = DCN_BASE__INST0_SEGregODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX + regODMid_OPTC_INPUT_CLOCK_CONTROL, .OPTC_DATA_SOURCE_SELECT = DCN_BASE__INST0_SEGregODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX + regODMid_OPTC_DATA_SOURCE_SELECT, .OPTC_INPUT_GLOBAL_CONTROL = DCN_BASE__INST0_SEGregODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX + regODMid_OPTC_INPUT_GLOBAL_CONTROL, .CONTROL = DCN_BASE__INST0_SEGregVTGid_CONTROL_BASE_IDX + regVTGid_CONTROL, .OTG_VERT_SYNC_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX + regOTGid_OTG_VERT_SYNC_CONTROL, .OTG_GSL_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_GSL_CONTROL_BASE_IDX + regOTGid_OTG_GSL_CONTROL, .OTG_CRC_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC_CNTL_BASE_IDX + regOTGid_OTG_CRC_CNTL, .OTG_CRC0_DATA_RG = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_DATA_RG_BASE_IDX + regOTGid_OTG_CRC0_DATA_RG, .OTG_CRC0_DATA_B = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_DATA_B_BASE_IDX + regOTGid_OTG_CRC0_DATA_B, .OTG_CRC0_WINDOWA_X_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX + regOTGid_OTG_CRC0_WINDOWA_X_CONTROL, .OTG_CRC0_WINDOWA_Y_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX + regOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, .OTG_CRC0_WINDOWB_X_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX + regOTGid_OTG_CRC0_WINDOWB_X_CONTROL, .OTG_CRC0_WINDOWB_Y_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX + regOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = DCN_BASE__INST0_SEGregOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX + regOTGid_OTG_TRIGA_MANUAL_TRIG, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL2, .OTG_GSL_WINDOW_X = DCN_BASE__INST0_SEGregOTGid_OTG_GSL_WINDOW_X_BASE_IDX + regOTGid_OTG_GSL_WINDOW_X, .OTG_GSL_WINDOW_Y = DCN_BASE__INST0_SEGregOTGid_OTG_GSL_WINDOW_Y_BASE_IDX + regOTGid_OTG_GSL_WINDOW_Y, .OTG_VUPDATE_KEEPOUT = DCN_BASE__INST0_SEGregOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX + regOTGid_OTG_VUPDATE_KEEPOUT, .OTG_DSC_START_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_DSC_START_POSITION_BASE_IDX + regOTGid_OTG_DSC_START_POSITION, .OTG_DRR_TRIGGER_WINDOW = DCN_BASE__INST0_SEGregOTGid_OTG_DRR_TRIGGER_WINDOW_BASE_IDX + regOTGid_OTG_DRR_TRIGGER_WINDOW, .OTG_DRR_V_TOTAL_CHANGE = DCN_BASE__INST0_SEGregOTGid_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX + regOTGid_OTG_DRR_V_TOTAL_CHANGE, .OPTC_DATA_FORMAT_CONTROL = DCN_BASE__INST0_SEGregODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX + regODMid_OPTC_DATA_FORMAT_CONTROL, .OPTC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGregODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX + regODMid_OPTC_BYTES_PER_PIXEL , .OPTC_WIDTH_CONTROL = DCN_BASE__INST0_SEGregODMid_OPTC_WIDTH_CONTROL_BASE_IDX + regODMid_OPTC_WIDTH_CONTROL, .OPTC_MEMORY_CONFIG = DCN_BASE__INST0_SEGregODMid_OPTC_MEMORY_CONFIG_BASE_IDX + regODMid_OPTC_MEMORY_CONFIG, .OTG_CRC_CNTL2 = DCN_BASE__INST0_SEGregOTGid_OTG_CRC_CNTL2_BASE_IDX + regOTGid_OTG_CRC_CNTL2, .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a , .OTG_DRR_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_DRR_CONTROL_BASE_IDX + regOTGid_OTG_DRR_CONTROL}\ | ||||
| 607 | [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id).OTG_VSTARTUP_PARAM = DCN_BASE__INST0_SEGregOTGid_OTG_VSTARTUP_PARAM_BASE_IDX + regOTGid_OTG_VSTARTUP_PARAM, .OTG_VUPDATE_PARAM = DCN_BASE__INST0_SEGregOTGid_OTG_VUPDATE_PARAM_BASE_IDX + regOTGid_OTG_VUPDATE_PARAM, .OTG_VREADY_PARAM = DCN_BASE__INST0_SEGregOTGid_OTG_VREADY_PARAM_BASE_IDX + regOTGid_OTG_VREADY_PARAM, .OTG_MASTER_UPDATE_LOCK = DCN_BASE__INST0_SEGregOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX + regOTGid_OTG_MASTER_UPDATE_LOCK, .OTG_GLOBAL_CONTROL0 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL0, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL2, .OTG_GLOBAL_CONTROL4 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL4_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL4, .OTG_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX + regOTGid_OTG_DOUBLE_BUFFER_CONTROL, .OTG_H_TOTAL = DCN_BASE__INST0_SEGregOTGid_OTG_H_TOTAL_BASE_IDX + regOTGid_OTG_H_TOTAL, .OTG_H_BLANK_START_END = DCN_BASE__INST0_SEGregOTGid_OTG_H_BLANK_START_END_BASE_IDX + regOTGid_OTG_H_BLANK_START_END, .OTG_H_SYNC_A = DCN_BASE__INST0_SEGregOTGid_OTG_H_SYNC_A_BASE_IDX + regOTGid_OTG_H_SYNC_A, .OTG_H_SYNC_A_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX + regOTGid_OTG_H_SYNC_A_CNTL, .OTG_H_TIMING_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_H_TIMING_CNTL_BASE_IDX + regOTGid_OTG_H_TIMING_CNTL, .OTG_V_TOTAL = DCN_BASE__INST0_SEGregOTGid_OTG_V_TOTAL_BASE_IDX + regOTGid_OTG_V_TOTAL, .OTG_V_BLANK_START_END = DCN_BASE__INST0_SEGregOTGid_OTG_V_BLANK_START_END_BASE_IDX + regOTGid_OTG_V_BLANK_START_END, .OTG_V_SYNC_A = DCN_BASE__INST0_SEGregOTGid_OTG_V_SYNC_A_BASE_IDX + regOTGid_OTG_V_SYNC_A, .OTG_V_SYNC_A_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX + regOTGid_OTG_V_SYNC_A_CNTL, .OTG_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CONTROL_BASE_IDX + regOTGid_OTG_CONTROL, .OTG_STEREO_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_STEREO_CONTROL_BASE_IDX + regOTGid_OTG_STEREO_CONTROL, .OTG_3D_STRUCTURE_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX + regOTGid_OTG_3D_STRUCTURE_CONTROL, .OTG_STEREO_STATUS = DCN_BASE__INST0_SEGregOTGid_OTG_STEREO_STATUS_BASE_IDX + regOTGid_OTG_STEREO_STATUS, .OTG_V_TOTAL_MAX = DCN_BASE__INST0_SEGregOTGid_OTG_V_TOTAL_MAX_BASE_IDX + regOTGid_OTG_V_TOTAL_MAX, .OTG_V_TOTAL_MIN = DCN_BASE__INST0_SEGregOTGid_OTG_V_TOTAL_MIN_BASE_IDX + regOTGid_OTG_V_TOTAL_MIN, .OTG_V_TOTAL_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX + regOTGid_OTG_V_TOTAL_CONTROL, .OTG_TRIGA_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_TRIGA_CNTL_BASE_IDX + regOTGid_OTG_TRIGA_CNTL, .OTG_FORCE_COUNT_NOW_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX + regOTGid_OTG_FORCE_COUNT_NOW_CNTL, .OTG_STATIC_SCREEN_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX + regOTGid_OTG_STATIC_SCREEN_CONTROL, .OTG_STATUS_FRAME_COUNT = DCN_BASE__INST0_SEGregOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX + regOTGid_OTG_STATUS_FRAME_COUNT, .OTG_STATUS = DCN_BASE__INST0_SEGregOTGid_OTG_STATUS_BASE_IDX + regOTGid_OTG_STATUS, .OTG_STATUS_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_STATUS_POSITION_BASE_IDX + regOTGid_OTG_STATUS_POSITION, .OTG_NOM_VERT_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_NOM_VERT_POSITION_BASE_IDX + regOTGid_OTG_NOM_VERT_POSITION, .OTG_M_CONST_DTO0 = DCN_BASE__INST0_SEGregOTGid_OTG_M_CONST_DTO0_BASE_IDX + regOTGid_OTG_M_CONST_DTO0, .OTG_M_CONST_DTO1 = DCN_BASE__INST0_SEGregOTGid_OTG_M_CONST_DTO1_BASE_IDX + regOTGid_OTG_M_CONST_DTO1, .OTG_CLOCK_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CLOCK_CONTROL_BASE_IDX + regOTGid_OTG_CLOCK_CONTROL, .OTG_VERTICAL_INTERRUPT0_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, .OTG_VERTICAL_INTERRUPT0_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, .OTG_VERTICAL_INTERRUPT1_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, .OTG_VERTICAL_INTERRUPT1_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, .OTG_VERTICAL_INTERRUPT2_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, .OTG_VERTICAL_INTERRUPT2_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX + regOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, .OPTC_INPUT_CLOCK_CONTROL = DCN_BASE__INST0_SEGregODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX + regODMid_OPTC_INPUT_CLOCK_CONTROL, .OPTC_DATA_SOURCE_SELECT = DCN_BASE__INST0_SEGregODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX + regODMid_OPTC_DATA_SOURCE_SELECT, .OPTC_INPUT_GLOBAL_CONTROL = DCN_BASE__INST0_SEGregODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX + regODMid_OPTC_INPUT_GLOBAL_CONTROL, .CONTROL = DCN_BASE__INST0_SEGregVTGid_CONTROL_BASE_IDX + regVTGid_CONTROL, .OTG_VERT_SYNC_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX + regOTGid_OTG_VERT_SYNC_CONTROL, .OTG_GSL_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_GSL_CONTROL_BASE_IDX + regOTGid_OTG_GSL_CONTROL, .OTG_CRC_CNTL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC_CNTL_BASE_IDX + regOTGid_OTG_CRC_CNTL, .OTG_CRC0_DATA_RG = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_DATA_RG_BASE_IDX + regOTGid_OTG_CRC0_DATA_RG, .OTG_CRC0_DATA_B = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_DATA_B_BASE_IDX + regOTGid_OTG_CRC0_DATA_B, .OTG_CRC0_WINDOWA_X_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX + regOTGid_OTG_CRC0_WINDOWA_X_CONTROL, .OTG_CRC0_WINDOWA_Y_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX + regOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, .OTG_CRC0_WINDOWB_X_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX + regOTGid_OTG_CRC0_WINDOWB_X_CONTROL, .OTG_CRC0_WINDOWB_Y_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX + regOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = DCN_BASE__INST0_SEGregOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX + regOTGid_OTG_TRIGA_MANUAL_TRIG, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGregOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX + regOTGid_OTG_GLOBAL_CONTROL2, .OTG_GSL_WINDOW_X = DCN_BASE__INST0_SEGregOTGid_OTG_GSL_WINDOW_X_BASE_IDX + regOTGid_OTG_GSL_WINDOW_X, .OTG_GSL_WINDOW_Y = DCN_BASE__INST0_SEGregOTGid_OTG_GSL_WINDOW_Y_BASE_IDX + regOTGid_OTG_GSL_WINDOW_Y, .OTG_VUPDATE_KEEPOUT = DCN_BASE__INST0_SEGregOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX + regOTGid_OTG_VUPDATE_KEEPOUT, .OTG_DSC_START_POSITION = DCN_BASE__INST0_SEGregOTGid_OTG_DSC_START_POSITION_BASE_IDX + regOTGid_OTG_DSC_START_POSITION, .OTG_DRR_TRIGGER_WINDOW = DCN_BASE__INST0_SEGregOTGid_OTG_DRR_TRIGGER_WINDOW_BASE_IDX + regOTGid_OTG_DRR_TRIGGER_WINDOW, .OTG_DRR_V_TOTAL_CHANGE = DCN_BASE__INST0_SEGregOTGid_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX + regOTGid_OTG_DRR_V_TOTAL_CHANGE, .OPTC_DATA_FORMAT_CONTROL = DCN_BASE__INST0_SEGregODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX + regODMid_OPTC_DATA_FORMAT_CONTROL, .OPTC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGregODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX + regODMid_OPTC_BYTES_PER_PIXEL , .OPTC_WIDTH_CONTROL = DCN_BASE__INST0_SEGregODMid_OPTC_WIDTH_CONTROL_BASE_IDX + regODMid_OPTC_WIDTH_CONTROL, .OPTC_MEMORY_CONFIG = DCN_BASE__INST0_SEGregODMid_OPTC_MEMORY_CONFIG_BASE_IDX + regODMid_OPTC_MEMORY_CONFIG, .OTG_CRC_CNTL2 = DCN_BASE__INST0_SEGregOTGid_OTG_CRC_CNTL2_BASE_IDX + regOTGid_OTG_CRC_CNTL2, .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a , .OTG_DRR_CONTROL = DCN_BASE__INST0_SEGregOTGid_OTG_DRR_CONTROL_BASE_IDX + regOTGid_OTG_DRR_CONTROL} | ||||
| 608 | |||||
| 609 | static const struct dcn_optc_registers optc_regs[] = { | ||||
| 610 | optc_regs(0)[0] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1b87, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1b88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1b89 , .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1b8b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1b90, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1b91 , .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1b92, .OTG_GLOBAL_CONTROL4 = 0x000034C0 + 0x1b94, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1b5b, .OTG_H_TOTAL = 0x000034C0 + 0x1b2a, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1b2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1b2c, . OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1b2d, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1b2e, .OTG_V_TOTAL = 0x000034C0 + 0x1b2f, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1b36, .OTG_V_SYNC_A = 0x000034C0 + 0x1b37, . OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1b38, .OTG_CONTROL = 0x000034C0 + 0x1b41, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1b54, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1b83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1b53 , .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1b31, .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1b30, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1b33, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1b39, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1b3d, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1b82, . OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1b4c, .OTG_STATUS = 0x000034C0 + 0x1b49, .OTG_STATUS_POSITION = 0x000034C0 + 0x1b4a, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1b4b, .OTG_M_CONST_DTO0 = 0x000034C0 + 0x1b9c , .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1b9d, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1b86, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1b63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1b62 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1b65, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1b64, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1b67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1b66 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1acf, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1acb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1aca, .CONTROL = 0x000034C0 + 0x052d, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1b52, .OTG_GSL_CONTROL = 0x000034C0 + 0x1b8c , .OTG_CRC_CNTL = 0x000034C0 + 0x1b68, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1b6e, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1b6f, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1b6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1b6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1b6c, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1b6d, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1b3a, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1b91, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1b92, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1b8d , .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1b8e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1b8f, .OTG_DSC_START_POSITION = 0x000034C0 + 0x1b9f, .OTG_DRR_TRIGGER_WINDOW = 0x000034C0 + 0x1b9a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 + 0x1b99, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1acc, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1acd, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1ace, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1ad0 , .OTG_CRC_CNTL2 = 0x000034C0 + 0x1b69, .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_DRR_CONTROL = 0x000034C0 + 0x1b9b}, | ||||
| 611 | optc_regs(1)[1] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1c07, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1c08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1c09 , .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1c0b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1c10, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c11 , .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c12, .OTG_GLOBAL_CONTROL4 = 0x000034C0 + 0x1c14, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1bdb, .OTG_H_TOTAL = 0x000034C0 + 0x1baa, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1bab, .OTG_H_SYNC_A = 0x000034C0 + 0x1bac, . OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1bad, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1bae, .OTG_V_TOTAL = 0x000034C0 + 0x1baf, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1bb6, .OTG_V_SYNC_A = 0x000034C0 + 0x1bb7, . OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1bb8, .OTG_CONTROL = 0x000034C0 + 0x1bc1, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1bd4, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1c03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1bd3 , .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1bb1, .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1bb0, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1bb3, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1bb9, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1bbd, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1c02, . OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1bcc, .OTG_STATUS = 0x000034C0 + 0x1bc9, .OTG_STATUS_POSITION = 0x000034C0 + 0x1bca, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1bcb, .OTG_M_CONST_DTO0 = 0x000034C0 + 0x1c1c , .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1c1d, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1c06, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1be3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1be2 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1be5, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1be4, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1be7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1be6 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1adf, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1adb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1ada, .CONTROL = 0x000034C0 + 0x052e, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1bd2, .OTG_GSL_CONTROL = 0x000034C0 + 0x1c0c , .OTG_CRC_CNTL = 0x000034C0 + 0x1be8, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1bee, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1bef, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1bea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1beb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1bec, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1bed, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1bba, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c11, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c12, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1c0d , .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1c0e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1c0f, .OTG_DSC_START_POSITION = 0x000034C0 + 0x1c1f, .OTG_DRR_TRIGGER_WINDOW = 0x000034C0 + 0x1c1a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 + 0x1c19, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1adc, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1add, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1ade, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1ae0 , .OTG_CRC_CNTL2 = 0x000034C0 + 0x1be9, .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_DRR_CONTROL = 0x000034C0 + 0x1c1b}, | ||||
| 612 | optc_regs(2)[2] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1c87, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1c88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1c89 , .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1c8b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1c90, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c91 , .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c92, .OTG_GLOBAL_CONTROL4 = 0x000034C0 + 0x1c94, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1c5b, .OTG_H_TOTAL = 0x000034C0 + 0x1c2a, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1c2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1c2c, . OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1c2d, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1c2e, .OTG_V_TOTAL = 0x000034C0 + 0x1c2f, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1c36, .OTG_V_SYNC_A = 0x000034C0 + 0x1c37, . OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1c38, .OTG_CONTROL = 0x000034C0 + 0x1c41, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1c54, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1c83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1c53 , .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1c31, .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1c30, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1c33, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1c39, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1c3d, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1c82, . OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1c4c, .OTG_STATUS = 0x000034C0 + 0x1c49, .OTG_STATUS_POSITION = 0x000034C0 + 0x1c4a, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1c4b, .OTG_M_CONST_DTO0 = 0x000034C0 + 0x1c9c , .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1c9d, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1c86, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1c63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1c62 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1c65, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1c64, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1c67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1c66 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1aef, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1aeb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1aea, .CONTROL = 0x000034C0 + 0x052f, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1c52, .OTG_GSL_CONTROL = 0x000034C0 + 0x1c8c , .OTG_CRC_CNTL = 0x000034C0 + 0x1c68, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1c6e, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1c6f, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1c6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1c6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1c6c, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1c6d, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1c3a, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c91, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c92, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1c8d , .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1c8e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1c8f, .OTG_DSC_START_POSITION = 0x000034C0 + 0x1c9f, .OTG_DRR_TRIGGER_WINDOW = 0x000034C0 + 0x1c9a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 + 0x1c99, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1aec, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1aed, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1aee, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1af0 , .OTG_CRC_CNTL2 = 0x000034C0 + 0x1c69, .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_DRR_CONTROL = 0x000034C0 + 0x1c9b}, | ||||
| 613 | optc_regs(3)[3] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1d07, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1d08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1d09 , .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1d0b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1d10, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1d11 , .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1d12, .OTG_GLOBAL_CONTROL4 = 0x000034C0 + 0x1d14, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1cdb, .OTG_H_TOTAL = 0x000034C0 + 0x1caa, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1cab, .OTG_H_SYNC_A = 0x000034C0 + 0x1cac, . OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1cad, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1cae, .OTG_V_TOTAL = 0x000034C0 + 0x1caf, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1cb6, .OTG_V_SYNC_A = 0x000034C0 + 0x1cb7, . OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1cb8, .OTG_CONTROL = 0x000034C0 + 0x1cc1, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1cd4, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1d03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1cd3 , .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1cb1, .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1cb0, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1cb3, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1cb9, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1cbd, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1d02, . OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1ccc, .OTG_STATUS = 0x000034C0 + 0x1cc9, .OTG_STATUS_POSITION = 0x000034C0 + 0x1cca, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1ccb, .OTG_M_CONST_DTO0 = 0x000034C0 + 0x1d1c , .OTG_M_CONST_DTO1 = 0x000034C0 + 0x1d1d, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1d06, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1ce3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1ce2 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1ce5, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1ce4, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1ce7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1ce6 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1aff, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1afb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1afa, .CONTROL = 0x000034C0 + 0x0530, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1cd2, .OTG_GSL_CONTROL = 0x000034C0 + 0x1d0c , .OTG_CRC_CNTL = 0x000034C0 + 0x1ce8, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1cee, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1cef, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1cea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1ceb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1cec, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1ced, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1cba, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1d11, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1d12, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1d0d , .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1d0e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1d0f, .OTG_DSC_START_POSITION = 0x000034C0 + 0x1d1f, .OTG_DRR_TRIGGER_WINDOW = 0x000034C0 + 0x1d1a, .OTG_DRR_V_TOTAL_CHANGE = 0x000034C0 + 0x1d19, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1afc, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1afd, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1afe, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1b00 , .OTG_CRC_CNTL2 = 0x000034C0 + 0x1ce9, .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_DRR_CONTROL = 0x000034C0 + 0x1d1b} | ||||
| 614 | }; | ||||
| 615 | |||||
| 616 | static const struct dcn_optc_shift optc_shift = { | ||||
| 617 | OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT).VSTARTUP_START = 0x0, .VUPDATE_OFFSET = 0x0, .VUPDATE_WIDTH = 0x10, .VREADY_OFFSET = 0x0, .OTG_MASTER_UPDATE_LOCK = 0x0, . UPDATE_LOCK_STATUS = 0x8, .MASTER_UPDATE_LOCK_DB_START_X = 0x0 , .MASTER_UPDATE_LOCK_DB_END_X = 0x10, .MASTER_UPDATE_LOCK_DB_EN = 0x1f, .MASTER_UPDATE_LOCK_DB_START_Y = 0x0, .MASTER_UPDATE_LOCK_DB_END_Y = 0x10, .OTG_MASTER_UPDATE_LOCK_SEL = 0x19, .DIG_UPDATE_POSITION_X = 0x0, .DIG_UPDATE_POSITION_Y = 0x10, .OTG_UPDATE_PENDING = 0x0 , .OTG_H_TOTAL = 0x0, .OTG_H_BLANK_START = 0x0, .OTG_H_BLANK_END = 0x10, .OTG_H_SYNC_A_START = 0x0, .OTG_H_SYNC_A_END = 0x10, .OTG_H_SYNC_A_POL = 0x0, .OTG_V_TOTAL = 0x0, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END = 0x10, .OTG_V_SYNC_A_START = 0x0, . OTG_V_SYNC_A_END = 0x10, .OTG_V_SYNC_A_POL = 0x0, .OTG_V_SYNC_MODE = 0x8, .OTG_MASTER_EN = 0x0, .OTG_START_POINT_CNTL = 0xc, .OTG_DISABLE_POINT_CNTL = 0x8, .OTG_FIELD_NUMBER_CNTL = 0xd, .OTG_OUT_MUX = 0x14, .OTG_STEREO_EN = 0x18, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM = 0x0, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0xf, .OTG_STEREO_EYE_FLAG_POLARITY = 0x11, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x12, .OTG_STEREO_CURRENT_EYE = 0x0, .OTG_3D_STRUCTURE_EN = 0x0, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x8, .OTG_3D_STRUCTURE_STEREO_SEL_OVR = 0xc, .OTG_V_TOTAL_MAX = 0x0, .OTG_V_TOTAL_MIN = 0x0, .OTG_V_TOTAL_MIN_SEL = 0x0, .OTG_V_TOTAL_MAX_SEL = 0x1, .OTG_FORCE_LOCK_ON_EVENT = 0x4, .OTG_SET_V_TOTAL_MIN_MASK = 0x10, .OTG_VTOTAL_MID_REPLACING_MIN_EN = 0x3, .OTG_VTOTAL_MID_REPLACING_MAX_EN = 0x2, .OTG_FORCE_COUNT_NOW_CLEAR = 0x18, .OTG_FORCE_COUNT_NOW_MODE = 0x0, .OTG_FORCE_COUNT_NOW_OCCURRED = 0x10, .OTG_TRIGA_SOURCE_SELECT = 0x0, .OTG_TRIGA_SOURCE_PIPE_SELECT = 0x5, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x10, .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x12, .OTG_TRIGA_POLARITY_SELECT = 0x8, .OTG_TRIGA_FREQUENCY_SELECT = 0x14, .OTG_TRIGA_DELAY = 0x18, .OTG_TRIGA_CLEAR = 0x1f, .OTG_STATIC_SCREEN_EVENT_MASK = 0x0, .OTG_STATIC_SCREEN_FRAME_COUNT = 0x10, .OTG_FRAME_COUNT = 0x0, .OTG_V_BLANK = 0x0, .OTG_V_ACTIVE_DISP = 0x1, .OTG_HORZ_COUNT = 0x10, .OTG_VERT_COUNT = 0x0, .OTG_VERT_COUNT_NOM = 0x0, .OTG_M_CONST_DTO_PHASE = 0x0, .OTG_M_CONST_DTO_MODULO = 0x0, .OTG_BUSY = 0x10, .OTG_CLOCK_EN = 0x0, .OTG_CLOCK_ON = 0x8, .OTG_CLOCK_GATE_DIS = 0x1, .OTG_VERTICAL_INTERRUPT0_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT0_LINE_START = 0x0, .OTG_VERTICAL_INTERRUPT0_LINE_END = 0x10, .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT1_LINE_START = 0x0, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT2_LINE_START = 0x0, .OPTC_INPUT_CLK_EN = 0x1, .OPTC_INPUT_CLK_ON = 0x2, . OPTC_INPUT_CLK_GATE_DIS = 0x0, .OPTC_UNDERFLOW_OCCURRED_STATUS = 0xa, .OPTC_UNDERFLOW_CLEAR = 0xc, .VTG0_ENABLE = 0x1f, .VTG0_FP2 = 0x0, .VTG0_VCOUNT_INIT = 0x10, .OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED = 0x0, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = 0x8, .OTG_AUTO_FORCE_VSYNC_MODE = 0x10, .OTG_GSL0_EN = 0x0, .OTG_GSL1_EN = 0x1, .OTG_GSL2_EN = 0x2, .OTG_GSL_MASTER_EN = 0x3, .OTG_GSL_FORCE_DELAY = 0x10 , .OTG_GSL_CHECK_ALL_FIELDS = 0x1c, .OTG_CRC_CONT_EN = 0x4, . OTG_CRC0_SELECT = 0x14, .OTG_CRC_EN = 0x0, .CRC0_R_CR = 0x0, . CRC0_G_Y = 0x10, .CRC0_B_CB = 0x0, .OTG_CRC0_WINDOWA_X_START = 0x0, .OTG_CRC0_WINDOWA_X_END = 0x10, .OTG_CRC0_WINDOWA_Y_START = 0x0, .OTG_CRC0_WINDOWA_Y_END = 0x10, .OTG_CRC0_WINDOWB_X_START = 0x0, .OTG_CRC0_WINDOWB_X_END = 0x10, .OTG_CRC0_WINDOWB_Y_START = 0x0, .OTG_CRC0_WINDOWB_Y_END = 0x10, .OTG_TRIGA_MANUAL_TRIG = 0x0, .GSL0_READY_SOURCE_SEL = 0x0, .GSL1_READY_SOURCE_SEL = 0x4, .GSL2_READY_SOURCE_SEL = 0x8, .MANUAL_FLOW_CONTROL_SEL = 0x10, .GLOBAL_UPDATE_LOCK_EN = 0xa, .OTG_GSL_WINDOW_START_X = 0x0, .OTG_GSL_WINDOW_END_X = 0x10, .OTG_GSL_WINDOW_START_Y = 0x0, .OTG_GSL_WINDOW_END_Y = 0x10, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x1f, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0 , .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x10, .OTG_GSL_MASTER_MODE = 0x4, .OTG_MASTER_UPDATE_LOCK_GSL_EN = 0x1f, .OTG_DSC_START_POSITION_X = 0x0, .OTG_DSC_START_POSITION_LINE_NUM = 0x10, .OPTC_SEG0_SRC_SEL = 0x10, .OPTC_SEG1_SRC_SEL = 0x14, .OPTC_SEG2_SRC_SEL = 0x18 , .OPTC_SEG3_SRC_SEL = 0x1c, .OPTC_NUM_OF_INPUT_SEGMENT = 0x0 , .OPTC_MEM_SEL = 0x0, .OPTC_DATA_FORMAT = 0x0, .OPTC_DSC_MODE = 0x4, .OPTC_DSC_BYTES_PER_PIXEL = 0x0, .OPTC_DSC_SLICE_WIDTH = 0x10, .OPTC_SEGMENT_WIDTH = 0x0, .OPTC_DWB0_SOURCE_SELECT = 0x0, .OPTC_DWB1_SOURCE_SELECT = 0x3, .OTG_DRR_TRIGGER_WINDOW_START_X = 0x0, .OTG_DRR_TRIGGER_WINDOW_END_X = 0x10, .OTG_DRR_V_TOTAL_CHANGE_LIMIT = 0x0, .OTG_H_TIMING_DIV_MODE = 0x0, .OTG_DRR_TIMING_DBUF_UPDATE_MODE = 0x18, .OTG_CRC_DSC_MODE = 0x0, .OTG_CRC_DATA_STREAM_COMBINE_MODE = 0x1, .OTG_CRC_DATA_STREAM_SPLIT_MODE = 0x4, .OTG_CRC_DATA_FORMAT = 0x8, .OTG_V_TOTAL_LAST_USED_BY_DRR = 0x10 | ||||
| 618 | }; | ||||
| 619 | |||||
| 620 | static const struct dcn_optc_mask optc_mask = { | ||||
| 621 | OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK).VSTARTUP_START = 0x000003FFL, .VUPDATE_OFFSET = 0x0000FFFFL, .VUPDATE_WIDTH = 0x03FF0000L, .VREADY_OFFSET = 0x0000FFFFL, . OTG_MASTER_UPDATE_LOCK = 0x00000001L, .UPDATE_LOCK_STATUS = 0x00000100L , .MASTER_UPDATE_LOCK_DB_START_X = 0x00007FFFL, .MASTER_UPDATE_LOCK_DB_END_X = 0x7FFF0000L, .MASTER_UPDATE_LOCK_DB_EN = 0x80000000L, .MASTER_UPDATE_LOCK_DB_START_Y = 0x00007FFFL, .MASTER_UPDATE_LOCK_DB_END_Y = 0x7FFF0000L, . OTG_MASTER_UPDATE_LOCK_SEL = 0x0E000000L, .DIG_UPDATE_POSITION_X = 0x00007FFFL, .DIG_UPDATE_POSITION_Y = 0x7FFF0000L, .OTG_UPDATE_PENDING = 0x00000001L, .OTG_H_TOTAL = 0x00007FFFL, .OTG_H_BLANK_START = 0x00007FFFL, .OTG_H_BLANK_END = 0x7FFF0000L, .OTG_H_SYNC_A_START = 0x00007FFFL, .OTG_H_SYNC_A_END = 0x7FFF0000L, .OTG_H_SYNC_A_POL = 0x00000001L, .OTG_V_TOTAL = 0x00007FFFL, .OTG_V_BLANK_START = 0x00007FFFL, .OTG_V_BLANK_END = 0x7FFF0000L, .OTG_V_SYNC_A_START = 0x00007FFFL, .OTG_V_SYNC_A_END = 0x7FFF0000L, .OTG_V_SYNC_A_POL = 0x00000001L, .OTG_V_SYNC_MODE = 0x00000100L, .OTG_MASTER_EN = 0x00000001L, .OTG_START_POINT_CNTL = 0x00001000L, .OTG_DISABLE_POINT_CNTL = 0x00000300L, .OTG_FIELD_NUMBER_CNTL = 0x00002000L, .OTG_OUT_MUX = 0x00300000L, .OTG_STEREO_EN = 0x01000000L, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM = 0x00007FFFL, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0x00008000L , .OTG_STEREO_EYE_FLAG_POLARITY = 0x00020000L, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x00040000L, .OTG_STEREO_CURRENT_EYE = 0x00000001L, .OTG_3D_STRUCTURE_EN = 0x00000001L, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x00000300L , .OTG_3D_STRUCTURE_STEREO_SEL_OVR = 0x00001000L, .OTG_V_TOTAL_MAX = 0x00007FFFL, .OTG_V_TOTAL_MIN = 0x00007FFFL, .OTG_V_TOTAL_MIN_SEL = 0x00000001L, .OTG_V_TOTAL_MAX_SEL = 0x00000002L, .OTG_FORCE_LOCK_ON_EVENT = 0x00000010L, .OTG_SET_V_TOTAL_MIN_MASK = 0xFFFF0000L, .OTG_VTOTAL_MID_REPLACING_MIN_EN = 0x00000008L, .OTG_VTOTAL_MID_REPLACING_MAX_EN = 0x00000004L , .OTG_FORCE_COUNT_NOW_CLEAR = 0x01000000L, .OTG_FORCE_COUNT_NOW_MODE = 0x00000003L, .OTG_FORCE_COUNT_NOW_OCCURRED = 0x00010000L, . OTG_TRIGA_SOURCE_SELECT = 0x0000001FL, .OTG_TRIGA_SOURCE_PIPE_SELECT = 0x000000E0L, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x00030000L , .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x000C0000L, .OTG_TRIGA_POLARITY_SELECT = 0x00000700L, .OTG_TRIGA_FREQUENCY_SELECT = 0x00300000L, .OTG_TRIGA_DELAY = 0x1F000000L, .OTG_TRIGA_CLEAR = 0x80000000L, .OTG_STATIC_SCREEN_EVENT_MASK = 0x0000FFFFL, .OTG_STATIC_SCREEN_FRAME_COUNT = 0x00FF0000L, .OTG_FRAME_COUNT = 0x00FFFFFFL, .OTG_V_BLANK = 0x00000001L, . OTG_V_ACTIVE_DISP = 0x00000002L, .OTG_HORZ_COUNT = 0x7FFF0000L , .OTG_VERT_COUNT = 0x00007FFFL, .OTG_VERT_COUNT_NOM = 0x00007FFFL , .OTG_M_CONST_DTO_PHASE = 0xFFFFFFFFL, .OTG_M_CONST_DTO_MODULO = 0xFFFFFFFFL, .OTG_BUSY = 0x00010000L, .OTG_CLOCK_EN = 0x00000001L , .OTG_CLOCK_ON = 0x00000100L, .OTG_CLOCK_GATE_DIS = 0x00000002L , .OTG_VERTICAL_INTERRUPT0_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT0_LINE_START = 0x00007FFFL, .OTG_VERTICAL_INTERRUPT0_LINE_END = 0x7FFF0000L , .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT1_LINE_START = 0x00007FFFL, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x00000100L , .OTG_VERTICAL_INTERRUPT2_LINE_START = 0x00007FFFL, .OPTC_INPUT_CLK_EN = 0x00000002L, .OPTC_INPUT_CLK_ON = 0x00000004L, .OPTC_INPUT_CLK_GATE_DIS = 0x00000001L, .OPTC_UNDERFLOW_OCCURRED_STATUS = 0x00000400L , .OPTC_UNDERFLOW_CLEAR = 0x00001000L, .VTG0_ENABLE = 0x80000000L , .VTG0_FP2 = 0x00007FFFL, .VTG0_VCOUNT_INIT = 0x7FFF0000L, . OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED = 0x00000001L, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = 0x00000100L, .OTG_AUTO_FORCE_VSYNC_MODE = 0x00030000L, .OTG_GSL0_EN = 0x00000001L, .OTG_GSL1_EN = 0x00000002L, .OTG_GSL2_EN = 0x00000004L , .OTG_GSL_MASTER_EN = 0x00000008L, .OTG_GSL_FORCE_DELAY = 0x001F0000L , .OTG_GSL_CHECK_ALL_FIELDS = 0x10000000L, .OTG_CRC_CONT_EN = 0x00000010L, .OTG_CRC0_SELECT = 0x00700000L, .OTG_CRC_EN = 0x00000001L , .CRC0_R_CR = 0x0000FFFFL, .CRC0_G_Y = 0xFFFF0000L, .CRC0_B_CB = 0x0000FFFFL, .OTG_CRC0_WINDOWA_X_START = 0x00007FFFL, .OTG_CRC0_WINDOWA_X_END = 0x7FFF0000L, .OTG_CRC0_WINDOWA_Y_START = 0x00007FFFL, .OTG_CRC0_WINDOWA_Y_END = 0x7FFF0000L, .OTG_CRC0_WINDOWB_X_START = 0x00007FFFL, .OTG_CRC0_WINDOWB_X_END = 0x7FFF0000L, .OTG_CRC0_WINDOWB_Y_START = 0x00007FFFL, .OTG_CRC0_WINDOWB_Y_END = 0x7FFF0000L, .OTG_TRIGA_MANUAL_TRIG = 0x00000001L, .GSL0_READY_SOURCE_SEL = 0x00000007L, .GSL1_READY_SOURCE_SEL = 0x00000070L, .GSL2_READY_SOURCE_SEL = 0x00000700L, .MANUAL_FLOW_CONTROL_SEL = 0x00070000L, .GLOBAL_UPDATE_LOCK_EN = 0x00000400L, .OTG_GSL_WINDOW_START_X = 0x00007FFFL, .OTG_GSL_WINDOW_END_X = 0x7FFF0000L, .OTG_GSL_WINDOW_START_Y = 0x00007FFFL, .OTG_GSL_WINDOW_END_Y = 0x7FFF0000L, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x80000000L , .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0000FFFFL , .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x03FF0000L , .OTG_GSL_MASTER_MODE = 0x00000030L, .OTG_MASTER_UPDATE_LOCK_GSL_EN = 0x80000000L, .OTG_DSC_START_POSITION_X = 0x00007FFFL, .OTG_DSC_START_POSITION_LINE_NUM = 0x03FF0000L, .OPTC_SEG0_SRC_SEL = 0x000F0000L, .OPTC_SEG1_SRC_SEL = 0x00F00000L, .OPTC_SEG2_SRC_SEL = 0x0F000000L, .OPTC_SEG3_SRC_SEL = 0xF0000000L, .OPTC_NUM_OF_INPUT_SEGMENT = 0x00000003L, .OPTC_MEM_SEL = 0x0000FFFFL, .OPTC_DATA_FORMAT = 0x00000003L, .OPTC_DSC_MODE = 0x00000030L, .OPTC_DSC_BYTES_PER_PIXEL = 0x7FFFFFFFL, .OPTC_DSC_SLICE_WIDTH = 0x1FFF0000L, .OPTC_SEGMENT_WIDTH = 0x00001FFFL, .OPTC_DWB0_SOURCE_SELECT = 0x00000007L, .OPTC_DWB1_SOURCE_SELECT = 0x00000038L, .OTG_DRR_TRIGGER_WINDOW_START_X = 0x00007FFFL, .OTG_DRR_TRIGGER_WINDOW_END_X = 0x7FFF0000L, . OTG_DRR_V_TOTAL_CHANGE_LIMIT = 0x00007FFFL, .OTG_H_TIMING_DIV_MODE = 0x00000003L, .OTG_DRR_TIMING_DBUF_UPDATE_MODE = 0x03000000L , .OTG_CRC_DSC_MODE = 0x00000001L, .OTG_CRC_DATA_STREAM_COMBINE_MODE = 0x00000002L, .OTG_CRC_DATA_STREAM_SPLIT_MODE = 0x00000030L , .OTG_CRC_DATA_FORMAT = 0x00000300L, .OTG_V_TOTAL_LAST_USED_BY_DRR = 0x7FFF0000L | ||||
| 622 | }; | ||||
| 623 | |||||
| 624 | #define hubp_regs(id)[id] = { .DCHUBP_CNTL = DCN_BASE__INST0_SEGregHUBPid_DCHUBP_CNTL_BASE_IDX + regHUBPid_DCHUBP_CNTL, .HUBPREQ_DEBUG_DB = DCN_BASE__INST0_SEGregHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX + regHUBPid_HUBPREQ_DEBUG_DB, .HUBPREQ_DEBUG = DCN_BASE__INST0_SEGregHUBPid_HUBPREQ_DEBUG_BASE_IDX + regHUBPid_HUBPREQ_DEBUG, .DCSURF_ADDR_CONFIG = DCN_BASE__INST0_SEGregHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX + regHUBPid_DCSURF_ADDR_CONFIG, .DCSURF_TILING_CONFIG = DCN_BASE__INST0_SEGregHUBPid_DCSURF_TILING_CONFIG_BASE_IDX + regHUBPid_DCSURF_TILING_CONFIG, .DCSURF_SURFACE_PITCH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_PITCH, .DCSURF_SURFACE_PITCH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_PITCH_C, .DCSURF_SURFACE_CONFIG = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX + regHUBPid_DCSURF_SURFACE_CONFIG, .DCSURF_FLIP_CONTROL = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX + regHUBPREQid_DCSURF_FLIP_CONTROL, .DCSURF_PRI_VIEWPORT_DIMENSION = DCN_BASE__INST0_SEGregHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX + regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION, .DCSURF_PRI_VIEWPORT_START = DCN_BASE__INST0_SEGregHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX + regHUBPid_DCSURF_PRI_VIEWPORT_START, .DCSURF_SEC_VIEWPORT_DIMENSION = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX + regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION, .DCSURF_SEC_VIEWPORT_START = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX + regHUBPid_DCSURF_SEC_VIEWPORT_START, .DCSURF_PRI_VIEWPORT_DIMENSION_C = DCN_BASE__INST0_SEGregHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX + regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C, .DCSURF_PRI_VIEWPORT_START_C = DCN_BASE__INST0_SEGregHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX + regHUBPid_DCSURF_PRI_VIEWPORT_START_C, .DCSURF_SEC_VIEWPORT_DIMENSION_C = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX + regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C, .DCSURF_SEC_VIEWPORT_START_C = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX + regHUBPid_DCSURF_SEC_VIEWPORT_START_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, . DCSURF_SECONDARY_META_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, .DCSURF_SURFACE_INUSE = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_INUSE, .DCSURF_SURFACE_INUSE_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, .DCSURF_SURFACE_INUSE_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_INUSE_C, .DCSURF_SURFACE_INUSE_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, .DCSURF_SURFACE_EARLIEST_INUSE = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, .DCSURF_SURFACE_EARLIEST_INUSE_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, .DCSURF_SURFACE_CONTROL = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_CONTROL, .DCSURF_SURFACE_FLIP_INTERRUPT = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT, .HUBPRET_CONTROL = DCN_BASE__INST0_SEGregHUBPRETid_HUBPRET_CONTROL_BASE_IDX + regHUBPRETid_HUBPRET_CONTROL, .HUBPRET_READ_LINE_STATUS = DCN_BASE__INST0_SEGregHUBPRETid_HUBPRET_READ_LINE_STATUS_BASE_IDX + regHUBPRETid_HUBPRET_READ_LINE_STATUS, .DCN_EXPANSION_MODE = DCN_BASE__INST0_SEGregHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX + regHUBPREQid_DCN_EXPANSION_MODE, .DCHUBP_REQ_SIZE_CONFIG = DCN_BASE__INST0_SEGregHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX + regHUBPid_DCHUBP_REQ_SIZE_CONFIG, .DCHUBP_REQ_SIZE_CONFIG_C = DCN_BASE__INST0_SEGregHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX + regHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, .BLANK_OFFSET_0 = DCN_BASE__INST0_SEGregHUBPREQid_BLANK_OFFSET_0_BASE_IDX + regHUBPREQid_BLANK_OFFSET_0, .BLANK_OFFSET_1 = DCN_BASE__INST0_SEGregHUBPREQid_BLANK_OFFSET_1_BASE_IDX + regHUBPREQid_BLANK_OFFSET_1, .DST_DIMENSIONS = DCN_BASE__INST0_SEGregHUBPREQid_DST_DIMENSIONS_BASE_IDX + regHUBPREQid_DST_DIMENSIONS, .DST_AFTER_SCALER = DCN_BASE__INST0_SEGregHUBPREQid_DST_AFTER_SCALER_BASE_IDX + regHUBPREQid_DST_AFTER_SCALER, .VBLANK_PARAMETERS_0 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_0, .REF_FREQ_TO_PIX_FREQ = DCN_BASE__INST0_SEGregHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX + regHUBPREQid_REF_FREQ_TO_PIX_FREQ, .VBLANK_PARAMETERS_1 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_1, .VBLANK_PARAMETERS_3 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_3, .NOM_PARAMETERS_4 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_4_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_4, .NOM_PARAMETERS_5 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_5_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_5, .PER_LINE_DELIVERY_PRE = DCN_BASE__INST0_SEGregHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX + regHUBPREQid_PER_LINE_DELIVERY_PRE, .PER_LINE_DELIVERY = DCN_BASE__INST0_SEGregHUBPREQid_PER_LINE_DELIVERY_BASE_IDX + regHUBPREQid_PER_LINE_DELIVERY, .VBLANK_PARAMETERS_2 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_2, .VBLANK_PARAMETERS_4 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_4, .NOM_PARAMETERS_6 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_6_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_6, .NOM_PARAMETERS_7 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_7_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_7, .DCN_TTU_QOS_WM = DCN_BASE__INST0_SEGregHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX + regHUBPREQid_DCN_TTU_QOS_WM, .DCN_GLOBAL_TTU_CNTL = DCN_BASE__INST0_SEGregHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX + regHUBPREQid_DCN_GLOBAL_TTU_CNTL, .DCN_SURF0_TTU_CNTL0 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX + regHUBPREQid_DCN_SURF0_TTU_CNTL0, .DCN_SURF0_TTU_CNTL1 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX + regHUBPREQid_DCN_SURF0_TTU_CNTL1, .DCN_SURF1_TTU_CNTL0 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX + regHUBPREQid_DCN_SURF1_TTU_CNTL0, .DCN_SURF1_TTU_CNTL1 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX + regHUBPREQid_DCN_SURF1_TTU_CNTL1, .DCN_CUR0_TTU_CNTL0 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX + regHUBPREQid_DCN_CUR0_TTU_CNTL0, .DCN_CUR0_TTU_CNTL1 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX + regHUBPREQid_DCN_CUR0_TTU_CNTL1, .HUBP_CLK_CNTL = DCN_BASE__INST0_SEGregHUBPid_HUBP_CLK_CNTL_BASE_IDX + regHUBPid_HUBP_CLK_CNTL, .NOM_PARAMETERS_0 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_0_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_0, .NOM_PARAMETERS_1 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_1_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_1, .NOM_PARAMETERS_2 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_2_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_2, .NOM_PARAMETERS_3 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_3_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_3, .DCN_VM_MX_L1_TLB_CNTL = DCN_BASE__INST0_SEGregHUBPREQid_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX + regHUBPREQid_DCN_VM_MX_L1_TLB_CNTL, .PREFETCH_SETTINGS = DCN_BASE__INST0_SEGregHUBPREQid_PREFETCH_SETTINGS_BASE_IDX + regHUBPREQid_PREFETCH_SETTINGS, .PREFETCH_SETTINGS_C = DCN_BASE__INST0_SEGregHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX + regHUBPREQid_PREFETCH_SETTINGS_C, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = DCN_BASE__INST0_SEGregHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX + regHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = DCN_BASE__INST0_SEGregHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX + regHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, .CURSOR_SETTINGS = DCN_BASE__INST0_SEGregHUBPREQid_CURSOR_SETTINGS_BASE_IDX + regHUBPREQid_CURSOR_SETTINGS, .CURSOR_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX + regCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX + regCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_SIZE_BASE_IDX + regCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_CONTROL_BASE_IDX + regCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_POSITION_BASE_IDX + regCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX + regCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX + regCURSOR0_id_CURSOR_DST_OFFSET, .DMDATA_ADDRESS_HIGH = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX + regCURSOR0_id_DMDATA_ADDRESS_HIGH, .DMDATA_ADDRESS_LOW = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX + regCURSOR0_id_DMDATA_ADDRESS_LOW, .DMDATA_CNTL = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_CNTL_BASE_IDX + regCURSOR0_id_DMDATA_CNTL, .DMDATA_SW_CNTL = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX + regCURSOR0_id_DMDATA_SW_CNTL, .DMDATA_QOS_CNTL = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX + regCURSOR0_id_DMDATA_QOS_CNTL, .DMDATA_SW_DATA = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_SW_DATA_BASE_IDX + regCURSOR0_id_DMDATA_SW_DATA, .DMDATA_STATUS = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_STATUS_BASE_IDX + regCURSOR0_id_DMDATA_STATUS, .FLIP_PARAMETERS_0 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_0, .FLIP_PARAMETERS_1 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_1_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_1, .FLIP_PARAMETERS_2 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_2, .DCN_CUR1_TTU_CNTL0 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_CUR1_TTU_CNTL0_BASE_IDX + regHUBPREQid_DCN_CUR1_TTU_CNTL0, .DCN_CUR1_TTU_CNTL1 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_CUR1_TTU_CNTL1_BASE_IDX + regHUBPREQid_DCN_CUR1_TTU_CNTL1, .DCSURF_FLIP_CONTROL2 = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX + regHUBPREQid_DCSURF_FLIP_CONTROL2, .VMID_SETTINGS_0 = DCN_BASE__INST0_SEGregHUBPREQid_VMID_SETTINGS_0_BASE_IDX + regHUBPREQid_VMID_SETTINGS_0, .FLIP_PARAMETERS_3 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_3_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_3, .FLIP_PARAMETERS_4 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_4_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_4, .FLIP_PARAMETERS_5 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_5_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_5, .FLIP_PARAMETERS_6 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_6_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_6, .VBLANK_PARAMETERS_5 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_5_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_5, .VBLANK_PARAMETERS_6 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_6_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_6, .DCN_DMDATA_VM_CNTL = DCN_BASE__INST0_SEGregHUBPREQid_DCN_DMDATA_VM_CNTL_BASE_IDX + regHUBPREQid_DCN_DMDATA_VM_CNTL}\ | ||||
| 625 | [id] = {\ | ||||
| 626 | HUBP_REG_LIST_DCN30(id).DCHUBP_CNTL = DCN_BASE__INST0_SEGregHUBPid_DCHUBP_CNTL_BASE_IDX + regHUBPid_DCHUBP_CNTL, .HUBPREQ_DEBUG_DB = DCN_BASE__INST0_SEGregHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX + regHUBPid_HUBPREQ_DEBUG_DB, .HUBPREQ_DEBUG = DCN_BASE__INST0_SEGregHUBPid_HUBPREQ_DEBUG_BASE_IDX + regHUBPid_HUBPREQ_DEBUG, .DCSURF_ADDR_CONFIG = DCN_BASE__INST0_SEGregHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX + regHUBPid_DCSURF_ADDR_CONFIG, .DCSURF_TILING_CONFIG = DCN_BASE__INST0_SEGregHUBPid_DCSURF_TILING_CONFIG_BASE_IDX + regHUBPid_DCSURF_TILING_CONFIG, .DCSURF_SURFACE_PITCH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_PITCH, .DCSURF_SURFACE_PITCH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_PITCH_C, .DCSURF_SURFACE_CONFIG = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX + regHUBPid_DCSURF_SURFACE_CONFIG, .DCSURF_FLIP_CONTROL = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX + regHUBPREQid_DCSURF_FLIP_CONTROL, .DCSURF_PRI_VIEWPORT_DIMENSION = DCN_BASE__INST0_SEGregHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX + regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION, .DCSURF_PRI_VIEWPORT_START = DCN_BASE__INST0_SEGregHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX + regHUBPid_DCSURF_PRI_VIEWPORT_START, .DCSURF_SEC_VIEWPORT_DIMENSION = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX + regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION, .DCSURF_SEC_VIEWPORT_START = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX + regHUBPid_DCSURF_SEC_VIEWPORT_START, .DCSURF_PRI_VIEWPORT_DIMENSION_C = DCN_BASE__INST0_SEGregHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX + regHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C, .DCSURF_PRI_VIEWPORT_START_C = DCN_BASE__INST0_SEGregHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX + regHUBPid_DCSURF_PRI_VIEWPORT_START_C, .DCSURF_SEC_VIEWPORT_DIMENSION_C = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX + regHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C, .DCSURF_SEC_VIEWPORT_START_C = DCN_BASE__INST0_SEGregHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX + regHUBPid_DCSURF_SEC_VIEWPORT_START_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, . DCSURF_SECONDARY_META_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX + regHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX + regHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, .DCSURF_SURFACE_INUSE = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_INUSE, .DCSURF_SURFACE_INUSE_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, .DCSURF_SURFACE_INUSE_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_INUSE_C, .DCSURF_SURFACE_INUSE_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, .DCSURF_SURFACE_EARLIEST_INUSE = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, .DCSURF_SURFACE_EARLIEST_INUSE_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, .DCSURF_SURFACE_CONTROL = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_CONTROL, .DCSURF_SURFACE_FLIP_INTERRUPT = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX + regHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT, .HUBPRET_CONTROL = DCN_BASE__INST0_SEGregHUBPRETid_HUBPRET_CONTROL_BASE_IDX + regHUBPRETid_HUBPRET_CONTROL, .HUBPRET_READ_LINE_STATUS = DCN_BASE__INST0_SEGregHUBPRETid_HUBPRET_READ_LINE_STATUS_BASE_IDX + regHUBPRETid_HUBPRET_READ_LINE_STATUS, .DCN_EXPANSION_MODE = DCN_BASE__INST0_SEGregHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX + regHUBPREQid_DCN_EXPANSION_MODE, .DCHUBP_REQ_SIZE_CONFIG = DCN_BASE__INST0_SEGregHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX + regHUBPid_DCHUBP_REQ_SIZE_CONFIG, .DCHUBP_REQ_SIZE_CONFIG_C = DCN_BASE__INST0_SEGregHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX + regHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, .BLANK_OFFSET_0 = DCN_BASE__INST0_SEGregHUBPREQid_BLANK_OFFSET_0_BASE_IDX + regHUBPREQid_BLANK_OFFSET_0, .BLANK_OFFSET_1 = DCN_BASE__INST0_SEGregHUBPREQid_BLANK_OFFSET_1_BASE_IDX + regHUBPREQid_BLANK_OFFSET_1, .DST_DIMENSIONS = DCN_BASE__INST0_SEGregHUBPREQid_DST_DIMENSIONS_BASE_IDX + regHUBPREQid_DST_DIMENSIONS, .DST_AFTER_SCALER = DCN_BASE__INST0_SEGregHUBPREQid_DST_AFTER_SCALER_BASE_IDX + regHUBPREQid_DST_AFTER_SCALER, .VBLANK_PARAMETERS_0 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_0, .REF_FREQ_TO_PIX_FREQ = DCN_BASE__INST0_SEGregHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX + regHUBPREQid_REF_FREQ_TO_PIX_FREQ, .VBLANK_PARAMETERS_1 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_1, .VBLANK_PARAMETERS_3 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_3, .NOM_PARAMETERS_4 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_4_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_4, .NOM_PARAMETERS_5 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_5_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_5, .PER_LINE_DELIVERY_PRE = DCN_BASE__INST0_SEGregHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX + regHUBPREQid_PER_LINE_DELIVERY_PRE, .PER_LINE_DELIVERY = DCN_BASE__INST0_SEGregHUBPREQid_PER_LINE_DELIVERY_BASE_IDX + regHUBPREQid_PER_LINE_DELIVERY, .VBLANK_PARAMETERS_2 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_2, .VBLANK_PARAMETERS_4 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_4, .NOM_PARAMETERS_6 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_6_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_6, .NOM_PARAMETERS_7 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_7_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_7, .DCN_TTU_QOS_WM = DCN_BASE__INST0_SEGregHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX + regHUBPREQid_DCN_TTU_QOS_WM, .DCN_GLOBAL_TTU_CNTL = DCN_BASE__INST0_SEGregHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX + regHUBPREQid_DCN_GLOBAL_TTU_CNTL, .DCN_SURF0_TTU_CNTL0 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX + regHUBPREQid_DCN_SURF0_TTU_CNTL0, .DCN_SURF0_TTU_CNTL1 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX + regHUBPREQid_DCN_SURF0_TTU_CNTL1, .DCN_SURF1_TTU_CNTL0 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX + regHUBPREQid_DCN_SURF1_TTU_CNTL0, .DCN_SURF1_TTU_CNTL1 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX + regHUBPREQid_DCN_SURF1_TTU_CNTL1, .DCN_CUR0_TTU_CNTL0 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX + regHUBPREQid_DCN_CUR0_TTU_CNTL0, .DCN_CUR0_TTU_CNTL1 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX + regHUBPREQid_DCN_CUR0_TTU_CNTL1, .HUBP_CLK_CNTL = DCN_BASE__INST0_SEGregHUBPid_HUBP_CLK_CNTL_BASE_IDX + regHUBPid_HUBP_CLK_CNTL, .NOM_PARAMETERS_0 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_0_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_0, .NOM_PARAMETERS_1 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_1_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_1, .NOM_PARAMETERS_2 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_2_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_2, .NOM_PARAMETERS_3 = DCN_BASE__INST0_SEGregHUBPREQid_NOM_PARAMETERS_3_BASE_IDX + regHUBPREQid_NOM_PARAMETERS_3, .DCN_VM_MX_L1_TLB_CNTL = DCN_BASE__INST0_SEGregHUBPREQid_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX + regHUBPREQid_DCN_VM_MX_L1_TLB_CNTL, .PREFETCH_SETTINGS = DCN_BASE__INST0_SEGregHUBPREQid_PREFETCH_SETTINGS_BASE_IDX + regHUBPREQid_PREFETCH_SETTINGS, .PREFETCH_SETTINGS_C = DCN_BASE__INST0_SEGregHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX + regHUBPREQid_PREFETCH_SETTINGS_C, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = DCN_BASE__INST0_SEGregHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX + regHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = DCN_BASE__INST0_SEGregHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX + regHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, .CURSOR_SETTINGS = DCN_BASE__INST0_SEGregHUBPREQid_CURSOR_SETTINGS_BASE_IDX + regHUBPREQid_CURSOR_SETTINGS, .CURSOR_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX + regCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX + regCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_SIZE_BASE_IDX + regCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_CONTROL_BASE_IDX + regCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_POSITION_BASE_IDX + regCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX + regCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DCN_BASE__INST0_SEGregCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX + regCURSOR0_id_CURSOR_DST_OFFSET, .DMDATA_ADDRESS_HIGH = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX + regCURSOR0_id_DMDATA_ADDRESS_HIGH, .DMDATA_ADDRESS_LOW = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX + regCURSOR0_id_DMDATA_ADDRESS_LOW, .DMDATA_CNTL = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_CNTL_BASE_IDX + regCURSOR0_id_DMDATA_CNTL, .DMDATA_SW_CNTL = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX + regCURSOR0_id_DMDATA_SW_CNTL, .DMDATA_QOS_CNTL = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX + regCURSOR0_id_DMDATA_QOS_CNTL, .DMDATA_SW_DATA = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_SW_DATA_BASE_IDX + regCURSOR0_id_DMDATA_SW_DATA, .DMDATA_STATUS = DCN_BASE__INST0_SEGregCURSOR0_id_DMDATA_STATUS_BASE_IDX + regCURSOR0_id_DMDATA_STATUS, .FLIP_PARAMETERS_0 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_0, .FLIP_PARAMETERS_1 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_1_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_1, .FLIP_PARAMETERS_2 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_2, .DCN_CUR1_TTU_CNTL0 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_CUR1_TTU_CNTL0_BASE_IDX + regHUBPREQid_DCN_CUR1_TTU_CNTL0, .DCN_CUR1_TTU_CNTL1 = DCN_BASE__INST0_SEGregHUBPREQid_DCN_CUR1_TTU_CNTL1_BASE_IDX + regHUBPREQid_DCN_CUR1_TTU_CNTL1, .DCSURF_FLIP_CONTROL2 = DCN_BASE__INST0_SEGregHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX + regHUBPREQid_DCSURF_FLIP_CONTROL2, .VMID_SETTINGS_0 = DCN_BASE__INST0_SEGregHUBPREQid_VMID_SETTINGS_0_BASE_IDX + regHUBPREQid_VMID_SETTINGS_0, .FLIP_PARAMETERS_3 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_3_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_3, .FLIP_PARAMETERS_4 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_4_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_4, .FLIP_PARAMETERS_5 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_5_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_5, .FLIP_PARAMETERS_6 = DCN_BASE__INST0_SEGregHUBPREQid_FLIP_PARAMETERS_6_BASE_IDX + regHUBPREQid_FLIP_PARAMETERS_6, .VBLANK_PARAMETERS_5 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_5_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_5, .VBLANK_PARAMETERS_6 = DCN_BASE__INST0_SEGregHUBPREQid_VBLANK_PARAMETERS_6_BASE_IDX + regHUBPREQid_VBLANK_PARAMETERS_6, .DCN_DMDATA_VM_CNTL = DCN_BASE__INST0_SEGregHUBPREQid_DCN_DMDATA_VM_CNTL_BASE_IDX + regHUBPREQid_DCN_DMDATA_VM_CNTL\ | ||||
| 627 | } | ||||
| 628 | |||||
| 629 | static const struct dcn_hubp2_registers hubp_regs[] = { | ||||
| 630 | hubp_regs(0)[0] = { .DCHUBP_CNTL = 0x000034C0 + 0x05f3, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x05f6, .HUBPREQ_DEBUG = 0x000034C0 + 0x05f7, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x05e6, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x05e7, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x0607 , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x0608, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x05e5, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x061b , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x05ea, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x05e9, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x05ee, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x05ed, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x05ec, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x05eb, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x05f0, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x05ef , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x060b, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x060a, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x060f, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x060e, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0613, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x0612, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0617, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x0616, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x060d, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x060c , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0611 , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0610, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0615 , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0614 , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0619, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0618, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x0621, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x0622, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x0623, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0624, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0625, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x0626, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x0627, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x0628, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x061a, .DCSURF_SURFACE_FLIP_INTERRUPT = 0x000034C0 + 0x0620, .HUBPRET_CONTROL = 0x000034C0 + 0x066c , .HUBPRET_READ_LINE_STATUS = 0x000034C0 + 0x0675, .DCN_EXPANSION_MODE = 0x000034C0 + 0x0629, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x05f1, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x05f2, .BLANK_OFFSET_0 = 0x000034C0 + 0x0644, .BLANK_OFFSET_1 = 0x000034C0 + 0x0645 , .DST_DIMENSIONS = 0x000034C0 + 0x0646, .DST_AFTER_SCALER = 0x000034C0 + 0x0647, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x064a, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x065d, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x064b , .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x064d, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0656, .NOM_PARAMETERS_5 = 0x000034C0 + 0x0657 , .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x065a, .PER_LINE_DELIVERY = 0x000034C0 + 0x065b, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x064c , .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x064e, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0658, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0659 , .DCN_TTU_QOS_WM = 0x000034C0 + 0x062a, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x062b, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x062c , .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x062d, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x062e, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x062f , .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x0630, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x0631, .HUBP_CLK_CNTL = 0x000034C0 + 0x05f4, .NOM_PARAMETERS_0 = 0x000034C0 + 0x0652, .NOM_PARAMETERS_1 = 0x000034C0 + 0x0653, .NOM_PARAMETERS_2 = 0x000034C0 + 0x0654 , .NOM_PARAMETERS_3 = 0x000034C0 + 0x0655, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x0643, .PREFETCH_SETTINGS = 0x000034C0 + 0x0648 , .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0649, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x0635, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x0636, .CURSOR_SETTINGS = 0x000034C0 + 0x065c, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x067a, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0679, .CURSOR_SIZE = 0x000034C0 + 0x067b, .CURSOR_CONTROL = 0x000034C0 + 0x0678, .CURSOR_POSITION = 0x000034C0 + 0x067c, .CURSOR_HOT_SPOT = 0x000034C0 + 0x067d, .CURSOR_DST_OFFSET = 0x000034C0 + 0x067f, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0682 , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0683, .DMDATA_CNTL = 0x000034C0 + 0x0684, .DMDATA_SW_CNTL = 0x000034C0 + 0x0687, .DMDATA_QOS_CNTL = 0x000034C0 + 0x0685, .DMDATA_SW_DATA = 0x000034C0 + 0x0688 , .DMDATA_STATUS = 0x000034C0 + 0x0686, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x064f, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x0650, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x0651, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x0632 , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x0633, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x061c, .VMID_SETTINGS_0 = 0x000034C0 + 0x0609 , .FLIP_PARAMETERS_3 = 0x000034C0 + 0x0665, .FLIP_PARAMETERS_4 = 0x000034C0 + 0x0666, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x0667 , .FLIP_PARAMETERS_6 = 0x000034C0 + 0x0668, .VBLANK_PARAMETERS_5 = 0x000034C0 + 0x0663, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x0664 , .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x0634}, | ||||
| 631 | hubp_regs(1)[1] = { .DCHUBP_CNTL = 0x000034C0 + 0x06cf, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x06d2, .HUBPREQ_DEBUG = 0x000034C0 + 0x06d3, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x06c2, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x06c3, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x06e3 , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x06e4, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x06c1, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x06f7 , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x06c6, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x06c5, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x06ca, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x06c9, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x06c8, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x06c7, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x06cc, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x06cb , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06e7, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x06e6, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06eb, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x06ea, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06ef, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x06ee, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06f3, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x06f2, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06e9, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x06e8 , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06ed , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x06ec, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06f1 , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x06f0 , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06f5, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x06f4, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x06fd, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x06fe, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x06ff, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0700, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0701, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x0702, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x0703, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x0704, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x06f6, .DCSURF_SURFACE_FLIP_INTERRUPT = 0x000034C0 + 0x06fc, .HUBPRET_CONTROL = 0x000034C0 + 0x0748 , .HUBPRET_READ_LINE_STATUS = 0x000034C0 + 0x0751, .DCN_EXPANSION_MODE = 0x000034C0 + 0x0705, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x06cd, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x06ce, .BLANK_OFFSET_0 = 0x000034C0 + 0x0720, .BLANK_OFFSET_1 = 0x000034C0 + 0x0721 , .DST_DIMENSIONS = 0x000034C0 + 0x0722, .DST_AFTER_SCALER = 0x000034C0 + 0x0723, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x0726, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x0739, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0727 , .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x0729, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0732, .NOM_PARAMETERS_5 = 0x000034C0 + 0x0733 , .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x0736, .PER_LINE_DELIVERY = 0x000034C0 + 0x0737, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x0728 , .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x072a, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0734, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0735 , .DCN_TTU_QOS_WM = 0x000034C0 + 0x0706, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x0707, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x0708 , .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x0709, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x070a, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x070b , .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x070c, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x070d, .HUBP_CLK_CNTL = 0x000034C0 + 0x06d0, .NOM_PARAMETERS_0 = 0x000034C0 + 0x072e, .NOM_PARAMETERS_1 = 0x000034C0 + 0x072f, .NOM_PARAMETERS_2 = 0x000034C0 + 0x0730 , .NOM_PARAMETERS_3 = 0x000034C0 + 0x0731, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x071f, .PREFETCH_SETTINGS = 0x000034C0 + 0x0724 , .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0725, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x0711, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x0712, .CURSOR_SETTINGS = 0x000034C0 + 0x0738, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0756, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0755, .CURSOR_SIZE = 0x000034C0 + 0x0757, .CURSOR_CONTROL = 0x000034C0 + 0x0754, .CURSOR_POSITION = 0x000034C0 + 0x0758, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0759, .CURSOR_DST_OFFSET = 0x000034C0 + 0x075b, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x075e , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x075f, .DMDATA_CNTL = 0x000034C0 + 0x0760, .DMDATA_SW_CNTL = 0x000034C0 + 0x0763, .DMDATA_QOS_CNTL = 0x000034C0 + 0x0761, .DMDATA_SW_DATA = 0x000034C0 + 0x0764 , .DMDATA_STATUS = 0x000034C0 + 0x0762, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x072b, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x072c, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x072d, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x070e , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x070f, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x06f8, .VMID_SETTINGS_0 = 0x000034C0 + 0x06e5 , .FLIP_PARAMETERS_3 = 0x000034C0 + 0x0741, .FLIP_PARAMETERS_4 = 0x000034C0 + 0x0742, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x0743 , .FLIP_PARAMETERS_6 = 0x000034C0 + 0x0744, .VBLANK_PARAMETERS_5 = 0x000034C0 + 0x073f, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x0740 , .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x0710}, | ||||
| 632 | hubp_regs(2)[2] = { .DCHUBP_CNTL = 0x000034C0 + 0x07ab, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x07ae, .HUBPREQ_DEBUG = 0x000034C0 + 0x07af, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x079e, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x079f, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x07bf , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x07c0, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x079d, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x07d3 , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x07a2, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x07a1, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x07a6, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x07a5, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x07a4, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x07a3, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x07a8, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x07a7 , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07c3, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x07c2, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07c7, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x07c6, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07cb, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x07ca, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07cf, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x07ce, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07c5, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x07c4 , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07c9 , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x07c8, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07cd , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x07cc , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07d1, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x07d0, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x07d9, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x07da, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x07db, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x07dc, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x07dd, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x07de, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x07df, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x07e0, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x07d2, .DCSURF_SURFACE_FLIP_INTERRUPT = 0x000034C0 + 0x07d8, .HUBPRET_CONTROL = 0x000034C0 + 0x0824 , .HUBPRET_READ_LINE_STATUS = 0x000034C0 + 0x082d, .DCN_EXPANSION_MODE = 0x000034C0 + 0x07e1, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x07a9, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x07aa, .BLANK_OFFSET_0 = 0x000034C0 + 0x07fc, .BLANK_OFFSET_1 = 0x000034C0 + 0x07fd , .DST_DIMENSIONS = 0x000034C0 + 0x07fe, .DST_AFTER_SCALER = 0x000034C0 + 0x07ff, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x0802, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x0815, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0803 , .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x0805, .NOM_PARAMETERS_4 = 0x000034C0 + 0x080e, .NOM_PARAMETERS_5 = 0x000034C0 + 0x080f , .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x0812, .PER_LINE_DELIVERY = 0x000034C0 + 0x0813, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x0804 , .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x0806, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0810, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0811 , .DCN_TTU_QOS_WM = 0x000034C0 + 0x07e2, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x07e3, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x07e4 , .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x07e5, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x07e6, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x07e7 , .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x07e8, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x07e9, .HUBP_CLK_CNTL = 0x000034C0 + 0x07ac, .NOM_PARAMETERS_0 = 0x000034C0 + 0x080a, .NOM_PARAMETERS_1 = 0x000034C0 + 0x080b, .NOM_PARAMETERS_2 = 0x000034C0 + 0x080c , .NOM_PARAMETERS_3 = 0x000034C0 + 0x080d, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x07fb, .PREFETCH_SETTINGS = 0x000034C0 + 0x0800 , .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0801, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x07ed, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x07ee, .CURSOR_SETTINGS = 0x000034C0 + 0x0814, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0832, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0831, .CURSOR_SIZE = 0x000034C0 + 0x0833, .CURSOR_CONTROL = 0x000034C0 + 0x0830, .CURSOR_POSITION = 0x000034C0 + 0x0834, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0835, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0837, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x083a , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x083b, .DMDATA_CNTL = 0x000034C0 + 0x083c, .DMDATA_SW_CNTL = 0x000034C0 + 0x083f, .DMDATA_QOS_CNTL = 0x000034C0 + 0x083d, .DMDATA_SW_DATA = 0x000034C0 + 0x0840 , .DMDATA_STATUS = 0x000034C0 + 0x083e, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x0807, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x0808, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x0809, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x07ea , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x07eb, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x07d4, .VMID_SETTINGS_0 = 0x000034C0 + 0x07c1 , .FLIP_PARAMETERS_3 = 0x000034C0 + 0x081d, .FLIP_PARAMETERS_4 = 0x000034C0 + 0x081e, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x081f , .FLIP_PARAMETERS_6 = 0x000034C0 + 0x0820, .VBLANK_PARAMETERS_5 = 0x000034C0 + 0x081b, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x081c , .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x07ec}, | ||||
| 633 | hubp_regs(3)[3] = { .DCHUBP_CNTL = 0x000034C0 + 0x0887, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x088a, .HUBPREQ_DEBUG = 0x000034C0 + 0x088b, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x087a, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x087b, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x089b , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x089c, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x0879, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x08af , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x087e, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x087d, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x0882, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x0881, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0880, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x087f, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0884, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x0883 , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x089f, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x089e, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x08a3, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x08a2, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x08a7, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x08a6, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x08ab, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x08aa, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a1, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a0 , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a5 , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a4, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a9 , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a8 , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08ad, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x08ac, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x08b5, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x08b6, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x08b7, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x08b8, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x08b9, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x08ba, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x08bb, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x08bc, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x08ae, .DCSURF_SURFACE_FLIP_INTERRUPT = 0x000034C0 + 0x08b4, .HUBPRET_CONTROL = 0x000034C0 + 0x0900 , .HUBPRET_READ_LINE_STATUS = 0x000034C0 + 0x0909, .DCN_EXPANSION_MODE = 0x000034C0 + 0x08bd, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x0885, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x0886, .BLANK_OFFSET_0 = 0x000034C0 + 0x08d8, .BLANK_OFFSET_1 = 0x000034C0 + 0x08d9 , .DST_DIMENSIONS = 0x000034C0 + 0x08da, .DST_AFTER_SCALER = 0x000034C0 + 0x08db, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x08de, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x08f1, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x08df , .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x08e1, .NOM_PARAMETERS_4 = 0x000034C0 + 0x08ea, .NOM_PARAMETERS_5 = 0x000034C0 + 0x08eb , .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x08ee, .PER_LINE_DELIVERY = 0x000034C0 + 0x08ef, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x08e0 , .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x08e2, .NOM_PARAMETERS_6 = 0x000034C0 + 0x08ec, .NOM_PARAMETERS_7 = 0x000034C0 + 0x08ed , .DCN_TTU_QOS_WM = 0x000034C0 + 0x08be, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x08bf, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x08c0 , .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x08c1, .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x08c2, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x08c3 , .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x08c4, .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x08c5, .HUBP_CLK_CNTL = 0x000034C0 + 0x0888, .NOM_PARAMETERS_0 = 0x000034C0 + 0x08e6, .NOM_PARAMETERS_1 = 0x000034C0 + 0x08e7, .NOM_PARAMETERS_2 = 0x000034C0 + 0x08e8 , .NOM_PARAMETERS_3 = 0x000034C0 + 0x08e9, .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x08d7, .PREFETCH_SETTINGS = 0x000034C0 + 0x08dc , .PREFETCH_SETTINGS_C = 0x000034C0 + 0x08dd, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x08c9, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x08ca, .CURSOR_SETTINGS = 0x000034C0 + 0x08f0, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x090e, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x090d, .CURSOR_SIZE = 0x000034C0 + 0x090f, .CURSOR_CONTROL = 0x000034C0 + 0x090c, .CURSOR_POSITION = 0x000034C0 + 0x0910, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0911, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0913, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0916 , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0917, .DMDATA_CNTL = 0x000034C0 + 0x0918, .DMDATA_SW_CNTL = 0x000034C0 + 0x091b, .DMDATA_QOS_CNTL = 0x000034C0 + 0x0919, .DMDATA_SW_DATA = 0x000034C0 + 0x091c , .DMDATA_STATUS = 0x000034C0 + 0x091a, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x08e3, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x08e4, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x08e5, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x08c6 , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x08c7, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x08b0, .VMID_SETTINGS_0 = 0x000034C0 + 0x089d , .FLIP_PARAMETERS_3 = 0x000034C0 + 0x08f9, .FLIP_PARAMETERS_4 = 0x000034C0 + 0x08fa, .FLIP_PARAMETERS_5 = 0x000034C0 + 0x08fb , .FLIP_PARAMETERS_6 = 0x000034C0 + 0x08fc, .VBLANK_PARAMETERS_5 = 0x000034C0 + 0x08f7, .VBLANK_PARAMETERS_6 = 0x000034C0 + 0x08f8 , .DCN_DMDATA_VM_CNTL = 0x000034C0 + 0x08c8} | ||||
| 634 | }; | ||||
| 635 | |||||
| 636 | |||||
| 637 | static const struct dcn_hubp2_shift hubp_shift = { | ||||
| 638 | HUBP_MASK_SH_LIST_DCN31(__SHIFT).REFCYC_PER_VM_DMDATA = 0x0, .DMDATA_VM_FAULT_STATUS = 0x10, . DMDATA_VM_FAULT_STATUS_CLEAR = 0x14, .DMDATA_VM_UNDERFLOW_STATUS = 0x18, .DMDATA_VM_LATE_STATUS = 0x19, .DMDATA_VM_UNDERFLOW_STATUS_CLEAR = 0x1a, .DMDATA_VM_DONE = 0x1f, .HUBP_BLANK_EN = 0x0, .HUBP_TTU_DISABLE = 0xc, .HUBP_UNDERFLOW_STATUS = 0x1c, .HUBP_UNDERFLOW_CLEAR = 0x1f, .HUBP_NO_OUTSTANDING_REQ = 0x1, .HUBP_VTG_SEL = 0x4, . HUBP_UNBOUNDED_REQ_MODE = 0xa, .HUBP_IN_BLANK = 0x3, .HUBP_SOFT_RESET = 0x2, .NUM_PIPES = 0x0, .PIPE_INTERLEAVE = 0x6, .MAX_COMPRESSED_FRAGS = 0xc, .NUM_PKRS = 0x10, .SW_MODE = 0x0, .META_LINEAR = 0x9, .PIPE_ALIGNED = 0xb, .PITCH = 0x0, .META_PITCH = 0x10, .PITCH_C = 0x0, .META_PITCH_C = 0x10, .SURFACE_PIXEL_FORMAT = 0x0, .SURFACE_FLIP_TYPE = 0x1, .SURFACE_FLIP_MODE_FOR_STEREOSYNC = 0xc, .SURFACE_FLIP_IN_STEREOSYNC = 0x10, .SURFACE_FLIP_PENDING = 0x8, .SURFACE_UPDATE_LOCK = 0x0 , .PRI_VIEWPORT_WIDTH = 0x0, .PRI_VIEWPORT_HEIGHT = 0x10, .PRI_VIEWPORT_X_START = 0x0, .PRI_VIEWPORT_Y_START = 0x10, .SEC_VIEWPORT_WIDTH = 0x0 , .SEC_VIEWPORT_HEIGHT = 0x10, .SEC_VIEWPORT_X_START = 0x0, . SEC_VIEWPORT_Y_START = 0x10, .PRI_VIEWPORT_WIDTH_C = 0x0, .PRI_VIEWPORT_HEIGHT_C = 0x10, .PRI_VIEWPORT_X_START_C = 0x0, .PRI_VIEWPORT_Y_START_C = 0x10, .SEC_VIEWPORT_WIDTH_C = 0x0, .SEC_VIEWPORT_HEIGHT_C = 0x10, .SEC_VIEWPORT_X_START_C = 0x0, .SEC_VIEWPORT_Y_START_C = 0x10, .PRIMARY_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_SURFACE_ADDRESS = 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_SURFACE_ADDRESS = 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_META_SURFACE_ADDRESS = 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_META_SURFACE_ADDRESS = 0x0, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_SURFACE_ADDRESS_C = 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_SURFACE_ADDRESS_C = 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_META_SURFACE_ADDRESS_C = 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_META_SURFACE_ADDRESS_C = 0x0, .SURFACE_INUSE_ADDRESS = 0x0, .SURFACE_INUSE_ADDRESS_HIGH = 0x0, .SURFACE_INUSE_ADDRESS_C = 0x0, .SURFACE_INUSE_ADDRESS_HIGH_C = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C = 0x0, .PRIMARY_SURFACE_TMZ = 0x0, .PRIMARY_SURFACE_TMZ_C = 0x4 , .PRIMARY_META_SURFACE_TMZ = 0x10, .PRIMARY_META_SURFACE_TMZ_C = 0x11, .PRIMARY_SURFACE_DCC_EN = 0x1, .PRIMARY_SURFACE_DCC_IND_BLK = 0x2, .PRIMARY_SURFACE_DCC_IND_BLK_C = 0x5, .SECONDARY_SURFACE_TMZ = 0x8, .SECONDARY_SURFACE_TMZ_C = 0xc, .SECONDARY_META_SURFACE_TMZ = 0x12, .SECONDARY_META_SURFACE_TMZ_C = 0x13, .SECONDARY_SURFACE_DCC_EN = 0x9, .SECONDARY_SURFACE_DCC_IND_BLK = 0xa, .SECONDARY_SURFACE_DCC_IND_BLK_C = 0xd, .SURFACE_FLIP_INT_MASK = 0x0, .DET_BUF_PLANE1_BASE_ADDRESS = 0x4, .CROSSBAR_SRC_CB_B = 0x14, .CROSSBAR_SRC_CR_R = 0x16, .CROSSBAR_SRC_Y_G = 0x12, .CROSSBAR_SRC_ALPHA = 0x10, .PACK_3TO2_ELEMENT_DISABLE = 0xf, .DRQ_EXPANSION_MODE = 0x0, .PRQ_EXPANSION_MODE = 0x6, .MRQ_EXPANSION_MODE = 0x4, .CRQ_EXPANSION_MODE = 0x2, .CHUNK_SIZE = 0x8, .MIN_CHUNK_SIZE = 0xb, .META_CHUNK_SIZE = 0x10, .MIN_META_CHUNK_SIZE = 0x12, .DPTE_GROUP_SIZE = 0x14, .SWATH_HEIGHT = 0x0, .PTE_ROW_HEIGHT_LINEAR = 0x4, .CHUNK_SIZE_C = 0x8, .MIN_CHUNK_SIZE_C = 0xb, .META_CHUNK_SIZE_C = 0x10, .MIN_META_CHUNK_SIZE_C = 0x12, .DPTE_GROUP_SIZE_C = 0x14 , .SWATH_HEIGHT_C = 0x0, .PTE_ROW_HEIGHT_LINEAR_C = 0x4, .REFCYC_H_BLANK_END = 0x0, .DLG_V_BLANK_END = 0x10, .MIN_DST_Y_NEXT_START = 0x0, .REFCYC_PER_HTOTAL = 0x0, .REFCYC_X_AFTER_SCALER = 0x0, .DST_Y_AFTER_SCALER = 0x10, .DST_Y_PER_VM_VBLANK = 0x0, .DST_Y_PER_ROW_VBLANK = 0x8 , .REF_FREQ_TO_PIX_FREQ = 0x0, .REFCYC_PER_PTE_GROUP_VBLANK_L = 0x0, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x0, .DST_Y_PER_META_ROW_NOM_L = 0x0, .REFCYC_PER_META_CHUNK_NOM_L = 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_L = 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x10, .REFCYC_PER_LINE_DELIVERY_L = 0x0, .REFCYC_PER_LINE_DELIVERY_C = 0x10, .REFCYC_PER_PTE_GROUP_VBLANK_C = 0x0, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x0, .DST_Y_PER_META_ROW_NOM_C = 0x0, .REFCYC_PER_META_CHUNK_NOM_C = 0x0, .QoS_LEVEL_LOW_WM = 0x0, .QoS_LEVEL_HIGH_WM = 0x10, .MIN_TTU_VBLANK = 0x0, .QoS_LEVEL_FLIP = 0x1c, .ROW_TTU_MODE = 0x1b, .REFCYC_PER_REQ_DELIVERY = 0x0 , .QoS_LEVEL_FIXED = 0x18, .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE = 0x0, .HUBP_CLOCK_ENABLE = 0x0, .DST_Y_PER_PTE_ROW_NOM_L = 0x0 , .REFCYC_PER_PTE_GROUP_NOM_L = 0x0, .DST_Y_PER_PTE_ROW_NOM_C = 0x0, .REFCYC_PER_PTE_GROUP_NOM_C = 0x0, .ENABLE_L1_TLB = 0x0 , .SYSTEM_ACCESS_MODE = 0x3, .REFCYC_PER_REQ_DELIVERY = 0x0, . QoS_LEVEL_FIXED = 0x18, .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE = 0x0, .ROTATION_ANGLE = 0x8, .H_MIRROR_EN = 0xa, .ALPHA_PLANE_EN = 0xb, .DST_Y_PREFETCH = 0x18, .VRATIO_PREFETCH = 0x0, .VRATIO_PREFETCH_C = 0x0, .MC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x0, .MC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x0, .CURSOR0_DST_Y_OFFSET = 0x0, .CURSOR0_CHUNK_HDL_ADJUST = 0x8, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0, .CURSOR_SURFACE_ADDRESS = 0x0, .CURSOR_WIDTH = 0x10, .CURSOR_HEIGHT = 0x0, .CURSOR_MODE = 0x8, .CURSOR_REQ_MODE = 0x2, .CURSOR_2X_MAGNIFY = 0x4, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK = 0x18, .CURSOR_ENABLE = 0x0 , .CURSOR_X_POSITION = 0x10, .CURSOR_Y_POSITION = 0x0, .CURSOR_HOT_SPOT_X = 0x10, .CURSOR_HOT_SPOT_Y = 0x0, .CURSOR_DST_X_OFFSET = 0x0 , .DMDATA_ADDRESS_HIGH = 0x0, .DMDATA_MODE = 0x2, .DMDATA_UPDATED = 0x0, .DMDATA_REPEAT = 0x1, .DMDATA_SIZE = 0x10, .DMDATA_SW_UPDATED = 0x0, .DMDATA_SW_REPEAT = 0x1, .DMDATA_SW_SIZE = 0x10, .DMDATA_QOS_MODE = 0x0, .DMDATA_QOS_LEVEL = 0x4, .DMDATA_DL_DELTA = 0x10, .DMDATA_DONE = 0x0, .DST_Y_PER_VM_FLIP = 0x0, .DST_Y_PER_ROW_FLIP = 0x8, . REFCYC_PER_PTE_GROUP_FLIP_L = 0x0, .REFCYC_PER_META_CHUNK_FLIP_L = 0x0, .HUBP_VREADY_AT_OR_AFTER_VSYNC = 0x8, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x9, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS = 0x9, .SURFACE_GSL_ENABLE = 0x8, .SURFACE_TRIPLE_BUFFER_ENABLE = 0xa, .VMID = 0x0, .REFCYC_PER_VM_GROUP_FLIP = 0x0, .REFCYC_PER_VM_REQ_FLIP = 0x0, .REFCYC_PER_PTE_GROUP_FLIP_C = 0x0, .REFCYC_PER_META_CHUNK_FLIP_C = 0x0, .REFCYC_PER_VM_GROUP_VBLANK = 0x0, .REFCYC_PER_VM_REQ_VBLANK = 0x0, .VM_GROUP_SIZE = 0x18 | ||||
| 639 | }; | ||||
| 640 | |||||
| 641 | static const struct dcn_hubp2_mask hubp_mask = { | ||||
| 642 | HUBP_MASK_SH_LIST_DCN31(_MASK).REFCYC_PER_VM_DMDATA = 0x0000FFFFL, .DMDATA_VM_FAULT_STATUS = 0x000F0000L, .DMDATA_VM_FAULT_STATUS_CLEAR = 0x00100000L, .DMDATA_VM_UNDERFLOW_STATUS = 0x01000000L, .DMDATA_VM_LATE_STATUS = 0x02000000L, .DMDATA_VM_UNDERFLOW_STATUS_CLEAR = 0x04000000L, .DMDATA_VM_DONE = 0x80000000L, .HUBP_BLANK_EN = 0x00000001L, .HUBP_TTU_DISABLE = 0x00001000L, .HUBP_UNDERFLOW_STATUS = 0x70000000L, .HUBP_UNDERFLOW_CLEAR = 0x80000000L, .HUBP_NO_OUTSTANDING_REQ = 0x00000002L, .HUBP_VTG_SEL = 0x000000F0L, .HUBP_UNBOUNDED_REQ_MODE = 0x00000400L, .HUBP_IN_BLANK = 0x00000008L, .HUBP_SOFT_RESET = 0x00000004L, .NUM_PIPES = 0x00000007L, .PIPE_INTERLEAVE = 0x000000C0L , .MAX_COMPRESSED_FRAGS = 0x00003000L, .NUM_PKRS = 0x00070000L , .SW_MODE = 0x0000001FL, .META_LINEAR = 0x00000200L, .PIPE_ALIGNED = 0x00000800L, .PITCH = 0x00003FFFL, .META_PITCH = 0x3FFF0000L , .PITCH_C = 0x00003FFFL, .META_PITCH_C = 0x3FFF0000L, .SURFACE_PIXEL_FORMAT = 0x0000007FL, .SURFACE_FLIP_TYPE = 0x00000002L, .SURFACE_FLIP_MODE_FOR_STEREOSYNC = 0x00003000L, .SURFACE_FLIP_IN_STEREOSYNC = 0x00010000L, .SURFACE_FLIP_PENDING = 0x00000100L, .SURFACE_UPDATE_LOCK = 0x00000001L, .PRI_VIEWPORT_WIDTH = 0x00003FFFL, .PRI_VIEWPORT_HEIGHT = 0x3FFF0000L, .PRI_VIEWPORT_X_START = 0x00003FFFL, .PRI_VIEWPORT_Y_START = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH = 0x00003FFFL, .SEC_VIEWPORT_HEIGHT = 0x3FFF0000L, .SEC_VIEWPORT_X_START = 0x00003FFFL, .SEC_VIEWPORT_Y_START = 0x3FFF0000L, .PRI_VIEWPORT_WIDTH_C = 0x00003FFFL, .PRI_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .PRI_VIEWPORT_X_START_C = 0x00003FFFL, .PRI_VIEWPORT_Y_START_C = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH_C = 0x00003FFFL, .SEC_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .SEC_VIEWPORT_X_START_C = 0x00003FFFL, .SEC_VIEWPORT_Y_START_C = 0x3FFF0000L, .PRIMARY_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .PRIMARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS = 0xFFFFFFFFL, . SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .SECONDARY_META_SURFACE_ADDRESS = 0xFFFFFFFFL, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL , .PRIMARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, . PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL , .SECONDARY_META_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH = 0x0000FFFFL, .SURFACE_INUSE_ADDRESS_C = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, . SURFACE_EARLIEST_INUSE_ADDRESS = 0xFFFFFFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH = 0x0000FFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0xFFFFFFFFL , .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_SURFACE_TMZ = 0x00000001L, .PRIMARY_SURFACE_TMZ_C = 0x00000010L, .PRIMARY_META_SURFACE_TMZ = 0x00010000L, .PRIMARY_META_SURFACE_TMZ_C = 0x00020000L, .PRIMARY_SURFACE_DCC_EN = 0x00000002L, .PRIMARY_SURFACE_DCC_IND_BLK = 0x0000000CL, . PRIMARY_SURFACE_DCC_IND_BLK_C = 0x00000060L, .SECONDARY_SURFACE_TMZ = 0x00000100L, .SECONDARY_SURFACE_TMZ_C = 0x00001000L, .SECONDARY_META_SURFACE_TMZ = 0x00040000L, .SECONDARY_META_SURFACE_TMZ_C = 0x00080000L, . SECONDARY_SURFACE_DCC_EN = 0x00000200L, .SECONDARY_SURFACE_DCC_IND_BLK = 0x00000C00L, .SECONDARY_SURFACE_DCC_IND_BLK_C = 0x00006000L , .SURFACE_FLIP_INT_MASK = 0x00000001L, .DET_BUF_PLANE1_BASE_ADDRESS = 0x00001FF0L, .CROSSBAR_SRC_CB_B = 0x00300000L, .CROSSBAR_SRC_CR_R = 0x00C00000L, .CROSSBAR_SRC_Y_G = 0x000C0000L, .CROSSBAR_SRC_ALPHA = 0x00030000L, .PACK_3TO2_ELEMENT_DISABLE = 0x00008000L, .DRQ_EXPANSION_MODE = 0x00000003L, .PRQ_EXPANSION_MODE = 0x000000C0L, .MRQ_EXPANSION_MODE = 0x00000030L, .CRQ_EXPANSION_MODE = 0x0000000CL, .CHUNK_SIZE = 0x00000700L, .MIN_CHUNK_SIZE = 0x00001800L, .META_CHUNK_SIZE = 0x00030000L, .MIN_META_CHUNK_SIZE = 0x000C0000L, .DPTE_GROUP_SIZE = 0x00700000L, .SWATH_HEIGHT = 0x00000007L, .PTE_ROW_HEIGHT_LINEAR = 0x00000070L, .CHUNK_SIZE_C = 0x00000700L, .MIN_CHUNK_SIZE_C = 0x00001800L, .META_CHUNK_SIZE_C = 0x00030000L, .MIN_META_CHUNK_SIZE_C = 0x000C0000L, .DPTE_GROUP_SIZE_C = 0x00700000L, .SWATH_HEIGHT_C = 0x00000007L, .PTE_ROW_HEIGHT_LINEAR_C = 0x00000070L, .REFCYC_H_BLANK_END = 0x00001FFFL, .DLG_V_BLANK_END = 0x7FFF0000L, .MIN_DST_Y_NEXT_START = 0x0003FFFFL, .REFCYC_PER_HTOTAL = 0x001FFFFFL, .REFCYC_X_AFTER_SCALER = 0x00001FFFL, .DST_Y_AFTER_SCALER = 0x00070000L, .DST_Y_PER_VM_VBLANK = 0x0000007FL, .DST_Y_PER_ROW_VBLANK = 0x00003F00L, .REF_FREQ_TO_PIX_FREQ = 0x001FFFFFL, .REFCYC_PER_PTE_GROUP_VBLANK_L = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x007FFFFFL, .DST_Y_PER_META_ROW_NOM_L = 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_L = 0x007FFFFFL, . REFCYC_PER_LINE_DELIVERY_PRE_L = 0x00001FFFL, .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x1FFF0000L, .REFCYC_PER_LINE_DELIVERY_L = 0x00001FFFL, .REFCYC_PER_LINE_DELIVERY_C = 0x1FFF0000L, .REFCYC_PER_PTE_GROUP_VBLANK_C = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x007FFFFFL, .DST_Y_PER_META_ROW_NOM_C = 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_C = 0x007FFFFFL, . QoS_LEVEL_LOW_WM = 0x00003FFFL, .QoS_LEVEL_HIGH_WM = 0x3FFF0000L , .MIN_TTU_VBLANK = 0x00FFFFFFL, .QoS_LEVEL_FLIP = 0xF0000000L , .ROW_TTU_MODE = 0x08000000L, .REFCYC_PER_REQ_DELIVERY = 0x007FFFFFL , .QoS_LEVEL_FIXED = 0x0F000000L, .QoS_RAMP_DISABLE = 0x10000000L , .REFCYC_PER_REQ_DELIVERY_PRE = 0x007FFFFFL, .HUBP_CLOCK_ENABLE = 0x00000001L, .DST_Y_PER_PTE_ROW_NOM_L = 0x0001FFFFL, .REFCYC_PER_PTE_GROUP_NOM_L = 0x007FFFFFL, .DST_Y_PER_PTE_ROW_NOM_C = 0x0001FFFFL, .REFCYC_PER_PTE_GROUP_NOM_C = 0x007FFFFFL, .ENABLE_L1_TLB = 0x00000001L, .SYSTEM_ACCESS_MODE = 0x00000018L, .REFCYC_PER_REQ_DELIVERY = 0x007FFFFFL, .QoS_LEVEL_FIXED = 0x0F000000L, .QoS_RAMP_DISABLE = 0x10000000L, .REFCYC_PER_REQ_DELIVERY_PRE = 0x007FFFFFL, .ROTATION_ANGLE = 0x00000300L, .H_MIRROR_EN = 0x00000400L, .ALPHA_PLANE_EN = 0x00000800L, .DST_Y_PREFETCH = 0xFF000000L, .VRATIO_PREFETCH = 0x003FFFFFL, .VRATIO_PREFETCH_C = 0x003FFFFFL, .MC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x3FFFFFFFL , .MC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x3FFFFFFFL, .CURSOR0_DST_Y_OFFSET = 0x000000FFL, .CURSOR0_CHUNK_HDL_ADJUST = 0x00000300L, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .CURSOR_SURFACE_ADDRESS = 0xFFFFFFFFL, .CURSOR_WIDTH = 0x01FF0000L, .CURSOR_HEIGHT = 0x000001FFL, .CURSOR_MODE = 0x00000700L , .CURSOR_REQ_MODE = 0x00000004L, .CURSOR_2X_MAGNIFY = 0x00000010L , .CURSOR_PITCH = 0x00030000L, .CURSOR_LINES_PER_CHUNK = 0x1F000000L , .CURSOR_ENABLE = 0x00000001L, .CURSOR_X_POSITION = 0x3FFF0000L , .CURSOR_Y_POSITION = 0x00003FFFL, .CURSOR_HOT_SPOT_X = 0x00FF0000L , .CURSOR_HOT_SPOT_Y = 0x000000FFL, .CURSOR_DST_X_OFFSET = 0x00001FFFL , .DMDATA_ADDRESS_HIGH = 0x0000FFFFL, .DMDATA_MODE = 0x00000004L , .DMDATA_UPDATED = 0x00000001L, .DMDATA_REPEAT = 0x00000002L , .DMDATA_SIZE = 0x0FFF0000L, .DMDATA_SW_UPDATED = 0x00000001L , .DMDATA_SW_REPEAT = 0x00000002L, .DMDATA_SW_SIZE = 0x0FFF0000L , .DMDATA_QOS_MODE = 0x00000001L, .DMDATA_QOS_LEVEL = 0x000000F0L , .DMDATA_DL_DELTA = 0xFFFF0000L, .DMDATA_DONE = 0x00000001L, .DST_Y_PER_VM_FLIP = 0x0000007FL, .DST_Y_PER_ROW_FLIP = 0x00003F00L , .REFCYC_PER_PTE_GROUP_FLIP_L = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_FLIP_L = 0x007FFFFFL, .HUBP_VREADY_AT_OR_AFTER_VSYNC = 0x00000100L, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x00000200L, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS = 0x00000200L, .SURFACE_GSL_ENABLE = 0x00000100L, .SURFACE_TRIPLE_BUFFER_ENABLE = 0x00000400L, .VMID = 0x0000000FL, .REFCYC_PER_VM_GROUP_FLIP = 0x007FFFFFL, .REFCYC_PER_VM_REQ_FLIP = 0x007FFFFFL, .REFCYC_PER_PTE_GROUP_FLIP_C = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_FLIP_C = 0x007FFFFFL, . REFCYC_PER_VM_GROUP_VBLANK = 0x007FFFFFL, .REFCYC_PER_VM_REQ_VBLANK = 0x007FFFFFL, .VM_GROUP_SIZE = 0x07000000L | ||||
| 643 | }; | ||||
| 644 | static const struct dcn_hubbub_registers hubbub_reg = { | ||||
| 645 | HUBBUB_REG_LIST_DCN31(0).DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x000034C0 + 0x04fd, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x000034C0 + 0x0503, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x000034C0 + 0x0506, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x000034C0 + 0x050c, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x000034C0 + 0x050f, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x000034C0 + 0x0515, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x000034C0 + 0x0518, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x000034C0 + 0x051e, .DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL = 0x000034C0 + 0x0522, .DCHUBBUB_ARB_DRAM_STATE_CNTL = 0x000034C0 + 0x04fc, .DCHUBBUB_ARB_SAT_LEVEL = 0x000034C0 + 0x04fa, .DCHUBBUB_ARB_DF_REQ_OUTSTAND = 0x000034C0 + 0x04f9, .DCHUBBUB_GLOBAL_TIMER_CNTL = 0x000034C0 + 0x0524, .DCHUBBUB_TEST_DEBUG_INDEX = 0x000034C0 + 0x0541, . DCHUBBUB_TEST_DEBUG_DATA = 0x000034C0 + 0x0542, .DCHUBBUB_SOFT_RESET = 0x000034C0 + 0x0531, .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04c2 , .DCN_VM_FB_LOCATION_BASE = 0x000034C0 + 0x0475, .DCN_VM_FB_LOCATION_TOP = 0x000034C0 + 0x0476, .DCN_VM_FB_OFFSET = 0x000034C0 + 0x0477 , .DCN_VM_AGP_BOT = 0x000034C0 + 0x0478, .DCN_VM_AGP_TOP = 0x000034C0 + 0x0479, .DCN_VM_AGP_BASE = 0x000034C0 + 0x047a, .DCN_VM_FAULT_ADDR_MSB = 0x000034C0 + 0x05cd, .DCN_VM_FAULT_ADDR_LSB = 0x000034C0 + 0x05ce, .DCN_VM_FAULT_CNTL = 0x000034C0 + 0x05cb, .DCN_VM_FAULT_STATUS = 0x000034C0 + 0x05cc, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x000034C0 + 0x04ff, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x000034C0 + 0x0501, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = 0x000034C0 + 0x0508, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x000034C0 + 0x050a, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x000034C0 + 0x0511, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x000034C0 + 0x0513, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x000034C0 + 0x051a, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = 0x000034C0 + 0x051c, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = 0x000034C0 + 0x0504, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = 0x000034C0 + 0x050d , .DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = 0x000034C0 + 0x0516, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = 0x000034C0 + 0x051f, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = 0x000034C0 + 0x0505, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = 0x000034C0 + 0x050e , .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = 0x000034C0 + 0x0517, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = 0x000034C0 + 0x0520, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = 0x000034C0 + 0x04fe, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = 0x000034C0 + 0x0507, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = 0x000034C0 + 0x0510, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D = 0x000034C0 + 0x0519, .DCHVM_CTRL0 = 0x000034C0 + 0x3603, . DCHVM_MEM_CTRL = 0x000034C0 + 0x3606, .DCHVM_CLK_CTRL = 0x000034C0 + 0x3605, .DCHVM_RIOMMU_CTRL0 = 0x000034C0 + 0x3607, .DCHVM_RIOMMU_STAT0 = 0x000034C0 + 0x3608, .DCHUBBUB_DET0_CTRL = 0x000034C0 + 0x04cc , .DCHUBBUB_DET1_CTRL = 0x000034C0 + 0x04cd, .DCHUBBUB_DET2_CTRL = 0x000034C0 + 0x04ce, .DCHUBBUB_DET3_CTRL = 0x000034C0 + 0x04cf , .DCHUBBUB_COMPBUF_CTRL = 0x000034C0 + 0x04cb, .COMPBUF_RESERVED_SPACE = 0x000034C0 + 0x04d5, .DCHUBBUB_DEBUG_CTRL_0 = 0x000034C0 + 0x04d6, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A = 0x000034C0 + 0x0500, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A = 0x000034C0 + 0x0502, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B = 0x000034C0 + 0x0509, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B = 0x000034C0 + 0x050b, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C = 0x000034C0 + 0x0512, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C = 0x000034C0 + 0x0514, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D = 0x000034C0 + 0x051b, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D = 0x000034C0 + 0x051d | ||||
| 646 | }; | ||||
| 647 | |||||
| 648 | static const struct dcn_hubbub_shift hubbub_shift = { | ||||
| 649 | HUBBUB_MASK_SH_LIST_DCN31(__SHIFT).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCHUBBUB_GLOBAL_SOFT_RESET = 0x0, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x8, .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE = 0x4, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x0, . DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x1, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE = 0x4, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x5, .DCHUBBUB_ARB_SAT_LEVEL = 0x0, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND = 0xc, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x0 , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x0 , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0, .FB_BASE = 0x0, . FB_TOP = 0x0, .FB_OFFSET = 0x0, .AGP_BOT = 0x0, .AGP_TOP = 0x0 , .AGP_BASE = 0x0, .HOSTVM_INIT_REQ = 0x0, .HVM_GPUVMRET_PWR_REQ_DIS = 0x0, .HVM_GPUVMRET_FORCE_REQ = 0x2, .HVM_GPUVMRET_POWER_STATUS = 0x4, .HVM_DISPCLK_R_GATE_DIS = 0x0, .HVM_DISPCLK_G_GATE_DIS = 0x1, .HVM_DCFCLK_R_GATE_DIS = 0x4, .HVM_DCFCLK_G_GATE_DIS = 0x5, .TR_REQ_REQCLKREQ_MODE = 0x8, .TW_RSP_COMPCLKREQ_MODE = 0xa, .HOSTVM_PREFETCH_REQ = 0x0, .HOSTVM_POWERSTATUS = 0x1, . RIOMMU_ACTIVE = 0x0, .HOSTVM_PREFETCH_DONE = 0x1, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = 0x0, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = 0x0, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D = 0x0, .DET_DEPTH = 0x10, .DET0_SIZE = 0x0, .DET0_SIZE_CURRENT = 0x8, .DET1_SIZE = 0x0, .DET1_SIZE_CURRENT = 0x8, .DET2_SIZE = 0x0, .DET2_SIZE_CURRENT = 0x8, .DET3_SIZE = 0x0, .DET3_SIZE_CURRENT = 0x8, .COMPBUF_SIZE = 0x0, .COMPBUF_SIZE_CURRENT = 0x8, .CONFIG_ERROR = 0x1f, .COMPBUF_RESERVED_SPACE_64B = 0x0, .COMPBUF_RESERVED_SPACE_ZS = 0x10, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D = 0x0, .DCN_VM_FAULT_ADDR_MSB = 0x0, .DCN_VM_FAULT_ADDR_LSB = 0x0, .DCN_VM_ERROR_STATUS_CLEAR = 0x0, .DCN_VM_ERROR_STATUS_MODE = 0x1, .DCN_VM_ERROR_INTERRUPT_ENABLE = 0x2, .DCN_VM_RANGE_FAULT_DISABLE = 0x8, .DCN_VM_PRQ_FAULT_DISABLE = 0x9, .DCN_VM_ERROR_STATUS = 0x0, .DCN_VM_ERROR_VMID = 0x10 , .DCN_VM_ERROR_TABLE_LEVEL = 0x18, .DCN_VM_ERROR_PIPE = 0x1a , .DCN_VM_ERROR_INTERRUPT_STATUS = 0x1f | ||||
| 650 | }; | ||||
| 651 | |||||
| 652 | static const struct dcn_hubbub_mask hubbub_mask = { | ||||
| 653 | HUBBUB_MASK_SH_LIST_DCN31(_MASK).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0x00001000L, .DCHUBBUB_GLOBAL_SOFT_RESET = 0x00000001L, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x00000100L , .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE = 0x00000010L , .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x00000001L, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x00000002L, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE = 0x00000010L, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x00000020L , .DCHUBBUB_ARB_SAT_LEVEL = 0xFFFFFFFFL, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND = 0x001FF000L, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x00003FFFL , .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x00003FFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x00003FFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x00003FFFL , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x0000FFFFL , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x0000FFFFL , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x0000FFFFL , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x0000FFFFL , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x0000FFFFL , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x0000FFFFL , .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x0000FFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = 0x0000FFFFL, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, . FB_BASE = 0x00FFFFFFL, .FB_TOP = 0x00FFFFFFL, .FB_OFFSET = 0x00FFFFFFL , .AGP_BOT = 0x00FFFFFFL, .AGP_TOP = 0x00FFFFFFL, .AGP_BASE = 0x00FFFFFFL, .HOSTVM_INIT_REQ = 0x00000001L, .HVM_GPUVMRET_PWR_REQ_DIS = 0x00000001L, .HVM_GPUVMRET_FORCE_REQ = 0x0000000CL, .HVM_GPUVMRET_POWER_STATUS = 0x00000030L, .HVM_DISPCLK_R_GATE_DIS = 0x00000001L, .HVM_DISPCLK_G_GATE_DIS = 0x00000002L, .HVM_DCFCLK_R_GATE_DIS = 0x00000010L, .HVM_DCFCLK_G_GATE_DIS = 0x00000020L, .TR_REQ_REQCLKREQ_MODE = 0x00000300L, .TW_RSP_COMPCLKREQ_MODE = 0x00000C00L, .HOSTVM_PREFETCH_REQ = 0x00000001L, .HOSTVM_POWERSTATUS = 0x00000002L, .RIOMMU_ACTIVE = 0x00000001L, .HOSTVM_PREFETCH_DONE = 0x00000002L, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A = 0x000003FFL , .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D = 0x000003FFL , .DCHUBBUB_ARB_FRAC_URG_BW_NOM_A = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_B = 0x000003FFL, .DCHUBBUB_ARB_FRAC_URG_BW_NOM_C = 0x000003FFL , .DCHUBBUB_ARB_FRAC_URG_BW_NOM_D = 0x000003FFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A = 0x00003FFFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B = 0x00003FFFL , .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C = 0x00003FFFL, .DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D = 0x00003FFFL, .DET_DEPTH = 0x01FF0000L, .DET0_SIZE = 0x00000007L , .DET0_SIZE_CURRENT = 0x00000700L, .DET1_SIZE = 0x00000007L, .DET1_SIZE_CURRENT = 0x00000700L, .DET2_SIZE = 0x00000007L, . DET2_SIZE_CURRENT = 0x00000700L, .DET3_SIZE = 0x00000007L, .DET3_SIZE_CURRENT = 0x00000700L, .COMPBUF_SIZE = 0x0000001FL, .COMPBUF_SIZE_CURRENT = 0x00001F00L, .CONFIG_ERROR = 0x80000000L, .COMPBUF_RESERVED_SPACE_64B = 0x00000FFFL, .COMPBUF_RESERVED_SPACE_ZS = 0x0FFF0000L, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A = 0x000FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B = 0x000FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C = 0x000FFFFFL , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D = 0x000FFFFFL, . DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A = 0x000FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B = 0x000FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C = 0x000FFFFFL , .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D = 0x000FFFFFL, . DCN_VM_FAULT_ADDR_MSB = 0x0000000FL, .DCN_VM_FAULT_ADDR_LSB = 0xFFFFFFFFL, .DCN_VM_ERROR_STATUS_CLEAR = 0x00000001L, .DCN_VM_ERROR_STATUS_MODE = 0x00000002L, .DCN_VM_ERROR_INTERRUPT_ENABLE = 0x00000004L, .DCN_VM_RANGE_FAULT_DISABLE = 0x00000100L, .DCN_VM_PRQ_FAULT_DISABLE = 0x00000200L, .DCN_VM_ERROR_STATUS = 0x0000FFFFL, .DCN_VM_ERROR_VMID = 0x000F0000L, .DCN_VM_ERROR_TABLE_LEVEL = 0x03000000L, .DCN_VM_ERROR_PIPE = 0x3C000000L, .DCN_VM_ERROR_INTERRUPT_STATUS = 0x80000000L | ||||
| 654 | }; | ||||
| 655 | |||||
| 656 | static const struct dccg_registers dccg_regs = { | ||||
| 657 | DCCG_REG_LIST_DCN31().DPPCLK_DTO_CTRL = 0x000000C0 + 0x00b6, .DPPCLK_DTO_PARAM[0] = 0x000000C0 + 0x0099, .DPPCLK_DTO_PARAM[1] = 0x000000C0 + 0x009a , .DPPCLK_DTO_PARAM[2] = 0x000000C0 + 0x009b, .DPPCLK_DTO_PARAM [3] = 0x000000C0 + 0x009c, .PHYASYMCLK_CLOCK_CNTL = 0x000034C0 + 0x0052, .PHYBSYMCLK_CLOCK_CNTL = 0x000034C0 + 0x0053, .PHYCSYMCLK_CLOCK_CNTL = 0x000034C0 + 0x0054, .PHYDSYMCLK_CLOCK_CNTL = 0x000034C0 + 0x0055, .PHYESYMCLK_CLOCK_CNTL = 0x000034C0 + 0x0056, .DPSTREAMCLK_CNTL = 0x000000C0 + 0x004a, .SYMCLK32_SE_CNTL = 0x000000C0 + 0x0065 , .SYMCLK32_LE_CNTL = 0x000000C0 + 0x0066, .OTG_PIXEL_RATE_CNTL [0] = 0x000000C0 + 0x0080, .OTG_PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .OTG_PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .OTG_PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008c, .DTBCLK_DTO_MODULO[0] = 0x000034C0 + 0x001f, .DTBCLK_DTO_MODULO[1] = 0x000034C0 + 0x0020, .DTBCLK_DTO_MODULO [2] = 0x000034C0 + 0x0021, .DTBCLK_DTO_MODULO[3] = 0x000034C0 + 0x0022, .DTBCLK_DTO_PHASE[0] = 0x000034C0 + 0x0018, .DTBCLK_DTO_PHASE [1] = 0x000034C0 + 0x0019, .DTBCLK_DTO_PHASE[2] = 0x000034C0 + 0x001a, .DTBCLK_DTO_PHASE[3] = 0x000034C0 + 0x001b, .DCCG_AUDIO_DTBCLK_DTO_MODULO = 0x000034C0 + 0x0062, .DCCG_AUDIO_DTBCLK_DTO_PHASE = 0x000034C0 + 0x0061, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DENTIST_DISPCLK_CNTL = 0x000000C0 + 0x0064, .DSCCLK0_DTO_PARAM = 0x000000C0 + 0x006c , .DSCCLK1_DTO_PARAM = 0x000000C0 + 0x006d, .DSCCLK2_DTO_PARAM = 0x000000C0 + 0x006e, .DSCCLK_DTO_CTRL = 0x000000C0 + 0x00a7 , .DCCG_GATE_DISABLE_CNTL2 = 0x000000C0 + 0x007c, .DCCG_GATE_DISABLE_CNTL3 = 0x000034C0 + 0x005a, .HDMISTREAMCLK0_DTO_PARAM = 0x000034C0 + 0x005b | ||||
| 658 | }; | ||||
| 659 | |||||
| 660 | static const struct dccg_shift dccg_shift = { | ||||
| 661 | DCCG_MASK_SH_LIST_DCN31(__SHIFT).DPPCLK_DTO_ENABLE[0] = 0x0, .DPPCLK_DTO_DB_EN[0] = 0x1, .DPPCLK_DTO_ENABLE [1] = 0x4, .DPPCLK_DTO_DB_EN[1] = 0x5, .DPPCLK_DTO_ENABLE[2] = 0x8, .DPPCLK_DTO_DB_EN[2] = 0x9, .DPPCLK_DTO_ENABLE[3] = 0xc , .DPPCLK_DTO_DB_EN[3] = 0xd, .DPPCLK0_DTO_PHASE = 0x0, .DPPCLK0_DTO_MODULO = 0x10, .PHYASYMCLK_FORCE_EN = 0x0, .PHYASYMCLK_FORCE_SRC_SEL = 0x4, .PHYBSYMCLK_FORCE_EN = 0x0, .PHYBSYMCLK_FORCE_SRC_SEL = 0x4, .PHYCSYMCLK_FORCE_EN = 0x0, .PHYCSYMCLK_FORCE_SRC_SEL = 0x4, .PHYDSYMCLK_FORCE_EN = 0x0, .PHYDSYMCLK_FORCE_SRC_SEL = 0x4, .PHYESYMCLK_FORCE_EN = 0x0, .PHYESYMCLK_FORCE_SRC_SEL = 0x4, .DPSTREAMCLK_PIPE0_EN = 0x1, .DPSTREAMCLK_PIPE1_EN = 0x2 , .DPSTREAMCLK_PIPE2_EN = 0x3, .DPSTREAMCLK_PIPE3_EN = 0x4, . SYMCLK32_SE0_SRC_SEL = 0x0, .SYMCLK32_SE1_SRC_SEL = 0x4, .SYMCLK32_SE2_SRC_SEL = 0x8, .SYMCLK32_SE3_SRC_SEL = 0xc, .SYMCLK32_SE0_EN = 0x3, . SYMCLK32_SE1_EN = 0x7, .SYMCLK32_SE2_EN = 0xb, .SYMCLK32_SE3_EN = 0xf, .SYMCLK32_LE0_SRC_SEL = 0x0, .SYMCLK32_LE1_SRC_SEL = 0x4 , .SYMCLK32_LE0_EN = 0x3, .SYMCLK32_LE1_EN = 0x7, .DTBCLK_DTO_ENABLE [0] = 0x3, .DTBCLK_DTO_ENABLE[1] = 0x3, .DTBCLK_DTO_ENABLE[2] = 0x3, .DTBCLK_DTO_ENABLE[3] = 0x3, .DTBCLKDTO_ENABLE_STATUS [0] = 0x6, .DTBCLKDTO_ENABLE_STATUS[1] = 0x6, .DTBCLKDTO_ENABLE_STATUS [2] = 0x6, .DTBCLKDTO_ENABLE_STATUS[3] = 0x6, .PIPE_DTO_SRC_SEL [0] = 0xc, .PIPE_DTO_SRC_SEL[1] = 0xc, .PIPE_DTO_SRC_SEL[2] = 0xc, .PIPE_DTO_SRC_SEL[3] = 0xc, .DTBCLK_DTO_DIV[0] = 0x1c, . DTBCLK_DTO_DIV[1] = 0x1c, .DTBCLK_DTO_DIV[2] = 0x1c, .DTBCLK_DTO_DIV [3] = 0x1c, .OTG_ADD_PIXEL[0] = 0x8, .OTG_ADD_PIXEL[1] = 0x8, .OTG_ADD_PIXEL[2] = 0x8, .OTG_ADD_PIXEL[3] = 0x8, .DCCG_AUDIO_DTO_SEL = 0x4, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x0, .DENTIST_DISPCLK_CHG_MODE = 0xf, .DSCCLK0_DTO_PHASE = 0x0, .DSCCLK0_DTO_MODULO = 0x10, .DSCCLK1_DTO_PHASE = 0x0, .DSCCLK1_DTO_MODULO = 0x10, .DSCCLK2_DTO_PHASE = 0x0, .DSCCLK2_DTO_MODULO = 0x10, .DSCCLK0_DTO_ENABLE = 0x0 , .DSCCLK1_DTO_ENABLE = 0x1, .DSCCLK2_DTO_ENABLE = 0x2, .PHYASYMCLK_GATE_DISABLE = 0x18, .PHYBSYMCLK_GATE_DISABLE = 0x19, .PHYCSYMCLK_GATE_DISABLE = 0x1a, .PHYDSYMCLK_GATE_DISABLE = 0x1b, .PHYESYMCLK_GATE_DISABLE = 0x1c, .DPSTREAMCLK_ROOT_GATE_DISABLE = 0x6, .DPSTREAMCLK_GATE_DISABLE = 0x7, .SYMCLK32_ROOT_SE0_GATE_DISABLE = 0x8, .SYMCLK32_ROOT_SE1_GATE_DISABLE = 0xa, .SYMCLK32_ROOT_SE2_GATE_DISABLE = 0xc, .SYMCLK32_ROOT_SE3_GATE_DISABLE = 0xe, .SYMCLK32_ROOT_LE0_GATE_DISABLE = 0x14, .SYMCLK32_ROOT_LE1_GATE_DISABLE = 0x16, .HDMISTREAMCLK0_DTO_PHASE = 0x0, .HDMISTREAMCLK0_DTO_MODULO = 0x10 | ||||
| 662 | }; | ||||
| 663 | |||||
| 664 | static const struct dccg_mask dccg_mask = { | ||||
| 665 | DCCG_MASK_SH_LIST_DCN31(_MASK).DPPCLK_DTO_ENABLE[0] = 0x00000001L, .DPPCLK_DTO_DB_EN[0] = 0x00000002L , .DPPCLK_DTO_ENABLE[1] = 0x00000010L, .DPPCLK_DTO_DB_EN[1] = 0x00000020L, .DPPCLK_DTO_ENABLE[2] = 0x00000100L, .DPPCLK_DTO_DB_EN [2] = 0x00000200L, .DPPCLK_DTO_ENABLE[3] = 0x00001000L, .DPPCLK_DTO_DB_EN [3] = 0x00002000L, .DPPCLK0_DTO_PHASE = 0x000000FFL, .DPPCLK0_DTO_MODULO = 0x00FF0000L, .PHYASYMCLK_FORCE_EN = 0x00000001L, .PHYASYMCLK_FORCE_SRC_SEL = 0x00000030L, .PHYBSYMCLK_FORCE_EN = 0x00000001L, .PHYBSYMCLK_FORCE_SRC_SEL = 0x00000030L, .PHYCSYMCLK_FORCE_EN = 0x00000001L, .PHYCSYMCLK_FORCE_SRC_SEL = 0x00000030L, .PHYDSYMCLK_FORCE_EN = 0x00000001L, .PHYDSYMCLK_FORCE_SRC_SEL = 0x00000030L, .PHYESYMCLK_FORCE_EN = 0x00000001L, .PHYESYMCLK_FORCE_SRC_SEL = 0x00000030L, .DPSTREAMCLK_PIPE0_EN = 0x00000002L, .DPSTREAMCLK_PIPE1_EN = 0x00000004L, .DPSTREAMCLK_PIPE2_EN = 0x00000008L, .DPSTREAMCLK_PIPE3_EN = 0x00000010L, .SYMCLK32_SE0_SRC_SEL = 0x00000007L, .SYMCLK32_SE1_SRC_SEL = 0x00000070L, .SYMCLK32_SE2_SRC_SEL = 0x00000700L, .SYMCLK32_SE3_SRC_SEL = 0x00007000L, .SYMCLK32_SE0_EN = 0x00000008L, .SYMCLK32_SE1_EN = 0x00000080L, .SYMCLK32_SE2_EN = 0x00000800L, .SYMCLK32_SE3_EN = 0x00008000L, .SYMCLK32_LE0_SRC_SEL = 0x00000007L, .SYMCLK32_LE1_SRC_SEL = 0x00000070L, .SYMCLK32_LE0_EN = 0x00000008L, .SYMCLK32_LE1_EN = 0x00000080L, .DTBCLK_DTO_ENABLE[0] = 0x00000008L, .DTBCLK_DTO_ENABLE [1] = 0x00000008L, .DTBCLK_DTO_ENABLE[2] = 0x00000008L, .DTBCLK_DTO_ENABLE [3] = 0x00000008L, .DTBCLKDTO_ENABLE_STATUS[0] = 0x00000040L, .DTBCLKDTO_ENABLE_STATUS[1] = 0x00000040L, .DTBCLKDTO_ENABLE_STATUS [2] = 0x00000040L, .DTBCLKDTO_ENABLE_STATUS[3] = 0x00000040L, .PIPE_DTO_SRC_SEL[0] = 0x00001000L, .PIPE_DTO_SRC_SEL[1] = 0x00001000L , .PIPE_DTO_SRC_SEL[2] = 0x00001000L, .PIPE_DTO_SRC_SEL[3] = 0x00001000L , .DTBCLK_DTO_DIV[0] = 0xF0000000L, .DTBCLK_DTO_DIV[1] = 0xF0000000L , .DTBCLK_DTO_DIV[2] = 0xF0000000L, .DTBCLK_DTO_DIV[3] = 0xF0000000L , .OTG_ADD_PIXEL[0] = 0x00000100L, .OTG_ADD_PIXEL[1] = 0x00000100L , .OTG_ADD_PIXEL[2] = 0x00000100L, .OTG_ADD_PIXEL[3] = 0x00000100L , .DCCG_AUDIO_DTO_SEL = 0x00000070L, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x00000007L, .DENTIST_DISPCLK_CHG_MODE = 0x00018000L, .DSCCLK0_DTO_PHASE = 0x000000FFL, .DSCCLK0_DTO_MODULO = 0x00FF0000L, .DSCCLK1_DTO_PHASE = 0x000000FFL, .DSCCLK1_DTO_MODULO = 0x00FF0000L, .DSCCLK2_DTO_PHASE = 0x000000FFL, .DSCCLK2_DTO_MODULO = 0x00FF0000L, .DSCCLK0_DTO_ENABLE = 0x00000001L, .DSCCLK1_DTO_ENABLE = 0x00000002L, .DSCCLK2_DTO_ENABLE = 0x00000004L, .PHYASYMCLK_GATE_DISABLE = 0x01000000L, .PHYBSYMCLK_GATE_DISABLE = 0x02000000L, .PHYCSYMCLK_GATE_DISABLE = 0x04000000L, .PHYDSYMCLK_GATE_DISABLE = 0x08000000L, .PHYESYMCLK_GATE_DISABLE = 0x10000000L, .DPSTREAMCLK_ROOT_GATE_DISABLE = 0x00000040L, .DPSTREAMCLK_GATE_DISABLE = 0x00000080L, .SYMCLK32_ROOT_SE0_GATE_DISABLE = 0x00000100L, .SYMCLK32_ROOT_SE1_GATE_DISABLE = 0x00000400L , .SYMCLK32_ROOT_SE2_GATE_DISABLE = 0x00001000L, .SYMCLK32_ROOT_SE3_GATE_DISABLE = 0x00004000L, .SYMCLK32_ROOT_LE0_GATE_DISABLE = 0x00100000L , .SYMCLK32_ROOT_LE1_GATE_DISABLE = 0x00400000L, .HDMISTREAMCLK0_DTO_PHASE = 0x000000FFL, .HDMISTREAMCLK0_DTO_MODULO = 0x00FF0000L | ||||
| 666 | }; | ||||
| 667 | |||||
| 668 | |||||
| 669 | #define SRII2(reg_name_pre, reg_name_post, id).reg_name_pre_reg_name_post[id] = DCN_BASE__INST0_SEGregreg_name_preid_reg_name_post_BASE_IDX + regreg_name_preid_reg_name_post\ | ||||
| 670 | .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \DCN_BASE__INST0_SEGreg ## reg_name_pre ## id ## _ ## reg_name_post ## _BASE_IDX | ||||
| 671 | ## id ## _ ## reg_name_post ## _BASE_IDX)DCN_BASE__INST0_SEGreg ## reg_name_pre ## id ## _ ## reg_name_post ## _BASE_IDX + \ | ||||
| 672 | reg ## reg_name_pre ## id ## _ ## reg_name_post | ||||
| 673 | |||||
| 674 | |||||
| 675 | #define HWSEQ_DCN31_REG_LIST().DCHUBBUB_GLOBAL_TIMER_CNTL = 0x000034C0 + 0x0524, .DCHUBBUB_ARB_HOSTVM_CNTL = 0x000034C0 + 0x0521, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .ODM_MEM_PWR_CTRL3 = 0x000034C0 + 0x1e2f, .DMU_MEM_PWR_CNTL = 0x000034C0 + 0x00cc, .MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x0340, .DCCG_GATE_DISABLE_CNTL = 0x000000C0 + 0x0074, .DCCG_GATE_DISABLE_CNTL2 = 0x000000C0 + 0x007c, .DCFCLK_CNTL = 0x000034C0 + 0x0533, . DC_MEM_GLOBAL_PWR_REQ_CNTL = 0x000000C0 + 0x0072, .PIXEL_RATE_CNTL [0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008c, .PHYPLL_PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0083, .PHYPLL_PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0087, . PHYPLL_PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x008b, .PHYPLL_PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008f, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .MILLISECOND_TIME_BASE_DIV = 0x000000C0 + 0x0070, . DISPCLK_FREQ_CHANGE_CNTL = 0x000000C0 + 0x0071, .RBBMIF_TIMEOUT_DIS = 0x000034C0 + 0x0183, .RBBMIF_TIMEOUT_DIS_2 = 0x000034C0 + 0x0184 , .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04c2, .DPP_TOP0_DPP_CRC_CTRL = 0x000034C0 + 0x0cc9, .DPP_TOP0_DPP_CRC_VAL_B_A = 0x000034C0 + 0x0cc8, .DPP_TOP0_DPP_CRC_VAL_R_G = 0x000034C0 + 0x0cc7, . MPC_CRC_CTRL = 0x00009000 + 0x0502, .MPC_CRC_RESULT_GB = 0x00009000 + 0x0505, .MPC_CRC_RESULT_C = 0x00009000 + 0x0506, .MPC_CRC_RESULT_AR = 0x00009000 + 0x0504, .DOMAIN0_PG_CONFIG = 0x000034C0 + 0x0080 , .DOMAIN1_PG_CONFIG = 0x000034C0 + 0x0082, .DOMAIN2_PG_CONFIG = 0x000034C0 + 0x0084, .DOMAIN3_PG_CONFIG = 0x000034C0 + 0x0086 , .DOMAIN16_PG_CONFIG = 0x000034C0 + 0x0089, .DOMAIN17_PG_CONFIG = 0x000034C0 + 0x008b, .DOMAIN18_PG_CONFIG = 0x000034C0 + 0x008d , .DOMAIN0_PG_STATUS = 0x000034C0 + 0x0081, .DOMAIN1_PG_STATUS = 0x000034C0 + 0x0083, .DOMAIN2_PG_STATUS = 0x000034C0 + 0x0085 , .DOMAIN3_PG_STATUS = 0x000034C0 + 0x0087, .DOMAIN16_PG_STATUS = 0x000034C0 + 0x008a, .DOMAIN17_PG_STATUS = 0x000034C0 + 0x008c , .DOMAIN18_PG_STATUS = 0x000034C0 + 0x008e, .D1VGA_CONTROL = 0x000000C0 + 0x000c, .D2VGA_CONTROL = 0x000000C0 + 0x000e, . D3VGA_CONTROL = 0x000000C0 + 0x0038, .D4VGA_CONTROL = 0x000000C0 + 0x0039, .D5VGA_CONTROL = 0x000000C0 + 0x003a, .D6VGA_CONTROL = 0x000000C0 + 0x003b, .DC_IP_REQUEST_CNTL = 0x000034C0 + 0x0093 , .AZALIA_AUDIO_DTO = 0x000034C0 + 0x03c3, .AZALIA_CONTROLLER_CLOCK_GATING = 0x000034C0 + 0x03c2, .HPO_TOP_HW_CONTROL = 0x00009000 + 0x0e4a\ | ||||
| 676 | SR(DCHUBBUB_GLOBAL_TIMER_CNTL).DCHUBBUB_GLOBAL_TIMER_CNTL = 0x000034C0 + 0x0524, \ | ||||
| 677 | SR(DCHUBBUB_ARB_HOSTVM_CNTL).DCHUBBUB_ARB_HOSTVM_CNTL = 0x000034C0 + 0x0521, \ | ||||
| 678 | SR(DIO_MEM_PWR_CTRL).DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede, \ | ||||
| 679 | SR(ODM_MEM_PWR_CTRL3).ODM_MEM_PWR_CTRL3 = 0x000034C0 + 0x1e2f, \ | ||||
| 680 | SR(DMU_MEM_PWR_CNTL).DMU_MEM_PWR_CNTL = 0x000034C0 + 0x00cc, \ | ||||
| 681 | SR(MMHUBBUB_MEM_PWR_CNTL).MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x0340, \ | ||||
| 682 | SR(DCCG_GATE_DISABLE_CNTL).DCCG_GATE_DISABLE_CNTL = 0x000000C0 + 0x0074, \ | ||||
| 683 | SR(DCCG_GATE_DISABLE_CNTL2).DCCG_GATE_DISABLE_CNTL2 = 0x000000C0 + 0x007c, \ | ||||
| 684 | SR(DCFCLK_CNTL).DCFCLK_CNTL = 0x000034C0 + 0x0533,\ | ||||
| 685 | SR(DC_MEM_GLOBAL_PWR_REQ_CNTL).DC_MEM_GLOBAL_PWR_REQ_CNTL = 0x000000C0 + 0x0072, \ | ||||
| 686 | SRII(PIXEL_RATE_CNTL, OTG, 0).PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, \ | ||||
| 687 | SRII(PIXEL_RATE_CNTL, OTG, 1).PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084,\ | ||||
| 688 | SRII(PIXEL_RATE_CNTL, OTG, 2).PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088,\ | ||||
| 689 | SRII(PIXEL_RATE_CNTL, OTG, 3).PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c,\ | ||||
| 690 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0).PHYPLL_PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0083,\ | ||||
| 691 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1).PHYPLL_PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0087,\ | ||||
| 692 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2).PHYPLL_PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x008b,\ | ||||
| 693 | SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3).PHYPLL_PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008f,\ | ||||
| 694 | SR(MICROSECOND_TIME_BASE_DIV).MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, \ | ||||
| 695 | SR(MILLISECOND_TIME_BASE_DIV).MILLISECOND_TIME_BASE_DIV = 0x000000C0 + 0x0070, \ | ||||
| 696 | SR(DISPCLK_FREQ_CHANGE_CNTL).DISPCLK_FREQ_CHANGE_CNTL = 0x000000C0 + 0x0071, \ | ||||
| 697 | SR(RBBMIF_TIMEOUT_DIS).RBBMIF_TIMEOUT_DIS = 0x000034C0 + 0x0183, \ | ||||
| 698 | SR(RBBMIF_TIMEOUT_DIS_2).RBBMIF_TIMEOUT_DIS_2 = 0x000034C0 + 0x0184, \ | ||||
| 699 | SR(DCHUBBUB_CRC_CTRL).DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04c2, \ | ||||
| 700 | SR(DPP_TOP0_DPP_CRC_CTRL).DPP_TOP0_DPP_CRC_CTRL = 0x000034C0 + 0x0cc9, \ | ||||
| 701 | SR(DPP_TOP0_DPP_CRC_VAL_B_A).DPP_TOP0_DPP_CRC_VAL_B_A = 0x000034C0 + 0x0cc8, \ | ||||
| 702 | SR(DPP_TOP0_DPP_CRC_VAL_R_G).DPP_TOP0_DPP_CRC_VAL_R_G = 0x000034C0 + 0x0cc7, \ | ||||
| 703 | SR(MPC_CRC_CTRL).MPC_CRC_CTRL = 0x00009000 + 0x0502, \ | ||||
| 704 | SR(MPC_CRC_RESULT_GB).MPC_CRC_RESULT_GB = 0x00009000 + 0x0505, \ | ||||
| 705 | SR(MPC_CRC_RESULT_C).MPC_CRC_RESULT_C = 0x00009000 + 0x0506, \ | ||||
| 706 | SR(MPC_CRC_RESULT_AR).MPC_CRC_RESULT_AR = 0x00009000 + 0x0504, \ | ||||
| 707 | SR(DOMAIN0_PG_CONFIG).DOMAIN0_PG_CONFIG = 0x000034C0 + 0x0080, \ | ||||
| 708 | SR(DOMAIN1_PG_CONFIG).DOMAIN1_PG_CONFIG = 0x000034C0 + 0x0082, \ | ||||
| 709 | SR(DOMAIN2_PG_CONFIG).DOMAIN2_PG_CONFIG = 0x000034C0 + 0x0084, \ | ||||
| 710 | SR(DOMAIN3_PG_CONFIG).DOMAIN3_PG_CONFIG = 0x000034C0 + 0x0086, \ | ||||
| 711 | SR(DOMAIN16_PG_CONFIG).DOMAIN16_PG_CONFIG = 0x000034C0 + 0x0089, \ | ||||
| 712 | SR(DOMAIN17_PG_CONFIG).DOMAIN17_PG_CONFIG = 0x000034C0 + 0x008b, \ | ||||
| 713 | SR(DOMAIN18_PG_CONFIG).DOMAIN18_PG_CONFIG = 0x000034C0 + 0x008d, \ | ||||
| 714 | SR(DOMAIN0_PG_STATUS).DOMAIN0_PG_STATUS = 0x000034C0 + 0x0081, \ | ||||
| 715 | SR(DOMAIN1_PG_STATUS).DOMAIN1_PG_STATUS = 0x000034C0 + 0x0083, \ | ||||
| 716 | SR(DOMAIN2_PG_STATUS).DOMAIN2_PG_STATUS = 0x000034C0 + 0x0085, \ | ||||
| 717 | SR(DOMAIN3_PG_STATUS).DOMAIN3_PG_STATUS = 0x000034C0 + 0x0087, \ | ||||
| 718 | SR(DOMAIN16_PG_STATUS).DOMAIN16_PG_STATUS = 0x000034C0 + 0x008a, \ | ||||
| 719 | SR(DOMAIN17_PG_STATUS).DOMAIN17_PG_STATUS = 0x000034C0 + 0x008c, \ | ||||
| 720 | SR(DOMAIN18_PG_STATUS).DOMAIN18_PG_STATUS = 0x000034C0 + 0x008e, \ | ||||
| 721 | SR(D1VGA_CONTROL).D1VGA_CONTROL = 0x000000C0 + 0x000c, \ | ||||
| 722 | SR(D2VGA_CONTROL).D2VGA_CONTROL = 0x000000C0 + 0x000e, \ | ||||
| 723 | SR(D3VGA_CONTROL).D3VGA_CONTROL = 0x000000C0 + 0x0038, \ | ||||
| 724 | SR(D4VGA_CONTROL).D4VGA_CONTROL = 0x000000C0 + 0x0039, \ | ||||
| 725 | SR(D5VGA_CONTROL).D5VGA_CONTROL = 0x000000C0 + 0x003a, \ | ||||
| 726 | SR(D6VGA_CONTROL).D6VGA_CONTROL = 0x000000C0 + 0x003b, \ | ||||
| 727 | SR(DC_IP_REQUEST_CNTL).DC_IP_REQUEST_CNTL = 0x000034C0 + 0x0093, \ | ||||
| 728 | SR(AZALIA_AUDIO_DTO).AZALIA_AUDIO_DTO = 0x000034C0 + 0x03c3, \ | ||||
| 729 | SR(AZALIA_CONTROLLER_CLOCK_GATING).AZALIA_CONTROLLER_CLOCK_GATING = 0x000034C0 + 0x03c2, \ | ||||
| 730 | SR(HPO_TOP_HW_CONTROL).HPO_TOP_HW_CONTROL = 0x00009000 + 0x0e4a | ||||
| 731 | |||||
| 732 | static const struct dce_hwseq_registers hwseq_reg = { | ||||
| 733 | HWSEQ_DCN31_REG_LIST().DCHUBBUB_GLOBAL_TIMER_CNTL = 0x000034C0 + 0x0524, .DCHUBBUB_ARB_HOSTVM_CNTL = 0x000034C0 + 0x0521, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .ODM_MEM_PWR_CTRL3 = 0x000034C0 + 0x1e2f, .DMU_MEM_PWR_CNTL = 0x000034C0 + 0x00cc, .MMHUBBUB_MEM_PWR_CNTL = 0x000034C0 + 0x0340, .DCCG_GATE_DISABLE_CNTL = 0x000000C0 + 0x0074, .DCCG_GATE_DISABLE_CNTL2 = 0x000000C0 + 0x007c, .DCFCLK_CNTL = 0x000034C0 + 0x0533, . DC_MEM_GLOBAL_PWR_REQ_CNTL = 0x000000C0 + 0x0072, .PIXEL_RATE_CNTL [0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008c, .PHYPLL_PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0083, .PHYPLL_PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0087, . PHYPLL_PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x008b, .PHYPLL_PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008f, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .MILLISECOND_TIME_BASE_DIV = 0x000000C0 + 0x0070, . DISPCLK_FREQ_CHANGE_CNTL = 0x000000C0 + 0x0071, .RBBMIF_TIMEOUT_DIS = 0x000034C0 + 0x0183, .RBBMIF_TIMEOUT_DIS_2 = 0x000034C0 + 0x0184 , .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04c2, .DPP_TOP0_DPP_CRC_CTRL = 0x000034C0 + 0x0cc9, .DPP_TOP0_DPP_CRC_VAL_B_A = 0x000034C0 + 0x0cc8, .DPP_TOP0_DPP_CRC_VAL_R_G = 0x000034C0 + 0x0cc7, . MPC_CRC_CTRL = 0x00009000 + 0x0502, .MPC_CRC_RESULT_GB = 0x00009000 + 0x0505, .MPC_CRC_RESULT_C = 0x00009000 + 0x0506, .MPC_CRC_RESULT_AR = 0x00009000 + 0x0504, .DOMAIN0_PG_CONFIG = 0x000034C0 + 0x0080 , .DOMAIN1_PG_CONFIG = 0x000034C0 + 0x0082, .DOMAIN2_PG_CONFIG = 0x000034C0 + 0x0084, .DOMAIN3_PG_CONFIG = 0x000034C0 + 0x0086 , .DOMAIN16_PG_CONFIG = 0x000034C0 + 0x0089, .DOMAIN17_PG_CONFIG = 0x000034C0 + 0x008b, .DOMAIN18_PG_CONFIG = 0x000034C0 + 0x008d , .DOMAIN0_PG_STATUS = 0x000034C0 + 0x0081, .DOMAIN1_PG_STATUS = 0x000034C0 + 0x0083, .DOMAIN2_PG_STATUS = 0x000034C0 + 0x0085 , .DOMAIN3_PG_STATUS = 0x000034C0 + 0x0087, .DOMAIN16_PG_STATUS = 0x000034C0 + 0x008a, .DOMAIN17_PG_STATUS = 0x000034C0 + 0x008c , .DOMAIN18_PG_STATUS = 0x000034C0 + 0x008e, .D1VGA_CONTROL = 0x000000C0 + 0x000c, .D2VGA_CONTROL = 0x000000C0 + 0x000e, . D3VGA_CONTROL = 0x000000C0 + 0x0038, .D4VGA_CONTROL = 0x000000C0 + 0x0039, .D5VGA_CONTROL = 0x000000C0 + 0x003a, .D6VGA_CONTROL = 0x000000C0 + 0x003b, .DC_IP_REQUEST_CNTL = 0x000034C0 + 0x0093 , .AZALIA_AUDIO_DTO = 0x000034C0 + 0x03c3, .AZALIA_CONTROLLER_CLOCK_GATING = 0x000034C0 + 0x03c2, .HPO_TOP_HW_CONTROL = 0x00009000 + 0x0e4a | ||||
| 734 | }; | ||||
| 735 | |||||
| 736 | #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh).PIXEL_RATE_SOURCE = OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCEmask_sh , .DP_DTO0_ENABLE = OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLEmask_sh , .PHYPLL_PIXEL_RATE_SOURCE = OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCEmask_sh , .DCHUBBUB_GLOBAL_TIMER_ENABLE = DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLEmask_sh , .DCFCLK_GATE_DIS = DCFCLK_CNTL__DCFCLK_GATE_DISmask_sh, .DC_MEM_GLOBAL_PWR_REQ_DIS = DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DISmask_sh , .DCHUBBUB_GLOBAL_TIMER_REFDIV = DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIVmask_sh , .DISABLE_HOSTVM_FORCE_ALLOW_PSTATE = DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_POWER_FORCEON = DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh , .DOMAIN_POWER_GATE = DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATEmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .DOMAIN_PGFSM_PWR_STATUS = DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh , .IP_REQUEST_EN = DC_IP_REQUEST_CNTL__IP_REQUEST_ENmask_sh, . AZALIA_AUDIO_DTO_MODULE = AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULEmask_sh , .HPO_HDMISTREAMCLK_G_GATE_DIS = HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DISmask_sh , .DMCU_ERAM_MEM_PWR_FORCE = DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCEmask_sh , .ODM_MEM_UNASSIGNED_PWR_MODE = ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODEmask_sh , .ODM_MEM_VBLANK_PWR_MODE = ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODEmask_sh , .VGA_MEM_PWR_FORCE = MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCEmask_sh , .I2C_LIGHT_SLEEP_FORCE = DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCEmask_sh , .HPO_IO_EN = HPO_TOP_HW_CONTROL__HPO_IO_ENmask_sh\ | ||||
| 737 | HWSEQ_DCN_MASK_SH_LIST(mask_sh).PIXEL_RATE_SOURCE = OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCEmask_sh , .DP_DTO0_ENABLE = OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLEmask_sh , .PHYPLL_PIXEL_RATE_SOURCE = OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCEmask_sh , .DCHUBBUB_GLOBAL_TIMER_ENABLE = DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLEmask_sh , .DCFCLK_GATE_DIS = DCFCLK_CNTL__DCFCLK_GATE_DISmask_sh, .DC_MEM_GLOBAL_PWR_REQ_DIS = DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DISmask_sh, \ | ||||
| 738 | HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh).DCHUBBUB_GLOBAL_TIMER_REFDIV = DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIVmask_sh, \ | ||||
| 739 | HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh).DISABLE_HOSTVM_FORCE_ALLOW_PSTATE = DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATEmask_sh, \ | ||||
| 740 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ | ||||
| 741 | HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ | ||||
| 742 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ | ||||
| 743 | HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ | ||||
| 744 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ | ||||
| 745 | HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ | ||||
| 746 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ | ||||
| 747 | HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ | ||||
| 748 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ | ||||
| 749 | HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ | ||||
| 750 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ | ||||
| 751 | HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ | ||||
| 752 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh).DOMAIN_POWER_FORCEON = DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEONmask_sh, \ | ||||
| 753 | HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh).DOMAIN_POWER_GATE = DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATEmask_sh, \ | ||||
| 754 | HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ | ||||
| 755 | HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ | ||||
| 756 | HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ | ||||
| 757 | HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ | ||||
| 758 | HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ | ||||
| 759 | HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ | ||||
| 760 | HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh).DOMAIN_PGFSM_PWR_STATUS = DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUSmask_sh, \ | ||||
| 761 | HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh).IP_REQUEST_EN = DC_IP_REQUEST_CNTL__IP_REQUEST_ENmask_sh, \ | ||||
| 762 | HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh).AZALIA_AUDIO_DTO_MODULE = AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULEmask_sh, \ | ||||
| 763 | HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh).HPO_HDMISTREAMCLK_G_GATE_DIS = HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DISmask_sh, \ | ||||
| 764 | HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh).DMCU_ERAM_MEM_PWR_FORCE = DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCEmask_sh, \ | ||||
| 765 | HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh).ODM_MEM_UNASSIGNED_PWR_MODE = ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODEmask_sh, \ | ||||
| 766 | HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh).ODM_MEM_VBLANK_PWR_MODE = ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODEmask_sh, \ | ||||
| 767 | HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh).VGA_MEM_PWR_FORCE = MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCEmask_sh, \ | ||||
| 768 | HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh).I2C_LIGHT_SLEEP_FORCE = DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCEmask_sh, \ | ||||
| 769 | HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh).HPO_IO_EN = HPO_TOP_HW_CONTROL__HPO_IO_ENmask_sh | ||||
| 770 | |||||
| 771 | static const struct dce_hwseq_shift hwseq_shift = { | ||||
| 772 | HWSEQ_DCN31_MASK_SH_LIST(__SHIFT).PIXEL_RATE_SOURCE = 0x0, .DP_DTO0_ENABLE = 0x4, .PHYPLL_PIXEL_RATE_SOURCE = 0x0, .DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCFCLK_GATE_DIS = 0x1f, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0, .DISABLE_HOSTVM_FORCE_ALLOW_PSTATE = 0x1, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0 , .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8 , .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0, .DOMAIN_POWER_GATE = 0x8, .DOMAIN_POWER_FORCEON = 0x0 , .DOMAIN_POWER_GATE = 0x8, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, . DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e , .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .DOMAIN_PGFSM_PWR_STATUS = 0x1e, .IP_REQUEST_EN = 0x0, .AZALIA_AUDIO_DTO_MODULE = 0x10 , .HPO_HDMISTREAMCLK_G_GATE_DIS = 0x9, .DMCU_ERAM_MEM_PWR_FORCE = 0x1, .ODM_MEM_UNASSIGNED_PWR_MODE = 0x0, .ODM_MEM_VBLANK_PWR_MODE = 0x2, .VGA_MEM_PWR_FORCE = 0x0, .I2C_LIGHT_SLEEP_FORCE = 0x0 , .HPO_IO_EN = 0x0 | ||||
| 773 | }; | ||||
| 774 | |||||
| 775 | static const struct dce_hwseq_mask hwseq_mask = { | ||||
| 776 | HWSEQ_DCN31_MASK_SH_LIST(_MASK).PIXEL_RATE_SOURCE = 0x00000003L, .DP_DTO0_ENABLE = 0x00000010L , .PHYPLL_PIXEL_RATE_SOURCE = 0x00000007L, .DCHUBBUB_GLOBAL_TIMER_ENABLE = 0x00001000L, .DCFCLK_GATE_DIS = 0x80000000L, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x00000001L, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, . DISABLE_HOSTVM_FORCE_ALLOW_PSTATE = 0x00000002L, .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L, .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L, .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L, .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L, .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L, .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L, .DOMAIN_POWER_FORCEON = 0x00000001L, .DOMAIN_POWER_GATE = 0x00000100L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN_PGFSM_PWR_STATUS = 0xC0000000L, .IP_REQUEST_EN = 0x00000001L, .AZALIA_AUDIO_DTO_MODULE = 0xFFFF0000L, .HPO_HDMISTREAMCLK_G_GATE_DIS = 0x00000200L, . DMCU_ERAM_MEM_PWR_FORCE = 0x00000006L, .ODM_MEM_UNASSIGNED_PWR_MODE = 0x00000003L, .ODM_MEM_VBLANK_PWR_MODE = 0x0000000CL, .VGA_MEM_PWR_FORCE = 0x00000001L, .I2C_LIGHT_SLEEP_FORCE = 0x00000001L, .HPO_IO_EN = 0x00000001L | ||||
| 777 | }; | ||||
| 778 | #define vmid_regs(id)[id] = { .CNTL = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_CNTL_BASE_IDX + regDCN_VM_CONTEXTid_CNTL, .PAGE_TABLE_BASE_ADDR_HI32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32, .PAGE_TABLE_BASE_ADDR_LO32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32, .PAGE_TABLE_START_ADDR_HI32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32, .PAGE_TABLE_START_ADDR_LO32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32, .PAGE_TABLE_END_ADDR_HI32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32, .PAGE_TABLE_END_ADDR_LO32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32}\ | ||||
| 779 | [id] = {\ | ||||
| 780 | DCN20_VMID_REG_LIST(id).CNTL = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_CNTL_BASE_IDX + regDCN_VM_CONTEXTid_CNTL, .PAGE_TABLE_BASE_ADDR_HI32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32, .PAGE_TABLE_BASE_ADDR_LO32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32, .PAGE_TABLE_START_ADDR_HI32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32, .PAGE_TABLE_START_ADDR_LO32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32, .PAGE_TABLE_END_ADDR_HI32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32, .PAGE_TABLE_END_ADDR_LO32 = DCN_BASE__INST0_SEGregDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32_BASE_IDX + regDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32\ | ||||
| 781 | } | ||||
| 782 | |||||
| 783 | static const struct dcn_vmid_registers vmid_regs[] = { | ||||
| 784 | vmid_regs(0)[0] = { .CNTL = 0x000034C0 + 0x0559, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x055a, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x055b, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x055c, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x055d, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x055e, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x055f}, | ||||
| 785 | vmid_regs(1)[1] = { .CNTL = 0x000034C0 + 0x0560, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0561, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0562, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0563, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0564, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0565, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0566}, | ||||
| 786 | vmid_regs(2)[2] = { .CNTL = 0x000034C0 + 0x0567, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0568, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0569, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x056a, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x056b, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x056c, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x056d}, | ||||
| 787 | vmid_regs(3)[3] = { .CNTL = 0x000034C0 + 0x056e, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x056f, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0570, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0571, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0572, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0573, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0574}, | ||||
| 788 | vmid_regs(4)[4] = { .CNTL = 0x000034C0 + 0x0575, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0576, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0577, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0578, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0579, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x057a, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x057b}, | ||||
| 789 | vmid_regs(5)[5] = { .CNTL = 0x000034C0 + 0x057c, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x057d, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x057e, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x057f, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0580, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0581, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0582}, | ||||
| 790 | vmid_regs(6)[6] = { .CNTL = 0x000034C0 + 0x0583, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0584, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0585, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0586, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0587, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0588, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0589}, | ||||
| 791 | vmid_regs(7)[7] = { .CNTL = 0x000034C0 + 0x058a, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x058b, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x058c, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x058d, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x058e, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x058f, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0590}, | ||||
| 792 | vmid_regs(8)[8] = { .CNTL = 0x000034C0 + 0x0591, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0592, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0593, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0594, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0595, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0596, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0597}, | ||||
| 793 | vmid_regs(9)[9] = { .CNTL = 0x000034C0 + 0x0598, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0599, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x059a, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x059b, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x059c, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x059d, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x059e}, | ||||
| 794 | vmid_regs(10)[10] = { .CNTL = 0x000034C0 + 0x059f, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05a0, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05a1, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05a2, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05a3, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05a4, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05a5}, | ||||
| 795 | vmid_regs(11)[11] = { .CNTL = 0x000034C0 + 0x05a6, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05a7, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05a8, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05a9, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05aa, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05ab, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05ac}, | ||||
| 796 | vmid_regs(12)[12] = { .CNTL = 0x000034C0 + 0x05ad, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05ae, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05af, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05b0, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05b1, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05b2, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05b3}, | ||||
| 797 | vmid_regs(13)[13] = { .CNTL = 0x000034C0 + 0x05b4, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05b5, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05b6, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05b7, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05b8, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05b9, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05ba}, | ||||
| 798 | vmid_regs(14)[14] = { .CNTL = 0x000034C0 + 0x05bb, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05bc, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05bd, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05be, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05bf, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05c0, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05c1}, | ||||
| 799 | vmid_regs(15)[15] = { .CNTL = 0x000034C0 + 0x05c2, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05c3, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05c4, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05c5, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05c6, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05c7, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05c8} | ||||
| 800 | }; | ||||
| 801 | |||||
| 802 | static const struct dcn20_vmid_shift vmid_shifts = { | ||||
| 803 | DCN20_VMID_MASK_SH_LIST(__SHIFT).VM_CONTEXT0_PAGE_TABLE_DEPTH = 0x1, .VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE = 0x3, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 = 0x0, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 = 0x0, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 = 0x0, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 = 0x0, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 = 0x0, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 = 0x0 | ||||
| 804 | }; | ||||
| 805 | |||||
| 806 | static const struct dcn20_vmid_mask vmid_masks = { | ||||
| 807 | DCN20_VMID_MASK_SH_LIST(_MASK).VM_CONTEXT0_PAGE_TABLE_DEPTH = 0x00000006L, .VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE = 0x00000078L, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 = 0xFFFFFFFFL , .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 = 0xFFFFFFFFL, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 = 0x0000000FL, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 = 0xFFFFFFFFL, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 = 0x0000000FL , .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 = 0xFFFFFFFFL | ||||
| 808 | }; | ||||
| 809 | |||||
| 810 | static const struct resource_caps res_cap_dcn31 = { | ||||
| 811 | .num_timing_generator = 4, | ||||
| 812 | .num_opp = 4, | ||||
| 813 | .num_video_plane = 4, | ||||
| 814 | .num_audio = 5, | ||||
| 815 | .num_stream_encoder = 5, | ||||
| 816 | .num_dig_link_enc = 5, | ||||
| 817 | .num_hpo_dp_stream_encoder = 4, | ||||
| 818 | .num_hpo_dp_link_encoder = 2, | ||||
| 819 | .num_pll = 5, | ||||
| 820 | .num_dwb = 1, | ||||
| 821 | .num_ddc = 5, | ||||
| 822 | .num_vmid = 16, | ||||
| 823 | .num_mpc_3dlut = 2, | ||||
| 824 | .num_dsc = 3, | ||||
| 825 | }; | ||||
| 826 | |||||
| 827 | static const struct dc_plane_cap plane_cap = { | ||||
| 828 | .type = DC_PLANE_TYPE_DCN_UNIVERSAL, | ||||
| 829 | .blends_with_above = true1, | ||||
| 830 | .blends_with_below = true1, | ||||
| 831 | .per_pixel_alpha = true1, | ||||
| 832 | |||||
| 833 | .pixel_format_support = { | ||||
| 834 | .argb8888 = true1, | ||||
| 835 | .nv12 = true1, | ||||
| 836 | .fp16 = true1, | ||||
| 837 | .p010 = true1, | ||||
| 838 | .ayuv = false0, | ||||
| 839 | }, | ||||
| 840 | |||||
| 841 | .max_upscale_factor = { | ||||
| 842 | .argb8888 = 16000, | ||||
| 843 | .nv12 = 16000, | ||||
| 844 | .fp16 = 16000 | ||||
| 845 | }, | ||||
| 846 | |||||
| 847 | // 6:1 downscaling ratio: 1000/6 = 166.666 | ||||
| 848 | .max_downscale_factor = { | ||||
| 849 | .argb8888 = 167, | ||||
| 850 | .nv12 = 167, | ||||
| 851 | .fp16 = 167 | ||||
| 852 | }, | ||||
| 853 | 64, | ||||
| 854 | 64 | ||||
| 855 | }; | ||||
| 856 | |||||
| 857 | static const struct dc_debug_options debug_defaults_drv = { | ||||
| 858 | .disable_z10 = true1, /*hw not support it*/ | ||||
| 859 | .disable_dmcu = true1, | ||||
| 860 | .force_abm_enable = false0, | ||||
| 861 | .timing_trace = false0, | ||||
| 862 | .clock_trace = true1, | ||||
| 863 | .disable_pplib_clock_request = false0, | ||||
| 864 | .pipe_split_policy = MPC_SPLIT_DYNAMIC, | ||||
| 865 | .force_single_disp_pipe_split = false0, | ||||
| 866 | .disable_dcc = DCC_ENABLE, | ||||
| 867 | .vsr_support = true1, | ||||
| 868 | .performance_trace = false0, | ||||
| 869 | .max_downscale_src_width = 4096,/*upto true 4k*/ | ||||
| 870 | .disable_pplib_wm_range = false0, | ||||
| 871 | .scl_reset_length10 = true1, | ||||
| 872 | .sanity_checks = false0, | ||||
| 873 | .underflow_assert_delay_us = 0xFFFFFFFF, | ||||
| 874 | .dwb_fi_phase = -1, // -1 = disable, | ||||
| 875 | .dmub_command_table = true1, | ||||
| 876 | .pstate_enabled = true1, | ||||
| 877 | .use_max_lb = true1, | ||||
| 878 | .enable_mem_low_power = { | ||||
| 879 | .bits = { | ||||
| 880 | .vga = true1, | ||||
| 881 | .i2c = true1, | ||||
| 882 | .dmcu = false0, // This is previously known to cause hang on S3 cycles if enabled | ||||
| 883 | .dscl = true1, | ||||
| 884 | .cm = true1, | ||||
| 885 | .mpc = true1, | ||||
| 886 | .optc = true1, | ||||
| 887 | .vpg = true1, | ||||
| 888 | .afmt = true1, | ||||
| 889 | } | ||||
| 890 | }, | ||||
| 891 | .psr_power_use_phy_fsm = 0, | ||||
| 892 | }; | ||||
| 893 | |||||
| 894 | static const struct dc_debug_options debug_defaults_diags = { | ||||
| 895 | .disable_dmcu = true1, | ||||
| 896 | .force_abm_enable = false0, | ||||
| 897 | .timing_trace = true1, | ||||
| 898 | .clock_trace = true1, | ||||
| 899 | .disable_dpp_power_gate = true1, | ||||
| 900 | .disable_hubp_power_gate = true1, | ||||
| 901 | .disable_clock_gate = true1, | ||||
| 902 | .disable_pplib_clock_request = true1, | ||||
| 903 | .disable_pplib_wm_range = true1, | ||||
| 904 | .disable_stutter = false0, | ||||
| 905 | .scl_reset_length10 = true1, | ||||
| 906 | .dwb_fi_phase = -1, // -1 = disable | ||||
| 907 | .dmub_command_table = true1, | ||||
| 908 | .enable_tri_buf = true1, | ||||
| 909 | .use_max_lb = true1 | ||||
| 910 | }; | ||||
| 911 | |||||
| 912 | static const struct dc_panel_config panel_config_defaults = { | ||||
| 913 | .psr = { | ||||
| 914 | .disable_psr = false0, | ||||
| 915 | .disallow_psrsu = false0, | ||||
| 916 | }, | ||||
| 917 | .ilr = { | ||||
| 918 | .optimize_edp_link_rate = true1, | ||||
| 919 | }, | ||||
| 920 | }; | ||||
| 921 | |||||
| 922 | static void dcn31_dpp_destroy(struct dpp **dpp) | ||||
| 923 | { | ||||
| 924 | kfree(TO_DCN20_DPP(*dpp)({ const __typeof( ((struct dcn20_dpp *)0)->base ) *__mptr = (*dpp); (struct dcn20_dpp *)( (char *)__mptr - __builtin_offsetof (struct dcn20_dpp, base) );})); | ||||
| 925 | *dpp = NULL((void *)0); | ||||
| 926 | } | ||||
| 927 | |||||
| 928 | static struct dpp *dcn31_dpp_create( | ||||
| 929 | struct dc_context *ctx, | ||||
| 930 | uint32_t inst) | ||||
| 931 | { | ||||
| 932 | struct dcn3_dpp *dpp = | ||||
| 933 | kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 934 | |||||
| 935 | if (!dpp) | ||||
| 936 | return NULL((void *)0); | ||||
| 937 | |||||
| 938 | if (dpp3_construct(dpp, ctx, inst, | ||||
| 939 | &dpp_regs[inst], &tf_shift, &tf_mask)) | ||||
| 940 | return &dpp->base; | ||||
| 941 | |||||
| 942 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 942); do {} while (0); } while (0); | ||||
| 943 | kfree(dpp); | ||||
| 944 | return NULL((void *)0); | ||||
| 945 | } | ||||
| 946 | |||||
| 947 | static struct output_pixel_processor *dcn31_opp_create( | ||||
| 948 | struct dc_context *ctx, uint32_t inst) | ||||
| 949 | { | ||||
| 950 | struct dcn20_opp *opp = | ||||
| 951 | kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 952 | |||||
| 953 | if (!opp) { | ||||
| 954 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 954); do {} while (0); } while (0); | ||||
| 955 | return NULL((void *)0); | ||||
| 956 | } | ||||
| 957 | |||||
| 958 | dcn20_opp_construct(opp, ctx, inst, | ||||
| 959 | &opp_regs[inst], &opp_shift, &opp_mask); | ||||
| 960 | return &opp->base; | ||||
| 961 | } | ||||
| 962 | |||||
| 963 | static struct dce_aux *dcn31_aux_engine_create( | ||||
| 964 | struct dc_context *ctx, | ||||
| 965 | uint32_t inst) | ||||
| 966 | { | ||||
| 967 | struct aux_engine_dce110 *aux_engine = | ||||
| 968 | kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 969 | |||||
| 970 | if (!aux_engine) | ||||
| 971 | return NULL((void *)0); | ||||
| 972 | |||||
| 973 | dce110_aux_engine_construct(aux_engine, ctx, inst, | ||||
| 974 | SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, | ||||
| 975 | &aux_engine_regs[inst], | ||||
| 976 | &aux_mask, | ||||
| 977 | &aux_shift, | ||||
| 978 | ctx->dc->caps.extended_aux_timeout_support); | ||||
| 979 | |||||
| 980 | return &aux_engine->base; | ||||
| 981 | } | ||||
| 982 | #define i2c_inst_regs(id){ .SETUP = DCN_BASE__INST0_SEGregDC_I2C_DDCid_SETUP_BASE_IDX + regDC_I2C_DDCid_SETUP, .SPEED = DCN_BASE__INST0_SEGregDC_I2C_DDCid_SPEED_BASE_IDX + regDC_I2C_DDCid_SPEED, .HW_STATUS = DCN_BASE__INST0_SEGregDC_I2C_DDCid_HW_STATUS_BASE_IDX + regDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .DIO_MEM_PWR_STATUS = 0x000034C0 + 0x1edd } { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id).SETUP = DCN_BASE__INST0_SEGregDC_I2C_DDCid_SETUP_BASE_IDX + regDC_I2C_DDCid_SETUP , .SPEED = DCN_BASE__INST0_SEGregDC_I2C_DDCid_SPEED_BASE_IDX + regDC_I2C_DDCid_SPEED, .HW_STATUS = DCN_BASE__INST0_SEGregDC_I2C_DDCid_HW_STATUS_BASE_IDX + regDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .DIO_MEM_PWR_STATUS = 0x000034C0 + 0x1edd } | ||||
| 983 | |||||
| 984 | static const struct dce_i2c_registers i2c_hw_regs[] = { | ||||
| 985 | i2c_inst_regs(1){ .SETUP = 0x000034C0 + 0x1ea3, .SPEED = 0x000034C0 + 0x1ea2, .HW_STATUS = 0x000034C0 + 0x1e9c, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .DIO_MEM_PWR_STATUS = 0x000034C0 + 0x1edd }, | ||||
| 986 | i2c_inst_regs(2){ .SETUP = 0x000034C0 + 0x1ea5, .SPEED = 0x000034C0 + 0x1ea4, .HW_STATUS = 0x000034C0 + 0x1e9d, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .DIO_MEM_PWR_STATUS = 0x000034C0 + 0x1edd }, | ||||
| 987 | i2c_inst_regs(3){ .SETUP = 0x000034C0 + 0x1ea7, .SPEED = 0x000034C0 + 0x1ea6, .HW_STATUS = 0x000034C0 + 0x1e9e, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .DIO_MEM_PWR_STATUS = 0x000034C0 + 0x1edd }, | ||||
| 988 | i2c_inst_regs(4){ .SETUP = 0x000034C0 + 0x1ea9, .SPEED = 0x000034C0 + 0x1ea8, .HW_STATUS = 0x000034C0 + 0x1e9f, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .DIO_MEM_PWR_STATUS = 0x000034C0 + 0x1edd }, | ||||
| 989 | i2c_inst_regs(5){ .SETUP = 0x000034C0 + 0x1eab, .SPEED = 0x000034C0 + 0x1eaa, .HW_STATUS = 0x000034C0 + 0x1ea0, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .DIO_MEM_PWR_STATUS = 0x000034C0 + 0x1edd }, | ||||
| 990 | }; | ||||
| 991 | |||||
| 992 | static const struct dce_i2c_shift i2c_shifts = { | ||||
| 993 | I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT).DC_I2C_DDC1_ENABLE = 0x6, .DC_I2C_DDC1_TIME_LIMIT = 0x18, .DC_I2C_DDC1_DATA_DRIVE_EN = 0x0, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x7, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x1, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x10, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0x8, .DC_I2C_DDC1_HW_STATUS = 0x0, .DC_I2C_SW_USE_I2C_REG_REQ = 0x14, .DC_I2C_SW_DONE_USING_I2C_REG = 0x15, .DC_I2C_NO_QUEUED_SW_GO = 0x4, .DC_I2C_SW_PRIORITY = 0x0, .DC_I2C_SOFT_RESET = 0x1, . DC_I2C_SW_STATUS_RESET = 0x3, .DC_I2C_GO = 0x0, .DC_I2C_SEND_RESET = 0x2, .DC_I2C_TRANSACTION_COUNT = 0x14, .DC_I2C_DDC_SELECT = 0x8, .DC_I2C_DDC1_PRESCALE = 0x10, .DC_I2C_DDC1_THRESHOLD = 0x0 , .DC_I2C_SW_STOPPED_ON_NACK = 0x8, .DC_I2C_SW_TIMEOUT = 0x5, .DC_I2C_SW_ABORTED = 0x4, .DC_I2C_SW_DONE = 0x2, .DC_I2C_SW_STATUS = 0x0, .DC_I2C_STOP_ON_NACK0 = 0x8, .DC_I2C_START0 = 0xc, .DC_I2C_RW0 = 0x0, .DC_I2C_STOP0 = 0xd, .DC_I2C_COUNT0 = 0x10, .DC_I2C_DATA_RW = 0x0, .DC_I2C_DATA = 0x8, .DC_I2C_INDEX = 0x10, .DC_I2C_INDEX_WRITE = 0x1f, .XTAL_REF_DIV = 0x8, .MICROSECOND_TIME_BASE_DIV = 0x0 , .DC_I2C_REG_RW_CNTL_STATUS = 0x2, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x8, .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x2, .I2C_LIGHT_SLEEP_FORCE = 0x0, .I2C_MEM_PWR_STATE = 0x0 | ||||
| 994 | }; | ||||
| 995 | |||||
| 996 | static const struct dce_i2c_mask i2c_masks = { | ||||
| 997 | I2C_COMMON_MASK_SH_LIST_DCN30(_MASK).DC_I2C_DDC1_ENABLE = 0x00000040L, .DC_I2C_DDC1_TIME_LIMIT = 0xFF000000L , .DC_I2C_DDC1_DATA_DRIVE_EN = 0x00000001L, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x00000080L, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x00000002L, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x00FF0000L, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0x0000FF00L, . DC_I2C_DDC1_HW_STATUS = 0x00000003L, .DC_I2C_SW_USE_I2C_REG_REQ = 0x00100000L, .DC_I2C_SW_DONE_USING_I2C_REG = 0x00200000L, . DC_I2C_NO_QUEUED_SW_GO = 0x00000010L, .DC_I2C_SW_PRIORITY = 0x00000003L , .DC_I2C_SOFT_RESET = 0x00000002L, .DC_I2C_SW_STATUS_RESET = 0x00000008L, .DC_I2C_GO = 0x00000001L, .DC_I2C_SEND_RESET = 0x00000004L , .DC_I2C_TRANSACTION_COUNT = 0x00300000L, .DC_I2C_DDC_SELECT = 0x00000700L, .DC_I2C_DDC1_PRESCALE = 0xFFFF0000L, .DC_I2C_DDC1_THRESHOLD = 0x00000003L, .DC_I2C_SW_STOPPED_ON_NACK = 0x00000100L, .DC_I2C_SW_TIMEOUT = 0x00000020L, .DC_I2C_SW_ABORTED = 0x00000010L, .DC_I2C_SW_DONE = 0x00000004L, .DC_I2C_SW_STATUS = 0x00000003L, .DC_I2C_STOP_ON_NACK0 = 0x00000100L, .DC_I2C_START0 = 0x00001000L, .DC_I2C_RW0 = 0x00000001L , .DC_I2C_STOP0 = 0x00002000L, .DC_I2C_COUNT0 = 0x03FF0000L, . DC_I2C_DATA_RW = 0x00000001L, .DC_I2C_DATA = 0x0000FF00L, .DC_I2C_INDEX = 0x03FF0000L, .DC_I2C_INDEX_WRITE = 0x80000000L, .XTAL_REF_DIV = 0x00007F00L, .MICROSECOND_TIME_BASE_DIV = 0x0000007FL, .DC_I2C_REG_RW_CNTL_STATUS = 0x0000000CL, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x00000300L , .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x00000004L, .I2C_LIGHT_SLEEP_FORCE = 0x00000001L, .I2C_MEM_PWR_STATE = 0x00000001L | ||||
| 998 | }; | ||||
| 999 | |||||
| 1000 | static struct dce_i2c_hw *dcn31_i2c_hw_create( | ||||
| 1001 | struct dc_context *ctx, | ||||
| 1002 | uint32_t inst) | ||||
| 1003 | { | ||||
| 1004 | struct dce_i2c_hw *dce_i2c_hw = | ||||
| 1005 | kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1006 | |||||
| 1007 | if (!dce_i2c_hw) | ||||
| 1008 | return NULL((void *)0); | ||||
| 1009 | |||||
| 1010 | dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, | ||||
| 1011 | &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); | ||||
| 1012 | |||||
| 1013 | return dce_i2c_hw; | ||||
| 1014 | } | ||||
| 1015 | static struct mpc *dcn31_mpc_create( | ||||
| 1016 | struct dc_context *ctx, | ||||
| 1017 | int num_mpcc, | ||||
| 1018 | int num_rmu) | ||||
| 1019 | { | ||||
| 1020 | struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), | ||||
| 1021 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1022 | |||||
| 1023 | if (!mpc30) | ||||
| 1024 | return NULL((void *)0); | ||||
| 1025 | |||||
| 1026 | dcn30_mpc_construct(mpc30, ctx, | ||||
| 1027 | &mpc_regs, | ||||
| 1028 | &mpc_shift, | ||||
| 1029 | &mpc_mask, | ||||
| 1030 | num_mpcc, | ||||
| 1031 | num_rmu); | ||||
| 1032 | |||||
| 1033 | return &mpc30->base; | ||||
| 1034 | } | ||||
| 1035 | |||||
| 1036 | static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx) | ||||
| 1037 | { | ||||
| 1038 | int i; | ||||
| 1039 | |||||
| 1040 | struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), | ||||
| 1041 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1042 | |||||
| 1043 | if (!hubbub3) | ||||
| 1044 | return NULL((void *)0); | ||||
| 1045 | |||||
| 1046 | hubbub31_construct(hubbub3, ctx, | ||||
| 1047 | &hubbub_reg, | ||||
| 1048 | &hubbub_shift, | ||||
| 1049 | &hubbub_mask, | ||||
| 1050 | dcn3_15_ip.det_buffer_size_kbytes, | ||||
| 1051 | dcn3_15_ip.pixel_chunk_size_kbytes, | ||||
| 1052 | dcn3_15_ip.config_return_buffer_size_in_kbytes); | ||||
| 1053 | |||||
| 1054 | |||||
| 1055 | for (i = 0; i < res_cap_dcn31.num_vmid; i++) { | ||||
| 1056 | struct dcn20_vmid *vmid = &hubbub3->vmid[i]; | ||||
| 1057 | |||||
| 1058 | vmid->ctx = ctx; | ||||
| 1059 | |||||
| 1060 | vmid->regs = &vmid_regs[i]; | ||||
| 1061 | vmid->shifts = &vmid_shifts; | ||||
| 1062 | vmid->masks = &vmid_masks; | ||||
| 1063 | } | ||||
| 1064 | |||||
| 1065 | return &hubbub3->base; | ||||
| 1066 | } | ||||
| 1067 | |||||
| 1068 | static struct timing_generator *dcn31_timing_generator_create( | ||||
| 1069 | struct dc_context *ctx, | ||||
| 1070 | uint32_t instance) | ||||
| 1071 | { | ||||
| 1072 | struct optc *tgn10 = | ||||
| 1073 | kzalloc(sizeof(struct optc), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1074 | |||||
| 1075 | if (!tgn10) | ||||
| 1076 | return NULL((void *)0); | ||||
| 1077 | |||||
| 1078 | tgn10->base.inst = instance; | ||||
| 1079 | tgn10->base.ctx = ctx; | ||||
| 1080 | |||||
| 1081 | tgn10->tg_regs = &optc_regs[instance]; | ||||
| 1082 | tgn10->tg_shift = &optc_shift; | ||||
| 1083 | tgn10->tg_mask = &optc_mask; | ||||
| 1084 | |||||
| 1085 | dcn31_timing_generator_init(tgn10); | ||||
| 1086 | |||||
| 1087 | return &tgn10->base; | ||||
| 1088 | } | ||||
| 1089 | |||||
| 1090 | static const struct encoder_feature_support link_enc_feature = { | ||||
| 1091 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | ||||
| 1092 | .max_hdmi_pixel_clock = 600000, | ||||
| 1093 | .hdmi_ycbcr420_supported = true1, | ||||
| 1094 | .dp_ycbcr420_supported = true1, | ||||
| 1095 | .fec_supported = true1, | ||||
| 1096 | .flags.bits.IS_HBR2_CAPABLE = true1, | ||||
| 1097 | .flags.bits.IS_HBR3_CAPABLE = true1, | ||||
| 1098 | .flags.bits.IS_TPS3_CAPABLE = true1, | ||||
| 1099 | .flags.bits.IS_TPS4_CAPABLE = true1 | ||||
| 1100 | }; | ||||
| 1101 | |||||
| 1102 | static struct link_encoder *dcn31_link_encoder_create( | ||||
| 1103 | struct dc_context *ctx, | ||||
| 1104 | const struct encoder_init_data *enc_init_data) | ||||
| 1105 | { | ||||
| 1106 | struct dcn20_link_encoder *enc20 = | ||||
| 1107 | kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1108 | |||||
| 1109 | if (!enc20) | ||||
| 1110 | return NULL((void *)0); | ||||
| 1111 | |||||
| 1112 | dcn31_link_encoder_construct(enc20, | ||||
| 1113 | enc_init_data, | ||||
| 1114 | &link_enc_feature, | ||||
| 1115 | &link_enc_regs[enc_init_data->transmitter], | ||||
| 1116 | &link_enc_aux_regs[enc_init_data->channel - 1], | ||||
| 1117 | &link_enc_hpd_regs[enc_init_data->hpd_source], | ||||
| 1118 | &le_shift, | ||||
| 1119 | &le_mask); | ||||
| 1120 | |||||
| 1121 | return &enc20->enc10.base; | ||||
| 1122 | } | ||||
| 1123 | |||||
| 1124 | /* Create a minimal link encoder object not associated with a particular | ||||
| 1125 | * physical connector. | ||||
| 1126 | * resource_funcs.link_enc_create_minimal | ||||
| 1127 | */ | ||||
| 1128 | static struct link_encoder *dcn31_link_enc_create_minimal( | ||||
| 1129 | struct dc_context *ctx, enum engine_id eng_id) | ||||
| 1130 | { | ||||
| 1131 | struct dcn20_link_encoder *enc20; | ||||
| 1132 | |||||
| 1133 | if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) | ||||
| 1134 | return NULL((void *)0); | ||||
| 1135 | |||||
| 1136 | enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1137 | if (!enc20) | ||||
| 1138 | return NULL((void *)0); | ||||
| 1139 | |||||
| 1140 | dcn31_link_encoder_construct_minimal( | ||||
| 1141 | enc20, | ||||
| 1142 | ctx, | ||||
| 1143 | &link_enc_feature, | ||||
| 1144 | &link_enc_regs[eng_id - ENGINE_ID_DIGA], | ||||
| 1145 | eng_id); | ||||
| 1146 | |||||
| 1147 | return &enc20->enc10.base; | ||||
| 1148 | } | ||||
| 1149 | |||||
| 1150 | static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data) | ||||
| 1151 | { | ||||
| 1152 | struct dcn31_panel_cntl *panel_cntl = | ||||
| 1153 | kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1154 | |||||
| 1155 | if (!panel_cntl) | ||||
| 1156 | return NULL((void *)0); | ||||
| 1157 | |||||
| 1158 | dcn31_panel_cntl_construct(panel_cntl, init_data); | ||||
| 1159 | |||||
| 1160 | return &panel_cntl->base; | ||||
| 1161 | } | ||||
| 1162 | |||||
| 1163 | static void read_dce_straps( | ||||
| 1164 | struct dc_context *ctx, | ||||
| 1165 | struct resource_straps *straps) | ||||
| 1166 | { | ||||
| 1167 | generic_reg_get(ctx, regDC_PINSTRAPS0x2880 + BASE(regDC_PINSTRAPS_BASE_IDX)0x000034C0, | ||||
| 1168 | FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO)0xe, 0x0000C000L, &straps->dc_pinstraps_audio); | ||||
| 1169 | |||||
| 1170 | } | ||||
| 1171 | |||||
| 1172 | static struct audio *dcn31_create_audio( | ||||
| 1173 | struct dc_context *ctx, unsigned int inst) | ||||
| 1174 | { | ||||
| 1175 | return dce_audio_create(ctx, inst, | ||||
| 1176 | &audio_regs[inst], &audio_shift, &audio_mask); | ||||
| 1177 | } | ||||
| 1178 | |||||
| 1179 | static struct vpg *dcn31_vpg_create( | ||||
| 1180 | struct dc_context *ctx, | ||||
| 1181 | uint32_t inst) | ||||
| 1182 | { | ||||
| 1183 | struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1184 | |||||
| 1185 | if (!vpg31) | ||||
| 1186 | return NULL((void *)0); | ||||
| 1187 | |||||
| 1188 | vpg31_construct(vpg31, ctx, inst, | ||||
| 1189 | &vpg_regs[inst], | ||||
| 1190 | &vpg_shift, | ||||
| 1191 | &vpg_mask); | ||||
| 1192 | |||||
| 1193 | return &vpg31->base; | ||||
| 1194 | } | ||||
| 1195 | |||||
| 1196 | static struct afmt *dcn31_afmt_create( | ||||
| 1197 | struct dc_context *ctx, | ||||
| 1198 | uint32_t inst) | ||||
| 1199 | { | ||||
| 1200 | struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1201 | |||||
| 1202 | if (!afmt31) | ||||
| 1203 | return NULL((void *)0); | ||||
| 1204 | |||||
| 1205 | afmt31_construct(afmt31, ctx, inst, | ||||
| 1206 | &afmt_regs[inst], | ||||
| 1207 | &afmt_shift, | ||||
| 1208 | &afmt_mask); | ||||
| 1209 | |||||
| 1210 | // Light sleep by default, no need to power down here | ||||
| 1211 | |||||
| 1212 | return &afmt31->base; | ||||
| 1213 | } | ||||
| 1214 | |||||
| 1215 | static struct apg *dcn31_apg_create( | ||||
| 1216 | struct dc_context *ctx, | ||||
| 1217 | uint32_t inst) | ||||
| 1218 | { | ||||
| 1219 | struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1220 | |||||
| 1221 | if (!apg31) | ||||
| 1222 | return NULL((void *)0); | ||||
| 1223 | |||||
| 1224 | apg31_construct(apg31, ctx, inst, | ||||
| 1225 | &apg_regs[inst], | ||||
| 1226 | &apg_shift, | ||||
| 1227 | &apg_mask); | ||||
| 1228 | |||||
| 1229 | return &apg31->base; | ||||
| 1230 | } | ||||
| 1231 | |||||
| 1232 | static struct stream_encoder *dcn315_stream_encoder_create( | ||||
| 1233 | enum engine_id eng_id, | ||||
| 1234 | struct dc_context *ctx) | ||||
| 1235 | { | ||||
| 1236 | struct dcn10_stream_encoder *enc1; | ||||
| 1237 | struct vpg *vpg; | ||||
| 1238 | struct afmt *afmt; | ||||
| 1239 | int vpg_inst; | ||||
| 1240 | int afmt_inst; | ||||
| 1241 | |||||
| 1242 | /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ | ||||
| 1243 | |||||
| 1244 | /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ | ||||
| 1245 | if (eng_id <= ENGINE_ID_DIGF) { | ||||
| 1246 | vpg_inst = eng_id; | ||||
| 1247 | afmt_inst = eng_id; | ||||
| 1248 | } else | ||||
| 1249 | return NULL((void *)0); | ||||
| 1250 | |||||
| 1251 | enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1252 | vpg = dcn31_vpg_create(ctx, vpg_inst); | ||||
| 1253 | afmt = dcn31_afmt_create(ctx, afmt_inst); | ||||
| 1254 | |||||
| 1255 | if (!enc1 || !vpg || !afmt) { | ||||
| 1256 | kfree(enc1); | ||||
| 1257 | kfree(vpg); | ||||
| 1258 | kfree(afmt); | ||||
| 1259 | return NULL((void *)0); | ||||
| 1260 | } | ||||
| 1261 | |||||
| 1262 | dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, | ||||
| 1263 | eng_id, vpg, afmt, | ||||
| 1264 | &stream_enc_regs[eng_id], | ||||
| 1265 | &se_shift, &se_mask); | ||||
| 1266 | |||||
| 1267 | return &enc1->base; | ||||
| 1268 | } | ||||
| 1269 | |||||
| 1270 | static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create( | ||||
| 1271 | enum engine_id eng_id, | ||||
| 1272 | struct dc_context *ctx) | ||||
| 1273 | { | ||||
| 1274 | struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; | ||||
| 1275 | struct vpg *vpg; | ||||
| 1276 | struct apg *apg; | ||||
| 1277 | uint32_t hpo_dp_inst; | ||||
| 1278 | uint32_t vpg_inst; | ||||
| 1279 | uint32_t apg_inst; | ||||
| 1280 | |||||
| 1281 | ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3))do { if (({ static int __warned; int __ret = !!(!((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn315/dcn315_resource.c" , 1281); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
| 1282 | hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; | ||||
| 1283 | |||||
| 1284 | /* Mapping of VPG register blocks to HPO DP block instance: | ||||
| 1285 | * VPG[6] -> HPO_DP[0] | ||||
| 1286 | * VPG[7] -> HPO_DP[1] | ||||
| 1287 | * VPG[8] -> HPO_DP[2] | ||||
| 1288 | * VPG[9] -> HPO_DP[3] | ||||
| 1289 | */ | ||||
| 1290 | vpg_inst = hpo_dp_inst + 6; | ||||
| 1291 | |||||
| 1292 | /* Mapping of APG register blocks to HPO DP block instance: | ||||
| 1293 | * APG[0] -> HPO_DP[0] | ||||
| 1294 | * APG[1] -> HPO_DP[1] | ||||
| 1295 | * APG[2] -> HPO_DP[2] | ||||
| 1296 | * APG[3] -> HPO_DP[3] | ||||
| 1297 | */ | ||||
| 1298 | apg_inst = hpo_dp_inst; | ||||
| 1299 | |||||
| 1300 | /* allocate HPO stream encoder and create VPG sub-block */ | ||||
| 1301 | hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1302 | vpg = dcn31_vpg_create(ctx, vpg_inst); | ||||
| 1303 | apg = dcn31_apg_create(ctx, apg_inst); | ||||
| 1304 | |||||
| 1305 | if (!hpo_dp_enc31 || !vpg || !apg) { | ||||
| 1306 | kfree(hpo_dp_enc31); | ||||
| 1307 | kfree(vpg); | ||||
| 1308 | kfree(apg); | ||||
| 1309 | return NULL((void *)0); | ||||
| 1310 | } | ||||
| 1311 | |||||
| 1312 | dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, | ||||
| 1313 | hpo_dp_inst, eng_id, vpg, apg, | ||||
| 1314 | &hpo_dp_stream_enc_regs[hpo_dp_inst], | ||||
| 1315 | &hpo_dp_se_shift, &hpo_dp_se_mask); | ||||
| 1316 | |||||
| 1317 | return &hpo_dp_enc31->base; | ||||
| 1318 | } | ||||
| 1319 | |||||
| 1320 | static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create( | ||||
| 1321 | uint8_t inst, | ||||
| 1322 | struct dc_context *ctx) | ||||
| 1323 | { | ||||
| 1324 | struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; | ||||
| 1325 | |||||
| 1326 | /* allocate HPO link encoder */ | ||||
| 1327 | hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1328 | |||||
| 1329 | hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst, | ||||
| 1330 | &hpo_dp_link_enc_regs[inst], | ||||
| 1331 | &hpo_dp_le_shift, &hpo_dp_le_mask); | ||||
| 1332 | |||||
| 1333 | return &hpo_dp_enc31->base; | ||||
| 1334 | } | ||||
| 1335 | |||||
| 1336 | static struct dce_hwseq *dcn31_hwseq_create( | ||||
| 1337 | struct dc_context *ctx) | ||||
| 1338 | { | ||||
| 1339 | struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1340 | |||||
| 1341 | if (hws) { | ||||
| 1342 | hws->ctx = ctx; | ||||
| 1343 | hws->regs = &hwseq_reg; | ||||
| 1344 | hws->shifts = &hwseq_shift; | ||||
| 1345 | hws->masks = &hwseq_mask; | ||||
| 1346 | /* DCN3.1 FPGA Workaround | ||||
| 1347 | * Need to enable HPO DP Stream Encoder before setting OTG master enable. | ||||
| 1348 | * To do so, move calling function enable_stream_timing to only be done AFTER calling | ||||
| 1349 | * function core_link_enable_stream | ||||
| 1350 | */ | ||||
| 1351 | if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)(ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) | ||||
| 1352 | hws->wa.dp_hpo_and_otg_sequence = true1; | ||||
| 1353 | } | ||||
| 1354 | return hws; | ||||
| 1355 | } | ||||
| 1356 | static const struct resource_create_funcs res_create_funcs = { | ||||
| 1357 | .read_dce_straps = read_dce_straps, | ||||
| 1358 | .create_audio = dcn31_create_audio, | ||||
| 1359 | .create_stream_encoder = dcn315_stream_encoder_create, | ||||
| 1360 | .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, | ||||
| 1361 | .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, | ||||
| 1362 | .create_hwseq = dcn31_hwseq_create, | ||||
| 1363 | }; | ||||
| 1364 | |||||
| 1365 | static const struct resource_create_funcs res_create_maximus_funcs = { | ||||
| 1366 | .read_dce_straps = NULL((void *)0), | ||||
| 1367 | .create_audio = NULL((void *)0), | ||||
| 1368 | .create_stream_encoder = NULL((void *)0), | ||||
| 1369 | .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create, | ||||
| 1370 | .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create, | ||||
| 1371 | .create_hwseq = dcn31_hwseq_create, | ||||
| 1372 | }; | ||||
| 1373 | |||||
| 1374 | static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) | ||||
| 1375 | { | ||||
| 1376 | unsigned int i; | ||||
| 1377 | |||||
| 1378 | for (i = 0; i < pool->base.stream_enc_count; i++) { | ||||
| 1379 | if (pool->base.stream_enc[i] != NULL((void *)0)) { | ||||
| 1380 | if (pool->base.stream_enc[i]->vpg != NULL((void *)0)) { | ||||
| 1381 | kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)({ const __typeof( ((struct dcn30_vpg *)0)->base ) *__mptr = (pool->base.stream_enc[i]->vpg); (struct dcn30_vpg * )( (char *)__mptr - __builtin_offsetof(struct dcn30_vpg, base ) );})); | ||||
| 1382 | pool->base.stream_enc[i]->vpg = NULL((void *)0); | ||||
| 1383 | } | ||||
| 1384 | if (pool->base.stream_enc[i]->afmt != NULL((void *)0)) { | ||||
| 1385 | kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)({ const __typeof( ((struct dcn30_afmt *)0)->base ) *__mptr = (pool->base.stream_enc[i]->afmt); (struct dcn30_afmt *)( (char *)__mptr - __builtin_offsetof(struct dcn30_afmt, base ) );})); | ||||
| 1386 | pool->base.stream_enc[i]->afmt = NULL((void *)0); | ||||
| 1387 | } | ||||
| 1388 | kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])({ const __typeof( ((struct dcn10_stream_encoder *)0)->base ) *__mptr = (pool->base.stream_enc[i]); (struct dcn10_stream_encoder *)( (char *)__mptr - __builtin_offsetof(struct dcn10_stream_encoder , base) );})); | ||||
| 1389 | pool->base.stream_enc[i] = NULL((void *)0); | ||||
| 1390 | } | ||||
| 1391 | } | ||||
| 1392 | |||||
| 1393 | for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { | ||||
| 1394 | if (pool->base.hpo_dp_stream_enc[i] != NULL((void *)0)) { | ||||
| 1395 | if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL((void *)0)) { | ||||
| 1396 | kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)({ const __typeof( ((struct dcn30_vpg *)0)->base ) *__mptr = (pool->base.hpo_dp_stream_enc[i]->vpg); (struct dcn30_vpg *)( (char *)__mptr - __builtin_offsetof(struct dcn30_vpg, base ) );})); | ||||
| 1397 | pool->base.hpo_dp_stream_enc[i]->vpg = NULL((void *)0); | ||||
| 1398 | } | ||||
| 1399 | if (pool->base.hpo_dp_stream_enc[i]->apg != NULL((void *)0)) { | ||||
| 1400 | kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)({ const __typeof( ((struct dcn31_apg *)0)->base ) *__mptr = (pool->base.hpo_dp_stream_enc[i]->apg); (struct dcn31_apg *)( (char *)__mptr - __builtin_offsetof(struct dcn31_apg, base ) );})); | ||||
| 1401 | pool->base.hpo_dp_stream_enc[i]->apg = NULL((void *)0); | ||||
| 1402 | } | ||||
| 1403 | kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])({ const __typeof( ((struct dcn31_hpo_dp_stream_encoder *)0)-> base ) *__mptr = (pool->base.hpo_dp_stream_enc[i]); (struct dcn31_hpo_dp_stream_encoder *)( (char *)__mptr - __builtin_offsetof (struct dcn31_hpo_dp_stream_encoder, base) );})); | ||||
| 1404 | pool->base.hpo_dp_stream_enc[i] = NULL((void *)0); | ||||
| 1405 | } | ||||
| 1406 | } | ||||
| 1407 | |||||
| 1408 | for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { | ||||
| 1409 | if (pool->base.hpo_dp_link_enc[i] != NULL((void *)0)) { | ||||
| 1410 | kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])({ const __typeof( ((struct dcn31_hpo_dp_link_encoder *)0)-> base ) *__mptr = (pool->base.hpo_dp_link_enc[i]); (struct dcn31_hpo_dp_link_encoder *)( (char *)__mptr - __builtin_offsetof(struct dcn31_hpo_dp_link_encoder , base) );})); | ||||
| 1411 | pool->base.hpo_dp_link_enc[i] = NULL((void *)0); | ||||
| 1412 | } | ||||
| 1413 | } | ||||
| 1414 | |||||
| 1415 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { | ||||
| 1416 | if (pool->base.dscs[i] != NULL((void *)0)) | ||||
| 1417 | dcn20_dsc_destroy(&pool->base.dscs[i]); | ||||
| 1418 | } | ||||
| 1419 | |||||
| 1420 | if (pool->base.mpc != NULL((void *)0)) { | ||||
| 1421 | kfree(TO_DCN20_MPC(pool->base.mpc)({ const __typeof( ((struct dcn20_mpc *)0)->base ) *__mptr = (pool->base.mpc); (struct dcn20_mpc *)( (char *)__mptr - __builtin_offsetof(struct dcn20_mpc, base) );})); | ||||
| 1422 | pool->base.mpc = NULL((void *)0); | ||||
| 1423 | } | ||||
| 1424 | if (pool->base.hubbub != NULL((void *)0)) { | ||||
| 1425 | kfree(pool->base.hubbub); | ||||
| 1426 | pool->base.hubbub = NULL((void *)0); | ||||
| 1427 | } | ||||
| 1428 | for (i = 0; i < pool->base.pipe_count; i++) { | ||||
| 1429 | if (pool->base.dpps[i] != NULL((void *)0)) | ||||
| 1430 | dcn31_dpp_destroy(&pool->base.dpps[i]); | ||||
| 1431 | |||||
| 1432 | if (pool->base.ipps[i] != NULL((void *)0)) | ||||
| 1433 | pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); | ||||
| 1434 | |||||
| 1435 | if (pool->base.hubps[i] != NULL((void *)0)) { | ||||
| 1436 | kfree(TO_DCN20_HUBP(pool->base.hubps[i])({ const __typeof( ((struct dcn20_hubp *)0)->base ) *__mptr = (pool->base.hubps[i]); (struct dcn20_hubp *)( (char *)__mptr - __builtin_offsetof(struct dcn20_hubp, base) );})); | ||||
| 1437 | pool->base.hubps[i] = NULL((void *)0); | ||||
| 1438 | } | ||||
| 1439 | |||||
| 1440 | if (pool->base.irqs != NULL((void *)0)) { | ||||
| 1441 | dal_irq_service_destroy(&pool->base.irqs); | ||||
| 1442 | } | ||||
| 1443 | } | ||||
| 1444 | |||||
| 1445 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | ||||
| 1446 | if (pool->base.engines[i] != NULL((void *)0)) | ||||
| 1447 | dce110_engine_destroy(&pool->base.engines[i]); | ||||
| 1448 | if (pool->base.hw_i2cs[i] != NULL((void *)0)) { | ||||
| 1449 | kfree(pool->base.hw_i2cs[i]); | ||||
| 1450 | pool->base.hw_i2cs[i] = NULL((void *)0); | ||||
| 1451 | } | ||||
| 1452 | if (pool->base.sw_i2cs[i] != NULL((void *)0)) { | ||||
| 1453 | kfree(pool->base.sw_i2cs[i]); | ||||
| 1454 | pool->base.sw_i2cs[i] = NULL((void *)0); | ||||
| 1455 | } | ||||
| 1456 | } | ||||
| 1457 | |||||
| 1458 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | ||||
| 1459 | if (pool->base.opps[i] != NULL((void *)0)) | ||||
| 1460 | pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); | ||||
| 1461 | } | ||||
| 1462 | |||||
| 1463 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | ||||
| 1464 | if (pool->base.timing_generators[i] != NULL((void *)0)) { | ||||
| 1465 | kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])({ const __typeof( ((struct optc *)0)->base ) *__mptr = (pool ->base.timing_generators[i]); (struct optc *)( (char *)__mptr - __builtin_offsetof(struct optc, base) );})); | ||||
| 1466 | pool->base.timing_generators[i] = NULL((void *)0); | ||||
| 1467 | } | ||||
| 1468 | } | ||||
| 1469 | |||||
| 1470 | for (i = 0; i < pool->base.res_cap->num_dwb; i++) { | ||||
| 1471 | if (pool->base.dwbc[i] != NULL((void *)0)) { | ||||
| 1472 | kfree(TO_DCN30_DWBC(pool->base.dwbc[i])({ const __typeof( ((struct dcn30_dwbc *)0)->base ) *__mptr = (pool->base.dwbc[i]); (struct dcn30_dwbc *)( (char *)__mptr - __builtin_offsetof(struct dcn30_dwbc, base) );})); | ||||
| 1473 | pool->base.dwbc[i] = NULL((void *)0); | ||||
| 1474 | } | ||||
| 1475 | if (pool->base.mcif_wb[i] != NULL((void *)0)) { | ||||
| 1476 | kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])({ const __typeof( ((struct dcn30_mmhubbub *)0)->base ) *__mptr = (pool->base.mcif_wb[i]); (struct dcn30_mmhubbub *)( (char *)__mptr - __builtin_offsetof(struct dcn30_mmhubbub, base) ) ;})); | ||||
| 1477 | pool->base.mcif_wb[i] = NULL((void *)0); | ||||
| 1478 | } | ||||
| 1479 | } | ||||
| 1480 | |||||
| 1481 | for (i = 0; i < pool->base.audio_count; i++) { | ||||
| 1482 | if (pool->base.audios[i]) | ||||
| 1483 | dce_aud_destroy(&pool->base.audios[i]); | ||||
| 1484 | } | ||||
| 1485 | |||||
| 1486 | for (i = 0; i < pool->base.clk_src_count; i++) { | ||||
| 1487 | if (pool->base.clock_sources[i] != NULL((void *)0)) { | ||||
| 1488 | dcn20_clock_source_destroy(&pool->base.clock_sources[i]); | ||||
| 1489 | pool->base.clock_sources[i] = NULL((void *)0); | ||||
| 1490 | } | ||||
| 1491 | } | ||||
| 1492 | |||||
| 1493 | for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { | ||||
| 1494 | if (pool->base.mpc_lut[i] != NULL((void *)0)) { | ||||
| 1495 | dc_3dlut_func_release(pool->base.mpc_lut[i]); | ||||
| 1496 | pool->base.mpc_lut[i] = NULL((void *)0); | ||||
| 1497 | } | ||||
| 1498 | if (pool->base.mpc_shaper[i] != NULL((void *)0)) { | ||||
| 1499 | dc_transfer_func_release(pool->base.mpc_shaper[i]); | ||||
| 1500 | pool->base.mpc_shaper[i] = NULL((void *)0); | ||||
| 1501 | } | ||||
| 1502 | } | ||||
| 1503 | |||||
| 1504 | if (pool->base.dp_clock_source != NULL((void *)0)) { | ||||
| 1505 | dcn20_clock_source_destroy(&pool->base.dp_clock_source); | ||||
| 1506 | pool->base.dp_clock_source = NULL((void *)0); | ||||
| 1507 | } | ||||
| 1508 | |||||
| 1509 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | ||||
| 1510 | if (pool->base.multiple_abms[i] != NULL((void *)0)) | ||||
| 1511 | dce_abm_destroy(&pool->base.multiple_abms[i]); | ||||
| 1512 | } | ||||
| 1513 | |||||
| 1514 | if (pool->base.psr != NULL((void *)0)) | ||||
| 1515 | dmub_psr_destroy(&pool->base.psr); | ||||
| 1516 | |||||
| 1517 | if (pool->base.dccg != NULL((void *)0)) | ||||
| 1518 | dcn_dccg_destroy(&pool->base.dccg); | ||||
| 1519 | } | ||||
| 1520 | |||||
| 1521 | static struct hubp *dcn31_hubp_create( | ||||
| 1522 | struct dc_context *ctx, | ||||
| 1523 | uint32_t inst) | ||||
| 1524 | { | ||||
| 1525 | struct dcn20_hubp *hubp2 = | ||||
| 1526 | kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1527 | |||||
| 1528 | if (!hubp2) | ||||
| 1529 | return NULL((void *)0); | ||||
| 1530 | |||||
| 1531 | if (hubp31_construct(hubp2, ctx, inst, | ||||
| 1532 | &hubp_regs[inst], &hubp_shift, &hubp_mask)) | ||||
| 1533 | return &hubp2->base; | ||||
| 1534 | |||||
| 1535 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 1535); do {} while (0); } while (0); | ||||
| 1536 | kfree(hubp2); | ||||
| 1537 | return NULL((void *)0); | ||||
| 1538 | } | ||||
| 1539 | |||||
| 1540 | static bool_Bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) | ||||
| 1541 | { | ||||
| 1542 | int i; | ||||
| 1543 | uint32_t pipe_count = pool->res_cap->num_dwb; | ||||
| 1544 | |||||
| 1545 | for (i = 0; i < pipe_count; i++) { | ||||
| 1546 | struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), | ||||
| 1547 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1548 | |||||
| 1549 | if (!dwbc30) { | ||||
| 1550 | dm_error("DC: failed to create dwbc30!\n")__drm_err("DC: failed to create dwbc30!\n"); | ||||
| 1551 | return false0; | ||||
| 1552 | } | ||||
| 1553 | |||||
| 1554 | dcn30_dwbc_construct(dwbc30, ctx, | ||||
| 1555 | &dwbc30_regs[i], | ||||
| 1556 | &dwbc30_shift, | ||||
| 1557 | &dwbc30_mask, | ||||
| 1558 | i); | ||||
| 1559 | |||||
| 1560 | pool->dwbc[i] = &dwbc30->base; | ||||
| 1561 | } | ||||
| 1562 | return true1; | ||||
| 1563 | } | ||||
| 1564 | |||||
| 1565 | static bool_Bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) | ||||
| 1566 | { | ||||
| 1567 | int i; | ||||
| 1568 | uint32_t pipe_count = pool->res_cap->num_dwb; | ||||
| 1569 | |||||
| 1570 | for (i = 0; i < pipe_count; i++) { | ||||
| 1571 | struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), | ||||
| 1572 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1573 | |||||
| 1574 | if (!mcif_wb30) { | ||||
| 1575 | dm_error("DC: failed to create mcif_wb30!\n")__drm_err("DC: failed to create mcif_wb30!\n"); | ||||
| 1576 | return false0; | ||||
| 1577 | } | ||||
| 1578 | |||||
| 1579 | dcn30_mmhubbub_construct(mcif_wb30, ctx, | ||||
| 1580 | &mcif_wb30_regs[i], | ||||
| 1581 | &mcif_wb30_shift, | ||||
| 1582 | &mcif_wb30_mask, | ||||
| 1583 | i); | ||||
| 1584 | |||||
| 1585 | pool->mcif_wb[i] = &mcif_wb30->base; | ||||
| 1586 | } | ||||
| 1587 | return true1; | ||||
| 1588 | } | ||||
| 1589 | |||||
| 1590 | static struct display_stream_compressor *dcn31_dsc_create( | ||||
| 1591 | struct dc_context *ctx, uint32_t inst) | ||||
| 1592 | { | ||||
| 1593 | struct dcn20_dsc *dsc = | ||||
| 1594 | kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1595 | |||||
| 1596 | if (!dsc) { | ||||
| 1597 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 1597); do {} while (0); } while (0); | ||||
| 1598 | return NULL((void *)0); | ||||
| 1599 | } | ||||
| 1600 | |||||
| 1601 | dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); | ||||
| 1602 | return &dsc->base; | ||||
| 1603 | } | ||||
| 1604 | |||||
| 1605 | static void dcn315_destroy_resource_pool(struct resource_pool **pool) | ||||
| 1606 | { | ||||
| 1607 | struct dcn315_resource_pool *dcn31_pool = TO_DCN315_RES_POOL(*pool)({ const __typeof( ((struct dcn315_resource_pool *)0)->base ) *__mptr = (*pool); (struct dcn315_resource_pool *)( (char * )__mptr - __builtin_offsetof(struct dcn315_resource_pool, base ) );}); | ||||
| 1608 | |||||
| 1609 | dcn315_resource_destruct(dcn31_pool); | ||||
| 1610 | kfree(dcn31_pool); | ||||
| 1611 | *pool = NULL((void *)0); | ||||
| 1612 | } | ||||
| 1613 | |||||
| 1614 | static struct clock_source *dcn31_clock_source_create( | ||||
| 1615 | struct dc_context *ctx, | ||||
| 1616 | struct dc_bios *bios, | ||||
| 1617 | enum clock_source_id id, | ||||
| 1618 | const struct dce110_clk_src_regs *regs, | ||||
| 1619 | bool_Bool dp_clk_src) | ||||
| 1620 | { | ||||
| 1621 | struct dce110_clk_src *clk_src = | ||||
| 1622 | kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 1623 | |||||
| 1624 | if (!clk_src) | ||||
| 1625 | return NULL((void *)0); | ||||
| 1626 | |||||
| 1627 | if (dcn31_clk_src_construct(clk_src, ctx, bios, id, | ||||
| 1628 | regs, &cs_shift, &cs_mask)) { | ||||
| 1629 | clk_src->base.dp_clk_src = dp_clk_src; | ||||
| 1630 | return &clk_src->base; | ||||
| 1631 | } | ||||
| 1632 | |||||
| 1633 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 1633); do {} while (0); } while (0); | ||||
| 1634 | return NULL((void *)0); | ||||
| 1635 | } | ||||
| 1636 | |||||
| 1637 | static bool_Bool is_dual_plane(enum surface_pixel_format format) | ||||
| 1638 | { | ||||
| 1639 | return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA; | ||||
| 1640 | } | ||||
| 1641 | |||||
| 1642 | static int source_format_to_bpp (enum source_format_class SourcePixelFormat) | ||||
| 1643 | { | ||||
| 1644 | if (SourcePixelFormat == dm_444_64) | ||||
| 1645 | return 8; | ||||
| 1646 | else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) | ||||
| 1647 | return 2; | ||||
| 1648 | else if (SourcePixelFormat == dm_444_8) | ||||
| 1649 | return 1; | ||||
| 1650 | else if (SourcePixelFormat == dm_rgbe_alpha) | ||||
| 1651 | return 5; | ||||
| 1652 | else if (SourcePixelFormat == dm_420_8) | ||||
| 1653 | return 3; | ||||
| 1654 | else if (SourcePixelFormat == dm_420_12) | ||||
| 1655 | return 6; | ||||
| 1656 | else | ||||
| 1657 | return 4; | ||||
| 1658 | } | ||||
| 1659 | |||||
| 1660 | static bool_Bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) | ||||
| 1661 | { | ||||
| 1662 | int i; | ||||
| 1663 | struct resource_context *res_ctx = &context->res_ctx; | ||||
| 1664 | |||||
| 1665 | /*Don't apply for single stream*/ | ||||
| 1666 | if (context->stream_count < 2) | ||||
| 1667 | return false0; | ||||
| 1668 | |||||
| 1669 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||
| 1670 | if (!res_ctx->pipe_ctx[i].stream) | ||||
| 1671 | continue; | ||||
| 1672 | |||||
| 1673 | /*Don't apply if MPO to avoid transition issues*/ | ||||
| 1674 | if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state != res_ctx->pipe_ctx[i].plane_state) | ||||
| 1675 | return false0; | ||||
| 1676 | } | ||||
| 1677 | return true1; | ||||
| 1678 | } | ||||
| 1679 | |||||
| 1680 | static int dcn315_populate_dml_pipes_from_context( | ||||
| 1681 | struct dc *dc, struct dc_state *context, | ||||
| 1682 | display_e2e_pipe_params_st *pipes, | ||||
| 1683 | bool_Bool fast_validate) | ||||
| 1684 | { | ||||
| 1685 | int i, pipe_cnt, crb_idx, crb_pipes; | ||||
| 1686 | struct resource_context *res_ctx = &context->res_ctx; | ||||
| 1687 | struct pipe_ctx *pipe; | ||||
| 1688 | const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB128; | ||||
| 1689 | int remaining_det_segs = max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB64; | ||||
| 1690 | bool_Bool pixel_rate_crb = allow_pixel_rate_crb(dc, context); | ||||
| 1691 | |||||
| 1692 | DC_FP_START()dc_fpu_begin(__func__, 1692); | ||||
| 1693 | dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); | ||||
| |||||
| 1694 | DC_FP_END()dc_fpu_end(__func__, 1694); | ||||
| 1695 | |||||
| 1696 | for (i = 0, pipe_cnt = 0, crb_pipes = 0; i < dc->res_pool->pipe_count; i++) { | ||||
| 1697 | struct dc_crtc_timing *timing; | ||||
| 1698 | |||||
| 1699 | if (!res_ctx->pipe_ctx[i].stream) | ||||
| 1700 | continue; | ||||
| 1701 | pipe = &res_ctx->pipe_ctx[i]; | ||||
| 1702 | timing = &pipe->stream->timing; | ||||
| 1703 | |||||
| 1704 | /* | ||||
| 1705 | * Immediate flip can be set dynamically after enabling the plane. | ||||
| 1706 | * We need to require support for immediate flip or underflow can be | ||||
| 1707 | * intermittently experienced depending on peak b/w requirements. | ||||
| 1708 | */ | ||||
| 1709 | pipes[pipe_cnt].pipe.src.immediate_flip = true1; | ||||
| 1710 | |||||
| 1711 | pipes[pipe_cnt].pipe.src.unbounded_req_mode = false0; | ||||
| 1712 | pipes[pipe_cnt].pipe.src.gpuvm = true1; | ||||
| 1713 | pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch; | ||||
| 1714 | pipes[pipe_cnt].pipe.src.dcc_rate = 3; | ||||
| 1715 | pipes[pipe_cnt].dout.dsc_input_bpc = 0; | ||||
| 1716 | DC_FP_START()dc_fpu_begin(__func__, 1716); | ||||
| 1717 | dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt); | ||||
| 1718 | if (pixel_rate_crb
| ||||
| 1719 | int bpp = source_format_to_bpp(pipes[pipe_cnt].pipe.src.source_format); | ||||
| 1720 | /* Ceil to crb segment size */ | ||||
| 1721 | int approx_det_segs_required_for_pstate = dcn_get_approx_det_segs_required_for_pstate( | ||||
| 1722 | &context->bw_ctx.dml.soc, timing->pix_clk_100hz, bpp, DCN3_15_CRB_SEGMENT_SIZE_KB64); | ||||
| 1723 | if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS(384 / 64)) { | ||||
| 1724 | bool_Bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS(384 / 64); | ||||
| 1725 | split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); | ||||
| 1726 | split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); | ||||
| 1727 | if (split_required) | ||||
| 1728 | approx_det_segs_required_for_pstate += approx_det_segs_required_for_pstate % 2; | ||||
| 1729 | pipes[pipe_cnt].pipe.src.det_size_override = approx_det_segs_required_for_pstate; | ||||
| 1730 | remaining_det_segs -= approx_det_segs_required_for_pstate; | ||||
| 1731 | } else | ||||
| 1732 | remaining_det_segs = -1; | ||||
| 1733 | crb_pipes++; | ||||
| 1734 | } | ||||
| 1735 | DC_FP_END()dc_fpu_end(__func__, 1735); | ||||
| 1736 | |||||
| 1737 | if (pipes[pipe_cnt].dout.dsc_enable) { | ||||
| 1738 | switch (timing->display_color_depth) { | ||||
| 1739 | case COLOR_DEPTH_888: | ||||
| 1740 | pipes[pipe_cnt].dout.dsc_input_bpc = 8; | ||||
| 1741 | break; | ||||
| 1742 | case COLOR_DEPTH_101010: | ||||
| 1743 | pipes[pipe_cnt].dout.dsc_input_bpc = 10; | ||||
| 1744 | break; | ||||
| 1745 | case COLOR_DEPTH_121212: | ||||
| 1746 | pipes[pipe_cnt].dout.dsc_input_bpc = 12; | ||||
| 1747 | break; | ||||
| 1748 | default: | ||||
| 1749 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn315/dcn315_resource.c" , 1749); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
| 1750 | break; | ||||
| 1751 | } | ||||
| 1752 | } | ||||
| 1753 | pipe_cnt++; | ||||
| 1754 | } | ||||
| 1755 | |||||
| 1756 | /* Spread remaining unreserved crb evenly among all pipes*/ | ||||
| 1757 | if (pixel_rate_crb
| ||||
| 1758 | for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) { | ||||
| 1759 | pipe = &res_ctx->pipe_ctx[i]; | ||||
| 1760 | if (!pipe->stream
| ||||
| 1761 | continue; | ||||
| 1762 | |||||
| 1763 | /* Do not use asymetric crb if not enough for pstate support */ | ||||
| 1764 | if (remaining_det_segs < 0) { | ||||
| 1765 | pipes[pipe_cnt].pipe.src.det_size_override = 0; | ||||
| 1766 | continue; | ||||
| 1767 | } | ||||
| 1768 | |||||
| 1769 | if (!pipe->top_pipe
| ||||
| 1770 | bool_Bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) | ||||
| 1771 | || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); | ||||
| 1772 | |||||
| 1773 | if (remaining_det_segs > MIN_RESERVED_DET_SEGS2) | ||||
| 1774 | pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS2) / crb_pipes + | ||||
| 1775 | (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS2) % crb_pipes ? 1 : 0); | ||||
| 1776 | if (pipes[pipe_cnt].pipe.src.det_size_override > 2 * DCN3_15_MAX_DET_SEGS(384 / 64)) { | ||||
| 1777 | /* Clamp to 2 pipe split max det segments */ | ||||
| 1778 | remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override - 2 * (DCN3_15_MAX_DET_SEGS(384 / 64)); | ||||
| 1779 | pipes[pipe_cnt].pipe.src.det_size_override = 2 * DCN3_15_MAX_DET_SEGS(384 / 64); | ||||
| 1780 | } | ||||
| 1781 | if (pipes[pipe_cnt].pipe.src.det_size_override > DCN3_15_MAX_DET_SEGS(384 / 64) || split_required) { | ||||
| 1782 | /* If we are splitting we must have an even number of segments */ | ||||
| 1783 | remaining_det_segs += pipes[pipe_cnt].pipe.src.det_size_override % 2; | ||||
| 1784 | pipes[pipe_cnt].pipe.src.det_size_override -= pipes[pipe_cnt].pipe.src.det_size_override % 2; | ||||
| 1785 | } | ||||
| 1786 | /* Convert segments into size for DML use */ | ||||
| 1787 | pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB64; | ||||
| 1788 | |||||
| 1789 | crb_idx++; | ||||
| 1790 | } | ||||
| 1791 | pipe_cnt++; | ||||
| 1792 | } | ||||
| 1793 | } | ||||
| 1794 | |||||
| 1795 | if (pipe_cnt
| ||||
| 1796 | context->bw_ctx.dml.ip.det_buffer_size_kbytes = | ||||
| 1797 | (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB64 / pipe_cnt) * DCN3_15_CRB_SEGMENT_SIZE_KB64; | ||||
| 1798 | if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE384) | ||||
| 1799 | context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE384; | ||||
| 1800 | |||||
| 1801 | dc->config.enable_4to1MPC = false0; | ||||
| 1802 | if (pipe_cnt
| ||||
| 1803 | if (is_dual_plane(pipe->plane_state->format) | ||||
| 1804 | && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) { | ||||
| 1805 | dc->config.enable_4to1MPC = true1; | ||||
| 1806 | context->bw_ctx.dml.ip.det_buffer_size_kbytes = | ||||
| 1807 | (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB64 / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB64; | ||||
| 1808 | } else if (!is_dual_plane(pipe->plane_state->format) | ||||
| 1809 | && pipe->plane_state->src_rect.width <= 5120 | ||||
| 1810 | && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { | ||||
| |||||
| 1811 | /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ | ||||
| 1812 | context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; | ||||
| 1813 | pipes[0].pipe.src.unbounded_req_mode = true1; | ||||
| 1814 | } | ||||
| 1815 | } | ||||
| 1816 | |||||
| 1817 | return pipe_cnt; | ||||
| 1818 | } | ||||
| 1819 | |||||
| 1820 | static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_config) | ||||
| 1821 | { | ||||
| 1822 | *panel_config = panel_config_defaults; | ||||
| 1823 | } | ||||
| 1824 | |||||
| 1825 | static struct dc_cap_funcs cap_funcs = { | ||||
| 1826 | .get_dcc_compression_cap = dcn20_get_dcc_compression_cap | ||||
| 1827 | }; | ||||
| 1828 | |||||
| 1829 | static struct resource_funcs dcn315_res_pool_funcs = { | ||||
| 1830 | .destroy = dcn315_destroy_resource_pool, | ||||
| 1831 | .link_enc_create = dcn31_link_encoder_create, | ||||
| 1832 | .link_enc_create_minimal = dcn31_link_enc_create_minimal, | ||||
| 1833 | .link_encs_assign = link_enc_cfg_link_encs_assign, | ||||
| 1834 | .link_enc_unassign = link_enc_cfg_link_enc_unassign, | ||||
| 1835 | .panel_cntl_create = dcn31_panel_cntl_create, | ||||
| 1836 | .validate_bandwidth = dcn31_validate_bandwidth, | ||||
| 1837 | .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg, | ||||
| 1838 | .update_soc_for_wm_a = dcn315_update_soc_for_wm_a, | ||||
| 1839 | .populate_dml_pipes = dcn315_populate_dml_pipes_from_context, | ||||
| 1840 | .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, | ||||
| 1841 | .add_stream_to_ctx = dcn30_add_stream_to_ctx, | ||||
| 1842 | .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, | ||||
| 1843 | .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, | ||||
| 1844 | .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, | ||||
| 1845 | .set_mcif_arb_params = dcn31_set_mcif_arb_params, | ||||
| 1846 | .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, | ||||
| 1847 | .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, | ||||
| 1848 | .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, | ||||
| 1849 | .update_bw_bounding_box = dcn315_update_bw_bounding_box, | ||||
| 1850 | .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, | ||||
| 1851 | .get_panel_config_defaults = dcn315_get_panel_config_defaults, | ||||
| 1852 | }; | ||||
| 1853 | |||||
| 1854 | static bool_Bool dcn315_resource_construct( | ||||
| 1855 | uint8_t num_virtual_links, | ||||
| 1856 | struct dc *dc, | ||||
| 1857 | struct dcn315_resource_pool *pool) | ||||
| 1858 | { | ||||
| 1859 | int i; | ||||
| 1860 | struct dc_context *ctx = dc->ctx; | ||||
| 1861 | struct irq_service_init_data init_data; | ||||
| 1862 | |||||
| 1863 | ctx->dc_bios->regs = &bios_regs; | ||||
| 1864 | |||||
| 1865 | pool->base.res_cap = &res_cap_dcn31; | ||||
| 1866 | |||||
| 1867 | pool->base.funcs = &dcn315_res_pool_funcs; | ||||
| 1868 | |||||
| 1869 | /************************************************* | ||||
| 1870 | * Resource + asic cap harcoding * | ||||
| 1871 | *************************************************/ | ||||
| 1872 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE-1; | ||||
| 1873 | pool->base.pipe_count = pool->base.res_cap->num_timing_generator; | ||||
| 1874 | pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; | ||||
| 1875 | dc->caps.max_downscale_ratio = 600; | ||||
| 1876 | dc->caps.i2c_speed_in_khz = 100; | ||||
| 1877 | dc->caps.i2c_speed_in_khz_hdcp = 100; | ||||
| 1878 | dc->caps.max_cursor_size = 256; | ||||
| 1879 | dc->caps.min_horizontal_blanking_period = 80; | ||||
| 1880 | dc->caps.dmdata_alloc_size = 2048; | ||||
| 1881 | dc->caps.max_slave_planes = 2; | ||||
| 1882 | dc->caps.max_slave_yuv_planes = 2; | ||||
| 1883 | dc->caps.max_slave_rgb_planes = 2; | ||||
| 1884 | dc->caps.post_blend_color_processing = true1; | ||||
| 1885 | dc->caps.force_dp_tps4_for_cp2520 = true1; | ||||
| 1886 | dc->caps.dp_hpo = true1; | ||||
| 1887 | dc->caps.dp_hdmi21_pcon_support = true1; | ||||
| 1888 | dc->caps.edp_dsc_support = true1; | ||||
| 1889 | dc->caps.extended_aux_timeout_support = true1; | ||||
| 1890 | dc->caps.dmcub_support = true1; | ||||
| 1891 | dc->caps.is_apu = true1; | ||||
| 1892 | |||||
| 1893 | /* Color pipeline capabilities */ | ||||
| 1894 | dc->caps.color.dpp.dcn_arch = 1; | ||||
| 1895 | dc->caps.color.dpp.input_lut_shared = 0; | ||||
| 1896 | dc->caps.color.dpp.icsc = 1; | ||||
| 1897 | dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr | ||||
| 1898 | dc->caps.color.dpp.dgam_rom_caps.srgb = 1; | ||||
| 1899 | dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; | ||||
| 1900 | dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; | ||||
| 1901 | dc->caps.color.dpp.dgam_rom_caps.pq = 1; | ||||
| 1902 | dc->caps.color.dpp.dgam_rom_caps.hlg = 1; | ||||
| 1903 | dc->caps.color.dpp.post_csc = 1; | ||||
| 1904 | dc->caps.color.dpp.gamma_corr = 1; | ||||
| 1905 | dc->caps.color.dpp.dgam_rom_for_yuv = 0; | ||||
| 1906 | |||||
| 1907 | dc->caps.color.dpp.hw_3d_lut = 1; | ||||
| 1908 | dc->caps.color.dpp.ogam_ram = 1; | ||||
| 1909 | // no OGAM ROM on DCN301 | ||||
| 1910 | dc->caps.color.dpp.ogam_rom_caps.srgb = 0; | ||||
| 1911 | dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; | ||||
| 1912 | dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; | ||||
| 1913 | dc->caps.color.dpp.ogam_rom_caps.pq = 0; | ||||
| 1914 | dc->caps.color.dpp.ogam_rom_caps.hlg = 0; | ||||
| 1915 | dc->caps.color.dpp.ocsc = 0; | ||||
| 1916 | |||||
| 1917 | dc->caps.color.mpc.gamut_remap = 1; | ||||
| 1918 | dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 | ||||
| 1919 | dc->caps.color.mpc.ogam_ram = 1; | ||||
| 1920 | dc->caps.color.mpc.ogam_rom_caps.srgb = 0; | ||||
| 1921 | dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; | ||||
| 1922 | dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; | ||||
| 1923 | dc->caps.color.mpc.ogam_rom_caps.pq = 0; | ||||
| 1924 | dc->caps.color.mpc.ogam_rom_caps.hlg = 0; | ||||
| 1925 | dc->caps.color.mpc.ocsc = 1; | ||||
| 1926 | |||||
| 1927 | /* read VBIOS LTTPR caps */ | ||||
| 1928 | { | ||||
| 1929 | if (ctx->dc_bios->funcs->get_lttpr_caps) { | ||||
| 1930 | enum bp_result bp_query_result; | ||||
| 1931 | uint8_t is_vbios_lttpr_enable = 0; | ||||
| 1932 | |||||
| 1933 | bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); | ||||
| 1934 | dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; | ||||
| 1935 | } | ||||
| 1936 | |||||
| 1937 | /* interop bit is implicit */ | ||||
| 1938 | { | ||||
| 1939 | dc->caps.vbios_lttpr_aware = true1; | ||||
| 1940 | } | ||||
| 1941 | } | ||||
| 1942 | |||||
| 1943 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) | ||||
| 1944 | dc->debug = debug_defaults_drv; | ||||
| 1945 | else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { | ||||
| 1946 | dc->debug = debug_defaults_diags; | ||||
| 1947 | } else | ||||
| 1948 | dc->debug = debug_defaults_diags; | ||||
| 1949 | // Init the vm_helper | ||||
| 1950 | if (dc->vm_helper) | ||||
| 1951 | vm_helper_init(dc->vm_helper, 16); | ||||
| 1952 | |||||
| 1953 | /************************************************* | ||||
| 1954 | * Create resources * | ||||
| 1955 | *************************************************/ | ||||
| 1956 | |||||
| 1957 | /* Clock Sources for Pixel Clock*/ | ||||
| 1958 | pool->base.clock_sources[DCN31_CLK_SRC_PLL0] = | ||||
| 1959 | dcn31_clock_source_create(ctx, ctx->dc_bios, | ||||
| 1960 | CLOCK_SOURCE_COMBO_PHY_PLL0, | ||||
| 1961 | &clk_src_regs[0], false0); | ||||
| 1962 | pool->base.clock_sources[DCN31_CLK_SRC_PLL1] = | ||||
| 1963 | dcn31_clock_source_create(ctx, ctx->dc_bios, | ||||
| 1964 | CLOCK_SOURCE_COMBO_PHY_PLL1, | ||||
| 1965 | &clk_src_regs[1], false0); | ||||
| 1966 | pool->base.clock_sources[DCN31_CLK_SRC_PLL2] = | ||||
| 1967 | dcn31_clock_source_create(ctx, ctx->dc_bios, | ||||
| 1968 | CLOCK_SOURCE_COMBO_PHY_PLL2, | ||||
| 1969 | &clk_src_regs[2], false0); | ||||
| 1970 | pool->base.clock_sources[DCN31_CLK_SRC_PLL3] = | ||||
| 1971 | dcn31_clock_source_create(ctx, ctx->dc_bios, | ||||
| 1972 | CLOCK_SOURCE_COMBO_PHY_PLL3, | ||||
| 1973 | &clk_src_regs[3], false0); | ||||
| 1974 | pool->base.clock_sources[DCN31_CLK_SRC_PLL4] = | ||||
| 1975 | dcn31_clock_source_create(ctx, ctx->dc_bios, | ||||
| 1976 | CLOCK_SOURCE_COMBO_PHY_PLL4, | ||||
| 1977 | &clk_src_regs[4], false0); | ||||
| 1978 | |||||
| 1979 | pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; | ||||
| 1980 | |||||
| 1981 | /* todo: not reuse phy_pll registers */ | ||||
| 1982 | pool->base.dp_clock_source = | ||||
| 1983 | dcn31_clock_source_create(ctx, ctx->dc_bios, | ||||
| 1984 | CLOCK_SOURCE_ID_DP_DTO, | ||||
| 1985 | &clk_src_regs[0], true1); | ||||
| 1986 | |||||
| 1987 | for (i = 0; i < pool->base.clk_src_count; i++) { | ||||
| 1988 | if (pool->base.clock_sources[i] == NULL((void *)0)) { | ||||
| 1989 | dm_error("DC: failed to create clock sources!\n")__drm_err("DC: failed to create clock sources!\n"); | ||||
| 1990 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 1990); do {} while (0); } while (0); | ||||
| 1991 | goto create_fail; | ||||
| 1992 | } | ||||
| 1993 | } | ||||
| 1994 | |||||
| 1995 | /* TODO: DCCG */ | ||||
| 1996 | pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); | ||||
| 1997 | if (pool->base.dccg == NULL((void *)0)) { | ||||
| 1998 | dm_error("DC: failed to create dccg!\n")__drm_err("DC: failed to create dccg!\n"); | ||||
| 1999 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 1999); do {} while (0); } while (0); | ||||
| 2000 | goto create_fail; | ||||
| 2001 | } | ||||
| 2002 | |||||
| 2003 | /* TODO: IRQ */ | ||||
| 2004 | init_data.ctx = dc->ctx; | ||||
| 2005 | pool->base.irqs = dal_irq_service_dcn315_create(&init_data); | ||||
| 2006 | if (!pool->base.irqs) | ||||
| 2007 | goto create_fail; | ||||
| 2008 | |||||
| 2009 | /* HUBBUB */ | ||||
| 2010 | pool->base.hubbub = dcn31_hubbub_create(ctx); | ||||
| 2011 | if (pool->base.hubbub == NULL((void *)0)) { | ||||
| 2012 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2012); do {} while (0); } while (0); | ||||
| 2013 | dm_error("DC: failed to create hubbub!\n")__drm_err("DC: failed to create hubbub!\n"); | ||||
| 2014 | goto create_fail; | ||||
| 2015 | } | ||||
| 2016 | |||||
| 2017 | /* HUBPs, DPPs, OPPs and TGs */ | ||||
| 2018 | for (i = 0; i < pool->base.pipe_count; i++) { | ||||
| 2019 | pool->base.hubps[i] = dcn31_hubp_create(ctx, i); | ||||
| 2020 | if (pool->base.hubps[i] == NULL((void *)0)) { | ||||
| 2021 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2021); do {} while (0); } while (0); | ||||
| 2022 | dm_error(__drm_err("DC: failed to create hubps!\n") | ||||
| 2023 | "DC: failed to create hubps!\n")__drm_err("DC: failed to create hubps!\n"); | ||||
| 2024 | goto create_fail; | ||||
| 2025 | } | ||||
| 2026 | |||||
| 2027 | pool->base.dpps[i] = dcn31_dpp_create(ctx, i); | ||||
| 2028 | if (pool->base.dpps[i] == NULL((void *)0)) { | ||||
| 2029 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2029); do {} while (0); } while (0); | ||||
| 2030 | dm_error(__drm_err("DC: failed to create dpps!\n") | ||||
| 2031 | "DC: failed to create dpps!\n")__drm_err("DC: failed to create dpps!\n"); | ||||
| 2032 | goto create_fail; | ||||
| 2033 | } | ||||
| 2034 | } | ||||
| 2035 | |||||
| 2036 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | ||||
| 2037 | pool->base.opps[i] = dcn31_opp_create(ctx, i); | ||||
| 2038 | if (pool->base.opps[i] == NULL((void *)0)) { | ||||
| 2039 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2039); do {} while (0); } while (0); | ||||
| 2040 | dm_error(__drm_err("DC: failed to create output pixel processor!\n") | ||||
| 2041 | "DC: failed to create output pixel processor!\n")__drm_err("DC: failed to create output pixel processor!\n"); | ||||
| 2042 | goto create_fail; | ||||
| 2043 | } | ||||
| 2044 | } | ||||
| 2045 | |||||
| 2046 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | ||||
| 2047 | pool->base.timing_generators[i] = dcn31_timing_generator_create( | ||||
| 2048 | ctx, i); | ||||
| 2049 | if (pool->base.timing_generators[i] == NULL((void *)0)) { | ||||
| 2050 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2050); do {} while (0); } while (0); | ||||
| 2051 | dm_error("DC: failed to create tg!\n")__drm_err("DC: failed to create tg!\n"); | ||||
| 2052 | goto create_fail; | ||||
| 2053 | } | ||||
| 2054 | } | ||||
| 2055 | pool->base.timing_generator_count = i; | ||||
| 2056 | |||||
| 2057 | /* PSR */ | ||||
| 2058 | pool->base.psr = dmub_psr_create(ctx); | ||||
| 2059 | if (pool->base.psr == NULL((void *)0)) { | ||||
| 2060 | dm_error("DC: failed to create psr obj!\n")__drm_err("DC: failed to create psr obj!\n"); | ||||
| 2061 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2061); do {} while (0); } while (0); | ||||
| 2062 | goto create_fail; | ||||
| 2063 | } | ||||
| 2064 | |||||
| 2065 | /* ABM */ | ||||
| 2066 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | ||||
| 2067 | pool->base.multiple_abms[i] = dmub_abm_create(ctx, | ||||
| 2068 | &abm_regs[i], | ||||
| 2069 | &abm_shift, | ||||
| 2070 | &abm_mask); | ||||
| 2071 | if (pool->base.multiple_abms[i] == NULL((void *)0)) { | ||||
| 2072 | dm_error("DC: failed to create abm for pipe %d!\n", i)__drm_err("DC: failed to create abm for pipe %d!\n", i); | ||||
| 2073 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2073); do {} while (0); } while (0); | ||||
| 2074 | goto create_fail; | ||||
| 2075 | } | ||||
| 2076 | } | ||||
| 2077 | |||||
| 2078 | /* MPC and DSC */ | ||||
| 2079 | pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); | ||||
| 2080 | if (pool->base.mpc == NULL((void *)0)) { | ||||
| 2081 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2081); do {} while (0); } while (0); | ||||
| 2082 | dm_error("DC: failed to create mpc!\n")__drm_err("DC: failed to create mpc!\n"); | ||||
| 2083 | goto create_fail; | ||||
| 2084 | } | ||||
| 2085 | |||||
| 2086 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { | ||||
| 2087 | pool->base.dscs[i] = dcn31_dsc_create(ctx, i); | ||||
| 2088 | if (pool->base.dscs[i] == NULL((void *)0)) { | ||||
| 2089 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2089); do {} while (0); } while (0); | ||||
| 2090 | dm_error("DC: failed to create display stream compressor %d!\n", i)__drm_err("DC: failed to create display stream compressor %d!\n" , i); | ||||
| 2091 | goto create_fail; | ||||
| 2092 | } | ||||
| 2093 | } | ||||
| 2094 | |||||
| 2095 | /* DWB and MMHUBBUB */ | ||||
| 2096 | if (!dcn31_dwbc_create(ctx, &pool->base)) { | ||||
| 2097 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2097); do {} while (0); } while (0); | ||||
| 2098 | dm_error("DC: failed to create dwbc!\n")__drm_err("DC: failed to create dwbc!\n"); | ||||
| 2099 | goto create_fail; | ||||
| 2100 | } | ||||
| 2101 | |||||
| 2102 | if (!dcn31_mmhubbub_create(ctx, &pool->base)) { | ||||
| 2103 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2103); do {} while (0); } while (0); | ||||
| 2104 | dm_error("DC: failed to create mcif_wb!\n")__drm_err("DC: failed to create mcif_wb!\n"); | ||||
| 2105 | goto create_fail; | ||||
| 2106 | } | ||||
| 2107 | |||||
| 2108 | /* AUX and I2C */ | ||||
| 2109 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | ||||
| 2110 | pool->base.engines[i] = dcn31_aux_engine_create(ctx, i); | ||||
| 2111 | if (pool->base.engines[i] == NULL((void *)0)) { | ||||
| 2112 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2112); do {} while (0); } while (0); | ||||
| 2113 | dm_error(__drm_err("DC:failed to create aux engine!!\n") | ||||
| 2114 | "DC:failed to create aux engine!!\n")__drm_err("DC:failed to create aux engine!!\n"); | ||||
| 2115 | goto create_fail; | ||||
| 2116 | } | ||||
| 2117 | pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i); | ||||
| 2118 | if (pool->base.hw_i2cs[i] == NULL((void *)0)) { | ||||
| 2119 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2119); do {} while (0); } while (0); | ||||
| 2120 | dm_error(__drm_err("DC:failed to create hw i2c!!\n") | ||||
| 2121 | "DC:failed to create hw i2c!!\n")__drm_err("DC:failed to create hw i2c!!\n"); | ||||
| 2122 | goto create_fail; | ||||
| 2123 | } | ||||
| 2124 | pool->base.sw_i2cs[i] = NULL((void *)0); | ||||
| 2125 | } | ||||
| 2126 | |||||
| 2127 | /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ | ||||
| 2128 | if (!resource_construct(num_virtual_links, dc, &pool->base, | ||||
| 2129 | (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) ? | ||||
| 2130 | &res_create_funcs : &res_create_maximus_funcs))) | ||||
| 2131 | goto create_fail; | ||||
| 2132 | |||||
| 2133 | /* HW Sequencer and Plane caps */ | ||||
| 2134 | dcn31_hw_sequencer_construct(dc); | ||||
| 2135 | |||||
| 2136 | dc->caps.max_planes = pool->base.pipe_count; | ||||
| 2137 | |||||
| 2138 | for (i = 0; i < dc->caps.max_planes; ++i) | ||||
| 2139 | dc->caps.planes[i] = plane_cap; | ||||
| 2140 | |||||
| 2141 | dc->cap_funcs = cap_funcs; | ||||
| 2142 | |||||
| 2143 | dc->dcn_ip->max_num_dpp = dcn3_15_ip.max_num_dpp; | ||||
| 2144 | |||||
| 2145 | return true1; | ||||
| 2146 | |||||
| 2147 | create_fail: | ||||
| 2148 | |||||
| 2149 | dcn315_resource_destruct(pool); | ||||
| 2150 | |||||
| 2151 | return false0; | ||||
| 2152 | } | ||||
| 2153 | |||||
| 2154 | struct resource_pool *dcn315_create_resource_pool( | ||||
| 2155 | const struct dc_init_data *init_data, | ||||
| 2156 | struct dc *dc) | ||||
| 2157 | { | ||||
| 2158 | struct dcn315_resource_pool *pool = | ||||
| 2159 | kzalloc(sizeof(struct dcn315_resource_pool), GFP_KERNEL(0x0001 | 0x0004)); | ||||
| 2160 | |||||
| 2161 | if (!pool) | ||||
| 2162 | return NULL((void *)0); | ||||
| 2163 | |||||
| 2164 | if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool)) | ||||
| 2165 | return &pool->base; | ||||
| 2166 | |||||
| 2167 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 2167); do {} while (0); } while (0); | ||||
| 2168 | kfree(pool); | ||||
| 2169 | return NULL((void *)0); | ||||
| 2170 | } |