File: | dev/pci/drm/amd/amdgpu/gmc_v7_0.c |
Warning: | line 1217, column 3 Value stored to 'tmp' is never read |
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1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/firmware.h> |
25 | #include <linux/module.h> |
26 | #include <linux/pci.h> |
27 | |
28 | #include <drm/drm_cache.h> |
29 | #include "amdgpu.h" |
30 | #include "cikd.h" |
31 | #include "cik.h" |
32 | #include "gmc_v7_0.h" |
33 | #include "amdgpu_ucode.h" |
34 | #include "amdgpu_amdkfd.h" |
35 | #include "amdgpu_gem.h" |
36 | |
37 | #include "bif/bif_4_1_d.h" |
38 | #include "bif/bif_4_1_sh_mask.h" |
39 | |
40 | #include "gmc/gmc_7_1_d.h" |
41 | #include "gmc/gmc_7_1_sh_mask.h" |
42 | |
43 | #include "oss/oss_2_0_d.h" |
44 | #include "oss/oss_2_0_sh_mask.h" |
45 | |
46 | #include "dce/dce_8_0_d.h" |
47 | #include "dce/dce_8_0_sh_mask.h" |
48 | |
49 | #include "amdgpu_atombios.h" |
50 | |
51 | #include "ivsrcid/ivsrcid_vislands30.h" |
52 | |
53 | static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); |
54 | static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); |
55 | static int gmc_v7_0_wait_for_idle(void *handle); |
56 | |
57 | MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); |
58 | MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); |
59 | MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); |
60 | |
61 | static const u32 golden_settings_iceland_a11[] = |
62 | { |
63 | mmVM_PRT_APERTURE0_LOW_ADDR0x52c, 0x0fffffff, 0x0fffffff, |
64 | mmVM_PRT_APERTURE1_LOW_ADDR0x52d, 0x0fffffff, 0x0fffffff, |
65 | mmVM_PRT_APERTURE2_LOW_ADDR0x52e, 0x0fffffff, 0x0fffffff, |
66 | mmVM_PRT_APERTURE3_LOW_ADDR0x52f, 0x0fffffff, 0x0fffffff |
67 | }; |
68 | |
69 | static const u32 iceland_mgcg_cgcg_init[] = |
70 | { |
71 | mmMC_MEM_POWER_LS0x82a, 0xffffffff, 0x00000104 |
72 | }; |
73 | |
74 | static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) |
75 | { |
76 | switch (adev->asic_type) { |
77 | case CHIP_TOPAZ: |
78 | amdgpu_device_program_register_sequence(adev, |
79 | iceland_mgcg_cgcg_init, |
80 | ARRAY_SIZE(iceland_mgcg_cgcg_init)(sizeof((iceland_mgcg_cgcg_init)) / sizeof((iceland_mgcg_cgcg_init )[0]))); |
81 | amdgpu_device_program_register_sequence(adev, |
82 | golden_settings_iceland_a11, |
83 | ARRAY_SIZE(golden_settings_iceland_a11)(sizeof((golden_settings_iceland_a11)) / sizeof((golden_settings_iceland_a11 )[0]))); |
84 | break; |
85 | default: |
86 | break; |
87 | } |
88 | } |
89 | |
90 | static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) |
91 | { |
92 | u32 blackout; |
93 | |
94 | gmc_v7_0_wait_for_idle((void *)adev); |
95 | |
96 | blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL)amdgpu_device_rreg(adev, (0x82b), 0); |
97 | if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE)(((blackout) & 0x7) >> 0x0) != 1) { |
98 | /* Block CPU access */ |
99 | WREG32(mmBIF_FB_EN, 0)amdgpu_device_wreg(adev, (0x1524), (0), 0); |
100 | /* blackout the MC */ |
101 | blackout = REG_SET_FIELD(blackout,(((blackout) & ~0x7) | (0x7 & ((0) << 0x0))) |
102 | MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0)(((blackout) & ~0x7) | (0x7 & ((0) << 0x0))); |
103 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1)amdgpu_device_wreg(adev, (0x82b), (blackout | 1), 0); |
104 | } |
105 | /* wait for the MC to settle */ |
106 | udelay(100); |
107 | } |
108 | |
109 | static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) |
110 | { |
111 | u32 tmp; |
112 | |
113 | /* unblackout the MC */ |
114 | tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL)amdgpu_device_rreg(adev, (0x82b), 0); |
115 | tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0)(((tmp) & ~0x7) | (0x7 & ((0) << 0x0))); |
116 | WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp)amdgpu_device_wreg(adev, (0x82b), (tmp), 0); |
117 | /* allow CPU access */ |
118 | tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1)(((0) & ~0x1) | (0x1 & ((1) << 0x0))); |
119 | tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1))); |
120 | WREG32(mmBIF_FB_EN, tmp)amdgpu_device_wreg(adev, (0x1524), (tmp), 0); |
121 | } |
122 | |
123 | /** |
124 | * gmc_v7_0_init_microcode - load ucode images from disk |
125 | * |
126 | * @adev: amdgpu_device pointer |
127 | * |
128 | * Use the firmware interface to load the ucode images into |
129 | * the driver (not loaded into hw). |
130 | * Returns 0 on success, error on failure. |
131 | */ |
132 | static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) |
133 | { |
134 | const char *chip_name; |
135 | char fw_name[30]; |
136 | int err; |
137 | |
138 | DRM_DEBUG("\n")___drm_dbg(((void *)0), DRM_UT_CORE, "\n"); |
139 | |
140 | switch (adev->asic_type) { |
141 | case CHIP_BONAIRE: |
142 | chip_name = "bonaire"; |
143 | break; |
144 | case CHIP_HAWAII: |
145 | chip_name = "hawaii"; |
146 | break; |
147 | case CHIP_TOPAZ: |
148 | chip_name = "topaz"; |
149 | break; |
150 | case CHIP_KAVERI: |
151 | case CHIP_KABINI: |
152 | case CHIP_MULLINS: |
153 | return 0; |
154 | default: BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c" , 154); } while (0); |
155 | } |
156 | |
157 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); |
158 | |
159 | err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); |
160 | if (err) |
161 | goto out; |
162 | err = amdgpu_ucode_validate(adev->gmc.fw); |
163 | |
164 | out: |
165 | if (err) { |
166 | pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name)printk("\0013" "amdgpu: " "cik_mc: Failed to load firmware \"%s\"\n" , fw_name); |
167 | release_firmware(adev->gmc.fw); |
168 | adev->gmc.fw = NULL((void *)0); |
169 | } |
170 | return err; |
171 | } |
172 | |
173 | /** |
174 | * gmc_v7_0_mc_load_microcode - load MC ucode into the hw |
175 | * |
176 | * @adev: amdgpu_device pointer |
177 | * |
178 | * Load the GDDR MC ucode into the hw (CIK). |
179 | * Returns 0 on success, error on failure. |
180 | */ |
181 | static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) |
182 | { |
183 | const struct mc_firmware_header_v1_0 *hdr; |
184 | const __le32 *fw_data = NULL((void *)0); |
185 | const __le32 *io_mc_regs = NULL((void *)0); |
186 | u32 running; |
187 | int i, ucode_size, regs_size; |
188 | |
189 | if (!adev->gmc.fw) |
190 | return -EINVAL22; |
191 | |
192 | hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; |
193 | amdgpu_ucode_print_mc_hdr(&hdr->header); |
194 | |
195 | adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version)); |
196 | regs_size = le32_to_cpu(hdr->io_debug_size_bytes)((__uint32_t)(hdr->io_debug_size_bytes)) / (4 * 2); |
197 | io_mc_regs = (const __le32 *) |
198 | (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)((__uint32_t)(hdr->io_debug_array_offset_bytes))); |
199 | ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes)((__uint32_t)(hdr->header.ucode_size_bytes)) / 4; |
200 | fw_data = (const __le32 *) |
201 | (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes))); |
202 | |
203 | running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN)(((amdgpu_device_rreg(adev, (0xa32), 0)) & 0x1) >> 0x0 ); |
204 | |
205 | if (running == 0) { |
206 | /* reset the engine and set to writable */ |
207 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008)amdgpu_device_wreg(adev, (0xa32), (0x00000008), 0); |
208 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010)amdgpu_device_wreg(adev, (0xa32), (0x00000010), 0); |
209 | |
210 | /* load mc io regs */ |
211 | for (i = 0; i < regs_size; i++) { |
212 | WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++))amdgpu_device_wreg(adev, (0xa91), (((__uint32_t)(*(__uint32_t *)(io_mc_regs++)))), 0); |
213 | WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++))amdgpu_device_wreg(adev, (0xa92), (((__uint32_t)(*(__uint32_t *)(io_mc_regs++)))), 0); |
214 | } |
215 | /* load the MC ucode */ |
216 | for (i = 0; i < ucode_size; i++) |
217 | WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, (0xa33), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0); |
218 | |
219 | /* put the engine back into the active state */ |
220 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008)amdgpu_device_wreg(adev, (0xa32), (0x00000008), 0); |
221 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004)amdgpu_device_wreg(adev, (0xa32), (0x00000004), 0); |
222 | WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001)amdgpu_device_wreg(adev, (0xa32), (0x00000001), 0); |
223 | |
224 | /* wait for training to complete */ |
225 | for (i = 0; i < adev->usec_timeout; i++) { |
226 | if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),(((amdgpu_device_rreg(adev, (0xa3a), 0)) & 0x40000000) >> 0x1e) |
227 | MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)(((amdgpu_device_rreg(adev, (0xa3a), 0)) & 0x40000000) >> 0x1e)) |
228 | break; |
229 | udelay(1); |
230 | } |
231 | for (i = 0; i < adev->usec_timeout; i++) { |
232 | if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),(((amdgpu_device_rreg(adev, (0xa3a), 0)) & 0x80000000) >> 0x1f) |
233 | MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)(((amdgpu_device_rreg(adev, (0xa3a), 0)) & 0x80000000) >> 0x1f)) |
234 | break; |
235 | udelay(1); |
236 | } |
237 | } |
238 | |
239 | return 0; |
240 | } |
241 | |
242 | static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, |
243 | struct amdgpu_gmc *mc) |
244 | { |
245 | u64 base = RREG32(mmMC_VM_FB_LOCATION)amdgpu_device_rreg(adev, (0x809), 0) & 0xFFFF; |
246 | base <<= 24; |
247 | |
248 | amdgpu_gmc_vram_location(adev, mc, base); |
249 | amdgpu_gmc_gart_location(adev, mc); |
250 | } |
251 | |
252 | /** |
253 | * gmc_v7_0_mc_program - program the GPU memory controller |
254 | * |
255 | * @adev: amdgpu_device pointer |
256 | * |
257 | * Set the location of vram, gart, and AGP in the GPU's |
258 | * physical address space (CIK). |
259 | */ |
260 | static void gmc_v7_0_mc_program(struct amdgpu_device *adev) |
261 | { |
262 | u32 tmp; |
263 | int i, j; |
264 | |
265 | /* Initialize HDP */ |
266 | for (i = 0, j = 0; i < 32; i++, j += 0x6) { |
267 | WREG32((0xb05 + j), 0x00000000)amdgpu_device_wreg(adev, ((0xb05 + j)), (0x00000000), 0); |
268 | WREG32((0xb06 + j), 0x00000000)amdgpu_device_wreg(adev, ((0xb06 + j)), (0x00000000), 0); |
269 | WREG32((0xb07 + j), 0x00000000)amdgpu_device_wreg(adev, ((0xb07 + j)), (0x00000000), 0); |
270 | WREG32((0xb08 + j), 0x00000000)amdgpu_device_wreg(adev, ((0xb08 + j)), (0x00000000), 0); |
271 | WREG32((0xb09 + j), 0x00000000)amdgpu_device_wreg(adev, ((0xb09 + j)), (0x00000000), 0); |
272 | } |
273 | WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0)amdgpu_device_wreg(adev, (0x1528), (0), 0); |
274 | |
275 | if (gmc_v7_0_wait_for_idle((void *)adev)) { |
276 | dev_warn(adev->dev, "Wait for MC idle timedout !\n")printf("drm:pid%d:%s *WARNING* " "Wait for MC idle timedout !\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
277 | } |
278 | if (adev->mode_info.num_crtc) { |
279 | /* Lockout access through VGA aperture*/ |
280 | tmp = RREG32(mmVGA_HDP_CONTROL)amdgpu_device_rreg(adev, (0xca), 0); |
281 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); |
282 | WREG32(mmVGA_HDP_CONTROL, tmp)amdgpu_device_wreg(adev, (0xca), (tmp), 0); |
283 | |
284 | /* disable VGA render */ |
285 | tmp = RREG32(mmVGA_RENDER_CONTROL)amdgpu_device_rreg(adev, (0xc0), 0); |
286 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0)(((tmp) & ~0x30000) | (0x30000 & ((0) << 0x10)) ); |
287 | WREG32(mmVGA_RENDER_CONTROL, tmp)amdgpu_device_wreg(adev, (0xc0), (tmp), 0); |
288 | } |
289 | /* Update configuration */ |
290 | WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,amdgpu_device_wreg(adev, (0x80d), (adev->gmc.vram_start >> 12), 0) |
291 | adev->gmc.vram_start >> 12)amdgpu_device_wreg(adev, (0x80d), (adev->gmc.vram_start >> 12), 0); |
292 | WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,amdgpu_device_wreg(adev, (0x80e), (adev->gmc.vram_end >> 12), 0) |
293 | adev->gmc.vram_end >> 12)amdgpu_device_wreg(adev, (0x80e), (adev->gmc.vram_end >> 12), 0); |
294 | WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,amdgpu_device_wreg(adev, (0x80f), (adev->vram_scratch.gpu_addr >> 12), 0) |
295 | adev->vram_scratch.gpu_addr >> 12)amdgpu_device_wreg(adev, (0x80f), (adev->vram_scratch.gpu_addr >> 12), 0); |
296 | WREG32(mmMC_VM_AGP_BASE, 0)amdgpu_device_wreg(adev, (0x80c), (0), 0); |
297 | WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF)amdgpu_device_wreg(adev, (0x80a), (0x0FFFFFFF), 0); |
298 | WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF)amdgpu_device_wreg(adev, (0x80b), (0x0FFFFFFF), 0); |
299 | if (gmc_v7_0_wait_for_idle((void *)adev)) { |
300 | dev_warn(adev->dev, "Wait for MC idle timedout !\n")printf("drm:pid%d:%s *WARNING* " "Wait for MC idle timedout !\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
301 | } |
302 | |
303 | WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK)amdgpu_device_wreg(adev, (0x1524), (0x1 | 0x2), 0); |
304 | |
305 | tmp = RREG32(mmHDP_MISC_CNTL)amdgpu_device_rreg(adev, (0xbd3), 0); |
306 | tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0))); |
307 | WREG32(mmHDP_MISC_CNTL, tmp)amdgpu_device_wreg(adev, (0xbd3), (tmp), 0); |
308 | |
309 | tmp = RREG32(mmHDP_HOST_PATH_CNTL)amdgpu_device_rreg(adev, (0xb00), 0); |
310 | WREG32(mmHDP_HOST_PATH_CNTL, tmp)amdgpu_device_wreg(adev, (0xb00), (tmp), 0); |
311 | } |
312 | |
313 | /** |
314 | * gmc_v7_0_mc_init - initialize the memory controller driver params |
315 | * |
316 | * @adev: amdgpu_device pointer |
317 | * |
318 | * Look up the amount of vram, vram width, and decide how to place |
319 | * vram and gart within the GPU's physical address space (CIK). |
320 | * Returns 0 for success. |
321 | */ |
322 | static int gmc_v7_0_mc_init(struct amdgpu_device *adev) |
323 | { |
324 | int r; |
325 | |
326 | adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); |
327 | if (!adev->gmc.vram_width) { |
328 | u32 tmp; |
329 | int chansize, numchan; |
330 | |
331 | /* Get VRAM informations */ |
332 | tmp = RREG32(mmMC_ARB_RAMCFG)amdgpu_device_rreg(adev, (0x9d8), 0); |
333 | if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)(((tmp) & 0x100) >> 0x8)) { |
334 | chansize = 64; |
335 | } else { |
336 | chansize = 32; |
337 | } |
338 | tmp = RREG32(mmMC_SHARED_CHMAP)amdgpu_device_rreg(adev, (0x801), 0); |
339 | switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)(((tmp) & 0xf000) >> 0xc)) { |
340 | case 0: |
341 | default: |
342 | numchan = 1; |
343 | break; |
344 | case 1: |
345 | numchan = 2; |
346 | break; |
347 | case 2: |
348 | numchan = 4; |
349 | break; |
350 | case 3: |
351 | numchan = 8; |
352 | break; |
353 | case 4: |
354 | numchan = 3; |
355 | break; |
356 | case 5: |
357 | numchan = 6; |
358 | break; |
359 | case 6: |
360 | numchan = 10; |
361 | break; |
362 | case 7: |
363 | numchan = 12; |
364 | break; |
365 | case 8: |
366 | numchan = 16; |
367 | break; |
368 | } |
369 | adev->gmc.vram_width = numchan * chansize; |
370 | } |
371 | /* size in MB on si */ |
372 | adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE)amdgpu_device_rreg(adev, (0x150a), 0) * 1024ULL * 1024ULL; |
373 | adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE)amdgpu_device_rreg(adev, (0x150a), 0) * 1024ULL * 1024ULL; |
374 | |
375 | if (!(adev->flags & AMD_IS_APU)) { |
376 | r = amdgpu_device_resize_fb_bar(adev); |
377 | if (r) |
378 | return r; |
379 | } |
380 | adev->gmc.aper_base = adev->fb_aper_offset; |
381 | adev->gmc.aper_size = adev->fb_aper_size; |
382 | |
383 | #ifdef CONFIG_X86_641 |
384 | if ((adev->flags & AMD_IS_APU) && |
385 | adev->gmc.real_vram_size > adev->gmc.aper_size && |
386 | !amdgpu_passthrough(adev)((adev)->virt.caps & (1 << 3))) { |
387 | adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)amdgpu_device_rreg(adev, (0x81a), 0)) << 22; |
388 | adev->gmc.aper_size = adev->gmc.real_vram_size; |
389 | } |
390 | #endif |
391 | |
392 | /* In case the PCI BAR is larger than the actual amount of vram */ |
393 | adev->gmc.visible_vram_size = adev->gmc.aper_size; |
394 | if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) |
395 | adev->gmc.visible_vram_size = adev->gmc.real_vram_size; |
396 | |
397 | /* set the gart size */ |
398 | if (amdgpu_gart_size == -1) { |
399 | switch (adev->asic_type) { |
400 | case CHIP_TOPAZ: /* no MM engines */ |
401 | default: |
402 | adev->gmc.gart_size = 256ULL << 20; |
403 | break; |
404 | #ifdef CONFIG_DRM_AMDGPU_CIK |
405 | case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ |
406 | case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ |
407 | case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ |
408 | case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ |
409 | case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ |
410 | adev->gmc.gart_size = 1024ULL << 20; |
411 | break; |
412 | #endif |
413 | } |
414 | } else { |
415 | adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; |
416 | } |
417 | |
418 | adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; |
419 | gmc_v7_0_vram_gtt_location(adev, &adev->gmc); |
420 | |
421 | return 0; |
422 | } |
423 | |
424 | /** |
425 | * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid |
426 | * |
427 | * @adev: amdgpu_device pointer |
428 | * @pasid: pasid to be flush |
429 | * @flush_type: type of flush |
430 | * @all_hub: flush all hubs |
431 | * |
432 | * Flush the TLB for the requested pasid. |
433 | */ |
434 | static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, |
435 | uint16_t pasid, uint32_t flush_type, |
436 | bool_Bool all_hub) |
437 | { |
438 | int vmid; |
439 | unsigned int tmp; |
440 | |
441 | if (amdgpu_in_reset(adev)) |
442 | return -EIO5; |
443 | |
444 | for (vmid = 1; vmid < 16; vmid++) { |
445 | |
446 | tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid)amdgpu_device_rreg(adev, (0xce7 + vmid), 0); |
447 | if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK0x80000000) && |
448 | (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK0xffff) == pasid) { |
449 | WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid)amdgpu_device_wreg(adev, (0x51e), (1 << vmid), 0); |
450 | RREG32(mmVM_INVALIDATE_RESPONSE)amdgpu_device_rreg(adev, (0x51f), 0); |
451 | break; |
452 | } |
453 | } |
454 | |
455 | return 0; |
456 | } |
457 | |
458 | /* |
459 | * GART |
460 | * VMID 0 is the physical GPU addresses as used by the kernel. |
461 | * VMIDs 1-15 are used for userspace clients and are handled |
462 | * by the amdgpu vm/hsa code. |
463 | */ |
464 | |
465 | /** |
466 | * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback |
467 | * |
468 | * @adev: amdgpu_device pointer |
469 | * @vmid: vm instance to flush |
470 | * @vmhub: which hub to flush |
471 | * @flush_type: type of flush |
472 | * * |
473 | * Flush the TLB for the requested page table (CIK). |
474 | */ |
475 | static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, |
476 | uint32_t vmhub, uint32_t flush_type) |
477 | { |
478 | /* bits 0-15 are the VM contexts0-15 */ |
479 | WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid)amdgpu_device_wreg(adev, (0x51e), (1 << vmid), 0); |
480 | } |
481 | |
482 | static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, |
483 | unsigned vmid, uint64_t pd_addr) |
484 | { |
485 | uint32_t reg; |
486 | |
487 | if (vmid < 8) |
488 | reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR0x54f + vmid; |
489 | else |
490 | reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR0x50e + vmid - 8; |
491 | amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12)(ring)->funcs->emit_wreg((ring), (reg), (pd_addr >> 12)); |
492 | |
493 | /* bits 0-15 are the VM contexts0-15 */ |
494 | amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid)(ring)->funcs->emit_wreg((ring), (0x51e), (1 << vmid )); |
495 | |
496 | return pd_addr; |
497 | } |
498 | |
499 | static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, |
500 | unsigned pasid) |
501 | { |
502 | amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid)(ring)->funcs->emit_wreg((ring), (0xf50 + vmid), (pasid )); |
503 | } |
504 | |
505 | static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, |
506 | uint64_t *addr, uint64_t *flags) |
507 | { |
508 | BUG_ON(*addr & 0xFFFFFF0000000FFFULL)((!(*addr & 0xFFFFFF0000000FFFULL)) ? (void)0 : __assert( "diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gmc_v7_0.c" , 508, "!(*addr & 0xFFFFFF0000000FFFULL)")); |
509 | } |
510 | |
511 | static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, |
512 | struct amdgpu_bo_va_mapping *mapping, |
513 | uint64_t *flags) |
514 | { |
515 | *flags &= ~AMDGPU_PTE_EXECUTABLE(1ULL << 4); |
516 | *flags &= ~AMDGPU_PTE_PRT(1ULL << 51); |
517 | } |
518 | |
519 | /** |
520 | * gmc_v7_0_set_fault_enable_default - update VM fault handling |
521 | * |
522 | * @adev: amdgpu_device pointer |
523 | * @value: true redirects VM faults to the default page |
524 | */ |
525 | static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, |
526 | bool_Bool value) |
527 | { |
528 | u32 tmp; |
529 | |
530 | tmp = RREG32(mmVM_CONTEXT1_CNTL)amdgpu_device_rreg(adev, (0x505), 0); |
531 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,(((tmp) & ~0x10) | (0x10 & ((value) << 0x4))) |
532 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value)(((tmp) & ~0x10) | (0x10 & ((value) << 0x4))); |
533 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,(((tmp) & ~0x80) | (0x80 & ((value) << 0x7))) |
534 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value)(((tmp) & ~0x80) | (0x80 & ((value) << 0x7))); |
535 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,(((tmp) & ~0x400) | (0x400 & ((value) << 0xa))) |
536 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value)(((tmp) & ~0x400) | (0x400 & ((value) << 0xa))); |
537 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,(((tmp) & ~0x2000) | (0x2000 & ((value) << 0xd) )) |
538 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value)(((tmp) & ~0x2000) | (0x2000 & ((value) << 0xd) )); |
539 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,(((tmp) & ~0x10000) | (0x10000 & ((value) << 0x10 ))) |
540 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, value)(((tmp) & ~0x10000) | (0x10000 & ((value) << 0x10 ))); |
541 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,(((tmp) & ~0x80000) | (0x80000 & ((value) << 0x13 ))) |
542 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value)(((tmp) & ~0x80000) | (0x80000 & ((value) << 0x13 ))); |
543 | WREG32(mmVM_CONTEXT1_CNTL, tmp)amdgpu_device_wreg(adev, (0x505), (tmp), 0); |
544 | } |
545 | |
546 | /** |
547 | * gmc_v7_0_set_prt - set PRT VM fault |
548 | * |
549 | * @adev: amdgpu_device pointer |
550 | * @enable: enable/disable VM fault handling for PRT |
551 | */ |
552 | static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool_Bool enable) |
553 | { |
554 | uint32_t tmp; |
555 | |
556 | if (enable && !adev->gmc.prt_warning) { |
557 | dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n")printf("drm:pid%d:%s *WARNING* " "Disabling VM faults because of PRT request!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
558 | adev->gmc.prt_warning = true1; |
559 | } |
560 | |
561 | tmp = RREG32(mmVM_PRT_CNTL)amdgpu_device_rreg(adev, (0x534), 0); |
562 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,(((tmp) & ~0x1) | (0x1 & ((enable) << 0x0))) |
563 | CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable)(((tmp) & ~0x1) | (0x1 & ((enable) << 0x0))); |
564 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,(((tmp) & ~0x10) | (0x10 & ((enable) << 0x4))) |
565 | CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable)(((tmp) & ~0x10) | (0x10 & ((enable) << 0x4))); |
566 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,(((tmp) & ~0x2) | (0x2 & ((enable) << 0x1))) |
567 | TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable)(((tmp) & ~0x2) | (0x2 & ((enable) << 0x1))); |
568 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,(((tmp) & ~0x20) | (0x20 & ((enable) << 0x5))) |
569 | TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable)(((tmp) & ~0x20) | (0x20 & ((enable) << 0x5))); |
570 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,(((tmp) & ~0x4) | (0x4 & ((enable) << 0x2))) |
571 | L2_CACHE_STORE_INVALID_ENTRIES, enable)(((tmp) & ~0x4) | (0x4 & ((enable) << 0x2))); |
572 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,(((tmp) & ~0x8) | (0x8 & ((enable) << 0x3))) |
573 | L1_TLB_STORE_INVALID_ENTRIES, enable)(((tmp) & ~0x8) | (0x8 & ((enable) << 0x3))); |
574 | tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,(((tmp) & ~0x40) | (0x40 & ((enable) << 0x6))) |
575 | MASK_PDE0_FAULT, enable)(((tmp) & ~0x40) | (0x40 & ((enable) << 0x6))); |
576 | WREG32(mmVM_PRT_CNTL, tmp)amdgpu_device_wreg(adev, (0x534), (tmp), 0); |
577 | |
578 | if (enable) { |
579 | uint32_t low = AMDGPU_VA_RESERVED_SIZE(2ULL << 20) >> AMDGPU_GPU_PAGE_SHIFT12; |
580 | uint32_t high = adev->vm_manager.max_pfn - |
581 | (AMDGPU_VA_RESERVED_SIZE(2ULL << 20) >> AMDGPU_GPU_PAGE_SHIFT12); |
582 | |
583 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low)amdgpu_device_wreg(adev, (0x52c), (low), 0); |
584 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low)amdgpu_device_wreg(adev, (0x52d), (low), 0); |
585 | WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low)amdgpu_device_wreg(adev, (0x52e), (low), 0); |
586 | WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low)amdgpu_device_wreg(adev, (0x52f), (low), 0); |
587 | WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high)amdgpu_device_wreg(adev, (0x530), (high), 0); |
588 | WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high)amdgpu_device_wreg(adev, (0x531), (high), 0); |
589 | WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high)amdgpu_device_wreg(adev, (0x532), (high), 0); |
590 | WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high)amdgpu_device_wreg(adev, (0x533), (high), 0); |
591 | } else { |
592 | WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff)amdgpu_device_wreg(adev, (0x52c), (0xfffffff), 0); |
593 | WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff)amdgpu_device_wreg(adev, (0x52d), (0xfffffff), 0); |
594 | WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff)amdgpu_device_wreg(adev, (0x52e), (0xfffffff), 0); |
595 | WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff)amdgpu_device_wreg(adev, (0x52f), (0xfffffff), 0); |
596 | WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0)amdgpu_device_wreg(adev, (0x530), (0x0), 0); |
597 | WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0)amdgpu_device_wreg(adev, (0x531), (0x0), 0); |
598 | WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0)amdgpu_device_wreg(adev, (0x532), (0x0), 0); |
599 | WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0)amdgpu_device_wreg(adev, (0x533), (0x0), 0); |
600 | } |
601 | } |
602 | |
603 | /** |
604 | * gmc_v7_0_gart_enable - gart enable |
605 | * |
606 | * @adev: amdgpu_device pointer |
607 | * |
608 | * This sets up the TLBs, programs the page tables for VMID0, |
609 | * sets up the hw for VMIDs 1-15 which are allocated on |
610 | * demand, and sets up the global locations for the LDS, GDS, |
611 | * and GPUVM for FSA64 clients (CIK). |
612 | * Returns 0 for success, errors for failure. |
613 | */ |
614 | static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) |
615 | { |
616 | uint64_t table_addr; |
617 | u32 tmp, field; |
618 | int i; |
619 | |
620 | if (adev->gart.bo == NULL((void *)0)) { |
621 | dev_err(adev->dev, "No VRAM object for PCIE GART.\n")printf("drm:pid%d:%s *ERROR* " "No VRAM object for PCIE GART.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
622 | return -EINVAL22; |
623 | } |
624 | amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); |
625 | table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); |
626 | |
627 | /* Setup TLB control */ |
628 | tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL)amdgpu_device_rreg(adev, (0x819), 0); |
629 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
630 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1))); |
631 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3)(((tmp) & ~0x18) | (0x18 & ((3) << 0x3))); |
632 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1)(((tmp) & ~0x40) | (0x40 & ((1) << 0x6))); |
633 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0)(((tmp) & ~0x20) | (0x20 & ((0) << 0x5))); |
634 | WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp)amdgpu_device_wreg(adev, (0x819), (tmp), 0); |
635 | /* Setup L2 cache */ |
636 | tmp = RREG32(mmVM_L2_CNTL)amdgpu_device_rreg(adev, (0x500), 0); |
637 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
638 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1))); |
639 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1)(((tmp) & ~0x200) | (0x200 & ((1) << 0x9))); |
640 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1)(((tmp) & ~0x400) | (0x400 & ((1) << 0xa))); |
641 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7)(((tmp) & ~0x38000) | (0x38000 & ((7) << 0xf))); |
642 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1)(((tmp) & ~0x180000) | (0x180000 & ((1) << 0x13 ))); |
643 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1)(((tmp) & ~0x800) | (0x800 & ((1) << 0xb))); |
644 | WREG32(mmVM_L2_CNTL, tmp)amdgpu_device_wreg(adev, (0x500), (tmp), 0); |
645 | tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1)(((0) & ~0x1) | (0x1 & ((1) << 0x0))); |
646 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1))); |
647 | WREG32(mmVM_L2_CNTL2, tmp)amdgpu_device_wreg(adev, (0x501), (tmp), 0); |
648 | |
649 | field = adev->vm_manager.fragment_size; |
650 | tmp = RREG32(mmVM_L2_CNTL3)amdgpu_device_rreg(adev, (0x502), 0); |
651 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1)(((tmp) & ~0x100000) | (0x100000 & ((1) << 0x14 ))); |
652 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field)(((tmp) & ~0x3f) | (0x3f & ((field) << 0x0))); |
653 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field)(((tmp) & ~0xf8000) | (0xf8000 & ((field) << 0xf ))); |
654 | WREG32(mmVM_L2_CNTL3, tmp)amdgpu_device_wreg(adev, (0x502), (tmp), 0); |
655 | /* setup context0 */ |
656 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12)amdgpu_device_wreg(adev, (0x557), (adev->gmc.gart_start >> 12), 0); |
657 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12)amdgpu_device_wreg(adev, (0x55f), (adev->gmc.gart_end >> 12), 0); |
658 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12)amdgpu_device_wreg(adev, (0x54f), (table_addr >> 12), 0 ); |
659 | WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,amdgpu_device_wreg(adev, (0x546), ((u32)(adev->dummy_page_addr >> 12)), 0) |
660 | (u32)(adev->dummy_page_addr >> 12))amdgpu_device_wreg(adev, (0x546), ((u32)(adev->dummy_page_addr >> 12)), 0); |
661 | WREG32(mmVM_CONTEXT0_CNTL2, 0)amdgpu_device_wreg(adev, (0x50c), (0), 0); |
662 | tmp = RREG32(mmVM_CONTEXT0_CNTL)amdgpu_device_rreg(adev, (0x504), 0); |
663 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
664 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0)(((tmp) & ~0x6) | (0x6 & ((0) << 0x1))); |
665 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); |
666 | WREG32(mmVM_CONTEXT0_CNTL, tmp)amdgpu_device_wreg(adev, (0x504), (tmp), 0); |
667 | |
668 | WREG32(0x575, 0)amdgpu_device_wreg(adev, (0x575), (0), 0); |
669 | WREG32(0x576, 0)amdgpu_device_wreg(adev, (0x576), (0), 0); |
670 | WREG32(0x577, 0)amdgpu_device_wreg(adev, (0x577), (0), 0); |
671 | |
672 | /* empty context1-15 */ |
673 | /* FIXME start with 4G, once using 2 level pt switch to full |
674 | * vm size space |
675 | */ |
676 | /* set vm size, must be a multiple of 4 */ |
677 | WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0)amdgpu_device_wreg(adev, (0x558), (0), 0); |
678 | WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1)amdgpu_device_wreg(adev, (0x560), (adev->vm_manager.max_pfn - 1), 0); |
679 | for (i = 1; i < AMDGPU_NUM_VMID16; i++) { |
680 | if (i < 8) |
681 | WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,amdgpu_device_wreg(adev, (0x54f + i), (table_addr >> 12 ), 0) |
682 | table_addr >> 12)amdgpu_device_wreg(adev, (0x54f + i), (table_addr >> 12 ), 0); |
683 | else |
684 | WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,amdgpu_device_wreg(adev, (0x50e + i - 8), (table_addr >> 12), 0) |
685 | table_addr >> 12)amdgpu_device_wreg(adev, (0x50e + i - 8), (table_addr >> 12), 0); |
686 | } |
687 | |
688 | /* enable context1-15 */ |
689 | WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,amdgpu_device_wreg(adev, (0x547), ((u32)(adev->dummy_page_addr >> 12)), 0) |
690 | (u32)(adev->dummy_page_addr >> 12))amdgpu_device_wreg(adev, (0x547), ((u32)(adev->dummy_page_addr >> 12)), 0); |
691 | WREG32(mmVM_CONTEXT1_CNTL2, 4)amdgpu_device_wreg(adev, (0x50d), (4), 0); |
692 | tmp = RREG32(mmVM_CONTEXT1_CNTL)amdgpu_device_rreg(adev, (0x505), 0); |
693 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
694 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1)(((tmp) & ~0x6) | (0x6 & ((1) << 0x1))); |
695 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,(((tmp) & ~0xf000000) | (0xf000000 & ((adev->vm_manager .block_size - 9) << 0x18))) |
696 | adev->vm_manager.block_size - 9)(((tmp) & ~0xf000000) | (0xf000000 & ((adev->vm_manager .block_size - 9) << 0x18))); |
697 | WREG32(mmVM_CONTEXT1_CNTL, tmp)amdgpu_device_wreg(adev, (0x505), (tmp), 0); |
698 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS2) |
699 | gmc_v7_0_set_fault_enable_default(adev, false0); |
700 | else |
701 | gmc_v7_0_set_fault_enable_default(adev, true1); |
702 | |
703 | if (adev->asic_type == CHIP_KAVERI) { |
704 | tmp = RREG32(mmCHUB_CONTROL)amdgpu_device_rreg(adev, (0x619), 0); |
705 | tmp &= ~BYPASS_VM(1 << 0); |
706 | WREG32(mmCHUB_CONTROL, tmp)amdgpu_device_wreg(adev, (0x619), (tmp), 0); |
707 | } |
708 | |
709 | gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0); |
710 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n" , (unsigned)(adev->gmc.gart_size >> 20), (unsigned long long)table_addr) |
711 | (unsigned)(adev->gmc.gart_size >> 20),printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n" , (unsigned)(adev->gmc.gart_size >> 20), (unsigned long long)table_addr) |
712 | (unsigned long long)table_addr)printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n" , (unsigned)(adev->gmc.gart_size >> 20), (unsigned long long)table_addr); |
713 | return 0; |
714 | } |
715 | |
716 | static int gmc_v7_0_gart_init(struct amdgpu_device *adev) |
717 | { |
718 | int r; |
719 | |
720 | if (adev->gart.bo) { |
721 | WARN(1, "R600 PCIE GART already initialized\n")({ int __ret = !!(1); if (__ret) printf("R600 PCIE GART already initialized\n" ); __builtin_expect(!!(__ret), 0); }); |
722 | return 0; |
723 | } |
724 | /* Initialize common gart structure */ |
725 | r = amdgpu_gart_init(adev); |
726 | if (r) |
727 | return r; |
728 | adev->gart.table_size = adev->gart.num_gpu_pages * 8; |
729 | adev->gart.gart_pte_flags = 0; |
730 | return amdgpu_gart_table_vram_alloc(adev); |
731 | } |
732 | |
733 | /** |
734 | * gmc_v7_0_gart_disable - gart disable |
735 | * |
736 | * @adev: amdgpu_device pointer |
737 | * |
738 | * This disables all VM page table (CIK). |
739 | */ |
740 | static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) |
741 | { |
742 | u32 tmp; |
743 | |
744 | /* Disable all tables */ |
745 | WREG32(mmVM_CONTEXT0_CNTL, 0)amdgpu_device_wreg(adev, (0x504), (0), 0); |
746 | WREG32(mmVM_CONTEXT1_CNTL, 0)amdgpu_device_wreg(adev, (0x505), (0), 0); |
747 | /* Setup TLB control */ |
748 | tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL)amdgpu_device_rreg(adev, (0x819), 0); |
749 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0))); |
750 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0)(((tmp) & ~0x2) | (0x2 & ((0) << 0x1))); |
751 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0)(((tmp) & ~0x40) | (0x40 & ((0) << 0x6))); |
752 | WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp)amdgpu_device_wreg(adev, (0x819), (tmp), 0); |
753 | /* Setup L2 cache */ |
754 | tmp = RREG32(mmVM_L2_CNTL)amdgpu_device_rreg(adev, (0x500), 0); |
755 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0))); |
756 | WREG32(mmVM_L2_CNTL, tmp)amdgpu_device_wreg(adev, (0x500), (tmp), 0); |
757 | WREG32(mmVM_L2_CNTL2, 0)amdgpu_device_wreg(adev, (0x501), (0), 0); |
758 | } |
759 | |
760 | /** |
761 | * gmc_v7_0_vm_decode_fault - print human readable fault info |
762 | * |
763 | * @adev: amdgpu_device pointer |
764 | * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value |
765 | * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value |
766 | * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value |
767 | * @pasid: debug logging only - no functional use |
768 | * |
769 | * Print human readable fault information (CIK). |
770 | */ |
771 | static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, |
772 | u32 addr, u32 mc_client, unsigned pasid) |
773 | { |
774 | u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID)(((status) & 0x1e000000) >> 0x19); |
775 | u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,(((status) & 0xff) >> 0x0) |
776 | PROTECTIONS)(((status) & 0xff) >> 0x0); |
777 | char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, |
778 | (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; |
779 | u32 mc_id; |
780 | |
781 | mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,(((status) & 0x1ff000) >> 0xc) |
782 | MEMORY_CLIENT_ID)(((status) & 0x1ff000) >> 0xc); |
783 | |
784 | dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",printf("drm:pid%d:%s *ERROR* " "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , protections , vmid, pasid, addr, (((status) & 0x1000000) >> 0x18 ) ? "write" : "read", block, mc_client, mc_id) |
785 | protections, vmid, pasid, addr,printf("drm:pid%d:%s *ERROR* " "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , protections , vmid, pasid, addr, (((status) & 0x1000000) >> 0x18 ) ? "write" : "read", block, mc_client, mc_id) |
786 | REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,printf("drm:pid%d:%s *ERROR* " "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , protections , vmid, pasid, addr, (((status) & 0x1000000) >> 0x18 ) ? "write" : "read", block, mc_client, mc_id) |
787 | MEMORY_CLIENT_RW) ?printf("drm:pid%d:%s *ERROR* " "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , protections , vmid, pasid, addr, (((status) & 0x1000000) >> 0x18 ) ? "write" : "read", block, mc_client, mc_id) |
788 | "write" : "read", block, mc_client, mc_id)printf("drm:pid%d:%s *ERROR* " "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , protections , vmid, pasid, addr, (((status) & 0x1000000) >> 0x18 ) ? "write" : "read", block, mc_client, mc_id); |
789 | } |
790 | |
791 | |
792 | static const u32 mc_cg_registers[] = { |
793 | mmMC_HUB_MISC_HUB_CG0x82e, |
794 | mmMC_HUB_MISC_SIP_CG0x830, |
795 | mmMC_HUB_MISC_VM_CG0x82f, |
796 | mmMC_XPB_CLK_GAT0x91e, |
797 | mmATC_MISC_CG0xcd4, |
798 | mmMC_CITF_MISC_WR_CG0x993, |
799 | mmMC_CITF_MISC_RD_CG0x992, |
800 | mmMC_CITF_MISC_VM_CG0x994, |
801 | mmVM_L2_CG0x570, |
802 | }; |
803 | |
804 | static const u32 mc_cg_ls_en[] = { |
805 | MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK0x80000, |
806 | MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK0x80000, |
807 | MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK0x80000, |
808 | MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK0x80000, |
809 | ATC_MISC_CG__MEM_LS_ENABLE_MASK0x80000, |
810 | MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK0x80000, |
811 | MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK0x80000, |
812 | MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK0x80000, |
813 | VM_L2_CG__MEM_LS_ENABLE_MASK0x80000, |
814 | }; |
815 | |
816 | static const u32 mc_cg_en[] = { |
817 | MC_HUB_MISC_HUB_CG__ENABLE_MASK0x40000, |
818 | MC_HUB_MISC_SIP_CG__ENABLE_MASK0x40000, |
819 | MC_HUB_MISC_VM_CG__ENABLE_MASK0x40000, |
820 | MC_XPB_CLK_GAT__ENABLE_MASK0x40000, |
821 | ATC_MISC_CG__ENABLE_MASK0x40000, |
822 | MC_CITF_MISC_WR_CG__ENABLE_MASK0x40000, |
823 | MC_CITF_MISC_RD_CG__ENABLE_MASK0x40000, |
824 | MC_CITF_MISC_VM_CG__ENABLE_MASK0x40000, |
825 | VM_L2_CG__ENABLE_MASK0x40000, |
826 | }; |
827 | |
828 | static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, |
829 | bool_Bool enable) |
830 | { |
831 | int i; |
832 | u32 orig, data; |
833 | |
834 | for (i = 0; i < ARRAY_SIZE(mc_cg_registers)(sizeof((mc_cg_registers)) / sizeof((mc_cg_registers)[0])); i++) { |
835 | orig = data = RREG32(mc_cg_registers[i])amdgpu_device_rreg(adev, (mc_cg_registers[i]), 0); |
836 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS(1ULL << 8))) |
837 | data |= mc_cg_ls_en[i]; |
838 | else |
839 | data &= ~mc_cg_ls_en[i]; |
840 | if (data != orig) |
841 | WREG32(mc_cg_registers[i], data)amdgpu_device_wreg(adev, (mc_cg_registers[i]), (data), 0); |
842 | } |
843 | } |
844 | |
845 | static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, |
846 | bool_Bool enable) |
847 | { |
848 | int i; |
849 | u32 orig, data; |
850 | |
851 | for (i = 0; i < ARRAY_SIZE(mc_cg_registers)(sizeof((mc_cg_registers)) / sizeof((mc_cg_registers)[0])); i++) { |
852 | orig = data = RREG32(mc_cg_registers[i])amdgpu_device_rreg(adev, (mc_cg_registers[i]), 0); |
853 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG(1ULL << 9))) |
854 | data |= mc_cg_en[i]; |
855 | else |
856 | data &= ~mc_cg_en[i]; |
857 | if (data != orig) |
858 | WREG32(mc_cg_registers[i], data)amdgpu_device_wreg(adev, (mc_cg_registers[i]), (data), 0); |
859 | } |
860 | } |
861 | |
862 | static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, |
863 | bool_Bool enable) |
864 | { |
865 | u32 orig, data; |
866 | |
867 | orig = data = RREG32_PCIE(ixPCIE_CNTL2)adev->pcie_rreg(adev, (0x140001c)); |
868 | |
869 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS(1ULL << 12))) { |
870 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1)(((data) & ~0x10000) | (0x10000 & ((1) << 0x10) )); |
871 | data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1)(((data) & ~0x40000) | (0x40000 & ((1) << 0x12) )); |
872 | data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1)(((data) & ~0x80000) | (0x80000 & ((1) << 0x13) )); |
873 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1)(((data) & ~0x20000) | (0x20000 & ((1) << 0x11) )); |
874 | } else { |
875 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0)(((data) & ~0x10000) | (0x10000 & ((0) << 0x10) )); |
876 | data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0)(((data) & ~0x40000) | (0x40000 & ((0) << 0x12) )); |
877 | data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0)(((data) & ~0x80000) | (0x80000 & ((0) << 0x13) )); |
878 | data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0)(((data) & ~0x20000) | (0x20000 & ((0) << 0x11) )); |
879 | } |
880 | |
881 | if (orig != data) |
882 | WREG32_PCIE(ixPCIE_CNTL2, data)adev->pcie_wreg(adev, (0x140001c), (data)); |
883 | } |
884 | |
885 | static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, |
886 | bool_Bool enable) |
887 | { |
888 | u32 orig, data; |
889 | |
890 | orig = data = RREG32(mmHDP_HOST_PATH_CNTL)amdgpu_device_rreg(adev, (0xb00), 0); |
891 | |
892 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG(1ULL << 16))) |
893 | data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0)(((data) & ~0x800000) | (0x800000 & ((0) << 0x17 ))); |
894 | else |
895 | data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1)(((data) & ~0x800000) | (0x800000 & ((1) << 0x17 ))); |
896 | |
897 | if (orig != data) |
898 | WREG32(mmHDP_HOST_PATH_CNTL, data)amdgpu_device_wreg(adev, (0xb00), (data), 0); |
899 | } |
900 | |
901 | static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, |
902 | bool_Bool enable) |
903 | { |
904 | u32 orig, data; |
905 | |
906 | orig = data = RREG32(mmHDP_MEM_POWER_LS)amdgpu_device_rreg(adev, (0xbd4), 0); |
907 | |
908 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS(1ULL << 15))) |
909 | data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1)(((data) & ~0x1) | (0x1 & ((1) << 0x0))); |
910 | else |
911 | data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0)(((data) & ~0x1) | (0x1 & ((0) << 0x0))); |
912 | |
913 | if (orig != data) |
914 | WREG32(mmHDP_MEM_POWER_LS, data)amdgpu_device_wreg(adev, (0xbd4), (data), 0); |
915 | } |
916 | |
917 | static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) |
918 | { |
919 | switch (mc_seq_vram_type) { |
920 | case MC_SEQ_MISC0__MT__GDDR10x10000000: |
921 | return AMDGPU_VRAM_TYPE_GDDR11; |
922 | case MC_SEQ_MISC0__MT__DDR20x20000000: |
923 | return AMDGPU_VRAM_TYPE_DDR22; |
924 | case MC_SEQ_MISC0__MT__GDDR30x30000000: |
925 | return AMDGPU_VRAM_TYPE_GDDR33; |
926 | case MC_SEQ_MISC0__MT__GDDR40x40000000: |
927 | return AMDGPU_VRAM_TYPE_GDDR44; |
928 | case MC_SEQ_MISC0__MT__GDDR50x50000000: |
929 | return AMDGPU_VRAM_TYPE_GDDR55; |
930 | case MC_SEQ_MISC0__MT__HBM0x60000000: |
931 | return AMDGPU_VRAM_TYPE_HBM6; |
932 | case MC_SEQ_MISC0__MT__DDR30xB0000000: |
933 | return AMDGPU_VRAM_TYPE_DDR37; |
934 | default: |
935 | return AMDGPU_VRAM_TYPE_UNKNOWN0; |
936 | } |
937 | } |
938 | |
939 | static int gmc_v7_0_early_init(void *handle) |
940 | { |
941 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
942 | |
943 | gmc_v7_0_set_gmc_funcs(adev); |
944 | gmc_v7_0_set_irq_funcs(adev); |
945 | |
946 | adev->gmc.shared_aperture_start = 0x2000000000000000ULL; |
947 | adev->gmc.shared_aperture_end = |
948 | adev->gmc.shared_aperture_start + (4ULL << 30) - 1; |
949 | adev->gmc.private_aperture_start = |
950 | adev->gmc.shared_aperture_end + 1; |
951 | adev->gmc.private_aperture_end = |
952 | adev->gmc.private_aperture_start + (4ULL << 30) - 1; |
953 | |
954 | return 0; |
955 | } |
956 | |
957 | static int gmc_v7_0_late_init(void *handle) |
958 | { |
959 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
960 | |
961 | if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS2) |
962 | return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); |
963 | else |
964 | return 0; |
965 | } |
966 | |
967 | static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) |
968 | { |
969 | u32 d1vga_control = RREG32(mmD1VGA_CONTROL)amdgpu_device_rreg(adev, (0xcc), 0); |
970 | unsigned size; |
971 | |
972 | if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)(((d1vga_control) & 0x1) >> 0x0)) { |
973 | size = AMDGPU_VBIOS_VGA_ALLOCATION(9 * 1024 * 1024); |
974 | } else { |
975 | u32 viewport = RREG32(mmVIEWPORT_SIZE)amdgpu_device_rreg(adev, (0x1b5d), 0); |
976 | size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT)(((viewport) & 0x3fff) >> 0x0) * |
977 | REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH)(((viewport) & 0x3fff0000) >> 0x10) * |
978 | 4); |
979 | } |
980 | |
981 | return size; |
982 | } |
983 | |
984 | static int gmc_v7_0_sw_init(void *handle) |
985 | { |
986 | int r; |
987 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
988 | |
989 | adev->num_vmhubs = 1; |
990 | |
991 | if (adev->flags & AMD_IS_APU) { |
992 | adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN0; |
993 | } else { |
994 | u32 tmp = RREG32(mmMC_SEQ_MISC0)amdgpu_device_rreg(adev, (0xa80), 0); |
995 | tmp &= MC_SEQ_MISC0__MT__MASK0xf0000000; |
996 | adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); |
997 | } |
998 | |
999 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT0x00000092, &adev->gmc.vm_fault); |
1000 | if (r) |
1001 | return r; |
1002 | |
1003 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT0x00000093, &adev->gmc.vm_fault); |
1004 | if (r) |
1005 | return r; |
1006 | |
1007 | /* Adjust VM size here. |
1008 | * Currently set to 4GB ((1 << 20) 4k pages). |
1009 | * Max GPUVM size for cayman and SI is 40 bits. |
1010 | */ |
1011 | amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); |
1012 | |
1013 | /* Set the internal MC address mask |
1014 | * This is the max address of the GPU's |
1015 | * internal address space. |
1016 | */ |
1017 | adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ |
1018 | |
1019 | r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)(((40) == 64) ? ~0ULL : (1ULL<<(40)) -1)); |
1020 | if (r) { |
1021 | pr_warn("No suitable DMA available\n")printk("\0014" "amdgpu: " "No suitable DMA available\n"); |
1022 | return r; |
1023 | } |
1024 | adev->need_swiotlb = drm_need_swiotlb(40); |
1025 | |
1026 | r = gmc_v7_0_init_microcode(adev); |
1027 | if (r) { |
1028 | DRM_ERROR("Failed to load mc firmware!\n")__drm_err("Failed to load mc firmware!\n"); |
1029 | return r; |
1030 | } |
1031 | |
1032 | r = gmc_v7_0_mc_init(adev); |
1033 | if (r) |
1034 | return r; |
1035 | |
1036 | amdgpu_gmc_get_vbios_allocations(adev); |
1037 | |
1038 | /* Memory manager */ |
1039 | r = amdgpu_bo_init(adev); |
1040 | if (r) |
1041 | return r; |
1042 | |
1043 | r = gmc_v7_0_gart_init(adev); |
1044 | if (r) |
1045 | return r; |
1046 | |
1047 | /* |
1048 | * number of VMs |
1049 | * VMID 0 is reserved for System |
1050 | * amdgpu graphics/compute will use VMIDs 1-7 |
1051 | * amdkfd will use VMIDs 8-15 |
1052 | */ |
1053 | adev->vm_manager.first_kfd_vmid = 8; |
1054 | amdgpu_vm_manager_init(adev); |
1055 | |
1056 | /* base offset of vram pages */ |
1057 | if (adev->flags & AMD_IS_APU) { |
1058 | u64 tmp = RREG32(mmMC_VM_FB_OFFSET)amdgpu_device_rreg(adev, (0x81a), 0); |
1059 | |
1060 | tmp <<= 22; |
1061 | adev->vm_manager.vram_base_offset = tmp; |
1062 | } else { |
1063 | adev->vm_manager.vram_base_offset = 0; |
1064 | } |
1065 | |
1066 | adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), |
1067 | GFP_KERNEL(0x0001 | 0x0004)); |
1068 | if (!adev->gmc.vm_fault_info) |
1069 | return -ENOMEM12; |
1070 | atomic_set(&adev->gmc.vm_fault_info_updated, 0)({ typeof(*(&adev->gmc.vm_fault_info_updated)) __tmp = ((0)); *(volatile typeof(*(&adev->gmc.vm_fault_info_updated )) *)&(*(&adev->gmc.vm_fault_info_updated)) = __tmp ; __tmp; }); |
1071 | |
1072 | return 0; |
1073 | } |
1074 | |
1075 | static int gmc_v7_0_sw_fini(void *handle) |
1076 | { |
1077 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1078 | |
1079 | amdgpu_gem_force_release(adev); |
1080 | amdgpu_vm_manager_fini(adev); |
1081 | kfree(adev->gmc.vm_fault_info); |
1082 | amdgpu_gart_table_vram_free(adev); |
1083 | amdgpu_bo_fini(adev); |
1084 | release_firmware(adev->gmc.fw); |
1085 | adev->gmc.fw = NULL((void *)0); |
1086 | |
1087 | return 0; |
1088 | } |
1089 | |
1090 | static int gmc_v7_0_hw_init(void *handle) |
1091 | { |
1092 | int r; |
1093 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1094 | |
1095 | gmc_v7_0_init_golden_registers(adev); |
1096 | |
1097 | gmc_v7_0_mc_program(adev); |
1098 | |
1099 | if (!(adev->flags & AMD_IS_APU)) { |
1100 | r = gmc_v7_0_mc_load_microcode(adev); |
1101 | if (r) { |
1102 | DRM_ERROR("Failed to load MC firmware!\n")__drm_err("Failed to load MC firmware!\n"); |
1103 | return r; |
1104 | } |
1105 | } |
1106 | |
1107 | r = gmc_v7_0_gart_enable(adev); |
1108 | if (r) |
1109 | return r; |
1110 | |
1111 | if (amdgpu_emu_mode == 1) |
1112 | return amdgpu_gmc_vram_checking(adev); |
1113 | else |
1114 | return r; |
1115 | } |
1116 | |
1117 | static int gmc_v7_0_hw_fini(void *handle) |
1118 | { |
1119 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1120 | |
1121 | amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); |
1122 | gmc_v7_0_gart_disable(adev); |
1123 | |
1124 | return 0; |
1125 | } |
1126 | |
1127 | static int gmc_v7_0_suspend(void *handle) |
1128 | { |
1129 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1130 | |
1131 | gmc_v7_0_hw_fini(adev); |
1132 | |
1133 | return 0; |
1134 | } |
1135 | |
1136 | static int gmc_v7_0_resume(void *handle) |
1137 | { |
1138 | int r; |
1139 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1140 | |
1141 | r = gmc_v7_0_hw_init(adev); |
1142 | if (r) |
1143 | return r; |
1144 | |
1145 | amdgpu_vmid_reset_all(adev); |
1146 | |
1147 | return 0; |
1148 | } |
1149 | |
1150 | static bool_Bool gmc_v7_0_is_idle(void *handle) |
1151 | { |
1152 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1153 | u32 tmp = RREG32(mmSRBM_STATUS)amdgpu_device_rreg(adev, (0x394), 0); |
1154 | |
1155 | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK0x200 | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK0x400 | |
1156 | SRBM_STATUS__MCC_BUSY_MASK0x800 | SRBM_STATUS__MCD_BUSY_MASK0x1000 | SRBM_STATUS__VMC_BUSY_MASK0x100)) |
1157 | return false0; |
1158 | |
1159 | return true1; |
1160 | } |
1161 | |
1162 | static int gmc_v7_0_wait_for_idle(void *handle) |
1163 | { |
1164 | unsigned i; |
1165 | u32 tmp; |
1166 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1167 | |
1168 | for (i = 0; i < adev->usec_timeout; i++) { |
1169 | /* read MC_STATUS */ |
1170 | tmp = RREG32(mmSRBM_STATUS)amdgpu_device_rreg(adev, (0x394), 0) & (SRBM_STATUS__MCB_BUSY_MASK0x200 | |
1171 | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK0x400 | |
1172 | SRBM_STATUS__MCC_BUSY_MASK0x800 | |
1173 | SRBM_STATUS__MCD_BUSY_MASK0x1000 | |
1174 | SRBM_STATUS__VMC_BUSY_MASK0x100); |
1175 | if (!tmp) |
1176 | return 0; |
1177 | udelay(1); |
1178 | } |
1179 | return -ETIMEDOUT60; |
1180 | |
1181 | } |
1182 | |
1183 | static int gmc_v7_0_soft_reset(void *handle) |
1184 | { |
1185 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1186 | u32 srbm_soft_reset = 0; |
1187 | u32 tmp = RREG32(mmSRBM_STATUS)amdgpu_device_rreg(adev, (0x394), 0); |
1188 | |
1189 | if (tmp & SRBM_STATUS__VMC_BUSY_MASK0x100) |
1190 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,(((srbm_soft_reset) & ~0x20000) | (0x20000 & ((1) << 0x11))) |
1191 | SRBM_SOFT_RESET, SOFT_RESET_VMC, 1)(((srbm_soft_reset) & ~0x20000) | (0x20000 & ((1) << 0x11))); |
1192 | |
1193 | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK0x200 | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK0x400 | |
1194 | SRBM_STATUS__MCC_BUSY_MASK0x800 | SRBM_STATUS__MCD_BUSY_MASK0x1000)) { |
1195 | if (!(adev->flags & AMD_IS_APU)) |
1196 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,(((srbm_soft_reset) & ~0x800) | (0x800 & ((1) << 0xb))) |
1197 | SRBM_SOFT_RESET, SOFT_RESET_MC, 1)(((srbm_soft_reset) & ~0x800) | (0x800 & ((1) << 0xb))); |
1198 | } |
1199 | |
1200 | if (srbm_soft_reset) { |
1201 | gmc_v7_0_mc_stop(adev); |
1202 | if (gmc_v7_0_wait_for_idle((void *)adev)) { |
1203 | dev_warn(adev->dev, "Wait for GMC idle timed out !\n")printf("drm:pid%d:%s *WARNING* " "Wait for GMC idle timed out !\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1204 | } |
1205 | |
1206 | |
1207 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
1208 | tmp |= srbm_soft_reset; |
1209 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0); |
1210 | WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0); |
1211 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
1212 | |
1213 | udelay(50); |
1214 | |
1215 | tmp &= ~srbm_soft_reset; |
1216 | WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0); |
1217 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
Value stored to 'tmp' is never read | |
1218 | |
1219 | /* Wait a little for things to settle down */ |
1220 | udelay(50); |
1221 | |
1222 | gmc_v7_0_mc_resume(adev); |
1223 | udelay(50); |
1224 | } |
1225 | |
1226 | return 0; |
1227 | } |
1228 | |
1229 | static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, |
1230 | struct amdgpu_irq_src *src, |
1231 | unsigned type, |
1232 | enum amdgpu_interrupt_state state) |
1233 | { |
1234 | u32 tmp; |
1235 | u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK0x8 | |
1236 | VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK0x40 | |
1237 | VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK0x200 | |
1238 | VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK0x1000 | |
1239 | VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK0x8000 | |
1240 | VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK0x40000); |
1241 | |
1242 | switch (state) { |
1243 | case AMDGPU_IRQ_STATE_DISABLE: |
1244 | /* system context */ |
1245 | tmp = RREG32(mmVM_CONTEXT0_CNTL)amdgpu_device_rreg(adev, (0x504), 0); |
1246 | tmp &= ~bits; |
1247 | WREG32(mmVM_CONTEXT0_CNTL, tmp)amdgpu_device_wreg(adev, (0x504), (tmp), 0); |
1248 | /* VMs */ |
1249 | tmp = RREG32(mmVM_CONTEXT1_CNTL)amdgpu_device_rreg(adev, (0x505), 0); |
1250 | tmp &= ~bits; |
1251 | WREG32(mmVM_CONTEXT1_CNTL, tmp)amdgpu_device_wreg(adev, (0x505), (tmp), 0); |
1252 | break; |
1253 | case AMDGPU_IRQ_STATE_ENABLE: |
1254 | /* system context */ |
1255 | tmp = RREG32(mmVM_CONTEXT0_CNTL)amdgpu_device_rreg(adev, (0x504), 0); |
1256 | tmp |= bits; |
1257 | WREG32(mmVM_CONTEXT0_CNTL, tmp)amdgpu_device_wreg(adev, (0x504), (tmp), 0); |
1258 | /* VMs */ |
1259 | tmp = RREG32(mmVM_CONTEXT1_CNTL)amdgpu_device_rreg(adev, (0x505), 0); |
1260 | tmp |= bits; |
1261 | WREG32(mmVM_CONTEXT1_CNTL, tmp)amdgpu_device_wreg(adev, (0x505), (tmp), 0); |
1262 | break; |
1263 | default: |
1264 | break; |
1265 | } |
1266 | |
1267 | return 0; |
1268 | } |
1269 | |
1270 | static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, |
1271 | struct amdgpu_irq_src *source, |
1272 | struct amdgpu_iv_entry *entry) |
1273 | { |
1274 | u32 addr, status, mc_client, vmid; |
1275 | |
1276 | addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)amdgpu_device_rreg(adev, (0x53f), 0); |
1277 | status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)amdgpu_device_rreg(adev, (0x537), 0); |
1278 | mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT)amdgpu_device_rreg(adev, (0x539), 0); |
1279 | /* reset addr and status */ |
1280 | WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x50d), 0); tmp_ &= (~1); tmp_ |= ((1) & ~(~1)); amdgpu_device_wreg(adev , (0x50d), (tmp_), 0); } while (0); |
1281 | |
1282 | if (!addr && !status) |
1283 | return 0; |
1284 | |
1285 | if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST1) |
1286 | gmc_v7_0_set_fault_enable_default(adev, false0); |
1287 | |
1288 | if (printk_ratelimit()1) { |
1289 | dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",printf("drm:pid%d:%s *ERROR* " "GPU fault detected: %d 0x%08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , entry-> src_id, entry->src_data[0]) |
1290 | entry->src_id, entry->src_data[0])printf("drm:pid%d:%s *ERROR* " "GPU fault detected: %d 0x%08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , entry-> src_id, entry->src_data[0]); |
1291 | dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",printf("drm:pid%d:%s *ERROR* " " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , addr) |
1292 | addr)printf("drm:pid%d:%s *ERROR* " " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , addr); |
1293 | dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",printf("drm:pid%d:%s *ERROR* " " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , status ) |
1294 | status)printf("drm:pid%d:%s *ERROR* " " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , status ); |
1295 | gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, |
1296 | entry->pasid); |
1297 | } |
1298 | |
1299 | vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,(((status) & 0x1e000000) >> 0x19) |
1300 | VMID)(((status) & 0x1e000000) >> 0x19); |
1301 | if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) |
1302 | && !atomic_read(&adev->gmc.vm_fault_info_updated)({ typeof(*(&adev->gmc.vm_fault_info_updated)) __tmp = *(volatile typeof(*(&adev->gmc.vm_fault_info_updated) ) *)&(*(&adev->gmc.vm_fault_info_updated)); membar_datadep_consumer (); __tmp; })) { |
1303 | struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; |
1304 | u32 protections = REG_GET_FIELD(status,(((status) & 0xff) >> 0x0) |
1305 | VM_CONTEXT1_PROTECTION_FAULT_STATUS,(((status) & 0xff) >> 0x0) |
1306 | PROTECTIONS)(((status) & 0xff) >> 0x0); |
1307 | |
1308 | info->vmid = vmid; |
1309 | info->mc_id = REG_GET_FIELD(status,(((status) & 0x1ff000) >> 0xc) |
1310 | VM_CONTEXT1_PROTECTION_FAULT_STATUS,(((status) & 0x1ff000) >> 0xc) |
1311 | MEMORY_CLIENT_ID)(((status) & 0x1ff000) >> 0xc); |
1312 | info->status = status; |
1313 | info->page_addr = addr; |
1314 | info->prot_valid = protections & 0x7 ? true1 : false0; |
1315 | info->prot_read = protections & 0x8 ? true1 : false0; |
1316 | info->prot_write = protections & 0x10 ? true1 : false0; |
1317 | info->prot_exec = protections & 0x20 ? true1 : false0; |
1318 | mb()do { __asm volatile("mfence" ::: "memory"); } while (0); |
1319 | atomic_set(&adev->gmc.vm_fault_info_updated, 1)({ typeof(*(&adev->gmc.vm_fault_info_updated)) __tmp = ((1)); *(volatile typeof(*(&adev->gmc.vm_fault_info_updated )) *)&(*(&adev->gmc.vm_fault_info_updated)) = __tmp ; __tmp; }); |
1320 | } |
1321 | |
1322 | return 0; |
1323 | } |
1324 | |
1325 | static int gmc_v7_0_set_clockgating_state(void *handle, |
1326 | enum amd_clockgating_state state) |
1327 | { |
1328 | bool_Bool gate = false0; |
1329 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1330 | |
1331 | if (state == AMD_CG_STATE_GATE) |
1332 | gate = true1; |
1333 | |
1334 | if (!(adev->flags & AMD_IS_APU)) { |
1335 | gmc_v7_0_enable_mc_mgcg(adev, gate); |
1336 | gmc_v7_0_enable_mc_ls(adev, gate); |
1337 | } |
1338 | gmc_v7_0_enable_bif_mgls(adev, gate); |
1339 | gmc_v7_0_enable_hdp_mgcg(adev, gate); |
1340 | gmc_v7_0_enable_hdp_ls(adev, gate); |
1341 | |
1342 | return 0; |
1343 | } |
1344 | |
1345 | static int gmc_v7_0_set_powergating_state(void *handle, |
1346 | enum amd_powergating_state state) |
1347 | { |
1348 | return 0; |
1349 | } |
1350 | |
1351 | static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { |
1352 | .name = "gmc_v7_0", |
1353 | .early_init = gmc_v7_0_early_init, |
1354 | .late_init = gmc_v7_0_late_init, |
1355 | .sw_init = gmc_v7_0_sw_init, |
1356 | .sw_fini = gmc_v7_0_sw_fini, |
1357 | .hw_init = gmc_v7_0_hw_init, |
1358 | .hw_fini = gmc_v7_0_hw_fini, |
1359 | .suspend = gmc_v7_0_suspend, |
1360 | .resume = gmc_v7_0_resume, |
1361 | .is_idle = gmc_v7_0_is_idle, |
1362 | .wait_for_idle = gmc_v7_0_wait_for_idle, |
1363 | .soft_reset = gmc_v7_0_soft_reset, |
1364 | .set_clockgating_state = gmc_v7_0_set_clockgating_state, |
1365 | .set_powergating_state = gmc_v7_0_set_powergating_state, |
1366 | }; |
1367 | |
1368 | static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { |
1369 | .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, |
1370 | .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid, |
1371 | .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, |
1372 | .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, |
1373 | .set_prt = gmc_v7_0_set_prt, |
1374 | .get_vm_pde = gmc_v7_0_get_vm_pde, |
1375 | .get_vm_pte = gmc_v7_0_get_vm_pte, |
1376 | .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size, |
1377 | }; |
1378 | |
1379 | static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { |
1380 | .set = gmc_v7_0_vm_fault_interrupt_state, |
1381 | .process = gmc_v7_0_process_interrupt, |
1382 | }; |
1383 | |
1384 | static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) |
1385 | { |
1386 | adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; |
1387 | } |
1388 | |
1389 | static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) |
1390 | { |
1391 | adev->gmc.vm_fault.num_types = 1; |
1392 | adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; |
1393 | } |
1394 | |
1395 | const struct amdgpu_ip_block_version gmc_v7_0_ip_block = |
1396 | { |
1397 | .type = AMD_IP_BLOCK_TYPE_GMC, |
1398 | .major = 7, |
1399 | .minor = 0, |
1400 | .rev = 0, |
1401 | .funcs = &gmc_v7_0_ip_funcs, |
1402 | }; |
1403 | |
1404 | const struct amdgpu_ip_block_version gmc_v7_4_ip_block = |
1405 | { |
1406 | .type = AMD_IP_BLOCK_TYPE_GMC, |
1407 | .major = 7, |
1408 | .minor = 4, |
1409 | .rev = 0, |
1410 | .funcs = &gmc_v7_0_ip_funcs, |
1411 | }; |