Bug Summary

File:dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
Warning:line 115, column 2
Value stored to 'temp' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name dce110_mem_input_v.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c
1/*
2 * Copyright 2012-16 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "dm_services.h"
26
27#include "dce/dce_11_0_d.h"
28#include "dce/dce_11_0_sh_mask.h"
29/* TODO: this needs to be looked at, used by Stella's workaround*/
30#include "gmc/gmc_8_2_d.h"
31#include "gmc/gmc_8_2_sh_mask.h"
32
33#include "include/logger_interface.h"
34#include "inc/dce_calcs.h"
35
36#include "dce/dce_mem_input.h"
37#include "dce110_mem_input_v.h"
38
39static void set_flip_control(
40 struct dce_mem_input *mem_input110,
41 bool_Bool immediate)
42{
43 uint32_t value = 0;
44
45 value = dm_read_reg(dm_read_reg_func(mem_input110->base.ctx, 0x462f, __func__)
46 mem_input110->base.ctx,dm_read_reg_func(mem_input110->base.ctx, 0x462f, __func__)
47 mmUNP_FLIP_CONTROL)dm_read_reg_func(mem_input110->base.ctx, 0x462f, __func__);
48
49 set_reg_field_value(value, 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
50 UNP_FLIP_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
51 GRPH_SURFACE_UPDATE_PENDING_MODE)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0);
52
53 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x462f, value, __func__
)
54 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x462f, value, __func__
)
55 mmUNP_FLIP_CONTROL,dm_write_reg_func(mem_input110->base.ctx, 0x462f, value, __func__
)
56 value)dm_write_reg_func(mem_input110->base.ctx, 0x462f, value, __func__
);
57}
58
59/* chroma part */
60static void program_pri_addr_c(
61 struct dce_mem_input *mem_input110,
62 PHYSICAL_ADDRESS_LOCunion large_integer address)
63{
64 uint32_t value = 0;
65 uint32_t temp = 0;
66 /*high register MUST be programmed first*/
67 temp = address.high_part &
68UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK0xff;
69
70 set_reg_field_value(value, temp,(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0)
71 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0)
72 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C)(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0);
73
74 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4609, value, __func__
)
75 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4609, value, __func__
)
76 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,dm_write_reg_func(mem_input110->base.ctx, 0x4609, value, __func__
)
77 value)dm_write_reg_func(mem_input110->base.ctx, 0x4609, value, __func__
);
78
79 temp = 0;
80 value = 0;
81 temp = address.low_part >>
82 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT0x8;
83
84 set_reg_field_value(value, temp,(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00
, 0x8)
85 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00
, 0x8)
86 GRPH_PRIMARY_SURFACE_ADDRESS_C)(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00
, 0x8);
87
88 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4607, value, __func__
)
89 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4607, value, __func__
)
90 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,dm_write_reg_func(mem_input110->base.ctx, 0x4607, value, __func__
)
91 value)dm_write_reg_func(mem_input110->base.ctx, 0x4607, value, __func__
);
92}
93
94/* luma part */
95static void program_pri_addr_l(
96 struct dce_mem_input *mem_input110,
97 PHYSICAL_ADDRESS_LOCunion large_integer address)
98{
99 uint32_t value = 0;
100 uint32_t temp = 0;
101
102 /*high register MUST be programmed first*/
103 temp = address.high_part &
104UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK0xff;
105
106 set_reg_field_value(value, temp,(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0)
107 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0)
108 GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L)(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0);
109
110 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4608, value, __func__
)
111 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4608, value, __func__
)
112 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,dm_write_reg_func(mem_input110->base.ctx, 0x4608, value, __func__
)
113 value)dm_write_reg_func(mem_input110->base.ctx, 0x4608, value, __func__
);
114
115 temp = 0;
Value stored to 'temp' is never read
116 value = 0;
117 temp = address.low_part >>
118 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT0x8;
119
120 set_reg_field_value(value, temp,(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00
, 0x8)
121 UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00
, 0x8)
122 GRPH_PRIMARY_SURFACE_ADDRESS_L)(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00
, 0x8);
123
124 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4606, value, __func__
)
125 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4606, value, __func__
)
126 mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,dm_write_reg_func(mem_input110->base.ctx, 0x4606, value, __func__
)
127 value)dm_write_reg_func(mem_input110->base.ctx, 0x4606, value, __func__
);
128}
129
130static void program_addr(
131 struct dce_mem_input *mem_input110,
132 const struct dc_plane_address *addr)
133{
134 switch (addr->type) {
135 case PLN_ADDR_TYPE_GRAPHICS:
136 program_pri_addr_l(
137 mem_input110,
138 addr->grph.addr);
139 break;
140 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
141 program_pri_addr_c(
142 mem_input110,
143 addr->video_progressive.chroma_addr);
144 program_pri_addr_l(
145 mem_input110,
146 addr->video_progressive.luma_addr);
147 break;
148 default:
149 /* not supported */
150 BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 150); do {} while (0); } while (0);
151 }
152}
153
154static void enable(struct dce_mem_input *mem_input110)
155{
156 uint32_t value = 0;
157
158 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE)dm_read_reg_func(mem_input110->base.ctx, 0x4600, __func__);
159 set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0);
160 dm_write_reg(mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4600, value, __func__
)
161 mmUNP_GRPH_ENABLE,dm_write_reg_func(mem_input110->base.ctx, 0x4600, value, __func__
)
162 value)dm_write_reg_func(mem_input110->base.ctx, 0x4600, value, __func__
);
163}
164
165static void program_tiling(
166 struct dce_mem_input *mem_input110,
167 const union dc_tiling_info *info,
168 const enum surface_pixel_format pixel_format)
169{
170 uint32_t value = 0;
171
172 set_reg_field_value(value, info->gfx8.num_banks,(value) = set_reg_field_value_ex( (value), (info->gfx8.num_banks
), 0xc, 0x2)
173 UNP_GRPH_CONTROL, GRPH_NUM_BANKS)(value) = set_reg_field_value_ex( (value), (info->gfx8.num_banks
), 0xc, 0x2);
174
175 set_reg_field_value(value, info->gfx8.bank_width,(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_width
), 0xc0, 0x6)
176 UNP_GRPH_CONTROL, GRPH_BANK_WIDTH_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_width
), 0xc0, 0x6);
177
178 set_reg_field_value(value, info->gfx8.bank_height,(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_height
), 0x1800, 0xb)
179 UNP_GRPH_CONTROL, GRPH_BANK_HEIGHT_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_height
), 0x1800, 0xb);
180
181 set_reg_field_value(value, info->gfx8.tile_aspect,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_aspect
), 0xc0000, 0x12)
182 UNP_GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_aspect
), 0xc0000, 0x12);
183
184 set_reg_field_value(value, info->gfx8.tile_split,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_split
), 0xe000, 0xd)
185 UNP_GRPH_CONTROL, GRPH_TILE_SPLIT_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_split
), 0xe000, 0xd);
186
187 set_reg_field_value(value, info->gfx8.tile_mode,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_mode
), 0x60000000, 0x1d)
188 UNP_GRPH_CONTROL, GRPH_MICRO_TILE_MODE_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_mode
), 0x60000000, 0x1d);
189
190 set_reg_field_value(value, info->gfx8.pipe_config,(value) = set_reg_field_value_ex( (value), (info->gfx8.pipe_config
), 0x1f000000, 0x18)
191 UNP_GRPH_CONTROL, GRPH_PIPE_CONFIG)(value) = set_reg_field_value_ex( (value), (info->gfx8.pipe_config
), 0x1f000000, 0x18);
192
193 set_reg_field_value(value, info->gfx8.array_mode,(value) = set_reg_field_value_ex( (value), (info->gfx8.array_mode
), 0xf00000, 0x14)
194 UNP_GRPH_CONTROL, GRPH_ARRAY_MODE)(value) = set_reg_field_value_ex( (value), (info->gfx8.array_mode
), 0xf00000, 0x14);
195
196 set_reg_field_value(value, 1,(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f
)
197 UNP_GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE)(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f
);
198
199 set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x30, 0x4)
200 UNP_GRPH_CONTROL, GRPH_Z)(value) = set_reg_field_value_ex( (value), (0), 0x30, 0x4);
201
202 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__
)
203 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__
)
204 mmUNP_GRPH_CONTROL,dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__
)
205 value)dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__
);
206
207 value = 0;
208
209 set_reg_field_value(value, info->gfx8.bank_width_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_width_c
), 0xc0, 0x6)
210 UNP_GRPH_CONTROL_C, GRPH_BANK_WIDTH_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_width_c
), 0xc0, 0x6);
211
212 set_reg_field_value(value, info->gfx8.bank_height_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_height_c
), 0x1800, 0xb)
213 UNP_GRPH_CONTROL_C, GRPH_BANK_HEIGHT_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_height_c
), 0x1800, 0xb);
214
215 set_reg_field_value(value, info->gfx8.tile_aspect_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_aspect_c
), 0xc0000, 0x12)
216 UNP_GRPH_CONTROL_C, GRPH_MACRO_TILE_ASPECT_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_aspect_c
), 0xc0000, 0x12);
217
218 set_reg_field_value(value, info->gfx8.tile_split_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_split_c
), 0xe000, 0xd)
219 UNP_GRPH_CONTROL_C, GRPH_TILE_SPLIT_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_split_c
), 0xe000, 0xd);
220
221 set_reg_field_value(value, info->gfx8.tile_mode_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_mode_c
), 0x60000000, 0x1d)
222 UNP_GRPH_CONTROL_C, GRPH_MICRO_TILE_MODE_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_mode_c
), 0x60000000, 0x1d);
223
224 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4602, value, __func__
)
225 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4602, value, __func__
)
226 mmUNP_GRPH_CONTROL_C,dm_write_reg_func(mem_input110->base.ctx, 0x4602, value, __func__
)
227 value)dm_write_reg_func(mem_input110->base.ctx, 0x4602, value, __func__
);
228}
229
230static void program_size_and_rotation(
231 struct dce_mem_input *mem_input110,
232 enum dc_rotation_angle rotation,
233 const struct plane_size *plane_size)
234{
235 uint32_t value = 0;
236 struct plane_size local_size = *plane_size;
237
238 if (rotation == ROTATION_ANGLE_90 ||
239 rotation == ROTATION_ANGLE_270) {
240
241 swap(local_size.surface_size.x,do { __typeof(local_size.surface_size.x) __tmp = (local_size.
surface_size.x); (local_size.surface_size.x) = (local_size.surface_size
.y); (local_size.surface_size.y) = __tmp; } while(0)
242 local_size.surface_size.y)do { __typeof(local_size.surface_size.x) __tmp = (local_size.
surface_size.x); (local_size.surface_size.x) = (local_size.surface_size
.y); (local_size.surface_size.y) = __tmp; } while(0);
243 swap(local_size.surface_size.width,do { __typeof(local_size.surface_size.width) __tmp = (local_size
.surface_size.width); (local_size.surface_size.width) = (local_size
.surface_size.height); (local_size.surface_size.height) = __tmp
; } while(0)
244 local_size.surface_size.height)do { __typeof(local_size.surface_size.width) __tmp = (local_size
.surface_size.width); (local_size.surface_size.width) = (local_size
.surface_size.height); (local_size.surface_size.height) = __tmp
; } while(0);
245 swap(local_size.chroma_size.x,do { __typeof(local_size.chroma_size.x) __tmp = (local_size.chroma_size
.x); (local_size.chroma_size.x) = (local_size.chroma_size.y);
(local_size.chroma_size.y) = __tmp; } while(0)
246 local_size.chroma_size.y)do { __typeof(local_size.chroma_size.x) __tmp = (local_size.chroma_size
.x); (local_size.chroma_size.x) = (local_size.chroma_size.y);
(local_size.chroma_size.y) = __tmp; } while(0);
247 swap(local_size.chroma_size.width,do { __typeof(local_size.chroma_size.width) __tmp = (local_size
.chroma_size.width); (local_size.chroma_size.width) = (local_size
.chroma_size.height); (local_size.chroma_size.height) = __tmp
; } while(0)
248 local_size.chroma_size.height)do { __typeof(local_size.chroma_size.width) __tmp = (local_size
.chroma_size.width); (local_size.chroma_size.width) = (local_size
.chroma_size.height); (local_size.chroma_size.height) = __tmp
; } while(0);
249 }
250
251 value = 0;
252 set_reg_field_value(value, local_size.surface_pitch,(value) = set_reg_field_value_ex( (value), (local_size.surface_pitch
), 0x7fff, 0x0)
253 UNP_GRPH_PITCH_L, GRPH_PITCH_L)(value) = set_reg_field_value_ex( (value), (local_size.surface_pitch
), 0x7fff, 0x0);
254
255 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4616, value, __func__
)
256 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4616, value, __func__
)
257 mmUNP_GRPH_PITCH_L,dm_write_reg_func(mem_input110->base.ctx, 0x4616, value, __func__
)
258 value)dm_write_reg_func(mem_input110->base.ctx, 0x4616, value, __func__
);
259
260 value = 0;
261 set_reg_field_value(value, local_size.chroma_pitch,(value) = set_reg_field_value_ex( (value), (local_size.chroma_pitch
), 0x7fff, 0x0)
262 UNP_GRPH_PITCH_C, GRPH_PITCH_C)(value) = set_reg_field_value_ex( (value), (local_size.chroma_pitch
), 0x7fff, 0x0);
263 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4617, value, __func__
)
264 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4617, value, __func__
)
265 mmUNP_GRPH_PITCH_C,dm_write_reg_func(mem_input110->base.ctx, 0x4617, value, __func__
)
266 value)dm_write_reg_func(mem_input110->base.ctx, 0x4617, value, __func__
);
267
268 value = 0;
269 set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0)
270 UNP_GRPH_X_START_L, GRPH_X_START_L)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0);
271 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x461c, value, __func__
)
272 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x461c, value, __func__
)
273 mmUNP_GRPH_X_START_L,dm_write_reg_func(mem_input110->base.ctx, 0x461c, value, __func__
)
274 value)dm_write_reg_func(mem_input110->base.ctx, 0x461c, value, __func__
);
275
276 value = 0;
277 set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0)
278 UNP_GRPH_X_START_C, GRPH_X_START_C)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0);
279 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x461d, value, __func__
)
280 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x461d, value, __func__
)
281 mmUNP_GRPH_X_START_C,dm_write_reg_func(mem_input110->base.ctx, 0x461d, value, __func__
)
282 value)dm_write_reg_func(mem_input110->base.ctx, 0x461d, value, __func__
);
283
284 value = 0;
285 set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0)
286 UNP_GRPH_Y_START_L, GRPH_Y_START_L)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0);
287 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x461e, value, __func__
)
288 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x461e, value, __func__
)
289 mmUNP_GRPH_Y_START_L,dm_write_reg_func(mem_input110->base.ctx, 0x461e, value, __func__
)
290 value)dm_write_reg_func(mem_input110->base.ctx, 0x461e, value, __func__
);
291
292 value = 0;
293 set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0)
294 UNP_GRPH_Y_START_C, GRPH_Y_START_C)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0);
295 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x461f, value, __func__
)
296 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x461f, value, __func__
)
297 mmUNP_GRPH_Y_START_C,dm_write_reg_func(mem_input110->base.ctx, 0x461f, value, __func__
)
298 value)dm_write_reg_func(mem_input110->base.ctx, 0x461f, value, __func__
);
299
300 value = 0;
301 set_reg_field_value(value, local_size.surface_size.x +(value) = set_reg_field_value_ex( (value), (local_size.surface_size
.x + local_size.surface_size.width), 0x7fff, 0x0)
302 local_size.surface_size.width,(value) = set_reg_field_value_ex( (value), (local_size.surface_size
.x + local_size.surface_size.width), 0x7fff, 0x0)
303 UNP_GRPH_X_END_L, GRPH_X_END_L)(value) = set_reg_field_value_ex( (value), (local_size.surface_size
.x + local_size.surface_size.width), 0x7fff, 0x0);
304 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4620, value, __func__
)
305 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4620, value, __func__
)
306 mmUNP_GRPH_X_END_L,dm_write_reg_func(mem_input110->base.ctx, 0x4620, value, __func__
)
307 value)dm_write_reg_func(mem_input110->base.ctx, 0x4620, value, __func__
);
308
309 value = 0;
310 set_reg_field_value(value, local_size.chroma_size.x +(value) = set_reg_field_value_ex( (value), (local_size.chroma_size
.x + local_size.chroma_size.width), 0x7fff, 0x0)
311 local_size.chroma_size.width,(value) = set_reg_field_value_ex( (value), (local_size.chroma_size
.x + local_size.chroma_size.width), 0x7fff, 0x0)
312 UNP_GRPH_X_END_C, GRPH_X_END_C)(value) = set_reg_field_value_ex( (value), (local_size.chroma_size
.x + local_size.chroma_size.width), 0x7fff, 0x0);
313 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4621, value, __func__
)
314 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4621, value, __func__
)
315 mmUNP_GRPH_X_END_C,dm_write_reg_func(mem_input110->base.ctx, 0x4621, value, __func__
)
316 value)dm_write_reg_func(mem_input110->base.ctx, 0x4621, value, __func__
);
317
318 value = 0;
319 set_reg_field_value(value, local_size.surface_size.y +(value) = set_reg_field_value_ex( (value), (local_size.surface_size
.y + local_size.surface_size.height), 0x7fff, 0x0)
320 local_size.surface_size.height,(value) = set_reg_field_value_ex( (value), (local_size.surface_size
.y + local_size.surface_size.height), 0x7fff, 0x0)
321 UNP_GRPH_Y_END_L, GRPH_Y_END_L)(value) = set_reg_field_value_ex( (value), (local_size.surface_size
.y + local_size.surface_size.height), 0x7fff, 0x0);
322 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4622, value, __func__
)
323 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4622, value, __func__
)
324 mmUNP_GRPH_Y_END_L,dm_write_reg_func(mem_input110->base.ctx, 0x4622, value, __func__
)
325 value)dm_write_reg_func(mem_input110->base.ctx, 0x4622, value, __func__
);
326
327 value = 0;
328 set_reg_field_value(value, local_size.chroma_size.y +(value) = set_reg_field_value_ex( (value), (local_size.chroma_size
.y + local_size.chroma_size.height), 0x7fff, 0x0)
329 local_size.chroma_size.height,(value) = set_reg_field_value_ex( (value), (local_size.chroma_size
.y + local_size.chroma_size.height), 0x7fff, 0x0)
330 UNP_GRPH_Y_END_C, GRPH_Y_END_C)(value) = set_reg_field_value_ex( (value), (local_size.chroma_size
.y + local_size.chroma_size.height), 0x7fff, 0x0);
331 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4623, value, __func__
)
332 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4623, value, __func__
)
333 mmUNP_GRPH_Y_END_C,dm_write_reg_func(mem_input110->base.ctx, 0x4623, value, __func__
)
334 value)dm_write_reg_func(mem_input110->base.ctx, 0x4623, value, __func__
);
335
336 value = 0;
337 switch (rotation) {
338 case ROTATION_ANGLE_90:
339 set_reg_field_value(value, 3,(value) = set_reg_field_value_ex( (value), (3), 0x7, 0x0)
340 UNP_HW_ROTATION, ROTATION_ANGLE)(value) = set_reg_field_value_ex( (value), (3), 0x7, 0x0);
341 break;
342 case ROTATION_ANGLE_180:
343 set_reg_field_value(value, 2,(value) = set_reg_field_value_ex( (value), (2), 0x7, 0x0)
344 UNP_HW_ROTATION, ROTATION_ANGLE)(value) = set_reg_field_value_ex( (value), (2), 0x7, 0x0);
345 break;
346 case ROTATION_ANGLE_270:
347 set_reg_field_value(value, 1,(value) = set_reg_field_value_ex( (value), (1), 0x7, 0x0)
348 UNP_HW_ROTATION, ROTATION_ANGLE)(value) = set_reg_field_value_ex( (value), (1), 0x7, 0x0);
349 break;
350 default:
351 set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0)
352 UNP_HW_ROTATION, ROTATION_ANGLE)(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0);
353 break;
354 }
355
356 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4635, value, __func__
)
357 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4635, value, __func__
)
358 mmUNP_HW_ROTATION,dm_write_reg_func(mem_input110->base.ctx, 0x4635, value, __func__
)
359 value)dm_write_reg_func(mem_input110->base.ctx, 0x4635, value, __func__
);
360}
361
362static void program_pixel_format(
363 struct dce_mem_input *mem_input110,
364 enum surface_pixel_format format)
365{
366 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
367 uint32_t value;
368 uint8_t grph_depth;
369 uint8_t grph_format;
370
371 value = dm_read_reg(dm_read_reg_func(mem_input110->base.ctx, 0x4601, __func__)
372 mem_input110->base.ctx,dm_read_reg_func(mem_input110->base.ctx, 0x4601, __func__)
373 mmUNP_GRPH_CONTROL)dm_read_reg_func(mem_input110->base.ctx, 0x4601, __func__);
374
375 switch (format) {
376 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
377 grph_depth = 0;
378 grph_format = 0;
379 break;
380 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
381 grph_depth = 1;
382 grph_format = 1;
383 break;
384 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
385 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
386 grph_depth = 2;
387 grph_format = 0;
388 break;
389 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
390 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
391 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
392 grph_depth = 2;
393 grph_format = 1;
394 break;
395 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
396 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
397 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
398 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
399 grph_depth = 3;
400 grph_format = 0;
401 break;
402 default:
403 grph_depth = 2;
404 grph_format = 0;
405 break;
406 }
407
408 set_reg_field_value((value) = set_reg_field_value_ex( (value), (grph_depth), 0x3,
0x0)
409 value,(value) = set_reg_field_value_ex( (value), (grph_depth), 0x3,
0x0)
410 grph_depth,(value) = set_reg_field_value_ex( (value), (grph_depth), 0x3,
0x0)
411 UNP_GRPH_CONTROL,(value) = set_reg_field_value_ex( (value), (grph_depth), 0x3,
0x0)
412 GRPH_DEPTH)(value) = set_reg_field_value_ex( (value), (grph_depth), 0x3,
0x0);
413 set_reg_field_value((value) = set_reg_field_value_ex( (value), (grph_format), 0x700
, 0x8)
414 value,(value) = set_reg_field_value_ex( (value), (grph_format), 0x700
, 0x8)
415 grph_format,(value) = set_reg_field_value_ex( (value), (grph_format), 0x700
, 0x8)
416 UNP_GRPH_CONTROL,(value) = set_reg_field_value_ex( (value), (grph_format), 0x700
, 0x8)
417 GRPH_FORMAT)(value) = set_reg_field_value_ex( (value), (grph_format), 0x700
, 0x8);
418
419 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__
)
420 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__
)
421 mmUNP_GRPH_CONTROL,dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__
)
422 value)dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__
);
423
424 value = dm_read_reg(dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__)
425 mem_input110->base.ctx,dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__)
426 mmUNP_GRPH_CONTROL_EXP)dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__);
427
428 /* VIDEO FORMAT 0 */
429 set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0)
430 value,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0)
431 0,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0)
432 UNP_GRPH_CONTROL_EXP,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0)
433 VIDEO_FORMAT)(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0);
434 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__
)
435 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__
)
436 mmUNP_GRPH_CONTROL_EXP,dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__
)
437 value)dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__
);
438
439 } else {
440 /* Video 422 and 420 needs UNP_GRPH_CONTROL_EXP programmed */
441 uint32_t value;
442 uint8_t video_format;
443
444 value = dm_read_reg(dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__)
445 mem_input110->base.ctx,dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__)
446 mmUNP_GRPH_CONTROL_EXP)dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__);
447
448 switch (format) {
449 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
450 video_format = 2;
451 break;
452 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
453 video_format = 3;
454 break;
455 default:
456 video_format = 0;
457 break;
458 }
459
460 set_reg_field_value((value) = set_reg_field_value_ex( (value), (video_format), 0x7
, 0x0)
461 value,(value) = set_reg_field_value_ex( (value), (video_format), 0x7
, 0x0)
462 video_format,(value) = set_reg_field_value_ex( (value), (video_format), 0x7
, 0x0)
463 UNP_GRPH_CONTROL_EXP,(value) = set_reg_field_value_ex( (value), (video_format), 0x7
, 0x0)
464 VIDEO_FORMAT)(value) = set_reg_field_value_ex( (value), (video_format), 0x7
, 0x0);
465
466 dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__
)
467 mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__
)
468 mmUNP_GRPH_CONTROL_EXP,dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__
)
469 value)dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__
);
470 }
471}
472
473static bool_Bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
474{
475 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input)({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr
= (mem_input); (struct dce_mem_input *)( (char *)__mptr - __builtin_offsetof
(struct dce_mem_input, base) );});
476 uint32_t value;
477
478 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE)dm_read_reg_func(mem_input110->base.ctx, 0x4624, __func__);
479
480 if (get_reg_field_value(value, UNP_GRPH_UPDATE,get_reg_field_value_ex( (value), 0x4, 0x2)
481 GRPH_SURFACE_UPDATE_PENDING)get_reg_field_value_ex( (value), 0x4, 0x2))
482 return true1;
483
484 mem_input->current_address = mem_input->request_address;
485 return false0;
486}
487
488static bool_Bool dce_mem_input_v_program_surface_flip_and_addr(
489 struct mem_input *mem_input,
490 const struct dc_plane_address *address,
491 bool_Bool flip_immediate)
492{
493 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input)({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr
= (mem_input); (struct dce_mem_input *)( (char *)__mptr - __builtin_offsetof
(struct dce_mem_input, base) );});
494
495 set_flip_control(mem_input110, flip_immediate);
496 program_addr(mem_input110,
497 address);
498
499 mem_input->request_address = *address;
500
501 return true1;
502}
503
504/* Scatter Gather param tables */
505static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = {
506 { 8, 64, 64, 8, 8, 1, 4, 0, 0},
507 { 16, 64, 32, 8, 16, 1, 8, 0, 0},
508 { 32, 32, 32, 16, 16, 1, 8, 0, 0},
509 { 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */
510};
511
512static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = {
513 { 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */
514 { 16, 256, 8, 2, 0, 1, 0, 0, 0},
515 { 32, 128, 8, 4, 0, 1, 0, 0, 0},
516 { 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */
517};
518
519static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {
520 { 8, 4096, 1, 8, 0, 1, 0, 0, 0},
521 { 16, 2048, 1, 8, 0, 1, 0, 0, 0},
522 { 32, 1024, 1, 8, 0, 1, 0, 0, 0},
523 { 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */
524};
525
526/* Helper to get table entry from surface info */
527static const unsigned int *get_dvmm_hw_setting(
528 union dc_tiling_info *tiling_info,
529 enum surface_pixel_format format,
530 bool_Bool chroma)
531{
532 enum bits_per_pixel {
533 bpp_8 = 0,
534 bpp_16,
535 bpp_32,
536 bpp_64
537 } bpp;
538
539 if (format >= SURFACE_PIXEL_FORMAT_INVALID)
540 bpp = bpp_32;
541 else if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
542 bpp = chroma ? bpp_16 : bpp_8;
543 else
544 bpp = bpp_8;
545
546 switch (tiling_info->gfx8.array_mode) {
547 case DC_ARRAY_1D_TILED_THIN1:
548 case DC_ARRAY_1D_TILED_THICK:
549 case DC_ARRAY_PRT_TILED_THIN1:
550 return dvmm_Hw_Setting_1DTiling[bpp];
551 case DC_ARRAY_2D_TILED_THIN1:
552 case DC_ARRAY_2D_TILED_THICK:
553 case DC_ARRAY_2D_TILED_X_THICK:
554 case DC_ARRAY_PRT_2D_TILED_THIN1:
555 case DC_ARRAY_PRT_2D_TILED_THICK:
556 return dvmm_Hw_Setting_2DTiling[bpp];
557 case DC_ARRAY_LINEAR_GENERAL:
558 case DC_ARRAY_LINEAR_ALLIGNED:
559 return dvmm_Hw_Setting_Linear[bpp];
560 default:
561 return dvmm_Hw_Setting_2DTiling[bpp];
562 }
563}
564
565static void dce_mem_input_v_program_pte_vm(
566 struct mem_input *mem_input,
567 enum surface_pixel_format format,
568 union dc_tiling_info *tiling_info,
569 enum dc_rotation_angle rotation)
570{
571 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input)({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr
= (mem_input); (struct dce_mem_input *)( (char *)__mptr - __builtin_offsetof
(struct dce_mem_input, base) );});
572 const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false0);
573 const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true1);
574
575 unsigned int page_width = 0;
576 unsigned int page_height = 0;
577 unsigned int page_width_chroma = 0;
578 unsigned int page_height_chroma = 0;
579 unsigned int temp_page_width = pte[1];
580 unsigned int temp_page_height = pte[2];
581 unsigned int min_pte_before_flip = 0;
582 unsigned int min_pte_before_flip_chroma = 0;
583 uint32_t value = 0;
584
585 while ((temp_page_width >>= 1) != 0)
586 page_width++;
587 while ((temp_page_height >>= 1) != 0)
588 page_height++;
589
590 temp_page_width = pte_chroma[1];
591 temp_page_height = pte_chroma[2];
592 while ((temp_page_width >>= 1) != 0)
593 page_width_chroma++;
594 while ((temp_page_height >>= 1) != 0)
595 page_height_chroma++;
596
597 switch (rotation) {
598 case ROTATION_ANGLE_90:
599 case ROTATION_ANGLE_270:
600 min_pte_before_flip = pte[4];
601 min_pte_before_flip_chroma = pte_chroma[4];
602 break;
603 default:
604 min_pte_before_flip = pte[3];
605 min_pte_before_flip_chroma = pte_chroma[3];
606 break;
607 }
608
609 value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT)dm_read_reg_func(mem_input110->base.ctx, 0x463a, __func__);
610 /* TODO: un-hardcode requestlimit */
611 set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L)(value) = set_reg_field_value_ex( (value), (0xff), 0xff, 0x0);
612 set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C)(value) = set_reg_field_value_ex( (value), (0xff), 0xff00, 0x8
);
613 dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value)dm_write_reg_func(mem_input110->base.ctx, 0x463a, value, __func__
);
614
615 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL)dm_read_reg_func(mem_input110->base.ctx, 0x4629, __func__);
616 set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH)(value) = set_reg_field_value_ex( (value), (page_width), 0x1e
, 0x1);
617 set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT)(value) = set_reg_field_value_ex( (value), (page_height), 0x1e0
, 0x5);
618 set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP)(value) = set_reg_field_value_ex( (value), (min_pte_before_flip
), 0x7fe00, 0x9);
619 dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value)dm_write_reg_func(mem_input110->base.ctx, 0x4629, value, __func__
);
620
621 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL)dm_read_reg_func(mem_input110->base.ctx, 0x462a, __func__);
622 set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK)(value) = set_reg_field_value_ex( (value), (pte[5]), 0x3f, 0x0
);
623 set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING)(value) = set_reg_field_value_ex( (value), (0xff), 0xff00, 0x8
);
624 dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value)dm_write_reg_func(mem_input110->base.ctx, 0x462a, value, __func__
);
625
626 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C)dm_read_reg_func(mem_input110->base.ctx, 0x4604, __func__);
627 set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C)(value) = set_reg_field_value_ex( (value), (page_width_chroma
), 0x1e, 0x1);
628 set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C)(value) = set_reg_field_value_ex( (value), (page_height_chroma
), 0x1e0, 0x5);
629 set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C)(value) = set_reg_field_value_ex( (value), (min_pte_before_flip_chroma
), 0x7fe00, 0x9);
630 dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value)dm_write_reg_func(mem_input110->base.ctx, 0x4604, value, __func__
);
631
632 value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C)dm_read_reg_func(mem_input110->base.ctx, 0x462d, __func__);
633 set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C)(value) = set_reg_field_value_ex( (value), (pte_chroma[5]), 0x3f
, 0x0);
634 set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C)(value) = set_reg_field_value_ex( (value), (0xff), 0xff00, 0x8
);
635 dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value)dm_write_reg_func(mem_input110->base.ctx, 0x462d, value, __func__
);
636}
637
638static void dce_mem_input_v_program_surface_config(
639 struct mem_input *mem_input,
640 enum surface_pixel_format format,
641 union dc_tiling_info *tiling_info,
642 struct plane_size *plane_size,
643 enum dc_rotation_angle rotation,
644 struct dc_plane_dcc_param *dcc,
645 bool_Bool horizotal_mirror)
646{
647 struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input)({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr
= (mem_input); (struct dce_mem_input *)( (char *)__mptr - __builtin_offsetof
(struct dce_mem_input, base) );});
648
649 enable(mem_input110);
650 program_tiling(mem_input110, tiling_info, format);
651 program_size_and_rotation(mem_input110, rotation, plane_size);
652 program_pixel_format(mem_input110, format);
653}
654
655static void program_urgency_watermark(
656 const struct dc_context *ctx,
657 const uint32_t urgency_addr,
658 const uint32_t wm_addr,
659 struct dce_watermarks marks_low,
660 uint32_t total_dest_line_time_ns)
661{
662 /* register value */
663 uint32_t urgency_cntl = 0;
664 uint32_t wm_mask_cntl = 0;
665
666 /*Write mask to enable reading/writing of watermark set A*/
667 wm_mask_cntl = dm_read_reg(ctx, wm_addr)dm_read_reg_func(ctx, wm_addr, __func__);
668 set_reg_field_value(wm_mask_cntl,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1),
0x300, 0x8)
669 1,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1),
0x300, 0x8)
670 DPGV0_WATERMARK_MASK_CONTROL,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1),
0x300, 0x8)
671 URGENCY_WATERMARK_MASK)(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1),
0x300, 0x8);
672 dm_write_reg(ctx, wm_addr, wm_mask_cntl)dm_write_reg_func(ctx, wm_addr, wm_mask_cntl, __func__);
673
674 urgency_cntl = dm_read_reg(ctx, urgency_addr)dm_read_reg_func(ctx, urgency_addr, __func__);
675
676 set_reg_field_value((urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.a_mark), 0xffff, 0x0)
677 urgency_cntl,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.a_mark), 0xffff, 0x0)
678 marks_low.a_mark,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.a_mark), 0xffff, 0x0)
679 DPGV0_PIPE_URGENCY_CONTROL,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.a_mark), 0xffff, 0x0)
680 URGENCY_LOW_WATERMARK)(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.a_mark), 0xffff, 0x0);
681
682 set_reg_field_value((urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10)
683 urgency_cntl,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10)
684 total_dest_line_time_ns,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10)
685 DPGV0_PIPE_URGENCY_CONTROL,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10)
686 URGENCY_HIGH_WATERMARK)(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10);
687 dm_write_reg(ctx, urgency_addr, urgency_cntl)dm_write_reg_func(ctx, urgency_addr, urgency_cntl, __func__);
688
689 /*Write mask to enable reading/writing of watermark set B*/
690 wm_mask_cntl = dm_read_reg(ctx, wm_addr)dm_read_reg_func(ctx, wm_addr, __func__);
691 set_reg_field_value(wm_mask_cntl,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2),
0x300, 0x8)
692 2,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2),
0x300, 0x8)
693 DPGV0_WATERMARK_MASK_CONTROL,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2),
0x300, 0x8)
694 URGENCY_WATERMARK_MASK)(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2),
0x300, 0x8);
695 dm_write_reg(ctx, wm_addr, wm_mask_cntl)dm_write_reg_func(ctx, wm_addr, wm_mask_cntl, __func__);
696
697 urgency_cntl = dm_read_reg(ctx, urgency_addr)dm_read_reg_func(ctx, urgency_addr, __func__);
698
699 set_reg_field_value(urgency_cntl,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.b_mark), 0xffff, 0x0)
700 marks_low.b_mark,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.b_mark), 0xffff, 0x0)
701 DPGV0_PIPE_URGENCY_CONTROL,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.b_mark), 0xffff, 0x0)
702 URGENCY_LOW_WATERMARK)(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low
.b_mark), 0xffff, 0x0);
703
704 set_reg_field_value(urgency_cntl,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10)
705 total_dest_line_time_ns,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10)
706 DPGV0_PIPE_URGENCY_CONTROL,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10)
707 URGENCY_HIGH_WATERMARK)(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns
), 0xffff0000, 0x10);
708
709 dm_write_reg(ctx, urgency_addr, urgency_cntl)dm_write_reg_func(ctx, urgency_addr, urgency_cntl, __func__);
710}
711
712static void program_urgency_watermark_l(
713 const struct dc_context *ctx,
714 struct dce_watermarks marks_low,
715 uint32_t total_dest_line_time_ns)
716{
717 program_urgency_watermark(
718 ctx,
719 mmDPGV0_PIPE_URGENCY_CONTROL0x4733,
720 mmDPGV0_WATERMARK_MASK_CONTROL0x4732,
721 marks_low,
722 total_dest_line_time_ns);
723}
724
725static void program_urgency_watermark_c(
726 const struct dc_context *ctx,
727 struct dce_watermarks marks_low,
728 uint32_t total_dest_line_time_ns)
729{
730 program_urgency_watermark(
731 ctx,
732 mmDPGV1_PIPE_URGENCY_CONTROL0x4740,
733 mmDPGV1_WATERMARK_MASK_CONTROL0x473f,
734 marks_low,
735 total_dest_line_time_ns);
736}
737
738static void program_stutter_watermark(
739 const struct dc_context *ctx,
740 const uint32_t stutter_addr,
741 const uint32_t wm_addr,
742 struct dce_watermarks marks)
743{
744 /* register value */
745 uint32_t stutter_cntl = 0;
746 uint32_t wm_mask_cntl = 0;
747
748 /*Write mask to enable reading/writing of watermark set A*/
749
750 wm_mask_cntl = dm_read_reg(ctx, wm_addr)dm_read_reg_func(ctx, wm_addr, __func__);
751 set_reg_field_value(wm_mask_cntl,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1),
0x3, 0x0)
752 1,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1),
0x3, 0x0)
753 DPGV0_WATERMARK_MASK_CONTROL,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1),
0x3, 0x0)
754 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK)(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1),
0x3, 0x0);
755 dm_write_reg(ctx, wm_addr, wm_mask_cntl)dm_write_reg_func(ctx, wm_addr, wm_mask_cntl, __func__);
756
757 stutter_cntl = dm_read_reg(ctx, stutter_addr)dm_read_reg_func(ctx, stutter_addr, __func__);
758
759 if (ctx->dc->debug.disable_stutter) {
760 set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (0),
0x1, 0x0)
761 0,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (0),
0x1, 0x0)
762 DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (0),
0x1, 0x0)
763 STUTTER_ENABLE)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (0),
0x1, 0x0);
764 } else {
765 set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1),
0x1, 0x0)
766 1,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1),
0x1, 0x0)
767 DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1),
0x1, 0x0)
768 STUTTER_ENABLE)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1),
0x1, 0x0);
769 }
770
771 set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1),
0x80, 0x7)
772 1,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1),
0x80, 0x7)
773 DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1),
0x80, 0x7)
774 STUTTER_IGNORE_FBC)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1),
0x80, 0x7);
775
776 /*Write watermark set A*/
777 set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks
.a_mark), 0xffff0000, 0x10)
778 marks.a_mark,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks
.a_mark), 0xffff0000, 0x10)
779 DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks
.a_mark), 0xffff0000, 0x10)
780 STUTTER_EXIT_SELF_REFRESH_WATERMARK)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks
.a_mark), 0xffff0000, 0x10);
781 dm_write_reg(ctx, stutter_addr, stutter_cntl)dm_write_reg_func(ctx, stutter_addr, stutter_cntl, __func__);
782
783 /*Write mask to enable reading/writing of watermark set B*/
784 wm_mask_cntl = dm_read_reg(ctx, wm_addr)dm_read_reg_func(ctx, wm_addr, __func__);
785 set_reg_field_value(wm_mask_cntl,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2),
0x3, 0x0)
786 2,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2),
0x3, 0x0)
787 DPGV0_WATERMARK_MASK_CONTROL,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2),
0x3, 0x0)
788 STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK)(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2),
0x3, 0x0);
789 dm_write_reg(ctx, wm_addr, wm_mask_cntl)dm_write_reg_func(ctx, wm_addr, wm_mask_cntl, __func__);
790
791 stutter_cntl = dm_read_reg(ctx, stutter_addr)dm_read_reg_func(ctx, stutter_addr, __func__);
792 /*Write watermark set B*/
793 set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks
.b_mark), 0xffff0000, 0x10)
794 marks.b_mark,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks
.b_mark), 0xffff0000, 0x10)
795 DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks
.b_mark), 0xffff0000, 0x10)
796 STUTTER_EXIT_SELF_REFRESH_WATERMARK)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks
.b_mark), 0xffff0000, 0x10);
797 dm_write_reg(ctx, stutter_addr, stutter_cntl)dm_write_reg_func(ctx, stutter_addr, stutter_cntl, __func__);
798}
799
800static void program_stutter_watermark_l(
801 const struct dc_context *ctx,
802 struct dce_watermarks marks)
803{
804 program_stutter_watermark(ctx,
805 mmDPGV0_PIPE_STUTTER_CONTROL0x4735,
806 mmDPGV0_WATERMARK_MASK_CONTROL0x4732,
807 marks);
808}
809
810static void program_stutter_watermark_c(
811 const struct dc_context *ctx,
812 struct dce_watermarks marks)
813{
814 program_stutter_watermark(ctx,
815 mmDPGV1_PIPE_STUTTER_CONTROL0x4742,
816 mmDPGV1_WATERMARK_MASK_CONTROL0x473f,
817 marks);
818}
819
820static void program_nbp_watermark(
821 const struct dc_context *ctx,
822 const uint32_t wm_mask_ctrl_addr,
823 const uint32_t nbp_pstate_ctrl_addr,
824 struct dce_watermarks marks)
825{
826 uint32_t value;
827
828 /* Write mask to enable reading/writing of watermark set A */
829
830 value = dm_read_reg(ctx, wm_mask_ctrl_addr)dm_read_reg_func(ctx, wm_mask_ctrl_addr, __func__);
831
832 set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10
)
833 value,(value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10
)
834 1,(value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10
)
835 DPGV0_WATERMARK_MASK_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10
)
836 NB_PSTATE_CHANGE_WATERMARK_MASK)(value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10
);
837 dm_write_reg(ctx, wm_mask_ctrl_addr, value)dm_write_reg_func(ctx, wm_mask_ctrl_addr, value, __func__);
838
839 value = dm_read_reg(ctx, nbp_pstate_ctrl_addr)dm_read_reg_func(ctx, nbp_pstate_ctrl_addr, __func__);
840
841 set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
842 value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
843 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
844 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
845 NB_PSTATE_CHANGE_ENABLE)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0);
846 set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4)
847 value,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4)
848 1,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4)
849 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4)
850 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST)(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4);
851 set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8)
852 value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8)
853 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8)
854 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8)
855 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8);
856 dm_write_reg(ctx, nbp_pstate_ctrl_addr, value)dm_write_reg_func(ctx, nbp_pstate_ctrl_addr, value, __func__);
857
858 /* Write watermark set A */
859 value = dm_read_reg(ctx, nbp_pstate_ctrl_addr)dm_read_reg_func(ctx, nbp_pstate_ctrl_addr, __func__);
860 set_reg_field_value((value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000
, 0x10)
861 value,(value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000
, 0x10)
862 marks.a_mark,(value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000
, 0x10)
863 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000
, 0x10)
864 NB_PSTATE_CHANGE_WATERMARK)(value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000
, 0x10);
865 dm_write_reg(ctx, nbp_pstate_ctrl_addr, value)dm_write_reg_func(ctx, nbp_pstate_ctrl_addr, value, __func__);
866
867 /* Write mask to enable reading/writing of watermark set B */
868 value = dm_read_reg(ctx, wm_mask_ctrl_addr)dm_read_reg_func(ctx, wm_mask_ctrl_addr, __func__);
869 set_reg_field_value((value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10
)
870 value,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10
)
871 2,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10
)
872 DPGV0_WATERMARK_MASK_CONTROL,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10
)
873 NB_PSTATE_CHANGE_WATERMARK_MASK)(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10
);
874 dm_write_reg(ctx, wm_mask_ctrl_addr, value)dm_write_reg_func(ctx, wm_mask_ctrl_addr, value, __func__);
875
876 value = dm_read_reg(ctx, nbp_pstate_ctrl_addr)dm_read_reg_func(ctx, nbp_pstate_ctrl_addr, __func__);
877 set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
878 value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
879 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
880 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0)
881 NB_PSTATE_CHANGE_ENABLE)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0);
882 set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4)
883 value,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4)
884 1,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4)
885 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4)
886 NB_PSTATE_CHANGE_URGENT_DURING_REQUEST)(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4);
887 set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8)
888 value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8)
889 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8)
890 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8)
891 NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8);
892 dm_write_reg(ctx, nbp_pstate_ctrl_addr, value)dm_write_reg_func(ctx, nbp_pstate_ctrl_addr, value, __func__);
893
894 /* Write watermark set B */
895 value = dm_read_reg(ctx, nbp_pstate_ctrl_addr)dm_read_reg_func(ctx, nbp_pstate_ctrl_addr, __func__);
896 set_reg_field_value((value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000
, 0x10)
897 value,(value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000
, 0x10)
898 marks.b_mark,(value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000
, 0x10)
899 DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000
, 0x10)
900 NB_PSTATE_CHANGE_WATERMARK)(value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000
, 0x10);
901 dm_write_reg(ctx, nbp_pstate_ctrl_addr, value)dm_write_reg_func(ctx, nbp_pstate_ctrl_addr, value, __func__);
902}
903
904static void program_nbp_watermark_l(
905 const struct dc_context *ctx,
906 struct dce_watermarks marks)
907{
908 program_nbp_watermark(ctx,
909 mmDPGV0_WATERMARK_MASK_CONTROL0x4732,
910 mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL0x4736,
911 marks);
912}
913
914static void program_nbp_watermark_c(
915 const struct dc_context *ctx,
916 struct dce_watermarks marks)
917{
918 program_nbp_watermark(ctx,
919 mmDPGV1_WATERMARK_MASK_CONTROL0x473f,
920 mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL0x4743,
921 marks);
922}
923
924static void dce_mem_input_v_program_display_marks(
925 struct mem_input *mem_input,
926 struct dce_watermarks nbp,
927 struct dce_watermarks stutter,
928 struct dce_watermarks stutter_enter,
929 struct dce_watermarks urgent,
930 uint32_t total_dest_line_time_ns)
931{
932 program_urgency_watermark_l(
933 mem_input->ctx,
934 urgent,
935 total_dest_line_time_ns);
936
937 program_nbp_watermark_l(
938 mem_input->ctx,
939 nbp);
940
941 program_stutter_watermark_l(
942 mem_input->ctx,
943 stutter);
944
945}
946
947static void dce_mem_input_program_chroma_display_marks(
948 struct mem_input *mem_input,
949 struct dce_watermarks nbp,
950 struct dce_watermarks stutter,
951 struct dce_watermarks urgent,
952 uint32_t total_dest_line_time_ns)
953{
954 program_urgency_watermark_c(
955 mem_input->ctx,
956 urgent,
957 total_dest_line_time_ns);
958
959 program_nbp_watermark_c(
960 mem_input->ctx,
961 nbp);
962
963 program_stutter_watermark_c(
964 mem_input->ctx,
965 stutter);
966}
967
968static void dce110_allocate_mem_input_v(
969 struct mem_input *mi,
970 uint32_t h_total,/* for current stream */
971 uint32_t v_total,/* for current stream */
972 uint32_t pix_clk_khz,/* for current stream */
973 uint32_t total_stream_num)
974{
975 uint32_t addr;
976 uint32_t value;
977 uint32_t pix_dur;
978 if (pix_clk_khz != 0) {
979 addr = mmDPGV0_PIPE_ARBITRATION_CONTROL10x4730;
980 value = dm_read_reg(mi->ctx, addr)dm_read_reg_func(mi->ctx, addr, __func__);
981 pix_dur = 1000000000ULL / pix_clk_khz;
982 set_reg_field_value((value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0)
983 value,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0)
984 pix_dur,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0)
985 DPGV0_PIPE_ARBITRATION_CONTROL1,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0)
986 PIXEL_DURATION)(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0);
987 dm_write_reg(mi->ctx, addr, value)dm_write_reg_func(mi->ctx, addr, value, __func__);
988
989 addr = mmDPGV1_PIPE_ARBITRATION_CONTROL10x473d;
990 value = dm_read_reg(mi->ctx, addr)dm_read_reg_func(mi->ctx, addr, __func__);
991 pix_dur = 1000000000ULL / pix_clk_khz;
992 set_reg_field_value((value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0)
993 value,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0)
994 pix_dur,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0)
995 DPGV1_PIPE_ARBITRATION_CONTROL1,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0)
996 PIXEL_DURATION)(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff,
0x0);
997 dm_write_reg(mi->ctx, addr, value)dm_write_reg_func(mi->ctx, addr, value, __func__);
998
999 addr = mmDPGV0_PIPE_ARBITRATION_CONTROL20x4731;
1000 value = 0x4000800;
1001 dm_write_reg(mi->ctx, addr, value)dm_write_reg_func(mi->ctx, addr, value, __func__);
1002
1003 addr = mmDPGV1_PIPE_ARBITRATION_CONTROL20x473e;
1004 value = 0x4000800;
1005 dm_write_reg(mi->ctx, addr, value)dm_write_reg_func(mi->ctx, addr, value, __func__);
1006 }
1007
1008}
1009
1010static void dce110_free_mem_input_v(
1011 struct mem_input *mi,
1012 uint32_t total_stream_num)
1013{
1014}
1015
1016static const struct mem_input_funcs dce110_mem_input_v_funcs = {
1017 .mem_input_program_display_marks =
1018 dce_mem_input_v_program_display_marks,
1019 .mem_input_program_chroma_display_marks =
1020 dce_mem_input_program_chroma_display_marks,
1021 .allocate_mem_input = dce110_allocate_mem_input_v,
1022 .free_mem_input = dce110_free_mem_input_v,
1023 .mem_input_program_surface_flip_and_addr =
1024 dce_mem_input_v_program_surface_flip_and_addr,
1025 .mem_input_program_pte_vm =
1026 dce_mem_input_v_program_pte_vm,
1027 .mem_input_program_surface_config =
1028 dce_mem_input_v_program_surface_config,
1029 .mem_input_is_flip_pending =
1030 dce_mem_input_v_is_surface_pending
1031};
1032/*****************************************/
1033/* Constructor, Destructor */
1034/*****************************************/
1035
1036void dce110_mem_input_v_construct(
1037 struct dce_mem_input *dce_mi,
1038 struct dc_context *ctx)
1039{
1040 dce_mi->base.funcs = &dce110_mem_input_v_funcs;
1041 dce_mi->base.ctx = ctx;
1042}
1043