Bug Summary

File:dev/pci/drm/amd/display/dc/dcn201/dcn201_resource.c
Warning:line 1018, column 22
Access to field 'stream' results in a dereference of a null pointer (loaded from variable 'head_pipe')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name dcn201_resource.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_resource.c
1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "dc.h"
28
29#include "dcn201_init.h"
30#include "dml/dcn20/dcn20_fpu.h"
31#include "resource.h"
32#include "include/irq_service_interface.h"
33#include "dcn201_resource.h"
34
35#include "dcn20/dcn20_resource.h"
36
37#include "dcn10/dcn10_hubp.h"
38#include "dcn10/dcn10_ipp.h"
39#include "dcn201_mpc.h"
40#include "dcn201_hubp.h"
41#include "irq/dcn201/irq_service_dcn201.h"
42#include "dcn201/dcn201_dpp.h"
43#include "dcn201/dcn201_hubbub.h"
44#include "dcn201_dccg.h"
45#include "dcn201_optc.h"
46#include "dcn201_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
48#include "dcn201_opp.h"
49#include "dcn201/dcn201_link_encoder.h"
50#include "dcn20/dcn20_stream_encoder.h"
51#include "dce/dce_clock_source.h"
52#include "dce/dce_audio.h"
53#include "dce/dce_hwseq.h"
54#include "virtual/virtual_stream_encoder.h"
55#include "dce110/dce110_resource.h"
56#include "dce/dce_aux.h"
57#include "dce/dce_i2c.h"
58#include "dcn201_hubbub.h"
59#include "dcn10/dcn10_resource.h"
60
61#include "cyan_skillfish_ip_offset.h"
62
63#include "dcn/dcn_2_0_3_offset.h"
64#include "dcn/dcn_2_0_3_sh_mask.h"
65#include "dpcs/dpcs_2_0_3_offset.h"
66#include "dpcs/dpcs_2_0_3_sh_mask.h"
67
68#include "mmhub/mmhub_2_0_0_offset.h"
69#include "mmhub/mmhub_2_0_0_sh_mask.h"
70#include "nbio/nbio_7_4_offset.h"
71
72#include "reg_helper.h"
73
74#define MIN_DISP_CLK_KHZ100000 100000
75#define MIN_DPP_CLK_KHZ100000 100000
76
77struct _vcs_dpi_ip_params_st dcn201_ip = {
78 .gpuvm_enable = 0,
79 .hostvm_enable = 0,
80 .gpuvm_max_page_table_levels = 4,
81 .hostvm_max_page_table_levels = 4,
82 .hostvm_cached_page_table_levels = 0,
83 .pte_group_size_bytes = 2048,
84 .rob_buffer_size_kbytes = 168,
85 .det_buffer_size_kbytes = 164,
86 .dpte_buffer_size_in_pte_reqs_luma = 84,
87 .pde_proc_buffer_size_64k_reqs = 48,
88 .dpp_output_buffer_pixels = 2560,
89 .opp_output_buffer_lines = 1,
90 .pixel_chunk_size_kbytes = 8,
91 .pte_chunk_size_kbytes = 2,
92 .meta_chunk_size_kbytes = 2,
93 .writeback_chunk_size_kbytes = 2,
94 .line_buffer_size_bits = 789504,
95 .is_line_buffer_bpp_fixed = 0,
96 .line_buffer_fixed_bpp = 0,
97 .dcc_supported = true1,
98 .max_line_buffer_lines = 12,
99 .writeback_luma_buffer_size_kbytes = 12,
100 .writeback_chroma_buffer_size_kbytes = 8,
101 .writeback_chroma_line_buffer_width_pixels = 4,
102 .writeback_max_hscl_ratio = 1,
103 .writeback_max_vscl_ratio = 1,
104 .writeback_min_hscl_ratio = 1,
105 .writeback_min_vscl_ratio = 1,
106 .writeback_max_hscl_taps = 12,
107 .writeback_max_vscl_taps = 12,
108 .writeback_line_buffer_luma_buffer_size = 0,
109 .writeback_line_buffer_chroma_buffer_size = 9600,
110 .cursor_buffer_size = 8,
111 .cursor_chunk_size = 2,
112 .max_num_otg = 2,
113 .max_num_dpp = 4,
114 .max_num_wb = 0,
115 .max_dchub_pscl_bw_pix_per_clk = 4,
116 .max_pscl_lb_bw_pix_per_clk = 2,
117 .max_lb_vscl_bw_pix_per_clk = 4,
118 .max_vscl_hscl_bw_pix_per_clk = 4,
119 .max_hscl_ratio = 8,
120 .max_vscl_ratio = 8,
121 .hscl_mults = 4,
122 .vscl_mults = 4,
123 .max_hscl_taps = 8,
124 .max_vscl_taps = 8,
125 .dispclk_ramp_margin_percent = 1,
126 .underscan_factor = 1.10,
127 .min_vblank_lines = 30,
128 .dppclk_delay_subtotal = 77,
129 .dppclk_delay_scl_lb_only = 16,
130 .dppclk_delay_scl = 50,
131 .dppclk_delay_cnvc_formatter = 8,
132 .dppclk_delay_cnvc_cursor = 6,
133 .dispclk_delay_subtotal = 87,
134 .dcfclk_cstate_latency = 10,
135 .max_inter_dcn_tile_repeaters = 8,
136 .number_of_cursors = 1,
137};
138
139struct _vcs_dpi_soc_bounding_box_st dcn201_soc = {
140 .clock_limits = {
141 {
142 .state = 0,
143 .dscclk_mhz = 400.0,
144 .dcfclk_mhz = 1000.0,
145 .fabricclk_mhz = 200.0,
146 .dispclk_mhz = 300.0,
147 .dppclk_mhz = 300.0,
148 .phyclk_mhz = 810.0,
149 .socclk_mhz = 1254.0,
150 .dram_speed_mts = 2000.0,
151 },
152 {
153 .state = 1,
154 .dscclk_mhz = 400.0,
155 .dcfclk_mhz = 1000.0,
156 .fabricclk_mhz = 250.0,
157 .dispclk_mhz = 1200.0,
158 .dppclk_mhz = 1200.0,
159 .phyclk_mhz = 810.0,
160 .socclk_mhz = 1254.0,
161 .dram_speed_mts = 3600.0,
162 },
163 {
164 .state = 2,
165 .dscclk_mhz = 400.0,
166 .dcfclk_mhz = 1000.0,
167 .fabricclk_mhz = 750.0,
168 .dispclk_mhz = 1200.0,
169 .dppclk_mhz = 1200.0,
170 .phyclk_mhz = 810.0,
171 .socclk_mhz = 1254.0,
172 .dram_speed_mts = 6800.0,
173 },
174 {
175 .state = 3,
176 .dscclk_mhz = 400.0,
177 .dcfclk_mhz = 1000.0,
178 .fabricclk_mhz = 250.0,
179 .dispclk_mhz = 1200.0,
180 .dppclk_mhz = 1200.0,
181 .phyclk_mhz = 810.0,
182 .socclk_mhz = 1254.0,
183 .dram_speed_mts = 14000.0,
184 },
185 {
186 .state = 4,
187 .dscclk_mhz = 400.0,
188 .dcfclk_mhz = 1000.0,
189 .fabricclk_mhz = 750.0,
190 .dispclk_mhz = 1200.0,
191 .dppclk_mhz = 1200.0,
192 .phyclk_mhz = 810.0,
193 .socclk_mhz = 1254.0,
194 .dram_speed_mts = 14000.0,
195 }
196 },
197 .num_states = 4,
198 .sr_exit_time_us = 9.0,
199 .sr_enter_plus_exit_time_us = 11.0,
200 .urgent_latency_us = 4.0,
201 .urgent_latency_pixel_data_only_us = 4.0,
202 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
203 .urgent_latency_vm_data_only_us = 4.0,
204 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 256,
205 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 256,
206 .urgent_out_of_order_return_per_channel_vm_only_bytes = 256,
207 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
208 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 80.0,
209 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 80.0,
210 .max_avg_sdp_bw_use_normal_percent = 80.0,
211 .max_avg_dram_bw_use_normal_percent = 69.0,
212 .writeback_latency_us = 12.0,
213 .ideal_dram_bw_after_urgent_percent = 80.0,
214 .max_request_size_bytes = 256,
215 .dram_channel_width_bytes = 2,
216 .fabric_datapath_to_dcn_data_return_bytes = 64,
217 .dcn_downspread_percent = 0.3,
218 .downspread_percent = 0.3,
219 .dram_page_open_time_ns = 50.0,
220 .dram_rw_turnaround_time_ns = 17.5,
221 .dram_return_buffer_per_channel_bytes = 8192,
222 .round_trip_ping_latency_dcfclk_cycles = 128,
223 .urgent_out_of_order_return_per_channel_bytes = 256,
224 .channel_interleave_bytes = 256,
225 .num_banks = 8,
226 .num_chans = 16,
227 .vmm_page_size_bytes = 4096,
228 .dram_clock_change_latency_us = 250.0,
229 .writeback_dram_clock_change_latency_us = 23.0,
230 .return_bus_width_bytes = 64,
231 .dispclk_dppclk_vco_speed_mhz = 3000,
232 .use_urgent_burst_bw = 0,
233};
234
235enum dcn20_clk_src_array_id {
236 DCN20_CLK_SRC_PLL0,
237 DCN20_CLK_SRC_PLL1,
238 DCN20_CLK_SRC_TOTAL_DCN201
239};
240
241/* begin *********************
242 * macros to expend register list macro defined in HW object header file */
243
244/* DCN */
245
246#undef BASE_INNER
247#define BASE_INNER(seg)DMU_BASE__INST0_SEGseg DMU_BASE__INST0_SEG ## seg
248
249#define BASE(seg)DMU_BASE__INST0_SEGseg BASE_INNER(seg)DMU_BASE__INST0_SEGseg
250
251#define SR(reg_name).reg_name = DMU_BASE__INST0_SEGmmreg_name_BASE_IDX + mmreg_name\
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX)DMU_BASE__INST0_SEGmm ## reg_name ## _BASE_IDX + \
253 mm ## reg_name
254
255#define SRI(reg_name, block, id).reg_name = DMU_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX + mmblockid_reg_name\
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DMU_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
257 mm ## block ## id ## _ ## reg_name
258
259#define SRIR(var_name, reg_name, block, id).var_name = DMU_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX + mmblockid_reg_name\
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DMU_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
261 mm ## block ## id ## _ ## reg_name
262
263#define SRII(reg_name, block, id).reg_name[id] = DMU_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX
+ mmblockid_reg_name\
264 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DMU_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
265 mm ## block ## id ## _ ## reg_name
266
267#define SRI_IX(reg_name, block, id).reg_name = ixblockid_reg_name\
268 .reg_name = ix ## block ## id ## _ ## reg_name
269
270#define DCCG_SRII(reg_name, block, id).block_reg_name[id] = DMU_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX
+ mmblockid_reg_name\
271 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DMU_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \
272 mm ## block ## id ## _ ## reg_name
273
274#define VUPDATE_SRII(reg_name, block, id).reg_name[id] = DMU_BASE__INST0_SEGmmreg_name_blockid_BASE_IDX
+ mmreg_name_blockid\
275 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX)DMU_BASE__INST0_SEGmm ## reg_name ## _ ## block ## id ## _BASE_IDX + \
276 mm ## reg_name ## _ ## block ## id
277
278/* NBIO */
279#define NBIO_BASE_INNER(seg)NBIO_BASE__INST0_SEGseg \
280 NBIO_BASE__INST0_SEG ## seg
281
282#define NBIO_BASE(seg)NBIO_BASE__INST0_SEGseg \
283 NBIO_BASE_INNER(seg)NBIO_BASE__INST0_SEGseg
284
285#define NBIO_SR(reg_name).reg_name = NBIO_BASE__INST0_SEGmmreg_name_BASE_IDX + mmreg_name\
286 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX)NBIO_BASE__INST0_SEGmm ## reg_name ## _BASE_IDX + \
287 mm ## reg_name
288
289/* MMHUB */
290#define MMHUB_BASE_INNER(seg)MMHUB_BASE__INST0_SEGseg \
291 MMHUB_BASE__INST0_SEG ## seg
292
293#define MMHUB_BASE(seg)MMHUB_BASE__INST0_SEGseg \
294 MMHUB_BASE_INNER(seg)MMHUB_BASE__INST0_SEGseg
295
296#define MMHUB_SR(reg_name).reg_name = MMHUB_BASE__INST0_SEGmmMMreg_name_BASE_IDX + mmMMreg_name\
297 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX)MMHUB_BASE__INST0_SEGmmMM ## reg_name ## _BASE_IDX + \
298 mmMM ## reg_name
299
300static const struct bios_registers bios_regs = {
301 NBIO_SR(BIOS_SCRATCH_3).BIOS_SCRATCH_3 = 0x00000014 + 0x003b,
302 NBIO_SR(BIOS_SCRATCH_6).BIOS_SCRATCH_6 = 0x00000014 + 0x003e
303};
304
305#define clk_src_regs(index, pllid)[index] = { .PIXCLK_RESYNC_CNTL = DMU_BASE__INST0_SEGmmPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX
+ mmPHYPLLpllid_PIXCLK_RESYNC_CNTL, .PHASE[0] = 0x000000C0 +
0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .MODULO[0] = 0x000000C0
+ 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .PIXEL_RATE_CNTL
[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 +
0x0084,}\
306[index] = {\
307 CS_COMMON_REG_LIST_DCN201(index, pllid).PIXCLK_RESYNC_CNTL = DMU_BASE__INST0_SEGmmPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX
+ mmPHYPLLpllid_PIXCLK_RESYNC_CNTL, .PHASE[0] = 0x000000C0 +
0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .MODULO[0] = 0x000000C0
+ 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .PIXEL_RATE_CNTL
[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 +
0x0084,\
308}
309
310static const struct dce110_clk_src_regs clk_src_regs[] = {
311 clk_src_regs(0, A)[0] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0040, .PHASE[0] =
0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .MODULO
[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .
PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1]
= 0x000000C0 + 0x0084,},
312 clk_src_regs(1, B)[1] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0041, .PHASE[0] =
0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .MODULO
[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .
PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1]
= 0x000000C0 + 0x0084,}
313};
314
315static const struct dce110_clk_src_shift cs_shift = {
316 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT).DP_DTO0_PHASE = 0x0, .DP_DTO0_MODULO = 0x0, .PHYPLLA_DCCG_DEEP_COLOR_CNTL
= 0x4, .DP_DTO0_ENABLE = 0x4
317};
318
319static const struct dce110_clk_src_mask cs_mask = {
320 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK).DP_DTO0_PHASE = 0xFFFFFFFFL, .DP_DTO0_MODULO = 0xFFFFFFFFL, .
PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x00000030L, .DP_DTO0_ENABLE =
0x00000010L
321};
322
323#define audio_regs(id)[id] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = DMU_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
+ mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, .AZALIA_F0_CODEC_ENDPOINT_DATA
= DMU_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX
+ mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}\
324[id] = {\
325 AUD_COMMON_REG_LIST(id).AZALIA_F0_CODEC_ENDPOINT_INDEX = DMU_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
+ mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, .AZALIA_F0_CODEC_ENDPOINT_DATA
= DMU_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX
+ mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae\
326}
327
328static const struct dce_audio_registers audio_regs[] = {
329 audio_regs(0)[0] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0386
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0387, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae},
330 audio_regs(1)[1] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x038c
, .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x038d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
= 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
= 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
= 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 +
0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE
= 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 +
0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae},
331};
332
333#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh
, .AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh
, .DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh
, .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh
, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh
, .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh
, .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh
, .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh
, .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh
, .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh
, .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh\
334 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh,\
335 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh).AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh,\
336 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh).DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh
, .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh
, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh
, .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh
, .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh
, .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh
, .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh
, .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh
, .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh
, .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh
337
338static const struct dce_audio_shift audio_shift = {
339 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT).AZALIA_ENDPOINT_REG_INDEX = 0x0, .AZALIA_ENDPOINT_REG_DATA =
0x0, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x0, .DCCG_AUDIO_DTO_SEL =
0x4, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x14, .DCCG_AUDIO_DTO0_USE_512FBR_DTO
= 0x18, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x1c, .DCCG_AUDIO_DTO0_MODULE
= 0x0, .DCCG_AUDIO_DTO0_PHASE = 0x0, .DCCG_AUDIO_DTO1_MODULE
= 0x0, .DCCG_AUDIO_DTO1_PHASE = 0x0, .AUDIO_RATE_CAPABILITIES
= 0x0, .CLKSTOP = 0x1e, .EPSS = 0x1f
340};
341
342static const struct dce_audio_mask audio_mask = {
343 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK).AZALIA_ENDPOINT_REG_INDEX = 0x00003FFFL, .AZALIA_ENDPOINT_REG_DATA
= 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x00000007L, .DCCG_AUDIO_DTO_SEL
= 0x00000030L, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x00100000L
, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = 0x01000000L, .DCCG_AUDIO_DTO1_USE_512FBR_DTO
= 0x10000000L, .DCCG_AUDIO_DTO0_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_PHASE
= 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_PHASE
= 0xFFFFFFFFL, .AUDIO_RATE_CAPABILITIES = 0x00000FFFL, .CLKSTOP
= 0x40000000L, .EPSS = 0x80000000L
344};
345
346#define stream_enc_regs(id)[id] = { .AFMT_CNTL = DMU_BASE__INST0_SEGmmDIGid_AFMT_CNTL_BASE_IDX
+ mmDIGid_AFMT_CNTL, .AFMT_GENERIC_0 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_0_BASE_IDX
+ mmDIGid_AFMT_GENERIC_0, .AFMT_GENERIC_1 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_1_BASE_IDX
+ mmDIGid_AFMT_GENERIC_1, .AFMT_GENERIC_2 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_2_BASE_IDX
+ mmDIGid_AFMT_GENERIC_2, .AFMT_GENERIC_3 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_3_BASE_IDX
+ mmDIGid_AFMT_GENERIC_3, .AFMT_GENERIC_4 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_4_BASE_IDX
+ mmDIGid_AFMT_GENERIC_4, .AFMT_GENERIC_5 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_5_BASE_IDX
+ mmDIGid_AFMT_GENERIC_5, .AFMT_GENERIC_6 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_6_BASE_IDX
+ mmDIGid_AFMT_GENERIC_6, .AFMT_GENERIC_7 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_7_BASE_IDX
+ mmDIGid_AFMT_GENERIC_7, .AFMT_GENERIC_HDR = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_HDR_BASE_IDX
+ mmDIGid_AFMT_GENERIC_HDR, .AFMT_INFOFRAME_CONTROL0 = DMU_BASE__INST0_SEGmmDIGid_AFMT_INFOFRAME_CONTROL0_BASE_IDX
+ mmDIGid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL =
DMU_BASE__INST0_SEGmmDIGid_AFMT_VBI_PACKET_CONTROL_BASE_IDX +
mmDIGid_AFMT_VBI_PACKET_CONTROL, .AFMT_VBI_PACKET_CONTROL1 =
DMU_BASE__INST0_SEGmmDIGid_AFMT_VBI_PACKET_CONTROL1_BASE_IDX
+ mmDIGid_AFMT_VBI_PACKET_CONTROL1, .AFMT_AUDIO_PACKET_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX
+ mmDIGid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2
= DMU_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX
+ mmDIGid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX
+ mmDIGid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = DMU_BASE__INST0_SEGmmDIGid_AFMT_60958_0_BASE_IDX
+ mmDIGid_AFMT_60958_0, .AFMT_60958_1 = DMU_BASE__INST0_SEGmmDIGid_AFMT_60958_1_BASE_IDX
+ mmDIGid_AFMT_60958_1, .AFMT_60958_2 = DMU_BASE__INST0_SEGmmDIGid_AFMT_60958_2_BASE_IDX
+ mmDIGid_AFMT_60958_2, .DIG_FE_CNTL = DMU_BASE__INST0_SEGmmDIGid_DIG_FE_CNTL_BASE_IDX
+ mmDIGid_DIG_FE_CNTL, .DIG_FIFO_STATUS = DMU_BASE__INST0_SEGmmDIGid_DIG_FIFO_STATUS_BASE_IDX
+ mmDIGid_DIG_FIFO_STATUS, .HDMI_CONTROL = DMU_BASE__INST0_SEGmmDIGid_HDMI_CONTROL_BASE_IDX
+ mmDIGid_HDMI_CONTROL, .HDMI_DB_CONTROL = DMU_BASE__INST0_SEGmmDIGid_HDMI_DB_CONTROL_BASE_IDX
+ mmDIGid_HDMI_DB_CONTROL, .HDMI_GC = DMU_BASE__INST0_SEGmmDIGid_HDMI_GC_BASE_IDX
+ mmDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 = DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1
= DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_GENERIC_PACKET_CONTROL2
= DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL2, .HDMI_GENERIC_PACKET_CONTROL3
= DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL3, .HDMI_INFOFRAME_CONTROL0
= DMU_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX
+ mmDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 =
DMU_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX +
mmDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = DMU_BASE__INST0_SEGmmDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_0_BASE_IDX
+ mmDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_1_BASE_IDX
+ mmDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_0_BASE_IDX
+ mmDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_1_BASE_IDX
+ mmDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_0_BASE_IDX
+ mmDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_1_BASE_IDX
+ mmDIGid_HDMI_ACR_48_1, .DP_DB_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DB_CNTL_BASE_IDX
+ mmDPid_DP_DB_CNTL, .DP_MSA_MISC = DMU_BASE__INST0_SEGmmDPid_DP_MSA_MISC_BASE_IDX
+ mmDPid_DP_MSA_MISC, .DP_MSA_VBID_MISC = DMU_BASE__INST0_SEGmmDPid_DP_MSA_VBID_MISC_BASE_IDX
+ mmDPid_DP_MSA_VBID_MISC, .DP_MSA_COLORIMETRY = DMU_BASE__INST0_SEGmmDPid_DP_MSA_COLORIMETRY_BASE_IDX
+ mmDPid_DP_MSA_COLORIMETRY, .DP_MSA_TIMING_PARAM1 = DMU_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM1_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM1, .DP_MSA_TIMING_PARAM2 = DMU_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM2_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM2, .DP_MSA_TIMING_PARAM3 = DMU_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM3_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM3, .DP_MSA_TIMING_PARAM4 = DMU_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM4_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM4, .DP_MSE_RATE_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_MSE_RATE_CNTL_BASE_IDX
+ mmDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE = DMU_BASE__INST0_SEGmmDPid_DP_MSE_RATE_UPDATE_BASE_IDX
+ mmDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = DMU_BASE__INST0_SEGmmDPid_DP_PIXEL_FORMAT_BASE_IDX
+ mmDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX
+ mmDPid_DP_SEC_CNTL, .DP_SEC_CNTL1 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL1_BASE_IDX
+ mmDPid_DP_SEC_CNTL1, .DP_SEC_CNTL2 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL2_BASE_IDX
+ mmDPid_DP_SEC_CNTL2, .DP_SEC_CNTL5 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL5_BASE_IDX
+ mmDPid_DP_SEC_CNTL5, .DP_SEC_CNTL6 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL6_BASE_IDX
+ mmDPid_DP_SEC_CNTL6, .DP_STEER_FIFO = DMU_BASE__INST0_SEGmmDPid_DP_STEER_FIFO_BASE_IDX
+ mmDPid_DP_STEER_FIFO, .DP_VID_M = DMU_BASE__INST0_SEGmmDPid_DP_VID_M_BASE_IDX
+ mmDPid_DP_VID_M, .DP_VID_N = DMU_BASE__INST0_SEGmmDPid_DP_VID_N_BASE_IDX
+ mmDPid_DP_VID_N, .DP_VID_STREAM_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX
+ mmDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING = DMU_BASE__INST0_SEGmmDPid_DP_VID_TIMING_BASE_IDX
+ mmDPid_DP_VID_TIMING, .DP_SEC_AUD_N = DMU_BASE__INST0_SEGmmDPid_DP_SEC_AUD_N_BASE_IDX
+ mmDPid_DP_SEC_AUD_N, .DP_SEC_AUD_N_READBACK = DMU_BASE__INST0_SEGmmDPid_DP_SEC_AUD_N_READBACK_BASE_IDX
+ mmDPid_DP_SEC_AUD_N_READBACK, .DP_SEC_AUD_M_READBACK = DMU_BASE__INST0_SEGmmDPid_DP_SEC_AUD_M_READBACK_BASE_IDX
+ mmDPid_DP_SEC_AUD_M_READBACK, .DP_SEC_TIMESTAMP = DMU_BASE__INST0_SEGmmDPid_DP_SEC_TIMESTAMP_BASE_IDX
+ mmDPid_DP_SEC_TIMESTAMP, .DIG_CLOCK_PATTERN = DMU_BASE__INST0_SEGmmDIGid_DIG_CLOCK_PATTERN_BASE_IDX
+ mmDIGid_DIG_CLOCK_PATTERN, .HDMI_GENERIC_PACKET_CONTROL4 =
DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL4, .HDMI_GENERIC_PACKET_CONTROL5
= DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL5, .DP_DSC_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DSC_CNTL_BASE_IDX
+ mmDPid_DP_DSC_CNTL, .DP_DSC_BYTES_PER_PIXEL = DMU_BASE__INST0_SEGmmDPid_DP_DSC_BYTES_PER_PIXEL_BASE_IDX
+ mmDPid_DP_DSC_BYTES_PER_PIXEL, .DME_CONTROL = DMU_BASE__INST0_SEGmmDIGid_DME_CONTROL_BASE_IDX
+ mmDIGid_DME_CONTROL, .DP_SEC_METADATA_TRANSMISSION = DMU_BASE__INST0_SEGmmDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX
+ mmDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_METADATA_PACKET_CONTROL, .DP_SEC_FRAMING4 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_FRAMING4_BASE_IDX
+ mmDPid_DP_SEC_FRAMING4}\
347[id] = {\
348 SE_DCN2_REG_LIST(id).AFMT_CNTL = DMU_BASE__INST0_SEGmmDIGid_AFMT_CNTL_BASE_IDX + mmDIGid_AFMT_CNTL
, .AFMT_GENERIC_0 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_0_BASE_IDX
+ mmDIGid_AFMT_GENERIC_0, .AFMT_GENERIC_1 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_1_BASE_IDX
+ mmDIGid_AFMT_GENERIC_1, .AFMT_GENERIC_2 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_2_BASE_IDX
+ mmDIGid_AFMT_GENERIC_2, .AFMT_GENERIC_3 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_3_BASE_IDX
+ mmDIGid_AFMT_GENERIC_3, .AFMT_GENERIC_4 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_4_BASE_IDX
+ mmDIGid_AFMT_GENERIC_4, .AFMT_GENERIC_5 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_5_BASE_IDX
+ mmDIGid_AFMT_GENERIC_5, .AFMT_GENERIC_6 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_6_BASE_IDX
+ mmDIGid_AFMT_GENERIC_6, .AFMT_GENERIC_7 = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_7_BASE_IDX
+ mmDIGid_AFMT_GENERIC_7, .AFMT_GENERIC_HDR = DMU_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_HDR_BASE_IDX
+ mmDIGid_AFMT_GENERIC_HDR, .AFMT_INFOFRAME_CONTROL0 = DMU_BASE__INST0_SEGmmDIGid_AFMT_INFOFRAME_CONTROL0_BASE_IDX
+ mmDIGid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL =
DMU_BASE__INST0_SEGmmDIGid_AFMT_VBI_PACKET_CONTROL_BASE_IDX +
mmDIGid_AFMT_VBI_PACKET_CONTROL, .AFMT_VBI_PACKET_CONTROL1 =
DMU_BASE__INST0_SEGmmDIGid_AFMT_VBI_PACKET_CONTROL1_BASE_IDX
+ mmDIGid_AFMT_VBI_PACKET_CONTROL1, .AFMT_AUDIO_PACKET_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX
+ mmDIGid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2
= DMU_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX
+ mmDIGid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX
+ mmDIGid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = DMU_BASE__INST0_SEGmmDIGid_AFMT_60958_0_BASE_IDX
+ mmDIGid_AFMT_60958_0, .AFMT_60958_1 = DMU_BASE__INST0_SEGmmDIGid_AFMT_60958_1_BASE_IDX
+ mmDIGid_AFMT_60958_1, .AFMT_60958_2 = DMU_BASE__INST0_SEGmmDIGid_AFMT_60958_2_BASE_IDX
+ mmDIGid_AFMT_60958_2, .DIG_FE_CNTL = DMU_BASE__INST0_SEGmmDIGid_DIG_FE_CNTL_BASE_IDX
+ mmDIGid_DIG_FE_CNTL, .DIG_FIFO_STATUS = DMU_BASE__INST0_SEGmmDIGid_DIG_FIFO_STATUS_BASE_IDX
+ mmDIGid_DIG_FIFO_STATUS, .HDMI_CONTROL = DMU_BASE__INST0_SEGmmDIGid_HDMI_CONTROL_BASE_IDX
+ mmDIGid_HDMI_CONTROL, .HDMI_DB_CONTROL = DMU_BASE__INST0_SEGmmDIGid_HDMI_DB_CONTROL_BASE_IDX
+ mmDIGid_HDMI_DB_CONTROL, .HDMI_GC = DMU_BASE__INST0_SEGmmDIGid_HDMI_GC_BASE_IDX
+ mmDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 = DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1
= DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_GENERIC_PACKET_CONTROL2
= DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL2, .HDMI_GENERIC_PACKET_CONTROL3
= DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL3, .HDMI_INFOFRAME_CONTROL0
= DMU_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX
+ mmDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 =
DMU_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX +
mmDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = DMU_BASE__INST0_SEGmmDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_0_BASE_IDX
+ mmDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_1_BASE_IDX
+ mmDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_0_BASE_IDX
+ mmDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_1_BASE_IDX
+ mmDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_0_BASE_IDX
+ mmDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = DMU_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_1_BASE_IDX
+ mmDIGid_HDMI_ACR_48_1, .DP_DB_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DB_CNTL_BASE_IDX
+ mmDPid_DP_DB_CNTL, .DP_MSA_MISC = DMU_BASE__INST0_SEGmmDPid_DP_MSA_MISC_BASE_IDX
+ mmDPid_DP_MSA_MISC, .DP_MSA_VBID_MISC = DMU_BASE__INST0_SEGmmDPid_DP_MSA_VBID_MISC_BASE_IDX
+ mmDPid_DP_MSA_VBID_MISC, .DP_MSA_COLORIMETRY = DMU_BASE__INST0_SEGmmDPid_DP_MSA_COLORIMETRY_BASE_IDX
+ mmDPid_DP_MSA_COLORIMETRY, .DP_MSA_TIMING_PARAM1 = DMU_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM1_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM1, .DP_MSA_TIMING_PARAM2 = DMU_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM2_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM2, .DP_MSA_TIMING_PARAM3 = DMU_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM3_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM3, .DP_MSA_TIMING_PARAM4 = DMU_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM4_BASE_IDX
+ mmDPid_DP_MSA_TIMING_PARAM4, .DP_MSE_RATE_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_MSE_RATE_CNTL_BASE_IDX
+ mmDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE = DMU_BASE__INST0_SEGmmDPid_DP_MSE_RATE_UPDATE_BASE_IDX
+ mmDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = DMU_BASE__INST0_SEGmmDPid_DP_PIXEL_FORMAT_BASE_IDX
+ mmDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX
+ mmDPid_DP_SEC_CNTL, .DP_SEC_CNTL1 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL1_BASE_IDX
+ mmDPid_DP_SEC_CNTL1, .DP_SEC_CNTL2 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL2_BASE_IDX
+ mmDPid_DP_SEC_CNTL2, .DP_SEC_CNTL5 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL5_BASE_IDX
+ mmDPid_DP_SEC_CNTL5, .DP_SEC_CNTL6 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL6_BASE_IDX
+ mmDPid_DP_SEC_CNTL6, .DP_STEER_FIFO = DMU_BASE__INST0_SEGmmDPid_DP_STEER_FIFO_BASE_IDX
+ mmDPid_DP_STEER_FIFO, .DP_VID_M = DMU_BASE__INST0_SEGmmDPid_DP_VID_M_BASE_IDX
+ mmDPid_DP_VID_M, .DP_VID_N = DMU_BASE__INST0_SEGmmDPid_DP_VID_N_BASE_IDX
+ mmDPid_DP_VID_N, .DP_VID_STREAM_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX
+ mmDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING = DMU_BASE__INST0_SEGmmDPid_DP_VID_TIMING_BASE_IDX
+ mmDPid_DP_VID_TIMING, .DP_SEC_AUD_N = DMU_BASE__INST0_SEGmmDPid_DP_SEC_AUD_N_BASE_IDX
+ mmDPid_DP_SEC_AUD_N, .DP_SEC_AUD_N_READBACK = DMU_BASE__INST0_SEGmmDPid_DP_SEC_AUD_N_READBACK_BASE_IDX
+ mmDPid_DP_SEC_AUD_N_READBACK, .DP_SEC_AUD_M_READBACK = DMU_BASE__INST0_SEGmmDPid_DP_SEC_AUD_M_READBACK_BASE_IDX
+ mmDPid_DP_SEC_AUD_M_READBACK, .DP_SEC_TIMESTAMP = DMU_BASE__INST0_SEGmmDPid_DP_SEC_TIMESTAMP_BASE_IDX
+ mmDPid_DP_SEC_TIMESTAMP, .DIG_CLOCK_PATTERN = DMU_BASE__INST0_SEGmmDIGid_DIG_CLOCK_PATTERN_BASE_IDX
+ mmDIGid_DIG_CLOCK_PATTERN, .HDMI_GENERIC_PACKET_CONTROL4 =
DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL4, .HDMI_GENERIC_PACKET_CONTROL5
= DMU_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX
+ mmDIGid_HDMI_GENERIC_PACKET_CONTROL5, .DP_DSC_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DSC_CNTL_BASE_IDX
+ mmDPid_DP_DSC_CNTL, .DP_DSC_BYTES_PER_PIXEL = DMU_BASE__INST0_SEGmmDPid_DP_DSC_BYTES_PER_PIXEL_BASE_IDX
+ mmDPid_DP_DSC_BYTES_PER_PIXEL, .DME_CONTROL = DMU_BASE__INST0_SEGmmDIGid_DME_CONTROL_BASE_IDX
+ mmDIGid_DME_CONTROL, .DP_SEC_METADATA_TRANSMISSION = DMU_BASE__INST0_SEGmmDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX
+ mmDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL
= DMU_BASE__INST0_SEGmmDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX
+ mmDIGid_HDMI_METADATA_PACKET_CONTROL, .DP_SEC_FRAMING4 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_FRAMING4_BASE_IDX
+ mmDPid_DP_SEC_FRAMING4\
349}
350
351static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
352 stream_enc_regs(0)[0] = { .AFMT_CNTL = 0x000034C0 + 0x20e6, .AFMT_GENERIC_0 = 0x000034C0
+ 0x208d, .AFMT_GENERIC_1 = 0x000034C0 + 0x208e, .AFMT_GENERIC_2
= 0x000034C0 + 0x208f, .AFMT_GENERIC_3 = 0x000034C0 + 0x2090
, .AFMT_GENERIC_4 = 0x000034C0 + 0x2091, .AFMT_GENERIC_5 = 0x000034C0
+ 0x2092, .AFMT_GENERIC_6 = 0x000034C0 + 0x2093, .AFMT_GENERIC_7
= 0x000034C0 + 0x2094, .AFMT_GENERIC_HDR = 0x000034C0 + 0x208c
, .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x20ac, .AFMT_VBI_PACKET_CONTROL
= 0x000034C0 + 0x20ab, .AFMT_VBI_PACKET_CONTROL1 = 0x000034C0
+ 0x20e7, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x20aa, .
AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x207c, .AFMT_AUDIO_SRC_CONTROL
= 0x000034C0 + 0x20ad, .AFMT_60958_0 = 0x000034C0 + 0x20a0, .
AFMT_60958_1 = 0x000034C0 + 0x20a1, .AFMT_60958_2 = 0x000034C0
+ 0x20a7, .DIG_FE_CNTL = 0x000034C0 + 0x2068, .DIG_FIFO_STATUS
= 0x000034C0 + 0x206e, .HDMI_CONTROL = 0x000034C0 + 0x2071, .
HDMI_DB_CONTROL = 0x000034C0 + 0x2088, .HDMI_GC = 0x000034C0 +
0x207b, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x2078,
.HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x2095, .HDMI_GENERIC_PACKET_CONTROL2
= 0x000034C0 + 0x2086, .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0
+ 0x2087, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2076, .HDMI_INFOFRAME_CONTROL1
= 0x000034C0 + 0x2077, .HDMI_VBI_PACKET_CONTROL = 0x000034C0
+ 0x2075, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2073, .
HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2074, .HDMI_ACR_32_0
= 0x000034C0 + 0x2096, .HDMI_ACR_32_1 = 0x000034C0 + 0x2097,
.HDMI_ACR_44_0 = 0x000034C0 + 0x2098, .HDMI_ACR_44_1 = 0x000034C0
+ 0x2099, .HDMI_ACR_48_0 = 0x000034C0 + 0x209a, .HDMI_ACR_48_1
= 0x000034C0 + 0x209b, .DP_DB_CNTL = 0x000034C0 + 0x2159, .DP_MSA_MISC
= 0x000034C0 + 0x210e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x215a
, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x210a, .DP_MSA_TIMING_PARAM1
= 0x000034C0 + 0x214c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x214d
, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x214e, .DP_MSA_TIMING_PARAM4
= 0x000034C0 + 0x214f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2137
, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2139, .DP_PIXEL_FORMAT
= 0x000034C0 + 0x2109, .DP_SEC_CNTL = 0x000034C0 + 0x212b, .
DP_SEC_CNTL1 = 0x000034C0 + 0x212c, .DP_SEC_CNTL2 = 0x000034C0
+ 0x2153, .DP_SEC_CNTL5 = 0x000034C0 + 0x2156, .DP_SEC_CNTL6
= 0x000034C0 + 0x2157, .DP_STEER_FIFO = 0x000034C0 + 0x210d,
.DP_VID_M = 0x000034C0 + 0x2112, .DP_VID_N = 0x000034C0 + 0x2111
, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x210c, .DP_VID_TIMING =
0x000034C0 + 0x2110, .DP_SEC_AUD_N = 0x000034C0 + 0x2131, .DP_SEC_AUD_N_READBACK
= 0x000034C0 + 0x2132, .DP_SEC_AUD_M_READBACK = 0x000034C0 +
0x2134, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2135, .DIG_CLOCK_PATTERN
= 0x000034C0 + 0x206b, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0
+ 0x2070, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x20f6
, .DP_DSC_CNTL = 0x000034C0 + 0x2152, .DP_DSC_BYTES_PER_PIXEL
= 0x000034C0 + 0x215c, .DME_CONTROL = 0x000034C0 + 0x2089, .
DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x215b, .HDMI_METADATA_PACKET_CONTROL
= 0x000034C0 + 0x206f, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2130
},
353 stream_enc_regs(1)[1] = { .AFMT_CNTL = 0x000034C0 + 0x21e6, .AFMT_GENERIC_0 = 0x000034C0
+ 0x218d, .AFMT_GENERIC_1 = 0x000034C0 + 0x218e, .AFMT_GENERIC_2
= 0x000034C0 + 0x218f, .AFMT_GENERIC_3 = 0x000034C0 + 0x2190
, .AFMT_GENERIC_4 = 0x000034C0 + 0x2191, .AFMT_GENERIC_5 = 0x000034C0
+ 0x2192, .AFMT_GENERIC_6 = 0x000034C0 + 0x2193, .AFMT_GENERIC_7
= 0x000034C0 + 0x2194, .AFMT_GENERIC_HDR = 0x000034C0 + 0x218c
, .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x21ac, .AFMT_VBI_PACKET_CONTROL
= 0x000034C0 + 0x21ab, .AFMT_VBI_PACKET_CONTROL1 = 0x000034C0
+ 0x21e7, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x21aa, .
AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x217c, .AFMT_AUDIO_SRC_CONTROL
= 0x000034C0 + 0x21ad, .AFMT_60958_0 = 0x000034C0 + 0x21a0, .
AFMT_60958_1 = 0x000034C0 + 0x21a1, .AFMT_60958_2 = 0x000034C0
+ 0x21a7, .DIG_FE_CNTL = 0x000034C0 + 0x2168, .DIG_FIFO_STATUS
= 0x000034C0 + 0x216e, .HDMI_CONTROL = 0x000034C0 + 0x2171, .
HDMI_DB_CONTROL = 0x000034C0 + 0x2188, .HDMI_GC = 0x000034C0 +
0x217b, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x2178,
.HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x2195, .HDMI_GENERIC_PACKET_CONTROL2
= 0x000034C0 + 0x2186, .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0
+ 0x2187, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2176, .HDMI_INFOFRAME_CONTROL1
= 0x000034C0 + 0x2177, .HDMI_VBI_PACKET_CONTROL = 0x000034C0
+ 0x2175, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2173, .
HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2174, .HDMI_ACR_32_0
= 0x000034C0 + 0x2196, .HDMI_ACR_32_1 = 0x000034C0 + 0x2197,
.HDMI_ACR_44_0 = 0x000034C0 + 0x2198, .HDMI_ACR_44_1 = 0x000034C0
+ 0x2199, .HDMI_ACR_48_0 = 0x000034C0 + 0x219a, .HDMI_ACR_48_1
= 0x000034C0 + 0x219b, .DP_DB_CNTL = 0x000034C0 + 0x2259, .DP_MSA_MISC
= 0x000034C0 + 0x220e, .DP_MSA_VBID_MISC = 0x000034C0 + 0x225a
, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x220a, .DP_MSA_TIMING_PARAM1
= 0x000034C0 + 0x224c, .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x224d
, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x224e, .DP_MSA_TIMING_PARAM4
= 0x000034C0 + 0x224f, .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2237
, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2239, .DP_PIXEL_FORMAT
= 0x000034C0 + 0x2209, .DP_SEC_CNTL = 0x000034C0 + 0x222b, .
DP_SEC_CNTL1 = 0x000034C0 + 0x222c, .DP_SEC_CNTL2 = 0x000034C0
+ 0x2253, .DP_SEC_CNTL5 = 0x000034C0 + 0x2256, .DP_SEC_CNTL6
= 0x000034C0 + 0x2257, .DP_STEER_FIFO = 0x000034C0 + 0x220d,
.DP_VID_M = 0x000034C0 + 0x2212, .DP_VID_N = 0x000034C0 + 0x2211
, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x220c, .DP_VID_TIMING =
0x000034C0 + 0x2210, .DP_SEC_AUD_N = 0x000034C0 + 0x2231, .DP_SEC_AUD_N_READBACK
= 0x000034C0 + 0x2232, .DP_SEC_AUD_M_READBACK = 0x000034C0 +
0x2234, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2235, .DIG_CLOCK_PATTERN
= 0x000034C0 + 0x216b, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0
+ 0x2170, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x21f6
, .DP_DSC_CNTL = 0x000034C0 + 0x2252, .DP_DSC_BYTES_PER_PIXEL
= 0x000034C0 + 0x225c, .DME_CONTROL = 0x000034C0 + 0x2189, .
DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x225b, .HDMI_METADATA_PACKET_CONTROL
= 0x000034C0 + 0x216f, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2230
}
354};
355
356static const struct dcn10_stream_encoder_shift se_shift = {
357 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT).AFMT_GENERIC_INDEX = 0x1c, .AFMT_GENERIC_HB0 = 0x0, .AFMT_GENERIC_HB1
= 0x8, .AFMT_GENERIC_HB2 = 0x10, .AFMT_GENERIC_HB3 = 0x18, .
DP_PIXEL_ENCODING = 0x0, .DP_COMPONENT_DEPTH = 0x18, .HDMI_PACKET_GEN_VERSION
= 0x4, .HDMI_KEEPOUT_MODE = 0x0, .HDMI_DEEP_COLOR_ENABLE = 0x18
, .HDMI_DEEP_COLOR_DEPTH = 0x1c, .HDMI_DATA_SCRAMBLE_EN = 0x1
, .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x3, .HDMI_GC_CONT = 0x5
, .HDMI_GC_SEND = 0x4, .HDMI_NULL_SEND = 0x0, .HDMI_ACP_SEND =
0xc, .HDMI_AUDIO_INFO_SEND = 0x4, .AFMT_AUDIO_INFO_UPDATE = 0x7
, .HDMI_AUDIO_INFO_LINE = 0x8, .HDMI_GC_AVMUTE = 0x0, .DP_MSE_RATE_X
= 0x1a, .DP_MSE_RATE_Y = 0x0, .DP_MSE_RATE_UPDATE_PENDING = 0x0
, .DP_SEC_GSP0_ENABLE = 0x14, .DP_SEC_STREAM_ENABLE = 0x0, .DP_SEC_GSP1_ENABLE
= 0x15, .DP_SEC_GSP2_ENABLE = 0x16, .DP_SEC_GSP3_ENABLE = 0x17
, .DP_SEC_MPG_ENABLE = 0x1c, .DP_SEC_GSP4_SEND = 0xc, .DP_SEC_GSP4_SEND_PENDING
= 0xd, .DP_SEC_GSP4_LINE_NUM = 0x10, .DP_SEC_GSP4_SEND_ANY_LINE
= 0xf, .DP_VID_STREAM_DIS_DEFER = 0x8, .DP_VID_STREAM_ENABLE
= 0x0, .DP_VID_STREAM_STATUS = 0x10, .DP_STEER_FIFO_RESET = 0x0
, .DP_VID_M_N_GEN_EN = 0x8, .DP_VID_N = 0x0, .DP_VID_M = 0x0,
.DIG_START = 0xa, .AFMT_AUDIO_SRC_SELECT = 0x0, .AFMT_AUDIO_CHANNEL_ENABLE
= 0x8, .HDMI_AUDIO_PACKETS_PER_LINE = 0x10, .HDMI_AUDIO_DELAY_EN
= 0x4, .AFMT_60958_CS_UPDATE = 0x1a, .AFMT_AUDIO_LAYOUT_OVRD
= 0x0, .AFMT_60958_OSF_OVRD = 0x1c, .HDMI_ACR_AUTO_SEND = 0xc
, .HDMI_ACR_SOURCE = 0x8, .HDMI_ACR_AUDIO_PRIORITY = 0x1f, .HDMI_ACR_CTS_32
= 0xc, .HDMI_ACR_N_32 = 0x0, .HDMI_ACR_CTS_44 = 0xc, .HDMI_ACR_N_44
= 0x0, .HDMI_ACR_CTS_48 = 0xc, .HDMI_ACR_N_48 = 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_L
= 0x14, .AFMT_60958_CS_CLOCK_ACCURACY = 0x1c, .AFMT_60958_CS_CHANNEL_NUMBER_R
= 0x14, .AFMT_60958_CS_CHANNEL_NUMBER_2 = 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_3
= 0x4, .AFMT_60958_CS_CHANNEL_NUMBER_4 = 0x8, .AFMT_60958_CS_CHANNEL_NUMBER_5
= 0xc, .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x10, .AFMT_60958_CS_CHANNEL_NUMBER_7
= 0x14, .DP_SEC_AUD_N = 0x0, .DP_SEC_AUD_N_READBACK = 0x0, .
DP_SEC_AUD_M_READBACK = 0x0, .DP_SEC_TIMESTAMP_MODE = 0x0, .DP_SEC_ASP_ENABLE
= 0x4, .DP_SEC_ATP_ENABLE = 0x8, .DP_SEC_AIP_ENABLE = 0xc, .
DP_SEC_ACM_ENABLE = 0x10, .AFMT_AUDIO_SAMPLE_SEND = 0x0, .AFMT_AUDIO_CLOCK_EN
= 0x0, .HDMI_CLOCK_CHANNEL_RATE = 0x2, .TMDS_PIXEL_ENCODING =
0x1c, .TMDS_COLOR_FORMAT = 0x1e, .DIG_STEREOSYNC_SELECT = 0x4
, .DIG_STEREOSYNC_GATE_EN = 0x8, .DIG_FIFO_LEVEL_ERROR = 0x0,
.DIG_FIFO_USE_OVERWRITE_LEVEL = 0x1, .DIG_FIFO_OVERWRITE_LEVEL
= 0x2, .DIG_FIFO_ERROR_ACK = 0x8, .DIG_FIFO_CAL_AVERAGE_LEVEL
= 0xa, .DIG_FIFO_MAXIMUM_LEVEL = 0x10, .DIG_FIFO_MINIMUM_LEVEL
= 0x16, .DIG_FIFO_READ_CLOCK_SRC = 0x1a, .DIG_FIFO_CALIBRATED
= 0x1d, .DIG_FIFO_FORCE_RECAL_AVERAGE = 0x1e, .DIG_FIFO_FORCE_RECOMP_MINMAX
= 0x1f, .AFMT_GENERIC_LOCK_STATUS = 0x8, .AFMT_GENERIC_CONFLICT
= 0x10, .AFMT_GENERIC_CONFLICT_CLR = 0x11, .AFMT_GENERIC0_FRAME_UPDATE_PENDING
= 0x1, .AFMT_GENERIC1_FRAME_UPDATE_PENDING = 0x5, .AFMT_GENERIC2_FRAME_UPDATE_PENDING
= 0x9, .AFMT_GENERIC3_FRAME_UPDATE_PENDING = 0xd, .AFMT_GENERIC4_FRAME_UPDATE_PENDING
= 0x11, .AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING = 0x13, .AFMT_GENERIC5_FRAME_UPDATE_PENDING
= 0x15, .AFMT_GENERIC6_FRAME_UPDATE_PENDING = 0x19, .AFMT_GENERIC7_FRAME_UPDATE_PENDING
= 0x1d, .AFMT_GENERIC0_FRAME_UPDATE = 0x0, .AFMT_GENERIC1_FRAME_UPDATE
= 0x4, .AFMT_GENERIC2_FRAME_UPDATE = 0x8, .AFMT_GENERIC3_FRAME_UPDATE
= 0xc, .AFMT_GENERIC4_FRAME_UPDATE = 0x10, .AFMT_GENERIC0_IMMEDIATE_UPDATE
= 0x2, .AFMT_GENERIC1_IMMEDIATE_UPDATE = 0x6, .AFMT_GENERIC2_IMMEDIATE_UPDATE
= 0xa, .AFMT_GENERIC3_IMMEDIATE_UPDATE = 0xe, .AFMT_GENERIC4_IMMEDIATE_UPDATE
= 0x12, .AFMT_GENERIC5_IMMEDIATE_UPDATE = 0x16, .AFMT_GENERIC6_IMMEDIATE_UPDATE
= 0x1a, .AFMT_GENERIC7_IMMEDIATE_UPDATE = 0x1e, .AFMT_GENERIC5_FRAME_UPDATE
= 0x14, .AFMT_GENERIC6_FRAME_UPDATE = 0x18, .AFMT_GENERIC7_FRAME_UPDATE
= 0x1c, .DP_SEC_GSP4_ENABLE = 0x18, .DP_SEC_GSP5_ENABLE = 0x19
, .DP_SEC_GSP6_ENABLE = 0x1a, .DP_SEC_GSP7_ENABLE = 0x1b, .DP_SEC_GSP7_PPS
= 0x1c, .DP_SEC_GSP7_SEND = 0x18, .DP_SEC_GSP7_LINE_NUM = 0x0
, .DP_DB_DISABLE = 0xc, .DP_MSA_MISC0 = 0x18, .DP_MSA_HTOTAL =
0x10, .DP_MSA_VTOTAL = 0x0, .DP_MSA_HSTART = 0x10, .DP_MSA_VSTART
= 0x0, .DP_MSA_HSYNCWIDTH = 0x10, .DP_MSA_HSYNCPOLARITY = 0x1f
, .DP_MSA_VSYNCWIDTH = 0x0, .DP_MSA_VSYNCPOLARITY = 0xf, .DP_MSA_HWIDTH
= 0x10, .DP_MSA_VHEIGHT = 0x0, .HDMI_DB_DISABLE = 0xc, .DP_VID_N_MUL
= 0xa, .DIG_SOURCE_SELECT = 0x0, .DIG_CLOCK_PATTERN = 0x0, .
HDMI_GENERIC0_CONT = 0x1, .HDMI_GENERIC0_SEND = 0x0, .HDMI_GENERIC1_CONT
= 0x5, .HDMI_GENERIC1_SEND = 0x4, .HDMI_GENERIC2_CONT = 0x9,
.HDMI_GENERIC2_SEND = 0x8, .HDMI_GENERIC3_CONT = 0xd, .HDMI_GENERIC3_SEND
= 0xc, .HDMI_GENERIC4_CONT = 0x11, .HDMI_GENERIC4_SEND = 0x10
, .HDMI_GENERIC5_CONT = 0x15, .HDMI_GENERIC5_SEND = 0x14, .HDMI_GENERIC6_CONT
= 0x19, .HDMI_GENERIC6_SEND = 0x18, .HDMI_GENERIC7_CONT = 0x1d
, .HDMI_GENERIC7_SEND = 0x1c, .HDMI_GENERIC0_LINE = 0x0, .HDMI_GENERIC1_LINE
= 0x10, .HDMI_GENERIC2_LINE = 0x0, .HDMI_GENERIC3_LINE = 0x10
, .HDMI_GENERIC4_LINE = 0x0, .HDMI_GENERIC5_LINE = 0x10, .HDMI_GENERIC6_LINE
= 0x0, .HDMI_GENERIC7_LINE = 0x10, .DP_DSC_MODE = 0x0, .DP_DSC_SLICE_WIDTH
= 0x10, .DP_DSC_BYTES_PER_PIXEL = 0x0, .DP_VBID6_LINE_REFERENCE
= 0xf, .DP_VBID6_LINE_NUM = 0x10, .METADATA_ENGINE_EN = 0x4,
.METADATA_HUBP_REQUESTOR_ID = 0x0, .METADATA_STREAM_TYPE = 0x8
, .DP_SEC_METADATA_PACKET_ENABLE = 0x0, .DP_SEC_METADATA_PACKET_LINE_REFERENCE
= 0x1, .DP_SEC_METADATA_PACKET_LINE = 0x10, .HDMI_METADATA_PACKET_ENABLE
= 0x0, .HDMI_METADATA_PACKET_LINE_REFERENCE = 0x4, .HDMI_METADATA_PACKET_LINE
= 0x10, .DOLBY_VISION_EN = 0x12, .DP_PIXEL_COMBINE = 0x1c, .
DP_SEC_GSP5_LINE_REFERENCE = 0xd, .DP_SEC_GSP5_LINE_NUM = 0x0
, .DP_SST_SDP_SPLITTING = 0x0
358};
359
360static const struct dcn10_stream_encoder_mask se_mask = {
361 SE_COMMON_MASK_SH_LIST_DCN20(_MASK).AFMT_GENERIC_INDEX = 0xF0000000L, .AFMT_GENERIC_HB0 = 0x000000FFL
, .AFMT_GENERIC_HB1 = 0x0000FF00L, .AFMT_GENERIC_HB2 = 0x00FF0000L
, .AFMT_GENERIC_HB3 = 0xFF000000L, .DP_PIXEL_ENCODING = 0x00000007L
, .DP_COMPONENT_DEPTH = 0x07000000L, .HDMI_PACKET_GEN_VERSION
= 0x00000010L, .HDMI_KEEPOUT_MODE = 0x00000001L, .HDMI_DEEP_COLOR_ENABLE
= 0x01000000L, .HDMI_DEEP_COLOR_DEPTH = 0x30000000L, .HDMI_DATA_SCRAMBLE_EN
= 0x00000002L, .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x00000008L
, .HDMI_GC_CONT = 0x00000020L, .HDMI_GC_SEND = 0x00000010L, .
HDMI_NULL_SEND = 0x00000001L, .HDMI_ACP_SEND = 0x00001000L, .
HDMI_AUDIO_INFO_SEND = 0x00000010L, .AFMT_AUDIO_INFO_UPDATE =
0x00000080L, .HDMI_AUDIO_INFO_LINE = 0x00003F00L, .HDMI_GC_AVMUTE
= 0x00000001L, .DP_MSE_RATE_X = 0xFC000000L, .DP_MSE_RATE_Y =
0x03FFFFFFL, .DP_MSE_RATE_UPDATE_PENDING = 0x00000001L, .DP_SEC_GSP0_ENABLE
= 0x00100000L, .DP_SEC_STREAM_ENABLE = 0x00000001L, .DP_SEC_GSP1_ENABLE
= 0x00200000L, .DP_SEC_GSP2_ENABLE = 0x00400000L, .DP_SEC_GSP3_ENABLE
= 0x00800000L, .DP_SEC_MPG_ENABLE = 0x10000000L, .DP_SEC_GSP4_SEND
= 0x00001000L, .DP_SEC_GSP4_SEND_PENDING = 0x00002000L, .DP_SEC_GSP4_LINE_NUM
= 0xFFFF0000L, .DP_SEC_GSP4_SEND_ANY_LINE = 0x00008000L, .DP_VID_STREAM_DIS_DEFER
= 0x00000300L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_VID_STREAM_STATUS
= 0x00010000L, .DP_STEER_FIFO_RESET = 0x00000001L, .DP_VID_M_N_GEN_EN
= 0x00000100L, .DP_VID_N = 0x00FFFFFFL, .DP_VID_M = 0x00FFFFFFL
, .DIG_START = 0x00000400L, .AFMT_AUDIO_SRC_SELECT = 0x00000007L
, .AFMT_AUDIO_CHANNEL_ENABLE = 0x0000FF00L, .HDMI_AUDIO_PACKETS_PER_LINE
= 0x001F0000L, .HDMI_AUDIO_DELAY_EN = 0x00000030L, .AFMT_60958_CS_UPDATE
= 0x04000000L, .AFMT_AUDIO_LAYOUT_OVRD = 0x00000001L, .AFMT_60958_OSF_OVRD
= 0x10000000L, .HDMI_ACR_AUTO_SEND = 0x00001000L, .HDMI_ACR_SOURCE
= 0x00000100L, .HDMI_ACR_AUDIO_PRIORITY = 0x80000000L, .HDMI_ACR_CTS_32
= 0xFFFFF000L, .HDMI_ACR_N_32 = 0x000FFFFFL, .HDMI_ACR_CTS_44
= 0xFFFFF000L, .HDMI_ACR_N_44 = 0x000FFFFFL, .HDMI_ACR_CTS_48
= 0xFFFFF000L, .HDMI_ACR_N_48 = 0x000FFFFFL, .AFMT_60958_CS_CHANNEL_NUMBER_L
= 0x00F00000L, .AFMT_60958_CS_CLOCK_ACCURACY = 0x30000000L, .
AFMT_60958_CS_CHANNEL_NUMBER_R = 0x00F00000L, .AFMT_60958_CS_CHANNEL_NUMBER_2
= 0x0000000FL, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x000000F0L
, .AFMT_60958_CS_CHANNEL_NUMBER_4 = 0x00000F00L, .AFMT_60958_CS_CHANNEL_NUMBER_5
= 0x0000F000L, .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x000F0000L
, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x00F00000L, .DP_SEC_AUD_N
= 0x00FFFFFFL, .DP_SEC_AUD_N_READBACK = 0x00FFFFFFL, .DP_SEC_AUD_M_READBACK
= 0x00FFFFFFL, .DP_SEC_TIMESTAMP_MODE = 0x00000001L, .DP_SEC_ASP_ENABLE
= 0x00000010L, .DP_SEC_ATP_ENABLE = 0x00000100L, .DP_SEC_AIP_ENABLE
= 0x00001000L, .DP_SEC_ACM_ENABLE = 0x00010000L, .AFMT_AUDIO_SAMPLE_SEND
= 0x00000001L, .AFMT_AUDIO_CLOCK_EN = 0x00000001L, .HDMI_CLOCK_CHANNEL_RATE
= 0x00000004L, .TMDS_PIXEL_ENCODING = 0x10000000L, .TMDS_COLOR_FORMAT
= 0xC0000000L, .DIG_STEREOSYNC_SELECT = 0x00000070L, .DIG_STEREOSYNC_GATE_EN
= 0x00000100L, .DIG_FIFO_LEVEL_ERROR = 0x00000001L, .DIG_FIFO_USE_OVERWRITE_LEVEL
= 0x00000002L, .DIG_FIFO_OVERWRITE_LEVEL = 0x000000FCL, .DIG_FIFO_ERROR_ACK
= 0x00000100L, .DIG_FIFO_CAL_AVERAGE_LEVEL = 0x0000FC00L, .DIG_FIFO_MAXIMUM_LEVEL
= 0x001F0000L, .DIG_FIFO_MINIMUM_LEVEL = 0x03C00000L, .DIG_FIFO_READ_CLOCK_SRC
= 0x04000000L, .DIG_FIFO_CALIBRATED = 0x20000000L, .DIG_FIFO_FORCE_RECAL_AVERAGE
= 0x40000000L, .DIG_FIFO_FORCE_RECOMP_MINMAX = 0x80000000L, .
AFMT_GENERIC_LOCK_STATUS = 0x00000100L, .AFMT_GENERIC_CONFLICT
= 0x00010000L, .AFMT_GENERIC_CONFLICT_CLR = 0x00020000L, .AFMT_GENERIC0_FRAME_UPDATE_PENDING
= 0x00000002L, .AFMT_GENERIC1_FRAME_UPDATE_PENDING = 0x00000020L
, .AFMT_GENERIC2_FRAME_UPDATE_PENDING = 0x00000200L, .AFMT_GENERIC3_FRAME_UPDATE_PENDING
= 0x00002000L, .AFMT_GENERIC4_FRAME_UPDATE_PENDING = 0x00020000L
, .AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING = 0x00080000L, .AFMT_GENERIC5_FRAME_UPDATE_PENDING
= 0x00200000L, .AFMT_GENERIC6_FRAME_UPDATE_PENDING = 0x02000000L
, .AFMT_GENERIC7_FRAME_UPDATE_PENDING = 0x20000000L, .AFMT_GENERIC0_FRAME_UPDATE
= 0x00000001L, .AFMT_GENERIC1_FRAME_UPDATE = 0x00000010L, .AFMT_GENERIC2_FRAME_UPDATE
= 0x00000100L, .AFMT_GENERIC3_FRAME_UPDATE = 0x00001000L, .AFMT_GENERIC4_FRAME_UPDATE
= 0x00010000L, .AFMT_GENERIC0_IMMEDIATE_UPDATE = 0x00000004L
, .AFMT_GENERIC1_IMMEDIATE_UPDATE = 0x00000040L, .AFMT_GENERIC2_IMMEDIATE_UPDATE
= 0x00000400L, .AFMT_GENERIC3_IMMEDIATE_UPDATE = 0x00004000L
, .AFMT_GENERIC4_IMMEDIATE_UPDATE = 0x00040000L, .AFMT_GENERIC5_IMMEDIATE_UPDATE
= 0x00400000L, .AFMT_GENERIC6_IMMEDIATE_UPDATE = 0x04000000L
, .AFMT_GENERIC7_IMMEDIATE_UPDATE = 0x40000000L, .AFMT_GENERIC5_FRAME_UPDATE
= 0x00100000L, .AFMT_GENERIC6_FRAME_UPDATE = 0x01000000L, .AFMT_GENERIC7_FRAME_UPDATE
= 0x10000000L, .DP_SEC_GSP4_ENABLE = 0x01000000L, .DP_SEC_GSP5_ENABLE
= 0x02000000L, .DP_SEC_GSP6_ENABLE = 0x04000000L, .DP_SEC_GSP7_ENABLE
= 0x08000000L, .DP_SEC_GSP7_PPS = 0x10000000L, .DP_SEC_GSP7_SEND
= 0x01000000L, .DP_SEC_GSP7_LINE_NUM = 0x0000FFFFL, .DP_DB_DISABLE
= 0x00001000L, .DP_MSA_MISC0 = 0xFF000000L, .DP_MSA_HTOTAL =
0xFFFF0000L, .DP_MSA_VTOTAL = 0x0000FFFFL, .DP_MSA_HSTART = 0xFFFF0000L
, .DP_MSA_VSTART = 0x0000FFFFL, .DP_MSA_HSYNCWIDTH = 0x7FFF0000L
, .DP_MSA_HSYNCPOLARITY = 0x80000000L, .DP_MSA_VSYNCWIDTH = 0x00007FFFL
, .DP_MSA_VSYNCPOLARITY = 0x00008000L, .DP_MSA_HWIDTH = 0xFFFF0000L
, .DP_MSA_VHEIGHT = 0x0000FFFFL, .HDMI_DB_DISABLE = 0x00001000L
, .DP_VID_N_MUL = 0x00000C00L, .DIG_SOURCE_SELECT = 0x00000007L
, .DIG_CLOCK_PATTERN = 0x000003FFL, .HDMI_GENERIC0_CONT = 0x00000002L
, .HDMI_GENERIC0_SEND = 0x00000001L, .HDMI_GENERIC1_CONT = 0x00000020L
, .HDMI_GENERIC1_SEND = 0x00000010L, .HDMI_GENERIC2_CONT = 0x00000200L
, .HDMI_GENERIC2_SEND = 0x00000100L, .HDMI_GENERIC3_CONT = 0x00002000L
, .HDMI_GENERIC3_SEND = 0x00001000L, .HDMI_GENERIC4_CONT = 0x00020000L
, .HDMI_GENERIC4_SEND = 0x00010000L, .HDMI_GENERIC5_CONT = 0x00200000L
, .HDMI_GENERIC5_SEND = 0x00100000L, .HDMI_GENERIC6_CONT = 0x02000000L
, .HDMI_GENERIC6_SEND = 0x01000000L, .HDMI_GENERIC7_CONT = 0x20000000L
, .HDMI_GENERIC7_SEND = 0x10000000L, .HDMI_GENERIC0_LINE = 0x0000FFFFL
, .HDMI_GENERIC1_LINE = 0xFFFF0000L, .HDMI_GENERIC2_LINE = 0x0000FFFFL
, .HDMI_GENERIC3_LINE = 0xFFFF0000L, .HDMI_GENERIC4_LINE = 0x0000FFFFL
, .HDMI_GENERIC5_LINE = 0xFFFF0000L, .HDMI_GENERIC6_LINE = 0x0000FFFFL
, .HDMI_GENERIC7_LINE = 0xFFFF0000L, .DP_DSC_MODE = 0x00000003L
, .DP_DSC_SLICE_WIDTH = 0x1FFF0000L, .DP_DSC_BYTES_PER_PIXEL =
0x7FFFFFFFL, .DP_VBID6_LINE_REFERENCE = 0x00008000L, .DP_VBID6_LINE_NUM
= 0xFFFF0000L, .METADATA_ENGINE_EN = 0x00000010L, .METADATA_HUBP_REQUESTOR_ID
= 0x00000007L, .METADATA_STREAM_TYPE = 0x00000100L, .DP_SEC_METADATA_PACKET_ENABLE
= 0x00000001L, .DP_SEC_METADATA_PACKET_LINE_REFERENCE = 0x00000002L
, .DP_SEC_METADATA_PACKET_LINE = 0xFFFF0000L, .HDMI_METADATA_PACKET_ENABLE
= 0x00000001L, .HDMI_METADATA_PACKET_LINE_REFERENCE = 0x00000010L
, .HDMI_METADATA_PACKET_LINE = 0xFFFF0000L, .DOLBY_VISION_EN =
0x00040000L, .DP_PIXEL_COMBINE = 0x30000000L, .DP_SEC_GSP5_LINE_REFERENCE
= 0x00002000L, .DP_SEC_GSP5_LINE_NUM = 0x0000FFFFL, .DP_SST_SDP_SPLITTING
= 0x00000001L
362};
363
364static const struct dce110_aux_registers_shift aux_shift = {
365 DCN_AUX_MASK_SH_LIST(__SHIFT).AUX_EN = 0x0, .AUX_RESET = 0x4, .AUX_RESET_DONE = 0x5, .AUX_REG_RW_CNTL_STATUS
= 0x2, .AUX_SW_USE_AUX_REG_REQ = 0x10, .AUX_SW_DONE_USING_AUX_REG
= 0x11, .AUX_SW_START_DELAY = 0x4, .AUX_SW_WR_BYTES = 0x10, .
AUX_SW_GO = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_DATA_RW
= 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_INDEX =
0x10, .AUX_SW_DATA = 0x8, .AUX_SW_REPLY_BYTE_COUNT = 0x18, .
AUX_SW_DONE = 0x0, .AUX_SW_DONE_ACK = 0x1, .AUX_RX_TIMEOUT_LEN
= 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf
366};
367
368static const struct dce110_aux_registers_mask aux_mask = {
369 DCN_AUX_MASK_SH_LIST(_MASK).AUX_EN = 0x00000001L, .AUX_RESET = 0x00000010L, .AUX_RESET_DONE
= 0x00000020L, .AUX_REG_RW_CNTL_STATUS = 0x0000000CL, .AUX_SW_USE_AUX_REG_REQ
= 0x00010000L, .AUX_SW_DONE_USING_AUX_REG = 0x00020000L, .AUX_SW_START_DELAY
= 0x000000F0L, .AUX_SW_WR_BYTES = 0x001F0000L, .AUX_SW_GO = 0x00000001L
, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, .AUX_SW_DATA_RW
= 0x00000001L, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, .
AUX_SW_INDEX = 0x001F0000L, .AUX_SW_DATA = 0x0000FF00L, .AUX_SW_REPLY_BYTE_COUNT
= 0x1F000000L, .AUX_SW_DONE = 0x00000001L, .AUX_SW_DONE_ACK =
0x00000002L, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL
= 0x00018000L
370};
371
372#define aux_regs(id)[id] = { .AUX_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_DPHY_TX_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_TX_CONTROL}\
373[id] = {\
374 DCN2_AUX_REG_LIST(id).AUX_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_DPHY_TX_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_TX_CONTROL\
375}
376
377static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
378 aux_regs(0)[0] = { .AUX_CONTROL = 0x000034C0 + 0x1f50, .AUX_DPHY_RX_CONTROL0
= 0x000034C0 + 0x1f5a, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f5b
, .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f59},
379 aux_regs(1)[1] = { .AUX_CONTROL = 0x000034C0 + 0x1f6c, .AUX_DPHY_RX_CONTROL0
= 0x000034C0 + 0x1f76, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f77
, .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f75},
380};
381
382#define hpd_regs(id)[id] = { .DC_HPD_CONTROL = DMU_BASE__INST0_SEGmmHPDid_DC_HPD_CONTROL_BASE_IDX
+ mmHPDid_DC_HPD_CONTROL}\
383[id] = {\
384 HPD_REG_LIST(id).DC_HPD_CONTROL = DMU_BASE__INST0_SEGmmHPDid_DC_HPD_CONTROL_BASE_IDX
+ mmHPDid_DC_HPD_CONTROL\
385}
386
387static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
388 hpd_regs(0)[0] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f16},
389 hpd_regs(1)[1] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f1e},
390};
391
392#define link_regs(id, phyid)[id] = { .DIG_BE_CNTL = DMU_BASE__INST0_SEGmmDIGid_DIG_BE_CNTL_BASE_IDX
+ mmDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = DMU_BASE__INST0_SEGmmDIGid_DIG_BE_EN_CNTL_BASE_IDX
+ mmDIGid_DIG_BE_EN_CNTL, .DIG_CLOCK_PATTERN = DMU_BASE__INST0_SEGmmDIGid_DIG_CLOCK_PATTERN_BASE_IDX
+ mmDIGid_DIG_CLOCK_PATTERN, .TMDS_CTL_BITS = DMU_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX
+ mmDIGid_TMDS_CTL_BITS, .DP_CONFIG = DMU_BASE__INST0_SEGmmDPid_DP_CONFIG_BASE_IDX
+ mmDPid_DP_CONFIG, .DP_DPHY_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_PRBS_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_SYM0_BASE_IDX
+ mmDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_SYM1_BASE_IDX
+ mmDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_SYM2_BASE_IDX
+ mmDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX
+ mmDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_LINK_CNTL_BASE_IDX
+ mmDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_LINK_FRAMING_CNTL_BASE_IDX
+ mmDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = DMU_BASE__INST0_SEGmmDPid_DP_MSE_SAT0_BASE_IDX
+ mmDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = DMU_BASE__INST0_SEGmmDPid_DP_MSE_SAT1_BASE_IDX
+ mmDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = DMU_BASE__INST0_SEGmmDPid_DP_MSE_SAT2_BASE_IDX
+ mmDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = DMU_BASE__INST0_SEGmmDPid_DP_MSE_SAT_UPDATE_BASE_IDX
+ mmDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX
+ mmDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX
+ mmDPid_DP_VID_STREAM_CNTL, .DP_DPHY_FAST_TRAINING = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_FAST_TRAINING_BASE_IDX
+ mmDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL1_BASE_IDX
+ mmDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_BS_SR_SWAP_CNTL, .DP_DPHY_HBR2_PATTERN_CONTROL
= DMU_BASE__INST0_SEGmmDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX
+ mmDPid_DP_DPHY_HBR2_PATTERN_CONTROL, .CLOCK_ENABLE = DMU_BASE__INST0_SEGmmSYMCLKphyid_CLOCK_ENABLE_BASE_IDX
+ mmSYMCLKphyid_CLOCK_ENABLE, .CHANNEL_XBAR_CNTL = DMU_BASE__INST0_SEGmmUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX
+ mmUNIPHYphyid_CHANNEL_XBAR_CNTL }\
393[id] = {\
394 LE_DCN_COMMON_REG_LIST(id).DIG_BE_CNTL = DMU_BASE__INST0_SEGmmDIGid_DIG_BE_CNTL_BASE_IDX
+ mmDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = DMU_BASE__INST0_SEGmmDIGid_DIG_BE_EN_CNTL_BASE_IDX
+ mmDIGid_DIG_BE_EN_CNTL, .DIG_CLOCK_PATTERN = DMU_BASE__INST0_SEGmmDIGid_DIG_CLOCK_PATTERN_BASE_IDX
+ mmDIGid_DIG_CLOCK_PATTERN, .TMDS_CTL_BITS = DMU_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX
+ mmDIGid_TMDS_CTL_BITS, .DP_CONFIG = DMU_BASE__INST0_SEGmmDPid_DP_CONFIG_BASE_IDX
+ mmDPid_DP_CONFIG, .DP_DPHY_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_PRBS_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_SYM0_BASE_IDX
+ mmDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_SYM1_BASE_IDX
+ mmDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_SYM2_BASE_IDX
+ mmDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX
+ mmDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_LINK_CNTL_BASE_IDX
+ mmDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_LINK_FRAMING_CNTL_BASE_IDX
+ mmDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = DMU_BASE__INST0_SEGmmDPid_DP_MSE_SAT0_BASE_IDX
+ mmDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = DMU_BASE__INST0_SEGmmDPid_DP_MSE_SAT1_BASE_IDX
+ mmDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = DMU_BASE__INST0_SEGmmDPid_DP_MSE_SAT2_BASE_IDX
+ mmDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = DMU_BASE__INST0_SEGmmDPid_DP_MSE_SAT_UPDATE_BASE_IDX
+ mmDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX
+ mmDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX
+ mmDPid_DP_VID_STREAM_CNTL, .DP_DPHY_FAST_TRAINING = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_FAST_TRAINING_BASE_IDX
+ mmDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1 = DMU_BASE__INST0_SEGmmDPid_DP_SEC_CNTL1_BASE_IDX
+ mmDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = DMU_BASE__INST0_SEGmmDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX
+ mmDPid_DP_DPHY_BS_SR_SWAP_CNTL, .DP_DPHY_HBR2_PATTERN_CONTROL
= DMU_BASE__INST0_SEGmmDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX
+ mmDPid_DP_DPHY_HBR2_PATTERN_CONTROL, \
395 UNIPHY_DCN2_REG_LIST(phyid).CLOCK_ENABLE = DMU_BASE__INST0_SEGmmSYMCLKphyid_CLOCK_ENABLE_BASE_IDX
+ mmSYMCLKphyid_CLOCK_ENABLE, .CHANNEL_XBAR_CNTL = DMU_BASE__INST0_SEGmmUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX
+ mmUNIPHYphyid_CHANNEL_XBAR_CNTL \
396}
397
398static const struct dcn10_link_enc_registers link_enc_regs[] = {
399 link_regs(0, A)[0] = { .DIG_BE_CNTL = 0x000034C0 + 0x20af, .DIG_BE_EN_CNTL =
0x000034C0 + 0x20b0, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x206b
, .TMDS_CTL_BITS = 0x000034C0 + 0x20da, .DP_CONFIG = 0x000034C0
+ 0x210b, .DP_DPHY_CNTL = 0x000034C0 + 0x2117, .DP_DPHY_PRBS_CNTL
= 0x000034C0 + 0x211d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x211e
, .DP_DPHY_SYM0 = 0x000034C0 + 0x2119, .DP_DPHY_SYM1 = 0x000034C0
+ 0x211a, .DP_DPHY_SYM2 = 0x000034C0 + 0x211b, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x000034C0 + 0x2118, .DP_LINK_CNTL = 0x000034C0 + 0x2108, .
DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2113, .DP_MSE_SAT0 = 0x000034C0
+ 0x213a, .DP_MSE_SAT1 = 0x000034C0 + 0x213b, .DP_MSE_SAT2 =
0x000034C0 + 0x213c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x213d
, .DP_SEC_CNTL = 0x000034C0 + 0x212b, .DP_VID_STREAM_CNTL = 0x000034C0
+ 0x210c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2124, .DP_SEC_CNTL1
= 0x000034C0 + 0x212c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0
+ 0x2144, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2145
, .CLOCK_ENABLE = 0x000000C0 + 0x00a0, .CHANNEL_XBAR_CNTL = 0x000034C0
+ 0x286e },
400 link_regs(1, B)[1] = { .DIG_BE_CNTL = 0x000034C0 + 0x21af, .DIG_BE_EN_CNTL =
0x000034C0 + 0x21b0, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x216b
, .TMDS_CTL_BITS = 0x000034C0 + 0x21da, .DP_CONFIG = 0x000034C0
+ 0x220b, .DP_DPHY_CNTL = 0x000034C0 + 0x2217, .DP_DPHY_PRBS_CNTL
= 0x000034C0 + 0x221d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x221e
, .DP_DPHY_SYM0 = 0x000034C0 + 0x2219, .DP_DPHY_SYM1 = 0x000034C0
+ 0x221a, .DP_DPHY_SYM2 = 0x000034C0 + 0x221b, .DP_DPHY_TRAINING_PATTERN_SEL
= 0x000034C0 + 0x2218, .DP_LINK_CNTL = 0x000034C0 + 0x2208, .
DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2213, .DP_MSE_SAT0 = 0x000034C0
+ 0x223a, .DP_MSE_SAT1 = 0x000034C0 + 0x223b, .DP_MSE_SAT2 =
0x000034C0 + 0x223c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x223d
, .DP_SEC_CNTL = 0x000034C0 + 0x222b, .DP_VID_STREAM_CNTL = 0x000034C0
+ 0x220c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2224, .DP_SEC_CNTL1
= 0x000034C0 + 0x222c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0
+ 0x2244, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2245
, .CLOCK_ENABLE = 0x000000C0 + 0x00a1, .CHANNEL_XBAR_CNTL = 0x000034C0
+ 0x2870 },
401};
402
403#define LINK_ENCODER_MASK_SH_LIST_DCN201(mask_sh).DIG_ENABLE = DIG0_DIG_BE_EN_CNTL__DIG_ENABLEmask_sh, .DIG_HPD_SELECT
= DIG0_DIG_BE_CNTL__DIG_HPD_SELECTmask_sh, .DIG_MODE = DIG0_DIG_BE_CNTL__DIG_MODEmask_sh
, .DIG_FE_SOURCE_SELECT = DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECTmask_sh
, .DIG_CLOCK_PATTERN = DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERNmask_sh
, .TMDS_CTL0 = DIG0_TMDS_CTL_BITS__TMDS_CTL0mask_sh, .DPHY_BYPASS
= DP0_DP_DPHY_CNTL__DPHY_BYPASSmask_sh, .DPHY_ATEST_SEL_LANE0
= DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0mask_sh, .DPHY_ATEST_SEL_LANE1
= DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1mask_sh, .DPHY_ATEST_SEL_LANE2
= DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2mask_sh, .DPHY_ATEST_SEL_LANE3
= DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3mask_sh, .DPHY_PRBS_EN
= DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_ENmask_sh, .DPHY_PRBS_SEL
= DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SELmask_sh, .DPHY_SYM1 = DP0_DP_DPHY_SYM0__DPHY_SYM1mask_sh
, .DPHY_SYM2 = DP0_DP_DPHY_SYM0__DPHY_SYM2mask_sh, .DPHY_SYM3
= DP0_DP_DPHY_SYM0__DPHY_SYM3mask_sh, .DPHY_SYM4 = DP0_DP_DPHY_SYM1__DPHY_SYM4mask_sh
, .DPHY_SYM5 = DP0_DP_DPHY_SYM1__DPHY_SYM5mask_sh, .DPHY_SYM6
= DP0_DP_DPHY_SYM1__DPHY_SYM6mask_sh, .DPHY_SYM7 = DP0_DP_DPHY_SYM2__DPHY_SYM7mask_sh
, .DPHY_SYM8 = DP0_DP_DPHY_SYM2__DPHY_SYM8mask_sh, .DPHY_SCRAMBLER_BS_COUNT
= DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNTmask_sh, .DPHY_SCRAMBLER_ADVANCE
= DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCEmask_sh, .DPHY_RX_FAST_TRAINING_CAPABLE
= DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLEmask_sh
, .DPHY_LOAD_BS_COUNT = DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNTmask_sh
, .DPHY_TRAINING_PATTERN_SEL = DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SELmask_sh
, .DP_DPHY_HBR2_PATTERN_CONTROL = DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROLmask_sh
, .DP_LINK_TRAINING_COMPLETE = DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETEmask_sh
, .DP_IDLE_BS_INTERVAL = DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVALmask_sh
, .DP_VBID_DISABLE = DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLEmask_sh
, .DP_VID_ENHANCED_FRAME_MODE = DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODEmask_sh
, .DP_VID_STREAM_ENABLE = DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLEmask_sh
, .DP_UDI_LANES = DP0_DP_CONFIG__DP_UDI_LANESmask_sh, .DP_SEC_GSP0_LINE_NUM
= DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUMmask_sh, .DP_SEC_GSP0_PRIORITY
= DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITYmask_sh, .DP_MSE_SAT_SRC0
= DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0mask_sh, .DP_MSE_SAT_SRC1 =
DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1mask_sh, .DP_MSE_SAT_SLOT_COUNT0
= DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0mask_sh, .DP_MSE_SAT_SLOT_COUNT1
= DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1mask_sh, .DP_MSE_SAT_SRC2
= DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2mask_sh, .DP_MSE_SAT_SRC3 =
DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3mask_sh, .DP_MSE_SAT_SLOT_COUNT2
= DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2mask_sh, .DP_MSE_SAT_SLOT_COUNT3
= DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3mask_sh, .DP_MSE_SAT_UPDATE
= DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATEmask_sh, .DP_MSE_16_MTP_KEEPOUT
= DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUTmask_sh, .AUX_HPD_SEL
= DP_AUX0_AUX_CONTROL__AUX_HPD_SELmask_sh, .AUX_LS_READ_EN =
DP_AUX0_AUX_CONTROL__AUX_LS_READ_ENmask_sh, .AUX_RX_RECEIVE_WINDOW
= DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOWmask_sh
, .DC_HPD_EN = HPD0_DC_HPD_CONTROL__DC_HPD_ENmask_sh, .DPHY_FEC_EN
= DP0_DP_DPHY_CNTL__DPHY_FEC_ENmask_sh, .DPHY_FEC_READY_SHADOW
= DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOWmask_sh, .DPHY_FEC_ACTIVE_STATUS
= DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUSmask_sh, .DIG_LANE0EN
= DIG0_DIG_LANE_ENABLE__DIG_LANE0ENmask_sh, .DIG_LANE1EN = DIG0_DIG_LANE_ENABLE__DIG_LANE1ENmask_sh
, .DIG_LANE2EN = DIG0_DIG_LANE_ENABLE__DIG_LANE2ENmask_sh, .DIG_LANE3EN
= DIG0_DIG_LANE_ENABLE__DIG_LANE3ENmask_sh, .DIG_CLK_EN = DIG0_DIG_LANE_ENABLE__DIG_CLK_ENmask_sh
, .TMDS_CTL0 = DIG0_TMDS_CTL_BITS__TMDS_CTL0mask_sh, .SYMCLKA_CLOCK_ENABLE
= SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLEmask_sh, .UNIPHY_LINK_ENABLE
= UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLEmask_sh, .UNIPHY_CHANNEL0_XBAR_SOURCE
= UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCEmask_sh
, .UNIPHY_CHANNEL1_XBAR_SOURCE = UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCEmask_sh
, .UNIPHY_CHANNEL2_XBAR_SOURCE = UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCEmask_sh
, .UNIPHY_CHANNEL3_XBAR_SOURCE = UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCEmask_sh
, .AUX_RX_START_WINDOW = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOWmask_sh
, .AUX_RX_HALF_SYM_DETECT_LEN = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LENmask_sh
, .AUX_RX_TRANSITION_FILTER_EN = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_ENmask_sh
, .AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECTmask_sh
, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STARTmask_sh
, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOPmask_sh
, .AUX_RX_PHASE_DETECT_LEN = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LENmask_sh
, .AUX_RX_DETECTION_THRESHOLD = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLDmask_sh
, .AUX_TX_PRECHARGE_LEN = DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LENmask_sh
, .AUX_TX_PRECHARGE_SYMBOLS = DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLSmask_sh
, .AUX_MODE_DET_CHECK_DELAY = DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAYmask_sh
, .AUX_RX_PRECHARGE_SKIP = DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIPmask_sh
, .AUX_RX_TIMEOUT_LEN = DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LENmask_sh
, .AUX_RX_TIMEOUT_LEN_MUL = DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MULmask_sh\
404 LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh).DIG_ENABLE = DIG0_DIG_BE_EN_CNTL__DIG_ENABLEmask_sh, .DIG_HPD_SELECT
= DIG0_DIG_BE_CNTL__DIG_HPD_SELECTmask_sh, .DIG_MODE = DIG0_DIG_BE_CNTL__DIG_MODEmask_sh
, .DIG_FE_SOURCE_SELECT = DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECTmask_sh
, .DIG_CLOCK_PATTERN = DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERNmask_sh
, .TMDS_CTL0 = DIG0_TMDS_CTL_BITS__TMDS_CTL0mask_sh, .DPHY_BYPASS
= DP0_DP_DPHY_CNTL__DPHY_BYPASSmask_sh, .DPHY_ATEST_SEL_LANE0
= DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0mask_sh, .DPHY_ATEST_SEL_LANE1
= DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1mask_sh, .DPHY_ATEST_SEL_LANE2
= DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2mask_sh, .DPHY_ATEST_SEL_LANE3
= DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3mask_sh, .DPHY_PRBS_EN
= DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_ENmask_sh, .DPHY_PRBS_SEL
= DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SELmask_sh, .DPHY_SYM1 = DP0_DP_DPHY_SYM0__DPHY_SYM1mask_sh
, .DPHY_SYM2 = DP0_DP_DPHY_SYM0__DPHY_SYM2mask_sh, .DPHY_SYM3
= DP0_DP_DPHY_SYM0__DPHY_SYM3mask_sh, .DPHY_SYM4 = DP0_DP_DPHY_SYM1__DPHY_SYM4mask_sh
, .DPHY_SYM5 = DP0_DP_DPHY_SYM1__DPHY_SYM5mask_sh, .DPHY_SYM6
= DP0_DP_DPHY_SYM1__DPHY_SYM6mask_sh, .DPHY_SYM7 = DP0_DP_DPHY_SYM2__DPHY_SYM7mask_sh
, .DPHY_SYM8 = DP0_DP_DPHY_SYM2__DPHY_SYM8mask_sh, .DPHY_SCRAMBLER_BS_COUNT
= DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNTmask_sh, .DPHY_SCRAMBLER_ADVANCE
= DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCEmask_sh, .DPHY_RX_FAST_TRAINING_CAPABLE
= DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLEmask_sh
, .DPHY_LOAD_BS_COUNT = DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNTmask_sh
, .DPHY_TRAINING_PATTERN_SEL = DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SELmask_sh
, .DP_DPHY_HBR2_PATTERN_CONTROL = DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROLmask_sh
, .DP_LINK_TRAINING_COMPLETE = DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETEmask_sh
, .DP_IDLE_BS_INTERVAL = DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVALmask_sh
, .DP_VBID_DISABLE = DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLEmask_sh
, .DP_VID_ENHANCED_FRAME_MODE = DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODEmask_sh
, .DP_VID_STREAM_ENABLE = DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLEmask_sh
, .DP_UDI_LANES = DP0_DP_CONFIG__DP_UDI_LANESmask_sh, .DP_SEC_GSP0_LINE_NUM
= DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUMmask_sh, .DP_SEC_GSP0_PRIORITY
= DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITYmask_sh, .DP_MSE_SAT_SRC0
= DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0mask_sh, .DP_MSE_SAT_SRC1 =
DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1mask_sh, .DP_MSE_SAT_SLOT_COUNT0
= DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0mask_sh, .DP_MSE_SAT_SLOT_COUNT1
= DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1mask_sh, .DP_MSE_SAT_SRC2
= DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2mask_sh, .DP_MSE_SAT_SRC3 =
DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3mask_sh, .DP_MSE_SAT_SLOT_COUNT2
= DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2mask_sh, .DP_MSE_SAT_SLOT_COUNT3
= DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3mask_sh, .DP_MSE_SAT_UPDATE
= DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATEmask_sh, .DP_MSE_16_MTP_KEEPOUT
= DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUTmask_sh, .AUX_HPD_SEL
= DP_AUX0_AUX_CONTROL__AUX_HPD_SELmask_sh, .AUX_LS_READ_EN =
DP_AUX0_AUX_CONTROL__AUX_LS_READ_ENmask_sh, .AUX_RX_RECEIVE_WINDOW
= DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOWmask_sh
, .DC_HPD_EN = HPD0_DC_HPD_CONTROL__DC_HPD_ENmask_sh, .DPHY_FEC_EN
= DP0_DP_DPHY_CNTL__DPHY_FEC_ENmask_sh, .DPHY_FEC_READY_SHADOW
= DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOWmask_sh, .DPHY_FEC_ACTIVE_STATUS
= DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUSmask_sh, .DIG_LANE0EN
= DIG0_DIG_LANE_ENABLE__DIG_LANE0ENmask_sh, .DIG_LANE1EN = DIG0_DIG_LANE_ENABLE__DIG_LANE1ENmask_sh
, .DIG_LANE2EN = DIG0_DIG_LANE_ENABLE__DIG_LANE2ENmask_sh, .DIG_LANE3EN
= DIG0_DIG_LANE_ENABLE__DIG_LANE3ENmask_sh, .DIG_CLK_EN = DIG0_DIG_LANE_ENABLE__DIG_CLK_ENmask_sh
, .TMDS_CTL0 = DIG0_TMDS_CTL_BITS__TMDS_CTL0mask_sh, .SYMCLKA_CLOCK_ENABLE
= SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLEmask_sh, .UNIPHY_LINK_ENABLE
= UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLEmask_sh, .UNIPHY_CHANNEL0_XBAR_SOURCE
= UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCEmask_sh
, .UNIPHY_CHANNEL1_XBAR_SOURCE = UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCEmask_sh
, .UNIPHY_CHANNEL2_XBAR_SOURCE = UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCEmask_sh
, .UNIPHY_CHANNEL3_XBAR_SOURCE = UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCEmask_sh
, .AUX_RX_START_WINDOW = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOWmask_sh
, .AUX_RX_HALF_SYM_DETECT_LEN = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LENmask_sh
, .AUX_RX_TRANSITION_FILTER_EN = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_ENmask_sh
, .AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECTmask_sh
, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STARTmask_sh
, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOPmask_sh
, .AUX_RX_PHASE_DETECT_LEN = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LENmask_sh
, .AUX_RX_DETECTION_THRESHOLD = DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLDmask_sh
, .AUX_TX_PRECHARGE_LEN = DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LENmask_sh
, .AUX_TX_PRECHARGE_SYMBOLS = DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLSmask_sh
, .AUX_MODE_DET_CHECK_DELAY = DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAYmask_sh
, .AUX_RX_PRECHARGE_SKIP = DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIPmask_sh
, .AUX_RX_TIMEOUT_LEN = DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LENmask_sh
, .AUX_RX_TIMEOUT_LEN_MUL = DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MULmask_sh
405
406static const struct dcn10_link_enc_shift le_shift = {
407 LINK_ENCODER_MASK_SH_LIST_DCN201(__SHIFT).DIG_ENABLE = 0x0, .DIG_HPD_SELECT = 0x1c, .DIG_MODE = 0x10, .
DIG_FE_SOURCE_SELECT = 0x8, .DIG_CLOCK_PATTERN = 0x0, .TMDS_CTL0
= 0x0, .DPHY_BYPASS = 0x10, .DPHY_ATEST_SEL_LANE0 = 0x0, .DPHY_ATEST_SEL_LANE1
= 0x1, .DPHY_ATEST_SEL_LANE2 = 0x2, .DPHY_ATEST_SEL_LANE3 = 0x3
, .DPHY_PRBS_EN = 0x0, .DPHY_PRBS_SEL = 0x4, .DPHY_SYM1 = 0x0
, .DPHY_SYM2 = 0xa, .DPHY_SYM3 = 0x14, .DPHY_SYM4 = 0x0, .DPHY_SYM5
= 0xa, .DPHY_SYM6 = 0x14, .DPHY_SYM7 = 0x0, .DPHY_SYM8 = 0xa
, .DPHY_SCRAMBLER_BS_COUNT = 0x8, .DPHY_SCRAMBLER_ADVANCE = 0x4
, .DPHY_RX_FAST_TRAINING_CAPABLE = 0x0, .DPHY_LOAD_BS_COUNT =
0x0, .DPHY_TRAINING_PATTERN_SEL = 0x0, .DP_DPHY_HBR2_PATTERN_CONTROL
= 0x0, .DP_LINK_TRAINING_COMPLETE = 0x4, .DP_IDLE_BS_INTERVAL
= 0x0, .DP_VBID_DISABLE = 0x18, .DP_VID_ENHANCED_FRAME_MODE =
0x1c, .DP_VID_STREAM_ENABLE = 0x0, .DP_UDI_LANES = 0x0, .DP_SEC_GSP0_LINE_NUM
= 0x10, .DP_SEC_GSP0_PRIORITY = 0x4, .DP_MSE_SAT_SRC0 = 0x0,
.DP_MSE_SAT_SRC1 = 0x10, .DP_MSE_SAT_SLOT_COUNT0 = 0x8, .DP_MSE_SAT_SLOT_COUNT1
= 0x18, .DP_MSE_SAT_SRC2 = 0x0, .DP_MSE_SAT_SRC3 = 0x10, .DP_MSE_SAT_SLOT_COUNT2
= 0x8, .DP_MSE_SAT_SLOT_COUNT3 = 0x18, .DP_MSE_SAT_UPDATE = 0x0
, .DP_MSE_16_MTP_KEEPOUT = 0x8, .AUX_HPD_SEL = 0x14, .AUX_LS_READ_EN
= 0x8, .AUX_RX_RECEIVE_WINDOW = 0x8, .DC_HPD_EN = 0x1c, .DPHY_FEC_EN
= 0x4, .DPHY_FEC_READY_SHADOW = 0x5, .DPHY_FEC_ACTIVE_STATUS
= 0x6, .DIG_LANE0EN = 0x0, .DIG_LANE1EN = 0x1, .DIG_LANE2EN =
0x2, .DIG_LANE3EN = 0x3, .DIG_CLK_EN = 0x8, .TMDS_CTL0 = 0x0
, .SYMCLKA_CLOCK_ENABLE = 0x0, .UNIPHY_LINK_ENABLE = 0x1c, .UNIPHY_CHANNEL0_XBAR_SOURCE
= 0x0, .UNIPHY_CHANNEL1_XBAR_SOURCE = 0x8, .UNIPHY_CHANNEL2_XBAR_SOURCE
= 0x10, .UNIPHY_CHANNEL3_XBAR_SOURCE = 0x18, .AUX_RX_START_WINDOW
= 0x4, .AUX_RX_HALF_SYM_DETECT_LEN = 0xc, .AUX_RX_TRANSITION_FILTER_EN
= 0x10, .AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x11, .
AUX_RX_ALLOW_BELOW_THRESHOLD_START = 0x12, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP
= 0x13, .AUX_RX_PHASE_DETECT_LEN = 0x14, .AUX_RX_DETECTION_THRESHOLD
= 0x1c, .AUX_TX_PRECHARGE_LEN = 0x0, .AUX_TX_PRECHARGE_SYMBOLS
= 0x8, .AUX_MODE_DET_CHECK_DELAY = 0x10, .AUX_RX_PRECHARGE_SKIP
= 0x0, .AUX_RX_TIMEOUT_LEN = 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf
408};
409
410static const struct dcn10_link_enc_mask le_mask = {
411 LINK_ENCODER_MASK_SH_LIST_DCN201(_MASK).DIG_ENABLE = 0x00000001L, .DIG_HPD_SELECT = 0x70000000L, .DIG_MODE
= 0x00070000L, .DIG_FE_SOURCE_SELECT = 0x00007F00L, .DIG_CLOCK_PATTERN
= 0x000003FFL, .TMDS_CTL0 = 0x00000001L, .DPHY_BYPASS = 0x00010000L
, .DPHY_ATEST_SEL_LANE0 = 0x00000001L, .DPHY_ATEST_SEL_LANE1 =
0x00000002L, .DPHY_ATEST_SEL_LANE2 = 0x00000004L, .DPHY_ATEST_SEL_LANE3
= 0x00000008L, .DPHY_PRBS_EN = 0x00000001L, .DPHY_PRBS_SEL =
0x00000030L, .DPHY_SYM1 = 0x000003FFL, .DPHY_SYM2 = 0x000FFC00L
, .DPHY_SYM3 = 0x3FF00000L, .DPHY_SYM4 = 0x000003FFL, .DPHY_SYM5
= 0x000FFC00L, .DPHY_SYM6 = 0x3FF00000L, .DPHY_SYM7 = 0x000003FFL
, .DPHY_SYM8 = 0x000FFC00L, .DPHY_SCRAMBLER_BS_COUNT = 0x0003FF00L
, .DPHY_SCRAMBLER_ADVANCE = 0x00000010L, .DPHY_RX_FAST_TRAINING_CAPABLE
= 0x00000001L, .DPHY_LOAD_BS_COUNT = 0x000003FFL, .DPHY_TRAINING_PATTERN_SEL
= 0x00000003L, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x00000007L, .
DP_LINK_TRAINING_COMPLETE = 0x00000010L, .DP_IDLE_BS_INTERVAL
= 0x0003FFFFL, .DP_VBID_DISABLE = 0x01000000L, .DP_VID_ENHANCED_FRAME_MODE
= 0x10000000L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_UDI_LANES
= 0x00000003L, .DP_SEC_GSP0_LINE_NUM = 0xFFFF0000L, .DP_SEC_GSP0_PRIORITY
= 0x00000010L, .DP_MSE_SAT_SRC0 = 0x00000007L, .DP_MSE_SAT_SRC1
= 0x00070000L, .DP_MSE_SAT_SLOT_COUNT0 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT1
= 0x3F000000L, .DP_MSE_SAT_SRC2 = 0x00000007L, .DP_MSE_SAT_SRC3
= 0x00070000L, .DP_MSE_SAT_SLOT_COUNT2 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT3
= 0x3F000000L, .DP_MSE_SAT_UPDATE = 0x00000003L, .DP_MSE_16_MTP_KEEPOUT
= 0x00000100L, .AUX_HPD_SEL = 0x00700000L, .AUX_LS_READ_EN =
0x00000100L, .AUX_RX_RECEIVE_WINDOW = 0x00000700L, .DC_HPD_EN
= 0x10000000L, .DPHY_FEC_EN = 0x00000010L, .DPHY_FEC_READY_SHADOW
= 0x00000020L, .DPHY_FEC_ACTIVE_STATUS = 0x00000040L, .DIG_LANE0EN
= 0x00000001L, .DIG_LANE1EN = 0x00000002L, .DIG_LANE2EN = 0x00000004L
, .DIG_LANE3EN = 0x00000008L, .DIG_CLK_EN = 0x00000100L, .TMDS_CTL0
= 0x00000001L, .SYMCLKA_CLOCK_ENABLE = 0x00000001L, .UNIPHY_LINK_ENABLE
= 0x10000000L, .UNIPHY_CHANNEL0_XBAR_SOURCE = 0x00000003L, .
UNIPHY_CHANNEL1_XBAR_SOURCE = 0x00000300L, .UNIPHY_CHANNEL2_XBAR_SOURCE
= 0x00030000L, .UNIPHY_CHANNEL3_XBAR_SOURCE = 0x03000000L, .
AUX_RX_START_WINDOW = 0x00000070L, .AUX_RX_HALF_SYM_DETECT_LEN
= 0x00003000L, .AUX_RX_TRANSITION_FILTER_EN = 0x00010000L, .
AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00020000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_START
= 0x00040000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = 0x00080000L
, .AUX_RX_PHASE_DETECT_LEN = 0x00300000L, .AUX_RX_DETECTION_THRESHOLD
= 0x70000000L, .AUX_TX_PRECHARGE_LEN = 0x0000000FL, .AUX_TX_PRECHARGE_SYMBOLS
= 0x00003F00L, .AUX_MODE_DET_CHECK_DELAY = 0x00070000L, .AUX_RX_PRECHARGE_SKIP
= 0x000000FFL, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL
= 0x00018000L
412};
413
414#define ipp_regs(id)[id] = { .FORMAT_CONTROL = DMU_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX
+ mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DMU_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX
+ mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL =
DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL
, .CURSOR0_COLOR0 = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR_SURFACE_ADDRESS_HIGH =
DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX
+ mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX
+ mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX
+ mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX
+ mmCURSOR0_id_CURSOR_DST_OFFSET,}\
415[id] = {\
416 IPP_REG_LIST_DCN201(id).FORMAT_CONTROL = DMU_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX
+ mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DMU_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX
+ mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL =
DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL
, .CURSOR0_COLOR0 = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR_SURFACE_ADDRESS_HIGH =
DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX
+ mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX
+ mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX
+ mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX
+ mmCURSOR0_id_CURSOR_DST_OFFSET,\
417}
418
419static const struct dcn10_ipp_registers ipp_regs[] = {
420 ipp_regs(0)[0] = { .FORMAT_CONTROL = 0x000034C0 + 0x0cd0, .CNVC_SURFACE_PIXEL_FORMAT
= 0x000034C0 + 0x0ccf, .CURSOR0_CONTROL = 0x000034C0 + 0x0ce0
, .CURSOR0_COLOR0 = 0x000034C0 + 0x0ce1, .CURSOR0_COLOR1 = 0x000034C0
+ 0x0ce2, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x067a
, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0679, .CURSOR_SIZE
= 0x000034C0 + 0x067b, .CURSOR_CONTROL = 0x000034C0 + 0x0678
, .CURSOR_POSITION = 0x000034C0 + 0x067c, .CURSOR_HOT_SPOT = 0x000034C0
+ 0x067d, .CURSOR_DST_OFFSET = 0x000034C0 + 0x067f,},
421 ipp_regs(1)[1] = { .FORMAT_CONTROL = 0x000034C0 + 0x0e3b, .CNVC_SURFACE_PIXEL_FORMAT
= 0x000034C0 + 0x0e3a, .CURSOR0_CONTROL = 0x000034C0 + 0x0e4b
, .CURSOR0_COLOR0 = 0x000034C0 + 0x0e4c, .CURSOR0_COLOR1 = 0x000034C0
+ 0x0e4d, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0756
, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0755, .CURSOR_SIZE
= 0x000034C0 + 0x0757, .CURSOR_CONTROL = 0x000034C0 + 0x0754
, .CURSOR_POSITION = 0x000034C0 + 0x0758, .CURSOR_HOT_SPOT = 0x000034C0
+ 0x0759, .CURSOR_DST_OFFSET = 0x000034C0 + 0x075b,},
422 ipp_regs(2)[2] = { .FORMAT_CONTROL = 0x000034C0 + 0x0fa6, .CNVC_SURFACE_PIXEL_FORMAT
= 0x000034C0 + 0x0fa5, .CURSOR0_CONTROL = 0x000034C0 + 0x0fb6
, .CURSOR0_COLOR0 = 0x000034C0 + 0x0fb7, .CURSOR0_COLOR1 = 0x000034C0
+ 0x0fb8, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0832
, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0831, .CURSOR_SIZE
= 0x000034C0 + 0x0833, .CURSOR_CONTROL = 0x000034C0 + 0x0830
, .CURSOR_POSITION = 0x000034C0 + 0x0834, .CURSOR_HOT_SPOT = 0x000034C0
+ 0x0835, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0837,},
423 ipp_regs(3)[3] = { .FORMAT_CONTROL = 0x000034C0 + 0x1111, .CNVC_SURFACE_PIXEL_FORMAT
= 0x000034C0 + 0x1110, .CURSOR0_CONTROL = 0x000034C0 + 0x1121
, .CURSOR0_COLOR0 = 0x000034C0 + 0x1122, .CURSOR0_COLOR1 = 0x000034C0
+ 0x1123, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x090e
, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x090d, .CURSOR_SIZE
= 0x000034C0 + 0x090f, .CURSOR_CONTROL = 0x000034C0 + 0x090c
, .CURSOR_POSITION = 0x000034C0 + 0x0910, .CURSOR_HOT_SPOT = 0x000034C0
+ 0x0911, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0913,},
424};
425
426static const struct dcn10_ipp_shift ipp_shift = {
427 IPP_MASK_SH_LIST_DCN201(__SHIFT).CNVC_SURFACE_PIXEL_FORMAT = 0x0, .CNVC_BYPASS = 0xc, .ALPHA_EN
= 0x8, .FORMAT_EXPANSION_MODE = 0x0, .CUR0_MODE = 0x4, .CUR0_COLOR0
= 0x0, .CUR0_COLOR1 = 0x0, .CUR0_EXPANSION_MODE = 0x1, .CUR0_ENABLE
= 0x0, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0, .CURSOR_SURFACE_ADDRESS
= 0x0, .CURSOR_WIDTH = 0x10, .CURSOR_HEIGHT = 0x0, .CURSOR_MODE
= 0x8, .CURSOR_2X_MAGNIFY = 0x4, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK
= 0x18, .CURSOR_ENABLE = 0x0, .CURSOR_X_POSITION = 0x10, .CURSOR_Y_POSITION
= 0x0, .CURSOR_HOT_SPOT_X = 0x10, .CURSOR_HOT_SPOT_Y = 0x0, .
CURSOR_DST_X_OFFSET = 0x0
428};
429
430static const struct dcn10_ipp_mask ipp_mask = {
431 IPP_MASK_SH_LIST_DCN201(_MASK).CNVC_SURFACE_PIXEL_FORMAT = 0x0000007FL, .CNVC_BYPASS = 0x00001000L
, .ALPHA_EN = 0x00000100L, .FORMAT_EXPANSION_MODE = 0x00000001L
, .CUR0_MODE = 0x00000070L, .CUR0_COLOR0 = 0x00FFFFFFL, .CUR0_COLOR1
= 0x00FFFFFFL, .CUR0_EXPANSION_MODE = 0x00000002L, .CUR0_ENABLE
= 0x00000001L, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .
CURSOR_SURFACE_ADDRESS = 0xFFFFFFFFL, .CURSOR_WIDTH = 0x01FF0000L
, .CURSOR_HEIGHT = 0x000001FFL, .CURSOR_MODE = 0x00000700L, .
CURSOR_2X_MAGNIFY = 0x00000010L, .CURSOR_PITCH = 0x00030000L,
.CURSOR_LINES_PER_CHUNK = 0x1F000000L, .CURSOR_ENABLE = 0x00000001L
, .CURSOR_X_POSITION = 0x3FFF0000L, .CURSOR_Y_POSITION = 0x00003FFFL
, .CURSOR_HOT_SPOT_X = 0x00FF0000L, .CURSOR_HOT_SPOT_Y = 0x000000FFL
, .CURSOR_DST_X_OFFSET = 0x00001FFFL
432};
433
434#define opp_regs(id)[id] = { .FMT_BIT_DEPTH_CONTROL = DMU_BASE__INST0_SEGmmFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX
+ mmFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = DMU_BASE__INST0_SEGmmFMTid_FMT_CONTROL_BASE_IDX
+ mmFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = DMU_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_R_SEED, .FMT_DITHER_RAND_G_SEED = DMU_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED = DMU_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = DMU_BASE__INST0_SEGmmFMTid_FMT_CLAMP_CNTL_BASE_IDX
+ mmFMTid_FMT_CLAMP_CNTL, .FMT_DYNAMIC_EXP_CNTL = DMU_BASE__INST0_SEGmmFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX
+ mmFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_MAP420_MEMORY_CONTROL =
DMU_BASE__INST0_SEGmmFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX
+ mmFMTid_FMT_MAP420_MEMORY_CONTROL, .OPPBUF_CONTROL = DMU_BASE__INST0_SEGmmOPPBUFid_OPPBUF_CONTROL_BASE_IDX
+ mmOPPBUFid_OPPBUF_CONTROL, .OPPBUF_3D_PARAMETERS_0 = DMU_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX
+ mmOPPBUFid_OPPBUF_3D_PARAMETERS_0, .OPPBUF_3D_PARAMETERS_1
= DMU_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX
+ mmOPPBUFid_OPPBUF_3D_PARAMETERS_1, .OPP_PIPE_CONTROL = DMU_BASE__INST0_SEGmmOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX
+ mmOPP_PIPEid_OPP_PIPE_CONTROL, .DPG_CONTROL = DMU_BASE__INST0_SEGmmDPGid_DPG_CONTROL_BASE_IDX
+ mmDPGid_DPG_CONTROL, .DPG_DIMENSIONS = DMU_BASE__INST0_SEGmmDPGid_DPG_DIMENSIONS_BASE_IDX
+ mmDPGid_DPG_DIMENSIONS, .DPG_OFFSET_SEGMENT = DMU_BASE__INST0_SEGmmDPGid_DPG_OFFSET_SEGMENT_BASE_IDX
+ mmDPGid_DPG_OFFSET_SEGMENT, .DPG_COLOUR_B_CB = DMU_BASE__INST0_SEGmmDPGid_DPG_COLOUR_B_CB_BASE_IDX
+ mmDPGid_DPG_COLOUR_B_CB, .DPG_COLOUR_G_Y = DMU_BASE__INST0_SEGmmDPGid_DPG_COLOUR_G_Y_BASE_IDX
+ mmDPGid_DPG_COLOUR_G_Y, .DPG_COLOUR_R_CR = DMU_BASE__INST0_SEGmmDPGid_DPG_COLOUR_R_CR_BASE_IDX
+ mmDPGid_DPG_COLOUR_R_CR, .DPG_RAMP_CONTROL = DMU_BASE__INST0_SEGmmDPGid_DPG_RAMP_CONTROL_BASE_IDX
+ mmDPGid_DPG_RAMP_CONTROL, .DPG_STATUS = DMU_BASE__INST0_SEGmmDPGid_DPG_STATUS_BASE_IDX
+ mmDPGid_DPG_STATUS, .FMT_422_CONTROL = DMU_BASE__INST0_SEGmmFMTid_FMT_422_CONTROL_BASE_IDX
+ mmFMTid_FMT_422_CONTROL,}\
435[id] = {\
436 OPP_REG_LIST_DCN201(id).FMT_BIT_DEPTH_CONTROL = DMU_BASE__INST0_SEGmmFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX
+ mmFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = DMU_BASE__INST0_SEGmmFMTid_FMT_CONTROL_BASE_IDX
+ mmFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = DMU_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_R_SEED, .FMT_DITHER_RAND_G_SEED = DMU_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED = DMU_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX
+ mmFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = DMU_BASE__INST0_SEGmmFMTid_FMT_CLAMP_CNTL_BASE_IDX
+ mmFMTid_FMT_CLAMP_CNTL, .FMT_DYNAMIC_EXP_CNTL = DMU_BASE__INST0_SEGmmFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX
+ mmFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_MAP420_MEMORY_CONTROL =
DMU_BASE__INST0_SEGmmFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX
+ mmFMTid_FMT_MAP420_MEMORY_CONTROL, .OPPBUF_CONTROL = DMU_BASE__INST0_SEGmmOPPBUFid_OPPBUF_CONTROL_BASE_IDX
+ mmOPPBUFid_OPPBUF_CONTROL, .OPPBUF_3D_PARAMETERS_0 = DMU_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX
+ mmOPPBUFid_OPPBUF_3D_PARAMETERS_0, .OPPBUF_3D_PARAMETERS_1
= DMU_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX
+ mmOPPBUFid_OPPBUF_3D_PARAMETERS_1, .OPP_PIPE_CONTROL = DMU_BASE__INST0_SEGmmOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX
+ mmOPP_PIPEid_OPP_PIPE_CONTROL, .DPG_CONTROL = DMU_BASE__INST0_SEGmmDPGid_DPG_CONTROL_BASE_IDX
+ mmDPGid_DPG_CONTROL, .DPG_DIMENSIONS = DMU_BASE__INST0_SEGmmDPGid_DPG_DIMENSIONS_BASE_IDX
+ mmDPGid_DPG_DIMENSIONS, .DPG_OFFSET_SEGMENT = DMU_BASE__INST0_SEGmmDPGid_DPG_OFFSET_SEGMENT_BASE_IDX
+ mmDPGid_DPG_OFFSET_SEGMENT, .DPG_COLOUR_B_CB = DMU_BASE__INST0_SEGmmDPGid_DPG_COLOUR_B_CB_BASE_IDX
+ mmDPGid_DPG_COLOUR_B_CB, .DPG_COLOUR_G_Y = DMU_BASE__INST0_SEGmmDPGid_DPG_COLOUR_G_Y_BASE_IDX
+ mmDPGid_DPG_COLOUR_G_Y, .DPG_COLOUR_R_CR = DMU_BASE__INST0_SEGmmDPGid_DPG_COLOUR_R_CR_BASE_IDX
+ mmDPGid_DPG_COLOUR_R_CR, .DPG_RAMP_CONTROL = DMU_BASE__INST0_SEGmmDPGid_DPG_RAMP_CONTROL_BASE_IDX
+ mmDPGid_DPG_RAMP_CONTROL, .DPG_STATUS = DMU_BASE__INST0_SEGmmDPGid_DPG_STATUS_BASE_IDX
+ mmDPGid_DPG_STATUS, .FMT_422_CONTROL = DMU_BASE__INST0_SEGmmFMTid_FMT_422_CONTROL_BASE_IDX
+ mmFMTid_FMT_422_CONTROL,\
437}
438
439static const struct dcn201_opp_registers opp_regs[] = {
440 opp_regs(0)[0] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x1841, .FMT_CONTROL
= 0x000034C0 + 0x1840, .FMT_DITHER_RAND_R_SEED = 0x000034C0 +
0x1842, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1843, .FMT_DITHER_RAND_B_SEED
= 0x000034C0 + 0x1844, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1845
, .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x183f, .FMT_MAP420_MEMORY_CONTROL
= 0x000034C0 + 0x1847, .OPPBUF_CONTROL = 0x000034C0 + 0x1884
, .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1885, .OPPBUF_3D_PARAMETERS_1
= 0x000034C0 + 0x1886, .OPP_PIPE_CONTROL = 0x000034C0 + 0x188c
, .DPG_CONTROL = 0x000034C0 + 0x1854, .DPG_DIMENSIONS = 0x000034C0
+ 0x1856, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x185a, .DPG_COLOUR_B_CB
= 0x000034C0 + 0x1859, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1858
, .DPG_COLOUR_R_CR = 0x000034C0 + 0x1857, .DPG_RAMP_CONTROL =
0x000034C0 + 0x1855, .DPG_STATUS = 0x000034C0 + 0x185b, .FMT_422_CONTROL
= 0x000034C0 + 0x1849,},
441 opp_regs(1)[1] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x189b, .FMT_CONTROL
= 0x000034C0 + 0x189a, .FMT_DITHER_RAND_R_SEED = 0x000034C0 +
0x189c, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x189d, .FMT_DITHER_RAND_B_SEED
= 0x000034C0 + 0x189e, .FMT_CLAMP_CNTL = 0x000034C0 + 0x189f
, .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x1899, .FMT_MAP420_MEMORY_CONTROL
= 0x000034C0 + 0x18a1, .OPPBUF_CONTROL = 0x000034C0 + 0x18de
, .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x18df, .OPPBUF_3D_PARAMETERS_1
= 0x000034C0 + 0x18e0, .OPP_PIPE_CONTROL = 0x000034C0 + 0x18e6
, .DPG_CONTROL = 0x000034C0 + 0x18ae, .DPG_DIMENSIONS = 0x000034C0
+ 0x18b0, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x18b4, .DPG_COLOUR_B_CB
= 0x000034C0 + 0x18b3, .DPG_COLOUR_G_Y = 0x000034C0 + 0x18b2
, .DPG_COLOUR_R_CR = 0x000034C0 + 0x18b1, .DPG_RAMP_CONTROL =
0x000034C0 + 0x18af, .DPG_STATUS = 0x000034C0 + 0x18b5, .FMT_422_CONTROL
= 0x000034C0 + 0x18a3,},
442};
443
444static const struct dcn201_opp_shift opp_shift = {
445 OPP_MASK_SH_LIST_DCN201(__SHIFT).FMT_TRUNCATE_EN = 0x0, .FMT_TRUNCATE_DEPTH = 0x4, .FMT_TRUNCATE_MODE
= 0x1, .FMT_SPATIAL_DITHER_EN = 0x8, .FMT_SPATIAL_DITHER_MODE
= 0x9, .FMT_SPATIAL_DITHER_DEPTH = 0xb, .FMT_TEMPORAL_DITHER_EN
= 0x10, .FMT_HIGHPASS_RANDOM_ENABLE = 0xf, .FMT_FRAME_RANDOM_ENABLE
= 0xd, .FMT_RGB_RANDOM_ENABLE = 0xe, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX
= 0x8, .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0xc, .FMT_PIXEL_ENCODING
= 0x10, .FMT_STEREOSYNC_OVERRIDE = 0x0, .FMT_RAND_R_SEED = 0x0
, .FMT_RAND_G_SEED = 0x0, .FMT_RAND_B_SEED = 0x0, .FMT_CLAMP_DATA_EN
= 0x0, .FMT_CLAMP_COLOR_FORMAT = 0x10, .FMT_DYNAMIC_EXP_EN =
0x0, .FMT_DYNAMIC_EXP_MODE = 0x4, .FMT_MAP420MEM_PWR_FORCE =
0x0, .OPPBUF_ACTIVE_WIDTH = 0x0, .OPPBUF_PIXEL_REPETITION = 0x18
, .OPPBUF_3D_VACT_SPACE1_SIZE = 0x0, .OPPBUF_3D_VACT_SPACE2_SIZE
= 0xa, .OPP_PIPE_CLOCK_EN = 0x0, .DPG_EN = 0x0, .DPG_MODE = 0x4
, .DPG_DYNAMIC_RANGE = 0x8, .DPG_BIT_DEPTH = 0xc, .DPG_VRES =
0x10, .DPG_HRES = 0x14, .DPG_ACTIVE_WIDTH = 0x10, .DPG_ACTIVE_HEIGHT
= 0x0, .DPG_X_OFFSET = 0x0, .DPG_SEGMENT_WIDTH = 0x10, .DPG_COLOUR0_R_CR
= 0x0, .DPG_COLOUR1_R_CR = 0x10, .DPG_COLOUR0_B_CB = 0x0, .DPG_COLOUR1_B_CB
= 0x10, .DPG_COLOUR0_G_Y = 0x0, .DPG_COLOUR1_G_Y = 0x10, .DPG_RAMP0_OFFSET
= 0x0, .DPG_INC0 = 0x18, .DPG_INC1 = 0x1c, .DPG_DOUBLE_BUFFER_PENDING
= 0x0, .OPPBUF_DISPLAY_SEGMENTATION = 0x10, .OPPBUF_OVERLAP_PIXEL_NUM
= 0x14, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x0
446};
447
448static const struct dcn201_opp_mask opp_mask = {
449 OPP_MASK_SH_LIST_DCN201(_MASK).FMT_TRUNCATE_EN = 0x00000001L, .FMT_TRUNCATE_DEPTH = 0x00000030L
, .FMT_TRUNCATE_MODE = 0x00000002L, .FMT_SPATIAL_DITHER_EN = 0x00000100L
, .FMT_SPATIAL_DITHER_MODE = 0x00000600L, .FMT_SPATIAL_DITHER_DEPTH
= 0x00001800L, .FMT_TEMPORAL_DITHER_EN = 0x00010000L, .FMT_HIGHPASS_RANDOM_ENABLE
= 0x00008000L, .FMT_FRAME_RANDOM_ENABLE = 0x00002000L, .FMT_RGB_RANDOM_ENABLE
= 0x00004000L, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0x00000F00L
, .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0x00003000L, .
FMT_PIXEL_ENCODING = 0x00030000L, .FMT_STEREOSYNC_OVERRIDE = 0x00000001L
, .FMT_RAND_R_SEED = 0x000000FFL, .FMT_RAND_G_SEED = 0x000000FFL
, .FMT_RAND_B_SEED = 0x000000FFL, .FMT_CLAMP_DATA_EN = 0x00000001L
, .FMT_CLAMP_COLOR_FORMAT = 0x00070000L, .FMT_DYNAMIC_EXP_EN =
0x00000001L, .FMT_DYNAMIC_EXP_MODE = 0x00000010L, .FMT_MAP420MEM_PWR_FORCE
= 0x00000003L, .OPPBUF_ACTIVE_WIDTH = 0x00003FFFL, .OPPBUF_PIXEL_REPETITION
= 0x0F000000L, .OPPBUF_3D_VACT_SPACE1_SIZE = 0x000003FFL, .OPPBUF_3D_VACT_SPACE2_SIZE
= 0x000FFC00L, .OPP_PIPE_CLOCK_EN = 0x00000001L, .DPG_EN = 0x00000001L
, .DPG_MODE = 0x00000070L, .DPG_DYNAMIC_RANGE = 0x00000100L, .
DPG_BIT_DEPTH = 0x00003000L, .DPG_VRES = 0x000F0000L, .DPG_HRES
= 0x00F00000L, .DPG_ACTIVE_WIDTH = 0x3FFF0000L, .DPG_ACTIVE_HEIGHT
= 0x00003FFFL, .DPG_X_OFFSET = 0x00003FFFL, .DPG_SEGMENT_WIDTH
= 0x3FFF0000L, .DPG_COLOUR0_R_CR = 0x0000FFFFL, .DPG_COLOUR1_R_CR
= 0xFFFF0000L, .DPG_COLOUR0_B_CB = 0x0000FFFFL, .DPG_COLOUR1_B_CB
= 0xFFFF0000L, .DPG_COLOUR0_G_Y = 0x0000FFFFL, .DPG_COLOUR1_G_Y
= 0xFFFF0000L, .DPG_RAMP0_OFFSET = 0x0000FFFFL, .DPG_INC0 = 0x0F000000L
, .DPG_INC1 = 0xF0000000L, .DPG_DOUBLE_BUFFER_PENDING = 0x00000001L
, .OPPBUF_DISPLAY_SEGMENTATION = 0x00070000L, .OPPBUF_OVERLAP_PIXEL_NUM
= 0x00F00000L, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x00000001L
450};
451
452#define aux_engine_regs(id)[id] = { .AUX_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_ARB_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_SW_DATA_BASE_IDX
+ mmDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_SW_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_DPHY_RX_CONTROL1 = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_SW_STATUS = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_SW_STATUS_BASE_IDX
+ mmDP_AUXid_AUX_SW_STATUS, .AUX_RESET_MASK = 0 }\
453[id] = {\
454 AUX_COMMON_REG_LIST0(id).AUX_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_ARB_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_SW_DATA_BASE_IDX
+ mmDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_SW_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX
+ mmDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_DPHY_RX_CONTROL1 = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX
+ mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_SW_STATUS = DMU_BASE__INST0_SEGmmDP_AUXid_AUX_SW_STATUS_BASE_IDX
+ mmDP_AUXid_AUX_SW_STATUS, \
455 .AUX_RESET_MASK = 0 \
456}
457
458static const struct dce110_aux_registers aux_engine_regs[] = {
459 aux_engine_regs(0)[0] = { .AUX_CONTROL = 0x000034C0 + 0x1f50, .AUX_ARB_CONTROL =
0x000034C0 + 0x1f52, .AUX_SW_DATA = 0x000034C0 + 0x1f56, .AUX_SW_CONTROL
= 0x000034C0 + 0x1f51, .AUX_INTERRUPT_CONTROL = 0x000034C0 +
0x1f53, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f5b, .AUX_SW_STATUS
= 0x000034C0 + 0x1f54, .AUX_RESET_MASK = 0 },
460 aux_engine_regs(1)[1] = { .AUX_CONTROL = 0x000034C0 + 0x1f6c, .AUX_ARB_CONTROL =
0x000034C0 + 0x1f6e, .AUX_SW_DATA = 0x000034C0 + 0x1f72, .AUX_SW_CONTROL
= 0x000034C0 + 0x1f6d, .AUX_INTERRUPT_CONTROL = 0x000034C0 +
0x1f6f, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f77, .AUX_SW_STATUS
= 0x000034C0 + 0x1f70, .AUX_RESET_MASK = 0 }
461};
462
463#define tf_regs(id)[id] = { .CM_GAMUT_REMAP_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_CONTROL, .CM_GAMUT_REMAP_C11_C12 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C11_C12, .CM_GAMUT_REMAP_C13_C14 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C13_C14, .CM_GAMUT_REMAP_C21_C22 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C21_C22, .CM_GAMUT_REMAP_C23_C24 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C23_C24, .CM_GAMUT_REMAP_C31_C32 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C31_C32, .CM_GAMUT_REMAP_C33_C34 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C33_C34, .DSCL_EXT_OVERSCAN_LEFT_RIGHT
= DMU_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX
+ mmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, .DSCL_EXT_OVERSCAN_TOP_BOTTOM
= DMU_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX
+ mmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, .DSCL_MEM_PWR_STATUS
= DMU_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_STATUS_BASE_IDX +
mmDSCLid_DSCL_MEM_PWR_STATUS, .DSCL_MEM_PWR_CTRL = DMU_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_DSCL_MEM_PWR_CTRL, .OTG_H_BLANK = DMU_BASE__INST0_SEGmmDSCLid_OTG_H_BLANK_BASE_IDX
+ mmDSCLid_OTG_H_BLANK, .OTG_V_BLANK = DMU_BASE__INST0_SEGmmDSCLid_OTG_V_BLANK_BASE_IDX
+ mmDSCLid_OTG_V_BLANK, .SCL_MODE = DMU_BASE__INST0_SEGmmDSCLid_SCL_MODE_BASE_IDX
+ mmDSCLid_SCL_MODE, .LB_DATA_FORMAT = DMU_BASE__INST0_SEGmmDSCLid_LB_DATA_FORMAT_BASE_IDX
+ mmDSCLid_LB_DATA_FORMAT, .LB_MEMORY_CTRL = DMU_BASE__INST0_SEGmmDSCLid_LB_MEMORY_CTRL_BASE_IDX
+ mmDSCLid_LB_MEMORY_CTRL, .DSCL_AUTOCAL = DMU_BASE__INST0_SEGmmDSCLid_DSCL_AUTOCAL_BASE_IDX
+ mmDSCLid_DSCL_AUTOCAL, .SCL_BLACK_OFFSET = DMU_BASE__INST0_SEGmmDSCLid_SCL_BLACK_OFFSET_BASE_IDX
+ mmDSCLid_SCL_BLACK_OFFSET, .SCL_TAP_CONTROL = DMU_BASE__INST0_SEGmmDSCLid_SCL_TAP_CONTROL_BASE_IDX
+ mmDSCLid_SCL_TAP_CONTROL, .SCL_COEF_RAM_TAP_SELECT = DMU_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX
+ mmDSCLid_SCL_COEF_RAM_TAP_SELECT, .SCL_COEF_RAM_TAP_DATA =
DMU_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX +
mmDSCLid_SCL_COEF_RAM_TAP_DATA, .DSCL_2TAP_CONTROL = DMU_BASE__INST0_SEGmmDSCLid_DSCL_2TAP_CONTROL_BASE_IDX
+ mmDSCLid_DSCL_2TAP_CONTROL, .MPC_SIZE = DMU_BASE__INST0_SEGmmDSCLid_MPC_SIZE_BASE_IDX
+ mmDSCLid_MPC_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO = DMU_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO
= DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_SCALE_RATIO_C
= DMU_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C, .SCL_VERT_FILTER_SCALE_RATIO_C
= DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C, .SCL_HORZ_FILTER_INIT
= DMU_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX +
mmDSCLid_SCL_HORZ_FILTER_INIT, .SCL_HORZ_FILTER_INIT_C = DMU_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_INIT_C, .SCL_VERT_FILTER_INIT = DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT, .SCL_VERT_FILTER_INIT_BOT =
DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BOT_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT_BOT, .SCL_VERT_FILTER_INIT_C
= DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT_C, .SCL_VERT_FILTER_INIT_BOT_C
= DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT_BOT_C, .RECOUT_START = DMU_BASE__INST0_SEGmmDSCLid_RECOUT_START_BASE_IDX
+ mmDSCLid_RECOUT_START, .RECOUT_SIZE = DMU_BASE__INST0_SEGmmDSCLid_RECOUT_SIZE_BASE_IDX
+ mmDSCLid_RECOUT_SIZE, .CM_ICSC_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_ICSC_CONTROL_BASE_IDX
+ mmCMid_CM_ICSC_CONTROL, .CM_ICSC_C11_C12 = DMU_BASE__INST0_SEGmmCMid_CM_ICSC_C11_C12_BASE_IDX
+ mmCMid_CM_ICSC_C11_C12, .CM_ICSC_C33_C34 = DMU_BASE__INST0_SEGmmCMid_CM_ICSC_C33_C34_BASE_IDX
+ mmCMid_CM_ICSC_C33_C34, .CM_DGAM_RAMB_START_CNTL_B = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_START_CNTL_B, .CM_DGAM_RAMB_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_START_CNTL_G, .CM_DGAM_RAMB_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_START_CNTL_R, .CM_DGAM_RAMB_SLOPE_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_B, .CM_DGAM_RAMB_SLOPE_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_G, .CM_DGAM_RAMB_SLOPE_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_R, .CM_DGAM_RAMB_END_CNTL1_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL1_B, .CM_DGAM_RAMB_END_CNTL2_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL2_B, .CM_DGAM_RAMB_END_CNTL1_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL1_G, .CM_DGAM_RAMB_END_CNTL2_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL2_G, .CM_DGAM_RAMB_END_CNTL1_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL1_R, .CM_DGAM_RAMB_END_CNTL2_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL2_R, .CM_DGAM_RAMB_REGION_0_1 =
DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_REGION_0_1_BASE_IDX +
mmCMid_CM_DGAM_RAMB_REGION_0_1, .CM_DGAM_RAMB_REGION_14_15 =
DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_REGION_14_15, .CM_DGAM_RAMA_START_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_START_CNTL_B, .CM_DGAM_RAMA_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_START_CNTL_G, .CM_DGAM_RAMA_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_START_CNTL_R, .CM_DGAM_RAMA_SLOPE_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_B, .CM_DGAM_RAMA_SLOPE_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_G, .CM_DGAM_RAMA_SLOPE_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_R, .CM_DGAM_RAMA_END_CNTL1_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL1_B, .CM_DGAM_RAMA_END_CNTL2_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL2_B, .CM_DGAM_RAMA_END_CNTL1_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL1_G, .CM_DGAM_RAMA_END_CNTL2_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL2_G, .CM_DGAM_RAMA_END_CNTL1_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL1_R, .CM_DGAM_RAMA_END_CNTL2_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL2_R, .CM_DGAM_RAMA_REGION_0_1 =
DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_REGION_0_1_BASE_IDX +
mmCMid_CM_DGAM_RAMA_REGION_0_1, .CM_DGAM_RAMA_REGION_14_15 =
DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_REGION_14_15, .CM_MEM_PWR_CTRL = DMU_BASE__INST0_SEGmmCMid_CM_MEM_PWR_CTRL_BASE_IDX
+ mmCMid_CM_MEM_PWR_CTRL, .CM_DGAM_LUT_WRITE_EN_MASK = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX
+ mmCMid_CM_DGAM_LUT_WRITE_EN_MASK, .CM_DGAM_LUT_INDEX = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_INDEX_BASE_IDX
+ mmCMid_CM_DGAM_LUT_INDEX, .CM_DGAM_LUT_DATA = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_DATA_BASE_IDX
+ mmCMid_CM_DGAM_LUT_DATA, .CM_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_CONTROL_BASE_IDX
+ mmCMid_CM_CONTROL, .CM_DGAM_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_CONTROL_BASE_IDX
+ mmCMid_CM_DGAM_CONTROL, .CM_TEST_DEBUG_INDEX = DMU_BASE__INST0_SEGmmCMid_CM_TEST_DEBUG_INDEX_BASE_IDX
+ mmCMid_CM_TEST_DEBUG_INDEX, .CM_TEST_DEBUG_DATA = DMU_BASE__INST0_SEGmmCMid_CM_TEST_DEBUG_DATA_BASE_IDX
+ mmCMid_CM_TEST_DEBUG_DATA, .FORMAT_CONTROL = DMU_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX
+ mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DMU_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX
+ mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL =
DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL
, .CURSOR0_COLOR0 = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR0_FP_SCALE_BIAS = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX
+ mmCNVC_CURid_CURSOR0_FP_SCALE_BIAS, .DPP_CONTROL = DMU_BASE__INST0_SEGmmDPP_TOPid_DPP_CONTROL_BASE_IDX
+ mmDPP_TOPid_DPP_CONTROL, .CM_HDR_MULT_COEF = DMU_BASE__INST0_SEGmmCMid_CM_HDR_MULT_COEF_BASE_IDX
+ mmCMid_CM_HDR_MULT_COEF, .CM_BLNDGAM_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_CONTROL_BASE_IDX
+ mmCMid_CM_BLNDGAM_CONTROL, .CM_BLNDGAM_RAMB_START_CNTL_B =
DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_B, .CM_BLNDGAM_RAMB_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_G, .CM_BLNDGAM_RAMB_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_R, .CM_BLNDGAM_RAMB_END_CNTL1_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B, .CM_BLNDGAM_RAMB_END_CNTL2_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B, .CM_BLNDGAM_RAMB_END_CNTL1_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G, .CM_BLNDGAM_RAMB_END_CNTL2_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G, .CM_BLNDGAM_RAMB_END_CNTL1_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R, .CM_BLNDGAM_RAMB_END_CNTL2_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R, .CM_BLNDGAM_RAMB_REGION_0_1
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_0_1, .CM_BLNDGAM_RAMB_REGION_2_3
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_2_3, .CM_BLNDGAM_RAMB_REGION_4_5
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_4_5, .CM_BLNDGAM_RAMB_REGION_6_7
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_6_7, .CM_BLNDGAM_RAMB_REGION_8_9
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_8_9, .CM_BLNDGAM_RAMB_REGION_10_11
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_10_11, .CM_BLNDGAM_RAMB_REGION_12_13
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_12_13, .CM_BLNDGAM_RAMB_REGION_14_15
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_14_15, .CM_BLNDGAM_RAMB_REGION_16_17
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_16_17, .CM_BLNDGAM_RAMB_REGION_18_19
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_18_19, .CM_BLNDGAM_RAMB_REGION_20_21
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_20_21, .CM_BLNDGAM_RAMB_REGION_22_23
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_22_23, .CM_BLNDGAM_RAMB_REGION_24_25
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_24_25, .CM_BLNDGAM_RAMB_REGION_26_27
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_26_27, .CM_BLNDGAM_RAMB_REGION_28_29
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_28_29, .CM_BLNDGAM_RAMB_REGION_30_31
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_30_31, .CM_BLNDGAM_RAMB_REGION_32_33
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_32_33, .CM_BLNDGAM_RAMA_START_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_B, .CM_BLNDGAM_RAMA_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_G, .CM_BLNDGAM_RAMA_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_R, .CM_BLNDGAM_RAMA_END_CNTL1_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B, .CM_BLNDGAM_RAMA_END_CNTL2_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B, .CM_BLNDGAM_RAMA_END_CNTL1_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G, .CM_BLNDGAM_RAMA_END_CNTL2_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G, .CM_BLNDGAM_RAMA_END_CNTL1_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R, .CM_BLNDGAM_RAMA_END_CNTL2_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R, .CM_BLNDGAM_RAMA_REGION_0_1
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_0_1, .CM_BLNDGAM_RAMA_REGION_2_3
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_2_3, .CM_BLNDGAM_RAMA_REGION_4_5
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_4_5, .CM_BLNDGAM_RAMA_REGION_6_7
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_6_7, .CM_BLNDGAM_RAMA_REGION_8_9
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_8_9, .CM_BLNDGAM_RAMA_REGION_10_11
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_10_11, .CM_BLNDGAM_RAMA_REGION_12_13
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_12_13, .CM_BLNDGAM_RAMA_REGION_14_15
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_14_15, .CM_BLNDGAM_RAMA_REGION_16_17
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_16_17, .CM_BLNDGAM_RAMA_REGION_18_19
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_18_19, .CM_BLNDGAM_RAMA_REGION_20_21
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_20_21, .CM_BLNDGAM_RAMA_REGION_22_23
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_22_23, .CM_BLNDGAM_RAMA_REGION_24_25
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_24_25, .CM_BLNDGAM_RAMA_REGION_26_27
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_26_27, .CM_BLNDGAM_RAMA_REGION_28_29
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_28_29, .CM_BLNDGAM_RAMA_REGION_30_31
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_30_31, .CM_BLNDGAM_RAMA_REGION_32_33
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_32_33, .CM_BLNDGAM_LUT_INDEX
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_INDEX_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_INDEX
, .CM_BLNDGAM_LUT_DATA = DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_DATA_BASE_IDX
+ mmCMid_CM_BLNDGAM_LUT_DATA, .CM_3DLUT_MODE = DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_MODE_BASE_IDX
+ mmCMid_CM_3DLUT_MODE, .CM_3DLUT_INDEX = DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_INDEX_BASE_IDX
+ mmCMid_CM_3DLUT_INDEX, .CM_3DLUT_DATA = DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_BASE_IDX
+ mmCMid_CM_3DLUT_DATA, .CM_3DLUT_DATA_30BIT = DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_30BIT_BASE_IDX
+ mmCMid_CM_3DLUT_DATA_30BIT, .CM_3DLUT_READ_WRITE_CONTROL =
DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX
+ mmCMid_CM_3DLUT_READ_WRITE_CONTROL, .CM_SHAPER_LUT_WRITE_EN_MASK
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX
+ mmCMid_CM_SHAPER_LUT_WRITE_EN_MASK, .CM_SHAPER_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_CONTROL_BASE_IDX
+ mmCMid_CM_SHAPER_CONTROL, .CM_SHAPER_RAMB_START_CNTL_B = DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_B, .CM_SHAPER_RAMB_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_G, .CM_SHAPER_RAMB_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_R, .CM_SHAPER_RAMB_END_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_B, .CM_SHAPER_RAMB_END_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_G, .CM_SHAPER_RAMB_END_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_R, .CM_SHAPER_RAMB_REGION_0_1
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_0_1, .CM_SHAPER_RAMB_REGION_2_3
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_2_3, .CM_SHAPER_RAMB_REGION_4_5
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_4_5, .CM_SHAPER_RAMB_REGION_6_7
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_6_7, .CM_SHAPER_RAMB_REGION_8_9
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_8_9, .CM_SHAPER_RAMB_REGION_10_11
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_10_11, .CM_SHAPER_RAMB_REGION_12_13
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_12_13, .CM_SHAPER_RAMB_REGION_14_15
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_14_15, .CM_SHAPER_RAMB_REGION_16_17
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_16_17, .CM_SHAPER_RAMB_REGION_18_19
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_18_19, .CM_SHAPER_RAMB_REGION_20_21
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_20_21, .CM_SHAPER_RAMB_REGION_22_23
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_22_23, .CM_SHAPER_RAMB_REGION_24_25
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_24_25, .CM_SHAPER_RAMB_REGION_26_27
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_26_27, .CM_SHAPER_RAMB_REGION_28_29
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_28_29, .CM_SHAPER_RAMB_REGION_30_31
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_30_31, .CM_SHAPER_RAMB_REGION_32_33
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_32_33, .CM_SHAPER_RAMA_START_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_B, .CM_SHAPER_RAMA_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_G, .CM_SHAPER_RAMA_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_R, .CM_SHAPER_RAMA_END_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_B, .CM_SHAPER_RAMA_END_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_G, .CM_SHAPER_RAMA_END_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_R, .CM_SHAPER_RAMA_REGION_0_1
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_0_1, .CM_SHAPER_RAMA_REGION_2_3
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_2_3, .CM_SHAPER_RAMA_REGION_4_5
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_4_5, .CM_SHAPER_RAMA_REGION_6_7
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_6_7, .CM_SHAPER_RAMA_REGION_8_9
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_8_9, .CM_SHAPER_RAMA_REGION_10_11
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_10_11, .CM_SHAPER_RAMA_REGION_12_13
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_12_13, .CM_SHAPER_RAMA_REGION_14_15
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_14_15, .CM_SHAPER_RAMA_REGION_16_17
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_16_17, .CM_SHAPER_RAMA_REGION_18_19
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_18_19, .CM_SHAPER_RAMA_REGION_20_21
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_20_21, .CM_SHAPER_RAMA_REGION_22_23
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_22_23, .CM_SHAPER_RAMA_REGION_24_25
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_24_25, .CM_SHAPER_RAMA_REGION_26_27
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_26_27, .CM_SHAPER_RAMA_REGION_28_29
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_28_29, .CM_SHAPER_RAMA_REGION_30_31
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_30_31, .CM_SHAPER_RAMA_REGION_32_33
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_32_33, .CM_SHAPER_LUT_INDEX =
DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_INDEX_BASE_IDX + mmCMid_CM_SHAPER_LUT_INDEX
, .CM_BLNDGAM_LUT_WRITE_EN_MASK = DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX
+ mmCMid_CM_BLNDGAM_LUT_WRITE_EN_MASK, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, .CM_BLNDGAM_RAMB_SLOPE_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, .CURSOR_CONTROL = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .ALPHA_2BIT_LUT = DMU_BASE__INST0_SEGmmCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX
+ mmCNVC_CFGid_ALPHA_2BIT_LUT, .FCNV_FP_BIAS_R = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_R, .FCNV_FP_BIAS_G = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_G, .FCNV_FP_BIAS_B = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_B, .FCNV_FP_SCALE_R = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_R, .FCNV_FP_SCALE_G = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_G, .FCNV_FP_SCALE_B = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_B, .COLOR_KEYER_CONTROL = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_CONTROL, .COLOR_KEYER_ALPHA = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_ALPHA, .COLOR_KEYER_RED = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_RED, .COLOR_KEYER_GREEN = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_GREEN, .COLOR_KEYER_BLUE = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_BLUE, .CM_SHAPER_LUT_DATA = DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_DATA_BASE_IDX
+ mmCMid_CM_SHAPER_LUT_DATA, .CURSOR_CONTROL = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .OBUF_MEM_PWR_CTRL = DMU_BASE__INST0_SEGmmDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_OBUF_MEM_PWR_CTRL, .DSCL_MEM_PWR_CTRL = DMU_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_DSCL_MEM_PWR_CTRL,}\
464[id] = {\
465 TF_REG_LIST_DCN201(id).CM_GAMUT_REMAP_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_CONTROL, .CM_GAMUT_REMAP_C11_C12 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C11_C12, .CM_GAMUT_REMAP_C13_C14 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C13_C14, .CM_GAMUT_REMAP_C21_C22 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C21_C22, .CM_GAMUT_REMAP_C23_C24 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C23_C24, .CM_GAMUT_REMAP_C31_C32 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C31_C32, .CM_GAMUT_REMAP_C33_C34 = DMU_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX
+ mmCMid_CM_GAMUT_REMAP_C33_C34, .DSCL_EXT_OVERSCAN_LEFT_RIGHT
= DMU_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX
+ mmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, .DSCL_EXT_OVERSCAN_TOP_BOTTOM
= DMU_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX
+ mmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, .DSCL_MEM_PWR_STATUS
= DMU_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_STATUS_BASE_IDX +
mmDSCLid_DSCL_MEM_PWR_STATUS, .DSCL_MEM_PWR_CTRL = DMU_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_DSCL_MEM_PWR_CTRL, .OTG_H_BLANK = DMU_BASE__INST0_SEGmmDSCLid_OTG_H_BLANK_BASE_IDX
+ mmDSCLid_OTG_H_BLANK, .OTG_V_BLANK = DMU_BASE__INST0_SEGmmDSCLid_OTG_V_BLANK_BASE_IDX
+ mmDSCLid_OTG_V_BLANK, .SCL_MODE = DMU_BASE__INST0_SEGmmDSCLid_SCL_MODE_BASE_IDX
+ mmDSCLid_SCL_MODE, .LB_DATA_FORMAT = DMU_BASE__INST0_SEGmmDSCLid_LB_DATA_FORMAT_BASE_IDX
+ mmDSCLid_LB_DATA_FORMAT, .LB_MEMORY_CTRL = DMU_BASE__INST0_SEGmmDSCLid_LB_MEMORY_CTRL_BASE_IDX
+ mmDSCLid_LB_MEMORY_CTRL, .DSCL_AUTOCAL = DMU_BASE__INST0_SEGmmDSCLid_DSCL_AUTOCAL_BASE_IDX
+ mmDSCLid_DSCL_AUTOCAL, .SCL_BLACK_OFFSET = DMU_BASE__INST0_SEGmmDSCLid_SCL_BLACK_OFFSET_BASE_IDX
+ mmDSCLid_SCL_BLACK_OFFSET, .SCL_TAP_CONTROL = DMU_BASE__INST0_SEGmmDSCLid_SCL_TAP_CONTROL_BASE_IDX
+ mmDSCLid_SCL_TAP_CONTROL, .SCL_COEF_RAM_TAP_SELECT = DMU_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX
+ mmDSCLid_SCL_COEF_RAM_TAP_SELECT, .SCL_COEF_RAM_TAP_DATA =
DMU_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX +
mmDSCLid_SCL_COEF_RAM_TAP_DATA, .DSCL_2TAP_CONTROL = DMU_BASE__INST0_SEGmmDSCLid_DSCL_2TAP_CONTROL_BASE_IDX
+ mmDSCLid_DSCL_2TAP_CONTROL, .MPC_SIZE = DMU_BASE__INST0_SEGmmDSCLid_MPC_SIZE_BASE_IDX
+ mmDSCLid_MPC_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO = DMU_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO
= DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_SCALE_RATIO_C
= DMU_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C, .SCL_VERT_FILTER_SCALE_RATIO_C
= DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C, .SCL_HORZ_FILTER_INIT
= DMU_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX +
mmDSCLid_SCL_HORZ_FILTER_INIT, .SCL_HORZ_FILTER_INIT_C = DMU_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX
+ mmDSCLid_SCL_HORZ_FILTER_INIT_C, .SCL_VERT_FILTER_INIT = DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT, .SCL_VERT_FILTER_INIT_BOT =
DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BOT_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT_BOT, .SCL_VERT_FILTER_INIT_C
= DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT_C, .SCL_VERT_FILTER_INIT_BOT_C
= DMU_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX
+ mmDSCLid_SCL_VERT_FILTER_INIT_BOT_C, .RECOUT_START = DMU_BASE__INST0_SEGmmDSCLid_RECOUT_START_BASE_IDX
+ mmDSCLid_RECOUT_START, .RECOUT_SIZE = DMU_BASE__INST0_SEGmmDSCLid_RECOUT_SIZE_BASE_IDX
+ mmDSCLid_RECOUT_SIZE, .CM_ICSC_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_ICSC_CONTROL_BASE_IDX
+ mmCMid_CM_ICSC_CONTROL, .CM_ICSC_C11_C12 = DMU_BASE__INST0_SEGmmCMid_CM_ICSC_C11_C12_BASE_IDX
+ mmCMid_CM_ICSC_C11_C12, .CM_ICSC_C33_C34 = DMU_BASE__INST0_SEGmmCMid_CM_ICSC_C33_C34_BASE_IDX
+ mmCMid_CM_ICSC_C33_C34, .CM_DGAM_RAMB_START_CNTL_B = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_START_CNTL_B, .CM_DGAM_RAMB_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_START_CNTL_G, .CM_DGAM_RAMB_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_START_CNTL_R, .CM_DGAM_RAMB_SLOPE_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_B, .CM_DGAM_RAMB_SLOPE_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_G, .CM_DGAM_RAMB_SLOPE_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_R, .CM_DGAM_RAMB_END_CNTL1_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL1_B, .CM_DGAM_RAMB_END_CNTL2_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL2_B, .CM_DGAM_RAMB_END_CNTL1_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL1_G, .CM_DGAM_RAMB_END_CNTL2_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL2_G, .CM_DGAM_RAMB_END_CNTL1_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL1_R, .CM_DGAM_RAMB_END_CNTL2_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_END_CNTL2_R, .CM_DGAM_RAMB_REGION_0_1 =
DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_REGION_0_1_BASE_IDX +
mmCMid_CM_DGAM_RAMB_REGION_0_1, .CM_DGAM_RAMB_REGION_14_15 =
DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_DGAM_RAMB_REGION_14_15, .CM_DGAM_RAMA_START_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_START_CNTL_B, .CM_DGAM_RAMA_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_START_CNTL_G, .CM_DGAM_RAMA_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_START_CNTL_R, .CM_DGAM_RAMA_SLOPE_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_B, .CM_DGAM_RAMA_SLOPE_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_G, .CM_DGAM_RAMA_SLOPE_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_R, .CM_DGAM_RAMA_END_CNTL1_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL1_B, .CM_DGAM_RAMA_END_CNTL2_B
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL2_B, .CM_DGAM_RAMA_END_CNTL1_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL1_G, .CM_DGAM_RAMA_END_CNTL2_G
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL2_G, .CM_DGAM_RAMA_END_CNTL1_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL1_R, .CM_DGAM_RAMA_END_CNTL2_R
= DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_END_CNTL2_R, .CM_DGAM_RAMA_REGION_0_1 =
DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_REGION_0_1_BASE_IDX +
mmCMid_CM_DGAM_RAMA_REGION_0_1, .CM_DGAM_RAMA_REGION_14_15 =
DMU_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_DGAM_RAMA_REGION_14_15, .CM_MEM_PWR_CTRL = DMU_BASE__INST0_SEGmmCMid_CM_MEM_PWR_CTRL_BASE_IDX
+ mmCMid_CM_MEM_PWR_CTRL, .CM_DGAM_LUT_WRITE_EN_MASK = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX
+ mmCMid_CM_DGAM_LUT_WRITE_EN_MASK, .CM_DGAM_LUT_INDEX = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_INDEX_BASE_IDX
+ mmCMid_CM_DGAM_LUT_INDEX, .CM_DGAM_LUT_DATA = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_DATA_BASE_IDX
+ mmCMid_CM_DGAM_LUT_DATA, .CM_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_CONTROL_BASE_IDX
+ mmCMid_CM_CONTROL, .CM_DGAM_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_DGAM_CONTROL_BASE_IDX
+ mmCMid_CM_DGAM_CONTROL, .CM_TEST_DEBUG_INDEX = DMU_BASE__INST0_SEGmmCMid_CM_TEST_DEBUG_INDEX_BASE_IDX
+ mmCMid_CM_TEST_DEBUG_INDEX, .CM_TEST_DEBUG_DATA = DMU_BASE__INST0_SEGmmCMid_CM_TEST_DEBUG_DATA_BASE_IDX
+ mmCMid_CM_TEST_DEBUG_DATA, .FORMAT_CONTROL = DMU_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX
+ mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DMU_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX
+ mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL =
DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL
, .CURSOR0_COLOR0 = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX
+ mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR0_FP_SCALE_BIAS = DMU_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX
+ mmCNVC_CURid_CURSOR0_FP_SCALE_BIAS, .DPP_CONTROL = DMU_BASE__INST0_SEGmmDPP_TOPid_DPP_CONTROL_BASE_IDX
+ mmDPP_TOPid_DPP_CONTROL, .CM_HDR_MULT_COEF = DMU_BASE__INST0_SEGmmCMid_CM_HDR_MULT_COEF_BASE_IDX
+ mmCMid_CM_HDR_MULT_COEF, .CM_BLNDGAM_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_CONTROL_BASE_IDX
+ mmCMid_CM_BLNDGAM_CONTROL, .CM_BLNDGAM_RAMB_START_CNTL_B =
DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_B, .CM_BLNDGAM_RAMB_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_G, .CM_BLNDGAM_RAMB_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_START_CNTL_R, .CM_BLNDGAM_RAMB_END_CNTL1_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B, .CM_BLNDGAM_RAMB_END_CNTL2_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B, .CM_BLNDGAM_RAMB_END_CNTL1_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G, .CM_BLNDGAM_RAMB_END_CNTL2_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G, .CM_BLNDGAM_RAMB_END_CNTL1_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R, .CM_BLNDGAM_RAMB_END_CNTL2_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R, .CM_BLNDGAM_RAMB_REGION_0_1
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_0_1, .CM_BLNDGAM_RAMB_REGION_2_3
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_2_3, .CM_BLNDGAM_RAMB_REGION_4_5
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_4_5, .CM_BLNDGAM_RAMB_REGION_6_7
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_6_7, .CM_BLNDGAM_RAMB_REGION_8_9
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_8_9, .CM_BLNDGAM_RAMB_REGION_10_11
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_10_11, .CM_BLNDGAM_RAMB_REGION_12_13
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_12_13, .CM_BLNDGAM_RAMB_REGION_14_15
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_14_15, .CM_BLNDGAM_RAMB_REGION_16_17
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_16_17, .CM_BLNDGAM_RAMB_REGION_18_19
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_18_19, .CM_BLNDGAM_RAMB_REGION_20_21
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_20_21, .CM_BLNDGAM_RAMB_REGION_22_23
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_22_23, .CM_BLNDGAM_RAMB_REGION_24_25
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_24_25, .CM_BLNDGAM_RAMB_REGION_26_27
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_26_27, .CM_BLNDGAM_RAMB_REGION_28_29
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_28_29, .CM_BLNDGAM_RAMB_REGION_30_31
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_30_31, .CM_BLNDGAM_RAMB_REGION_32_33
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_REGION_32_33, .CM_BLNDGAM_RAMA_START_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_B, .CM_BLNDGAM_RAMA_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_G, .CM_BLNDGAM_RAMA_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_START_CNTL_R, .CM_BLNDGAM_RAMA_END_CNTL1_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B, .CM_BLNDGAM_RAMA_END_CNTL2_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B, .CM_BLNDGAM_RAMA_END_CNTL1_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G, .CM_BLNDGAM_RAMA_END_CNTL2_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G, .CM_BLNDGAM_RAMA_END_CNTL1_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R, .CM_BLNDGAM_RAMA_END_CNTL2_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R, .CM_BLNDGAM_RAMA_REGION_0_1
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_0_1, .CM_BLNDGAM_RAMA_REGION_2_3
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_2_3, .CM_BLNDGAM_RAMA_REGION_4_5
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_4_5, .CM_BLNDGAM_RAMA_REGION_6_7
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_6_7, .CM_BLNDGAM_RAMA_REGION_8_9
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_8_9, .CM_BLNDGAM_RAMA_REGION_10_11
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_10_11, .CM_BLNDGAM_RAMA_REGION_12_13
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_12_13, .CM_BLNDGAM_RAMA_REGION_14_15
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_14_15, .CM_BLNDGAM_RAMA_REGION_16_17
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_16_17, .CM_BLNDGAM_RAMA_REGION_18_19
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_18_19, .CM_BLNDGAM_RAMA_REGION_20_21
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_20_21, .CM_BLNDGAM_RAMA_REGION_22_23
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_22_23, .CM_BLNDGAM_RAMA_REGION_24_25
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_24_25, .CM_BLNDGAM_RAMA_REGION_26_27
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_26_27, .CM_BLNDGAM_RAMA_REGION_28_29
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_28_29, .CM_BLNDGAM_RAMA_REGION_30_31
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_30_31, .CM_BLNDGAM_RAMA_REGION_32_33
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_REGION_32_33, .CM_BLNDGAM_LUT_INDEX
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_INDEX_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_INDEX
, .CM_BLNDGAM_LUT_DATA = DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_DATA_BASE_IDX
+ mmCMid_CM_BLNDGAM_LUT_DATA, .CM_3DLUT_MODE = DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_MODE_BASE_IDX
+ mmCMid_CM_3DLUT_MODE, .CM_3DLUT_INDEX = DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_INDEX_BASE_IDX
+ mmCMid_CM_3DLUT_INDEX, .CM_3DLUT_DATA = DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_BASE_IDX
+ mmCMid_CM_3DLUT_DATA, .CM_3DLUT_DATA_30BIT = DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_30BIT_BASE_IDX
+ mmCMid_CM_3DLUT_DATA_30BIT, .CM_3DLUT_READ_WRITE_CONTROL =
DMU_BASE__INST0_SEGmmCMid_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX
+ mmCMid_CM_3DLUT_READ_WRITE_CONTROL, .CM_SHAPER_LUT_WRITE_EN_MASK
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX
+ mmCMid_CM_SHAPER_LUT_WRITE_EN_MASK, .CM_SHAPER_CONTROL = DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_CONTROL_BASE_IDX
+ mmCMid_CM_SHAPER_CONTROL, .CM_SHAPER_RAMB_START_CNTL_B = DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_B, .CM_SHAPER_RAMB_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_G, .CM_SHAPER_RAMB_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_START_CNTL_R, .CM_SHAPER_RAMB_END_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_B, .CM_SHAPER_RAMB_END_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_G, .CM_SHAPER_RAMB_END_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_END_CNTL_R, .CM_SHAPER_RAMB_REGION_0_1
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_0_1, .CM_SHAPER_RAMB_REGION_2_3
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_2_3, .CM_SHAPER_RAMB_REGION_4_5
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_4_5, .CM_SHAPER_RAMB_REGION_6_7
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_6_7, .CM_SHAPER_RAMB_REGION_8_9
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_8_9, .CM_SHAPER_RAMB_REGION_10_11
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_10_11, .CM_SHAPER_RAMB_REGION_12_13
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_12_13, .CM_SHAPER_RAMB_REGION_14_15
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_14_15, .CM_SHAPER_RAMB_REGION_16_17
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_16_17, .CM_SHAPER_RAMB_REGION_18_19
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_18_19, .CM_SHAPER_RAMB_REGION_20_21
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_20_21, .CM_SHAPER_RAMB_REGION_22_23
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_22_23, .CM_SHAPER_RAMB_REGION_24_25
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_24_25, .CM_SHAPER_RAMB_REGION_26_27
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_26_27, .CM_SHAPER_RAMB_REGION_28_29
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_28_29, .CM_SHAPER_RAMB_REGION_30_31
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_30_31, .CM_SHAPER_RAMB_REGION_32_33
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX
+ mmCMid_CM_SHAPER_RAMB_REGION_32_33, .CM_SHAPER_RAMA_START_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_B, .CM_SHAPER_RAMA_START_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_G, .CM_SHAPER_RAMA_START_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_START_CNTL_R, .CM_SHAPER_RAMA_END_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_B, .CM_SHAPER_RAMA_END_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_G, .CM_SHAPER_RAMA_END_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_END_CNTL_R, .CM_SHAPER_RAMA_REGION_0_1
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_0_1, .CM_SHAPER_RAMA_REGION_2_3
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_2_3, .CM_SHAPER_RAMA_REGION_4_5
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_4_5, .CM_SHAPER_RAMA_REGION_6_7
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_6_7, .CM_SHAPER_RAMA_REGION_8_9
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_8_9, .CM_SHAPER_RAMA_REGION_10_11
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_10_11, .CM_SHAPER_RAMA_REGION_12_13
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_12_13, .CM_SHAPER_RAMA_REGION_14_15
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_14_15, .CM_SHAPER_RAMA_REGION_16_17
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_16_17, .CM_SHAPER_RAMA_REGION_18_19
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_18_19, .CM_SHAPER_RAMA_REGION_20_21
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_20_21, .CM_SHAPER_RAMA_REGION_22_23
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_22_23, .CM_SHAPER_RAMA_REGION_24_25
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_24_25, .CM_SHAPER_RAMA_REGION_26_27
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_26_27, .CM_SHAPER_RAMA_REGION_28_29
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_28_29, .CM_SHAPER_RAMA_REGION_30_31
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_30_31, .CM_SHAPER_RAMA_REGION_32_33
= DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX
+ mmCMid_CM_SHAPER_RAMA_REGION_32_33, .CM_SHAPER_LUT_INDEX =
DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_INDEX_BASE_IDX + mmCMid_CM_SHAPER_LUT_INDEX
, .CM_BLNDGAM_LUT_WRITE_EN_MASK = DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX
+ mmCMid_CM_BLNDGAM_LUT_WRITE_EN_MASK, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, .CM_BLNDGAM_RAMB_SLOPE_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R
= DMU_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX
+ mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, .CURSOR_CONTROL = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .ALPHA_2BIT_LUT = DMU_BASE__INST0_SEGmmCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX
+ mmCNVC_CFGid_ALPHA_2BIT_LUT, .FCNV_FP_BIAS_R = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_R, .FCNV_FP_BIAS_G = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_G, .FCNV_FP_BIAS_B = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_BIAS_B, .FCNV_FP_SCALE_R = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_R, .FCNV_FP_SCALE_G = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_G, .FCNV_FP_SCALE_B = DMU_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX
+ mmCNVC_CFGid_FCNV_FP_SCALE_B, .COLOR_KEYER_CONTROL = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_CONTROL, .COLOR_KEYER_ALPHA = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_ALPHA, .COLOR_KEYER_RED = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_RED, .COLOR_KEYER_GREEN = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_GREEN, .COLOR_KEYER_BLUE = DMU_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX
+ mmCNVC_CFGid_COLOR_KEYER_BLUE, .CM_SHAPER_LUT_DATA = DMU_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_DATA_BASE_IDX
+ mmCMid_CM_SHAPER_LUT_DATA, .CURSOR_CONTROL = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .OBUF_MEM_PWR_CTRL = DMU_BASE__INST0_SEGmmDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_OBUF_MEM_PWR_CTRL, .DSCL_MEM_PWR_CTRL = DMU_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX
+ mmDSCLid_DSCL_MEM_PWR_CTRL,\
466}
467
468static const struct dcn201_dpp_registers tf_regs[] = {
469 tf_regs(0)[0] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x0d28, .CM_GAMUT_REMAP_C11_C12
= 0x000034C0 + 0x0d29, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 +
0x0d2a, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x0d2b, .CM_GAMUT_REMAP_C23_C24
= 0x000034C0 + 0x0d2c, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 +
0x0d2d, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x0d2e, .DSCL_EXT_OVERSCAN_LEFT_RIGHT
= 0x000034C0 + 0x0cfe, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0
+ 0x0cff, .DSCL_MEM_PWR_STATUS = 0x000034C0 + 0x0d09, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x0d08, .OTG_H_BLANK = 0x000034C0 + 0x0d00, .
OTG_V_BLANK = 0x000034C0 + 0x0d01, .SCL_MODE = 0x000034C0 + 0x0cec
, .LB_DATA_FORMAT = 0x000034C0 + 0x0d05, .LB_MEMORY_CTRL = 0x000034C0
+ 0x0d06, .DSCL_AUTOCAL = 0x000034C0 + 0x0cfd, .SCL_BLACK_OFFSET
= 0x000034C0 + 0x0cfb, .SCL_TAP_CONTROL = 0x000034C0 + 0x0ced
, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0cea, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x0ceb, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0cef
, .MPC_SIZE = 0x000034C0 + 0x0d04, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x0cf1, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x0cf5, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0cf3
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0cf8, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x0cf2, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x0cf4, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0cf6, .SCL_VERT_FILTER_INIT_BOT
= 0x000034C0 + 0x0cf7, .SCL_VERT_FILTER_INIT_C = 0x000034C0 +
0x0cf9, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x0cfa, .
RECOUT_START = 0x000034C0 + 0x0d02, .RECOUT_SIZE = 0x000034C0
+ 0x0d03, .CM_ICSC_CONTROL = 0x000034C0 + 0x0d1b, .CM_ICSC_C11_C12
= 0x000034C0 + 0x0d1c, .CM_ICSC_C33_C34 = 0x000034C0 + 0x0d21
, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0d4f, .CM_DGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x0d50, .CM_DGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x0d51, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x0d52, .
CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x0d53, .CM_DGAM_RAMB_SLOPE_CNTL_R
= 0x000034C0 + 0x0d54, .CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0
+ 0x0d55, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0d56, .
CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x0d57, .CM_DGAM_RAMB_END_CNTL2_G
= 0x000034C0 + 0x0d58, .CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0
+ 0x0d59, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0d5a, .
CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x0d5b, .CM_DGAM_RAMB_REGION_14_15
= 0x000034C0 + 0x0d62, .CM_DGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x0d3b, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0d3c, .
CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0d3d, .CM_DGAM_RAMA_SLOPE_CNTL_B
= 0x000034C0 + 0x0d3e, .CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0
+ 0x0d3f, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x0d40, .
CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x0d41, .CM_DGAM_RAMA_END_CNTL2_B
= 0x000034C0 + 0x0d42, .CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0
+ 0x0d43, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0d44, .
CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x0d45, .CM_DGAM_RAMA_END_CNTL2_R
= 0x000034C0 + 0x0d46, .CM_DGAM_RAMA_REGION_0_1 = 0x000034C0
+ 0x0d47, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0d4e, .
CM_MEM_PWR_CTRL = 0x000034C0 + 0x0da2, .CM_DGAM_LUT_WRITE_EN_MASK
= 0x000034C0 + 0x0d3a, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x0d38
, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x0d39, .CM_CONTROL = 0x000034C0
+ 0x0d1a, .CM_DGAM_CONTROL = 0x000034C0 + 0x0d37, .CM_TEST_DEBUG_INDEX
= 0x000034C0 + 0x0de9, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x0dea
, .FORMAT_CONTROL = 0x000034C0 + 0x0cd0, .CNVC_SURFACE_PIXEL_FORMAT
= 0x000034C0 + 0x0ccf, .CURSOR0_CONTROL = 0x000034C0 + 0x0ce0
, .CURSOR0_COLOR0 = 0x000034C0 + 0x0ce1, .CURSOR0_COLOR1 = 0x000034C0
+ 0x0ce2, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0ce3, .DPP_CONTROL
= 0x000034C0 + 0x0cc5, .CM_HDR_MULT_COEF = 0x000034C0 + 0x0da1
, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0d63, .CM_BLNDGAM_RAMB_START_CNTL_B
= 0x000034C0 + 0x0d84, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0
+ 0x0d85, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x0d86
, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0d8a, .CM_BLNDGAM_RAMB_END_CNTL2_B
= 0x000034C0 + 0x0d8b, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0
+ 0x0d8c, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x0d8d
, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0d8e, .CM_BLNDGAM_RAMB_END_CNTL2_R
= 0x000034C0 + 0x0d8f, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0
+ 0x0d90, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x0d91,
.CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x0d92, .CM_BLNDGAM_RAMB_REGION_6_7
= 0x000034C0 + 0x0d93, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0
+ 0x0d94, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x0d95
, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x0d96, .CM_BLNDGAM_RAMB_REGION_14_15
= 0x000034C0 + 0x0d97, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0
+ 0x0d98, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x0d99
, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x0d9a, .CM_BLNDGAM_RAMB_REGION_22_23
= 0x000034C0 + 0x0d9b, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0
+ 0x0d9c, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x0d9d
, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x0d9e, .CM_BLNDGAM_RAMB_REGION_30_31
= 0x000034C0 + 0x0d9f, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0
+ 0x0da0, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x0d67
, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0d68, .CM_BLNDGAM_RAMA_START_CNTL_R
= 0x000034C0 + 0x0d69, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0
+ 0x0d6d, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x0d6e
, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0d6f, .CM_BLNDGAM_RAMA_END_CNTL2_G
= 0x000034C0 + 0x0d70, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0
+ 0x0d71, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x0d72
, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0d73, .CM_BLNDGAM_RAMA_REGION_2_3
= 0x000034C0 + 0x0d74, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0
+ 0x0d75, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x0d76,
.CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x0d77, .CM_BLNDGAM_RAMA_REGION_10_11
= 0x000034C0 + 0x0d78, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0
+ 0x0d79, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0d7a
, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x0d7b, .CM_BLNDGAM_RAMA_REGION_18_19
= 0x000034C0 + 0x0d7c, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0
+ 0x0d7d, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x0d7e
, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x0d7f, .CM_BLNDGAM_RAMA_REGION_26_27
= 0x000034C0 + 0x0d80, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0
+ 0x0d81, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x0d82
, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x0d83, .CM_BLNDGAM_LUT_INDEX
= 0x000034C0 + 0x0d64, .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x0d65
, .CM_3DLUT_MODE = 0x000034C0 + 0x0de0, .CM_3DLUT_INDEX = 0x000034C0
+ 0x0de1, .CM_3DLUT_DATA = 0x000034C0 + 0x0de2, .CM_3DLUT_DATA_30BIT
= 0x000034C0 + 0x0de3, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0
+ 0x0de4, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0daf
, .CM_SHAPER_CONTROL = 0x000034C0 + 0x0da7, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x0dc7, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x0dc8, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x0dc9
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x0dca, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x0dcb, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x0dcc, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x0dcd, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x0dce, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x0dcf, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x0dd0, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x0dd1, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x0dd2, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x0dd3, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x0dd4, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x0dd5
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x0dd6, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x0dd7, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x0dd8, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x0dd9
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x0dda, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x0ddb, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x0ddc, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x0ddd
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x0db0, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x0db1, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x0db2, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x0db3, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x0db4, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x0db5, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x0db6, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x0db7, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x0db8, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x0db9, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x0dba, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x0dbb
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x0dbc, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x0dbd, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x0dbe, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x0dbf
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x0dc0, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x0dc1, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x0dc2, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x0dc3
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x0dc4, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x0dc5, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x0dc6, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x0dad, .CM_BLNDGAM_LUT_WRITE_EN_MASK
= 0x000034C0 + 0x0d66, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0
+ 0x0d87, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x0d88
, .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x0d89, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B
= 0x000034C0 + 0x0d6a, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0
+ 0x0d6b, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x0d6c
, .CURSOR_CONTROL = 0x000034C0 + 0x0678, .ALPHA_2BIT_LUT = 0x000034C0
+ 0x0cdd, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0cd1, .FCNV_FP_BIAS_G
= 0x000034C0 + 0x0cd2, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0cd3
, .FCNV_FP_SCALE_R = 0x000034C0 + 0x0cd4, .FCNV_FP_SCALE_G = 0x000034C0
+ 0x0cd5, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0cd6, .COLOR_KEYER_CONTROL
= 0x000034C0 + 0x0cd7, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0cd8
, .COLOR_KEYER_RED = 0x000034C0 + 0x0cd9, .COLOR_KEYER_GREEN =
0x000034C0 + 0x0cda, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0cdb
, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x0dae, .CURSOR_CONTROL =
0x000034C0 + 0x0678, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0d0b
, .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0d08,},
470 tf_regs(1)[1] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x0e93, .CM_GAMUT_REMAP_C11_C12
= 0x000034C0 + 0x0e94, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 +
0x0e95, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x0e96, .CM_GAMUT_REMAP_C23_C24
= 0x000034C0 + 0x0e97, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 +
0x0e98, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x0e99, .DSCL_EXT_OVERSCAN_LEFT_RIGHT
= 0x000034C0 + 0x0e69, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0
+ 0x0e6a, .DSCL_MEM_PWR_STATUS = 0x000034C0 + 0x0e74, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x0e73, .OTG_H_BLANK = 0x000034C0 + 0x0e6b, .
OTG_V_BLANK = 0x000034C0 + 0x0e6c, .SCL_MODE = 0x000034C0 + 0x0e57
, .LB_DATA_FORMAT = 0x000034C0 + 0x0e70, .LB_MEMORY_CTRL = 0x000034C0
+ 0x0e71, .DSCL_AUTOCAL = 0x000034C0 + 0x0e68, .SCL_BLACK_OFFSET
= 0x000034C0 + 0x0e66, .SCL_TAP_CONTROL = 0x000034C0 + 0x0e58
, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0e55, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x0e56, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0e5a
, .MPC_SIZE = 0x000034C0 + 0x0e6f, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x0e5c, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x0e60, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0e5e
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0e63, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x0e5d, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x0e5f, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0e61, .SCL_VERT_FILTER_INIT_BOT
= 0x000034C0 + 0x0e62, .SCL_VERT_FILTER_INIT_C = 0x000034C0 +
0x0e64, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x0e65, .
RECOUT_START = 0x000034C0 + 0x0e6d, .RECOUT_SIZE = 0x000034C0
+ 0x0e6e, .CM_ICSC_CONTROL = 0x000034C0 + 0x0e86, .CM_ICSC_C11_C12
= 0x000034C0 + 0x0e87, .CM_ICSC_C33_C34 = 0x000034C0 + 0x0e8c
, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0eba, .CM_DGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x0ebb, .CM_DGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x0ebc, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x0ebd, .
CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x0ebe, .CM_DGAM_RAMB_SLOPE_CNTL_R
= 0x000034C0 + 0x0ebf, .CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0
+ 0x0ec0, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0ec1, .
CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x0ec2, .CM_DGAM_RAMB_END_CNTL2_G
= 0x000034C0 + 0x0ec3, .CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0
+ 0x0ec4, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0ec5, .
CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x0ec6, .CM_DGAM_RAMB_REGION_14_15
= 0x000034C0 + 0x0ecd, .CM_DGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x0ea6, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0ea7, .
CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0ea8, .CM_DGAM_RAMA_SLOPE_CNTL_B
= 0x000034C0 + 0x0ea9, .CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0
+ 0x0eaa, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x0eab, .
CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x0eac, .CM_DGAM_RAMA_END_CNTL2_B
= 0x000034C0 + 0x0ead, .CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0
+ 0x0eae, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0eaf, .
CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x0eb0, .CM_DGAM_RAMA_END_CNTL2_R
= 0x000034C0 + 0x0eb1, .CM_DGAM_RAMA_REGION_0_1 = 0x000034C0
+ 0x0eb2, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0eb9, .
CM_MEM_PWR_CTRL = 0x000034C0 + 0x0f0d, .CM_DGAM_LUT_WRITE_EN_MASK
= 0x000034C0 + 0x0ea5, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x0ea3
, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x0ea4, .CM_CONTROL = 0x000034C0
+ 0x0e85, .CM_DGAM_CONTROL = 0x000034C0 + 0x0ea2, .CM_TEST_DEBUG_INDEX
= 0x000034C0 + 0x0f54, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x0f55
, .FORMAT_CONTROL = 0x000034C0 + 0x0e3b, .CNVC_SURFACE_PIXEL_FORMAT
= 0x000034C0 + 0x0e3a, .CURSOR0_CONTROL = 0x000034C0 + 0x0e4b
, .CURSOR0_COLOR0 = 0x000034C0 + 0x0e4c, .CURSOR0_COLOR1 = 0x000034C0
+ 0x0e4d, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0e4e, .DPP_CONTROL
= 0x000034C0 + 0x0e30, .CM_HDR_MULT_COEF = 0x000034C0 + 0x0f0c
, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0ece, .CM_BLNDGAM_RAMB_START_CNTL_B
= 0x000034C0 + 0x0eef, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0
+ 0x0ef0, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x0ef1
, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0ef5, .CM_BLNDGAM_RAMB_END_CNTL2_B
= 0x000034C0 + 0x0ef6, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0
+ 0x0ef7, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x0ef8
, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0ef9, .CM_BLNDGAM_RAMB_END_CNTL2_R
= 0x000034C0 + 0x0efa, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0
+ 0x0efb, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x0efc,
.CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x0efd, .CM_BLNDGAM_RAMB_REGION_6_7
= 0x000034C0 + 0x0efe, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0
+ 0x0eff, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x0f00
, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x0f01, .CM_BLNDGAM_RAMB_REGION_14_15
= 0x000034C0 + 0x0f02, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0
+ 0x0f03, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x0f04
, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x0f05, .CM_BLNDGAM_RAMB_REGION_22_23
= 0x000034C0 + 0x0f06, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0
+ 0x0f07, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x0f08
, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x0f09, .CM_BLNDGAM_RAMB_REGION_30_31
= 0x000034C0 + 0x0f0a, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0
+ 0x0f0b, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x0ed2
, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0ed3, .CM_BLNDGAM_RAMA_START_CNTL_R
= 0x000034C0 + 0x0ed4, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0
+ 0x0ed8, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x0ed9
, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0eda, .CM_BLNDGAM_RAMA_END_CNTL2_G
= 0x000034C0 + 0x0edb, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0
+ 0x0edc, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x0edd
, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0ede, .CM_BLNDGAM_RAMA_REGION_2_3
= 0x000034C0 + 0x0edf, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0
+ 0x0ee0, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x0ee1,
.CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x0ee2, .CM_BLNDGAM_RAMA_REGION_10_11
= 0x000034C0 + 0x0ee3, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0
+ 0x0ee4, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0ee5
, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x0ee6, .CM_BLNDGAM_RAMA_REGION_18_19
= 0x000034C0 + 0x0ee7, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0
+ 0x0ee8, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x0ee9
, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x0eea, .CM_BLNDGAM_RAMA_REGION_26_27
= 0x000034C0 + 0x0eeb, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0
+ 0x0eec, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x0eed
, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x0eee, .CM_BLNDGAM_LUT_INDEX
= 0x000034C0 + 0x0ecf, .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x0ed0
, .CM_3DLUT_MODE = 0x000034C0 + 0x0f4b, .CM_3DLUT_INDEX = 0x000034C0
+ 0x0f4c, .CM_3DLUT_DATA = 0x000034C0 + 0x0f4d, .CM_3DLUT_DATA_30BIT
= 0x000034C0 + 0x0f4e, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0
+ 0x0f4f, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0f1a
, .CM_SHAPER_CONTROL = 0x000034C0 + 0x0f12, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x0f32, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x0f33, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x0f34
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x0f35, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x0f36, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x0f37, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x0f38, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x0f39, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x0f3a, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x0f3b, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x0f3c, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x0f3d, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x0f3e, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x0f3f, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x0f40
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x0f41, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x0f42, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x0f43, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x0f44
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x0f45, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x0f46, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x0f47, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x0f48
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x0f1b, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x0f1c, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x0f1d, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x0f1e, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x0f1f, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x0f20, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x0f21, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x0f22, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x0f23, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x0f24, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x0f25, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x0f26
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x0f27, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x0f28, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x0f29, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x0f2a
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x0f2b, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x0f2c, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x0f2d, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x0f2e
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x0f2f, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x0f30, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x0f31, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x0f18, .CM_BLNDGAM_LUT_WRITE_EN_MASK
= 0x000034C0 + 0x0ed1, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0
+ 0x0ef2, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x0ef3
, .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x0ef4, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B
= 0x000034C0 + 0x0ed5, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0
+ 0x0ed6, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x0ed7
, .CURSOR_CONTROL = 0x000034C0 + 0x0754, .ALPHA_2BIT_LUT = 0x000034C0
+ 0x0e48, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0e3c, .FCNV_FP_BIAS_G
= 0x000034C0 + 0x0e3d, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0e3e
, .FCNV_FP_SCALE_R = 0x000034C0 + 0x0e3f, .FCNV_FP_SCALE_G = 0x000034C0
+ 0x0e40, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0e41, .COLOR_KEYER_CONTROL
= 0x000034C0 + 0x0e42, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0e43
, .COLOR_KEYER_RED = 0x000034C0 + 0x0e44, .COLOR_KEYER_GREEN =
0x000034C0 + 0x0e45, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0e46
, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x0f19, .CURSOR_CONTROL =
0x000034C0 + 0x0754, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0e76
, .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0e73,},
471 tf_regs(2)[2] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x0ffe, .CM_GAMUT_REMAP_C11_C12
= 0x000034C0 + 0x0fff, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 +
0x1000, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x1001, .CM_GAMUT_REMAP_C23_C24
= 0x000034C0 + 0x1002, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 +
0x1003, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x1004, .DSCL_EXT_OVERSCAN_LEFT_RIGHT
= 0x000034C0 + 0x0fd4, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0
+ 0x0fd5, .DSCL_MEM_PWR_STATUS = 0x000034C0 + 0x0fdf, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x0fde, .OTG_H_BLANK = 0x000034C0 + 0x0fd6, .
OTG_V_BLANK = 0x000034C0 + 0x0fd7, .SCL_MODE = 0x000034C0 + 0x0fc2
, .LB_DATA_FORMAT = 0x000034C0 + 0x0fdb, .LB_MEMORY_CTRL = 0x000034C0
+ 0x0fdc, .DSCL_AUTOCAL = 0x000034C0 + 0x0fd3, .SCL_BLACK_OFFSET
= 0x000034C0 + 0x0fd1, .SCL_TAP_CONTROL = 0x000034C0 + 0x0fc3
, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0fc0, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x0fc1, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0fc5
, .MPC_SIZE = 0x000034C0 + 0x0fda, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x0fc7, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x0fcb, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0fc9
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0fce, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x0fc8, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x0fca, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0fcc, .SCL_VERT_FILTER_INIT_BOT
= 0x000034C0 + 0x0fcd, .SCL_VERT_FILTER_INIT_C = 0x000034C0 +
0x0fcf, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x0fd0, .
RECOUT_START = 0x000034C0 + 0x0fd8, .RECOUT_SIZE = 0x000034C0
+ 0x0fd9, .CM_ICSC_CONTROL = 0x000034C0 + 0x0ff1, .CM_ICSC_C11_C12
= 0x000034C0 + 0x0ff2, .CM_ICSC_C33_C34 = 0x000034C0 + 0x0ff7
, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x1025, .CM_DGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x1026, .CM_DGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x1027, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x1028, .
CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x1029, .CM_DGAM_RAMB_SLOPE_CNTL_R
= 0x000034C0 + 0x102a, .CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0
+ 0x102b, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x102c, .
CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x102d, .CM_DGAM_RAMB_END_CNTL2_G
= 0x000034C0 + 0x102e, .CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0
+ 0x102f, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x1030, .
CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x1031, .CM_DGAM_RAMB_REGION_14_15
= 0x000034C0 + 0x1038, .CM_DGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x1011, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x1012, .
CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x1013, .CM_DGAM_RAMA_SLOPE_CNTL_B
= 0x000034C0 + 0x1014, .CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0
+ 0x1015, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x1016, .
CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x1017, .CM_DGAM_RAMA_END_CNTL2_B
= 0x000034C0 + 0x1018, .CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0
+ 0x1019, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x101a, .
CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x101b, .CM_DGAM_RAMA_END_CNTL2_R
= 0x000034C0 + 0x101c, .CM_DGAM_RAMA_REGION_0_1 = 0x000034C0
+ 0x101d, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x1024, .
CM_MEM_PWR_CTRL = 0x000034C0 + 0x1078, .CM_DGAM_LUT_WRITE_EN_MASK
= 0x000034C0 + 0x1010, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x100e
, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x100f, .CM_CONTROL = 0x000034C0
+ 0x0ff0, .CM_DGAM_CONTROL = 0x000034C0 + 0x100d, .CM_TEST_DEBUG_INDEX
= 0x000034C0 + 0x10bf, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x10c0
, .FORMAT_CONTROL = 0x000034C0 + 0x0fa6, .CNVC_SURFACE_PIXEL_FORMAT
= 0x000034C0 + 0x0fa5, .CURSOR0_CONTROL = 0x000034C0 + 0x0fb6
, .CURSOR0_COLOR0 = 0x000034C0 + 0x0fb7, .CURSOR0_COLOR1 = 0x000034C0
+ 0x0fb8, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0fb9, .DPP_CONTROL
= 0x000034C0 + 0x0f9b, .CM_HDR_MULT_COEF = 0x000034C0 + 0x1077
, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x1039, .CM_BLNDGAM_RAMB_START_CNTL_B
= 0x000034C0 + 0x105a, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0
+ 0x105b, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x105c
, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x1060, .CM_BLNDGAM_RAMB_END_CNTL2_B
= 0x000034C0 + 0x1061, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0
+ 0x1062, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x1063
, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x1064, .CM_BLNDGAM_RAMB_END_CNTL2_R
= 0x000034C0 + 0x1065, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0
+ 0x1066, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x1067,
.CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x1068, .CM_BLNDGAM_RAMB_REGION_6_7
= 0x000034C0 + 0x1069, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0
+ 0x106a, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x106b
, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x106c, .CM_BLNDGAM_RAMB_REGION_14_15
= 0x000034C0 + 0x106d, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0
+ 0x106e, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x106f
, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x1070, .CM_BLNDGAM_RAMB_REGION_22_23
= 0x000034C0 + 0x1071, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0
+ 0x1072, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x1073
, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x1074, .CM_BLNDGAM_RAMB_REGION_30_31
= 0x000034C0 + 0x1075, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0
+ 0x1076, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x103d
, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x103e, .CM_BLNDGAM_RAMA_START_CNTL_R
= 0x000034C0 + 0x103f, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0
+ 0x1043, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x1044
, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x1045, .CM_BLNDGAM_RAMA_END_CNTL2_G
= 0x000034C0 + 0x1046, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0
+ 0x1047, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x1048
, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x1049, .CM_BLNDGAM_RAMA_REGION_2_3
= 0x000034C0 + 0x104a, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0
+ 0x104b, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x104c,
.CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x104d, .CM_BLNDGAM_RAMA_REGION_10_11
= 0x000034C0 + 0x104e, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0
+ 0x104f, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x1050
, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x1051, .CM_BLNDGAM_RAMA_REGION_18_19
= 0x000034C0 + 0x1052, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0
+ 0x1053, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x1054
, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x1055, .CM_BLNDGAM_RAMA_REGION_26_27
= 0x000034C0 + 0x1056, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0
+ 0x1057, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x1058
, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x1059, .CM_BLNDGAM_LUT_INDEX
= 0x000034C0 + 0x103a, .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x103b
, .CM_3DLUT_MODE = 0x000034C0 + 0x10b6, .CM_3DLUT_INDEX = 0x000034C0
+ 0x10b7, .CM_3DLUT_DATA = 0x000034C0 + 0x10b8, .CM_3DLUT_DATA_30BIT
= 0x000034C0 + 0x10b9, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0
+ 0x10ba, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x1085
, .CM_SHAPER_CONTROL = 0x000034C0 + 0x107d, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x109d, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x109e, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x109f
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x10a0, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x10a1, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x10a2, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x10a3, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x10a4, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x10a5, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x10a6, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x10a7, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x10a8, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x10a9, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x10aa, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x10ab
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x10ac, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x10ad, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x10ae, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x10af
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x10b0, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x10b1, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x10b2, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x10b3
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x1086, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x1087, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x1088, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x1089, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x108a, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x108b, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x108c, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x108d, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x108e, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x108f, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x1090, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x1091
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x1092, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x1093, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x1094, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x1095
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x1096, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x1097, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x1098, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x1099
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x109a, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x109b, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x109c, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x1083, .CM_BLNDGAM_LUT_WRITE_EN_MASK
= 0x000034C0 + 0x103c, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0
+ 0x105d, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x105e
, .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x105f, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B
= 0x000034C0 + 0x1040, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0
+ 0x1041, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x1042
, .CURSOR_CONTROL = 0x000034C0 + 0x0830, .ALPHA_2BIT_LUT = 0x000034C0
+ 0x0fb3, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0fa7, .FCNV_FP_BIAS_G
= 0x000034C0 + 0x0fa8, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0fa9
, .FCNV_FP_SCALE_R = 0x000034C0 + 0x0faa, .FCNV_FP_SCALE_G = 0x000034C0
+ 0x0fab, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0fac, .COLOR_KEYER_CONTROL
= 0x000034C0 + 0x0fad, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0fae
, .COLOR_KEYER_RED = 0x000034C0 + 0x0faf, .COLOR_KEYER_GREEN =
0x000034C0 + 0x0fb0, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0fb1
, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x1084, .CURSOR_CONTROL =
0x000034C0 + 0x0830, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0fe1
, .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0fde,},
472 tf_regs(3)[3] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x1169, .CM_GAMUT_REMAP_C11_C12
= 0x000034C0 + 0x116a, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 +
0x116b, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x116c, .CM_GAMUT_REMAP_C23_C24
= 0x000034C0 + 0x116d, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 +
0x116e, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x116f, .DSCL_EXT_OVERSCAN_LEFT_RIGHT
= 0x000034C0 + 0x113f, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0
+ 0x1140, .DSCL_MEM_PWR_STATUS = 0x000034C0 + 0x114a, .DSCL_MEM_PWR_CTRL
= 0x000034C0 + 0x1149, .OTG_H_BLANK = 0x000034C0 + 0x1141, .
OTG_V_BLANK = 0x000034C0 + 0x1142, .SCL_MODE = 0x000034C0 + 0x112d
, .LB_DATA_FORMAT = 0x000034C0 + 0x1146, .LB_MEMORY_CTRL = 0x000034C0
+ 0x1147, .DSCL_AUTOCAL = 0x000034C0 + 0x113e, .SCL_BLACK_OFFSET
= 0x000034C0 + 0x113c, .SCL_TAP_CONTROL = 0x000034C0 + 0x112e
, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x112b, .SCL_COEF_RAM_TAP_DATA
= 0x000034C0 + 0x112c, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x1130
, .MPC_SIZE = 0x000034C0 + 0x1145, .SCL_HORZ_FILTER_SCALE_RATIO
= 0x000034C0 + 0x1132, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0
+ 0x1136, .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1134
, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1139, .SCL_HORZ_FILTER_INIT
= 0x000034C0 + 0x1133, .SCL_HORZ_FILTER_INIT_C = 0x000034C0 +
0x1135, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x1137, .SCL_VERT_FILTER_INIT_BOT
= 0x000034C0 + 0x1138, .SCL_VERT_FILTER_INIT_C = 0x000034C0 +
0x113a, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x113b, .
RECOUT_START = 0x000034C0 + 0x1143, .RECOUT_SIZE = 0x000034C0
+ 0x1144, .CM_ICSC_CONTROL = 0x000034C0 + 0x115c, .CM_ICSC_C11_C12
= 0x000034C0 + 0x115d, .CM_ICSC_C33_C34 = 0x000034C0 + 0x1162
, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x1190, .CM_DGAM_RAMB_START_CNTL_G
= 0x000034C0 + 0x1191, .CM_DGAM_RAMB_START_CNTL_R = 0x000034C0
+ 0x1192, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x1193, .
CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x1194, .CM_DGAM_RAMB_SLOPE_CNTL_R
= 0x000034C0 + 0x1195, .CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0
+ 0x1196, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x1197, .
CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x1198, .CM_DGAM_RAMB_END_CNTL2_G
= 0x000034C0 + 0x1199, .CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0
+ 0x119a, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x119b, .
CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x119c, .CM_DGAM_RAMB_REGION_14_15
= 0x000034C0 + 0x11a3, .CM_DGAM_RAMA_START_CNTL_B = 0x000034C0
+ 0x117c, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x117d, .
CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x117e, .CM_DGAM_RAMA_SLOPE_CNTL_B
= 0x000034C0 + 0x117f, .CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0
+ 0x1180, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x1181, .
CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x1182, .CM_DGAM_RAMA_END_CNTL2_B
= 0x000034C0 + 0x1183, .CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0
+ 0x1184, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x1185, .
CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x1186, .CM_DGAM_RAMA_END_CNTL2_R
= 0x000034C0 + 0x1187, .CM_DGAM_RAMA_REGION_0_1 = 0x000034C0
+ 0x1188, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x118f, .
CM_MEM_PWR_CTRL = 0x000034C0 + 0x11e3, .CM_DGAM_LUT_WRITE_EN_MASK
= 0x000034C0 + 0x117b, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x1179
, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x117a, .CM_CONTROL = 0x000034C0
+ 0x115b, .CM_DGAM_CONTROL = 0x000034C0 + 0x1178, .CM_TEST_DEBUG_INDEX
= 0x000034C0 + 0x122a, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x122b
, .FORMAT_CONTROL = 0x000034C0 + 0x1111, .CNVC_SURFACE_PIXEL_FORMAT
= 0x000034C0 + 0x1110, .CURSOR0_CONTROL = 0x000034C0 + 0x1121
, .CURSOR0_COLOR0 = 0x000034C0 + 0x1122, .CURSOR0_COLOR1 = 0x000034C0
+ 0x1123, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x1124, .DPP_CONTROL
= 0x000034C0 + 0x1106, .CM_HDR_MULT_COEF = 0x000034C0 + 0x11e2
, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x11a4, .CM_BLNDGAM_RAMB_START_CNTL_B
= 0x000034C0 + 0x11c5, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0
+ 0x11c6, .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x11c7
, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x11cb, .CM_BLNDGAM_RAMB_END_CNTL2_B
= 0x000034C0 + 0x11cc, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0
+ 0x11cd, .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x11ce
, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x11cf, .CM_BLNDGAM_RAMB_END_CNTL2_R
= 0x000034C0 + 0x11d0, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0
+ 0x11d1, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x11d2,
.CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x11d3, .CM_BLNDGAM_RAMB_REGION_6_7
= 0x000034C0 + 0x11d4, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0
+ 0x11d5, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x11d6
, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x11d7, .CM_BLNDGAM_RAMB_REGION_14_15
= 0x000034C0 + 0x11d8, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0
+ 0x11d9, .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x11da
, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x11db, .CM_BLNDGAM_RAMB_REGION_22_23
= 0x000034C0 + 0x11dc, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0
+ 0x11dd, .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x11de
, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x11df, .CM_BLNDGAM_RAMB_REGION_30_31
= 0x000034C0 + 0x11e0, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0
+ 0x11e1, .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x11a8
, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x11a9, .CM_BLNDGAM_RAMA_START_CNTL_R
= 0x000034C0 + 0x11aa, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0
+ 0x11ae, .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x11af
, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x11b0, .CM_BLNDGAM_RAMA_END_CNTL2_G
= 0x000034C0 + 0x11b1, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0
+ 0x11b2, .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x11b3
, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x11b4, .CM_BLNDGAM_RAMA_REGION_2_3
= 0x000034C0 + 0x11b5, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0
+ 0x11b6, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x11b7,
.CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x11b8, .CM_BLNDGAM_RAMA_REGION_10_11
= 0x000034C0 + 0x11b9, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0
+ 0x11ba, .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x11bb
, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x11bc, .CM_BLNDGAM_RAMA_REGION_18_19
= 0x000034C0 + 0x11bd, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0
+ 0x11be, .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x11bf
, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x11c0, .CM_BLNDGAM_RAMA_REGION_26_27
= 0x000034C0 + 0x11c1, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0
+ 0x11c2, .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x11c3
, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x11c4, .CM_BLNDGAM_LUT_INDEX
= 0x000034C0 + 0x11a5, .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x11a6
, .CM_3DLUT_MODE = 0x000034C0 + 0x1221, .CM_3DLUT_INDEX = 0x000034C0
+ 0x1222, .CM_3DLUT_DATA = 0x000034C0 + 0x1223, .CM_3DLUT_DATA_30BIT
= 0x000034C0 + 0x1224, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0
+ 0x1225, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x11f0
, .CM_SHAPER_CONTROL = 0x000034C0 + 0x11e8, .CM_SHAPER_RAMB_START_CNTL_B
= 0x000034C0 + 0x1208, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0
+ 0x1209, .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x120a
, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x120b, .CM_SHAPER_RAMB_END_CNTL_G
= 0x000034C0 + 0x120c, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0
+ 0x120d, .CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x120e, .
CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x120f, .CM_SHAPER_RAMB_REGION_4_5
= 0x000034C0 + 0x1210, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0
+ 0x1211, .CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x1212, .
CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x1213, .CM_SHAPER_RAMB_REGION_12_13
= 0x000034C0 + 0x1214, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0
+ 0x1215, .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x1216
, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x1217, .CM_SHAPER_RAMB_REGION_20_21
= 0x000034C0 + 0x1218, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0
+ 0x1219, .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x121a
, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x121b, .CM_SHAPER_RAMB_REGION_28_29
= 0x000034C0 + 0x121c, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0
+ 0x121d, .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x121e
, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x11f1, .CM_SHAPER_RAMA_START_CNTL_G
= 0x000034C0 + 0x11f2, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0
+ 0x11f3, .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x11f4, .
CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x11f5, .CM_SHAPER_RAMA_END_CNTL_R
= 0x000034C0 + 0x11f6, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0
+ 0x11f7, .CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x11f8, .
CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x11f9, .CM_SHAPER_RAMA_REGION_6_7
= 0x000034C0 + 0x11fa, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0
+ 0x11fb, .CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x11fc
, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x11fd, .CM_SHAPER_RAMA_REGION_14_15
= 0x000034C0 + 0x11fe, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0
+ 0x11ff, .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x1200
, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x1201, .CM_SHAPER_RAMA_REGION_22_23
= 0x000034C0 + 0x1202, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0
+ 0x1203, .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x1204
, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x1205, .CM_SHAPER_RAMA_REGION_30_31
= 0x000034C0 + 0x1206, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0
+ 0x1207, .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x11ee, .CM_BLNDGAM_LUT_WRITE_EN_MASK
= 0x000034C0 + 0x11a7, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0
+ 0x11c8, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x11c9
, .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x11ca, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B
= 0x000034C0 + 0x11ab, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0
+ 0x11ac, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x11ad
, .CURSOR_CONTROL = 0x000034C0 + 0x090c, .ALPHA_2BIT_LUT = 0x000034C0
+ 0x111e, .FCNV_FP_BIAS_R = 0x000034C0 + 0x1112, .FCNV_FP_BIAS_G
= 0x000034C0 + 0x1113, .FCNV_FP_BIAS_B = 0x000034C0 + 0x1114
, .FCNV_FP_SCALE_R = 0x000034C0 + 0x1115, .FCNV_FP_SCALE_G = 0x000034C0
+ 0x1116, .FCNV_FP_SCALE_B = 0x000034C0 + 0x1117, .COLOR_KEYER_CONTROL
= 0x000034C0 + 0x1118, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x1119
, .COLOR_KEYER_RED = 0x000034C0 + 0x111a, .COLOR_KEYER_GREEN =
0x000034C0 + 0x111b, .COLOR_KEYER_BLUE = 0x000034C0 + 0x111c
, .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x11ef, .CURSOR_CONTROL =
0x000034C0 + 0x090c, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x114c
, .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x1149,},
473};
474
475static const struct dcn201_dpp_shift tf_shift = {
476 TF_REG_LIST_SH_MASK_DCN201(__SHIFT).CM_GAMUT_REMAP_MODE = 0x0, .CM_GAMUT_REMAP_C11 = 0x0, .CM_GAMUT_REMAP_C12
= 0x10, .CM_GAMUT_REMAP_C13 = 0x0, .CM_GAMUT_REMAP_C14 = 0x10
, .CM_GAMUT_REMAP_C21 = 0x0, .CM_GAMUT_REMAP_C22 = 0x10, .CM_GAMUT_REMAP_C23
= 0x0, .CM_GAMUT_REMAP_C24 = 0x10, .CM_GAMUT_REMAP_C31 = 0x0
, .CM_GAMUT_REMAP_C32 = 0x10, .CM_GAMUT_REMAP_C33 = 0x0, .CM_GAMUT_REMAP_C34
= 0x10, .EXT_OVERSCAN_LEFT = 0x10, .EXT_OVERSCAN_RIGHT = 0x0
, .EXT_OVERSCAN_BOTTOM = 0x0, .EXT_OVERSCAN_TOP = 0x10, .OTG_H_BLANK_START
= 0x0, .OTG_H_BLANK_END = 0x10, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END
= 0x10, .INTERLEAVE_EN = 0x0, .LB_DATA_FORMAT__ALPHA_EN = 0x4
, .MEMORY_CONFIG = 0x0, .LB_MAX_PARTITIONS = 0x8, .AUTOCAL_MODE
= 0x0, .AUTOCAL_NUM_PIPE = 0x8, .AUTOCAL_PIPE_ID = 0xc, .SCL_BLACK_OFFSET_RGB_Y
= 0x0, .SCL_BLACK_OFFSET_CBCR = 0x10, .SCL_V_NUM_TAPS = 0x0,
.SCL_H_NUM_TAPS = 0x4, .SCL_V_NUM_TAPS_C = 0x8, .SCL_H_NUM_TAPS_C
= 0xc, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x0, .SCL_COEF_RAM_PHASE
= 0x8, .SCL_COEF_RAM_FILTER_TYPE = 0x10, .SCL_COEF_RAM_EVEN_TAP_COEF
= 0x0, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0xf, .SCL_COEF_RAM_ODD_TAP_COEF
= 0x10, .SCL_COEF_RAM_ODD_TAP_COEF_EN = 0x1f, .SCL_H_2TAP_HARDCODE_COEF_EN
= 0x0, .SCL_H_2TAP_SHARP_EN = 0x4, .SCL_H_2TAP_SHARP_FACTOR =
0x8, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x10, .SCL_V_2TAP_SHARP_EN
= 0x14, .SCL_V_2TAP_SHARP_FACTOR = 0x18, .SCL_COEF_RAM_SELECT
= 0x8, .DSCL_MODE = 0x0, .RECOUT_START_X = 0x0, .RECOUT_START_Y
= 0x10, .RECOUT_WIDTH = 0x0, .RECOUT_HEIGHT = 0x10, .MPC_WIDTH
= 0x0, .MPC_HEIGHT = 0x10, .SCL_H_SCALE_RATIO = 0x0, .SCL_V_SCALE_RATIO
= 0x0, .SCL_H_SCALE_RATIO_C = 0x0, .SCL_V_SCALE_RATIO_C = 0x0
, .SCL_H_INIT_FRAC = 0x0, .SCL_H_INIT_INT = 0x18, .SCL_H_INIT_FRAC_C
= 0x0, .SCL_H_INIT_INT_C = 0x18, .SCL_V_INIT_FRAC = 0x0, .SCL_V_INIT_INT
= 0x18, .SCL_V_INIT_FRAC_BOT = 0x0, .SCL_V_INIT_INT_BOT = 0x18
, .SCL_V_INIT_FRAC_C = 0x0, .SCL_V_INIT_INT_C = 0x18, .SCL_V_INIT_FRAC_BOT_C
= 0x0, .SCL_V_INIT_INT_BOT_C = 0x18, .SCL_CHROMA_COEF_MODE =
0x10, .SCL_COEF_RAM_SELECT_CURRENT = 0xc, .LUT_MEM_PWR_FORCE
= 0x0, .LUT_MEM_PWR_STATE = 0x0, .CM_ICSC_MODE = 0x0, .CM_ICSC_C11
= 0x0, .CM_ICSC_C12 = 0x10, .CM_ICSC_C33 = 0x0, .CM_ICSC_C34
= 0x10, .CM_DGAM_RAMB_EXP_REGION_START_B = 0x0, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B
= 0x14, .CM_DGAM_RAMB_EXP_REGION_START_G = 0x0, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G
= 0x14, .CM_DGAM_RAMB_EXP_REGION_START_R = 0x0, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R
= 0x14, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G
= 0x0, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_B
= 0x0, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_BASE_B
= 0x10, .CM_DGAM_RAMB_EXP_REGION_END_G = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G
= 0x0, .CM_DGAM_RAMB_EXP_REGION_END_BASE_G = 0x10, .CM_DGAM_RAMB_EXP_REGION_END_R
= 0x0, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_BASE_R
= 0x10, .CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS
= 0xc, .CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS
= 0x1c, .CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS
= 0xc, .CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS
= 0x1c, .CM_DGAM_RAMA_EXP_REGION_START_B = 0x0, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B
= 0x14, .CM_DGAM_RAMA_EXP_REGION_START_G = 0x0, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G
= 0x14, .CM_DGAM_RAMA_EXP_REGION_START_R = 0x0, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R
= 0x14, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G
= 0x0, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_B
= 0x0, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_BASE_B
= 0x10, .CM_DGAM_RAMA_EXP_REGION_END_G = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G
= 0x0, .CM_DGAM_RAMA_EXP_REGION_END_BASE_G = 0x10, .CM_DGAM_RAMA_EXP_REGION_END_R
= 0x0, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_BASE_R
= 0x10, .CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0xc, .CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS
= 0x1c, .CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS
= 0xc, .CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS
= 0x1c, .SHARED_MEM_PWR_DIS = 0x2, .CM_DGAM_LUT_WRITE_EN_MASK
= 0x0, .CM_DGAM_LUT_WRITE_SEL = 0x4, .CM_DGAM_LUT_INDEX = 0x0
, .CM_DGAM_LUT_DATA = 0x0, .CM_DGAM_LUT_MODE = 0x0, .CM_TEST_DEBUG_INDEX
= 0x0, .CNVC_BYPASS = 0xc, .FORMAT_CONTROL__ALPHA_EN = 0x8, .
FORMAT_EXPANSION_MODE = 0x0, .CNVC_SURFACE_PIXEL_FORMAT = 0x0
, .CUR0_MODE = 0x4, .CUR0_EXPANSION_MODE = 0x1, .CUR0_ENABLE =
0x0, .CUR0_COLOR0 = 0x0, .CUR0_COLOR1 = 0x0, .CUR0_FP_BIAS =
0x10, .CUR0_FP_SCALE = 0x0, .DPP_CLOCK_ENABLE = 0x4, .CM_HDR_MULT_COEF
= 0x0, .CM_3DLUT_MODE = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_B
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .
CM_BLNDGAM_RAMB_EXP_REGION_START_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G
= 0x14, .CM_BLNDGAM_RAMB_EXP_REGION_START_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R
= 0x14, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, .
CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION_START_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B
= 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_START_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G
= 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_START_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R
= 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, .
CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS
= 0xc, .CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS
= 0x1c, .CM_BLNDGAM_LUT_INDEX = 0x0, .CM_BLNDGAM_LUT_DATA = 0x0
, .BLNDGAM_MEM_PWR_FORCE = 0x4, .CM_3DLUT_MODE = 0x0, .CM_3DLUT_SIZE
= 0x4, .CM_3DLUT_INDEX = 0x0, .CM_3DLUT_DATA0 = 0x0, .CM_3DLUT_DATA1
= 0x10, .CM_3DLUT_DATA_30BIT = 0x2, .CM_3DLUT_WRITE_EN_MASK =
0x0, .CM_3DLUT_RAM_SEL = 0x4, .CM_3DLUT_30BIT_EN = 0x8, .CM_3DLUT_READ_SEL
= 0x10, .CM_SHAPER_LUT_MODE = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_B
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .CM_SHAPER_RAMB_EXP_REGION_START_G
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .CM_SHAPER_RAMB_EXP_REGION_START_R
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .CM_SHAPER_RAMB_EXP_REGION_END_B
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_B = 0x10, .CM_SHAPER_RAMB_EXP_REGION_END_G
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_G = 0x10, .CM_SHAPER_RAMB_EXP_REGION_END_R
= 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_R = 0x10, .CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION_START_B
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_SHAPER_RAMA_EXP_REGION_START_G
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .CM_SHAPER_RAMA_EXP_REGION_START_R
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .CM_SHAPER_RAMA_EXP_REGION_END_B
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x10, .CM_SHAPER_RAMA_EXP_REGION_END_G
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_G = 0x10, .CM_SHAPER_RAMA_EXP_REGION_END_R
= 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_R = 0x10, .CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET
= 0x0, .CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET
= 0x10, .CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_SHAPER_LUT_WRITE_EN_MASK
= 0x0, .CM_SHAPER_LUT_WRITE_SEL = 0x4, .CM_SHAPER_LUT_INDEX =
0x0, .CM_SHAPER_LUT_DATA = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_G
= 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_G
= 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B
= 0x10, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R
= 0x10, .CM_BLNDGAM_LUT_MODE = 0x0, .CM_BLNDGAM_LUT_WRITE_EN_MASK
= 0x0, .CM_BLNDGAM_LUT_WRITE_SEL = 0x4, .CM_BLNDGAM_CONFIG_STATUS
= 0x8, .CM_SHAPER_LUT_MODE = 0x0, .CM_DGAM_CONFIG_STATUS = 0x8
, .CM_BYPASS = 0x0, .CURSOR_MODE = 0x8, .CURSOR_PITCH = 0x10,
.CURSOR_LINES_PER_CHUNK = 0x18, .CURSOR_ENABLE = 0x0, .FORMAT_CNV16
= 0x4, .CNVC_BYPASS_MSB_ALIGN = 0xd, .CLAMP_POSITIVE = 0x10,
.CLAMP_POSITIVE_C = 0x11, .ALPHA_2BIT_LUT0 = 0x0, .ALPHA_2BIT_LUT1
= 0x8, .ALPHA_2BIT_LUT2 = 0x10, .ALPHA_2BIT_LUT3 = 0x18, .FCNV_FP_BIAS_R
= 0x0, .FCNV_FP_BIAS_G = 0x0, .FCNV_FP_BIAS_B = 0x0, .FCNV_FP_SCALE_R
= 0x0, .FCNV_FP_SCALE_G = 0x0, .FCNV_FP_SCALE_B = 0x0, .COLOR_KEYER_EN
= 0x0, .COLOR_KEYER_MODE = 0x4, .COLOR_KEYER_ALPHA_LOW = 0x0
, .COLOR_KEYER_ALPHA_HIGH = 0x10, .COLOR_KEYER_RED_LOW = 0x0,
.COLOR_KEYER_RED_HIGH = 0x10, .COLOR_KEYER_GREEN_LOW = 0x0, .
COLOR_KEYER_GREEN_HIGH = 0x10, .COLOR_KEYER_BLUE_LOW = 0x0, .
COLOR_KEYER_BLUE_HIGH = 0x10, .CUR0_PIX_INV_MODE = 0x2, .CUR0_PIXEL_ALPHA_MOD_EN
= 0x7, .CUR0_ROM_EN = 0x3, .OBUF_MEM_PWR_FORCE = 0x0, .LUT_MEM_PWR_FORCE
= 0x0
477};
478
479static const struct dcn201_dpp_mask tf_mask = {
480 TF_REG_LIST_SH_MASK_DCN201(_MASK).CM_GAMUT_REMAP_MODE = 0x00000003L, .CM_GAMUT_REMAP_C11 = 0x0000FFFFL
, .CM_GAMUT_REMAP_C12 = 0xFFFF0000L, .CM_GAMUT_REMAP_C13 = 0x0000FFFFL
, .CM_GAMUT_REMAP_C14 = 0xFFFF0000L, .CM_GAMUT_REMAP_C21 = 0x0000FFFFL
, .CM_GAMUT_REMAP_C22 = 0xFFFF0000L, .CM_GAMUT_REMAP_C23 = 0x0000FFFFL
, .CM_GAMUT_REMAP_C24 = 0xFFFF0000L, .CM_GAMUT_REMAP_C31 = 0x0000FFFFL
, .CM_GAMUT_REMAP_C32 = 0xFFFF0000L, .CM_GAMUT_REMAP_C33 = 0x0000FFFFL
, .CM_GAMUT_REMAP_C34 = 0xFFFF0000L, .EXT_OVERSCAN_LEFT = 0x1FFF0000L
, .EXT_OVERSCAN_RIGHT = 0x00001FFFL, .EXT_OVERSCAN_BOTTOM = 0x00001FFFL
, .EXT_OVERSCAN_TOP = 0x1FFF0000L, .OTG_H_BLANK_START = 0x00003FFFL
, .OTG_H_BLANK_END = 0x3FFF0000L, .OTG_V_BLANK_START = 0x00003FFFL
, .OTG_V_BLANK_END = 0x3FFF0000L, .INTERLEAVE_EN = 0x00000001L
, .LB_DATA_FORMAT__ALPHA_EN = 0x00000010L, .MEMORY_CONFIG = 0x00000003L
, .LB_MAX_PARTITIONS = 0x00003F00L, .AUTOCAL_MODE = 0x00000003L
, .AUTOCAL_NUM_PIPE = 0x00000300L, .AUTOCAL_PIPE_ID = 0x00003000L
, .SCL_BLACK_OFFSET_RGB_Y = 0x0000FFFFL, .SCL_BLACK_OFFSET_CBCR
= 0xFFFF0000L, .SCL_V_NUM_TAPS = 0x00000007L, .SCL_H_NUM_TAPS
= 0x00000070L, .SCL_V_NUM_TAPS_C = 0x00000700L, .SCL_H_NUM_TAPS_C
= 0x00007000L, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x00000003L, .SCL_COEF_RAM_PHASE
= 0x00003F00L, .SCL_COEF_RAM_FILTER_TYPE = 0x00070000L, .SCL_COEF_RAM_EVEN_TAP_COEF
= 0x00003FFFL, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0x00008000L,
.SCL_COEF_RAM_ODD_TAP_COEF = 0x3FFF0000L, .SCL_COEF_RAM_ODD_TAP_COEF_EN
= 0x80000000L, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x00000001L, .
SCL_H_2TAP_SHARP_EN = 0x00000010L, .SCL_H_2TAP_SHARP_FACTOR =
0x00000700L, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x00010000L, .SCL_V_2TAP_SHARP_EN
= 0x00100000L, .SCL_V_2TAP_SHARP_FACTOR = 0x07000000L, .SCL_COEF_RAM_SELECT
= 0x00000100L, .DSCL_MODE = 0x00000007L, .RECOUT_START_X = 0x00001FFFL
, .RECOUT_START_Y = 0x1FFF0000L, .RECOUT_WIDTH = 0x00003FFFL,
.RECOUT_HEIGHT = 0x3FFF0000L, .MPC_WIDTH = 0x00003FFFL, .MPC_HEIGHT
= 0x3FFF0000L, .SCL_H_SCALE_RATIO = 0x07FFFFFFL, .SCL_V_SCALE_RATIO
= 0x07FFFFFFL, .SCL_H_SCALE_RATIO_C = 0x07FFFFFFL, .SCL_V_SCALE_RATIO_C
= 0x07FFFFFFL, .SCL_H_INIT_FRAC = 0x00FFFFFFL, .SCL_H_INIT_INT
= 0x0F000000L, .SCL_H_INIT_FRAC_C = 0x00FFFFFFL, .SCL_H_INIT_INT_C
= 0x0F000000L, .SCL_V_INIT_FRAC = 0x00FFFFFFL, .SCL_V_INIT_INT
= 0x0F000000L, .SCL_V_INIT_FRAC_BOT = 0x00FFFFFFL, .SCL_V_INIT_INT_BOT
= 0x0F000000L, .SCL_V_INIT_FRAC_C = 0x00FFFFFFL, .SCL_V_INIT_INT_C
= 0x0F000000L, .SCL_V_INIT_FRAC_BOT_C = 0x00FFFFFFL, .SCL_V_INIT_INT_BOT_C
= 0x0F000000L, .SCL_CHROMA_COEF_MODE = 0x00010000L, .SCL_COEF_RAM_SELECT_CURRENT
= 0x00001000L, .LUT_MEM_PWR_FORCE = 0x00000003L, .LUT_MEM_PWR_STATE
= 0x00000003L, .CM_ICSC_MODE = 0x00000003L, .CM_ICSC_C11 = 0x0000FFFFL
, .CM_ICSC_C12 = 0xFFFF0000L, .CM_ICSC_C33 = 0x0000FFFFL, .CM_ICSC_C34
= 0xFFFF0000L, .CM_DGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL
, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .CM_DGAM_RAMB_EXP_REGION_START_G
= 0x0003FFFFL, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L
, .CM_DGAM_RAMB_EXP_REGION_START_R = 0x0003FFFFL, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R
= 0x07F00000L, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL
, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G = 0x0003FFFFL, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R
= 0x0003FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_B = 0x0000FFFFL,
.CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_BASE_B
= 0xFFFF0000L, .CM_DGAM_RAMB_EXP_REGION_END_G = 0x0000FFFFL,
.CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_BASE_G
= 0xFFFF0000L, .CM_DGAM_RAMB_EXP_REGION_END_R = 0x0000FFFFL,
.CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_BASE_R
= 0xFFFF0000L, .CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL
, .CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET
= 0x01FF0000L, .CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L
, .CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL, .CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS
= 0x00007000L, .CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L
, .CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_DGAM_RAMA_EXP_REGION_START_B
= 0x0003FFFFL, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L
, .CM_DGAM_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G
= 0x07F00000L, .CM_DGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL
, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B
= 0x0003FFFFL, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G = 0x0003FFFFL
, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R = 0x0003FFFFL, .CM_DGAM_RAMA_EXP_REGION_END_B
= 0x0000FFFFL, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0000FFFFL
, .CM_DGAM_RAMA_EXP_REGION_END_BASE_B = 0xFFFF0000L, .CM_DGAM_RAMA_EXP_REGION_END_G
= 0x0000FFFFL, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G = 0x0000FFFFL
, .CM_DGAM_RAMA_EXP_REGION_END_BASE_G = 0xFFFF0000L, .CM_DGAM_RAMA_EXP_REGION_END_R
= 0x0000FFFFL, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x0000FFFFL
, .CM_DGAM_RAMA_EXP_REGION_END_BASE_R = 0xFFFF0000L, .CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET
= 0x000001FFL, .CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L
, .CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS
= 0x70000000L, .CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL
, .CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET
= 0x01FF0000L, .CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L
, .SHARED_MEM_PWR_DIS = 0x00000004L, .CM_DGAM_LUT_WRITE_EN_MASK
= 0x00000007L, .CM_DGAM_LUT_WRITE_SEL = 0x00000010L, .CM_DGAM_LUT_INDEX
= 0x000001FFL, .CM_DGAM_LUT_DATA = 0x0007FFFFL, .CM_DGAM_LUT_MODE
= 0x00000007L, .CM_TEST_DEBUG_INDEX = 0x000000FFL, .CNVC_BYPASS
= 0x00001000L, .FORMAT_CONTROL__ALPHA_EN = 0x00000100L, .FORMAT_EXPANSION_MODE
= 0x00000001L, .CNVC_SURFACE_PIXEL_FORMAT = 0x0000007FL, .CUR0_MODE
= 0x00000070L, .CUR0_EXPANSION_MODE = 0x00000002L, .CUR0_ENABLE
= 0x00000001L, .CUR0_COLOR0 = 0x00FFFFFFL, .CUR0_COLOR1 = 0x00FFFFFFL
, .CUR0_FP_BIAS = 0xFFFF0000L, .CUR0_FP_SCALE = 0x0000FFFFL, .
DPP_CLOCK_ENABLE = 0x00000010L, .CM_HDR_MULT_COEF = 0x0007FFFFL
, .CM_3DLUT_MODE = 0x00000003L, .CM_BLNDGAM_RAMB_EXP_REGION_START_B
= 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B =
0x07F00000L, .CM_BLNDGAM_RAMB_EXP_REGION_START_G = 0x0003FFFFL
, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .
CM_BLNDGAM_RAMB_EXP_REGION_START_R = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R
= 0x07F00000L, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0000FFFFL
, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x0000FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R
= 0x0000FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET
= 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L
, .CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS
= 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L
, .CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET
= 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L
, .CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET
= 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L
, .CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS
= 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L
, .CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET
= 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L
, .CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .
CM_BLNDGAM_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G
= 0x07F00000L, .CM_BLNDGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .
CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G
= 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x0000FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L
, .CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET
= 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L
, .CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET
= 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L
, .CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS
= 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L
, .CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET
= 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L
, .CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL
, .CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, .
CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS
= 0x70000000L, .CM_BLNDGAM_LUT_INDEX = 0x000001FFL, .CM_BLNDGAM_LUT_DATA
= 0x0007FFFFL, .BLNDGAM_MEM_PWR_FORCE = 0x00000030L, .CM_3DLUT_MODE
= 0x00000003L, .CM_3DLUT_SIZE = 0x00000010L, .CM_3DLUT_INDEX
= 0x000007FFL, .CM_3DLUT_DATA0 = 0x0000FFFFL, .CM_3DLUT_DATA1
= 0xFFFF0000L, .CM_3DLUT_DATA_30BIT = 0xFFFFFFFCL, .CM_3DLUT_WRITE_EN_MASK
= 0x0000000FL, .CM_3DLUT_RAM_SEL = 0x00000010L, .CM_3DLUT_30BIT_EN
= 0x00000100L, .CM_3DLUT_READ_SEL = 0x00030000L, .CM_SHAPER_LUT_MODE
= 0x00000003L, .CM_SHAPER_RAMB_EXP_REGION_START_B = 0x0003FFFFL
, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .
CM_SHAPER_RAMB_EXP_REGION_START_G = 0x0003FFFFL, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G
= 0x07F00000L, .CM_SHAPER_RAMB_EXP_REGION_START_R = 0x0003FFFFL
, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .
CM_SHAPER_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_B
= 0x3FFF0000L, .CM_SHAPER_RAMB_EXP_REGION_END_G = 0x0000FFFFL
, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_G = 0x3FFF0000L, .CM_SHAPER_RAMB_EXP_REGION_END_R
= 0x0000FFFFL, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_R = 0x3FFF0000L
, .CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION_START_B = 0x0003FFFFL
, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .
CM_SHAPER_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G
= 0x07F00000L, .CM_SHAPER_RAMA_EXP_REGION_START_R = 0x0003FFFFL
, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .
CM_SHAPER_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_B
= 0x3FFF0000L, .CM_SHAPER_RAMA_EXP_REGION_END_G = 0x0000FFFFL
, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_G = 0x3FFF0000L, .CM_SHAPER_RAMA_EXP_REGION_END_R
= 0x0000FFFFL, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_R = 0x3FFF0000L
, .CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL
, .CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET
= 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L
, .CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS
= 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L
, .CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET
= 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L
, .CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS
= 0x70000000L, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x00000007L, .
CM_SHAPER_LUT_WRITE_SEL = 0x00000010L, .CM_SHAPER_LUT_INDEX =
0x000000FFL, .CM_SHAPER_LUT_DATA = 0x00FFFFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B
= 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G = 0x0003FFFFL
, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R = 0x0003FFFFL, .
CM_BLNDGAM_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_G
= 0x0000FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_R = 0x0000FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL, .
CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R
= 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL
, .CM_BLNDGAM_RAMA_EXP_REGION_END_G = 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_R
= 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B = 0xFFFF0000L
, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G = 0xFFFF0000L, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R
= 0xFFFF0000L, .CM_BLNDGAM_LUT_MODE = 0x00000003L, .CM_BLNDGAM_LUT_WRITE_EN_MASK
= 0x00000007L, .CM_BLNDGAM_LUT_WRITE_SEL = 0x00000010L, .CM_BLNDGAM_CONFIG_STATUS
= 0x00000300L, .CM_SHAPER_LUT_MODE = 0x00000003L, .CM_DGAM_CONFIG_STATUS
= 0x00000700L, .CM_BYPASS = 0x00000001L, .CURSOR_MODE = 0x00000700L
, .CURSOR_PITCH = 0x00030000L, .CURSOR_LINES_PER_CHUNK = 0x1F000000L
, .CURSOR_ENABLE = 0x00000001L, .FORMAT_CNV16 = 0x00000010L, .
CNVC_BYPASS_MSB_ALIGN = 0x00002000L, .CLAMP_POSITIVE = 0x00010000L
, .CLAMP_POSITIVE_C = 0x00020000L, .ALPHA_2BIT_LUT0 = 0x000000FFL
, .ALPHA_2BIT_LUT1 = 0x0000FF00L, .ALPHA_2BIT_LUT2 = 0x00FF0000L
, .ALPHA_2BIT_LUT3 = 0xFF000000L, .FCNV_FP_BIAS_R = 0x0007FFFFL
, .FCNV_FP_BIAS_G = 0x0007FFFFL, .FCNV_FP_BIAS_B = 0x0007FFFFL
, .FCNV_FP_SCALE_R = 0x0007FFFFL, .FCNV_FP_SCALE_G = 0x0007FFFFL
, .FCNV_FP_SCALE_B = 0x0007FFFFL, .COLOR_KEYER_EN = 0x00000001L
, .COLOR_KEYER_MODE = 0x00000030L, .COLOR_KEYER_ALPHA_LOW = 0x0000FFFFL
, .COLOR_KEYER_ALPHA_HIGH = 0xFFFF0000L, .COLOR_KEYER_RED_LOW
= 0x0000FFFFL, .COLOR_KEYER_RED_HIGH = 0xFFFF0000L, .COLOR_KEYER_GREEN_LOW
= 0x0000FFFFL, .COLOR_KEYER_GREEN_HIGH = 0xFFFF0000L, .COLOR_KEYER_BLUE_LOW
= 0x0000FFFFL, .COLOR_KEYER_BLUE_HIGH = 0xFFFF0000L, .CUR0_PIX_INV_MODE
= 0x00000004L, .CUR0_PIXEL_ALPHA_MOD_EN = 0x00000080L, .CUR0_ROM_EN
= 0x00000008L, .OBUF_MEM_PWR_FORCE = 0x00000003L, .LUT_MEM_PWR_FORCE
= 0x00000003L
481};
482
483static const struct dcn201_mpc_registers mpc_regs = {
484 MPC_REG_LIST_DCN201(0).MPCC_TOP_SEL[0] = 0x000034C0 + 0x1271, .MPCC_BOT_SEL[0] = 0x000034C0
+ 0x1272, .MPCC_CONTROL[0] = 0x000034C0 + 0x1274, .MPCC_STATUS
[0] = 0x000034C0 + 0x127f, .MPCC_OPP_ID[0] = 0x000034C0 + 0x1273
, .MPCC_BG_G_Y[0] = 0x000034C0 + 0x127b, .MPCC_BG_R_CR[0] = 0x000034C0
+ 0x127a, .MPCC_BG_B_CB[0] = 0x000034C0 + 0x127c, .MPCC_SM_CONTROL
[0] = 0x000034C0 + 0x1275, .MPCC_UPDATE_LOCK_SEL[0] = 0x000034C0
+ 0x1276, .MPCC_TOP_GAIN[0] = 0x000034C0 + 0x1277, .MPCC_BOT_GAIN_INSIDE
[0] = 0x000034C0 + 0x1278, .MPCC_BOT_GAIN_OUTSIDE[0] = 0x000034C0
+ 0x1279, .MPCC_OGAM_RAMA_START_CNTL_B[0] = 0x000034C0 + 0x13b2
, .MPCC_OGAM_RAMA_START_CNTL_G[0] = 0x000034C0 + 0x13b3, .MPCC_OGAM_RAMA_START_CNTL_R
[0] = 0x000034C0 + 0x13b4, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[0] = 0x000034C0
+ 0x13b5, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[0] = 0x000034C0 + 0x13b6
, .MPCC_OGAM_RAMA_SLOPE_CNTL_R[0] = 0x000034C0 + 0x13b7, .MPCC_OGAM_RAMA_END_CNTL1_B
[0] = 0x000034C0 + 0x13b8, .MPCC_OGAM_RAMA_END_CNTL2_B[0] = 0x000034C0
+ 0x13b9, .MPCC_OGAM_RAMA_END_CNTL1_G[0] = 0x000034C0 + 0x13ba
, .MPCC_OGAM_RAMA_END_CNTL2_G[0] = 0x000034C0 + 0x13bb, .MPCC_OGAM_RAMA_END_CNTL1_R
[0] = 0x000034C0 + 0x13bc, .MPCC_OGAM_RAMA_END_CNTL2_R[0] = 0x000034C0
+ 0x13bd, .MPCC_OGAM_RAMA_REGION_0_1[0] = 0x000034C0 + 0x13be
, .MPCC_OGAM_RAMA_REGION_32_33[0] = 0x000034C0 + 0x13ce, .MPCC_OGAM_RAMB_START_CNTL_B
[0] = 0x000034C0 + 0x13cf, .MPCC_OGAM_RAMB_START_CNTL_G[0] = 0x000034C0
+ 0x13d0, .MPCC_OGAM_RAMB_START_CNTL_R[0] = 0x000034C0 + 0x13d1
, .MPCC_OGAM_RAMB_SLOPE_CNTL_B[0] = 0x000034C0 + 0x13d2, .MPCC_OGAM_RAMB_SLOPE_CNTL_G
[0] = 0x000034C0 + 0x13d3, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[0] = 0x000034C0
+ 0x13d4, .MPCC_OGAM_RAMB_END_CNTL1_B[0] = 0x000034C0 + 0x13d5
, .MPCC_OGAM_RAMB_END_CNTL2_B[0] = 0x000034C0 + 0x13d6, .MPCC_OGAM_RAMB_END_CNTL1_G
[0] = 0x000034C0 + 0x13d7, .MPCC_OGAM_RAMB_END_CNTL2_G[0] = 0x000034C0
+ 0x13d8, .MPCC_OGAM_RAMB_END_CNTL1_R[0] = 0x000034C0 + 0x13d9
, .MPCC_OGAM_RAMB_END_CNTL2_R[0] = 0x000034C0 + 0x13da, .MPCC_OGAM_RAMB_REGION_0_1
[0] = 0x000034C0 + 0x13db, .MPCC_OGAM_RAMB_REGION_32_33[0] = 0x000034C0
+ 0x13eb, .MPCC_MEM_PWR_CTRL[0] = 0x000034C0 + 0x127d, .MPCC_OGAM_LUT_INDEX
[0] = 0x000034C0 + 0x13af, .MPCC_OGAM_LUT_RAM_CONTROL[0] = 0x000034C0
+ 0x13b1, .MPCC_OGAM_LUT_DATA[0] = 0x000034C0 + 0x13b0, .MPCC_OGAM_MODE
[0] = 0x000034C0 + 0x13ae,
485 MPC_REG_LIST_DCN201(1).MPCC_TOP_SEL[1] = 0x000034C0 + 0x128c, .MPCC_BOT_SEL[1] = 0x000034C0
+ 0x128d, .MPCC_CONTROL[1] = 0x000034C0 + 0x128f, .MPCC_STATUS
[1] = 0x000034C0 + 0x129a, .MPCC_OPP_ID[1] = 0x000034C0 + 0x128e
, .MPCC_BG_G_Y[1] = 0x000034C0 + 0x1296, .MPCC_BG_R_CR[1] = 0x000034C0
+ 0x1295, .MPCC_BG_B_CB[1] = 0x000034C0 + 0x1297, .MPCC_SM_CONTROL
[1] = 0x000034C0 + 0x1290, .MPCC_UPDATE_LOCK_SEL[1] = 0x000034C0
+ 0x1291, .MPCC_TOP_GAIN[1] = 0x000034C0 + 0x1292, .MPCC_BOT_GAIN_INSIDE
[1] = 0x000034C0 + 0x1293, .MPCC_BOT_GAIN_OUTSIDE[1] = 0x000034C0
+ 0x1294, .MPCC_OGAM_RAMA_START_CNTL_B[1] = 0x000034C0 + 0x13f3
, .MPCC_OGAM_RAMA_START_CNTL_G[1] = 0x000034C0 + 0x13f4, .MPCC_OGAM_RAMA_START_CNTL_R
[1] = 0x000034C0 + 0x13f5, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[1] = 0x000034C0
+ 0x13f6, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[1] = 0x000034C0 + 0x13f7
, .MPCC_OGAM_RAMA_SLOPE_CNTL_R[1] = 0x000034C0 + 0x13f8, .MPCC_OGAM_RAMA_END_CNTL1_B
[1] = 0x000034C0 + 0x13f9, .MPCC_OGAM_RAMA_END_CNTL2_B[1] = 0x000034C0
+ 0x13fa, .MPCC_OGAM_RAMA_END_CNTL1_G[1] = 0x000034C0 + 0x13fb
, .MPCC_OGAM_RAMA_END_CNTL2_G[1] = 0x000034C0 + 0x13fc, .MPCC_OGAM_RAMA_END_CNTL1_R
[1] = 0x000034C0 + 0x13fd, .MPCC_OGAM_RAMA_END_CNTL2_R[1] = 0x000034C0
+ 0x13fe, .MPCC_OGAM_RAMA_REGION_0_1[1] = 0x000034C0 + 0x13ff
, .MPCC_OGAM_RAMA_REGION_32_33[1] = 0x000034C0 + 0x140f, .MPCC_OGAM_RAMB_START_CNTL_B
[1] = 0x000034C0 + 0x1410, .MPCC_OGAM_RAMB_START_CNTL_G[1] = 0x000034C0
+ 0x1411, .MPCC_OGAM_RAMB_START_CNTL_R[1] = 0x000034C0 + 0x1412
, .MPCC_OGAM_RAMB_SLOPE_CNTL_B[1] = 0x000034C0 + 0x1413, .MPCC_OGAM_RAMB_SLOPE_CNTL_G
[1] = 0x000034C0 + 0x1414, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[1] = 0x000034C0
+ 0x1415, .MPCC_OGAM_RAMB_END_CNTL1_B[1] = 0x000034C0 + 0x1416
, .MPCC_OGAM_RAMB_END_CNTL2_B[1] = 0x000034C0 + 0x1417, .MPCC_OGAM_RAMB_END_CNTL1_G
[1] = 0x000034C0 + 0x1418, .MPCC_OGAM_RAMB_END_CNTL2_G[1] = 0x000034C0
+ 0x1419, .MPCC_OGAM_RAMB_END_CNTL1_R[1] = 0x000034C0 + 0x141a
, .MPCC_OGAM_RAMB_END_CNTL2_R[1] = 0x000034C0 + 0x141b, .MPCC_OGAM_RAMB_REGION_0_1
[1] = 0x000034C0 + 0x141c, .MPCC_OGAM_RAMB_REGION_32_33[1] = 0x000034C0
+ 0x142c, .MPCC_MEM_PWR_CTRL[1] = 0x000034C0 + 0x1298, .MPCC_OGAM_LUT_INDEX
[1] = 0x000034C0 + 0x13f0, .MPCC_OGAM_LUT_RAM_CONTROL[1] = 0x000034C0
+ 0x13f2, .MPCC_OGAM_LUT_DATA[1] = 0x000034C0 + 0x13f1, .MPCC_OGAM_MODE
[1] = 0x000034C0 + 0x13ef,
486 MPC_REG_LIST_DCN201(2).MPCC_TOP_SEL[2] = 0x000034C0 + 0x12a7, .MPCC_BOT_SEL[2] = 0x000034C0
+ 0x12a8, .MPCC_CONTROL[2] = 0x000034C0 + 0x12aa, .MPCC_STATUS
[2] = 0x000034C0 + 0x12b5, .MPCC_OPP_ID[2] = 0x000034C0 + 0x12a9
, .MPCC_BG_G_Y[2] = 0x000034C0 + 0x12b1, .MPCC_BG_R_CR[2] = 0x000034C0
+ 0x12b0, .MPCC_BG_B_CB[2] = 0x000034C0 + 0x12b2, .MPCC_SM_CONTROL
[2] = 0x000034C0 + 0x12ab, .MPCC_UPDATE_LOCK_SEL[2] = 0x000034C0
+ 0x12ac, .MPCC_TOP_GAIN[2] = 0x000034C0 + 0x12ad, .MPCC_BOT_GAIN_INSIDE
[2] = 0x000034C0 + 0x12ae, .MPCC_BOT_GAIN_OUTSIDE[2] = 0x000034C0
+ 0x12af, .MPCC_OGAM_RAMA_START_CNTL_B[2] = 0x000034C0 + 0x1434
, .MPCC_OGAM_RAMA_START_CNTL_G[2] = 0x000034C0 + 0x1435, .MPCC_OGAM_RAMA_START_CNTL_R
[2] = 0x000034C0 + 0x1436, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[2] = 0x000034C0
+ 0x1437, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[2] = 0x000034C0 + 0x1438
, .MPCC_OGAM_RAMA_SLOPE_CNTL_R[2] = 0x000034C0 + 0x1439, .MPCC_OGAM_RAMA_END_CNTL1_B
[2] = 0x000034C0 + 0x143a, .MPCC_OGAM_RAMA_END_CNTL2_B[2] = 0x000034C0
+ 0x143b, .MPCC_OGAM_RAMA_END_CNTL1_G[2] = 0x000034C0 + 0x143c
, .MPCC_OGAM_RAMA_END_CNTL2_G[2] = 0x000034C0 + 0x143d, .MPCC_OGAM_RAMA_END_CNTL1_R
[2] = 0x000034C0 + 0x143e, .MPCC_OGAM_RAMA_END_CNTL2_R[2] = 0x000034C0
+ 0x143f, .MPCC_OGAM_RAMA_REGION_0_1[2] = 0x000034C0 + 0x1440
, .MPCC_OGAM_RAMA_REGION_32_33[2] = 0x000034C0 + 0x1450, .MPCC_OGAM_RAMB_START_CNTL_B
[2] = 0x000034C0 + 0x1451, .MPCC_OGAM_RAMB_START_CNTL_G[2] = 0x000034C0
+ 0x1452, .MPCC_OGAM_RAMB_START_CNTL_R[2] = 0x000034C0 + 0x1453
, .MPCC_OGAM_RAMB_SLOPE_CNTL_B[2] = 0x000034C0 + 0x1454, .MPCC_OGAM_RAMB_SLOPE_CNTL_G
[2] = 0x000034C0 + 0x1455, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[2] = 0x000034C0
+ 0x1456, .MPCC_OGAM_RAMB_END_CNTL1_B[2] = 0x000034C0 + 0x1457
, .MPCC_OGAM_RAMB_END_CNTL2_B[2] = 0x000034C0 + 0x1458, .MPCC_OGAM_RAMB_END_CNTL1_G
[2] = 0x000034C0 + 0x1459, .MPCC_OGAM_RAMB_END_CNTL2_G[2] = 0x000034C0
+ 0x145a, .MPCC_OGAM_RAMB_END_CNTL1_R[2] = 0x000034C0 + 0x145b
, .MPCC_OGAM_RAMB_END_CNTL2_R[2] = 0x000034C0 + 0x145c, .MPCC_OGAM_RAMB_REGION_0_1
[2] = 0x000034C0 + 0x145d, .MPCC_OGAM_RAMB_REGION_32_33[2] = 0x000034C0
+ 0x146d, .MPCC_MEM_PWR_CTRL[2] = 0x000034C0 + 0x12b3, .MPCC_OGAM_LUT_INDEX
[2] = 0x000034C0 + 0x1431, .MPCC_OGAM_LUT_RAM_CONTROL[2] = 0x000034C0
+ 0x1433, .MPCC_OGAM_LUT_DATA[2] = 0x000034C0 + 0x1432, .MPCC_OGAM_MODE
[2] = 0x000034C0 + 0x1430,
487 MPC_REG_LIST_DCN201(3).MPCC_TOP_SEL[3] = 0x000034C0 + 0x12c2, .MPCC_BOT_SEL[3] = 0x000034C0
+ 0x12c3, .MPCC_CONTROL[3] = 0x000034C0 + 0x12c5, .MPCC_STATUS
[3] = 0x000034C0 + 0x12d0, .MPCC_OPP_ID[3] = 0x000034C0 + 0x12c4
, .MPCC_BG_G_Y[3] = 0x000034C0 + 0x12cc, .MPCC_BG_R_CR[3] = 0x000034C0
+ 0x12cb, .MPCC_BG_B_CB[3] = 0x000034C0 + 0x12cd, .MPCC_SM_CONTROL
[3] = 0x000034C0 + 0x12c6, .MPCC_UPDATE_LOCK_SEL[3] = 0x000034C0
+ 0x12c7, .MPCC_TOP_GAIN[3] = 0x000034C0 + 0x12c8, .MPCC_BOT_GAIN_INSIDE
[3] = 0x000034C0 + 0x12c9, .MPCC_BOT_GAIN_OUTSIDE[3] = 0x000034C0
+ 0x12ca, .MPCC_OGAM_RAMA_START_CNTL_B[3] = 0x000034C0 + 0x1475
, .MPCC_OGAM_RAMA_START_CNTL_G[3] = 0x000034C0 + 0x1476, .MPCC_OGAM_RAMA_START_CNTL_R
[3] = 0x000034C0 + 0x1477, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[3] = 0x000034C0
+ 0x1478, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[3] = 0x000034C0 + 0x1479
, .MPCC_OGAM_RAMA_SLOPE_CNTL_R[3] = 0x000034C0 + 0x147a, .MPCC_OGAM_RAMA_END_CNTL1_B
[3] = 0x000034C0 + 0x147b, .MPCC_OGAM_RAMA_END_CNTL2_B[3] = 0x000034C0
+ 0x147c, .MPCC_OGAM_RAMA_END_CNTL1_G[3] = 0x000034C0 + 0x147d
, .MPCC_OGAM_RAMA_END_CNTL2_G[3] = 0x000034C0 + 0x147e, .MPCC_OGAM_RAMA_END_CNTL1_R
[3] = 0x000034C0 + 0x147f, .MPCC_OGAM_RAMA_END_CNTL2_R[3] = 0x000034C0
+ 0x1480, .MPCC_OGAM_RAMA_REGION_0_1[3] = 0x000034C0 + 0x1481
, .MPCC_OGAM_RAMA_REGION_32_33[3] = 0x000034C0 + 0x1491, .MPCC_OGAM_RAMB_START_CNTL_B
[3] = 0x000034C0 + 0x1492, .MPCC_OGAM_RAMB_START_CNTL_G[3] = 0x000034C0
+ 0x1493, .MPCC_OGAM_RAMB_START_CNTL_R[3] = 0x000034C0 + 0x1494
, .MPCC_OGAM_RAMB_SLOPE_CNTL_B[3] = 0x000034C0 + 0x1495, .MPCC_OGAM_RAMB_SLOPE_CNTL_G
[3] = 0x000034C0 + 0x1496, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[3] = 0x000034C0
+ 0x1497, .MPCC_OGAM_RAMB_END_CNTL1_B[3] = 0x000034C0 + 0x1498
, .MPCC_OGAM_RAMB_END_CNTL2_B[3] = 0x000034C0 + 0x1499, .MPCC_OGAM_RAMB_END_CNTL1_G
[3] = 0x000034C0 + 0x149a, .MPCC_OGAM_RAMB_END_CNTL2_G[3] = 0x000034C0
+ 0x149b, .MPCC_OGAM_RAMB_END_CNTL1_R[3] = 0x000034C0 + 0x149c
, .MPCC_OGAM_RAMB_END_CNTL2_R[3] = 0x000034C0 + 0x149d, .MPCC_OGAM_RAMB_REGION_0_1
[3] = 0x000034C0 + 0x149e, .MPCC_OGAM_RAMB_REGION_32_33[3] = 0x000034C0
+ 0x14ae, .MPCC_MEM_PWR_CTRL[3] = 0x000034C0 + 0x12ce, .MPCC_OGAM_LUT_INDEX
[3] = 0x000034C0 + 0x1472, .MPCC_OGAM_LUT_RAM_CONTROL[3] = 0x000034C0
+ 0x1474, .MPCC_OGAM_LUT_DATA[3] = 0x000034C0 + 0x1473, .MPCC_OGAM_MODE
[3] = 0x000034C0 + 0x1471,
488 MPC_REG_LIST_DCN201(4).MPCC_TOP_SEL[4] = 0x000034C0 + 0x12dd, .MPCC_BOT_SEL[4] = 0x000034C0
+ 0x12de, .MPCC_CONTROL[4] = 0x000034C0 + 0x12e0, .MPCC_STATUS
[4] = 0x000034C0 + 0x12eb, .MPCC_OPP_ID[4] = 0x000034C0 + 0x12df
, .MPCC_BG_G_Y[4] = 0x000034C0 + 0x12e7, .MPCC_BG_R_CR[4] = 0x000034C0
+ 0x12e6, .MPCC_BG_B_CB[4] = 0x000034C0 + 0x12e8, .MPCC_SM_CONTROL
[4] = 0x000034C0 + 0x12e1, .MPCC_UPDATE_LOCK_SEL[4] = 0x000034C0
+ 0x12e2, .MPCC_TOP_GAIN[4] = 0x000034C0 + 0x12e3, .MPCC_BOT_GAIN_INSIDE
[4] = 0x000034C0 + 0x12e4, .MPCC_BOT_GAIN_OUTSIDE[4] = 0x000034C0
+ 0x12e5, .MPCC_OGAM_RAMA_START_CNTL_B[4] = 0x000034C0 + 0x14b6
, .MPCC_OGAM_RAMA_START_CNTL_G[4] = 0x000034C0 + 0x14b7, .MPCC_OGAM_RAMA_START_CNTL_R
[4] = 0x000034C0 + 0x14b8, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[4] = 0x000034C0
+ 0x14b9, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[4] = 0x000034C0 + 0x14ba
, .MPCC_OGAM_RAMA_SLOPE_CNTL_R[4] = 0x000034C0 + 0x14bb, .MPCC_OGAM_RAMA_END_CNTL1_B
[4] = 0x000034C0 + 0x14bc, .MPCC_OGAM_RAMA_END_CNTL2_B[4] = 0x000034C0
+ 0x14bd, .MPCC_OGAM_RAMA_END_CNTL1_G[4] = 0x000034C0 + 0x14be
, .MPCC_OGAM_RAMA_END_CNTL2_G[4] = 0x000034C0 + 0x14bf, .MPCC_OGAM_RAMA_END_CNTL1_R
[4] = 0x000034C0 + 0x14c0, .MPCC_OGAM_RAMA_END_CNTL2_R[4] = 0x000034C0
+ 0x14c1, .MPCC_OGAM_RAMA_REGION_0_1[4] = 0x000034C0 + 0x14c2
, .MPCC_OGAM_RAMA_REGION_32_33[4] = 0x000034C0 + 0x14d2, .MPCC_OGAM_RAMB_START_CNTL_B
[4] = 0x000034C0 + 0x14d3, .MPCC_OGAM_RAMB_START_CNTL_G[4] = 0x000034C0
+ 0x14d4, .MPCC_OGAM_RAMB_START_CNTL_R[4] = 0x000034C0 + 0x14d5
, .MPCC_OGAM_RAMB_SLOPE_CNTL_B[4] = 0x000034C0 + 0x14d6, .MPCC_OGAM_RAMB_SLOPE_CNTL_G
[4] = 0x000034C0 + 0x14d7, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[4] = 0x000034C0
+ 0x14d8, .MPCC_OGAM_RAMB_END_CNTL1_B[4] = 0x000034C0 + 0x14d9
, .MPCC_OGAM_RAMB_END_CNTL2_B[4] = 0x000034C0 + 0x14da, .MPCC_OGAM_RAMB_END_CNTL1_G
[4] = 0x000034C0 + 0x14db, .MPCC_OGAM_RAMB_END_CNTL2_G[4] = 0x000034C0
+ 0x14dc, .MPCC_OGAM_RAMB_END_CNTL1_R[4] = 0x000034C0 + 0x14dd
, .MPCC_OGAM_RAMB_END_CNTL2_R[4] = 0x000034C0 + 0x14de, .MPCC_OGAM_RAMB_REGION_0_1
[4] = 0x000034C0 + 0x14df, .MPCC_OGAM_RAMB_REGION_32_33[4] = 0x000034C0
+ 0x14ef, .MPCC_MEM_PWR_CTRL[4] = 0x000034C0 + 0x12e9, .MPCC_OGAM_LUT_INDEX
[4] = 0x000034C0 + 0x14b3, .MPCC_OGAM_LUT_RAM_CONTROL[4] = 0x000034C0
+ 0x14b5, .MPCC_OGAM_LUT_DATA[4] = 0x000034C0 + 0x14b4, .MPCC_OGAM_MODE
[4] = 0x000034C0 + 0x14b2,
489 MPC_OUT_MUX_REG_LIST_DCN201(0).MUX[0] = 0x000034C0 + 0x1385, .CUR[0] = 0x000034C0 + 0x1361,
.CSC_MODE[0] = 0x000034C0 + 0x15b7, .CSC_C11_C12_A[0] = 0x000034C0
+ 0x15b8, .CSC_C33_C34_A[0] = 0x000034C0 + 0x15bd, .CSC_C11_C12_B
[0] = 0x000034C0 + 0x15be, .CSC_C33_C34_B[0] = 0x000034C0 + 0x15c3
, .DENORM_CONTROL[0] = 0x000034C0 + 0x1386, .DENORM_CLAMP_G_Y
[0] = 0x000034C0 + 0x1387, .DENORM_CLAMP_B_CB[0] = 0x000034C0
+ 0x1388,
490 MPC_OUT_MUX_REG_LIST_DCN201(1).MUX[1] = 0x000034C0 + 0x1389, .CUR[1] = 0x000034C0 + 0x1366,
.CSC_MODE[1] = 0x000034C0 + 0x15c4, .CSC_C11_C12_A[1] = 0x000034C0
+ 0x15c5, .CSC_C33_C34_A[1] = 0x000034C0 + 0x15ca, .CSC_C11_C12_B
[1] = 0x000034C0 + 0x15cb, .CSC_C33_C34_B[1] = 0x000034C0 + 0x15d0
, .DENORM_CONTROL[1] = 0x000034C0 + 0x138a, .DENORM_CLAMP_G_Y
[1] = 0x000034C0 + 0x138b, .DENORM_CLAMP_B_CB[1] = 0x000034C0
+ 0x138c,
491};
492
493static const struct dcn201_mpc_shift mpc_shift = {
494 MPC_COMMON_MASK_SH_LIST_DCN201(__SHIFT).MPCC_TOP_SEL = 0x0, .MPCC_BOT_SEL = 0x0, .MPCC_MODE = 0x0, .
MPCC_ALPHA_BLND_MODE = 0x4, .MPCC_ALPHA_MULTIPLIED_MODE = 0x6
, .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x7, .MPCC_GLOBAL_ALPHA = 0x10
, .MPCC_GLOBAL_GAIN = 0x18, .MPCC_IDLE = 0x0, .MPCC_BUSY = 0x1
, .MPCC_OPP_ID = 0x0, .MPCC_BG_G_Y = 0x0, .MPCC_BG_R_CR = 0x0
, .MPCC_BG_B_CB = 0x0, .MPCC_SM_EN = 0x0, .MPCC_SM_MODE = 0x1
, .MPCC_SM_FRAME_ALT = 0x4, .MPCC_SM_FIELD_ALT = 0x5, .MPCC_SM_FORCE_NEXT_FRAME_POL
= 0x8, .MPCC_SM_FORCE_NEXT_TOP_POL = 0x10, .MPC_OUT_MUX = 0x0
, .MPCC_UPDATE_LOCK_SEL = 0x0, .MPCC_BG_BPC = 0x8, .MPCC_BOT_GAIN_MODE
= 0xb, .MPCC_TOP_GAIN = 0x0, .MPCC_BOT_GAIN_INSIDE = 0x0, .MPCC_BOT_GAIN_OUTSIDE
= 0x0, .MPC_OCSC_TEST_DEBUG_INDEX = 0x0, .MPC_OCSC_MODE = 0x0
, .MPC_OCSC_C11_A = 0x0, .MPC_OCSC_C12_A = 0x10, .MPCC_DISABLED
= 0x2, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS
= 0xc, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS
= 0x1c, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B
= 0x0, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x10, .MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B
= 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B
= 0x14, .MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS
= 0xc, .MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS
= 0x1c, .MPCC_OGAM_RAMB_EXP_REGION_END_B = 0x0, .MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B
= 0x0, .MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B = 0x10, .MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B
= 0x0, .MPCC_OGAM_RAMB_EXP_REGION_START_B = 0x0, .MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B
= 0x14, .MPCC_OGAM_MEM_PWR_FORCE = 0x0, .MPCC_OGAM_MEM_PWR_DIS
= 0x2, .MPCC_OGAM_LUT_INDEX = 0x0, .MPCC_OGAM_LUT_WRITE_EN_MASK
= 0x0, .MPCC_OGAM_LUT_RAM_SEL = 0x3, .MPCC_OGAM_CONFIG_STATUS
= 0x4, .MPCC_OGAM_LUT_DATA = 0x0, .MPCC_OGAM_MODE = 0x0, .MPC_OUT_DENORM_MODE
= 0x18, .MPC_OUT_DENORM_CLAMP_MAX_R_CR = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_R_CR
= 0x0, .MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_G_Y
= 0x0, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_B_CB
= 0x0, .CUR_VUPDATE_LOCK_SET = 0x0, .MPC_OUT_RATE_CONTROL = 0x9
, .MPC_OUT_RATE_CONTROL_DISABLE = 0x8, .MPC_OUT_FLOW_CONTROL_MODE
= 0xa, .MPC_OUT_FLOW_CONTROL_COUNT0 = 0xb, .MPC_OUT_FLOW_CONTROL_COUNT1
= 0x14
495};
496
497static const struct dcn201_mpc_mask mpc_mask = {
498 MPC_COMMON_MASK_SH_LIST_DCN201(_MASK).MPCC_TOP_SEL = 0x0000000FL, .MPCC_BOT_SEL = 0x0000000FL, .MPCC_MODE
= 0x00000003L, .MPCC_ALPHA_BLND_MODE = 0x00000030L, .MPCC_ALPHA_MULTIPLIED_MODE
= 0x00000040L, .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x00000080L,
.MPCC_GLOBAL_ALPHA = 0x00FF0000L, .MPCC_GLOBAL_GAIN = 0xFF000000L
, .MPCC_IDLE = 0x00000001L, .MPCC_BUSY = 0x00000002L, .MPCC_OPP_ID
= 0x0000000FL, .MPCC_BG_G_Y = 0x00000FFFL, .MPCC_BG_R_CR = 0x00000FFFL
, .MPCC_BG_B_CB = 0x00000FFFL, .MPCC_SM_EN = 0x00000001L, .MPCC_SM_MODE
= 0x0000000EL, .MPCC_SM_FRAME_ALT = 0x00000010L, .MPCC_SM_FIELD_ALT
= 0x00000020L, .MPCC_SM_FORCE_NEXT_FRAME_POL = 0x00000300L, .
MPCC_SM_FORCE_NEXT_TOP_POL = 0x00030000L, .MPC_OUT_MUX = 0x0000000FL
, .MPCC_UPDATE_LOCK_SEL = 0x0000000FL, .MPCC_BG_BPC = 0x00000700L
, .MPCC_BOT_GAIN_MODE = 0x00000800L, .MPCC_TOP_GAIN = 0x0007FFFFL
, .MPCC_BOT_GAIN_INSIDE = 0x0007FFFFL, .MPCC_BOT_GAIN_OUTSIDE
= 0x0007FFFFL, .MPC_OCSC_TEST_DEBUG_INDEX = 0x000000FFL, .MPC_OCSC_MODE
= 0x00000003L, .MPC_OCSC_C11_A = 0x0000FFFFL, .MPC_OCSC_C12_A
= 0xFFFF0000L, .MPCC_DISABLED = 0x00000004L, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET
= 0x000001FFL, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L
, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS
= 0x70000000L, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL
, .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0000FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B
= 0xFFFF0000L, .MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL
, .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B
= 0x07F00000L, .MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL
, .MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET
= 0x01FF0000L, .MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L
, .MPCC_OGAM_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B
= 0x0000FFFFL, .MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B = 0xFFFF0000L
, .MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL, .MPCC_OGAM_RAMB_EXP_REGION_START_B
= 0x0003FFFFL, .MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L
, .MPCC_OGAM_MEM_PWR_FORCE = 0x00000003L, .MPCC_OGAM_MEM_PWR_DIS
= 0x00000004L, .MPCC_OGAM_LUT_INDEX = 0x000001FFL, .MPCC_OGAM_LUT_WRITE_EN_MASK
= 0x00000007L, .MPCC_OGAM_LUT_RAM_SEL = 0x00000008L, .MPCC_OGAM_CONFIG_STATUS
= 0x00000030L, .MPCC_OGAM_LUT_DATA = 0x0007FFFFL, .MPCC_OGAM_MODE
= 0x00000003L, .MPC_OUT_DENORM_MODE = 0x07000000L, .MPC_OUT_DENORM_CLAMP_MAX_R_CR
= 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_R_CR = 0x00000FFFL,
.MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_G_Y
= 0x00000FFFL, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0x00FFF000L,
.MPC_OUT_DENORM_CLAMP_MIN_B_CB = 0x00000FFFL, .CUR_VUPDATE_LOCK_SET
= 0x00000001L, .MPC_OUT_RATE_CONTROL = 0x00000200L, .MPC_OUT_RATE_CONTROL_DISABLE
= 0x00000100L, .MPC_OUT_FLOW_CONTROL_MODE = 0x00000400L, .MPC_OUT_FLOW_CONTROL_COUNT0
= 0x000FF800L, .MPC_OUT_FLOW_CONTROL_COUNT1 = 0xFFF00000L
499};
500
501#define tg_regs_dcn201(id)[id] = {.OTG_VSTARTUP_PARAM = DMU_BASE__INST0_SEGmmOTGid_OTG_VSTARTUP_PARAM_BASE_IDX
+ mmOTGid_OTG_VSTARTUP_PARAM, .OTG_VUPDATE_PARAM = DMU_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_PARAM_BASE_IDX
+ mmOTGid_OTG_VUPDATE_PARAM, .OTG_VREADY_PARAM = DMU_BASE__INST0_SEGmmOTGid_OTG_VREADY_PARAM_BASE_IDX
+ mmOTGid_OTG_VREADY_PARAM, .OTG_BLANK_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_BLANK_CONTROL_BASE_IDX
+ mmOTGid_OTG_BLANK_CONTROL, .OTG_MASTER_UPDATE_LOCK = DMU_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX
+ mmOTGid_OTG_MASTER_UPDATE_LOCK, .OTG_GLOBAL_CONTROL0 = DMU_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL0, .OTG_DOUBLE_BUFFER_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX
+ mmOTGid_OTG_DOUBLE_BUFFER_CONTROL, .OTG_H_TOTAL = DMU_BASE__INST0_SEGmmOTGid_OTG_H_TOTAL_BASE_IDX
+ mmOTGid_OTG_H_TOTAL, .OTG_H_BLANK_START_END = DMU_BASE__INST0_SEGmmOTGid_OTG_H_BLANK_START_END_BASE_IDX
+ mmOTGid_OTG_H_BLANK_START_END, .OTG_H_SYNC_A = DMU_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_BASE_IDX
+ mmOTGid_OTG_H_SYNC_A, .OTG_H_SYNC_A_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX
+ mmOTGid_OTG_H_SYNC_A_CNTL, .OTG_H_TIMING_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_H_TIMING_CNTL_BASE_IDX
+ mmOTGid_OTG_H_TIMING_CNTL, .OTG_V_TOTAL = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_BASE_IDX
+ mmOTGid_OTG_V_TOTAL, .OTG_V_BLANK_START_END = DMU_BASE__INST0_SEGmmOTGid_OTG_V_BLANK_START_END_BASE_IDX
+ mmOTGid_OTG_V_BLANK_START_END, .OTG_V_SYNC_A = DMU_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_BASE_IDX
+ mmOTGid_OTG_V_SYNC_A, .OTG_V_SYNC_A_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX
+ mmOTGid_OTG_V_SYNC_A_CNTL, .OTG_INTERLACE_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_INTERLACE_CONTROL_BASE_IDX
+ mmOTGid_OTG_INTERLACE_CONTROL, .OTG_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_CONTROL_BASE_IDX
+ mmOTGid_OTG_CONTROL, .OTG_STEREO_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_STEREO_CONTROL_BASE_IDX
+ mmOTGid_OTG_STEREO_CONTROL, .OTG_3D_STRUCTURE_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX
+ mmOTGid_OTG_3D_STRUCTURE_CONTROL, .OTG_STEREO_STATUS = DMU_BASE__INST0_SEGmmOTGid_OTG_STEREO_STATUS_BASE_IDX
+ mmOTGid_OTG_STEREO_STATUS, .OTG_V_TOTAL_MAX = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MAX_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MAX, .OTG_V_TOTAL_MID = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MID_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MID, .OTG_V_TOTAL_MIN = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MIN_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MIN, .OTG_V_TOTAL_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_CONTROL, .OTG_TRIGA_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_TRIGA_CNTL_BASE_IDX
+ mmOTGid_OTG_TRIGA_CNTL, .OTG_FORCE_COUNT_NOW_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX
+ mmOTGid_OTG_FORCE_COUNT_NOW_CNTL, .OTG_STATIC_SCREEN_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX
+ mmOTGid_OTG_STATIC_SCREEN_CONTROL, .OTG_STATUS_FRAME_COUNT
= DMU_BASE__INST0_SEGmmOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX
+ mmOTGid_OTG_STATUS_FRAME_COUNT, .OTG_STATUS = DMU_BASE__INST0_SEGmmOTGid_OTG_STATUS_BASE_IDX
+ mmOTGid_OTG_STATUS, .OTG_STATUS_POSITION = DMU_BASE__INST0_SEGmmOTGid_OTG_STATUS_POSITION_BASE_IDX
+ mmOTGid_OTG_STATUS_POSITION, .OTG_NOM_VERT_POSITION = DMU_BASE__INST0_SEGmmOTGid_OTG_NOM_VERT_POSITION_BASE_IDX
+ mmOTGid_OTG_NOM_VERT_POSITION, .OTG_BLACK_COLOR = DMU_BASE__INST0_SEGmmOTGid_OTG_BLACK_COLOR_BASE_IDX
+ mmOTGid_OTG_BLACK_COLOR, .OTG_CLOCK_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_CLOCK_CONTROL_BASE_IDX
+ mmOTGid_OTG_CLOCK_CONTROL, .OTG_VERTICAL_INTERRUPT0_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, .OTG_VERTICAL_INTERRUPT0_POSITION
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, .OTG_VERTICAL_INTERRUPT1_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, .OTG_VERTICAL_INTERRUPT1_POSITION
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, .OTG_VERTICAL_INTERRUPT2_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, .OTG_VERTICAL_INTERRUPT2_POSITION
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, .OPTC_INPUT_CLOCK_CONTROL
= DMU_BASE__INST0_SEGmmODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX
+ mmODMid_OPTC_INPUT_CLOCK_CONTROL, .OPTC_DATA_SOURCE_SELECT
= DMU_BASE__INST0_SEGmmODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX
+ mmODMid_OPTC_DATA_SOURCE_SELECT, .OPTC_INPUT_GLOBAL_CONTROL
= DMU_BASE__INST0_SEGmmODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
+ mmODMid_OPTC_INPUT_GLOBAL_CONTROL, .CONTROL = DMU_BASE__INST0_SEGmmVTGid_CONTROL_BASE_IDX
+ mmVTGid_CONTROL, .OTG_VERT_SYNC_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERT_SYNC_CONTROL, .OTG_MASTER_UPDATE_MODE = DMU_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_MODE_BASE_IDX
+ mmOTGid_OTG_MASTER_UPDATE_MODE, .OTG_GSL_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_GSL_CONTROL_BASE_IDX
+ mmOTGid_OTG_GSL_CONTROL, .OTG_CRC_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL_BASE_IDX
+ mmOTGid_OTG_CRC_CNTL, .OTG_CRC0_DATA_RG = DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_RG_BASE_IDX
+ mmOTGid_OTG_CRC0_DATA_RG, .OTG_CRC0_DATA_B = DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_B_BASE_IDX
+ mmOTGid_OTG_CRC0_DATA_B, .OTG_CRC0_WINDOWA_X_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWA_X_CONTROL, .OTG_CRC0_WINDOWA_Y_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, .OTG_CRC0_WINDOWB_X_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWB_X_CONTROL, .OTG_CRC0_WINDOWB_Y_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, .GSL_SOURCE_SELECT = 0x000034C0
+ 0x1e2b, .OTG_GLOBAL_CONTROL2 = DMU_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_TRIGA_MANUAL_TRIG = DMU_BASE__INST0_SEGmmOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX
+ mmOTGid_OTG_TRIGA_MANUAL_TRIG, .OTG_GLOBAL_CONTROL1 = DMU_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DMU_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_GSL_WINDOW_X = DMU_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_X_BASE_IDX
+ mmOTGid_OTG_GSL_WINDOW_X, .OTG_GSL_WINDOW_Y = DMU_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_Y_BASE_IDX
+ mmOTGid_OTG_GSL_WINDOW_Y, .OTG_VUPDATE_KEEPOUT = DMU_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX
+ mmOTGid_OTG_VUPDATE_KEEPOUT, .OTG_DSC_START_POSITION = DMU_BASE__INST0_SEGmmOTGid_OTG_DSC_START_POSITION_BASE_IDX
+ mmOTGid_OTG_DSC_START_POSITION, .OPTC_DATA_FORMAT_CONTROL =
DMU_BASE__INST0_SEGmmODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX
+ mmODMid_OPTC_DATA_FORMAT_CONTROL, .OPTC_BYTES_PER_PIXEL = DMU_BASE__INST0_SEGmmODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX
+ mmODMid_OPTC_BYTES_PER_PIXEL, .OPTC_WIDTH_CONTROL = DMU_BASE__INST0_SEGmmODMid_OPTC_WIDTH_CONTROL_BASE_IDX
+ mmODMid_OPTC_WIDTH_CONTROL, .DWB_SOURCE_SELECT = 0x000034C0
+ 0x1e2a}\
502[id] = {TG_COMMON_REG_LIST_DCN201(id).OTG_VSTARTUP_PARAM = DMU_BASE__INST0_SEGmmOTGid_OTG_VSTARTUP_PARAM_BASE_IDX
+ mmOTGid_OTG_VSTARTUP_PARAM, .OTG_VUPDATE_PARAM = DMU_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_PARAM_BASE_IDX
+ mmOTGid_OTG_VUPDATE_PARAM, .OTG_VREADY_PARAM = DMU_BASE__INST0_SEGmmOTGid_OTG_VREADY_PARAM_BASE_IDX
+ mmOTGid_OTG_VREADY_PARAM, .OTG_BLANK_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_BLANK_CONTROL_BASE_IDX
+ mmOTGid_OTG_BLANK_CONTROL, .OTG_MASTER_UPDATE_LOCK = DMU_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX
+ mmOTGid_OTG_MASTER_UPDATE_LOCK, .OTG_GLOBAL_CONTROL0 = DMU_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL0, .OTG_DOUBLE_BUFFER_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX
+ mmOTGid_OTG_DOUBLE_BUFFER_CONTROL, .OTG_H_TOTAL = DMU_BASE__INST0_SEGmmOTGid_OTG_H_TOTAL_BASE_IDX
+ mmOTGid_OTG_H_TOTAL, .OTG_H_BLANK_START_END = DMU_BASE__INST0_SEGmmOTGid_OTG_H_BLANK_START_END_BASE_IDX
+ mmOTGid_OTG_H_BLANK_START_END, .OTG_H_SYNC_A = DMU_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_BASE_IDX
+ mmOTGid_OTG_H_SYNC_A, .OTG_H_SYNC_A_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX
+ mmOTGid_OTG_H_SYNC_A_CNTL, .OTG_H_TIMING_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_H_TIMING_CNTL_BASE_IDX
+ mmOTGid_OTG_H_TIMING_CNTL, .OTG_V_TOTAL = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_BASE_IDX
+ mmOTGid_OTG_V_TOTAL, .OTG_V_BLANK_START_END = DMU_BASE__INST0_SEGmmOTGid_OTG_V_BLANK_START_END_BASE_IDX
+ mmOTGid_OTG_V_BLANK_START_END, .OTG_V_SYNC_A = DMU_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_BASE_IDX
+ mmOTGid_OTG_V_SYNC_A, .OTG_V_SYNC_A_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX
+ mmOTGid_OTG_V_SYNC_A_CNTL, .OTG_INTERLACE_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_INTERLACE_CONTROL_BASE_IDX
+ mmOTGid_OTG_INTERLACE_CONTROL, .OTG_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_CONTROL_BASE_IDX
+ mmOTGid_OTG_CONTROL, .OTG_STEREO_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_STEREO_CONTROL_BASE_IDX
+ mmOTGid_OTG_STEREO_CONTROL, .OTG_3D_STRUCTURE_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX
+ mmOTGid_OTG_3D_STRUCTURE_CONTROL, .OTG_STEREO_STATUS = DMU_BASE__INST0_SEGmmOTGid_OTG_STEREO_STATUS_BASE_IDX
+ mmOTGid_OTG_STEREO_STATUS, .OTG_V_TOTAL_MAX = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MAX_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MAX, .OTG_V_TOTAL_MID = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MID_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MID, .OTG_V_TOTAL_MIN = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MIN_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_MIN, .OTG_V_TOTAL_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX
+ mmOTGid_OTG_V_TOTAL_CONTROL, .OTG_TRIGA_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_TRIGA_CNTL_BASE_IDX
+ mmOTGid_OTG_TRIGA_CNTL, .OTG_FORCE_COUNT_NOW_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX
+ mmOTGid_OTG_FORCE_COUNT_NOW_CNTL, .OTG_STATIC_SCREEN_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX
+ mmOTGid_OTG_STATIC_SCREEN_CONTROL, .OTG_STATUS_FRAME_COUNT
= DMU_BASE__INST0_SEGmmOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX
+ mmOTGid_OTG_STATUS_FRAME_COUNT, .OTG_STATUS = DMU_BASE__INST0_SEGmmOTGid_OTG_STATUS_BASE_IDX
+ mmOTGid_OTG_STATUS, .OTG_STATUS_POSITION = DMU_BASE__INST0_SEGmmOTGid_OTG_STATUS_POSITION_BASE_IDX
+ mmOTGid_OTG_STATUS_POSITION, .OTG_NOM_VERT_POSITION = DMU_BASE__INST0_SEGmmOTGid_OTG_NOM_VERT_POSITION_BASE_IDX
+ mmOTGid_OTG_NOM_VERT_POSITION, .OTG_BLACK_COLOR = DMU_BASE__INST0_SEGmmOTGid_OTG_BLACK_COLOR_BASE_IDX
+ mmOTGid_OTG_BLACK_COLOR, .OTG_CLOCK_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_CLOCK_CONTROL_BASE_IDX
+ mmOTGid_OTG_CLOCK_CONTROL, .OTG_VERTICAL_INTERRUPT0_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, .OTG_VERTICAL_INTERRUPT0_POSITION
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, .OTG_VERTICAL_INTERRUPT1_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, .OTG_VERTICAL_INTERRUPT1_POSITION
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, .OTG_VERTICAL_INTERRUPT2_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, .OTG_VERTICAL_INTERRUPT2_POSITION
= DMU_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX
+ mmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, .OPTC_INPUT_CLOCK_CONTROL
= DMU_BASE__INST0_SEGmmODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX
+ mmODMid_OPTC_INPUT_CLOCK_CONTROL, .OPTC_DATA_SOURCE_SELECT
= DMU_BASE__INST0_SEGmmODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX
+ mmODMid_OPTC_DATA_SOURCE_SELECT, .OPTC_INPUT_GLOBAL_CONTROL
= DMU_BASE__INST0_SEGmmODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
+ mmODMid_OPTC_INPUT_GLOBAL_CONTROL, .CONTROL = DMU_BASE__INST0_SEGmmVTGid_CONTROL_BASE_IDX
+ mmVTGid_CONTROL, .OTG_VERT_SYNC_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX
+ mmOTGid_OTG_VERT_SYNC_CONTROL, .OTG_MASTER_UPDATE_MODE = DMU_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_MODE_BASE_IDX
+ mmOTGid_OTG_MASTER_UPDATE_MODE, .OTG_GSL_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_GSL_CONTROL_BASE_IDX
+ mmOTGid_OTG_GSL_CONTROL, .OTG_CRC_CNTL = DMU_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL_BASE_IDX
+ mmOTGid_OTG_CRC_CNTL, .OTG_CRC0_DATA_RG = DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_RG_BASE_IDX
+ mmOTGid_OTG_CRC0_DATA_RG, .OTG_CRC0_DATA_B = DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_B_BASE_IDX
+ mmOTGid_OTG_CRC0_DATA_B, .OTG_CRC0_WINDOWA_X_CONTROL = DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWA_X_CONTROL, .OTG_CRC0_WINDOWA_Y_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, .OTG_CRC0_WINDOWB_X_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWB_X_CONTROL, .OTG_CRC0_WINDOWB_Y_CONTROL
= DMU_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX
+ mmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, .GSL_SOURCE_SELECT = 0x000034C0
+ 0x1e2b, .OTG_GLOBAL_CONTROL2 = DMU_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_TRIGA_MANUAL_TRIG = DMU_BASE__INST0_SEGmmOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX
+ mmOTGid_OTG_TRIGA_MANUAL_TRIG, .OTG_GLOBAL_CONTROL1 = DMU_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DMU_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX
+ mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_GSL_WINDOW_X = DMU_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_X_BASE_IDX
+ mmOTGid_OTG_GSL_WINDOW_X, .OTG_GSL_WINDOW_Y = DMU_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_Y_BASE_IDX
+ mmOTGid_OTG_GSL_WINDOW_Y, .OTG_VUPDATE_KEEPOUT = DMU_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX
+ mmOTGid_OTG_VUPDATE_KEEPOUT, .OTG_DSC_START_POSITION = DMU_BASE__INST0_SEGmmOTGid_OTG_DSC_START_POSITION_BASE_IDX
+ mmOTGid_OTG_DSC_START_POSITION, .OPTC_DATA_FORMAT_CONTROL =
DMU_BASE__INST0_SEGmmODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX
+ mmODMid_OPTC_DATA_FORMAT_CONTROL, .OPTC_BYTES_PER_PIXEL = DMU_BASE__INST0_SEGmmODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX
+ mmODMid_OPTC_BYTES_PER_PIXEL, .OPTC_WIDTH_CONTROL = DMU_BASE__INST0_SEGmmODMid_OPTC_WIDTH_CONTROL_BASE_IDX
+ mmODMid_OPTC_WIDTH_CONTROL, .DWB_SOURCE_SELECT = 0x000034C0
+ 0x1e2a}
503
504static const struct dcn_optc_registers tg_regs[] = {
505 tg_regs_dcn201(0)[0] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1b87, .OTG_VUPDATE_PARAM
= 0x000034C0 + 0x1b88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1b89
, .OTG_BLANK_CONTROL = 0x000034C0 + 0x1b42, .OTG_MASTER_UPDATE_LOCK
= 0x000034C0 + 0x1b8b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1b90
, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1b5b, .OTG_H_TOTAL
= 0x000034C0 + 0x1b2a, .OTG_H_BLANK_START_END = 0x000034C0 +
0x1b2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1b2c, .OTG_H_SYNC_A_CNTL
= 0x000034C0 + 0x1b2d, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1b2e
, .OTG_V_TOTAL = 0x000034C0 + 0x1b2f, .OTG_V_BLANK_START_END =
0x000034C0 + 0x1b36, .OTG_V_SYNC_A = 0x000034C0 + 0x1b37, .OTG_V_SYNC_A_CNTL
= 0x000034C0 + 0x1b38, .OTG_INTERLACE_CONTROL = 0x000034C0 +
0x1b44, .OTG_CONTROL = 0x000034C0 + 0x1b41, .OTG_STEREO_CONTROL
= 0x000034C0 + 0x1b54, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0
+ 0x1b83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1b53, .OTG_V_TOTAL_MAX
= 0x000034C0 + 0x1b31, .OTG_V_TOTAL_MID = 0x000034C0 + 0x1b32
, .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1b30, .OTG_V_TOTAL_CONTROL
= 0x000034C0 + 0x1b33, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1b39
, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1b3d, .OTG_STATIC_SCREEN_CONTROL
= 0x000034C0 + 0x1b82, .OTG_STATUS_FRAME_COUNT = 0x000034C0 +
0x1b4c, .OTG_STATUS = 0x000034C0 + 0x1b49, .OTG_STATUS_POSITION
= 0x000034C0 + 0x1b4a, .OTG_NOM_VERT_POSITION = 0x000034C0 +
0x1b4b, .OTG_BLACK_COLOR = 0x000034C0 + 0x1b60, .OTG_CLOCK_CONTROL
= 0x000034C0 + 0x1b86, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0
+ 0x1b63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1b62
, .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1b65, .OTG_VERTICAL_INTERRUPT1_POSITION
= 0x000034C0 + 0x1b64, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0
+ 0x1b67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1b66
, .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1acf, .OPTC_DATA_SOURCE_SELECT
= 0x000034C0 + 0x1acb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0
+ 0x1aca, .CONTROL = 0x000034C0 + 0x0528, .OTG_VERT_SYNC_CONTROL
= 0x000034C0 + 0x1b52, .OTG_MASTER_UPDATE_MODE = 0x000034C0 +
0x1b85, .OTG_GSL_CONTROL = 0x000034C0 + 0x1b8c, .OTG_CRC_CNTL
= 0x000034C0 + 0x1b68, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1b6e
, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1b6f, .OTG_CRC0_WINDOWA_X_CONTROL
= 0x000034C0 + 0x1b6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0
+ 0x1b6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1b6c,
.OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1b6d, .GSL_SOURCE_SELECT
= 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1b92
, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1b3a, .OTG_GLOBAL_CONTROL1
= 0x000034C0 + 0x1b91, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1b92
, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1b8d, .OTG_GSL_WINDOW_Y =
0x000034C0 + 0x1b8e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1b8f
, .OTG_DSC_START_POSITION = 0x000034C0 + 0x1b99, .OPTC_DATA_FORMAT_CONTROL
= 0x000034C0 + 0x1acc, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1acd
, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1ace, .DWB_SOURCE_SELECT
= 0x000034C0 + 0x1e2a},
506 tg_regs_dcn201(1)[1] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1c07, .OTG_VUPDATE_PARAM
= 0x000034C0 + 0x1c08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1c09
, .OTG_BLANK_CONTROL = 0x000034C0 + 0x1bc2, .OTG_MASTER_UPDATE_LOCK
= 0x000034C0 + 0x1c0b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1c10
, .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1bdb, .OTG_H_TOTAL
= 0x000034C0 + 0x1baa, .OTG_H_BLANK_START_END = 0x000034C0 +
0x1bab, .OTG_H_SYNC_A = 0x000034C0 + 0x1bac, .OTG_H_SYNC_A_CNTL
= 0x000034C0 + 0x1bad, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1bae
, .OTG_V_TOTAL = 0x000034C0 + 0x1baf, .OTG_V_BLANK_START_END =
0x000034C0 + 0x1bb6, .OTG_V_SYNC_A = 0x000034C0 + 0x1bb7, .OTG_V_SYNC_A_CNTL
= 0x000034C0 + 0x1bb8, .OTG_INTERLACE_CONTROL = 0x000034C0 +
0x1bc4, .OTG_CONTROL = 0x000034C0 + 0x1bc1, .OTG_STEREO_CONTROL
= 0x000034C0 + 0x1bd4, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0
+ 0x1c03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1bd3, .OTG_V_TOTAL_MAX
= 0x000034C0 + 0x1bb1, .OTG_V_TOTAL_MID = 0x000034C0 + 0x1bb2
, .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1bb0, .OTG_V_TOTAL_CONTROL
= 0x000034C0 + 0x1bb3, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1bb9
, .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1bbd, .OTG_STATIC_SCREEN_CONTROL
= 0x000034C0 + 0x1c02, .OTG_STATUS_FRAME_COUNT = 0x000034C0 +
0x1bcc, .OTG_STATUS = 0x000034C0 + 0x1bc9, .OTG_STATUS_POSITION
= 0x000034C0 + 0x1bca, .OTG_NOM_VERT_POSITION = 0x000034C0 +
0x1bcb, .OTG_BLACK_COLOR = 0x000034C0 + 0x1be0, .OTG_CLOCK_CONTROL
= 0x000034C0 + 0x1c06, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0
+ 0x1be3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1be2
, .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1be5, .OTG_VERTICAL_INTERRUPT1_POSITION
= 0x000034C0 + 0x1be4, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0
+ 0x1be7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1be6
, .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1adf, .OPTC_DATA_SOURCE_SELECT
= 0x000034C0 + 0x1adb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0
+ 0x1ada, .CONTROL = 0x000034C0 + 0x0529, .OTG_VERT_SYNC_CONTROL
= 0x000034C0 + 0x1bd2, .OTG_MASTER_UPDATE_MODE = 0x000034C0 +
0x1c05, .OTG_GSL_CONTROL = 0x000034C0 + 0x1c0c, .OTG_CRC_CNTL
= 0x000034C0 + 0x1be8, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1bee
, .OTG_CRC0_DATA_B = 0x000034C0 + 0x1bef, .OTG_CRC0_WINDOWA_X_CONTROL
= 0x000034C0 + 0x1bea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0
+ 0x1beb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1bec,
.OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1bed, .GSL_SOURCE_SELECT
= 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c12
, .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1bba, .OTG_GLOBAL_CONTROL1
= 0x000034C0 + 0x1c11, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c12
, .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1c0d, .OTG_GSL_WINDOW_Y =
0x000034C0 + 0x1c0e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1c0f
, .OTG_DSC_START_POSITION = 0x000034C0 + 0x1c19, .OPTC_DATA_FORMAT_CONTROL
= 0x000034C0 + 0x1adc, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1add
, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1ade, .DWB_SOURCE_SELECT
= 0x000034C0 + 0x1e2a}
507};
508
509static const struct dcn_optc_shift tg_shift = {
510 TG_COMMON_MASK_SH_LIST_DCN201(__SHIFT).VSTARTUP_START = 0x0, .VUPDATE_OFFSET = 0x0, .VUPDATE_WIDTH =
0x10, .VREADY_OFFSET = 0x0, .OTG_BLANK_DATA_EN = 0x8, .OTG_BLANK_DE_MODE
= 0x10, .OTG_CURRENT_BLANK_STATE = 0x0, .OTG_MASTER_UPDATE_LOCK
= 0x0, .UPDATE_LOCK_STATUS = 0x8, .OTG_MASTER_UPDATE_LOCK_SEL
= 0x19, .OTG_UPDATE_PENDING = 0x0, .OTG_BLANK_DATA_DOUBLE_BUFFER_EN
= 0x10, .OTG_RANGE_TIMING_DBUF_UPDATE_MODE = 0x18, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN
= 0x1f, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0
, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x10, .OTG_H_TOTAL
= 0x0, .OTG_H_BLANK_START = 0x0, .OTG_H_BLANK_END = 0x10, .OTG_H_SYNC_A_START
= 0x0, .OTG_H_SYNC_A_END = 0x10, .OTG_H_SYNC_A_POL = 0x0, .OTG_H_TIMING_DIV_BY2
= 0x0, .OTG_V_TOTAL = 0x0, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END
= 0x10, .OTG_V_SYNC_A_START = 0x0, .OTG_V_SYNC_A_END = 0x10,
.OTG_V_SYNC_A_POL = 0x0, .OTG_INTERLACE_ENABLE = 0x0, .OTG_MASTER_EN
= 0x0, .OTG_START_POINT_CNTL = 0xc, .OTG_DISABLE_POINT_CNTL =
0x8, .OTG_FIELD_NUMBER_CNTL = 0xd, .OTG_CURRENT_MASTER_EN_STATE
= 0x10, .OTG_STEREO_EN = 0x18, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM
= 0x0, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0xf, .OTG_STEREO_EYE_FLAG_POLARITY
= 0x11, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x12, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP
= 0x12, .OTG_STEREO_CURRENT_EYE = 0x0, .OTG_3D_STRUCTURE_EN =
0x0, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x8, .OTG_3D_STRUCTURE_STEREO_SEL_OVR
= 0xc, .OTG_V_TOTAL_MAX = 0x0, .OTG_V_TOTAL_MID = 0x0, .OTG_V_TOTAL_MIN
= 0x0, .OTG_V_TOTAL_MIN_SEL = 0x0, .OTG_V_TOTAL_MAX_SEL = 0x1
, .OTG_FORCE_LOCK_ON_EVENT = 0x4, .OTG_SET_V_TOTAL_MIN_MASK_EN
= 0x7, .OTG_SET_V_TOTAL_MIN_MASK = 0x10, .OTG_VTOTAL_MID_REPLACING_MAX_EN
= 0x2, .OTG_VTOTAL_MID_FRAME_NUM = 0x8, .OTG_FORCE_COUNT_NOW_CLEAR
= 0x18, .OTG_FORCE_COUNT_NOW_MODE = 0x0, .OTG_FORCE_COUNT_NOW_OCCURRED
= 0x10, .OTG_TRIGA_SOURCE_SELECT = 0x0, .OTG_TRIGA_SOURCE_PIPE_SELECT
= 0x5, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x10, .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL
= 0x12, .OTG_TRIGA_POLARITY_SELECT = 0x8, .OTG_TRIGA_FREQUENCY_SELECT
= 0x14, .OTG_TRIGA_DELAY = 0x18, .OTG_TRIGA_CLEAR = 0x1f, .OTG_TRIGA_MANUAL_TRIG
= 0x0, .OTG_STATIC_SCREEN_EVENT_MASK = 0x0, .OTG_STATIC_SCREEN_FRAME_COUNT
= 0x10, .OTG_FRAME_COUNT = 0x0, .OTG_V_BLANK = 0x0, .OTG_V_ACTIVE_DISP
= 0x1, .OTG_HORZ_COUNT = 0x10, .OTG_VERT_COUNT = 0x0, .OTG_VERT_COUNT_NOM
= 0x0, .OTG_BLACK_COLOR_B_CB = 0x0, .OTG_BLACK_COLOR_G_Y = 0xa
, .OTG_BLACK_COLOR_R_CR = 0x14, .OTG_BUSY = 0x10, .OTG_CLOCK_EN
= 0x0, .OTG_CLOCK_ON = 0x8, .OTG_CLOCK_GATE_DIS = 0x1, .OTG_VERTICAL_INTERRUPT0_INT_ENABLE
= 0x8, .OTG_VERTICAL_INTERRUPT0_LINE_START = 0x0, .OTG_VERTICAL_INTERRUPT0_LINE_END
= 0x10, .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT1_LINE_START
= 0x0, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT2_LINE_START
= 0x0, .OPTC_INPUT_CLK_EN = 0x1, .OPTC_INPUT_CLK_ON = 0x2, .
OPTC_INPUT_CLK_GATE_DIS = 0x0, .OPTC_UNDERFLOW_OCCURRED_STATUS
= 0xa, .OPTC_UNDERFLOW_CLEAR = 0xc, .VTG0_ENABLE = 0x1f, .VTG0_FP2
= 0x0, .VTG0_VCOUNT_INIT = 0x10, .OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED
= 0x0, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = 0x8, .OTG_AUTO_FORCE_VSYNC_MODE
= 0x10, .MASTER_UPDATE_INTERLACED_MODE = 0x0, .OTG_GSL0_EN =
0x0, .OTG_GSL1_EN = 0x1, .OTG_GSL2_EN = 0x2, .OTG_GSL_MASTER_EN
= 0x3, .OTG_GSL_FORCE_DELAY = 0x10, .OTG_GSL_CHECK_ALL_FIELDS
= 0x1c, .OTG_CRC_CONT_EN = 0x4, .OTG_CRC0_SELECT = 0x14, .OTG_CRC_EN
= 0x0, .CRC0_R_CR = 0x0, .CRC0_G_Y = 0x10, .CRC0_B_CB = 0x0,
.OTG_CRC0_WINDOWA_X_START = 0x0, .OTG_CRC0_WINDOWA_X_END = 0x10
, .OTG_CRC0_WINDOWA_Y_START = 0x0, .OTG_CRC0_WINDOWA_Y_END = 0x10
, .OTG_CRC0_WINDOWB_X_START = 0x0, .OTG_CRC0_WINDOWB_X_END = 0x10
, .OTG_CRC0_WINDOWB_Y_START = 0x0, .OTG_CRC0_WINDOWB_Y_END = 0x10
, .GSL0_READY_SOURCE_SEL = 0x0, .GSL1_READY_SOURCE_SEL = 0x4,
.GSL2_READY_SOURCE_SEL = 0x8, .MANUAL_FLOW_CONTROL_SEL = 0x10
, .MASTER_UPDATE_LOCK_DB_X = 0x0, .MASTER_UPDATE_LOCK_DB_Y = 0x10
, .MASTER_UPDATE_LOCK_DB_EN = 0x1f, .GLOBAL_UPDATE_LOCK_EN = 0xa
, .OTG_RANGE_TIMING_DBUF_UPDATE_MODE = 0x18, .OTG_GSL_WINDOW_START_X
= 0x0, .OTG_GSL_WINDOW_END_X = 0x10, .OTG_GSL_WINDOW_START_Y
= 0x0, .OTG_GSL_WINDOW_END_Y = 0x10, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN
= 0x1f, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0
, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x10, .OTG_GSL_MASTER_MODE
= 0x4, .OTG_MASTER_UPDATE_LOCK_GSL_EN = 0x1f, .OTG_DSC_START_POSITION_X
= 0x0, .OTG_DSC_START_POSITION_LINE_NUM = 0x10, .OPTC_SEG0_SRC_SEL
= 0x8, .OPTC_DSC_MODE = 0x4, .OPTC_DSC_BYTES_PER_PIXEL = 0x0
, .OPTC_DSC_SLICE_WIDTH = 0x10, .OPTC_DWB0_SOURCE_SELECT = 0x0
, .OPTC_DWB1_SOURCE_SELECT = 0x3, .OPTC_DWB1_SOURCE_SELECT = 0x3
511};
512
513static const struct dcn_optc_mask tg_mask = {
514 TG_COMMON_MASK_SH_LIST_DCN201(_MASK).VSTARTUP_START = 0x000003FFL, .VUPDATE_OFFSET = 0x0000FFFFL,
.VUPDATE_WIDTH = 0x03FF0000L, .VREADY_OFFSET = 0x0000FFFFL, .
OTG_BLANK_DATA_EN = 0x00000100L, .OTG_BLANK_DE_MODE = 0x00010000L
, .OTG_CURRENT_BLANK_STATE = 0x00000001L, .OTG_MASTER_UPDATE_LOCK
= 0x00000001L, .UPDATE_LOCK_STATUS = 0x00000100L, .OTG_MASTER_UPDATE_LOCK_SEL
= 0x0E000000L, .OTG_UPDATE_PENDING = 0x00000001L, .OTG_BLANK_DATA_DOUBLE_BUFFER_EN
= 0x00010000L, .OTG_RANGE_TIMING_DBUF_UPDATE_MODE = 0x03000000L
, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x80000000L, .
MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0000FFFFL
, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x03FF0000L
, .OTG_H_TOTAL = 0x00007FFFL, .OTG_H_BLANK_START = 0x00007FFFL
, .OTG_H_BLANK_END = 0x7FFF0000L, .OTG_H_SYNC_A_START = 0x00007FFFL
, .OTG_H_SYNC_A_END = 0x7FFF0000L, .OTG_H_SYNC_A_POL = 0x00000001L
, .OTG_H_TIMING_DIV_BY2 = 0x00000001L, .OTG_V_TOTAL = 0x00007FFFL
, .OTG_V_BLANK_START = 0x00007FFFL, .OTG_V_BLANK_END = 0x7FFF0000L
, .OTG_V_SYNC_A_START = 0x00007FFFL, .OTG_V_SYNC_A_END = 0x7FFF0000L
, .OTG_V_SYNC_A_POL = 0x00000001L, .OTG_INTERLACE_ENABLE = 0x00000001L
, .OTG_MASTER_EN = 0x00000001L, .OTG_START_POINT_CNTL = 0x00001000L
, .OTG_DISABLE_POINT_CNTL = 0x00000300L, .OTG_FIELD_NUMBER_CNTL
= 0x00002000L, .OTG_CURRENT_MASTER_EN_STATE = 0x00010000L, .
OTG_STEREO_EN = 0x01000000L, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM
= 0x00007FFFL, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0x00008000L
, .OTG_STEREO_EYE_FLAG_POLARITY = 0x00020000L, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP
= 0x00040000L, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x00040000L
, .OTG_STEREO_CURRENT_EYE = 0x00000001L, .OTG_3D_STRUCTURE_EN
= 0x00000001L, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x00000300L
, .OTG_3D_STRUCTURE_STEREO_SEL_OVR = 0x00001000L, .OTG_V_TOTAL_MAX
= 0x00007FFFL, .OTG_V_TOTAL_MID = 0x00007FFFL, .OTG_V_TOTAL_MIN
= 0x00007FFFL, .OTG_V_TOTAL_MIN_SEL = 0x00000001L, .OTG_V_TOTAL_MAX_SEL
= 0x00000002L, .OTG_FORCE_LOCK_ON_EVENT = 0x00000010L, .OTG_SET_V_TOTAL_MIN_MASK_EN
= 0x00000080L, .OTG_SET_V_TOTAL_MIN_MASK = 0xFFFF0000L, .OTG_VTOTAL_MID_REPLACING_MAX_EN
= 0x00000004L, .OTG_VTOTAL_MID_FRAME_NUM = 0x0000FF00L, .OTG_FORCE_COUNT_NOW_CLEAR
= 0x01000000L, .OTG_FORCE_COUNT_NOW_MODE = 0x00000003L, .OTG_FORCE_COUNT_NOW_OCCURRED
= 0x00010000L, .OTG_TRIGA_SOURCE_SELECT = 0x0000001FL, .OTG_TRIGA_SOURCE_PIPE_SELECT
= 0x000000E0L, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x00030000L
, .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x000C0000L, .OTG_TRIGA_POLARITY_SELECT
= 0x00000700L, .OTG_TRIGA_FREQUENCY_SELECT = 0x00300000L, .OTG_TRIGA_DELAY
= 0x1F000000L, .OTG_TRIGA_CLEAR = 0x80000000L, .OTG_TRIGA_MANUAL_TRIG
= 0x00000001L, .OTG_STATIC_SCREEN_EVENT_MASK = 0x0000FFFFL, .
OTG_STATIC_SCREEN_FRAME_COUNT = 0x00FF0000L, .OTG_FRAME_COUNT
= 0x00FFFFFFL, .OTG_V_BLANK = 0x00000001L, .OTG_V_ACTIVE_DISP
= 0x00000002L, .OTG_HORZ_COUNT = 0x7FFF0000L, .OTG_VERT_COUNT
= 0x00007FFFL, .OTG_VERT_COUNT_NOM = 0x00007FFFL, .OTG_BLACK_COLOR_B_CB
= 0x000003FFL, .OTG_BLACK_COLOR_G_Y = 0x000FFC00L, .OTG_BLACK_COLOR_R_CR
= 0x3FF00000L, .OTG_BUSY = 0x00010000L, .OTG_CLOCK_EN = 0x00000001L
, .OTG_CLOCK_ON = 0x00000100L, .OTG_CLOCK_GATE_DIS = 0x00000002L
, .OTG_VERTICAL_INTERRUPT0_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT0_LINE_START
= 0x00007FFFL, .OTG_VERTICAL_INTERRUPT0_LINE_END = 0x7FFF0000L
, .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT1_LINE_START
= 0x00007FFFL, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x00000100L
, .OTG_VERTICAL_INTERRUPT2_LINE_START = 0x00007FFFL, .OPTC_INPUT_CLK_EN
= 0x00000002L, .OPTC_INPUT_CLK_ON = 0x00000004L, .OPTC_INPUT_CLK_GATE_DIS
= 0x00000001L, .OPTC_UNDERFLOW_OCCURRED_STATUS = 0x00000400L
, .OPTC_UNDERFLOW_CLEAR = 0x00001000L, .VTG0_ENABLE = 0x80000000L
, .VTG0_FP2 = 0x00007FFFL, .VTG0_VCOUNT_INIT = 0x7FFF0000L, .
OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED = 0x00000001L, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR
= 0x00000100L, .OTG_AUTO_FORCE_VSYNC_MODE = 0x00030000L, .MASTER_UPDATE_INTERLACED_MODE
= 0x00000003L, .OTG_GSL0_EN = 0x00000001L, .OTG_GSL1_EN = 0x00000002L
, .OTG_GSL2_EN = 0x00000004L, .OTG_GSL_MASTER_EN = 0x00000008L
, .OTG_GSL_FORCE_DELAY = 0x001F0000L, .OTG_GSL_CHECK_ALL_FIELDS
= 0x10000000L, .OTG_CRC_CONT_EN = 0x00000010L, .OTG_CRC0_SELECT
= 0x00700000L, .OTG_CRC_EN = 0x00000001L, .CRC0_R_CR = 0x0000FFFFL
, .CRC0_G_Y = 0xFFFF0000L, .CRC0_B_CB = 0x0000FFFFL, .OTG_CRC0_WINDOWA_X_START
= 0x00007FFFL, .OTG_CRC0_WINDOWA_X_END = 0x7FFF0000L, .OTG_CRC0_WINDOWA_Y_START
= 0x00007FFFL, .OTG_CRC0_WINDOWA_Y_END = 0x7FFF0000L, .OTG_CRC0_WINDOWB_X_START
= 0x00007FFFL, .OTG_CRC0_WINDOWB_X_END = 0x7FFF0000L, .OTG_CRC0_WINDOWB_Y_START
= 0x00007FFFL, .OTG_CRC0_WINDOWB_Y_END = 0x7FFF0000L, .GSL0_READY_SOURCE_SEL
= 0x00000007L, .GSL1_READY_SOURCE_SEL = 0x00000070L, .GSL2_READY_SOURCE_SEL
= 0x00000700L, .MANUAL_FLOW_CONTROL_SEL = 0x00070000L, .MASTER_UPDATE_LOCK_DB_X
= 0x00007FFFL, .MASTER_UPDATE_LOCK_DB_Y = 0x7FFF0000L, .MASTER_UPDATE_LOCK_DB_EN
= 0x80000000L, .GLOBAL_UPDATE_LOCK_EN = 0x00000400L, .OTG_RANGE_TIMING_DBUF_UPDATE_MODE
= 0x03000000L, .OTG_GSL_WINDOW_START_X = 0x00007FFFL, .OTG_GSL_WINDOW_END_X
= 0x7FFF0000L, .OTG_GSL_WINDOW_START_Y = 0x00007FFFL, .OTG_GSL_WINDOW_END_Y
= 0x7FFF0000L, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x80000000L
, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0000FFFFL
, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x03FF0000L
, .OTG_GSL_MASTER_MODE = 0x00000030L, .OTG_MASTER_UPDATE_LOCK_GSL_EN
= 0x80000000L, .OTG_DSC_START_POSITION_X = 0x00007FFFL, .OTG_DSC_START_POSITION_LINE_NUM
= 0x03FF0000L, .OPTC_SEG0_SRC_SEL = 0x00000F00L, .OPTC_DSC_MODE
= 0x00000030L, .OPTC_DSC_BYTES_PER_PIXEL = 0x7FFFFFFFL, .OPTC_DSC_SLICE_WIDTH
= 0x1FFF0000L, .OPTC_DWB0_SOURCE_SELECT = 0x00000007L, .OPTC_DWB1_SOURCE_SELECT
= 0x00000038L, .OPTC_DWB1_SOURCE_SELECT = 0x00000038L
515};
516
517#define hubp_regsDCN201(id)[id] = { .DCHUBP_CNTL = DMU_BASE__INST0_SEGmmHUBPid_DCHUBP_CNTL_BASE_IDX
+ mmHUBPid_DCHUBP_CNTL, .HUBPREQ_DEBUG_DB = DMU_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX
+ mmHUBPid_HUBPREQ_DEBUG_DB, .HUBPREQ_DEBUG = DMU_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_BASE_IDX
+ mmHUBPid_HUBPREQ_DEBUG, .DCSURF_ADDR_CONFIG = DMU_BASE__INST0_SEGmmHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_ADDR_CONFIG, .DCSURF_TILING_CONFIG = DMU_BASE__INST0_SEGmmHUBPid_DCSURF_TILING_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_TILING_CONFIG, .DCSURF_SURFACE_PITCH = DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_PITCH, .DCSURF_SURFACE_PITCH_C =
DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_PITCH_C, .DCSURF_SURFACE_CONFIG
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_SURFACE_CONFIG, .DCSURF_FLIP_CONTROL = DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX
+ mmHUBPREQid_DCSURF_FLIP_CONTROL, .DCSURF_PRI_VIEWPORT_DIMENSION
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION, .DCSURF_PRI_VIEWPORT_START
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_START, .DCSURF_SEC_VIEWPORT_DIMENSION
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION, .DCSURF_SEC_VIEWPORT_START
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_START, .DCSURF_PRI_VIEWPORT_DIMENSION_C
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C, .DCSURF_PRI_VIEWPORT_START_C
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_START_C, .DCSURF_SEC_VIEWPORT_DIMENSION_C
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C, .DCSURF_SEC_VIEWPORT_START_C
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_START_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_META_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_META_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, .
DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, .DCSURF_SURFACE_INUSE
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE, .DCSURF_SURFACE_INUSE_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, .DCSURF_SURFACE_INUSE_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_C, .DCSURF_SURFACE_INUSE_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, .DCSURF_SURFACE_EARLIEST_INUSE
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, .DCSURF_SURFACE_EARLIEST_INUSE_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, .DCSURF_SURFACE_CONTROL
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_CONTROL, .DCSURF_SURFACE_FLIP_INTERRUPT
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT, .HUBPRET_CONTROL
= DMU_BASE__INST0_SEGmmHUBPRETid_HUBPRET_CONTROL_BASE_IDX + mmHUBPRETid_HUBPRET_CONTROL
, .HUBPRET_READ_LINE_STATUS = DMU_BASE__INST0_SEGmmHUBPRETid_HUBPRET_READ_LINE_STATUS_BASE_IDX
+ mmHUBPRETid_HUBPRET_READ_LINE_STATUS, .DCN_EXPANSION_MODE =
DMU_BASE__INST0_SEGmmHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX +
mmHUBPREQid_DCN_EXPANSION_MODE, .DCHUBP_REQ_SIZE_CONFIG = DMU_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX
+ mmHUBPid_DCHUBP_REQ_SIZE_CONFIG, .DCHUBP_REQ_SIZE_CONFIG_C
= DMU_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX
+ mmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, .BLANK_OFFSET_0 = DMU_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_0_BASE_IDX
+ mmHUBPREQid_BLANK_OFFSET_0, .BLANK_OFFSET_1 = DMU_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_1_BASE_IDX
+ mmHUBPREQid_BLANK_OFFSET_1, .DST_DIMENSIONS = DMU_BASE__INST0_SEGmmHUBPREQid_DST_DIMENSIONS_BASE_IDX
+ mmHUBPREQid_DST_DIMENSIONS, .DST_AFTER_SCALER = DMU_BASE__INST0_SEGmmHUBPREQid_DST_AFTER_SCALER_BASE_IDX
+ mmHUBPREQid_DST_AFTER_SCALER, .VBLANK_PARAMETERS_0 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_0, .REF_FREQ_TO_PIX_FREQ = DMU_BASE__INST0_SEGmmHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX
+ mmHUBPREQid_REF_FREQ_TO_PIX_FREQ, .VBLANK_PARAMETERS_1 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_1, .VBLANK_PARAMETERS_3 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_3, .NOM_PARAMETERS_4 = DMU_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_4, .NOM_PARAMETERS_5 = DMU_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_5_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_5, .PER_LINE_DELIVERY_PRE = DMU_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX
+ mmHUBPREQid_PER_LINE_DELIVERY_PRE, .PER_LINE_DELIVERY = DMU_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_BASE_IDX
+ mmHUBPREQid_PER_LINE_DELIVERY, .VBLANK_PARAMETERS_2 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_2, .VBLANK_PARAMETERS_4 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_4, .NOM_PARAMETERS_6 = DMU_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_6_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_6, .NOM_PARAMETERS_7 = DMU_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_7_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_7, .DCN_TTU_QOS_WM = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX
+ mmHUBPREQid_DCN_TTU_QOS_WM, .DCN_GLOBAL_TTU_CNTL = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX
+ mmHUBPREQid_DCN_GLOBAL_TTU_CNTL, .DCN_SURF0_TTU_CNTL0 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_SURF0_TTU_CNTL0, .DCN_SURF0_TTU_CNTL1 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_SURF0_TTU_CNTL1, .DCN_SURF1_TTU_CNTL0 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_SURF1_TTU_CNTL0, .DCN_SURF1_TTU_CNTL1 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_SURF1_TTU_CNTL1, .DCN_CUR0_TTU_CNTL0 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_CUR0_TTU_CNTL0, .DCN_CUR0_TTU_CNTL1 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_CUR0_TTU_CNTL1, .HUBP_CLK_CNTL = DMU_BASE__INST0_SEGmmHUBPid_HUBP_CLK_CNTL_BASE_IDX
+ mmHUBPid_HUBP_CLK_CNTL, .PREFETCH_SETTINGS = DMU_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_BASE_IDX
+ mmHUBPREQid_PREFETCH_SETTINGS, .PREFETCH_SETTINGS_C = DMU_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX
+ mmHUBPREQid_PREFETCH_SETTINGS_C, .DCSURF_FLIP_CONTROL2 = DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX
+ mmHUBPREQid_DCSURF_FLIP_CONTROL2, .CURSOR_SETTINGS = DMU_BASE__INST0_SEGmmHUBPREQid_CURSOR_SETTINGS_BASE_IDX
+ mmHUBPREQid_CURSOR_SETTINGS, .CURSOR_SURFACE_ADDRESS_HIGH =
DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX
+ mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX
+ mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX
+ mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX
+ mmCURSOR0_id_CURSOR_DST_OFFSET, .DMDATA_ADDRESS_HIGH = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_DMDATA_ADDRESS_HIGH, .DMDATA_ADDRESS_LOW = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX
+ mmCURSOR0_id_DMDATA_ADDRESS_LOW, .DMDATA_CNTL = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_CNTL, .DMDATA_SW_CNTL = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_SW_CNTL, .DMDATA_QOS_CNTL = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_QOS_CNTL, .DMDATA_SW_DATA = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_DATA_BASE_IDX
+ mmCURSOR0_id_DMDATA_SW_DATA, .DMDATA_STATUS = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_STATUS_BASE_IDX
+ mmCURSOR0_id_DMDATA_STATUS, .FLIP_PARAMETERS_0 = DMU_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_0, .FLIP_PARAMETERS_2 = DMU_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_2}\
518[id] = {\
519 HUBP_REG_LIST_DCN201(id).DCHUBP_CNTL = DMU_BASE__INST0_SEGmmHUBPid_DCHUBP_CNTL_BASE_IDX
+ mmHUBPid_DCHUBP_CNTL, .HUBPREQ_DEBUG_DB = DMU_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX
+ mmHUBPid_HUBPREQ_DEBUG_DB, .HUBPREQ_DEBUG = DMU_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_BASE_IDX
+ mmHUBPid_HUBPREQ_DEBUG, .DCSURF_ADDR_CONFIG = DMU_BASE__INST0_SEGmmHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_ADDR_CONFIG, .DCSURF_TILING_CONFIG = DMU_BASE__INST0_SEGmmHUBPid_DCSURF_TILING_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_TILING_CONFIG, .DCSURF_SURFACE_PITCH = DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_PITCH, .DCSURF_SURFACE_PITCH_C =
DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_PITCH_C, .DCSURF_SURFACE_CONFIG
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX
+ mmHUBPid_DCSURF_SURFACE_CONFIG, .DCSURF_FLIP_CONTROL = DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX
+ mmHUBPREQid_DCSURF_FLIP_CONTROL, .DCSURF_PRI_VIEWPORT_DIMENSION
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION, .DCSURF_PRI_VIEWPORT_START
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_START, .DCSURF_SEC_VIEWPORT_DIMENSION
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION, .DCSURF_SEC_VIEWPORT_START
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_START, .DCSURF_PRI_VIEWPORT_DIMENSION_C
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C, .DCSURF_PRI_VIEWPORT_START_C
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX
+ mmHUBPid_DCSURF_PRI_VIEWPORT_START_C, .DCSURF_SEC_VIEWPORT_DIMENSION_C
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C, .DCSURF_SEC_VIEWPORT_START_C
= DMU_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX
+ mmHUBPid_DCSURF_SEC_VIEWPORT_START_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_META_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_META_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, .
DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, .DCSURF_SURFACE_INUSE
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE, .DCSURF_SURFACE_INUSE_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, .DCSURF_SURFACE_INUSE_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_C, .DCSURF_SURFACE_INUSE_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, .DCSURF_SURFACE_EARLIEST_INUSE
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, .DCSURF_SURFACE_EARLIEST_INUSE_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, .DCSURF_SURFACE_CONTROL
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_CONTROL, .DCSURF_SURFACE_FLIP_INTERRUPT
= DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX
+ mmHUBPREQid_DCSURF_SURFACE_FLIP_INTERRUPT, .HUBPRET_CONTROL
= DMU_BASE__INST0_SEGmmHUBPRETid_HUBPRET_CONTROL_BASE_IDX + mmHUBPRETid_HUBPRET_CONTROL
, .HUBPRET_READ_LINE_STATUS = DMU_BASE__INST0_SEGmmHUBPRETid_HUBPRET_READ_LINE_STATUS_BASE_IDX
+ mmHUBPRETid_HUBPRET_READ_LINE_STATUS, .DCN_EXPANSION_MODE =
DMU_BASE__INST0_SEGmmHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX +
mmHUBPREQid_DCN_EXPANSION_MODE, .DCHUBP_REQ_SIZE_CONFIG = DMU_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX
+ mmHUBPid_DCHUBP_REQ_SIZE_CONFIG, .DCHUBP_REQ_SIZE_CONFIG_C
= DMU_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX
+ mmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, .BLANK_OFFSET_0 = DMU_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_0_BASE_IDX
+ mmHUBPREQid_BLANK_OFFSET_0, .BLANK_OFFSET_1 = DMU_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_1_BASE_IDX
+ mmHUBPREQid_BLANK_OFFSET_1, .DST_DIMENSIONS = DMU_BASE__INST0_SEGmmHUBPREQid_DST_DIMENSIONS_BASE_IDX
+ mmHUBPREQid_DST_DIMENSIONS, .DST_AFTER_SCALER = DMU_BASE__INST0_SEGmmHUBPREQid_DST_AFTER_SCALER_BASE_IDX
+ mmHUBPREQid_DST_AFTER_SCALER, .VBLANK_PARAMETERS_0 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_0, .REF_FREQ_TO_PIX_FREQ = DMU_BASE__INST0_SEGmmHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX
+ mmHUBPREQid_REF_FREQ_TO_PIX_FREQ, .VBLANK_PARAMETERS_1 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_1, .VBLANK_PARAMETERS_3 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_3, .NOM_PARAMETERS_4 = DMU_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_4, .NOM_PARAMETERS_5 = DMU_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_5_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_5, .PER_LINE_DELIVERY_PRE = DMU_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX
+ mmHUBPREQid_PER_LINE_DELIVERY_PRE, .PER_LINE_DELIVERY = DMU_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_BASE_IDX
+ mmHUBPREQid_PER_LINE_DELIVERY, .VBLANK_PARAMETERS_2 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_2, .VBLANK_PARAMETERS_4 = DMU_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX
+ mmHUBPREQid_VBLANK_PARAMETERS_4, .NOM_PARAMETERS_6 = DMU_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_6_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_6, .NOM_PARAMETERS_7 = DMU_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_7_BASE_IDX
+ mmHUBPREQid_NOM_PARAMETERS_7, .DCN_TTU_QOS_WM = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX
+ mmHUBPREQid_DCN_TTU_QOS_WM, .DCN_GLOBAL_TTU_CNTL = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX
+ mmHUBPREQid_DCN_GLOBAL_TTU_CNTL, .DCN_SURF0_TTU_CNTL0 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_SURF0_TTU_CNTL0, .DCN_SURF0_TTU_CNTL1 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_SURF0_TTU_CNTL1, .DCN_SURF1_TTU_CNTL0 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_SURF1_TTU_CNTL0, .DCN_SURF1_TTU_CNTL1 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_SURF1_TTU_CNTL1, .DCN_CUR0_TTU_CNTL0 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX
+ mmHUBPREQid_DCN_CUR0_TTU_CNTL0, .DCN_CUR0_TTU_CNTL1 = DMU_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX
+ mmHUBPREQid_DCN_CUR0_TTU_CNTL1, .HUBP_CLK_CNTL = DMU_BASE__INST0_SEGmmHUBPid_HUBP_CLK_CNTL_BASE_IDX
+ mmHUBPid_HUBP_CLK_CNTL, .PREFETCH_SETTINGS = DMU_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_BASE_IDX
+ mmHUBPREQid_PREFETCH_SETTINGS, .PREFETCH_SETTINGS_C = DMU_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX
+ mmHUBPREQid_PREFETCH_SETTINGS_C, .DCSURF_FLIP_CONTROL2 = DMU_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX
+ mmHUBPREQid_DCSURF_FLIP_CONTROL2, .CURSOR_SETTINGS = DMU_BASE__INST0_SEGmmHUBPREQid_CURSOR_SETTINGS_BASE_IDX
+ mmHUBPREQid_CURSOR_SETTINGS, .CURSOR_SURFACE_ADDRESS_HIGH =
DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS
= DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX
+ mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX
+ mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX
+ mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX
+ mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX
+ mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DMU_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX
+ mmCURSOR0_id_CURSOR_DST_OFFSET, .DMDATA_ADDRESS_HIGH = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX
+ mmCURSOR0_id_DMDATA_ADDRESS_HIGH, .DMDATA_ADDRESS_LOW = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX
+ mmCURSOR0_id_DMDATA_ADDRESS_LOW, .DMDATA_CNTL = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_CNTL, .DMDATA_SW_CNTL = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_SW_CNTL, .DMDATA_QOS_CNTL = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX
+ mmCURSOR0_id_DMDATA_QOS_CNTL, .DMDATA_SW_DATA = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_DATA_BASE_IDX
+ mmCURSOR0_id_DMDATA_SW_DATA, .DMDATA_STATUS = DMU_BASE__INST0_SEGmmCURSOR0_id_DMDATA_STATUS_BASE_IDX
+ mmCURSOR0_id_DMDATA_STATUS, .FLIP_PARAMETERS_0 = DMU_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_0, .FLIP_PARAMETERS_2 = DMU_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX
+ mmHUBPREQid_FLIP_PARAMETERS_2\
520}
521
522static const struct dcn201_hubp_registers hubp_regs[] = {
523 hubp_regsDCN201(0)[0] = { .DCHUBP_CNTL = 0x000034C0 + 0x05f3, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x05f6, .HUBPREQ_DEBUG = 0x000034C0 + 0x05f7,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x05e6, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x05e7, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x0607
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x0608, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x05e5, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x061b
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x05ea, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x05e9, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x05ee, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x05ed, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x05ec, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x05eb, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x05f0, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x05ef
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x060b,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x060a, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x060f, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x060e, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x0613, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x0612, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x0617, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x0616, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x060d, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x060c
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0611
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0610, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0615
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0614
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x0619, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x0618, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x0621, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x0622, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x0623, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0624, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0625, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x0626, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x0627, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x0628, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x061a, .DCSURF_SURFACE_FLIP_INTERRUPT
= 0x000034C0 + 0x0620, .HUBPRET_CONTROL = 0x000034C0 + 0x066a
, .HUBPRET_READ_LINE_STATUS = 0x000034C0 + 0x0673, .DCN_EXPANSION_MODE
= 0x000034C0 + 0x062c, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 +
0x05f1, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x05f2, .BLANK_OFFSET_0
= 0x000034C0 + 0x0646, .BLANK_OFFSET_1 = 0x000034C0 + 0x0647
, .DST_DIMENSIONS = 0x000034C0 + 0x0648, .DST_AFTER_SCALER = 0x000034C0
+ 0x0649, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x064c, .REF_FREQ_TO_PIX_FREQ
= 0x000034C0 + 0x065f, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x064d
, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x064f, .NOM_PARAMETERS_4
= 0x000034C0 + 0x0658, .NOM_PARAMETERS_5 = 0x000034C0 + 0x0659
, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x065c, .PER_LINE_DELIVERY
= 0x000034C0 + 0x065d, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x064e
, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x0650, .NOM_PARAMETERS_6
= 0x000034C0 + 0x065a, .NOM_PARAMETERS_7 = 0x000034C0 + 0x065b
, .DCN_TTU_QOS_WM = 0x000034C0 + 0x062d, .DCN_GLOBAL_TTU_CNTL
= 0x000034C0 + 0x062e, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x062f
, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x0630, .DCN_SURF1_TTU_CNTL0
= 0x000034C0 + 0x0631, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x0632
, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x0633, .DCN_CUR0_TTU_CNTL1
= 0x000034C0 + 0x0634, .HUBP_CLK_CNTL = 0x000034C0 + 0x05f4,
.PREFETCH_SETTINGS = 0x000034C0 + 0x064a, .PREFETCH_SETTINGS_C
= 0x000034C0 + 0x064b, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x061c
, .CURSOR_SETTINGS = 0x000034C0 + 0x065e, .CURSOR_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x067a, .CURSOR_SURFACE_ADDRESS = 0x000034C0 +
0x0679, .CURSOR_SIZE = 0x000034C0 + 0x067b, .CURSOR_CONTROL =
0x000034C0 + 0x0678, .CURSOR_POSITION = 0x000034C0 + 0x067c,
.CURSOR_HOT_SPOT = 0x000034C0 + 0x067d, .CURSOR_DST_OFFSET =
0x000034C0 + 0x067f, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0682
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0683, .DMDATA_CNTL = 0x000034C0
+ 0x0684, .DMDATA_SW_CNTL = 0x000034C0 + 0x0687, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x0685, .DMDATA_SW_DATA = 0x000034C0 + 0x0688
, .DMDATA_STATUS = 0x000034C0 + 0x0686, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x0651, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x0653},
524 hubp_regsDCN201(1)[1] = { .DCHUBP_CNTL = 0x000034C0 + 0x06cf, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x06d2, .HUBPREQ_DEBUG = 0x000034C0 + 0x06d3,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x06c2, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x06c3, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x06e3
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x06e4, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x06c1, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x06f7
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x06c6, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x06c5, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x06ca, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x06c9, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x06c8, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x06c7, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x06cc, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x06cb
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06e7,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x06e6, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x06eb, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x06ea, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x06ef, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x06ee, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x06f3, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x06f2, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x06e9, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x06e8
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06ed
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x06ec, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06f1
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x06f0
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x06f5, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x06f4, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x06fd, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x06fe, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x06ff, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0700, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0701, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x0702, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x0703, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x0704, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x06f6, .DCSURF_SURFACE_FLIP_INTERRUPT
= 0x000034C0 + 0x06fc, .HUBPRET_CONTROL = 0x000034C0 + 0x0746
, .HUBPRET_READ_LINE_STATUS = 0x000034C0 + 0x074f, .DCN_EXPANSION_MODE
= 0x000034C0 + 0x0708, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 +
0x06cd, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x06ce, .BLANK_OFFSET_0
= 0x000034C0 + 0x0722, .BLANK_OFFSET_1 = 0x000034C0 + 0x0723
, .DST_DIMENSIONS = 0x000034C0 + 0x0724, .DST_AFTER_SCALER = 0x000034C0
+ 0x0725, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x0728, .REF_FREQ_TO_PIX_FREQ
= 0x000034C0 + 0x073b, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0729
, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x072b, .NOM_PARAMETERS_4
= 0x000034C0 + 0x0734, .NOM_PARAMETERS_5 = 0x000034C0 + 0x0735
, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x0738, .PER_LINE_DELIVERY
= 0x000034C0 + 0x0739, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x072a
, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x072c, .NOM_PARAMETERS_6
= 0x000034C0 + 0x0736, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0737
, .DCN_TTU_QOS_WM = 0x000034C0 + 0x0709, .DCN_GLOBAL_TTU_CNTL
= 0x000034C0 + 0x070a, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x070b
, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x070c, .DCN_SURF1_TTU_CNTL0
= 0x000034C0 + 0x070d, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x070e
, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x070f, .DCN_CUR0_TTU_CNTL1
= 0x000034C0 + 0x0710, .HUBP_CLK_CNTL = 0x000034C0 + 0x06d0,
.PREFETCH_SETTINGS = 0x000034C0 + 0x0726, .PREFETCH_SETTINGS_C
= 0x000034C0 + 0x0727, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x06f8
, .CURSOR_SETTINGS = 0x000034C0 + 0x073a, .CURSOR_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x0756, .CURSOR_SURFACE_ADDRESS = 0x000034C0 +
0x0755, .CURSOR_SIZE = 0x000034C0 + 0x0757, .CURSOR_CONTROL =
0x000034C0 + 0x0754, .CURSOR_POSITION = 0x000034C0 + 0x0758,
.CURSOR_HOT_SPOT = 0x000034C0 + 0x0759, .CURSOR_DST_OFFSET =
0x000034C0 + 0x075b, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x075e
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x075f, .DMDATA_CNTL = 0x000034C0
+ 0x0760, .DMDATA_SW_CNTL = 0x000034C0 + 0x0763, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x0761, .DMDATA_SW_DATA = 0x000034C0 + 0x0764
, .DMDATA_STATUS = 0x000034C0 + 0x0762, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x072d, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x072f},
525 hubp_regsDCN201(2)[2] = { .DCHUBP_CNTL = 0x000034C0 + 0x07ab, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x07ae, .HUBPREQ_DEBUG = 0x000034C0 + 0x07af,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x079e, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x079f, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x07bf
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x07c0, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x079d, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x07d3
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x07a2, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x07a1, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x07a6, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x07a5, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x07a4, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x07a3, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x07a8, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x07a7
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07c3,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x07c2, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x07c7, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x07c6, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x07cb, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x07ca, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x07cf, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x07ce, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x07c5, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x07c4
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07c9
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x07c8, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07cd
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x07cc
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x07d1, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x07d0, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x07d9, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x07da, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x07db, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x07dc, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x07dd, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x07de, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x07df, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x07e0, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x07d2, .DCSURF_SURFACE_FLIP_INTERRUPT
= 0x000034C0 + 0x07d8, .HUBPRET_CONTROL = 0x000034C0 + 0x0822
, .HUBPRET_READ_LINE_STATUS = 0x000034C0 + 0x082b, .DCN_EXPANSION_MODE
= 0x000034C0 + 0x07e4, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 +
0x07a9, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x07aa, .BLANK_OFFSET_0
= 0x000034C0 + 0x07fe, .BLANK_OFFSET_1 = 0x000034C0 + 0x07ff
, .DST_DIMENSIONS = 0x000034C0 + 0x0800, .DST_AFTER_SCALER = 0x000034C0
+ 0x0801, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x0804, .REF_FREQ_TO_PIX_FREQ
= 0x000034C0 + 0x0817, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0805
, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x0807, .NOM_PARAMETERS_4
= 0x000034C0 + 0x0810, .NOM_PARAMETERS_5 = 0x000034C0 + 0x0811
, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x0814, .PER_LINE_DELIVERY
= 0x000034C0 + 0x0815, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x0806
, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x0808, .NOM_PARAMETERS_6
= 0x000034C0 + 0x0812, .NOM_PARAMETERS_7 = 0x000034C0 + 0x0813
, .DCN_TTU_QOS_WM = 0x000034C0 + 0x07e5, .DCN_GLOBAL_TTU_CNTL
= 0x000034C0 + 0x07e6, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x07e7
, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x07e8, .DCN_SURF1_TTU_CNTL0
= 0x000034C0 + 0x07e9, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x07ea
, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x07eb, .DCN_CUR0_TTU_CNTL1
= 0x000034C0 + 0x07ec, .HUBP_CLK_CNTL = 0x000034C0 + 0x07ac,
.PREFETCH_SETTINGS = 0x000034C0 + 0x0802, .PREFETCH_SETTINGS_C
= 0x000034C0 + 0x0803, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x07d4
, .CURSOR_SETTINGS = 0x000034C0 + 0x0816, .CURSOR_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x0832, .CURSOR_SURFACE_ADDRESS = 0x000034C0 +
0x0831, .CURSOR_SIZE = 0x000034C0 + 0x0833, .CURSOR_CONTROL =
0x000034C0 + 0x0830, .CURSOR_POSITION = 0x000034C0 + 0x0834,
.CURSOR_HOT_SPOT = 0x000034C0 + 0x0835, .CURSOR_DST_OFFSET =
0x000034C0 + 0x0837, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x083a
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x083b, .DMDATA_CNTL = 0x000034C0
+ 0x083c, .DMDATA_SW_CNTL = 0x000034C0 + 0x083f, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x083d, .DMDATA_SW_DATA = 0x000034C0 + 0x0840
, .DMDATA_STATUS = 0x000034C0 + 0x083e, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x0809, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x080b},
526 hubp_regsDCN201(3)[3] = { .DCHUBP_CNTL = 0x000034C0 + 0x0887, .HUBPREQ_DEBUG_DB
= 0x000034C0 + 0x088a, .HUBPREQ_DEBUG = 0x000034C0 + 0x088b,
.DCSURF_ADDR_CONFIG = 0x000034C0 + 0x087a, .DCSURF_TILING_CONFIG
= 0x000034C0 + 0x087b, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x089b
, .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x089c, .DCSURF_SURFACE_CONFIG
= 0x000034C0 + 0x0879, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x08af
, .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x087e, .DCSURF_PRI_VIEWPORT_START
= 0x000034C0 + 0x087d, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0
+ 0x0882, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x0881, .
DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0880, .DCSURF_PRI_VIEWPORT_START_C
= 0x000034C0 + 0x087f, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0
+ 0x0884, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x0883
, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x089f,
.DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x089e, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x08a3, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0
+ 0x08a2, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x08a7, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 +
0x08a6, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0
+ 0x08ab, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0
+ 0x08aa, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0
+ 0x08a1, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a0
, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a5
, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a4, .
DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a9
, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a8
, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 +
0x08ad, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0
+ 0x08ac, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x08b5, .DCSURF_SURFACE_INUSE_HIGH
= 0x000034C0 + 0x08b6, .DCSURF_SURFACE_INUSE_C = 0x000034C0 +
0x08b7, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x08b8, .
DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x08b9, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH
= 0x000034C0 + 0x08ba, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0
+ 0x08bb, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0
+ 0x08bc, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x08ae, .DCSURF_SURFACE_FLIP_INTERRUPT
= 0x000034C0 + 0x08b4, .HUBPRET_CONTROL = 0x000034C0 + 0x08fe
, .HUBPRET_READ_LINE_STATUS = 0x000034C0 + 0x0907, .DCN_EXPANSION_MODE
= 0x000034C0 + 0x08c0, .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 +
0x0885, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x0886, .BLANK_OFFSET_0
= 0x000034C0 + 0x08da, .BLANK_OFFSET_1 = 0x000034C0 + 0x08db
, .DST_DIMENSIONS = 0x000034C0 + 0x08dc, .DST_AFTER_SCALER = 0x000034C0
+ 0x08dd, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x08e0, .REF_FREQ_TO_PIX_FREQ
= 0x000034C0 + 0x08f3, .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x08e1
, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x08e3, .NOM_PARAMETERS_4
= 0x000034C0 + 0x08ec, .NOM_PARAMETERS_5 = 0x000034C0 + 0x08ed
, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x08f0, .PER_LINE_DELIVERY
= 0x000034C0 + 0x08f1, .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x08e2
, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x08e4, .NOM_PARAMETERS_6
= 0x000034C0 + 0x08ee, .NOM_PARAMETERS_7 = 0x000034C0 + 0x08ef
, .DCN_TTU_QOS_WM = 0x000034C0 + 0x08c1, .DCN_GLOBAL_TTU_CNTL
= 0x000034C0 + 0x08c2, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x08c3
, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x08c4, .DCN_SURF1_TTU_CNTL0
= 0x000034C0 + 0x08c5, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x08c6
, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x08c7, .DCN_CUR0_TTU_CNTL1
= 0x000034C0 + 0x08c8, .HUBP_CLK_CNTL = 0x000034C0 + 0x0888,
.PREFETCH_SETTINGS = 0x000034C0 + 0x08de, .PREFETCH_SETTINGS_C
= 0x000034C0 + 0x08df, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x08b0
, .CURSOR_SETTINGS = 0x000034C0 + 0x08f2, .CURSOR_SURFACE_ADDRESS_HIGH
= 0x000034C0 + 0x090e, .CURSOR_SURFACE_ADDRESS = 0x000034C0 +
0x090d, .CURSOR_SIZE = 0x000034C0 + 0x090f, .CURSOR_CONTROL =
0x000034C0 + 0x090c, .CURSOR_POSITION = 0x000034C0 + 0x0910,
.CURSOR_HOT_SPOT = 0x000034C0 + 0x0911, .CURSOR_DST_OFFSET =
0x000034C0 + 0x0913, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0916
, .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0917, .DMDATA_CNTL = 0x000034C0
+ 0x0918, .DMDATA_SW_CNTL = 0x000034C0 + 0x091b, .DMDATA_QOS_CNTL
= 0x000034C0 + 0x0919, .DMDATA_SW_DATA = 0x000034C0 + 0x091c
, .DMDATA_STATUS = 0x000034C0 + 0x091a, .FLIP_PARAMETERS_0 = 0x000034C0
+ 0x08e5, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x08e7}
527};
528
529static const struct dcn201_hubp_shift hubp_shift = {
530 HUBP_MASK_SH_LIST_DCN201(__SHIFT).HUBP_BLANK_EN = 0x0, .HUBP_TTU_DISABLE = 0xc, .HUBP_UNDERFLOW_STATUS
= 0x1c, .HUBP_UNDERFLOW_CLEAR = 0x1f, .HUBP_NO_OUTSTANDING_REQ
= 0x1, .HUBP_VTG_SEL = 0x4, .HUBP_DISABLE = 0x2, .HUBP_IN_BLANK
= 0x3, .NUM_PIPES = 0x0, .NUM_BANKS = 0x3, .PIPE_INTERLEAVE =
0x6, .NUM_SE = 0x8, .NUM_RB_PER_SE = 0xa, .MAX_COMPRESSED_FRAGS
= 0xc, .SW_MODE = 0x0, .META_LINEAR = 0x9, .PIPE_ALIGNED = 0xb
, .PITCH = 0x0, .META_PITCH = 0x10, .PITCH_C = 0x0, .META_PITCH_C
= 0x10, .SURFACE_PIXEL_FORMAT = 0x0, .SURFACE_FLIP_TYPE = 0x1
, .SURFACE_FLIP_MODE_FOR_STEREOSYNC = 0xc, .SURFACE_FLIP_IN_STEREOSYNC
= 0x10, .SURFACE_FLIP_PENDING = 0x8, .SURFACE_UPDATE_LOCK = 0x0
, .PRI_VIEWPORT_WIDTH = 0x0, .PRI_VIEWPORT_HEIGHT = 0x10, .PRI_VIEWPORT_X_START
= 0x0, .PRI_VIEWPORT_Y_START = 0x10, .SEC_VIEWPORT_WIDTH = 0x0
, .SEC_VIEWPORT_HEIGHT = 0x10, .SEC_VIEWPORT_X_START = 0x0, .
SEC_VIEWPORT_Y_START = 0x10, .PRI_VIEWPORT_WIDTH_C = 0x0, .PRI_VIEWPORT_HEIGHT_C
= 0x10, .PRI_VIEWPORT_X_START_C = 0x0, .PRI_VIEWPORT_Y_START_C
= 0x10, .SEC_VIEWPORT_WIDTH_C = 0x0, .SEC_VIEWPORT_HEIGHT_C =
0x10, .SEC_VIEWPORT_X_START_C = 0x0, .SEC_VIEWPORT_Y_START_C
= 0x10, .PRIMARY_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_SURFACE_ADDRESS
= 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_SURFACE_ADDRESS
= 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_META_SURFACE_ADDRESS
= 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_META_SURFACE_ADDRESS
= 0x0, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_SURFACE_ADDRESS_C
= 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_SURFACE_ADDRESS_C
= 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_META_SURFACE_ADDRESS_C
= 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_META_SURFACE_ADDRESS_C
= 0x0, .SURFACE_INUSE_ADDRESS = 0x0, .SURFACE_INUSE_ADDRESS_HIGH
= 0x0, .SURFACE_INUSE_ADDRESS_C = 0x0, .SURFACE_INUSE_ADDRESS_HIGH_C
= 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH
= 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C
= 0x0, .PRIMARY_SURFACE_TMZ = 0x0, .PRIMARY_SURFACE_TMZ_C = 0x4
, .PRIMARY_META_SURFACE_TMZ = 0x10, .PRIMARY_META_SURFACE_TMZ_C
= 0x11, .PRIMARY_SURFACE_DCC_EN = 0x1, .PRIMARY_SURFACE_DCC_IND_64B_BLK
= 0x2, .SECONDARY_SURFACE_TMZ = 0x8, .SECONDARY_SURFACE_TMZ_C
= 0xc, .SECONDARY_META_SURFACE_TMZ = 0x12, .SECONDARY_META_SURFACE_TMZ_C
= 0x13, .SECONDARY_SURFACE_DCC_EN = 0x9, .SECONDARY_SURFACE_DCC_IND_64B_BLK
= 0xa, .SURFACE_FLIP_INT_MASK = 0x0, .DET_BUF_PLANE1_BASE_ADDRESS
= 0x0, .CROSSBAR_SRC_CB_B = 0x14, .CROSSBAR_SRC_CR_R = 0x16,
.PIPE_READ_VBLANK = 0x0, .DRQ_EXPANSION_MODE = 0x0, .PRQ_EXPANSION_MODE
= 0x6, .MRQ_EXPANSION_MODE = 0x4, .CRQ_EXPANSION_MODE = 0x2,
.CHUNK_SIZE = 0x8, .MIN_CHUNK_SIZE = 0xb, .META_CHUNK_SIZE =
0x10, .MIN_META_CHUNK_SIZE = 0x12, .DPTE_GROUP_SIZE = 0x14, .
SWATH_HEIGHT = 0x0, .PTE_ROW_HEIGHT_LINEAR = 0x4, .CHUNK_SIZE_C
= 0x8, .MIN_CHUNK_SIZE_C = 0xb, .META_CHUNK_SIZE_C = 0x10, .
MIN_META_CHUNK_SIZE_C = 0x12, .DPTE_GROUP_SIZE_C = 0x14, .SWATH_HEIGHT_C
= 0x0, .PTE_ROW_HEIGHT_LINEAR_C = 0x4, .REFCYC_H_BLANK_END =
0x0, .DLG_V_BLANK_END = 0x10, .MIN_DST_Y_NEXT_START = 0x0, .
REFCYC_PER_HTOTAL = 0x0, .REFCYC_X_AFTER_SCALER = 0x0, .DST_Y_AFTER_SCALER
= 0x10, .DST_Y_PER_VM_VBLANK = 0x0, .DST_Y_PER_ROW_VBLANK = 0x8
, .REF_FREQ_TO_PIX_FREQ = 0x0, .REFCYC_PER_PTE_GROUP_VBLANK_L
= 0x0, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x0, .DST_Y_PER_META_ROW_NOM_L
= 0x0, .REFCYC_PER_META_CHUNK_NOM_L = 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_L
= 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x10, .REFCYC_PER_LINE_DELIVERY_L
= 0x0, .REFCYC_PER_LINE_DELIVERY_C = 0x10, .REFCYC_PER_PTE_GROUP_VBLANK_C
= 0x0, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x0, .DST_Y_PER_META_ROW_NOM_C
= 0x0, .REFCYC_PER_META_CHUNK_NOM_C = 0x0, .QoS_LEVEL_LOW_WM
= 0x0, .QoS_LEVEL_HIGH_WM = 0x10, .MIN_TTU_VBLANK = 0x0, .QoS_LEVEL_FLIP
= 0x1c, .REFCYC_PER_REQ_DELIVERY = 0x0, .QoS_LEVEL_FIXED = 0x18
, .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE = 0x0
, .HUBP_CLOCK_ENABLE = 0x0, .RB_ALIGNED = 0xa, .MPTE_GROUP_SIZE
= 0x18, .MPTE_GROUP_SIZE_C = 0x18, .DST_Y_PREFETCH = 0x18, .
VRATIO_PREFETCH = 0x0, .VRATIO_PREFETCH_C = 0x0, .SURFACE_TRIPLE_BUFFER_ENABLE
= 0xa, .CURSOR0_DST_Y_OFFSET = 0x0, .CURSOR0_CHUNK_HDL_ADJUST
= 0x8, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0, .CURSOR_SURFACE_ADDRESS
= 0x0, .CURSOR_WIDTH = 0x10, .CURSOR_HEIGHT = 0x0, .CURSOR_MODE
= 0x8, .CURSOR_2X_MAGNIFY = 0x4, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK
= 0x18, .CURSOR_ENABLE = 0x0, .CURSOR_X_POSITION = 0x10, .CURSOR_Y_POSITION
= 0x0, .CURSOR_HOT_SPOT_X = 0x10, .CURSOR_HOT_SPOT_Y = 0x0, .
CURSOR_DST_X_OFFSET = 0x0, .DMDATA_ADDRESS_HIGH = 0x0, .DMDATA_MODE
= 0x2, .DMDATA_UPDATED = 0x0, .DMDATA_REPEAT = 0x1, .DMDATA_SIZE
= 0x10, .DMDATA_SW_UPDATED = 0x0, .DMDATA_SW_REPEAT = 0x1, .
DMDATA_SW_SIZE = 0x10, .DMDATA_QOS_MODE = 0x0, .DMDATA_QOS_LEVEL
= 0x4, .DMDATA_DL_DELTA = 0x10, .DST_Y_PER_VM_FLIP = 0x0, .DST_Y_PER_ROW_FLIP
= 0x8, .REFCYC_PER_META_CHUNK_FLIP_L = 0x0, .HUBP_VREADY_AT_OR_AFTER_VSYNC
= 0x8, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x9, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS
= 0x9
531};
532
533static const struct dcn201_hubp_mask hubp_mask = {
534 HUBP_MASK_SH_LIST_DCN201(_MASK).HUBP_BLANK_EN = 0x00000001L, .HUBP_TTU_DISABLE = 0x00001000L
, .HUBP_UNDERFLOW_STATUS = 0x70000000L, .HUBP_UNDERFLOW_CLEAR
= 0x80000000L, .HUBP_NO_OUTSTANDING_REQ = 0x00000002L, .HUBP_VTG_SEL
= 0x000000F0L, .HUBP_DISABLE = 0x00000004L, .HUBP_IN_BLANK =
0x00000008L, .NUM_PIPES = 0x00000007L, .NUM_BANKS = 0x00000038L
, .PIPE_INTERLEAVE = 0x000000C0L, .NUM_SE = 0x00000300L, .NUM_RB_PER_SE
= 0x00000C00L, .MAX_COMPRESSED_FRAGS = 0x00003000L, .SW_MODE
= 0x0000001FL, .META_LINEAR = 0x00000200L, .PIPE_ALIGNED = 0x00000800L
, .PITCH = 0x00003FFFL, .META_PITCH = 0x3FFF0000L, .PITCH_C =
0x00003FFFL, .META_PITCH_C = 0x3FFF0000L, .SURFACE_PIXEL_FORMAT
= 0x0000007FL, .SURFACE_FLIP_TYPE = 0x00000002L, .SURFACE_FLIP_MODE_FOR_STEREOSYNC
= 0x00003000L, .SURFACE_FLIP_IN_STEREOSYNC = 0x00010000L, .SURFACE_FLIP_PENDING
= 0x00000100L, .SURFACE_UPDATE_LOCK = 0x00000001L, .PRI_VIEWPORT_WIDTH
= 0x00003FFFL, .PRI_VIEWPORT_HEIGHT = 0x3FFF0000L, .PRI_VIEWPORT_X_START
= 0x00003FFFL, .PRI_VIEWPORT_Y_START = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH
= 0x00003FFFL, .SEC_VIEWPORT_HEIGHT = 0x3FFF0000L, .SEC_VIEWPORT_X_START
= 0x00003FFFL, .SEC_VIEWPORT_Y_START = 0x3FFF0000L, .PRI_VIEWPORT_WIDTH_C
= 0x00003FFFL, .PRI_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .PRI_VIEWPORT_X_START_C
= 0x00003FFFL, .PRI_VIEWPORT_Y_START_C = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH_C
= 0x00003FFFL, .SEC_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .SEC_VIEWPORT_X_START_C
= 0x00003FFFL, .SEC_VIEWPORT_Y_START_C = 0x3FFF0000L, .PRIMARY_SURFACE_ADDRESS_HIGH
= 0x0000FFFFL, .PRIMARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH
= 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .PRIMARY_META_SURFACE_ADDRESS_HIGH
= 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS = 0xFFFFFFFFL, .
SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .SECONDARY_META_SURFACE_ADDRESS
= 0xFFFFFFFFL, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL
, .PRIMARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH_C
= 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .
PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS_C
= 0xFFFFFFFFL, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL
, .SECONDARY_META_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS
= 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH = 0x0000FFFFL, .SURFACE_INUSE_ADDRESS_C
= 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, .
SURFACE_EARLIEST_INUSE_ADDRESS = 0xFFFFFFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH
= 0x0000FFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0xFFFFFFFFL
, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_SURFACE_TMZ
= 0x00000001L, .PRIMARY_SURFACE_TMZ_C = 0x00000010L, .PRIMARY_META_SURFACE_TMZ
= 0x00010000L, .PRIMARY_META_SURFACE_TMZ_C = 0x00020000L, .PRIMARY_SURFACE_DCC_EN
= 0x00000002L, .PRIMARY_SURFACE_DCC_IND_64B_BLK = 0x00000004L
, .SECONDARY_SURFACE_TMZ = 0x00000100L, .SECONDARY_SURFACE_TMZ_C
= 0x00001000L, .SECONDARY_META_SURFACE_TMZ = 0x00040000L, .SECONDARY_META_SURFACE_TMZ_C
= 0x00080000L, .SECONDARY_SURFACE_DCC_EN = 0x00000200L, .SECONDARY_SURFACE_DCC_IND_64B_BLK
= 0x00000400L, .SURFACE_FLIP_INT_MASK = 0x00000001L, .DET_BUF_PLANE1_BASE_ADDRESS
= 0x00000FFFL, .CROSSBAR_SRC_CB_B = 0x00300000L, .CROSSBAR_SRC_CR_R
= 0x00C00000L, .PIPE_READ_VBLANK = 0x00000001L, .DRQ_EXPANSION_MODE
= 0x00000003L, .PRQ_EXPANSION_MODE = 0x000000C0L, .MRQ_EXPANSION_MODE
= 0x00000030L, .CRQ_EXPANSION_MODE = 0x0000000CL, .CHUNK_SIZE
= 0x00000700L, .MIN_CHUNK_SIZE = 0x00001800L, .META_CHUNK_SIZE
= 0x00030000L, .MIN_META_CHUNK_SIZE = 0x000C0000L, .DPTE_GROUP_SIZE
= 0x00700000L, .SWATH_HEIGHT = 0x00000007L, .PTE_ROW_HEIGHT_LINEAR
= 0x00000070L, .CHUNK_SIZE_C = 0x00000700L, .MIN_CHUNK_SIZE_C
= 0x00001800L, .META_CHUNK_SIZE_C = 0x00030000L, .MIN_META_CHUNK_SIZE_C
= 0x000C0000L, .DPTE_GROUP_SIZE_C = 0x00700000L, .SWATH_HEIGHT_C
= 0x00000007L, .PTE_ROW_HEIGHT_LINEAR_C = 0x00000070L, .REFCYC_H_BLANK_END
= 0x00001FFFL, .DLG_V_BLANK_END = 0x7FFF0000L, .MIN_DST_Y_NEXT_START
= 0x0003FFFFL, .REFCYC_PER_HTOTAL = 0x001FFFFFL, .REFCYC_X_AFTER_SCALER
= 0x00001FFFL, .DST_Y_AFTER_SCALER = 0x00070000L, .DST_Y_PER_VM_VBLANK
= 0x0000001FL, .DST_Y_PER_ROW_VBLANK = 0x00003F00L, .REF_FREQ_TO_PIX_FREQ
= 0x001FFFFFL, .REFCYC_PER_PTE_GROUP_VBLANK_L = 0x007FFFFFL,
.REFCYC_PER_META_CHUNK_VBLANK_L = 0x007FFFFFL, .DST_Y_PER_META_ROW_NOM_L
= 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_L = 0x007FFFFFL, .
REFCYC_PER_LINE_DELIVERY_PRE_L = 0x00001FFFL, .REFCYC_PER_LINE_DELIVERY_PRE_C
= 0x1FFF0000L, .REFCYC_PER_LINE_DELIVERY_L = 0x00001FFFL, .REFCYC_PER_LINE_DELIVERY_C
= 0x1FFF0000L, .REFCYC_PER_PTE_GROUP_VBLANK_C = 0x007FFFFFL,
.REFCYC_PER_META_CHUNK_VBLANK_C = 0x007FFFFFL, .DST_Y_PER_META_ROW_NOM_C
= 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_C = 0x007FFFFFL, .
QoS_LEVEL_LOW_WM = 0x00003FFFL, .QoS_LEVEL_HIGH_WM = 0x3FFF0000L
, .MIN_TTU_VBLANK = 0x00FFFFFFL, .QoS_LEVEL_FLIP = 0xF0000000L
, .REFCYC_PER_REQ_DELIVERY = 0x007FFFFFL, .QoS_LEVEL_FIXED = 0x0F000000L
, .QoS_RAMP_DISABLE = 0x10000000L, .REFCYC_PER_REQ_DELIVERY_PRE
= 0x007FFFFFL, .HUBP_CLOCK_ENABLE = 0x00000001L, .RB_ALIGNED
= 0x00000400L, .MPTE_GROUP_SIZE = 0x07000000L, .MPTE_GROUP_SIZE_C
= 0x07000000L, .DST_Y_PREFETCH = 0xFF000000L, .VRATIO_PREFETCH
= 0x003FFFFFL, .VRATIO_PREFETCH_C = 0x003FFFFFL, .SURFACE_TRIPLE_BUFFER_ENABLE
= 0x00000400L, .CURSOR0_DST_Y_OFFSET = 0x000000FFL, .CURSOR0_CHUNK_HDL_ADJUST
= 0x00000300L, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .
CURSOR_SURFACE_ADDRESS = 0xFFFFFFFFL, .CURSOR_WIDTH = 0x01FF0000L
, .CURSOR_HEIGHT = 0x000001FFL, .CURSOR_MODE = 0x00000700L, .
CURSOR_2X_MAGNIFY = 0x00000010L, .CURSOR_PITCH = 0x00030000L,
.CURSOR_LINES_PER_CHUNK = 0x1F000000L, .CURSOR_ENABLE = 0x00000001L
, .CURSOR_X_POSITION = 0x3FFF0000L, .CURSOR_Y_POSITION = 0x00003FFFL
, .CURSOR_HOT_SPOT_X = 0x00FF0000L, .CURSOR_HOT_SPOT_Y = 0x000000FFL
, .CURSOR_DST_X_OFFSET = 0x00001FFFL, .DMDATA_ADDRESS_HIGH = 0x0000FFFFL
, .DMDATA_MODE = 0x00000004L, .DMDATA_UPDATED = 0x00000001L, .
DMDATA_REPEAT = 0x00000002L, .DMDATA_SIZE = 0x0FFF0000L, .DMDATA_SW_UPDATED
= 0x00000001L, .DMDATA_SW_REPEAT = 0x00000002L, .DMDATA_SW_SIZE
= 0x0FFF0000L, .DMDATA_QOS_MODE = 0x00000001L, .DMDATA_QOS_LEVEL
= 0x000000F0L, .DMDATA_DL_DELTA = 0xFFFF0000L, .DST_Y_PER_VM_FLIP
= 0x0000001FL, .DST_Y_PER_ROW_FLIP = 0x00003F00L, .REFCYC_PER_META_CHUNK_FLIP_L
= 0x007FFFFFL, .HUBP_VREADY_AT_OR_AFTER_VSYNC = 0x00000100L,
.HUBP_DISABLE_STOP_DATA_DURING_VM = 0x00000200L, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS
= 0x00000200L
535};
536
537static const struct dcn_hubbub_registers hubbub_reg = {
538 HUBBUB_REG_LIST_DCN201(0).DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x000034C0 + 0x0509,
.DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x000034C0
+ 0x050d, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x000034C0
+ 0x050e, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x000034C0
+ 0x0512, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x000034C0
+ 0x0513, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x000034C0
+ 0x0517, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x000034C0
+ 0x0518, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x000034C0
+ 0x051c, .DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL = 0x000034C0 +
0x051d, .DCHUBBUB_ARB_DRAM_STATE_CNTL = 0x000034C0 + 0x0508,
.DCHUBBUB_ARB_SAT_LEVEL = 0x000034C0 + 0x0506, .DCHUBBUB_ARB_DF_REQ_OUTSTAND
= 0x000034C0 + 0x0505, .DCHUBBUB_GLOBAL_TIMER_CNTL = 0x000034C0
+ 0x051f, .DCHUBBUB_TEST_DEBUG_INDEX = 0x000034C0 + 0x053d, .
DCHUBBUB_TEST_DEBUG_DATA = 0x000034C0 + 0x053e, .DCHUBBUB_SOFT_RESET
= 0x000034C0 + 0x052e, .DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A
= 0x000034C0 + 0x050a, .DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B
= 0x000034C0 + 0x050f, .DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C
= 0x000034C0 + 0x0514, .DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D
= 0x000034C0 + 0x0519, .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04f1
539};
540
541static const struct dcn_hubbub_shift hubbub_shift = {
542 HUBBUB_MASK_SH_LIST_DCN201(__SHIFT).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCHUBBUB_GLOBAL_SOFT_RESET
= 0x0, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x8, .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE
= 0x4, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x0, .
DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x1, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE
= 0x4, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x5,
.DCHUBBUB_ARB_SAT_LEVEL = 0x0, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND
= 0x10, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
= 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
= 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x0
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
= 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x0
, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0
543};
544
545static const struct dcn_hubbub_mask hubbub_mask = {
546 HUBBUB_MASK_SH_LIST_DCN201(_MASK).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0x00001000L, .DCHUBBUB_GLOBAL_SOFT_RESET
= 0x00000001L, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x00000100L
, .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE = 0x00000010L
, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x00000001L,
.DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x00000002L,
.DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE = 0x00000010L,
.DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x00000020L
, .DCHUBBUB_ARB_SAT_LEVEL = 0xFFFFFFFFL, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND
= 0x01FF0000L, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x001FFFFFL
, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x001FFFFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
= 0x001FFFFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x001FFFFFL
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x001FFFFFL
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x001FFFFFL
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x001FFFFFL
, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x001FFFFFL
, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL
547};
548
549
550static const struct dccg_registers dccg_regs = {
551 DCCG_COMMON_REG_LIST_DCN_BASE().DPPCLK_DTO_CTRL = 0x000000C0 + 0x00b6, .DPPCLK_DTO_PARAM[0] =
0x000000C0 + 0x0099, .DPPCLK_DTO_PARAM[1] = 0x000000C0 + 0x009a
, .DPPCLK_DTO_PARAM[2] = 0x000000C0 + 0x009b, .DPPCLK_DTO_PARAM
[3] = 0x000000C0 + 0x009c, .REFCLK_CNTL = 0x000000C0 + 0x0049
, .OTG_PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .OTG_PIXEL_RATE_CNTL
[1] = 0x000000C0 + 0x0084, .DISPCLK_FREQ_CHANGE_CNTL = 0x000000C0
+ 0x0071
552};
553
554static const struct dccg_shift dccg_shift = {
555 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(__SHIFT).DPPCLK_DTO_ENABLE[0] = 0x0, .DPPCLK_DTO_DB_EN[0] = 0x1, .DPPCLK_DTO_ENABLE
[1] = 0x4, .DPPCLK_DTO_DB_EN[1] = 0x5, .DPPCLK_DTO_ENABLE[2] =
0x8, .DPPCLK_DTO_DB_EN[2] = 0x9, .DPPCLK_DTO_ENABLE[3] = 0xc
, .DPPCLK_DTO_DB_EN[3] = 0xd, .DPPCLK0_DTO_PHASE = 0x0, .DPPCLK0_DTO_MODULO
= 0x10, .REFCLK_CLOCK_EN = 0x0, .REFCLK_SRC_SEL = 0x1, .DISPCLK_STEP_DELAY
= 0x0, .DISPCLK_STEP_SIZE = 0x10, .DISPCLK_FREQ_RAMP_DONE = 0x14
, .DISPCLK_MAX_ERRDET_CYCLES = 0x19, .DCCG_FIFO_ERRDET_RESET =
0x1c, .DCCG_FIFO_ERRDET_STATE = 0x1d, .DCCG_FIFO_ERRDET_OVR_EN
= 0x1e, .DISPCLK_CHG_FWD_CORR_DISABLE = 0x1f, .OTG_ADD_PIXEL
[0] = 0x8, .OTG_ADD_PIXEL[1] = 0x8, .OTG_DROP_PIXEL[0] = 0x9,
.OTG_DROP_PIXEL[1] = 0x9
556};
557
558static const struct dccg_mask dccg_mask = {
559 DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(_MASK).DPPCLK_DTO_ENABLE[0] = 0x00000001L, .DPPCLK_DTO_DB_EN[0] = 0x00000002L
, .DPPCLK_DTO_ENABLE[1] = 0x00000010L, .DPPCLK_DTO_DB_EN[1] =
0x00000020L, .DPPCLK_DTO_ENABLE[2] = 0x00000100L, .DPPCLK_DTO_DB_EN
[2] = 0x00000200L, .DPPCLK_DTO_ENABLE[3] = 0x00001000L, .DPPCLK_DTO_DB_EN
[3] = 0x00002000L, .DPPCLK0_DTO_PHASE = 0x000000FFL, .DPPCLK0_DTO_MODULO
= 0x00FF0000L, .REFCLK_CLOCK_EN = 0x00000001L, .REFCLK_SRC_SEL
= 0x00000002L, .DISPCLK_STEP_DELAY = 0x00003FFFL, .DISPCLK_STEP_SIZE
= 0x000F0000L, .DISPCLK_FREQ_RAMP_DONE = 0x00100000L, .DISPCLK_MAX_ERRDET_CYCLES
= 0x0E000000L, .DCCG_FIFO_ERRDET_RESET = 0x10000000L, .DCCG_FIFO_ERRDET_STATE
= 0x20000000L, .DCCG_FIFO_ERRDET_OVR_EN = 0x40000000L, .DISPCLK_CHG_FWD_CORR_DISABLE
= 0x80000000L, .OTG_ADD_PIXEL[0] = 0x00000100L, .OTG_ADD_PIXEL
[1] = 0x00000100L, .OTG_DROP_PIXEL[0] = 0x00000200L, .OTG_DROP_PIXEL
[1] = 0x00000200L
560};
561
562static const struct resource_caps res_cap_dnc201 = {
563 .num_timing_generator = 2,
564 .num_opp = 2,
565 .num_video_plane = 4,
566 .num_audio = 2,
567 .num_stream_encoder = 2,
568 .num_pll = 2,
569 .num_ddc = 2,
570};
571
572static const struct dc_plane_cap plane_cap = {
573 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
574 .blends_with_above = true1,
575 .blends_with_below = true1,
576 .per_pixel_alpha = true1,
577
578 .pixel_format_support = {
579 .argb8888 = true1,
580 .nv12 = false0,
581 .fp16 = true1,
582 .p010 = false0,
583 },
584
585 .max_upscale_factor = {
586 .argb8888 = 16000,
587 .nv12 = 16000,
588 .fp16 = 1
589 },
590
591 .max_downscale_factor = {
592 .argb8888 = 250,
593 .nv12 = 250,
594 .fp16 = 250
595 },
596 64,
597 64
598};
599
600static const struct dc_debug_options debug_defaults_drv = {
601 .disable_dmcu = true1,
602 .force_abm_enable = false0,
603 .timing_trace = false0,
604 .clock_trace = true1,
605 .disable_pplib_clock_request = true1,
606 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
607 .force_single_disp_pipe_split = false0,
608 .disable_dcc = DCC_ENABLE,
609 .vsr_support = true1,
610 .performance_trace = false0,
611 .az_endpoint_mute_only = true1,
612 .max_downscale_src_width = 3840,
613 .disable_pplib_wm_range = true1,
614 .scl_reset_length10 = true1,
615 .sanity_checks = false0,
616 .underflow_assert_delay_us = 0xFFFFFFFF,
617 .enable_tri_buf = false0,
618};
619
620static void dcn201_dpp_destroy(struct dpp **dpp)
621{
622 kfree(TO_DCN201_DPP(*dpp)({ const __typeof( ((struct dcn201_dpp *)0)->base ) *__mptr
= (*dpp); (struct dcn201_dpp *)( (char *)__mptr - __builtin_offsetof
(struct dcn201_dpp, base) );}));
623 *dpp = NULL((void *)0);
624}
625
626static struct dpp *dcn201_dpp_create(
627 struct dc_context *ctx,
628 uint32_t inst)
629{
630 struct dcn201_dpp *dpp =
631 kzalloc(sizeof(struct dcn201_dpp), GFP_ATOMIC0x0002);
632
633 if (!dpp)
634 return NULL((void *)0);
635
636 if (dpp201_construct(dpp, ctx, inst,
637 &tf_regs[inst], &tf_shift, &tf_mask))
638 return &dpp->base;
639
640 kfree(dpp);
641 return NULL((void *)0);
642}
643
644static struct input_pixel_processor *dcn201_ipp_create(
645 struct dc_context *ctx, uint32_t inst)
646{
647 struct dcn10_ipp *ipp =
648 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC0x0002);
649
650 if (!ipp) {
651 return NULL((void *)0);
652 }
653
654 dcn20_ipp_construct(ipp, ctx, inst,
655 &ipp_regs[inst], &ipp_shift, &ipp_mask);
656 return &ipp->base;
657}
658
659
660static struct output_pixel_processor *dcn201_opp_create(
661 struct dc_context *ctx, uint32_t inst)
662{
663 struct dcn201_opp *opp =
664 kzalloc(sizeof(struct dcn201_opp), GFP_ATOMIC0x0002);
665
666 if (!opp) {
667 return NULL((void *)0);
668 }
669
670 dcn201_opp_construct(opp, ctx, inst,
671 &opp_regs[inst], &opp_shift, &opp_mask);
672 return &opp->base;
673}
674
675static struct dce_aux *dcn201_aux_engine_create(struct dc_context *ctx,
676 uint32_t inst)
677{
678 struct aux_engine_dce110 *aux_engine =
679 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC0x0002);
680
681 if (!aux_engine)
682 return NULL((void *)0);
683
684 dce110_aux_engine_construct(aux_engine, ctx, inst,
685 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
686 &aux_engine_regs[inst],
687 &aux_mask,
688 &aux_shift,
689 ctx->dc->caps.extended_aux_timeout_support);
690
691 return &aux_engine->base;
692}
693#define i2c_inst_regs(id){ .SETUP = DMU_BASE__INST0_SEGmmDC_I2C_DDCid_SETUP_BASE_IDX +
mmDC_I2C_DDCid_SETUP, .SPEED = DMU_BASE__INST0_SEGmmDC_I2C_DDCid_SPEED_BASE_IDX
+ mmDC_I2C_DDCid_SPEED, .HW_STATUS = DMU_BASE__INST0_SEGmmDC_I2C_DDCid_HW_STATUS_BASE_IDX
+ mmDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b } { I2C_HW_ENGINE_COMMON_REG_LIST(id).SETUP = DMU_BASE__INST0_SEGmmDC_I2C_DDCid_SETUP_BASE_IDX + mmDC_I2C_DDCid_SETUP
, .SPEED = DMU_BASE__INST0_SEGmmDC_I2C_DDCid_SPEED_BASE_IDX +
mmDC_I2C_DDCid_SPEED, .HW_STATUS = DMU_BASE__INST0_SEGmmDC_I2C_DDCid_HW_STATUS_BASE_IDX
+ mmDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b }
694
695static const struct dce_i2c_registers i2c_hw_regs[] = {
696 i2c_inst_regs(1){ .SETUP = 0x000034C0 + 0x1ea3, .SPEED = 0x000034C0 + 0x1ea2,
.HW_STATUS = 0x000034C0 + 0x1e9c, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b },
697 i2c_inst_regs(2){ .SETUP = 0x000034C0 + 0x1ea5, .SPEED = 0x000034C0 + 0x1ea4,
.HW_STATUS = 0x000034C0 + 0x1e9d, .DC_I2C_ARBITRATION = 0x000034C0
+ 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS
= 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae
, .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2
= 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1
, .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV
= 0x000000C0 + 0x007b },
698};
699
700static const struct dce_i2c_shift i2c_shifts = {
701 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT).DC_I2C_DDC1_ENABLE = 0x6, .DC_I2C_DDC1_TIME_LIMIT = 0x18, .DC_I2C_DDC1_DATA_DRIVE_EN
= 0x0, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x7, .DC_I2C_DDC1_DATA_DRIVE_SEL
= 0x1, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x10, .DC_I2C_DDC1_INTRA_BYTE_DELAY
= 0x8, .DC_I2C_DDC1_HW_STATUS = 0x0, .DC_I2C_SW_USE_I2C_REG_REQ
= 0x14, .DC_I2C_SW_DONE_USING_I2C_REG = 0x15, .DC_I2C_NO_QUEUED_SW_GO
= 0x4, .DC_I2C_SW_PRIORITY = 0x0, .DC_I2C_SOFT_RESET = 0x1, .
DC_I2C_SW_STATUS_RESET = 0x3, .DC_I2C_GO = 0x0, .DC_I2C_SEND_RESET
= 0x2, .DC_I2C_TRANSACTION_COUNT = 0x14, .DC_I2C_DDC_SELECT =
0x8, .DC_I2C_DDC1_PRESCALE = 0x10, .DC_I2C_DDC1_THRESHOLD = 0x0
, .DC_I2C_SW_STOPPED_ON_NACK = 0x8, .DC_I2C_SW_TIMEOUT = 0x5,
.DC_I2C_SW_ABORTED = 0x4, .DC_I2C_SW_DONE = 0x2, .DC_I2C_SW_STATUS
= 0x0, .DC_I2C_STOP_ON_NACK0 = 0x8, .DC_I2C_START0 = 0xc, .DC_I2C_RW0
= 0x0, .DC_I2C_STOP0 = 0xd, .DC_I2C_COUNT0 = 0x10, .DC_I2C_DATA_RW
= 0x0, .DC_I2C_DATA = 0x8, .DC_I2C_INDEX = 0x10, .DC_I2C_INDEX_WRITE
= 0x1f, .XTAL_REF_DIV = 0x8, .MICROSECOND_TIME_BASE_DIV = 0x0
, .DC_I2C_REG_RW_CNTL_STATUS = 0x2, .DC_I2C_DDC1_START_STOP_TIMING_CNTL
= 0x8, .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x2
702};
703
704static const struct dce_i2c_mask i2c_masks = {
705 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK).DC_I2C_DDC1_ENABLE = 0x00000040L, .DC_I2C_DDC1_TIME_LIMIT = 0xFF000000L
, .DC_I2C_DDC1_DATA_DRIVE_EN = 0x00000001L, .DC_I2C_DDC1_CLK_DRIVE_EN
= 0x00000080L, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x00000002L, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY
= 0x00FF0000L, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0x0000FF00L, .
DC_I2C_DDC1_HW_STATUS = 0x00000003L, .DC_I2C_SW_USE_I2C_REG_REQ
= 0x00100000L, .DC_I2C_SW_DONE_USING_I2C_REG = 0x00200000L, .
DC_I2C_NO_QUEUED_SW_GO = 0x00000010L, .DC_I2C_SW_PRIORITY = 0x00000003L
, .DC_I2C_SOFT_RESET = 0x00000002L, .DC_I2C_SW_STATUS_RESET =
0x00000008L, .DC_I2C_GO = 0x00000001L, .DC_I2C_SEND_RESET = 0x00000004L
, .DC_I2C_TRANSACTION_COUNT = 0x00300000L, .DC_I2C_DDC_SELECT
= 0x00000700L, .DC_I2C_DDC1_PRESCALE = 0xFFFF0000L, .DC_I2C_DDC1_THRESHOLD
= 0x00000003L, .DC_I2C_SW_STOPPED_ON_NACK = 0x00000100L, .DC_I2C_SW_TIMEOUT
= 0x00000020L, .DC_I2C_SW_ABORTED = 0x00000010L, .DC_I2C_SW_DONE
= 0x00000004L, .DC_I2C_SW_STATUS = 0x00000003L, .DC_I2C_STOP_ON_NACK0
= 0x00000100L, .DC_I2C_START0 = 0x00001000L, .DC_I2C_RW0 = 0x00000001L
, .DC_I2C_STOP0 = 0x00002000L, .DC_I2C_COUNT0 = 0x03FF0000L, .
DC_I2C_DATA_RW = 0x00000001L, .DC_I2C_DATA = 0x0000FF00L, .DC_I2C_INDEX
= 0x03FF0000L, .DC_I2C_INDEX_WRITE = 0x80000000L, .XTAL_REF_DIV
= 0x00007F00L, .MICROSECOND_TIME_BASE_DIV = 0x0000007FL, .DC_I2C_REG_RW_CNTL_STATUS
= 0x0000000CL, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x00000300L
, .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x00000004L
706};
707
708static struct dce_i2c_hw *dcn201_i2c_hw_create(struct dc_context *ctx,
709 uint32_t inst)
710{
711 struct dce_i2c_hw *dce_i2c_hw =
712 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC0x0002);
713
714 if (!dce_i2c_hw)
715 return NULL((void *)0);
716
717 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
718 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
719
720 return dce_i2c_hw;
721}
722
723static struct mpc *dcn201_mpc_create(struct dc_context *ctx, uint32_t num_mpcc)
724{
725 struct dcn201_mpc *mpc201 = kzalloc(sizeof(struct dcn201_mpc),
726 GFP_ATOMIC0x0002);
727
728 if (!mpc201)
729 return NULL((void *)0);
730
731 dcn201_mpc_construct(mpc201, ctx,
732 &mpc_regs,
733 &mpc_shift,
734 &mpc_mask,
735 num_mpcc);
736
737 return &mpc201->base;
738}
739
740static struct hubbub *dcn201_hubbub_create(struct dc_context *ctx)
741{
742 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
743 GFP_ATOMIC0x0002);
744
745 if (!hubbub)
746 return NULL((void *)0);
747
748 hubbub201_construct(hubbub, ctx,
749 &hubbub_reg,
750 &hubbub_shift,
751 &hubbub_mask);
752
753 return &hubbub->base;
754}
755
756static struct timing_generator *dcn201_timing_generator_create(
757 struct dc_context *ctx,
758 uint32_t instance)
759{
760 struct optc *tgn10 =
761 kzalloc(sizeof(struct optc), GFP_ATOMIC0x0002);
762
763 if (!tgn10)
764 return NULL((void *)0);
765
766 tgn10->base.inst = instance;
767 tgn10->base.ctx = ctx;
768
769 tgn10->tg_regs = &tg_regs[instance];
770 tgn10->tg_shift = &tg_shift;
771 tgn10->tg_mask = &tg_mask;
772
773 dcn201_timing_generator_init(tgn10);
774
775 return &tgn10->base;
776}
777
778static const struct encoder_feature_support link_enc_feature = {
779 .max_hdmi_deep_color = COLOR_DEPTH_121212,
780 .max_hdmi_pixel_clock = 600000,
781 .hdmi_ycbcr420_supported = true1,
782 .dp_ycbcr420_supported = true1,
783 .fec_supported = true1,
784 .flags.bits.IS_HBR2_CAPABLE = true1,
785 .flags.bits.IS_HBR3_CAPABLE = true1,
786 .flags.bits.IS_TPS3_CAPABLE = true1,
787 .flags.bits.IS_TPS4_CAPABLE = true1
788};
789
790static struct link_encoder *dcn201_link_encoder_create(
791 struct dc_context *ctx,
792 const struct encoder_init_data *enc_init_data)
793{
794 struct dcn20_link_encoder *enc20 =
795 kzalloc(sizeof(struct dcn20_link_encoder), GFP_ATOMIC0x0002);
796 struct dcn10_link_encoder *enc10 = &enc20->enc10;
797
798 if (!enc20)
799 return NULL((void *)0);
800
801 dcn201_link_encoder_construct(enc20,
802 enc_init_data,
803 &link_enc_feature,
804 &link_enc_regs[enc_init_data->transmitter],
805 &link_enc_aux_regs[enc_init_data->channel - 1],
806 &link_enc_hpd_regs[enc_init_data->hpd_source],
807 &le_shift,
808 &le_mask);
809
810 return &enc10->base;
811}
812
813static struct clock_source *dcn201_clock_source_create(
814 struct dc_context *ctx,
815 struct dc_bios *bios,
816 enum clock_source_id id,
817 const struct dce110_clk_src_regs *regs,
818 bool_Bool dp_clk_src)
819{
820 struct dce110_clk_src *clk_src =
821 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC0x0002);
822
823 if (!clk_src)
824 return NULL((void *)0);
825
826 if (dce112_clk_src_construct(clk_src, ctx, bios, id,
827 regs, &cs_shift, &cs_mask)) {
828 clk_src->base.dp_clk_src = dp_clk_src;
829 return &clk_src->base;
830 }
831 kfree(clk_src);
832 return NULL((void *)0);
833}
834
835static void read_dce_straps(
836 struct dc_context *ctx,
837 struct resource_straps *straps)
838{
839 generic_reg_get(ctx, mmDC_PINSTRAPS0x2880 + BASE(mmDC_PINSTRAPS_BASE_IDX)0x000034C0,
840
841 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO)0xe, 0x0000C000L, &straps->dc_pinstraps_audio);
842}
843
844static struct audio *dcn201_create_audio(
845 struct dc_context *ctx, unsigned int inst)
846{
847 return dce_audio_create(ctx, inst,
848 &audio_regs[inst], &audio_shift, &audio_mask);
849}
850
851static struct stream_encoder *dcn201_stream_encoder_create(
852 enum engine_id eng_id,
853 struct dc_context *ctx)
854{
855 struct dcn10_stream_encoder *enc1 =
856 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_ATOMIC0x0002);
857
858 if (!enc1)
859 return NULL((void *)0);
860
861 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
862 &stream_enc_regs[eng_id],
863 &se_shift, &se_mask);
864
865 return &enc1->base;
866}
867
868static const struct dce_hwseq_registers hwseq_reg = {
869 HWSEQ_DCN201_REG_LIST().REFCLK_CNTL = 0x000000C0 + 0x0049, .DCHUBBUB_GLOBAL_TIMER_CNTL
= 0x000034C0 + 0x051f, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede
, .DCCG_GATE_DISABLE_CNTL = 0x000000C0 + 0x0074, .DCCG_GATE_DISABLE_CNTL2
= 0x000000C0 + 0x007c, .DCFCLK_CNTL = 0x000034C0 + 0x0530, .
DCFCLK_CNTL = 0x000034C0 + 0x0530, .DC_MEM_GLOBAL_PWR_REQ_CNTL
= 0x000000C0 + 0x0072, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080
, .PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .PHYPLL_PIXEL_RATE_CNTL
[0] = 0x000000C0 + 0x0083, .PHYPLL_PIXEL_RATE_CNTL[1] = 0x000000C0
+ 0x0087, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .
MILLISECOND_TIME_BASE_DIV = 0x000000C0 + 0x0070, .DISPCLK_FREQ_CHANGE_CNTL
= 0x000000C0 + 0x0071, .RBBMIF_TIMEOUT_DIS = 0x000034C0 + 0x005f
, .RBBMIF_TIMEOUT_DIS_2 = 0x000034C0 + 0x0060, .DCHUBBUB_CRC_CTRL
= 0x000034C0 + 0x04f1, .DPP_TOP0_DPP_CRC_CTRL = 0x000034C0 +
0x0cc9, .DPP_TOP0_DPP_CRC_VAL_B_A = 0x000034C0 + 0x0cc8, .DPP_TOP0_DPP_CRC_VAL_R_G
= 0x000034C0 + 0x0cc7, .MPC_CRC_CTRL = 0x000034C0 + 0x134b, .
MPC_CRC_RESULT_GB = 0x000034C0 + 0x134e, .MPC_CRC_RESULT_C = 0x000034C0
+ 0x134f, .MPC_CRC_RESULT_AR = 0x000034C0 + 0x134d, .AZALIA_AUDIO_DTO
= 0x000034C0 + 0x03c3, .AZALIA_CONTROLLER_CLOCK_GATING = 0x000034C0
+ 0x03c2, .MC_VM_FB_LOCATION_BASE = 0x0001A000 + 0x086c, .MC_VM_FB_LOCATION_TOP
= 0x0001A000 + 0x086d, .MC_VM_FB_OFFSET = 0x0001A000 + 0x0857
870};
871
872static const struct dce_hwseq_shift hwseq_shift = {
873 HWSEQ_DCN201_MASK_SH_LIST(__SHIFT).PIXEL_RATE_SOURCE = 0x0, .DP_DTO0_ENABLE = 0x4, .PHYPLL_PIXEL_RATE_SOURCE
= 0x0, .DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCFCLK_GATE_DIS
= 0x1f, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV
= 0x0, .AZALIA_AUDIO_DTO_MODULE = 0x10
874};
875
876static const struct dce_hwseq_mask hwseq_mask = {
877 HWSEQ_DCN201_MASK_SH_LIST(_MASK).PIXEL_RATE_SOURCE = 0x00000003L, .DP_DTO0_ENABLE = 0x00000010L
, .PHYPLL_PIXEL_RATE_SOURCE = 0x00000007L, .DCHUBBUB_GLOBAL_TIMER_ENABLE
= 0x00001000L, .DCFCLK_GATE_DIS = 0x80000000L, .DC_MEM_GLOBAL_PWR_REQ_DIS
= 0x00000001L, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, .
AZALIA_AUDIO_DTO_MODULE = 0xFFFF0000L
878};
879
880static struct dce_hwseq *dcn201_hwseq_create(
881 struct dc_context *ctx)
882{
883 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_ATOMIC0x0002);
884
885 if (hws) {
886 hws->ctx = ctx;
887 hws->regs = &hwseq_reg;
888 hws->shifts = &hwseq_shift;
889 hws->masks = &hwseq_mask;
890 }
891 return hws;
892}
893
894static const struct resource_create_funcs res_create_funcs = {
895 .read_dce_straps = read_dce_straps,
896 .create_audio = dcn201_create_audio,
897 .create_stream_encoder = dcn201_stream_encoder_create,
898 .create_hwseq = dcn201_hwseq_create,
899};
900
901static const struct resource_create_funcs res_create_maximus_funcs = {
902 .read_dce_straps = NULL((void *)0),
903 .create_audio = NULL((void *)0),
904 .create_stream_encoder = NULL((void *)0),
905 .create_hwseq = dcn201_hwseq_create,
906};
907
908static void dcn201_clock_source_destroy(struct clock_source **clk_src)
909{
910 kfree(TO_DCE110_CLK_SRC(*clk_src)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr
= (*clk_src); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof
(struct dce110_clk_src, base) );}));
911 *clk_src = NULL((void *)0);
912}
913
914static void dcn201_resource_destruct(struct dcn201_resource_pool *pool)
915{
916 unsigned int i;
917
918 for (i = 0; i < pool->base.stream_enc_count; i++) {
919 if (pool->base.stream_enc[i] != NULL((void *)0)) {
920 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])({ const __typeof( ((struct dcn10_stream_encoder *)0)->base
) *__mptr = (pool->base.stream_enc[i]); (struct dcn10_stream_encoder
*)( (char *)__mptr - __builtin_offsetof(struct dcn10_stream_encoder
, base) );}));
921 pool->base.stream_enc[i] = NULL((void *)0);
922 }
923 }
924
925
926 if (pool->base.mpc != NULL((void *)0)) {
927 kfree(TO_DCN201_MPC(pool->base.mpc)({ const __typeof( ((struct dcn201_mpc *)0)->base ) *__mptr
= (pool->base.mpc); (struct dcn201_mpc *)( (char *)__mptr
- __builtin_offsetof(struct dcn201_mpc, base) );}));
928 pool->base.mpc = NULL((void *)0);
929 }
930
931 if (pool->base.hubbub != NULL((void *)0)) {
932 kfree(pool->base.hubbub);
933 pool->base.hubbub = NULL((void *)0);
934 }
935
936 for (i = 0; i < pool->base.pipe_count; i++) {
937 if (pool->base.dpps[i] != NULL((void *)0))
938 dcn201_dpp_destroy(&pool->base.dpps[i]);
939
940 if (pool->base.ipps[i] != NULL((void *)0))
941 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
942
943 if (pool->base.hubps[i] != NULL((void *)0)) {
944 kfree(TO_DCN10_HUBP(pool->base.hubps[i])({ const __typeof( ((struct dcn10_hubp *)0)->base ) *__mptr
= (pool->base.hubps[i]); (struct dcn10_hubp *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_hubp, base) );}));
945 pool->base.hubps[i] = NULL((void *)0);
946 }
947
948 if (pool->base.irqs != NULL((void *)0)) {
949 dal_irq_service_destroy(&pool->base.irqs);
950 }
951 }
952
953 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
954 if (pool->base.opps[i] != NULL((void *)0))
955 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
956 }
957
958 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
959 if (pool->base.timing_generators[i] != NULL((void *)0)) {
960 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])({ const __typeof( ((struct optc *)0)->base ) *__mptr = (pool
->base.timing_generators[i]); (struct optc *)( (char *)__mptr
- __builtin_offsetof(struct optc, base) );}));
961 pool->base.timing_generators[i] = NULL((void *)0);
962 }
963 }
964 for (i = 0; i < pool->base.audio_count; i++) {
965 if (pool->base.audios[i])
966 dce_aud_destroy(&pool->base.audios[i]);
967 }
968
969 for (i = 0; i < pool->base.clk_src_count; i++) {
970 if (pool->base.clock_sources[i] != NULL((void *)0)) {
971 dcn201_clock_source_destroy(&pool->base.clock_sources[i]);
972 pool->base.clock_sources[i] = NULL((void *)0);
973 }
974 }
975
976 if (pool->base.dp_clock_source != NULL((void *)0)) {
977 dcn201_clock_source_destroy(&pool->base.dp_clock_source);
978 pool->base.dp_clock_source = NULL((void *)0);
979 }
980
981 if (pool->base.dccg != NULL((void *)0))
982 dcn_dccg_destroy(&pool->base.dccg);
983}
984
985static struct hubp *dcn201_hubp_create(
986 struct dc_context *ctx,
987 uint32_t inst)
988{
989 struct dcn201_hubp *hubp201 =
990 kzalloc(sizeof(struct dcn201_hubp), GFP_ATOMIC0x0002);
991
992 if (!hubp201)
993 return NULL((void *)0);
994
995 if (dcn201_hubp_construct(hubp201, ctx, inst,
996 &hubp_regs[inst], &hubp_shift, &hubp_mask))
997 return &hubp201->base;
998
999 kfree(hubp201);
1000 return NULL((void *)0);
1001}
1002
1003static struct pipe_ctx *dcn201_acquire_idle_pipe_for_layer(
1004 struct dc_state *context,
1005 const struct resource_pool *pool,
1006 struct dc_stream_state *stream)
1007{
1008 struct resource_context *res_ctx = &context->res_ctx;
1009 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
1
'head_pipe' initialized here
→
1010 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
1011
1012 if (!head_pipe)
2
←
Assuming 'head_pipe' is null
→
3
←
Taking true branch
→
1013 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn201/dcn201_resource.c"
, 1013); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
4
←
Taking true branch
→
5
←
Taking true branch
→
6
←
Loop condition is false. Exiting loop
→
7
←
Loop condition is false. Exiting loop
→
1014
1015 if (!idle_pipe)
8
←
Assuming 'idle_pipe' is non-null
→
9
←
Taking false branch
→
1016 return NULL((void *)0);
1017
1018 idle_pipe->stream = head_pipe->stream;
10
←
Access to field 'stream' results in a dereference of a null pointer (loaded from variable 'head_pipe')
1019 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
1020 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
1021
1022 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
1023 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1024 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
1025 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
1026
1027 return idle_pipe;
1028}
1029
1030static bool_Bool dcn201_get_dcc_compression_cap(const struct dc *dc,
1031 const struct dc_dcc_surface_param *input,
1032 struct dc_surface_dcc_cap *output)
1033{
1034 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1035 dc->res_pool->hubbub,
1036 input,
1037 output);
1038}
1039
1040static void dcn201_populate_dml_writeback_from_context(struct dc *dc,
1041 struct resource_context *res_ctx,
1042 display_e2e_pipe_params_st *pipes)
1043{
1044 DC_FP_START()dc_fpu_begin(__func__, 1044);
1045 dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
1046 DC_FP_END()dc_fpu_end(__func__, 1046);
1047}
1048
1049static void dcn201_destroy_resource_pool(struct resource_pool **pool)
1050{
1051 struct dcn201_resource_pool *dcn201_pool = TO_DCN201_RES_POOL(*pool)({ const __typeof( ((struct dcn201_resource_pool *)0)->base
) *__mptr = (*pool); (struct dcn201_resource_pool *)( (char *
)__mptr - __builtin_offsetof(struct dcn201_resource_pool, base
) );});
1052
1053 dcn201_resource_destruct(dcn201_pool);
1054 kfree(dcn201_pool);
1055 *pool = NULL((void *)0);
1056}
1057
1058static void dcn201_link_init(struct dc_link *link)
1059{
1060 if (link->ctx->dc_bios->integrated_info)
1061 link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control;
1062}
1063
1064static struct dc_cap_funcs cap_funcs = {
1065 .get_dcc_compression_cap = dcn201_get_dcc_compression_cap,
1066};
1067
1068static struct resource_funcs dcn201_res_pool_funcs = {
1069 .link_init = dcn201_link_init,
1070 .destroy = dcn201_destroy_resource_pool,
1071 .link_enc_create = dcn201_link_encoder_create,
1072 .panel_cntl_create = NULL((void *)0),
1073 .validate_bandwidth = dcn20_validate_bandwidth,
1074 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
1075 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1076 .add_dsc_to_stream_resource = NULL((void *)0),
1077 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1078 .acquire_idle_pipe_for_layer = dcn201_acquire_idle_pipe_for_layer,
1079 .populate_dml_writeback_from_context = dcn201_populate_dml_writeback_from_context,
1080 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1081 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1082 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
1083};
1084
1085static bool_Bool dcn201_resource_construct(
1086 uint8_t num_virtual_links,
1087 struct dc *dc,
1088 struct dcn201_resource_pool *pool)
1089{
1090 int i;
1091 struct dc_context *ctx = dc->ctx;
1092
1093 ctx->dc_bios->regs = &bios_regs;
1094
1095 pool->base.res_cap = &res_cap_dnc201;
1096 pool->base.funcs = &dcn201_res_pool_funcs;
1097
1098 /*************************************************
1099 * Resource + asic cap harcoding *
1100 *************************************************/
1101 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE-1;
1102
1103 pool->base.pipe_count = 4;
1104 pool->base.mpcc_count = 5;
1105 dc->caps.max_downscale_ratio = 200;
1106 dc->caps.i2c_speed_in_khz = 100;
1107 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.5 w/a applied by default*/
1108 dc->caps.max_cursor_size = 256;
1109 dc->caps.min_horizontal_blanking_period = 80;
1110 dc->caps.dmdata_alloc_size = 2048;
1111
1112 dc->caps.max_slave_planes = 1;
1113 dc->caps.max_slave_yuv_planes = 1;
1114 dc->caps.max_slave_rgb_planes = 1;
1115 dc->caps.post_blend_color_processing = true1;
1116 dc->caps.force_dp_tps4_for_cp2520 = true1;
1117 dc->caps.extended_aux_timeout_support = true1;
1118
1119 /* Color pipeline capabilities */
1120 dc->caps.color.dpp.dcn_arch = 1;
1121 dc->caps.color.dpp.input_lut_shared = 0;
1122 dc->caps.color.dpp.icsc = 1;
1123 dc->caps.color.dpp.dgam_ram = 1;
1124 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1125 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1126 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
1127 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
1128 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
1129 dc->caps.color.dpp.post_csc = 0;
1130 dc->caps.color.dpp.gamma_corr = 0;
1131 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
1132
1133 dc->caps.color.dpp.hw_3d_lut = 1;
1134 dc->caps.color.dpp.ogam_ram = 1;
1135 // no OGAM ROM on DCN2
1136 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1137 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1138 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1139 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1140 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1141 dc->caps.color.dpp.ocsc = 0;
1142
1143 dc->caps.color.mpc.gamut_remap = 0;
1144 dc->caps.color.mpc.num_3dluts = 0;
1145 dc->caps.color.mpc.shared_3d_lut = 0;
1146 dc->caps.color.mpc.ogam_ram = 1;
1147 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1148 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1149 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1150 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1151 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1152 dc->caps.color.mpc.ocsc = 1;
1153
1154 dc->debug = debug_defaults_drv;
1155
1156 /*a0 only, remove later*/
1157 dc->work_arounds.no_connect_phy_config = true1;
1158 dc->work_arounds.dedcn20_305_wa = true1;
1159 /*************************************************
1160 * Create resources *
1161 *************************************************/
1162
1163 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1164 dcn201_clock_source_create(ctx, ctx->dc_bios,
1165 CLOCK_SOURCE_COMBO_PHY_PLL0,
1166 &clk_src_regs[0], false0);
1167 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1168 dcn201_clock_source_create(ctx, ctx->dc_bios,
1169 CLOCK_SOURCE_COMBO_PHY_PLL1,
1170 &clk_src_regs[1], false0);
1171
1172 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN201;
1173
1174 /* todo: not reuse phy_pll registers */
1175 pool->base.dp_clock_source =
1176 dcn201_clock_source_create(ctx, ctx->dc_bios,
1177 CLOCK_SOURCE_ID_DP_DTO,
1178 &clk_src_regs[0], true1);
1179
1180 for (i = 0; i < pool->base.clk_src_count; i++) {
1181 if (pool->base.clock_sources[i] == NULL((void *)0)) {
1182 dm_error("DC: failed to create clock sources!\n")__drm_err("DC: failed to create clock sources!\n");
1183 goto create_fail;
1184 }
1185 }
1186
1187 pool->base.dccg = dccg201_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1188 if (pool->base.dccg == NULL((void *)0)) {
1189 dm_error("DC: failed to create dccg!\n")__drm_err("DC: failed to create dccg!\n");
1190 goto create_fail;
1191 }
1192
1193 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1194 dcn201_ip.max_num_dpp = pool->base.pipe_count;
1195 dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201);
1196 {
1197 struct irq_service_init_data init_data;
1198 init_data.ctx = dc->ctx;
1199 pool->base.irqs = dal_irq_service_dcn201_create(&init_data);
1200 if (!pool->base.irqs)
1201 goto create_fail;
1202 }
1203
1204 /* mem input -> ipp -> dpp -> opp -> TG */
1205 for (i = 0; i < pool->base.pipe_count; i++) {
1206 pool->base.hubps[i] = dcn201_hubp_create(ctx, i);
1207 if (pool->base.hubps[i] == NULL((void *)0)) {
1208 dm_error(__drm_err("DC: failed to create memory input!\n")
1209 "DC: failed to create memory input!\n")__drm_err("DC: failed to create memory input!\n");
1210 goto create_fail;
1211 }
1212
1213 pool->base.ipps[i] = dcn201_ipp_create(ctx, i);
1214 if (pool->base.ipps[i] == NULL((void *)0)) {
1215 dm_error(__drm_err("DC: failed to create input pixel processor!\n")
1216 "DC: failed to create input pixel processor!\n")__drm_err("DC: failed to create input pixel processor!\n");
1217 goto create_fail;
1218 }
1219
1220 pool->base.dpps[i] = dcn201_dpp_create(ctx, i);
1221 if (pool->base.dpps[i] == NULL((void *)0)) {
1222 dm_error(__drm_err("DC: failed to create dpps!\n")
1223 "DC: failed to create dpps!\n")__drm_err("DC: failed to create dpps!\n");
1224 goto create_fail;
1225 }
1226 }
1227
1228 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1229 pool->base.opps[i] = dcn201_opp_create(ctx, i);
1230 if (pool->base.opps[i] == NULL((void *)0)) {
1231 dm_error(__drm_err("DC: failed to create output pixel processor!\n")
1232 "DC: failed to create output pixel processor!\n")__drm_err("DC: failed to create output pixel processor!\n");
1233 goto create_fail;
1234 }
1235 }
1236
1237 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1238 pool->base.engines[i] = dcn201_aux_engine_create(ctx, i);
1239 if (pool->base.engines[i] == NULL((void *)0)) {
1240 dm_error(__drm_err("DC:failed to create aux engine!!\n")
1241 "DC:failed to create aux engine!!\n")__drm_err("DC:failed to create aux engine!!\n");
1242 goto create_fail;
1243 }
1244 pool->base.hw_i2cs[i] = dcn201_i2c_hw_create(ctx, i);
1245 if (pool->base.hw_i2cs[i] == NULL((void *)0)) {
1246 dm_error(__drm_err("DC:failed to create hw i2c!!\n")
1247 "DC:failed to create hw i2c!!\n")__drm_err("DC:failed to create hw i2c!!\n");
1248 goto create_fail;
1249 }
1250 pool->base.sw_i2cs[i] = NULL((void *)0);
1251 }
1252
1253 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1254 pool->base.timing_generators[i] = dcn201_timing_generator_create(
1255 ctx, i);
1256 if (pool->base.timing_generators[i] == NULL((void *)0)) {
1257 dm_error("DC: failed to create tg!\n")__drm_err("DC: failed to create tg!\n");
1258 goto create_fail;
1259 }
1260 }
1261
1262 pool->base.timing_generator_count = i;
1263
1264 pool->base.mpc = dcn201_mpc_create(ctx, pool->base.mpcc_count);
1265 if (pool->base.mpc == NULL((void *)0)) {
1266 dm_error("DC: failed to create mpc!\n")__drm_err("DC: failed to create mpc!\n");
1267 goto create_fail;
1268 }
1269
1270 pool->base.hubbub = dcn201_hubbub_create(ctx);
1271 if (pool->base.hubbub == NULL((void *)0)) {
1272 dm_error("DC: failed to create hubbub!\n")__drm_err("DC: failed to create hubbub!\n");
1273 goto create_fail;
1274 }
1275
1276 if (!resource_construct(num_virtual_links, dc, &pool->base,
1277 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) ?
1278 &res_create_funcs : &res_create_maximus_funcs)))
1279 goto create_fail;
1280
1281 dcn201_hw_sequencer_construct(dc);
1282
1283 dc->caps.max_planes = pool->base.pipe_count;
1284
1285 for (i = 0; i < dc->caps.max_planes; ++i)
1286 dc->caps.planes[i] = plane_cap;
1287
1288 dc->cap_funcs = cap_funcs;
1289
1290 return true1;
1291
1292create_fail:
1293
1294 dcn201_resource_destruct(pool);
1295
1296 return false0;
1297}
1298
1299struct resource_pool *dcn201_create_resource_pool(
1300 const struct dc_init_data *init_data,
1301 struct dc *dc)
1302{
1303 struct dcn201_resource_pool *pool =
1304 kzalloc(sizeof(struct dcn201_resource_pool), GFP_ATOMIC0x0002);
1305
1306 if (!pool)
1307 return NULL((void *)0);
1308
1309 if (dcn201_resource_construct(init_data->num_virtual_links, dc, pool))
1310 return &pool->base;
1311
1312 kfree(pool);
1313 return NULL((void *)0);
1314}