File: | dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c |
Warning: | line 1202, column 2 Value stored to 'refcyc_per_req_delivery_pre_l' is never read |
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1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "../display_mode_lib.h" |
27 | #include "../display_mode_vba.h" |
28 | #include "display_rq_dlg_calc_20v2.h" |
29 | |
30 | // Function: dml20v2_rq_dlg_get_rq_params |
31 | // Calculate requestor related parameters that register definition agnostic |
32 | // (i.e. this layer does try to separate real values from register definition) |
33 | // Input: |
34 | // pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.) |
35 | // Output: |
36 | // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.) |
37 | // |
38 | static void dml20v2_rq_dlg_get_rq_params( |
39 | struct display_mode_lib *mode_lib, |
40 | display_rq_params_st * rq_param, |
41 | const display_pipe_source_params_st *pipe_src_param); |
42 | |
43 | // Function: dml20v2_rq_dlg_get_dlg_params |
44 | // Calculate deadline related parameters |
45 | // |
46 | static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, |
47 | const display_e2e_pipe_params_st *e2e_pipe_param, |
48 | const unsigned int num_pipes, |
49 | const unsigned int pipe_idx, |
50 | display_dlg_regs_st *disp_dlg_regs, |
51 | display_ttu_regs_st *disp_ttu_regs, |
52 | const display_rq_dlg_params_st *rq_dlg_param, |
53 | const display_dlg_sys_params_st *dlg_sys_param, |
54 | const bool_Bool cstate_en, |
55 | const bool_Bool pstate_en); |
56 | /* |
57 | * NOTE: |
58 | * This file is gcc-parseable HW gospel, coming straight from HW engineers. |
59 | * |
60 | * It doesn't adhere to Linux kernel style and sometimes will do things in odd |
61 | * ways. Unless there is something clearly wrong with it the code should |
62 | * remain as-is as it provides us with a guarantee from HW that it is correct. |
63 | */ |
64 | |
65 | static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, |
66 | double *refcyc_per_req_delivery_pre_cur, |
67 | double *refcyc_per_req_delivery_cur, |
68 | double refclk_freq_in_mhz, |
69 | double ref_freq_to_pix_freq, |
70 | double hscale_pixel_rate_l, |
71 | double hscl_ratio, |
72 | double vratio_pre_l, |
73 | double vratio_l, |
74 | unsigned int cur_width, |
75 | enum cursor_bpp cur_bpp); |
76 | |
77 | #include "../dml_inline_defs.h" |
78 | |
79 | static unsigned int get_bytes_per_element(enum source_format_class source_format, bool_Bool is_chroma) |
80 | { |
81 | unsigned int ret_val = 0; |
82 | |
83 | if (source_format == dm_444_16) { |
84 | if (!is_chroma) |
85 | ret_val = 2; |
86 | } else if (source_format == dm_444_32) { |
87 | if (!is_chroma) |
88 | ret_val = 4; |
89 | } else if (source_format == dm_444_64) { |
90 | if (!is_chroma) |
91 | ret_val = 8; |
92 | } else if (source_format == dm_420_8) { |
93 | if (is_chroma) |
94 | ret_val = 2; |
95 | else |
96 | ret_val = 1; |
97 | } else if (source_format == dm_420_10) { |
98 | if (is_chroma) |
99 | ret_val = 4; |
100 | else |
101 | ret_val = 2; |
102 | } else if (source_format == dm_444_8) { |
103 | ret_val = 1; |
104 | } |
105 | return ret_val; |
106 | } |
107 | |
108 | static bool_Bool is_dual_plane(enum source_format_class source_format) |
109 | { |
110 | bool_Bool ret_val = false0; |
111 | |
112 | if ((source_format == dm_420_8) || (source_format == dm_420_10)) |
113 | ret_val = true1; |
114 | |
115 | return ret_val; |
116 | } |
117 | |
118 | static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, |
119 | double refclk_freq_in_mhz, |
120 | double pclk_freq_in_mhz, |
121 | bool_Bool odm_combine, |
122 | unsigned int recout_width, |
123 | unsigned int hactive, |
124 | double vratio, |
125 | double hscale_pixel_rate, |
126 | unsigned int delivery_width, |
127 | unsigned int req_per_swath_ub) |
128 | { |
129 | double refcyc_per_delivery = 0.0; |
130 | |
131 | if (vratio <= 1.0) { |
132 | if (odm_combine) |
133 | refcyc_per_delivery = (double) refclk_freq_in_mhz |
134 | * dml_min((double) recout_width, (double) hactive / 2.0) |
135 | / pclk_freq_in_mhz / (double) req_per_swath_ub; |
136 | else |
137 | refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width |
138 | / pclk_freq_in_mhz / (double) req_per_swath_ub; |
139 | } else { |
140 | refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width |
141 | / (double) hscale_pixel_rate / (double) req_per_swath_ub; |
142 | } |
143 | |
144 | dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz){do { } while(0); }; |
145 | dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz){do { } while(0); }; |
146 | dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width){do { } while(0); }; |
147 | dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio){do { } while(0); }; |
148 | dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub){do { } while(0); }; |
149 | dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery){do { } while(0); }; |
150 | |
151 | return refcyc_per_delivery; |
152 | |
153 | } |
154 | |
155 | static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) |
156 | { |
157 | if (tile_size == dm_256k_tile) |
158 | return (256 * 1024); |
159 | else if (tile_size == dm_64k_tile) |
160 | return (64 * 1024); |
161 | else |
162 | return (4 * 1024); |
163 | } |
164 | |
165 | static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, |
166 | display_data_rq_regs_st *rq_regs, |
167 | const display_data_rq_sizing_params_st *rq_sizing) |
168 | { |
169 | dml_print("DML_DLG: %s: rq_sizing param\n", __func__){do { } while(0); }; |
170 | print__data_rq_sizing_params_st(mode_lib, rq_sizing); |
171 | |
172 | rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; |
173 | |
174 | if (rq_sizing->min_chunk_bytes == 0) |
175 | rq_regs->min_chunk_size = 0; |
176 | else |
177 | rq_regs->min_chunk_size = dml_log2(rq_sizing->min_chunk_bytes) - 8 + 1; |
178 | |
179 | rq_regs->meta_chunk_size = dml_log2(rq_sizing->meta_chunk_bytes) - 10; |
180 | if (rq_sizing->min_meta_chunk_bytes == 0) |
181 | rq_regs->min_meta_chunk_size = 0; |
182 | else |
183 | rq_regs->min_meta_chunk_size = dml_log2(rq_sizing->min_meta_chunk_bytes) - 6 + 1; |
184 | |
185 | rq_regs->dpte_group_size = dml_log2(rq_sizing->dpte_group_bytes) - 6; |
186 | rq_regs->mpte_group_size = dml_log2(rq_sizing->mpte_group_bytes) - 6; |
187 | } |
188 | |
189 | static void extract_rq_regs(struct display_mode_lib *mode_lib, |
190 | display_rq_regs_st *rq_regs, |
191 | const display_rq_params_st *rq_param) |
192 | { |
193 | unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; |
194 | unsigned int detile_buf_plane1_addr = 0; |
195 | |
196 | extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), &rq_param->sizing.rq_l); |
197 | |
198 | rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_l.dpte_row_height), |
199 | 1) - 3; |
200 | |
201 | if (rq_param->yuv420) { |
202 | extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), &rq_param->sizing.rq_c); |
203 | rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param->dlg.rq_c.dpte_row_height), |
204 | 1) - 3; |
205 | } |
206 | |
207 | rq_regs->rq_regs_l.swath_height = dml_log2(rq_param->dlg.rq_l.swath_height); |
208 | rq_regs->rq_regs_c.swath_height = dml_log2(rq_param->dlg.rq_c.swath_height); |
209 | |
210 | // TODO: take the max between luma, chroma chunk size? |
211 | // okay for now, as we are setting chunk_bytes to 8kb anyways |
212 | if (rq_param->sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb |
213 | rq_regs->drq_expansion_mode = 0; |
214 | } else { |
215 | rq_regs->drq_expansion_mode = 2; |
216 | } |
217 | rq_regs->prq_expansion_mode = 1; |
218 | rq_regs->mrq_expansion_mode = 1; |
219 | rq_regs->crq_expansion_mode = 1; |
220 | |
221 | if (rq_param->yuv420) { |
222 | if ((double) rq_param->misc.rq_l.stored_swath_bytes |
223 | / (double) rq_param->misc.rq_c.stored_swath_bytes <= 1.5) { |
224 | detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma |
225 | } else { |
226 | detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), |
227 | 256, |
228 | 0) / 64.0; // 2/3 to chroma |
229 | } |
230 | } |
231 | rq_regs->plane1_base_address = detile_buf_plane1_addr; |
232 | } |
233 | |
234 | static void handle_det_buf_split(struct display_mode_lib *mode_lib, |
235 | display_rq_params_st *rq_param, |
236 | const display_pipe_source_params_st *pipe_src_param) |
237 | { |
238 | unsigned int total_swath_bytes = 0; |
239 | unsigned int swath_bytes_l = 0; |
240 | unsigned int swath_bytes_c = 0; |
241 | unsigned int full_swath_bytes_packed_l = 0; |
242 | unsigned int full_swath_bytes_packed_c = 0; |
243 | bool_Bool req128_l = false0; |
244 | bool_Bool req128_c = false0; |
245 | bool_Bool surf_linear = (pipe_src_param->sw_mode == dm_sw_linear); |
246 | bool_Bool surf_vert = (pipe_src_param->source_scan == dm_vert); |
247 | unsigned int log2_swath_height_l = 0; |
248 | unsigned int log2_swath_height_c = 0; |
249 | unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; |
250 | |
251 | full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; |
252 | full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; |
253 | |
254 | if (rq_param->yuv420_10bpc) { |
255 | full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3, |
256 | 256, |
257 | 1) + 256; |
258 | full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3, |
259 | 256, |
260 | 1) + 256; |
261 | } |
262 | |
263 | if (rq_param->yuv420) { |
264 | total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; |
265 | |
266 | if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request |
267 | req128_l = false0; |
268 | req128_c = false0; |
269 | swath_bytes_l = full_swath_bytes_packed_l; |
270 | swath_bytes_c = full_swath_bytes_packed_c; |
271 | } else { //128b request (for luma only for yuv420 8bpc) |
272 | req128_l = true1; |
273 | req128_c = false0; |
274 | swath_bytes_l = full_swath_bytes_packed_l / 2; |
275 | swath_bytes_c = full_swath_bytes_packed_c; |
276 | } |
277 | // Note: assumption, the config that pass in will fit into |
278 | // the detiled buffer. |
279 | } else { |
280 | total_swath_bytes = 2 * full_swath_bytes_packed_l; |
281 | |
282 | if (total_swath_bytes <= detile_buf_size_in_bytes) |
283 | req128_l = false0; |
284 | else |
285 | req128_l = true1; |
286 | |
287 | swath_bytes_l = total_swath_bytes; |
288 | swath_bytes_c = 0; |
289 | } |
290 | rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; |
291 | rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; |
292 | |
293 | if (surf_linear) { |
294 | log2_swath_height_l = 0; |
295 | log2_swath_height_c = 0; |
296 | } else { |
297 | unsigned int swath_height_l; |
298 | unsigned int swath_height_c; |
299 | |
300 | if (!surf_vert) { |
301 | swath_height_l = rq_param->misc.rq_l.blk256_height; |
302 | swath_height_c = rq_param->misc.rq_c.blk256_height; |
303 | } else { |
304 | swath_height_l = rq_param->misc.rq_l.blk256_width; |
305 | swath_height_c = rq_param->misc.rq_c.blk256_width; |
306 | } |
307 | |
308 | if (swath_height_l > 0) |
309 | log2_swath_height_l = dml_log2(swath_height_l); |
310 | |
311 | if (req128_l && log2_swath_height_l > 0) |
312 | log2_swath_height_l -= 1; |
313 | |
314 | if (swath_height_c > 0) |
315 | log2_swath_height_c = dml_log2(swath_height_c); |
316 | |
317 | if (req128_c && log2_swath_height_c > 0) |
318 | log2_swath_height_c -= 1; |
319 | } |
320 | |
321 | rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; |
322 | rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; |
323 | |
324 | dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l){do { } while(0); }; |
325 | dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c){do { } while(0); }; |
326 | dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",{do { } while(0); } |
327 | __func__,{do { } while(0); } |
328 | full_swath_bytes_packed_l){do { } while(0); }; |
329 | dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",{do { } while(0); } |
330 | __func__,{do { } while(0); } |
331 | full_swath_bytes_packed_c){do { } while(0); }; |
332 | } |
333 | |
334 | static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, |
335 | display_data_rq_dlg_params_st *rq_dlg_param, |
336 | display_data_rq_misc_params_st *rq_misc_param, |
337 | display_data_rq_sizing_params_st *rq_sizing_param, |
338 | unsigned int vp_width, |
339 | unsigned int vp_height, |
340 | unsigned int data_pitch, |
341 | unsigned int meta_pitch, |
342 | unsigned int source_format, |
343 | unsigned int tiling, |
344 | unsigned int macro_tile_size, |
345 | unsigned int source_scan, |
346 | unsigned int is_chroma) |
347 | { |
348 | bool_Bool surf_linear = (tiling == dm_sw_linear); |
349 | bool_Bool surf_vert = (source_scan == dm_vert); |
350 | |
351 | unsigned int bytes_per_element; |
352 | unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format), |
353 | false0); |
354 | unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format), |
355 | true1); |
356 | |
357 | unsigned int blk256_width = 0; |
358 | unsigned int blk256_height = 0; |
359 | |
360 | unsigned int blk256_width_y = 0; |
361 | unsigned int blk256_height_y = 0; |
362 | unsigned int blk256_width_c = 0; |
363 | unsigned int blk256_height_c = 0; |
364 | unsigned int log2_bytes_per_element; |
365 | unsigned int log2_blk256_width; |
366 | unsigned int log2_blk256_height; |
367 | unsigned int blk_bytes; |
368 | unsigned int log2_blk_bytes; |
369 | unsigned int log2_blk_height; |
370 | unsigned int log2_blk_width; |
371 | unsigned int log2_meta_req_bytes; |
372 | unsigned int log2_meta_req_height; |
373 | unsigned int log2_meta_req_width; |
374 | unsigned int meta_req_width; |
375 | unsigned int meta_req_height; |
376 | unsigned int log2_meta_row_height; |
377 | unsigned int meta_row_width_ub; |
378 | unsigned int log2_meta_chunk_bytes; |
379 | unsigned int log2_meta_chunk_height; |
380 | |
381 | //full sized meta chunk width in unit of data elements |
382 | unsigned int log2_meta_chunk_width; |
383 | unsigned int log2_min_meta_chunk_bytes; |
384 | unsigned int min_meta_chunk_width; |
385 | unsigned int meta_chunk_width; |
386 | unsigned int meta_chunk_per_row_int; |
387 | unsigned int meta_row_remainder; |
388 | unsigned int meta_chunk_threshold; |
389 | unsigned int meta_blk_bytes; |
390 | unsigned int meta_blk_height; |
391 | unsigned int meta_blk_width; |
392 | unsigned int meta_surface_bytes; |
393 | unsigned int vmpg_bytes; |
394 | unsigned int meta_pte_req_per_frame_ub; |
395 | unsigned int meta_pte_bytes_per_frame_ub; |
396 | const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); |
397 | const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; |
398 | const unsigned int pde_proc_buffer_size_64k_reqs = |
399 | mode_lib->ip.pde_proc_buffer_size_64k_reqs; |
400 | |
401 | unsigned int log2_vmpg_height = 0; |
402 | unsigned int log2_vmpg_width = 0; |
403 | unsigned int log2_dpte_req_height_ptes = 0; |
404 | unsigned int log2_dpte_req_height = 0; |
405 | unsigned int log2_dpte_req_width = 0; |
406 | unsigned int log2_dpte_row_height_linear = 0; |
407 | unsigned int log2_dpte_row_height = 0; |
408 | unsigned int log2_dpte_group_width = 0; |
409 | unsigned int dpte_row_width_ub = 0; |
410 | unsigned int dpte_req_height = 0; |
411 | unsigned int dpte_req_width = 0; |
412 | unsigned int dpte_group_width = 0; |
413 | unsigned int log2_dpte_group_bytes = 0; |
414 | unsigned int log2_dpte_group_length = 0; |
415 | unsigned int pde_buf_entries; |
416 | bool_Bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10); |
417 | |
418 | Calculate256BBlockSizes((enum source_format_class)(source_format), |
419 | (enum dm_swizzle_mode)(tiling), |
420 | bytes_per_element_y, |
421 | bytes_per_element_c, |
422 | &blk256_height_y, |
423 | &blk256_height_c, |
424 | &blk256_width_y, |
425 | &blk256_width_c); |
426 | |
427 | if (!is_chroma) { |
428 | blk256_width = blk256_width_y; |
429 | blk256_height = blk256_height_y; |
430 | bytes_per_element = bytes_per_element_y; |
431 | } else { |
432 | blk256_width = blk256_width_c; |
433 | blk256_height = blk256_height_c; |
434 | bytes_per_element = bytes_per_element_c; |
435 | } |
436 | |
437 | log2_bytes_per_element = dml_log2(bytes_per_element); |
438 | |
439 | dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear){do { } while(0); }; |
440 | dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert){do { } while(0); }; |
441 | dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width){do { } while(0); }; |
442 | dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height){do { } while(0); }; |
443 | |
444 | log2_blk256_width = dml_log2((double) blk256_width); |
445 | log2_blk256_height = dml_log2((double) blk256_height); |
446 | blk_bytes = surf_linear ? |
447 | 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); |
448 | log2_blk_bytes = dml_log2((double) blk_bytes); |
449 | log2_blk_height = 0; |
450 | log2_blk_width = 0; |
451 | |
452 | // remember log rule |
453 | // "+" in log is multiply |
454 | // "-" in log is divide |
455 | // "/2" is like square root |
456 | // blk is vertical biased |
457 | if (tiling != dm_sw_linear) |
458 | log2_blk_height = log2_blk256_height |
459 | + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); |
460 | else |
461 | log2_blk_height = 0; // blk height of 1 |
462 | |
463 | log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; |
464 | |
465 | if (!surf_vert) { |
466 | rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) |
467 | + blk256_width; |
468 | rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; |
469 | } else { |
470 | rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1) |
471 | + blk256_height; |
472 | rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; |
473 | } |
474 | |
475 | if (!surf_vert) |
476 | rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height |
477 | * bytes_per_element; |
478 | else |
479 | rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width |
480 | * bytes_per_element; |
481 | |
482 | rq_misc_param->blk256_height = blk256_height; |
483 | rq_misc_param->blk256_width = blk256_width; |
484 | |
485 | // ------- |
486 | // meta |
487 | // ------- |
488 | log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element |
489 | |
490 | // each 64b meta request for dcn is 8x8 meta elements and |
491 | // a meta element covers one 256b block of the data surface. |
492 | log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 |
493 | log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element |
494 | - log2_meta_req_height; |
495 | meta_req_width = 1 << log2_meta_req_width; |
496 | meta_req_height = 1 << log2_meta_req_height; |
497 | log2_meta_row_height = 0; |
498 | meta_row_width_ub = 0; |
499 | |
500 | // the dimensions of a meta row are meta_row_width x meta_row_height in elements. |
501 | // calculate upper bound of the meta_row_width |
502 | if (!surf_vert) { |
503 | log2_meta_row_height = log2_meta_req_height; |
504 | meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) |
505 | + meta_req_width; |
506 | rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; |
507 | } else { |
508 | log2_meta_row_height = log2_meta_req_width; |
509 | meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) |
510 | + meta_req_height; |
511 | rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; |
512 | } |
513 | rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; |
514 | |
515 | rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; |
516 | |
517 | log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); |
518 | log2_meta_chunk_height = log2_meta_row_height; |
519 | |
520 | //full sized meta chunk width in unit of data elements |
521 | log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element |
522 | - log2_meta_chunk_height; |
523 | log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); |
524 | min_meta_chunk_width = 1 |
525 | << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element |
526 | - log2_meta_chunk_height); |
527 | meta_chunk_width = 1 << log2_meta_chunk_width; |
528 | meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); |
529 | meta_row_remainder = meta_row_width_ub % meta_chunk_width; |
530 | meta_chunk_threshold = 0; |
531 | meta_blk_bytes = 4096; |
532 | meta_blk_height = blk256_height * 64; |
533 | meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; |
534 | meta_surface_bytes = meta_pitch |
535 | * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) |
536 | * bytes_per_element / 256; |
537 | vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; |
538 | meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, |
539 | 8 * vmpg_bytes, |
540 | 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); |
541 | meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request |
542 | rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; |
543 | |
544 | dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height){do { } while(0); }; |
545 | dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width){do { } while(0); }; |
546 | dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes){do { } while(0); }; |
547 | dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n",{do { } while(0); } |
548 | __func__,{do { } while(0); } |
549 | meta_pte_req_per_frame_ub){do { } while(0); }; |
550 | dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",{do { } while(0); } |
551 | __func__,{do { } while(0); } |
552 | meta_pte_bytes_per_frame_ub){do { } while(0); }; |
553 | |
554 | if (!surf_vert) |
555 | meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; |
556 | else |
557 | meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; |
558 | |
559 | if (meta_row_remainder <= meta_chunk_threshold) |
560 | rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; |
561 | else |
562 | rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; |
563 | |
564 | // ------ |
565 | // dpte |
566 | // ------ |
567 | if (surf_linear) { |
568 | log2_vmpg_height = 0; // one line high |
569 | } else { |
570 | log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; |
571 | } |
572 | log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; |
573 | |
574 | // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. |
575 | if (surf_linear) { //one 64B PTE request returns 8 PTEs |
576 | log2_dpte_req_height_ptes = 0; |
577 | log2_dpte_req_width = log2_vmpg_width + 3; |
578 | log2_dpte_req_height = 0; |
579 | } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size |
580 | //one 64B req gives 8x1 PTEs for 4KB tile |
581 | log2_dpte_req_height_ptes = 0; |
582 | log2_dpte_req_width = log2_blk_width + 3; |
583 | log2_dpte_req_height = log2_blk_height + 0; |
584 | } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB |
585 | //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB |
586 | log2_dpte_req_height_ptes = 4; |
587 | log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width |
588 | log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height |
589 | } else { //64KB page size and must 64KB tile block |
590 | //one 64B req gives 8x1 PTEs for 64KB tile |
591 | log2_dpte_req_height_ptes = 0; |
592 | log2_dpte_req_width = log2_blk_width + 3; |
593 | log2_dpte_req_height = log2_blk_height + 0; |
594 | } |
595 | |
596 | // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height |
597 | // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent |
598 | // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) |
599 | //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; |
600 | //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; |
601 | dpte_req_height = 1 << log2_dpte_req_height; |
602 | dpte_req_width = 1 << log2_dpte_req_width; |
603 | |
604 | // calculate pitch dpte row buffer can hold |
605 | // round the result down to a power of two. |
606 | pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; |
607 | if (surf_linear) { |
608 | unsigned int dpte_row_height; |
609 | |
610 | log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries |
611 | / bytes_per_element, |
612 | dpte_buf_in_pte_reqs |
613 | * dpte_req_width) |
614 | / data_pitch), |
615 | 1); |
616 | |
617 | ASSERT(log2_dpte_row_height_linear >= 3)do { if (({ static int __warned; int __ret = !!(!(log2_dpte_row_height_linear >= 3)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(log2_dpte_row_height_linear >= 3)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 617); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
618 | |
619 | if (log2_dpte_row_height_linear > 7) |
620 | log2_dpte_row_height_linear = 7; |
621 | |
622 | log2_dpte_row_height = log2_dpte_row_height_linear; |
623 | // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. |
624 | // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. |
625 | dpte_row_height = 1 << log2_dpte_row_height; |
626 | dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, |
627 | dpte_req_width, |
628 | 1) + dpte_req_width; |
629 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; |
630 | } else { |
631 | // the upper bound of the dpte_row_width without dependency on viewport position follows. |
632 | // for tiled mode, row height is the same as req height and row store up to vp size upper bound |
633 | if (!surf_vert) { |
634 | log2_dpte_row_height = log2_dpte_req_height; |
635 | dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) |
636 | + dpte_req_width; |
637 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; |
638 | } else { |
639 | log2_dpte_row_height = |
640 | (log2_blk_width < log2_dpte_req_width) ? |
641 | log2_blk_width : log2_dpte_req_width; |
642 | dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) |
643 | + dpte_req_height; |
644 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; |
645 | } |
646 | } |
647 | if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB |
648 | rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request |
649 | else |
650 | rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request |
651 | |
652 | rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; |
653 | |
654 | // the dpte_group_bytes is reduced for the specific case of vertical |
655 | // access of a tile surface that has dpte request of 8x1 ptes. |
656 | if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group |
657 | rq_sizing_param->dpte_group_bytes = 512; |
658 | else |
659 | //full size |
660 | rq_sizing_param->dpte_group_bytes = 2048; |
661 | |
662 | //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. |
663 | log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); |
664 | log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests |
665 | |
666 | // full sized data pte group width in elements |
667 | if (!surf_vert) |
668 | log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; |
669 | else |
670 | log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; |
671 | |
672 | //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B |
673 | if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB |
674 | log2_dpte_group_width = log2_dpte_group_width - 1; |
675 | |
676 | dpte_group_width = 1 << log2_dpte_group_width; |
677 | |
678 | // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, |
679 | // the upper bound for the dpte groups per row is as follows. |
680 | rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, |
681 | 1); |
682 | } |
683 | |
684 | static void get_surf_rq_param(struct display_mode_lib *mode_lib, |
685 | display_data_rq_sizing_params_st *rq_sizing_param, |
686 | display_data_rq_dlg_params_st *rq_dlg_param, |
687 | display_data_rq_misc_params_st *rq_misc_param, |
688 | const display_pipe_source_params_st *pipe_src_param, |
689 | bool_Bool is_chroma) |
690 | { |
691 | bool_Bool mode_422 = false0; |
692 | unsigned int vp_width = 0; |
693 | unsigned int vp_height = 0; |
694 | unsigned int data_pitch = 0; |
695 | unsigned int meta_pitch = 0; |
696 | unsigned int ppe = mode_422 ? 2 : 1; |
697 | |
698 | // TODO check if ppe apply for both luma and chroma in 422 case |
699 | if (is_chroma) { |
700 | vp_width = pipe_src_param->viewport_width_c / ppe; |
701 | vp_height = pipe_src_param->viewport_height_c; |
702 | data_pitch = pipe_src_param->data_pitch_c; |
703 | meta_pitch = pipe_src_param->meta_pitch_c; |
704 | } else { |
705 | vp_width = pipe_src_param->viewport_width / ppe; |
706 | vp_height = pipe_src_param->viewport_height; |
707 | data_pitch = pipe_src_param->data_pitch; |
708 | meta_pitch = pipe_src_param->meta_pitch; |
709 | } |
710 | |
711 | rq_sizing_param->chunk_bytes = 8192; |
712 | |
713 | if (rq_sizing_param->chunk_bytes == 64 * 1024) |
714 | rq_sizing_param->min_chunk_bytes = 0; |
715 | else |
716 | rq_sizing_param->min_chunk_bytes = 1024; |
717 | |
718 | rq_sizing_param->meta_chunk_bytes = 2048; |
719 | rq_sizing_param->min_meta_chunk_bytes = 256; |
720 | |
721 | rq_sizing_param->mpte_group_bytes = 2048; |
722 | |
723 | get_meta_and_pte_attr(mode_lib, |
724 | rq_dlg_param, |
725 | rq_misc_param, |
726 | rq_sizing_param, |
727 | vp_width, |
728 | vp_height, |
729 | data_pitch, |
730 | meta_pitch, |
731 | pipe_src_param->source_format, |
732 | pipe_src_param->sw_mode, |
733 | pipe_src_param->macro_tile_size, |
734 | pipe_src_param->source_scan, |
735 | is_chroma); |
736 | } |
737 | |
738 | static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, |
739 | display_rq_params_st *rq_param, |
740 | const display_pipe_source_params_st *pipe_src_param) |
741 | { |
742 | // get param for luma surface |
743 | rq_param->yuv420 = pipe_src_param->source_format == dm_420_8 |
744 | || pipe_src_param->source_format == dm_420_10; |
745 | rq_param->yuv420_10bpc = pipe_src_param->source_format == dm_420_10; |
746 | |
747 | get_surf_rq_param(mode_lib, |
748 | &(rq_param->sizing.rq_l), |
749 | &(rq_param->dlg.rq_l), |
750 | &(rq_param->misc.rq_l), |
751 | pipe_src_param, |
752 | 0); |
753 | |
754 | if (is_dual_plane((enum source_format_class)(pipe_src_param->source_format))) { |
755 | // get param for chroma surface |
756 | get_surf_rq_param(mode_lib, |
757 | &(rq_param->sizing.rq_c), |
758 | &(rq_param->dlg.rq_c), |
759 | &(rq_param->misc.rq_c), |
760 | pipe_src_param, |
761 | 1); |
762 | } |
763 | |
764 | // calculate how to split the det buffer space between luma and chroma |
765 | handle_det_buf_split(mode_lib, rq_param, pipe_src_param); |
766 | print__rq_params_st(mode_lib, rq_param); |
767 | } |
768 | |
769 | void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, |
770 | display_rq_regs_st *rq_regs, |
771 | const display_pipe_params_st *pipe_param) |
772 | { |
773 | display_rq_params_st rq_param = {0}; |
774 | |
775 | memset(rq_regs, 0, sizeof(*rq_regs))__builtin_memset((rq_regs), (0), (sizeof(*rq_regs))); |
776 | dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, &pipe_param->src); |
777 | extract_rq_regs(mode_lib, rq_regs, &rq_param); |
778 | |
779 | print__rq_regs_st(mode_lib, rq_regs); |
780 | } |
781 | |
782 | // Note: currently taken in as is. |
783 | // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. |
784 | static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, |
785 | const display_e2e_pipe_params_st *e2e_pipe_param, |
786 | const unsigned int num_pipes, |
787 | const unsigned int pipe_idx, |
788 | display_dlg_regs_st *disp_dlg_regs, |
789 | display_ttu_regs_st *disp_ttu_regs, |
790 | const display_rq_dlg_params_st *rq_dlg_param, |
791 | const display_dlg_sys_params_st *dlg_sys_param, |
792 | const bool_Bool cstate_en, |
793 | const bool_Bool pstate_en) |
794 | { |
795 | const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; |
796 | const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; |
797 | const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; |
798 | const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; |
799 | const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; |
800 | const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; |
801 | |
802 | // ------------------------- |
803 | // Section 1.15.2.1: OTG dependent Params |
804 | // ------------------------- |
805 | // Timing |
806 | unsigned int htotal = dst->htotal; |
807 | // unsigned int hblank_start = dst.hblank_start; // TODO: Remove |
808 | unsigned int hblank_end = dst->hblank_end; |
809 | unsigned int vblank_start = dst->vblank_start; |
810 | unsigned int vblank_end = dst->vblank_end; |
811 | unsigned int min_vblank = mode_lib->ip.min_vblank_lines; |
812 | |
813 | double dppclk_freq_in_mhz = clks->dppclk_mhz; |
814 | double dispclk_freq_in_mhz = clks->dispclk_mhz; |
815 | double refclk_freq_in_mhz = clks->refclk_mhz; |
816 | double pclk_freq_in_mhz = dst->pixel_rate_mhz; |
817 | bool_Bool interlaced = dst->interlaced; |
818 | |
819 | double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; |
820 | |
821 | double min_dcfclk_mhz; |
822 | double t_calc_us; |
823 | double min_ttu_vblank; |
824 | |
825 | double min_dst_y_ttu_vblank; |
826 | unsigned int dlg_vblank_start; |
827 | bool_Bool dual_plane; |
828 | bool_Bool mode_422; |
829 | unsigned int access_dir; |
830 | unsigned int vp_height_l; |
831 | unsigned int vp_width_l; |
832 | unsigned int vp_height_c; |
833 | unsigned int vp_width_c; |
834 | |
835 | // Scaling |
836 | unsigned int htaps_l; |
837 | unsigned int htaps_c; |
838 | double hratio_l; |
839 | double hratio_c; |
840 | double vratio_l; |
841 | double vratio_c; |
842 | bool_Bool scl_enable; |
843 | |
844 | double line_time_in_us; |
845 | // double vinit_l; |
846 | // double vinit_c; |
847 | // double vinit_bot_l; |
848 | // double vinit_bot_c; |
849 | |
850 | // unsigned int swath_height_l; |
851 | unsigned int swath_width_ub_l; |
852 | // unsigned int dpte_bytes_per_row_ub_l; |
853 | unsigned int dpte_groups_per_row_ub_l; |
854 | // unsigned int meta_pte_bytes_per_frame_ub_l; |
855 | // unsigned int meta_bytes_per_row_ub_l; |
856 | |
857 | // unsigned int swath_height_c; |
858 | unsigned int swath_width_ub_c; |
859 | // unsigned int dpte_bytes_per_row_ub_c; |
860 | unsigned int dpte_groups_per_row_ub_c; |
861 | |
862 | unsigned int meta_chunks_per_row_ub_l; |
863 | unsigned int meta_chunks_per_row_ub_c; |
864 | unsigned int vupdate_offset; |
865 | unsigned int vupdate_width; |
866 | unsigned int vready_offset; |
867 | |
868 | unsigned int dppclk_delay_subtotal; |
869 | unsigned int dispclk_delay_subtotal; |
870 | unsigned int pixel_rate_delay_subtotal; |
871 | |
872 | unsigned int vstartup_start; |
873 | unsigned int dst_x_after_scaler; |
874 | unsigned int dst_y_after_scaler; |
875 | double line_wait; |
876 | double dst_y_prefetch; |
877 | double dst_y_per_vm_vblank; |
878 | double dst_y_per_row_vblank; |
879 | double dst_y_per_vm_flip; |
880 | double dst_y_per_row_flip; |
881 | double min_dst_y_per_vm_vblank; |
882 | double min_dst_y_per_row_vblank; |
883 | double lsw; |
884 | double vratio_pre_l; |
885 | double vratio_pre_c; |
886 | unsigned int req_per_swath_ub_l; |
887 | unsigned int req_per_swath_ub_c; |
888 | unsigned int meta_row_height_l; |
889 | unsigned int meta_row_height_c; |
890 | unsigned int swath_width_pixels_ub_l; |
891 | unsigned int swath_width_pixels_ub_c; |
892 | unsigned int scaler_rec_in_width_l; |
893 | unsigned int scaler_rec_in_width_c; |
894 | unsigned int dpte_row_height_l; |
895 | unsigned int dpte_row_height_c; |
896 | double hscale_pixel_rate_l; |
897 | double hscale_pixel_rate_c; |
898 | double min_hratio_fact_l; |
899 | double min_hratio_fact_c; |
900 | double refcyc_per_line_delivery_pre_l; |
901 | double refcyc_per_line_delivery_pre_c; |
902 | double refcyc_per_line_delivery_l; |
903 | double refcyc_per_line_delivery_c; |
904 | |
905 | double refcyc_per_req_delivery_pre_l; |
906 | double refcyc_per_req_delivery_pre_c; |
907 | double refcyc_per_req_delivery_l; |
908 | double refcyc_per_req_delivery_c; |
909 | |
910 | unsigned int full_recout_width; |
911 | double refcyc_per_req_delivery_pre_cur0; |
912 | double refcyc_per_req_delivery_cur0; |
913 | double refcyc_per_req_delivery_pre_cur1; |
914 | double refcyc_per_req_delivery_cur1; |
915 | |
916 | memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs))__builtin_memset((disp_dlg_regs), (0), (sizeof(*disp_dlg_regs ))); |
917 | memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs))__builtin_memset((disp_ttu_regs), (0), (sizeof(*disp_ttu_regs ))); |
918 | |
919 | dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en){do { } while(0); }; |
920 | dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en){do { } while(0); }; |
921 | |
922 | dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz){do { } while(0); }; |
923 | dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz){do { } while(0); }; |
924 | dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz){do { } while(0); }; |
925 | dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz){do { } while(0); }; |
926 | dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced){do { } while(0); }; |
927 | ASSERT(ref_freq_to_pix_freq < 4.0)do { if (({ static int __warned; int __ret = !!(!(ref_freq_to_pix_freq < 4.0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(ref_freq_to_pix_freq < 4.0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 927); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
928 | |
929 | disp_dlg_regs->ref_freq_to_pix_freq = |
930 | (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); |
931 | disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal |
932 | * dml_pow(2, 8)); |
933 | disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits |
934 | disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end |
935 | * (double) ref_freq_to_pix_freq); |
936 | ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 936); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
937 | |
938 | min_dcfclk_mhz = dlg_sys_param->deepsleep_dcfclk_mhz; |
939 | t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); |
940 | min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
941 | |
942 | min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; |
943 | dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; |
944 | |
945 | disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start |
946 | + min_dst_y_ttu_vblank) * dml_pow(2, 2)); |
947 | ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)) ); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 947); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
948 | |
949 | dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n",{do { } while(0); } |
950 | __func__,{do { } while(0); } |
951 | min_dcfclk_mhz){do { } while(0); }; |
952 | dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n",{do { } while(0); } |
953 | __func__,{do { } while(0); } |
954 | min_ttu_vblank){do { } while(0); }; |
955 | dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n",{do { } while(0); } |
956 | __func__,{do { } while(0); } |
957 | min_dst_y_ttu_vblank){do { } while(0); }; |
958 | dml_print("DML_DLG: %s: t_calc_us = %3.2f\n",{do { } while(0); } |
959 | __func__,{do { } while(0); } |
960 | t_calc_us){do { } while(0); }; |
961 | dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",{do { } while(0); } |
962 | __func__,{do { } while(0); } |
963 | disp_dlg_regs->min_dst_y_next_start){do { } while(0); }; |
964 | dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n",{do { } while(0); } |
965 | __func__,{do { } while(0); } |
966 | ref_freq_to_pix_freq){do { } while(0); }; |
967 | |
968 | // ------------------------- |
969 | // Section 1.15.2.2: Prefetch, Active and TTU |
970 | // ------------------------- |
971 | // Prefetch Calc |
972 | // Source |
973 | // dcc_en = src.dcc; |
974 | dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); |
975 | mode_422 = false0; // TODO |
976 | access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed |
977 | // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); |
978 | // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); |
979 | vp_height_l = src->viewport_height; |
980 | vp_width_l = src->viewport_width; |
981 | vp_height_c = src->viewport_height_c; |
982 | vp_width_c = src->viewport_width_c; |
983 | |
984 | // Scaling |
985 | htaps_l = taps->htaps; |
986 | htaps_c = taps->htaps_c; |
987 | hratio_l = scl->hscl_ratio; |
988 | hratio_c = scl->hscl_ratio_c; |
989 | vratio_l = scl->vscl_ratio; |
990 | vratio_c = scl->vscl_ratio_c; |
991 | scl_enable = scl->scl_enable; |
992 | |
993 | line_time_in_us = (htotal / pclk_freq_in_mhz); |
994 | // vinit_l = scl.vinit; |
995 | // vinit_c = scl.vinit_c; |
996 | // vinit_bot_l = scl.vinit_bot; |
997 | // vinit_bot_c = scl.vinit_bot_c; |
998 | |
999 | // unsigned int swath_height_l = rq_dlg_param->rq_l.swath_height; |
1000 | swath_width_ub_l = rq_dlg_param->rq_l.swath_width_ub; |
1001 | // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param->rq_l.dpte_bytes_per_row_ub; |
1002 | dpte_groups_per_row_ub_l = rq_dlg_param->rq_l.dpte_groups_per_row_ub; |
1003 | // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param->rq_l.meta_pte_bytes_per_frame_ub; |
1004 | // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param->rq_l.meta_bytes_per_row_ub; |
1005 | |
1006 | // unsigned int swath_height_c = rq_dlg_param->rq_c.swath_height; |
1007 | swath_width_ub_c = rq_dlg_param->rq_c.swath_width_ub; |
1008 | // dpte_bytes_per_row_ub_c = rq_dlg_param->rq_c.dpte_bytes_per_row_ub; |
1009 | dpte_groups_per_row_ub_c = rq_dlg_param->rq_c.dpte_groups_per_row_ub; |
1010 | |
1011 | meta_chunks_per_row_ub_l = rq_dlg_param->rq_l.meta_chunks_per_row_ub; |
1012 | meta_chunks_per_row_ub_c = rq_dlg_param->rq_c.meta_chunks_per_row_ub; |
1013 | vupdate_offset = dst->vupdate_offset; |
1014 | vupdate_width = dst->vupdate_width; |
1015 | vready_offset = dst->vready_offset; |
1016 | |
1017 | dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; |
1018 | dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; |
1019 | |
1020 | if (scl_enable) |
1021 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; |
1022 | else |
1023 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; |
1024 | |
1025 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter |
1026 | + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; |
1027 | |
1028 | if (dout->dsc_enable) { |
1029 | double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
1030 | |
1031 | dispclk_delay_subtotal += dsc_delay; |
1032 | } |
1033 | |
1034 | pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz |
1035 | + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; |
1036 | |
1037 | vstartup_start = dst->vstartup_start; |
1038 | if (interlaced) { |
1039 | if (vstartup_start / 2.0 |
1040 | - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal |
1041 | <= vblank_end / 2.0) |
1042 | disp_dlg_regs->vready_after_vcount0 = 1; |
1043 | else |
1044 | disp_dlg_regs->vready_after_vcount0 = 0; |
1045 | } else { |
1046 | if (vstartup_start |
1047 | - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal |
1048 | <= vblank_end) |
1049 | disp_dlg_regs->vready_after_vcount0 = 1; |
1050 | else |
1051 | disp_dlg_regs->vready_after_vcount0 = 0; |
1052 | } |
1053 | |
1054 | // TODO: Where is this coming from? |
1055 | if (interlaced) |
1056 | vstartup_start = vstartup_start / 2; |
1057 | |
1058 | // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? |
1059 | if (vstartup_start >= min_vblank) { |
1060 | dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",{do { } while(0); } |
1061 | __func__,{do { } while(0); } |
1062 | vblank_start,{do { } while(0); } |
1063 | vblank_end){do { } while(0); }; |
1064 | dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",{do { } while(0); } |
1065 | __func__,{do { } while(0); } |
1066 | vstartup_start,{do { } while(0); } |
1067 | min_vblank){do { } while(0); }; |
1068 | min_vblank = vstartup_start + 1; |
1069 | dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",{do { } while(0); } |
1070 | __func__,{do { } while(0); } |
1071 | vstartup_start,{do { } while(0); } |
1072 | min_vblank){do { } while(0); }; |
1073 | } |
1074 | |
1075 | dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
1076 | dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
1077 | |
1078 | dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal){do { } while(0); }; |
1079 | dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n",{do { } while(0); } |
1080 | __func__,{do { } while(0); } |
1081 | pixel_rate_delay_subtotal){do { } while(0); }; |
1082 | dml_print("DML_DLG: %s: dst_x_after_scaler = %d\n",{do { } while(0); } |
1083 | __func__,{do { } while(0); } |
1084 | dst_x_after_scaler){do { } while(0); }; |
1085 | dml_print("DML_DLG: %s: dst_y_after_scaler = %d\n",{do { } while(0); } |
1086 | __func__,{do { } while(0); } |
1087 | dst_y_after_scaler){do { } while(0); }; |
1088 | |
1089 | // Lwait |
1090 | line_wait = mode_lib->soc.urgent_latency_us; |
1091 | if (cstate_en) |
1092 | line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); |
1093 | if (pstate_en) |
1094 | line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us |
1095 | + mode_lib->soc.urgent_latency_us, |
1096 | line_wait); |
1097 | line_wait = line_wait / line_time_in_us; |
1098 | |
1099 | dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
1100 | dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch){do { } while(0); }; |
1101 | |
1102 | dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, |
1103 | e2e_pipe_param, |
1104 | num_pipes, |
1105 | pipe_idx); |
1106 | dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, |
1107 | e2e_pipe_param, |
1108 | num_pipes, |
1109 | pipe_idx); |
1110 | dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
1111 | dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
1112 | |
1113 | min_dst_y_per_vm_vblank = 8.0; |
1114 | min_dst_y_per_row_vblank = 16.0; |
1115 | |
1116 | // magic! |
1117 | if (htotal <= 75) { |
1118 | min_vblank = 300; |
1119 | min_dst_y_per_vm_vblank = 100.0; |
1120 | min_dst_y_per_row_vblank = 100.0; |
1121 | } |
1122 | |
1123 | dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank){do { } while(0); }; |
1124 | dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank){do { } while(0); }; |
1125 | |
1126 | ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank)do { if (({ static int __warned; int __ret = !!(!(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1126); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1127 | ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank)do { if (({ static int __warned; int __ret = !!(!(dst_y_per_row_vblank < min_dst_y_per_row_vblank)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dst_y_per_row_vblank < min_dst_y_per_row_vblank)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1127); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1128 | |
1129 | ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))do { if (({ static int __warned; int __ret = !!(!(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1129); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1130 | lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); |
1131 | |
1132 | dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw){do { } while(0); }; |
1133 | |
1134 | vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
1135 | vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); |
1136 | |
1137 | dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l){do { } while(0); }; |
1138 | dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c){do { } while(0); }; |
1139 | |
1140 | // Active |
1141 | req_per_swath_ub_l = rq_dlg_param->rq_l.req_per_swath_ub; |
1142 | req_per_swath_ub_c = rq_dlg_param->rq_c.req_per_swath_ub; |
1143 | meta_row_height_l = rq_dlg_param->rq_l.meta_row_height; |
1144 | meta_row_height_c = rq_dlg_param->rq_c.meta_row_height; |
1145 | swath_width_pixels_ub_l = 0; |
1146 | swath_width_pixels_ub_c = 0; |
1147 | scaler_rec_in_width_l = 0; |
1148 | scaler_rec_in_width_c = 0; |
1149 | dpte_row_height_l = rq_dlg_param->rq_l.dpte_row_height; |
1150 | dpte_row_height_c = rq_dlg_param->rq_c.dpte_row_height; |
1151 | |
1152 | if (mode_422) { |
1153 | swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element |
1154 | swath_width_pixels_ub_c = swath_width_ub_c * 2; |
1155 | } else { |
1156 | swath_width_pixels_ub_l = swath_width_ub_l * 1; |
1157 | swath_width_pixels_ub_c = swath_width_ub_c * 1; |
1158 | } |
1159 | |
1160 | hscale_pixel_rate_l = 0.; |
1161 | hscale_pixel_rate_c = 0.; |
1162 | min_hratio_fact_l = 1.0; |
1163 | min_hratio_fact_c = 1.0; |
1164 | |
1165 | if (htaps_l <= 1) |
1166 | min_hratio_fact_l = 2.0; |
1167 | else if (htaps_l <= 6) { |
1168 | if ((hratio_l * 2.0) > 4.0) |
1169 | min_hratio_fact_l = 4.0; |
1170 | else |
1171 | min_hratio_fact_l = hratio_l * 2.0; |
1172 | } else { |
1173 | if (hratio_l > 4.0) |
1174 | min_hratio_fact_l = 4.0; |
1175 | else |
1176 | min_hratio_fact_l = hratio_l; |
1177 | } |
1178 | |
1179 | hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; |
1180 | |
1181 | if (htaps_c <= 1) |
1182 | min_hratio_fact_c = 2.0; |
1183 | else if (htaps_c <= 6) { |
1184 | if ((hratio_c * 2.0) > 4.0) |
1185 | min_hratio_fact_c = 4.0; |
1186 | else |
1187 | min_hratio_fact_c = hratio_c * 2.0; |
1188 | } else { |
1189 | if (hratio_c > 4.0) |
1190 | min_hratio_fact_c = 4.0; |
1191 | else |
1192 | min_hratio_fact_c = hratio_c; |
1193 | } |
1194 | |
1195 | hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; |
1196 | |
1197 | refcyc_per_line_delivery_pre_l = 0.; |
1198 | refcyc_per_line_delivery_pre_c = 0.; |
1199 | refcyc_per_line_delivery_l = 0.; |
1200 | refcyc_per_line_delivery_c = 0.; |
1201 | |
1202 | refcyc_per_req_delivery_pre_l = 0.; |
Value stored to 'refcyc_per_req_delivery_pre_l' is never read | |
1203 | refcyc_per_req_delivery_pre_c = 0.; |
1204 | refcyc_per_req_delivery_l = 0.; |
1205 | refcyc_per_req_delivery_c = 0.; |
1206 | |
1207 | full_recout_width = 0; |
1208 | // In ODM |
1209 | if (src->is_hsplit) { |
1210 | // This "hack" is only allowed (and valid) for MPC combine. In ODM |
1211 | // combine, you MUST specify the full_recout_width...according to Oswin |
1212 | if (dst->full_recout_width == 0 && !dst->odm_combine) { |
1213 | dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",{do { } while(0); } |
1214 | __func__){do { } while(0); }; |
1215 | full_recout_width = dst->recout_width * 2; // assume half split for dcn1 |
1216 | } else |
1217 | full_recout_width = dst->full_recout_width; |
1218 | } else |
1219 | full_recout_width = dst->recout_width; |
1220 | |
1221 | // As of DCN2, mpc_combine and odm_combine are mutually exclusive |
1222 | refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, |
1223 | refclk_freq_in_mhz, |
1224 | pclk_freq_in_mhz, |
1225 | dst->odm_combine, |
1226 | full_recout_width, |
1227 | dst->hactive, |
1228 | vratio_pre_l, |
1229 | hscale_pixel_rate_l, |
1230 | swath_width_pixels_ub_l, |
1231 | 1); // per line |
1232 | |
1233 | refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, |
1234 | refclk_freq_in_mhz, |
1235 | pclk_freq_in_mhz, |
1236 | dst->odm_combine, |
1237 | full_recout_width, |
1238 | dst->hactive, |
1239 | vratio_l, |
1240 | hscale_pixel_rate_l, |
1241 | swath_width_pixels_ub_l, |
1242 | 1); // per line |
1243 | |
1244 | dml_print("DML_DLG: %s: full_recout_width = %d\n",{do { } while(0); } |
1245 | __func__,{do { } while(0); } |
1246 | full_recout_width){do { } while(0); }; |
1247 | dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n",{do { } while(0); } |
1248 | __func__,{do { } while(0); } |
1249 | hscale_pixel_rate_l){do { } while(0); }; |
1250 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",{do { } while(0); } |
1251 | __func__,{do { } while(0); } |
1252 | refcyc_per_line_delivery_pre_l){do { } while(0); }; |
1253 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n",{do { } while(0); } |
1254 | __func__,{do { } while(0); } |
1255 | refcyc_per_line_delivery_l){do { } while(0); }; |
1256 | |
1257 | if (dual_plane) { |
1258 | refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, |
1259 | refclk_freq_in_mhz, |
1260 | pclk_freq_in_mhz, |
1261 | dst->odm_combine, |
1262 | full_recout_width, |
1263 | dst->hactive, |
1264 | vratio_pre_c, |
1265 | hscale_pixel_rate_c, |
1266 | swath_width_pixels_ub_c, |
1267 | 1); // per line |
1268 | |
1269 | refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, |
1270 | refclk_freq_in_mhz, |
1271 | pclk_freq_in_mhz, |
1272 | dst->odm_combine, |
1273 | full_recout_width, |
1274 | dst->hactive, |
1275 | vratio_c, |
1276 | hscale_pixel_rate_c, |
1277 | swath_width_pixels_ub_c, |
1278 | 1); // per line |
1279 | |
1280 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",{do { } while(0); } |
1281 | __func__,{do { } while(0); } |
1282 | refcyc_per_line_delivery_pre_c){do { } while(0); }; |
1283 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n",{do { } while(0); } |
1284 | __func__,{do { } while(0); } |
1285 | refcyc_per_line_delivery_c){do { } while(0); }; |
1286 | } |
1287 | |
1288 | // TTU - Luma / Chroma |
1289 | if (access_dir) { // vertical access |
1290 | scaler_rec_in_width_l = vp_height_l; |
1291 | scaler_rec_in_width_c = vp_height_c; |
1292 | } else { |
1293 | scaler_rec_in_width_l = vp_width_l; |
1294 | scaler_rec_in_width_c = vp_width_c; |
1295 | } |
1296 | |
1297 | refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, |
1298 | refclk_freq_in_mhz, |
1299 | pclk_freq_in_mhz, |
1300 | dst->odm_combine, |
1301 | full_recout_width, |
1302 | dst->hactive, |
1303 | vratio_pre_l, |
1304 | hscale_pixel_rate_l, |
1305 | scaler_rec_in_width_l, |
1306 | req_per_swath_ub_l); // per req |
1307 | refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, |
1308 | refclk_freq_in_mhz, |
1309 | pclk_freq_in_mhz, |
1310 | dst->odm_combine, |
1311 | full_recout_width, |
1312 | dst->hactive, |
1313 | vratio_l, |
1314 | hscale_pixel_rate_l, |
1315 | scaler_rec_in_width_l, |
1316 | req_per_swath_ub_l); // per req |
1317 | |
1318 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",{do { } while(0); } |
1319 | __func__,{do { } while(0); } |
1320 | refcyc_per_req_delivery_pre_l){do { } while(0); }; |
1321 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n",{do { } while(0); } |
1322 | __func__,{do { } while(0); } |
1323 | refcyc_per_req_delivery_l){do { } while(0); }; |
1324 | |
1325 | ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1325); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1326 | ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_l < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_l < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1326); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1327 | |
1328 | if (dual_plane) { |
1329 | refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, |
1330 | refclk_freq_in_mhz, |
1331 | pclk_freq_in_mhz, |
1332 | dst->odm_combine, |
1333 | full_recout_width, |
1334 | dst->hactive, |
1335 | vratio_pre_c, |
1336 | hscale_pixel_rate_c, |
1337 | scaler_rec_in_width_c, |
1338 | req_per_swath_ub_c); // per req |
1339 | refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, |
1340 | refclk_freq_in_mhz, |
1341 | pclk_freq_in_mhz, |
1342 | dst->odm_combine, |
1343 | full_recout_width, |
1344 | dst->hactive, |
1345 | vratio_c, |
1346 | hscale_pixel_rate_c, |
1347 | scaler_rec_in_width_c, |
1348 | req_per_swath_ub_c); // per req |
1349 | |
1350 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",{do { } while(0); } |
1351 | __func__,{do { } while(0); } |
1352 | refcyc_per_req_delivery_pre_c){do { } while(0); }; |
1353 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n",{do { } while(0); } |
1354 | __func__,{do { } while(0); } |
1355 | refcyc_per_req_delivery_c){do { } while(0); }; |
1356 | |
1357 | ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1357); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1358 | ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_c < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_c < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1358); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1359 | } |
1360 | |
1361 | // TTU - Cursor |
1362 | refcyc_per_req_delivery_pre_cur0 = 0.0; |
1363 | refcyc_per_req_delivery_cur0 = 0.0; |
1364 | if (src->num_cursors > 0) { |
1365 | calculate_ttu_cursor(mode_lib, |
1366 | &refcyc_per_req_delivery_pre_cur0, |
1367 | &refcyc_per_req_delivery_cur0, |
1368 | refclk_freq_in_mhz, |
1369 | ref_freq_to_pix_freq, |
1370 | hscale_pixel_rate_l, |
1371 | scl->hscl_ratio, |
1372 | vratio_pre_l, |
1373 | vratio_l, |
1374 | src->cur0_src_width, |
1375 | (enum cursor_bpp)(src->cur0_bpp)); |
1376 | } |
1377 | |
1378 | refcyc_per_req_delivery_pre_cur1 = 0.0; |
1379 | refcyc_per_req_delivery_cur1 = 0.0; |
1380 | if (src->num_cursors > 1) { |
1381 | calculate_ttu_cursor(mode_lib, |
1382 | &refcyc_per_req_delivery_pre_cur1, |
1383 | &refcyc_per_req_delivery_cur1, |
1384 | refclk_freq_in_mhz, |
1385 | ref_freq_to_pix_freq, |
1386 | hscale_pixel_rate_l, |
1387 | scl->hscl_ratio, |
1388 | vratio_pre_l, |
1389 | vratio_l, |
1390 | src->cur1_src_width, |
1391 | (enum cursor_bpp)(src->cur1_bpp)); |
1392 | } |
1393 | |
1394 | // TTU - Misc |
1395 | // all hard-coded |
1396 | |
1397 | // Assignment to register structures |
1398 | disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line |
1399 | disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk |
1400 | ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13) )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1400); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1401 | disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); |
1402 | disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); |
1403 | disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); |
1404 | disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); |
1405 | disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); |
1406 | |
1407 | disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); |
1408 | disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); |
1409 | |
1410 | disp_dlg_regs->refcyc_per_pte_group_vblank_l = |
1411 | (unsigned int) (dst_y_per_row_vblank * (double) htotal |
1412 | * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); |
1413 | ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1413); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1414 | |
1415 | if (dual_plane) { |
1416 | disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank |
1417 | * (double) htotal * ref_freq_to_pix_freq |
1418 | / (double) dpte_groups_per_row_ub_c); |
1419 | ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_cdo { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1420); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0) |
1420 | < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1420); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1421 | } |
1422 | |
1423 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = |
1424 | (unsigned int) (dst_y_per_row_vblank * (double) htotal |
1425 | * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); |
1426 | ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1426); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1427 | |
1428 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = |
1429 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now |
1430 | |
1431 | disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal |
1432 | * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; |
1433 | disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal |
1434 | * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; |
1435 | |
1436 | if (dual_plane) { |
1437 | disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip |
1438 | * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; |
1439 | disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip |
1440 | * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; |
1441 | } |
1442 | |
1443 | disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l |
1444 | / (double) vratio_l * dml_pow(2, 2)); |
1445 | ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1445); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1446 | |
1447 | if (dual_plane) { |
1448 | disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c |
1449 | / (double) vratio_c * dml_pow(2, 2)); |
1450 | if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { |
1451 | dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",{do { } while(0); } |
1452 | __func__,{do { } while(0); } |
1453 | disp_dlg_regs->dst_y_per_pte_row_nom_c,{do { } while(0); } |
1454 | (unsigned int) dml_pow(2, 17) - 1){do { } while(0); }; |
1455 | } |
1456 | } |
1457 | |
1458 | disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l |
1459 | / (double) vratio_l * dml_pow(2, 2)); |
1460 | ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1460); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1461 | |
1462 | disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now |
1463 | |
1464 | disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l |
1465 | / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq |
1466 | / (double) dpte_groups_per_row_ub_l); |
1467 | if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) |
1468 | disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; |
1469 | disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l |
1470 | / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq |
1471 | / (double) meta_chunks_per_row_ub_l); |
1472 | if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) |
1473 | disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; |
1474 | |
1475 | if (dual_plane) { |
1476 | disp_dlg_regs->refcyc_per_pte_group_nom_c = |
1477 | (unsigned int) ((double) dpte_row_height_c / (double) vratio_c |
1478 | * (double) htotal * ref_freq_to_pix_freq |
1479 | / (double) dpte_groups_per_row_ub_c); |
1480 | if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) |
1481 | disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; |
1482 | |
1483 | // TODO: Is this the right calculation? Does htotal need to be halved? |
1484 | disp_dlg_regs->refcyc_per_meta_chunk_nom_c = |
1485 | (unsigned int) ((double) meta_row_height_c / (double) vratio_c |
1486 | * (double) htotal * ref_freq_to_pix_freq |
1487 | / (double) meta_chunks_per_row_ub_c); |
1488 | if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) |
1489 | disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; |
1490 | } |
1491 | |
1492 | disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, |
1493 | 1); |
1494 | disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, |
1495 | 1); |
1496 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1496); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1497 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2 , 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1497); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1498 | |
1499 | disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, |
1500 | 1); |
1501 | disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, |
1502 | 1); |
1503 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1503); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1504 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2 , 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1504); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1505 | |
1506 | disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; |
1507 | disp_dlg_regs->dst_y_offset_cur0 = 0; |
1508 | disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; |
1509 | disp_dlg_regs->dst_y_offset_cur1 = 0; |
1510 | |
1511 | disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off |
1512 | |
1513 | disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l |
1514 | * dml_pow(2, 10)); |
1515 | disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l |
1516 | * dml_pow(2, 10)); |
1517 | disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c |
1518 | * dml_pow(2, 10)); |
1519 | disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c |
1520 | * dml_pow(2, 10)); |
1521 | disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = |
1522 | (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); |
1523 | disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 |
1524 | * dml_pow(2, 10)); |
1525 | disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = |
1526 | (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); |
1527 | disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 |
1528 | * dml_pow(2, 10)); |
1529 | disp_ttu_regs->qos_level_low_wm = 0; |
1530 | ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->qos_level_low_wm < dml_pow(2, 14))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1530); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1531 | disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal |
1532 | * ref_freq_to_pix_freq); |
1533 | /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/ |
1534 | |
1535 | disp_ttu_regs->qos_level_flip = 14; |
1536 | disp_ttu_regs->qos_level_fixed_l = 8; |
1537 | disp_ttu_regs->qos_level_fixed_c = 8; |
1538 | disp_ttu_regs->qos_level_fixed_cur0 = 8; |
1539 | disp_ttu_regs->qos_ramp_disable_l = 0; |
1540 | disp_ttu_regs->qos_ramp_disable_c = 0; |
1541 | disp_ttu_regs->qos_ramp_disable_cur0 = 0; |
1542 | |
1543 | disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; |
1544 | ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->min_ttu_vblank < dml_pow(2, 24))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1544); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1545 | |
1546 | print__ttu_regs_st(mode_lib, disp_ttu_regs); |
1547 | print__dlg_regs_st(mode_lib, disp_dlg_regs); |
1548 | } |
1549 | |
1550 | void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, |
1551 | display_dlg_regs_st *dlg_regs, |
1552 | display_ttu_regs_st *ttu_regs, |
1553 | const display_e2e_pipe_params_st *e2e_pipe_param, |
1554 | const unsigned int num_pipes, |
1555 | const unsigned int pipe_idx, |
1556 | const bool_Bool cstate_en, |
1557 | const bool_Bool pstate_en, |
1558 | const bool_Bool vm_en, |
1559 | const bool_Bool ignore_viewport_pos, |
1560 | const bool_Bool immediate_flip_support) |
1561 | { |
1562 | display_rq_params_st rq_param = {0}; |
1563 | display_dlg_sys_params_st dlg_sys_param = {0}; |
1564 | |
1565 | // Get watermark and Tex. |
1566 | dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); |
1567 | dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, |
1568 | e2e_pipe_param, |
1569 | num_pipes); |
1570 | dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); |
1571 | dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); |
1572 | dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); |
1573 | dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); |
1574 | dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, |
1575 | e2e_pipe_param, |
1576 | num_pipes); |
1577 | dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, |
1578 | e2e_pipe_param, |
1579 | num_pipes); |
1580 | |
1581 | print__dlg_sys_params_st(mode_lib, &dlg_sys_param); |
1582 | |
1583 | // system parameter calculation done |
1584 | |
1585 | dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx){do { } while(0); }; |
1586 | dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, &e2e_pipe_param[pipe_idx].pipe.src); |
1587 | dml20v2_rq_dlg_get_dlg_params(mode_lib, |
1588 | e2e_pipe_param, |
1589 | num_pipes, |
1590 | pipe_idx, |
1591 | dlg_regs, |
1592 | ttu_regs, |
1593 | &rq_param.dlg, |
1594 | &dlg_sys_param, |
1595 | cstate_en, |
1596 | pstate_en); |
1597 | dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx){do { } while(0); }; |
1598 | } |
1599 | |
1600 | static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, |
1601 | double *refcyc_per_req_delivery_pre_cur, |
1602 | double *refcyc_per_req_delivery_cur, |
1603 | double refclk_freq_in_mhz, |
1604 | double ref_freq_to_pix_freq, |
1605 | double hscale_pixel_rate_l, |
1606 | double hscl_ratio, |
1607 | double vratio_pre_l, |
1608 | double vratio_l, |
1609 | unsigned int cur_width, |
1610 | enum cursor_bpp cur_bpp) |
1611 | { |
1612 | unsigned int cur_src_width = cur_width; |
1613 | unsigned int cur_req_size = 0; |
1614 | unsigned int cur_req_width = 0; |
1615 | double cur_width_ub = 0.0; |
1616 | double cur_req_per_width = 0.0; |
1617 | double hactive_cur = 0.0; |
1618 | |
1619 | ASSERT(cur_src_width <= 256)do { if (({ static int __warned; int __ret = !!(!(cur_src_width <= 256)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(cur_src_width <= 256)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1619); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1620 | |
1621 | *refcyc_per_req_delivery_pre_cur = 0.0; |
1622 | *refcyc_per_req_delivery_cur = 0.0; |
1623 | if (cur_src_width > 0) { |
1624 | unsigned int cur_bit_per_pixel = 0; |
1625 | |
1626 | if (cur_bpp == dm_cur_2bit) { |
1627 | cur_req_size = 64; // byte |
1628 | cur_bit_per_pixel = 2; |
1629 | } else { // 32bit |
1630 | cur_bit_per_pixel = 32; |
1631 | if (cur_src_width >= 1 && cur_src_width <= 16) |
1632 | cur_req_size = 64; |
1633 | else if (cur_src_width >= 17 && cur_src_width <= 31) |
1634 | cur_req_size = 128; |
1635 | else |
1636 | cur_req_size = 256; |
1637 | } |
1638 | |
1639 | cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); |
1640 | cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) |
1641 | * (double) cur_req_width; |
1642 | cur_req_per_width = cur_width_ub / (double) cur_req_width; |
1643 | hactive_cur = (double) cur_src_width / hscl_ratio; // TODO: oswin to think about what to do for cursor |
1644 | |
1645 | if (vratio_pre_l <= 1.0) { |
1646 | *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq |
1647 | / (double) cur_req_per_width; |
1648 | } else { |
1649 | *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz |
1650 | * (double) cur_src_width / hscale_pixel_rate_l |
1651 | / (double) cur_req_per_width; |
1652 | } |
1653 | |
1654 | ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1654); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1655 | |
1656 | if (vratio_l <= 1.0) { |
1657 | *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq |
1658 | / (double) cur_req_per_width; |
1659 | } else { |
1660 | *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz |
1661 | * (double) cur_src_width / hscale_pixel_rate_l |
1662 | / (double) cur_req_per_width; |
1663 | } |
1664 | |
1665 | dml_print("DML_DLG: %s: cur_req_width = %d\n",{do { } while(0); } |
1666 | __func__,{do { } while(0); } |
1667 | cur_req_width){do { } while(0); }; |
1668 | dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n",{do { } while(0); } |
1669 | __func__,{do { } while(0); } |
1670 | cur_width_ub){do { } while(0); }; |
1671 | dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n",{do { } while(0); } |
1672 | __func__,{do { } while(0); } |
1673 | cur_req_per_width){do { } while(0); }; |
1674 | dml_print("DML_DLG: %s: hactive_cur = %3.2f\n",{do { } while(0); } |
1675 | __func__,{do { } while(0); } |
1676 | hactive_cur){do { } while(0); }; |
1677 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n",{do { } while(0); } |
1678 | __func__,{do { } while(0); } |
1679 | *refcyc_per_req_delivery_pre_cur){do { } while(0); }; |
1680 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n",{do { } while(0); } |
1681 | __func__,{do { } while(0); } |
1682 | *refcyc_per_req_delivery_cur){do { } while(0); }; |
1683 | |
1684 | ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(*refcyc_per_req_delivery_cur < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(*refcyc_per_req_delivery_cur < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c" , 1684); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1685 | } |
1686 | } |