File: | dev/pci/drm/amd/amdgpu/aldebaran.c |
Warning: | line 50, column 24 Value stored to 'adev' during its initialization is never read |
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1 | /* |
2 | * Copyright 2021 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include "aldebaran.h" |
25 | #include "amdgpu_reset.h" |
26 | #include "amdgpu_amdkfd.h" |
27 | #include "amdgpu_dpm.h" |
28 | #include "amdgpu_job.h" |
29 | #include "amdgpu_ring.h" |
30 | #include "amdgpu_ras.h" |
31 | #include "amdgpu_psp.h" |
32 | #include "amdgpu_xgmi.h" |
33 | |
34 | static bool_Bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl) |
35 | { |
36 | struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; |
37 | |
38 | if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)(((13) << 16) | ((0) << 8) | (2)) && |
39 | adev->gmc.xgmi.connected_to_cpu)) |
40 | return true1; |
41 | |
42 | return false0; |
43 | } |
44 | |
45 | static struct amdgpu_reset_handler * |
46 | aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl, |
47 | struct amdgpu_reset_context *reset_context) |
48 | { |
49 | struct amdgpu_reset_handler *handler; |
50 | struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; |
Value stored to 'adev' during its initialization is never read | |
51 | |
52 | if (reset_context->method != AMD_RESET_METHOD_NONE) { |
53 | dev_dbg(adev->dev, "Getting reset handler for method %d\n",do { } while(0) |
54 | reset_context->method)do { } while(0); |
55 | list_for_each_entry(handler, &reset_ctl->reset_handlers,for (handler = ({ const __typeof( ((__typeof(*handler) *)0)-> handler_list ) *__mptr = ((&reset_ctl->reset_handlers) ->next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof (__typeof(*handler), handler_list) );}); &handler->handler_list != (&reset_ctl->reset_handlers); handler = ({ const __typeof ( ((__typeof(*handler) *)0)->handler_list ) *__mptr = (handler ->handler_list.next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof(__typeof(*handler), handler_list) );})) |
56 | handler_list)for (handler = ({ const __typeof( ((__typeof(*handler) *)0)-> handler_list ) *__mptr = ((&reset_ctl->reset_handlers) ->next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof (__typeof(*handler), handler_list) );}); &handler->handler_list != (&reset_ctl->reset_handlers); handler = ({ const __typeof ( ((__typeof(*handler) *)0)->handler_list ) *__mptr = (handler ->handler_list.next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof(__typeof(*handler), handler_list) );})) { |
57 | if (handler->reset_method == reset_context->method) |
58 | return handler; |
59 | } |
60 | } |
61 | |
62 | if (aldebaran_is_mode2_default(reset_ctl)) { |
63 | list_for_each_entry(handler, &reset_ctl->reset_handlers,for (handler = ({ const __typeof( ((__typeof(*handler) *)0)-> handler_list ) *__mptr = ((&reset_ctl->reset_handlers) ->next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof (__typeof(*handler), handler_list) );}); &handler->handler_list != (&reset_ctl->reset_handlers); handler = ({ const __typeof ( ((__typeof(*handler) *)0)->handler_list ) *__mptr = (handler ->handler_list.next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof(__typeof(*handler), handler_list) );})) |
64 | handler_list)for (handler = ({ const __typeof( ((__typeof(*handler) *)0)-> handler_list ) *__mptr = ((&reset_ctl->reset_handlers) ->next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof (__typeof(*handler), handler_list) );}); &handler->handler_list != (&reset_ctl->reset_handlers); handler = ({ const __typeof ( ((__typeof(*handler) *)0)->handler_list ) *__mptr = (handler ->handler_list.next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof(__typeof(*handler), handler_list) );})) { |
65 | if (handler->reset_method == AMD_RESET_METHOD_MODE2) { |
66 | reset_context->method = AMD_RESET_METHOD_MODE2; |
67 | return handler; |
68 | } |
69 | } |
70 | } |
71 | |
72 | dev_dbg(adev->dev, "Reset handler not found!\n")do { } while(0); |
73 | |
74 | return NULL((void *)0); |
75 | } |
76 | |
77 | static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev) |
78 | { |
79 | int r, i; |
80 | |
81 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); |
82 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); |
83 | |
84 | for (i = adev->num_ip_blocks - 1; i >= 0; i--) { |
85 | if (!(adev->ip_blocks[i].version->type == |
86 | AMD_IP_BLOCK_TYPE_GFX || |
87 | adev->ip_blocks[i].version->type == |
88 | AMD_IP_BLOCK_TYPE_SDMA)) |
89 | continue; |
90 | |
91 | r = adev->ip_blocks[i].version->funcs->suspend(adev); |
92 | |
93 | if (r) { |
94 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "suspend of IP block <%s> failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r) |
95 | "suspend of IP block <%s> failed %d\n",printf("drm:pid%d:%s *ERROR* " "suspend of IP block <%s> failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r) |
96 | adev->ip_blocks[i].version->funcs->name, r)printf("drm:pid%d:%s *ERROR* " "suspend of IP block <%s> failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r); |
97 | return r; |
98 | } |
99 | |
100 | adev->ip_blocks[i].status.hw = false0; |
101 | } |
102 | |
103 | return r; |
104 | } |
105 | |
106 | static int |
107 | aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, |
108 | struct amdgpu_reset_context *reset_context) |
109 | { |
110 | int r = 0; |
111 | struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; |
112 | |
113 | dev_dbg(adev->dev, "Aldebaran prepare hw context\n")do { } while(0); |
114 | /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ |
115 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) |
116 | r = aldebaran_mode2_suspend_ip(adev); |
117 | |
118 | return r; |
119 | } |
120 | |
121 | static void aldebaran_async_reset(struct work_struct *work) |
122 | { |
123 | struct amdgpu_reset_handler *handler; |
124 | struct amdgpu_reset_control *reset_ctl = |
125 | container_of(work, struct amdgpu_reset_control, reset_work)({ const __typeof( ((struct amdgpu_reset_control *)0)->reset_work ) *__mptr = (work); (struct amdgpu_reset_control *)( (char * )__mptr - __builtin_offsetof(struct amdgpu_reset_control, reset_work ) );}); |
126 | struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; |
127 | |
128 | list_for_each_entry(handler, &reset_ctl->reset_handlers,for (handler = ({ const __typeof( ((__typeof(*handler) *)0)-> handler_list ) *__mptr = ((&reset_ctl->reset_handlers) ->next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof (__typeof(*handler), handler_list) );}); &handler->handler_list != (&reset_ctl->reset_handlers); handler = ({ const __typeof ( ((__typeof(*handler) *)0)->handler_list ) *__mptr = (handler ->handler_list.next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof(__typeof(*handler), handler_list) );})) |
129 | handler_list)for (handler = ({ const __typeof( ((__typeof(*handler) *)0)-> handler_list ) *__mptr = ((&reset_ctl->reset_handlers) ->next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof (__typeof(*handler), handler_list) );}); &handler->handler_list != (&reset_ctl->reset_handlers); handler = ({ const __typeof ( ((__typeof(*handler) *)0)->handler_list ) *__mptr = (handler ->handler_list.next); (__typeof(*handler) *)( (char *)__mptr - __builtin_offsetof(__typeof(*handler), handler_list) );})) { |
130 | if (handler->reset_method == reset_ctl->active_reset) { |
131 | dev_dbg(adev->dev, "Resetting device\n")do { } while(0); |
132 | handler->do_reset(adev); |
133 | break; |
134 | } |
135 | } |
136 | } |
137 | |
138 | static int aldebaran_mode2_reset(struct amdgpu_device *adev) |
139 | { |
140 | /* disable BM */ |
141 | pci_clear_master(adev->pdev); |
142 | adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev); |
143 | return adev->asic_reset_res; |
144 | } |
145 | |
146 | static int |
147 | aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, |
148 | struct amdgpu_reset_context *reset_context) |
149 | { |
150 | struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; |
151 | struct list_head *reset_device_list = reset_context->reset_device_list; |
152 | struct amdgpu_device *tmp_adev = NULL((void *)0); |
153 | int r = 0; |
154 | |
155 | dev_dbg(adev->dev, "aldebaran perform hw reset\n")do { } while(0); |
156 | |
157 | if (reset_device_list == NULL((void *)0)) |
158 | return -EINVAL22; |
159 | |
160 | if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)(((13) << 16) | ((0) << 8) | (2)) && |
161 | reset_context->hive == NULL((void *)0)) { |
162 | /* Wrong context, return error */ |
163 | return -EINVAL22; |
164 | } |
165 | |
166 | list_for_each_entry(tmp_adev, reset_device_list, reset_list)for (tmp_adev = ({ const __typeof( ((__typeof(*tmp_adev) *)0) ->reset_list ) *__mptr = ((reset_device_list)->next); ( __typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof(__typeof (*tmp_adev), reset_list) );}); &tmp_adev->reset_list != (reset_device_list); tmp_adev = ({ const __typeof( ((__typeof (*tmp_adev) *)0)->reset_list ) *__mptr = (tmp_adev->reset_list .next); (__typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof (__typeof(*tmp_adev), reset_list) );})) { |
167 | mutex_lock(&tmp_adev->reset_cntl->reset_lock)rw_enter_write(&tmp_adev->reset_cntl->reset_lock); |
168 | tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2; |
169 | } |
170 | /* |
171 | * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch |
172 | * them together so that they can be completed asynchronously on multiple nodes |
173 | */ |
174 | list_for_each_entry(tmp_adev, reset_device_list, reset_list)for (tmp_adev = ({ const __typeof( ((__typeof(*tmp_adev) *)0) ->reset_list ) *__mptr = ((reset_device_list)->next); ( __typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof(__typeof (*tmp_adev), reset_list) );}); &tmp_adev->reset_list != (reset_device_list); tmp_adev = ({ const __typeof( ((__typeof (*tmp_adev) *)0)->reset_list ) *__mptr = (tmp_adev->reset_list .next); (__typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof (__typeof(*tmp_adev), reset_list) );})) { |
175 | /* For XGMI run all resets in parallel to speed up the process */ |
176 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
177 | if (!queue_work(system_unbound_wq, |
178 | &tmp_adev->reset_cntl->reset_work)) |
179 | r = -EALREADY37; |
180 | } else |
181 | r = aldebaran_mode2_reset(tmp_adev); |
182 | if (r) { |
183 | dev_err(tmp_adev->dev,printf("drm:pid%d:%s *ERROR* " "ASIC reset failed with error, %d for drm dev, %s" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r, adev_to_drm (tmp_adev)->unique) |
184 | "ASIC reset failed with error, %d for drm dev, %s",printf("drm:pid%d:%s *ERROR* " "ASIC reset failed with error, %d for drm dev, %s" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r, adev_to_drm (tmp_adev)->unique) |
185 | r, adev_to_drm(tmp_adev)->unique)printf("drm:pid%d:%s *ERROR* " "ASIC reset failed with error, %d for drm dev, %s" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r, adev_to_drm (tmp_adev)->unique); |
186 | break; |
187 | } |
188 | } |
189 | |
190 | /* For XGMI wait for all resets to complete before proceed */ |
191 | if (!r) { |
192 | list_for_each_entry(tmp_adev, reset_device_list, reset_list)for (tmp_adev = ({ const __typeof( ((__typeof(*tmp_adev) *)0) ->reset_list ) *__mptr = ((reset_device_list)->next); ( __typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof(__typeof (*tmp_adev), reset_list) );}); &tmp_adev->reset_list != (reset_device_list); tmp_adev = ({ const __typeof( ((__typeof (*tmp_adev) *)0)->reset_list ) *__mptr = (tmp_adev->reset_list .next); (__typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof (__typeof(*tmp_adev), reset_list) );})) { |
193 | if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { |
194 | flush_work(&tmp_adev->reset_cntl->reset_work); |
195 | r = tmp_adev->asic_reset_res; |
196 | if (r) |
197 | break; |
198 | } |
199 | } |
200 | } |
201 | |
202 | list_for_each_entry(tmp_adev, reset_device_list, reset_list)for (tmp_adev = ({ const __typeof( ((__typeof(*tmp_adev) *)0) ->reset_list ) *__mptr = ((reset_device_list)->next); ( __typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof(__typeof (*tmp_adev), reset_list) );}); &tmp_adev->reset_list != (reset_device_list); tmp_adev = ({ const __typeof( ((__typeof (*tmp_adev) *)0)->reset_list ) *__mptr = (tmp_adev->reset_list .next); (__typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof (__typeof(*tmp_adev), reset_list) );})) { |
203 | mutex_unlock(&tmp_adev->reset_cntl->reset_lock)rw_exit_write(&tmp_adev->reset_cntl->reset_lock); |
204 | tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE; |
205 | } |
206 | |
207 | return r; |
208 | } |
209 | |
210 | static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) |
211 | { |
212 | struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM]; |
213 | struct amdgpu_firmware_info *ucode; |
214 | struct amdgpu_ip_block *cmn_block; |
215 | int ucode_count = 0; |
216 | int i, r; |
217 | |
218 | dev_dbg(adev->dev, "Reloading ucodes after reset\n")do { } while(0); |
219 | for (i = 0; i < adev->firmware.max_ucodes; i++) { |
220 | ucode = &adev->firmware.ucode[i]; |
221 | if (!ucode->fw) |
222 | continue; |
223 | switch (ucode->ucode_id) { |
224 | case AMDGPU_UCODE_ID_SDMA0: |
225 | case AMDGPU_UCODE_ID_SDMA1: |
226 | case AMDGPU_UCODE_ID_SDMA2: |
227 | case AMDGPU_UCODE_ID_SDMA3: |
228 | case AMDGPU_UCODE_ID_SDMA4: |
229 | case AMDGPU_UCODE_ID_SDMA5: |
230 | case AMDGPU_UCODE_ID_SDMA6: |
231 | case AMDGPU_UCODE_ID_SDMA7: |
232 | case AMDGPU_UCODE_ID_CP_MEC1: |
233 | case AMDGPU_UCODE_ID_CP_MEC1_JT: |
234 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: |
235 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: |
236 | case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: |
237 | case AMDGPU_UCODE_ID_RLC_G: |
238 | ucode_list[ucode_count++] = ucode; |
239 | break; |
240 | default: |
241 | break; |
242 | } |
243 | } |
244 | |
245 | /* Reinit NBIF block */ |
246 | cmn_block = |
247 | amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON); |
248 | if (unlikely(!cmn_block)__builtin_expect(!!(!cmn_block), 0)) { |
249 | dev_err(adev->dev, "Failed to get BIF handle\n")printf("drm:pid%d:%s *ERROR* " "Failed to get BIF handle\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
250 | return -EINVAL22; |
251 | } |
252 | r = cmn_block->version->funcs->resume(adev); |
253 | if (r) |
254 | return r; |
255 | |
256 | /* Reinit GFXHUB */ |
257 | adev->gfxhub.funcs->init(adev); |
258 | r = adev->gfxhub.funcs->gart_enable(adev); |
259 | if (r) { |
260 | dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n")printf("drm:pid%d:%s *ERROR* " "GFXHUB gart reenable failed after reset\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
261 | return r; |
262 | } |
263 | |
264 | /* Reload GFX firmware */ |
265 | r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count); |
266 | if (r) { |
267 | dev_err(adev->dev, "GFX ucode load failed after reset\n")printf("drm:pid%d:%s *ERROR* " "GFX ucode load failed after reset\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
268 | return r; |
269 | } |
270 | |
271 | /* Resume RLC, FW needs RLC alive to complete reset process */ |
272 | adev->gfx.rlc.funcs->resume(adev); |
273 | |
274 | /* Wait for FW reset event complete */ |
275 | r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0); |
276 | if (r) { |
277 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "Failed to get response from firmware after reset\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
278 | "Failed to get response from firmware after reset\n")printf("drm:pid%d:%s *ERROR* " "Failed to get response from firmware after reset\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
279 | return r; |
280 | } |
281 | |
282 | for (i = 0; i < adev->num_ip_blocks; i++) { |
283 | if (!(adev->ip_blocks[i].version->type == |
284 | AMD_IP_BLOCK_TYPE_GFX || |
285 | adev->ip_blocks[i].version->type == |
286 | AMD_IP_BLOCK_TYPE_SDMA)) |
287 | continue; |
288 | r = adev->ip_blocks[i].version->funcs->resume(adev); |
289 | if (r) { |
290 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "resume of IP block <%s> failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r) |
291 | "resume of IP block <%s> failed %d\n",printf("drm:pid%d:%s *ERROR* " "resume of IP block <%s> failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r) |
292 | adev->ip_blocks[i].version->funcs->name, r)printf("drm:pid%d:%s *ERROR* " "resume of IP block <%s> failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r); |
293 | return r; |
294 | } |
295 | |
296 | adev->ip_blocks[i].status.hw = true1; |
297 | } |
298 | |
299 | for (i = 0; i < adev->num_ip_blocks; i++) { |
300 | if (!(adev->ip_blocks[i].version->type == |
301 | AMD_IP_BLOCK_TYPE_GFX || |
302 | adev->ip_blocks[i].version->type == |
303 | AMD_IP_BLOCK_TYPE_SDMA || |
304 | adev->ip_blocks[i].version->type == |
305 | AMD_IP_BLOCK_TYPE_COMMON)) |
306 | continue; |
307 | |
308 | if (adev->ip_blocks[i].version->funcs->late_init) { |
309 | r = adev->ip_blocks[i].version->funcs->late_init( |
310 | (void *)adev); |
311 | if (r) { |
312 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "late_init of IP block <%s> failed %d after reset\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r) |
313 | "late_init of IP block <%s> failed %d after reset\n",printf("drm:pid%d:%s *ERROR* " "late_init of IP block <%s> failed %d after reset\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r) |
314 | adev->ip_blocks[i].version->funcs->name,printf("drm:pid%d:%s *ERROR* " "late_init of IP block <%s> failed %d after reset\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r) |
315 | r)printf("drm:pid%d:%s *ERROR* " "late_init of IP block <%s> failed %d after reset\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> ip_blocks[i].version->funcs->name, r); |
316 | return r; |
317 | } |
318 | } |
319 | adev->ip_blocks[i].status.late_initialized = true1; |
320 | } |
321 | |
322 | amdgpu_ras_set_error_query_ready(adev, true1); |
323 | |
324 | amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); |
325 | amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); |
326 | |
327 | return r; |
328 | } |
329 | |
330 | static int |
331 | aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, |
332 | struct amdgpu_reset_context *reset_context) |
333 | { |
334 | struct list_head *reset_device_list = reset_context->reset_device_list; |
335 | struct amdgpu_device *tmp_adev = NULL((void *)0); |
336 | int r; |
337 | |
338 | if (reset_device_list == NULL((void *)0)) |
339 | return -EINVAL22; |
340 | |
341 | if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] == |
342 | IP_VERSION(13, 0, 2)(((13) << 16) | ((0) << 8) | (2)) && |
343 | reset_context->hive == NULL((void *)0)) { |
344 | /* Wrong context, return error */ |
345 | return -EINVAL22; |
346 | } |
347 | |
348 | list_for_each_entry(tmp_adev, reset_device_list, reset_list)for (tmp_adev = ({ const __typeof( ((__typeof(*tmp_adev) *)0) ->reset_list ) *__mptr = ((reset_device_list)->next); ( __typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof(__typeof (*tmp_adev), reset_list) );}); &tmp_adev->reset_list != (reset_device_list); tmp_adev = ({ const __typeof( ((__typeof (*tmp_adev) *)0)->reset_list ) *__mptr = (tmp_adev->reset_list .next); (__typeof(*tmp_adev) *)( (char *)__mptr - __builtin_offsetof (__typeof(*tmp_adev), reset_list) );})) { |
349 | dev_info(tmp_adev->dev,do { } while(0) |
350 | "GPU reset succeeded, trying to resume\n")do { } while(0); |
351 | r = aldebaran_mode2_restore_ip(tmp_adev); |
352 | if (r) |
353 | goto end; |
354 | |
355 | /* |
356 | * Add this ASIC as tracked as reset was already |
357 | * complete successfully. |
358 | */ |
359 | amdgpu_register_gpu_instance(tmp_adev); |
360 | |
361 | /* Resume RAS */ |
362 | amdgpu_ras_resume(tmp_adev); |
363 | |
364 | /* Update PSP FW topology after reset */ |
365 | if (reset_context->hive && |
366 | tmp_adev->gmc.xgmi.num_physical_nodes > 1) |
367 | r = amdgpu_xgmi_update_topology(reset_context->hive, |
368 | tmp_adev); |
369 | |
370 | if (!r) { |
371 | amdgpu_irq_gpu_reset_resume_helper(tmp_adev); |
372 | |
373 | r = amdgpu_ib_ring_tests(tmp_adev); |
374 | if (r) { |
375 | dev_err(tmp_adev->dev,printf("drm:pid%d:%s *ERROR* " "ib ring test failed (%d).\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r) |
376 | "ib ring test failed (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "ib ring test failed (%d).\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
377 | r = -EAGAIN35; |
378 | tmp_adev->asic_reset_res = r; |
379 | goto end; |
380 | } |
381 | } |
382 | } |
383 | |
384 | end: |
385 | return r; |
386 | } |
387 | |
388 | static struct amdgpu_reset_handler aldebaran_mode2_handler = { |
389 | .reset_method = AMD_RESET_METHOD_MODE2, |
390 | .prepare_env = NULL((void *)0), |
391 | .prepare_hwcontext = aldebaran_mode2_prepare_hwcontext, |
392 | .perform_reset = aldebaran_mode2_perform_reset, |
393 | .restore_hwcontext = aldebaran_mode2_restore_hwcontext, |
394 | .restore_env = NULL((void *)0), |
395 | .do_reset = aldebaran_mode2_reset, |
396 | }; |
397 | |
398 | int aldebaran_reset_init(struct amdgpu_device *adev) |
399 | { |
400 | struct amdgpu_reset_control *reset_ctl; |
401 | |
402 | reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL(0x0001 | 0x0004)); |
403 | if (!reset_ctl) |
404 | return -ENOMEM12; |
405 | |
406 | reset_ctl->handle = adev; |
407 | reset_ctl->async_reset = aldebaran_async_reset; |
408 | reset_ctl->active_reset = AMD_RESET_METHOD_NONE; |
409 | reset_ctl->get_reset_handler = aldebaran_get_reset_handler; |
410 | |
411 | INIT_LIST_HEAD(&reset_ctl->reset_handlers); |
412 | INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset); |
413 | /* Only mode2 is handled through reset control now */ |
414 | amdgpu_reset_add_handler(reset_ctl, &aldebaran_mode2_handler); |
415 | |
416 | adev->reset_cntl = reset_ctl; |
417 | |
418 | return 0; |
419 | } |
420 | |
421 | int aldebaran_reset_fini(struct amdgpu_device *adev) |
422 | { |
423 | kfree(adev->reset_cntl); |
424 | adev->reset_cntl = NULL((void *)0); |
425 | return 0; |
426 | } |