File: | dev/pci/drm/amd/amdgpu/sdma_v5_2.c |
Warning: | line 773, column 3 Value stored to 'tmp' is never read |
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1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/delay.h> |
25 | #include <linux/firmware.h> |
26 | #include <linux/module.h> |
27 | #include <linux/pci.h> |
28 | |
29 | #include "amdgpu.h" |
30 | #include "amdgpu_ucode.h" |
31 | #include "amdgpu_trace.h" |
32 | |
33 | #include "gc/gc_10_3_0_offset.h" |
34 | #include "gc/gc_10_3_0_sh_mask.h" |
35 | #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" |
36 | #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" |
37 | #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" |
38 | #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" |
39 | |
40 | #include "soc15_common.h" |
41 | #include "soc15.h" |
42 | #include "navi10_sdma_pkt_open.h" |
43 | #include "nbio_v2_3.h" |
44 | #include "sdma_common.h" |
45 | #include "sdma_v5_2.h" |
46 | |
47 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); |
48 | MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); |
49 | MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); |
50 | MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); |
51 | |
52 | MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); |
53 | MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); |
54 | MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin"); |
55 | MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin"); |
56 | |
57 | #define SDMA1_REG_OFFSET0x600 0x600 |
58 | #define SDMA3_REG_OFFSET0x400 0x400 |
59 | #define SDMA0_HYP_DEC_REG_START0x5880 0x5880 |
60 | #define SDMA0_HYP_DEC_REG_END0x5893 0x5893 |
61 | #define SDMA1_HYP_DEC_REG_OFFSET0x20 0x20 |
62 | |
63 | static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); |
64 | static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); |
65 | static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); |
66 | static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); |
67 | |
68 | static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) |
69 | { |
70 | u32 base; |
71 | |
72 | if (internal_offset >= SDMA0_HYP_DEC_REG_START0x5880 && |
73 | internal_offset <= SDMA0_HYP_DEC_REG_END0x5893) { |
74 | base = adev->reg_offset[GC_HWIP][0][1]; |
75 | if (instance != 0) |
76 | internal_offset += SDMA1_HYP_DEC_REG_OFFSET0x20 * instance; |
77 | } else { |
78 | if (instance < 2) { |
79 | base = adev->reg_offset[GC_HWIP][0][0]; |
80 | if (instance == 1) |
81 | internal_offset += SDMA1_REG_OFFSET0x600; |
82 | } else { |
83 | base = adev->reg_offset[GC_HWIP][0][2]; |
84 | if (instance == 3) |
85 | internal_offset += SDMA3_REG_OFFSET0x400; |
86 | } |
87 | } |
88 | |
89 | return base + internal_offset; |
90 | } |
91 | |
92 | /** |
93 | * sdma_v5_2_init_microcode - load ucode images from disk |
94 | * |
95 | * @adev: amdgpu_device pointer |
96 | * |
97 | * Use the firmware interface to load the ucode images into |
98 | * the driver (not loaded into hw). |
99 | * Returns 0 on success, error on failure. |
100 | */ |
101 | |
102 | // emulation only, won't work on real chip |
103 | // navi10 real chip need to use PSP to load firmware |
104 | static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) |
105 | { |
106 | const char *chip_name; |
107 | char fw_name[40]; |
108 | |
109 | DRM_DEBUG("\n")___drm_dbg(((void *)0), DRM_UT_CORE, "\n"); |
110 | |
111 | switch (adev->ip_versions[SDMA0_HWIP][0]) { |
112 | case IP_VERSION(5, 2, 0)(((5) << 16) | ((2) << 8) | (0)): |
113 | chip_name = "sienna_cichlid_sdma"; |
114 | break; |
115 | case IP_VERSION(5, 2, 2)(((5) << 16) | ((2) << 8) | (2)): |
116 | chip_name = "navy_flounder_sdma"; |
117 | break; |
118 | case IP_VERSION(5, 2, 1)(((5) << 16) | ((2) << 8) | (1)): |
119 | chip_name = "vangogh_sdma"; |
120 | break; |
121 | case IP_VERSION(5, 2, 4)(((5) << 16) | ((2) << 8) | (4)): |
122 | chip_name = "dimgrey_cavefish_sdma"; |
123 | break; |
124 | case IP_VERSION(5, 2, 5)(((5) << 16) | ((2) << 8) | (5)): |
125 | chip_name = "beige_goby_sdma"; |
126 | break; |
127 | case IP_VERSION(5, 2, 3)(((5) << 16) | ((2) << 8) | (3)): |
128 | chip_name = "yellow_carp_sdma"; |
129 | break; |
130 | case IP_VERSION(5, 2, 6)(((5) << 16) | ((2) << 8) | (6)): |
131 | chip_name = "sdma_5_2_6"; |
132 | break; |
133 | case IP_VERSION(5, 2, 7)(((5) << 16) | ((2) << 8) | (7)): |
134 | chip_name = "sdma_5_2_7"; |
135 | break; |
136 | default: |
137 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c" , 137); } while (0); |
138 | } |
139 | |
140 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name); |
141 | |
142 | return amdgpu_sdma_init_microcode(adev, fw_name, 0, true1); |
143 | } |
144 | |
145 | static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) |
146 | { |
147 | unsigned ret; |
148 | |
149 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)(((9) & 0x000000FF) << 0)); |
150 | amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)((u32)(ring->cond_exe_gpu_addr))); |
151 | amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)((u32)(((ring->cond_exe_gpu_addr) >> 16) >> 16 ))); |
152 | amdgpu_ring_write(ring, 1); |
153 | ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ |
154 | amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ |
155 | |
156 | return ret; |
157 | } |
158 | |
159 | static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, |
160 | unsigned offset) |
161 | { |
162 | unsigned cur; |
163 | |
164 | BUG_ON(offset > ring->buf_mask)((!(offset > ring->buf_mask)) ? (void)0 : __assert("diagnostic " , "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c", 164, "!(offset > ring->buf_mask)" )); |
165 | BUG_ON(ring->ring[offset] != 0x55aa55aa)((!(ring->ring[offset] != 0x55aa55aa)) ? (void)0 : __assert ("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c" , 165, "!(ring->ring[offset] != 0x55aa55aa)")); |
166 | |
167 | cur = (ring->wptr - 1) & ring->buf_mask; |
168 | if (cur > offset) |
169 | ring->ring[offset] = cur - offset; |
170 | else |
171 | ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; |
172 | } |
173 | |
174 | /** |
175 | * sdma_v5_2_ring_get_rptr - get the current read pointer |
176 | * |
177 | * @ring: amdgpu ring pointer |
178 | * |
179 | * Get the current rptr from the hardware (NAVI10+). |
180 | */ |
181 | static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) |
182 | { |
183 | u64 *rptr; |
184 | |
185 | /* XXX check if swapping is necessary on BE */ |
186 | rptr = (u64 *)ring->rptr_cpu_addr; |
187 | |
188 | DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr)___drm_dbg(((void *)0), DRM_UT_CORE, "rptr before shift == 0x%016llx\n" , *rptr); |
189 | return ((*rptr) >> 2); |
190 | } |
191 | |
192 | /** |
193 | * sdma_v5_2_ring_get_wptr - get the current write pointer |
194 | * |
195 | * @ring: amdgpu ring pointer |
196 | * |
197 | * Get the current wptr from the hardware (NAVI10+). |
198 | */ |
199 | static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) |
200 | { |
201 | struct amdgpu_device *adev = ring->adev; |
202 | u64 wptr; |
203 | |
204 | if (ring->use_doorbell) { |
205 | /* XXX check if swapping is necessary on BE */ |
206 | wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr))({ typeof(*((u64 *)ring->wptr_cpu_addr)) __tmp = *(volatile typeof(*((u64 *)ring->wptr_cpu_addr)) *)&(*((u64 *)ring ->wptr_cpu_addr)); membar_datadep_consumer(); __tmp; }); |
207 | DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr)___drm_dbg(((void *)0), DRM_UT_CORE, "wptr/doorbell before shift == 0x%016llx\n" , wptr); |
208 | } else { |
209 | wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, ring ->me, 0x0086)), 0); |
210 | wptr = wptr << 32; |
211 | wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, ring ->me, 0x0085)), 0); |
212 | DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr)___drm_dbg(((void *)0), DRM_UT_CORE, "wptr before shift [%i] wptr == 0x%016llx\n" , ring->me, wptr); |
213 | } |
214 | |
215 | return wptr >> 2; |
216 | } |
217 | |
218 | /** |
219 | * sdma_v5_2_ring_set_wptr - commit the write pointer |
220 | * |
221 | * @ring: amdgpu ring pointer |
222 | * |
223 | * Write the wptr back to the hardware (NAVI10+). |
224 | */ |
225 | static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) |
226 | { |
227 | struct amdgpu_device *adev = ring->adev; |
228 | |
229 | DRM_DEBUG("Setting write pointer\n")___drm_dbg(((void *)0), DRM_UT_CORE, "Setting write pointer\n" ); |
230 | if (ring->use_doorbell) { |
231 | DRM_DEBUG("Using doorbell -- "___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x " "lower_32_bits(ring->wptr << 2) == 0x%08x " "upper_32_bits(ring->wptr << 2) == 0x%08x\n" , ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32 )(((ring->wptr << 2) >> 16) >> 16))) |
232 | "wptr_offs == 0x%08x "___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x " "lower_32_bits(ring->wptr << 2) == 0x%08x " "upper_32_bits(ring->wptr << 2) == 0x%08x\n" , ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32 )(((ring->wptr << 2) >> 16) >> 16))) |
233 | "lower_32_bits(ring->wptr << 2) == 0x%08x "___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x " "lower_32_bits(ring->wptr << 2) == 0x%08x " "upper_32_bits(ring->wptr << 2) == 0x%08x\n" , ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32 )(((ring->wptr << 2) >> 16) >> 16))) |
234 | "upper_32_bits(ring->wptr << 2) == 0x%08x\n",___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x " "lower_32_bits(ring->wptr << 2) == 0x%08x " "upper_32_bits(ring->wptr << 2) == 0x%08x\n" , ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32 )(((ring->wptr << 2) >> 16) >> 16))) |
235 | ring->wptr_offs,___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x " "lower_32_bits(ring->wptr << 2) == 0x%08x " "upper_32_bits(ring->wptr << 2) == 0x%08x\n" , ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32 )(((ring->wptr << 2) >> 16) >> 16))) |
236 | lower_32_bits(ring->wptr << 2),___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x " "lower_32_bits(ring->wptr << 2) == 0x%08x " "upper_32_bits(ring->wptr << 2) == 0x%08x\n" , ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32 )(((ring->wptr << 2) >> 16) >> 16))) |
237 | upper_32_bits(ring->wptr << 2))___drm_dbg(((void *)0), DRM_UT_CORE, "Using doorbell -- " "wptr_offs == 0x%08x " "lower_32_bits(ring->wptr << 2) == 0x%08x " "upper_32_bits(ring->wptr << 2) == 0x%08x\n" , ring->wptr_offs, ((u32)(ring->wptr << 2)), ((u32 )(((ring->wptr << 2) >> 16) >> 16))); |
238 | /* XXX check if swapping is necessary on BE */ |
239 | atomic64_set((atomic64_t *)ring->wptr_cpu_addr,({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = (( ring->wptr << 2)); *(volatile typeof(*((atomic64_t * )ring->wptr_cpu_addr)) *)&(*((atomic64_t *)ring->wptr_cpu_addr )) = __tmp; __tmp; }) |
240 | ring->wptr << 2)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = (( ring->wptr << 2)); *(volatile typeof(*((atomic64_t * )ring->wptr_cpu_addr)) *)&(*((atomic64_t *)ring->wptr_cpu_addr )) = __tmp; __tmp; }); |
241 | DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",___drm_dbg(((void *)0), DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n" , ring->doorbell_index, ring->wptr << 2) |
242 | ring->doorbell_index, ring->wptr << 2)___drm_dbg(((void *)0), DRM_UT_CORE, "calling WDOORBELL64(0x%08x, 0x%016llx)\n" , ring->doorbell_index, ring->wptr << 2); |
243 | WDOORBELL64(ring->doorbell_index, ring->wptr << 2)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring-> wptr << 2)); |
244 | } else { |
245 | DRM_DEBUG("Not using doorbell -- "___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n" , ring->me, ((u32)(ring->wptr << 2)), ring->me , ((u32)(((ring->wptr << 2) >> 16) >> 16 ))) |
246 | "mmSDMA%i_GFX_RB_WPTR == 0x%08x "___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n" , ring->me, ((u32)(ring->wptr << 2)), ring->me , ((u32)(((ring->wptr << 2) >> 16) >> 16 ))) |
247 | "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n" , ring->me, ((u32)(ring->wptr << 2)), ring->me , ((u32)(((ring->wptr << 2) >> 16) >> 16 ))) |
248 | ring->me,___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n" , ring->me, ((u32)(ring->wptr << 2)), ring->me , ((u32)(((ring->wptr << 2) >> 16) >> 16 ))) |
249 | lower_32_bits(ring->wptr << 2),___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n" , ring->me, ((u32)(ring->wptr << 2)), ring->me , ((u32)(((ring->wptr << 2) >> 16) >> 16 ))) |
250 | ring->me,___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n" , ring->me, ((u32)(ring->wptr << 2)), ring->me , ((u32)(((ring->wptr << 2) >> 16) >> 16 ))) |
251 | upper_32_bits(ring->wptr << 2))___drm_dbg(((void *)0), DRM_UT_CORE, "Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x " "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n" , ring->me, ((u32)(ring->wptr << 2)), ring->me , ((u32)(((ring->wptr << 2) >> 16) >> 16 ))); |
252 | WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, ring ->me, 0x0085)), (((u32)(ring->wptr << 2))), 0) |
253 | lower_32_bits(ring->wptr << 2))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, ring ->me, 0x0085)), (((u32)(ring->wptr << 2))), 0); |
254 | WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, ring ->me, 0x0086)), (((u32)(((ring->wptr << 2) >> 16) >> 16))), 0) |
255 | upper_32_bits(ring->wptr << 2))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, ring ->me, 0x0086)), (((u32)(((ring->wptr << 2) >> 16) >> 16))), 0); |
256 | } |
257 | } |
258 | |
259 | static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) |
260 | { |
261 | struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); |
262 | int i; |
263 | |
264 | for (i = 0; i < count; i++) |
265 | if (sdma && sdma->burst_nop && (i == 0)) |
266 | amdgpu_ring_write(ring, ring->funcs->nop | |
267 | SDMA_PKT_NOP_HEADER_COUNT(count - 1)(((count - 1) & 0x00003FFF) << 16)); |
268 | else |
269 | amdgpu_ring_write(ring, ring->funcs->nop); |
270 | } |
271 | |
272 | /** |
273 | * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine |
274 | * |
275 | * @ring: amdgpu ring pointer |
276 | * @job: job to retrieve vmid from |
277 | * @ib: IB object to schedule |
278 | * @flags: unused |
279 | * |
280 | * Schedule an IB in the DMA ring. |
281 | */ |
282 | static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, |
283 | struct amdgpu_job *job, |
284 | struct amdgpu_ib *ib, |
285 | uint32_t flags) |
286 | { |
287 | unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0); |
288 | uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); |
289 | |
290 | /* An IB packet must end on a 8 DW boundary--the next dword |
291 | * must be on a 8-dword boundary. Our IB packet below is 6 |
292 | * dwords long, thus add x number of NOPs, such that, in |
293 | * modular arithmetic, |
294 | * wptr + 6 + x = 8k, k >= 0, which in C is, |
295 | * (wptr + 6 + x) % 8 = 0. |
296 | * The expression below, is a solution of x. |
297 | */ |
298 | sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)((u32)(ring->wptr))) & 7); |
299 | |
300 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT)(((4) & 0x000000FF) << 0) | |
301 | SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)(((vmid & 0xf) & 0x0000000F) << 16)); |
302 | /* base must be 32 byte aligned */ |
303 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)) & 0xffffffe0); |
304 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16))); |
305 | amdgpu_ring_write(ring, ib->length_dw); |
306 | amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)((u32)(csa_mc_addr))); |
307 | amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)((u32)(((csa_mc_addr) >> 16) >> 16))); |
308 | } |
309 | |
310 | /** |
311 | * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse |
312 | * |
313 | * @ring: amdgpu ring pointer |
314 | * |
315 | * flush the IB by graphics cache rinse. |
316 | */ |
317 | static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) |
318 | { |
319 | uint32_t gcr_cntl = SDMA_GCR_GL2_INV(1 << 14) | SDMA_GCR_GL2_WB(1 << 15) | |
320 | SDMA_GCR_GLM_INV(1 << 5) | SDMA_GCR_GL1_INV(1 << 9) | |
321 | SDMA_GCR_GLV_INV(1 << 8) | SDMA_GCR_GLK_INV(1 << 7) | |
322 | SDMA_GCR_GLI_INV(1)(((1) & 0x3) << 0); |
323 | |
324 | /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ |
325 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)(((17) & 0x000000FF) << 0)); |
326 | amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)(((0) & 0x01FFFFFF) << 7)); |
327 | amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl)(((gcr_cntl) & 0x0000FFFF) << 16) | |
328 | SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)(((0) & 0x0000FFFF) << 0)); |
329 | amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0)(((0) & 0x01FFFFFF) << 7) | |
330 | SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)(((gcr_cntl >> 16) & 0x00000007) << 0)); |
331 | amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0)(((0) & 0x0000FFFF) << 0) | |
332 | SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)(((0) & 0x0000000F) << 24)); |
333 | } |
334 | |
335 | /** |
336 | * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
337 | * |
338 | * @ring: amdgpu ring pointer |
339 | * |
340 | * Emit an hdp flush packet on the requested DMA ring. |
341 | */ |
342 | static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
343 | { |
344 | struct amdgpu_device *adev = ring->adev; |
345 | u32 ref_and_mask = 0; |
346 | const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; |
347 | |
348 | ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; |
349 | |
350 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) | |
351 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1)(((1) & 0x00000001) << 26) | |
352 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28)); /* == */ |
353 | amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); |
354 | amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); |
355 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ |
356 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ |
357 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) | |
358 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0)); /* retry count, poll interval */ |
359 | } |
360 | |
361 | /** |
362 | * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring |
363 | * |
364 | * @ring: amdgpu ring pointer |
365 | * @addr: address |
366 | * @seq: sequence number |
367 | * @flags: fence related flags |
368 | * |
369 | * Add a DMA fence packet to the ring to write |
370 | * the fence seq number and DMA trap packet to generate |
371 | * an interrupt if needed. |
372 | */ |
373 | static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, |
374 | unsigned flags) |
375 | { |
376 | bool_Bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT(1 << 0); |
377 | /* write the fence */ |
378 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0) | |
379 | SDMA_PKT_FENCE_HEADER_MTYPE(0x3)(((0x3) & 0x00000007) << 16)); /* Ucached(UC) */ |
380 | /* zero in first two bits */ |
381 | BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c" , 381, "!(addr & 0x3)")); |
382 | amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr))); |
383 | amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16))); |
384 | amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq))); |
385 | |
386 | /* optionally write high bits as well */ |
387 | if (write64bit) { |
388 | addr += 4; |
389 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0) | |
390 | SDMA_PKT_FENCE_HEADER_MTYPE(0x3)(((0x3) & 0x00000007) << 16)); |
391 | /* zero in first two bits */ |
392 | BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v5_2.c" , 392, "!(addr & 0x3)")); |
393 | amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr))); |
394 | amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16))); |
395 | amdgpu_ring_write(ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16))); |
396 | } |
397 | |
398 | if ((flags & AMDGPU_FENCE_FLAG_INT(1 << 1))) { |
399 | uint32_t ctx = ring->is_mes_queue ? |
400 | (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG0x1000000u) : 0; |
401 | /* generate an interrupt */ |
402 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)(((6) & 0x000000FF) << 0)); |
403 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)(((ctx) & 0x0FFFFFFF) << 0)); |
404 | } |
405 | } |
406 | |
407 | |
408 | /** |
409 | * sdma_v5_2_gfx_stop - stop the gfx async dma engines |
410 | * |
411 | * @adev: amdgpu_device pointer |
412 | * |
413 | * Stop the gfx async dma ring buffers. |
414 | */ |
415 | static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) |
416 | { |
417 | u32 rb_cntl, ib_cntl; |
418 | int i; |
419 | |
420 | amdgpu_sdma_unset_buffer_funcs_helper(adev); |
421 | |
422 | for (i = 0; i < adev->sdma.num_instances; i++) { |
423 | rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0080), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0080)), 0)); |
424 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0)(((rb_cntl) & ~0x00000001L) | (0x00000001L & ((0) << 0x0))); |
425 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0080), rb_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0080)), (rb_cntl), 0)); |
426 | ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x008a), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x008a)), 0)); |
427 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0)(((ib_cntl) & ~0x00000001L) | (0x00000001L & ((0) << 0x0))); |
428 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x008a), ib_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x008a)), (ib_cntl), 0)); |
429 | } |
430 | } |
431 | |
432 | /** |
433 | * sdma_v5_2_rlc_stop - stop the compute async dma engines |
434 | * |
435 | * @adev: amdgpu_device pointer |
436 | * |
437 | * Stop the compute async dma queues. |
438 | */ |
439 | static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) |
440 | { |
441 | /* XXX todo */ |
442 | } |
443 | |
444 | /** |
445 | * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch |
446 | * |
447 | * @adev: amdgpu_device pointer |
448 | * @enable: enable/disable the DMA MEs context switch. |
449 | * |
450 | * Halt or unhalt the async dma engines context switch. |
451 | */ |
452 | static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool_Bool enable) |
453 | { |
454 | u32 f32_cntl, phase_quantum = 0; |
455 | int i; |
456 | |
457 | if (amdgpu_sdma_phase_quantum) { |
458 | unsigned value = amdgpu_sdma_phase_quantum; |
459 | unsigned unit = 0; |
460 | |
461 | while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK0x00FFFF00L >> |
462 | SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8)) { |
463 | value = (value + 1) >> 1; |
464 | unit++; |
465 | } |
466 | if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK0x0000000FL >> |
467 | SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0)) { |
468 | value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK0x00FFFF00L >> |
469 | SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8); |
470 | unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK0x0000000FL >> |
471 | SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0); |
472 | WARN_ONCE(1,({ static int __warned; int __ret = !!(1); if (__ret && !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n" , value << unit); __warned = 1; } __builtin_expect(!!(__ret ), 0); }) |
473 | "clamping sdma_phase_quantum to %uK clock cycles\n",({ static int __warned; int __ret = !!(1); if (__ret && !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n" , value << unit); __warned = 1; } __builtin_expect(!!(__ret ), 0); }) |
474 | value << unit)({ static int __warned; int __ret = !!(1); if (__ret && !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n" , value << unit); __warned = 1; } __builtin_expect(!!(__ret ), 0); }); |
475 | } |
476 | phase_quantum = |
477 | value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8 | |
478 | unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0; |
479 | } |
480 | |
481 | for (i = 0; i < adev->sdma.num_instances; i++) { |
482 | if (enable && amdgpu_sdma_phase_quantum) { |
483 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x002c), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x002c)), (phase_quantum ), 0)) |
484 | phase_quantum)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x002c), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x002c)), (phase_quantum ), 0)); |
485 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x002d), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x002d)), (phase_quantum ), 0)) |
486 | phase_quantum)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x002d), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x002d)), (phase_quantum ), 0)); |
487 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x004f), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x004f)), (phase_quantum ), 0)) |
488 | phase_quantum)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x004f), phase_quantum, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x004f)), (phase_quantum ), 0)); |
489 | } |
490 | |
491 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
492 | f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001c )), 0); |
493 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,(((f32_cntl) & ~0x00040000L) | (0x00040000L & ((enable ? 1 : 0) << 0x12))) |
494 | AUTO_CTXSW_ENABLE, enable ? 1 : 0)(((f32_cntl) & ~0x00040000L) | (0x00040000L & ((enable ? 1 : 0) << 0x12))); |
495 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001c )), (f32_cntl), 0); |
496 | } |
497 | } |
498 | |
499 | } |
500 | |
501 | /** |
502 | * sdma_v5_2_enable - stop the async dma engines |
503 | * |
504 | * @adev: amdgpu_device pointer |
505 | * @enable: enable/disable the DMA MEs. |
506 | * |
507 | * Halt or unhalt the async dma engines. |
508 | */ |
509 | static void sdma_v5_2_enable(struct amdgpu_device *adev, bool_Bool enable) |
510 | { |
511 | u32 f32_cntl; |
512 | int i; |
513 | |
514 | if (!enable) { |
515 | sdma_v5_2_gfx_stop(adev); |
516 | sdma_v5_2_rlc_stop(adev); |
517 | } |
518 | |
519 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
520 | for (i = 0; i < adev->sdma.num_instances; i++) { |
521 | f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002a )), 0); |
522 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1)(((f32_cntl) & ~0x00000001L) | (0x00000001L & ((enable ? 0 : 1) << 0x0))); |
523 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002a )), (f32_cntl), 0); |
524 | } |
525 | } |
526 | } |
527 | |
528 | /** |
529 | * sdma_v5_2_gfx_resume - setup and start the async dma engines |
530 | * |
531 | * @adev: amdgpu_device pointer |
532 | * |
533 | * Set up the gfx DMA ring buffers and enable them. |
534 | * Returns 0 for success, error for failure. |
535 | */ |
536 | static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) |
537 | { |
538 | struct amdgpu_ring *ring; |
539 | u32 rb_cntl, ib_cntl; |
540 | u32 rb_bufsz; |
541 | u32 doorbell; |
542 | u32 doorbell_offset; |
543 | u32 temp; |
544 | u32 wptr_poll_cntl; |
545 | u64 wptr_gpu_addr; |
546 | int i, r; |
547 | |
548 | for (i = 0; i < adev->sdma.num_instances; i++) { |
549 | ring = &adev->sdma.instance[i].ring; |
550 | |
551 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) |
552 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0021), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0021)), (0), 0)); |
553 | |
554 | /* Set ring buffer size in dwords */ |
555 | rb_bufsz = order_base_2(ring->ring_size / 4)drm_order(ring->ring_size / 4); |
556 | rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0080), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0080)), 0)); |
557 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz)(((rb_cntl) & ~0x0000003EL) | (0x0000003EL & ((rb_bufsz ) << 0x1))); |
558 | #ifdef __BIG_ENDIAN |
559 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1)(((rb_cntl) & ~0x00000200L) | (0x00000200L & ((1) << 0x9))); |
560 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,(((rb_cntl) & ~0x00002000L) | (0x00002000L & ((1) << 0xd))) |
561 | RPTR_WRITEBACK_SWAP_ENABLE, 1)(((rb_cntl) & ~0x00002000L) | (0x00002000L & ((1) << 0xd))); |
562 | #endif |
563 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0080), rb_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0080)), (rb_cntl), 0)); |
564 | |
565 | /* Initialize the ring buffer's read and write pointers */ |
566 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0083), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0083)), (0), 0)); |
567 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0084), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0084)), (0), 0)); |
568 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0085), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0085)), (0), 0)); |
569 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0086), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0086)), (0), 0)); |
570 | |
571 | /* setup the wptr shadow polling */ |
572 | wptr_gpu_addr = ring->wptr_gpu_addr; |
573 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x00b3), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg (adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00b3)), (((u32)(wptr_gpu_addr ))), 0)) |
574 | lower_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x00b3), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg (adev, (sdma_v5_2_get_reg_offset(adev, i, 0x00b3)), (((u32)(wptr_gpu_addr ))), 0)); |
575 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x00b2), ((u32)(((wptr_gpu_addr) >> 16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x00b2)), (((u32)(((wptr_gpu_addr) >> 16) >> 16))), 0)) |
576 | upper_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x00b2), ((u32)(((wptr_gpu_addr) >> 16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x00b2)), (((u32)(((wptr_gpu_addr) >> 16) >> 16))), 0)); |
577 | wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0087), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0087)), 0)) |
578 | mmSDMA0_GFX_RB_WPTR_POLL_CNTL))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0087), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0087)), 0)); |
579 | wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & ( (1) << 0x2))) |
580 | SDMA0_GFX_RB_WPTR_POLL_CNTL,(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & ( (1) << 0x2))) |
581 | F32_POLL_ENABLE, 1)(((wptr_poll_cntl) & ~0x00000004L) | (0x00000004L & ( (1) << 0x2))); |
582 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0087), wptr_poll_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x0087)), (wptr_poll_cntl ), 0)) |
583 | wptr_poll_cntl)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0087), wptr_poll_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x0087)), (wptr_poll_cntl ), 0)); |
584 | |
585 | /* set the wb address whether it's enabled or not */ |
586 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0088), ((u32)(((ring->rptr_gpu_addr) >> 16) >> 16)) & 0xFFFFFFFF, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x0088)), (((u32)(((ring ->rptr_gpu_addr) >> 16) >> 16)) & 0xFFFFFFFF ), 0)) |
587 | upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0088), ((u32)(((ring->rptr_gpu_addr) >> 16) >> 16)) & 0xFFFFFFFF, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x0088)), (((u32)(((ring ->rptr_gpu_addr) >> 16) >> 16)) & 0xFFFFFFFF ), 0)); |
588 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0089), ((u32)(ring->rptr_gpu_addr)) & 0xFFFFFFFC, 0 , GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0089)), (((u32)(ring->rptr_gpu_addr)) & 0xFFFFFFFC ), 0)) |
589 | lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0089), ((u32)(ring->rptr_gpu_addr)) & 0xFFFFFFFC, 0 , GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0089)), (((u32)(ring->rptr_gpu_addr)) & 0xFFFFFFFC ), 0)); |
590 | |
591 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1)(((rb_cntl) & ~0x00001000L) | (0x00001000L & ((1) << 0xc))); |
592 | |
593 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0081), ring->gpu_addr >> 8, 0, GC_HWIP) : amdgpu_device_wreg (adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0081)), (ring-> gpu_addr >> 8), 0)); |
594 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0082), ring->gpu_addr >> 40, 0, GC_HWIP) : amdgpu_device_wreg (adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0082)), (ring-> gpu_addr >> 40), 0)); |
595 | |
596 | ring->wptr = 0; |
597 | |
598 | /* before programing wptr to a less value, need set minor_ptr_update first */ |
599 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x00b5), 1, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x00b5)), (1), 0)); |
600 | |
601 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { /* only bare-metal use register write for wptr */ |
602 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0085 )), (((u32)(ring->wptr << 2))), 0); |
603 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0086 )), (((u32)(((ring->wptr << 2) >> 16) >> 16))), 0); |
604 | } |
605 | |
606 | doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0092), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0092)), 0)); |
607 | doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x00ab), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x00ab)), 0)); |
608 | |
609 | if (ring->use_doorbell) { |
610 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1)(((doorbell) & ~0x10000000L) | (0x10000000L & ((1) << 0x1c))); |
611 | doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,(((doorbell_offset) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ( (ring->doorbell_index) << 0x2))) |
612 | OFFSET, ring->doorbell_index)(((doorbell_offset) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ( (ring->doorbell_index) << 0x2))); |
613 | } else { |
614 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0)(((doorbell) & ~0x10000000L) | (0x10000000L & ((0) << 0x1c))); |
615 | } |
616 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0092), doorbell, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0092)), (doorbell), 0)); |
617 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x00ab), doorbell_offset, 0, GC_HWIP) : amdgpu_device_wreg(adev , (sdma_v5_2_get_reg_offset(adev, i, 0x00ab)), (doorbell_offset ), 0)); |
618 | |
619 | adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, |
620 | ring->doorbell_index, |
621 | adev->doorbell_index.sdma_doorbell_range); |
622 | |
623 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) |
624 | sdma_v5_2_ring_set_wptr(ring); |
625 | |
626 | /* set minor_ptr_update to 0 after wptr programed */ |
627 | |
628 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x00b5), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x00b5)), (0), 0)); |
629 | |
630 | /* SRIOV VF has no control of any of registers below */ |
631 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
632 | /* set utc l1 enable flag always to 1 */ |
633 | temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001c )), 0); |
634 | temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1)(((temp) & ~0x00000002L) | (0x00000002L & ((1) << 0x1))); |
635 | |
636 | /* enable MCBP */ |
637 | temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1)(((temp) & ~0x00000020L) | (0x00000020L & ((1) << 0x5))); |
638 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001c )), (temp), 0); |
639 | |
640 | /* Set up RESP_MODE to non-copy addresses */ |
641 | temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x003c), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x003c)), 0)); |
642 | temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3)(((temp) & ~0x00000E00L) | (0x00000E00L & ((3) << 0x9))); |
643 | temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9)(((temp) & ~0x0000003EL) | (0x0000003EL & ((9) << 0x1))); |
644 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x003c), temp, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x003c)), (temp), 0)); |
645 | |
646 | /* program default cache read and write policy */ |
647 | temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0048), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0048)), 0)); |
648 | /* clean read policy and write policy bits */ |
649 | temp &= 0xFF0FFF; |
650 | temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | |
651 | (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | |
652 | SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK0x01000000L); |
653 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0048), temp, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0048)), (temp), 0)); |
654 | |
655 | /* unhalt engine */ |
656 | temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002a )), 0); |
657 | temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0)(((temp) & ~0x00000001L) | (0x00000001L & ((0) << 0x0))); |
658 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x002a )), (temp), 0); |
659 | } |
660 | |
661 | /* enable DMA RB */ |
662 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1)(((rb_cntl) & ~0x00000001L) | (0x00000001L & ((1) << 0x0))); |
663 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x0080), rb_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x0080)), (rb_cntl), 0)); |
664 | |
665 | ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL))((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x008a), 0, GC_HWIP) : amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x008a)), 0)); |
666 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1)(((ib_cntl) & ~0x00000001L) | (0x00000001L & ((1) << 0x0))); |
667 | #ifdef __BIG_ENDIAN |
668 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1)(((ib_cntl) & ~0x00000010L) | (0x00000010L & ((1) << 0x4))); |
669 | #endif |
670 | /* enable DMA IBs */ |
671 | WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, sdma_v5_2_get_reg_offset(adev, i, 0x008a), ib_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset (adev, i, 0x008a)), (ib_cntl), 0)); |
672 | |
673 | ring->sched.ready = true1; |
674 | |
675 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { /* bare-metal sequence doesn't need below to lines */ |
676 | sdma_v5_2_ctx_switch_enable(adev, true1); |
677 | sdma_v5_2_enable(adev, true1); |
678 | } |
679 | |
680 | r = amdgpu_ring_test_ring(ring)(ring)->funcs->test_ring((ring)); |
681 | if (r) { |
682 | ring->sched.ready = false0; |
683 | return r; |
684 | } |
685 | |
686 | if (adev->mman.buffer_funcs_ring == ring) |
687 | amdgpu_ttm_set_buffer_funcs_status(adev, true1); |
688 | } |
689 | |
690 | return 0; |
691 | } |
692 | |
693 | /** |
694 | * sdma_v5_2_rlc_resume - setup and start the async dma engines |
695 | * |
696 | * @adev: amdgpu_device pointer |
697 | * |
698 | * Set up the compute DMA queues and enable them. |
699 | * Returns 0 for success, error for failure. |
700 | */ |
701 | static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) |
702 | { |
703 | return 0; |
704 | } |
705 | |
706 | /** |
707 | * sdma_v5_2_load_microcode - load the sDMA ME ucode |
708 | * |
709 | * @adev: amdgpu_device pointer |
710 | * |
711 | * Loads the sDMA0/1/2/3 ucode. |
712 | * Returns 0 for success, -EINVAL if the ucode is not available. |
713 | */ |
714 | static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) |
715 | { |
716 | const struct sdma_firmware_header_v1_0 *hdr; |
717 | const __le32 *fw_data; |
718 | u32 fw_size; |
719 | int i, j; |
720 | |
721 | /* halt the MEs */ |
722 | sdma_v5_2_enable(adev, false0); |
723 | |
724 | for (i = 0; i < adev->sdma.num_instances; i++) { |
725 | if (!adev->sdma.instance[i].fw) |
726 | return -EINVAL22; |
727 | |
728 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; |
729 | amdgpu_ucode_print_sdma_hdr(&hdr->header); |
730 | fw_size = le32_to_cpu(hdr->header.ucode_size_bytes)((__uint32_t)(hdr->header.ucode_size_bytes)) / 4; |
731 | |
732 | fw_data = (const __le32 *) |
733 | (adev->sdma.instance[i].fw->data + |
734 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes))); |
735 | |
736 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x5880 )), (0), 0); |
737 | |
738 | for (j = 0; j < fw_size; j++) { |
739 | if (amdgpu_emu_mode == 1 && j % 500 == 0) |
740 | drm_msleep(1)mdelay(1); |
741 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x5881 )), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0); |
742 | } |
743 | |
744 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x5880 )), (adev->sdma.instance[i].fw_version), 0); |
745 | } |
746 | |
747 | return 0; |
748 | } |
749 | |
750 | static int sdma_v5_2_soft_reset(void *handle) |
751 | { |
752 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
753 | u32 grbm_soft_reset; |
754 | u32 tmp; |
755 | int i; |
756 | |
757 | for (i = 0; i < adev->sdma.num_instances; i++) { |
758 | grbm_soft_reset = REG_SET_FIELD(0,(((0) & ~0x00800000L) | (0x00800000L & ((1) << 0x17 ))) |
759 | GRBM_SOFT_RESET, SOFT_RESET_SDMA0,(((0) & ~0x00800000L) | (0x00800000L & ((1) << 0x17 ))) |
760 | 1)(((0) & ~0x00800000L) | (0x00800000L & ((1) << 0x17 ))); |
761 | grbm_soft_reset <<= i; |
762 | |
763 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0da8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0da8), 0)); |
764 | tmp |= grbm_soft_reset; |
765 | DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp)___drm_dbg(((void *)0), DRM_UT_CORE, "GRBM_SOFT_RESET=0x%08X\n" , tmp); |
766 | WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x0da8), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x0da8)), (tmp), 0)); |
767 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0da8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0da8), 0)); |
768 | |
769 | udelay(50); |
770 | |
771 | tmp &= ~grbm_soft_reset; |
772 | WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][ 0] + 0x0da8), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev ->reg_offset[GC_HWIP][0][0] + 0x0da8)), (tmp), 0)); |
773 | tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev ->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported ) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0 ] + 0x0da8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev-> reg_offset[GC_HWIP][0][0] + 0x0da8), 0)); |
Value stored to 'tmp' is never read | |
774 | |
775 | udelay(50); |
776 | } |
777 | |
778 | return 0; |
779 | } |
780 | |
781 | /** |
782 | * sdma_v5_2_start - setup and start the async dma engines |
783 | * |
784 | * @adev: amdgpu_device pointer |
785 | * |
786 | * Set up the DMA engines and enable them. |
787 | * Returns 0 for success, error for failure. |
788 | */ |
789 | static int sdma_v5_2_start(struct amdgpu_device *adev) |
790 | { |
791 | int r = 0; |
792 | |
793 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
794 | sdma_v5_2_ctx_switch_enable(adev, false0); |
795 | sdma_v5_2_enable(adev, false0); |
796 | |
797 | /* set RB registers */ |
798 | r = sdma_v5_2_gfx_resume(adev); |
799 | return r; |
800 | } |
801 | |
802 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { |
803 | r = sdma_v5_2_load_microcode(adev); |
804 | if (r) |
805 | return r; |
806 | |
807 | /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ |
808 | if (amdgpu_emu_mode == 1) |
809 | drm_msleep(1000)mdelay(1000); |
810 | } |
811 | |
812 | /* TODO: check whether can submit a doorbell request to raise |
813 | * a doorbell fence to exit gfxoff. |
814 | */ |
815 | if (adev->in_s0ix) |
816 | amdgpu_gfx_off_ctrl(adev, false0); |
817 | |
818 | sdma_v5_2_soft_reset(adev); |
819 | /* unhalt the MEs */ |
820 | sdma_v5_2_enable(adev, true1); |
821 | /* enable sdma ring preemption */ |
822 | sdma_v5_2_ctx_switch_enable(adev, true1); |
823 | |
824 | /* start the gfx rings and rlc compute queues */ |
825 | r = sdma_v5_2_gfx_resume(adev); |
826 | if (adev->in_s0ix) |
827 | amdgpu_gfx_off_ctrl(adev, true1); |
828 | if (r) |
829 | return r; |
830 | r = sdma_v5_2_rlc_resume(adev); |
831 | |
832 | return r; |
833 | } |
834 | |
835 | static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd, |
836 | struct amdgpu_mqd_prop *prop) |
837 | { |
838 | struct v10_sdma_mqd *m = mqd; |
839 | uint64_t wb_gpu_addr; |
840 | |
841 | m->sdmax_rlcx_rb_cntl = |
842 | order_base_2(prop->queue_size / 4)drm_order(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT0x1 | |
843 | 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT0xc | |
844 | 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT0x10 | |
845 | 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT0x17; |
846 | |
847 | m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8)((u32)(prop->hqd_base_gpu_addr >> 8)); |
848 | m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8)((u32)(((prop->hqd_base_gpu_addr >> 8) >> 16) >> 16)); |
849 | |
850 | m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x0087 )), 0) |
851 | mmSDMA0_GFX_RB_WPTR_POLL_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x0087 )), 0); |
852 | |
853 | wb_gpu_addr = prop->wptr_gpu_addr; |
854 | m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr)((u32)(wb_gpu_addr)); |
855 | m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)); |
856 | |
857 | wb_gpu_addr = prop->rptr_gpu_addr; |
858 | m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr)((u32)(wb_gpu_addr)); |
859 | m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)); |
860 | |
861 | m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x008a )), 0) |
862 | mmSDMA0_GFX_IB_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x008a )), 0); |
863 | |
864 | m->sdmax_rlcx_doorbell_offset = |
865 | prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT0x2; |
866 | |
867 | m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1)(((0) & ~0x10000000L) | (0x10000000L & ((1) << 0x1c ))); |
868 | |
869 | return 0; |
870 | } |
871 | |
872 | static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev) |
873 | { |
874 | adev->mqds[AMDGPU_HW_IP_DMA2].mqd_size = sizeof(struct v10_sdma_mqd); |
875 | adev->mqds[AMDGPU_HW_IP_DMA2].init_mqd = sdma_v5_2_mqd_init; |
876 | } |
877 | |
878 | /** |
879 | * sdma_v5_2_ring_test_ring - simple async dma engine test |
880 | * |
881 | * @ring: amdgpu_ring structure holding ring information |
882 | * |
883 | * Test the DMA engine by writing using it to write an |
884 | * value to memory. |
885 | * Returns 0 for success, error for failure. |
886 | */ |
887 | static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) |
888 | { |
889 | struct amdgpu_device *adev = ring->adev; |
890 | unsigned i; |
891 | unsigned index; |
892 | int r; |
893 | u32 tmp; |
894 | u64 gpu_addr; |
895 | volatile uint32_t *cpu_ptr = NULL((void *)0); |
896 | |
897 | tmp = 0xCAFEDEAD; |
898 | |
899 | if (ring->is_mes_queue) { |
900 | uint32_t offset = 0; |
901 | offset = amdgpu_mes_ctx_get_offs(ring, |
902 | AMDGPU_MES_CTX_PADDING_OFFS); |
903 | gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring-> mes_ctx->meta_data_gpu_addr + offset) : 0); |
904 | cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *) ((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : ( (void *)0)); |
905 | *cpu_ptr = tmp; |
906 | } else { |
907 | r = amdgpu_device_wb_get(adev, &index); |
908 | if (r) { |
909 | dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to allocate wb slot\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
910 | return r; |
911 | } |
912 | |
913 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
914 | adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp)); |
915 | } |
916 | |
917 | r = amdgpu_ring_alloc(ring, 20); |
918 | if (r) { |
919 | DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r)__drm_err("amdgpu: dma failed to lock ring %d (%d).\n", ring-> idx, r); |
920 | amdgpu_device_wb_free(adev, index); |
921 | return r; |
922 | } |
923 | |
924 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) | |
925 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8)); |
926 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)((u32)(gpu_addr))); |
927 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16))); |
928 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)(((0) & 0x000FFFFF) << 0)); |
929 | amdgpu_ring_write(ring, 0xDEADBEEF); |
930 | amdgpu_ring_commit(ring); |
931 | |
932 | for (i = 0; i < adev->usec_timeout; i++) { |
933 | if (ring->is_mes_queue) |
934 | tmp = le32_to_cpu(*cpu_ptr)((__uint32_t)(*cpu_ptr)); |
935 | else |
936 | tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index])); |
937 | if (tmp == 0xDEADBEEF) |
938 | break; |
939 | if (amdgpu_emu_mode == 1) |
940 | drm_msleep(1)mdelay(1); |
941 | else |
942 | udelay(1); |
943 | } |
944 | |
945 | if (i >= adev->usec_timeout) |
946 | r = -ETIMEDOUT60; |
947 | |
948 | if (!ring->is_mes_queue) |
949 | amdgpu_device_wb_free(adev, index); |
950 | |
951 | return r; |
952 | } |
953 | |
954 | /** |
955 | * sdma_v5_2_ring_test_ib - test an IB on the DMA engine |
956 | * |
957 | * @ring: amdgpu_ring structure holding ring information |
958 | * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT |
959 | * |
960 | * Test a simple IB in the DMA ring. |
961 | * Returns 0 on success, error on failure. |
962 | */ |
963 | static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
964 | { |
965 | struct amdgpu_device *adev = ring->adev; |
966 | struct amdgpu_ib ib; |
967 | struct dma_fence *f = NULL((void *)0); |
968 | unsigned index; |
969 | long r; |
970 | u32 tmp = 0; |
971 | u64 gpu_addr; |
972 | volatile uint32_t *cpu_ptr = NULL((void *)0); |
973 | |
974 | tmp = 0xCAFEDEAD; |
975 | memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib))); |
976 | |
977 | if (ring->is_mes_queue) { |
978 | uint32_t offset = 0; |
979 | offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); |
980 | ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring-> mes_ctx->meta_data_gpu_addr + offset) : 0); |
981 | ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *) ((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : ( (void *)0)); |
982 | |
983 | offset = amdgpu_mes_ctx_get_offs(ring, |
984 | AMDGPU_MES_CTX_PADDING_OFFS); |
985 | gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring-> mes_ctx->meta_data_gpu_addr + offset) : 0); |
986 | cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *) ((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : ( (void *)0)); |
987 | *cpu_ptr = tmp; |
988 | } else { |
989 | r = amdgpu_device_wb_get(adev, &index); |
990 | if (r) { |
991 | dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r)printf("drm:pid%d:%s *ERROR* " "(%ld) failed to allocate wb slot\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
992 | return r; |
993 | } |
994 | |
995 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
996 | adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp)); |
997 | |
998 | r = amdgpu_ib_get(adev, NULL((void *)0), 256, AMDGPU_IB_POOL_DIRECT, &ib); |
999 | if (r) { |
1000 | DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r)__drm_err("amdgpu: failed to get ib (%ld).\n", r); |
1001 | goto err0; |
1002 | } |
1003 | } |
1004 | |
1005 | ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) | |
1006 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8); |
1007 | ib.ptr[1] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
1008 | ib.ptr[2] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
1009 | ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)(((0) & 0x000FFFFF) << 0); |
1010 | ib.ptr[4] = 0xDEADBEEF; |
1011 | ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0); |
1012 | ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0); |
1013 | ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0); |
1014 | ib.length_dw = 8; |
1015 | |
1016 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f); |
1017 | if (r) |
1018 | goto err1; |
1019 | |
1020 | r = dma_fence_wait_timeout(f, false0, timeout); |
1021 | if (r == 0) { |
1022 | DRM_ERROR("amdgpu: IB test timed out\n")__drm_err("amdgpu: IB test timed out\n"); |
1023 | r = -ETIMEDOUT60; |
1024 | goto err1; |
1025 | } else if (r < 0) { |
1026 | DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r)__drm_err("amdgpu: fence wait failed (%ld).\n", r); |
1027 | goto err1; |
1028 | } |
1029 | |
1030 | if (ring->is_mes_queue) |
1031 | tmp = le32_to_cpu(*cpu_ptr)((__uint32_t)(*cpu_ptr)); |
1032 | else |
1033 | tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index])); |
1034 | |
1035 | if (tmp == 0xDEADBEEF) |
1036 | r = 0; |
1037 | else |
1038 | r = -EINVAL22; |
1039 | |
1040 | err1: |
1041 | amdgpu_ib_free(adev, &ib, NULL((void *)0)); |
1042 | dma_fence_put(f); |
1043 | err0: |
1044 | if (!ring->is_mes_queue) |
1045 | amdgpu_device_wb_free(adev, index); |
1046 | return r; |
1047 | } |
1048 | |
1049 | |
1050 | /** |
1051 | * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART |
1052 | * |
1053 | * @ib: indirect buffer to fill with commands |
1054 | * @pe: addr of the page entry |
1055 | * @src: src addr to copy from |
1056 | * @count: number of page entries to update |
1057 | * |
1058 | * Update PTEs by copying them from the GART using sDMA. |
1059 | */ |
1060 | static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, |
1061 | uint64_t pe, uint64_t src, |
1062 | unsigned count) |
1063 | { |
1064 | unsigned bytes = count * 8; |
1065 | |
1066 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) | |
1067 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8); |
1068 | ib->ptr[ib->length_dw++] = bytes - 1; |
1069 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ |
1070 | ib->ptr[ib->length_dw++] = lower_32_bits(src)((u32)(src)); |
1071 | ib->ptr[ib->length_dw++] = upper_32_bits(src)((u32)(((src) >> 16) >> 16)); |
1072 | ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); |
1073 | ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16)); |
1074 | |
1075 | } |
1076 | |
1077 | /** |
1078 | * sdma_v5_2_vm_write_pte - update PTEs by writing them manually |
1079 | * |
1080 | * @ib: indirect buffer to fill with commands |
1081 | * @pe: addr of the page entry |
1082 | * @value: dst addr to write into pe |
1083 | * @count: number of page entries to update |
1084 | * @incr: increase next addr by incr bytes |
1085 | * |
1086 | * Update PTEs by writing them manually using sDMA. |
1087 | */ |
1088 | static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, |
1089 | uint64_t value, unsigned count, |
1090 | uint32_t incr) |
1091 | { |
1092 | unsigned ndw = count * 2; |
1093 | |
1094 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) | |
1095 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8); |
1096 | ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); |
1097 | ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16)); |
1098 | ib->ptr[ib->length_dw++] = ndw - 1; |
1099 | for (; ndw > 0; ndw -= 2) { |
1100 | ib->ptr[ib->length_dw++] = lower_32_bits(value)((u32)(value)); |
1101 | ib->ptr[ib->length_dw++] = upper_32_bits(value)((u32)(((value) >> 16) >> 16)); |
1102 | value += incr; |
1103 | } |
1104 | } |
1105 | |
1106 | /** |
1107 | * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA |
1108 | * |
1109 | * @ib: indirect buffer to fill with commands |
1110 | * @pe: addr of the page entry |
1111 | * @addr: dst addr to write into pe |
1112 | * @count: number of page entries to update |
1113 | * @incr: increase next addr by incr bytes |
1114 | * @flags: access flags |
1115 | * |
1116 | * Update the page tables using sDMA. |
1117 | */ |
1118 | static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, |
1119 | uint64_t pe, |
1120 | uint64_t addr, unsigned count, |
1121 | uint32_t incr, uint64_t flags) |
1122 | { |
1123 | /* for physically contiguous pages (vram) */ |
1124 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE)(((12) & 0x000000FF) << 0); |
1125 | ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); /* dst addr */ |
1126 | ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16)); |
1127 | ib->ptr[ib->length_dw++] = lower_32_bits(flags)((u32)(flags)); /* mask */ |
1128 | ib->ptr[ib->length_dw++] = upper_32_bits(flags)((u32)(((flags) >> 16) >> 16)); |
1129 | ib->ptr[ib->length_dw++] = lower_32_bits(addr)((u32)(addr)); /* value */ |
1130 | ib->ptr[ib->length_dw++] = upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)); |
1131 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
1132 | ib->ptr[ib->length_dw++] = 0; |
1133 | ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ |
1134 | } |
1135 | |
1136 | /** |
1137 | * sdma_v5_2_ring_pad_ib - pad the IB |
1138 | * |
1139 | * @ib: indirect buffer to fill with padding |
1140 | * @ring: amdgpu_ring structure holding ring information |
1141 | * |
1142 | * Pad the IB with NOPs to a boundary multiple of 8. |
1143 | */ |
1144 | static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) |
1145 | { |
1146 | struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); |
1147 | u32 pad_count; |
1148 | int i; |
1149 | |
1150 | pad_count = (-ib->length_dw) & 0x7; |
1151 | for (i = 0; i < pad_count; i++) |
1152 | if (sdma && sdma->burst_nop && (i == 0)) |
1153 | ib->ptr[ib->length_dw++] = |
1154 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0) | |
1155 | SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1)(((pad_count - 1) & 0x00003FFF) << 16); |
1156 | else |
1157 | ib->ptr[ib->length_dw++] = |
1158 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0); |
1159 | } |
1160 | |
1161 | |
1162 | /** |
1163 | * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline |
1164 | * |
1165 | * @ring: amdgpu_ring pointer |
1166 | * |
1167 | * Make sure all previous operations are completed (CIK). |
1168 | */ |
1169 | static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) |
1170 | { |
1171 | uint32_t seq = ring->fence_drv.sync_seq; |
1172 | uint64_t addr = ring->fence_drv.gpu_addr; |
1173 | |
1174 | /* wait for idle */ |
1175 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) | |
1176 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) | |
1177 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28) | /* equal */ |
1178 | SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)(((1) & 0x00000001) << 31)); |
1179 | amdgpu_ring_write(ring, addr & 0xfffffffc); |
1180 | amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)) & 0xffffffff); |
1181 | amdgpu_ring_write(ring, seq); /* reference */ |
1182 | amdgpu_ring_write(ring, 0xffffffff); /* mask */ |
1183 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) | |
1184 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)(((4) & 0x0000FFFF) << 0)); /* retry count, poll interval */ |
1185 | } |
1186 | |
1187 | |
1188 | /** |
1189 | * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA |
1190 | * |
1191 | * @ring: amdgpu_ring pointer |
1192 | * @vmid: vmid number to use |
1193 | * @pd_addr: address |
1194 | * |
1195 | * Update the page table base and flush the VM TLB |
1196 | * using sDMA. |
1197 | */ |
1198 | static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, |
1199 | unsigned vmid, uint64_t pd_addr) |
1200 | { |
1201 | amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr)(ring)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((ring ), (vmid), (pd_addr)); |
1202 | } |
1203 | |
1204 | static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, |
1205 | uint32_t reg, uint32_t val) |
1206 | { |
1207 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE)(((14) & 0x000000FF) << 0) | |
1208 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)(((0xf) & 0x0000000F) << 28)); |
1209 | amdgpu_ring_write(ring, reg); |
1210 | amdgpu_ring_write(ring, val); |
1211 | } |
1212 | |
1213 | static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, |
1214 | uint32_t val, uint32_t mask) |
1215 | { |
1216 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) | |
1217 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) | |
1218 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28)); /* equal */ |
1219 | amdgpu_ring_write(ring, reg << 2); |
1220 | amdgpu_ring_write(ring, 0); |
1221 | amdgpu_ring_write(ring, val); /* reference */ |
1222 | amdgpu_ring_write(ring, mask); /* mask */ |
1223 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) | |
1224 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0)); |
1225 | } |
1226 | |
1227 | static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, |
1228 | uint32_t reg0, uint32_t reg1, |
1229 | uint32_t ref, uint32_t mask) |
1230 | { |
1231 | amdgpu_ring_emit_wreg(ring, reg0, ref)(ring)->funcs->emit_wreg((ring), (reg0), (ref)); |
1232 | /* wait for a cycle to reset vm_inv_eng*_ack */ |
1233 | amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0)(ring)->funcs->emit_reg_wait((ring), (reg0), (0), (0)); |
1234 | amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask)(ring)->funcs->emit_reg_wait((ring), (reg1), (mask), (mask )); |
1235 | } |
1236 | |
1237 | static int sdma_v5_2_early_init(void *handle) |
1238 | { |
1239 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1240 | |
1241 | sdma_v5_2_set_ring_funcs(adev); |
1242 | sdma_v5_2_set_buffer_funcs(adev); |
1243 | sdma_v5_2_set_vm_pte_funcs(adev); |
1244 | sdma_v5_2_set_irq_funcs(adev); |
1245 | sdma_v5_2_set_mqd_funcs(adev); |
1246 | |
1247 | return 0; |
1248 | } |
1249 | |
1250 | static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) |
1251 | { |
1252 | switch (seq_num) { |
1253 | case 0: |
1254 | return SOC15_IH_CLIENTID_SDMA0; |
1255 | case 1: |
1256 | return SOC15_IH_CLIENTID_SDMA1; |
1257 | case 2: |
1258 | return SOC15_IH_CLIENTID_SDMA2; |
1259 | case 3: |
1260 | return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; |
1261 | default: |
1262 | break; |
1263 | } |
1264 | return -EINVAL22; |
1265 | } |
1266 | |
1267 | static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) |
1268 | { |
1269 | switch (seq_num) { |
1270 | case 0: |
1271 | return SDMA0_5_0__SRCID__SDMA_TRAP224; |
1272 | case 1: |
1273 | return SDMA1_5_0__SRCID__SDMA_TRAP224; |
1274 | case 2: |
1275 | return SDMA2_5_0__SRCID__SDMA_TRAP224; |
1276 | case 3: |
1277 | return SDMA3_5_0__SRCID__SDMA_TRAP224; |
1278 | default: |
1279 | break; |
1280 | } |
1281 | return -EINVAL22; |
1282 | } |
1283 | |
1284 | static int sdma_v5_2_sw_init(void *handle) |
1285 | { |
1286 | struct amdgpu_ring *ring; |
1287 | int r, i; |
1288 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1289 | |
1290 | /* SDMA trap event */ |
1291 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1292 | r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), |
1293 | sdma_v5_2_seq_to_trap_id(i), |
1294 | &adev->sdma.trap_irq); |
1295 | if (r) |
1296 | return r; |
1297 | } |
1298 | |
1299 | r = sdma_v5_2_init_microcode(adev); |
1300 | if (r) { |
1301 | DRM_ERROR("Failed to load sdma firmware!\n")__drm_err("Failed to load sdma firmware!\n"); |
1302 | return r; |
1303 | } |
1304 | |
1305 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1306 | ring = &adev->sdma.instance[i].ring; |
1307 | ring->ring_obj = NULL((void *)0); |
1308 | ring->use_doorbell = true1; |
1309 | ring->me = i; |
1310 | |
1311 | DRM_INFO("use_doorbell being set to: [%s]\n",printk("\0016" "[" "drm" "] " "use_doorbell being set to: [%s]\n" , ring->use_doorbell?"true":"false") |
1312 | ring->use_doorbell?"true":"false")printk("\0016" "[" "drm" "] " "use_doorbell being set to: [%s]\n" , ring->use_doorbell?"true":"false"); |
1313 | |
1314 | ring->doorbell_index = |
1315 | (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset |
1316 | |
1317 | snprintf(ring->name, sizeof(ring->name), "sdma%d", i); |
1318 | r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, |
1319 | AMDGPU_SDMA_IRQ_INSTANCE0 + i, |
1320 | AMDGPU_RING_PRIO_DEFAULT, NULL((void *)0)); |
1321 | if (r) |
1322 | return r; |
1323 | } |
1324 | |
1325 | return r; |
1326 | } |
1327 | |
1328 | static int sdma_v5_2_sw_fini(void *handle) |
1329 | { |
1330 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1331 | int i; |
1332 | |
1333 | for (i = 0; i < adev->sdma.num_instances; i++) |
1334 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); |
1335 | |
1336 | amdgpu_sdma_destroy_inst_ctx(adev, true1); |
1337 | |
1338 | return 0; |
1339 | } |
1340 | |
1341 | static int sdma_v5_2_hw_init(void *handle) |
1342 | { |
1343 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1344 | |
1345 | return sdma_v5_2_start(adev); |
1346 | } |
1347 | |
1348 | static int sdma_v5_2_hw_fini(void *handle) |
1349 | { |
1350 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1351 | |
1352 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
1353 | /* disable the scheduler for SDMA */ |
1354 | amdgpu_sdma_unset_buffer_funcs_helper(adev); |
1355 | return 0; |
1356 | } |
1357 | |
1358 | sdma_v5_2_ctx_switch_enable(adev, false0); |
1359 | sdma_v5_2_enable(adev, false0); |
1360 | |
1361 | return 0; |
1362 | } |
1363 | |
1364 | static int sdma_v5_2_suspend(void *handle) |
1365 | { |
1366 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1367 | |
1368 | return sdma_v5_2_hw_fini(adev); |
1369 | } |
1370 | |
1371 | static int sdma_v5_2_resume(void *handle) |
1372 | { |
1373 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1374 | |
1375 | return sdma_v5_2_hw_init(adev); |
1376 | } |
1377 | |
1378 | static bool_Bool sdma_v5_2_is_idle(void *handle) |
1379 | { |
1380 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1381 | u32 i; |
1382 | |
1383 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1384 | u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x0025 )), 0); |
1385 | |
1386 | if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK0x00000001L)) |
1387 | return false0; |
1388 | } |
1389 | |
1390 | return true1; |
1391 | } |
1392 | |
1393 | static int sdma_v5_2_wait_for_idle(void *handle) |
1394 | { |
1395 | unsigned i; |
1396 | u32 sdma0, sdma1, sdma2, sdma3; |
1397 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1398 | |
1399 | for (i = 0; i < adev->usec_timeout; i++) { |
1400 | sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x0025 )), 0); |
1401 | sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 1, 0x0025 )), 0); |
1402 | sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 2, 0x0025 )), 0); |
1403 | sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 3, 0x0025 )), 0); |
1404 | |
1405 | if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK0x00000001L) |
1406 | return 0; |
1407 | udelay(1); |
1408 | } |
1409 | return -ETIMEDOUT60; |
1410 | } |
1411 | |
1412 | static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) |
1413 | { |
1414 | int i, r = 0; |
1415 | struct amdgpu_device *adev = ring->adev; |
1416 | u32 index = 0; |
1417 | u64 sdma_gfx_preempt; |
1418 | |
1419 | amdgpu_sdma_get_index_from_ring(ring, &index); |
1420 | sdma_gfx_preempt = |
1421 | sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT0x00b0); |
1422 | |
1423 | /* assert preemption condition */ |
1424 | amdgpu_ring_set_preempt_cond_exec(ring, false0); |
1425 | |
1426 | /* emit the trailing fence */ |
1427 | ring->trail_seq += 1; |
1428 | amdgpu_ring_alloc(ring, 10); |
1429 | sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, |
1430 | ring->trail_seq, 0); |
1431 | amdgpu_ring_commit(ring); |
1432 | |
1433 | /* assert IB preemption */ |
1434 | WREG32(sdma_gfx_preempt, 1)amdgpu_device_wreg(adev, (sdma_gfx_preempt), (1), 0); |
1435 | |
1436 | /* poll the trailing fence */ |
1437 | for (i = 0; i < adev->usec_timeout; i++) { |
1438 | if (ring->trail_seq == |
1439 | le32_to_cpu(*(ring->trail_fence_cpu_addr))((__uint32_t)(*(ring->trail_fence_cpu_addr)))) |
1440 | break; |
1441 | udelay(1); |
1442 | } |
1443 | |
1444 | if (i >= adev->usec_timeout) { |
1445 | r = -EINVAL22; |
1446 | DRM_ERROR("ring %d failed to be preempted\n", ring->idx)__drm_err("ring %d failed to be preempted\n", ring->idx); |
1447 | } |
1448 | |
1449 | /* deassert IB preemption */ |
1450 | WREG32(sdma_gfx_preempt, 0)amdgpu_device_wreg(adev, (sdma_gfx_preempt), (0), 0); |
1451 | |
1452 | /* deassert the preemption condition */ |
1453 | amdgpu_ring_set_preempt_cond_exec(ring, true1); |
1454 | return r; |
1455 | } |
1456 | |
1457 | static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, |
1458 | struct amdgpu_irq_src *source, |
1459 | unsigned type, |
1460 | enum amdgpu_interrupt_state state) |
1461 | { |
1462 | u32 sdma_cntl; |
1463 | u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL0x001c); |
1464 | |
1465 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
1466 | sdma_cntl = RREG32(reg_offset)amdgpu_device_rreg(adev, (reg_offset), 0); |
1467 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,(((sdma_cntl) & ~0x00000001L) | (0x00000001L & ((state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x0))) |
1468 | state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)(((sdma_cntl) & ~0x00000001L) | (0x00000001L & ((state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x0))); |
1469 | WREG32(reg_offset, sdma_cntl)amdgpu_device_wreg(adev, (reg_offset), (sdma_cntl), 0); |
1470 | } |
1471 | |
1472 | return 0; |
1473 | } |
1474 | |
1475 | static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, |
1476 | struct amdgpu_irq_src *source, |
1477 | struct amdgpu_iv_entry *entry) |
1478 | { |
1479 | uint32_t mes_queue_id = entry->src_data[0]; |
1480 | |
1481 | DRM_DEBUG("IH: SDMA trap\n")___drm_dbg(((void *)0), DRM_UT_CORE, "IH: SDMA trap\n"); |
1482 | |
1483 | if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG0x1000000u)) { |
1484 | struct amdgpu_mes_queue *queue; |
1485 | |
1486 | mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK(0x1000000u - 1); |
1487 | |
1488 | spin_lock(&adev->mes.queue_id_lock)mtx_enter(&adev->mes.queue_id_lock); |
1489 | queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); |
1490 | if (queue) { |
1491 | DRM_DEBUG("process smda queue id = %d\n", mes_queue_id)___drm_dbg(((void *)0), DRM_UT_CORE, "process smda queue id = %d\n" , mes_queue_id); |
1492 | amdgpu_fence_process(queue->ring); |
1493 | } |
1494 | spin_unlock(&adev->mes.queue_id_lock)mtx_leave(&adev->mes.queue_id_lock); |
1495 | return 0; |
1496 | } |
1497 | |
1498 | switch (entry->client_id) { |
1499 | case SOC15_IH_CLIENTID_SDMA0: |
1500 | switch (entry->ring_id) { |
1501 | case 0: |
1502 | amdgpu_fence_process(&adev->sdma.instance[0].ring); |
1503 | break; |
1504 | case 1: |
1505 | /* XXX compute */ |
1506 | break; |
1507 | case 2: |
1508 | /* XXX compute */ |
1509 | break; |
1510 | case 3: |
1511 | /* XXX page queue*/ |
1512 | break; |
1513 | } |
1514 | break; |
1515 | case SOC15_IH_CLIENTID_SDMA1: |
1516 | switch (entry->ring_id) { |
1517 | case 0: |
1518 | amdgpu_fence_process(&adev->sdma.instance[1].ring); |
1519 | break; |
1520 | case 1: |
1521 | /* XXX compute */ |
1522 | break; |
1523 | case 2: |
1524 | /* XXX compute */ |
1525 | break; |
1526 | case 3: |
1527 | /* XXX page queue*/ |
1528 | break; |
1529 | } |
1530 | break; |
1531 | case SOC15_IH_CLIENTID_SDMA2: |
1532 | switch (entry->ring_id) { |
1533 | case 0: |
1534 | amdgpu_fence_process(&adev->sdma.instance[2].ring); |
1535 | break; |
1536 | case 1: |
1537 | /* XXX compute */ |
1538 | break; |
1539 | case 2: |
1540 | /* XXX compute */ |
1541 | break; |
1542 | case 3: |
1543 | /* XXX page queue*/ |
1544 | break; |
1545 | } |
1546 | break; |
1547 | case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: |
1548 | switch (entry->ring_id) { |
1549 | case 0: |
1550 | amdgpu_fence_process(&adev->sdma.instance[3].ring); |
1551 | break; |
1552 | case 1: |
1553 | /* XXX compute */ |
1554 | break; |
1555 | case 2: |
1556 | /* XXX compute */ |
1557 | break; |
1558 | case 3: |
1559 | /* XXX page queue*/ |
1560 | break; |
1561 | } |
1562 | break; |
1563 | } |
1564 | return 0; |
1565 | } |
1566 | |
1567 | static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, |
1568 | struct amdgpu_irq_src *source, |
1569 | struct amdgpu_iv_entry *entry) |
1570 | { |
1571 | return 0; |
1572 | } |
1573 | |
1574 | static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
1575 | bool_Bool enable) |
1576 | { |
1577 | uint32_t data, def; |
1578 | int i; |
1579 | |
1580 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1581 | |
1582 | if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)(((5) << 16) | ((2) << 8) | (1))) |
1583 | adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG(1ULL << 11); |
1584 | |
1585 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG(1ULL << 11))) { |
1586 | /* Enable sdma clock gating */ |
1587 | def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001b )), 0); |
1588 | data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK0x04000000L | |
1589 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK0x08000000L | |
1590 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK0x10000000L | |
1591 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK0x20000000L | |
1592 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x40000000L | |
1593 | SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK0x80000000L); |
1594 | if (def != data) |
1595 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001b )), (data), 0); |
1596 | } else { |
1597 | /* Disable sdma clock gating */ |
1598 | def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001b )), 0); |
1599 | data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK0x04000000L | |
1600 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK0x08000000L | |
1601 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK0x10000000L | |
1602 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK0x20000000L | |
1603 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x40000000L | |
1604 | SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK0x80000000L); |
1605 | if (def != data) |
1606 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001b )), (data), 0); |
1607 | } |
1608 | } |
1609 | } |
1610 | |
1611 | static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, |
1612 | bool_Bool enable) |
1613 | { |
1614 | uint32_t data, def; |
1615 | int i; |
1616 | |
1617 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1618 | |
1619 | if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)(((5) << 16) | ((2) << 8) | (1))) |
1620 | adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS(1ULL << 10); |
1621 | |
1622 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS(1ULL << 10))) { |
1623 | /* Enable sdma mem light sleep */ |
1624 | def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001a )), 0); |
1625 | data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L; |
1626 | if (def != data) |
1627 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001a )), (data), 0); |
1628 | |
1629 | } else { |
1630 | /* Disable sdma mem light sleep */ |
1631 | def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001a )), 0); |
1632 | data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L; |
1633 | if (def != data) |
1634 | WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data)amdgpu_device_wreg(adev, (sdma_v5_2_get_reg_offset(adev, i, 0x001a )), (data), 0); |
1635 | |
1636 | } |
1637 | } |
1638 | } |
1639 | |
1640 | static int sdma_v5_2_set_clockgating_state(void *handle, |
1641 | enum amd_clockgating_state state) |
1642 | { |
1643 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1644 | |
1645 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) |
1646 | return 0; |
1647 | |
1648 | switch (adev->ip_versions[SDMA0_HWIP][0]) { |
1649 | case IP_VERSION(5, 2, 0)(((5) << 16) | ((2) << 8) | (0)): |
1650 | case IP_VERSION(5, 2, 2)(((5) << 16) | ((2) << 8) | (2)): |
1651 | case IP_VERSION(5, 2, 1)(((5) << 16) | ((2) << 8) | (1)): |
1652 | case IP_VERSION(5, 2, 4)(((5) << 16) | ((2) << 8) | (4)): |
1653 | case IP_VERSION(5, 2, 5)(((5) << 16) | ((2) << 8) | (5)): |
1654 | case IP_VERSION(5, 2, 6)(((5) << 16) | ((2) << 8) | (6)): |
1655 | case IP_VERSION(5, 2, 3)(((5) << 16) | ((2) << 8) | (3)): |
1656 | sdma_v5_2_update_medium_grain_clock_gating(adev, |
1657 | state == AMD_CG_STATE_GATE); |
1658 | sdma_v5_2_update_medium_grain_light_sleep(adev, |
1659 | state == AMD_CG_STATE_GATE); |
1660 | break; |
1661 | default: |
1662 | break; |
1663 | } |
1664 | |
1665 | return 0; |
1666 | } |
1667 | |
1668 | static int sdma_v5_2_set_powergating_state(void *handle, |
1669 | enum amd_powergating_state state) |
1670 | { |
1671 | return 0; |
1672 | } |
1673 | |
1674 | static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags) |
1675 | { |
1676 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1677 | int data; |
1678 | |
1679 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) |
1680 | *flags = 0; |
1681 | |
1682 | /* AMD_CG_SUPPORT_SDMA_MGCG */ |
1683 | data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL))amdgpu_device_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x001b )), 0); |
1684 | if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK0x02000000L)) |
1685 | *flags |= AMD_CG_SUPPORT_SDMA_MGCG(1ULL << 11); |
1686 | |
1687 | /* AMD_CG_SUPPORT_SDMA_LS */ |
1688 | data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL))amdgpu_kiq_rreg(adev, (sdma_v5_2_get_reg_offset(adev, 0, 0x001a ))); |
1689 | if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x00000100L) |
1690 | *flags |= AMD_CG_SUPPORT_SDMA_LS(1ULL << 10); |
1691 | } |
1692 | |
1693 | static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring) |
1694 | { |
1695 | struct amdgpu_device *adev = ring->adev; |
1696 | |
1697 | /* SDMA 5.2.3 (RMB) FW doesn't seem to properly |
1698 | * disallow GFXOFF in some cases leading to |
1699 | * hangs in SDMA. Disallow GFXOFF while SDMA is active. |
1700 | * We can probably just limit this to 5.2.3, |
1701 | * but it shouldn't hurt for other parts since |
1702 | * this GFXOFF will be disallowed anyway when SDMA is |
1703 | * active, this just makes it explicit. |
1704 | */ |
1705 | amdgpu_gfx_off_ctrl(adev, false0); |
1706 | } |
1707 | |
1708 | static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring) |
1709 | { |
1710 | struct amdgpu_device *adev = ring->adev; |
1711 | |
1712 | /* SDMA 5.2.3 (RMB) FW doesn't seem to properly |
1713 | * disallow GFXOFF in some cases leading to |
1714 | * hangs in SDMA. Allow GFXOFF when SDMA is complete. |
1715 | */ |
1716 | amdgpu_gfx_off_ctrl(adev, true1); |
1717 | } |
1718 | |
1719 | const struct amd_ip_funcs sdma_v5_2_ip_funcs = { |
1720 | .name = "sdma_v5_2", |
1721 | .early_init = sdma_v5_2_early_init, |
1722 | .late_init = NULL((void *)0), |
1723 | .sw_init = sdma_v5_2_sw_init, |
1724 | .sw_fini = sdma_v5_2_sw_fini, |
1725 | .hw_init = sdma_v5_2_hw_init, |
1726 | .hw_fini = sdma_v5_2_hw_fini, |
1727 | .suspend = sdma_v5_2_suspend, |
1728 | .resume = sdma_v5_2_resume, |
1729 | .is_idle = sdma_v5_2_is_idle, |
1730 | .wait_for_idle = sdma_v5_2_wait_for_idle, |
1731 | .soft_reset = sdma_v5_2_soft_reset, |
1732 | .set_clockgating_state = sdma_v5_2_set_clockgating_state, |
1733 | .set_powergating_state = sdma_v5_2_set_powergating_state, |
1734 | .get_clockgating_state = sdma_v5_2_get_clockgating_state, |
1735 | }; |
1736 | |
1737 | static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { |
1738 | .type = AMDGPU_RING_TYPE_SDMA, |
1739 | .align_mask = 0xf, |
1740 | .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0), |
1741 | .support_64bit_ptrs = true1, |
1742 | .secure_submission_supported = true1, |
1743 | .vmhub = AMDGPU_GFXHUB_00, |
1744 | .get_rptr = sdma_v5_2_ring_get_rptr, |
1745 | .get_wptr = sdma_v5_2_ring_get_wptr, |
1746 | .set_wptr = sdma_v5_2_ring_set_wptr, |
1747 | .emit_frame_size = |
1748 | 5 + /* sdma_v5_2_ring_init_cond_exec */ |
1749 | 6 + /* sdma_v5_2_ring_emit_hdp_flush */ |
1750 | 3 + /* hdp_invalidate */ |
1751 | 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ |
1752 | /* sdma_v5_2_ring_emit_vm_flush */ |
1753 | SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 3 + |
1754 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 6 + |
1755 | 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ |
1756 | .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ |
1757 | .emit_ib = sdma_v5_2_ring_emit_ib, |
1758 | .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, |
1759 | .emit_fence = sdma_v5_2_ring_emit_fence, |
1760 | .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, |
1761 | .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, |
1762 | .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, |
1763 | .test_ring = sdma_v5_2_ring_test_ring, |
1764 | .test_ib = sdma_v5_2_ring_test_ib, |
1765 | .insert_nop = sdma_v5_2_ring_insert_nop, |
1766 | .pad_ib = sdma_v5_2_ring_pad_ib, |
1767 | .begin_use = sdma_v5_2_ring_begin_use, |
1768 | .end_use = sdma_v5_2_ring_end_use, |
1769 | .emit_wreg = sdma_v5_2_ring_emit_wreg, |
1770 | .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, |
1771 | .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, |
1772 | .init_cond_exec = sdma_v5_2_ring_init_cond_exec, |
1773 | .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, |
1774 | .preempt_ib = sdma_v5_2_ring_preempt_ib, |
1775 | }; |
1776 | |
1777 | static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) |
1778 | { |
1779 | int i; |
1780 | |
1781 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1782 | adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; |
1783 | adev->sdma.instance[i].ring.me = i; |
1784 | } |
1785 | } |
1786 | |
1787 | static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { |
1788 | .set = sdma_v5_2_set_trap_irq_state, |
1789 | .process = sdma_v5_2_process_trap_irq, |
1790 | }; |
1791 | |
1792 | static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { |
1793 | .process = sdma_v5_2_process_illegal_inst_irq, |
1794 | }; |
1795 | |
1796 | static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) |
1797 | { |
1798 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + |
1799 | adev->sdma.num_instances; |
1800 | adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; |
1801 | adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; |
1802 | } |
1803 | |
1804 | /** |
1805 | * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine |
1806 | * |
1807 | * @ib: indirect buffer to copy to |
1808 | * @src_offset: src GPU address |
1809 | * @dst_offset: dst GPU address |
1810 | * @byte_count: number of bytes to xfer |
1811 | * @tmz: if a secure copy should be used |
1812 | * |
1813 | * Copy GPU buffers using the DMA engine. |
1814 | * Used by the amdgpu ttm implementation to move pages if |
1815 | * registered as the asic copy callback. |
1816 | */ |
1817 | static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, |
1818 | uint64_t src_offset, |
1819 | uint64_t dst_offset, |
1820 | uint32_t byte_count, |
1821 | bool_Bool tmz) |
1822 | { |
1823 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) | |
1824 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8) | |
1825 | SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0)(((tmz ? 1 : 0) & 0x00000001) << 18); |
1826 | ib->ptr[ib->length_dw++] = byte_count - 1; |
1827 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ |
1828 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset)((u32)(src_offset)); |
1829 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset)((u32)(((src_offset) >> 16) >> 16)); |
1830 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset)); |
1831 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16)); |
1832 | } |
1833 | |
1834 | /** |
1835 | * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine |
1836 | * |
1837 | * @ib: indirect buffer to fill |
1838 | * @src_data: value to write to buffer |
1839 | * @dst_offset: dst GPU address |
1840 | * @byte_count: number of bytes to xfer |
1841 | * |
1842 | * Fill GPU buffers using the DMA engine. |
1843 | */ |
1844 | static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, |
1845 | uint32_t src_data, |
1846 | uint64_t dst_offset, |
1847 | uint32_t byte_count) |
1848 | { |
1849 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)(((11) & 0x000000FF) << 0); |
1850 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset)); |
1851 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16)); |
1852 | ib->ptr[ib->length_dw++] = src_data; |
1853 | ib->ptr[ib->length_dw++] = byte_count - 1; |
1854 | } |
1855 | |
1856 | static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { |
1857 | .copy_max_bytes = 0x400000, |
1858 | .copy_num_dw = 7, |
1859 | .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, |
1860 | |
1861 | .fill_max_bytes = 0x400000, |
1862 | .fill_num_dw = 5, |
1863 | .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, |
1864 | }; |
1865 | |
1866 | static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) |
1867 | { |
1868 | if (adev->mman.buffer_funcs == NULL((void *)0)) { |
1869 | adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; |
1870 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; |
1871 | } |
1872 | } |
1873 | |
1874 | static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { |
1875 | .copy_pte_num_dw = 7, |
1876 | .copy_pte = sdma_v5_2_vm_copy_pte, |
1877 | .write_pte = sdma_v5_2_vm_write_pte, |
1878 | .set_pte_pde = sdma_v5_2_vm_set_pte_pde, |
1879 | }; |
1880 | |
1881 | static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) |
1882 | { |
1883 | unsigned i; |
1884 | |
1885 | if (adev->vm_manager.vm_pte_funcs == NULL((void *)0)) { |
1886 | adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; |
1887 | for (i = 0; i < adev->sdma.num_instances; i++) { |
1888 | adev->vm_manager.vm_pte_scheds[i] = |
1889 | &adev->sdma.instance[i].ring.sched; |
1890 | } |
1891 | adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; |
1892 | } |
1893 | } |
1894 | |
1895 | const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { |
1896 | .type = AMD_IP_BLOCK_TYPE_SDMA, |
1897 | .major = 5, |
1898 | .minor = 2, |
1899 | .rev = 0, |
1900 | .funcs = &sdma_v5_2_ip_funcs, |
1901 | }; |