| File: | dev/pci/drm/amd/display/dc/dc_dmub_srv.c |
| Warning: | line 452, column 43 Dereference of null pointer |
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| 1 | /* | ||||||||||
| 2 | * Copyright 2019 Advanced Micro Devices, Inc. | ||||||||||
| 3 | * | ||||||||||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||||||||||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||||||||||
| 6 | * to deal in the Software without restriction, including without limitation | ||||||||||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||||||||||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||||||||||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||||||||||
| 10 | * | ||||||||||
| 11 | * The above copyright notice and this permission notice shall be included in | ||||||||||
| 12 | * all copies or substantial portions of the Software. | ||||||||||
| 13 | * | ||||||||||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||||||||||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||||||||||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||||||||||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||||||||||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||||||||||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||||||||||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||||||||||
| 21 | * | ||||||||||
| 22 | * Authors: AMD | ||||||||||
| 23 | * | ||||||||||
| 24 | */ | ||||||||||
| 25 | |||||||||||
| 26 | #include "dc.h" | ||||||||||
| 27 | #include "dc_dmub_srv.h" | ||||||||||
| 28 | #include "../dmub/dmub_srv.h" | ||||||||||
| 29 | #include "dm_helpers.h" | ||||||||||
| 30 | #include "dc_hw_types.h" | ||||||||||
| 31 | #include "core_types.h" | ||||||||||
| 32 | #include "../basics/conversion.h" | ||||||||||
| 33 | #include "cursor_reg_cache.h" | ||||||||||
| 34 | |||||||||||
| 35 | #define CTXdc_dmub_srv->ctx dc_dmub_srv->ctx | ||||||||||
| 36 | #define DC_LOGGERdc_dmub_srv->ctx->logger CTXdc_dmub_srv->ctx->logger | ||||||||||
| 37 | |||||||||||
| 38 | static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, | ||||||||||
| 39 | struct dmub_srv *dmub) | ||||||||||
| 40 | { | ||||||||||
| 41 | dc_srv->dmub = dmub; | ||||||||||
| 42 | dc_srv->ctx = dc->ctx; | ||||||||||
| 43 | } | ||||||||||
| 44 | |||||||||||
| 45 | struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) | ||||||||||
| 46 | { | ||||||||||
| 47 | struct dc_dmub_srv *dc_srv = | ||||||||||
| 48 | kzalloc(sizeof(struct dc_dmub_srv), GFP_KERNEL(0x0001 | 0x0004)); | ||||||||||
| 49 | |||||||||||
| 50 | if (dc_srv == NULL((void *)0)) { | ||||||||||
| 51 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 51); do {} while (0); } while (0); | ||||||||||
| 52 | return NULL((void *)0); | ||||||||||
| 53 | } | ||||||||||
| 54 | |||||||||||
| 55 | dc_dmub_srv_construct(dc_srv, dc, dmub); | ||||||||||
| 56 | |||||||||||
| 57 | return dc_srv; | ||||||||||
| 58 | } | ||||||||||
| 59 | |||||||||||
| 60 | void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv) | ||||||||||
| 61 | { | ||||||||||
| 62 | if (*dmub_srv) { | ||||||||||
| 63 | kfree(*dmub_srv); | ||||||||||
| 64 | *dmub_srv = NULL((void *)0); | ||||||||||
| 65 | } | ||||||||||
| 66 | } | ||||||||||
| 67 | |||||||||||
| 68 | void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv, | ||||||||||
| 69 | union dmub_rb_cmd *cmd) | ||||||||||
| 70 | { | ||||||||||
| 71 | struct dmub_srv *dmub = dc_dmub_srv->dmub; | ||||||||||
| 72 | struct dc_context *dc_ctx = dc_dmub_srv->ctx; | ||||||||||
| 73 | enum dmub_status status; | ||||||||||
| 74 | |||||||||||
| 75 | status = dmub_srv_cmd_queue(dmub, cmd); | ||||||||||
| 76 | if (status == DMUB_STATUS_OK) | ||||||||||
| 77 | return; | ||||||||||
| 78 | |||||||||||
| 79 | if (status != DMUB_STATUS_QUEUE_FULL) | ||||||||||
| 80 | goto error; | ||||||||||
| 81 | |||||||||||
| 82 | /* Execute and wait for queue to become empty again. */ | ||||||||||
| 83 | dc_dmub_srv_cmd_execute(dc_dmub_srv); | ||||||||||
| 84 | dc_dmub_srv_wait_idle(dc_dmub_srv); | ||||||||||
| 85 | |||||||||||
| 86 | /* Requeue the command. */ | ||||||||||
| 87 | status = dmub_srv_cmd_queue(dmub, cmd); | ||||||||||
| 88 | if (status == DMUB_STATUS_OK) | ||||||||||
| 89 | return; | ||||||||||
| 90 | |||||||||||
| 91 | error: | ||||||||||
| 92 | DC_ERROR("Error queuing DMUB command: status=%d\n", status)do { (void)(dc_ctx); __drm_err("Error queuing DMUB command: status=%d\n" , status); } while (0); | ||||||||||
| 93 | dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); | ||||||||||
| 94 | } | ||||||||||
| 95 | |||||||||||
| 96 | void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) | ||||||||||
| 97 | { | ||||||||||
| 98 | struct dmub_srv *dmub = dc_dmub_srv->dmub; | ||||||||||
| 99 | struct dc_context *dc_ctx = dc_dmub_srv->ctx; | ||||||||||
| 100 | enum dmub_status status; | ||||||||||
| 101 | |||||||||||
| 102 | status = dmub_srv_cmd_execute(dmub); | ||||||||||
| 103 | if (status != DMUB_STATUS_OK) { | ||||||||||
| 104 | DC_ERROR("Error starting DMUB execution: status=%d\n", status)do { (void)(dc_ctx); __drm_err("Error starting DMUB execution: status=%d\n" , status); } while (0); | ||||||||||
| 105 | dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); | ||||||||||
| 106 | } | ||||||||||
| 107 | } | ||||||||||
| 108 | |||||||||||
| 109 | void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) | ||||||||||
| 110 | { | ||||||||||
| 111 | struct dmub_srv *dmub = dc_dmub_srv->dmub; | ||||||||||
| 112 | struct dc_context *dc_ctx = dc_dmub_srv->ctx; | ||||||||||
| 113 | enum dmub_status status; | ||||||||||
| 114 | |||||||||||
| 115 | status = dmub_srv_wait_for_idle(dmub, 100000); | ||||||||||
| 116 | if (status != DMUB_STATUS_OK) { | ||||||||||
| 117 | DC_ERROR("Error waiting for DMUB idle: status=%d\n", status)do { (void)(dc_ctx); __drm_err("Error waiting for DMUB idle: status=%d\n" , status); } while (0); | ||||||||||
| 118 | dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); | ||||||||||
| 119 | } | ||||||||||
| 120 | } | ||||||||||
| 121 | |||||||||||
| 122 | void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv) | ||||||||||
| 123 | { | ||||||||||
| 124 | struct dmub_srv *dmub = dmub_srv->dmub; | ||||||||||
| 125 | struct dc_context *dc_ctx = dmub_srv->ctx; | ||||||||||
| 126 | enum dmub_status status = DMUB_STATUS_OK; | ||||||||||
| 127 | |||||||||||
| 128 | status = dmub_srv_clear_inbox0_ack(dmub); | ||||||||||
| 129 | if (status != DMUB_STATUS_OK) { | ||||||||||
| 130 | DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status)do { (void)(dc_ctx); __drm_err("Error clearing INBOX0 ack: status=%d\n" , status); } while (0); | ||||||||||
| 131 | dc_dmub_srv_log_diagnostic_data(dmub_srv); | ||||||||||
| 132 | } | ||||||||||
| 133 | } | ||||||||||
| 134 | |||||||||||
| 135 | void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv) | ||||||||||
| 136 | { | ||||||||||
| 137 | struct dmub_srv *dmub = dmub_srv->dmub; | ||||||||||
| 138 | struct dc_context *dc_ctx = dmub_srv->ctx; | ||||||||||
| 139 | enum dmub_status status = DMUB_STATUS_OK; | ||||||||||
| 140 | |||||||||||
| 141 | status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); | ||||||||||
| 142 | if (status != DMUB_STATUS_OK) { | ||||||||||
| 143 | DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n")do { (void)(dc_ctx); __drm_err("Error waiting for INBOX0 HW Lock Ack\n" ); } while (0); | ||||||||||
| 144 | dc_dmub_srv_log_diagnostic_data(dmub_srv); | ||||||||||
| 145 | } | ||||||||||
| 146 | } | ||||||||||
| 147 | |||||||||||
| 148 | void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, | ||||||||||
| 149 | union dmub_inbox0_data_register data) | ||||||||||
| 150 | { | ||||||||||
| 151 | struct dmub_srv *dmub = dmub_srv->dmub; | ||||||||||
| 152 | struct dc_context *dc_ctx = dmub_srv->ctx; | ||||||||||
| 153 | enum dmub_status status = DMUB_STATUS_OK; | ||||||||||
| 154 | |||||||||||
| 155 | status = dmub_srv_send_inbox0_cmd(dmub, data); | ||||||||||
| 156 | if (status != DMUB_STATUS_OK) { | ||||||||||
| 157 | DC_ERROR("Error sending INBOX0 cmd\n")do { (void)(dc_ctx); __drm_err("Error sending INBOX0 cmd\n"); } while (0); | ||||||||||
| 158 | dc_dmub_srv_log_diagnostic_data(dmub_srv); | ||||||||||
| 159 | } | ||||||||||
| 160 | } | ||||||||||
| 161 | |||||||||||
| 162 | bool_Bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub_rb_cmd *cmd) | ||||||||||
| 163 | { | ||||||||||
| 164 | struct dmub_srv *dmub; | ||||||||||
| 165 | enum dmub_status status; | ||||||||||
| 166 | |||||||||||
| 167 | if (!dc_dmub_srv || !dc_dmub_srv->dmub) | ||||||||||
| 168 | return false0; | ||||||||||
| 169 | |||||||||||
| 170 | dmub = dc_dmub_srv->dmub; | ||||||||||
| 171 | |||||||||||
| 172 | status = dmub_srv_cmd_with_reply_data(dmub, cmd); | ||||||||||
| 173 | if (status != DMUB_STATUS_OK) { | ||||||||||
| 174 | DC_LOG_DEBUG("No reply for DMUB command: status=%d\n", status)___drm_dbg(((void *)0), DRM_UT_KMS, "No reply for DMUB command: status=%d\n" , status); | ||||||||||
| 175 | return false0; | ||||||||||
| 176 | } | ||||||||||
| 177 | |||||||||||
| 178 | return true1; | ||||||||||
| 179 | } | ||||||||||
| 180 | |||||||||||
| 181 | void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv) | ||||||||||
| 182 | { | ||||||||||
| 183 | struct dmub_srv *dmub = dc_dmub_srv->dmub; | ||||||||||
| 184 | struct dc_context *dc_ctx = dc_dmub_srv->ctx; | ||||||||||
| 185 | enum dmub_status status; | ||||||||||
| 186 | |||||||||||
| 187 | for (;;) { | ||||||||||
| 188 | /* Wait up to a second for PHY init. */ | ||||||||||
| 189 | status = dmub_srv_wait_for_phy_init(dmub, 1000000); | ||||||||||
| 190 | if (status == DMUB_STATUS_OK) | ||||||||||
| 191 | /* Initialization OK */ | ||||||||||
| 192 | break; | ||||||||||
| 193 | |||||||||||
| 194 | DC_ERROR("DMCUB PHY init failed: status=%d\n", status)do { (void)(dc_ctx); __drm_err("DMCUB PHY init failed: status=%d\n" , status); } while (0); | ||||||||||
| 195 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c" , 195); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||||||||
| 196 | |||||||||||
| 197 | if (status != DMUB_STATUS_TIMEOUT) | ||||||||||
| 198 | /* | ||||||||||
| 199 | * Server likely initialized or we don't have | ||||||||||
| 200 | * DMCUB HW support - this won't end. | ||||||||||
| 201 | */ | ||||||||||
| 202 | break; | ||||||||||
| 203 | |||||||||||
| 204 | /* Continue spinning so we don't hang the ASIC. */ | ||||||||||
| 205 | } | ||||||||||
| 206 | } | ||||||||||
| 207 | |||||||||||
| 208 | bool_Bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv, | ||||||||||
| 209 | unsigned int stream_mask) | ||||||||||
| 210 | { | ||||||||||
| 211 | struct dmub_srv *dmub; | ||||||||||
| 212 | const uint32_t timeout = 30; | ||||||||||
| 213 | |||||||||||
| 214 | if (!dc_dmub_srv || !dc_dmub_srv->dmub) | ||||||||||
| 215 | return false0; | ||||||||||
| 216 | |||||||||||
| 217 | dmub = dc_dmub_srv->dmub; | ||||||||||
| 218 | |||||||||||
| 219 | return dmub_srv_send_gpint_command( | ||||||||||
| 220 | dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK, | ||||||||||
| 221 | stream_mask, timeout) == DMUB_STATUS_OK; | ||||||||||
| 222 | } | ||||||||||
| 223 | |||||||||||
| 224 | bool_Bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv) | ||||||||||
| 225 | { | ||||||||||
| 226 | struct dmub_srv *dmub; | ||||||||||
| 227 | struct dc_context *dc_ctx; | ||||||||||
| 228 | union dmub_fw_boot_status boot_status; | ||||||||||
| 229 | enum dmub_status status; | ||||||||||
| 230 | |||||||||||
| 231 | if (!dc_dmub_srv || !dc_dmub_srv->dmub) | ||||||||||
| 232 | return false0; | ||||||||||
| 233 | |||||||||||
| 234 | dmub = dc_dmub_srv->dmub; | ||||||||||
| 235 | dc_ctx = dc_dmub_srv->ctx; | ||||||||||
| 236 | |||||||||||
| 237 | status = dmub_srv_get_fw_boot_status(dmub, &boot_status); | ||||||||||
| 238 | if (status != DMUB_STATUS_OK) { | ||||||||||
| 239 | DC_ERROR("Error querying DMUB boot status: error=%d\n", status)do { (void)(dc_ctx); __drm_err("Error querying DMUB boot status: error=%d\n" , status); } while (0); | ||||||||||
| 240 | return false0; | ||||||||||
| 241 | } | ||||||||||
| 242 | |||||||||||
| 243 | return boot_status.bits.restore_required; | ||||||||||
| 244 | } | ||||||||||
| 245 | |||||||||||
| 246 | bool_Bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry) | ||||||||||
| 247 | { | ||||||||||
| 248 | struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub; | ||||||||||
| 249 | return dmub_srv_get_outbox0_msg(dmub, entry); | ||||||||||
| 250 | } | ||||||||||
| 251 | |||||||||||
| 252 | void dc_dmub_trace_event_control(struct dc *dc, bool_Bool enable) | ||||||||||
| 253 | { | ||||||||||
| 254 | dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable); | ||||||||||
| 255 | } | ||||||||||
| 256 | |||||||||||
| 257 | void dc_dmub_srv_drr_update_cmd(struct dc *dc, uint32_t tg_inst, uint32_t vtotal_min, uint32_t vtotal_max) | ||||||||||
| 258 | { | ||||||||||
| 259 | union dmub_rb_cmd cmd = { 0 }; | ||||||||||
| 260 | |||||||||||
| 261 | cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; | ||||||||||
| 262 | cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_DRR_UPDATE; | ||||||||||
| 263 | cmd.drr_update.dmub_optc_state_req.v_total_max = vtotal_max; | ||||||||||
| 264 | cmd.drr_update.dmub_optc_state_req.v_total_min = vtotal_min; | ||||||||||
| 265 | cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; | ||||||||||
| 266 | |||||||||||
| 267 | cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); | ||||||||||
| 268 | |||||||||||
| 269 | // Send the command to the DMCUB. | ||||||||||
| 270 | dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); | ||||||||||
| 271 | dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); | ||||||||||
| 272 | dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); | ||||||||||
| 273 | } | ||||||||||
| 274 | |||||||||||
| 275 | void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst) | ||||||||||
| 276 | { | ||||||||||
| 277 | union dmub_rb_cmd cmd = { 0 }; | ||||||||||
| 278 | |||||||||||
| 279 | cmd.drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; | ||||||||||
| 280 | cmd.drr_update.header.sub_type = DMUB_CMD__FAMS_SET_MANUAL_TRIGGER; | ||||||||||
| 281 | cmd.drr_update.dmub_optc_state_req.tg_inst = tg_inst; | ||||||||||
| 282 | |||||||||||
| 283 | cmd.drr_update.header.payload_bytes = sizeof(cmd.drr_update) - sizeof(cmd.drr_update.header); | ||||||||||
| 284 | |||||||||||
| 285 | // Send the command to the DMCUB. | ||||||||||
| 286 | dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); | ||||||||||
| 287 | dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); | ||||||||||
| 288 | dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); | ||||||||||
| 289 | } | ||||||||||
| 290 | |||||||||||
| 291 | static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream) | ||||||||||
| 292 | { | ||||||||||
| 293 | uint8_t pipes = 0; | ||||||||||
| 294 | int i = 0; | ||||||||||
| 295 | |||||||||||
| 296 | for (i = 0; i < MAX_PIPES6; i++) { | ||||||||||
| 297 | struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||||||||
| 298 | |||||||||||
| 299 | if (pipe->stream == stream && pipe->stream_res.tg) | ||||||||||
| 300 | pipes = i; | ||||||||||
| 301 | } | ||||||||||
| 302 | return pipes; | ||||||||||
| 303 | } | ||||||||||
| 304 | |||||||||||
| 305 | static int dc_dmub_srv_get_timing_generator_offset(struct dc *dc, struct dc_stream_state *stream) | ||||||||||
| 306 | { | ||||||||||
| 307 | int tg_inst = 0; | ||||||||||
| 308 | int i = 0; | ||||||||||
| 309 | |||||||||||
| 310 | for (i = 0; i < MAX_PIPES6; i++) { | ||||||||||
| 311 | struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; | ||||||||||
| 312 | |||||||||||
| 313 | if (pipe->stream == stream && pipe->stream_res.tg) { | ||||||||||
| 314 | tg_inst = pipe->stream_res.tg->inst; | ||||||||||
| 315 | break; | ||||||||||
| 316 | } | ||||||||||
| 317 | } | ||||||||||
| 318 | return tg_inst; | ||||||||||
| 319 | } | ||||||||||
| 320 | |||||||||||
| 321 | bool_Bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool_Bool should_manage_pstate, struct dc_state *context) | ||||||||||
| 322 | { | ||||||||||
| 323 | union dmub_rb_cmd cmd = { 0 }; | ||||||||||
| 324 | struct dmub_cmd_fw_assisted_mclk_switch_config *config_data = &cmd.fw_assisted_mclk_switch.config_data; | ||||||||||
| 325 | int i = 0; | ||||||||||
| 326 | int ramp_up_num_steps = 1; // TODO: Ramp is currently disabled. Reenable it. | ||||||||||
| 327 | uint8_t visual_confirm_enabled; | ||||||||||
| 328 | |||||||||||
| 329 | if (dc == NULL((void *)0)) | ||||||||||
| 330 | return false0; | ||||||||||
| 331 | |||||||||||
| 332 | visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS; | ||||||||||
| 333 | |||||||||||
| 334 | // Format command. | ||||||||||
| 335 | cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; | ||||||||||
| 336 | cmd.fw_assisted_mclk_switch.header.sub_type = DMUB_CMD__FAMS_SETUP_FW_CTRL; | ||||||||||
| 337 | cmd.fw_assisted_mclk_switch.config_data.fams_enabled = should_manage_pstate; | ||||||||||
| 338 | cmd.fw_assisted_mclk_switch.config_data.visual_confirm_enabled = visual_confirm_enabled; | ||||||||||
| 339 | |||||||||||
| 340 | for (i = 0; context && i < context->stream_count; i++) { | ||||||||||
| 341 | struct dc_stream_state *stream = context->streams[i]; | ||||||||||
| 342 | uint8_t min_refresh_in_hz = (stream->timing.min_refresh_in_uhz + 999999) / 1000000; | ||||||||||
| 343 | int tg_inst = dc_dmub_srv_get_timing_generator_offset(dc, stream); | ||||||||||
| 344 | |||||||||||
| 345 | config_data->pipe_data[tg_inst].pix_clk_100hz = stream->timing.pix_clk_100hz; | ||||||||||
| 346 | config_data->pipe_data[tg_inst].min_refresh_in_hz = min_refresh_in_hz; | ||||||||||
| 347 | config_data->pipe_data[tg_inst].max_ramp_step = ramp_up_num_steps; | ||||||||||
| 348 | config_data->pipe_data[tg_inst].pipes = dc_dmub_srv_get_pipes_for_stream(dc, stream); | ||||||||||
| 349 | } | ||||||||||
| 350 | |||||||||||
| 351 | cmd.fw_assisted_mclk_switch.header.payload_bytes = | ||||||||||
| 352 | sizeof(cmd.fw_assisted_mclk_switch) - sizeof(cmd.fw_assisted_mclk_switch.header); | ||||||||||
| 353 | |||||||||||
| 354 | // Send the command to the DMCUB. | ||||||||||
| 355 | dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); | ||||||||||
| 356 | dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); | ||||||||||
| 357 | dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); | ||||||||||
| 358 | |||||||||||
| 359 | return true1; | ||||||||||
| 360 | } | ||||||||||
| 361 | |||||||||||
| 362 | void dc_dmub_srv_query_caps_cmd(struct dmub_srv *dmub) | ||||||||||
| 363 | { | ||||||||||
| 364 | union dmub_rb_cmd cmd = { 0 }; | ||||||||||
| 365 | enum dmub_status status; | ||||||||||
| 366 | |||||||||||
| 367 | if (!dmub) { | ||||||||||
| 368 | return; | ||||||||||
| 369 | } | ||||||||||
| 370 | |||||||||||
| 371 | memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd))); | ||||||||||
| 372 | |||||||||||
| 373 | /* Prepare fw command */ | ||||||||||
| 374 | cmd.query_feature_caps.header.type = DMUB_CMD__QUERY_FEATURE_CAPS; | ||||||||||
| 375 | cmd.query_feature_caps.header.sub_type = 0; | ||||||||||
| 376 | cmd.query_feature_caps.header.ret_status = 1; | ||||||||||
| 377 | cmd.query_feature_caps.header.payload_bytes = sizeof(struct dmub_cmd_query_feature_caps_data); | ||||||||||
| 378 | |||||||||||
| 379 | /* Send command to fw */ | ||||||||||
| 380 | status = dmub_srv_cmd_with_reply_data(dmub, &cmd); | ||||||||||
| 381 | |||||||||||
| 382 | ASSERT(status == DMUB_STATUS_OK)do { if (({ static int __warned; int __ret = !!(!(status == DMUB_STATUS_OK )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(status == DMUB_STATUS_OK)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c" , 382); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||||||||
| 383 | |||||||||||
| 384 | /* If command was processed, copy feature caps to dmub srv */ | ||||||||||
| 385 | if (status == DMUB_STATUS_OK && | ||||||||||
| 386 | cmd.query_feature_caps.header.ret_status == 0) { | ||||||||||
| 387 | memcpy(&dmub->feature_caps,__builtin_memcpy((&dmub->feature_caps), (&cmd.query_feature_caps .query_feature_caps_data), (sizeof(struct dmub_feature_caps)) ) | ||||||||||
| 388 | &cmd.query_feature_caps.query_feature_caps_data,__builtin_memcpy((&dmub->feature_caps), (&cmd.query_feature_caps .query_feature_caps_data), (sizeof(struct dmub_feature_caps)) ) | ||||||||||
| 389 | sizeof(struct dmub_feature_caps))__builtin_memcpy((&dmub->feature_caps), (&cmd.query_feature_caps .query_feature_caps_data), (sizeof(struct dmub_feature_caps)) ); | ||||||||||
| 390 | } | ||||||||||
| 391 | } | ||||||||||
| 392 | |||||||||||
| 393 | void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pipe_ctx) | ||||||||||
| 394 | { | ||||||||||
| 395 | union dmub_rb_cmd cmd = { 0 }; | ||||||||||
| 396 | enum dmub_status status; | ||||||||||
| 397 | unsigned int panel_inst = 0; | ||||||||||
| 398 | |||||||||||
| 399 | dc_get_edp_link_panel_inst(dc, pipe_ctx->stream->link, &panel_inst); | ||||||||||
| 400 | |||||||||||
| 401 | memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd))); | ||||||||||
| 402 | |||||||||||
| 403 | // Prepare fw command | ||||||||||
| 404 | cmd.visual_confirm_color.header.type = DMUB_CMD__GET_VISUAL_CONFIRM_COLOR; | ||||||||||
| 405 | cmd.visual_confirm_color.header.sub_type = 0; | ||||||||||
| 406 | cmd.visual_confirm_color.header.ret_status = 1; | ||||||||||
| 407 | cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data); | ||||||||||
| 408 | cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst; | ||||||||||
| 409 | |||||||||||
| 410 | // Send command to fw | ||||||||||
| 411 | status = dmub_srv_cmd_with_reply_data(dc->ctx->dmub_srv->dmub, &cmd); | ||||||||||
| 412 | |||||||||||
| 413 | ASSERT(status == DMUB_STATUS_OK)do { if (({ static int __warned; int __ret = !!(!(status == DMUB_STATUS_OK )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(status == DMUB_STATUS_OK)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c" , 413); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||||||||
| 414 | |||||||||||
| 415 | // If command was processed, copy feature caps to dmub srv | ||||||||||
| 416 | if (status == DMUB_STATUS_OK && | ||||||||||
| 417 | cmd.visual_confirm_color.header.ret_status == 0) { | ||||||||||
| 418 | memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,__builtin_memcpy((&dc->ctx->dmub_srv->dmub->visual_confirm_color ), (&cmd.visual_confirm_color.visual_confirm_color_data), (sizeof(struct dmub_visual_confirm_color))) | ||||||||||
| 419 | &cmd.visual_confirm_color.visual_confirm_color_data,__builtin_memcpy((&dc->ctx->dmub_srv->dmub->visual_confirm_color ), (&cmd.visual_confirm_color.visual_confirm_color_data), (sizeof(struct dmub_visual_confirm_color))) | ||||||||||
| 420 | sizeof(struct dmub_visual_confirm_color))__builtin_memcpy((&dc->ctx->dmub_srv->dmub->visual_confirm_color ), (&cmd.visual_confirm_color.visual_confirm_color_data), (sizeof(struct dmub_visual_confirm_color))); | ||||||||||
| 421 | } | ||||||||||
| 422 | } | ||||||||||
| 423 | |||||||||||
| 424 | #ifdef CONFIG_DRM_AMD_DC_DCN1 | ||||||||||
| 425 | /** | ||||||||||
| 426 | * *********************************************************************************************** | ||||||||||
| 427 | * populate_subvp_cmd_drr_info: Helper to populate DRR pipe info for the DMCUB subvp command | ||||||||||
| 428 | * | ||||||||||
| 429 | * Populate the DMCUB SubVP command with DRR pipe info. All the information required for calculating | ||||||||||
| 430 | * the SubVP + DRR microschedule is populated here. | ||||||||||
| 431 | * | ||||||||||
| 432 | * High level algorithm: | ||||||||||
| 433 | * 1. Get timing for SubVP pipe, phantom pipe, and DRR pipe | ||||||||||
| 434 | * 2. Calculate the min and max vtotal which supports SubVP + DRR microschedule | ||||||||||
| 435 | * 3. Populate the drr_info with the min and max supported vtotal values | ||||||||||
| 436 | * | ||||||||||
| 437 | * @param [in] dc: current dc state | ||||||||||
| 438 | * @param [in] subvp_pipe: pipe_ctx for the SubVP pipe | ||||||||||
| 439 | * @param [in] vblank_pipe: pipe_ctx for the DRR pipe | ||||||||||
| 440 | * @param [in] pipe_data: Pipe data which stores the VBLANK/DRR info | ||||||||||
| 441 | * | ||||||||||
| 442 | * @return: void | ||||||||||
| 443 | * | ||||||||||
| 444 | * *********************************************************************************************** | ||||||||||
| 445 | */ | ||||||||||
| 446 | static void populate_subvp_cmd_drr_info(struct dc *dc, | ||||||||||
| 447 | struct pipe_ctx *subvp_pipe, | ||||||||||
| 448 | struct pipe_ctx *vblank_pipe, | ||||||||||
| 449 | struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data) | ||||||||||
| 450 | { | ||||||||||
| 451 | struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; | ||||||||||
| 452 | struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; | ||||||||||
| |||||||||||
| 453 | struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; | ||||||||||
| 454 | uint16_t drr_frame_us = 0; | ||||||||||
| 455 | uint16_t min_drr_supported_us = 0; | ||||||||||
| 456 | uint16_t max_drr_supported_us = 0; | ||||||||||
| 457 | uint16_t max_drr_vblank_us = 0; | ||||||||||
| 458 | uint16_t max_drr_mallregion_us = 0; | ||||||||||
| 459 | uint16_t mall_region_us = 0; | ||||||||||
| 460 | uint16_t prefetch_us = 0; | ||||||||||
| 461 | uint16_t subvp_active_us = 0; | ||||||||||
| 462 | uint16_t drr_active_us = 0; | ||||||||||
| 463 | uint16_t min_vtotal_supported = 0; | ||||||||||
| 464 | uint16_t max_vtotal_supported = 0; | ||||||||||
| 465 | |||||||||||
| 466 | pipe_data->pipe_config.vblank_data.drr_info.drr_in_use = true1; | ||||||||||
| 467 | pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false0; // for now don't use ramping | ||||||||||
| 468 | pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now | ||||||||||
| 469 | |||||||||||
| 470 | drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), | ||||||||||
| 471 | (((uint64_t)drr_timing->pix_clk_100hz * 100))); | ||||||||||
| 472 | // P-State allow width and FW delays already included phantom_timing->v_addressable | ||||||||||
| 473 | mall_region_us = div64_u64(((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000), | ||||||||||
| 474 | (((uint64_t)phantom_timing->pix_clk_100hz * 100))); | ||||||||||
| 475 | min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US500; | ||||||||||
| 476 | min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us), | ||||||||||
| 477 | (((uint64_t)drr_timing->h_total * 1000000))); | ||||||||||
| 478 | |||||||||||
| 479 | prefetch_us = div64_u64(((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000), | ||||||||||
| 480 | (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); | ||||||||||
| 481 | subvp_active_us = div64_u64(((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000), | ||||||||||
| 482 | (((uint64_t)main_timing->pix_clk_100hz * 100))); | ||||||||||
| 483 | drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), | ||||||||||
| 484 | (((uint64_t)drr_timing->pix_clk_100hz * 100))); | ||||||||||
| 485 | max_drr_vblank_us = div64_u64((subvp_active_us - prefetch_us - drr_active_us), 2) + drr_active_us; | ||||||||||
| 486 | max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us; | ||||||||||
| 487 | max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us; | ||||||||||
| 488 | max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us), | ||||||||||
| 489 | (((uint64_t)drr_timing->h_total * 1000000))); | ||||||||||
| 490 | |||||||||||
| 491 | pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported; | ||||||||||
| 492 | pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported; | ||||||||||
| 493 | } | ||||||||||
| 494 | |||||||||||
| 495 | /** | ||||||||||
| 496 | * *********************************************************************************************** | ||||||||||
| 497 | * populate_subvp_cmd_vblank_pipe_info: Helper to populate VBLANK pipe info for the DMUB subvp command | ||||||||||
| 498 | * | ||||||||||
| 499 | * Populate the DMCUB SubVP command with VBLANK pipe info. All the information required to calculate | ||||||||||
| 500 | * the microschedule for SubVP + VBLANK case is stored in the pipe_data (subvp_data and vblank_data). | ||||||||||
| 501 | * Also check if the VBLANK pipe is a DRR display -- if it is make a call to populate drr_info. | ||||||||||
| 502 | * | ||||||||||
| 503 | * @param [in] dc: current dc state | ||||||||||
| 504 | * @param [in] context: new dc state | ||||||||||
| 505 | * @param [in] cmd: DMUB cmd to be populated with SubVP info | ||||||||||
| 506 | * @param [in] vblank_pipe: pipe_ctx for the VBLANK pipe | ||||||||||
| 507 | * @param [in] cmd_pipe_index: index for the pipe array in DMCUB SubVP cmd | ||||||||||
| 508 | * | ||||||||||
| 509 | * @return: void | ||||||||||
| 510 | * | ||||||||||
| 511 | * *********************************************************************************************** | ||||||||||
| 512 | */ | ||||||||||
| 513 | static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc, | ||||||||||
| 514 | struct dc_state *context, | ||||||||||
| 515 | union dmub_rb_cmd *cmd, | ||||||||||
| 516 | struct pipe_ctx *vblank_pipe, | ||||||||||
| 517 | uint8_t cmd_pipe_index) | ||||||||||
| 518 | { | ||||||||||
| 519 | uint32_t i; | ||||||||||
| 520 | struct pipe_ctx *pipe = NULL((void *)0); | ||||||||||
| 521 | struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = | ||||||||||
| 522 | &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; | ||||||||||
| 523 | |||||||||||
| 524 | // Find the SubVP pipe | ||||||||||
| 525 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||||||||
| 526 | pipe = &context->res_ctx.pipe_ctx[i]; | ||||||||||
| 527 | |||||||||||
| 528 | // We check for master pipe, but it shouldn't matter since we only need | ||||||||||
| 529 | // the pipe for timing info (stream should be same for any pipe splits) | ||||||||||
| 530 | if (!pipe->stream
| ||||||||||
| 531 | continue; | ||||||||||
| 532 | |||||||||||
| 533 | // Find the SubVP pipe | ||||||||||
| 534 | if (pipe->stream->mall_stream_config.type
| ||||||||||
| 535 | break; | ||||||||||
| 536 | } | ||||||||||
| 537 | |||||||||||
| 538 | pipe_data->mode = VBLANK; | ||||||||||
| 539 | pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz; | ||||||||||
| 540 | pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total - | ||||||||||
| 541 | vblank_pipe->stream->timing.v_front_porch; | ||||||||||
| 542 | pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total; | ||||||||||
| 543 | pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total; | ||||||||||
| 544 | pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; | ||||||||||
| 545 | pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start; | ||||||||||
| 546 | pipe_data->pipe_config.vblank_data.vblank_end = | ||||||||||
| 547 | vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable; | ||||||||||
| 548 | |||||||||||
| 549 | if (vblank_pipe->stream->ignore_msa_timing_param) | ||||||||||
| 550 | populate_subvp_cmd_drr_info(dc, pipe, vblank_pipe, pipe_data); | ||||||||||
| 551 | } | ||||||||||
| 552 | |||||||||||
| 553 | /** | ||||||||||
| 554 | * *********************************************************************************************** | ||||||||||
| 555 | * update_subvp_prefetch_end_to_mall_start: Helper for SubVP + SubVP case | ||||||||||
| 556 | * | ||||||||||
| 557 | * For SubVP + SubVP, we use a single vertical interrupt to start the microschedule for both | ||||||||||
| 558 | * SubVP pipes. In order for this to work correctly, the MALL REGION of both SubVP pipes must | ||||||||||
| 559 | * start at the same time. This function lengthens the prefetch end to mall start delay of the | ||||||||||
| 560 | * SubVP pipe that has the shorter prefetch so that both MALL REGION's will start at the same time. | ||||||||||
| 561 | * | ||||||||||
| 562 | * @param [in] dc: current dc state | ||||||||||
| 563 | * @param [in] context: new dc state | ||||||||||
| 564 | * @param [in] cmd: DMUB cmd to be populated with SubVP info | ||||||||||
| 565 | * @param [in] subvp_pipes: Array of SubVP pipes (should always be length 2) | ||||||||||
| 566 | * | ||||||||||
| 567 | * @return: void | ||||||||||
| 568 | * | ||||||||||
| 569 | * *********************************************************************************************** | ||||||||||
| 570 | */ | ||||||||||
| 571 | static void update_subvp_prefetch_end_to_mall_start(struct dc *dc, | ||||||||||
| 572 | struct dc_state *context, | ||||||||||
| 573 | union dmub_rb_cmd *cmd, | ||||||||||
| 574 | struct pipe_ctx *subvp_pipes[]) | ||||||||||
| 575 | { | ||||||||||
| 576 | uint32_t subvp0_prefetch_us = 0; | ||||||||||
| 577 | uint32_t subvp1_prefetch_us = 0; | ||||||||||
| 578 | uint32_t prefetch_delta_us = 0; | ||||||||||
| 579 | struct dc_crtc_timing *phantom_timing0 = &subvp_pipes[0]->stream->mall_stream_config.paired_stream->timing; | ||||||||||
| 580 | struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing; | ||||||||||
| 581 | struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL((void *)0); | ||||||||||
| 582 | |||||||||||
| 583 | subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * | ||||||||||
| 584 | (uint64_t)phantom_timing0->h_total * 1000000), | ||||||||||
| 585 | (((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); | ||||||||||
| 586 | subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * | ||||||||||
| 587 | (uint64_t)phantom_timing1->h_total * 1000000), | ||||||||||
| 588 | (((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us)); | ||||||||||
| 589 | |||||||||||
| 590 | // Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time) | ||||||||||
| 591 | // should increase it's prefetch time to match the other | ||||||||||
| 592 | if (subvp0_prefetch_us > subvp1_prefetch_us) { | ||||||||||
| 593 | pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1]; | ||||||||||
| 594 | prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us; | ||||||||||
| 595 | pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = | ||||||||||
| 596 | div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * | ||||||||||
| 597 | ((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)), | ||||||||||
| 598 | ((uint64_t)phantom_timing1->h_total * 1000000)); | ||||||||||
| 599 | |||||||||||
| 600 | } else if (subvp1_prefetch_us > subvp0_prefetch_us) { | ||||||||||
| 601 | pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0]; | ||||||||||
| 602 | prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us; | ||||||||||
| 603 | pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = | ||||||||||
| 604 | div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) * | ||||||||||
| 605 | ((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)), | ||||||||||
| 606 | ((uint64_t)phantom_timing0->h_total * 1000000)); | ||||||||||
| 607 | } | ||||||||||
| 608 | } | ||||||||||
| 609 | |||||||||||
| 610 | /** | ||||||||||
| 611 | * *************************************************************************************** | ||||||||||
| 612 | * setup_subvp_dmub_command: Helper to populate the SubVP pipe info for the DMUB subvp command | ||||||||||
| 613 | * | ||||||||||
| 614 | * Populate the DMCUB SubVP command with SubVP pipe info. All the information required to | ||||||||||
| 615 | * calculate the microschedule for the SubVP pipe is stored in the pipe_data of the DMCUB | ||||||||||
| 616 | * SubVP command. | ||||||||||
| 617 | * | ||||||||||
| 618 | * @param [in] dc: current dc state | ||||||||||
| 619 | * @param [in] context: new dc state | ||||||||||
| 620 | * @param [in] cmd: DMUB cmd to be populated with SubVP info | ||||||||||
| 621 | * @param [in] subvp_pipe: pipe_ctx for the SubVP pipe | ||||||||||
| 622 | * @param [in] cmd_pipe_index: index for the pipe array in DMCUB SubVP cmd | ||||||||||
| 623 | * | ||||||||||
| 624 | * @return: void | ||||||||||
| 625 | * | ||||||||||
| 626 | * *************************************************************************************** | ||||||||||
| 627 | */ | ||||||||||
| 628 | static void populate_subvp_cmd_pipe_info(struct dc *dc, | ||||||||||
| 629 | struct dc_state *context, | ||||||||||
| 630 | union dmub_rb_cmd *cmd, | ||||||||||
| 631 | struct pipe_ctx *subvp_pipe, | ||||||||||
| 632 | uint8_t cmd_pipe_index) | ||||||||||
| 633 | { | ||||||||||
| 634 | uint32_t j; | ||||||||||
| 635 | struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = | ||||||||||
| 636 | &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[cmd_pipe_index]; | ||||||||||
| 637 | struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing; | ||||||||||
| 638 | struct dc_crtc_timing *phantom_timing = &subvp_pipe->stream->mall_stream_config.paired_stream->timing; | ||||||||||
| 639 | uint32_t out_num_stream, out_den_stream, out_num_plane, out_den_plane, out_num, out_den; | ||||||||||
| 640 | |||||||||||
| 641 | pipe_data->mode = SUBVP; | ||||||||||
| 642 | pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz; | ||||||||||
| 643 | pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total; | ||||||||||
| 644 | pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total; | ||||||||||
| 645 | pipe_data->pipe_config.subvp_data.main_vblank_start = | ||||||||||
| 646 | main_timing->v_total - main_timing->v_front_porch; | ||||||||||
| 647 | pipe_data->pipe_config.subvp_data.main_vblank_end = | ||||||||||
| 648 | main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable; | ||||||||||
| 649 | pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable; | ||||||||||
| 650 | pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->pipe_idx; | ||||||||||
| 651 | pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param; | ||||||||||
| 652 | |||||||||||
| 653 | /* Calculate the scaling factor from the src and dst height. | ||||||||||
| 654 | * e.g. If 3840x2160 being downscaled to 1920x1080, the scaling factor is 1/2. | ||||||||||
| 655 | * Reduce the fraction 1080/2160 = 1/2 for the "scaling factor" | ||||||||||
| 656 | * | ||||||||||
| 657 | * Make sure to combine stream and plane scaling together. | ||||||||||
| 658 | */ | ||||||||||
| 659 | reduce_fraction(subvp_pipe->stream->src.height, subvp_pipe->stream->dst.height, | ||||||||||
| 660 | &out_num_stream, &out_den_stream); | ||||||||||
| 661 | reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height, | ||||||||||
| 662 | &out_num_plane, &out_den_plane); | ||||||||||
| 663 | reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den); | ||||||||||
| 664 | pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num; | ||||||||||
| 665 | pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den; | ||||||||||
| 666 | |||||||||||
| 667 | // Prefetch lines is equal to VACTIVE + BP + VSYNC | ||||||||||
| 668 | pipe_data->pipe_config.subvp_data.prefetch_lines = | ||||||||||
| 669 | phantom_timing->v_total - phantom_timing->v_front_porch; | ||||||||||
| 670 | |||||||||||
| 671 | // Round up | ||||||||||
| 672 | pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines = | ||||||||||
| 673 | div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + | ||||||||||
| 674 | ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); | ||||||||||
| 675 | pipe_data->pipe_config.subvp_data.processing_delay_lines = | ||||||||||
| 676 | div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) + | ||||||||||
| 677 | ((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000)); | ||||||||||
| 678 | |||||||||||
| 679 | if (subvp_pipe->bottom_pipe) { | ||||||||||
| 680 | pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; | ||||||||||
| 681 | } else if (subvp_pipe->next_odm_pipe) { | ||||||||||
| 682 | pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; | ||||||||||
| 683 | } else { | ||||||||||
| 684 | pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0; | ||||||||||
| 685 | } | ||||||||||
| 686 | |||||||||||
| 687 | // Find phantom pipe index based on phantom stream | ||||||||||
| 688 | for (j = 0; j < dc->res_pool->pipe_count; j++) { | ||||||||||
| 689 | struct pipe_ctx *phantom_pipe = &context->res_ctx.pipe_ctx[j]; | ||||||||||
| 690 | |||||||||||
| 691 | if (phantom_pipe->stream == subvp_pipe->stream->mall_stream_config.paired_stream) { | ||||||||||
| 692 | pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->pipe_idx; | ||||||||||
| 693 | if (phantom_pipe->bottom_pipe) { | ||||||||||
| 694 | pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->pipe_idx; | ||||||||||
| 695 | } else if (phantom_pipe->next_odm_pipe) { | ||||||||||
| 696 | pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->pipe_idx; | ||||||||||
| 697 | } else { | ||||||||||
| 698 | pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0; | ||||||||||
| 699 | } | ||||||||||
| 700 | break; | ||||||||||
| 701 | } | ||||||||||
| 702 | } | ||||||||||
| 703 | } | ||||||||||
| 704 | |||||||||||
| 705 | /** | ||||||||||
| 706 | * *************************************************************************************** | ||||||||||
| 707 | * dc_dmub_setup_subvp_dmub_command: Populate the DMCUB SubVP command | ||||||||||
| 708 | * | ||||||||||
| 709 | * This function loops through each pipe and populates the DMUB | ||||||||||
| 710 | * SubVP CMD info based on the pipe (e.g. SubVP, VBLANK). | ||||||||||
| 711 | * | ||||||||||
| 712 | * @param [in] dc: current dc state | ||||||||||
| 713 | * @param [in] context: new dc state | ||||||||||
| 714 | * @param [in] cmd: DMUB cmd to be populated with SubVP info | ||||||||||
| 715 | * | ||||||||||
| 716 | * @return: void | ||||||||||
| 717 | * | ||||||||||
| 718 | * *************************************************************************************** | ||||||||||
| 719 | */ | ||||||||||
| 720 | void dc_dmub_setup_subvp_dmub_command(struct dc *dc, | ||||||||||
| 721 | struct dc_state *context, | ||||||||||
| 722 | bool_Bool enable) | ||||||||||
| 723 | { | ||||||||||
| 724 | uint8_t cmd_pipe_index = 0; | ||||||||||
| 725 | uint32_t i, pipe_idx; | ||||||||||
| 726 | uint8_t subvp_count = 0; | ||||||||||
| 727 | union dmub_rb_cmd cmd; | ||||||||||
| 728 | struct pipe_ctx *subvp_pipes[2]; | ||||||||||
| 729 | uint32_t wm_val_refclk = 0; | ||||||||||
| 730 | |||||||||||
| 731 | memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd))); | ||||||||||
| 732 | // FW command for SUBVP | ||||||||||
| 733 | cmd.fw_assisted_mclk_switch_v2.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH; | ||||||||||
| 734 | cmd.fw_assisted_mclk_switch_v2.header.sub_type = DMUB_CMD__HANDLE_SUBVP_CMD; | ||||||||||
| 735 | cmd.fw_assisted_mclk_switch_v2.header.payload_bytes = | ||||||||||
| 736 | sizeof(cmd.fw_assisted_mclk_switch_v2) - sizeof(cmd.fw_assisted_mclk_switch_v2.header); | ||||||||||
| 737 | |||||||||||
| 738 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | ||||||||||
| |||||||||||
| 739 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | ||||||||||
| 740 | |||||||||||
| 741 | if (!pipe->stream) | ||||||||||
| 742 | continue; | ||||||||||
| 743 | |||||||||||
| 744 | /* For SubVP pipe count, only count the top most (ODM / MPC) pipe | ||||||||||
| 745 | */ | ||||||||||
| 746 | if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && | ||||||||||
| 747 | pipe->stream->mall_stream_config.type == SUBVP_MAIN) | ||||||||||
| 748 | subvp_pipes[subvp_count++] = pipe; | ||||||||||
| 749 | } | ||||||||||
| 750 | |||||||||||
| 751 | if (enable) { | ||||||||||
| 752 | // For each pipe that is a "main" SUBVP pipe, fill in pipe data for DMUB SUBVP cmd | ||||||||||
| 753 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | ||||||||||
| 754 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | ||||||||||
| 755 | |||||||||||
| 756 | if (!pipe->stream
| ||||||||||
| 757 | continue; | ||||||||||
| 758 | |||||||||||
| 759 | /* When populating subvp cmd info, only pass in the top most (ODM / MPC) pipe. | ||||||||||
| 760 | * Any ODM or MPC splits being used in SubVP will be handled internally in | ||||||||||
| 761 | * populate_subvp_cmd_pipe_info | ||||||||||
| 762 | */ | ||||||||||
| 763 | if (pipe->plane_state
| ||||||||||
| 764 | !pipe->top_pipe && !pipe->prev_odm_pipe && | ||||||||||
| 765 | pipe->stream->mall_stream_config.type == SUBVP_MAIN) { | ||||||||||
| 766 | populate_subvp_cmd_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); | ||||||||||
| 767 | } else if (pipe->plane_state
| ||||||||||
| 768 | !pipe->top_pipe
| ||||||||||
| 769 | // Don't need to check for ActiveDRAMClockChangeMargin < 0, not valid in cases where | ||||||||||
| 770 | // we run through DML without calculating "natural" P-state support | ||||||||||
| 771 | populate_subvp_cmd_vblank_pipe_info(dc, context, &cmd, pipe, cmd_pipe_index++); | ||||||||||
| 772 | |||||||||||
| 773 | } | ||||||||||
| 774 | pipe_idx++; | ||||||||||
| 775 | } | ||||||||||
| 776 | if (subvp_count == 2) { | ||||||||||
| 777 | update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes); | ||||||||||
| 778 | } | ||||||||||
| 779 | cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; | ||||||||||
| 780 | cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us; | ||||||||||
| 781 | |||||||||||
| 782 | // Store the original watermark value for this SubVP config so we can lower it when the | ||||||||||
| 783 | // MCLK switch starts | ||||||||||
| 784 | wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * | ||||||||||
| 785 | (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000; | ||||||||||
| 786 | |||||||||||
| 787 | cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF; | ||||||||||
| 788 | } | ||||||||||
| 789 | dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); | ||||||||||
| 790 | dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); | ||||||||||
| 791 | dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); | ||||||||||
| 792 | } | ||||||||||
| 793 | #endif | ||||||||||
| 794 | |||||||||||
| 795 | bool_Bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data) | ||||||||||
| 796 | { | ||||||||||
| 797 | if (!dc_dmub_srv || !dc_dmub_srv->dmub || !diag_data) | ||||||||||
| 798 | return false0; | ||||||||||
| 799 | return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data); | ||||||||||
| 800 | } | ||||||||||
| 801 | |||||||||||
| 802 | void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) | ||||||||||
| 803 | { | ||||||||||
| 804 | struct dmub_diagnostic_data diag_data = {0}; | ||||||||||
| 805 | |||||||||||
| 806 | if (!dc_dmub_srv || !dc_dmub_srv->dmub) { | ||||||||||
| 807 | DC_LOG_ERROR("%s: invalid parameters.", __func__)__drm_err("%s: invalid parameters.", __func__); | ||||||||||
| 808 | return; | ||||||||||
| 809 | } | ||||||||||
| 810 | |||||||||||
| 811 | if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) { | ||||||||||
| 812 | DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__)__drm_err("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__ ); | ||||||||||
| 813 | return; | ||||||||||
| 814 | } | ||||||||||
| 815 | |||||||||||
| 816 | DC_LOG_DEBUG(___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 817 | "DMCUB STATE\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 818 | " dmcub_version : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 819 | " scratch [0] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 820 | " scratch [1] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 821 | " scratch [2] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 822 | " scratch [3] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 823 | " scratch [4] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 824 | " scratch [5] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 825 | " scratch [6] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 826 | " scratch [7] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 827 | " scratch [8] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 828 | " scratch [9] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 829 | " scratch [10] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 830 | " scratch [11] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 831 | " scratch [12] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 832 | " scratch [13] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 833 | " scratch [14] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 834 | " scratch [15] : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 835 | " pc : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 836 | " unk_fault_addr : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 837 | " inst_fault_addr : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 838 | " data_fault_addr : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 839 | " inbox1_rptr : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 840 | " inbox1_wptr : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 841 | " inbox1_size : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 842 | " inbox0_rptr : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 843 | " inbox0_wptr : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 844 | " inbox0_size : %08x\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 845 | " is_enabled : %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 846 | " is_soft_reset : %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 847 | " is_secure_reset : %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 848 | " is_traceport_en : %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 849 | " is_cw0_en : %d\n"___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 850 | " is_cw6_en : %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 851 | diag_data.dmcub_version,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 852 | diag_data.scratch[0],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 853 | diag_data.scratch[1],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 854 | diag_data.scratch[2],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 855 | diag_data.scratch[3],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 856 | diag_data.scratch[4],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 857 | diag_data.scratch[5],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 858 | diag_data.scratch[6],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 859 | diag_data.scratch[7],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 860 | diag_data.scratch[8],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 861 | diag_data.scratch[9],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 862 | diag_data.scratch[10],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 863 | diag_data.scratch[11],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 864 | diag_data.scratch[12],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 865 | diag_data.scratch[13],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 866 | diag_data.scratch[14],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 867 | diag_data.scratch[15],___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 868 | diag_data.pc,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 869 | diag_data.undefined_address_fault_addr,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 870 | diag_data.inst_fetch_fault_addr,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 871 | diag_data.data_write_fault_addr,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 872 | diag_data.inbox1_rptr,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 873 | diag_data.inbox1_wptr,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 874 | diag_data.inbox1_size,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 875 | diag_data.inbox0_rptr,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 876 | diag_data.inbox0_wptr,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 877 | diag_data.inbox0_size,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 878 | diag_data.is_dmcub_enabled,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 879 | diag_data.is_dmcub_soft_reset,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 880 | diag_data.is_dmcub_secure_reset,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 881 | diag_data.is_traceport_en,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 882 | diag_data.is_cw0_enabled,___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled) | ||||||||||
| 883 | diag_data.is_cw6_enabled)___drm_dbg(((void *)0), DRM_UT_KMS, "DMCUB STATE\n" " dmcub_version : %08x\n" " scratch [0] : %08x\n" " scratch [1] : %08x\n" " scratch [2] : %08x\n" " scratch [3] : %08x\n" " scratch [4] : %08x\n" " scratch [5] : %08x\n" " scratch [6] : %08x\n" " scratch [7] : %08x\n" " scratch [8] : %08x\n" " scratch [9] : %08x\n" " scratch [10] : %08x\n" " scratch [11] : %08x\n" " scratch [12] : %08x\n" " scratch [13] : %08x\n" " scratch [14] : %08x\n" " scratch [15] : %08x\n" " pc : %08x\n" " unk_fault_addr : %08x\n" " inst_fault_addr : %08x\n" " data_fault_addr : %08x\n" " inbox1_rptr : %08x\n" " inbox1_wptr : %08x\n" " inbox1_size : %08x\n" " inbox0_rptr : %08x\n" " inbox0_wptr : %08x\n" " inbox0_size : %08x\n" " is_enabled : %d\n" " is_soft_reset : %d\n" " is_secure_reset : %d\n" " is_traceport_en : %d\n" " is_cw0_en : %d\n" " is_cw6_en : %d\n" , diag_data.dmcub_version, diag_data.scratch[0], diag_data.scratch [1], diag_data.scratch[2], diag_data.scratch[3], diag_data.scratch [4], diag_data.scratch[5], diag_data.scratch[6], diag_data.scratch [7], diag_data.scratch[8], diag_data.scratch[9], diag_data.scratch [10], diag_data.scratch[11], diag_data.scratch[12], diag_data .scratch[13], diag_data.scratch[14], diag_data.scratch[15], diag_data .pc, diag_data.undefined_address_fault_addr, diag_data.inst_fetch_fault_addr , diag_data.data_write_fault_addr, diag_data.inbox1_rptr, diag_data .inbox1_wptr, diag_data.inbox1_size, diag_data.inbox0_rptr, diag_data .inbox0_wptr, diag_data.inbox0_size, diag_data.is_dmcub_enabled , diag_data.is_dmcub_soft_reset, diag_data.is_dmcub_secure_reset , diag_data.is_traceport_en, diag_data.is_cw0_enabled, diag_data .is_cw6_enabled); | ||||||||||
| 884 | } | ||||||||||
| 885 | |||||||||||
| 886 | static bool_Bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) | ||||||||||
| 887 | { | ||||||||||
| 888 | if (pipe_ctx->plane_state != NULL((void *)0)) { | ||||||||||
| 889 | if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) | ||||||||||
| 890 | return false0; | ||||||||||
| 891 | } | ||||||||||
| 892 | |||||||||||
| 893 | if ((pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 || | ||||||||||
| 894 | pipe_ctx->stream->link->psr_settings.psr_version == DC_PSR_VERSION_1) && | ||||||||||
| 895 | pipe_ctx->stream->ctx->dce_version >= DCN_VERSION_3_1) | ||||||||||
| 896 | return true1; | ||||||||||
| 897 | |||||||||||
| 898 | return false0; | ||||||||||
| 899 | } | ||||||||||
| 900 | |||||||||||
| 901 | static void dc_build_cursor_update_payload0( | ||||||||||
| 902 | struct pipe_ctx *pipe_ctx, uint8_t p_idx, | ||||||||||
| 903 | struct dmub_cmd_update_cursor_payload0 *payload) | ||||||||||
| 904 | { | ||||||||||
| 905 | struct hubp *hubp = pipe_ctx->plane_res.hubp; | ||||||||||
| 906 | unsigned int panel_inst = 0; | ||||||||||
| 907 | |||||||||||
| 908 | if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, | ||||||||||
| 909 | pipe_ctx->stream->link, &panel_inst)) | ||||||||||
| 910 | return; | ||||||||||
| 911 | |||||||||||
| 912 | /* Payload: Cursor Rect is built from position & attribute | ||||||||||
| 913 | * x & y are obtained from postion | ||||||||||
| 914 | */ | ||||||||||
| 915 | payload->cursor_rect.x = hubp->cur_rect.x; | ||||||||||
| 916 | payload->cursor_rect.y = hubp->cur_rect.y; | ||||||||||
| 917 | /* w & h are obtained from attribute */ | ||||||||||
| 918 | payload->cursor_rect.width = hubp->cur_rect.w; | ||||||||||
| 919 | payload->cursor_rect.height = hubp->cur_rect.h; | ||||||||||
| 920 | |||||||||||
| 921 | payload->enable = hubp->pos.cur_ctl.bits.cur_enable; | ||||||||||
| 922 | payload->pipe_idx = p_idx; | ||||||||||
| 923 | payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_10x1; | ||||||||||
| 924 | payload->panel_inst = panel_inst; | ||||||||||
| 925 | } | ||||||||||
| 926 | |||||||||||
| 927 | static void dc_send_cmd_to_dmu(struct dc_dmub_srv *dmub_srv, | ||||||||||
| 928 | union dmub_rb_cmd *cmd) | ||||||||||
| 929 | { | ||||||||||
| 930 | dc_dmub_srv_cmd_queue(dmub_srv, cmd); | ||||||||||
| 931 | dc_dmub_srv_cmd_execute(dmub_srv); | ||||||||||
| 932 | dc_dmub_srv_wait_idle(dmub_srv); | ||||||||||
| 933 | } | ||||||||||
| 934 | |||||||||||
| 935 | static void dc_build_cursor_position_update_payload0( | ||||||||||
| 936 | struct dmub_cmd_update_cursor_payload0 *pl, const uint8_t p_idx, | ||||||||||
| 937 | const struct hubp *hubp, const struct dpp *dpp) | ||||||||||
| 938 | { | ||||||||||
| 939 | /* Hubp */ | ||||||||||
| 940 | pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; | ||||||||||
| 941 | pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; | ||||||||||
| 942 | pl->position_cfg.pHubp.hot_spot.raw = hubp->pos.hot_spot.raw; | ||||||||||
| 943 | pl->position_cfg.pHubp.dst_offset.raw = hubp->pos.dst_offset.raw; | ||||||||||
| 944 | |||||||||||
| 945 | /* dpp */ | ||||||||||
| 946 | pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; | ||||||||||
| 947 | pl->position_cfg.pipe_idx = p_idx; | ||||||||||
| 948 | } | ||||||||||
| 949 | |||||||||||
| 950 | static void dc_build_cursor_attribute_update_payload1( | ||||||||||
| 951 | struct dmub_cursor_attributes_cfg *pl_A, const uint8_t p_idx, | ||||||||||
| 952 | const struct hubp *hubp, const struct dpp *dpp) | ||||||||||
| 953 | { | ||||||||||
| 954 | /* Hubp */ | ||||||||||
| 955 | pl_A->aHubp.SURFACE_ADDR_HIGH = hubp->att.SURFACE_ADDR_HIGH; | ||||||||||
| 956 | pl_A->aHubp.SURFACE_ADDR = hubp->att.SURFACE_ADDR; | ||||||||||
| 957 | pl_A->aHubp.cur_ctl.raw = hubp->att.cur_ctl.raw; | ||||||||||
| 958 | pl_A->aHubp.size.raw = hubp->att.size.raw; | ||||||||||
| 959 | pl_A->aHubp.settings.raw = hubp->att.settings.raw; | ||||||||||
| 960 | |||||||||||
| 961 | /* dpp */ | ||||||||||
| 962 | pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; | ||||||||||
| 963 | } | ||||||||||
| 964 | |||||||||||
| 965 | /** | ||||||||||
| 966 | * *************************************************************************************** | ||||||||||
| 967 | * dc_send_update_cursor_info_to_dmu: Populate the DMCUB Cursor update info command | ||||||||||
| 968 | * | ||||||||||
| 969 | * This function would store the cursor related information and pass it into dmub | ||||||||||
| 970 | * | ||||||||||
| 971 | * @param [in] pCtx: pipe context | ||||||||||
| 972 | * @param [in] pipe_idx: pipe index | ||||||||||
| 973 | * | ||||||||||
| 974 | * @return: void | ||||||||||
| 975 | * | ||||||||||
| 976 | * *************************************************************************************** | ||||||||||
| 977 | */ | ||||||||||
| 978 | |||||||||||
| 979 | void dc_send_update_cursor_info_to_dmu( | ||||||||||
| 980 | struct pipe_ctx *pCtx, uint8_t pipe_idx) | ||||||||||
| 981 | { | ||||||||||
| 982 | union dmub_rb_cmd cmd = { 0 }; | ||||||||||
| 983 | union dmub_cmd_update_cursor_info_data *update_cursor_info = | ||||||||||
| 984 | &cmd.update_cursor_info.update_cursor_info_data; | ||||||||||
| 985 | |||||||||||
| 986 | if (!dc_dmub_should_update_cursor_data(pCtx)) | ||||||||||
| 987 | return; | ||||||||||
| 988 | /* | ||||||||||
| 989 | * Since we use multi_cmd_pending for dmub command, the 2nd command is | ||||||||||
| 990 | * only assigned to store cursor attributes info. | ||||||||||
| 991 | * 1st command can view as 2 parts, 1st is for PSR/Replay data, the other | ||||||||||
| 992 | * is to store cursor position info. | ||||||||||
| 993 | * | ||||||||||
| 994 | * Command heaer type must be the same type if using multi_cmd_pending. | ||||||||||
| 995 | * Besides, while process 2nd command in DMU, the sub type is useless. | ||||||||||
| 996 | * So it's meanless to pass the sub type header with different type. | ||||||||||
| 997 | */ | ||||||||||
| 998 | |||||||||||
| 999 | { | ||||||||||
| 1000 | /* Build Payload#0 Header */ | ||||||||||
| 1001 | cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; | ||||||||||
| 1002 | cmd.update_cursor_info.header.payload_bytes = | ||||||||||
| 1003 | sizeof(cmd.update_cursor_info.update_cursor_info_data); | ||||||||||
| 1004 | cmd.update_cursor_info.header.multi_cmd_pending = 1; /* To combine multi dmu cmd, 1st cmd */ | ||||||||||
| 1005 | |||||||||||
| 1006 | /* Prepare Payload */ | ||||||||||
| 1007 | dc_build_cursor_update_payload0(pCtx, pipe_idx, &update_cursor_info->payload0); | ||||||||||
| 1008 | |||||||||||
| 1009 | dc_build_cursor_position_update_payload0(&update_cursor_info->payload0, pipe_idx, | ||||||||||
| 1010 | pCtx->plane_res.hubp, pCtx->plane_res.dpp); | ||||||||||
| 1011 | /* Send update_curosr_info to queue */ | ||||||||||
| 1012 | dc_dmub_srv_cmd_queue(pCtx->stream->ctx->dmub_srv, &cmd); | ||||||||||
| 1013 | } | ||||||||||
| 1014 | { | ||||||||||
| 1015 | /* Build Payload#1 Header */ | ||||||||||
| 1016 | memset(update_cursor_info, 0, sizeof(union dmub_cmd_update_cursor_info_data))__builtin_memset((update_cursor_info), (0), (sizeof(union dmub_cmd_update_cursor_info_data ))); | ||||||||||
| 1017 | cmd.update_cursor_info.header.type = DMUB_CMD__UPDATE_CURSOR_INFO; | ||||||||||
| 1018 | cmd.update_cursor_info.header.payload_bytes = sizeof(struct cursor_attributes_cfg); | ||||||||||
| 1019 | cmd.update_cursor_info.header.multi_cmd_pending = 0; /* Indicate it's the last command. */ | ||||||||||
| 1020 | |||||||||||
| 1021 | dc_build_cursor_attribute_update_payload1( | ||||||||||
| 1022 | &cmd.update_cursor_info.update_cursor_info_data.payload1.attribute_cfg, | ||||||||||
| 1023 | pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); | ||||||||||
| 1024 | |||||||||||
| 1025 | /* Combine 2nd cmds update_curosr_info to DMU */ | ||||||||||
| 1026 | dc_send_cmd_to_dmu(pCtx->stream->ctx->dmub_srv, &cmd); | ||||||||||
| 1027 | } | ||||||||||
| 1028 | } | ||||||||||
| 1029 | |||||||||||
| 1030 | bool_Bool dc_dmub_check_min_version(struct dmub_srv *srv) | ||||||||||
| 1031 | { | ||||||||||
| 1032 | if (!srv->hw_funcs.is_psrsu_supported) | ||||||||||
| 1033 | return true1; | ||||||||||
| 1034 | return srv->hw_funcs.is_psrsu_supported(srv); | ||||||||||
| 1035 | } |