/usr/src/sys/dev/ic/dc.c

Bug Summary

File:	dev/ic/dc.c
Warning:	line 815, column 3 3rd function call argument is an uninitialized value
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name dc.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/ic/dc.c
1/*	$OpenBSD: dc.c,v 1.156 2023/11/10 15:51:20 bluhm Exp $	*/

3/*
* Copyright (c) 1997, 1998, 1999
*	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
*    must display the following acknowledgement:
*	This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
*    may be used to endorse or promote products derived from this software
*    without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD: src/sys/pci/if_dc.c,v 1.43 2001/01/19 23:55:07 wpaul Exp $
*/

37/*
* DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
* series chips and several workalikes including the following:
*
* Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
* Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
* Lite-On 82c168/82c169 PNIC (www.litecom.com)
* ASIX Electronics AX88140A (www.asix.com.tw)
* ASIX Electronics AX88141 (www.asix.com.tw)
* ADMtek AL981 (www.admtek.com.tw)
* ADMtek AN983 (www.admtek.com.tw)
* Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
* Accton EN1217, EN2242 (www.accton.com)
* Xircom X3201 (www.xircom.com)
*
* Datasheets for the 21143 are available at developer.intel.com.
* Datasheets for the clone parts can be found at their respective sites.
* (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
* The PNIC II is essentially a Macronix 98715A chip; the only difference
* worth noting is that its multicast hash table is only 128 bits wide
* instead of 512.
*
* Written by Bill Paul <wpaul@ee.columbia.edu>
* Electrical Engineering Department
* Columbia University, New York City
*/

64/*
* The Intel 21143 is the successor to the DEC 21140. It is basically
* the same as the 21140 but with a few new features. The 21143 supports
* three kinds of media attachments:
*
* o MII port, for 10Mbps and 100Mbps support and NWAY
*   autonegotiation provided by an external PHY.
* o SYM port, for symbol mode 100Mbps support.
* o 10baseT port.
* o AUI/BNC port.
*
* The 100Mbps SYM port and 10baseT port can be used together in
* combination with the internal NWAY support to create a 10/100
* autosensing configuration.
*
* Note that not all tulip workalikes are handled in this driver: we only
* deal with those which are relatively well behaved. The Winbond is
* handled separately due to its different register offsets and the
* special handling needed for its various bugs. The PNIC is handled
* here, but I'm not thrilled about it.
*
* All of the workalike chips use some form of MII transceiver support
* with the exception of the Macronix chips, which also have a SYM port.
* The ASIX AX88140A is also documented to have a SYM port, but all
* the cards I've seen use an MII transceiver, probably because the
* AX88140A doesn't support internal NWAY.
*/

92#include "bpfilter.h"

94#include <sys/param.h>
95#include <sys/systm.h>
96#include <sys/mbuf.h>
97#include <sys/socket.h>
98#include <sys/ioctl.h>
99#include <sys/errno.h>
100#include <sys/malloc.h>
101#include <sys/kernel.h>
102#include <sys/device.h>
103#include <sys/timeout.h>

105#include <net/if.h>

107#include <netinet/in.h>
108#include <netinet/if_ether.h>

110#include <net/if_media.h>

112#if NBPFILTER1 > 0
113#include <net/bpf.h>
114#endif

116#include <dev/mii/mii.h>
117#include <dev/mii/miivar.h>

119#include <machine/bus.h>
120#include <dev/pci/pcidevs.h>

122#include <dev/ic/dcreg.h>

124/*
* The Davicom DM9102 has a broken DMA engine that reads beyond the
* end of the programmed transfer.  Architectures with a proper IOMMU
* (such as sparc64) will trap on this access.  To avoid having to
* copy each transmitted mbuf to guarantee enough trailing space,
* those architectures should implement BUS_DMA_OVERRUN that takes
* appropriate action to tolerate this behaviour.
*/
132#ifndef BUS_DMA_OVERRUN0
133#define BUS_DMA_OVERRUN0 0
134#endif

136int dc_intr(void *);
137struct dc_type *dc_devtype(void *);
138int dc_newbuf(struct dc_softc *, int, struct mbuf *);
139int dc_encap(struct dc_softc *, bus_dmamap_t, struct mbuf *, u_int32_t *);

141void dc_pnic_rx_bug_war(struct dc_softc *, int);
142int dc_rx_resync(struct dc_softc *);
143int dc_rxeof(struct dc_softc *);
144void dc_txeof(struct dc_softc *);
145void dc_tick(void *);
146void dc_tx_underrun(struct dc_softc *);
147void dc_start(struct ifnet *);
148int dc_ioctl(struct ifnet *, u_long, caddr_t);
149void dc_watchdog(struct ifnet *);
150int dc_ifmedia_upd(struct ifnet *);
151void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);

153void dc_delay(struct dc_softc *);
154void dc_eeprom_width(struct dc_softc *);
155void dc_eeprom_idle(struct dc_softc *);
156void dc_eeprom_putbyte(struct dc_softc *, int);
157void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *);
158void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *);
159void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *);
160void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);

162void dc_mii_writebit(struct dc_softc *, int);
163int dc_mii_readbit(struct dc_softc *);
164void dc_mii_sync(struct dc_softc *);
165void dc_mii_send(struct dc_softc *, u_int32_t, int);
166int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
167int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
168int dc_miibus_readreg(struct device *, int, int);
169void dc_miibus_writereg(struct device *, int, int, int);
170void dc_miibus_statchg(struct device *);

172void dc_setcfg(struct dc_softc *, uint64_t);
173u_int32_t dc_crc_le(struct dc_softc *, caddr_t);
174u_int32_t dc_crc_be(caddr_t)((ether_crc32_be(caddr_t,6) >> 26) & 0x0000003F);
175void dc_setfilt_21143(struct dc_softc *);
176void dc_setfilt_asix(struct dc_softc *);
177void dc_setfilt_admtek(struct dc_softc *);
178void dc_setfilt_xircom(struct dc_softc *);

180void dc_setfilt(struct dc_softc *);

182void dc_reset(struct dc_softc *);
183int dc_list_rx_init(struct dc_softc *);
184int dc_list_tx_init(struct dc_softc *);

186void dc_read_srom(struct dc_softc *, int);
187void dc_parse_21143_srom(struct dc_softc *);
188void dc_decode_leaf_sia(struct dc_softc *,
		     struct dc_eblock_sia *);
190void dc_decode_leaf_mii(struct dc_softc *,
		     struct dc_eblock_mii *);
192void dc_decode_leaf_sym(struct dc_softc *,
		     struct dc_eblock_sym *);
194void dc_apply_fixup(struct dc_softc *, uint64_t);

196#define DC_SETBIT(sc, reg, x)((sc->dc_btag)->write_4((sc->dc_bhandle), (reg), (((
sc->dc_btag)->read_4((sc->dc_bhandle), (reg))) | (x)
)))				\
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))((sc->dc_btag)->write_4((sc->dc_bhandle), (reg), (((
sc->dc_btag)->read_4((sc->dc_bhandle), (reg))) | (x)
)))

199#define DC_CLRBIT(sc, reg, x)((sc->dc_btag)->write_4((sc->dc_bhandle), (reg), (((
sc->dc_btag)->read_4((sc->dc_bhandle), (reg))) &
 ~(x))))				\
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))((sc->dc_btag)->write_4((sc->dc_bhandle), (reg), (((
sc->dc_btag)->read_4((sc->dc_bhandle), (reg))) &
 ~(x))))

202#define SIO_SET(x)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
(x)))))	DC_SETBIT(sc, DC_SIO, (x))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
(x)))))
203#define SIO_CLR(x)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~((x)))))	DC_CLRBIT(sc, DC_SIO, (x))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~((x)))))

205void
206dc_delay(struct dc_softc *sc)
207{
int idx;

for (idx = (300 / 33) + 1; idx > 0; idx--)
CSR_READ_4(sc, DC_BUSCTL)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x00)));
212}

214void
215dc_eeprom_width(struct dc_softc *sc)
216{
int i;

/* Force EEPROM to idle state. */
dc_eeprom_idle(sc);

/* Enter EEPROM access mode. */
CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00000800
)));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00004000))));
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000001))));
dc_delay(sc);

for (i = 3; i--;) {
if (6 & (1 << i))
	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000004))));
else
	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000004))));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000002))));
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
}

for (i = 1; i <= 12; i++) {
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000002))));
dc_delay(sc);
if (!(CSR_READ_4(sc, DC_SIO)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) & DC_SIO_EE_DATAOUT0x00000008)) {
	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
	dc_delay(sc);
	break;
}
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
}

/* Turn off EEPROM access mode. */
dc_eeprom_idle(sc);

if (i < 4 || i > 12)
sc->dc_romwidth = 6;
else
sc->dc_romwidth = i;

/* Enter EEPROM access mode. */
CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00000800
)));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00004000))));
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000001))));
dc_delay(sc);

/* Turn off EEPROM access mode. */
dc_eeprom_idle(sc);
276}

278void
279dc_eeprom_idle(struct dc_softc *sc)
280{
int i;

CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00000800
)));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00004000))));
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000001))));
dc_delay(sc);

for (i = 0; i < 25; i++) {
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000002))));
dc_delay(sc);
}

DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000001))));
dc_delay(sc);
CSR_WRITE_4(sc, DC_SIO, 0x00000000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00000000
)));
304}

306/*
* Send a read command and address to the EEPROM, check for ACK.
*/
309void
310dc_eeprom_putbyte(struct dc_softc *sc, int addr)
311{
int d, i;

d = DC_EECMD_READ0x180 >> 6;

for (i = 3; i--; ) {
if (d & (1 << i))
	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000004))));
else
	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000004))));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000002))));
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
}

/*
* Feed in each bit and strobe the clock.
*/
for (i = sc->dc_romwidth; i--;) {
if (addr & (1 << i)) {
	SIO_SET(DC_SIO_EE_DATAIN)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
(0x00000004)))));
} else {
	SIO_CLR(DC_SIO_EE_DATAIN)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~((0x00000004)))));
}
dc_delay(sc);
SIO_SET(DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
(0x00000002)))));
dc_delay(sc);
SIO_CLR(DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~((0x00000002)))));
dc_delay(sc);
}
343}

345/*
* Read a word of data stored in the EEPROM at address 'addr.'
* The PNIC 82c168/82c169 has its own non-standard way to read
* the EEPROM.
*/
350void
351dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
352{
int i;
u_int32_t r;

CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x98), (0x00000600
|addr)));

for (i = 0; i < DC_TIMEOUT1000; i++) {
DELAY(1)(*delay_func)(1);
r = CSR_READ_4(sc, DC_SIO)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x48)));
if (!(r & DC_PN_SIOCTL_BUSY0x80000000)) {
	*dest = (u_int16_t)(r & 0xFFFF);
	return;
}
}
366}

368/*
* Read a word of data stored in the EEPROM at address 'addr.'
* The Xircom X3201 has its own non-standard way to read
* the EEPROM, too.
*/
373void
374dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
375{
SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
(0x00001000 | 0x00004000)))));

addr *= 2;
CSR_WRITE_4(sc, DC_ROM, addr | 0x160)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x50), (addr
 | 0x160)));
*dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) & 0xff;
addr += 1;
CSR_WRITE_4(sc, DC_ROM, addr | 0x160)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x50), (addr
 | 0x160)));
*dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) & 0xff) << 8;

SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~((0x00001000 | 0x00004000)))));
386}

388/*
* Read a word of data stored in the EEPROM at address 'addr.'
*/
391void
392dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
393{
int i;
u_int16_t word = 0;

/* Force EEPROM to idle state. */
dc_eeprom_idle(sc);

/* Enter EEPROM access mode. */
CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00000800
)));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO,  DC_SIO_ROMCTL_READ)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00004000))));
dc_delay(sc);
DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00000002))));
dc_delay(sc);
DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00000001))));
dc_delay(sc);

/*
* Send address of word we want to read.
*/
dc_eeprom_putbyte(sc, addr);

/*
* Start reading bits from EEPROM.
*/
for (i = 0x8000; i; i >>= 1) {
SIO_SET(DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
(0x00000002)))));
dc_delay(sc);
if (CSR_READ_4(sc, DC_SIO)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) & DC_SIO_EE_DATAOUT0x00000008)
	word |= i;
dc_delay(sc);
SIO_CLR(DC_SIO_EE_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~((0x00000002)))));
dc_delay(sc);
}

/* Turn off EEPROM access mode. */
dc_eeprom_idle(sc);

*dest = word;
432}

434/*
* Read a sequence of words from the EEPROM.
*/
437void
438dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt,
  int swap)
440{
int i;
u_int16_t word = 0, *ptr;

for (i = 0; i < cnt; i++) {
if (DC_IS_PNIC(sc)(sc->dc_type == 0xA))
	dc_eeprom_getword_pnic(sc, off + i, &word);
else if (DC_IS_XIRCOM(sc)(sc->dc_type == 0xB))
	dc_eeprom_getword_xircom(sc, off + i, &word);
else
	dc_eeprom_getword(sc, off + i, &word);
ptr = (u_int16_t *)(dest + (i * 2));
if (swap)
	*ptr = betoh16(word)(__uint16_t)(__builtin_constant_p(word) ? (__uint16_t)(((__uint16_t
)(word) & 0xffU) << 8 | ((__uint16_t)(word) & 0xff00U
) >> 8) : __swap16md(word));
else
	*ptr = letoh16(word)((__uint16_t)(word));
}
457}

459/*
* The following two routines are taken from the Macronix 98713
* Application Notes pp.19-21.
*/
463/*
* Write a bit to the MII bus.
*/
466void
467dc_mii_writebit(struct dc_softc *sc, int bit)
468{
if (bit)
CSR_WRITE_4(sc, DC_SIO,((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00002000
|0x00020000)))
    DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00002000
|0x00020000)));
else
CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00002000
)));

DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00010000))));
DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00010000))));
477}

479/*
* Read a bit from the MII bus.
*/
482int
483dc_mii_readbit(struct dc_softc *sc)
484{
CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00004000
|0x00040000)));
CSR_READ_4(sc, DC_SIO)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x48)));
DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) | (
0x00010000))));
DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) &
 ~(0x00010000))));
if (CSR_READ_4(sc, DC_SIO)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x48))) & DC_SIO_MII_DATAIN0x00080000)
return (1);
return (0);
492}

494/*
* Sync the PHYs by setting data bit and strobing the clock 32 times.
*/
497void
498dc_mii_sync(struct dc_softc *sc)
499{
int i;

CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x48), (0x00002000
)));

for (i = 0; i < 32; i++)
dc_mii_writebit(sc, 1);
506}

508/*
* Clock a series of bits through the MII.
*/
511void
512dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
513{
int i;

for (i = (0x1 << (cnt - 1)); i; i >>= 1)
dc_mii_writebit(sc, bits & i);
518}

520/*
* Read an PHY register through the MII.
*/
523int
524dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
525{
int i, ack, s;

s = splnet()splraise(0x4);

/*
* Set up frame for RX.
*/
frame->mii_stdelim = DC_MII_STARTDELIM0x01;
frame->mii_opcode = DC_MII_READOP0x02;
frame->mii_turnaround = 0;
frame->mii_data = 0;

/*
* Sync the PHYs.
*/
dc_mii_sync(sc);

/*
* Send command/address info.
*/
dc_mii_send(sc, frame->mii_stdelim, 2);
dc_mii_send(sc, frame->mii_opcode, 2);
dc_mii_send(sc, frame->mii_phyaddr, 5);
dc_mii_send(sc, frame->mii_regaddr, 5);

551#ifdef notdef
/* Idle bit */
dc_mii_writebit(sc, 1);
dc_mii_writebit(sc, 0);
555#endif

/* Check for ack */
ack = dc_mii_readbit(sc);

/*
* Now try reading data bits. If the ack failed, we still
* need to clock through 16 cycles to keep the PHY(s) in sync.
*/
if (ack) {
for(i = 0; i < 16; i++) {
	dc_mii_readbit(sc);
}
goto fail;
}

for (i = 0x8000; i; i >>= 1) {
if (!ack) {
	if (dc_mii_readbit(sc))
		frame->mii_data |= i;
}
}

578fail:

dc_mii_writebit(sc, 0);
dc_mii_writebit(sc, 0);

splx(s)spllower(s);

if (ack)
return (1);
return (0);
588}

590/*
* Write to a PHY register through the MII.
*/
593int
594dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
595{
int s;

s = splnet()splraise(0x4);
/*
* Set up frame for TX.
*/

frame->mii_stdelim = DC_MII_STARTDELIM0x01;
frame->mii_opcode = DC_MII_WRITEOP0x01;
frame->mii_turnaround = DC_MII_TURNAROUND0x02;

/*
* Sync the PHYs.
*/	
dc_mii_sync(sc);

dc_mii_send(sc, frame->mii_stdelim, 2);
dc_mii_send(sc, frame->mii_opcode, 2);
dc_mii_send(sc, frame->mii_phyaddr, 5);
dc_mii_send(sc, frame->mii_regaddr, 5);
dc_mii_send(sc, frame->mii_turnaround, 2);
dc_mii_send(sc, frame->mii_data, 16);

/* Idle bit. */
dc_mii_writebit(sc, 0);
dc_mii_writebit(sc, 0);

splx(s)spllower(s);
return (0);
625}

627int
628dc_miibus_readreg(struct device *self, int phy, int reg)
629{
struct dc_mii_frame frame;
struct dc_softc *sc = (struct dc_softc *)self;
int i, rval, phy_reg;

/*
* Note: both the AL981 and AN983 have internal PHYs,
* however the AL981 provides direct access to the PHY
* registers while the AN983 uses a serial MII interface.
* The AN983's MII interface is also buggy in that you
* can read from any MII address (0 to 31), but only address 1
* behaves normally. To deal with both cases, we pretend
* that the PHY is at MII address 1.
*/
if (DC_IS_ADMTEK(sc)(sc->dc_type == 0x6 || sc->dc_type == 0x7) && phy != DC_ADMTEK_PHYADDR0x1)
return (0);

/*
* Note: the ukphy probs of the RS7112 report a PHY at
* MII address 0 (possibly HomePNA?) and 1 (ethernet)
* so we only respond to correct one.
*/
if (DC_IS_CONEXANT(sc)(sc->dc_type == 0xC) && phy != DC_CONEXANT_PHYADDR0x1)
return (0);

if (sc->dc_pmode != DC_PMODE_MII0x1) {
if (phy == (MII_NPHY32 - 1)) {
	switch(reg) {
	case MII_BMSR0x01:
		/*
		 * Fake something to make the probe
		 * code think there's a PHY here.
		 */
		return (BMSR_MEDIAMASK(0x8000|0x4000|0x2000| 0x1000|0x0800|0x0400|0x0200));
		break;
	case MII_PHYIDR10x02:
		if (DC_IS_PNIC(sc)(sc->dc_type == 0xA))
			return (PCI_VENDOR_LITEON0x11ad);
		return (PCI_VENDOR_DEC0x1011);
		break;
	case MII_PHYIDR20x03:
		if (DC_IS_PNIC(sc)(sc->dc_type == 0xA))
			return (PCI_PRODUCT_LITEON_PNIC0x0002);
		return (PCI_PRODUCT_DEC_211420x0019);
		break;
	default:
		return (0);
		break;
	}
} else
	return (0);
}

if (DC_IS_PNIC(sc)(sc->dc_type == 0xA)) {
CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |((sc->dc_btag)->write_4((sc->dc_bhandle), (0xA0), (0x60020000
 | (phy << 23) | (reg << 18))))
    (phy << 23) | (reg << 18))((sc->dc_btag)->write_4((sc->dc_bhandle), (0xA0), (0x60020000
 | (phy << 23) | (reg << 18))));
for (i = 0; i < DC_TIMEOUT1000; i++) {
	DELAY(1)(*delay_func)(1);
	rval = CSR_READ_4(sc, DC_PN_MII)((sc->dc_btag)->read_4((sc->dc_bhandle), (0xA0)));
	if (!(rval & DC_PN_MII_BUSY0x80000000)) {
		rval &= 0xFFFF;
		return (rval == 0xFFFF ? 0 : rval);
	}
}
return (0);
}

if (DC_IS_COMET(sc)(sc->dc_type == 0x6)) {
switch(reg) {
case MII_BMCR0x00:
	phy_reg = DC_AL_BMCR0xB4;
	break;
case MII_BMSR0x01:
	phy_reg = DC_AL_BMSR0xB8;
	break;
case MII_PHYIDR10x02:
	phy_reg = DC_AL_VENID0xBC;
	break;
case MII_PHYIDR20x03:
	phy_reg = DC_AL_DEVID0xC0;
	break;
case MII_ANAR0x04:
	phy_reg = DC_AL_ANAR0xC4;
	break;
case MII_ANLPAR0x05:
	phy_reg = DC_AL_LPAR0xC8;
	break;
case MII_ANER0x06:
	phy_reg = DC_AL_ANER0xCC;
	break;
default:
	printf("%s: phy_read: bad phy register %x\n",
	    sc->sc_dev.dv_xname, reg);
	return (0);
	break;
}

rval = CSR_READ_4(sc, phy_reg)((sc->dc_btag)->read_4((sc->dc_bhandle), (phy_reg))) & 0x0000FFFF;

if (rval == 0xFFFF)
	return (0);
return (rval);
}

bzero(&frame, sizeof(frame))__builtin_bzero((&frame), (sizeof(frame)));

frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
if (sc->dc_type == DC_TYPE_987130x1) {
phy_reg = CSR_READ_4(sc, DC_NETCFG)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x30)));
CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), (phy_reg
 & ~0x00040000)));
}
dc_mii_readreg(sc, &frame);
if (sc->dc_type == DC_TYPE_987130x1)
CSR_WRITE_4(sc, DC_NETCFG, phy_reg)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), (phy_reg
)));

return (frame.mii_data);
746}

748void
749dc_miibus_writereg(struct device *self, int phy, int reg, int data)
750{
struct dc_softc *sc = (struct dc_softc *)self;
struct dc_mii_frame frame;
int i, phy_reg;
1
'phy_reg' declared without an initial value→

bzero(&frame, sizeof(frame))__builtin_bzero((&frame), (sizeof(frame)));

if (DC_IS_ADMTEK(sc)(sc->dc_type == 0x6 || sc->dc_type == 0x7) && phy != DC_ADMTEK_PHYADDR0x1)
2
←
Assuming field 'dc_type' is not equal to 6→
3
←
Assuming field 'dc_type' is equal to 7→
4
←
Assuming 'phy' is equal to DC_ADMTEK_PHYADDR→
return;
if (DC_IS_CONEXANT(sc)(sc->dc_type == 0xC) && phy != DC_CONEXANT_PHYADDR0x1)
5
←
Taking false branch→
return;

if (DC_IS_PNIC(sc)(sc->dc_type == 0xA)) {
6
←
Taking false branch→
CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |((sc->dc_btag)->write_4((sc->dc_bhandle), (0xA0), (0x50020000
 | (phy << 23) | (reg << 10) | data)))
    (phy << 23) | (reg << 10) | data)((sc->dc_btag)->write_4((sc->dc_bhandle), (0xA0), (0x50020000
 | (phy << 23) | (reg << 10) | data)));
for (i = 0; i < DC_TIMEOUT1000; i++) {
	if (!(CSR_READ_4(sc, DC_PN_MII)((sc->dc_btag)->read_4((sc->dc_bhandle), (0xA0))) & DC_PN_MII_BUSY0x80000000))
		break;
}
return;
}

if (DC_IS_COMET(sc)(sc->dc_type == 0x6)) {
7
←
Taking false branch→
switch(reg) {
case MII_BMCR0x00:
	phy_reg = DC_AL_BMCR0xB4;
	break;
case MII_BMSR0x01:
	phy_reg = DC_AL_BMSR0xB8;
	break;
case MII_PHYIDR10x02:
	phy_reg = DC_AL_VENID0xBC;
	break;
case MII_PHYIDR20x03:
	phy_reg = DC_AL_DEVID0xC0;
	break;
case MII_ANAR0x04:
	phy_reg = DC_AL_ANAR0xC4;
	break;
case MII_ANLPAR0x05:
	phy_reg = DC_AL_LPAR0xC8;
	break;
case MII_ANER0x06:
	phy_reg = DC_AL_ANER0xCC;
	break;
default:
	printf("%s: phy_write: bad phy register %x\n",
	    sc->sc_dev.dv_xname, reg);
	return;
}

CSR_WRITE_4(sc, phy_reg, data)((sc->dc_btag)->write_4((sc->dc_bhandle), (phy_reg),
 (data)));
return;
}

frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
frame.mii_data = data;

if (sc->dc_type7.1
Field 'dc_type' is not equal to DC_TYPE_98713
 == DC_TYPE_987130x1) {
8
←
Taking false branch→
phy_reg = CSR_READ_4(sc, DC_NETCFG)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x30)));
CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), (phy_reg
 & ~0x00040000)));
}
dc_mii_writereg(sc, &frame);
if (sc->dc_type == DC_TYPE_987130x1)
9
←
Assuming field 'dc_type' is equal to DC_TYPE_98713→
10
←
Taking true branch→
CSR_WRITE_4(sc, DC_NETCFG, phy_reg)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), (phy_reg
)));
11
←
3rd function call argument is an uninitialized value
816}

818void
819dc_miibus_statchg(struct device *self)
820{
struct dc_softc *sc = (struct dc_softc *)self;
struct mii_data *mii;
struct ifmedia *ifm;

if (DC_IS_ADMTEK(sc)(sc->dc_type == 0x6 || sc->dc_type == 0x7))
return;

mii = &sc->sc_mii;
ifm = &mii->mii_media;
if (DC_IS_DAVICOM(sc)(sc->dc_type == 0x8) && IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL) == IFM_HPNA_117) {
dc_setcfg(sc, ifm->ifm_media);
sc->dc_if_media = ifm->ifm_media;
} else {
dc_setcfg(sc, mii->mii_media_active);
sc->dc_if_media = mii->mii_media_active;
}
837}

839#define DC_BITS_5129	9
840#define DC_BITS_1287	7
841#define DC_BITS_646	6

843u_int32_t
844dc_crc_le(struct dc_softc *sc, caddr_t addr)
845{
u_int32_t crc;

/* Compute CRC for the address value. */
crc = ether_crc32_le(addr, ETHER_ADDR_LEN6);

/*
* The hash table on the PNIC II and the MX98715AEC-C/D/E
* chips is only 128 bits wide.
*/
if (sc->dc_flags & DC_128BIT_HASH0x00001000)
return (crc & ((1 << DC_BITS_1287) - 1));

/* The hash table on the MX98715BEC is only 64 bits wide. */
if (sc->dc_flags & DC_64BIT_HASH0x00002000)
return (crc & ((1 << DC_BITS_646) - 1));

/* Xircom's hash filtering table is different (read: weird) */
/* Xircom uses the LEAST significant bits */
if (DC_IS_XIRCOM(sc)(sc->dc_type == 0xB)) {
if ((crc & 0x180) == 0x180)
	return (crc & 0x0F) + (crc	& 0x70)*3 + (14 << 4);
else
	return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4);
}

return (crc & ((1 << DC_BITS_5129) - 1));
872}

874/*
* Calculate CRC of a multicast group address, return the lower 6 bits.
*/
877#define dc_crc_be(addr)((ether_crc32_be(addr,6) >> 26) & 0x0000003F)	((ether_crc32_be(addr,ETHER_ADDR_LEN6) >> 26) \
& 0x0000003F)

880/*
* 21143-style RX filter setup routine. Filter programming is done by
* downloading a special setup frame into the TX engine. 21143, Macronix,
* PNIC, PNIC II and Davicom chips are programmed this way.
*
* We always program the chip using 'hash perfect' mode, i.e. one perfect
* address (our node address) and a 512-bit hash filter for multicast
* frames. We also sneak the broadcast address into the hash filter since
* we need that too.
*/
890void
891dc_setfilt_21143(struct dc_softc *sc)
892{
struct arpcom *ac = &sc->sc_arpcom;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct ether_multi *enm;
struct ether_multistep step;
struct dc_desc *sframe;
u_int32_t h, *sp;
int i;

i = sc->dc_cdata.dc_tx_prod;
DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT)(sc->dc_cdata.dc_tx_prod) = (sc->dc_cdata.dc_tx_prod + 1
) % 256;
sc->dc_cdata.dc_tx_cnt++;
sframe = &sc->dc_ldata->dc_tx_list[i];
sp = &sc->dc_ldata->dc_sbuf[0];
bzero(sp, DC_SFRAME_LEN)__builtin_bzero((sp), (192));

sframe->dc_datadc_ptr1 = htole32(sc->sc_listmap->dm_segs[0].ds_addr +((__uint32_t)(sc->sc_listmap->dm_segs[0].ds_addr + __builtin_offsetof
(struct dc_list_data, dc_sbuf)))
   offsetof(struct dc_list_data, dc_sbuf))((__uint32_t)(sc->sc_listmap->dm_segs[0].ds_addr + __builtin_offsetof
(struct dc_list_data, dc_sbuf)));
sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |((__uint32_t)(192 | 0x08000000 | 0x01000000 | 0x00400000 | 0x80000000
))
   DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT)((__uint32_t)(192 | 0x08000000 | 0x01000000 | 0x00400000 | 0x80000000
));

sc->dc_cdata.dc_tx_chain[i].sd_mbuf =
   (struct mbuf *)&sc->dc_ldata->dc_sbuf[0];

DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ALLMULTI | DC_NETCFG_RX_PROMISC))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00000080 | 0x00000040)))));
ifp->if_flags &= ~IFF_ALLMULTI0x200;

if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI0x200;
if (ifp->if_flags & IFF_PROMISC0x100)
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000040))));
else
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000080))));
} else {
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	h = dc_crc_le(sc, enm->enm_addrlo);

	sp[h >> 4] |= htole32(1 << (h & 0xF))((__uint32_t)(1 << (h & 0xF)));

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}
}

/*
* Always accept broadcast frames.
*/
h = dc_crc_le(sc, (caddr_t)&etherbroadcastaddr);
sp[h >> 4] |= htole32(1 << (h & 0xF))((__uint32_t)(1 << (h & 0xF)));

/* Set our MAC address */
sp[39] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 0)(((u_int16_t *)(sc->sc_arpcom.ac_enaddr))[(0)]);
sp[40] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 1)(((u_int16_t *)(sc->sc_arpcom.ac_enaddr))[(1)]);
sp[41] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 2)(((u_int16_t *)(sc->sc_arpcom.ac_enaddr))[(2)]);

bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_sbuf
[0])), (sizeof(struct dc_list_data) - __builtin_offsetof(struct
 dc_list_data, dc_sbuf[0])), (0x01 | 0x04))
   offsetof(struct dc_list_data, dc_sbuf[0]),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_sbuf
[0])), (sizeof(struct dc_list_data) - __builtin_offsetof(struct
 dc_list_data, dc_sbuf[0])), (0x01 | 0x04))
   sizeof(struct dc_list_data) -(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_sbuf
[0])), (sizeof(struct dc_list_data) - __builtin_offsetof(struct
 dc_list_data, dc_sbuf[0])), (0x01 | 0x04)) 
   offsetof(struct dc_list_data, dc_sbuf[0]),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_sbuf
[0])), (sizeof(struct dc_list_data) - __builtin_offsetof(struct
 dc_list_data, dc_sbuf[0])), (0x01 | 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_sbuf
[0])), (sizeof(struct dc_list_data) - __builtin_offsetof(struct
 dc_list_data, dc_sbuf[0])), (0x01 | 0x04));

sframe->dc_status = htole32(DC_TXSTAT_OWN)((__uint32_t)(0x80000000));

bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
[i])), (sizeof(struct dc_desc)), (0x01 | 0x04))
   offsetof(struct dc_list_data, dc_tx_list[i]),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
[i])), (sizeof(struct dc_desc)), (0x01 | 0x04))
   sizeof(struct dc_desc), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
[i])), (sizeof(struct dc_desc)), (0x01 | 0x04));

CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x08), (0xFFFFFFFF
)));

/*
* The PNIC takes an exceedingly long time to process its
* setup frame; wait 10ms after posting the setup frame
* before proceeding, just so it has time to swallow its
* medicine.
*/
DELAY(10000)(*delay_func)(10000);

ifp->if_timer = 5;
970}

972void
973dc_setfilt_admtek(struct dc_softc *sc)
974{
struct arpcom *ac = &sc->sc_arpcom;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct ether_multi *enm;
struct ether_multistep step;
u_int32_t hashes[2];
int h = 0;

DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ALLMULTI | DC_NETCFG_RX_PROMISC))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00000080 | 0x00000040)))));
bzero(hashes, sizeof(hashes))__builtin_bzero((hashes), (sizeof(hashes)));
ifp->if_flags &= ~IFF_ALLMULTI0x200;

if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI0x200;
if (ifp->if_flags & IFF_PROMISC0x100)
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000040))));
else
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000080))));
} else {
/* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	if (DC_IS_CENTAUR(sc)(sc->dc_type == 0x7))
		h = dc_crc_le(sc, enm->enm_addrlo);
	else
		h = dc_crc_be(enm->enm_addrlo)((ether_crc32_be(enm->enm_addrlo,6) >> 26) & 0x0000003F
);

	if (h < 32)
		hashes[0] |= (1 << h);
	else
		hashes[1] |= (1 << (h - 32));

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}
}

/* Init our MAC address */
CSR_WRITE_4(sc, DC_AL_PAR0, ac->ac_enaddr[3] << 24 |((sc->dc_btag)->write_4((sc->dc_bhandle), (0xA4), (ac
->ac_enaddr[3] << 24 | ac->ac_enaddr[2] << 16
 | ac->ac_enaddr[1] << 8 | ac->ac_enaddr[0])))
   ac->ac_enaddr[2] << 16 | ac->ac_enaddr[1] << 8 | ac->ac_enaddr[0])((sc->dc_btag)->write_4((sc->dc_bhandle), (0xA4), (ac
->ac_enaddr[3] << 24 | ac->ac_enaddr[2] << 16
 | ac->ac_enaddr[1] << 8 | ac->ac_enaddr[0])));
CSR_WRITE_4(sc, DC_AL_PAR1, ac->ac_enaddr[5] << 8 | ac->ac_enaddr[4])((sc->dc_btag)->write_4((sc->dc_bhandle), (0xA8), (ac
->ac_enaddr[5] << 8 | ac->ac_enaddr[4])));

CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0])((sc->dc_btag)->write_4((sc->dc_bhandle), (0xAC), (hashes
[0])));
CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1])((sc->dc_btag)->write_4((sc->dc_bhandle), (0xB0), (hashes
[1])));
1017}

1019void
1020dc_setfilt_asix(struct dc_softc *sc)
1021{
struct arpcom *ac = &sc->sc_arpcom;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct ether_multi *enm;
struct ether_multistep step;
u_int32_t hashes[2];
int h = 0;

DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ALLMULTI | DC_AX_NETCFG_RX_BROAD |((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00000080 | 0x00000100 | 0x00000040)))))
   DC_NETCFG_RX_PROMISC))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00000080 | 0x00000100 | 0x00000040)))));
bzero(hashes, sizeof(hashes))__builtin_bzero((hashes), (sizeof(hashes)));
ifp->if_flags &= ~IFF_ALLMULTI0x200;

/*
* Always accept broadcast frames.
*/
DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000100))));

if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI0x200;
if (ifp->if_flags & IFF_PROMISC0x100)
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000040))));
else
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000080))));
} else {
/* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	h = dc_crc_be(enm->enm_addrlo)((ether_crc32_be(enm->enm_addrlo,6) >> 26) & 0x0000003F
);

	if (h < 32)
		hashes[0] |= (1 << h);
	else
		hashes[1] |= (1 << (h - 32));

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}
}

/* Init our MAC address */
CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x68), (0x00000000
)));
CSR_WRITE_4(sc, DC_AX_FILTDATA,((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), (*
(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[0]))))
   *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[0]))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), (*
(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[0]))));
CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x68), (0x00000001
)));
CSR_WRITE_4(sc, DC_AX_FILTDATA,((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), (*
(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[4]))))
   *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[4]))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), (*
(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[4]))));

CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x68), (0x00000002
)));
CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0])((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), (hashes
[0])));
CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x68), (0x00000003
)));
CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1])((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), (hashes
[1])));
1072}

1074void
1075dc_setfilt_xircom(struct dc_softc *sc)
1076{
struct arpcom *ac = &sc->sc_arpcom;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct ether_multi *enm;
struct ether_multistep step;
struct dc_desc *sframe;
u_int32_t h, *sp;
int i;

DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00002000|0x00000002)))));

i = sc->dc_cdata.dc_tx_prod;
DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT)(sc->dc_cdata.dc_tx_prod) = (sc->dc_cdata.dc_tx_prod + 1
) % 256;
sc->dc_cdata.dc_tx_cnt++;
sframe = &sc->dc_ldata->dc_tx_list[i];
sp = &sc->dc_ldata->dc_sbuf[0];
bzero(sp, DC_SFRAME_LEN)__builtin_bzero((sp), (192));

sframe->dc_datadc_ptr1 = htole32(sc->sc_listmap->dm_segs[0].ds_addr +((__uint32_t)(sc->sc_listmap->dm_segs[0].ds_addr + __builtin_offsetof
(struct dc_list_data, dc_sbuf)))
   offsetof(struct dc_list_data, dc_sbuf))((__uint32_t)(sc->sc_listmap->dm_segs[0].ds_addr + __builtin_offsetof
(struct dc_list_data, dc_sbuf)));
sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |((__uint32_t)(192 | 0x08000000 | 0x01000000 | 0x00400000 | 0x80000000
))
   DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT)((__uint32_t)(192 | 0x08000000 | 0x01000000 | 0x00400000 | 0x80000000
));

sc->dc_cdata.dc_tx_chain[i].sd_mbuf =
   (struct mbuf *)&sc->dc_ldata->dc_sbuf[0];

DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ALLMULTI | DC_NETCFG_RX_PROMISC))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00000080 | 0x00000040)))));
ifp->if_flags &= ~IFF_ALLMULTI0x200;

if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI0x200;
if (ifp->if_flags & IFF_PROMISC0x100)
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000040))));
else
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000080))));
} else {
/* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	h = dc_crc_le(sc, enm->enm_addrlo);

	sp[h >> 4] |= htole32(1 << (h & 0xF))((__uint32_t)(1 << (h & 0xF)));

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}
}

/*
* Always accept broadcast frames.
*/
h = dc_crc_le(sc, (caddr_t)&etherbroadcastaddr);
sp[h >> 4] |= htole32(1 << (h & 0xF))((__uint32_t)(1 << (h & 0xF)));

/* Set our MAC address */
sp[0] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 0)(((u_int16_t *)(sc->sc_arpcom.ac_enaddr))[(0)]);
sp[1] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 1)(((u_int16_t *)(sc->sc_arpcom.ac_enaddr))[(1)]);
sp[2] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 2)(((u_int16_t *)(sc->sc_arpcom.ac_enaddr))[(2)]);

DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00002000))));
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000002))));
ifp->if_flags |= IFF_RUNNING0x40;
sframe->dc_status = htole32(DC_TXSTAT_OWN)((__uint32_t)(0x80000000));
CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x08), (0xFFFFFFFF
)));

/*
* wait some time...
*/
DELAY(1000)(*delay_func)(1000);

ifp->if_timer = 5;
1146}

1148void
1149dc_setfilt(struct dc_softc *sc)
1150{
if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD) || DC_IS_MACRONIX(sc)(sc->dc_type == 0x1 || sc->dc_type == 0x2 || sc->dc_type
 == 0x3) || DC_IS_PNIC(sc)(sc->dc_type == 0xA) ||
   DC_IS_PNICII(sc)(sc->dc_type == 0x9) || DC_IS_DAVICOM(sc)(sc->dc_type == 0x8) || DC_IS_CONEXANT(sc)(sc->dc_type == 0xC))
dc_setfilt_21143(sc);

if (DC_IS_ASIX(sc)(sc->dc_type == 0x5))
dc_setfilt_asix(sc);

if (DC_IS_ADMTEK(sc)(sc->dc_type == 0x6 || sc->dc_type == 0x7))
dc_setfilt_admtek(sc);

if (DC_IS_XIRCOM(sc)(sc->dc_type == 0xB))
dc_setfilt_xircom(sc);
1163}

1165/*
* In order to fiddle with the
* 'full-duplex' and '100Mbps' bits in the netconfig register, we
* first have to put the transmit and/or receive logic in the idle state.
*/
1170void
1171dc_setcfg(struct dc_softc *sc, uint64_t media)
1172{
int i, restart = 0;
u_int32_t isr;

if (IFM_SUBTYPE(media)((media) & 0x00000000000000ffULL) == IFM_NONE2ULL)
return;

if (CSR_READ_4(sc, DC_NETCFG)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) & (DC_NETCFG_TX_ON0x00002000|DC_NETCFG_RX_ON0x00000002)) {
restart = 1;
DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00002000|0x00000002)))));

for (i = 0; i < DC_TIMEOUT1000; i++) {
	isr = CSR_READ_4(sc, DC_ISR)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x28)));
	if (isr & DC_ISR_TX_IDLE0x00000002 &&
	    ((isr & DC_ISR_RX_STATE0x000E0000) == DC_RXSTATE_STOPPED0x00000000 ||
	    (isr & DC_ISR_RX_STATE0x000E0000) == DC_RXSTATE_WAIT0x00060000))
		break;
	DELAY(10)(*delay_func)(10);
}

if (i == DC_TIMEOUT1000) {
	if (!(isr & DC_ISR_TX_IDLE0x00000002) && !DC_IS_ASIX(sc)(sc->dc_type == 0x5))
		printf("%s: failed to force tx to idle state\n",
		    sc->sc_dev.dv_xname);
	if (!((isr & DC_ISR_RX_STATE0x000E0000) == DC_RXSTATE_STOPPED0x00000000 ||
	    (isr & DC_ISR_RX_STATE0x000E0000) == DC_RXSTATE_WAIT0x00060000) &&
	    !DC_HAS_BROKEN_RXSTATE(sc)((sc->dc_type == 0x7) || (sc->dc_type == 0xC) || ((sc->
dc_type == 0x8) && sc->dc_revision >= 0x30)))
		printf("%s: failed to force rx to idle state\n",
		    sc->sc_dev.dv_xname);
}
}

if (IFM_SUBTYPE(media)((media) & 0x00000000000000ffULL) == IFM_100_TX6) {
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00400000))));
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00080000))));
if (sc->dc_pmode == DC_PMODE_MII0x1) {
	int watchdogreg;

	if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD)) {
	/* there's a write enable bit here that reads as 1 */
		watchdogreg = CSR_READ_4(sc, DC_WATCHDOG)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x78)));
		watchdogreg &= ~DC_WDOG_CTLWREN0x08000000;
		watchdogreg |= DC_WDOG_JABBERDIS0x00000001;
		CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (watchdogreg
)));
	} else {
		DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x78))) | (
0x00000001))));
	}
	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00800000| 0x00040000|0x01000000)))))
	    DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00800000| 0x00040000|0x01000000)))));
	if (sc->dc_type == DC_TYPE_987130x1)
		DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
(0x00800000| 0x01000000)))))
		    DC_NETCFG_SCRAMBLER))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
(0x00800000| 0x01000000)))));
	if (!DC_IS_DAVICOM(sc)(sc->dc_type == 0x8))
		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00040000))));
	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x70))) &
 ~(0xFFFF))));
	if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD))
		dc_apply_fixup(sc, IFM_AUTO0ULL);
} else {
	if (DC_IS_PNIC(sc)(sc->dc_type == 0xA)) {
		DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x60), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x60))) | (
((0x000000001) | (0x000000001 << 4))))));
		DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x60), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x60))) | (
((0x000000002) | (0x000000002 << 4))))));
		DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0xB8), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0xB8))) | (
0x00000800))));
	}
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00040000))));
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00800000))));
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x01000000))));
	if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD))
		dc_apply_fixup(sc,
		    (media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL ?
		    IFM_100_TX6|IFM_FDX0x0000010000000000ULL : IFM_100_TX6);
}
}

if (IFM_SUBTYPE(media)((media) & 0x00000000000000ffULL) == IFM_10_T3) {
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00400000))));
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00080000))));
if (sc->dc_pmode == DC_PMODE_MII0x1) {
	int watchdogreg;

	if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD)) {
	/* there's a write enable bit here that reads as 1 */
		watchdogreg = CSR_READ_4(sc, DC_WATCHDOG)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x78)));
		watchdogreg &= ~DC_WDOG_CTLWREN0x08000000;
		watchdogreg |= DC_WDOG_JABBERDIS0x00000001;
		CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (watchdogreg
)));
	} else {
		DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x78))) | (
0x00000001))));
	}
	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00800000| 0x00040000|0x01000000)))))
	    DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00800000| 0x00040000|0x01000000)))));
	if (sc->dc_type == DC_TYPE_987130x1)
		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00800000))));
	if (!DC_IS_DAVICOM(sc)(sc->dc_type == 0x8))
		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00040000))));
	DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x70))) &
 ~(0xFFFF))));
	if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD))
		dc_apply_fixup(sc, IFM_AUTO0ULL);
} else {
	if (DC_IS_PNIC(sc)(sc->dc_type == 0xA)) {
		DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL){ ((sc->dc_btag)->write_4((sc->dc_bhandle), (0x60), (
((sc->dc_btag)->read_4((sc->dc_bhandle), (0x60))) | (
((0x000000001) << 4))))); ((sc->dc_btag)->write_4
((sc->dc_bhandle), (0x60), (((sc->dc_btag)->read_4((
sc->dc_bhandle), (0x60))) & ~((0x000000001))))); };
		DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x60), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x60))) | (
((0x000000002) | (0x000000002 << 4))))));
		DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0xB8), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0xB8))) &
 ~(0x00000800))));
	}
	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00040000))));
	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00800000))));
	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x01000000))));
	if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD)) {
		DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x68), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x68))) &
 ~(0x00000001))));
		DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x70))) &
 ~(0xFFFF))));
		if ((media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL)
			DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x70))) | (
0x7F3D))));
		else
			DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x70))) | (
0x7F3F))));
		DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x68), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x68))) | (
0x00000001))));
		DC_CLRBIT(sc, DC_10BTCTRL,((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x70))) &
 ~(0x00000080))))
		    DC_TCTL_AUTONEGENBL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x70))) &
 ~(0x00000080))));
		dc_apply_fixup(sc,
		    (media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL ?
		    IFM_10_T3|IFM_FDX0x0000010000000000ULL : IFM_10_T3);
		DELAY(20000)(*delay_func)(20000);
	}
}
}

/*
* If this is a Davicom DM9102A card with a DM9801 HomePNA
* PHY and we want HomePNA mode, set the portsel bit to turn
* on the external MII port.
*/
if (DC_IS_DAVICOM(sc)(sc->dc_type == 0x8)) {
if (IFM_SUBTYPE(media)((media) & 0x00000000000000ffULL) == IFM_HPNA_117) {
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00040000))));
	sc->dc_link = 1;
} else {
	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00040000))));
}
}

if ((media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL) {
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000200))));
if (sc->dc_pmode == DC_PMODE_SYM0x2 && DC_IS_PNIC(sc)(sc->dc_type == 0xA))
	DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX)((sc->dc_btag)->write_4((sc->dc_bhandle), (0xB8), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0xB8))) | (
0x00000100))));
} else {
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00000200))));
if (sc->dc_pmode == DC_PMODE_SYM0x2 && DC_IS_PNIC(sc)(sc->dc_type == 0xA))
	DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX)((sc->dc_btag)->write_4((sc->dc_bhandle), (0xB8), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0xB8))) &
 ~(0x00000100))));
}

if (restart)
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00002000|0x00000002))));
1322}

1324void
1325dc_reset(struct dc_softc *sc)
1326{
int i;

DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x00000001))));

for (i = 0; i < DC_TIMEOUT1000; i++) {
DELAY(10)(*delay_func)(10);
if (!(CSR_READ_4(sc, DC_BUSCTL)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) & DC_BUSCTL_RESET0x00000001))
	break;
}

if (DC_IS_ASIX(sc)(sc->dc_type == 0x5) || DC_IS_ADMTEK(sc)(sc->dc_type == 0x6 || sc->dc_type == 0x7) || DC_IS_XIRCOM(sc)(sc->dc_type == 0xB) ||
   DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD) || DC_IS_CONEXANT(sc)(sc->dc_type == 0xC)) {
DELAY(10000)(*delay_func)(10000);
DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) &
 ~(0x00000001))));
i = 0;
}

if (i == DC_TIMEOUT1000)
printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);

/* Wait a little while for the chip to get its brains in order. */
DELAY(1000)(*delay_func)(1000);

CSR_WRITE_4(sc, DC_IMR, 0x00000000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x38), (0x00000000
)));
CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), (0x00000000
)));
CSR_WRITE_4(sc, DC_NETCFG, 0x00000000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), (0x00000000
)));

/*
* Bring the SIA out of reset. In some cases, it looks
* like failing to unreset the SIA soon enough gets it
* into a state where it will never come out of reset
* until we reset the whole chip again.
*/
if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD)) {
DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x68), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x68))) | (
0x00000001))));
CSR_WRITE_4(sc, DC_10BTCTRL, 0)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x70), (0
)));
CSR_WRITE_4(sc, DC_WATCHDOG, 0)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0
)));
}

if (sc->dc_type == DC_TYPE_211450xD)
dc_setcfg(sc, IFM_10_T3);
1368}

1370void
1371dc_apply_fixup(struct dc_softc *sc, uint64_t media)
1372{
struct dc_mediainfo *m;
u_int8_t *p;
int i;
u_int32_t reg;

m = sc->dc_mi;

while (m != NULL((void *)0)) {
if (m->dc_media == media)
	break;
m = m->dc_nextdc_ptr2;
}

if (m == NULL((void *)0))
return;

for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
reg = (p[0] | (p[1] << 8)) << 16;
CSR_WRITE_4(sc, DC_WATCHDOG, reg)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (reg
)));
}

for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
reg = (p[0] | (p[1] << 8)) << 16;
CSR_WRITE_4(sc, DC_WATCHDOG, reg)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (reg
)));
}
1398}

1400void
1401dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1402{
struct dc_mediainfo *m;

m = malloc(sizeof(*m), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (m == NULL((void *)0))
return;
switch (l->dc_sia_code & ~DC_SIA_CODE_EXT0x40) {
case DC_SIA_CODE_10BT0x00:
m->dc_media = IFM_10_T3;
break;
case DC_SIA_CODE_10BT_FDX0x04:
m->dc_media = IFM_10_T3|IFM_FDX0x0000010000000000ULL;
break;
case DC_SIA_CODE_10B20x01:
m->dc_media = IFM_10_24;
break;
case DC_SIA_CODE_10B50x02:
m->dc_media = IFM_10_55;
break;
default:
break;
}

/*
* We need to ignore CSR13, CSR14, CSR15 for SIA mode.
* Things apparently already work for cards that do
* supply Media Specific Data.
*/
if (l->dc_sia_code & DC_SIA_CODE_EXT0x40) {
m->dc_gp_len = 2;
m->dc_gp_ptr =
(u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
} else {
m->dc_gp_len = 2;
m->dc_gp_ptr =
(u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
}

m->dc_nextdc_ptr2 = sc->dc_mi;
sc->dc_mi = m;

sc->dc_pmode = DC_PMODE_SIA0x3;
1444}

1446void
1447dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1448{
struct dc_mediainfo *m;

m = malloc(sizeof(*m), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (m == NULL((void *)0))
return;
if (l->dc_sym_code == DC_SYM_CODE_100BT0x03)
m->dc_media = IFM_100_TX6;

if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX0x05)
m->dc_media = IFM_100_TX6|IFM_FDX0x0000010000000000ULL;

m->dc_gp_len = 2;
m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;

m->dc_nextdc_ptr2 = sc->dc_mi;
sc->dc_mi = m;

sc->dc_pmode = DC_PMODE_SYM0x2;
1467}

1469void
1470dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1471{
u_int8_t *p;
struct dc_mediainfo *m;

m = malloc(sizeof(*m), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (m == NULL((void *)0))
return;
/* We abuse IFM_AUTO to represent MII. */
m->dc_media = IFM_AUTO0ULL;
m->dc_gp_len = l->dc_gpr_len;

p = (u_int8_t *)l;
p += sizeof(struct dc_eblock_mii);
m->dc_gp_ptr = p;
p += 2 * l->dc_gpr_len;
m->dc_reset_len = *p;
p++;
m->dc_reset_ptr = p;

m->dc_nextdc_ptr2 = sc->dc_mi;
sc->dc_mi = m;
1492}

1494void
1495dc_read_srom(struct dc_softc *sc, int bits)
1496{
sc->dc_sromsize = 2 << bits;
sc->dc_srom = malloc(sc->dc_sromsize, M_DEVBUF2, M_NOWAIT0x0002);
if (sc->dc_srom == NULL((void *)0))
return;
dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (sc->dc_sromsize / 2), 0);
1502}

1504void
1505dc_parse_21143_srom(struct dc_softc *sc)
1506{
struct dc_leaf_hdr *lhdr;
struct dc_eblock_hdr *hdr;
int have_mii, i, loff;
char *ptr;

have_mii = 0;
loff = sc->dc_srom[27];
lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);

ptr = (char *)lhdr;
ptr += sizeof(struct dc_leaf_hdr) - 1;
/*
* Look if we got a MII media block.
*/
for (i = 0; i < lhdr->dc_mcnt; i++) {
hdr = (struct dc_eblock_hdr *)ptr;
if (hdr->dc_type == DC_EBLOCK_MII0x0003)
    have_mii++;

ptr += (hdr->dc_len & 0x7F);
ptr++;
}

/*
* Do the same thing again. Only use SIA and SYM media
* blocks if no MII media block is available.
*/
ptr = (char *)lhdr;
ptr += sizeof(struct dc_leaf_hdr) - 1;
for (i = 0; i < lhdr->dc_mcnt; i++) {
hdr = (struct dc_eblock_hdr *)ptr;
switch(hdr->dc_type) {
case DC_EBLOCK_MII0x0003:
	dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
	break;
case DC_EBLOCK_SIA0x0002:
	if (! have_mii)
	    dc_decode_leaf_sia(sc,
		(struct dc_eblock_sia *)hdr);
	break;
case DC_EBLOCK_SYM0x0004:
	if (! have_mii)
	    dc_decode_leaf_sym(sc,
		(struct dc_eblock_sym *)hdr);
	break;
default:
	/* Don't care. Yet. */
	break;
}
ptr += (hdr->dc_len & 0x7F);
ptr++;
}
1559}

1561/*
* Attach the interface. Allocate softc structures, do ifmedia
* setup and ethernet/BPF attach.
*/
1565void
1566dc_attach(struct dc_softc *sc)
1567{
struct ifnet *ifp;
int mac_offset, tmp, i;
u_int32_t reg;

/*
* Get station address from the EEPROM.
*/
if (sc->sc_hasmac)
goto hasmac;

switch(sc->dc_type) {
case DC_TYPE_987130x1:
case DC_TYPE_98713A0x2:
case DC_TYPE_987x50x3:
case DC_TYPE_PNICII0x9:
dc_read_eeprom(sc, (caddr_t)&mac_offset,
    (DC_EE_NODEADDR_OFFSET0x70 / 2), 1, 0);
dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
    (mac_offset / 2), 3, 0);
break;
case DC_TYPE_PNIC0xA:
dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr, 0, 3, 1);
break;
case DC_TYPE_DM91020x8:
case DC_TYPE_211430x4:
case DC_TYPE_211450xD:
case DC_TYPE_ASIX0x5:
dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,	
    DC_EE_NODEADDR10, 3, 0);
break;
case DC_TYPE_AL9810x6:
case DC_TYPE_AN9830x7:
reg = CSR_READ_4(sc, DC_AL_PAR0)((sc->dc_btag)->read_4((sc->dc_bhandle), (0xA4)));
sc->sc_arpcom.ac_enaddr[0] = (reg & 0xff);
sc->sc_arpcom.ac_enaddr[1] = (reg >> 8) & 0xff;
sc->sc_arpcom.ac_enaddr[2] = (reg >> 16) & 0xff;
sc->sc_arpcom.ac_enaddr[3] = (reg >> 24) & 0xff;
reg = CSR_READ_4(sc, DC_AL_PAR1)((sc->dc_btag)->read_4((sc->dc_bhandle), (0xA8)));
sc->sc_arpcom.ac_enaddr[4] = (reg & 0xff);
sc->sc_arpcom.ac_enaddr[5] = (reg >> 8) & 0xff;
break;
case DC_TYPE_CONEXANT0xC:
bcopy(&sc->dc_srom + DC_CONEXANT_EE_NODEADDR0x19A,
    &sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN6);
break;
case DC_TYPE_XIRCOM0xB:
/* Some newer units have the MAC at offset 8 */
dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr, 8, 3, 0);

if (sc->sc_arpcom.ac_enaddr[0] == 0x00 &&
    sc->sc_arpcom.ac_enaddr[1] == 0x10 &&
    sc->sc_arpcom.ac_enaddr[2] == 0xa4)
	break;
if (sc->sc_arpcom.ac_enaddr[0] == 0x00 &&
    sc->sc_arpcom.ac_enaddr[1] == 0x80 &&
    sc->sc_arpcom.ac_enaddr[2] == 0xc7)
	break;
dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr, 3, 3, 0);
break;
default:
dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
    DC_EE_NODEADDR10, 3, 0);
break;
}
1632hasmac:

if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct dc_list_data),(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (sizeof
(struct dc_list_data)), ((1 << 12)), (0), (sc->sc_listseg
), (1), (&sc->sc_listnseg), (0x0001 | 0x1000))
   PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (sizeof
(struct dc_list_data)), ((1 << 12)), (0), (sc->sc_listseg
), (1), (&sc->sc_listnseg), (0x0001 | 0x1000))
   BUS_DMA_NOWAIT | BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (sizeof
(struct dc_list_data)), ((1 << 12)), (0), (sc->sc_listseg
), (1), (&sc->sc_listnseg), (0x0001 | 0x1000)) != 0) {
printf(": can't alloc list mem\n");
goto fail;
}
if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (sc->
sc_listseg), (sc->sc_listnseg), (sizeof(struct dc_list_data
)), (&sc->sc_listkva), (0x0001))
   sizeof(struct dc_list_data), &sc->sc_listkva,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (sc->
sc_listseg), (sc->sc_listnseg), (sizeof(struct dc_list_data
)), (&sc->sc_listkva), (0x0001))
   BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (sc->
sc_listseg), (sc->sc_listnseg), (sizeof(struct dc_list_data
)), (&sc->sc_listkva), (0x0001)) != 0) {
printf(": can't map list mem\n");
goto fail;
}
if (bus_dmamap_create(sc->sc_dmat, sizeof(struct dc_list_data), 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (sizeof
(struct dc_list_data)), (1), (sizeof(struct dc_list_data)), (
0), (0x0001), (&sc->sc_listmap))
   sizeof(struct dc_list_data), 0, BUS_DMA_NOWAIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (sizeof
(struct dc_list_data)), (1), (sizeof(struct dc_list_data)), (
0), (0x0001), (&sc->sc_listmap))
   &sc->sc_listmap)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (sizeof
(struct dc_list_data)), (1), (sizeof(struct dc_list_data)), (
0), (0x0001), (&sc->sc_listmap)) != 0) {
printf(": can't alloc list map\n");
goto fail;
}
if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
sc_listmap), (sc->sc_listkva), (sizeof(struct dc_list_data
)), (((void *)0)), (0x0001))
   sizeof(struct dc_list_data), NULL, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
sc_listmap), (sc->sc_listkva), (sizeof(struct dc_list_data
)), (((void *)0)), (0x0001)) != 0) {
printf(": can't load list map\n");
goto fail;
}
sc->dc_ldata = (struct dc_list_data *)sc->sc_listkva;

for (i = 0; i < DC_RX_LIST_CNT64; i++) {
if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), (1), ((1 << 11)), (0), (0x0001), (&sc->dc_cdata
.dc_rx_chain[i].sd_map))
    0, BUS_DMA_NOWAIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), (1), ((1 << 11)), (0), (0x0001), (&sc->dc_cdata
.dc_rx_chain[i].sd_map))
    &sc->dc_cdata.dc_rx_chain[i].sd_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), (1), ((1 << 11)), (0), (0x0001), (&sc->dc_cdata
.dc_rx_chain[i].sd_map)) != 0) {
	printf(": can't create rx map\n");
	return;
}
}
if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), (1), ((1 << 11)), (0), (0x0001), (&sc->sc_rx_sparemap
))
   BUS_DMA_NOWAIT, &sc->sc_rx_sparemap)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), (1), ((1 << 11)), (0), (0x0001), (&sc->sc_rx_sparemap
)) != 0) {
printf(": can't create rx spare map\n");
return;
}	

for (i = 0; i < DC_TX_LIST_CNT256; i++) {
if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), ((sc->dc_flags & 0x00000002) ? 1 : 256 - 5), ((
<< 11)), (0), (0x0001), (&sc->dc_cdata.dc_tx_chain
[i].sd_map))
    (sc->dc_flags & DC_TX_COALESCE) ? 1 : DC_TX_LIST_CNT - 5,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), ((sc->dc_flags & 0x00000002) ? 1 : 256 - 5), ((
<< 11)), (0), (0x0001), (&sc->dc_cdata.dc_tx_chain
[i].sd_map))
    MCLBYTES, 0, BUS_DMA_NOWAIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), ((sc->dc_flags & 0x00000002) ? 1 : 256 - 5), ((
<< 11)), (0), (0x0001), (&sc->dc_cdata.dc_tx_chain
[i].sd_map))
    &sc->dc_cdata.dc_tx_chain[i].sd_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), ((sc->dc_flags & 0x00000002) ? 1 : 256 - 5), ((
<< 11)), (0), (0x0001), (&sc->dc_cdata.dc_tx_chain
[i].sd_map)) != 0) {
	printf(": can't create tx map\n");
	return;
}
}
if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), ((sc->dc_flags & 0x00000002) ? 1 : 256 - 5), ((
<< 11)), (0), (0x0001), (&sc->sc_tx_sparemap))
   (sc->dc_flags & DC_TX_COALESCE) ? 1 : DC_TX_LIST_CNT - 5,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), ((sc->dc_flags & 0x00000002) ? 1 : 256 - 5), ((
<< 11)), (0), (0x0001), (&sc->sc_tx_sparemap))
   MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
 11)), ((sc->dc_flags & 0x00000002) ? 1 : 256 - 5), ((
<< 11)), (0), (0x0001), (&sc->sc_tx_sparemap)) != 0) {
printf(": can't create tx spare map\n");
return;
}

/*
* A 21143 or clone chip was detected. Inform the world.
*/
printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));

ifp = &sc->sc_arpcom.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
ifp->if_ioctl = dc_ioctl;
ifp->if_start = dc_start;
ifp->if_watchdog = dc_watchdog;
ifq_init_maxlen(&ifp->if_snd, DC_TX_LIST_CNT256 - 1);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ16);

ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010;

/* Do MII setup. If this is a 21143, check for a PHY on the
* MII bus after applying any necessary fixups to twiddle the
* GPIO bits. If we don't end up finding a PHY, restore the
* old selection (SIA only or SIA/SYM) and attach the dcphy
* driver instead.
*/
if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD)) {
dc_apply_fixup(sc, IFM_AUTO0ULL);
tmp = sc->dc_pmode;
sc->dc_pmode = DC_PMODE_MII0x1;
}

/*
* Setup General Purpose port mode and data so the tulip can talk
* to the MII.  This needs to be done before mii_attach so that
* we can actually see them.
*/
if (DC_IS_XIRCOM(sc)(sc->dc_type == 0xB)) {
CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x08000000
 | 0x02000000 | 0x00040000 | 0x00010000)))
    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x08000000
 | 0x02000000 | 0x00040000 | 0x00010000)));
DELAY(10)(*delay_func)(10);
CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x02000000
 | 0x00040000 | 0x00010000)))
    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x02000000
 | 0x00040000 | 0x00010000)));
DELAY(10)(*delay_func)(10);
}

sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = dc_miibus_readreg;
sc->sc_mii.mii_writereg = dc_miibus_writereg;
sc->sc_mii.mii_statchg = dc_miibus_statchg;
ifmedia_init(&sc->sc_mii.mii_media, 0, dc_ifmedia_upd, dc_ifmedia_sts);
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY-1,
   MII_OFFSET_ANY-1, 0);

if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD)) {
if (LIST_EMPTY(&sc->sc_mii.mii_phys)(((&sc->sc_mii.mii_phys)->lh_first) == ((void *)0))) {
	sc->dc_pmode = tmp;
	if (sc->dc_pmode != DC_PMODE_SIA0x3)
		sc->dc_pmode = DC_PMODE_SYM0x2;
	sc->dc_flags |= DC_21143_NWAY0x00000800;
	if (sc->dc_flags & DC_MOMENCO_BOTCH0x00020000)
		sc->dc_pmode = DC_PMODE_MII0x1;
	mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff,
	    MII_PHY_ANY-1, MII_OFFSET_ANY-1, 0);
} else {
	/* we have a PHY, so we must clear this bit */
	sc->dc_flags &= ~DC_TULIP_LEDS0x00004000;
}
}

if (LIST_EMPTY(&sc->sc_mii.mii_phys)(((&sc->sc_mii.mii_phys)->lh_first) == ((void *)0))) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL, 0, NULL((void *)0));
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL);
printf("%s: MII without any PHY!\n", sc->sc_dev.dv_xname);
} else if (sc->dc_type == DC_TYPE_211450xD) {
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER0x0000000000000100ULL|IFM_10_T3);
} else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER0x0000000000000100ULL|IFM_AUTO0ULL);

if (DC_IS_DAVICOM(sc)(sc->dc_type == 0x8) && sc->dc_revision >= DC_REVISION_DM9102A0x30)
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER0x0000000000000100ULL|IFM_HPNA_117,0,NULL((void *)0));

if (DC_IS_ADMTEK(sc)(sc->dc_type == 0x6 || sc->dc_type == 0x7)) {
/*
 * Set automatic TX underrun recovery for the ADMtek chips
 */
DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x88), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x88))) | (
0x00000001))));
}

/*
* Call MI attach routines.
*/
if_attach(ifp);
ether_ifattach(ifp);

1780fail:
return;
1782}

1784/*
* Initialize the transmit descriptors.
*/
1787int
1788dc_list_tx_init(struct dc_softc *sc)
1789{
struct dc_chain_data *cd;
struct dc_list_data *ld;
int i;
bus_addr_t next;

cd = &sc->dc_cdata;
ld = sc->dc_ldata;
for (i = 0; i < DC_TX_LIST_CNT256; i++) {
next = sc->sc_listmap->dm_segs[0].ds_addr;
if (i == (DC_TX_LIST_CNT256 - 1))
	next +=
	    offsetof(struct dc_list_data, dc_tx_list[0])__builtin_offsetof(struct dc_list_data, dc_tx_list[0]);
else
	next +=
	    offsetof(struct dc_list_data, dc_tx_list[i + 1])__builtin_offsetof(struct dc_list_data, dc_tx_list[i + 1]);
cd->dc_tx_chain[i].sd_mbuf = NULL((void *)0);
ld->dc_tx_list[i].dc_datadc_ptr1 = htole32(0)((__uint32_t)(0));
ld->dc_tx_list[i].dc_ctl = htole32(0)((__uint32_t)(0));
ld->dc_tx_list[i].dc_nextdc_ptr2 = htole32(next)((__uint32_t)(next));
}

cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;

return (0);
1814}


1817/*
* Initialize the RX descriptors and allocate mbufs for them. Note that
* we arrange the descriptors in a closed ring, so that the last descriptor
* points back to the first.
*/
1822int
1823dc_list_rx_init(struct dc_softc *sc)
1824{
struct dc_chain_data *cd;
struct dc_list_data *ld;
int i;
bus_addr_t next;

cd = &sc->dc_cdata;
ld = sc->dc_ldata;

for (i = 0; i < DC_RX_LIST_CNT64; i++) {
if (dc_newbuf(sc, i, NULL((void *)0)) == ENOBUFS55)
	return (ENOBUFS55);
next = sc->sc_listmap->dm_segs[0].ds_addr;
if (i == (DC_RX_LIST_CNT64 - 1))
	next +=
	    offsetof(struct dc_list_data, dc_rx_list[0])__builtin_offsetof(struct dc_list_data, dc_rx_list[0]);
else
	next +=
	    offsetof(struct dc_list_data, dc_rx_list[i + 1])__builtin_offsetof(struct dc_list_data, dc_rx_list[i + 1]);
ld->dc_rx_list[i].dc_nextdc_ptr2 = htole32(next)((__uint32_t)(next));
}

cd->dc_rx_prod = 0;

return (0);
1849}

1851/*
* Initialize an RX descriptor and attach an MBUF cluster.
*/
1854int
1855dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m)
1856{
struct mbuf *m_new = NULL((void *)0);
struct dc_desc *c;
bus_dmamap_t map;

c = &sc->dc_ldata->dc_rx_list[i];

if (m == NULL((void *)0)) {
MGETHDR(m_new, M_DONTWAIT, MT_DATA)m_new = m_gethdr((0x0002), (1));
if (m_new == NULL((void *)0))
	return (ENOBUFS55);

MCLGET(m_new, M_DONTWAIT)(void) m_clget((m_new), (0x0002), (1 << 11));
if (!(m_new->m_flagsm_hdr.mh_flags & M_EXT0x0001)) {
	m_freem(m_new);
	return (ENOBUFS55);
}
m_new->m_lenm_hdr.mh_len = m_new->m_pkthdrM_dat.MH.MH_pkthdr.len = MCLBYTES(1 << 11);
if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rx_sparemap,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
sc->sc_rx_sparemap), (m_new), (0x0001))
    m_new, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
sc->sc_rx_sparemap), (m_new), (0x0001)) != 0) {
	m_freem(m_new);
	return (ENOBUFS55);
}
map = sc->dc_cdata.dc_rx_chain[i].sd_map;
sc->dc_cdata.dc_rx_chain[i].sd_map = sc->sc_rx_sparemap;
sc->sc_rx_sparemap = map;
} else {
/*
 * We're re-using a previously allocated mbuf;
 * be sure to re-init pointers and lengths to
 * default values.
 */
m_new = m;
m_new->m_lenm_hdr.mh_len = m_new->m_pkthdrM_dat.MH.MH_pkthdr.len = MCLBYTES(1 << 11);
m_new->m_datam_hdr.mh_data = m_new->m_extM_dat.MH.MH_dat.MH_ext.ext_buf;
}

m_adj(m_new, sizeof(u_int64_t));

/*
* If this is a PNIC chip, zero the buffer. This is part
* of the workaround for the receive bug in the 82c168 and
* 82c169 chips.
*/
if (sc->dc_flags & DC_PNIC_RX_BUG_WAR0x00000040)
bzero(mtod(m_new, char *), m_new->m_len)__builtin_bzero((((char *)((m_new)->m_hdr.mh_data))), (m_new
->m_hdr.mh_len));

bus_dmamap_sync(sc->sc_dmat, sc->dc_cdata.dc_rx_chain[i].sd_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
dc_cdata.dc_rx_chain[i].sd_map), (0), (sc->dc_cdata.dc_rx_chain
[i].sd_map->dm_mapsize), (0x01))
   sc->dc_cdata.dc_rx_chain[i].sd_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
dc_cdata.dc_rx_chain[i].sd_map), (0), (sc->dc_cdata.dc_rx_chain
[i].sd_map->dm_mapsize), (0x01))
   BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
dc_cdata.dc_rx_chain[i].sd_map), (0), (sc->dc_cdata.dc_rx_chain
[i].sd_map->dm_mapsize), (0x01));

sc->dc_cdata.dc_rx_chain[i].sd_mbuf = m_new;
c->dc_datadc_ptr1 = htole32(((__uint32_t)(sc->dc_cdata.dc_rx_chain[i].sd_map->dm_segs
[0].ds_addr + sizeof(u_int64_t)))
   sc->dc_cdata.dc_rx_chain[i].sd_map->dm_segs[0].ds_addr +((__uint32_t)(sc->dc_cdata.dc_rx_chain[i].sd_map->dm_segs
[0].ds_addr + sizeof(u_int64_t)))
   sizeof(u_int64_t))((__uint32_t)(sc->dc_cdata.dc_rx_chain[i].sd_map->dm_segs
[0].ds_addr + sizeof(u_int64_t)));
c->dc_ctl = htole32(DC_RXCTL_RLINK | ETHER_MAX_DIX_LEN)((__uint32_t)(0x01000000 | 1536));
c->dc_status = htole32(DC_RXSTAT_OWN)((__uint32_t)(0x80000000));

bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_rx_list
[i])), (sizeof(struct dc_desc)), (0x01 | 0x04))
   offsetof(struct dc_list_data, dc_rx_list[i]),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_rx_list
[i])), (sizeof(struct dc_desc)), (0x01 | 0x04))
   sizeof(struct dc_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_rx_list
[i])), (sizeof(struct dc_desc)), (0x01 | 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_rx_list
[i])), (sizeof(struct dc_desc)), (0x01 | 0x04));

return (0);
1920}

1922/*
* Grrrrr.
* The PNIC chip has a terrible bug in it that manifests itself during
* periods of heavy activity. The exact mode of failure if difficult to
* pinpoint: sometimes it only happens in promiscuous mode, sometimes it
* will happen on slow machines. The bug is that sometimes instead of
* uploading one complete frame during reception, it uploads what looks
* like the entire contents of its FIFO memory. The frame we want is at
* the end of the whole mess, but we never know exactly how much data has
* been uploaded, so salvaging the frame is hard.
*
* There is only one way to do it reliably, and it's disgusting.
* Here's what we know:
*
* - We know there will always be somewhere between one and three extra
*   descriptors uploaded.
*
* - We know the desired received frame will always be at the end of the
*   total data upload.
*
* - We know the size of the desired received frame because it will be
*   provided in the length field of the status word in the last descriptor.
*
* Here's what we do:
*
* - When we allocate buffers for the receive ring, we bzero() them.
*   This means that we know that the buffer contents should be all
*   zeros, except for data uploaded by the chip.
*
* - We also force the PNIC chip to upload frames that include the
*   ethernet CRC at the end.
*
* - We gather all of the bogus frame data into a single buffer.
*
* - We then position a pointer at the end of this buffer and scan
*   backwards until we encounter the first non-zero byte of data.
*   This is the end of the received frame. We know we will encounter
*   some data at the end of the frame because the CRC will always be
*   there, so even if the sender transmits a packet of all zeros,
*   we won't be fooled.
*
* - We know the size of the actual received frame, so we subtract
*   that value from the current pointer location. This brings us
*   to the start of the actual received packet.
*
* - We copy this into an mbuf and pass it on, along with the actual
*   frame length.
*
* The performance hit is tremendous, but it beats dropping frames all
* the time.
*/

1974#define DC_WHOLEFRAME(0x00000200|0x00000100)	(DC_RXSTAT_FIRSTFRAG0x00000200|DC_RXSTAT_LASTFRAG0x00000100)
1975void
1976dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
1977{
struct dc_desc		*cur_rx;
struct dc_desc		*c = NULL((void *)0);
struct mbuf		*m = NULL((void *)0);
unsigned char		*ptr;
int			i, total_len;
u_int32_t		rxstat = 0;

i = sc->dc_pnic_rx_bug_save;
cur_rx = &sc->dc_ldata->dc_rx_list[idx];
ptr = sc->dc_pnic_rx_buf;
bzero(ptr, ETHER_MAX_DIX_LEN * 5)__builtin_bzero((ptr), (1536 * 5));

/* Copy all the bytes from the bogus buffers. */
while (1) {
c = &sc->dc_ldata->dc_rx_list[i];
rxstat = letoh32(c->dc_status)((__uint32_t)(c->dc_status));
m = sc->dc_cdata.dc_rx_chain[i].sd_mbuf;
bcopy(mtod(m, char *)((char *)((m)->m_hdr.mh_data)), ptr, ETHER_MAX_DIX_LEN1536);
ptr += ETHER_MAX_DIX_LEN1536;
/* If this is the last buffer, break out. */
if (i == idx || rxstat & DC_RXSTAT_LASTFRAG0x00000100)
	break;
dc_newbuf(sc, i, m);
DC_INC(i, DC_RX_LIST_CNT)(i) = (i + 1) % 64;
}

/* Find the length of the actual receive frame. */
total_len = DC_RXBYTES(rxstat)((rxstat & 0x3FFF0000) >> 16);

/* Scan backwards until we hit a non-zero byte. */
while(*ptr == 0x00)
ptr--;

/* Round off. */
if ((unsigned long)(ptr) & 0x3)
ptr -= 1;

/* Now find the start of the frame. */
ptr -= total_len;
if (ptr < sc->dc_pnic_rx_buf)
ptr = sc->dc_pnic_rx_buf;

/*
* Now copy the salvaged frame to the last mbuf and fake up
* the status word to make it look like a successful
 * frame reception.
*/
dc_newbuf(sc, i, m);
bcopy(ptr, mtod(m, char *)((char *)((m)->m_hdr.mh_data)), total_len);	
cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG)((__uint32_t)(rxstat | 0x00000200));
2028}

2030/*
* This routine searches the RX ring for dirty descriptors in the
* event that the rxeof routine falls out of sync with the chip's
* current descriptor pointer. This may happen sometimes as a result
* of a "no RX buffer available" condition that happens when the chip
* consumes all of the RX buffers before the driver has a chance to
* process the RX ring. This routine may need to be called more than
* once to bring the driver back in sync with the chip, however we
* should still be getting RX DONE interrupts to drive the search
* for new packets in the RX ring, so we should catch up eventually.
*/
2041int
2042dc_rx_resync(struct dc_softc *sc)
2043{
u_int32_t stat;
int i, pos, offset;

pos = sc->dc_cdata.dc_rx_prod;

for (i = 0; i < DC_RX_LIST_CNT64; i++) {

offset = offsetof(struct dc_list_data, dc_rx_list[pos])__builtin_offsetof(struct dc_list_data, dc_rx_list[pos]);
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
))
    offset, sizeof(struct dc_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
));

stat = sc->dc_ldata->dc_rx_list[pos].dc_status;
if (!(stat & htole32(DC_RXSTAT_OWN)((__uint32_t)(0x80000000))))
	break;
DC_INC(pos, DC_RX_LIST_CNT)(pos) = (pos + 1) % 64;
}

/* If the ring really is empty, then just return. */
if (i == DC_RX_LIST_CNT64)
return (0);

/* We've fallen behind the chip: catch it. */
sc->dc_cdata.dc_rx_prod = pos;

return (EAGAIN35);
2070}

2072/*
* A frame has been uploaded: pass the resulting mbuf chain up to
* the higher level protocols.
*/
2076int
2077dc_rxeof(struct dc_softc *sc)
2078{
struct mbuf *m;
struct ifnet *ifp;
struct dc_desc *cur_rx;
struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
int i, offset, total_len = 0, consumed = 0;
u_int32_t rxstat;

ifp = &sc->sc_arpcom.ac_if;
i = sc->dc_cdata.dc_rx_prod;

for(;;) {
struct mbuf	*m0 = NULL((void *)0);

offset = offsetof(struct dc_list_data, dc_rx_list[i])__builtin_offsetof(struct dc_list_data, dc_rx_list[i]);
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
))
    offset, sizeof(struct dc_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
));

cur_rx = &sc->dc_ldata->dc_rx_list[i];
rxstat = letoh32(cur_rx->dc_status)((__uint32_t)(cur_rx->dc_status));
if (rxstat & DC_RXSTAT_OWN0x80000000)
	break;

m = sc->dc_cdata.dc_rx_chain[i].sd_mbuf;
total_len = DC_RXBYTES(rxstat)((rxstat & 0x3FFF0000) >> 16);

bus_dmamap_sync(sc->sc_dmat, sc->dc_cdata.dc_rx_chain[i].sd_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
dc_cdata.dc_rx_chain[i].sd_map), (0), (sc->dc_cdata.dc_rx_chain
[i].sd_map->dm_mapsize), (0x02))
    0, sc->dc_cdata.dc_rx_chain[i].sd_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
dc_cdata.dc_rx_chain[i].sd_map), (0), (sc->dc_cdata.dc_rx_chain
[i].sd_map->dm_mapsize), (0x02))
    BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
dc_cdata.dc_rx_chain[i].sd_map), (0), (sc->dc_cdata.dc_rx_chain
[i].sd_map->dm_mapsize), (0x02));

if (sc->dc_flags & DC_PNIC_RX_BUG_WAR0x00000040) {
	if ((rxstat & DC_WHOLEFRAME(0x00000200|0x00000100)) != DC_WHOLEFRAME(0x00000200|0x00000100)) {
		if (rxstat & DC_RXSTAT_FIRSTFRAG0x00000200)
			sc->dc_pnic_rx_bug_save = i;
		if ((rxstat & DC_RXSTAT_LASTFRAG0x00000100) == 0) {
			DC_INC(i, DC_RX_LIST_CNT)(i) = (i + 1) % 64;
			continue;
		}
		dc_pnic_rx_bug_war(sc, i);
		rxstat = letoh32(cur_rx->dc_status)((__uint32_t)(cur_rx->dc_status));
		total_len = DC_RXBYTES(rxstat)((rxstat & 0x3FFF0000) >> 16);
	}
}

sc->dc_cdata.dc_rx_chain[i].sd_mbuf = NULL((void *)0);

/*
 * If an error occurs, update stats, clear the
 * status word and leave the mbuf cluster in place:
 * it should simply get re-used next time this descriptor
 * comes up in the ring.  However, don't report long
 * frames as errors since they could be VLANs.
 */
if ((rxstat & DC_RXSTAT_RXERR0x00008000)) {
	if (!(rxstat & DC_RXSTAT_GIANT0x00000080) ||
	    (rxstat & (DC_RXSTAT_CRCERR0x00000002 | DC_RXSTAT_DRIBBLE0x00000004 |
		       DC_RXSTAT_MIIERE0x00000008 | DC_RXSTAT_COLLSEEN0x00000040 |
		       DC_RXSTAT_RUNT0x00000800   | DC_RXSTAT_DE0x00004000))) {
		ifp->if_ierrorsif_data.ifi_ierrors++;
		if (rxstat & DC_RXSTAT_COLLSEEN0x00000040)
			ifp->if_collisionsif_data.ifi_collisions++;
		dc_newbuf(sc, i, m);
		if (rxstat & DC_RXSTAT_CRCERR0x00000002) {
			DC_INC(i, DC_RX_LIST_CNT)(i) = (i + 1) % 64;
			continue;
		} else {
			dc_init(sc);
			break;
		}
	}
}

/* No errors; receive the packet. */	
total_len -= ETHER_CRC_LEN4;

m0 = m_devget(mtod(m, char *)((char *)((m)->m_hdr.mh_data)), total_len, ETHER_ALIGN2);
dc_newbuf(sc, i, m);
DC_INC(i, DC_RX_LIST_CNT)(i) = (i + 1) % 64;
if (m0 == NULL((void *)0)) {
	ifp->if_ierrorsif_data.ifi_ierrors++;
	continue;
}
m = m0;

consumed++;
ml_enqueue(&ml, m);
}

sc->dc_cdata.dc_rx_prod = i;

if_input(ifp, &ml);

return (consumed);
2172}

2174/*
* A frame was downloaded to the chip. It's safe for us to clean up
* the list buffers.
*/

2179void
2180dc_txeof(struct dc_softc *sc)
2181{
struct dc_desc *cur_tx = NULL((void *)0);
struct ifnet *ifp;
int idx, offset;

ifp = &sc->sc_arpcom.ac_if;

/*
* Go through our tx list and free mbufs for those
* frames that have been transmitted.
*/
idx = sc->dc_cdata.dc_tx_cons;
while(idx != sc->dc_cdata.dc_tx_prod) {
u_int32_t		txstat;

offset = offsetof(struct dc_list_data, dc_tx_list[idx])__builtin_offsetof(struct dc_list_data, dc_tx_list[idx]);
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
))
    offset, sizeof(struct dc_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
));

cur_tx = &sc->dc_ldata->dc_tx_list[idx];
txstat = letoh32(cur_tx->dc_status)((__uint32_t)(cur_tx->dc_status));

if (txstat & DC_TXSTAT_OWN0x80000000)
	break;

if (!(cur_tx->dc_ctl & htole32(DC_TXCTL_LASTFRAG)((__uint32_t)(0x40000000))) ||
    cur_tx->dc_ctl & htole32(DC_TXCTL_SETUP)((__uint32_t)(0x08000000))) {
	if (cur_tx->dc_ctl & htole32(DC_TXCTL_SETUP)((__uint32_t)(0x08000000))) {
		/*
		 * Yes, the PNIC is so brain damaged
		 * that it will sometimes generate a TX
		 * underrun error while DMAing the RX
		 * filter setup frame. If we detect this,
		 * we have to send the setup frame again,
		 * or else the filter won't be programmed
		 * correctly.
		 */
		if (DC_IS_PNIC(sc)(sc->dc_type == 0xA)) {
			if (txstat & DC_TXSTAT_ERRSUM0x00008000)
				dc_setfilt(sc);
		}
		sc->dc_cdata.dc_tx_chain[idx].sd_mbuf = NULL((void *)0);
	}
	sc->dc_cdata.dc_tx_cnt--;
	DC_INC(idx, DC_TX_LIST_CNT)(idx) = (idx + 1) % 256;
	continue;
}

if (DC_IS_XIRCOM(sc)(sc->dc_type == 0xB) || DC_IS_CONEXANT(sc)(sc->dc_type == 0xC)) {
	/*
	 * XXX: Why does my Xircom taunt me so?
	 * For some reason it likes setting the CARRLOST flag
	 * even when the carrier is there. wtf?!
	 * Who knows, but Conexant chips have the
	 * same problem. Maybe they took lessons
	 * from Xircom.
	 */
	if (/*sc->dc_type == DC_TYPE_21143 &&*/
	    sc->dc_pmode == DC_PMODE_MII0x1 &&
	    ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM0x00008000|
	    DC_TXSTAT_NOCARRIER0x00000400)))
		txstat &= ~DC_TXSTAT_ERRSUM0x00008000;
} else {
	if (/*sc->dc_type == DC_TYPE_21143 &&*/
	    sc->dc_pmode == DC_PMODE_MII0x1 &&
    	    ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM0x00008000|
    	    DC_TXSTAT_NOCARRIER0x00000400|DC_TXSTAT_CARRLOST0x00000800)))
		txstat &= ~DC_TXSTAT_ERRSUM0x00008000;
}

if (txstat & DC_TXSTAT_ERRSUM0x00008000) {
	ifp->if_oerrorsif_data.ifi_oerrors++;
	if (txstat & DC_TXSTAT_EXCESSCOLL0x00000100)
		ifp->if_collisionsif_data.ifi_collisions++;
	if (txstat & DC_TXSTAT_LATECOLL0x00000200)
		ifp->if_collisionsif_data.ifi_collisions++;
	if (!(txstat & DC_TXSTAT_UNDERRUN0x00000002)) {
		dc_init(sc);
		return;
	}
}

ifp->if_collisionsif_data.ifi_collisions += (txstat & DC_TXSTAT_COLLCNT0x00000078) >> 3;

if (sc->dc_cdata.dc_tx_chain[idx].sd_map->dm_nsegs != 0) {
	bus_dmamap_t map = sc->dc_cdata.dc_tx_chain[idx].sd_map;

	bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x08))
	    BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x08));
	bus_dmamap_unload(sc->sc_dmat, map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (map
));
}
if (sc->dc_cdata.dc_tx_chain[idx].sd_mbuf != NULL((void *)0)) {
	m_freem(sc->dc_cdata.dc_tx_chain[idx].sd_mbuf);
	sc->dc_cdata.dc_tx_chain[idx].sd_mbuf = NULL((void *)0);
}

bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
))
    offset, sizeof(struct dc_desc),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (offset), (sizeof(struct dc_desc)), (0x02 | 0x08
));

sc->dc_cdata.dc_tx_cnt--;
DC_INC(idx, DC_TX_LIST_CNT)(idx) = (idx + 1) % 256;
}
sc->dc_cdata.dc_tx_cons = idx;

if (DC_TX_LIST_CNT256 - sc->dc_cdata.dc_tx_cnt > 5)
ifq_clr_oactive(&ifp->if_snd);
if (sc->dc_cdata.dc_tx_cnt == 0)
ifp->if_timer = 0;
2291}

2293void
2294dc_tick(void *xsc)
2295{
struct dc_softc *sc = (struct dc_softc *)xsc;
struct mii_data *mii;
struct ifnet *ifp;
int s;
u_int32_t r;

s = splnet()splraise(0x4);

ifp = &sc->sc_arpcom.ac_if;
mii = &sc->sc_mii;

if (sc->dc_flags & DC_REDUCED_MII_POLL0x00000200) {
if (sc->dc_flags & DC_21143_NWAY0x00000800) {
	r = CSR_READ_4(sc, DC_10BTSTAT)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x60)));
	if (IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) ==
	    IFM_100_TX6 && (r & DC_TSTAT_LS1000x00000002)) {
		sc->dc_link = 0;
		mii_mediachg(mii);
	}
	if (IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) ==
	    IFM_10_T3 && (r & DC_TSTAT_LS100x00000004)) {
		sc->dc_link = 0;
		mii_mediachg(mii);
	}
	if (sc->dc_link == 0)
		mii_tick(mii);
} else {
	/*
	 * For NICs which never report DC_RXSTATE_WAIT, we
	 * have to bite the bullet...
	 */
	if ((DC_HAS_BROKEN_RXSTATE(sc)((sc->dc_type == 0x7) || (sc->dc_type == 0xC) || ((sc->
dc_type == 0x8) && sc->dc_revision >= 0x30)) || (CSR_READ_4(sc,((sc->dc_btag)->read_4((sc->dc_bhandle), (0x28)))
	    DC_ISR)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x28))) & DC_ISR_RX_STATE0x000E0000) == DC_RXSTATE_WAIT0x00060000) &&
	    sc->dc_cdata.dc_tx_cnt == 0 && !DC_IS_ASIX(sc)(sc->dc_type == 0x5)) {
		mii_tick(mii);
		if (!(mii->mii_media_status & IFM_ACTIVE0x0000000000000002ULL))
			sc->dc_link = 0;
	}
}
} else
mii_tick(mii);

/*
* When the init routine completes, we expect to be able to send
* packets right away, and in fact the network code will send a
* gratuitous ARP the moment the init routine marks the interface
* as running. However, even though the MAC may have been initialized,
* there may be a delay of a few seconds before the PHY completes
* autonegotiation and the link is brought up. Any transmissions
* made during that delay will be lost. Dealing with this is tricky:
* we can't just pause in the init routine while waiting for the
* PHY to come ready since that would bring the whole system to
* a screeching halt for several seconds.
*
* What we do here is prevent the TX start routine from sending
* any packets until a link has been established. After the
* interface has been initialized, the tick routine will poll
* the state of the PHY until the IFM_ACTIVE flag is set. Until
* that time, packets will stay in the send queue, and once the
* link comes up, they will be flushed out to the wire.
*/
if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE0x0000000000000002ULL &&
   IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) != IFM_NONE2ULL) {
sc->dc_link++;
if (ifq_empty(&ifp->if_snd)(({ typeof((&ifp->if_snd)->ifq_len) __tmp = *(volatile
 typeof((&ifp->if_snd)->ifq_len) *)&((&ifp->
if_snd)->ifq_len); membar_datadep_consumer(); __tmp; }) ==
 0) == 0)
	    dc_start(ifp);
}

if (sc->dc_flags & DC_21143_NWAY0x00000800 && !sc->dc_link)
timeout_add_msec(&sc->dc_tick_tmo, 100);
else
timeout_add_sec(&sc->dc_tick_tmo, 1);

splx(s)spllower(s);
2370}

2372/* A transmit underrun has occurred.  Back off the transmit threshold,
* or switch to store and forward mode if we have to.
*/
2375void
2376dc_tx_underrun(struct dc_softc *sc)
2377{
u_int32_t	isr;
int		i;

if (DC_IS_DAVICOM(sc)(sc->dc_type == 0x8))
dc_init(sc);

if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD)) {
/*
 * The real 21143 requires that the transmitter be idle
 * in order to change the transmit threshold or store
 * and forward state.
 */
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00002000))));

for (i = 0; i < DC_TIMEOUT1000; i++) {
	isr = CSR_READ_4(sc, DC_ISR)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x28)));
	if (isr & DC_ISR_TX_IDLE0x00000002)
		break;
	DELAY(10)(*delay_func)(10);
}
if (i == DC_TIMEOUT1000) {
	printf("%s: failed to force tx to idle state\n",
	    sc->sc_dev.dv_xname);
	dc_init(sc);
}
}

sc->dc_txthresh += DC_TXTHRESH_INC0x00004000;
if (sc->dc_txthresh > DC_TXTHRESH_MAX0x0000C000) {
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00200000))));
} else {
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x0000C000))));
DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
sc->dc_txthresh))));
}

if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD))
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00002000))));

return;
2417}

2419int
2420dc_intr(void *arg)
2421{
struct dc_softc *sc;
struct ifnet *ifp;
u_int32_t status, ints;
int claimed = 0;

sc = arg;

ifp = &sc->sc_arpcom.ac_if;

ints = CSR_READ_4(sc, DC_ISR)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x28)));
if ((ints & DC_INTRS(0x00000040|0x00000001|0x00000080|0x00000200| 0x00000002|0x00000004
|0x00000020|0x00002000| 0x00008000|0x00010000 )) == 0)
return (claimed);
if (ints == 0xffffffff)
return (0);

/* Suppress unwanted interrupts */
if (!(ifp->if_flags & IFF_UP0x1)) {
if (CSR_READ_4(sc, DC_ISR)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x28))) & DC_INTRS(0x00000040|0x00000001|0x00000080|0x00000200| 0x00000002|0x00000004
|0x00000020|0x00002000| 0x00008000|0x00010000 ))
	dc_stop(sc, 0);
return (claimed);
}

/* Disable interrupts. */
CSR_WRITE_4(sc, DC_IMR, 0x00000000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x38), (0x00000000
)));

while (((status = CSR_READ_4(sc, DC_ISR)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x28)))) & DC_INTRS(0x00000040|0x00000001|0x00000080|0x00000200| 0x00000002|0x00000004
|0x00000020|0x00002000| 0x00008000|0x00010000 )) &&
   status != 0xFFFFFFFF &&
   (ifp->if_flags & IFF_RUNNING0x40)) {

claimed = 1;
CSR_WRITE_4(sc, DC_ISR, status)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x28), (status
)));

if (status & DC_ISR_RX_OK0x00000040) {
	if (dc_rxeof(sc) == 0) {
		while(dc_rx_resync(sc))
			dc_rxeof(sc);
	}
}

if (status & (DC_ISR_TX_OK0x00000001|DC_ISR_TX_NOBUF0x00000004))
	dc_txeof(sc);

if (status & DC_ISR_TX_IDLE0x00000002) {
	dc_txeof(sc);
	if (sc->dc_cdata.dc_tx_cnt) {
		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00002000))));
		CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x08), (0xFFFFFFFF
)));
	}
}

if (status & DC_ISR_TX_UNDERRUN0x00000020)
	dc_tx_underrun(sc);

if ((status & DC_ISR_RX_WATDOGTIMEO0x00000200)
    || (status & DC_ISR_RX_NOBUF0x00000080)) {
	if (dc_rxeof(sc) == 0) {
		while(dc_rx_resync(sc))
			dc_rxeof(sc);
	}
}

if (status & DC_ISR_BUS_ERR0x00002000)
	dc_init(sc);
}

/* Re-enable interrupts. */
CSR_WRITE_4(sc, DC_IMR, DC_INTRS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x38), ((
0x00000040|0x00000001|0x00000080|0x00000200| 0x00000002|0x00000004
|0x00000020|0x00002000| 0x00008000|0x00010000 ))));

if (ifq_empty(&ifp->if_snd)(({ typeof((&ifp->if_snd)->ifq_len) __tmp = *(volatile
 typeof((&ifp->if_snd)->ifq_len) *)&((&ifp->
if_snd)->ifq_len); membar_datadep_consumer(); __tmp; }) ==
 0) == 0)
dc_start(ifp);

return (claimed);
2494}

2496/*
* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
* pointers to the fragment pointers.
*/
2500int
2501dc_encap(struct dc_softc *sc, bus_dmamap_t map, struct mbuf *m, u_int32_t *idx)
2502{
struct dc_desc *f = NULL((void *)0);
int frag, cur, cnt = 0, i;

cur = frag = *idx;

for (i = 0; i < map->dm_nsegs; i++) {
f = &sc->dc_ldata->dc_tx_list[frag];
f->dc_ctl = htole32(DC_TXCTL_TLINK | map->dm_segs[i].ds_len)((__uint32_t)(0x01000000 | map->dm_segs[i].ds_len));
if (cnt == 0) {
	f->dc_status = htole32(0)((__uint32_t)(0));
	f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG)((__uint32_t)(0x20000000));
} else
	f->dc_status = htole32(DC_TXSTAT_OWN)((__uint32_t)(0x80000000));
f->dc_datadc_ptr1 = htole32(map->dm_segs[i].ds_addr)((__uint32_t)(map->dm_segs[i].ds_addr));
cur = frag;
DC_INC(frag, DC_TX_LIST_CNT)(frag) = (frag + 1) % 256;
cnt++;
}

sc->dc_cdata.dc_tx_cnt += cnt;
sc->dc_cdata.dc_tx_chain[cur].sd_mbuf = m;
sc->sc_tx_sparemap = sc->dc_cdata.dc_tx_chain[cur].sd_map;
sc->dc_cdata.dc_tx_chain[cur].sd_map = map;
sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG)((__uint32_t)(0x40000000));
if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG0x00000020)
sc->dc_ldata->dc_tx_list[*idx].dc_ctl |=
    htole32(DC_TXCTL_FINT)((__uint32_t)(0x80000000));
if (sc->dc_flags & DC_TX_INTR_ALWAYS0x00000400)
sc->dc_ldata->dc_tx_list[cur].dc_ctl |=
    htole32(DC_TXCTL_FINT)((__uint32_t)(0x80000000));
if (sc->dc_flags & DC_TX_USE_TX_INTR0x00000008 && sc->dc_cdata.dc_tx_cnt > 64)
sc->dc_ldata->dc_tx_list[cur].dc_ctl |=
    htole32(DC_TXCTL_FINT)((__uint32_t)(0x80000000));
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x04))
   BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x04));

sc->dc_ldata->dc_tx_list[*idx].dc_status = htole32(DC_TXSTAT_OWN)((__uint32_t)(0x80000000));

*idx = frag;

return (0);
2544}

2546/*
* Main transmit routine. To avoid having to do mbuf copies, we put pointers
* to the mbuf data regions directly in the transmit lists. We also save a
* copy of the pointers since the transmit list fragment pointers are
* physical addresses.
*/

2553static inline int
2554dc_fits(struct dc_softc *sc, int idx, bus_dmamap_t map)
2555{
if (sc->dc_flags & DC_TX_ADMTEK_WAR0x00000004) {
if (sc->dc_cdata.dc_tx_prod != idx &&
    idx + map->dm_nsegs >= DC_TX_LIST_CNT256)
	return (0);
}

if (sc->dc_cdata.dc_tx_cnt + map->dm_nsegs + 5 > DC_TX_LIST_CNT256)
return (0);

return (1);
2566}

2568void
2569dc_start(struct ifnet *ifp)
2570{
struct dc_softc *sc = ifp->if_softc;
bus_dmamap_t map;
struct mbuf *m;
int idx;

if (!sc->dc_link && ifq_len(&ifp->if_snd)({ typeof((&ifp->if_snd)->ifq_len) __tmp = *(volatile
 typeof((&ifp->if_snd)->ifq_len) *)&((&ifp->
if_snd)->ifq_len); membar_datadep_consumer(); __tmp; }) < 10)
return;

if (ifq_is_oactive(&ifp->if_snd))
return;

idx = sc->dc_cdata.dc_tx_prod;

bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
)), (sizeof(struct dc_desc) * 256), (0x02 | 0x08))
   offsetof(struct dc_list_data, dc_tx_list),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
)), (sizeof(struct dc_desc) * 256), (0x02 | 0x08))
   sizeof(struct dc_desc) * DC_TX_LIST_CNT,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
)), (sizeof(struct dc_desc) * 256), (0x02 | 0x08))
   BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
)), (sizeof(struct dc_desc) * 256), (0x02 | 0x08));

for (;;) {
m = ifq_deq_begin(&ifp->if_snd);
if (m == NULL((void *)0))
	break;

map = sc->sc_tx_sparemap;
switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0001 | 0))
    BUS_DMA_NOWAIT | BUS_DMA_OVERRUN)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0001 | 0))) {
case 0:
	break;
case EFBIG27:
	if (m_defrag(m, M_DONTWAIT0x0002) == 0 &&
	    bus_dmamap_load_mbuf(sc->sc_dmat, map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0001 | 0))
	     BUS_DMA_NOWAIT | BUS_DMA_OVERRUN)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0001 | 0)) == 0)
		break;

	/* FALLTHROUGH */
default:
	ifq_deq_commit(&ifp->if_snd, m);
	m_freem(m);
	ifp->if_oerrorsif_data.ifi_oerrors++;
	continue;
}

if (!dc_fits(sc, idx, map)) {
	bus_dmamap_unload(sc->sc_dmat, map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (map
));
	ifq_deq_rollback(&ifp->if_snd, m);
	ifq_set_oactive(&ifp->if_snd);
	break;
}

/* now we are committed to transmit the packet */
ifq_deq_commit(&ifp->if_snd, m);

if (dc_encap(sc, map, m, &idx) != 0) {
	m_freem(m);
	ifp->if_oerrorsif_data.ifi_oerrors++;
	continue;
}

/*
 * If there's a BPF listener, bounce a copy of this frame
 * to him.
 */
2633#if NBPFILTER1 > 0
if (ifp->if_bpf)
	bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
2636#endif

if (sc->dc_flags & DC_TX_ONE0x00008000) {
	ifq_set_oactive(&ifp->if_snd);
	break;
}
}

bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
)), (sizeof(struct dc_desc) * 256), (0x01 | 0x04))
   offsetof(struct dc_list_data, dc_tx_list),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
)), (sizeof(struct dc_desc) * 256), (0x01 | 0x04))
   sizeof(struct dc_desc) * DC_TX_LIST_CNT,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
)), (sizeof(struct dc_desc) * 256), (0x01 | 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (__builtin_offsetof(struct dc_list_data, dc_tx_list
)), (sizeof(struct dc_desc) * 256), (0x01 | 0x04));

if (idx == sc->dc_cdata.dc_tx_prod)
return;

/* Transmit */
sc->dc_cdata.dc_tx_prod = idx;
if (!(sc->dc_flags & DC_TX_POLL0x00000001))
CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x08), (0xFFFFFFFF
)));

/*
* Set a timeout in case the chip goes out to lunch.
*/
ifp->if_timer = 5;
2661}

2663void
2664dc_init(void *xsc)
2665{
struct dc_softc *sc = xsc;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct mii_data *mii;
int s;

s = splnet()splraise(0x4);

mii = &sc->sc_mii;

/*
* Cancel pending I/O and free all RX/TX buffers.
*/
dc_stop(sc, 0);
dc_reset(sc);

/*
* Set cache alignment and burst length.
*/
if (DC_IS_ASIX(sc)(sc->dc_type == 0x5) || DC_IS_DAVICOM(sc)(sc->dc_type == 0x8))
CSR_WRITE_4(sc, DC_BUSCTL, 0)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), (0
)));
else
CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), (0x00200000
|0x00800000)));
/*
* Evenly share the bus between receive and transmit process.
*/
if (DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD))
DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x00000002))));
if (DC_IS_DAVICOM(sc)(sc->dc_type == 0x8) || DC_IS_INTEL(sc)(sc->dc_type == 0x4 || sc->dc_type == 0xD)) {
DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x00000000))));
} else {
DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x00001000))));
}
if (sc->dc_flags & DC_TX_POLL0x00000001)
DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x00020000))));
switch(sc->dc_cachesize) {
case 32:
DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x0000C000))));
break;
case 16:
DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x00008000))));
break; 
case 8:
DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x00004000))));
break;  
case 0:
default:
DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x00), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x00))) | (
0x00000000))));
break;
}

if (sc->dc_flags & DC_TX_STORENFWD0x00000100)
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00200000))));
else {
if (sc->dc_txthresh > DC_TXTHRESH_MAX0x0000C000) {
	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00200000))));
} else {
	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00200000))));
	DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
sc->dc_txthresh))));
}
}

DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x02000000))));
DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x00020000))));

if (DC_IS_MACRONIX(sc)(sc->dc_type == 0x1 || sc->dc_type == 0x2 || sc->dc_type
 == 0x3) || DC_IS_PNICII(sc)(sc->dc_type == 0x9)) {
/*
 * The app notes for the 98713 and 98715A say that
 * in order to have the chips operate properly, a magic
 * number must be written to CSR16. Macronix does not
 * document the meaning of these bits so there's no way
 * to know exactly what they do. The 98713 has a magic
 * number all its own; the rest all use a different one.
 */
DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x80), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x80))) &
 ~(0xFFFF0000))));
if (sc->dc_type == DC_TYPE_987130x1)
	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x80), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x80))) | (
0x0F370000))));
else
	DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x80), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x80))) | (
0x0B3C0000))));
}

if (DC_IS_XIRCOM(sc)(sc->dc_type == 0xB)) {
CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x08000000
 | 0x02000000 | 0x00040000 | 0x00010000)))
    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x08000000
 | 0x02000000 | 0x00040000 | 0x00010000)));
DELAY(10)(*delay_func)(10);
CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x02000000
 | 0x00040000 | 0x00010000)))
    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x02000000
 | 0x00040000 | 0x00010000)));
DELAY(10)(*delay_func)(10);
}

DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~(0x0000C000))));
DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000000))));

/* Init circular RX list. */
if (dc_list_rx_init(sc) == ENOBUFS55) {
printf("%s: initialization failed: no "
    "memory for rx buffers\n", sc->sc_dev.dv_xname);
dc_stop(sc, 0);
splx(s)spllower(s);
return;
}

/*
* Init tx descriptors.
*/
dc_list_tx_init(sc);

/*
* Sync down both lists initialized.
*/
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (0), (sc->sc_listmap->dm_mapsize), (0x01 |
 0x04))
   0, sc->sc_listmap->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (0), (sc->sc_listmap->dm_mapsize), (0x01 |
 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (0), (sc->sc_listmap->dm_mapsize), (0x01 |
 0x04));

/*
* Load the address of the RX list.
*/
CSR_WRITE_4(sc, DC_RXADDR, sc->sc_listmap->dm_segs[0].ds_addr +((sc->dc_btag)->write_4((sc->dc_bhandle), (0x18), (sc
->sc_listmap->dm_segs[0].ds_addr + __builtin_offsetof(struct
 dc_list_data, dc_rx_list[0]))))
   offsetof(struct dc_list_data, dc_rx_list[0]))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x18), (sc
->sc_listmap->dm_segs[0].ds_addr + __builtin_offsetof(struct
 dc_list_data, dc_rx_list[0]))));
CSR_WRITE_4(sc, DC_TXADDR, sc->sc_listmap->dm_segs[0].ds_addr +((sc->dc_btag)->write_4((sc->dc_bhandle), (0x20), (sc
->sc_listmap->dm_segs[0].ds_addr + __builtin_offsetof(struct
 dc_list_data, dc_tx_list[0]))))
   offsetof(struct dc_list_data, dc_tx_list[0]))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x20), (sc
->sc_listmap->dm_segs[0].ds_addr + __builtin_offsetof(struct
 dc_list_data, dc_tx_list[0]))));

/*
* Enable interrupts.
*/
CSR_WRITE_4(sc, DC_IMR, DC_INTRS)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x38), ((
0x00000040|0x00000001|0x00000080|0x00000200| 0x00000002|0x00000004
|0x00000020|0x00002000| 0x00008000|0x00010000 ))));
CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x28), (0xFFFFFFFF
)));

/* Enable transmitter. */
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00002000))));

/*
* If this is an Intel 21143 and we're not using the
* MII port, program the LED control pins so we get
* link and activity indications.
*/
if (sc->dc_flags & DC_TULIP_LEDS0x00004000) {
CSR_WRITE_4(sc, DC_WATCHDOG,((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x08000000
|0x00800000|0x00200000)))
    DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0x08000000
|0x00800000|0x00200000)));
CSR_WRITE_4(sc, DC_WATCHDOG, 0)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x78), (0
)));
}

/*
* Load the RX/multicast filter. We do this sort of late
* because the filter programming scheme on the 21143 and
* some clones requires DMAing a setup frame via the TX
* engine, and we need the transmitter enabled for that.
*/
dc_setfilt(sc);

/* Enable receiver. */
DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) | (
0x00000002))));
CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x10), (0xFFFFFFFF
)));

mii_mediachg(mii);
dc_setcfg(sc, sc->dc_if_media);

ifp->if_flags |= IFF_RUNNING0x40;
ifq_clr_oactive(&ifp->if_snd);

splx(s)spllower(s);

timeout_set(&sc->dc_tick_tmo, dc_tick, sc);

if (IFM_SUBTYPE(mii->mii_media.ifm_media)((mii->mii_media.ifm_media) & 0x00000000000000ffULL) == IFM_HPNA_117)
sc->dc_link = 1;
else {
if (sc->dc_flags & DC_21143_NWAY0x00000800)
	timeout_add_msec(&sc->dc_tick_tmo, 100);
else
	timeout_add_sec(&sc->dc_tick_tmo, 1);
}

2838#ifdef SRM_MEDIA
if(sc->dc_srm_media) {
struct ifreq ifr;

ifr.ifr_mediaifr_ifru.ifru_media = sc->dc_srm_media;
ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((55))));
sc->dc_srm_media = 0;
}
2846#endif
2847}

2849/*
* Set media options.
*/
2852int
2853dc_ifmedia_upd(struct ifnet *ifp)
2854{
struct dc_softc *sc;
struct mii_data *mii;
struct ifmedia *ifm;

sc = ifp->if_softc;
mii = &sc->sc_mii;
mii_mediachg(mii);

ifm = &mii->mii_media;

if (DC_IS_DAVICOM(sc)(sc->dc_type == 0x8) &&
   IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL) == IFM_HPNA_117)
dc_setcfg(sc, ifm->ifm_media);
else
sc->dc_link = 0;

return (0);
2872}

2874/*
* Report current media status.
*/
2877void
2878dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2879{
struct dc_softc *sc;
struct mii_data *mii;
struct ifmedia *ifm;

sc = ifp->if_softc;
mii = &sc->sc_mii;
mii_pollstat(mii);
ifm = &mii->mii_media;
if (DC_IS_DAVICOM(sc)(sc->dc_type == 0x8)) {
if (IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL) == IFM_HPNA_117) {
	ifmr->ifm_active = ifm->ifm_media;
	ifmr->ifm_status = 0;
	return;
}
}
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
2897}

2899int
2900dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2901{
struct dc_softc		*sc = ifp->if_softc;
struct ifreq		*ifr = (struct ifreq *) data;
int			s, error = 0;

s = splnet()splraise(0x4);

switch(command) {
case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
ifp->if_flags |= IFF_UP0x1;
if (!(ifp->if_flags & IFF_RUNNING0x40))
	dc_init(sc);
break;
case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
if (ifp->if_flags & IFF_UP0x1) {
	if (ifp->if_flags & IFF_RUNNING0x40)
		error = ENETRESET52;
	else {
		sc->dc_txthresh = 0;
		dc_init(sc);
	}
} else {
	if (ifp->if_flags & IFF_RUNNING0x40)
		dc_stop(sc, 0);
}
break;
case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((56))):
case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((55))):
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
2930#ifdef SRM_MEDIA
if (sc->dc_srm_media)
	sc->dc_srm_media = 0;
2933#endif
break;
default:
error = ether_ioctl(ifp, &sc->sc_arpcom, command, data);
}

if (error == ENETRESET52) {
if (ifp->if_flags & IFF_RUNNING0x40)
	dc_setfilt(sc);
error = 0;
}

splx(s)spllower(s);
return (error);
2947}

2949void
2950dc_watchdog(struct ifnet *ifp)
2951{
struct dc_softc *sc;

sc = ifp->if_softc;

ifp->if_oerrorsif_data.ifi_oerrors++;
printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);

dc_init(sc);

if (ifq_empty(&ifp->if_snd)(({ typeof((&ifp->if_snd)->ifq_len) __tmp = *(volatile
 typeof((&ifp->if_snd)->ifq_len) *)&((&ifp->
if_snd)->ifq_len); membar_datadep_consumer(); __tmp; }) ==
 0) == 0)
dc_start(ifp);
2963}

2965/*
* Stop the adapter and free any mbufs allocated to the
* RX and TX lists.
*/
2969void
2970dc_stop(struct dc_softc *sc, int softonly)
2971{
struct ifnet *ifp;
u_int32_t isr;
int i;

ifp = &sc->sc_arpcom.ac_if;
ifp->if_timer = 0;

timeout_del(&sc->dc_tick_tmo);

ifp->if_flags &= ~IFF_RUNNING0x40;
ifq_clr_oactive(&ifp->if_snd);

if (!softonly) {
DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON))((sc->dc_btag)->write_4((sc->dc_bhandle), (0x30), ((
(sc->dc_btag)->read_4((sc->dc_bhandle), (0x30))) &
 ~((0x00000002|0x00002000)))));

for (i = 0; i < DC_TIMEOUT1000; i++) {
	isr = CSR_READ_4(sc, DC_ISR)((sc->dc_btag)->read_4((sc->dc_bhandle), (0x28)));
	if ((isr & DC_ISR_TX_IDLE0x00000002 ||
	    (isr & DC_ISR_TX_STATE0x00700000) == DC_TXSTATE_RESET0x00000000) &&
	    (isr & DC_ISR_RX_STATE0x000E0000) == DC_RXSTATE_STOPPED0x00000000)
		break;
	DELAY(10)(*delay_func)(10);
}

if (i == DC_TIMEOUT1000) {
	if (!((isr & DC_ISR_TX_IDLE0x00000002) ||
	    (isr & DC_ISR_TX_STATE0x00700000) == DC_TXSTATE_RESET0x00000000) &&
	    !DC_IS_ASIX(sc)(sc->dc_type == 0x5) && !DC_IS_DAVICOM(sc)(sc->dc_type == 0x8))
		printf("%s: failed to force tx to idle state\n",
		    sc->sc_dev.dv_xname);
	if (!((isr & DC_ISR_RX_STATE0x000E0000) == DC_RXSTATE_STOPPED0x00000000) &&
	    !DC_HAS_BROKEN_RXSTATE(sc)((sc->dc_type == 0x7) || (sc->dc_type == 0xC) || ((sc->
dc_type == 0x8) && sc->dc_revision >= 0x30)))
		printf("%s: failed to force rx to idle state\n",
		    sc->sc_dev.dv_xname);
}

CSR_WRITE_4(sc, DC_IMR, 0x00000000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x38), (0x00000000
)));
CSR_WRITE_4(sc, DC_TXADDR, 0x00000000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x20), (0x00000000
)));
CSR_WRITE_4(sc, DC_RXADDR, 0x00000000)((sc->dc_btag)->write_4((sc->dc_bhandle), (0x18), (0x00000000
)));
sc->dc_link = 0;
}

/*
* Free data in the RX lists.
*/
for (i = 0; i < DC_RX_LIST_CNT64; i++) {
if (sc->dc_cdata.dc_rx_chain[i].sd_map->dm_nsegs != 0) {
	bus_dmamap_t map = sc->dc_cdata.dc_rx_chain[i].sd_map;

	bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x02))
	    BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x02));
	bus_dmamap_unload(sc->sc_dmat, map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (map
));
}
if (sc->dc_cdata.dc_rx_chain[i].sd_mbuf != NULL((void *)0)) {
	m_freem(sc->dc_cdata.dc_rx_chain[i].sd_mbuf);
	sc->dc_cdata.dc_rx_chain[i].sd_mbuf = NULL((void *)0);
}
}
bzero(&sc->dc_ldata->dc_rx_list, sizeof(sc->dc_ldata->dc_rx_list))__builtin_bzero((&sc->dc_ldata->dc_rx_list), (sizeof
(sc->dc_ldata->dc_rx_list)));

/*
* Free the TX list buffers.
*/
for (i = 0; i < DC_TX_LIST_CNT256; i++) {
if (sc->dc_cdata.dc_tx_chain[i].sd_map->dm_nsegs != 0) {
	bus_dmamap_t map = sc->dc_cdata.dc_tx_chain[i].sd_map;

	bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x08))
	    BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x08));
	bus_dmamap_unload(sc->sc_dmat, map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (map
));
}
if (sc->dc_cdata.dc_tx_chain[i].sd_mbuf != NULL((void *)0)) {
	if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
	    htole32(DC_TXCTL_SETUP)((__uint32_t)(0x08000000))) {
		sc->dc_cdata.dc_tx_chain[i].sd_mbuf = NULL((void *)0);
		continue;
	}
	m_freem(sc->dc_cdata.dc_tx_chain[i].sd_mbuf);
	sc->dc_cdata.dc_tx_chain[i].sd_mbuf = NULL((void *)0);
}
}
bzero(&sc->dc_ldata->dc_tx_list, sizeof(sc->dc_ldata->dc_tx_list))__builtin_bzero((&sc->dc_ldata->dc_tx_list), (sizeof
(sc->dc_ldata->dc_tx_list)));

bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (0), (sc->sc_listmap->dm_mapsize), (0x01 |
 0x04))
   0, sc->sc_listmap->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (0), (sc->sc_listmap->dm_mapsize), (0x01 |
 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
sc_listmap), (0), (sc->sc_listmap->dm_mapsize), (0x01 |
 0x04));
3058}

3060int
3061dc_activate(struct device *self, int act)
3062{
struct dc_softc *sc = (struct dc_softc *)self;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int rv = 0;

switch (act) {
case DVACT_SUSPEND3:
if (ifp->if_flags & IFF_RUNNING0x40)
	dc_stop(sc, 0);
rv = config_activate_children(self, act);
break;
case DVACT_RESUME4:
if (ifp->if_flags & IFF_UP0x1)
	dc_init(sc);
break;
default:
rv = config_activate_children(self, act);
break;
}
return (rv);
3082}

3084int
3085dc_detach(struct dc_softc *sc)
3086{
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int i;

dc_stop(sc, 1);

if (LIST_FIRST(&sc->sc_mii.mii_phys)((&sc->sc_mii.mii_phys)->lh_first) != NULL((void *)0))
mii_detach(&sc->sc_mii, MII_PHY_ANY-1, MII_OFFSET_ANY-1);

if (sc->dc_srom)
free(sc->dc_srom, M_DEVBUF2, sc->dc_sromsize);

for (i = 0; i < DC_RX_LIST_CNT64; i++)
bus_dmamap_destroy(sc->sc_dmat, sc->dc_cdata.dc_rx_chain[i].sd_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->dc_cdata.dc_rx_chain[i].sd_map));
if (sc->sc_rx_sparemap)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_sparemap)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->sc_rx_sparemap));
for (i = 0; i < DC_TX_LIST_CNT256; i++)
bus_dmamap_destroy(sc->sc_dmat, sc->dc_cdata.dc_tx_chain[i].sd_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->dc_cdata.dc_tx_chain[i].sd_map));
if (sc->sc_tx_sparemap)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_sparemap)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->sc_tx_sparemap));

/// XXX bus_dmamap_sync
bus_dmamap_unload(sc->sc_dmat, sc->sc_listmap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (sc->
sc_listmap));
bus_dmamem_unmap(sc->sc_dmat, sc->sc_listkva, sc->sc_listnseg)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (sc->
sc_listkva), (sc->sc_listnseg));
bus_dmamap_destroy(sc->sc_dmat, sc->sc_listmap)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->sc_listmap));
bus_dmamem_free(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (sc->
sc_listseg), (sc->sc_listnseg));

ether_ifdetach(ifp);
if_detach(ifp);
return (0);
3116}

3118struct cfdriver dc_cd = {
0, "dc", DV_IFNET
3120};