| File: | dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c |
| Warning: | line 904, column 2 Value stored to 'result' is never read |
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| 1 | /* |
| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: AMD |
| 23 | * |
| 24 | */ |
| 25 | #include <linux/delay.h> |
| 26 | |
| 27 | #include "dm_services.h" |
| 28 | #include "basics/dc_common.h" |
| 29 | #include "dm_helpers.h" |
| 30 | #include "core_types.h" |
| 31 | #include "resource.h" |
| 32 | #include "dcn20_resource.h" |
| 33 | #include "dcn20_hwseq.h" |
| 34 | #include "dce/dce_hwseq.h" |
| 35 | #include "dcn20_dsc.h" |
| 36 | #include "dcn20_optc.h" |
| 37 | #include "abm.h" |
| 38 | #include "clk_mgr.h" |
| 39 | #include "dmcu.h" |
| 40 | #include "hubp.h" |
| 41 | #include "timing_generator.h" |
| 42 | #include "opp.h" |
| 43 | #include "ipp.h" |
| 44 | #include "mpc.h" |
| 45 | #include "mcif_wb.h" |
| 46 | #include "dchubbub.h" |
| 47 | #include "reg_helper.h" |
| 48 | #include "dcn10/dcn10_cm_common.h" |
| 49 | #include "dc_link_dp.h" |
| 50 | #include "vm_helper.h" |
| 51 | #include "dccg.h" |
| 52 | #include "dc_dmub_srv.h" |
| 53 | #include "dce/dmub_hw_lock_mgr.h" |
| 54 | #include "hw_sequencer.h" |
| 55 | #include "inc/link_dpcd.h" |
| 56 | #include "dpcd_defs.h" |
| 57 | #include "inc/link_enc_cfg.h" |
| 58 | #include "link_hwss.h" |
| 59 | |
| 60 | #define DC_LOGGER_INIT(logger) |
| 61 | |
| 62 | #define CTXhws->ctx \ |
| 63 | hws->ctx |
| 64 | #define REG(reg)hws->regs->reg\ |
| 65 | hws->regs->reg |
| 66 | |
| 67 | #undef FN |
| 68 | #define FN(reg_name, field_name)hws->shifts->field_name, hws->masks->field_name \ |
| 69 | hws->shifts->field_name, hws->masks->field_name |
| 70 | |
| 71 | static int find_free_gsl_group(const struct dc *dc) |
| 72 | { |
| 73 | if (dc->res_pool->gsl_groups.gsl_0 == 0) |
| 74 | return 1; |
| 75 | if (dc->res_pool->gsl_groups.gsl_1 == 0) |
| 76 | return 2; |
| 77 | if (dc->res_pool->gsl_groups.gsl_2 == 0) |
| 78 | return 3; |
| 79 | |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock) |
| 84 | * This is only used to lock pipes in pipe splitting case with immediate flip |
| 85 | * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate, |
| 86 | * so we get tearing with freesync since we cannot flip multiple pipes |
| 87 | * atomically. |
| 88 | * We use GSL for this: |
| 89 | * - immediate flip: find first available GSL group if not already assigned |
| 90 | * program gsl with that group, set current OTG as master |
| 91 | * and always us 0x4 = AND of flip_ready from all pipes |
| 92 | * - vsync flip: disable GSL if used |
| 93 | * |
| 94 | * Groups in stream_res are stored as +1 from HW registers, i.e. |
| 95 | * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1 |
| 96 | * Using a magic value like -1 would require tracking all inits/resets |
| 97 | */ |
| 98 | static void dcn20_setup_gsl_group_as_lock( |
| 99 | const struct dc *dc, |
| 100 | struct pipe_ctx *pipe_ctx, |
| 101 | bool_Bool enable) |
| 102 | { |
| 103 | struct gsl_params gsl; |
| 104 | int group_idx; |
| 105 | |
| 106 | memset(&gsl, 0, sizeof(struct gsl_params))__builtin_memset((&gsl), (0), (sizeof(struct gsl_params)) ); |
| 107 | |
| 108 | if (enable) { |
| 109 | /* return if group already assigned since GSL was set up |
| 110 | * for vsync flip, we would unassign so it can't be "left over" |
| 111 | */ |
| 112 | if (pipe_ctx->stream_res.gsl_group > 0) |
| 113 | return; |
| 114 | |
| 115 | group_idx = find_free_gsl_group(dc); |
| 116 | ASSERT(group_idx != 0)do { if (({ static int __warned; int __ret = !!(!(group_idx != 0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(group_idx != 0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 116); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 117 | pipe_ctx->stream_res.gsl_group = group_idx; |
| 118 | |
| 119 | /* set gsl group reg field and mark resource used */ |
| 120 | switch (group_idx) { |
| 121 | case 1: |
| 122 | gsl.gsl0_en = 1; |
| 123 | dc->res_pool->gsl_groups.gsl_0 = 1; |
| 124 | break; |
| 125 | case 2: |
| 126 | gsl.gsl1_en = 1; |
| 127 | dc->res_pool->gsl_groups.gsl_1 = 1; |
| 128 | break; |
| 129 | case 3: |
| 130 | gsl.gsl2_en = 1; |
| 131 | dc->res_pool->gsl_groups.gsl_2 = 1; |
| 132 | break; |
| 133 | default: |
| 134 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 134); do {} while (0); } while (0); |
| 135 | return; // invalid case |
| 136 | } |
| 137 | gsl.gsl_master_en = 1; |
| 138 | } else { |
| 139 | group_idx = pipe_ctx->stream_res.gsl_group; |
| 140 | if (group_idx == 0) |
| 141 | return; // if not in use, just return |
| 142 | |
| 143 | pipe_ctx->stream_res.gsl_group = 0; |
| 144 | |
| 145 | /* unset gsl group reg field and mark resource free */ |
| 146 | switch (group_idx) { |
| 147 | case 1: |
| 148 | gsl.gsl0_en = 0; |
| 149 | dc->res_pool->gsl_groups.gsl_0 = 0; |
| 150 | break; |
| 151 | case 2: |
| 152 | gsl.gsl1_en = 0; |
| 153 | dc->res_pool->gsl_groups.gsl_1 = 0; |
| 154 | break; |
| 155 | case 3: |
| 156 | gsl.gsl2_en = 0; |
| 157 | dc->res_pool->gsl_groups.gsl_2 = 0; |
| 158 | break; |
| 159 | default: |
| 160 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 160); do {} while (0); } while (0); |
| 161 | return; |
| 162 | } |
| 163 | gsl.gsl_master_en = 0; |
| 164 | } |
| 165 | |
| 166 | /* at this point we want to program whether it's to enable or disable */ |
| 167 | if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL((void *)0) && |
| 168 | pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL((void *)0)) { |
| 169 | pipe_ctx->stream_res.tg->funcs->set_gsl( |
| 170 | pipe_ctx->stream_res.tg, |
| 171 | &gsl); |
| 172 | |
| 173 | pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( |
| 174 | pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); |
| 175 | } else |
| 176 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 176); do {} while (0); } while (0); |
| 177 | } |
| 178 | |
| 179 | void dcn20_set_flip_control_gsl( |
| 180 | struct pipe_ctx *pipe_ctx, |
| 181 | bool_Bool flip_immediate) |
| 182 | { |
| 183 | if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) |
| 184 | pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( |
| 185 | pipe_ctx->plane_res.hubp, flip_immediate); |
| 186 | |
| 187 | } |
| 188 | |
| 189 | void dcn20_enable_power_gating_plane( |
| 190 | struct dce_hwseq *hws, |
| 191 | bool_Bool enable) |
| 192 | { |
| 193 | bool_Bool force_on = true1; /* disable power gating */ |
| 194 | |
| 195 | if (enable) |
| 196 | force_on = false0; |
| 197 | |
| 198 | /* DCHUBP0/1/2/3/4/5 */ |
| 199 | REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN0_PG_CONFIG , 1, hws->shifts->DOMAIN0_POWER_FORCEON, hws->masks-> DOMAIN0_POWER_FORCEON, force_on); |
| 200 | REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN2_PG_CONFIG , 1, hws->shifts->DOMAIN2_POWER_FORCEON, hws->masks-> DOMAIN2_POWER_FORCEON, force_on); |
| 201 | REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN4_PG_CONFIG , 1, hws->shifts->DOMAIN4_POWER_FORCEON, hws->masks-> DOMAIN4_POWER_FORCEON, force_on); |
| 202 | REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN6_PG_CONFIG , 1, hws->shifts->DOMAIN6_POWER_FORCEON, hws->masks-> DOMAIN6_POWER_FORCEON, force_on); |
| 203 | if (REG(DOMAIN8_PG_CONFIG)hws->regs->DOMAIN8_PG_CONFIG) |
| 204 | REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN8_PG_CONFIG , 1, hws->shifts->DOMAIN8_POWER_FORCEON, hws->masks-> DOMAIN8_POWER_FORCEON, force_on); |
| 205 | if (REG(DOMAIN10_PG_CONFIG)hws->regs->DOMAIN10_PG_CONFIG) |
| 206 | REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN10_PG_CONFIG , 1, hws->shifts->DOMAIN8_POWER_FORCEON, hws->masks-> DOMAIN8_POWER_FORCEON, force_on); |
| 207 | |
| 208 | /* DPP0/1/2/3/4/5 */ |
| 209 | REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN1_PG_CONFIG , 1, hws->shifts->DOMAIN1_POWER_FORCEON, hws->masks-> DOMAIN1_POWER_FORCEON, force_on); |
| 210 | REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN3_PG_CONFIG , 1, hws->shifts->DOMAIN3_POWER_FORCEON, hws->masks-> DOMAIN3_POWER_FORCEON, force_on); |
| 211 | REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN5_PG_CONFIG , 1, hws->shifts->DOMAIN5_POWER_FORCEON, hws->masks-> DOMAIN5_POWER_FORCEON, force_on); |
| 212 | REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN7_PG_CONFIG , 1, hws->shifts->DOMAIN7_POWER_FORCEON, hws->masks-> DOMAIN7_POWER_FORCEON, force_on); |
| 213 | if (REG(DOMAIN9_PG_CONFIG)hws->regs->DOMAIN9_PG_CONFIG) |
| 214 | REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN9_PG_CONFIG , 1, hws->shifts->DOMAIN9_POWER_FORCEON, hws->masks-> DOMAIN9_POWER_FORCEON, force_on); |
| 215 | if (REG(DOMAIN11_PG_CONFIG)hws->regs->DOMAIN11_PG_CONFIG) |
| 216 | REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN11_PG_CONFIG , 1, hws->shifts->DOMAIN9_POWER_FORCEON, hws->masks-> DOMAIN9_POWER_FORCEON, force_on); |
| 217 | |
| 218 | /* DCS0/1/2/3/4/5 */ |
| 219 | REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN16_PG_CONFIG , 1, hws->shifts->DOMAIN16_POWER_FORCEON, hws->masks ->DOMAIN16_POWER_FORCEON, force_on); |
| 220 | REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN17_PG_CONFIG , 1, hws->shifts->DOMAIN17_POWER_FORCEON, hws->masks ->DOMAIN17_POWER_FORCEON, force_on); |
| 221 | REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN18_PG_CONFIG , 1, hws->shifts->DOMAIN18_POWER_FORCEON, hws->masks ->DOMAIN18_POWER_FORCEON, force_on); |
| 222 | if (REG(DOMAIN19_PG_CONFIG)hws->regs->DOMAIN19_PG_CONFIG) |
| 223 | REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN19_PG_CONFIG , 1, hws->shifts->DOMAIN19_POWER_FORCEON, hws->masks ->DOMAIN19_POWER_FORCEON, force_on); |
| 224 | if (REG(DOMAIN20_PG_CONFIG)hws->regs->DOMAIN20_PG_CONFIG) |
| 225 | REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN20_PG_CONFIG , 1, hws->shifts->DOMAIN20_POWER_FORCEON, hws->masks ->DOMAIN20_POWER_FORCEON, force_on); |
| 226 | if (REG(DOMAIN21_PG_CONFIG)hws->regs->DOMAIN21_PG_CONFIG) |
| 227 | REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN21_PG_CONFIG , 1, hws->shifts->DOMAIN21_POWER_FORCEON, hws->masks ->DOMAIN21_POWER_FORCEON, force_on); |
| 228 | } |
| 229 | |
| 230 | void dcn20_dccg_init(struct dce_hwseq *hws) |
| 231 | { |
| 232 | /* |
| 233 | * set MICROSECOND_TIME_BASE_DIV |
| 234 | * 100Mhz refclk -> 0x120264 |
| 235 | * 27Mhz refclk -> 0x12021b |
| 236 | * 48Mhz refclk -> 0x120230 |
| 237 | * |
| 238 | */ |
| 239 | REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264)dm_write_reg_func(hws->ctx, hws->regs->MICROSECOND_TIME_BASE_DIV , 0x120264, __func__); |
| 240 | |
| 241 | /* |
| 242 | * set MILLISECOND_TIME_BASE_DIV |
| 243 | * 100Mhz refclk -> 0x1186a0 |
| 244 | * 27Mhz refclk -> 0x106978 |
| 245 | * 48Mhz refclk -> 0x10bb80 |
| 246 | * |
| 247 | */ |
| 248 | REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0)dm_write_reg_func(hws->ctx, hws->regs->MILLISECOND_TIME_BASE_DIV , 0x1186a0, __func__); |
| 249 | |
| 250 | /* This value is dependent on the hardware pipeline delay so set once per SOC */ |
| 251 | REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c)dm_write_reg_func(hws->ctx, hws->regs->DISPCLK_FREQ_CHANGE_CNTL , 0xe01003c, __func__); |
| 252 | } |
| 253 | |
| 254 | void dcn20_disable_vga( |
| 255 | struct dce_hwseq *hws) |
| 256 | { |
| 257 | REG_WRITE(D1VGA_CONTROL, 0)dm_write_reg_func(hws->ctx, hws->regs->D1VGA_CONTROL , 0, __func__); |
| 258 | REG_WRITE(D2VGA_CONTROL, 0)dm_write_reg_func(hws->ctx, hws->regs->D2VGA_CONTROL , 0, __func__); |
| 259 | REG_WRITE(D3VGA_CONTROL, 0)dm_write_reg_func(hws->ctx, hws->regs->D3VGA_CONTROL , 0, __func__); |
| 260 | REG_WRITE(D4VGA_CONTROL, 0)dm_write_reg_func(hws->ctx, hws->regs->D4VGA_CONTROL , 0, __func__); |
| 261 | REG_WRITE(D5VGA_CONTROL, 0)dm_write_reg_func(hws->ctx, hws->regs->D5VGA_CONTROL , 0, __func__); |
| 262 | REG_WRITE(D6VGA_CONTROL, 0)dm_write_reg_func(hws->ctx, hws->regs->D6VGA_CONTROL , 0, __func__); |
| 263 | } |
| 264 | |
| 265 | void dcn20_program_triple_buffer( |
| 266 | const struct dc *dc, |
| 267 | struct pipe_ctx *pipe_ctx, |
| 268 | bool_Bool enable_triple_buffer) |
| 269 | { |
| 270 | if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { |
| 271 | pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( |
| 272 | pipe_ctx->plane_res.hubp, |
| 273 | enable_triple_buffer); |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | /* Blank pixel data during initialization */ |
| 278 | void dcn20_init_blank( |
| 279 | struct dc *dc, |
| 280 | struct timing_generator *tg) |
| 281 | { |
| 282 | struct dce_hwseq *hws = dc->hwseq; |
| 283 | enum dc_color_space color_space; |
| 284 | struct tg_color black_color = {0}; |
| 285 | struct output_pixel_processor *opp = NULL((void *)0); |
| 286 | struct output_pixel_processor *bottom_opp = NULL((void *)0); |
| 287 | uint32_t num_opps, opp_id_src0, opp_id_src1; |
| 288 | uint32_t otg_active_width, otg_active_height; |
| 289 | |
| 290 | /* program opp dpg blank color */ |
| 291 | color_space = COLOR_SPACE_SRGB; |
| 292 | color_space_to_black_color(dc, color_space, &black_color); |
| 293 | |
| 294 | /* get the OTG active size */ |
| 295 | tg->funcs->get_otg_active_size(tg, |
| 296 | &otg_active_width, |
| 297 | &otg_active_height); |
| 298 | |
| 299 | /* get the OPTC source */ |
| 300 | tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); |
| 301 | |
| 302 | if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { |
| 303 | ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 303); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 304 | return; |
| 305 | } |
| 306 | opp = dc->res_pool->opps[opp_id_src0]; |
| 307 | |
| 308 | if (num_opps == 2) { |
| 309 | otg_active_width = otg_active_width / 2; |
| 310 | |
| 311 | if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { |
| 312 | ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 312); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 313 | return; |
| 314 | } |
| 315 | bottom_opp = dc->res_pool->opps[opp_id_src1]; |
| 316 | } |
| 317 | |
| 318 | opp->funcs->opp_set_disp_pattern_generator( |
| 319 | opp, |
| 320 | CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, |
| 321 | CONTROLLER_DP_COLOR_SPACE_UDEFINED, |
| 322 | COLOR_DEPTH_UNDEFINED, |
| 323 | &black_color, |
| 324 | otg_active_width, |
| 325 | otg_active_height, |
| 326 | 0); |
| 327 | |
| 328 | if (num_opps == 2) { |
| 329 | bottom_opp->funcs->opp_set_disp_pattern_generator( |
| 330 | bottom_opp, |
| 331 | CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, |
| 332 | CONTROLLER_DP_COLOR_SPACE_UDEFINED, |
| 333 | COLOR_DEPTH_UNDEFINED, |
| 334 | &black_color, |
| 335 | otg_active_width, |
| 336 | otg_active_height, |
| 337 | 0); |
| 338 | } |
| 339 | |
| 340 | hws->funcs.wait_for_blank_complete(opp); |
| 341 | } |
| 342 | |
| 343 | void dcn20_dsc_pg_control( |
| 344 | struct dce_hwseq *hws, |
| 345 | unsigned int dsc_inst, |
| 346 | bool_Bool power_on) |
| 347 | { |
| 348 | uint32_t power_gate = power_on ? 0 : 1; |
| 349 | uint32_t pwr_status = power_on ? 0 : 2; |
| 350 | uint32_t org_ip_request_cntl = 0; |
| 351 | |
| 352 | if (hws->ctx->dc->debug.disable_dsc_power_gate) |
| 353 | return; |
| 354 | |
| 355 | if (REG(DOMAIN16_PG_CONFIG)hws->regs->DOMAIN16_PG_CONFIG == 0) |
| 356 | return; |
| 357 | |
| 358 | REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl)generic_reg_get(hws->ctx, hws->regs->DC_IP_REQUEST_CNTL , hws->shifts->IP_REQUEST_EN, hws->masks->IP_REQUEST_EN , &org_ip_request_cntl); |
| 359 | if (org_ip_request_cntl == 0) |
| 360 | REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1)generic_reg_set_ex(hws->ctx, hws->regs->DC_IP_REQUEST_CNTL , 0, 1, hws->shifts->IP_REQUEST_EN, hws->masks->IP_REQUEST_EN , 1); |
| 361 | |
| 362 | switch (dsc_inst) { |
| 363 | case 0: /* DSC0 */ |
| 364 | REG_UPDATE(DOMAIN16_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN16_PG_CONFIG , 1, hws->shifts->DOMAIN16_POWER_GATE, hws->masks-> DOMAIN16_POWER_GATE, power_gate) |
| 365 | DOMAIN16_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN16_PG_CONFIG , 1, hws->shifts->DOMAIN16_POWER_GATE, hws->masks-> DOMAIN16_POWER_GATE, power_gate); |
| 366 | |
| 367 | REG_WAIT(DOMAIN16_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN16_PG_STATUS , hws->shifts->DOMAIN16_PGFSM_PWR_STATUS, hws->masks ->DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 369) |
| 368 | DOMAIN16_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN16_PG_STATUS , hws->shifts->DOMAIN16_PGFSM_PWR_STATUS, hws->masks ->DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 369) |
| 369 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN16_PG_STATUS , hws->shifts->DOMAIN16_PGFSM_PWR_STATUS, hws->masks ->DOMAIN16_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 369); |
| 370 | break; |
| 371 | case 1: /* DSC1 */ |
| 372 | REG_UPDATE(DOMAIN17_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN17_PG_CONFIG , 1, hws->shifts->DOMAIN17_POWER_GATE, hws->masks-> DOMAIN17_POWER_GATE, power_gate) |
| 373 | DOMAIN17_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN17_PG_CONFIG , 1, hws->shifts->DOMAIN17_POWER_GATE, hws->masks-> DOMAIN17_POWER_GATE, power_gate); |
| 374 | |
| 375 | REG_WAIT(DOMAIN17_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN17_PG_STATUS , hws->shifts->DOMAIN17_PGFSM_PWR_STATUS, hws->masks ->DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 377) |
| 376 | DOMAIN17_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN17_PG_STATUS , hws->shifts->DOMAIN17_PGFSM_PWR_STATUS, hws->masks ->DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 377) |
| 377 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN17_PG_STATUS , hws->shifts->DOMAIN17_PGFSM_PWR_STATUS, hws->masks ->DOMAIN17_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 377); |
| 378 | break; |
| 379 | case 2: /* DSC2 */ |
| 380 | REG_UPDATE(DOMAIN18_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN18_PG_CONFIG , 1, hws->shifts->DOMAIN18_POWER_GATE, hws->masks-> DOMAIN18_POWER_GATE, power_gate) |
| 381 | DOMAIN18_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN18_PG_CONFIG , 1, hws->shifts->DOMAIN18_POWER_GATE, hws->masks-> DOMAIN18_POWER_GATE, power_gate); |
| 382 | |
| 383 | REG_WAIT(DOMAIN18_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN18_PG_STATUS , hws->shifts->DOMAIN18_PGFSM_PWR_STATUS, hws->masks ->DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 385) |
| 384 | DOMAIN18_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN18_PG_STATUS , hws->shifts->DOMAIN18_PGFSM_PWR_STATUS, hws->masks ->DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 385) |
| 385 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN18_PG_STATUS , hws->shifts->DOMAIN18_PGFSM_PWR_STATUS, hws->masks ->DOMAIN18_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 385); |
| 386 | break; |
| 387 | case 3: /* DSC3 */ |
| 388 | REG_UPDATE(DOMAIN19_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN19_PG_CONFIG , 1, hws->shifts->DOMAIN19_POWER_GATE, hws->masks-> DOMAIN19_POWER_GATE, power_gate) |
| 389 | DOMAIN19_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN19_PG_CONFIG , 1, hws->shifts->DOMAIN19_POWER_GATE, hws->masks-> DOMAIN19_POWER_GATE, power_gate); |
| 390 | |
| 391 | REG_WAIT(DOMAIN19_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN19_PG_STATUS , hws->shifts->DOMAIN19_PGFSM_PWR_STATUS, hws->masks ->DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 393) |
| 392 | DOMAIN19_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN19_PG_STATUS , hws->shifts->DOMAIN19_PGFSM_PWR_STATUS, hws->masks ->DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 393) |
| 393 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN19_PG_STATUS , hws->shifts->DOMAIN19_PGFSM_PWR_STATUS, hws->masks ->DOMAIN19_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 393); |
| 394 | break; |
| 395 | case 4: /* DSC4 */ |
| 396 | REG_UPDATE(DOMAIN20_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN20_PG_CONFIG , 1, hws->shifts->DOMAIN20_POWER_GATE, hws->masks-> DOMAIN20_POWER_GATE, power_gate) |
| 397 | DOMAIN20_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN20_PG_CONFIG , 1, hws->shifts->DOMAIN20_POWER_GATE, hws->masks-> DOMAIN20_POWER_GATE, power_gate); |
| 398 | |
| 399 | REG_WAIT(DOMAIN20_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN20_PG_STATUS , hws->shifts->DOMAIN20_PGFSM_PWR_STATUS, hws->masks ->DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 401) |
| 400 | DOMAIN20_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN20_PG_STATUS , hws->shifts->DOMAIN20_PGFSM_PWR_STATUS, hws->masks ->DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 401) |
| 401 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN20_PG_STATUS , hws->shifts->DOMAIN20_PGFSM_PWR_STATUS, hws->masks ->DOMAIN20_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 401); |
| 402 | break; |
| 403 | case 5: /* DSC5 */ |
| 404 | REG_UPDATE(DOMAIN21_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN21_PG_CONFIG , 1, hws->shifts->DOMAIN21_POWER_GATE, hws->masks-> DOMAIN21_POWER_GATE, power_gate) |
| 405 | DOMAIN21_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN21_PG_CONFIG , 1, hws->shifts->DOMAIN21_POWER_GATE, hws->masks-> DOMAIN21_POWER_GATE, power_gate); |
| 406 | |
| 407 | REG_WAIT(DOMAIN21_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN21_PG_STATUS , hws->shifts->DOMAIN21_PGFSM_PWR_STATUS, hws->masks ->DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 409) |
| 408 | DOMAIN21_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN21_PG_STATUS , hws->shifts->DOMAIN21_PGFSM_PWR_STATUS, hws->masks ->DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 409) |
| 409 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN21_PG_STATUS , hws->shifts->DOMAIN21_PGFSM_PWR_STATUS, hws->masks ->DOMAIN21_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__ , 409); |
| 410 | break; |
| 411 | default: |
| 412 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 412); do {} while (0); } while (0); |
| 413 | break; |
| 414 | } |
| 415 | |
| 416 | if (org_ip_request_cntl == 0) |
| 417 | REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0)generic_reg_set_ex(hws->ctx, hws->regs->DC_IP_REQUEST_CNTL , 0, 1, hws->shifts->IP_REQUEST_EN, hws->masks->IP_REQUEST_EN , 0); |
| 418 | } |
| 419 | |
| 420 | void dcn20_dpp_pg_control( |
| 421 | struct dce_hwseq *hws, |
| 422 | unsigned int dpp_inst, |
| 423 | bool_Bool power_on) |
| 424 | { |
| 425 | uint32_t power_gate = power_on ? 0 : 1; |
| 426 | uint32_t pwr_status = power_on ? 0 : 2; |
| 427 | |
| 428 | if (hws->ctx->dc->debug.disable_dpp_power_gate) |
| 429 | return; |
| 430 | if (REG(DOMAIN1_PG_CONFIG)hws->regs->DOMAIN1_PG_CONFIG == 0) |
| 431 | return; |
| 432 | |
| 433 | switch (dpp_inst) { |
| 434 | case 0: /* DPP0 */ |
| 435 | REG_UPDATE(DOMAIN1_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN1_PG_CONFIG , 1, hws->shifts->DOMAIN1_POWER_GATE, hws->masks-> DOMAIN1_POWER_GATE, power_gate) |
| 436 | DOMAIN1_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN1_PG_CONFIG , 1, hws->shifts->DOMAIN1_POWER_GATE, hws->masks-> DOMAIN1_POWER_GATE, power_gate); |
| 437 | |
| 438 | REG_WAIT(DOMAIN1_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN1_PG_STATUS , hws->shifts->DOMAIN1_PGFSM_PWR_STATUS, hws->masks-> DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 440) |
| 439 | DOMAIN1_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN1_PG_STATUS , hws->shifts->DOMAIN1_PGFSM_PWR_STATUS, hws->masks-> DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 440) |
| 440 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN1_PG_STATUS , hws->shifts->DOMAIN1_PGFSM_PWR_STATUS, hws->masks-> DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 440); |
| 441 | break; |
| 442 | case 1: /* DPP1 */ |
| 443 | REG_UPDATE(DOMAIN3_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN3_PG_CONFIG , 1, hws->shifts->DOMAIN3_POWER_GATE, hws->masks-> DOMAIN3_POWER_GATE, power_gate) |
| 444 | DOMAIN3_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN3_PG_CONFIG , 1, hws->shifts->DOMAIN3_POWER_GATE, hws->masks-> DOMAIN3_POWER_GATE, power_gate); |
| 445 | |
| 446 | REG_WAIT(DOMAIN3_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN3_PG_STATUS , hws->shifts->DOMAIN3_PGFSM_PWR_STATUS, hws->masks-> DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 448) |
| 447 | DOMAIN3_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN3_PG_STATUS , hws->shifts->DOMAIN3_PGFSM_PWR_STATUS, hws->masks-> DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 448) |
| 448 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN3_PG_STATUS , hws->shifts->DOMAIN3_PGFSM_PWR_STATUS, hws->masks-> DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 448); |
| 449 | break; |
| 450 | case 2: /* DPP2 */ |
| 451 | REG_UPDATE(DOMAIN5_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN5_PG_CONFIG , 1, hws->shifts->DOMAIN5_POWER_GATE, hws->masks-> DOMAIN5_POWER_GATE, power_gate) |
| 452 | DOMAIN5_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN5_PG_CONFIG , 1, hws->shifts->DOMAIN5_POWER_GATE, hws->masks-> DOMAIN5_POWER_GATE, power_gate); |
| 453 | |
| 454 | REG_WAIT(DOMAIN5_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN5_PG_STATUS , hws->shifts->DOMAIN5_PGFSM_PWR_STATUS, hws->masks-> DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 456) |
| 455 | DOMAIN5_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN5_PG_STATUS , hws->shifts->DOMAIN5_PGFSM_PWR_STATUS, hws->masks-> DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 456) |
| 456 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN5_PG_STATUS , hws->shifts->DOMAIN5_PGFSM_PWR_STATUS, hws->masks-> DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 456); |
| 457 | break; |
| 458 | case 3: /* DPP3 */ |
| 459 | REG_UPDATE(DOMAIN7_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN7_PG_CONFIG , 1, hws->shifts->DOMAIN7_POWER_GATE, hws->masks-> DOMAIN7_POWER_GATE, power_gate) |
| 460 | DOMAIN7_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN7_PG_CONFIG , 1, hws->shifts->DOMAIN7_POWER_GATE, hws->masks-> DOMAIN7_POWER_GATE, power_gate); |
| 461 | |
| 462 | REG_WAIT(DOMAIN7_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN7_PG_STATUS , hws->shifts->DOMAIN7_PGFSM_PWR_STATUS, hws->masks-> DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 464) |
| 463 | DOMAIN7_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN7_PG_STATUS , hws->shifts->DOMAIN7_PGFSM_PWR_STATUS, hws->masks-> DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 464) |
| 464 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN7_PG_STATUS , hws->shifts->DOMAIN7_PGFSM_PWR_STATUS, hws->masks-> DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 464); |
| 465 | break; |
| 466 | case 4: /* DPP4 */ |
| 467 | REG_UPDATE(DOMAIN9_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN9_PG_CONFIG , 1, hws->shifts->DOMAIN9_POWER_GATE, hws->masks-> DOMAIN9_POWER_GATE, power_gate) |
| 468 | DOMAIN9_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN9_PG_CONFIG , 1, hws->shifts->DOMAIN9_POWER_GATE, hws->masks-> DOMAIN9_POWER_GATE, power_gate); |
| 469 | |
| 470 | REG_WAIT(DOMAIN9_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN9_PG_STATUS , hws->shifts->DOMAIN9_PGFSM_PWR_STATUS, hws->masks-> DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 472) |
| 471 | DOMAIN9_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN9_PG_STATUS , hws->shifts->DOMAIN9_PGFSM_PWR_STATUS, hws->masks-> DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 472) |
| 472 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN9_PG_STATUS , hws->shifts->DOMAIN9_PGFSM_PWR_STATUS, hws->masks-> DOMAIN9_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 472); |
| 473 | break; |
| 474 | case 5: /* DPP5 */ |
| 475 | /* |
| 476 | * Do not power gate DPP5, should be left at HW default, power on permanently. |
| 477 | * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard |
| 478 | * reset. |
| 479 | * REG_UPDATE(DOMAIN11_PG_CONFIG, |
| 480 | * DOMAIN11_POWER_GATE, power_gate); |
| 481 | * |
| 482 | * REG_WAIT(DOMAIN11_PG_STATUS, |
| 483 | * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, |
| 484 | * 1, 1000); |
| 485 | */ |
| 486 | break; |
| 487 | default: |
| 488 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 488); do {} while (0); } while (0); |
| 489 | break; |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | |
| 494 | void dcn20_hubp_pg_control( |
| 495 | struct dce_hwseq *hws, |
| 496 | unsigned int hubp_inst, |
| 497 | bool_Bool power_on) |
| 498 | { |
| 499 | uint32_t power_gate = power_on ? 0 : 1; |
| 500 | uint32_t pwr_status = power_on ? 0 : 2; |
| 501 | |
| 502 | if (hws->ctx->dc->debug.disable_hubp_power_gate) |
| 503 | return; |
| 504 | if (REG(DOMAIN0_PG_CONFIG)hws->regs->DOMAIN0_PG_CONFIG == 0) |
| 505 | return; |
| 506 | |
| 507 | switch (hubp_inst) { |
| 508 | case 0: /* DCHUBP0 */ |
| 509 | REG_UPDATE(DOMAIN0_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN0_PG_CONFIG , 1, hws->shifts->DOMAIN0_POWER_GATE, hws->masks-> DOMAIN0_POWER_GATE, power_gate) |
| 510 | DOMAIN0_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN0_PG_CONFIG , 1, hws->shifts->DOMAIN0_POWER_GATE, hws->masks-> DOMAIN0_POWER_GATE, power_gate); |
| 511 | |
| 512 | REG_WAIT(DOMAIN0_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN0_PG_STATUS , hws->shifts->DOMAIN0_PGFSM_PWR_STATUS, hws->masks-> DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 514) |
| 513 | DOMAIN0_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN0_PG_STATUS , hws->shifts->DOMAIN0_PGFSM_PWR_STATUS, hws->masks-> DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 514) |
| 514 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN0_PG_STATUS , hws->shifts->DOMAIN0_PGFSM_PWR_STATUS, hws->masks-> DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 514); |
| 515 | break; |
| 516 | case 1: /* DCHUBP1 */ |
| 517 | REG_UPDATE(DOMAIN2_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN2_PG_CONFIG , 1, hws->shifts->DOMAIN2_POWER_GATE, hws->masks-> DOMAIN2_POWER_GATE, power_gate) |
| 518 | DOMAIN2_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN2_PG_CONFIG , 1, hws->shifts->DOMAIN2_POWER_GATE, hws->masks-> DOMAIN2_POWER_GATE, power_gate); |
| 519 | |
| 520 | REG_WAIT(DOMAIN2_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN2_PG_STATUS , hws->shifts->DOMAIN2_PGFSM_PWR_STATUS, hws->masks-> DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 522) |
| 521 | DOMAIN2_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN2_PG_STATUS , hws->shifts->DOMAIN2_PGFSM_PWR_STATUS, hws->masks-> DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 522) |
| 522 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN2_PG_STATUS , hws->shifts->DOMAIN2_PGFSM_PWR_STATUS, hws->masks-> DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 522); |
| 523 | break; |
| 524 | case 2: /* DCHUBP2 */ |
| 525 | REG_UPDATE(DOMAIN4_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN4_PG_CONFIG , 1, hws->shifts->DOMAIN4_POWER_GATE, hws->masks-> DOMAIN4_POWER_GATE, power_gate) |
| 526 | DOMAIN4_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN4_PG_CONFIG , 1, hws->shifts->DOMAIN4_POWER_GATE, hws->masks-> DOMAIN4_POWER_GATE, power_gate); |
| 527 | |
| 528 | REG_WAIT(DOMAIN4_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN4_PG_STATUS , hws->shifts->DOMAIN4_PGFSM_PWR_STATUS, hws->masks-> DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 530) |
| 529 | DOMAIN4_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN4_PG_STATUS , hws->shifts->DOMAIN4_PGFSM_PWR_STATUS, hws->masks-> DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 530) |
| 530 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN4_PG_STATUS , hws->shifts->DOMAIN4_PGFSM_PWR_STATUS, hws->masks-> DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 530); |
| 531 | break; |
| 532 | case 3: /* DCHUBP3 */ |
| 533 | REG_UPDATE(DOMAIN6_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN6_PG_CONFIG , 1, hws->shifts->DOMAIN6_POWER_GATE, hws->masks-> DOMAIN6_POWER_GATE, power_gate) |
| 534 | DOMAIN6_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN6_PG_CONFIG , 1, hws->shifts->DOMAIN6_POWER_GATE, hws->masks-> DOMAIN6_POWER_GATE, power_gate); |
| 535 | |
| 536 | REG_WAIT(DOMAIN6_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN6_PG_STATUS , hws->shifts->DOMAIN6_PGFSM_PWR_STATUS, hws->masks-> DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 538) |
| 537 | DOMAIN6_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN6_PG_STATUS , hws->shifts->DOMAIN6_PGFSM_PWR_STATUS, hws->masks-> DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 538) |
| 538 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN6_PG_STATUS , hws->shifts->DOMAIN6_PGFSM_PWR_STATUS, hws->masks-> DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 538); |
| 539 | break; |
| 540 | case 4: /* DCHUBP4 */ |
| 541 | REG_UPDATE(DOMAIN8_PG_CONFIG,generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN8_PG_CONFIG , 1, hws->shifts->DOMAIN8_POWER_GATE, hws->masks-> DOMAIN8_POWER_GATE, power_gate) |
| 542 | DOMAIN8_POWER_GATE, power_gate)generic_reg_update_ex(hws->ctx, hws->regs->DOMAIN8_PG_CONFIG , 1, hws->shifts->DOMAIN8_POWER_GATE, hws->masks-> DOMAIN8_POWER_GATE, power_gate); |
| 543 | |
| 544 | REG_WAIT(DOMAIN8_PG_STATUS,generic_reg_wait(hws->ctx, hws->regs->DOMAIN8_PG_STATUS , hws->shifts->DOMAIN8_PGFSM_PWR_STATUS, hws->masks-> DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 546) |
| 545 | DOMAIN8_PGFSM_PWR_STATUS, pwr_status,generic_reg_wait(hws->ctx, hws->regs->DOMAIN8_PG_STATUS , hws->shifts->DOMAIN8_PGFSM_PWR_STATUS, hws->masks-> DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 546) |
| 546 | 1, 1000)generic_reg_wait(hws->ctx, hws->regs->DOMAIN8_PG_STATUS , hws->shifts->DOMAIN8_PGFSM_PWR_STATUS, hws->masks-> DOMAIN8_PGFSM_PWR_STATUS, pwr_status, 1, 1000, __func__, 546); |
| 547 | break; |
| 548 | case 5: /* DCHUBP5 */ |
| 549 | /* |
| 550 | * Do not power gate DCHUB5, should be left at HW default, power on permanently. |
| 551 | * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard |
| 552 | * reset. |
| 553 | * REG_UPDATE(DOMAIN10_PG_CONFIG, |
| 554 | * DOMAIN10_POWER_GATE, power_gate); |
| 555 | * |
| 556 | * REG_WAIT(DOMAIN10_PG_STATUS, |
| 557 | * DOMAIN10_PGFSM_PWR_STATUS, pwr_status, |
| 558 | * 1, 1000); |
| 559 | */ |
| 560 | break; |
| 561 | default: |
| 562 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 562); do {} while (0); } while (0); |
| 563 | break; |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | |
| 568 | /* disable HW used by plane. |
| 569 | * note: cannot disable until disconnect is complete |
| 570 | */ |
| 571 | void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) |
| 572 | { |
| 573 | struct dce_hwseq *hws = dc->hwseq; |
| 574 | struct hubp *hubp = pipe_ctx->plane_res.hubp; |
| 575 | struct dpp *dpp = pipe_ctx->plane_res.dpp; |
| 576 | |
| 577 | dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); |
| 578 | |
| 579 | /* In flip immediate with pipe splitting case GSL is used for |
| 580 | * synchronization so we must disable it when the plane is disabled. |
| 581 | */ |
| 582 | if (pipe_ctx->stream_res.gsl_group != 0) |
| 583 | dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false0); |
| 584 | |
| 585 | dc->hwss.set_flip_control_gsl(pipe_ctx, false0); |
| 586 | |
| 587 | hubp->funcs->hubp_clk_cntl(hubp, false0); |
| 588 | |
| 589 | dpp->funcs->dpp_dppclk_control(dpp, false0, false0); |
| 590 | |
| 591 | hubp->power_gated = true1; |
| 592 | |
| 593 | hws->funcs.plane_atomic_power_down(dc, |
| 594 | pipe_ctx->plane_res.dpp, |
| 595 | pipe_ctx->plane_res.hubp); |
| 596 | |
| 597 | pipe_ctx->stream = NULL((void *)0); |
| 598 | memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res))__builtin_memset((&pipe_ctx->stream_res), (0), (sizeof (pipe_ctx->stream_res))); |
| 599 | memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res))__builtin_memset((&pipe_ctx->plane_res), (0), (sizeof( pipe_ctx->plane_res))); |
| 600 | pipe_ctx->top_pipe = NULL((void *)0); |
| 601 | pipe_ctx->bottom_pipe = NULL((void *)0); |
| 602 | pipe_ctx->plane_state = NULL((void *)0); |
| 603 | } |
| 604 | |
| 605 | |
| 606 | void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) |
| 607 | { |
| 608 | DC_LOGGER_INIT(dc->ctx->logger); |
| 609 | |
| 610 | if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) |
| 611 | return; |
| 612 | |
| 613 | dcn20_plane_atomic_disable(dc, pipe_ctx); |
| 614 | |
| 615 | DC_LOG_DC("Power down front end %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Power down front end %d\n" , pipe_ctx->pipe_idx) |
| 616 | pipe_ctx->pipe_idx)___drm_dbg(((void *)0), DRM_UT_KMS, "Power down front end %d\n" , pipe_ctx->pipe_idx); |
| 617 | } |
| 618 | |
| 619 | void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool_Bool blank) |
| 620 | { |
| 621 | dcn20_blank_pixel_data(dc, pipe_ctx, blank); |
| 622 | } |
| 623 | |
| 624 | static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream, |
| 625 | int opp_cnt) |
| 626 | { |
| 627 | bool_Bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); |
| 628 | int flow_ctrl_cnt; |
| 629 | |
| 630 | if (opp_cnt >= 2) |
| 631 | hblank_halved = true1; |
| 632 | |
| 633 | flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - |
| 634 | stream->timing.h_border_left - |
| 635 | stream->timing.h_border_right; |
| 636 | |
| 637 | if (hblank_halved) |
| 638 | flow_ctrl_cnt /= 2; |
| 639 | |
| 640 | /* ODM combine 4:1 case */ |
| 641 | if (opp_cnt == 4) |
| 642 | flow_ctrl_cnt /= 2; |
| 643 | |
| 644 | return flow_ctrl_cnt; |
| 645 | } |
| 646 | |
| 647 | enum dc_status dcn20_enable_stream_timing( |
| 648 | struct pipe_ctx *pipe_ctx, |
| 649 | struct dc_state *context, |
| 650 | struct dc *dc) |
| 651 | { |
| 652 | struct dce_hwseq *hws = dc->hwseq; |
| 653 | struct dc_stream_state *stream = pipe_ctx->stream; |
| 654 | struct drr_params params = {0}; |
| 655 | unsigned int event_triggers = 0; |
| 656 | struct pipe_ctx *odm_pipe; |
| 657 | int opp_cnt = 1; |
| 658 | int opp_inst[MAX_PIPES6] = { pipe_ctx->stream_res.opp->inst }; |
| 659 | bool_Bool interlace = stream->timing.flags.INTERLACE; |
| 660 | int i; |
| 661 | struct mpc_dwb_flow_control flow_control; |
| 662 | struct mpc *mpc = dc->res_pool->mpc; |
| 663 | bool_Bool rate_control_2x_pclk = (interlace || optc2_is_two_pixels_per_containter(&stream->timing)); |
| 664 | unsigned int k1_div = PIXEL_RATE_DIV_NA; |
| 665 | unsigned int k2_div = PIXEL_RATE_DIV_NA; |
| 666 | |
| 667 | if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { |
| 668 | hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); |
| 669 | |
| 670 | dc->res_pool->dccg->funcs->set_pixel_rate_div( |
| 671 | dc->res_pool->dccg, |
| 672 | pipe_ctx->stream_res.tg->inst, |
| 673 | k1_div, k2_div); |
| 674 | } |
| 675 | /* by upper caller loop, pipe0 is parent pipe and be called first. |
| 676 | * back end is set up by for pipe0. Other children pipe share back end |
| 677 | * with pipe 0. No program is needed. |
| 678 | */ |
| 679 | if (pipe_ctx->top_pipe != NULL((void *)0)) |
| 680 | return DC_OK; |
| 681 | |
| 682 | /* TODO check if timing_changed, disable stream if timing changed */ |
| 683 | |
| 684 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { |
| 685 | opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; |
| 686 | opp_cnt++; |
| 687 | } |
| 688 | |
| 689 | if (opp_cnt > 1) |
| 690 | pipe_ctx->stream_res.tg->funcs->set_odm_combine( |
| 691 | pipe_ctx->stream_res.tg, |
| 692 | opp_inst, opp_cnt, |
| 693 | &pipe_ctx->stream->timing); |
| 694 | |
| 695 | /* HW program guide assume display already disable |
| 696 | * by unplug sequence. OTG assume stop. |
| 697 | */ |
| 698 | pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true1); |
| 699 | |
| 700 | if (false0 == pipe_ctx->clock_source->funcs->program_pix_clk( |
| 701 | pipe_ctx->clock_source, |
| 702 | &pipe_ctx->stream_res.pix_clk_params, |
| 703 | dp_get_link_encoding_format(&pipe_ctx->link_config.dp_link_settings), |
| 704 | &pipe_ctx->pll_settings)) { |
| 705 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 705); do {} while (0); } while (0); |
| 706 | return DC_ERROR_UNEXPECTED; |
| 707 | } |
| 708 | |
| 709 | if (dc_is_hdmi_tmds_signal(stream->signal)) { |
| 710 | stream->link->phy_state.symclk_ref_cnts.otg = 1; |
| 711 | if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) |
| 712 | stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; |
| 713 | else |
| 714 | stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; |
| 715 | } |
| 716 | |
| 717 | if (dc->hwseq->funcs.PLAT_58856_wa && (!dc_is_dp_signal(stream->signal))) |
| 718 | dc->hwseq->funcs.PLAT_58856_wa(context, pipe_ctx); |
| 719 | |
| 720 | pipe_ctx->stream_res.tg->funcs->program_timing( |
| 721 | pipe_ctx->stream_res.tg, |
| 722 | &stream->timing, |
| 723 | pipe_ctx->pipe_dlg_param.vready_offset, |
| 724 | pipe_ctx->pipe_dlg_param.vstartup_start, |
| 725 | pipe_ctx->pipe_dlg_param.vupdate_offset, |
| 726 | pipe_ctx->pipe_dlg_param.vupdate_width, |
| 727 | pipe_ctx->stream->signal, |
| 728 | true1); |
| 729 | |
| 730 | rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; |
| 731 | flow_control.flow_ctrl_mode = 0; |
| 732 | flow_control.flow_ctrl_cnt0 = 0x80; |
| 733 | flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); |
| 734 | if (mpc->funcs->set_out_rate_control) { |
| 735 | for (i = 0; i < opp_cnt; ++i) { |
| 736 | mpc->funcs->set_out_rate_control( |
| 737 | mpc, opp_inst[i], |
| 738 | true1, |
| 739 | rate_control_2x_pclk, |
| 740 | &flow_control); |
| 741 | } |
| 742 | } |
| 743 | |
| 744 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) |
| 745 | odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control( |
| 746 | odm_pipe->stream_res.opp, |
| 747 | true1); |
| 748 | |
| 749 | pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( |
| 750 | pipe_ctx->stream_res.opp, |
| 751 | true1); |
| 752 | |
| 753 | hws->funcs.blank_pixel_data(dc, pipe_ctx, true1); |
| 754 | |
| 755 | /* VTG is within DCHUB command block. DCFCLK is always on */ |
| 756 | if (false0 == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) { |
| 757 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 757); do {} while (0); } while (0); |
| 758 | return DC_ERROR_UNEXPECTED; |
| 759 | } |
| 760 | |
| 761 | hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp); |
| 762 | |
| 763 | params.vertical_total_min = stream->adjust.v_total_min; |
| 764 | params.vertical_total_max = stream->adjust.v_total_max; |
| 765 | params.vertical_total_mid = stream->adjust.v_total_mid; |
| 766 | params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num; |
| 767 | if (pipe_ctx->stream_res.tg->funcs->set_drr) |
| 768 | pipe_ctx->stream_res.tg->funcs->set_drr( |
| 769 | pipe_ctx->stream_res.tg, ¶ms); |
| 770 | |
| 771 | // DRR should set trigger event to monitor surface update event |
| 772 | if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) |
| 773 | event_triggers = 0x80; |
| 774 | /* Event triggers and num frames initialized for DRR, but can be |
| 775 | * later updated for PSR use. Note DRR trigger events are generated |
| 776 | * regardless of whether num frames met. |
| 777 | */ |
| 778 | if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) |
| 779 | pipe_ctx->stream_res.tg->funcs->set_static_screen_control( |
| 780 | pipe_ctx->stream_res.tg, event_triggers, 2); |
| 781 | |
| 782 | /* TODO program crtc source select for non-virtual signal*/ |
| 783 | /* TODO program FMT */ |
| 784 | /* TODO setup link_enc */ |
| 785 | /* TODO set stream attributes */ |
| 786 | /* TODO program audio */ |
| 787 | /* TODO enable stream if timing changed */ |
| 788 | /* TODO unblank stream if DP */ |
| 789 | |
| 790 | if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) { |
| 791 | if (pipe_ctx->stream_res.tg && pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable) |
| 792 | pipe_ctx->stream_res.tg->funcs->phantom_crtc_post_enable(pipe_ctx->stream_res.tg); |
| 793 | } |
| 794 | return DC_OK; |
| 795 | } |
| 796 | |
| 797 | void dcn20_program_output_csc(struct dc *dc, |
| 798 | struct pipe_ctx *pipe_ctx, |
| 799 | enum dc_color_space colorspace, |
| 800 | uint16_t *matrix, |
| 801 | int opp_id) |
| 802 | { |
| 803 | struct mpc *mpc = dc->res_pool->mpc; |
| 804 | enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A; |
| 805 | int mpcc_id = pipe_ctx->plane_res.hubp->inst; |
| 806 | |
| 807 | if (mpc->funcs->power_on_mpc_mem_pwr) |
| 808 | mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true1); |
| 809 | |
| 810 | if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true1) { |
| 811 | if (mpc->funcs->set_output_csc != NULL((void *)0)) |
| 812 | mpc->funcs->set_output_csc(mpc, |
| 813 | opp_id, |
| 814 | matrix, |
| 815 | ocsc_mode); |
| 816 | } else { |
| 817 | if (mpc->funcs->set_ocsc_default != NULL((void *)0)) |
| 818 | mpc->funcs->set_ocsc_default(mpc, |
| 819 | opp_id, |
| 820 | colorspace, |
| 821 | ocsc_mode); |
| 822 | } |
| 823 | } |
| 824 | |
| 825 | bool_Bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, |
| 826 | const struct dc_stream_state *stream) |
| 827 | { |
| 828 | int mpcc_id = pipe_ctx->plane_res.hubp->inst; |
| 829 | struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; |
| 830 | struct pwl_params *params = NULL((void *)0); |
| 831 | /* |
| 832 | * program OGAM only for the top pipe |
| 833 | * if there is a pipe split then fix diagnostic is required: |
| 834 | * how to pass OGAM parameter for stream. |
| 835 | * if programming for all pipes is required then remove condition |
| 836 | * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic. |
| 837 | */ |
| 838 | if (mpc->funcs->power_on_mpc_mem_pwr) |
| 839 | mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true1); |
| 840 | if (pipe_ctx->top_pipe == NULL((void *)0) |
| 841 | && mpc->funcs->set_output_gamma && stream->out_transfer_func) { |
| 842 | if (stream->out_transfer_func->type == TF_TYPE_HWPWL) |
| 843 | params = &stream->out_transfer_func->pwl; |
| 844 | else if (pipe_ctx->stream->out_transfer_func->type == |
| 845 | TF_TYPE_DISTRIBUTED_POINTS && |
| 846 | cm_helper_translate_curve_to_hw_format(dc->ctx, |
| 847 | stream->out_transfer_func, |
| 848 | &mpc->blender_params, false0)) |
| 849 | params = &mpc->blender_params; |
| 850 | /* |
| 851 | * there is no ROM |
| 852 | */ |
| 853 | if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) |
| 854 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 854); do {} while (0); } while (0); |
| 855 | } |
| 856 | /* |
| 857 | * if above if is not executed then 'params' equal to 0 and set in bypass |
| 858 | */ |
| 859 | mpc->funcs->set_output_gamma(mpc, mpcc_id, params); |
| 860 | |
| 861 | return true1; |
| 862 | } |
| 863 | |
| 864 | bool_Bool dcn20_set_blend_lut( |
| 865 | struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) |
| 866 | { |
| 867 | struct dpp *dpp_base = pipe_ctx->plane_res.dpp; |
| 868 | bool_Bool result = true1; |
| 869 | struct pwl_params *blend_lut = NULL((void *)0); |
| 870 | |
| 871 | if (plane_state->blend_tf) { |
| 872 | if (plane_state->blend_tf->type == TF_TYPE_HWPWL) |
| 873 | blend_lut = &plane_state->blend_tf->pwl; |
| 874 | else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { |
| 875 | cm_helper_translate_curve_to_hw_format(plane_state->ctx, |
| 876 | plane_state->blend_tf, |
| 877 | &dpp_base->regamma_params, false0); |
| 878 | blend_lut = &dpp_base->regamma_params; |
| 879 | } |
| 880 | } |
| 881 | result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); |
| 882 | |
| 883 | return result; |
| 884 | } |
| 885 | |
| 886 | bool_Bool dcn20_set_shaper_3dlut( |
| 887 | struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) |
| 888 | { |
| 889 | struct dpp *dpp_base = pipe_ctx->plane_res.dpp; |
| 890 | bool_Bool result = true1; |
| 891 | struct pwl_params *shaper_lut = NULL((void *)0); |
| 892 | |
| 893 | if (plane_state->in_shaper_func) { |
| 894 | if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL) |
| 895 | shaper_lut = &plane_state->in_shaper_func->pwl; |
| 896 | else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) { |
| 897 | cm_helper_translate_curve_to_hw_format(plane_state->ctx, |
| 898 | plane_state->in_shaper_func, |
| 899 | &dpp_base->shaper_params, true1); |
| 900 | shaper_lut = &dpp_base->shaper_params; |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); |
Value stored to 'result' is never read | |
| 905 | if (plane_state->lut3d_func && |
| 906 | plane_state->lut3d_func->state.bits.initialized == 1) |
| 907 | result = dpp_base->funcs->dpp_program_3dlut(dpp_base, |
| 908 | &plane_state->lut3d_func->lut_3d); |
| 909 | else |
| 910 | result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL((void *)0)); |
| 911 | |
| 912 | return result; |
| 913 | } |
| 914 | |
| 915 | bool_Bool dcn20_set_input_transfer_func(struct dc *dc, |
| 916 | struct pipe_ctx *pipe_ctx, |
| 917 | const struct dc_plane_state *plane_state) |
| 918 | { |
| 919 | struct dce_hwseq *hws = dc->hwseq; |
| 920 | struct dpp *dpp_base = pipe_ctx->plane_res.dpp; |
| 921 | const struct dc_transfer_func *tf = NULL((void *)0); |
| 922 | bool_Bool result = true1; |
| 923 | bool_Bool use_degamma_ram = false0; |
| 924 | |
| 925 | if (dpp_base == NULL((void *)0) || plane_state == NULL((void *)0)) |
| 926 | return false0; |
| 927 | |
| 928 | hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); |
| 929 | hws->funcs.set_blend_lut(pipe_ctx, plane_state); |
| 930 | |
| 931 | if (plane_state->in_transfer_func) |
| 932 | tf = plane_state->in_transfer_func; |
| 933 | |
| 934 | |
| 935 | if (tf == NULL((void *)0)) { |
| 936 | dpp_base->funcs->dpp_set_degamma(dpp_base, |
| 937 | IPP_DEGAMMA_MODE_BYPASS); |
| 938 | return true1; |
| 939 | } |
| 940 | |
| 941 | if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS) |
| 942 | use_degamma_ram = true1; |
| 943 | |
| 944 | if (use_degamma_ram == true1) { |
| 945 | if (tf->type == TF_TYPE_HWPWL) |
| 946 | dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, |
| 947 | &tf->pwl); |
| 948 | else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) { |
| 949 | cm_helper_translate_curve_to_degamma_hw_format(tf, |
| 950 | &dpp_base->degamma_params); |
| 951 | dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, |
| 952 | &dpp_base->degamma_params); |
| 953 | } |
| 954 | return true1; |
| 955 | } |
| 956 | /* handle here the optimized cases when de-gamma ROM could be used. |
| 957 | * |
| 958 | */ |
| 959 | if (tf->type == TF_TYPE_PREDEFINED) { |
| 960 | switch (tf->tf) { |
| 961 | case TRANSFER_FUNCTION_SRGB: |
| 962 | dpp_base->funcs->dpp_set_degamma(dpp_base, |
| 963 | IPP_DEGAMMA_MODE_HW_sRGB); |
| 964 | break; |
| 965 | case TRANSFER_FUNCTION_BT709: |
| 966 | dpp_base->funcs->dpp_set_degamma(dpp_base, |
| 967 | IPP_DEGAMMA_MODE_HW_xvYCC); |
| 968 | break; |
| 969 | case TRANSFER_FUNCTION_LINEAR: |
| 970 | dpp_base->funcs->dpp_set_degamma(dpp_base, |
| 971 | IPP_DEGAMMA_MODE_BYPASS); |
| 972 | break; |
| 973 | case TRANSFER_FUNCTION_PQ: |
| 974 | dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); |
| 975 | cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params); |
| 976 | dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); |
| 977 | result = true1; |
| 978 | break; |
| 979 | default: |
| 980 | result = false0; |
| 981 | break; |
| 982 | } |
| 983 | } else if (tf->type == TF_TYPE_BYPASS) |
| 984 | dpp_base->funcs->dpp_set_degamma(dpp_base, |
| 985 | IPP_DEGAMMA_MODE_BYPASS); |
| 986 | else { |
| 987 | /* |
| 988 | * if we are here, we did not handle correctly. |
| 989 | * fix is required for this use case |
| 990 | */ |
| 991 | BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__ , 991); do {} while (0); } while (0); |
| 992 | dpp_base->funcs->dpp_set_degamma(dpp_base, |
| 993 | IPP_DEGAMMA_MODE_BYPASS); |
| 994 | } |
| 995 | |
| 996 | return result; |
| 997 | } |
| 998 | |
| 999 | void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) |
| 1000 | { |
| 1001 | struct pipe_ctx *odm_pipe; |
| 1002 | int opp_cnt = 1; |
| 1003 | int opp_inst[MAX_PIPES6] = { pipe_ctx->stream_res.opp->inst }; |
| 1004 | |
| 1005 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { |
| 1006 | opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; |
| 1007 | opp_cnt++; |
| 1008 | } |
| 1009 | |
| 1010 | if (opp_cnt > 1) |
| 1011 | pipe_ctx->stream_res.tg->funcs->set_odm_combine( |
| 1012 | pipe_ctx->stream_res.tg, |
| 1013 | opp_inst, opp_cnt, |
| 1014 | &pipe_ctx->stream->timing); |
| 1015 | else |
| 1016 | pipe_ctx->stream_res.tg->funcs->set_odm_bypass( |
| 1017 | pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); |
| 1018 | } |
| 1019 | |
| 1020 | void dcn20_blank_pixel_data( |
| 1021 | struct dc *dc, |
| 1022 | struct pipe_ctx *pipe_ctx, |
| 1023 | bool_Bool blank) |
| 1024 | { |
| 1025 | struct tg_color black_color = {0}; |
| 1026 | struct stream_resource *stream_res = &pipe_ctx->stream_res; |
| 1027 | struct dc_stream_state *stream = pipe_ctx->stream; |
| 1028 | enum dc_color_space color_space = stream->output_color_space; |
| 1029 | enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR; |
| 1030 | enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED; |
| 1031 | struct pipe_ctx *odm_pipe; |
| 1032 | int odm_cnt = 1; |
| 1033 | |
| 1034 | int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; |
| 1035 | int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; |
| 1036 | |
| 1037 | if (stream->link->test_pattern_enabled) |
| 1038 | return; |
| 1039 | |
| 1040 | /* get opp dpg blank color */ |
| 1041 | color_space_to_black_color(dc, color_space, &black_color); |
| 1042 | |
| 1043 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) |
| 1044 | odm_cnt++; |
| 1045 | |
| 1046 | width = width / odm_cnt; |
| 1047 | |
| 1048 | if (blank) { |
| 1049 | dc->hwss.set_abm_immediate_disable(pipe_ctx); |
| 1050 | |
| 1051 | if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { |
| 1052 | test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES; |
| 1053 | test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB; |
| 1054 | } |
| 1055 | } else { |
| 1056 | test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE; |
| 1057 | } |
| 1058 | |
| 1059 | dc->hwss.set_disp_pattern_generator(dc, |
| 1060 | pipe_ctx, |
| 1061 | test_pattern, |
| 1062 | test_pattern_color_space, |
| 1063 | stream->timing.display_color_depth, |
| 1064 | &black_color, |
| 1065 | width, |
| 1066 | height, |
| 1067 | 0); |
| 1068 | |
| 1069 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { |
| 1070 | dc->hwss.set_disp_pattern_generator(dc, |
| 1071 | odm_pipe, |
| 1072 | dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ? |
| 1073 | CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern, |
| 1074 | test_pattern_color_space, |
| 1075 | stream->timing.display_color_depth, |
| 1076 | &black_color, |
| 1077 | width, |
| 1078 | height, |
| 1079 | 0); |
| 1080 | } |
| 1081 | |
| 1082 | if (!blank) |
| 1083 | if (stream_res->abm) { |
| 1084 | dc->hwss.set_pipe(pipe_ctx); |
| 1085 | stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level); |
| 1086 | } |
| 1087 | } |
| 1088 | |
| 1089 | |
| 1090 | static void dcn20_power_on_plane_resources( |
| 1091 | struct dce_hwseq *hws, |
| 1092 | struct pipe_ctx *pipe_ctx) |
| 1093 | { |
| 1094 | DC_LOGGER_INIT(hws->ctx->logger); |
| 1095 | |
| 1096 | if (hws->funcs.dpp_root_clock_control) |
| 1097 | hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true1); |
| 1098 | |
| 1099 | if (REG(DC_IP_REQUEST_CNTL)hws->regs->DC_IP_REQUEST_CNTL) { |
| 1100 | REG_SET(DC_IP_REQUEST_CNTL, 0,generic_reg_set_ex(hws->ctx, hws->regs->DC_IP_REQUEST_CNTL , 0, 1, hws->shifts->IP_REQUEST_EN, hws->masks->IP_REQUEST_EN , 1) |
| 1101 | IP_REQUEST_EN, 1)generic_reg_set_ex(hws->ctx, hws->regs->DC_IP_REQUEST_CNTL , 0, 1, hws->shifts->IP_REQUEST_EN, hws->masks->IP_REQUEST_EN , 1); |
| 1102 | |
| 1103 | if (hws->funcs.dpp_pg_control) |
| 1104 | hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true1); |
| 1105 | |
| 1106 | if (hws->funcs.hubp_pg_control) |
| 1107 | hws->funcs.hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true1); |
| 1108 | |
| 1109 | REG_SET(DC_IP_REQUEST_CNTL, 0,generic_reg_set_ex(hws->ctx, hws->regs->DC_IP_REQUEST_CNTL , 0, 1, hws->shifts->IP_REQUEST_EN, hws->masks->IP_REQUEST_EN , 0) |
| 1110 | IP_REQUEST_EN, 0)generic_reg_set_ex(hws->ctx, hws->regs->DC_IP_REQUEST_CNTL , 0, 1, hws->shifts->IP_REQUEST_EN, hws->masks->IP_REQUEST_EN , 0); |
| 1111 | DC_LOG_DEBUG(___drm_dbg(((void *)0), DRM_UT_KMS, "Un-gated front end for pipe %d\n" , pipe_ctx->plane_res.hubp->inst) |
| 1112 | "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst)___drm_dbg(((void *)0), DRM_UT_KMS, "Un-gated front end for pipe %d\n" , pipe_ctx->plane_res.hubp->inst); |
| 1113 | } |
| 1114 | } |
| 1115 | |
| 1116 | static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, |
| 1117 | struct dc_state *context) |
| 1118 | { |
| 1119 | //if (dc->debug.sanity_checks) { |
| 1120 | // dcn10_verify_allow_pstate_change_high(dc); |
| 1121 | //} |
| 1122 | dcn20_power_on_plane_resources(dc->hwseq, pipe_ctx); |
| 1123 | |
| 1124 | /* enable DCFCLK current DCHUB */ |
| 1125 | pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true1); |
| 1126 | |
| 1127 | /* initialize HUBP on power up */ |
| 1128 | pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp); |
| 1129 | |
| 1130 | /* make sure OPP_PIPE_CLOCK_EN = 1 */ |
| 1131 | pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( |
| 1132 | pipe_ctx->stream_res.opp, |
| 1133 | true1); |
| 1134 | |
| 1135 | /* TODO: enable/disable in dm as per update type. |
| 1136 | if (plane_state) { |
| 1137 | DC_LOG_DC(dc->ctx->logger, |
| 1138 | "Pipe:%d 0x%x: addr hi:0x%x, " |
| 1139 | "addr low:0x%x, " |
| 1140 | "src: %d, %d, %d," |
| 1141 | " %d; dst: %d, %d, %d, %d;\n", |
| 1142 | pipe_ctx->pipe_idx, |
| 1143 | plane_state, |
| 1144 | plane_state->address.grph.addr.high_part, |
| 1145 | plane_state->address.grph.addr.low_part, |
| 1146 | plane_state->src_rect.x, |
| 1147 | plane_state->src_rect.y, |
| 1148 | plane_state->src_rect.width, |
| 1149 | plane_state->src_rect.height, |
| 1150 | plane_state->dst_rect.x, |
| 1151 | plane_state->dst_rect.y, |
| 1152 | plane_state->dst_rect.width, |
| 1153 | plane_state->dst_rect.height); |
| 1154 | |
| 1155 | DC_LOG_DC(dc->ctx->logger, |
| 1156 | "Pipe %d: width, height, x, y format:%d\n" |
| 1157 | "viewport:%d, %d, %d, %d\n" |
| 1158 | "recout: %d, %d, %d, %d\n", |
| 1159 | pipe_ctx->pipe_idx, |
| 1160 | plane_state->format, |
| 1161 | pipe_ctx->plane_res.scl_data.viewport.width, |
| 1162 | pipe_ctx->plane_res.scl_data.viewport.height, |
| 1163 | pipe_ctx->plane_res.scl_data.viewport.x, |
| 1164 | pipe_ctx->plane_res.scl_data.viewport.y, |
| 1165 | pipe_ctx->plane_res.scl_data.recout.width, |
| 1166 | pipe_ctx->plane_res.scl_data.recout.height, |
| 1167 | pipe_ctx->plane_res.scl_data.recout.x, |
| 1168 | pipe_ctx->plane_res.scl_data.recout.y); |
| 1169 | print_rq_dlg_ttu(dc, pipe_ctx); |
| 1170 | } |
| 1171 | */ |
| 1172 | if (dc->vm_pa_config.valid) { |
| 1173 | struct vm_system_aperture_param apt; |
| 1174 | |
| 1175 | apt.sys_default.quad_part = 0; |
| 1176 | |
| 1177 | apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; |
| 1178 | apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; |
| 1179 | |
| 1180 | // Program system aperture settings |
| 1181 | pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); |
| 1182 | } |
| 1183 | |
| 1184 | if (!pipe_ctx->top_pipe |
| 1185 | && pipe_ctx->plane_state |
| 1186 | && pipe_ctx->plane_state->flip_int_enabled |
| 1187 | && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int) |
| 1188 | pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_int(pipe_ctx->plane_res.hubp); |
| 1189 | |
| 1190 | // if (dc->debug.sanity_checks) { |
| 1191 | // dcn10_verify_allow_pstate_change_high(dc); |
| 1192 | // } |
| 1193 | } |
| 1194 | |
| 1195 | void dcn20_pipe_control_lock( |
| 1196 | struct dc *dc, |
| 1197 | struct pipe_ctx *pipe, |
| 1198 | bool_Bool lock) |
| 1199 | { |
| 1200 | struct pipe_ctx *temp_pipe; |
| 1201 | bool_Bool flip_immediate = false0; |
| 1202 | |
| 1203 | /* use TG master update lock to lock everything on the TG |
| 1204 | * therefore only top pipe need to lock |
| 1205 | */ |
| 1206 | if (!pipe || pipe->top_pipe) |
| 1207 | return; |
| 1208 | |
| 1209 | if (pipe->plane_state != NULL((void *)0)) |
| 1210 | flip_immediate = pipe->plane_state->flip_immediate; |
| 1211 | |
| 1212 | if (pipe->stream_res.gsl_group > 0) { |
| 1213 | temp_pipe = pipe->bottom_pipe; |
| 1214 | while (!flip_immediate && temp_pipe) { |
| 1215 | if (temp_pipe->plane_state != NULL((void *)0)) |
| 1216 | flip_immediate = temp_pipe->plane_state->flip_immediate; |
| 1217 | temp_pipe = temp_pipe->bottom_pipe; |
| 1218 | } |
| 1219 | } |
| 1220 | |
| 1221 | if (flip_immediate && lock) { |
| 1222 | const int TIMEOUT_FOR_FLIP_PENDING = 100000; |
| 1223 | int i; |
| 1224 | |
| 1225 | temp_pipe = pipe; |
| 1226 | while (temp_pipe) { |
| 1227 | if (temp_pipe->plane_state && temp_pipe->plane_state->flip_immediate) { |
| 1228 | for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) { |
| 1229 | if (!temp_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(temp_pipe->plane_res.hubp)) |
| 1230 | break; |
| 1231 | udelay(1); |
| 1232 | } |
| 1233 | |
| 1234 | /* no reason it should take this long for immediate flips */ |
| 1235 | ASSERT(i != TIMEOUT_FOR_FLIP_PENDING)do { if (({ static int __warned; int __ret = !!(!(i != TIMEOUT_FOR_FLIP_PENDING )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(i != TIMEOUT_FOR_FLIP_PENDING)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 1235); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1236 | } |
| 1237 | temp_pipe = temp_pipe->bottom_pipe; |
| 1238 | } |
| 1239 | } |
| 1240 | |
| 1241 | /* In flip immediate and pipe splitting case, we need to use GSL |
| 1242 | * for synchronization. Only do setup on locking and on flip type change. |
| 1243 | */ |
| 1244 | if (lock && (pipe->bottom_pipe != NULL((void *)0) || !flip_immediate)) |
| 1245 | if ((flip_immediate && pipe->stream_res.gsl_group == 0) || |
| 1246 | (!flip_immediate && pipe->stream_res.gsl_group > 0)) |
| 1247 | dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); |
| 1248 | |
| 1249 | if (pipe->plane_state != NULL((void *)0)) |
| 1250 | flip_immediate = pipe->plane_state->flip_immediate; |
| 1251 | |
| 1252 | temp_pipe = pipe->bottom_pipe; |
| 1253 | while (flip_immediate && temp_pipe) { |
| 1254 | if (temp_pipe->plane_state != NULL((void *)0)) |
| 1255 | flip_immediate = temp_pipe->plane_state->flip_immediate; |
| 1256 | temp_pipe = temp_pipe->bottom_pipe; |
| 1257 | } |
| 1258 | |
| 1259 | if (!lock && pipe->stream_res.gsl_group > 0 && pipe->plane_state && |
| 1260 | !flip_immediate) |
| 1261 | dcn20_setup_gsl_group_as_lock(dc, pipe, false0); |
| 1262 | |
| 1263 | if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { |
| 1264 | union dmub_hw_lock_flags hw_locks = { 0 }; |
| 1265 | struct dmub_hw_lock_inst_flags inst_flags = { 0 }; |
| 1266 | |
| 1267 | hw_locks.bits.lock_pipe = 1; |
| 1268 | inst_flags.otg_inst = pipe->stream_res.tg->inst; |
| 1269 | |
| 1270 | if (pipe->plane_state != NULL((void *)0)) |
| 1271 | hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; |
| 1272 | |
| 1273 | dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, |
| 1274 | lock, |
| 1275 | &hw_locks, |
| 1276 | &inst_flags); |
| 1277 | } else if (pipe->plane_state != NULL((void *)0) && pipe->plane_state->triplebuffer_flips) { |
| 1278 | if (lock) |
| 1279 | pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); |
| 1280 | else |
| 1281 | pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); |
| 1282 | } else { |
| 1283 | if (lock) |
| 1284 | pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); |
| 1285 | else |
| 1286 | pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); |
| 1287 | } |
| 1288 | } |
| 1289 | |
| 1290 | static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) |
| 1291 | { |
| 1292 | new_pipe->update_flags.raw = 0; |
| 1293 | |
| 1294 | /* Exit on unchanged, unused pipe */ |
| 1295 | if (!old_pipe->plane_state && !new_pipe->plane_state) |
| 1296 | return; |
| 1297 | /* Detect pipe enable/disable */ |
| 1298 | if (!old_pipe->plane_state && new_pipe->plane_state) { |
| 1299 | new_pipe->update_flags.bits.enable = 1; |
| 1300 | new_pipe->update_flags.bits.mpcc = 1; |
| 1301 | new_pipe->update_flags.bits.dppclk = 1; |
| 1302 | new_pipe->update_flags.bits.hubp_interdependent = 1; |
| 1303 | new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; |
| 1304 | new_pipe->update_flags.bits.gamut_remap = 1; |
| 1305 | new_pipe->update_flags.bits.scaler = 1; |
| 1306 | new_pipe->update_flags.bits.viewport = 1; |
| 1307 | new_pipe->update_flags.bits.det_size = 1; |
| 1308 | if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { |
| 1309 | new_pipe->update_flags.bits.odm = 1; |
| 1310 | new_pipe->update_flags.bits.global_sync = 1; |
| 1311 | } |
| 1312 | return; |
| 1313 | } |
| 1314 | |
| 1315 | /* For SubVP we need to unconditionally enable because any phantom pipes are |
| 1316 | * always removed then newly added for every full updates whenever SubVP is in use. |
| 1317 | * The remove-add sequence of the phantom pipe always results in the pipe |
| 1318 | * being blanked in enable_stream_timing (DPG). |
| 1319 | */ |
| 1320 | if (new_pipe->stream && new_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) |
| 1321 | new_pipe->update_flags.bits.enable = 1; |
| 1322 | |
| 1323 | /* Phantom pipes are effectively disabled, if the pipe was previously phantom |
| 1324 | * we have to enable |
| 1325 | */ |
| 1326 | if (old_pipe->plane_state && old_pipe->plane_state->is_phantom && |
| 1327 | new_pipe->plane_state && !new_pipe->plane_state->is_phantom) |
| 1328 | new_pipe->update_flags.bits.enable = 1; |
| 1329 | |
| 1330 | if (old_pipe->plane_state && !new_pipe->plane_state) { |
| 1331 | new_pipe->update_flags.bits.disable = 1; |
| 1332 | return; |
| 1333 | } |
| 1334 | |
| 1335 | /* Detect plane change */ |
| 1336 | if (old_pipe->plane_state != new_pipe->plane_state) { |
| 1337 | new_pipe->update_flags.bits.plane_changed = true1; |
| 1338 | } |
| 1339 | |
| 1340 | /* Detect top pipe only changes */ |
| 1341 | if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) { |
| 1342 | /* Detect odm changes */ |
| 1343 | if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe |
| 1344 | && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) |
| 1345 | || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) |
| 1346 | || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) |
| 1347 | || old_pipe->stream_res.opp != new_pipe->stream_res.opp) |
| 1348 | new_pipe->update_flags.bits.odm = 1; |
| 1349 | |
| 1350 | /* Detect global sync changes */ |
| 1351 | if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset |
| 1352 | || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start |
| 1353 | || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset |
| 1354 | || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width) |
| 1355 | new_pipe->update_flags.bits.global_sync = 1; |
| 1356 | } |
| 1357 | |
| 1358 | if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb) |
| 1359 | new_pipe->update_flags.bits.det_size = 1; |
| 1360 | |
| 1361 | /* |
| 1362 | * Detect opp / tg change, only set on change, not on enable |
| 1363 | * Assume mpcc inst = pipe index, if not this code needs to be updated |
| 1364 | * since mpcc is what is affected by these. In fact all of our sequence |
| 1365 | * makes this assumption at the moment with how hubp reset is matched to |
| 1366 | * same index mpcc reset. |
| 1367 | */ |
| 1368 | if (old_pipe->stream_res.opp != new_pipe->stream_res.opp) |
| 1369 | new_pipe->update_flags.bits.opp_changed = 1; |
| 1370 | if (old_pipe->stream_res.tg != new_pipe->stream_res.tg) |
| 1371 | new_pipe->update_flags.bits.tg_changed = 1; |
| 1372 | |
| 1373 | /* |
| 1374 | * Detect mpcc blending changes, only dpp inst and opp matter here, |
| 1375 | * mpccs getting removed/inserted update connected ones during their own |
| 1376 | * programming |
| 1377 | */ |
| 1378 | if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp |
| 1379 | || old_pipe->stream_res.opp != new_pipe->stream_res.opp) |
| 1380 | new_pipe->update_flags.bits.mpcc = 1; |
| 1381 | |
| 1382 | /* Detect dppclk change */ |
| 1383 | if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) |
| 1384 | new_pipe->update_flags.bits.dppclk = 1; |
| 1385 | |
| 1386 | /* Check for scl update */ |
| 1387 | if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data))__builtin_memcmp((&old_pipe->plane_res.scl_data), (& new_pipe->plane_res.scl_data), (sizeof(struct scaler_data) ))) |
| 1388 | new_pipe->update_flags.bits.scaler = 1; |
| 1389 | /* Check for vp update */ |
| 1390 | if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))__builtin_memcmp((&old_pipe->plane_res.scl_data.viewport ), (&new_pipe->plane_res.scl_data.viewport), (sizeof(struct rect))) |
| 1391 | || memcmp(&old_pipe->plane_res.scl_data.viewport_c,__builtin_memcmp((&old_pipe->plane_res.scl_data.viewport_c ), (&new_pipe->plane_res.scl_data.viewport_c), (sizeof (struct rect))) |
| 1392 | &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))__builtin_memcmp((&old_pipe->plane_res.scl_data.viewport_c ), (&new_pipe->plane_res.scl_data.viewport_c), (sizeof (struct rect)))) |
| 1393 | new_pipe->update_flags.bits.viewport = 1; |
| 1394 | |
| 1395 | /* Detect dlg/ttu/rq updates */ |
| 1396 | { |
| 1397 | struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs; |
| 1398 | struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs; |
| 1399 | struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs; |
| 1400 | struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs; |
| 1401 | |
| 1402 | /* Detect pipe interdependent updates */ |
| 1403 | if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch || |
| 1404 | old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch || |
| 1405 | old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c || |
| 1406 | old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank || |
| 1407 | old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank || |
| 1408 | old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip || |
| 1409 | old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip || |
| 1410 | old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l || |
| 1411 | old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c || |
| 1412 | old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l || |
| 1413 | old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l || |
| 1414 | old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c || |
| 1415 | old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l || |
| 1416 | old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c || |
| 1417 | old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 || |
| 1418 | old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 || |
| 1419 | old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank || |
| 1420 | old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) { |
| 1421 | old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch; |
| 1422 | old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch; |
| 1423 | old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c; |
| 1424 | old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank; |
| 1425 | old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank; |
| 1426 | old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip; |
| 1427 | old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip; |
| 1428 | old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l; |
| 1429 | old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c; |
| 1430 | old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l; |
| 1431 | old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l; |
| 1432 | old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c; |
| 1433 | old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l; |
| 1434 | old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c; |
| 1435 | old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0; |
| 1436 | old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1; |
| 1437 | old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank; |
| 1438 | old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip; |
| 1439 | new_pipe->update_flags.bits.hubp_interdependent = 1; |
| 1440 | } |
| 1441 | /* Detect any other updates to ttu/rq/dlg */ |
| 1442 | if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr))__builtin_memcmp((&old_dlg_attr), (&new_pipe->dlg_regs ), (sizeof(old_dlg_attr))) || |
| 1443 | memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr))__builtin_memcmp((&old_ttu_attr), (&new_pipe->ttu_regs ), (sizeof(old_ttu_attr))) || |
| 1444 | memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs))__builtin_memcmp((&old_pipe->rq_regs), (&new_pipe-> rq_regs), (sizeof(old_pipe->rq_regs)))) |
| 1445 | new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1; |
| 1446 | } |
| 1447 | } |
| 1448 | |
| 1449 | static void dcn20_update_dchubp_dpp( |
| 1450 | struct dc *dc, |
| 1451 | struct pipe_ctx *pipe_ctx, |
| 1452 | struct dc_state *context) |
| 1453 | { |
| 1454 | struct dce_hwseq *hws = dc->hwseq; |
| 1455 | struct hubp *hubp = pipe_ctx->plane_res.hubp; |
| 1456 | struct dpp *dpp = pipe_ctx->plane_res.dpp; |
| 1457 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
| 1458 | struct dccg *dccg = dc->res_pool->dccg; |
| 1459 | bool_Bool viewport_changed = false0; |
| 1460 | |
| 1461 | if (pipe_ctx->update_flags.bits.dppclk) |
| 1462 | dpp->funcs->dpp_dppclk_control(dpp, false0, true1); |
| 1463 | |
| 1464 | if (pipe_ctx->update_flags.bits.enable) |
| 1465 | dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); |
| 1466 | |
| 1467 | /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG |
| 1468 | * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. |
| 1469 | * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG |
| 1470 | */ |
| 1471 | if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) { |
| 1472 | hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); |
| 1473 | |
| 1474 | hubp->funcs->hubp_setup( |
| 1475 | hubp, |
| 1476 | &pipe_ctx->dlg_regs, |
| 1477 | &pipe_ctx->ttu_regs, |
| 1478 | &pipe_ctx->rq_regs, |
| 1479 | &pipe_ctx->pipe_dlg_param); |
| 1480 | |
| 1481 | if (hubp->funcs->set_unbounded_requesting) |
| 1482 | hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req); |
| 1483 | } |
| 1484 | if (pipe_ctx->update_flags.bits.hubp_interdependent) |
| 1485 | hubp->funcs->hubp_setup_interdependent( |
| 1486 | hubp, |
| 1487 | &pipe_ctx->dlg_regs, |
| 1488 | &pipe_ctx->ttu_regs); |
| 1489 | |
| 1490 | if (pipe_ctx->update_flags.bits.enable || |
| 1491 | pipe_ctx->update_flags.bits.plane_changed || |
| 1492 | plane_state->update_flags.bits.bpp_change || |
| 1493 | plane_state->update_flags.bits.input_csc_change || |
| 1494 | plane_state->update_flags.bits.color_space_change || |
| 1495 | plane_state->update_flags.bits.coeff_reduction_change) { |
| 1496 | struct dc_bias_and_scale bns_params = {0}; |
| 1497 | |
| 1498 | // program the input csc |
| 1499 | dpp->funcs->dpp_setup(dpp, |
| 1500 | plane_state->format, |
| 1501 | EXPANSION_MODE_ZERO, |
| 1502 | plane_state->input_csc_color_matrix, |
| 1503 | plane_state->color_space, |
| 1504 | NULL((void *)0)); |
| 1505 | |
| 1506 | if (dpp->funcs->dpp_program_bias_and_scale) { |
| 1507 | //TODO :for CNVC set scale and bias registers if necessary |
| 1508 | build_prescale_params(&bns_params, plane_state); |
| 1509 | dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); |
| 1510 | } |
| 1511 | } |
| 1512 | |
| 1513 | if (pipe_ctx->update_flags.bits.mpcc |
| 1514 | || pipe_ctx->update_flags.bits.plane_changed |
| 1515 | || plane_state->update_flags.bits.global_alpha_change |
| 1516 | || plane_state->update_flags.bits.per_pixel_alpha_change) { |
| 1517 | // MPCC inst is equal to pipe index in practice |
| 1518 | hws->funcs.update_mpcc(dc, pipe_ctx); |
| 1519 | } |
| 1520 | |
| 1521 | if (pipe_ctx->update_flags.bits.scaler || |
| 1522 | plane_state->update_flags.bits.scaling_change || |
| 1523 | plane_state->update_flags.bits.position_change || |
| 1524 | plane_state->update_flags.bits.per_pixel_alpha_change || |
| 1525 | pipe_ctx->stream->update_flags.bits.scaling) { |
| 1526 | pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; |
| 1527 | ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP)do { if (({ static int __warned; int __ret = !!(!(pipe_ctx-> plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_36BPP)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 1527); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1528 | /* scaler configuration */ |
| 1529 | pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( |
| 1530 | pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); |
| 1531 | } |
| 1532 | |
| 1533 | if (pipe_ctx->update_flags.bits.viewport || |
| 1534 | (context == dc->current_state && plane_state->update_flags.bits.position_change) || |
| 1535 | (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || |
| 1536 | (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { |
| 1537 | |
| 1538 | hubp->funcs->mem_program_viewport( |
| 1539 | hubp, |
| 1540 | &pipe_ctx->plane_res.scl_data.viewport, |
| 1541 | &pipe_ctx->plane_res.scl_data.viewport_c); |
| 1542 | viewport_changed = true1; |
| 1543 | } |
| 1544 | |
| 1545 | /* Any updates are handled in dc interface, just need to apply existing for plane enable */ |
| 1546 | if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed || |
| 1547 | pipe_ctx->update_flags.bits.scaler || viewport_changed == true1) && |
| 1548 | pipe_ctx->stream->cursor_attributes.address.quad_part != 0) { |
| 1549 | dc->hwss.set_cursor_position(pipe_ctx); |
| 1550 | dc->hwss.set_cursor_attribute(pipe_ctx); |
| 1551 | |
| 1552 | if (dc->hwss.set_cursor_sdr_white_level) |
| 1553 | dc->hwss.set_cursor_sdr_white_level(pipe_ctx); |
| 1554 | } |
| 1555 | |
| 1556 | /* Any updates are handled in dc interface, just need |
| 1557 | * to apply existing for plane enable / opp change */ |
| 1558 | if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed |
| 1559 | || pipe_ctx->update_flags.bits.plane_changed |
| 1560 | || pipe_ctx->stream->update_flags.bits.gamut_remap |
| 1561 | || pipe_ctx->stream->update_flags.bits.out_csc) { |
| 1562 | /* dpp/cm gamut remap*/ |
| 1563 | dc->hwss.program_gamut_remap(pipe_ctx); |
| 1564 | |
| 1565 | /*call the dcn2 method which uses mpc csc*/ |
| 1566 | dc->hwss.program_output_csc(dc, |
| 1567 | pipe_ctx, |
| 1568 | pipe_ctx->stream->output_color_space, |
| 1569 | pipe_ctx->stream->csc_color_matrix.matrix, |
| 1570 | hubp->opp_id); |
| 1571 | } |
| 1572 | |
| 1573 | if (pipe_ctx->update_flags.bits.enable || |
| 1574 | pipe_ctx->update_flags.bits.plane_changed || |
| 1575 | pipe_ctx->update_flags.bits.opp_changed || |
| 1576 | plane_state->update_flags.bits.pixel_format_change || |
| 1577 | plane_state->update_flags.bits.horizontal_mirror_change || |
| 1578 | plane_state->update_flags.bits.rotation_change || |
| 1579 | plane_state->update_flags.bits.swizzle_change || |
| 1580 | plane_state->update_flags.bits.dcc_change || |
| 1581 | plane_state->update_flags.bits.bpp_change || |
| 1582 | plane_state->update_flags.bits.scaling_change || |
| 1583 | plane_state->update_flags.bits.plane_size_change) { |
| 1584 | struct plane_size size = plane_state->plane_size; |
| 1585 | |
| 1586 | size.surface_size = pipe_ctx->plane_res.scl_data.viewport; |
| 1587 | hubp->funcs->hubp_program_surface_config( |
| 1588 | hubp, |
| 1589 | plane_state->format, |
| 1590 | &plane_state->tiling_info, |
| 1591 | &size, |
| 1592 | plane_state->rotation, |
| 1593 | &plane_state->dcc, |
| 1594 | plane_state->horizontal_mirror, |
| 1595 | 0); |
| 1596 | hubp->power_gated = false0; |
| 1597 | } |
| 1598 | |
| 1599 | if (pipe_ctx->update_flags.bits.enable || |
| 1600 | pipe_ctx->update_flags.bits.plane_changed || |
| 1601 | plane_state->update_flags.bits.addr_update) |
| 1602 | hws->funcs.update_plane_addr(dc, pipe_ctx); |
| 1603 | |
| 1604 | if (pipe_ctx->update_flags.bits.enable) |
| 1605 | hubp->funcs->set_blank(hubp, false0); |
| 1606 | /* If the stream paired with this plane is phantom, the plane is also phantom */ |
| 1607 | if (pipe_ctx->stream && pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM |
| 1608 | && hubp->funcs->phantom_hubp_post_enable) |
| 1609 | hubp->funcs->phantom_hubp_post_enable(hubp); |
| 1610 | } |
| 1611 | |
| 1612 | static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) |
| 1613 | { |
| 1614 | struct pipe_ctx *other_pipe; |
| 1615 | int vready_offset = pipe->pipe_dlg_param.vready_offset; |
| 1616 | |
| 1617 | /* Always use the largest vready_offset of all connected pipes */ |
| 1618 | for (other_pipe = pipe->bottom_pipe; other_pipe != NULL((void *)0); other_pipe = other_pipe->bottom_pipe) { |
| 1619 | if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) |
| 1620 | vready_offset = other_pipe->pipe_dlg_param.vready_offset; |
| 1621 | } |
| 1622 | for (other_pipe = pipe->top_pipe; other_pipe != NULL((void *)0); other_pipe = other_pipe->top_pipe) { |
| 1623 | if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) |
| 1624 | vready_offset = other_pipe->pipe_dlg_param.vready_offset; |
| 1625 | } |
| 1626 | for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL((void *)0); other_pipe = other_pipe->next_odm_pipe) { |
| 1627 | if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) |
| 1628 | vready_offset = other_pipe->pipe_dlg_param.vready_offset; |
| 1629 | } |
| 1630 | for (other_pipe = pipe->prev_odm_pipe; other_pipe != NULL((void *)0); other_pipe = other_pipe->prev_odm_pipe) { |
| 1631 | if (other_pipe->pipe_dlg_param.vready_offset > vready_offset) |
| 1632 | vready_offset = other_pipe->pipe_dlg_param.vready_offset; |
| 1633 | } |
| 1634 | |
| 1635 | return vready_offset; |
| 1636 | } |
| 1637 | |
| 1638 | static void dcn20_program_pipe( |
| 1639 | struct dc *dc, |
| 1640 | struct pipe_ctx *pipe_ctx, |
| 1641 | struct dc_state *context) |
| 1642 | { |
| 1643 | struct dce_hwseq *hws = dc->hwseq; |
| 1644 | /* Only need to unblank on top pipe */ |
| 1645 | |
| 1646 | if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) |
| 1647 | && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) |
| 1648 | hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); |
| 1649 | |
| 1650 | /* Only update TG on top pipe */ |
| 1651 | if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe |
| 1652 | && !pipe_ctx->prev_odm_pipe) { |
| 1653 | pipe_ctx->stream_res.tg->funcs->program_global_sync( |
| 1654 | pipe_ctx->stream_res.tg, |
| 1655 | calculate_vready_offset_for_group(pipe_ctx), |
| 1656 | pipe_ctx->pipe_dlg_param.vstartup_start, |
| 1657 | pipe_ctx->pipe_dlg_param.vupdate_offset, |
| 1658 | pipe_ctx->pipe_dlg_param.vupdate_width); |
| 1659 | |
| 1660 | if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) { |
| 1661 | pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); |
| 1662 | pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); |
| 1663 | } |
| 1664 | |
| 1665 | pipe_ctx->stream_res.tg->funcs->set_vtg_params( |
| 1666 | pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, true1); |
| 1667 | |
| 1668 | if (hws->funcs.setup_vupdate_interrupt) |
| 1669 | hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); |
| 1670 | |
| 1671 | if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { |
| 1672 | unsigned int k1_div, k2_div; |
| 1673 | |
| 1674 | hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); |
| 1675 | |
| 1676 | dc->res_pool->dccg->funcs->set_pixel_rate_div( |
| 1677 | dc->res_pool->dccg, |
| 1678 | pipe_ctx->stream_res.tg->inst, |
| 1679 | k1_div, k2_div); |
| 1680 | } |
| 1681 | } |
| 1682 | |
| 1683 | if (pipe_ctx->update_flags.bits.odm) |
| 1684 | hws->funcs.update_odm(dc, context, pipe_ctx); |
| 1685 | |
| 1686 | if (pipe_ctx->update_flags.bits.enable) { |
| 1687 | dcn20_enable_plane(dc, pipe_ctx, context); |
| 1688 | if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes) |
| 1689 | dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); |
| 1690 | } |
| 1691 | |
| 1692 | if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size) |
| 1693 | dc->res_pool->hubbub->funcs->program_det_size( |
| 1694 | dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb); |
| 1695 | |
| 1696 | if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw) |
| 1697 | dcn20_update_dchubp_dpp(dc, pipe_ctx, context); |
| 1698 | |
| 1699 | if (pipe_ctx->update_flags.bits.enable |
| 1700 | || pipe_ctx->plane_state->update_flags.bits.hdr_mult) |
| 1701 | hws->funcs.set_hdr_multiplier(pipe_ctx); |
| 1702 | |
| 1703 | if (pipe_ctx->update_flags.bits.enable || |
| 1704 | pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || |
| 1705 | pipe_ctx->plane_state->update_flags.bits.gamma_change) |
| 1706 | hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); |
| 1707 | |
| 1708 | /* dcn10_translate_regamma_to_hw_format takes 750us to finish |
| 1709 | * only do gamma programming for powering on, internal memcmp to avoid |
| 1710 | * updating on slave planes |
| 1711 | */ |
| 1712 | if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf) |
| 1713 | hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); |
| 1714 | |
| 1715 | /* If the pipe has been enabled or has a different opp, we |
| 1716 | * should reprogram the fmt. This deals with cases where |
| 1717 | * interation between mpc and odm combine on different streams |
| 1718 | * causes a different pipe to be chosen to odm combine with. |
| 1719 | */ |
| 1720 | if (pipe_ctx->update_flags.bits.enable |
| 1721 | || pipe_ctx->update_flags.bits.opp_changed) { |
| 1722 | |
| 1723 | pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( |
| 1724 | pipe_ctx->stream_res.opp, |
| 1725 | COLOR_SPACE_YCBCR601, |
| 1726 | pipe_ctx->stream->timing.display_color_depth, |
| 1727 | pipe_ctx->stream->signal); |
| 1728 | |
| 1729 | pipe_ctx->stream_res.opp->funcs->opp_program_fmt( |
| 1730 | pipe_ctx->stream_res.opp, |
| 1731 | &pipe_ctx->stream->bit_depth_params, |
| 1732 | &pipe_ctx->stream->clamping); |
| 1733 | } |
| 1734 | } |
| 1735 | |
| 1736 | void dcn20_program_front_end_for_ctx( |
| 1737 | struct dc *dc, |
| 1738 | struct dc_state *context) |
| 1739 | { |
| 1740 | int i; |
| 1741 | struct dce_hwseq *hws = dc->hwseq; |
| 1742 | DC_LOGGER_INIT(dc->ctx->logger); |
| 1743 | |
| 1744 | /* Carry over GSL groups in case the context is changing. */ |
| 1745 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 1746 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
| 1747 | struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; |
| 1748 | |
| 1749 | if (pipe_ctx->stream == old_pipe_ctx->stream) |
| 1750 | pipe_ctx->stream_res.gsl_group = old_pipe_ctx->stream_res.gsl_group; |
| 1751 | } |
| 1752 | |
| 1753 | if (dc->hwss.program_triplebuffer != NULL((void *)0) && dc->debug.enable_tri_buf) { |
| 1754 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 1755 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
| 1756 | |
| 1757 | if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && pipe_ctx->plane_state) { |
| 1758 | ASSERT(!pipe_ctx->plane_state->triplebuffer_flips)do { if (({ static int __warned; int __ret = !!(!(!pipe_ctx-> plane_state->triplebuffer_flips)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(!pipe_ctx->plane_state->triplebuffer_flips)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 1758); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 1759 | /*turn off triple buffer for full update*/ |
| 1760 | dc->hwss.program_triplebuffer( |
| 1761 | dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); |
| 1762 | } |
| 1763 | } |
| 1764 | } |
| 1765 | |
| 1766 | /* Set pipe update flags and lock pipes */ |
| 1767 | for (i = 0; i < dc->res_pool->pipe_count; i++) |
| 1768 | dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i], |
| 1769 | &context->res_ctx.pipe_ctx[i]); |
| 1770 | |
| 1771 | /* OTG blank before disabling all front ends */ |
| 1772 | for (i = 0; i < dc->res_pool->pipe_count; i++) |
| 1773 | if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable |
| 1774 | && !context->res_ctx.pipe_ctx[i].top_pipe |
| 1775 | && !context->res_ctx.pipe_ctx[i].prev_odm_pipe |
| 1776 | && context->res_ctx.pipe_ctx[i].stream) |
| 1777 | hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true1); |
| 1778 | |
| 1779 | |
| 1780 | /* Disconnect mpcc */ |
| 1781 | for (i = 0; i < dc->res_pool->pipe_count; i++) |
| 1782 | if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable |
| 1783 | || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) { |
| 1784 | struct hubbub *hubbub = dc->res_pool->hubbub; |
| 1785 | |
| 1786 | /* Phantom pipe DET should be 0, but if a pipe in use is being transitioned to phantom |
| 1787 | * then we want to do the programming here (effectively it's being disabled). If we do |
| 1788 | * the programming later the DET won't be updated until the OTG for the phantom pipe is |
| 1789 | * turned on (i.e. in an MCLK switch) which can come in too late and cause issues with |
| 1790 | * DET allocation. |
| 1791 | */ |
| 1792 | if (hubbub->funcs->program_det_size && (context->res_ctx.pipe_ctx[i].update_flags.bits.disable || |
| 1793 | (context->res_ctx.pipe_ctx[i].plane_state && context->res_ctx.pipe_ctx[i].plane_state->is_phantom))) |
| 1794 | hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0); |
| 1795 | hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]); |
| 1796 | DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx)___drm_dbg(((void *)0), DRM_UT_KMS, "Reset mpcc for pipe %d\n" , dc->current_state->res_ctx.pipe_ctx[i].pipe_idx); |
| 1797 | } |
| 1798 | |
| 1799 | /* |
| 1800 | * Program all updated pipes, order matters for mpcc setup. Start with |
| 1801 | * top pipe and program all pipes that follow in order |
| 1802 | */ |
| 1803 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 1804 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
| 1805 | |
| 1806 | if (pipe->plane_state && !pipe->top_pipe) { |
| 1807 | while (pipe) { |
| 1808 | if (hws->funcs.program_pipe) |
| 1809 | hws->funcs.program_pipe(dc, pipe, context); |
| 1810 | else { |
| 1811 | /* Don't program phantom pipes in the regular front end programming sequence. |
| 1812 | * There is an MPO transition case where a pipe being used by a video plane is |
| 1813 | * transitioned directly to be a phantom pipe when closing the MPO video. However |
| 1814 | * the phantom pipe will program a new HUBP_VTG_SEL (update takes place right away), |
| 1815 | * but the MPO still exists until the double buffered update of the main pipe so we |
| 1816 | * will get a frame of underflow if the phantom pipe is programmed here. |
| 1817 | */ |
| 1818 | if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) |
| 1819 | dcn20_program_pipe(dc, pipe, context); |
| 1820 | } |
| 1821 | |
| 1822 | pipe = pipe->bottom_pipe; |
| 1823 | } |
| 1824 | } |
| 1825 | /* Program secondary blending tree and writeback pipes */ |
| 1826 | pipe = &context->res_ctx.pipe_ctx[i]; |
| 1827 | if (!pipe->top_pipe && !pipe->prev_odm_pipe |
| 1828 | && pipe->stream && pipe->stream->num_wb_info > 0 |
| 1829 | && (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw) |
| 1830 | || pipe->stream->update_flags.raw) |
| 1831 | && hws->funcs.program_all_writeback_pipes_in_tree) |
| 1832 | hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context); |
| 1833 | |
| 1834 | /* Avoid underflow by check of pipe line read when adding 2nd plane. */ |
| 1835 | if (hws->wa.wait_hubpret_read_start_during_mpo_transition && |
| 1836 | !pipe->top_pipe && |
| 1837 | pipe->stream && |
| 1838 | pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start && |
| 1839 | dc->current_state->stream_status[0].plane_count == 1 && |
| 1840 | context->stream_status[0].plane_count > 1) { |
| 1841 | pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp); |
| 1842 | } |
| 1843 | } |
| 1844 | } |
| 1845 | |
| 1846 | void dcn20_post_unlock_program_front_end( |
| 1847 | struct dc *dc, |
| 1848 | struct dc_state *context) |
| 1849 | { |
| 1850 | int i; |
| 1851 | const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100; |
| 1852 | struct dce_hwseq *hwseq = dc->hwseq; |
| 1853 | |
| 1854 | DC_LOGGER_INIT(dc->ctx->logger); |
| 1855 | |
| 1856 | for (i = 0; i < dc->res_pool->pipe_count; i++) |
| 1857 | if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable) |
| 1858 | dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); |
| 1859 | |
| 1860 | /* |
| 1861 | * If we are enabling a pipe, we need to wait for pending clear as this is a critical |
| 1862 | * part of the enable operation otherwise, DM may request an immediate flip which |
| 1863 | * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which |
| 1864 | * is unsupported on DCN. |
| 1865 | */ |
| 1866 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 1867 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
| 1868 | // Don't check flip pending on phantom pipes |
| 1869 | if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable && |
| 1870 | pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { |
| 1871 | struct hubp *hubp = pipe->plane_res.hubp; |
| 1872 | int j = 0; |
| 1873 | |
| 1874 | for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000 |
| 1875 | && hubp->funcs->hubp_is_flip_pending(hubp); j++) |
| 1876 | udelay(1); |
| 1877 | } |
| 1878 | } |
| 1879 | |
| 1880 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 1881 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
| 1882 | struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; |
| 1883 | |
| 1884 | /* If an active, non-phantom pipe is being transitioned into a phantom |
| 1885 | * pipe, wait for the double buffer update to complete first before we do |
| 1886 | * phantom pipe programming (HUBP_VTG_SEL updates right away so that can |
| 1887 | * cause issues). |
| 1888 | */ |
| 1889 | if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM && |
| 1890 | old_pipe->stream && old_pipe->stream->mall_stream_config.type != SUBVP_PHANTOM) { |
| 1891 | old_pipe->stream_res.tg->funcs->wait_for_state( |
| 1892 | old_pipe->stream_res.tg, |
| 1893 | CRTC_STATE_VBLANK); |
| 1894 | old_pipe->stream_res.tg->funcs->wait_for_state( |
| 1895 | old_pipe->stream_res.tg, |
| 1896 | CRTC_STATE_VACTIVE); |
| 1897 | } |
| 1898 | } |
| 1899 | |
| 1900 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 1901 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
| 1902 | |
| 1903 | if (pipe->plane_state && !pipe->top_pipe) { |
| 1904 | /* Program phantom pipe here to prevent a frame of underflow in the MPO transition |
| 1905 | * case (if a pipe being used for a video plane transitions to a phantom pipe, it |
| 1906 | * can underflow due to HUBP_VTG_SEL programming if done in the regular front end |
| 1907 | * programming sequence). |
| 1908 | */ |
| 1909 | while (pipe) { |
| 1910 | if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { |
| 1911 | if (dc->hwss.update_phantom_vp_position) |
| 1912 | dc->hwss.update_phantom_vp_position(dc, context, pipe); |
| 1913 | dcn20_program_pipe(dc, pipe, context); |
| 1914 | } |
| 1915 | pipe = pipe->bottom_pipe; |
| 1916 | } |
| 1917 | } |
| 1918 | } |
| 1919 | |
| 1920 | /* Only program the MALL registers after all the main and phantom pipes |
| 1921 | * are done programming. |
| 1922 | */ |
| 1923 | if (hwseq->funcs.program_mall_pipe_config) |
| 1924 | hwseq->funcs.program_mall_pipe_config(dc, context); |
| 1925 | |
| 1926 | /* WA to apply WM setting*/ |
| 1927 | if (hwseq->wa.DEGVIDCN21) |
| 1928 | dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); |
| 1929 | |
| 1930 | |
| 1931 | /* WA for stutter underflow during MPO transitions when adding 2nd plane */ |
| 1932 | if (hwseq->wa.disallow_self_refresh_during_multi_plane_transition) { |
| 1933 | |
| 1934 | if (dc->current_state->stream_status[0].plane_count == 1 && |
| 1935 | context->stream_status[0].plane_count > 1) { |
| 1936 | |
| 1937 | struct timing_generator *tg = dc->res_pool->timing_generators[0]; |
| 1938 | |
| 1939 | dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, false0); |
| 1940 | |
| 1941 | hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied = true1; |
| 1942 | hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame = tg->funcs->get_frame_count(tg); |
| 1943 | } |
| 1944 | } |
| 1945 | } |
| 1946 | |
| 1947 | void dcn20_prepare_bandwidth( |
| 1948 | struct dc *dc, |
| 1949 | struct dc_state *context) |
| 1950 | { |
| 1951 | struct hubbub *hubbub = dc->res_pool->hubbub; |
| 1952 | unsigned int compbuf_size_kb = 0; |
| 1953 | unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; |
| 1954 | unsigned int i; |
| 1955 | |
| 1956 | dc->clk_mgr->funcs->update_clocks( |
| 1957 | dc->clk_mgr, |
| 1958 | context, |
| 1959 | false0); |
| 1960 | |
| 1961 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 1962 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
| 1963 | |
| 1964 | // At optimize don't restore the original watermark value |
| 1965 | if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { |
| 1966 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; |
| 1967 | break; |
| 1968 | } |
| 1969 | } |
| 1970 | |
| 1971 | /* program dchubbub watermarks */ |
| 1972 | dc->wm_optimized_required = hubbub->funcs->program_watermarks(hubbub, |
| 1973 | &context->bw_ctx.bw.dcn.watermarks, |
| 1974 | dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, |
| 1975 | false0); |
| 1976 | |
| 1977 | // Restore the real watermark so we can commit the value to DMCUB |
| 1978 | // DMCUB uses the "original" watermark value in SubVP MCLK switch |
| 1979 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; |
| 1980 | |
| 1981 | /* decrease compbuf size */ |
| 1982 | if (hubbub->funcs->program_compbuf_size) { |
| 1983 | if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) |
| 1984 | compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; |
| 1985 | else |
| 1986 | compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; |
| 1987 | |
| 1988 | hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false0); |
| 1989 | } |
| 1990 | } |
| 1991 | |
| 1992 | void dcn20_optimize_bandwidth( |
| 1993 | struct dc *dc, |
| 1994 | struct dc_state *context) |
| 1995 | { |
| 1996 | struct hubbub *hubbub = dc->res_pool->hubbub; |
| 1997 | int i; |
| 1998 | |
| 1999 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 2000 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
| 2001 | |
| 2002 | // At optimize don't need to restore the original watermark value |
| 2003 | if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) { |
| 2004 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; |
| 2005 | break; |
| 2006 | } |
| 2007 | } |
| 2008 | |
| 2009 | /* program dchubbub watermarks */ |
| 2010 | hubbub->funcs->program_watermarks(hubbub, |
| 2011 | &context->bw_ctx.bw.dcn.watermarks, |
| 2012 | dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, |
| 2013 | true1); |
| 2014 | |
| 2015 | if (dc->clk_mgr->dc_mode_softmax_enabled) |
| 2016 | if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && |
| 2017 | context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) |
| 2018 | dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->dc_mode_softmax_memclk); |
| 2019 | |
| 2020 | /* increase compbuf size */ |
| 2021 | if (hubbub->funcs->program_compbuf_size) |
| 2022 | hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true1); |
| 2023 | |
| 2024 | dc->clk_mgr->funcs->update_clocks( |
| 2025 | dc->clk_mgr, |
| 2026 | context, |
| 2027 | true1); |
| 2028 | if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { |
| 2029 | for (i = 0; i < dc->res_pool->pipe_count; ++i) { |
| 2030 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
| 2031 | |
| 2032 | if (pipe_ctx->stream && pipe_ctx->plane_res.hubp->funcs->program_extended_blank |
| 2033 | && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max |
| 2034 | && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) |
| 2035 | pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, |
| 2036 | pipe_ctx->dlg_regs.min_dst_y_next_start); |
| 2037 | } |
| 2038 | } |
| 2039 | } |
| 2040 | |
| 2041 | bool_Bool dcn20_update_bandwidth( |
| 2042 | struct dc *dc, |
| 2043 | struct dc_state *context) |
| 2044 | { |
| 2045 | int i; |
| 2046 | struct dce_hwseq *hws = dc->hwseq; |
| 2047 | |
| 2048 | /* recalculate DML parameters */ |
| 2049 | if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false0)) |
| 2050 | return false0; |
| 2051 | |
| 2052 | /* apply updated bandwidth parameters */ |
| 2053 | dc->hwss.prepare_bandwidth(dc, context); |
| 2054 | |
| 2055 | /* update hubp configs for all pipes */ |
| 2056 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 2057 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
| 2058 | |
| 2059 | if (pipe_ctx->plane_state == NULL((void *)0)) |
| 2060 | continue; |
| 2061 | |
| 2062 | if (pipe_ctx->top_pipe == NULL((void *)0)) { |
| 2063 | bool_Bool blank = !is_pipe_tree_visible(pipe_ctx); |
| 2064 | |
| 2065 | pipe_ctx->stream_res.tg->funcs->program_global_sync( |
| 2066 | pipe_ctx->stream_res.tg, |
| 2067 | calculate_vready_offset_for_group(pipe_ctx), |
| 2068 | pipe_ctx->pipe_dlg_param.vstartup_start, |
| 2069 | pipe_ctx->pipe_dlg_param.vupdate_offset, |
| 2070 | pipe_ctx->pipe_dlg_param.vupdate_width); |
| 2071 | |
| 2072 | pipe_ctx->stream_res.tg->funcs->set_vtg_params( |
| 2073 | pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, false0); |
| 2074 | |
| 2075 | if (pipe_ctx->prev_odm_pipe == NULL((void *)0)) |
| 2076 | hws->funcs.blank_pixel_data(dc, pipe_ctx, blank); |
| 2077 | |
| 2078 | if (hws->funcs.setup_vupdate_interrupt) |
| 2079 | hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); |
| 2080 | } |
| 2081 | |
| 2082 | pipe_ctx->plane_res.hubp->funcs->hubp_setup( |
| 2083 | pipe_ctx->plane_res.hubp, |
| 2084 | &pipe_ctx->dlg_regs, |
| 2085 | &pipe_ctx->ttu_regs, |
| 2086 | &pipe_ctx->rq_regs, |
| 2087 | &pipe_ctx->pipe_dlg_param); |
| 2088 | } |
| 2089 | |
| 2090 | return true1; |
| 2091 | } |
| 2092 | |
| 2093 | void dcn20_enable_writeback( |
| 2094 | struct dc *dc, |
| 2095 | struct dc_writeback_info *wb_info, |
| 2096 | struct dc_state *context) |
| 2097 | { |
| 2098 | struct dwbc *dwb; |
| 2099 | struct mcif_wb *mcif_wb; |
| 2100 | struct timing_generator *optc; |
| 2101 | |
| 2102 | ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES)do { if (({ static int __warned; int __ret = !!(!(wb_info-> dwb_pipe_inst < 1)); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(wb_info->dwb_pipe_inst < 1)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 2102); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 2103 | ASSERT(wb_info->wb_enabled)do { if (({ static int __warned; int __ret = !!(!(wb_info-> wb_enabled)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(wb_info->wb_enabled)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 2103); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 2104 | dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; |
| 2105 | mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; |
| 2106 | |
| 2107 | /* set the OPTC source mux */ |
| 2108 | optc = dc->res_pool->timing_generators[dwb->otg_inst]; |
| 2109 | optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); |
| 2110 | /* set MCIF_WB buffer and arbitration configuration */ |
| 2111 | mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); |
| 2112 | mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); |
| 2113 | /* Enable MCIF_WB */ |
| 2114 | mcif_wb->funcs->enable_mcif(mcif_wb); |
| 2115 | /* Enable DWB */ |
| 2116 | dwb->funcs->enable(dwb, &wb_info->dwb_params); |
| 2117 | /* TODO: add sequence to enable/disable warmup */ |
| 2118 | } |
| 2119 | |
| 2120 | void dcn20_disable_writeback( |
| 2121 | struct dc *dc, |
| 2122 | unsigned int dwb_pipe_inst) |
| 2123 | { |
| 2124 | struct dwbc *dwb; |
| 2125 | struct mcif_wb *mcif_wb; |
| 2126 | |
| 2127 | ASSERT(dwb_pipe_inst < MAX_DWB_PIPES)do { if (({ static int __warned; int __ret = !!(!(dwb_pipe_inst < 1)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dwb_pipe_inst < 1)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 2127); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 2128 | dwb = dc->res_pool->dwbc[dwb_pipe_inst]; |
| 2129 | mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; |
| 2130 | |
| 2131 | dwb->funcs->disable(dwb); |
| 2132 | mcif_wb->funcs->disable_mcif(mcif_wb); |
| 2133 | } |
| 2134 | |
| 2135 | bool_Bool dcn20_wait_for_blank_complete( |
| 2136 | struct output_pixel_processor *opp) |
| 2137 | { |
| 2138 | int counter; |
| 2139 | |
| 2140 | for (counter = 0; counter < 1000; counter++) { |
| 2141 | if (opp->funcs->dpg_is_blanked(opp)) |
| 2142 | break; |
| 2143 | |
| 2144 | udelay(100); |
| 2145 | } |
| 2146 | |
| 2147 | if (counter == 1000) { |
| 2148 | dm_error("DC: failed to blank crtc!\n")__drm_err("DC: failed to blank crtc!\n"); |
| 2149 | return false0; |
| 2150 | } |
| 2151 | |
| 2152 | return true1; |
| 2153 | } |
| 2154 | |
| 2155 | bool_Bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) |
| 2156 | { |
| 2157 | struct hubp *hubp = pipe_ctx->plane_res.hubp; |
| 2158 | |
| 2159 | if (!hubp) |
| 2160 | return false0; |
| 2161 | return hubp->funcs->dmdata_status_done(hubp); |
| 2162 | } |
| 2163 | |
| 2164 | void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) |
| 2165 | { |
| 2166 | struct dce_hwseq *hws = dc->hwseq; |
| 2167 | |
| 2168 | if (pipe_ctx->stream_res.dsc) { |
| 2169 | struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; |
| 2170 | |
| 2171 | hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true1); |
| 2172 | while (odm_pipe) { |
| 2173 | hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true1); |
| 2174 | odm_pipe = odm_pipe->next_odm_pipe; |
| 2175 | } |
| 2176 | } |
| 2177 | } |
| 2178 | |
| 2179 | void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) |
| 2180 | { |
| 2181 | struct dce_hwseq *hws = dc->hwseq; |
| 2182 | |
| 2183 | if (pipe_ctx->stream_res.dsc) { |
| 2184 | struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; |
| 2185 | |
| 2186 | hws->funcs.dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false0); |
| 2187 | while (odm_pipe) { |
| 2188 | hws->funcs.dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false0); |
| 2189 | odm_pipe = odm_pipe->next_odm_pipe; |
| 2190 | } |
| 2191 | } |
| 2192 | } |
| 2193 | |
| 2194 | void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) |
| 2195 | { |
| 2196 | struct dc_dmdata_attributes attr = { 0 }; |
| 2197 | struct hubp *hubp = pipe_ctx->plane_res.hubp; |
| 2198 | |
| 2199 | attr.dmdata_mode = DMDATA_HW_MODE; |
| 2200 | attr.dmdata_size = |
| 2201 | dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36; |
| 2202 | attr.address.quad_part = |
| 2203 | pipe_ctx->stream->dmdata_address.quad_part; |
| 2204 | attr.dmdata_dl_delta = 0; |
| 2205 | attr.dmdata_qos_mode = 0; |
| 2206 | attr.dmdata_qos_level = 0; |
| 2207 | attr.dmdata_repeat = 1; /* always repeat */ |
| 2208 | attr.dmdata_updated = 1; |
| 2209 | attr.dmdata_sw_data = NULL((void *)0); |
| 2210 | |
| 2211 | hubp->funcs->dmdata_set_attributes(hubp, &attr); |
| 2212 | } |
| 2213 | |
| 2214 | void dcn20_init_vm_ctx( |
| 2215 | struct dce_hwseq *hws, |
| 2216 | struct dc *dc, |
| 2217 | struct dc_virtual_addr_space_config *va_config, |
| 2218 | int vmid) |
| 2219 | { |
| 2220 | struct dcn_hubbub_virt_addr_config config; |
| 2221 | |
| 2222 | if (vmid == 0) { |
| 2223 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 2223); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* VMID cannot be 0 for vm context */ |
| 2224 | return; |
| 2225 | } |
| 2226 | |
| 2227 | config.page_table_start_addr = va_config->page_table_start_addr; |
| 2228 | config.page_table_end_addr = va_config->page_table_end_addr; |
| 2229 | config.page_table_block_size = va_config->page_table_block_size_in_bytes; |
| 2230 | config.page_table_depth = va_config->page_table_depth; |
| 2231 | config.page_table_base_addr = va_config->page_table_base_addr; |
| 2232 | |
| 2233 | dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); |
| 2234 | } |
| 2235 | |
| 2236 | int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) |
| 2237 | { |
| 2238 | struct dcn_hubbub_phys_addr_config config; |
| 2239 | |
| 2240 | config.system_aperture.fb_top = pa_config->system_aperture.fb_top; |
| 2241 | config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; |
| 2242 | config.system_aperture.fb_base = pa_config->system_aperture.fb_base; |
| 2243 | config.system_aperture.agp_top = pa_config->system_aperture.agp_top; |
| 2244 | config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; |
| 2245 | config.system_aperture.agp_base = pa_config->system_aperture.agp_base; |
| 2246 | config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; |
| 2247 | config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; |
| 2248 | config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; |
| 2249 | config.page_table_default_page_addr = pa_config->page_table_default_page_addr; |
| 2250 | |
| 2251 | return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); |
| 2252 | } |
| 2253 | |
| 2254 | static bool_Bool patch_address_for_sbs_tb_stereo( |
| 2255 | struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOCunion large_integer *addr) |
| 2256 | { |
| 2257 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
| 2258 | bool_Bool sec_split = pipe_ctx->top_pipe && |
| 2259 | pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; |
| 2260 | if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && |
| 2261 | (pipe_ctx->stream->timing.timing_3d_format == |
| 2262 | TIMING_3D_FORMAT_SIDE_BY_SIDE || |
| 2263 | pipe_ctx->stream->timing.timing_3d_format == |
| 2264 | TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { |
| 2265 | *addr = plane_state->address.grph_stereo.left_addr; |
| 2266 | plane_state->address.grph_stereo.left_addr = |
| 2267 | plane_state->address.grph_stereo.right_addr; |
| 2268 | return true1; |
| 2269 | } |
| 2270 | |
| 2271 | if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && |
| 2272 | plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { |
| 2273 | plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; |
| 2274 | plane_state->address.grph_stereo.right_addr = |
| 2275 | plane_state->address.grph_stereo.left_addr; |
| 2276 | plane_state->address.grph_stereo.right_meta_addr = |
| 2277 | plane_state->address.grph_stereo.left_meta_addr; |
| 2278 | } |
| 2279 | return false0; |
| 2280 | } |
| 2281 | |
| 2282 | void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) |
| 2283 | { |
| 2284 | bool_Bool addr_patched = false0; |
| 2285 | PHYSICAL_ADDRESS_LOCunion large_integer addr; |
| 2286 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
| 2287 | |
| 2288 | if (plane_state == NULL((void *)0)) |
| 2289 | return; |
| 2290 | |
| 2291 | addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); |
| 2292 | |
| 2293 | // Call Helper to track VMID use |
| 2294 | vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst); |
| 2295 | |
| 2296 | pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( |
| 2297 | pipe_ctx->plane_res.hubp, |
| 2298 | &plane_state->address, |
| 2299 | plane_state->flip_immediate); |
| 2300 | |
| 2301 | plane_state->status.requested_address = plane_state->address; |
| 2302 | |
| 2303 | if (plane_state->flip_immediate) |
| 2304 | plane_state->status.current_address = plane_state->address; |
| 2305 | |
| 2306 | if (addr_patched) |
| 2307 | pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; |
| 2308 | } |
| 2309 | |
| 2310 | void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx, |
| 2311 | struct dc_link_settings *link_settings) |
| 2312 | { |
| 2313 | struct encoder_unblank_param params = {0}; |
| 2314 | struct dc_stream_state *stream = pipe_ctx->stream; |
| 2315 | struct dc_link *link = stream->link; |
| 2316 | struct dce_hwseq *hws = link->dc->hwseq; |
| 2317 | struct pipe_ctx *odm_pipe; |
| 2318 | |
| 2319 | params.opp_cnt = 1; |
| 2320 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { |
| 2321 | params.opp_cnt++; |
| 2322 | } |
| 2323 | /* only 3 items below are used by unblank */ |
| 2324 | params.timing = pipe_ctx->stream->timing; |
| 2325 | |
| 2326 | params.link_settings.link_rate = link_settings->link_rate; |
| 2327 | |
| 2328 | if (is_dp_128b_132b_signal(pipe_ctx)) { |
| 2329 | /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ |
| 2330 | pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_unblank( |
| 2331 | pipe_ctx->stream_res.hpo_dp_stream_enc, |
| 2332 | pipe_ctx->stream_res.tg->inst); |
| 2333 | } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { |
| 2334 | if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1) |
| 2335 | params.timing.pix_clk_100hz /= 2; |
| 2336 | pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine( |
| 2337 | pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1); |
| 2338 | pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); |
| 2339 | } |
| 2340 | |
| 2341 | if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { |
| 2342 | hws->funcs.edp_backlight_control(link, true1); |
| 2343 | } |
| 2344 | } |
| 2345 | |
| 2346 | void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) |
| 2347 | { |
| 2348 | struct timing_generator *tg = pipe_ctx->stream_res.tg; |
| 2349 | int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx); |
| 2350 | |
| 2351 | if (start_line < 0) |
| 2352 | start_line = 0; |
| 2353 | |
| 2354 | if (tg->funcs->setup_vertical_interrupt2) |
| 2355 | tg->funcs->setup_vertical_interrupt2(tg, start_line); |
| 2356 | } |
| 2357 | |
| 2358 | static void dcn20_reset_back_end_for_pipe( |
| 2359 | struct dc *dc, |
| 2360 | struct pipe_ctx *pipe_ctx, |
| 2361 | struct dc_state *context) |
| 2362 | { |
| 2363 | int i; |
| 2364 | struct dc_link *link = pipe_ctx->stream->link; |
| 2365 | const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); |
| 2366 | |
| 2367 | DC_LOGGER_INIT(dc->ctx->logger); |
| 2368 | if (pipe_ctx->stream_res.stream_enc == NULL((void *)0)) { |
| 2369 | pipe_ctx->stream = NULL((void *)0); |
| 2370 | return; |
| 2371 | } |
| 2372 | |
| 2373 | if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) { |
| 2374 | /* DPMS may already disable or */ |
| 2375 | /* dpms_off status is incorrect due to fastboot |
| 2376 | * feature. When system resume from S4 with second |
| 2377 | * screen only, the dpms_off would be true but |
| 2378 | * VBIOS lit up eDP, so check link status too. |
| 2379 | */ |
| 2380 | if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) |
| 2381 | core_link_disable_stream(pipe_ctx); |
| 2382 | else if (pipe_ctx->stream_res.audio) |
| 2383 | dc->hwss.disable_audio_stream(pipe_ctx); |
| 2384 | |
| 2385 | /* free acquired resources */ |
| 2386 | if (pipe_ctx->stream_res.audio) { |
| 2387 | /*disable az_endpoint*/ |
| 2388 | pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); |
| 2389 | |
| 2390 | /*free audio*/ |
| 2391 | if (dc->caps.dynamic_audio == true1) { |
| 2392 | /*we have to dynamic arbitrate the audio endpoints*/ |
| 2393 | /*we free the resource, need reset is_audio_acquired*/ |
| 2394 | update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, |
| 2395 | pipe_ctx->stream_res.audio, false0); |
| 2396 | pipe_ctx->stream_res.audio = NULL((void *)0); |
| 2397 | } |
| 2398 | } |
| 2399 | } |
| 2400 | else if (pipe_ctx->stream_res.dsc) { |
| 2401 | dp_set_dsc_enable(pipe_ctx, false0); |
| 2402 | } |
| 2403 | |
| 2404 | /* by upper caller loop, parent pipe: pipe0, will be reset last. |
| 2405 | * back end share by all pipes and will be disable only when disable |
| 2406 | * parent pipe. |
| 2407 | */ |
| 2408 | if (pipe_ctx->top_pipe == NULL((void *)0)) { |
| 2409 | |
| 2410 | dc->hwss.set_abm_immediate_disable(pipe_ctx); |
| 2411 | |
| 2412 | pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); |
| 2413 | |
| 2414 | pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false0); |
| 2415 | if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) |
| 2416 | pipe_ctx->stream_res.tg->funcs->set_odm_bypass( |
| 2417 | pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); |
| 2418 | |
| 2419 | if (pipe_ctx->stream_res.tg->funcs->set_drr) |
| 2420 | pipe_ctx->stream_res.tg->funcs->set_drr( |
| 2421 | pipe_ctx->stream_res.tg, NULL((void *)0)); |
| 2422 | /* TODO - convert symclk_ref_cnts for otg to a bit map to solve |
| 2423 | * the case where the same symclk is shared across multiple otg |
| 2424 | * instances |
| 2425 | */ |
| 2426 | link->phy_state.symclk_ref_cnts.otg = 0; |
| 2427 | if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { |
| 2428 | link_hwss->disable_link_output(link, |
| 2429 | &pipe_ctx->link_res, pipe_ctx->stream->signal); |
| 2430 | link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; |
| 2431 | } |
| 2432 | } |
| 2433 | |
| 2434 | for (i = 0; i < dc->res_pool->pipe_count; i++) |
| 2435 | if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) |
| 2436 | break; |
| 2437 | |
| 2438 | if (i == dc->res_pool->pipe_count) |
| 2439 | return; |
| 2440 | |
| 2441 | pipe_ctx->stream = NULL((void *)0); |
| 2442 | DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Reset back end for pipe %d, tg:%d\n" , pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst) |
| 2443 | pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst)___drm_dbg(((void *)0), DRM_UT_KMS, "Reset back end for pipe %d, tg:%d\n" , pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); |
| 2444 | } |
| 2445 | |
| 2446 | void dcn20_reset_hw_ctx_wrap( |
| 2447 | struct dc *dc, |
| 2448 | struct dc_state *context) |
| 2449 | { |
| 2450 | int i; |
| 2451 | struct dce_hwseq *hws = dc->hwseq; |
| 2452 | |
| 2453 | /* Reset Back End*/ |
| 2454 | for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { |
| 2455 | struct pipe_ctx *pipe_ctx_old = |
| 2456 | &dc->current_state->res_ctx.pipe_ctx[i]; |
| 2457 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
| 2458 | |
| 2459 | if (!pipe_ctx_old->stream) |
| 2460 | continue; |
| 2461 | |
| 2462 | if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) |
| 2463 | continue; |
| 2464 | |
| 2465 | if (!pipe_ctx->stream || |
| 2466 | pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { |
| 2467 | struct clock_source *old_clk = pipe_ctx_old->clock_source; |
| 2468 | |
| 2469 | dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); |
| 2470 | if (hws->funcs.enable_stream_gating) |
| 2471 | hws->funcs.enable_stream_gating(dc, pipe_ctx_old); |
| 2472 | if (old_clk) |
| 2473 | old_clk->funcs->cs_power_down(old_clk); |
| 2474 | } |
| 2475 | } |
| 2476 | } |
| 2477 | |
| 2478 | void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id) |
| 2479 | { |
| 2480 | struct mpc *mpc = dc->res_pool->mpc; |
| 2481 | |
| 2482 | // input to MPCC is always RGB, by default leave black_color at 0 |
| 2483 | if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) |
| 2484 | get_hdr_visual_confirm_color(pipe_ctx, color); |
| 2485 | else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) |
| 2486 | get_surface_visual_confirm_color(pipe_ctx, color); |
| 2487 | else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) |
| 2488 | get_mpctree_visual_confirm_color(pipe_ctx, color); |
| 2489 | else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) |
| 2490 | get_surface_tile_visual_confirm_color(pipe_ctx, color); |
| 2491 | else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP) |
| 2492 | get_subvp_visual_confirm_color(dc, pipe_ctx, color); |
| 2493 | |
| 2494 | if (mpc->funcs->set_bg_color) { |
| 2495 | memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color))__builtin_memcpy((&pipe_ctx->plane_state->visual_confirm_color ), (color), (sizeof(struct tg_color))); |
| 2496 | mpc->funcs->set_bg_color(mpc, color, mpcc_id); |
| 2497 | } |
| 2498 | } |
| 2499 | |
| 2500 | void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) |
| 2501 | { |
| 2502 | struct hubp *hubp = pipe_ctx->plane_res.hubp; |
| 2503 | struct mpcc_blnd_cfg blnd_cfg = {0}; |
| 2504 | bool_Bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; |
| 2505 | int mpcc_id; |
| 2506 | struct mpcc *new_mpcc; |
| 2507 | struct mpc *mpc = dc->res_pool->mpc; |
| 2508 | struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); |
| 2509 | |
| 2510 | blnd_cfg.overlap_only = false0; |
| 2511 | blnd_cfg.global_gain = 0xff; |
| 2512 | |
| 2513 | if (per_pixel_alpha) { |
| 2514 | blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; |
| 2515 | if (pipe_ctx->plane_state->global_alpha) { |
| 2516 | blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; |
| 2517 | blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; |
| 2518 | } else { |
| 2519 | blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; |
| 2520 | } |
| 2521 | } else { |
| 2522 | blnd_cfg.pre_multiplied_alpha = false0; |
| 2523 | blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; |
| 2524 | } |
| 2525 | |
| 2526 | if (pipe_ctx->plane_state->global_alpha) |
| 2527 | blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; |
| 2528 | else |
| 2529 | blnd_cfg.global_alpha = 0xff; |
| 2530 | |
| 2531 | blnd_cfg.background_color_bpc = 4; |
| 2532 | blnd_cfg.bottom_gain_mode = 0; |
| 2533 | blnd_cfg.top_gain = 0x1f000; |
| 2534 | blnd_cfg.bottom_inside_gain = 0x1f000; |
| 2535 | blnd_cfg.bottom_outside_gain = 0x1f000; |
| 2536 | |
| 2537 | if (pipe_ctx->plane_state->format |
| 2538 | == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) |
| 2539 | blnd_cfg.pre_multiplied_alpha = false0; |
| 2540 | |
| 2541 | /* |
| 2542 | * TODO: remove hack |
| 2543 | * Note: currently there is a bug in init_hw such that |
| 2544 | * on resume from hibernate, BIOS sets up MPCC0, and |
| 2545 | * we do mpcc_remove but the mpcc cannot go to idle |
| 2546 | * after remove. This cause us to pick mpcc1 here, |
| 2547 | * which causes a pstate hang for yet unknown reason. |
| 2548 | */ |
| 2549 | mpcc_id = hubp->inst; |
| 2550 | |
| 2551 | /* If there is no full update, don't need to touch MPC tree*/ |
| 2552 | if (!pipe_ctx->plane_state->update_flags.bits.full_update && |
| 2553 | !pipe_ctx->update_flags.bits.mpcc) { |
| 2554 | mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); |
| 2555 | dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); |
| 2556 | return; |
| 2557 | } |
| 2558 | |
| 2559 | /* check if this MPCC is already being used */ |
| 2560 | new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); |
| 2561 | /* remove MPCC if being used */ |
| 2562 | if (new_mpcc != NULL((void *)0)) |
| 2563 | mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); |
| 2564 | else |
| 2565 | if (dc->debug.sanity_checks) |
| 2566 | mpc->funcs->assert_mpcc_idle_before_connect( |
| 2567 | dc->res_pool->mpc, mpcc_id); |
| 2568 | |
| 2569 | /* Call MPC to insert new plane */ |
| 2570 | new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, |
| 2571 | mpc_tree_params, |
| 2572 | &blnd_cfg, |
| 2573 | NULL((void *)0), |
| 2574 | NULL((void *)0), |
| 2575 | hubp->inst, |
| 2576 | mpcc_id); |
| 2577 | dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id); |
| 2578 | |
| 2579 | ASSERT(new_mpcc != NULL)do { if (({ static int __warned; int __ret = !!(!(new_mpcc != ((void *)0))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(new_mpcc != ((void *)0))", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c" , 2579); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 2580 | hubp->opp_id = pipe_ctx->stream_res.opp->inst; |
| 2581 | hubp->mpcc_id = mpcc_id; |
| 2582 | } |
| 2583 | |
| 2584 | void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) |
| 2585 | { |
| 2586 | enum dc_lane_count lane_count = |
| 2587 | pipe_ctx->stream->link->cur_link_settings.lane_count; |
| 2588 | |
| 2589 | struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; |
| 2590 | struct dc_link *link = pipe_ctx->stream->link; |
| 2591 | |
| 2592 | uint32_t active_total_with_borders; |
| 2593 | uint32_t early_control = 0; |
| 2594 | struct timing_generator *tg = pipe_ctx->stream_res.tg; |
| 2595 | const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); |
| 2596 | struct dc *dc = pipe_ctx->stream->ctx->dc; |
| 2597 | |
| 2598 | if (is_dp_128b_132b_signal(pipe_ctx)) { |
| 2599 | if (dc->hwseq->funcs.setup_hpo_hw_control) |
| 2600 | dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, true1); |
| 2601 | } |
| 2602 | |
| 2603 | link_hwss->setup_stream_encoder(pipe_ctx); |
| 2604 | |
| 2605 | if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) { |
| 2606 | if (dc->hwss.program_dmdata_engine) |
| 2607 | dc->hwss.program_dmdata_engine(pipe_ctx); |
| 2608 | } |
| 2609 | |
| 2610 | dc->hwss.update_info_frame(pipe_ctx); |
| 2611 | |
| 2612 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) |
| 2613 | dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); |
| 2614 | |
| 2615 | /* enable early control to avoid corruption on DP monitor*/ |
| 2616 | active_total_with_borders = |
| 2617 | timing->h_addressable |
| 2618 | + timing->h_border_left |
| 2619 | + timing->h_border_right; |
| 2620 | |
| 2621 | if (lane_count != 0) |
| 2622 | early_control = active_total_with_borders % lane_count; |
| 2623 | |
| 2624 | if (early_control == 0) |
| 2625 | early_control = lane_count; |
| 2626 | |
| 2627 | tg->funcs->set_early_control(tg, early_control); |
| 2628 | |
| 2629 | if (dc->hwseq->funcs.set_pixels_per_cycle) |
| 2630 | dc->hwseq->funcs.set_pixels_per_cycle(pipe_ctx); |
| 2631 | |
| 2632 | /* enable audio only within mode set */ |
| 2633 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { |
| 2634 | if (is_dp_128b_132b_signal(pipe_ctx)) |
| 2635 | pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.hpo_dp_stream_enc); |
| 2636 | else if (dc_is_dp_signal(pipe_ctx->stream->signal)) |
| 2637 | pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); |
| 2638 | } |
| 2639 | } |
| 2640 | |
| 2641 | void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx) |
| 2642 | { |
| 2643 | struct dc_stream_state *stream = pipe_ctx->stream; |
| 2644 | struct hubp *hubp = pipe_ctx->plane_res.hubp; |
| 2645 | bool_Bool enable = false0; |
| 2646 | struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; |
| 2647 | enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) |
| 2648 | ? dmdata_dp |
| 2649 | : dmdata_hdmi; |
| 2650 | |
| 2651 | /* if using dynamic meta, don't set up generic infopackets */ |
| 2652 | if (pipe_ctx->stream->dmdata_address.quad_part != 0) { |
| 2653 | pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false0; |
| 2654 | enable = true1; |
| 2655 | } |
| 2656 | |
| 2657 | if (!hubp) |
| 2658 | return; |
| 2659 | |
| 2660 | if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) |
| 2661 | return; |
| 2662 | |
| 2663 | stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, |
| 2664 | hubp->inst, mode); |
| 2665 | } |
| 2666 | |
| 2667 | void dcn20_fpga_init_hw(struct dc *dc) |
| 2668 | { |
| 2669 | int i, j; |
| 2670 | struct dce_hwseq *hws = dc->hwseq; |
| 2671 | struct resource_pool *res_pool = dc->res_pool; |
| 2672 | struct dc_state *context = dc->current_state; |
| 2673 | |
| 2674 | if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) |
| 2675 | dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); |
| 2676 | |
| 2677 | // Initialize the dccg |
| 2678 | if (res_pool->dccg->funcs->dccg_init) |
| 2679 | res_pool->dccg->funcs->dccg_init(res_pool->dccg); |
| 2680 | |
| 2681 | //Enable ability to power gate / don't force power on permanently |
| 2682 | hws->funcs.enable_power_gating_plane(hws, true1); |
| 2683 | |
| 2684 | // Specific to FPGA dccg and registers |
| 2685 | REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF)dm_write_reg_func(hws->ctx, hws->regs->RBBMIF_TIMEOUT_DIS , 0xFFFFFFFF, __func__); |
| 2686 | REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF)dm_write_reg_func(hws->ctx, hws->regs->RBBMIF_TIMEOUT_DIS_2 , 0xFFFFFFFF, __func__); |
| 2687 | |
| 2688 | hws->funcs.dccg_init(hws); |
| 2689 | |
| 2690 | REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2)generic_reg_update_ex(hws->ctx, hws->regs->DCHUBBUB_GLOBAL_TIMER_CNTL , 1, hws->shifts->DCHUBBUB_GLOBAL_TIMER_REFDIV, hws-> masks->DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); |
| 2691 | REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1)generic_reg_update_ex(hws->ctx, hws->regs->DCHUBBUB_GLOBAL_TIMER_CNTL , 1, hws->shifts->DCHUBBUB_GLOBAL_TIMER_ENABLE, hws-> masks->DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); |
| 2692 | if (REG(REFCLK_CNTL)hws->regs->REFCLK_CNTL) |
| 2693 | REG_WRITE(REFCLK_CNTL, 0)dm_write_reg_func(hws->ctx, hws->regs->REFCLK_CNTL, 0 , __func__); |
| 2694 | // |
| 2695 | |
| 2696 | |
| 2697 | /* Blank pixel data with OPP DPG */ |
| 2698 | for (i = 0; i < dc->res_pool->timing_generator_count; i++) { |
| 2699 | struct timing_generator *tg = dc->res_pool->timing_generators[i]; |
| 2700 | |
| 2701 | if (tg->funcs->is_tg_enabled(tg)) |
| 2702 | dcn20_init_blank(dc, tg); |
| 2703 | } |
| 2704 | |
| 2705 | for (i = 0; i < res_pool->timing_generator_count; i++) { |
| 2706 | struct timing_generator *tg = dc->res_pool->timing_generators[i]; |
| 2707 | |
| 2708 | if (tg->funcs->is_tg_enabled(tg)) |
| 2709 | tg->funcs->lock(tg); |
| 2710 | } |
| 2711 | |
| 2712 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 2713 | struct dpp *dpp = res_pool->dpps[i]; |
| 2714 | |
| 2715 | dpp->funcs->dpp_reset(dpp); |
| 2716 | } |
| 2717 | |
| 2718 | /* Reset all MPCC muxes */ |
| 2719 | res_pool->mpc->funcs->mpc_init(res_pool->mpc); |
| 2720 | |
| 2721 | /* initialize OPP mpc_tree parameter */ |
| 2722 | for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { |
| 2723 | res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; |
| 2724 | res_pool->opps[i]->mpc_tree_params.opp_list = NULL((void *)0); |
| 2725 | for (j = 0; j < MAX_PIPES6; j++) |
| 2726 | res_pool->opps[i]->mpcc_disconnect_pending[j] = false0; |
| 2727 | } |
| 2728 | |
| 2729 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 2730 | struct timing_generator *tg = dc->res_pool->timing_generators[i]; |
| 2731 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
| 2732 | struct hubp *hubp = dc->res_pool->hubps[i]; |
| 2733 | struct dpp *dpp = dc->res_pool->dpps[i]; |
| 2734 | |
| 2735 | pipe_ctx->stream_res.tg = tg; |
| 2736 | pipe_ctx->pipe_idx = i; |
| 2737 | |
| 2738 | pipe_ctx->plane_res.hubp = hubp; |
| 2739 | pipe_ctx->plane_res.dpp = dpp; |
| 2740 | pipe_ctx->plane_res.mpcc_inst = dpp->inst; |
| 2741 | hubp->mpcc_id = dpp->inst; |
| 2742 | hubp->opp_id = OPP_ID_INVALID0xf; |
| 2743 | hubp->power_gated = false0; |
| 2744 | pipe_ctx->stream_res.opp = NULL((void *)0); |
| 2745 | |
| 2746 | hubp->funcs->hubp_init(hubp); |
| 2747 | |
| 2748 | //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; |
| 2749 | //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL; |
| 2750 | dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true1; |
| 2751 | pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; |
| 2752 | /*to do*/ |
| 2753 | hws->funcs.plane_atomic_disconnect(dc, pipe_ctx); |
| 2754 | } |
| 2755 | |
| 2756 | /* initialize DWB pointer to MCIF_WB */ |
| 2757 | for (i = 0; i < res_pool->res_cap->num_dwb; i++) |
| 2758 | res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; |
| 2759 | |
| 2760 | for (i = 0; i < dc->res_pool->timing_generator_count; i++) { |
| 2761 | struct timing_generator *tg = dc->res_pool->timing_generators[i]; |
| 2762 | |
| 2763 | if (tg->funcs->is_tg_enabled(tg)) |
| 2764 | tg->funcs->unlock(tg); |
| 2765 | } |
| 2766 | |
| 2767 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
| 2768 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
| 2769 | |
| 2770 | dc->hwss.disable_plane(dc, pipe_ctx); |
| 2771 | |
| 2772 | pipe_ctx->stream_res.tg = NULL((void *)0); |
| 2773 | pipe_ctx->plane_res.hubp = NULL((void *)0); |
| 2774 | } |
| 2775 | |
| 2776 | for (i = 0; i < dc->res_pool->timing_generator_count; i++) { |
| 2777 | struct timing_generator *tg = dc->res_pool->timing_generators[i]; |
| 2778 | |
| 2779 | tg->funcs->tg_init(tg); |
| 2780 | } |
| 2781 | |
| 2782 | if (dc->res_pool->hubbub->funcs->init_crb) |
| 2783 | dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); |
| 2784 | } |
| 2785 | #ifndef TRIM_FSFT |
| 2786 | bool_Bool dcn20_optimize_timing_for_fsft(struct dc *dc, |
| 2787 | struct dc_crtc_timing *timing, |
| 2788 | unsigned int max_input_rate_in_khz) |
| 2789 | { |
| 2790 | unsigned int old_v_front_porch; |
| 2791 | unsigned int old_v_total; |
| 2792 | unsigned int max_input_rate_in_100hz; |
| 2793 | unsigned long long new_v_total; |
| 2794 | |
| 2795 | max_input_rate_in_100hz = max_input_rate_in_khz * 10; |
| 2796 | if (max_input_rate_in_100hz < timing->pix_clk_100hz) |
| 2797 | return false0; |
| 2798 | |
| 2799 | old_v_total = timing->v_total; |
| 2800 | old_v_front_porch = timing->v_front_porch; |
| 2801 | |
| 2802 | timing->fast_transport_output_rate_100hz = timing->pix_clk_100hz; |
| 2803 | timing->pix_clk_100hz = max_input_rate_in_100hz; |
| 2804 | |
| 2805 | new_v_total = div_u64((unsigned long long)old_v_total * max_input_rate_in_100hz, timing->pix_clk_100hz); |
| 2806 | |
| 2807 | timing->v_total = new_v_total; |
| 2808 | timing->v_front_porch = old_v_front_porch + (timing->v_total - old_v_total); |
| 2809 | return true1; |
| 2810 | } |
| 2811 | #endif |
| 2812 | |
| 2813 | void dcn20_set_disp_pattern_generator(const struct dc *dc, |
| 2814 | struct pipe_ctx *pipe_ctx, |
| 2815 | enum controller_dp_test_pattern test_pattern, |
| 2816 | enum controller_dp_color_space color_space, |
| 2817 | enum dc_color_depth color_depth, |
| 2818 | const struct tg_color *solid_color, |
| 2819 | int width, int height, int offset) |
| 2820 | { |
| 2821 | pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, |
| 2822 | color_space, color_depth, solid_color, width, height, offset); |
| 2823 | } |