Bug Summary

File:dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
Warning:line 1113, column 24
Value stored to 'adev' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name yellow_carp_ppt.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#define SWSMU_CODE_LAYER_L2
25
26#include "amdgpu.h"
27#include "amdgpu_smu.h"
28#include "smu_v13_0.h"
29#include "smu13_driver_if_yellow_carp.h"
30#include "yellow_carp_ppt.h"
31#include "smu_v13_0_1_ppsmc.h"
32#include "smu_v13_0_1_pmfw.h"
33#include "smu_cmn.h"
34
35/*
36 * DO NOT use these for err/warn/info/debug messages.
37 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
38 * They are more MGPU friendly.
39 */
40#undef pr_err
41#undef pr_warn
42#undef pr_info
43#undef pr_debug
44
45#define regSMUIO_GFX_MISC_CNTL0x00c5 0x00c5
46#define regSMUIO_GFX_MISC_CNTL_BASE_IDX0 0
47#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK0x00000006L 0x00000006L
48#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT0x1L 0x1L
49
50#define FEATURE_MASK(feature)(1ULL << feature) (1ULL << feature)
51#define SMC_DPM_FEATURE( (1ULL << 0) | (1ULL << 11) | (1ULL << 13)
| (1ULL << 14) | (1ULL << 15) | (1ULL << 16
) | (1ULL << 17) | (1ULL << 18)| (1ULL << 19
)) ( \
52 FEATURE_MASK(FEATURE_CCLK_DPM_BIT)(1ULL << 0) | \
53 FEATURE_MASK(FEATURE_VCN_DPM_BIT)(1ULL << 11) | \
54 FEATURE_MASK(FEATURE_FCLK_DPM_BIT)(1ULL << 13) | \
55 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)(1ULL << 14) | \
56 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)(1ULL << 15) | \
57 FEATURE_MASK(FEATURE_LCLK_DPM_BIT)(1ULL << 16) | \
58 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)(1ULL << 17) | \
59 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)(1ULL << 18)| \
60 FEATURE_MASK(FEATURE_GFX_DPM_BIT)(1ULL << 19))
61
62static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = {
63 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1)[SMU_MSG_TestMessage] = {1, (0x01), (1)},
64 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1)[SMU_MSG_GetSmuVersion] = {1, (0x02), (1)},
65 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1)[SMU_MSG_GetDriverIfVersion] = {1, (0x03), (1)},
66 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1)[SMU_MSG_EnableGfxOff] = {1, (0x04), (1)},
67 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1)[SMU_MSG_AllowGfxOff] = {1, (0x19), (1)},
68 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1)[SMU_MSG_DisallowGfxOff] = {1, (0x1A), (1)},
69 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1)[SMU_MSG_PowerDownVcn] = {1, (0x06), (1)},
70 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1)[SMU_MSG_PowerUpVcn] = {1, (0x07), (1)},
71 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1)[SMU_MSG_SetHardMinVcn] = {1, (0x08), (1)},
72 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1)[SMU_MSG_PrepareMp1ForUnload] = {1, (0x0C), (1)},
73 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1)[SMU_MSG_SetDriverDramAddrHigh] = {1, (0x0D), (1)},
74 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1)[SMU_MSG_SetDriverDramAddrLow] = {1, (0x0E), (1)},
75 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1)[SMU_MSG_TransferTableSmu2Dram] = {1, (0x0F), (1)},
76 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1)[SMU_MSG_TransferTableDram2Smu] = {1, (0x10), (1)},
77 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1)[SMU_MSG_GfxDeviceDriverReset] = {1, (0x11), (1)},
78 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1)[SMU_MSG_GetEnabledSmuFeatures] = {1, (0x12), (1)},
79 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1)[SMU_MSG_SetHardMinSocclkByFreq] = {1, (0x13), (1)},
80 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1)[SMU_MSG_SetSoftMinVcn] = {1, (0x15), (1)},
81 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1)[SMU_MSG_GetGfxclkFrequency] = {1, (0x17), (1)},
82 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1)[SMU_MSG_GetFclkFrequency] = {1, (0x18), (1)},
83 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1)[SMU_MSG_SetSoftMaxGfxClk] = {1, (0x1B), (1)},
84 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1)[SMU_MSG_SetHardMinGfxClk] = {1, (0x1C), (1)},
85 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1)[SMU_MSG_SetSoftMaxSocclkByFreq] = {1, (0x1D), (1)},
86 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1)[SMU_MSG_SetSoftMaxFclkByFreq] = {1, (0x1E), (1)},
87 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1)[SMU_MSG_SetSoftMaxVcn] = {1, (0x1F), (1)},
88 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1)[SMU_MSG_SetPowerLimitPercentage] = {1, (0x20), (1)},
89 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1)[SMU_MSG_PowerDownJpeg] = {1, (0x21), (1)},
90 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1)[SMU_MSG_PowerUpJpeg] = {1, (0x22), (1)},
91 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1)[SMU_MSG_SetHardMinFclkByFreq] = {1, (0x23), (1)},
92 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1)[SMU_MSG_SetSoftMinSocclkByFreq] = {1, (0x24), (1)},
93};
94
95static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = {
96 FEA_MAP(CCLK_DPM)[SMU_FEATURE_CCLK_DPM_BIT] = {1, 0},
97 FEA_MAP(FAN_CONTROLLER)[SMU_FEATURE_FAN_CONTROLLER_BIT] = {1, 1},
98 FEA_MAP(PPT)[SMU_FEATURE_PPT_BIT] = {1, 3},
99 FEA_MAP(TDC)[SMU_FEATURE_TDC_BIT] = {1, 4},
100 FEA_MAP(THERMAL)[SMU_FEATURE_THERMAL_BIT] = {1, 5},
101 FEA_MAP(ULV)[SMU_FEATURE_ULV_BIT] = {1, 9},
102 FEA_MAP(VCN_DPM)[SMU_FEATURE_VCN_DPM_BIT] = {1, 11},
103 FEA_MAP_REVERSE(FCLK)[SMU_FEATURE_DPM_FCLK_BIT] = {1, 13},
104 FEA_MAP_REVERSE(SOCCLK)[SMU_FEATURE_DPM_SOCCLK_BIT] = {1, 14},
105 FEA_MAP(LCLK_DPM)[SMU_FEATURE_LCLK_DPM_BIT] = {1, 16},
106 FEA_MAP(SHUBCLK_DPM)[SMU_FEATURE_SHUBCLK_DPM_BIT] = {1, 17},
107 FEA_MAP(DCFCLK_DPM)[SMU_FEATURE_DCFCLK_DPM_BIT] = {1, 18},
108 FEA_MAP_HALF_REVERSE(GFX)[SMU_FEATURE_DPM_GFXCLK_BIT] = {1, 19},
109 FEA_MAP(DS_GFXCLK)[SMU_FEATURE_DS_GFXCLK_BIT] = {1, 20},
110 FEA_MAP(DS_SOCCLK)[SMU_FEATURE_DS_SOCCLK_BIT] = {1, 21},
111 FEA_MAP(DS_LCLK)[SMU_FEATURE_DS_LCLK_BIT] = {1, 22},
112 FEA_MAP(DS_DCFCLK)[SMU_FEATURE_DS_DCFCLK_BIT] = {1, 23},
113 FEA_MAP(DS_FCLK)[SMU_FEATURE_DS_FCLK_BIT] = {1, 28},
114 FEA_MAP(DS_MP1CLK)[SMU_FEATURE_DS_MP1CLK_BIT] = {1, 30},
115 FEA_MAP(DS_MP0CLK)[SMU_FEATURE_DS_MP0CLK_BIT] = {1, 31},
116 FEA_MAP(GFX_DEM)[SMU_FEATURE_GFX_DEM_BIT] = {1, 34},
117 FEA_MAP(PSI)[SMU_FEATURE_PSI_BIT] = {1, 35},
118 FEA_MAP(PROCHOT)[SMU_FEATURE_PROCHOT_BIT] = {1, 36},
119 FEA_MAP(CPUOFF)[SMU_FEATURE_CPUOFF_BIT] = {1, 37},
120 FEA_MAP(STAPM)[SMU_FEATURE_STAPM_BIT] = {1, 38},
121 FEA_MAP(S0I3)[SMU_FEATURE_S0I3_BIT] = {1, 39},
122 FEA_MAP(PERF_LIMIT)[SMU_FEATURE_PERF_LIMIT_BIT] = {1, 41},
123 FEA_MAP(CORE_DLDO)[SMU_FEATURE_CORE_DLDO_BIT] = {1, 42},
124 FEA_MAP(RSMU_LOW_POWER)[SMU_FEATURE_RSMU_LOW_POWER_BIT] = {1, 43},
125 FEA_MAP(SMN_LOW_POWER)[SMU_FEATURE_SMN_LOW_POWER_BIT] = {1, 44},
126 FEA_MAP(THM_LOW_POWER)[SMU_FEATURE_THM_LOW_POWER_BIT] = {1, 45},
127 FEA_MAP(SMUIO_LOW_POWER)[SMU_FEATURE_SMUIO_LOW_POWER_BIT] = {1, 46},
128 FEA_MAP(MP1_LOW_POWER)[SMU_FEATURE_MP1_LOW_POWER_BIT] = {1, 47},
129 FEA_MAP(DS_VCN)[SMU_FEATURE_DS_VCN_BIT] = {1, 48},
130 FEA_MAP(CPPC)[SMU_FEATURE_CPPC_BIT] = {1, 49},
131 FEA_MAP(DF_CSTATES)[SMU_FEATURE_DF_CSTATES_BIT] = {1, 52},
132 FEA_MAP(MSMU_LOW_POWER)[SMU_FEATURE_MSMU_LOW_POWER_BIT] = {1, 53},
133 FEA_MAP(ATHUB_PG)[SMU_FEATURE_ATHUB_PG_BIT] = {1, 55},
134};
135
136static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
137 TAB_MAP_VALID(WATERMARKS)[SMU_TABLE_WATERMARKS] = {1, 1},
138 TAB_MAP_VALID(SMU_METRICS)[SMU_TABLE_SMU_METRICS] = {1, 7},
139 TAB_MAP_VALID(CUSTOM_DPM)[SMU_TABLE_CUSTOM_DPM] = {1, 2},
140 TAB_MAP_VALID(DPMCLOCKS)[SMU_TABLE_DPMCLOCKS] = {1, 4},
141};
142
143static int yellow_carp_init_smc_tables(struct smu_context *smu)
144{
145 struct smu_table_context *smu_table = &smu->smu_table;
146 struct smu_table *tables = smu_table->tables;
147
148 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),do { tables[SMU_TABLE_WATERMARKS].size = sizeof(Watermarks_t)
; tables[SMU_TABLE_WATERMARKS].align = (1 << 12); tables
[SMU_TABLE_WATERMARKS].domain = 0x4; } while (0)
149 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_WATERMARKS].size = sizeof(Watermarks_t)
; tables[SMU_TABLE_WATERMARKS].align = (1 << 12); tables
[SMU_TABLE_WATERMARKS].domain = 0x4; } while (0);
150 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),do { tables[SMU_TABLE_DPMCLOCKS].size = sizeof(DpmClocks_t); tables
[SMU_TABLE_DPMCLOCKS].align = (1 << 12); tables[SMU_TABLE_DPMCLOCKS
].domain = 0x4; } while (0)
151 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_DPMCLOCKS].size = sizeof(DpmClocks_t); tables
[SMU_TABLE_DPMCLOCKS].align = (1 << 12); tables[SMU_TABLE_DPMCLOCKS
].domain = 0x4; } while (0);
152 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),do { tables[SMU_TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t
); tables[SMU_TABLE_SMU_METRICS].align = (1 << 12); tables
[SMU_TABLE_SMU_METRICS].domain = 0x4; } while (0)
153 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t
); tables[SMU_TABLE_SMU_METRICS].align = (1 << 12); tables
[SMU_TABLE_SMU_METRICS].domain = 0x4; } while (0);
154
155 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL(0x0001 | 0x0004));
156 if (!smu_table->clocks_table)
157 goto err0_out;
158
159 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL(0x0001 | 0x0004));
160 if (!smu_table->metrics_table)
161 goto err1_out;
162 smu_table->metrics_time = 0;
163
164 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL(0x0001 | 0x0004));
165 if (!smu_table->watermarks_table)
166 goto err2_out;
167
168 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
169 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL(0x0001 | 0x0004));
170 if (!smu_table->gpu_metrics_table)
171 goto err3_out;
172
173 return 0;
174
175err3_out:
176 kfree(smu_table->watermarks_table);
177err2_out:
178 kfree(smu_table->metrics_table);
179err1_out:
180 kfree(smu_table->clocks_table);
181err0_out:
182 return -ENOMEM12;
183}
184
185static int yellow_carp_fini_smc_tables(struct smu_context *smu)
186{
187 struct smu_table_context *smu_table = &smu->smu_table;
188
189 kfree(smu_table->clocks_table);
190 smu_table->clocks_table = NULL((void *)0);
191
192 kfree(smu_table->metrics_table);
193 smu_table->metrics_table = NULL((void *)0);
194
195 kfree(smu_table->watermarks_table);
196 smu_table->watermarks_table = NULL((void *)0);
197
198 kfree(smu_table->gpu_metrics_table);
199 smu_table->gpu_metrics_table = NULL((void *)0);
200
201 return 0;
202}
203
204static int yellow_carp_system_features_control(struct smu_context *smu, bool_Bool en)
205{
206 struct amdgpu_device *adev = smu->adev;
207 int ret = 0;
208
209 if (!en && !adev->in_s0ix)
210 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL((void *)0));
211
212 return ret;
213}
214
215static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool_Bool enable)
216{
217 int ret = 0;
218
219 /* vcn dpm on is a prerequisite for vcn power gate messages */
220 if (enable)
221 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
222 0, NULL((void *)0));
223 else
224 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
225 0, NULL((void *)0));
226
227 return ret;
228}
229
230static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool_Bool enable)
231{
232 int ret = 0;
233
234 if (enable)
235 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
236 0, NULL((void *)0));
237 else
238 ret = smu_cmn_send_smc_msg_with_param(smu,
239 SMU_MSG_PowerDownJpeg, 0,
240 NULL((void *)0));
241
242 return ret;
243}
244
245
246static bool_Bool yellow_carp_is_dpm_running(struct smu_context *smu)
247{
248 int ret = 0;
249 uint64_t feature_enabled;
250
251 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
252
253 if (ret)
254 return false0;
255
256 return !!(feature_enabled & SMC_DPM_FEATURE( (1ULL << 0) | (1ULL << 11) | (1ULL << 13)
| (1ULL << 14) | (1ULL << 15) | (1ULL << 16
) | (1ULL << 17) | (1ULL << 18)| (1ULL << 19
)));
257}
258
259static int yellow_carp_post_smu_init(struct smu_context *smu)
260{
261 struct amdgpu_device *adev = smu->adev;
262 int ret = 0;
263
264 /* allow message will be sent after enable message on Yellow Carp*/
265 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL((void *)0));
266 if (ret)
267 dev_err(adev->dev, "Failed to Enable GfxOff!\n")printf("drm:pid%d:%s *ERROR* " "Failed to Enable GfxOff!\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
268 return ret;
269}
270
271static int yellow_carp_mode_reset(struct smu_context *smu, int type)
272{
273 int ret = 0;
274
275 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL((void *)0));
276 if (ret)
277 dev_err(smu->adev->dev, "Failed to mode reset!\n")printf("drm:pid%d:%s *ERROR* " "Failed to mode reset!\n", ({struct
cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__);
278
279 return ret;
280}
281
282static int yellow_carp_mode2_reset(struct smu_context *smu)
283{
284 return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2);
285}
286
287
288static void yellow_carp_get_ss_power_percent(SmuMetrics_t *metrics,
289 uint32_t *apu_percent, uint32_t *dgpu_percent)
290{
291 uint32_t apu_boost = 0;
292 uint32_t dgpu_boost = 0;
293 uint16_t apu_limit = 0;
294 uint16_t dgpu_limit = 0;
295 uint16_t apu_power = 0;
296 uint16_t dgpu_power = 0;
297
298 /* APU and dGPU power values are reported in milli Watts
299 * and STAPM power limits are in Watts */
300 apu_power = metrics->ApuPower/1000;
301 apu_limit = metrics->StapmOpnLimit;
302 if (apu_power > apu_limit && apu_limit != 0)
303 apu_boost = ((apu_power - apu_limit) * 100) / apu_limit;
304 apu_boost = (apu_boost > 100) ? 100 : apu_boost;
305
306 dgpu_power = metrics->dGpuPower/1000;
307 if (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)
308 dgpu_limit = metrics->StapmCurrentLimit - metrics->StapmOpnLimit;
309 if (dgpu_power > dgpu_limit && dgpu_limit != 0)
310 dgpu_boost = ((dgpu_power - dgpu_limit) * 100) / dgpu_limit;
311 dgpu_boost = (dgpu_boost > 100) ? 100 : dgpu_boost;
312
313 if (dgpu_boost >= apu_boost)
314 apu_boost = 0;
315 else
316 dgpu_boost = 0;
317
318 *apu_percent = apu_boost;
319 *dgpu_percent = dgpu_boost;
320
321}
322
323static int yellow_carp_get_smu_metrics_data(struct smu_context *smu,
324 MetricsMember_t member,
325 uint32_t *value)
326{
327 struct smu_table_context *smu_table = &smu->smu_table;
328
329 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
330 int ret = 0;
331 uint32_t apu_percent = 0;
332 uint32_t dgpu_percent = 0;
333
334 ret = smu_cmn_get_metrics_table(smu, NULL((void *)0), false0);
335 if (ret)
336 return ret;
337
338 switch (member) {
339 case METRICS_AVERAGE_GFXCLK:
340 *value = metrics->GfxclkFrequency;
341 break;
342 case METRICS_AVERAGE_SOCCLK:
343 *value = metrics->SocclkFrequency;
344 break;
345 case METRICS_AVERAGE_VCLK:
346 *value = metrics->VclkFrequency;
347 break;
348 case METRICS_AVERAGE_DCLK:
349 *value = metrics->DclkFrequency;
350 break;
351 case METRICS_AVERAGE_UCLK:
352 *value = metrics->MemclkFrequency;
353 break;
354 case METRICS_AVERAGE_GFXACTIVITY:
355 *value = metrics->GfxActivity / 100;
356 break;
357 case METRICS_AVERAGE_VCNACTIVITY:
358 *value = metrics->UvdActivity;
359 break;
360 case METRICS_AVERAGE_SOCKETPOWER:
361 *value = (metrics->CurrentSocketPower << 8) / 1000;
362 break;
363 case METRICS_TEMPERATURE_EDGE:
364 *value = metrics->GfxTemperature / 100 *
365 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
366 break;
367 case METRICS_TEMPERATURE_HOTSPOT:
368 *value = metrics->SocTemperature / 100 *
369 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
370 break;
371 case METRICS_THROTTLER_STATUS:
372 *value = metrics->ThrottlerStatus;
373 break;
374 case METRICS_VOLTAGE_VDDGFX:
375 *value = metrics->Voltage[0];
376 break;
377 case METRICS_VOLTAGE_VDDSOC:
378 *value = metrics->Voltage[1];
379 break;
380 case METRICS_SS_APU_SHARE:
381 /* return the percentage of APU power boost
382 * with respect to APU's power limit.
383 */
384 yellow_carp_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
385 *value = apu_percent;
386 break;
387 case METRICS_SS_DGPU_SHARE:
388 /* return the percentage of dGPU power boost
389 * with respect to dGPU's power limit.
390 */
391 yellow_carp_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
392 *value = dgpu_percent;
393 break;
394 default:
395 *value = UINT_MAX0xffffffffU;
396 break;
397 }
398
399 return ret;
400}
401
402static int yellow_carp_read_sensor(struct smu_context *smu,
403 enum amd_pp_sensors sensor,
404 void *data, uint32_t *size)
405{
406 int ret = 0;
407
408 if (!data || !size)
409 return -EINVAL22;
410
411 switch (sensor) {
412 case AMDGPU_PP_SENSOR_GPU_LOAD:
413 ret = yellow_carp_get_smu_metrics_data(smu,
414 METRICS_AVERAGE_GFXACTIVITY,
415 (uint32_t *)data);
416 *size = 4;
417 break;
418 case AMDGPU_PP_SENSOR_GPU_POWER:
419 ret = yellow_carp_get_smu_metrics_data(smu,
420 METRICS_AVERAGE_SOCKETPOWER,
421 (uint32_t *)data);
422 *size = 4;
423 break;
424 case AMDGPU_PP_SENSOR_EDGE_TEMP:
425 ret = yellow_carp_get_smu_metrics_data(smu,
426 METRICS_TEMPERATURE_EDGE,
427 (uint32_t *)data);
428 *size = 4;
429 break;
430 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
431 ret = yellow_carp_get_smu_metrics_data(smu,
432 METRICS_TEMPERATURE_HOTSPOT,
433 (uint32_t *)data);
434 *size = 4;
435 break;
436 case AMDGPU_PP_SENSOR_GFX_MCLK:
437 ret = yellow_carp_get_smu_metrics_data(smu,
438 METRICS_AVERAGE_UCLK,
439 (uint32_t *)data);
440 *(uint32_t *)data *= 100;
441 *size = 4;
442 break;
443 case AMDGPU_PP_SENSOR_GFX_SCLK:
444 ret = yellow_carp_get_smu_metrics_data(smu,
445 METRICS_AVERAGE_GFXCLK,
446 (uint32_t *)data);
447 *(uint32_t *)data *= 100;
448 *size = 4;
449 break;
450 case AMDGPU_PP_SENSOR_VDDGFX:
451 ret = yellow_carp_get_smu_metrics_data(smu,
452 METRICS_VOLTAGE_VDDGFX,
453 (uint32_t *)data);
454 *size = 4;
455 break;
456 case AMDGPU_PP_SENSOR_VDDNB:
457 ret = yellow_carp_get_smu_metrics_data(smu,
458 METRICS_VOLTAGE_VDDSOC,
459 (uint32_t *)data);
460 *size = 4;
461 break;
462 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
463 ret = yellow_carp_get_smu_metrics_data(smu,
464 METRICS_SS_APU_SHARE,
465 (uint32_t *)data);
466 *size = 4;
467 break;
468 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
469 ret = yellow_carp_get_smu_metrics_data(smu,
470 METRICS_SS_DGPU_SHARE,
471 (uint32_t *)data);
472 *size = 4;
473 break;
474 default:
475 ret = -EOPNOTSUPP45;
476 break;
477 }
478
479 return ret;
480}
481
482static int yellow_carp_set_watermarks_table(struct smu_context *smu,
483 struct pp_smu_wm_range_sets *clock_ranges)
484{
485 int i;
486 int ret = 0;
487 Watermarks_t *table = smu->smu_table.watermarks_table;
488
489 if (!table || !clock_ranges)
490 return -EINVAL22;
491
492 if (clock_ranges) {
493 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES4 ||
494 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES4)
495 return -EINVAL22;
496
497 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
498 table->WatermarkRow[WM_DCFCLK][i].MinClock =
499 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
500 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
501 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
502 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
503 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
504 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
505 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
506
507 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
508 clock_ranges->reader_wm_sets[i].wm_inst;
509 }
510
511 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
512 table->WatermarkRow[WM_SOCCLK][i].MinClock =
513 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
514 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
515 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
516 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
517 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
518 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
519 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
520
521 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
522 clock_ranges->writer_wm_sets[i].wm_inst;
523 }
524
525 smu->watermarks_bitmap |= WATERMARKS_EXIST(1 << 0);
526 }
527
528 /* pass data to smu controller */
529 if ((smu->watermarks_bitmap & WATERMARKS_EXIST(1 << 0)) &&
530 !(smu->watermarks_bitmap & WATERMARKS_LOADED(1 << 1))) {
531 ret = smu_cmn_write_watermarks_table(smu);
532 if (ret) {
533 dev_err(smu->adev->dev, "Failed to update WMTABLE!")printf("drm:pid%d:%s *ERROR* " "Failed to update WMTABLE!", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
534 return ret;
535 }
536 smu->watermarks_bitmap |= WATERMARKS_LOADED(1 << 1);
537 }
538
539 return 0;
540}
541
542static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
543 void **table)
544{
545 struct smu_table_context *smu_table = &smu->smu_table;
546 struct gpu_metrics_v2_1 *gpu_metrics =
547 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
548 SmuMetrics_t metrics;
549 int ret = 0;
550
551 ret = smu_cmn_get_metrics_table(smu, &metrics, true1);
552 if (ret)
553 return ret;
554
555 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
556
557 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
558 gpu_metrics->temperature_soc = metrics.SocTemperature;
559 memcpy(&gpu_metrics->temperature_core[0],__builtin_memcpy((&gpu_metrics->temperature_core[0]), (
&metrics.CoreTemperature[0]), (sizeof(uint16_t) * 8))
560 &metrics.CoreTemperature[0],__builtin_memcpy((&gpu_metrics->temperature_core[0]), (
&metrics.CoreTemperature[0]), (sizeof(uint16_t) * 8))
561 sizeof(uint16_t) * 8)__builtin_memcpy((&gpu_metrics->temperature_core[0]), (
&metrics.CoreTemperature[0]), (sizeof(uint16_t) * 8));
562 gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
563
564 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
565 gpu_metrics->average_mm_activity = metrics.UvdActivity;
566
567 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
568 gpu_metrics->average_gfx_power = metrics.Power[0];
569 gpu_metrics->average_soc_power = metrics.Power[1];
570 memcpy(&gpu_metrics->average_core_power[0],__builtin_memcpy((&gpu_metrics->average_core_power[0])
, (&metrics.CorePower[0]), (sizeof(uint16_t) * 8))
571 &metrics.CorePower[0],__builtin_memcpy((&gpu_metrics->average_core_power[0])
, (&metrics.CorePower[0]), (sizeof(uint16_t) * 8))
572 sizeof(uint16_t) * 8)__builtin_memcpy((&gpu_metrics->average_core_power[0])
, (&metrics.CorePower[0]), (sizeof(uint16_t) * 8));
573
574 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
575 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
576 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
577 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
578 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
579 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
580
581 memcpy(&gpu_metrics->current_coreclk[0],__builtin_memcpy((&gpu_metrics->current_coreclk[0]), (
&metrics.CoreFrequency[0]), (sizeof(uint16_t) * 8))
582 &metrics.CoreFrequency[0],__builtin_memcpy((&gpu_metrics->current_coreclk[0]), (
&metrics.CoreFrequency[0]), (sizeof(uint16_t) * 8))
583 sizeof(uint16_t) * 8)__builtin_memcpy((&gpu_metrics->current_coreclk[0]), (
&metrics.CoreFrequency[0]), (sizeof(uint16_t) * 8));
584 gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
585
586 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
587
588 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
589
590 *table = (void *)gpu_metrics;
591
592 return sizeof(struct gpu_metrics_v2_1);
593}
594
595/**
596 * yellow_carp_get_gfxoff_status - get gfxoff status
597 *
598 * @smu: smu_context pointer
599 *
600 * This function will be used to get gfxoff status
601 *
602 * Returns 0=GFXOFF(default).
603 * Returns 1=Transition out of GFX State.
604 * Returns 2=Not in GFXOFF.
605 * Returns 3=Transition into GFXOFF.
606 */
607static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
608{
609 uint32_t reg;
610 uint32_t gfxoff_status = 0;
611 struct amdgpu_device *adev = smu->adev;
612
613 reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][0] + 0x00c5, 0, SMUIO_HWIP) : amdgpu_device_rreg(adev, (adev
->reg_offset[SMUIO_HWIP][0][0] + 0x00c5), 0));
614 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK0x00000006L)
615 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT0x1L;
616
617 return gfxoff_status;
618}
619
620static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
621{
622 struct smu_table_context *smu_table = &smu->smu_table;
623
624 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false0);
625}
626
627static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
628 long input[], uint32_t size)
629{
630 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
631 int ret = 0;
632
633 /* Only allowed in manual mode */
634 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
635 return -EINVAL22;
636
637 switch (type) {
638 case PP_OD_EDIT_SCLK_VDDC_TABLE:
639 if (size != 2) {
640 dev_err(smu->adev->dev, "Input parameter number not correct\n")printf("drm:pid%d:%s *ERROR* " "Input parameter number not correct\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
641 return -EINVAL22;
642 }
643
644 if (input[0] == 0) {
645 if (input[1] < smu->gfx_default_hard_min_freq) {
646 dev_warn(smu->adev->dev,printf("drm:pid%d:%s *WARNING* " "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , input[
1], smu->gfx_default_hard_min_freq)
647 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",printf("drm:pid%d:%s *WARNING* " "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , input[
1], smu->gfx_default_hard_min_freq)
648 input[1], smu->gfx_default_hard_min_freq)printf("drm:pid%d:%s *WARNING* " "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , input[
1], smu->gfx_default_hard_min_freq);
649 return -EINVAL22;
650 }
651 smu->gfx_actual_hard_min_freq = input[1];
652 } else if (input[0] == 1) {
653 if (input[1] > smu->gfx_default_soft_max_freq) {
654 dev_warn(smu->adev->dev,printf("drm:pid%d:%s *WARNING* " "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , input[
1], smu->gfx_default_soft_max_freq)
655 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",printf("drm:pid%d:%s *WARNING* " "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , input[
1], smu->gfx_default_soft_max_freq)
656 input[1], smu->gfx_default_soft_max_freq)printf("drm:pid%d:%s *WARNING* " "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , input[
1], smu->gfx_default_soft_max_freq);
657 return -EINVAL22;
658 }
659 smu->gfx_actual_soft_max_freq = input[1];
660 } else {
661 return -EINVAL22;
662 }
663 break;
664 case PP_OD_RESTORE_DEFAULT_TABLE:
665 if (size != 0) {
666 dev_err(smu->adev->dev, "Input parameter number not correct\n")printf("drm:pid%d:%s *ERROR* " "Input parameter number not correct\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
667 return -EINVAL22;
668 } else {
669 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
670 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
671 }
672 break;
673 case PP_OD_COMMIT_DPM_TABLE:
674 if (size != 0) {
675 dev_err(smu->adev->dev, "Input parameter number not correct\n")printf("drm:pid%d:%s *ERROR* " "Input parameter number not correct\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
676 return -EINVAL22;
677 } else {
678 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
679 dev_err(smu->adev->dev,printf("drm:pid%d:%s *ERROR* " "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , smu->
gfx_actual_hard_min_freq, smu->gfx_actual_soft_max_freq)
680 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",printf("drm:pid%d:%s *ERROR* " "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , smu->
gfx_actual_hard_min_freq, smu->gfx_actual_soft_max_freq)
681 smu->gfx_actual_hard_min_freq,printf("drm:pid%d:%s *ERROR* " "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , smu->
gfx_actual_hard_min_freq, smu->gfx_actual_soft_max_freq)
682 smu->gfx_actual_soft_max_freq)printf("drm:pid%d:%s *ERROR* " "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , smu->
gfx_actual_hard_min_freq, smu->gfx_actual_soft_max_freq);
683 return -EINVAL22;
684 }
685
686 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
687 smu->gfx_actual_hard_min_freq, NULL((void *)0));
688 if (ret) {
689 dev_err(smu->adev->dev, "Set hard min sclk failed!")printf("drm:pid%d:%s *ERROR* " "Set hard min sclk failed!", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
690 return ret;
691 }
692
693 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
694 smu->gfx_actual_soft_max_freq, NULL((void *)0));
695 if (ret) {
696 dev_err(smu->adev->dev, "Set soft max sclk failed!")printf("drm:pid%d:%s *ERROR* " "Set soft max sclk failed!", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
697 return ret;
698 }
699 }
700 break;
701 default:
702 return -ENOSYS78;
703 }
704
705 return ret;
706}
707
708static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
709 enum smu_clk_type clk_type,
710 uint32_t *value)
711{
712 MetricsMember_t member_type;
713
714 switch (clk_type) {
715 case SMU_SOCCLK:
716 member_type = METRICS_AVERAGE_SOCCLK;
717 break;
718 case SMU_VCLK:
719 member_type = METRICS_AVERAGE_VCLK;
720 break;
721 case SMU_DCLK:
722 member_type = METRICS_AVERAGE_DCLK;
723 break;
724 case SMU_MCLK:
725 member_type = METRICS_AVERAGE_UCLK;
726 break;
727 case SMU_FCLK:
728 return smu_cmn_send_smc_msg_with_param(smu,
729 SMU_MSG_GetFclkFrequency, 0, value);
730 case SMU_GFXCLK:
731 case SMU_SCLK:
732 return smu_cmn_send_smc_msg_with_param(smu,
733 SMU_MSG_GetGfxclkFrequency, 0, value);
734 break;
735 default:
736 return -EINVAL22;
737 }
738
739 return yellow_carp_get_smu_metrics_data(smu, member_type, value);
740}
741
742static int yellow_carp_get_dpm_level_count(struct smu_context *smu,
743 enum smu_clk_type clk_type,
744 uint32_t *count)
745{
746 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
747
748 switch (clk_type) {
749 case SMU_SOCCLK:
750 *count = clk_table->NumSocClkLevelsEnabled;
751 break;
752 case SMU_VCLK:
753 *count = clk_table->VcnClkLevelsEnabled;
754 break;
755 case SMU_DCLK:
756 *count = clk_table->VcnClkLevelsEnabled;
757 break;
758 case SMU_MCLK:
759 *count = clk_table->NumDfPstatesEnabled;
760 break;
761 case SMU_FCLK:
762 *count = clk_table->NumDfPstatesEnabled;
763 break;
764 default:
765 break;
766 }
767
768 return 0;
769}
770
771static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu,
772 enum smu_clk_type clk_type,
773 uint32_t dpm_level,
774 uint32_t *freq)
775{
776 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
777
778 if (!clk_table || clk_type >= SMU_CLK_COUNT)
779 return -EINVAL22;
780
781 switch (clk_type) {
782 case SMU_SOCCLK:
783 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
784 return -EINVAL22;
785 *freq = clk_table->SocClocks[dpm_level];
786 break;
787 case SMU_VCLK:
788 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
789 return -EINVAL22;
790 *freq = clk_table->VClocks[dpm_level];
791 break;
792 case SMU_DCLK:
793 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
794 return -EINVAL22;
795 *freq = clk_table->DClocks[dpm_level];
796 break;
797 case SMU_UCLK:
798 case SMU_MCLK:
799 if (dpm_level >= clk_table->NumDfPstatesEnabled)
800 return -EINVAL22;
801 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
802 break;
803 case SMU_FCLK:
804 if (dpm_level >= clk_table->NumDfPstatesEnabled)
805 return -EINVAL22;
806 *freq = clk_table->DfPstateTable[dpm_level].FClk;
807 break;
808 default:
809 return -EINVAL22;
810 }
811
812 return 0;
813}
814
815static bool_Bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
816 enum smu_clk_type clk_type)
817{
818 enum smu_feature_mask feature_id = 0;
819
820 switch (clk_type) {
821 case SMU_MCLK:
822 case SMU_UCLK:
823 case SMU_FCLK:
824 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
825 break;
826 case SMU_GFXCLK:
827 case SMU_SCLK:
828 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
829 break;
830 case SMU_SOCCLK:
831 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
832 break;
833 case SMU_VCLK:
834 case SMU_DCLK:
835 feature_id = SMU_FEATURE_VCN_DPM_BIT;
836 break;
837 default:
838 return true1;
839 }
840
841 return smu_cmn_feature_is_enabled(smu, feature_id);
842}
843
844static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
845 enum smu_clk_type clk_type,
846 uint32_t *min,
847 uint32_t *max)
848{
849 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
850 uint32_t clock_limit;
851 uint32_t max_dpm_level, min_dpm_level;
852 int ret = 0;
853
854 if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
855 switch (clk_type) {
856 case SMU_MCLK:
857 case SMU_UCLK:
858 clock_limit = smu->smu_table.boot_values.uclk;
859 break;
860 case SMU_FCLK:
861 clock_limit = smu->smu_table.boot_values.fclk;
862 break;
863 case SMU_GFXCLK:
864 case SMU_SCLK:
865 clock_limit = smu->smu_table.boot_values.gfxclk;
866 break;
867 case SMU_SOCCLK:
868 clock_limit = smu->smu_table.boot_values.socclk;
869 break;
870 case SMU_VCLK:
871 clock_limit = smu->smu_table.boot_values.vclk;
872 break;
873 case SMU_DCLK:
874 clock_limit = smu->smu_table.boot_values.dclk;
875 break;
876 default:
877 clock_limit = 0;
878 break;
879 }
880
881 /* clock in Mhz unit */
882 if (min)
883 *min = clock_limit / 100;
884 if (max)
885 *max = clock_limit / 100;
886
887 return 0;
888 }
889
890 if (max) {
891 switch (clk_type) {
892 case SMU_GFXCLK:
893 case SMU_SCLK:
894 *max = clk_table->MaxGfxClk;
895 break;
896 case SMU_MCLK:
897 case SMU_UCLK:
898 case SMU_FCLK:
899 max_dpm_level = 0;
900 break;
901 case SMU_SOCCLK:
902 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
903 break;
904 case SMU_VCLK:
905 case SMU_DCLK:
906 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
907 break;
908 default:
909 ret = -EINVAL22;
910 goto failed;
911 }
912
913 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
914 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
915 if (ret)
916 goto failed;
917 }
918 }
919
920 if (min) {
921 switch (clk_type) {
922 case SMU_GFXCLK:
923 case SMU_SCLK:
924 *min = clk_table->MinGfxClk;
925 break;
926 case SMU_MCLK:
927 case SMU_UCLK:
928 case SMU_FCLK:
929 min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
930 break;
931 case SMU_SOCCLK:
932 min_dpm_level = 0;
933 break;
934 case SMU_VCLK:
935 case SMU_DCLK:
936 min_dpm_level = 0;
937 break;
938 default:
939 ret = -EINVAL22;
940 goto failed;
941 }
942
943 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
944 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
945 if (ret)
946 goto failed;
947 }
948 }
949
950failed:
951 return ret;
952}
953
954static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
955 enum smu_clk_type clk_type,
956 uint32_t min,
957 uint32_t max)
958{
959 enum smu_message_type msg_set_min, msg_set_max;
960 int ret = 0;
961
962 if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
963 return -EINVAL22;
964
965 switch (clk_type) {
966 case SMU_GFXCLK:
967 case SMU_SCLK:
968 msg_set_min = SMU_MSG_SetHardMinGfxClk;
969 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
970 break;
971 case SMU_FCLK:
972 msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
973 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
974 break;
975 case SMU_SOCCLK:
976 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
977 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
978 break;
979 case SMU_VCLK:
980 case SMU_DCLK:
981 msg_set_min = SMU_MSG_SetHardMinVcn;
982 msg_set_max = SMU_MSG_SetSoftMaxVcn;
983 break;
984 default:
985 return -EINVAL22;
986 }
987
988 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL((void *)0));
989 if (ret)
990 goto out;
991
992 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL((void *)0));
993 if (ret)
994 goto out;
995
996out:
997 return ret;
998}
999
1000static int yellow_carp_print_clk_levels(struct smu_context *smu,
1001 enum smu_clk_type clk_type, char *buf)
1002{
1003 int i, idx, size = 0, ret = 0;
1004 uint32_t cur_value = 0, value = 0, count = 0;
1005 uint32_t min, max;
1006
1007 smu_cmn_get_sysfs_buf(&buf, &size);
1008
1009 switch (clk_type) {
1010 case SMU_OD_SCLK:
1011 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1012 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
1013 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
1014 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
1015 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
1016 break;
1017 case SMU_OD_RANGE:
1018 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1019 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1020 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
1021 break;
1022 case SMU_SOCCLK:
1023 case SMU_VCLK:
1024 case SMU_DCLK:
1025 case SMU_MCLK:
1026 case SMU_FCLK:
1027 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1028 if (ret)
1029 goto print_clk_out;
1030
1031 ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);
1032 if (ret)
1033 goto print_clk_out;
1034
1035 for (i = 0; i < count; i++) {
1036 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
1037 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, idx, &value);
1038 if (ret)
1039 goto print_clk_out;
1040
1041 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1042 cur_value == value ? "*" : "");
1043 }
1044 break;
1045 case SMU_GFXCLK:
1046 case SMU_SCLK:
1047 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1048 if (ret)
1049 goto print_clk_out;
1050 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
1051 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
1052 if (cur_value == max)
1053 i = 2;
1054 else if (cur_value == min)
1055 i = 0;
1056 else
1057 i = 1;
1058 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
1059 i == 0 ? "*" : "");
1060 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1061 i == 1 ? cur_value : YELLOW_CARP_UMD_PSTATE_GFXCLK1100,
1062 i == 1 ? "*" : "");
1063 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
1064 i == 2 ? "*" : "");
1065 break;
1066 default:
1067 break;
1068 }
1069
1070print_clk_out:
1071 return size;
1072}
1073
1074static int yellow_carp_force_clk_levels(struct smu_context *smu,
1075 enum smu_clk_type clk_type, uint32_t mask)
1076{
1077 uint32_t soft_min_level = 0, soft_max_level = 0;
1078 uint32_t min_freq = 0, max_freq = 0;
1079 int ret = 0;
1080
1081 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1082 soft_max_level = mask ? (fls(mask) - 1) : 0;
1083
1084 switch (clk_type) {
1085 case SMU_SOCCLK:
1086 case SMU_FCLK:
1087 case SMU_VCLK:
1088 case SMU_DCLK:
1089 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1090 if (ret)
1091 goto force_level_out;
1092
1093 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1094 if (ret)
1095 goto force_level_out;
1096
1097 ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1098 if (ret)
1099 goto force_level_out;
1100 break;
1101 default:
1102 ret = -EINVAL22;
1103 break;
1104 }
1105
1106force_level_out:
1107 return ret;
1108}
1109
1110static int yellow_carp_set_performance_level(struct smu_context *smu,
1111 enum amd_dpm_forced_level level)
1112{
1113 struct amdgpu_device *adev = smu->adev;
Value stored to 'adev' during its initialization is never read
1114 uint32_t sclk_min = 0, sclk_max = 0;
1115 uint32_t fclk_min = 0, fclk_max = 0;
1116 uint32_t socclk_min = 0, socclk_max = 0;
1117 int ret = 0;
1118
1119 switch (level) {
1120 case AMD_DPM_FORCED_LEVEL_HIGH:
1121 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL((void *)0), &sclk_max);
1122 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL((void *)0), &fclk_max);
1123 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL((void *)0), &socclk_max);
1124 sclk_min = sclk_max;
1125 fclk_min = fclk_max;
1126 socclk_min = socclk_max;
1127 break;
1128 case AMD_DPM_FORCED_LEVEL_LOW:
1129 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL((void *)0));
1130 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL((void *)0));
1131 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL((void *)0));
1132 sclk_max = sclk_min;
1133 fclk_max = fclk_min;
1134 socclk_max = socclk_min;
1135 break;
1136 case AMD_DPM_FORCED_LEVEL_AUTO:
1137 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1138 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
1139 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1140 break;
1141 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1142 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1143 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1144 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1145 /* Temporarily do nothing since the optimal clocks haven't been provided yet */
1146 break;
1147 case AMD_DPM_FORCED_LEVEL_MANUAL:
1148 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1149 return 0;
1150 default:
1151 dev_err(adev->dev, "Invalid performance level %d\n", level)printf("drm:pid%d:%s *ERROR* " "Invalid performance level %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , level);
1152 return -EINVAL22;
1153 }
1154
1155 if (sclk_min && sclk_max) {
1156 ret = yellow_carp_set_soft_freq_limited_range(smu,
1157 SMU_SCLK,
1158 sclk_min,
1159 sclk_max);
1160 if (ret)
1161 return ret;
1162
1163 smu->gfx_actual_hard_min_freq = sclk_min;
1164 smu->gfx_actual_soft_max_freq = sclk_max;
1165 }
1166
1167 if (fclk_min && fclk_max) {
1168 ret = yellow_carp_set_soft_freq_limited_range(smu,
1169 SMU_FCLK,
1170 fclk_min,
1171 fclk_max);
1172 if (ret)
1173 return ret;
1174 }
1175
1176 if (socclk_min && socclk_max) {
1177 ret = yellow_carp_set_soft_freq_limited_range(smu,
1178 SMU_SOCCLK,
1179 socclk_min,
1180 socclk_max);
1181 if (ret)
1182 return ret;
1183 }
1184
1185 return ret;
1186}
1187
1188static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1189{
1190 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1191
1192 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1193 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1194 smu->gfx_actual_hard_min_freq = 0;
1195 smu->gfx_actual_soft_max_freq = 0;
1196
1197 return 0;
1198}
1199
1200static const struct pptable_funcs yellow_carp_ppt_funcs = {
1201 .check_fw_status = smu_v13_0_check_fw_status,
1202 .check_fw_version = smu_v13_0_check_fw_version,
1203 .init_smc_tables = yellow_carp_init_smc_tables,
1204 .fini_smc_tables = yellow_carp_fini_smc_tables,
1205 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1206 .system_features_control = yellow_carp_system_features_control,
1207 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1208 .send_smc_msg = smu_cmn_send_smc_msg,
1209 .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable,
1210 .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable,
1211 .set_default_dpm_table = yellow_carp_set_default_dpm_tables,
1212 .read_sensor = yellow_carp_read_sensor,
1213 .is_dpm_running = yellow_carp_is_dpm_running,
1214 .set_watermarks_table = yellow_carp_set_watermarks_table,
1215 .get_gpu_metrics = yellow_carp_get_gpu_metrics,
1216 .get_enabled_mask = smu_cmn_get_enabled_mask,
1217 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1218 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1219 .gfx_off_control = smu_v13_0_gfx_off_control,
1220 .get_gfx_off_status = yellow_carp_get_gfxoff_status,
1221 .post_init = yellow_carp_post_smu_init,
1222 .mode2_reset = yellow_carp_mode2_reset,
1223 .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
1224 .od_edit_dpm_table = yellow_carp_od_edit_dpm_table,
1225 .print_clk_levels = yellow_carp_print_clk_levels,
1226 .force_clk_levels = yellow_carp_force_clk_levels,
1227 .set_performance_level = yellow_carp_set_performance_level,
1228 .set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters,
1229};
1230
1231void yellow_carp_set_ppt_funcs(struct smu_context *smu)
1232{
1233 smu->ppt_funcs = &yellow_carp_ppt_funcs;
1234 smu->message_map = yellow_carp_message_map;
1235 smu->feature_map = yellow_carp_feature_mask_map;
1236 smu->table_map = yellow_carp_table_map;
1237 smu->is_apu = true1;
1238 smu_v13_0_set_smu_mailbox_registers(smu);
1239}