| File: | dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c |
| Warning: | line 7272, column 24 Value stored to 'adev' during its initialization is never read |
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| 1 | /* |
| 2 | * Copyright 2015 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: AMD |
| 23 | * |
| 24 | */ |
| 25 | |
| 26 | /* The caprices of the preprocessor require that this be declared right here */ |
| 27 | #define CREATE_TRACE_POINTS |
| 28 | |
| 29 | #include "dm_services_types.h" |
| 30 | #include "dc.h" |
| 31 | #include "dc_link_dp.h" |
| 32 | #include "link_enc_cfg.h" |
| 33 | #include "dc/inc/core_types.h" |
| 34 | #include "dal_asic_id.h" |
| 35 | #include "dmub/dmub_srv.h" |
| 36 | #include "dc/inc/hw/dmcu.h" |
| 37 | #include "dc/inc/hw/abm.h" |
| 38 | #include "dc/dc_dmub_srv.h" |
| 39 | #include "dc/dc_edid_parser.h" |
| 40 | #include "dc/dc_stat.h" |
| 41 | #include "amdgpu_dm_trace.h" |
| 42 | #include "dc/inc/dc_link_ddc.h" |
| 43 | #include "dpcd_defs.h" |
| 44 | #include "dc/inc/link_dpcd.h" |
| 45 | #include "link_service_types.h" |
| 46 | |
| 47 | #include "vid.h" |
| 48 | #include "amdgpu.h" |
| 49 | #include "amdgpu_display.h" |
| 50 | #include "amdgpu_ucode.h" |
| 51 | #include "atom.h" |
| 52 | #include "amdgpu_dm.h" |
| 53 | #include "amdgpu_dm_plane.h" |
| 54 | #include "amdgpu_dm_crtc.h" |
| 55 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 56 | #include "amdgpu_dm_hdcp.h" |
| 57 | #include <drm/display/drm_hdcp_helper.h> |
| 58 | #endif |
| 59 | #include "amdgpu_pm.h" |
| 60 | #include "amdgpu_atombios.h" |
| 61 | |
| 62 | #include "amd_shared.h" |
| 63 | #include "amdgpu_dm_irq.h" |
| 64 | #include "dm_helpers.h" |
| 65 | #include "amdgpu_dm_mst_types.h" |
| 66 | #if defined(CONFIG_DEBUG_FS) |
| 67 | #include "amdgpu_dm_debugfs.h" |
| 68 | #endif |
| 69 | #include "amdgpu_dm_psr.h" |
| 70 | |
| 71 | #include "ivsrcid/ivsrcid_vislands30.h" |
| 72 | |
| 73 | #include "i2caux_interface.h" |
| 74 | #include <linux/module.h> |
| 75 | #include <linux/moduleparam.h> |
| 76 | #include <linux/types.h> |
| 77 | #include <linux/pm_runtime.h> |
| 78 | #include <linux/pci.h> |
| 79 | #include <linux/firmware.h> |
| 80 | #include <linux/component.h> |
| 81 | #include <linux/dmi.h> |
| 82 | |
| 83 | #include <drm/display/drm_dp_mst_helper.h> |
| 84 | #include <drm/display/drm_hdmi_helper.h> |
| 85 | #include <drm/drm_atomic.h> |
| 86 | #include <drm/drm_atomic_uapi.h> |
| 87 | #include <drm/drm_atomic_helper.h> |
| 88 | #include <drm/drm_blend.h> |
| 89 | #include <drm/drm_fourcc.h> |
| 90 | #include <drm/drm_edid.h> |
| 91 | #include <drm/drm_vblank.h> |
| 92 | #include <drm/drm_audio_component.h> |
| 93 | #include <drm/drm_gem_atomic_helper.h> |
| 94 | #include <drm/drm_plane_helper.h> |
| 95 | |
| 96 | #include <acpi/video.h> |
| 97 | |
| 98 | #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" |
| 99 | |
| 100 | #include "dcn/dcn_1_0_offset.h" |
| 101 | #include "dcn/dcn_1_0_sh_mask.h" |
| 102 | #include "soc15_hw_ip.h" |
| 103 | #include "soc15_common.h" |
| 104 | #include "vega10_ip_offset.h" |
| 105 | |
| 106 | #include "gc/gc_11_0_0_offset.h" |
| 107 | #include "gc/gc_11_0_0_sh_mask.h" |
| 108 | |
| 109 | #include "modules/inc/mod_freesync.h" |
| 110 | #include "modules/power/power_helpers.h" |
| 111 | #include "modules/inc/mod_info_packet.h" |
| 112 | |
| 113 | #define FIRMWARE_RENOIR_DMUB"amdgpu/renoir_dmcub.bin" "amdgpu/renoir_dmcub.bin" |
| 114 | MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB); |
| 115 | #define FIRMWARE_SIENNA_CICHLID_DMUB"amdgpu/sienna_cichlid_dmcub.bin" "amdgpu/sienna_cichlid_dmcub.bin" |
| 116 | MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB); |
| 117 | #define FIRMWARE_NAVY_FLOUNDER_DMUB"amdgpu/navy_flounder_dmcub.bin" "amdgpu/navy_flounder_dmcub.bin" |
| 118 | MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB); |
| 119 | #define FIRMWARE_GREEN_SARDINE_DMUB"amdgpu/green_sardine_dmcub.bin" "amdgpu/green_sardine_dmcub.bin" |
| 120 | MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB); |
| 121 | #define FIRMWARE_VANGOGH_DMUB"amdgpu/vangogh_dmcub.bin" "amdgpu/vangogh_dmcub.bin" |
| 122 | MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB); |
| 123 | #define FIRMWARE_DIMGREY_CAVEFISH_DMUB"amdgpu/dimgrey_cavefish_dmcub.bin" "amdgpu/dimgrey_cavefish_dmcub.bin" |
| 124 | MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB); |
| 125 | #define FIRMWARE_BEIGE_GOBY_DMUB"amdgpu/beige_goby_dmcub.bin" "amdgpu/beige_goby_dmcub.bin" |
| 126 | MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB); |
| 127 | #define FIRMWARE_YELLOW_CARP_DMUB"amdgpu/yellow_carp_dmcub.bin" "amdgpu/yellow_carp_dmcub.bin" |
| 128 | MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB); |
| 129 | #define FIRMWARE_DCN_314_DMUB"amdgpu/dcn_3_1_4_dmcub.bin" "amdgpu/dcn_3_1_4_dmcub.bin" |
| 130 | MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB); |
| 131 | #define FIRMWARE_DCN_315_DMUB"amdgpu/dcn_3_1_5_dmcub.bin" "amdgpu/dcn_3_1_5_dmcub.bin" |
| 132 | MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB); |
| 133 | #define FIRMWARE_DCN316_DMUB"amdgpu/dcn_3_1_6_dmcub.bin" "amdgpu/dcn_3_1_6_dmcub.bin" |
| 134 | MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB); |
| 135 | |
| 136 | #define FIRMWARE_DCN_V3_2_0_DMCUB"amdgpu/dcn_3_2_0_dmcub.bin" "amdgpu/dcn_3_2_0_dmcub.bin" |
| 137 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB); |
| 138 | #define FIRMWARE_DCN_V3_2_1_DMCUB"amdgpu/dcn_3_2_1_dmcub.bin" "amdgpu/dcn_3_2_1_dmcub.bin" |
| 139 | MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB); |
| 140 | |
| 141 | #define FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin" "amdgpu/raven_dmcu.bin" |
| 142 | MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU); |
| 143 | |
| 144 | #define FIRMWARE_NAVI12_DMCU"amdgpu/navi12_dmcu.bin" "amdgpu/navi12_dmcu.bin" |
| 145 | MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU); |
| 146 | |
| 147 | /* Number of bytes in PSP header for firmware. */ |
| 148 | #define PSP_HEADER_BYTES0x100 0x100 |
| 149 | |
| 150 | /* Number of bytes in PSP footer for firmware. */ |
| 151 | #define PSP_FOOTER_BYTES0x100 0x100 |
| 152 | |
| 153 | /** |
| 154 | * DOC: overview |
| 155 | * |
| 156 | * The AMDgpu display manager, **amdgpu_dm** (or even simpler, |
| 157 | * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM |
| 158 | * requests into DC requests, and DC responses into DRM responses. |
| 159 | * |
| 160 | * The root control structure is &struct amdgpu_display_manager. |
| 161 | */ |
| 162 | |
| 163 | /* basic init/fini API */ |
| 164 | static int amdgpu_dm_init(struct amdgpu_device *adev); |
| 165 | static void amdgpu_dm_fini(struct amdgpu_device *adev); |
| 166 | static bool_Bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector); |
| 167 | |
| 168 | static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link) |
| 169 | { |
| 170 | switch (link->dpcd_caps.dongle_type) { |
| 171 | case DISPLAY_DONGLE_NONE: |
| 172 | return DRM_MODE_SUBCONNECTOR_Native; |
| 173 | case DISPLAY_DONGLE_DP_VGA_CONVERTER: |
| 174 | return DRM_MODE_SUBCONNECTOR_VGA; |
| 175 | case DISPLAY_DONGLE_DP_DVI_CONVERTER: |
| 176 | case DISPLAY_DONGLE_DP_DVI_DONGLE: |
| 177 | return DRM_MODE_SUBCONNECTOR_DVID; |
| 178 | case DISPLAY_DONGLE_DP_HDMI_CONVERTER: |
| 179 | case DISPLAY_DONGLE_DP_HDMI_DONGLE: |
| 180 | return DRM_MODE_SUBCONNECTOR_HDMIA; |
| 181 | case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: |
| 182 | default: |
| 183 | return DRM_MODE_SUBCONNECTOR_Unknown; |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) |
| 188 | { |
| 189 | struct dc_link *link = aconnector->dc_link; |
| 190 | struct drm_connector *connector = &aconnector->base; |
| 191 | enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; |
| 192 | |
| 193 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort10) |
| 194 | return; |
| 195 | |
| 196 | if (aconnector->dc_sink) |
| 197 | subconnector = get_subconnector_type(link); |
| 198 | |
| 199 | drm_object_property_set_value(&connector->base, |
| 200 | connector->dev->mode_config.dp_subconnector_property, |
| 201 | subconnector); |
| 202 | } |
| 203 | |
| 204 | /* |
| 205 | * initializes drm_device display related structures, based on the information |
| 206 | * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, |
| 207 | * drm_encoder, drm_mode_config |
| 208 | * |
| 209 | * Returns 0 on success |
| 210 | */ |
| 211 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); |
| 212 | /* removes and deallocates the drm structures, created by the above function */ |
| 213 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); |
| 214 | |
| 215 | static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, |
| 216 | struct amdgpu_dm_connector *amdgpu_dm_connector, |
| 217 | u32 link_index, |
| 218 | struct amdgpu_encoder *amdgpu_encoder); |
| 219 | static int amdgpu_dm_encoder_init(struct drm_device *dev, |
| 220 | struct amdgpu_encoder *aencoder, |
| 221 | uint32_t link_index); |
| 222 | |
| 223 | static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); |
| 224 | |
| 225 | static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); |
| 226 | |
| 227 | static int amdgpu_dm_atomic_check(struct drm_device *dev, |
| 228 | struct drm_atomic_state *state); |
| 229 | |
| 230 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); |
| 231 | static void handle_hpd_rx_irq(void *param); |
| 232 | |
| 233 | static bool_Bool |
| 234 | is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, |
| 235 | struct drm_crtc_state *new_crtc_state); |
| 236 | /* |
| 237 | * dm_vblank_get_counter |
| 238 | * |
| 239 | * @brief |
| 240 | * Get counter for number of vertical blanks |
| 241 | * |
| 242 | * @param |
| 243 | * struct amdgpu_device *adev - [in] desired amdgpu device |
| 244 | * int disp_idx - [in] which CRTC to get the counter from |
| 245 | * |
| 246 | * @return |
| 247 | * Counter for vertical blanks |
| 248 | */ |
| 249 | static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) |
| 250 | { |
| 251 | if (crtc >= adev->mode_info.num_crtc) |
| 252 | return 0; |
| 253 | else { |
| 254 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; |
| 255 | |
| 256 | if (acrtc->dm_irq_params.stream == NULL((void *)0)) { |
| 257 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc) |
| 258 | crtc)__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc); |
| 259 | return 0; |
| 260 | } |
| 261 | |
| 262 | return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); |
| 263 | } |
| 264 | } |
| 265 | |
| 266 | static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, |
| 267 | u32 *vbl, u32 *position) |
| 268 | { |
| 269 | u32 v_blank_start, v_blank_end, h_position, v_position; |
| 270 | |
| 271 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
| 272 | return -EINVAL22; |
| 273 | else { |
| 274 | struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; |
| 275 | |
| 276 | if (acrtc->dm_irq_params.stream == NULL((void *)0)) { |
| 277 | DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc) |
| 278 | crtc)__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc); |
| 279 | return 0; |
| 280 | } |
| 281 | |
| 282 | /* |
| 283 | * TODO rework base driver to use values directly. |
| 284 | * for now parse it back into reg-format |
| 285 | */ |
| 286 | dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, |
| 287 | &v_blank_start, |
| 288 | &v_blank_end, |
| 289 | &h_position, |
| 290 | &v_position); |
| 291 | |
| 292 | *position = v_position | (h_position << 16); |
| 293 | *vbl = v_blank_start | (v_blank_end << 16); |
| 294 | } |
| 295 | |
| 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | static bool_Bool dm_is_idle(void *handle) |
| 300 | { |
| 301 | /* XXX todo */ |
| 302 | return true1; |
| 303 | } |
| 304 | |
| 305 | static int dm_wait_for_idle(void *handle) |
| 306 | { |
| 307 | /* XXX todo */ |
| 308 | return 0; |
| 309 | } |
| 310 | |
| 311 | static bool_Bool dm_check_soft_reset(void *handle) |
| 312 | { |
| 313 | return false0; |
| 314 | } |
| 315 | |
| 316 | static int dm_soft_reset(void *handle) |
| 317 | { |
| 318 | /* XXX todo */ |
| 319 | return 0; |
| 320 | } |
| 321 | |
| 322 | static struct amdgpu_crtc * |
| 323 | get_crtc_by_otg_inst(struct amdgpu_device *adev, |
| 324 | int otg_inst) |
| 325 | { |
| 326 | struct drm_device *dev = adev_to_drm(adev); |
| 327 | struct drm_crtc *crtc; |
| 328 | struct amdgpu_crtc *amdgpu_crtc; |
| 329 | |
| 330 | if (WARN_ON(otg_inst == -1)({ int __ret = !!(otg_inst == -1); if (__ret) printf("WARNING %s failed at %s:%d\n" , "otg_inst == -1", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 330); __builtin_expect(!!(__ret), 0); })) |
| 331 | return adev->mode_info.crtcs[0]; |
| 332 | |
| 333 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head ) *__mptr = ((&dev->mode_config.crtc_list)->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof (*crtc), head) );}); &crtc->head != (&dev->mode_config .crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0) ->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) * )( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head) );})) { |
| 334 | amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_crtc, base) );}); |
| 335 | |
| 336 | if (amdgpu_crtc->otg_inst == otg_inst) |
| 337 | return amdgpu_crtc; |
| 338 | } |
| 339 | |
| 340 | return NULL((void *)0); |
| 341 | } |
| 342 | |
| 343 | static inline bool_Bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state, |
| 344 | struct dm_crtc_state *new_state) |
| 345 | { |
| 346 | if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) |
| 347 | return true1; |
| 348 | else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state)) |
| 349 | return true1; |
| 350 | else |
| 351 | return false0; |
| 352 | } |
| 353 | |
| 354 | static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update, |
| 355 | int planes_count) |
| 356 | { |
| 357 | int i, j; |
| 358 | struct dc_surface_update surface_updates_temp; |
| 359 | |
| 360 | for (i = 0, j = planes_count - 1; i < j; i++, j--) { |
| 361 | surface_updates_temp = array_of_surface_update[i]; |
| 362 | array_of_surface_update[i] = array_of_surface_update[j]; |
| 363 | array_of_surface_update[j] = surface_updates_temp; |
| 364 | } |
| 365 | } |
| 366 | |
| 367 | /** |
| 368 | * update_planes_and_stream_adapter() - Send planes to be updated in DC |
| 369 | * |
| 370 | * DC has a generic way to update planes and stream via |
| 371 | * dc_update_planes_and_stream function; however, DM might need some |
| 372 | * adjustments and preparation before calling it. This function is a wrapper |
| 373 | * for the dc_update_planes_and_stream that does any required configuration |
| 374 | * before passing control to DC. |
| 375 | */ |
| 376 | static inline bool_Bool update_planes_and_stream_adapter(struct dc *dc, |
| 377 | int update_type, |
| 378 | int planes_count, |
| 379 | struct dc_stream_state *stream, |
| 380 | struct dc_stream_update *stream_update, |
| 381 | struct dc_surface_update *array_of_surface_update) |
| 382 | { |
| 383 | reverse_planes_order(array_of_surface_update, planes_count); |
| 384 | |
| 385 | /* |
| 386 | * Previous frame finished and HW is ready for optimization. |
| 387 | */ |
| 388 | if (update_type == UPDATE_TYPE_FAST) |
| 389 | dc_post_update_surfaces_to_stream(dc); |
| 390 | |
| 391 | return dc_update_planes_and_stream(dc, |
| 392 | array_of_surface_update, |
| 393 | planes_count, |
| 394 | stream, |
| 395 | stream_update); |
| 396 | } |
| 397 | |
| 398 | /** |
| 399 | * dm_pflip_high_irq() - Handle pageflip interrupt |
| 400 | * @interrupt_params: ignored |
| 401 | * |
| 402 | * Handles the pageflip interrupt by notifying all interested parties |
| 403 | * that the pageflip has been completed. |
| 404 | */ |
| 405 | static void dm_pflip_high_irq(void *interrupt_params) |
| 406 | { |
| 407 | struct amdgpu_crtc *amdgpu_crtc; |
| 408 | struct common_irq_params *irq_params = interrupt_params; |
| 409 | struct amdgpu_device *adev = irq_params->adev; |
| 410 | unsigned long flags; |
| 411 | struct drm_pending_vblank_event *e; |
| 412 | u32 vpos, hpos, v_blank_start, v_blank_end; |
| 413 | bool_Bool vrr_active; |
| 414 | |
| 415 | amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); |
| 416 | |
| 417 | /* IRQ could occur when in initial stage */ |
| 418 | /* TODO work and BO cleanup */ |
| 419 | if (amdgpu_crtc == NULL((void *)0)) { |
| 420 | DC_LOG_PFLIP("CRTC is null, returning.\n")do { } while(0); |
| 421 | return; |
| 422 | } |
| 423 | |
| 424 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock ); } while (0); |
| 425 | |
| 426 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { |
| 427 | DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",do { } while(0) |
| 428 | amdgpu_crtc->pflip_status,do { } while(0) |
| 429 | AMDGPU_FLIP_SUBMITTED,do { } while(0) |
| 430 | amdgpu_crtc->crtc_id,do { } while(0) |
| 431 | amdgpu_crtc)do { } while(0); |
| 432 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock ); } while (0); |
| 433 | return; |
| 434 | } |
| 435 | |
| 436 | /* page flip completed. */ |
| 437 | e = amdgpu_crtc->event; |
| 438 | amdgpu_crtc->event = NULL((void *)0); |
| 439 | |
| 440 | WARN_ON(!e)({ int __ret = !!(!e); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!e", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 440); __builtin_expect(!!(__ret), 0); }); |
| 441 | |
| 442 | vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc); |
| 443 | |
| 444 | /* Fixed refresh rate, or VRR scanout position outside front-porch? */ |
| 445 | if (!vrr_active || |
| 446 | !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, |
| 447 | &v_blank_end, &hpos, &vpos) || |
| 448 | (vpos < v_blank_start)) { |
| 449 | /* Update to correct count and vblank timestamp if racing with |
| 450 | * vblank irq. This also updates to the correct vblank timestamp |
| 451 | * even in VRR mode, as scanout is past the front-porch atm. |
| 452 | */ |
| 453 | drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); |
| 454 | |
| 455 | /* Wake up userspace by sending the pageflip event with proper |
| 456 | * count and timestamp of vblank of flip completion. |
| 457 | */ |
| 458 | if (e) { |
| 459 | drm_crtc_send_vblank_event(&amdgpu_crtc->base, e); |
| 460 | |
| 461 | /* Event sent, so done with vblank for this flip */ |
| 462 | drm_crtc_vblank_put(&amdgpu_crtc->base); |
| 463 | } |
| 464 | } else if (e) { |
| 465 | /* VRR active and inside front-porch: vblank count and |
| 466 | * timestamp for pageflip event will only be up to date after |
| 467 | * drm_crtc_handle_vblank() has been executed from late vblank |
| 468 | * irq handler after start of back-porch (vline 0). We queue the |
| 469 | * pageflip event for send-out by drm_crtc_handle_vblank() with |
| 470 | * updated timestamp and count, once it runs after us. |
| 471 | * |
| 472 | * We need to open-code this instead of using the helper |
| 473 | * drm_crtc_arm_vblank_event(), as that helper would |
| 474 | * call drm_crtc_accurate_vblank_count(), which we must |
| 475 | * not call in VRR mode while we are in front-porch! |
| 476 | */ |
| 477 | |
| 478 | /* sequence will be replaced by real count during send-out. */ |
| 479 | e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base); |
| 480 | e->pipe = amdgpu_crtc->crtc_id; |
| 481 | |
| 482 | list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list); |
| 483 | e = NULL((void *)0); |
| 484 | } |
| 485 | |
| 486 | /* Keep track of vblank of this flip for flip throttling. We use the |
| 487 | * cooked hw counter, as that one incremented at start of this vblank |
| 488 | * of pageflip completion, so last_flip_vblank is the forbidden count |
| 489 | * for queueing new pageflips if vsync + VRR is enabled. |
| 490 | */ |
| 491 | amdgpu_crtc->dm_irq_params.last_flip_vblank = |
| 492 | amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base); |
| 493 | |
| 494 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
| 495 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock ); } while (0); |
| 496 | |
| 497 | DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",do { } while(0) |
| 498 | amdgpu_crtc->crtc_id, amdgpu_crtc,do { } while(0) |
| 499 | vrr_active, (int) !e)do { } while(0); |
| 500 | } |
| 501 | |
| 502 | static void dm_vupdate_high_irq(void *interrupt_params) |
| 503 | { |
| 504 | struct common_irq_params *irq_params = interrupt_params; |
| 505 | struct amdgpu_device *adev = irq_params->adev; |
| 506 | struct amdgpu_crtc *acrtc; |
| 507 | struct drm_device *drm_dev; |
| 508 | struct drm_vblank_crtc *vblank; |
| 509 | ktime_t frame_duration_ns, previous_timestamp; |
| 510 | unsigned long flags; |
| 511 | int vrr_active; |
| 512 | |
| 513 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); |
| 514 | |
| 515 | if (acrtc) { |
| 516 | vrr_active = amdgpu_dm_vrr_active_irq(acrtc); |
| 517 | drm_dev = acrtc->base.dev; |
| 518 | vblank = &drm_dev->vblank[acrtc->base.index]; |
| 519 | previous_timestamp = atomic64_read(&irq_params->previous_timestamp)({ typeof(*(&irq_params->previous_timestamp)) __tmp = * (volatile typeof(*(&irq_params->previous_timestamp)) * )&(*(&irq_params->previous_timestamp)); membar_datadep_consumer (); __tmp; }); |
| 520 | frame_duration_ns = vblank->time - previous_timestamp; |
| 521 | |
| 522 | if (frame_duration_ns > 0) { |
| 523 | trace_amdgpu_refresh_rate_track(acrtc->base.index, |
| 524 | frame_duration_ns, |
| 525 | ktime_divns(NSEC_PER_SEC1000000000L, frame_duration_ns)); |
| 526 | atomic64_set(&irq_params->previous_timestamp, vblank->time)({ typeof(*(&irq_params->previous_timestamp)) __tmp = ( (vblank->time)); *(volatile typeof(*(&irq_params->previous_timestamp )) *)&(*(&irq_params->previous_timestamp)) = __tmp ; __tmp; }); |
| 527 | } |
| 528 | |
| 529 | DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",do { } while(0) |
| 530 | acrtc->crtc_id,do { } while(0) |
| 531 | vrr_active)do { } while(0); |
| 532 | |
| 533 | /* Core vblank handling is done here after end of front-porch in |
| 534 | * vrr mode, as vblank timestamping will give valid results |
| 535 | * while now done after front-porch. This will also deliver |
| 536 | * page-flip completion events that have been queued to us |
| 537 | * if a pageflip happened inside front-porch. |
| 538 | */ |
| 539 | if (vrr_active) { |
| 540 | dm_crtc_handle_vblank(acrtc); |
| 541 | |
| 542 | /* BTR processing for pre-DCE12 ASICs */ |
| 543 | if (acrtc->dm_irq_params.stream && |
| 544 | adev->family < AMDGPU_FAMILY_AI141) { |
| 545 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock ); } while (0); |
| 546 | mod_freesync_handle_v_update( |
| 547 | adev->dm.freesync_module, |
| 548 | acrtc->dm_irq_params.stream, |
| 549 | &acrtc->dm_irq_params.vrr_params); |
| 550 | |
| 551 | dc_stream_adjust_vmin_vmax( |
| 552 | adev->dm.dc, |
| 553 | acrtc->dm_irq_params.stream, |
| 554 | &acrtc->dm_irq_params.vrr_params.adjust); |
| 555 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock ); } while (0); |
| 556 | } |
| 557 | } |
| 558 | } |
| 559 | } |
| 560 | |
| 561 | /** |
| 562 | * dm_crtc_high_irq() - Handles CRTC interrupt |
| 563 | * @interrupt_params: used for determining the CRTC instance |
| 564 | * |
| 565 | * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK |
| 566 | * event handler. |
| 567 | */ |
| 568 | static void dm_crtc_high_irq(void *interrupt_params) |
| 569 | { |
| 570 | struct common_irq_params *irq_params = interrupt_params; |
| 571 | struct amdgpu_device *adev = irq_params->adev; |
| 572 | struct amdgpu_crtc *acrtc; |
| 573 | unsigned long flags; |
| 574 | int vrr_active; |
| 575 | |
| 576 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); |
| 577 | if (!acrtc) |
| 578 | return; |
| 579 | |
| 580 | vrr_active = amdgpu_dm_vrr_active_irq(acrtc); |
| 581 | |
| 582 | DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,do { } while(0) |
| 583 | vrr_active, acrtc->dm_irq_params.active_planes)do { } while(0); |
| 584 | |
| 585 | /** |
| 586 | * Core vblank handling at start of front-porch is only possible |
| 587 | * in non-vrr mode, as only there vblank timestamping will give |
| 588 | * valid results while done in front-porch. Otherwise defer it |
| 589 | * to dm_vupdate_high_irq after end of front-porch. |
| 590 | */ |
| 591 | if (!vrr_active) |
| 592 | dm_crtc_handle_vblank(acrtc); |
| 593 | |
| 594 | /** |
| 595 | * Following stuff must happen at start of vblank, for crc |
| 596 | * computation and below-the-range btr support in vrr mode. |
| 597 | */ |
| 598 | amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); |
| 599 | |
| 600 | /* BTR updates need to happen before VUPDATE on Vega and above. */ |
| 601 | if (adev->family < AMDGPU_FAMILY_AI141) |
| 602 | return; |
| 603 | |
| 604 | spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock ); } while (0); |
| 605 | |
| 606 | if (acrtc->dm_irq_params.stream && |
| 607 | acrtc->dm_irq_params.vrr_params.supported && |
| 608 | acrtc->dm_irq_params.freesync_config.state == |
| 609 | VRR_STATE_ACTIVE_VARIABLE) { |
| 610 | mod_freesync_handle_v_update(adev->dm.freesync_module, |
| 611 | acrtc->dm_irq_params.stream, |
| 612 | &acrtc->dm_irq_params.vrr_params); |
| 613 | |
| 614 | dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream, |
| 615 | &acrtc->dm_irq_params.vrr_params.adjust); |
| 616 | } |
| 617 | |
| 618 | /* |
| 619 | * If there aren't any active_planes then DCH HUBP may be clock-gated. |
| 620 | * In that case, pageflip completion interrupts won't fire and pageflip |
| 621 | * completion events won't get delivered. Prevent this by sending |
| 622 | * pending pageflip events from here if a flip is still pending. |
| 623 | * |
| 624 | * If any planes are enabled, use dm_pflip_high_irq() instead, to |
| 625 | * avoid race conditions between flip programming and completion, |
| 626 | * which could cause too early flip completion events. |
| 627 | */ |
| 628 | if (adev->family >= AMDGPU_FAMILY_RV142 && |
| 629 | acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED && |
| 630 | acrtc->dm_irq_params.active_planes == 0) { |
| 631 | if (acrtc->event) { |
| 632 | drm_crtc_send_vblank_event(&acrtc->base, acrtc->event); |
| 633 | acrtc->event = NULL((void *)0); |
| 634 | drm_crtc_vblank_put(&acrtc->base); |
| 635 | } |
| 636 | acrtc->pflip_status = AMDGPU_FLIP_NONE; |
| 637 | } |
| 638 | |
| 639 | spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock ); } while (0); |
| 640 | } |
| 641 | |
| 642 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 643 | /** |
| 644 | * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for |
| 645 | * DCN generation ASICs |
| 646 | * @interrupt_params: interrupt parameters |
| 647 | * |
| 648 | * Used to set crc window/read out crc value at vertical line 0 position |
| 649 | */ |
| 650 | static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params) |
| 651 | { |
| 652 | struct common_irq_params *irq_params = interrupt_params; |
| 653 | struct amdgpu_device *adev = irq_params->adev; |
| 654 | struct amdgpu_crtc *acrtc; |
| 655 | |
| 656 | acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0); |
| 657 | |
| 658 | if (!acrtc) |
| 659 | return; |
| 660 | |
| 661 | amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base); |
| 662 | } |
| 663 | #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */ |
| 664 | |
| 665 | /** |
| 666 | * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command. |
| 667 | * @adev: amdgpu_device pointer |
| 668 | * @notify: dmub notification structure |
| 669 | * |
| 670 | * Dmub AUX or SET_CONFIG command completion processing callback |
| 671 | * Copies dmub notification to DM which is to be read by AUX command. |
| 672 | * issuing thread and also signals the event to wake up the thread. |
| 673 | */ |
| 674 | static void dmub_aux_setconfig_callback(struct amdgpu_device *adev, |
| 675 | struct dmub_notification *notify) |
| 676 | { |
| 677 | if (adev->dm.dmub_notify) |
| 678 | memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification))__builtin_memcpy((adev->dm.dmub_notify), (notify), (sizeof (struct dmub_notification))); |
| 679 | if (notify->type == DMUB_NOTIFICATION_AUX_REPLY) |
| 680 | complete(&adev->dm.dmub_aux_transfer_done); |
| 681 | } |
| 682 | |
| 683 | /** |
| 684 | * dmub_hpd_callback - DMUB HPD interrupt processing callback. |
| 685 | * @adev: amdgpu_device pointer |
| 686 | * @notify: dmub notification structure |
| 687 | * |
| 688 | * Dmub Hpd interrupt processing callback. Gets displayindex through the |
| 689 | * ink index and calls helper to do the processing. |
| 690 | */ |
| 691 | static void dmub_hpd_callback(struct amdgpu_device *adev, |
| 692 | struct dmub_notification *notify) |
| 693 | { |
| 694 | struct amdgpu_dm_connector *aconnector; |
| 695 | struct amdgpu_dm_connector *hpd_aconnector = NULL((void *)0); |
| 696 | struct drm_connector *connector; |
| 697 | struct drm_connector_list_iter iter; |
| 698 | struct dc_link *link; |
| 699 | u8 link_index = 0; |
| 700 | struct drm_device *dev; |
| 701 | |
| 702 | if (adev == NULL((void *)0)) |
| 703 | return; |
| 704 | |
| 705 | if (notify == NULL((void *)0)) { |
| 706 | DRM_ERROR("DMUB HPD callback notification was NULL")__drm_err("DMUB HPD callback notification was NULL"); |
| 707 | return; |
| 708 | } |
| 709 | |
| 710 | if (notify->link_index > adev->dm.dc->link_count) { |
| 711 | DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index)__drm_err("DMUB HPD index (%u)is abnormal", notify->link_index ); |
| 712 | return; |
| 713 | } |
| 714 | |
| 715 | link_index = notify->link_index; |
| 716 | link = adev->dm.dc->links[link_index]; |
| 717 | dev = adev->dm.ddev; |
| 718 | |
| 719 | drm_connector_list_iter_begin(dev, &iter); |
| 720 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 721 | aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 722 | if (link && aconnector->dc_link == link) { |
| 723 | DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index)printk("\0016" "[" "drm" "] " "DMUB HPD callback: link_index=%u\n" , link_index); |
| 724 | hpd_aconnector = aconnector; |
| 725 | break; |
| 726 | } |
| 727 | } |
| 728 | drm_connector_list_iter_end(&iter); |
| 729 | |
| 730 | if (hpd_aconnector) { |
| 731 | if (notify->type == DMUB_NOTIFICATION_HPD) |
| 732 | handle_hpd_irq_helper(hpd_aconnector); |
| 733 | else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) |
| 734 | handle_hpd_rx_irq(hpd_aconnector); |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | /** |
| 739 | * register_dmub_notify_callback - Sets callback for DMUB notify |
| 740 | * @adev: amdgpu_device pointer |
| 741 | * @type: Type of dmub notification |
| 742 | * @callback: Dmub interrupt callback function |
| 743 | * @dmub_int_thread_offload: offload indicator |
| 744 | * |
| 745 | * API to register a dmub callback handler for a dmub notification |
| 746 | * Also sets indicator whether callback processing to be offloaded. |
| 747 | * to dmub interrupt handling thread |
| 748 | * Return: true if successfully registered, false if there is existing registration |
| 749 | */ |
| 750 | static bool_Bool register_dmub_notify_callback(struct amdgpu_device *adev, |
| 751 | enum dmub_notification_type type, |
| 752 | dmub_notify_interrupt_callback_t callback, |
| 753 | bool_Bool dmub_int_thread_offload) |
| 754 | { |
| 755 | if (callback != NULL((void *)0) && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)(sizeof((adev->dm.dmub_thread_offload)) / sizeof((adev-> dm.dmub_thread_offload)[0]))) { |
| 756 | adev->dm.dmub_callback[type] = callback; |
| 757 | adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload; |
| 758 | } else |
| 759 | return false0; |
| 760 | |
| 761 | return true1; |
| 762 | } |
| 763 | |
| 764 | static void dm_handle_hpd_work(struct work_struct *work) |
| 765 | { |
| 766 | struct dmub_hpd_work *dmub_hpd_wrk; |
| 767 | |
| 768 | dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work)({ const __typeof( ((struct dmub_hpd_work *)0)->handle_hpd_work ) *__mptr = (work); (struct dmub_hpd_work *)( (char *)__mptr - __builtin_offsetof(struct dmub_hpd_work, handle_hpd_work) ) ;}); |
| 769 | |
| 770 | if (!dmub_hpd_wrk->dmub_notify) { |
| 771 | DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL")__drm_err("dmub_hpd_wrk dmub_notify is NULL"); |
| 772 | return; |
| 773 | } |
| 774 | |
| 775 | if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)(sizeof((dmub_hpd_wrk->adev->dm.dmub_callback)) / sizeof ((dmub_hpd_wrk->adev->dm.dmub_callback)[0]))) { |
| 776 | dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev, |
| 777 | dmub_hpd_wrk->dmub_notify); |
| 778 | } |
| 779 | |
| 780 | kfree(dmub_hpd_wrk->dmub_notify); |
| 781 | kfree(dmub_hpd_wrk); |
| 782 | |
| 783 | } |
| 784 | |
| 785 | #define DMUB_TRACE_MAX_READ64 64 |
| 786 | /** |
| 787 | * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt |
| 788 | * @interrupt_params: used for determining the Outbox instance |
| 789 | * |
| 790 | * Handles the Outbox Interrupt |
| 791 | * event handler. |
| 792 | */ |
| 793 | static void dm_dmub_outbox1_low_irq(void *interrupt_params) |
| 794 | { |
| 795 | struct dmub_notification notify; |
| 796 | struct common_irq_params *irq_params = interrupt_params; |
| 797 | struct amdgpu_device *adev = irq_params->adev; |
| 798 | struct amdgpu_display_manager *dm = &adev->dm; |
| 799 | struct dmcub_trace_buf_entry entry = { 0 }; |
| 800 | u32 count = 0; |
| 801 | struct dmub_hpd_work *dmub_hpd_wrk; |
| 802 | struct dc_link *plink = NULL((void *)0); |
| 803 | |
| 804 | if (dc_enable_dmub_notifications(adev->dm.dc) && |
| 805 | irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) { |
| 806 | |
| 807 | do { |
| 808 | dc_stat_get_dmub_notification(adev->dm.dc, ¬ify); |
| 809 | if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)(sizeof((dm->dmub_thread_offload)) / sizeof((dm->dmub_thread_offload )[0]))) { |
| 810 | DRM_ERROR("DM: notify type %d invalid!", notify.type)__drm_err("DM: notify type %d invalid!", notify.type); |
| 811 | continue; |
| 812 | } |
| 813 | if (!dm->dmub_callback[notify.type]) { |
| 814 | DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DMUB notification skipped, no handler: type=%d\n" , notify.type); |
| 815 | continue; |
| 816 | } |
| 817 | if (dm->dmub_thread_offload[notify.type] == true1) { |
| 818 | dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC0x0002); |
| 819 | if (!dmub_hpd_wrk) { |
| 820 | DRM_ERROR("Failed to allocate dmub_hpd_wrk")__drm_err("Failed to allocate dmub_hpd_wrk"); |
| 821 | return; |
| 822 | } |
| 823 | dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC0x0002); |
| 824 | if (!dmub_hpd_wrk->dmub_notify) { |
| 825 | kfree(dmub_hpd_wrk); |
| 826 | DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify")__drm_err("Failed to allocate dmub_hpd_wrk->dmub_notify"); |
| 827 | return; |
| 828 | } |
| 829 | INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work); |
| 830 | if (dmub_hpd_wrk->dmub_notify) |
| 831 | memcpy(dmub_hpd_wrk->dmub_notify, ¬ify, sizeof(struct dmub_notification))__builtin_memcpy((dmub_hpd_wrk->dmub_notify), (¬ify ), (sizeof(struct dmub_notification))); |
| 832 | dmub_hpd_wrk->adev = adev; |
| 833 | if (notify.type == DMUB_NOTIFICATION_HPD) { |
| 834 | plink = adev->dm.dc->links[notify.link_index]; |
| 835 | if (plink) { |
| 836 | plink->hpd_status = |
| 837 | notify.hpd_status == DP_HPD_PLUG; |
| 838 | } |
| 839 | } |
| 840 | queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work); |
| 841 | } else { |
| 842 | dm->dmub_callback[notify.type](adev, ¬ify); |
| 843 | } |
| 844 | } while (notify.pending_notification); |
| 845 | } |
| 846 | |
| 847 | |
| 848 | do { |
| 849 | if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) { |
| 850 | trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count, |
| 851 | entry.param0, entry.param1); |
| 852 | |
| 853 | DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "trace_code:%u, tick_count:%u, param0:%u, param1:%u\n" , entry.trace_code, entry.tick_count, entry.param0, entry.param1 ) |
| 854 | entry.trace_code, entry.tick_count, entry.param0, entry.param1)___drm_dbg(((void *)0), DRM_UT_DRIVER, "trace_code:%u, tick_count:%u, param0:%u, param1:%u\n" , entry.trace_code, entry.tick_count, entry.param0, entry.param1 ); |
| 855 | } else |
| 856 | break; |
| 857 | |
| 858 | count++; |
| 859 | |
| 860 | } while (count <= DMUB_TRACE_MAX_READ64); |
| 861 | |
| 862 | if (count > DMUB_TRACE_MAX_READ64) |
| 863 | DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ")___drm_dbg(((void *)0), DRM_UT_DRIVER, "Warning : count > DMUB_TRACE_MAX_READ" ); |
| 864 | } |
| 865 | |
| 866 | static int dm_set_clockgating_state(void *handle, |
| 867 | enum amd_clockgating_state state) |
| 868 | { |
| 869 | return 0; |
| 870 | } |
| 871 | |
| 872 | static int dm_set_powergating_state(void *handle, |
| 873 | enum amd_powergating_state state) |
| 874 | { |
| 875 | return 0; |
| 876 | } |
| 877 | |
| 878 | /* Prototypes of private functions */ |
| 879 | static int dm_early_init(void *handle); |
| 880 | |
| 881 | /* Allocate memory for FBC compressed data */ |
| 882 | static void amdgpu_dm_fbc_init(struct drm_connector *connector) |
| 883 | { |
| 884 | struct drm_device *dev = connector->dev; |
| 885 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 886 | struct dm_compressor_info *compressor = &adev->dm.compressor; |
| 887 | struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 888 | struct drm_display_mode *mode; |
| 889 | unsigned long max_size = 0; |
| 890 | |
| 891 | if (adev->dm.dc->fbc_compressor == NULL((void *)0)) |
| 892 | return; |
| 893 | |
| 894 | if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP) |
| 895 | return; |
| 896 | |
| 897 | if (compressor->bo_ptr) |
| 898 | return; |
| 899 | |
| 900 | |
| 901 | list_for_each_entry(mode, &connector->modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&connector->modes)->next); (__typeof (*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode ), head) );}); &mode->head != (&connector->modes ); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char * )__mptr - __builtin_offsetof(__typeof(*mode), head) );})) { |
| 902 | if (max_size < mode->htotal * mode->vtotal) |
| 903 | max_size = mode->htotal * mode->vtotal; |
| 904 | } |
| 905 | |
| 906 | if (max_size) { |
| 907 | int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE(1 << 12), |
| 908 | AMDGPU_GEM_DOMAIN_GTT0x2, &compressor->bo_ptr, |
| 909 | &compressor->gpu_addr, &compressor->cpu_addr); |
| 910 | |
| 911 | if (r) |
| 912 | DRM_ERROR("DM: Failed to initialize FBC\n")__drm_err("DM: Failed to initialize FBC\n"); |
| 913 | else { |
| 914 | adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr; |
| 915 | DRM_INFO("DM: FBC alloc %lu\n", max_size*4)printk("\0016" "[" "drm" "] " "DM: FBC alloc %lu\n", max_size *4); |
| 916 | } |
| 917 | |
| 918 | } |
| 919 | |
| 920 | } |
| 921 | |
| 922 | static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, |
| 923 | int pipe, bool_Bool *enabled, |
| 924 | unsigned char *buf, int max_bytes) |
| 925 | { |
| 926 | struct drm_device *dev = dev_get_drvdata(kdev); |
| 927 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 928 | struct drm_connector *connector; |
| 929 | struct drm_connector_list_iter conn_iter; |
| 930 | struct amdgpu_dm_connector *aconnector; |
| 931 | int ret = 0; |
| 932 | |
| 933 | *enabled = false0; |
| 934 | |
| 935 | mutex_lock(&adev->dm.audio_lock)rw_enter_write(&adev->dm.audio_lock); |
| 936 | |
| 937 | drm_connector_list_iter_begin(dev, &conn_iter); |
| 938 | drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter ))) { |
| 939 | aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 940 | if (aconnector->audio_inst != port) |
| 941 | continue; |
| 942 | |
| 943 | *enabled = true1; |
| 944 | ret = drm_eld_size(connector->eld); |
| 945 | memcpy(buf, connector->eld, min(max_bytes, ret))__builtin_memcpy((buf), (connector->eld), ((((max_bytes)< (ret))?(max_bytes):(ret)))); |
| 946 | |
| 947 | break; |
| 948 | } |
| 949 | drm_connector_list_iter_end(&conn_iter); |
| 950 | |
| 951 | mutex_unlock(&adev->dm.audio_lock)rw_exit_write(&adev->dm.audio_lock); |
| 952 | |
| 953 | DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled)___drm_dbg(((void *)0), DRM_UT_KMS, "Get ELD : idx=%d ret=%d en=%d\n" , port, ret, *enabled); |
| 954 | |
| 955 | return ret; |
| 956 | } |
| 957 | |
| 958 | static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { |
| 959 | .get_eld = amdgpu_dm_audio_component_get_eld, |
| 960 | }; |
| 961 | |
| 962 | static int amdgpu_dm_audio_component_bind(struct device *kdev, |
| 963 | struct device *hda_kdev, void *data) |
| 964 | { |
| 965 | struct drm_device *dev = dev_get_drvdata(kdev); |
| 966 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 967 | struct drm_audio_component *acomp = data; |
| 968 | |
| 969 | acomp->ops = &amdgpu_dm_audio_component_ops; |
| 970 | acomp->dev = kdev; |
| 971 | adev->dm.audio_component = acomp; |
| 972 | |
| 973 | return 0; |
| 974 | } |
| 975 | |
| 976 | static void amdgpu_dm_audio_component_unbind(struct device *kdev, |
| 977 | struct device *hda_kdev, void *data) |
| 978 | { |
| 979 | struct drm_device *dev = dev_get_drvdata(kdev); |
| 980 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 981 | struct drm_audio_component *acomp = data; |
| 982 | |
| 983 | acomp->ops = NULL((void *)0); |
| 984 | acomp->dev = NULL((void *)0); |
| 985 | adev->dm.audio_component = NULL((void *)0); |
| 986 | } |
| 987 | |
| 988 | static const struct component_ops amdgpu_dm_audio_component_bind_ops = { |
| 989 | .bind = amdgpu_dm_audio_component_bind, |
| 990 | .unbind = amdgpu_dm_audio_component_unbind, |
| 991 | }; |
| 992 | |
| 993 | static int amdgpu_dm_audio_init(struct amdgpu_device *adev) |
| 994 | { |
| 995 | int i, ret; |
| 996 | |
| 997 | if (!amdgpu_audio) |
| 998 | return 0; |
| 999 | |
| 1000 | adev->mode_info.audio.enabled = true1; |
| 1001 | |
| 1002 | adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; |
| 1003 | |
| 1004 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 1005 | adev->mode_info.audio.pin[i].channels = -1; |
| 1006 | adev->mode_info.audio.pin[i].rate = -1; |
| 1007 | adev->mode_info.audio.pin[i].bits_per_sample = -1; |
| 1008 | adev->mode_info.audio.pin[i].status_bits = 0; |
| 1009 | adev->mode_info.audio.pin[i].category_code = 0; |
| 1010 | adev->mode_info.audio.pin[i].connected = false0; |
| 1011 | adev->mode_info.audio.pin[i].id = |
| 1012 | adev->dm.dc->res_pool->audios[i]->inst; |
| 1013 | adev->mode_info.audio.pin[i].offset = 0; |
| 1014 | } |
| 1015 | |
| 1016 | ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops)0; |
| 1017 | if (ret < 0) |
| 1018 | return ret; |
| 1019 | |
| 1020 | adev->dm.audio_registered = true1; |
| 1021 | |
| 1022 | return 0; |
| 1023 | } |
| 1024 | |
| 1025 | static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) |
| 1026 | { |
| 1027 | if (!amdgpu_audio) |
| 1028 | return; |
| 1029 | |
| 1030 | if (!adev->mode_info.audio.enabled) |
| 1031 | return; |
| 1032 | |
| 1033 | if (adev->dm.audio_registered) { |
| 1034 | component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); |
| 1035 | adev->dm.audio_registered = false0; |
| 1036 | } |
| 1037 | |
| 1038 | /* TODO: Disable audio? */ |
| 1039 | |
| 1040 | adev->mode_info.audio.enabled = false0; |
| 1041 | } |
| 1042 | |
| 1043 | static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) |
| 1044 | { |
| 1045 | struct drm_audio_component *acomp = adev->dm.audio_component; |
| 1046 | |
| 1047 | if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { |
| 1048 | DRM_DEBUG_KMS("Notify ELD: %d\n", pin)___drm_dbg(((void *)0), DRM_UT_KMS, "Notify ELD: %d\n", pin); |
| 1049 | |
| 1050 | acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, |
| 1051 | pin, -1); |
| 1052 | } |
| 1053 | } |
| 1054 | |
| 1055 | static int dm_dmub_hw_init(struct amdgpu_device *adev) |
| 1056 | { |
| 1057 | const struct dmcub_firmware_header_v1_0 *hdr; |
| 1058 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; |
| 1059 | struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; |
| 1060 | const struct firmware *dmub_fw = adev->dm.dmub_fw; |
| 1061 | struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; |
| 1062 | struct abm *abm = adev->dm.dc->res_pool->abm; |
| 1063 | struct dmub_srv_hw_params hw_params; |
| 1064 | enum dmub_status status; |
| 1065 | const unsigned char *fw_inst_const, *fw_bss_data; |
| 1066 | u32 i, fw_inst_const_size, fw_bss_data_size; |
| 1067 | bool_Bool has_hw_support; |
| 1068 | |
| 1069 | if (!dmub_srv) |
| 1070 | /* DMUB isn't supported on the ASIC. */ |
| 1071 | return 0; |
| 1072 | |
| 1073 | if (!fb_info) { |
| 1074 | DRM_ERROR("No framebuffer info for DMUB service.\n")__drm_err("No framebuffer info for DMUB service.\n"); |
| 1075 | return -EINVAL22; |
| 1076 | } |
| 1077 | |
| 1078 | if (!dmub_fw) { |
| 1079 | /* Firmware required for DMUB support. */ |
| 1080 | DRM_ERROR("No firmware provided for DMUB.\n")__drm_err("No firmware provided for DMUB.\n"); |
| 1081 | return -EINVAL22; |
| 1082 | } |
| 1083 | |
| 1084 | status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support); |
| 1085 | if (status != DMUB_STATUS_OK) { |
| 1086 | DRM_ERROR("Error checking HW support for DMUB: %d\n", status)__drm_err("Error checking HW support for DMUB: %d\n", status); |
| 1087 | return -EINVAL22; |
| 1088 | } |
| 1089 | |
| 1090 | if (!has_hw_support) { |
| 1091 | DRM_INFO("DMUB unsupported on ASIC\n")printk("\0016" "[" "drm" "] " "DMUB unsupported on ASIC\n"); |
| 1092 | return 0; |
| 1093 | } |
| 1094 | |
| 1095 | /* Reset DMCUB if it was previously running - before we overwrite its memory. */ |
| 1096 | status = dmub_srv_hw_reset(dmub_srv); |
| 1097 | if (status != DMUB_STATUS_OK) |
| 1098 | DRM_WARN("Error resetting DMUB HW: %d\n", status)printk("\0014" "[" "drm" "] " "Error resetting DMUB HW: %d\n" , status); |
| 1099 | |
| 1100 | hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data; |
| 1101 | |
| 1102 | fw_inst_const = dmub_fw->data + |
| 1103 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) + |
| 1104 | PSP_HEADER_BYTES0x100; |
| 1105 | |
| 1106 | fw_bss_data = dmub_fw->data + |
| 1107 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) + |
| 1108 | le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)); |
| 1109 | |
| 1110 | /* Copy firmware and bios info into FB memory. */ |
| 1111 | fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) - |
| 1112 | PSP_HEADER_BYTES0x100 - PSP_FOOTER_BYTES0x100; |
| 1113 | |
| 1114 | fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes)((__uint32_t)(hdr->bss_data_bytes)); |
| 1115 | |
| 1116 | /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP, |
| 1117 | * amdgpu_ucode_init_single_fw will load dmub firmware |
| 1118 | * fw_inst_const part to cw0; otherwise, the firmware back door load |
| 1119 | * will be done by dm_dmub_hw_init |
| 1120 | */ |
| 1121 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 1122 | memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr ), (fw_inst_const), (fw_inst_const_size)) |
| 1123 | fw_inst_const_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr ), (fw_inst_const), (fw_inst_const_size)); |
| 1124 | } |
| 1125 | |
| 1126 | if (fw_bss_data_size) |
| 1127 | memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr ), (fw_bss_data), (fw_bss_data_size)) |
| 1128 | fw_bss_data, fw_bss_data_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr ), (fw_bss_data), (fw_bss_data_size)); |
| 1129 | |
| 1130 | /* Copy firmware bios info into FB memory. */ |
| 1131 | memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr ), (adev->bios), (adev->bios_size)) |
| 1132 | adev->bios_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr ), (adev->bios), (adev->bios_size)); |
| 1133 | |
| 1134 | /* Reset regions that need to be reset. */ |
| 1135 | memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr ), (0), (fb_info->fb[DMUB_WINDOW_4_MAILBOX].size)) |
| 1136 | fb_info->fb[DMUB_WINDOW_4_MAILBOX].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr ), (0), (fb_info->fb[DMUB_WINDOW_4_MAILBOX].size)); |
| 1137 | |
| 1138 | memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr ), (0), (fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size)) |
| 1139 | fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr ), (0), (fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size)); |
| 1140 | |
| 1141 | memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr ), (0), (fb_info->fb[DMUB_WINDOW_6_FW_STATE].size)) |
| 1142 | fb_info->fb[DMUB_WINDOW_6_FW_STATE].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr ), (0), (fb_info->fb[DMUB_WINDOW_6_FW_STATE].size)); |
| 1143 | |
| 1144 | /* Initialize hardware. */ |
| 1145 | memset(&hw_params, 0, sizeof(hw_params))__builtin_memset((&hw_params), (0), (sizeof(hw_params))); |
| 1146 | hw_params.fb_base = adev->gmc.fb_start; |
| 1147 | hw_params.fb_offset = adev->gmc.aper_base; |
| 1148 | |
| 1149 | /* backdoor load firmware and trigger dmub running */ |
| 1150 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) |
| 1151 | hw_params.load_inst_const = true1; |
| 1152 | |
| 1153 | if (dmcu) |
| 1154 | hw_params.psp_version = dmcu->psp_version; |
| 1155 | |
| 1156 | for (i = 0; i < fb_info->num_fb; ++i) |
| 1157 | hw_params.fb[i] = &fb_info->fb[i]; |
| 1158 | |
| 1159 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 1160 | case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)): |
| 1161 | case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)): |
| 1162 | hw_params.dpia_supported = true1; |
| 1163 | hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; |
| 1164 | break; |
| 1165 | default: |
| 1166 | break; |
| 1167 | } |
| 1168 | |
| 1169 | status = dmub_srv_hw_init(dmub_srv, &hw_params); |
| 1170 | if (status != DMUB_STATUS_OK) { |
| 1171 | DRM_ERROR("Error initializing DMUB HW: %d\n", status)__drm_err("Error initializing DMUB HW: %d\n", status); |
| 1172 | return -EINVAL22; |
| 1173 | } |
| 1174 | |
| 1175 | /* Wait for firmware load to finish. */ |
| 1176 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); |
| 1177 | if (status != DMUB_STATUS_OK) |
| 1178 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status)printk("\0014" "[" "drm" "] " "Wait for DMUB auto-load failed: %d\n" , status); |
| 1179 | |
| 1180 | /* Init DMCU and ABM if available. */ |
| 1181 | if (dmcu && abm) { |
| 1182 | dmcu->funcs->dmcu_init(dmcu); |
| 1183 | abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); |
| 1184 | } |
| 1185 | |
| 1186 | if (!adev->dm.dc->ctx->dmub_srv) |
| 1187 | adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv); |
| 1188 | if (!adev->dm.dc->ctx->dmub_srv) { |
| 1189 | DRM_ERROR("Couldn't allocate DC DMUB server!\n")__drm_err("Couldn't allocate DC DMUB server!\n"); |
| 1190 | return -ENOMEM12; |
| 1191 | } |
| 1192 | |
| 1193 | DRM_INFO("DMUB hardware initialized: version=0x%08X\n",printk("\0016" "[" "drm" "] " "DMUB hardware initialized: version=0x%08X\n" , adev->dm.dmcub_fw_version) |
| 1194 | adev->dm.dmcub_fw_version)printk("\0016" "[" "drm" "] " "DMUB hardware initialized: version=0x%08X\n" , adev->dm.dmcub_fw_version); |
| 1195 | |
| 1196 | return 0; |
| 1197 | } |
| 1198 | |
| 1199 | static void dm_dmub_hw_resume(struct amdgpu_device *adev) |
| 1200 | { |
| 1201 | struct dmub_srv *dmub_srv = adev->dm.dmub_srv; |
| 1202 | enum dmub_status status; |
| 1203 | bool_Bool init; |
| 1204 | |
| 1205 | if (!dmub_srv) { |
| 1206 | /* DMUB isn't supported on the ASIC. */ |
| 1207 | return; |
| 1208 | } |
| 1209 | |
| 1210 | status = dmub_srv_is_hw_init(dmub_srv, &init); |
| 1211 | if (status != DMUB_STATUS_OK) |
| 1212 | DRM_WARN("DMUB hardware init check failed: %d\n", status)printk("\0014" "[" "drm" "] " "DMUB hardware init check failed: %d\n" , status); |
| 1213 | |
| 1214 | if (status == DMUB_STATUS_OK && init) { |
| 1215 | /* Wait for firmware load to finish. */ |
| 1216 | status = dmub_srv_wait_for_auto_load(dmub_srv, 100000); |
| 1217 | if (status != DMUB_STATUS_OK) |
| 1218 | DRM_WARN("Wait for DMUB auto-load failed: %d\n", status)printk("\0014" "[" "drm" "] " "Wait for DMUB auto-load failed: %d\n" , status); |
| 1219 | } else { |
| 1220 | /* Perform the full hardware initialization. */ |
| 1221 | dm_dmub_hw_init(adev); |
| 1222 | } |
| 1223 | } |
| 1224 | |
| 1225 | static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config) |
| 1226 | { |
| 1227 | u64 pt_base; |
| 1228 | u32 logical_addr_low; |
| 1229 | u32 logical_addr_high; |
| 1230 | u32 agp_base, agp_bot, agp_top; |
| 1231 | PHYSICAL_ADDRESS_LOCunion large_integer page_table_start, page_table_end, page_table_base; |
| 1232 | |
| 1233 | memset(pa_config, 0, sizeof(*pa_config))__builtin_memset((pa_config), (0), (sizeof(*pa_config))); |
| 1234 | |
| 1235 | agp_base = 0; |
| 1236 | agp_bot = adev->gmc.agp_start >> 24; |
| 1237 | agp_top = adev->gmc.agp_end >> 24; |
| 1238 | |
| 1239 | /* AGP aperture is disabled */ |
| 1240 | if (agp_bot == agp_top) { |
| 1241 | logical_addr_low = adev->gmc.vram_start >> 18; |
| 1242 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
| 1243 | /* |
| 1244 | * Raven2 has a HW issue that it is unable to use the vram which |
| 1245 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the |
| 1246 | * workaround that increase system aperture high address (add 1) |
| 1247 | * to get rid of the VM fault and hardware hang. |
| 1248 | */ |
| 1249 | logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1; |
| 1250 | else |
| 1251 | logical_addr_high = adev->gmc.vram_end >> 18; |
| 1252 | } else { |
| 1253 | logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start)(((adev->gmc.fb_start)<(adev->gmc.agp_start))?(adev-> gmc.fb_start):(adev->gmc.agp_start)) >> 18; |
| 1254 | if (adev->apu_flags & AMD_APU_IS_RAVEN2) |
| 1255 | /* |
| 1256 | * Raven2 has a HW issue that it is unable to use the vram which |
| 1257 | * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the |
| 1258 | * workaround that increase system aperture high address (add 1) |
| 1259 | * to get rid of the VM fault and hardware hang. |
| 1260 | */ |
| 1261 | logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18)((((adev->gmc.fb_end >> 18) + 0x1)>(adev->gmc. agp_end >> 18))?((adev->gmc.fb_end >> 18) + 0x1 ):(adev->gmc.agp_end >> 18)); |
| 1262 | else |
| 1263 | logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end)(((adev->gmc.fb_end)>(adev->gmc.agp_end))?(adev-> gmc.fb_end):(adev->gmc.agp_end)) >> 18; |
| 1264 | } |
| 1265 | |
| 1266 | pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); |
| 1267 | |
| 1268 | page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>((u32)(((adev->gmc.gart_start >> 12) >> 16) >> 16)) |
| 1269 | AMDGPU_GPU_PAGE_SHIFT)((u32)(((adev->gmc.gart_start >> 12) >> 16) >> 16)); |
| 1270 | page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>((u32)(adev->gmc.gart_start >> 12)) |
| 1271 | AMDGPU_GPU_PAGE_SHIFT)((u32)(adev->gmc.gart_start >> 12)); |
| 1272 | page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>((u32)(((adev->gmc.gart_end >> 12) >> 16) >> 16)) |
| 1273 | AMDGPU_GPU_PAGE_SHIFT)((u32)(((adev->gmc.gart_end >> 12) >> 16) >> 16)); |
| 1274 | page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>((u32)(adev->gmc.gart_end >> 12)) |
| 1275 | AMDGPU_GPU_PAGE_SHIFT)((u32)(adev->gmc.gart_end >> 12)); |
| 1276 | page_table_base.high_part = upper_32_bits(pt_base)((u32)(((pt_base) >> 16) >> 16)); |
| 1277 | page_table_base.low_part = lower_32_bits(pt_base)((u32)(pt_base)); |
| 1278 | |
| 1279 | pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; |
| 1280 | pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18; |
| 1281 | |
| 1282 | pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24; |
| 1283 | pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24; |
| 1284 | pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24; |
| 1285 | |
| 1286 | pa_config->system_aperture.fb_base = adev->gmc.fb_start; |
| 1287 | pa_config->system_aperture.fb_offset = adev->gmc.aper_base; |
| 1288 | pa_config->system_aperture.fb_top = adev->gmc.fb_end; |
| 1289 | |
| 1290 | pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12; |
| 1291 | pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12; |
| 1292 | pa_config->gart_config.page_table_base_addr = page_table_base.quad_part; |
| 1293 | |
| 1294 | pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support; |
| 1295 | |
| 1296 | } |
| 1297 | |
| 1298 | static void force_connector_state( |
| 1299 | struct amdgpu_dm_connector *aconnector, |
| 1300 | enum drm_connector_force force_state) |
| 1301 | { |
| 1302 | struct drm_connector *connector = &aconnector->base; |
| 1303 | |
| 1304 | mutex_lock(&connector->dev->mode_config.mutex)rw_enter_write(&connector->dev->mode_config.mutex); |
| 1305 | aconnector->base.force = force_state; |
| 1306 | mutex_unlock(&connector->dev->mode_config.mutex)rw_exit_write(&connector->dev->mode_config.mutex); |
| 1307 | |
| 1308 | mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock); |
| 1309 | drm_kms_helper_connector_hotplug_event(connector); |
| 1310 | mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock); |
| 1311 | } |
| 1312 | |
| 1313 | static void dm_handle_hpd_rx_offload_work(struct work_struct *work) |
| 1314 | { |
| 1315 | struct hpd_rx_irq_offload_work *offload_work; |
| 1316 | struct amdgpu_dm_connector *aconnector; |
| 1317 | struct dc_link *dc_link; |
| 1318 | struct amdgpu_device *adev; |
| 1319 | enum dc_connection_type new_connection_type = dc_connection_none; |
| 1320 | unsigned long flags; |
| 1321 | union test_response test_response; |
| 1322 | |
| 1323 | memset(&test_response, 0, sizeof(test_response))__builtin_memset((&test_response), (0), (sizeof(test_response ))); |
| 1324 | |
| 1325 | offload_work = container_of(work, struct hpd_rx_irq_offload_work, work)({ const __typeof( ((struct hpd_rx_irq_offload_work *)0)-> work ) *__mptr = (work); (struct hpd_rx_irq_offload_work *)( ( char *)__mptr - __builtin_offsetof(struct hpd_rx_irq_offload_work , work) );}); |
| 1326 | aconnector = offload_work->offload_wq->aconnector; |
| 1327 | |
| 1328 | if (!aconnector) { |
| 1329 | DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work")__drm_err("Can't retrieve aconnector in hpd_rx_irq_offload_work" ); |
| 1330 | goto skip; |
| 1331 | } |
| 1332 | |
| 1333 | adev = drm_to_adev(aconnector->base.dev); |
| 1334 | dc_link = aconnector->dc_link; |
| 1335 | |
| 1336 | mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock); |
| 1337 | if (!dc_link_detect_sink(dc_link, &new_connection_type)) |
| 1338 | DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n"); |
| 1339 | mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock); |
| 1340 | |
| 1341 | if (new_connection_type == dc_connection_none) |
| 1342 | goto skip; |
| 1343 | |
| 1344 | if (amdgpu_in_reset(adev)) |
| 1345 | goto skip; |
| 1346 | |
| 1347 | if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || |
| 1348 | offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { |
| 1349 | dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT); |
| 1350 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags)do { flags = 0; mtx_enter(&offload_work->offload_wq-> offload_lock); } while (0); |
| 1351 | offload_work->offload_wq->is_handling_mst_msg_rdy_event = false0; |
| 1352 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags)do { (void)(flags); mtx_leave(&offload_work->offload_wq ->offload_lock); } while (0); |
| 1353 | goto skip; |
| 1354 | } |
| 1355 | |
| 1356 | mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock); |
| 1357 | if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) { |
| 1358 | dc_link_dp_handle_automated_test(dc_link); |
| 1359 | |
| 1360 | if (aconnector->timing_changed) { |
| 1361 | /* force connector disconnect and reconnect */ |
| 1362 | force_connector_state(aconnector, DRM_FORCE_OFF); |
| 1363 | drm_msleep(100)mdelay(100); |
| 1364 | force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED); |
| 1365 | } |
| 1366 | |
| 1367 | test_response.bits.ACK = 1; |
| 1368 | |
| 1369 | core_link_write_dpcd( |
| 1370 | dc_link, |
| 1371 | DP_TEST_RESPONSE0x260, |
| 1372 | &test_response.raw, |
| 1373 | sizeof(test_response)); |
| 1374 | } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) && |
| 1375 | hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) && |
| 1376 | dc_link_dp_allow_hpd_rx_irq(dc_link)) { |
| 1377 | /* offload_work->data is from handle_hpd_rx_irq-> |
| 1378 | * schedule_hpd_rx_offload_work.this is defer handle |
| 1379 | * for hpd short pulse. upon here, link status may be |
| 1380 | * changed, need get latest link status from dpcd |
| 1381 | * registers. if link status is good, skip run link |
| 1382 | * training again. |
| 1383 | */ |
| 1384 | union hpd_irq_data irq_data; |
| 1385 | |
| 1386 | memset(&irq_data, 0, sizeof(irq_data))__builtin_memset((&irq_data), (0), (sizeof(irq_data))); |
| 1387 | |
| 1388 | /* before dc_link_dp_handle_link_loss, allow new link lost handle |
| 1389 | * request be added to work queue if link lost at end of dc_link_ |
| 1390 | * dp_handle_link_loss |
| 1391 | */ |
| 1392 | spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags)do { flags = 0; mtx_enter(&offload_work->offload_wq-> offload_lock); } while (0); |
| 1393 | offload_work->offload_wq->is_handling_link_loss = false0; |
| 1394 | spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags)do { (void)(flags); mtx_leave(&offload_work->offload_wq ->offload_lock); } while (0); |
| 1395 | |
| 1396 | if ((read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) && |
| 1397 | hpd_rx_irq_check_link_loss_status(dc_link, &irq_data)) |
| 1398 | dc_link_dp_handle_link_loss(dc_link); |
| 1399 | } |
| 1400 | mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock); |
| 1401 | |
| 1402 | skip: |
| 1403 | kfree(offload_work); |
| 1404 | |
| 1405 | } |
| 1406 | |
| 1407 | static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc) |
| 1408 | { |
| 1409 | int max_caps = dc->caps.max_links; |
| 1410 | int i = 0; |
| 1411 | struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL((void *)0); |
| 1412 | |
| 1413 | hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL(0x0001 | 0x0004)); |
| 1414 | |
| 1415 | if (!hpd_rx_offload_wq) |
| 1416 | return NULL((void *)0); |
| 1417 | |
| 1418 | |
| 1419 | for (i = 0; i < max_caps; i++) { |
| 1420 | hpd_rx_offload_wq[i].wq = |
| 1421 | create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq"); |
| 1422 | |
| 1423 | if (hpd_rx_offload_wq[i].wq == NULL((void *)0)) { |
| 1424 | DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!")__drm_err("create amdgpu_dm_hpd_rx_offload_wq fail!"); |
| 1425 | goto out_err; |
| 1426 | } |
| 1427 | |
| 1428 | mtx_init(&hpd_rx_offload_wq[i].offload_lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&hpd_rx_offload_wq [i].offload_lock), ((((0x9)) > 0x0 && ((0x9)) < 0x9) ? 0x9 : ((0x9)))); } while (0); |
| 1429 | } |
| 1430 | |
| 1431 | return hpd_rx_offload_wq; |
| 1432 | |
| 1433 | out_err: |
| 1434 | for (i = 0; i < max_caps; i++) { |
| 1435 | if (hpd_rx_offload_wq[i].wq) |
| 1436 | destroy_workqueue(hpd_rx_offload_wq[i].wq); |
| 1437 | } |
| 1438 | kfree(hpd_rx_offload_wq); |
| 1439 | return NULL((void *)0); |
| 1440 | } |
| 1441 | |
| 1442 | struct amdgpu_stutter_quirk { |
| 1443 | u16 chip_vendor; |
| 1444 | u16 chip_device; |
| 1445 | u16 subsys_vendor; |
| 1446 | u16 subsys_device; |
| 1447 | u8 revision; |
| 1448 | }; |
| 1449 | |
| 1450 | static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = { |
| 1451 | /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */ |
| 1452 | { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, |
| 1453 | { 0, 0, 0, 0, 0 }, |
| 1454 | }; |
| 1455 | |
| 1456 | static bool_Bool dm_should_disable_stutter(struct pci_dev *pdev) |
| 1457 | { |
| 1458 | const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list; |
| 1459 | |
| 1460 | while (p && p->chip_device != 0) { |
| 1461 | if (pdev->vendor == p->chip_vendor && |
| 1462 | pdev->device == p->chip_device && |
| 1463 | pdev->subsystem_vendor == p->subsys_vendor && |
| 1464 | pdev->subsystem_device == p->subsys_device && |
| 1465 | pdev->revision == p->revision) { |
| 1466 | return true1; |
| 1467 | } |
| 1468 | ++p; |
| 1469 | } |
| 1470 | return false0; |
| 1471 | } |
| 1472 | |
| 1473 | static const struct dmi_system_id hpd_disconnect_quirk_table[] = { |
| 1474 | { |
| 1475 | .matches = { |
| 1476 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1477 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"){(DMI_PRODUCT_NAME), ("Precision 3660")}, |
| 1478 | }, |
| 1479 | }, |
| 1480 | { |
| 1481 | .matches = { |
| 1482 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1483 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"){(DMI_PRODUCT_NAME), ("Precision 3260")}, |
| 1484 | }, |
| 1485 | }, |
| 1486 | { |
| 1487 | .matches = { |
| 1488 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1489 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"){(DMI_PRODUCT_NAME), ("Precision 3460")}, |
| 1490 | }, |
| 1491 | }, |
| 1492 | { |
| 1493 | .matches = { |
| 1494 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1495 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"){(DMI_PRODUCT_NAME), ("OptiPlex Tower Plus 7010")}, |
| 1496 | }, |
| 1497 | }, |
| 1498 | { |
| 1499 | .matches = { |
| 1500 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1501 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"){(DMI_PRODUCT_NAME), ("OptiPlex Tower 7010")}, |
| 1502 | }, |
| 1503 | }, |
| 1504 | { |
| 1505 | .matches = { |
| 1506 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1507 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"){(DMI_PRODUCT_NAME), ("OptiPlex SFF Plus 7010")}, |
| 1508 | }, |
| 1509 | }, |
| 1510 | { |
| 1511 | .matches = { |
| 1512 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1513 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"){(DMI_PRODUCT_NAME), ("OptiPlex SFF 7010")}, |
| 1514 | }, |
| 1515 | }, |
| 1516 | { |
| 1517 | .matches = { |
| 1518 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1519 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"){(DMI_PRODUCT_NAME), ("OptiPlex Micro Plus 7010")}, |
| 1520 | }, |
| 1521 | }, |
| 1522 | { |
| 1523 | .matches = { |
| 1524 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")}, |
| 1525 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"){(DMI_PRODUCT_NAME), ("OptiPlex Micro 7010")}, |
| 1526 | }, |
| 1527 | }, |
| 1528 | {} |
| 1529 | /* TODO: refactor this from a fixed table to a dynamic option */ |
| 1530 | }; |
| 1531 | |
| 1532 | static void retrieve_dmi_info(struct amdgpu_display_manager *dm) |
| 1533 | { |
| 1534 | const struct dmi_system_id *dmi_id; |
| 1535 | |
| 1536 | dm->aux_hpd_discon_quirk = false0; |
| 1537 | |
| 1538 | dmi_id = dmi_first_match(hpd_disconnect_quirk_table); |
| 1539 | if (dmi_id) { |
| 1540 | dm->aux_hpd_discon_quirk = true1; |
| 1541 | DRM_INFO("aux_hpd_discon_quirk attached\n")printk("\0016" "[" "drm" "] " "aux_hpd_discon_quirk attached\n" ); |
| 1542 | } |
| 1543 | } |
| 1544 | |
| 1545 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
| 1546 | { |
| 1547 | struct dc_init_data init_data; |
| 1548 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 1549 | struct dc_callback_init init_params; |
| 1550 | #endif |
| 1551 | int r; |
| 1552 | |
| 1553 | adev->dm.ddev = adev_to_drm(adev); |
| 1554 | adev->dm.adev = adev; |
| 1555 | |
| 1556 | /* Zero all the fields */ |
| 1557 | memset(&init_data, 0, sizeof(init_data))__builtin_memset((&init_data), (0), (sizeof(init_data))); |
| 1558 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 1559 | memset(&init_params, 0, sizeof(init_params))__builtin_memset((&init_params), (0), (sizeof(init_params ))); |
| 1560 | #endif |
| 1561 | |
| 1562 | rw_init(&adev->dm.dpia_aux_lock, "dmdpia")_rw_init_flags(&adev->dm.dpia_aux_lock, "dmdpia", 0, ( (void *)0)); |
| 1563 | rw_init(&adev->dm.dc_lock, "dmdc")_rw_init_flags(&adev->dm.dc_lock, "dmdc", 0, ((void *) 0)); |
| 1564 | rw_init(&adev->dm.audio_lock, "dmaud")_rw_init_flags(&adev->dm.audio_lock, "dmaud", 0, ((void *)0)); |
| 1565 | mtx_init(&adev->dm.vblank_lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&adev-> dm.vblank_lock), ((((0x9)) > 0x0 && ((0x9)) < 0x9 ) ? 0x9 : ((0x9)))); } while (0); |
| 1566 | |
| 1567 | if (amdgpu_dm_irq_init(adev)) { |
| 1568 | DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n")__drm_err("amdgpu: failed to initialize DM IRQ support.\n"); |
| 1569 | goto error; |
| 1570 | } |
| 1571 | |
| 1572 | init_data.asic_id.chip_family = adev->family; |
| 1573 | |
| 1574 | init_data.asic_id.pci_revision_id = adev->pdev->revision; |
| 1575 | init_data.asic_id.hw_internal_rev = adev->external_rev_id; |
| 1576 | init_data.asic_id.chip_id = adev->pdev->device; |
| 1577 | |
| 1578 | init_data.asic_id.vram_width = adev->gmc.vram_width; |
| 1579 | /* TODO: initialize init_data.asic_id.vram_type here!!!! */ |
| 1580 | init_data.asic_id.atombios_base_address = |
| 1581 | adev->mode_info.atom_context->bios; |
| 1582 | |
| 1583 | init_data.driver = adev; |
| 1584 | |
| 1585 | adev->dm.cgs_device = amdgpu_cgs_create_device(adev); |
| 1586 | |
| 1587 | if (!adev->dm.cgs_device) { |
| 1588 | DRM_ERROR("amdgpu: failed to create cgs device.\n")__drm_err("amdgpu: failed to create cgs device.\n"); |
| 1589 | goto error; |
| 1590 | } |
| 1591 | |
| 1592 | init_data.cgs_device = adev->dm.cgs_device; |
| 1593 | |
| 1594 | init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; |
| 1595 | |
| 1596 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 1597 | case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)): |
| 1598 | switch (adev->dm.dmcub_fw_version) { |
| 1599 | case 0: /* development */ |
| 1600 | case 0x1: /* linux-firmware.git hash 6d9f399 */ |
| 1601 | case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */ |
| 1602 | init_data.flags.disable_dmcu = false0; |
| 1603 | break; |
| 1604 | default: |
| 1605 | init_data.flags.disable_dmcu = true1; |
| 1606 | } |
| 1607 | break; |
| 1608 | case IP_VERSION(2, 0, 3)(((2) << 16) | ((0) << 8) | (3)): |
| 1609 | init_data.flags.disable_dmcu = true1; |
| 1610 | break; |
| 1611 | default: |
| 1612 | break; |
| 1613 | } |
| 1614 | |
| 1615 | switch (adev->asic_type) { |
| 1616 | case CHIP_CARRIZO: |
| 1617 | case CHIP_STONEY: |
| 1618 | init_data.flags.gpu_vm_support = true1; |
| 1619 | break; |
| 1620 | default: |
| 1621 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 1622 | case IP_VERSION(1, 0, 0)(((1) << 16) | ((0) << 8) | (0)): |
| 1623 | case IP_VERSION(1, 0, 1)(((1) << 16) | ((0) << 8) | (1)): |
| 1624 | /* enable S/G on PCO and RV2 */ |
| 1625 | if ((adev->apu_flags & AMD_APU_IS_RAVEN2) || |
| 1626 | (adev->apu_flags & AMD_APU_IS_PICASSO)) |
| 1627 | init_data.flags.gpu_vm_support = true1; |
| 1628 | break; |
| 1629 | case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)): |
| 1630 | case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)): |
| 1631 | case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)): |
| 1632 | case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)): |
| 1633 | case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)): |
| 1634 | init_data.flags.gpu_vm_support = true1; |
| 1635 | break; |
| 1636 | default: |
| 1637 | break; |
| 1638 | } |
| 1639 | break; |
| 1640 | } |
| 1641 | if (init_data.flags.gpu_vm_support && |
| 1642 | (amdgpu_sg_display == 0)) |
| 1643 | init_data.flags.gpu_vm_support = false0; |
| 1644 | |
| 1645 | if (init_data.flags.gpu_vm_support) |
| 1646 | adev->mode_info.gpu_vm_support = true1; |
| 1647 | |
| 1648 | if (amdgpu_dc_feature_mask & DC_FBC_MASK) |
| 1649 | init_data.flags.fbc_support = true1; |
| 1650 | |
| 1651 | if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK) |
| 1652 | init_data.flags.multi_mon_pp_mclk_switch = true1; |
| 1653 | |
| 1654 | if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK) |
| 1655 | init_data.flags.disable_fractional_pwm = true1; |
| 1656 | |
| 1657 | if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING) |
| 1658 | init_data.flags.edp_no_power_sequencing = true1; |
| 1659 | |
| 1660 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A) |
| 1661 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true1; |
| 1662 | if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0) |
| 1663 | init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true1; |
| 1664 | |
| 1665 | init_data.flags.seamless_boot_edp_requested = false0; |
| 1666 | |
| 1667 | if (check_seamless_boot_capability(adev)) { |
| 1668 | init_data.flags.seamless_boot_edp_requested = true1; |
| 1669 | init_data.flags.allow_seamless_boot_optimization = true1; |
| 1670 | DRM_INFO("Seamless boot condition check passed\n")printk("\0016" "[" "drm" "] " "Seamless boot condition check passed\n" ); |
| 1671 | } |
| 1672 | |
| 1673 | init_data.flags.enable_mipi_converter_optimization = true1; |
| 1674 | |
| 1675 | init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; |
| 1676 | init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; |
| 1677 | |
| 1678 | INIT_LIST_HEAD(&adev->dm.da_list); |
| 1679 | |
| 1680 | retrieve_dmi_info(&adev->dm); |
| 1681 | |
| 1682 | /* Display Core create. */ |
| 1683 | adev->dm.dc = dc_create(&init_data); |
| 1684 | |
| 1685 | if (adev->dm.dc) { |
| 1686 | DRM_INFO("Display Core initialized with v%s!\n", DC_VER)printk("\0016" "[" "drm" "] " "Display Core initialized with v%s!\n" , "3.2.207"); |
| 1687 | } else { |
| 1688 | DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER)printk("\0016" "[" "drm" "] " "Display Core failed to initialize with v%s!\n" , "3.2.207"); |
| 1689 | goto error; |
| 1690 | } |
| 1691 | |
| 1692 | if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) { |
| 1693 | adev->dm.dc->debug.force_single_disp_pipe_split = false0; |
| 1694 | adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; |
| 1695 | } |
| 1696 | |
| 1697 | if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) |
| 1698 | adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false0 : true1; |
| 1699 | if (dm_should_disable_stutter(adev->pdev)) |
| 1700 | adev->dm.dc->debug.disable_stutter = true1; |
| 1701 | |
| 1702 | if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER) |
| 1703 | adev->dm.dc->debug.disable_stutter = true1; |
| 1704 | |
| 1705 | if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) |
| 1706 | adev->dm.dc->debug.disable_dsc = true1; |
| 1707 | |
| 1708 | if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING) |
| 1709 | adev->dm.dc->debug.disable_clock_gate = true1; |
| 1710 | |
| 1711 | if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH) |
| 1712 | adev->dm.dc->debug.force_subvp_mclk_switch = true1; |
| 1713 | |
| 1714 | adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm; |
| 1715 | |
| 1716 | /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ |
| 1717 | adev->dm.dc->debug.ignore_cable_id = true1; |
| 1718 | |
| 1719 | r = dm_dmub_hw_init(adev); |
| 1720 | if (r) { |
| 1721 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r)__drm_err("DMUB interface failed to initialize: status=%d\n", r); |
| 1722 | goto error; |
| 1723 | } |
| 1724 | |
| 1725 | dc_hardware_init(adev->dm.dc); |
| 1726 | |
| 1727 | adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc); |
| 1728 | if (!adev->dm.hpd_rx_offload_wq) { |
| 1729 | DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n")__drm_err("amdgpu: failed to create hpd rx offload workqueue.\n" ); |
| 1730 | goto error; |
| 1731 | } |
| 1732 | |
| 1733 | if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) { |
| 1734 | struct dc_phy_addr_space_config pa_config; |
| 1735 | |
| 1736 | mmhub_read_system_context(adev, &pa_config); |
| 1737 | |
| 1738 | // Call the DC init_memory func |
| 1739 | dc_setup_system_context(adev->dm.dc, &pa_config); |
| 1740 | } |
| 1741 | |
| 1742 | adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); |
| 1743 | if (!adev->dm.freesync_module) { |
| 1744 | DRM_ERROR(__drm_err("amdgpu: failed to initialize freesync_module.\n") |
| 1745 | "amdgpu: failed to initialize freesync_module.\n")__drm_err("amdgpu: failed to initialize freesync_module.\n"); |
| 1746 | } else |
| 1747 | DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu: freesync_module init done %p.\n" , adev->dm.freesync_module) |
| 1748 | adev->dm.freesync_module)___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu: freesync_module init done %p.\n" , adev->dm.freesync_module); |
| 1749 | |
| 1750 | amdgpu_dm_init_color_mod(); |
| 1751 | |
| 1752 | if (adev->dm.dc->caps.max_links > 0) { |
| 1753 | adev->dm.vblank_control_workqueue = |
| 1754 | create_singlethread_workqueue("dm_vblank_control_workqueue"); |
| 1755 | if (!adev->dm.vblank_control_workqueue) |
| 1756 | DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n")__drm_err("amdgpu: failed to initialize vblank_workqueue.\n"); |
| 1757 | } |
| 1758 | |
| 1759 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 1760 | if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV142) { |
| 1761 | adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc); |
| 1762 | |
| 1763 | if (!adev->dm.hdcp_workqueue) |
| 1764 | DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n")__drm_err("amdgpu: failed to initialize hdcp_workqueue.\n"); |
| 1765 | else |
| 1766 | DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue)___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu: hdcp_workqueue init done %p.\n" , adev->dm.hdcp_workqueue); |
| 1767 | |
| 1768 | dc_init_callbacks(adev->dm.dc, &init_params); |
| 1769 | } |
| 1770 | #endif |
| 1771 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 1772 | adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work(); |
| 1773 | #endif |
| 1774 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
| 1775 | init_completion(&adev->dm.dmub_aux_transfer_done); |
| 1776 | adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL(0x0001 | 0x0004)); |
| 1777 | if (!adev->dm.dmub_notify) { |
| 1778 | DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify")printk("\0016" "[" "drm" "] " "amdgpu: fail to allocate adev->dm.dmub_notify" ); |
| 1779 | goto error; |
| 1780 | } |
| 1781 | |
| 1782 | adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq"); |
| 1783 | if (!adev->dm.delayed_hpd_wq) { |
| 1784 | DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n")__drm_err("amdgpu: failed to create hpd offload workqueue.\n" ); |
| 1785 | goto error; |
| 1786 | } |
| 1787 | |
| 1788 | amdgpu_dm_outbox_init(adev); |
| 1789 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY, |
| 1790 | dmub_aux_setconfig_callback, false0)) { |
| 1791 | DRM_ERROR("amdgpu: fail to register dmub aux callback")__drm_err("amdgpu: fail to register dmub aux callback"); |
| 1792 | goto error; |
| 1793 | } |
| 1794 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true1)) { |
| 1795 | DRM_ERROR("amdgpu: fail to register dmub hpd callback")__drm_err("amdgpu: fail to register dmub hpd callback"); |
| 1796 | goto error; |
| 1797 | } |
| 1798 | if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true1)) { |
| 1799 | DRM_ERROR("amdgpu: fail to register dmub hpd callback")__drm_err("amdgpu: fail to register dmub hpd callback"); |
| 1800 | goto error; |
| 1801 | } |
| 1802 | } |
| 1803 | |
| 1804 | /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive. |
| 1805 | * It is expected that DMUB will resend any pending notifications at this point, for |
| 1806 | * example HPD from DPIA. |
| 1807 | */ |
| 1808 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) |
| 1809 | dc_enable_dmub_outbox(adev->dm.dc); |
| 1810 | |
| 1811 | if (amdgpu_dm_initialize_drm_device(adev)) { |
| 1812 | DRM_ERROR(__drm_err("amdgpu: failed to initialize sw for display support.\n" ) |
| 1813 | "amdgpu: failed to initialize sw for display support.\n")__drm_err("amdgpu: failed to initialize sw for display support.\n" ); |
| 1814 | goto error; |
| 1815 | } |
| 1816 | |
| 1817 | /* create fake encoders for MST */ |
| 1818 | dm_dp_create_fake_mst_encoders(adev); |
| 1819 | |
| 1820 | /* TODO: Add_display_info? */ |
| 1821 | |
| 1822 | /* TODO use dynamic cursor width */ |
| 1823 | adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; |
| 1824 | adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; |
| 1825 | |
| 1826 | if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) { |
| 1827 | DRM_ERROR(__drm_err("amdgpu: failed to initialize sw for display support.\n" ) |
| 1828 | "amdgpu: failed to initialize sw for display support.\n")__drm_err("amdgpu: failed to initialize sw for display support.\n" ); |
| 1829 | goto error; |
| 1830 | } |
| 1831 | |
| 1832 | |
| 1833 | DRM_DEBUG_DRIVER("KMS initialized.\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "KMS initialized.\n"); |
| 1834 | |
| 1835 | return 0; |
| 1836 | error: |
| 1837 | amdgpu_dm_fini(adev); |
| 1838 | |
| 1839 | return -EINVAL22; |
| 1840 | } |
| 1841 | |
| 1842 | static int amdgpu_dm_early_fini(void *handle) |
| 1843 | { |
| 1844 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1845 | |
| 1846 | amdgpu_dm_audio_fini(adev); |
| 1847 | |
| 1848 | return 0; |
| 1849 | } |
| 1850 | |
| 1851 | static void amdgpu_dm_fini(struct amdgpu_device *adev) |
| 1852 | { |
| 1853 | int i; |
| 1854 | |
| 1855 | if (adev->dm.vblank_control_workqueue) { |
| 1856 | destroy_workqueue(adev->dm.vblank_control_workqueue); |
| 1857 | adev->dm.vblank_control_workqueue = NULL((void *)0); |
| 1858 | } |
| 1859 | |
| 1860 | amdgpu_dm_destroy_drm_device(&adev->dm); |
| 1861 | |
| 1862 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 1863 | if (adev->dm.crc_rd_wrk) { |
| 1864 | flush_work(&adev->dm.crc_rd_wrk->notify_ta_work); |
| 1865 | kfree(adev->dm.crc_rd_wrk); |
| 1866 | adev->dm.crc_rd_wrk = NULL((void *)0); |
| 1867 | } |
| 1868 | #endif |
| 1869 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 1870 | if (adev->dm.hdcp_workqueue) { |
| 1871 | hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue); |
| 1872 | adev->dm.hdcp_workqueue = NULL((void *)0); |
| 1873 | } |
| 1874 | |
| 1875 | if (adev->dm.dc) |
| 1876 | dc_deinit_callbacks(adev->dm.dc); |
| 1877 | #endif |
| 1878 | |
| 1879 | if (adev->dm.dc) |
| 1880 | dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv); |
| 1881 | |
| 1882 | if (dc_enable_dmub_notifications(adev->dm.dc)) { |
| 1883 | kfree(adev->dm.dmub_notify); |
| 1884 | adev->dm.dmub_notify = NULL((void *)0); |
| 1885 | destroy_workqueue(adev->dm.delayed_hpd_wq); |
| 1886 | adev->dm.delayed_hpd_wq = NULL((void *)0); |
| 1887 | } |
| 1888 | |
| 1889 | if (adev->dm.dmub_bo) |
| 1890 | amdgpu_bo_free_kernel(&adev->dm.dmub_bo, |
| 1891 | &adev->dm.dmub_bo_gpu_addr, |
| 1892 | &adev->dm.dmub_bo_cpu_addr); |
| 1893 | |
| 1894 | if (adev->dm.hpd_rx_offload_wq) { |
| 1895 | for (i = 0; i < adev->dm.dc->caps.max_links; i++) { |
| 1896 | if (adev->dm.hpd_rx_offload_wq[i].wq) { |
| 1897 | destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq); |
| 1898 | adev->dm.hpd_rx_offload_wq[i].wq = NULL((void *)0); |
| 1899 | } |
| 1900 | } |
| 1901 | |
| 1902 | kfree(adev->dm.hpd_rx_offload_wq); |
| 1903 | adev->dm.hpd_rx_offload_wq = NULL((void *)0); |
| 1904 | } |
| 1905 | |
| 1906 | /* DC Destroy TODO: Replace destroy DAL */ |
| 1907 | if (adev->dm.dc) |
| 1908 | dc_destroy(&adev->dm.dc); |
| 1909 | /* |
| 1910 | * TODO: pageflip, vlank interrupt |
| 1911 | * |
| 1912 | * amdgpu_dm_irq_fini(adev); |
| 1913 | */ |
| 1914 | |
| 1915 | if (adev->dm.cgs_device) { |
| 1916 | amdgpu_cgs_destroy_device(adev->dm.cgs_device); |
| 1917 | adev->dm.cgs_device = NULL((void *)0); |
| 1918 | } |
| 1919 | if (adev->dm.freesync_module) { |
| 1920 | mod_freesync_destroy(adev->dm.freesync_module); |
| 1921 | adev->dm.freesync_module = NULL((void *)0); |
| 1922 | } |
| 1923 | |
| 1924 | mutex_destroy(&adev->dm.audio_lock); |
| 1925 | mutex_destroy(&adev->dm.dc_lock); |
| 1926 | mutex_destroy(&adev->dm.dpia_aux_lock); |
| 1927 | } |
| 1928 | |
| 1929 | static int load_dmcu_fw(struct amdgpu_device *adev) |
| 1930 | { |
| 1931 | const char *fw_name_dmcu = NULL((void *)0); |
| 1932 | int r; |
| 1933 | const struct dmcu_firmware_header_v1_0 *hdr; |
| 1934 | |
| 1935 | switch (adev->asic_type) { |
| 1936 | #if defined(CONFIG_DRM_AMD_DC_SI) |
| 1937 | case CHIP_TAHITI: |
| 1938 | case CHIP_PITCAIRN: |
| 1939 | case CHIP_VERDE: |
| 1940 | case CHIP_OLAND: |
| 1941 | #endif |
| 1942 | case CHIP_BONAIRE: |
| 1943 | case CHIP_HAWAII: |
| 1944 | case CHIP_KAVERI: |
| 1945 | case CHIP_KABINI: |
| 1946 | case CHIP_MULLINS: |
| 1947 | case CHIP_TONGA: |
| 1948 | case CHIP_FIJI: |
| 1949 | case CHIP_CARRIZO: |
| 1950 | case CHIP_STONEY: |
| 1951 | case CHIP_POLARIS11: |
| 1952 | case CHIP_POLARIS10: |
| 1953 | case CHIP_POLARIS12: |
| 1954 | case CHIP_VEGAM: |
| 1955 | case CHIP_VEGA10: |
| 1956 | case CHIP_VEGA12: |
| 1957 | case CHIP_VEGA20: |
| 1958 | return 0; |
| 1959 | case CHIP_NAVI12: |
| 1960 | fw_name_dmcu = FIRMWARE_NAVI12_DMCU"amdgpu/navi12_dmcu.bin"; |
| 1961 | break; |
| 1962 | case CHIP_RAVEN: |
| 1963 | if (ASICREV_IS_PICASSO(adev->external_rev_id)((adev->external_rev_id >= 0x41) && (adev->external_rev_id < 0x81))) |
| 1964 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin"; |
| 1965 | else if (ASICREV_IS_RAVEN2(adev->external_rev_id)((adev->external_rev_id >= 0x81) && (adev->external_rev_id < 0x91))) |
| 1966 | fw_name_dmcu = FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin"; |
| 1967 | else |
| 1968 | return 0; |
| 1969 | break; |
| 1970 | default: |
| 1971 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 1972 | case IP_VERSION(2, 0, 2)(((2) << 16) | ((0) << 8) | (2)): |
| 1973 | case IP_VERSION(2, 0, 3)(((2) << 16) | ((0) << 8) | (3)): |
| 1974 | case IP_VERSION(2, 0, 0)(((2) << 16) | ((0) << 8) | (0)): |
| 1975 | case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)): |
| 1976 | case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)): |
| 1977 | case IP_VERSION(3, 0, 2)(((3) << 16) | ((0) << 8) | (2)): |
| 1978 | case IP_VERSION(3, 0, 3)(((3) << 16) | ((0) << 8) | (3)): |
| 1979 | case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)): |
| 1980 | case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)): |
| 1981 | case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)): |
| 1982 | case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)): |
| 1983 | case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)): |
| 1984 | case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)): |
| 1985 | case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)): |
| 1986 | case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)): |
| 1987 | return 0; |
| 1988 | default: |
| 1989 | break; |
| 1990 | } |
| 1991 | DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type)__drm_err("Unsupported ASIC type: 0x%X\n", adev->asic_type ); |
| 1992 | return -EINVAL22; |
| 1993 | } |
| 1994 | |
| 1995 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 1996 | DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n")___drm_dbg(((void *)0), DRM_UT_KMS, "dm: DMCU firmware not supported on direct or SMU loading\n" ); |
| 1997 | return 0; |
| 1998 | } |
| 1999 | |
| 2000 | r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev); |
| 2001 | if (r == -ENOENT2) { |
| 2002 | /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ |
| 2003 | DRM_DEBUG_KMS("dm: DMCU firmware not found\n")___drm_dbg(((void *)0), DRM_UT_KMS, "dm: DMCU firmware not found\n" ); |
| 2004 | adev->dm.fw_dmcu = NULL((void *)0); |
| 2005 | return 0; |
| 2006 | } |
| 2007 | if (r) { |
| 2008 | dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't load firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu ) |
| 2009 | fw_name_dmcu)printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't load firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu ); |
| 2010 | return r; |
| 2011 | } |
| 2012 | |
| 2013 | r = amdgpu_ucode_validate(adev->dm.fw_dmcu); |
| 2014 | if (r) { |
| 2015 | dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't validate firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu ) |
| 2016 | fw_name_dmcu)printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't validate firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu ); |
| 2017 | release_firmware(adev->dm.fw_dmcu); |
| 2018 | adev->dm.fw_dmcu = NULL((void *)0); |
| 2019 | return r; |
| 2020 | } |
| 2021 | |
| 2022 | hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data; |
| 2023 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM; |
| 2024 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu; |
| 2025 | adev->firmware.fw_size += |
| 2026 | roundup2(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->header.ucode_size_bytes)) - ((__uint32_t )(hdr->intv_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(hdr->header.ucode_size_bytes)) - ((__uint32_t)(hdr->intv_size_bytes))))((1 << 12)) - 1))); |
| 2027 | |
| 2028 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV; |
| 2029 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu; |
| 2030 | adev->firmware.fw_size += |
| 2031 | roundup2(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->intv_size_bytes))) + (((1 << 12 )) - 1)) & (~((__typeof(((__uint32_t)(hdr->intv_size_bytes ))))((1 << 12)) - 1))); |
| 2032 | |
| 2033 | adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version)); |
| 2034 | |
| 2035 | DRM_DEBUG_KMS("PSP loading DMCU firmware\n")___drm_dbg(((void *)0), DRM_UT_KMS, "PSP loading DMCU firmware\n" ); |
| 2036 | |
| 2037 | return 0; |
| 2038 | } |
| 2039 | |
| 2040 | static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address) |
| 2041 | { |
| 2042 | struct amdgpu_device *adev = ctx; |
| 2043 | |
| 2044 | return dm_read_reg(adev->dm.dc->ctx, address)dm_read_reg_func(adev->dm.dc->ctx, address, __func__); |
| 2045 | } |
| 2046 | |
| 2047 | static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, |
| 2048 | uint32_t value) |
| 2049 | { |
| 2050 | struct amdgpu_device *adev = ctx; |
| 2051 | |
| 2052 | return dm_write_reg(adev->dm.dc->ctx, address, value)dm_write_reg_func(adev->dm.dc->ctx, address, value, __func__ ); |
| 2053 | } |
| 2054 | |
| 2055 | static int dm_dmub_sw_init(struct amdgpu_device *adev) |
| 2056 | { |
| 2057 | struct dmub_srv_create_params create_params; |
| 2058 | struct dmub_srv_region_params region_params; |
| 2059 | struct dmub_srv_region_info region_info; |
| 2060 | struct dmub_srv_memory_params memory_params; |
| 2061 | struct dmub_srv_fb_info *fb_info; |
| 2062 | struct dmub_srv *dmub_srv; |
| 2063 | const struct dmcub_firmware_header_v1_0 *hdr; |
| 2064 | const char *fw_name_dmub; |
| 2065 | enum dmub_asic dmub_asic; |
| 2066 | enum dmub_status status; |
| 2067 | int r; |
| 2068 | |
| 2069 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 2070 | case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)): |
| 2071 | dmub_asic = DMUB_ASIC_DCN21; |
| 2072 | fw_name_dmub = FIRMWARE_RENOIR_DMUB"amdgpu/renoir_dmcub.bin"; |
| 2073 | if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)((adev->external_rev_id >= 0xA1) && (adev->external_rev_id < 0xFF))) |
| 2074 | fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB"amdgpu/green_sardine_dmcub.bin"; |
| 2075 | break; |
| 2076 | case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)): |
| 2077 | if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0))) { |
| 2078 | dmub_asic = DMUB_ASIC_DCN30; |
| 2079 | fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB"amdgpu/sienna_cichlid_dmcub.bin"; |
| 2080 | } else { |
| 2081 | dmub_asic = DMUB_ASIC_DCN30; |
| 2082 | fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB"amdgpu/navy_flounder_dmcub.bin"; |
| 2083 | } |
| 2084 | break; |
| 2085 | case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)): |
| 2086 | dmub_asic = DMUB_ASIC_DCN301; |
| 2087 | fw_name_dmub = FIRMWARE_VANGOGH_DMUB"amdgpu/vangogh_dmcub.bin"; |
| 2088 | break; |
| 2089 | case IP_VERSION(3, 0, 2)(((3) << 16) | ((0) << 8) | (2)): |
| 2090 | dmub_asic = DMUB_ASIC_DCN302; |
| 2091 | fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB"amdgpu/dimgrey_cavefish_dmcub.bin"; |
| 2092 | break; |
| 2093 | case IP_VERSION(3, 0, 3)(((3) << 16) | ((0) << 8) | (3)): |
| 2094 | dmub_asic = DMUB_ASIC_DCN303; |
| 2095 | fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB"amdgpu/beige_goby_dmcub.bin"; |
| 2096 | break; |
| 2097 | case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)): |
| 2098 | case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)): |
| 2099 | dmub_asic = (adev->external_rev_id == YELLOW_CARP_B00x20) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31; |
| 2100 | fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB"amdgpu/yellow_carp_dmcub.bin"; |
| 2101 | break; |
| 2102 | case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)): |
| 2103 | dmub_asic = DMUB_ASIC_DCN314; |
| 2104 | fw_name_dmub = FIRMWARE_DCN_314_DMUB"amdgpu/dcn_3_1_4_dmcub.bin"; |
| 2105 | break; |
| 2106 | case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)): |
| 2107 | dmub_asic = DMUB_ASIC_DCN315; |
| 2108 | fw_name_dmub = FIRMWARE_DCN_315_DMUB"amdgpu/dcn_3_1_5_dmcub.bin"; |
| 2109 | break; |
| 2110 | case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)): |
| 2111 | dmub_asic = DMUB_ASIC_DCN316; |
| 2112 | fw_name_dmub = FIRMWARE_DCN316_DMUB"amdgpu/dcn_3_1_6_dmcub.bin"; |
| 2113 | break; |
| 2114 | case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)): |
| 2115 | dmub_asic = DMUB_ASIC_DCN32; |
| 2116 | fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB"amdgpu/dcn_3_2_0_dmcub.bin"; |
| 2117 | break; |
| 2118 | case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)): |
| 2119 | dmub_asic = DMUB_ASIC_DCN321; |
| 2120 | fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB"amdgpu/dcn_3_2_1_dmcub.bin"; |
| 2121 | break; |
| 2122 | default: |
| 2123 | /* ASIC doesn't support DMUB. */ |
| 2124 | return 0; |
| 2125 | } |
| 2126 | |
| 2127 | r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev); |
| 2128 | if (r) { |
| 2129 | DRM_ERROR("DMUB firmware loading failed: %d\n", r)__drm_err("DMUB firmware loading failed: %d\n", r); |
| 2130 | return 0; |
| 2131 | } |
| 2132 | |
| 2133 | r = amdgpu_ucode_validate(adev->dm.dmub_fw); |
| 2134 | if (r) { |
| 2135 | DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r)__drm_err("Couldn't validate DMUB firmware: %d\n", r); |
| 2136 | return 0; |
| 2137 | } |
| 2138 | |
| 2139 | hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data; |
| 2140 | adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version)); |
| 2141 | |
| 2142 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
| 2143 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id = |
| 2144 | AMDGPU_UCODE_ID_DMCUB; |
| 2145 | adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw = |
| 2146 | adev->dm.dmub_fw; |
| 2147 | adev->firmware.fw_size += |
| 2148 | roundup2(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->inst_const_bytes))) + (((1 << 12 )) - 1)) & (~((__typeof(((__uint32_t)(hdr->inst_const_bytes ))))((1 << 12)) - 1))); |
| 2149 | |
| 2150 | DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",printk("\0016" "[" "drm" "] " "Loading DMUB firmware via PSP: version=0x%08X\n" , adev->dm.dmcub_fw_version) |
| 2151 | adev->dm.dmcub_fw_version)printk("\0016" "[" "drm" "] " "Loading DMUB firmware via PSP: version=0x%08X\n" , adev->dm.dmcub_fw_version); |
| 2152 | } |
| 2153 | |
| 2154 | |
| 2155 | adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL(0x0001 | 0x0004)); |
| 2156 | dmub_srv = adev->dm.dmub_srv; |
| 2157 | |
| 2158 | if (!dmub_srv) { |
| 2159 | DRM_ERROR("Failed to allocate DMUB service!\n")__drm_err("Failed to allocate DMUB service!\n"); |
| 2160 | return -ENOMEM12; |
| 2161 | } |
| 2162 | |
| 2163 | memset(&create_params, 0, sizeof(create_params))__builtin_memset((&create_params), (0), (sizeof(create_params ))); |
| 2164 | create_params.user_ctx = adev; |
| 2165 | create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read; |
| 2166 | create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write; |
| 2167 | create_params.asic = dmub_asic; |
| 2168 | |
| 2169 | /* Create the DMUB service. */ |
| 2170 | status = dmub_srv_create(dmub_srv, &create_params); |
| 2171 | if (status != DMUB_STATUS_OK) { |
| 2172 | DRM_ERROR("Error creating DMUB service: %d\n", status)__drm_err("Error creating DMUB service: %d\n", status); |
| 2173 | return -EINVAL22; |
| 2174 | } |
| 2175 | |
| 2176 | /* Calculate the size of all the regions for the DMUB service. */ |
| 2177 | memset(®ion_params, 0, sizeof(region_params))__builtin_memset((®ion_params), (0), (sizeof(region_params ))); |
| 2178 | |
| 2179 | region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) - |
| 2180 | PSP_HEADER_BYTES0x100 - PSP_FOOTER_BYTES0x100; |
| 2181 | region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes)((__uint32_t)(hdr->bss_data_bytes)); |
| 2182 | region_params.vbios_size = adev->bios_size; |
| 2183 | region_params.fw_bss_data = region_params.bss_data_size ? |
| 2184 | adev->dm.dmub_fw->data + |
| 2185 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) + |
| 2186 | le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) : NULL((void *)0); |
| 2187 | region_params.fw_inst_const = |
| 2188 | adev->dm.dmub_fw->data + |
| 2189 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) + |
| 2190 | PSP_HEADER_BYTES0x100; |
| 2191 | region_params.is_mailbox_in_inbox = false0; |
| 2192 | |
| 2193 | status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, |
| 2194 | ®ion_info); |
| 2195 | |
| 2196 | if (status != DMUB_STATUS_OK) { |
| 2197 | DRM_ERROR("Error calculating DMUB region info: %d\n", status)__drm_err("Error calculating DMUB region info: %d\n", status); |
| 2198 | return -EINVAL22; |
| 2199 | } |
| 2200 | |
| 2201 | /* |
| 2202 | * Allocate a framebuffer based on the total size of all the regions. |
| 2203 | * TODO: Move this into GART. |
| 2204 | */ |
| 2205 | r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE(1 << 12), |
| 2206 | AMDGPU_GEM_DOMAIN_VRAM0x4, &adev->dm.dmub_bo, |
| 2207 | &adev->dm.dmub_bo_gpu_addr, |
| 2208 | &adev->dm.dmub_bo_cpu_addr); |
| 2209 | if (r) |
| 2210 | return r; |
| 2211 | |
| 2212 | /* Rebase the regions on the framebuffer address. */ |
| 2213 | memset(&memory_params, 0, sizeof(memory_params))__builtin_memset((&memory_params), (0), (sizeof(memory_params ))); |
| 2214 | memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr; |
| 2215 | memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr; |
| 2216 | memory_params.region_info = ®ion_info; |
| 2217 | |
| 2218 | adev->dm.dmub_fb_info = |
| 2219 | kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL(0x0001 | 0x0004)); |
| 2220 | fb_info = adev->dm.dmub_fb_info; |
| 2221 | |
| 2222 | if (!fb_info) { |
| 2223 | DRM_ERROR(__drm_err("Failed to allocate framebuffer info for DMUB service!\n" ) |
| 2224 | "Failed to allocate framebuffer info for DMUB service!\n")__drm_err("Failed to allocate framebuffer info for DMUB service!\n" ); |
| 2225 | return -ENOMEM12; |
| 2226 | } |
| 2227 | |
| 2228 | status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info); |
| 2229 | if (status != DMUB_STATUS_OK) { |
| 2230 | DRM_ERROR("Error calculating DMUB FB info: %d\n", status)__drm_err("Error calculating DMUB FB info: %d\n", status); |
| 2231 | return -EINVAL22; |
| 2232 | } |
| 2233 | |
| 2234 | return 0; |
| 2235 | } |
| 2236 | |
| 2237 | static int dm_sw_init(void *handle) |
| 2238 | { |
| 2239 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2240 | int r; |
| 2241 | |
| 2242 | r = dm_dmub_sw_init(adev); |
| 2243 | if (r) |
| 2244 | return r; |
| 2245 | |
| 2246 | return load_dmcu_fw(adev); |
| 2247 | } |
| 2248 | |
| 2249 | static int dm_sw_fini(void *handle) |
| 2250 | { |
| 2251 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2252 | |
| 2253 | kfree(adev->dm.dmub_fb_info); |
| 2254 | adev->dm.dmub_fb_info = NULL((void *)0); |
| 2255 | |
| 2256 | if (adev->dm.dmub_srv) { |
| 2257 | dmub_srv_destroy(adev->dm.dmub_srv); |
| 2258 | adev->dm.dmub_srv = NULL((void *)0); |
| 2259 | } |
| 2260 | |
| 2261 | release_firmware(adev->dm.dmub_fw); |
| 2262 | adev->dm.dmub_fw = NULL((void *)0); |
| 2263 | |
| 2264 | release_firmware(adev->dm.fw_dmcu); |
| 2265 | adev->dm.fw_dmcu = NULL((void *)0); |
| 2266 | |
| 2267 | return 0; |
| 2268 | } |
| 2269 | |
| 2270 | static int detect_mst_link_for_all_connectors(struct drm_device *dev) |
| 2271 | { |
| 2272 | struct amdgpu_dm_connector *aconnector; |
| 2273 | struct drm_connector *connector; |
| 2274 | struct drm_connector_list_iter iter; |
| 2275 | int ret = 0; |
| 2276 | |
| 2277 | drm_connector_list_iter_begin(dev, &iter); |
| 2278 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 2279 | aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 2280 | if (aconnector->dc_link->type == dc_connection_mst_branch && |
| 2281 | aconnector->mst_mgr.aux) { |
| 2282 | DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n" , aconnector, aconnector->base.base.id) |
| 2283 | aconnector,___drm_dbg(((void *)0), DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n" , aconnector, aconnector->base.base.id) |
| 2284 | aconnector->base.base.id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n" , aconnector, aconnector->base.base.id); |
| 2285 | |
| 2286 | ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true1); |
| 2287 | if (ret < 0) { |
| 2288 | DRM_ERROR("DM_MST: Failed to start MST\n")__drm_err("DM_MST: Failed to start MST\n"); |
| 2289 | aconnector->dc_link->type = |
| 2290 | dc_connection_single; |
| 2291 | ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
| 2292 | aconnector->dc_link); |
| 2293 | break; |
| 2294 | } |
| 2295 | } |
| 2296 | } |
| 2297 | drm_connector_list_iter_end(&iter); |
| 2298 | |
| 2299 | return ret; |
| 2300 | } |
| 2301 | |
| 2302 | static int dm_late_init(void *handle) |
| 2303 | { |
| 2304 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2305 | |
| 2306 | struct dmcu_iram_parameters params; |
| 2307 | unsigned int linear_lut[16]; |
| 2308 | int i; |
| 2309 | struct dmcu *dmcu = NULL((void *)0); |
| 2310 | |
| 2311 | dmcu = adev->dm.dc->res_pool->dmcu; |
| 2312 | |
| 2313 | for (i = 0; i < 16; i++) |
| 2314 | linear_lut[i] = 0xFFFF * i / 15; |
| 2315 | |
| 2316 | params.set = 0; |
| 2317 | params.backlight_ramping_override = false0; |
| 2318 | params.backlight_ramping_start = 0xCCCC; |
| 2319 | params.backlight_ramping_reduction = 0xCCCCCCCC; |
| 2320 | params.backlight_lut_array_size = 16; |
| 2321 | params.backlight_lut_array = linear_lut; |
| 2322 | |
| 2323 | /* Min backlight level after ABM reduction, Don't allow below 1% |
| 2324 | * 0xFFFF x 0.01 = 0x28F |
| 2325 | */ |
| 2326 | params.min_abm_backlight = 0x28F; |
| 2327 | /* In the case where abm is implemented on dmcub, |
| 2328 | * dmcu object will be null. |
| 2329 | * ABM 2.4 and up are implemented on dmcub. |
| 2330 | */ |
| 2331 | if (dmcu) { |
| 2332 | if (!dmcu_load_iram(dmcu, params)) |
| 2333 | return -EINVAL22; |
| 2334 | } else if (adev->dm.dc->ctx->dmub_srv) { |
| 2335 | struct dc_link *edp_links[MAX_NUM_EDP2]; |
| 2336 | int edp_num; |
| 2337 | |
| 2338 | get_edp_links(adev->dm.dc, edp_links, &edp_num); |
| 2339 | for (i = 0; i < edp_num; i++) { |
| 2340 | if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i)) |
| 2341 | return -EINVAL22; |
| 2342 | } |
| 2343 | } |
| 2344 | |
| 2345 | return detect_mst_link_for_all_connectors(adev_to_drm(adev)); |
| 2346 | } |
| 2347 | |
| 2348 | static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) |
| 2349 | { |
| 2350 | int ret; |
| 2351 | u8 guid[16]; |
| 2352 | u64 tmp64; |
| 2353 | |
| 2354 | mutex_lock(&mgr->lock)rw_enter_write(&mgr->lock); |
| 2355 | if (!mgr->mst_primary) |
| 2356 | goto out_fail; |
| 2357 | |
| 2358 | if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { |
| 2359 | drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n")__drm_dev_dbg(((void *)0), (mgr->dev) ? (mgr->dev)-> dev : ((void *)0), DRM_UT_KMS, "dpcd read failed - undocked during suspend?\n" ); |
| 2360 | goto out_fail; |
| 2361 | } |
| 2362 | |
| 2363 | ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL0x111, |
| 2364 | DP_MST_EN(1 << 0) | |
| 2365 | DP_UP_REQ_EN(1 << 1) | |
| 2366 | DP_UPSTREAM_IS_SRC(1 << 2)); |
| 2367 | if (ret < 0) { |
| 2368 | drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n")__drm_dev_dbg(((void *)0), (mgr->dev) ? (mgr->dev)-> dev : ((void *)0), DRM_UT_KMS, "mst write failed - undocked during suspend?\n" ); |
| 2369 | goto out_fail; |
| 2370 | } |
| 2371 | |
| 2372 | /* Some hubs forget their guids after they resume */ |
| 2373 | ret = drm_dp_dpcd_read(mgr->aux, DP_GUID0x030, guid, 16); |
| 2374 | if (ret != 16) { |
| 2375 | drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n")__drm_dev_dbg(((void *)0), (mgr->dev) ? (mgr->dev)-> dev : ((void *)0), DRM_UT_KMS, "dpcd read failed - undocked during suspend?\n" ); |
| 2376 | goto out_fail; |
| 2377 | } |
| 2378 | |
| 2379 | if (memchr_inv(guid, 0, 16) == NULL((void *)0)) { |
| 2380 | tmp64 = get_jiffies_64(); |
| 2381 | memcpy(&guid[0], &tmp64, sizeof(u64))__builtin_memcpy((&guid[0]), (&tmp64), (sizeof(u64))); |
| 2382 | memcpy(&guid[8], &tmp64, sizeof(u64))__builtin_memcpy((&guid[8]), (&tmp64), (sizeof(u64))); |
| 2383 | |
| 2384 | ret = drm_dp_dpcd_write(mgr->aux, DP_GUID0x030, guid, 16); |
| 2385 | |
| 2386 | if (ret != 16) { |
| 2387 | drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n")__drm_dev_dbg(((void *)0), (mgr->dev) ? (mgr->dev)-> dev : ((void *)0), DRM_UT_KMS, "check mstb guid failed - undocked during suspend?\n" ); |
| 2388 | goto out_fail; |
| 2389 | } |
| 2390 | } |
| 2391 | |
| 2392 | memcpy(mgr->mst_primary->guid, guid, 16)__builtin_memcpy((mgr->mst_primary->guid), (guid), (16) ); |
| 2393 | |
| 2394 | out_fail: |
| 2395 | mutex_unlock(&mgr->lock)rw_exit_write(&mgr->lock); |
| 2396 | } |
| 2397 | |
| 2398 | static void s3_handle_mst(struct drm_device *dev, bool_Bool suspend) |
| 2399 | { |
| 2400 | struct amdgpu_dm_connector *aconnector; |
| 2401 | struct drm_connector *connector; |
| 2402 | struct drm_connector_list_iter iter; |
| 2403 | struct drm_dp_mst_topology_mgr *mgr; |
| 2404 | |
| 2405 | drm_connector_list_iter_begin(dev, &iter); |
| 2406 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 2407 | aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 2408 | if (aconnector->dc_link->type != dc_connection_mst_branch || |
| 2409 | aconnector->mst_port) |
| 2410 | continue; |
| 2411 | |
| 2412 | mgr = &aconnector->mst_mgr; |
| 2413 | |
| 2414 | if (suspend) { |
| 2415 | drm_dp_mst_topology_mgr_suspend(mgr); |
| 2416 | } else { |
| 2417 | /* if extended timeout is supported in hardware, |
| 2418 | * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer |
| 2419 | * CTS 4.2.1.1 regression introduced by CTS specs requirement update. |
| 2420 | */ |
| 2421 | dc_link_aux_try_to_configure_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD3200); |
| 2422 | if (!dp_is_lttpr_present(aconnector->dc_link)) |
| 2423 | dc_link_aux_try_to_configure_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD552); |
| 2424 | |
| 2425 | /* TODO: move resume_mst_branch_status() into drm mst resume again |
| 2426 | * once topology probing work is pulled out from mst resume into mst |
| 2427 | * resume 2nd step. mst resume 2nd step should be called after old |
| 2428 | * state getting restored (i.e. drm_atomic_helper_resume()). |
| 2429 | */ |
| 2430 | resume_mst_branch_status(mgr); |
| 2431 | } |
| 2432 | } |
| 2433 | drm_connector_list_iter_end(&iter); |
| 2434 | } |
| 2435 | |
| 2436 | static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) |
| 2437 | { |
| 2438 | int ret = 0; |
| 2439 | |
| 2440 | /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends |
| 2441 | * on window driver dc implementation. |
| 2442 | * For Navi1x, clock settings of dcn watermarks are fixed. the settings |
| 2443 | * should be passed to smu during boot up and resume from s3. |
| 2444 | * boot up: dc calculate dcn watermark clock settings within dc_create, |
| 2445 | * dcn20_resource_construct |
| 2446 | * then call pplib functions below to pass the settings to smu: |
| 2447 | * smu_set_watermarks_for_clock_ranges |
| 2448 | * smu_set_watermarks_table |
| 2449 | * navi10_set_watermarks_table |
| 2450 | * smu_write_watermarks_table |
| 2451 | * |
| 2452 | * For Renoir, clock settings of dcn watermark are also fixed values. |
| 2453 | * dc has implemented different flow for window driver: |
| 2454 | * dc_hardware_init / dc_set_power_state |
| 2455 | * dcn10_init_hw |
| 2456 | * notify_wm_ranges |
| 2457 | * set_wm_ranges |
| 2458 | * -- Linux |
| 2459 | * smu_set_watermarks_for_clock_ranges |
| 2460 | * renoir_set_watermarks_table |
| 2461 | * smu_write_watermarks_table |
| 2462 | * |
| 2463 | * For Linux, |
| 2464 | * dc_hardware_init -> amdgpu_dm_init |
| 2465 | * dc_set_power_state --> dm_resume |
| 2466 | * |
| 2467 | * therefore, this function apply to navi10/12/14 but not Renoir |
| 2468 | * * |
| 2469 | */ |
| 2470 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 2471 | case IP_VERSION(2, 0, 2)(((2) << 16) | ((0) << 8) | (2)): |
| 2472 | case IP_VERSION(2, 0, 0)(((2) << 16) | ((0) << 8) | (0)): |
| 2473 | break; |
| 2474 | default: |
| 2475 | return 0; |
| 2476 | } |
| 2477 | |
| 2478 | ret = amdgpu_dpm_write_watermarks_table(adev); |
| 2479 | if (ret) { |
| 2480 | DRM_ERROR("Failed to update WMTABLE!\n")__drm_err("Failed to update WMTABLE!\n"); |
| 2481 | return ret; |
| 2482 | } |
| 2483 | |
| 2484 | return 0; |
| 2485 | } |
| 2486 | |
| 2487 | /** |
| 2488 | * dm_hw_init() - Initialize DC device |
| 2489 | * @handle: The base driver device containing the amdgpu_dm device. |
| 2490 | * |
| 2491 | * Initialize the &struct amdgpu_display_manager device. This involves calling |
| 2492 | * the initializers of each DM component, then populating the struct with them. |
| 2493 | * |
| 2494 | * Although the function implies hardware initialization, both hardware and |
| 2495 | * software are initialized here. Splitting them out to their relevant init |
| 2496 | * hooks is a future TODO item. |
| 2497 | * |
| 2498 | * Some notable things that are initialized here: |
| 2499 | * |
| 2500 | * - Display Core, both software and hardware |
| 2501 | * - DC modules that we need (freesync and color management) |
| 2502 | * - DRM software states |
| 2503 | * - Interrupt sources and handlers |
| 2504 | * - Vblank support |
| 2505 | * - Debug FS entries, if enabled |
| 2506 | */ |
| 2507 | static int dm_hw_init(void *handle) |
| 2508 | { |
| 2509 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2510 | /* Create DAL display manager */ |
| 2511 | amdgpu_dm_init(adev); |
| 2512 | amdgpu_dm_hpd_init(adev); |
| 2513 | |
| 2514 | return 0; |
| 2515 | } |
| 2516 | |
| 2517 | /** |
| 2518 | * dm_hw_fini() - Teardown DC device |
| 2519 | * @handle: The base driver device containing the amdgpu_dm device. |
| 2520 | * |
| 2521 | * Teardown components within &struct amdgpu_display_manager that require |
| 2522 | * cleanup. This involves cleaning up the DRM device, DC, and any modules that |
| 2523 | * were loaded. Also flush IRQ workqueues and disable them. |
| 2524 | */ |
| 2525 | static int dm_hw_fini(void *handle) |
| 2526 | { |
| 2527 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2528 | |
| 2529 | amdgpu_dm_hpd_fini(adev); |
| 2530 | |
| 2531 | amdgpu_dm_irq_fini(adev); |
| 2532 | amdgpu_dm_fini(adev); |
| 2533 | return 0; |
| 2534 | } |
| 2535 | |
| 2536 | |
| 2537 | static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev, |
| 2538 | struct dc_state *state, bool_Bool enable) |
| 2539 | { |
| 2540 | enum dc_irq_source irq_source; |
| 2541 | struct amdgpu_crtc *acrtc; |
| 2542 | int rc = -EBUSY16; |
| 2543 | int i = 0; |
| 2544 | |
| 2545 | for (i = 0; i < state->stream_count; i++) { |
| 2546 | acrtc = get_crtc_by_otg_inst( |
| 2547 | adev, state->stream_status[i].primary_otg_inst); |
| 2548 | |
| 2549 | if (acrtc && state->stream_status[i].plane_count != 0) { |
| 2550 | irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst; |
| 2551 | rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY16; |
| 2552 | DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",___drm_dbg(((void *)0), DRM_UT_VBL, "crtc %d - vupdate irq %sabling: r=%d\n" , acrtc->crtc_id, enable ? "en" : "dis", rc) |
| 2553 | acrtc->crtc_id, enable ? "en" : "dis", rc)___drm_dbg(((void *)0), DRM_UT_VBL, "crtc %d - vupdate irq %sabling: r=%d\n" , acrtc->crtc_id, enable ? "en" : "dis", rc); |
| 2554 | if (rc) |
| 2555 | DRM_WARN("Failed to %s pflip interrupts\n",printk("\0014" "[" "drm" "] " "Failed to %s pflip interrupts\n" , enable ? "enable" : "disable") |
| 2556 | enable ? "enable" : "disable")printk("\0014" "[" "drm" "] " "Failed to %s pflip interrupts\n" , enable ? "enable" : "disable"); |
| 2557 | |
| 2558 | if (enable) { |
| 2559 | rc = dm_enable_vblank(&acrtc->base); |
| 2560 | if (rc) |
| 2561 | DRM_WARN("Failed to enable vblank interrupts\n")printk("\0014" "[" "drm" "] " "Failed to enable vblank interrupts\n" ); |
| 2562 | } else { |
| 2563 | dm_disable_vblank(&acrtc->base); |
| 2564 | } |
| 2565 | |
| 2566 | } |
| 2567 | } |
| 2568 | |
| 2569 | } |
| 2570 | |
| 2571 | static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc) |
| 2572 | { |
| 2573 | struct dc_state *context = NULL((void *)0); |
| 2574 | enum dc_status res = DC_ERROR_UNEXPECTED; |
| 2575 | int i; |
| 2576 | struct dc_stream_state *del_streams[MAX_PIPES6]; |
| 2577 | int del_streams_count = 0; |
| 2578 | |
| 2579 | memset(del_streams, 0, sizeof(del_streams))__builtin_memset((del_streams), (0), (sizeof(del_streams))); |
| 2580 | |
| 2581 | context = dc_create_state(dc); |
| 2582 | if (context == NULL((void *)0)) |
| 2583 | goto context_alloc_fail; |
| 2584 | |
| 2585 | dc_resource_state_copy_construct_current(dc, context); |
| 2586 | |
| 2587 | /* First remove from context all streams */ |
| 2588 | for (i = 0; i < context->stream_count; i++) { |
| 2589 | struct dc_stream_state *stream = context->streams[i]; |
| 2590 | |
| 2591 | del_streams[del_streams_count++] = stream; |
| 2592 | } |
| 2593 | |
| 2594 | /* Remove all planes for removed streams and then remove the streams */ |
| 2595 | for (i = 0; i < del_streams_count; i++) { |
| 2596 | if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) { |
| 2597 | res = DC_FAIL_DETACH_SURFACES; |
| 2598 | goto fail; |
| 2599 | } |
| 2600 | |
| 2601 | res = dc_remove_stream_from_ctx(dc, context, del_streams[i]); |
| 2602 | if (res != DC_OK) |
| 2603 | goto fail; |
| 2604 | } |
| 2605 | |
| 2606 | res = dc_commit_state(dc, context); |
| 2607 | |
| 2608 | fail: |
| 2609 | dc_release_state(context); |
| 2610 | |
| 2611 | context_alloc_fail: |
| 2612 | return res; |
| 2613 | } |
| 2614 | |
| 2615 | static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) |
| 2616 | { |
| 2617 | int i; |
| 2618 | |
| 2619 | if (dm->hpd_rx_offload_wq) { |
| 2620 | for (i = 0; i < dm->dc->caps.max_links; i++) |
| 2621 | flush_workqueue(dm->hpd_rx_offload_wq[i].wq); |
| 2622 | } |
| 2623 | } |
| 2624 | |
| 2625 | static int dm_suspend(void *handle) |
| 2626 | { |
| 2627 | struct amdgpu_device *adev = handle; |
| 2628 | struct amdgpu_display_manager *dm = &adev->dm; |
| 2629 | int ret = 0; |
| 2630 | |
| 2631 | if (amdgpu_in_reset(adev)) { |
| 2632 | mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock); |
| 2633 | |
| 2634 | dc_allow_idle_optimizations(adev->dm.dc, false0); |
| 2635 | |
| 2636 | dm->cached_dc_state = dc_copy_state(dm->dc->current_state); |
| 2637 | |
| 2638 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false0); |
| 2639 | |
| 2640 | amdgpu_dm_commit_zero_streams(dm->dc); |
| 2641 | |
| 2642 | amdgpu_dm_irq_suspend(adev); |
| 2643 | |
| 2644 | hpd_rx_irq_work_suspend(dm); |
| 2645 | |
| 2646 | return ret; |
| 2647 | } |
| 2648 | |
| 2649 | WARN_ON(adev->dm.cached_state)({ int __ret = !!(adev->dm.cached_state); if (__ret) printf ("WARNING %s failed at %s:%d\n", "adev->dm.cached_state", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 2649); __builtin_expect(!!(__ret), 0); }); |
| 2650 | adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); |
| 2651 | |
| 2652 | s3_handle_mst(adev_to_drm(adev), true1); |
| 2653 | |
| 2654 | amdgpu_dm_irq_suspend(adev); |
| 2655 | |
| 2656 | hpd_rx_irq_work_suspend(dm); |
| 2657 | |
| 2658 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); |
| 2659 | |
| 2660 | return 0; |
| 2661 | } |
| 2662 | |
| 2663 | struct amdgpu_dm_connector * |
| 2664 | amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, |
| 2665 | struct drm_crtc *crtc) |
| 2666 | { |
| 2667 | u32 i; |
| 2668 | struct drm_connector_state *new_con_state; |
| 2669 | struct drm_connector *connector; |
| 2670 | struct drm_crtc *crtc_from_state; |
| 2671 | |
| 2672 | for_each_new_connector_in_state(state, connector, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if ( !((state)->connectors[i].ptr && ((connector) = (state )->connectors[i].ptr, (void)(connector) , (new_con_state) = (state)->connectors[i].new_state, (void)(new_con_state) , 1))) {} else { |
| 2673 | crtc_from_state = new_con_state->crtc; |
| 2674 | |
| 2675 | if (crtc_from_state == crtc) |
| 2676 | return to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 2677 | } |
| 2678 | |
| 2679 | return NULL((void *)0); |
| 2680 | } |
| 2681 | |
| 2682 | static void emulated_link_detect(struct dc_link *link) |
| 2683 | { |
| 2684 | struct dc_sink_init_data sink_init_data = { 0 }; |
| 2685 | struct display_sink_capability sink_caps = { 0 }; |
| 2686 | enum dc_edid_status edid_status; |
| 2687 | struct dc_context *dc_ctx = link->ctx; |
| 2688 | struct dc_sink *sink = NULL((void *)0); |
| 2689 | struct dc_sink *prev_sink = NULL((void *)0); |
| 2690 | |
| 2691 | link->type = dc_connection_none; |
| 2692 | prev_sink = link->local_sink; |
| 2693 | |
| 2694 | if (prev_sink) |
| 2695 | dc_sink_release(prev_sink); |
| 2696 | |
| 2697 | switch (link->connector_signal) { |
| 2698 | case SIGNAL_TYPE_HDMI_TYPE_A: { |
| 2699 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; |
| 2700 | sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; |
| 2701 | break; |
| 2702 | } |
| 2703 | |
| 2704 | case SIGNAL_TYPE_DVI_SINGLE_LINK: { |
| 2705 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; |
| 2706 | sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; |
| 2707 | break; |
| 2708 | } |
| 2709 | |
| 2710 | case SIGNAL_TYPE_DVI_DUAL_LINK: { |
| 2711 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; |
| 2712 | sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; |
| 2713 | break; |
| 2714 | } |
| 2715 | |
| 2716 | case SIGNAL_TYPE_LVDS: { |
| 2717 | sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; |
| 2718 | sink_caps.signal = SIGNAL_TYPE_LVDS; |
| 2719 | break; |
| 2720 | } |
| 2721 | |
| 2722 | case SIGNAL_TYPE_EDP: { |
| 2723 | sink_caps.transaction_type = |
| 2724 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; |
| 2725 | sink_caps.signal = SIGNAL_TYPE_EDP; |
| 2726 | break; |
| 2727 | } |
| 2728 | |
| 2729 | case SIGNAL_TYPE_DISPLAY_PORT: { |
| 2730 | sink_caps.transaction_type = |
| 2731 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; |
| 2732 | sink_caps.signal = SIGNAL_TYPE_VIRTUAL; |
| 2733 | break; |
| 2734 | } |
| 2735 | |
| 2736 | default: |
| 2737 | DC_ERROR("Invalid connector type! signal:%d\n",do { (void)(dc_ctx); __drm_err("Invalid connector type! signal:%d\n" , link->connector_signal); } while (0) |
| 2738 | link->connector_signal)do { (void)(dc_ctx); __drm_err("Invalid connector type! signal:%d\n" , link->connector_signal); } while (0); |
| 2739 | return; |
| 2740 | } |
| 2741 | |
| 2742 | sink_init_data.link = link; |
| 2743 | sink_init_data.sink_signal = sink_caps.signal; |
| 2744 | |
| 2745 | sink = dc_sink_create(&sink_init_data); |
| 2746 | if (!sink) { |
| 2747 | DC_ERROR("Failed to create sink!\n")do { (void)(dc_ctx); __drm_err("Failed to create sink!\n"); } while (0); |
| 2748 | return; |
| 2749 | } |
| 2750 | |
| 2751 | /* dc_sink_create returns a new reference */ |
| 2752 | link->local_sink = sink; |
| 2753 | |
| 2754 | edid_status = dm_helpers_read_local_edid( |
| 2755 | link->ctx, |
| 2756 | link, |
| 2757 | sink); |
| 2758 | |
| 2759 | if (edid_status != EDID_OK) |
| 2760 | DC_ERROR("Failed to read EDID")do { (void)(dc_ctx); __drm_err("Failed to read EDID"); } while (0); |
| 2761 | |
| 2762 | } |
| 2763 | |
| 2764 | static void dm_gpureset_commit_state(struct dc_state *dc_state, |
| 2765 | struct amdgpu_display_manager *dm) |
| 2766 | { |
| 2767 | struct { |
| 2768 | struct dc_surface_update surface_updates[MAX_SURFACES3]; |
| 2769 | struct dc_plane_info plane_infos[MAX_SURFACES3]; |
| 2770 | struct dc_scaling_info scaling_infos[MAX_SURFACES3]; |
| 2771 | struct dc_flip_addrs flip_addrs[MAX_SURFACES3]; |
| 2772 | struct dc_stream_update stream_update; |
| 2773 | } *bundle; |
| 2774 | int k, m; |
| 2775 | |
| 2776 | bundle = kzalloc(sizeof(*bundle), GFP_KERNEL(0x0001 | 0x0004)); |
| 2777 | |
| 2778 | if (!bundle) { |
| 2779 | dm_error("Failed to allocate update bundle\n")__drm_err("Failed to allocate update bundle\n"); |
| 2780 | goto cleanup; |
| 2781 | } |
| 2782 | |
| 2783 | for (k = 0; k < dc_state->stream_count; k++) { |
| 2784 | bundle->stream_update.stream = dc_state->streams[k]; |
| 2785 | |
| 2786 | for (m = 0; m < dc_state->stream_status->plane_count; m++) { |
| 2787 | bundle->surface_updates[m].surface = |
| 2788 | dc_state->stream_status->plane_states[m]; |
| 2789 | bundle->surface_updates[m].surface->force_full_update = |
| 2790 | true1; |
| 2791 | } |
| 2792 | |
| 2793 | update_planes_and_stream_adapter(dm->dc, |
| 2794 | UPDATE_TYPE_FULL, |
| 2795 | dc_state->stream_status->plane_count, |
| 2796 | dc_state->streams[k], |
| 2797 | &bundle->stream_update, |
| 2798 | bundle->surface_updates); |
| 2799 | } |
| 2800 | |
| 2801 | cleanup: |
| 2802 | kfree(bundle); |
| 2803 | } |
| 2804 | |
| 2805 | static int dm_resume(void *handle) |
| 2806 | { |
| 2807 | struct amdgpu_device *adev = handle; |
| 2808 | struct drm_device *ddev = adev_to_drm(adev); |
| 2809 | struct amdgpu_display_manager *dm = &adev->dm; |
| 2810 | struct amdgpu_dm_connector *aconnector; |
| 2811 | struct drm_connector *connector; |
| 2812 | struct drm_connector_list_iter iter; |
| 2813 | struct drm_crtc *crtc; |
| 2814 | struct drm_crtc_state *new_crtc_state; |
| 2815 | struct dm_crtc_state *dm_new_crtc_state; |
| 2816 | struct drm_plane *plane; |
| 2817 | struct drm_plane_state *new_plane_state; |
| 2818 | struct dm_plane_state *dm_new_plane_state; |
| 2819 | struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) * __mptr = (dm->atomic_obj.state); (struct dm_atomic_state * )( (char *)__mptr - __builtin_offsetof(struct dm_atomic_state , base) );}); |
| 2820 | enum dc_connection_type new_connection_type = dc_connection_none; |
| 2821 | struct dc_state *dc_state; |
| 2822 | int i, r, j, ret; |
| 2823 | bool_Bool need_hotplug = false0; |
| 2824 | |
| 2825 | if (amdgpu_in_reset(adev)) { |
| 2826 | dc_state = dm->cached_dc_state; |
| 2827 | |
| 2828 | /* |
| 2829 | * The dc->current_state is backed up into dm->cached_dc_state |
| 2830 | * before we commit 0 streams. |
| 2831 | * |
| 2832 | * DC will clear link encoder assignments on the real state |
| 2833 | * but the changes won't propagate over to the copy we made |
| 2834 | * before the 0 streams commit. |
| 2835 | * |
| 2836 | * DC expects that link encoder assignments are *not* valid |
| 2837 | * when committing a state, so as a workaround we can copy |
| 2838 | * off of the current state. |
| 2839 | * |
| 2840 | * We lose the previous assignments, but we had already |
| 2841 | * commit 0 streams anyway. |
| 2842 | */ |
| 2843 | link_enc_cfg_copy(adev->dm.dc->current_state, dc_state); |
| 2844 | |
| 2845 | r = dm_dmub_hw_init(adev); |
| 2846 | if (r) |
| 2847 | DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r)__drm_err("DMUB interface failed to initialize: status=%d\n", r); |
| 2848 | |
| 2849 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); |
| 2850 | dc_resume(dm->dc); |
| 2851 | |
| 2852 | amdgpu_dm_irq_resume_early(adev); |
| 2853 | |
| 2854 | for (i = 0; i < dc_state->stream_count; i++) { |
| 2855 | dc_state->streams[i]->mode_changed = true1; |
| 2856 | for (j = 0; j < dc_state->stream_status[i].plane_count; j++) { |
| 2857 | dc_state->stream_status[i].plane_states[j]->update_flags.raw |
| 2858 | = 0xffffffff; |
| 2859 | } |
| 2860 | } |
| 2861 | |
| 2862 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
| 2863 | amdgpu_dm_outbox_init(adev); |
| 2864 | dc_enable_dmub_outbox(adev->dm.dc); |
| 2865 | } |
| 2866 | |
| 2867 | WARN_ON(!dc_commit_state(dm->dc, dc_state))({ int __ret = !!(!dc_commit_state(dm->dc, dc_state)); if ( __ret) printf("WARNING %s failed at %s:%d\n", "!dc_commit_state(dm->dc, dc_state)" , "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 2867); __builtin_expect(!!(__ret), 0); }); |
| 2868 | |
| 2869 | dm_gpureset_commit_state(dm->cached_dc_state, dm); |
| 2870 | |
| 2871 | dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true1); |
| 2872 | |
| 2873 | dc_release_state(dm->cached_dc_state); |
| 2874 | dm->cached_dc_state = NULL((void *)0); |
| 2875 | |
| 2876 | amdgpu_dm_irq_resume_late(adev); |
| 2877 | |
| 2878 | mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock); |
| 2879 | |
| 2880 | return 0; |
| 2881 | } |
| 2882 | /* Recreate dc_state - DC invalidates it when setting power state to S3. */ |
| 2883 | dc_release_state(dm_state->context); |
| 2884 | dm_state->context = dc_create_state(dm->dc); |
| 2885 | /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ |
| 2886 | dc_resource_state_construct(dm->dc, dm_state->context); |
| 2887 | |
| 2888 | /* Before powering on DC we need to re-initialize DMUB. */ |
| 2889 | dm_dmub_hw_resume(adev); |
| 2890 | |
| 2891 | /* Re-enable outbox interrupts for DPIA. */ |
| 2892 | if (dc_is_dmub_outbox_supported(adev->dm.dc)) { |
| 2893 | amdgpu_dm_outbox_init(adev); |
| 2894 | dc_enable_dmub_outbox(adev->dm.dc); |
| 2895 | } |
| 2896 | |
| 2897 | /* power on hardware */ |
| 2898 | dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); |
| 2899 | |
| 2900 | /* program HPD filter */ |
| 2901 | dc_resume(dm->dc); |
| 2902 | |
| 2903 | /* |
| 2904 | * early enable HPD Rx IRQ, should be done before set mode as short |
| 2905 | * pulse interrupts are used for MST |
| 2906 | */ |
| 2907 | amdgpu_dm_irq_resume_early(adev); |
| 2908 | |
| 2909 | /* On resume we need to rewrite the MSTM control bits to enable MST*/ |
| 2910 | s3_handle_mst(ddev, false0); |
| 2911 | |
| 2912 | /* Do detection*/ |
| 2913 | drm_connector_list_iter_begin(ddev, &iter); |
| 2914 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 2915 | aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 2916 | |
| 2917 | if (!aconnector->dc_link) |
| 2918 | continue; |
| 2919 | |
| 2920 | /* |
| 2921 | * this is the case when traversing through already created end sink |
| 2922 | * MST connectors, should be skipped |
| 2923 | */ |
| 2924 | if (aconnector && aconnector->mst_port) |
| 2925 | continue; |
| 2926 | |
| 2927 | mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock); |
| 2928 | if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) |
| 2929 | DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n"); |
| 2930 | |
| 2931 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
| 2932 | emulated_link_detect(aconnector->dc_link); |
| 2933 | } else { |
| 2934 | mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock); |
| 2935 | dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); |
| 2936 | mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock); |
| 2937 | } |
| 2938 | |
| 2939 | if (aconnector->fake_enable && aconnector->dc_link->local_sink) |
| 2940 | aconnector->fake_enable = false0; |
| 2941 | |
| 2942 | if (aconnector->dc_sink) |
| 2943 | dc_sink_release(aconnector->dc_sink); |
| 2944 | aconnector->dc_sink = NULL((void *)0); |
| 2945 | amdgpu_dm_update_connector_after_detect(aconnector); |
| 2946 | mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock); |
| 2947 | } |
| 2948 | drm_connector_list_iter_end(&iter); |
| 2949 | |
| 2950 | /* Force mode set in atomic commit */ |
| 2951 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config .num_crtc; (i)++) if (!((dm->cached_state)->crtcs[i].ptr && ((crtc) = (dm->cached_state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (dm->cached_state)-> crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else |
| 2952 | new_crtc_state->active_changed = true1; |
| 2953 | |
| 2954 | /* |
| 2955 | * atomic_check is expected to create the dc states. We need to release |
| 2956 | * them here, since they were duplicated as part of the suspend |
| 2957 | * procedure. |
| 2958 | */ |
| 2959 | for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config .num_crtc; (i)++) if (!((dm->cached_state)->crtcs[i].ptr && ((crtc) = (dm->cached_state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (dm->cached_state)-> crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else { |
| 2960 | dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct dm_crtc_state, base) );}); |
| 2961 | if (dm_new_crtc_state->stream) { |
| 2962 | WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1)({ int __ret = !!(kref_read(&dm_new_crtc_state->stream ->refcount) > 1); if (__ret) printf("WARNING %s failed at %s:%d\n" , "kref_read(&dm_new_crtc_state->stream->refcount) > 1" , "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 2962); __builtin_expect(!!(__ret), 0); }); |
| 2963 | dc_stream_release(dm_new_crtc_state->stream); |
| 2964 | dm_new_crtc_state->stream = NULL((void *)0); |
| 2965 | } |
| 2966 | } |
| 2967 | |
| 2968 | for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config .num_total_plane; (i)++) if (!((dm->cached_state)->planes [i].ptr && ((plane) = (dm->cached_state)->planes [i].ptr, (void)(plane) , (new_plane_state) = (dm->cached_state )->planes[i].new_state, (void)(new_plane_state) , 1))) {} else { |
| 2969 | dm_new_plane_state = to_dm_plane_state(new_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr = (new_plane_state); (struct dm_plane_state *)( (char *)__mptr - __builtin_offsetof(struct dm_plane_state, base) );}); |
| 2970 | if (dm_new_plane_state->dc_state) { |
| 2971 | WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1)({ int __ret = !!(kref_read(&dm_new_plane_state->dc_state ->refcount) > 1); if (__ret) printf("WARNING %s failed at %s:%d\n" , "kref_read(&dm_new_plane_state->dc_state->refcount) > 1" , "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 2971); __builtin_expect(!!(__ret), 0); }); |
| 2972 | dc_plane_state_release(dm_new_plane_state->dc_state); |
| 2973 | dm_new_plane_state->dc_state = NULL((void *)0); |
| 2974 | } |
| 2975 | } |
| 2976 | |
| 2977 | drm_atomic_helper_resume(ddev, dm->cached_state); |
| 2978 | |
| 2979 | dm->cached_state = NULL((void *)0); |
| 2980 | |
| 2981 | /* Do mst topology probing after resuming cached state*/ |
| 2982 | drm_connector_list_iter_begin(ddev, &iter); |
| 2983 | drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) { |
| 2984 | aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 2985 | if (aconnector->dc_link->type != dc_connection_mst_branch || |
| 2986 | aconnector->mst_port) |
| 2987 | continue; |
| 2988 | |
| 2989 | ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true1); |
| 2990 | |
| 2991 | if (ret < 0) { |
| 2992 | dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, |
| 2993 | aconnector->dc_link); |
| 2994 | need_hotplug = true1; |
| 2995 | } |
| 2996 | } |
| 2997 | drm_connector_list_iter_end(&iter); |
| 2998 | |
| 2999 | if (need_hotplug) |
| 3000 | drm_kms_helper_hotplug_event(ddev); |
| 3001 | |
| 3002 | amdgpu_dm_irq_resume_late(adev); |
| 3003 | |
| 3004 | amdgpu_dm_smu_write_watermarks_table(adev); |
| 3005 | |
| 3006 | return 0; |
| 3007 | } |
| 3008 | |
| 3009 | /** |
| 3010 | * DOC: DM Lifecycle |
| 3011 | * |
| 3012 | * DM (and consequently DC) is registered in the amdgpu base driver as a IP |
| 3013 | * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to |
| 3014 | * the base driver's device list to be initialized and torn down accordingly. |
| 3015 | * |
| 3016 | * The functions to do so are provided as hooks in &struct amd_ip_funcs. |
| 3017 | */ |
| 3018 | |
| 3019 | static const struct amd_ip_funcs amdgpu_dm_funcs = { |
| 3020 | .name = "dm", |
| 3021 | .early_init = dm_early_init, |
| 3022 | .late_init = dm_late_init, |
| 3023 | .sw_init = dm_sw_init, |
| 3024 | .sw_fini = dm_sw_fini, |
| 3025 | .early_fini = amdgpu_dm_early_fini, |
| 3026 | .hw_init = dm_hw_init, |
| 3027 | .hw_fini = dm_hw_fini, |
| 3028 | .suspend = dm_suspend, |
| 3029 | .resume = dm_resume, |
| 3030 | .is_idle = dm_is_idle, |
| 3031 | .wait_for_idle = dm_wait_for_idle, |
| 3032 | .check_soft_reset = dm_check_soft_reset, |
| 3033 | .soft_reset = dm_soft_reset, |
| 3034 | .set_clockgating_state = dm_set_clockgating_state, |
| 3035 | .set_powergating_state = dm_set_powergating_state, |
| 3036 | }; |
| 3037 | |
| 3038 | const struct amdgpu_ip_block_version dm_ip_block = { |
| 3039 | .type = AMD_IP_BLOCK_TYPE_DCE, |
| 3040 | .major = 1, |
| 3041 | .minor = 0, |
| 3042 | .rev = 0, |
| 3043 | .funcs = &amdgpu_dm_funcs, |
| 3044 | }; |
| 3045 | |
| 3046 | |
| 3047 | /** |
| 3048 | * DOC: atomic |
| 3049 | * |
| 3050 | * *WIP* |
| 3051 | */ |
| 3052 | |
| 3053 | static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { |
| 3054 | .fb_create = amdgpu_display_user_framebuffer_create, |
| 3055 | .get_format_info = amd_get_format_info, |
| 3056 | .atomic_check = amdgpu_dm_atomic_check, |
| 3057 | .atomic_commit = drm_atomic_helper_commit, |
| 3058 | }; |
| 3059 | |
| 3060 | static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { |
| 3061 | .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, |
| 3062 | .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, |
| 3063 | }; |
| 3064 | |
| 3065 | static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) |
| 3066 | { |
| 3067 | struct amdgpu_dm_backlight_caps *caps; |
| 3068 | struct amdgpu_display_manager *dm; |
| 3069 | struct drm_connector *conn_base; |
| 3070 | struct amdgpu_device *adev; |
| 3071 | struct dc_link *link = NULL((void *)0); |
| 3072 | struct drm_luminance_range_info *luminance_range; |
| 3073 | int i; |
| 3074 | |
| 3075 | if (!aconnector || !aconnector->dc_link) |
| 3076 | return; |
| 3077 | |
| 3078 | link = aconnector->dc_link; |
| 3079 | if (link->connector_signal != SIGNAL_TYPE_EDP) |
| 3080 | return; |
| 3081 | |
| 3082 | conn_base = &aconnector->base; |
| 3083 | adev = drm_to_adev(conn_base->dev); |
| 3084 | dm = &adev->dm; |
| 3085 | for (i = 0; i < dm->num_of_edps; i++) { |
| 3086 | if (link == dm->backlight_link[i]) |
| 3087 | break; |
| 3088 | } |
| 3089 | if (i >= dm->num_of_edps) |
| 3090 | return; |
| 3091 | caps = &dm->backlight_caps[i]; |
| 3092 | caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; |
| 3093 | caps->aux_support = false0; |
| 3094 | |
| 3095 | if (caps->ext_caps->bits.oled == 1 |
| 3096 | /* |
| 3097 | * || |
| 3098 | * caps->ext_caps->bits.sdr_aux_backlight_control == 1 || |
| 3099 | * caps->ext_caps->bits.hdr_aux_backlight_control == 1 |
| 3100 | */) |
| 3101 | caps->aux_support = true1; |
| 3102 | |
| 3103 | if (amdgpu_backlight == 0) |
| 3104 | caps->aux_support = false0; |
| 3105 | else if (amdgpu_backlight == 1) |
| 3106 | caps->aux_support = true1; |
| 3107 | |
| 3108 | luminance_range = &conn_base->display_info.luminance_range; |
| 3109 | caps->aux_min_input_signal = luminance_range->min_luminance; |
| 3110 | caps->aux_max_input_signal = luminance_range->max_luminance; |
| 3111 | } |
| 3112 | |
| 3113 | void amdgpu_dm_update_connector_after_detect( |
| 3114 | struct amdgpu_dm_connector *aconnector) |
| 3115 | { |
| 3116 | struct drm_connector *connector = &aconnector->base; |
| 3117 | struct drm_device *dev = connector->dev; |
| 3118 | struct dc_sink *sink; |
| 3119 | |
| 3120 | /* MST handled by drm_mst framework */ |
| 3121 | if (aconnector->mst_mgr.mst_state == true1) |
| 3122 | return; |
| 3123 | |
| 3124 | sink = aconnector->dc_link->local_sink; |
| 3125 | if (sink) |
| 3126 | dc_sink_retain(sink); |
| 3127 | |
| 3128 | /* |
| 3129 | * Edid mgmt connector gets first update only in mode_valid hook and then |
| 3130 | * the connector sink is set to either fake or physical sink depends on link status. |
| 3131 | * Skip if already done during boot. |
| 3132 | */ |
| 3133 | if (aconnector->base.force != DRM_FORCE_UNSPECIFIED |
| 3134 | && aconnector->dc_em_sink) { |
| 3135 | |
| 3136 | /* |
| 3137 | * For S3 resume with headless use eml_sink to fake stream |
| 3138 | * because on resume connector->sink is set to NULL |
| 3139 | */ |
| 3140 | mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex); |
| 3141 | |
| 3142 | if (sink) { |
| 3143 | if (aconnector->dc_sink) { |
| 3144 | amdgpu_dm_update_freesync_caps(connector, NULL((void *)0)); |
| 3145 | /* |
| 3146 | * retain and release below are used to |
| 3147 | * bump up refcount for sink because the link doesn't point |
| 3148 | * to it anymore after disconnect, so on next crtc to connector |
| 3149 | * reshuffle by UMD we will get into unwanted dc_sink release |
| 3150 | */ |
| 3151 | dc_sink_release(aconnector->dc_sink); |
| 3152 | } |
| 3153 | aconnector->dc_sink = sink; |
| 3154 | dc_sink_retain(aconnector->dc_sink); |
| 3155 | amdgpu_dm_update_freesync_caps(connector, |
| 3156 | aconnector->edid); |
| 3157 | } else { |
| 3158 | amdgpu_dm_update_freesync_caps(connector, NULL((void *)0)); |
| 3159 | if (!aconnector->dc_sink) { |
| 3160 | aconnector->dc_sink = aconnector->dc_em_sink; |
| 3161 | dc_sink_retain(aconnector->dc_sink); |
| 3162 | } |
| 3163 | } |
| 3164 | |
| 3165 | mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex); |
| 3166 | |
| 3167 | if (sink) |
| 3168 | dc_sink_release(sink); |
| 3169 | return; |
| 3170 | } |
| 3171 | |
| 3172 | /* |
| 3173 | * TODO: temporary guard to look for proper fix |
| 3174 | * if this sink is MST sink, we should not do anything |
| 3175 | */ |
| 3176 | if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { |
| 3177 | dc_sink_release(sink); |
| 3178 | return; |
| 3179 | } |
| 3180 | |
| 3181 | if (aconnector->dc_sink == sink) { |
| 3182 | /* |
| 3183 | * We got a DP short pulse (Link Loss, DP CTS, etc...). |
| 3184 | * Do nothing!! |
| 3185 | */ |
| 3186 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "DCHPD: connector_id=%d: dc_sink didn't change.\n" , aconnector->connector_id) |
| 3187 | aconnector->connector_id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DCHPD: connector_id=%d: dc_sink didn't change.\n" , aconnector->connector_id); |
| 3188 | if (sink) |
| 3189 | dc_sink_release(sink); |
| 3190 | return; |
| 3191 | } |
| 3192 | |
| 3193 | DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n" , aconnector->connector_id, aconnector->dc_sink, sink) |
| 3194 | aconnector->connector_id, aconnector->dc_sink, sink)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n" , aconnector->connector_id, aconnector->dc_sink, sink); |
| 3195 | |
| 3196 | mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex); |
| 3197 | |
| 3198 | /* |
| 3199 | * 1. Update status of the drm connector |
| 3200 | * 2. Send an event and let userspace tell us what to do |
| 3201 | */ |
| 3202 | if (sink) { |
| 3203 | /* |
| 3204 | * TODO: check if we still need the S3 mode update workaround. |
| 3205 | * If yes, put it here. |
| 3206 | */ |
| 3207 | if (aconnector->dc_sink) { |
| 3208 | amdgpu_dm_update_freesync_caps(connector, NULL((void *)0)); |
| 3209 | dc_sink_release(aconnector->dc_sink); |
| 3210 | } |
| 3211 | |
| 3212 | aconnector->dc_sink = sink; |
| 3213 | dc_sink_retain(aconnector->dc_sink); |
| 3214 | if (sink->dc_edid.length == 0) { |
| 3215 | aconnector->edid = NULL((void *)0); |
| 3216 | if (aconnector->dc_link->aux_mode) { |
| 3217 | drm_dp_cec_unset_edid( |
| 3218 | &aconnector->dm_dp_aux.aux); |
| 3219 | } |
| 3220 | } else { |
| 3221 | aconnector->edid = |
| 3222 | (struct edid *)sink->dc_edid.raw_edid; |
| 3223 | |
| 3224 | if (aconnector->dc_link->aux_mode) |
| 3225 | drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, |
| 3226 | aconnector->edid); |
| 3227 | } |
| 3228 | |
| 3229 | aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL(0x0001 | 0x0004)); |
| 3230 | if (!aconnector->timing_requested) |
| 3231 | dm_error("%s: failed to create aconnector->requested_timing\n", __func__)__drm_err("%s: failed to create aconnector->requested_timing\n" , __func__); |
| 3232 | |
| 3233 | drm_connector_update_edid_property(connector, aconnector->edid); |
| 3234 | amdgpu_dm_update_freesync_caps(connector, aconnector->edid); |
| 3235 | update_connector_ext_caps(aconnector); |
| 3236 | } else { |
| 3237 | drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); |
| 3238 | amdgpu_dm_update_freesync_caps(connector, NULL((void *)0)); |
| 3239 | drm_connector_update_edid_property(connector, NULL((void *)0)); |
| 3240 | aconnector->num_modes = 0; |
| 3241 | dc_sink_release(aconnector->dc_sink); |
| 3242 | aconnector->dc_sink = NULL((void *)0); |
| 3243 | aconnector->edid = NULL((void *)0); |
| 3244 | kfree(aconnector->timing_requested); |
| 3245 | aconnector->timing_requested = NULL((void *)0); |
| 3246 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 3247 | /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ |
| 3248 | if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2) |
| 3249 | connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1; |
| 3250 | #endif |
| 3251 | } |
| 3252 | |
| 3253 | mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex); |
| 3254 | |
| 3255 | update_subconnector_property(aconnector); |
| 3256 | |
| 3257 | if (sink) |
| 3258 | dc_sink_release(sink); |
| 3259 | } |
| 3260 | |
| 3261 | static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) |
| 3262 | { |
| 3263 | struct drm_connector *connector = &aconnector->base; |
| 3264 | struct drm_device *dev = connector->dev; |
| 3265 | enum dc_connection_type new_connection_type = dc_connection_none; |
| 3266 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 3267 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 3268 | struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base ) *__mptr = ((connector->state)); (struct dm_connector_state *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state , base) );}); |
| 3269 | #endif |
| 3270 | bool_Bool ret = false0; |
| 3271 | |
| 3272 | if (adev->dm.disable_hpd_irq) |
| 3273 | return; |
| 3274 | |
| 3275 | /* |
| 3276 | * In case of failure or MST no need to update connector status or notify the OS |
| 3277 | * since (for MST case) MST does this in its own context. |
| 3278 | */ |
| 3279 | mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock); |
| 3280 | |
| 3281 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 3282 | if (adev->dm.hdcp_workqueue) { |
| 3283 | hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index); |
| 3284 | dm_con_state->update_hdcp = true1; |
| 3285 | } |
| 3286 | #endif |
| 3287 | if (aconnector->fake_enable) |
| 3288 | aconnector->fake_enable = false0; |
| 3289 | |
| 3290 | aconnector->timing_changed = false0; |
| 3291 | |
| 3292 | if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type)) |
| 3293 | DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n"); |
| 3294 | |
| 3295 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
| 3296 | emulated_link_detect(aconnector->dc_link); |
| 3297 | |
| 3298 | drm_modeset_lock_all(dev); |
| 3299 | dm_restore_drm_connector_state(dev, connector); |
| 3300 | drm_modeset_unlock_all(dev); |
| 3301 | |
| 3302 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) |
| 3303 | drm_kms_helper_connector_hotplug_event(connector); |
| 3304 | } else { |
| 3305 | mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock); |
| 3306 | ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); |
| 3307 | mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock); |
| 3308 | if (ret) { |
| 3309 | amdgpu_dm_update_connector_after_detect(aconnector); |
| 3310 | |
| 3311 | drm_modeset_lock_all(dev); |
| 3312 | dm_restore_drm_connector_state(dev, connector); |
| 3313 | drm_modeset_unlock_all(dev); |
| 3314 | |
| 3315 | if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) |
| 3316 | drm_kms_helper_connector_hotplug_event(connector); |
| 3317 | } |
| 3318 | } |
| 3319 | mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock); |
| 3320 | |
| 3321 | } |
| 3322 | |
| 3323 | static void handle_hpd_irq(void *param) |
| 3324 | { |
| 3325 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
| 3326 | |
| 3327 | handle_hpd_irq_helper(aconnector); |
| 3328 | |
| 3329 | } |
| 3330 | |
| 3331 | static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq, |
| 3332 | union hpd_irq_data hpd_irq_data) |
| 3333 | { |
| 3334 | struct hpd_rx_irq_offload_work *offload_work = |
| 3335 | kzalloc(sizeof(*offload_work), GFP_KERNEL(0x0001 | 0x0004)); |
| 3336 | |
| 3337 | if (!offload_work) { |
| 3338 | DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n")__drm_err("Failed to allocate hpd_rx_irq_offload_work.\n"); |
| 3339 | return; |
| 3340 | } |
| 3341 | |
| 3342 | INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work); |
| 3343 | offload_work->data = hpd_irq_data; |
| 3344 | offload_work->offload_wq = offload_wq; |
| 3345 | |
| 3346 | queue_work(offload_wq->wq, &offload_work->work); |
| 3347 | DRM_DEBUG_KMS("queue work to handle hpd_rx offload work")___drm_dbg(((void *)0), DRM_UT_KMS, "queue work to handle hpd_rx offload work" ); |
| 3348 | } |
| 3349 | |
| 3350 | static void handle_hpd_rx_irq(void *param) |
| 3351 | { |
| 3352 | struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; |
| 3353 | struct drm_connector *connector = &aconnector->base; |
| 3354 | struct drm_device *dev = connector->dev; |
| 3355 | struct dc_link *dc_link = aconnector->dc_link; |
| 3356 | bool_Bool is_mst_root_connector = aconnector->mst_mgr.mst_state; |
| 3357 | bool_Bool result = false0; |
| 3358 | enum dc_connection_type new_connection_type = dc_connection_none; |
| 3359 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 3360 | union hpd_irq_data hpd_irq_data; |
| 3361 | bool_Bool link_loss = false0; |
| 3362 | bool_Bool has_left_work = false0; |
| 3363 | int idx = dc_link->link_index; |
| 3364 | struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx]; |
| 3365 | |
| 3366 | memset(&hpd_irq_data, 0, sizeof(hpd_irq_data))__builtin_memset((&hpd_irq_data), (0), (sizeof(hpd_irq_data ))); |
| 3367 | |
| 3368 | if (adev->dm.disable_hpd_irq) |
| 3369 | return; |
| 3370 | |
| 3371 | /* |
| 3372 | * TODO:Temporary add mutex to protect hpd interrupt not have a gpio |
| 3373 | * conflict, after implement i2c helper, this mutex should be |
| 3374 | * retired. |
| 3375 | */ |
| 3376 | mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock); |
| 3377 | |
| 3378 | result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, |
| 3379 | &link_loss, true1, &has_left_work); |
| 3380 | |
| 3381 | if (!has_left_work) |
| 3382 | goto out; |
| 3383 | |
| 3384 | if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) { |
| 3385 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); |
| 3386 | goto out; |
| 3387 | } |
| 3388 | |
| 3389 | if (dc_link_dp_allow_hpd_rx_irq(dc_link)) { |
| 3390 | if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY || |
| 3391 | hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) { |
| 3392 | bool_Bool skip = false0; |
| 3393 | |
| 3394 | /* |
| 3395 | * DOWN_REP_MSG_RDY is also handled by polling method |
| 3396 | * mgr->cbs->poll_hpd_irq() |
| 3397 | */ |
| 3398 | spin_lock(&offload_wq->offload_lock)mtx_enter(&offload_wq->offload_lock); |
| 3399 | skip = offload_wq->is_handling_mst_msg_rdy_event; |
| 3400 | |
| 3401 | if (!skip) |
| 3402 | offload_wq->is_handling_mst_msg_rdy_event = true1; |
| 3403 | |
| 3404 | spin_unlock(&offload_wq->offload_lock)mtx_leave(&offload_wq->offload_lock); |
| 3405 | |
| 3406 | if (!skip) |
| 3407 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); |
| 3408 | |
| 3409 | goto out; |
| 3410 | } |
| 3411 | |
| 3412 | if (link_loss) { |
| 3413 | bool_Bool skip = false0; |
| 3414 | |
| 3415 | spin_lock(&offload_wq->offload_lock)mtx_enter(&offload_wq->offload_lock); |
| 3416 | skip = offload_wq->is_handling_link_loss; |
| 3417 | |
| 3418 | if (!skip) |
| 3419 | offload_wq->is_handling_link_loss = true1; |
| 3420 | |
| 3421 | spin_unlock(&offload_wq->offload_lock)mtx_leave(&offload_wq->offload_lock); |
| 3422 | |
| 3423 | if (!skip) |
| 3424 | schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data); |
| 3425 | |
| 3426 | goto out; |
| 3427 | } |
| 3428 | } |
| 3429 | |
| 3430 | out: |
| 3431 | if (result && !is_mst_root_connector) { |
| 3432 | /* Downstream Port status changed. */ |
| 3433 | if (!dc_link_detect_sink(dc_link, &new_connection_type)) |
| 3434 | DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n"); |
| 3435 | |
| 3436 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
| 3437 | emulated_link_detect(dc_link); |
| 3438 | |
| 3439 | if (aconnector->fake_enable) |
| 3440 | aconnector->fake_enable = false0; |
| 3441 | |
| 3442 | amdgpu_dm_update_connector_after_detect(aconnector); |
| 3443 | |
| 3444 | |
| 3445 | drm_modeset_lock_all(dev); |
| 3446 | dm_restore_drm_connector_state(dev, connector); |
| 3447 | drm_modeset_unlock_all(dev); |
| 3448 | |
| 3449 | drm_kms_helper_connector_hotplug_event(connector); |
| 3450 | } else { |
| 3451 | bool_Bool ret = false0; |
| 3452 | |
| 3453 | mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock); |
| 3454 | ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX); |
| 3455 | mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock); |
| 3456 | |
| 3457 | if (ret) { |
| 3458 | if (aconnector->fake_enable) |
| 3459 | aconnector->fake_enable = false0; |
| 3460 | |
| 3461 | amdgpu_dm_update_connector_after_detect(aconnector); |
| 3462 | |
| 3463 | drm_modeset_lock_all(dev); |
| 3464 | dm_restore_drm_connector_state(dev, connector); |
| 3465 | drm_modeset_unlock_all(dev); |
| 3466 | |
| 3467 | drm_kms_helper_connector_hotplug_event(connector); |
| 3468 | } |
| 3469 | } |
| 3470 | } |
| 3471 | #ifdef CONFIG_DRM_AMD_DC_HDCP |
| 3472 | if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) { |
| 3473 | if (adev->dm.hdcp_workqueue) |
| 3474 | hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index); |
| 3475 | } |
| 3476 | #endif |
| 3477 | |
| 3478 | if (dc_link->type != dc_connection_mst_branch) |
| 3479 | drm_dp_cec_irq(&aconnector->dm_dp_aux.aux); |
| 3480 | |
| 3481 | mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock); |
| 3482 | } |
| 3483 | |
| 3484 | static void register_hpd_handlers(struct amdgpu_device *adev) |
| 3485 | { |
| 3486 | struct drm_device *dev = adev_to_drm(adev); |
| 3487 | struct drm_connector *connector; |
| 3488 | struct amdgpu_dm_connector *aconnector; |
| 3489 | const struct dc_link *dc_link; |
| 3490 | struct dc_interrupt_params int_params = {0}; |
| 3491 | |
| 3492 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3493 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3494 | |
| 3495 | list_for_each_entry(connector,for (connector = ({ const __typeof( ((__typeof(*connector) *) 0)->head ) *__mptr = ((&dev->mode_config.connector_list )->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof (__typeof(*connector), head) );}); &connector->head != (&dev->mode_config.connector_list); connector = ({ const __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = ( connector->head.next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof(__typeof(*connector), head) );})) |
| 3496 | &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *) 0)->head ) *__mptr = ((&dev->mode_config.connector_list )->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof (__typeof(*connector), head) );}); &connector->head != (&dev->mode_config.connector_list); connector = ({ const __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = ( connector->head.next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof(__typeof(*connector), head) );})) { |
| 3497 | |
| 3498 | aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 3499 | dc_link = aconnector->dc_link; |
| 3500 | |
| 3501 | if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) { |
| 3502 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
| 3503 | int_params.irq_source = dc_link->irq_source_hpd; |
| 3504 | |
| 3505 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3506 | handle_hpd_irq, |
| 3507 | (void *) aconnector); |
| 3508 | } |
| 3509 | |
| 3510 | if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) { |
| 3511 | |
| 3512 | /* Also register for DP short pulse (hpd_rx). */ |
| 3513 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
| 3514 | int_params.irq_source = dc_link->irq_source_hpd_rx; |
| 3515 | |
| 3516 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3517 | handle_hpd_rx_irq, |
| 3518 | (void *) aconnector); |
| 3519 | } |
| 3520 | |
| 3521 | if (adev->dm.hpd_rx_offload_wq) |
| 3522 | adev->dm.hpd_rx_offload_wq[connector->index].aconnector = |
| 3523 | aconnector; |
| 3524 | } |
| 3525 | } |
| 3526 | |
| 3527 | #if defined(CONFIG_DRM_AMD_DC_SI) |
| 3528 | /* Register IRQ sources and initialize IRQ callbacks */ |
| 3529 | static int dce60_register_irq_handlers(struct amdgpu_device *adev) |
| 3530 | { |
| 3531 | struct dc *dc = adev->dm.dc; |
| 3532 | struct common_irq_params *c_irq_params; |
| 3533 | struct dc_interrupt_params int_params = {0}; |
| 3534 | int r; |
| 3535 | int i; |
| 3536 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY0; |
| 3537 | |
| 3538 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3539 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3540 | |
| 3541 | /* |
| 3542 | * Actions of amdgpu_irq_add_id(): |
| 3543 | * 1. Register a set() function with base driver. |
| 3544 | * Base driver will call set() function to enable/disable an |
| 3545 | * interrupt in DC hardware. |
| 3546 | * 2. Register amdgpu_dm_irq_handler(). |
| 3547 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts |
| 3548 | * coming from DC hardware. |
| 3549 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC |
| 3550 | * for acknowledging and handling. |
| 3551 | */ |
| 3552 | |
| 3553 | /* Use VBLANK interrupt */ |
| 3554 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 3555 | r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); |
| 3556 | if (r) { |
| 3557 | DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n"); |
| 3558 | return r; |
| 3559 | } |
| 3560 | |
| 3561 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3562 | int_params.irq_source = |
| 3563 | dc_interrupt_to_irq_source(dc, i + 1, 0); |
| 3564 | |
| 3565 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
| 3566 | |
| 3567 | c_irq_params->adev = adev; |
| 3568 | c_irq_params->irq_src = int_params.irq_source; |
| 3569 | |
| 3570 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3571 | dm_crtc_high_irq, c_irq_params); |
| 3572 | } |
| 3573 | |
| 3574 | /* Use GRPH_PFLIP interrupt */ |
| 3575 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8; |
| 3576 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP18; i += 2) { |
| 3577 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
| 3578 | if (r) { |
| 3579 | DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n"); |
| 3580 | return r; |
| 3581 | } |
| 3582 | |
| 3583 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3584 | int_params.irq_source = |
| 3585 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3586 | |
| 3587 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; |
| 3588 | |
| 3589 | c_irq_params->adev = adev; |
| 3590 | c_irq_params->irq_src = int_params.irq_source; |
| 3591 | |
| 3592 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3593 | dm_pflip_high_irq, c_irq_params); |
| 3594 | |
| 3595 | } |
| 3596 | |
| 3597 | /* HPD */ |
| 3598 | r = amdgpu_irq_add_id(adev, client_id, |
| 3599 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq); |
| 3600 | if (r) { |
| 3601 | DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n"); |
| 3602 | return r; |
| 3603 | } |
| 3604 | |
| 3605 | register_hpd_handlers(adev); |
| 3606 | |
| 3607 | return 0; |
| 3608 | } |
| 3609 | #endif |
| 3610 | |
| 3611 | /* Register IRQ sources and initialize IRQ callbacks */ |
| 3612 | static int dce110_register_irq_handlers(struct amdgpu_device *adev) |
| 3613 | { |
| 3614 | struct dc *dc = adev->dm.dc; |
| 3615 | struct common_irq_params *c_irq_params; |
| 3616 | struct dc_interrupt_params int_params = {0}; |
| 3617 | int r; |
| 3618 | int i; |
| 3619 | unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY0; |
| 3620 | |
| 3621 | if (adev->family >= AMDGPU_FAMILY_AI141) |
| 3622 | client_id = SOC15_IH_CLIENTID_DCE; |
| 3623 | |
| 3624 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3625 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3626 | |
| 3627 | /* |
| 3628 | * Actions of amdgpu_irq_add_id(): |
| 3629 | * 1. Register a set() function with base driver. |
| 3630 | * Base driver will call set() function to enable/disable an |
| 3631 | * interrupt in DC hardware. |
| 3632 | * 2. Register amdgpu_dm_irq_handler(). |
| 3633 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts |
| 3634 | * coming from DC hardware. |
| 3635 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC |
| 3636 | * for acknowledging and handling. |
| 3637 | */ |
| 3638 | |
| 3639 | /* Use VBLANK interrupt */ |
| 3640 | for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT019; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT024; i++) { |
| 3641 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); |
| 3642 | if (r) { |
| 3643 | DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n"); |
| 3644 | return r; |
| 3645 | } |
| 3646 | |
| 3647 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3648 | int_params.irq_source = |
| 3649 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3650 | |
| 3651 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
| 3652 | |
| 3653 | c_irq_params->adev = adev; |
| 3654 | c_irq_params->irq_src = int_params.irq_source; |
| 3655 | |
| 3656 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3657 | dm_crtc_high_irq, c_irq_params); |
| 3658 | } |
| 3659 | |
| 3660 | /* Use VUPDATE interrupt */ |
| 3661 | for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT7; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT17; i += 2) { |
| 3662 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); |
| 3663 | if (r) { |
| 3664 | DRM_ERROR("Failed to add vupdate irq id!\n")__drm_err("Failed to add vupdate irq id!\n"); |
| 3665 | return r; |
| 3666 | } |
| 3667 | |
| 3668 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3669 | int_params.irq_source = |
| 3670 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3671 | |
| 3672 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; |
| 3673 | |
| 3674 | c_irq_params->adev = adev; |
| 3675 | c_irq_params->irq_src = int_params.irq_source; |
| 3676 | |
| 3677 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3678 | dm_vupdate_high_irq, c_irq_params); |
| 3679 | } |
| 3680 | |
| 3681 | /* Use GRPH_PFLIP interrupt */ |
| 3682 | for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8; |
| 3683 | i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP18; i += 2) { |
| 3684 | r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); |
| 3685 | if (r) { |
| 3686 | DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n"); |
| 3687 | return r; |
| 3688 | } |
| 3689 | |
| 3690 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3691 | int_params.irq_source = |
| 3692 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3693 | |
| 3694 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; |
| 3695 | |
| 3696 | c_irq_params->adev = adev; |
| 3697 | c_irq_params->irq_src = int_params.irq_source; |
| 3698 | |
| 3699 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3700 | dm_pflip_high_irq, c_irq_params); |
| 3701 | |
| 3702 | } |
| 3703 | |
| 3704 | /* HPD */ |
| 3705 | r = amdgpu_irq_add_id(adev, client_id, |
| 3706 | VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq); |
| 3707 | if (r) { |
| 3708 | DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n"); |
| 3709 | return r; |
| 3710 | } |
| 3711 | |
| 3712 | register_hpd_handlers(adev); |
| 3713 | |
| 3714 | return 0; |
| 3715 | } |
| 3716 | |
| 3717 | /* Register IRQ sources and initialize IRQ callbacks */ |
| 3718 | static int dcn10_register_irq_handlers(struct amdgpu_device *adev) |
| 3719 | { |
| 3720 | struct dc *dc = adev->dm.dc; |
| 3721 | struct common_irq_params *c_irq_params; |
| 3722 | struct dc_interrupt_params int_params = {0}; |
| 3723 | int r; |
| 3724 | int i; |
| 3725 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 3726 | static const unsigned int vrtl_int_srcid[] = { |
| 3727 | DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL0x1E, |
| 3728 | DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL0x1F, |
| 3729 | DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL0x20, |
| 3730 | DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL0x21, |
| 3731 | DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL0x22, |
| 3732 | DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL0x38 |
| 3733 | }; |
| 3734 | #endif |
| 3735 | |
| 3736 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3737 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3738 | |
| 3739 | /* |
| 3740 | * Actions of amdgpu_irq_add_id(): |
| 3741 | * 1. Register a set() function with base driver. |
| 3742 | * Base driver will call set() function to enable/disable an |
| 3743 | * interrupt in DC hardware. |
| 3744 | * 2. Register amdgpu_dm_irq_handler(). |
| 3745 | * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts |
| 3746 | * coming from DC hardware. |
| 3747 | * amdgpu_dm_irq_handler() will re-direct the interrupt to DC |
| 3748 | * for acknowledging and handling. |
| 3749 | */ |
| 3750 | |
| 3751 | /* Use VSTARTUP interrupt */ |
| 3752 | for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP0x3C; |
| 3753 | i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP0x3C + adev->mode_info.num_crtc - 1; |
| 3754 | i++) { |
| 3755 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq); |
| 3756 | |
| 3757 | if (r) { |
| 3758 | DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n"); |
| 3759 | return r; |
| 3760 | } |
| 3761 | |
| 3762 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3763 | int_params.irq_source = |
| 3764 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3765 | |
| 3766 | c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; |
| 3767 | |
| 3768 | c_irq_params->adev = adev; |
| 3769 | c_irq_params->irq_src = int_params.irq_source; |
| 3770 | |
| 3771 | amdgpu_dm_irq_register_interrupt( |
| 3772 | adev, &int_params, dm_crtc_high_irq, c_irq_params); |
| 3773 | } |
| 3774 | |
| 3775 | /* Use otg vertical line interrupt */ |
| 3776 | #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) |
| 3777 | for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) { |
| 3778 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, |
| 3779 | vrtl_int_srcid[i], &adev->vline0_irq); |
| 3780 | |
| 3781 | if (r) { |
| 3782 | DRM_ERROR("Failed to add vline0 irq id!\n")__drm_err("Failed to add vline0 irq id!\n"); |
| 3783 | return r; |
| 3784 | } |
| 3785 | |
| 3786 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3787 | int_params.irq_source = |
| 3788 | dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0); |
| 3789 | |
| 3790 | if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) { |
| 3791 | DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i])__drm_err("Failed to register vline0 irq %d!\n", vrtl_int_srcid [i]); |
| 3792 | break; |
| 3793 | } |
| 3794 | |
| 3795 | c_irq_params = &adev->dm.vline0_params[int_params.irq_source |
| 3796 | - DC_IRQ_SOURCE_DC1_VLINE0]; |
| 3797 | |
| 3798 | c_irq_params->adev = adev; |
| 3799 | c_irq_params->irq_src = int_params.irq_source; |
| 3800 | |
| 3801 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3802 | dm_dcn_vertical_interrupt0_high_irq, c_irq_params); |
| 3803 | } |
| 3804 | #endif |
| 3805 | |
| 3806 | /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to |
| 3807 | * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx |
| 3808 | * to trigger at end of each vblank, regardless of state of the lock, |
| 3809 | * matching DCE behaviour. |
| 3810 | */ |
| 3811 | for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT0x57; |
| 3812 | i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT0x57 + adev->mode_info.num_crtc - 1; |
| 3813 | i++) { |
| 3814 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq); |
| 3815 | |
| 3816 | if (r) { |
| 3817 | DRM_ERROR("Failed to add vupdate irq id!\n")__drm_err("Failed to add vupdate irq id!\n"); |
| 3818 | return r; |
| 3819 | } |
| 3820 | |
| 3821 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3822 | int_params.irq_source = |
| 3823 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3824 | |
| 3825 | c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; |
| 3826 | |
| 3827 | c_irq_params->adev = adev; |
| 3828 | c_irq_params->irq_src = int_params.irq_source; |
| 3829 | |
| 3830 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3831 | dm_vupdate_high_irq, c_irq_params); |
| 3832 | } |
| 3833 | |
| 3834 | /* Use GRPH_PFLIP interrupt */ |
| 3835 | for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT0x4F; |
| 3836 | i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT0x4F + dc->caps.max_otg_num - 1; |
| 3837 | i++) { |
| 3838 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq); |
| 3839 | if (r) { |
| 3840 | DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n"); |
| 3841 | return r; |
| 3842 | } |
| 3843 | |
| 3844 | int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; |
| 3845 | int_params.irq_source = |
| 3846 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3847 | |
| 3848 | c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; |
| 3849 | |
| 3850 | c_irq_params->adev = adev; |
| 3851 | c_irq_params->irq_src = int_params.irq_source; |
| 3852 | |
| 3853 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3854 | dm_pflip_high_irq, c_irq_params); |
| 3855 | |
| 3856 | } |
| 3857 | |
| 3858 | /* HPD */ |
| 3859 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT9, |
| 3860 | &adev->hpd_irq); |
| 3861 | if (r) { |
| 3862 | DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n"); |
| 3863 | return r; |
| 3864 | } |
| 3865 | |
| 3866 | register_hpd_handlers(adev); |
| 3867 | |
| 3868 | return 0; |
| 3869 | } |
| 3870 | /* Register Outbox IRQ sources and initialize IRQ callbacks */ |
| 3871 | static int register_outbox_irq_handlers(struct amdgpu_device *adev) |
| 3872 | { |
| 3873 | struct dc *dc = adev->dm.dc; |
| 3874 | struct common_irq_params *c_irq_params; |
| 3875 | struct dc_interrupt_params int_params = {0}; |
| 3876 | int r, i; |
| 3877 | |
| 3878 | int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3879 | int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; |
| 3880 | |
| 3881 | r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT0x68, |
| 3882 | &adev->dmub_outbox_irq); |
| 3883 | if (r) { |
| 3884 | DRM_ERROR("Failed to add outbox irq id!\n")__drm_err("Failed to add outbox irq id!\n"); |
| 3885 | return r; |
| 3886 | } |
| 3887 | |
| 3888 | if (dc->ctx->dmub_srv) { |
| 3889 | i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT0x68; |
| 3890 | int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; |
| 3891 | int_params.irq_source = |
| 3892 | dc_interrupt_to_irq_source(dc, i, 0); |
| 3893 | |
| 3894 | c_irq_params = &adev->dm.dmub_outbox_params[0]; |
| 3895 | |
| 3896 | c_irq_params->adev = adev; |
| 3897 | c_irq_params->irq_src = int_params.irq_source; |
| 3898 | |
| 3899 | amdgpu_dm_irq_register_interrupt(adev, &int_params, |
| 3900 | dm_dmub_outbox1_low_irq, c_irq_params); |
| 3901 | } |
| 3902 | |
| 3903 | return 0; |
| 3904 | } |
| 3905 | |
| 3906 | /* |
| 3907 | * Acquires the lock for the atomic state object and returns |
| 3908 | * the new atomic state. |
| 3909 | * |
| 3910 | * This should only be called during atomic check. |
| 3911 | */ |
| 3912 | int dm_atomic_get_state(struct drm_atomic_state *state, |
| 3913 | struct dm_atomic_state **dm_state) |
| 3914 | { |
| 3915 | struct drm_device *dev = state->dev; |
| 3916 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 3917 | struct amdgpu_display_manager *dm = &adev->dm; |
| 3918 | struct drm_private_state *priv_state; |
| 3919 | |
| 3920 | if (*dm_state) |
| 3921 | return 0; |
| 3922 | |
| 3923 | priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj); |
| 3924 | if (IS_ERR(priv_state)) |
| 3925 | return PTR_ERR(priv_state); |
| 3926 | |
| 3927 | *dm_state = to_dm_atomic_state(priv_state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) * __mptr = (priv_state); (struct dm_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct dm_atomic_state, base) );}); |
| 3928 | |
| 3929 | return 0; |
| 3930 | } |
| 3931 | |
| 3932 | static struct dm_atomic_state * |
| 3933 | dm_atomic_get_new_state(struct drm_atomic_state *state) |
| 3934 | { |
| 3935 | struct drm_device *dev = state->dev; |
| 3936 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 3937 | struct amdgpu_display_manager *dm = &adev->dm; |
| 3938 | struct drm_private_obj *obj; |
| 3939 | struct drm_private_state *new_obj_state; |
| 3940 | int i; |
| 3941 | |
| 3942 | for_each_new_private_obj_in_state(state, obj, new_obj_state, i)for ((i) = 0; (i) < (state)->num_private_objs && ((obj) = (state)->private_objs[i].ptr, (void)(obj) , (new_obj_state ) = (state)->private_objs[i].new_state, 1); (i)++) { |
| 3943 | if (obj->funcs == dm->atomic_obj.funcs) |
| 3944 | return to_dm_atomic_state(new_obj_state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) * __mptr = (new_obj_state); (struct dm_atomic_state *)( (char * )__mptr - __builtin_offsetof(struct dm_atomic_state, base) ); }); |
| 3945 | } |
| 3946 | |
| 3947 | return NULL((void *)0); |
| 3948 | } |
| 3949 | |
| 3950 | static struct drm_private_state * |
| 3951 | dm_atomic_duplicate_state(struct drm_private_obj *obj) |
| 3952 | { |
| 3953 | struct dm_atomic_state *old_state, *new_state; |
| 3954 | |
| 3955 | new_state = kzalloc(sizeof(*new_state), GFP_KERNEL(0x0001 | 0x0004)); |
| 3956 | if (!new_state) |
| 3957 | return NULL((void *)0); |
| 3958 | |
| 3959 | __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base); |
| 3960 | |
| 3961 | old_state = to_dm_atomic_state(obj->state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) * __mptr = (obj->state); (struct dm_atomic_state *)( (char * )__mptr - __builtin_offsetof(struct dm_atomic_state, base) ); }); |
| 3962 | |
| 3963 | if (old_state && old_state->context) |
| 3964 | new_state->context = dc_copy_state(old_state->context); |
| 3965 | |
| 3966 | if (!new_state->context) { |
| 3967 | kfree(new_state); |
| 3968 | return NULL((void *)0); |
| 3969 | } |
| 3970 | |
| 3971 | return &new_state->base; |
| 3972 | } |
| 3973 | |
| 3974 | static void dm_atomic_destroy_state(struct drm_private_obj *obj, |
| 3975 | struct drm_private_state *state) |
| 3976 | { |
| 3977 | struct dm_atomic_state *dm_state = to_dm_atomic_state(state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) * __mptr = (state); (struct dm_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct dm_atomic_state, base) );}); |
| 3978 | |
| 3979 | if (dm_state && dm_state->context) |
| 3980 | dc_release_state(dm_state->context); |
| 3981 | |
| 3982 | kfree(dm_state); |
| 3983 | } |
| 3984 | |
| 3985 | static struct drm_private_state_funcs dm_atomic_state_funcs = { |
| 3986 | .atomic_duplicate_state = dm_atomic_duplicate_state, |
| 3987 | .atomic_destroy_state = dm_atomic_destroy_state, |
| 3988 | }; |
| 3989 | |
| 3990 | static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) |
| 3991 | { |
| 3992 | struct dm_atomic_state *state; |
| 3993 | int r; |
| 3994 | |
| 3995 | adev->mode_info.mode_config_initialized = true1; |
| 3996 | |
| 3997 | adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; |
| 3998 | adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; |
| 3999 | |
| 4000 | adev_to_drm(adev)->mode_config.max_width = 16384; |
| 4001 | adev_to_drm(adev)->mode_config.max_height = 16384; |
| 4002 | |
| 4003 | adev_to_drm(adev)->mode_config.preferred_depth = 24; |
| 4004 | if (adev->asic_type == CHIP_HAWAII) |
| 4005 | /* disable prefer shadow for now due to hibernation issues */ |
| 4006 | adev_to_drm(adev)->mode_config.prefer_shadow = 0; |
| 4007 | else |
| 4008 | adev_to_drm(adev)->mode_config.prefer_shadow = 1; |
| 4009 | /* indicates support for immediate flip */ |
| 4010 | adev_to_drm(adev)->mode_config.async_page_flip = true1; |
| 4011 | |
| 4012 | adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base; |
| 4013 | |
| 4014 | state = kzalloc(sizeof(*state), GFP_KERNEL(0x0001 | 0x0004)); |
| 4015 | if (!state) |
| 4016 | return -ENOMEM12; |
| 4017 | |
| 4018 | state->context = dc_create_state(adev->dm.dc); |
| 4019 | if (!state->context) { |
| 4020 | kfree(state); |
| 4021 | return -ENOMEM12; |
| 4022 | } |
| 4023 | |
| 4024 | dc_resource_state_copy_construct_current(adev->dm.dc, state->context); |
| 4025 | |
| 4026 | drm_atomic_private_obj_init(adev_to_drm(adev), |
| 4027 | &adev->dm.atomic_obj, |
| 4028 | &state->base, |
| 4029 | &dm_atomic_state_funcs); |
| 4030 | |
| 4031 | r = amdgpu_display_modeset_create_props(adev); |
| 4032 | if (r) { |
| 4033 | dc_release_state(state->context); |
| 4034 | kfree(state); |
| 4035 | return r; |
| 4036 | } |
| 4037 | |
| 4038 | r = amdgpu_dm_audio_init(adev); |
| 4039 | if (r) { |
| 4040 | dc_release_state(state->context); |
| 4041 | kfree(state); |
| 4042 | return r; |
| 4043 | } |
| 4044 | |
| 4045 | return 0; |
| 4046 | } |
| 4047 | |
| 4048 | #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12 12 |
| 4049 | #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255 255 |
| 4050 | #define AUX_BL_DEFAULT_TRANSITION_TIME_MS50 50 |
| 4051 | |
| 4052 | static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, |
| 4053 | int bl_idx) |
| 4054 | { |
| 4055 | #if defined(CONFIG_ACPI1) |
| 4056 | struct amdgpu_dm_backlight_caps caps; |
| 4057 | |
| 4058 | memset(&caps, 0, sizeof(caps))__builtin_memset((&caps), (0), (sizeof(caps))); |
| 4059 | |
| 4060 | if (dm->backlight_caps[bl_idx].caps_valid) |
| 4061 | return; |
| 4062 | |
| 4063 | amdgpu_acpi_get_backlight_caps(&caps); |
| 4064 | if (caps.caps_valid) { |
| 4065 | dm->backlight_caps[bl_idx].caps_valid = true1; |
| 4066 | if (caps.aux_support) |
| 4067 | return; |
| 4068 | dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; |
| 4069 | dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; |
| 4070 | } else { |
| 4071 | dm->backlight_caps[bl_idx].min_input_signal = |
| 4072 | AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12; |
| 4073 | dm->backlight_caps[bl_idx].max_input_signal = |
| 4074 | AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255; |
| 4075 | } |
| 4076 | #else |
| 4077 | if (dm->backlight_caps[bl_idx].aux_support) |
| 4078 | return; |
| 4079 | |
| 4080 | dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12; |
| 4081 | dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255; |
| 4082 | #endif |
| 4083 | } |
| 4084 | |
| 4085 | static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, |
| 4086 | unsigned int *min, unsigned int *max) |
| 4087 | { |
| 4088 | if (!caps) |
| 4089 | return 0; |
| 4090 | |
| 4091 | if (caps->aux_support) { |
| 4092 | // Firmware limits are in nits, DC API wants millinits. |
| 4093 | *max = 1000 * caps->aux_max_input_signal; |
| 4094 | *min = 1000 * caps->aux_min_input_signal; |
| 4095 | } else { |
| 4096 | // Firmware limits are 8-bit, PWM control is 16-bit. |
| 4097 | *max = 0x101 * caps->max_input_signal; |
| 4098 | *min = 0x101 * caps->min_input_signal; |
| 4099 | } |
| 4100 | return 1; |
| 4101 | } |
| 4102 | |
| 4103 | static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps, |
| 4104 | uint32_t brightness) |
| 4105 | { |
| 4106 | unsigned int min, max; |
| 4107 | |
| 4108 | if (!get_brightness_range(caps, &min, &max)) |
| 4109 | return brightness; |
| 4110 | |
| 4111 | // Rescale 0..255 to min..max |
| 4112 | return min + DIV_ROUND_CLOSEST((max - min) * brightness,((((max - min) * brightness) + ((0xFF) / 2)) / (0xFF)) |
| 4113 | AMDGPU_MAX_BL_LEVEL)((((max - min) * brightness) + ((0xFF) / 2)) / (0xFF)); |
| 4114 | } |
| 4115 | |
| 4116 | static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps, |
| 4117 | uint32_t brightness) |
| 4118 | { |
| 4119 | unsigned int min, max; |
| 4120 | |
| 4121 | if (!get_brightness_range(caps, &min, &max)) |
| 4122 | return brightness; |
| 4123 | |
| 4124 | if (brightness < min) |
| 4125 | return 0; |
| 4126 | // Rescale min..max to 0..255 |
| 4127 | return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),(((0xFF * (brightness - min)) + ((max - min) / 2)) / (max - min )) |
| 4128 | max - min)(((0xFF * (brightness - min)) + ((max - min) / 2)) / (max - min )); |
| 4129 | } |
| 4130 | |
| 4131 | static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, |
| 4132 | int bl_idx, |
| 4133 | u32 user_brightness) |
| 4134 | { |
| 4135 | struct amdgpu_dm_backlight_caps caps; |
| 4136 | struct dc_link *link; |
| 4137 | u32 brightness; |
| 4138 | bool_Bool rc; |
| 4139 | |
| 4140 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
| 4141 | caps = dm->backlight_caps[bl_idx]; |
| 4142 | |
| 4143 | dm->brightness[bl_idx] = user_brightness; |
| 4144 | /* update scratch register */ |
| 4145 | if (bl_idx == 0) |
| 4146 | amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]); |
| 4147 | brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]); |
| 4148 | link = (struct dc_link *)dm->backlight_link[bl_idx]; |
| 4149 | |
| 4150 | /* Change brightness based on AUX property */ |
| 4151 | if (caps.aux_support) { |
| 4152 | rc = dc_link_set_backlight_level_nits(link, true1, brightness, |
| 4153 | AUX_BL_DEFAULT_TRANSITION_TIME_MS50); |
| 4154 | if (!rc) |
| 4155 | DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx)___drm_dbg(((void *)0), DRM_UT_CORE, "DM: Failed to update backlight via AUX on eDP[%d]\n" , bl_idx); |
| 4156 | } else { |
| 4157 | rc = dc_link_set_backlight_level(link, brightness, 0); |
| 4158 | if (!rc) |
| 4159 | DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx)___drm_dbg(((void *)0), DRM_UT_CORE, "DM: Failed to update backlight on eDP[%d]\n" , bl_idx); |
| 4160 | } |
| 4161 | |
| 4162 | if (rc) |
| 4163 | dm->actual_brightness[bl_idx] = user_brightness; |
| 4164 | } |
| 4165 | |
| 4166 | static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) |
| 4167 | { |
| 4168 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
| 4169 | int i; |
| 4170 | |
| 4171 | for (i = 0; i < dm->num_of_edps; i++) { |
| 4172 | if (bd == dm->backlight_dev[i]) |
| 4173 | break; |
| 4174 | } |
| 4175 | if (i >= AMDGPU_DM_MAX_NUM_EDP2) |
| 4176 | i = 0; |
| 4177 | amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness); |
| 4178 | |
| 4179 | return 0; |
| 4180 | } |
| 4181 | |
| 4182 | static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, |
| 4183 | int bl_idx) |
| 4184 | { |
| 4185 | struct amdgpu_dm_backlight_caps caps; |
| 4186 | struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx]; |
| 4187 | |
| 4188 | amdgpu_dm_update_backlight_caps(dm, bl_idx); |
| 4189 | caps = dm->backlight_caps[bl_idx]; |
| 4190 | |
| 4191 | if (caps.aux_support) { |
| 4192 | u32 avg, peak; |
| 4193 | bool_Bool rc; |
| 4194 | |
| 4195 | rc = dc_link_get_backlight_level_nits(link, &avg, &peak); |
| 4196 | if (!rc) |
| 4197 | return dm->brightness[bl_idx]; |
| 4198 | return convert_brightness_to_user(&caps, avg); |
| 4199 | } else { |
| 4200 | int ret = dc_link_get_backlight_level(link); |
| 4201 | |
| 4202 | if (ret == DC_ERROR_UNEXPECTED) |
| 4203 | return dm->brightness[bl_idx]; |
| 4204 | return convert_brightness_to_user(&caps, ret); |
| 4205 | } |
| 4206 | } |
| 4207 | |
| 4208 | static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) |
| 4209 | { |
| 4210 | struct amdgpu_display_manager *dm = bl_get_data(bd); |
| 4211 | int i; |
| 4212 | |
| 4213 | for (i = 0; i < dm->num_of_edps; i++) { |
| 4214 | if (bd == dm->backlight_dev[i]) |
| 4215 | break; |
| 4216 | } |
| 4217 | if (i >= AMDGPU_DM_MAX_NUM_EDP2) |
| 4218 | i = 0; |
| 4219 | return amdgpu_dm_backlight_get_level(dm, i); |
| 4220 | } |
| 4221 | |
| 4222 | static const struct backlight_ops amdgpu_dm_backlight_ops = { |
| 4223 | .options = BL_CORE_SUSPENDRESUME0x00000001, |
| 4224 | .get_brightness = amdgpu_dm_backlight_get_brightness, |
| 4225 | .update_status = amdgpu_dm_backlight_update_status, |
| 4226 | }; |
| 4227 | |
| 4228 | static void |
| 4229 | amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) |
| 4230 | { |
| 4231 | char bl_name[16]; |
| 4232 | struct backlight_properties props = { 0 }; |
| 4233 | |
| 4234 | amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps); |
| 4235 | dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL0xFF; |
| 4236 | |
| 4237 | if (!acpi_video_backlight_use_native()) { |
| 4238 | drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n")do { } while(0); |
| 4239 | /* Try registering an ACPI video backlight device instead. */ |
| 4240 | acpi_video_register_backlight(); |
| 4241 | return; |
| 4242 | } |
| 4243 | |
| 4244 | props.max_brightness = AMDGPU_MAX_BL_LEVEL0xFF; |
| 4245 | props.brightness = AMDGPU_MAX_BL_LEVEL0xFF; |
| 4246 | props.type = BACKLIGHT_RAW0; |
| 4247 | |
| 4248 | snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", |
| 4249 | adev_to_drm(dm->adev)->primary->index + dm->num_of_edps); |
| 4250 | |
| 4251 | dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name, |
| 4252 | adev_to_drm(dm->adev)->dev, |
| 4253 | dm, |
| 4254 | &amdgpu_dm_backlight_ops, |
| 4255 | &props); |
| 4256 | |
| 4257 | if (IS_ERR(dm->backlight_dev[dm->num_of_edps])) |
| 4258 | DRM_ERROR("DM: Backlight registration failed!\n")__drm_err("DM: Backlight registration failed!\n"); |
| 4259 | else |
| 4260 | DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DM: Registered Backlight device: %s\n" , bl_name); |
| 4261 | } |
| 4262 | |
| 4263 | static int initialize_plane(struct amdgpu_display_manager *dm, |
| 4264 | struct amdgpu_mode_info *mode_info, int plane_id, |
| 4265 | enum drm_plane_type plane_type, |
| 4266 | const struct dc_plane_cap *plane_cap) |
| 4267 | { |
| 4268 | struct drm_plane *plane; |
| 4269 | unsigned long possible_crtcs; |
| 4270 | int ret = 0; |
| 4271 | |
| 4272 | plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL(0x0001 | 0x0004)); |
| 4273 | if (!plane) { |
| 4274 | DRM_ERROR("KMS: Failed to allocate plane\n")__drm_err("KMS: Failed to allocate plane\n"); |
| 4275 | return -ENOMEM12; |
| 4276 | } |
| 4277 | plane->type = plane_type; |
| 4278 | |
| 4279 | /* |
| 4280 | * HACK: IGT tests expect that the primary plane for a CRTC |
| 4281 | * can only have one possible CRTC. Only expose support for |
| 4282 | * any CRTC if they're not going to be used as a primary plane |
| 4283 | * for a CRTC - like overlay or underlay planes. |
| 4284 | */ |
| 4285 | possible_crtcs = 1 << plane_id; |
| 4286 | if (plane_id >= dm->dc->caps.max_streams) |
| 4287 | possible_crtcs = 0xff; |
| 4288 | |
| 4289 | ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap); |
| 4290 | |
| 4291 | if (ret) { |
| 4292 | DRM_ERROR("KMS: Failed to initialize plane\n")__drm_err("KMS: Failed to initialize plane\n"); |
| 4293 | kfree(plane); |
| 4294 | return ret; |
| 4295 | } |
| 4296 | |
| 4297 | if (mode_info) |
| 4298 | mode_info->planes[plane_id] = plane; |
| 4299 | |
| 4300 | return ret; |
| 4301 | } |
| 4302 | |
| 4303 | |
| 4304 | static void register_backlight_device(struct amdgpu_display_manager *dm, |
| 4305 | struct dc_link *link) |
| 4306 | { |
| 4307 | if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) && |
| 4308 | link->type != dc_connection_none) { |
| 4309 | /* |
| 4310 | * Event if registration failed, we should continue with |
| 4311 | * DM initialization because not having a backlight control |
| 4312 | * is better then a black screen. |
| 4313 | */ |
| 4314 | if (!dm->backlight_dev[dm->num_of_edps]) |
| 4315 | amdgpu_dm_register_backlight_device(dm); |
| 4316 | |
| 4317 | if (dm->backlight_dev[dm->num_of_edps]) { |
| 4318 | dm->backlight_link[dm->num_of_edps] = link; |
| 4319 | dm->num_of_edps++; |
| 4320 | } |
| 4321 | } |
| 4322 | } |
| 4323 | |
| 4324 | static void amdgpu_set_panel_orientation(struct drm_connector *connector); |
| 4325 | |
| 4326 | /* |
| 4327 | * In this architecture, the association |
| 4328 | * connector -> encoder -> crtc |
| 4329 | * id not really requried. The crtc and connector will hold the |
| 4330 | * display_index as an abstraction to use with DAL component |
| 4331 | * |
| 4332 | * Returns 0 on success |
| 4333 | */ |
| 4334 | static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) |
| 4335 | { |
| 4336 | struct amdgpu_display_manager *dm = &adev->dm; |
| 4337 | s32 i; |
| 4338 | struct amdgpu_dm_connector *aconnector = NULL((void *)0); |
| 4339 | struct amdgpu_encoder *aencoder = NULL((void *)0); |
| 4340 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
| 4341 | u32 link_cnt; |
| 4342 | s32 primary_planes; |
| 4343 | enum dc_connection_type new_connection_type = dc_connection_none; |
| 4344 | const struct dc_plane_cap *plane; |
| 4345 | bool_Bool psr_feature_enabled = false0; |
| 4346 | |
| 4347 | dm->display_indexes_num = dm->dc->caps.max_streams; |
| 4348 | /* Update the actual used number of crtc */ |
| 4349 | adev->mode_info.num_crtc = adev->dm.display_indexes_num; |
| 4350 | |
| 4351 | link_cnt = dm->dc->caps.max_links; |
| 4352 | if (amdgpu_dm_mode_config_init(dm->adev)) { |
| 4353 | DRM_ERROR("DM: Failed to initialize mode config\n")__drm_err("DM: Failed to initialize mode config\n"); |
| 4354 | return -EINVAL22; |
| 4355 | } |
| 4356 | |
| 4357 | /* There is one primary plane per CRTC */ |
| 4358 | primary_planes = dm->dc->caps.max_streams; |
| 4359 | ASSERT(primary_planes <= AMDGPU_MAX_PLANES)do { if (({ static int __warned; int __ret = !!(!(primary_planes <= 6)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(primary_planes <= 6)", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 4359); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
| 4360 | |
| 4361 | /* |
| 4362 | * Initialize primary planes, implicit planes for legacy IOCTLS. |
| 4363 | * Order is reversed to match iteration order in atomic check. |
| 4364 | */ |
| 4365 | for (i = (primary_planes - 1); i >= 0; i--) { |
| 4366 | plane = &dm->dc->caps.planes[i]; |
| 4367 | |
| 4368 | if (initialize_plane(dm, mode_info, i, |
| 4369 | DRM_PLANE_TYPE_PRIMARY, plane)) { |
| 4370 | DRM_ERROR("KMS: Failed to initialize primary plane\n")__drm_err("KMS: Failed to initialize primary plane\n"); |
| 4371 | goto fail; |
| 4372 | } |
| 4373 | } |
| 4374 | |
| 4375 | /* |
| 4376 | * Initialize overlay planes, index starting after primary planes. |
| 4377 | * These planes have a higher DRM index than the primary planes since |
| 4378 | * they should be considered as having a higher z-order. |
| 4379 | * Order is reversed to match iteration order in atomic check. |
| 4380 | * |
| 4381 | * Only support DCN for now, and only expose one so we don't encourage |
| 4382 | * userspace to use up all the pipes. |
| 4383 | */ |
| 4384 | for (i = 0; i < dm->dc->caps.max_planes; ++i) { |
| 4385 | struct dc_plane_cap *plane = &dm->dc->caps.planes[i]; |
| 4386 | |
| 4387 | /* Do not create overlay if MPO disabled */ |
| 4388 | if (amdgpu_dc_debug_mask & DC_DISABLE_MPO) |
| 4389 | break; |
| 4390 | |
| 4391 | if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL) |
| 4392 | continue; |
| 4393 | |
| 4394 | if (!plane->blends_with_above || !plane->blends_with_below) |
| 4395 | continue; |
| 4396 | |
| 4397 | if (!plane->pixel_format_support.argb8888) |
| 4398 | continue; |
| 4399 | |
| 4400 | if (initialize_plane(dm, NULL((void *)0), primary_planes + i, |
| 4401 | DRM_PLANE_TYPE_OVERLAY, plane)) { |
| 4402 | DRM_ERROR("KMS: Failed to initialize overlay plane\n")__drm_err("KMS: Failed to initialize overlay plane\n"); |
| 4403 | goto fail; |
| 4404 | } |
| 4405 | |
| 4406 | /* Only create one overlay plane. */ |
| 4407 | break; |
| 4408 | } |
| 4409 | |
| 4410 | for (i = 0; i < dm->dc->caps.max_streams; i++) |
| 4411 | if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) { |
| 4412 | DRM_ERROR("KMS: Failed to initialize crtc\n")__drm_err("KMS: Failed to initialize crtc\n"); |
| 4413 | goto fail; |
| 4414 | } |
| 4415 | |
| 4416 | /* Use Outbox interrupt */ |
| 4417 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 4418 | case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)): |
| 4419 | case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)): |
| 4420 | case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)): |
| 4421 | case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)): |
| 4422 | case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)): |
| 4423 | case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)): |
| 4424 | case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)): |
| 4425 | case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)): |
| 4426 | case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)): |
| 4427 | if (register_outbox_irq_handlers(dm->adev)) { |
| 4428 | DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n"); |
| 4429 | goto fail; |
| 4430 | } |
| 4431 | break; |
| 4432 | default: |
| 4433 | DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Unsupported DCN IP version for outbox: 0x%X\n" , adev->ip_versions[DCE_HWIP][0]) |
| 4434 | adev->ip_versions[DCE_HWIP][0])___drm_dbg(((void *)0), DRM_UT_KMS, "Unsupported DCN IP version for outbox: 0x%X\n" , adev->ip_versions[DCE_HWIP][0]); |
| 4435 | } |
| 4436 | |
| 4437 | /* Determine whether to enable PSR support by default. */ |
| 4438 | if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) { |
| 4439 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 4440 | case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)): |
| 4441 | case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)): |
| 4442 | case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)): |
| 4443 | case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)): |
| 4444 | case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)): |
| 4445 | case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)): |
| 4446 | case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)): |
| 4447 | psr_feature_enabled = true1; |
| 4448 | break; |
| 4449 | default: |
| 4450 | psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK; |
| 4451 | break; |
| 4452 | } |
| 4453 | } |
| 4454 | |
| 4455 | /* loops over all connectors on the board */ |
| 4456 | for (i = 0; i < link_cnt; i++) { |
| 4457 | struct dc_link *link = NULL((void *)0); |
| 4458 | |
| 4459 | if (i > AMDGPU_DM_MAX_DISPLAY_INDEX31) { |
| 4460 | DRM_ERROR(__drm_err("KMS: Cannot support more than %d display indexes\n" , 31) |
| 4461 | "KMS: Cannot support more than %d display indexes\n",__drm_err("KMS: Cannot support more than %d display indexes\n" , 31) |
| 4462 | AMDGPU_DM_MAX_DISPLAY_INDEX)__drm_err("KMS: Cannot support more than %d display indexes\n" , 31); |
| 4463 | continue; |
| 4464 | } |
| 4465 | |
| 4466 | aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL(0x0001 | 0x0004)); |
| 4467 | if (!aconnector) |
| 4468 | goto fail; |
| 4469 | |
| 4470 | aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL(0x0001 | 0x0004)); |
| 4471 | if (!aencoder) |
| 4472 | goto fail; |
| 4473 | |
| 4474 | if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { |
| 4475 | DRM_ERROR("KMS: Failed to initialize encoder\n")__drm_err("KMS: Failed to initialize encoder\n"); |
| 4476 | goto fail; |
| 4477 | } |
| 4478 | |
| 4479 | if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { |
| 4480 | DRM_ERROR("KMS: Failed to initialize connector\n")__drm_err("KMS: Failed to initialize connector\n"); |
| 4481 | goto fail; |
| 4482 | } |
| 4483 | |
| 4484 | link = dc_get_link_at_index(dm->dc, i); |
| 4485 | |
| 4486 | if (!dc_link_detect_sink(link, &new_connection_type)) |
| 4487 | DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n"); |
| 4488 | |
| 4489 | if (aconnector->base.force && new_connection_type == dc_connection_none) { |
| 4490 | emulated_link_detect(link); |
| 4491 | amdgpu_dm_update_connector_after_detect(aconnector); |
| 4492 | } else { |
| 4493 | bool_Bool ret = false0; |
| 4494 | |
| 4495 | mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock); |
| 4496 | ret = dc_link_detect(link, DETECT_REASON_BOOT); |
| 4497 | mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock); |
| 4498 | |
| 4499 | if (ret) { |
| 4500 | amdgpu_dm_update_connector_after_detect(aconnector); |
| 4501 | register_backlight_device(dm, link); |
| 4502 | |
| 4503 | if (dm->num_of_edps) |
| 4504 | update_connector_ext_caps(aconnector); |
| 4505 | |
| 4506 | if (psr_feature_enabled) |
| 4507 | amdgpu_dm_set_psr_caps(link); |
| 4508 | |
| 4509 | /* TODO: Fix vblank control helpers to delay PSR entry to allow this when |
| 4510 | * PSR is also supported. |
| 4511 | */ |
| 4512 | if (link->psr_settings.psr_feature_enabled) |
| 4513 | adev_to_drm(adev)->vblank_disable_immediate = false0; |
| 4514 | } |
| 4515 | } |
| 4516 | amdgpu_set_panel_orientation(&aconnector->base); |
| 4517 | } |
| 4518 | |
| 4519 | /* If we didn't find a panel, notify the acpi video detection */ |
| 4520 | if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0) |
| 4521 | acpi_video_report_nolcd(); |
| 4522 | |
| 4523 | /* Software is initialized. Now we can register interrupt handlers. */ |
| 4524 | switch (adev->asic_type) { |
| 4525 | #if defined(CONFIG_DRM_AMD_DC_SI) |
| 4526 | case CHIP_TAHITI: |
| 4527 | case CHIP_PITCAIRN: |
| 4528 | case CHIP_VERDE: |
| 4529 | case CHIP_OLAND: |
| 4530 | if (dce60_register_irq_handlers(dm->adev)) { |
| 4531 | DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n"); |
| 4532 | goto fail; |
| 4533 | } |
| 4534 | break; |
| 4535 | #endif |
| 4536 | case CHIP_BONAIRE: |
| 4537 | case CHIP_HAWAII: |
| 4538 | case CHIP_KAVERI: |
| 4539 | case CHIP_KABINI: |
| 4540 | case CHIP_MULLINS: |
| 4541 | case CHIP_TONGA: |
| 4542 | case CHIP_FIJI: |
| 4543 | case CHIP_CARRIZO: |
| 4544 | case CHIP_STONEY: |
| 4545 | case CHIP_POLARIS11: |
| 4546 | case CHIP_POLARIS10: |
| 4547 | case CHIP_POLARIS12: |
| 4548 | case CHIP_VEGAM: |
| 4549 | case CHIP_VEGA10: |
| 4550 | case CHIP_VEGA12: |
| 4551 | case CHIP_VEGA20: |
| 4552 | if (dce110_register_irq_handlers(dm->adev)) { |
| 4553 | DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n"); |
| 4554 | goto fail; |
| 4555 | } |
| 4556 | break; |
| 4557 | default: |
| 4558 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 4559 | case IP_VERSION(1, 0, 0)(((1) << 16) | ((0) << 8) | (0)): |
| 4560 | case IP_VERSION(1, 0, 1)(((1) << 16) | ((0) << 8) | (1)): |
| 4561 | case IP_VERSION(2, 0, 2)(((2) << 16) | ((0) << 8) | (2)): |
| 4562 | case IP_VERSION(2, 0, 3)(((2) << 16) | ((0) << 8) | (3)): |
| 4563 | case IP_VERSION(2, 0, 0)(((2) << 16) | ((0) << 8) | (0)): |
| 4564 | case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)): |
| 4565 | case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)): |
| 4566 | case IP_VERSION(3, 0, 2)(((3) << 16) | ((0) << 8) | (2)): |
| 4567 | case IP_VERSION(3, 0, 3)(((3) << 16) | ((0) << 8) | (3)): |
| 4568 | case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)): |
| 4569 | case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)): |
| 4570 | case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)): |
| 4571 | case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)): |
| 4572 | case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)): |
| 4573 | case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)): |
| 4574 | case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)): |
| 4575 | case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)): |
| 4576 | if (dcn10_register_irq_handlers(dm->adev)) { |
| 4577 | DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n"); |
| 4578 | goto fail; |
| 4579 | } |
| 4580 | break; |
| 4581 | default: |
| 4582 | DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",__drm_err("Unsupported DCE IP versions: 0x%X\n", adev->ip_versions [DCE_HWIP][0]) |
| 4583 | adev->ip_versions[DCE_HWIP][0])__drm_err("Unsupported DCE IP versions: 0x%X\n", adev->ip_versions [DCE_HWIP][0]); |
| 4584 | goto fail; |
| 4585 | } |
| 4586 | break; |
| 4587 | } |
| 4588 | |
| 4589 | return 0; |
| 4590 | fail: |
| 4591 | kfree(aencoder); |
| 4592 | kfree(aconnector); |
| 4593 | |
| 4594 | return -EINVAL22; |
| 4595 | } |
| 4596 | |
| 4597 | static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) |
| 4598 | { |
| 4599 | drm_atomic_private_obj_fini(&dm->atomic_obj); |
| 4600 | } |
| 4601 | |
| 4602 | /****************************************************************************** |
| 4603 | * amdgpu_display_funcs functions |
| 4604 | *****************************************************************************/ |
| 4605 | |
| 4606 | /* |
| 4607 | * dm_bandwidth_update - program display watermarks |
| 4608 | * |
| 4609 | * @adev: amdgpu_device pointer |
| 4610 | * |
| 4611 | * Calculate and program the display watermarks and line buffer allocation. |
| 4612 | */ |
| 4613 | static void dm_bandwidth_update(struct amdgpu_device *adev) |
| 4614 | { |
| 4615 | /* TODO: implement later */ |
| 4616 | } |
| 4617 | |
| 4618 | static const struct amdgpu_display_funcs dm_display_funcs = { |
| 4619 | .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ |
| 4620 | .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ |
| 4621 | .backlight_set_level = NULL((void *)0), /* never called for DC */ |
| 4622 | .backlight_get_level = NULL((void *)0), /* never called for DC */ |
| 4623 | .hpd_sense = NULL((void *)0),/* called unconditionally */ |
| 4624 | .hpd_set_polarity = NULL((void *)0), /* called unconditionally */ |
| 4625 | .hpd_get_gpio_reg = NULL((void *)0), /* VBIOS parsing. DAL does it. */ |
| 4626 | .page_flip_get_scanoutpos = |
| 4627 | dm_crtc_get_scanoutpos,/* called unconditionally */ |
| 4628 | .add_encoder = NULL((void *)0), /* VBIOS parsing. DAL does it. */ |
| 4629 | .add_connector = NULL((void *)0), /* VBIOS parsing. DAL does it. */ |
| 4630 | }; |
| 4631 | |
| 4632 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
| 4633 | |
| 4634 | static ssize_t s3_debug_store(struct device *device, |
| 4635 | struct device_attribute *attr, |
| 4636 | const char *buf, |
| 4637 | size_t count) |
| 4638 | { |
| 4639 | int ret; |
| 4640 | int s3_state; |
| 4641 | struct drm_device *drm_dev = dev_get_drvdata(device); |
| 4642 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 4643 | |
| 4644 | ret = kstrtoint(buf, 0, &s3_state); |
| 4645 | |
| 4646 | if (ret == 0) { |
| 4647 | if (s3_state) { |
| 4648 | dm_resume(adev); |
| 4649 | drm_kms_helper_hotplug_event(adev_to_drm(adev)); |
| 4650 | } else |
| 4651 | dm_suspend(adev); |
| 4652 | } |
| 4653 | |
| 4654 | return ret == 0 ? count : 0; |
| 4655 | } |
| 4656 | |
| 4657 | DEVICE_ATTR_WO(s3_debug); |
| 4658 | |
| 4659 | #endif |
| 4660 | |
| 4661 | static int dm_early_init(void *handle) |
| 4662 | { |
| 4663 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 4664 | struct amdgpu_mode_info *mode_info = &adev->mode_info; |
| 4665 | struct atom_context *ctx = mode_info->atom_context; |
| 4666 | int index = GetIndexIntoMasterTable(DATA, Object_Header)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, Object_Header ) / sizeof(USHORT)); |
| 4667 | u16 data_offset; |
| 4668 | |
| 4669 | /* if there is no object header, skip DM */ |
| 4670 | if (!amdgpu_atom_parse_data_header(ctx, index, NULL((void *)0), NULL((void *)0), NULL((void *)0), &data_offset)) { |
| 4671 | adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; |
| 4672 | dev_info(adev->dev, "No object header, skipping DM\n")do { } while(0); |
| 4673 | return -ENOENT2; |
| 4674 | } |
| 4675 | |
| 4676 | switch (adev->asic_type) { |
| 4677 | #if defined(CONFIG_DRM_AMD_DC_SI) |
| 4678 | case CHIP_TAHITI: |
| 4679 | case CHIP_PITCAIRN: |
| 4680 | case CHIP_VERDE: |
| 4681 | adev->mode_info.num_crtc = 6; |
| 4682 | adev->mode_info.num_hpd = 6; |
| 4683 | adev->mode_info.num_dig = 6; |
| 4684 | break; |
| 4685 | case CHIP_OLAND: |
| 4686 | adev->mode_info.num_crtc = 2; |
| 4687 | adev->mode_info.num_hpd = 2; |
| 4688 | adev->mode_info.num_dig = 2; |
| 4689 | break; |
| 4690 | #endif |
| 4691 | case CHIP_BONAIRE: |
| 4692 | case CHIP_HAWAII: |
| 4693 | adev->mode_info.num_crtc = 6; |
| 4694 | adev->mode_info.num_hpd = 6; |
| 4695 | adev->mode_info.num_dig = 6; |
| 4696 | break; |
| 4697 | case CHIP_KAVERI: |
| 4698 | adev->mode_info.num_crtc = 4; |
| 4699 | adev->mode_info.num_hpd = 6; |
| 4700 | adev->mode_info.num_dig = 7; |
| 4701 | break; |
| 4702 | case CHIP_KABINI: |
| 4703 | case CHIP_MULLINS: |
| 4704 | adev->mode_info.num_crtc = 2; |
| 4705 | adev->mode_info.num_hpd = 6; |
| 4706 | adev->mode_info.num_dig = 6; |
| 4707 | break; |
| 4708 | case CHIP_FIJI: |
| 4709 | case CHIP_TONGA: |
| 4710 | adev->mode_info.num_crtc = 6; |
| 4711 | adev->mode_info.num_hpd = 6; |
| 4712 | adev->mode_info.num_dig = 7; |
| 4713 | break; |
| 4714 | case CHIP_CARRIZO: |
| 4715 | adev->mode_info.num_crtc = 3; |
| 4716 | adev->mode_info.num_hpd = 6; |
| 4717 | adev->mode_info.num_dig = 9; |
| 4718 | break; |
| 4719 | case CHIP_STONEY: |
| 4720 | adev->mode_info.num_crtc = 2; |
| 4721 | adev->mode_info.num_hpd = 6; |
| 4722 | adev->mode_info.num_dig = 9; |
| 4723 | break; |
| 4724 | case CHIP_POLARIS11: |
| 4725 | case CHIP_POLARIS12: |
| 4726 | adev->mode_info.num_crtc = 5; |
| 4727 | adev->mode_info.num_hpd = 5; |
| 4728 | adev->mode_info.num_dig = 5; |
| 4729 | break; |
| 4730 | case CHIP_POLARIS10: |
| 4731 | case CHIP_VEGAM: |
| 4732 | adev->mode_info.num_crtc = 6; |
| 4733 | adev->mode_info.num_hpd = 6; |
| 4734 | adev->mode_info.num_dig = 6; |
| 4735 | break; |
| 4736 | case CHIP_VEGA10: |
| 4737 | case CHIP_VEGA12: |
| 4738 | case CHIP_VEGA20: |
| 4739 | adev->mode_info.num_crtc = 6; |
| 4740 | adev->mode_info.num_hpd = 6; |
| 4741 | adev->mode_info.num_dig = 6; |
| 4742 | break; |
| 4743 | default: |
| 4744 | |
| 4745 | switch (adev->ip_versions[DCE_HWIP][0]) { |
| 4746 | case IP_VERSION(2, 0, 2)(((2) << 16) | ((0) << 8) | (2)): |
| 4747 | case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)): |
| 4748 | adev->mode_info.num_crtc = 6; |
| 4749 | adev->mode_info.num_hpd = 6; |
| 4750 | adev->mode_info.num_dig = 6; |
| 4751 | break; |
| 4752 | case IP_VERSION(2, 0, 0)(((2) << 16) | ((0) << 8) | (0)): |
| 4753 | case IP_VERSION(3, 0, 2)(((3) << 16) | ((0) << 8) | (2)): |
| 4754 | adev->mode_info.num_crtc = 5; |
| 4755 | adev->mode_info.num_hpd = 5; |
| 4756 | adev->mode_info.num_dig = 5; |
| 4757 | break; |
| 4758 | case IP_VERSION(2, 0, 3)(((2) << 16) | ((0) << 8) | (3)): |
| 4759 | case IP_VERSION(3, 0, 3)(((3) << 16) | ((0) << 8) | (3)): |
| 4760 | adev->mode_info.num_crtc = 2; |
| 4761 | adev->mode_info.num_hpd = 2; |
| 4762 | adev->mode_info.num_dig = 2; |
| 4763 | break; |
| 4764 | case IP_VERSION(1, 0, 0)(((1) << 16) | ((0) << 8) | (0)): |
| 4765 | case IP_VERSION(1, 0, 1)(((1) << 16) | ((0) << 8) | (1)): |
| 4766 | case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)): |
| 4767 | case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)): |
| 4768 | case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)): |
| 4769 | case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)): |
| 4770 | case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)): |
| 4771 | case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)): |
| 4772 | case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)): |
| 4773 | case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)): |
| 4774 | case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)): |
| 4775 | adev->mode_info.num_crtc = 4; |
| 4776 | adev->mode_info.num_hpd = 4; |
| 4777 | adev->mode_info.num_dig = 4; |
| 4778 | break; |
| 4779 | default: |
| 4780 | DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",__drm_err("Unsupported DCE IP versions: 0x%x\n", adev->ip_versions [DCE_HWIP][0]) |
| 4781 | adev->ip_versions[DCE_HWIP][0])__drm_err("Unsupported DCE IP versions: 0x%x\n", adev->ip_versions [DCE_HWIP][0]); |
| 4782 | return -EINVAL22; |
| 4783 | } |
| 4784 | break; |
| 4785 | } |
| 4786 | |
| 4787 | amdgpu_dm_set_irq_funcs(adev); |
| 4788 | |
| 4789 | if (adev->mode_info.funcs == NULL((void *)0)) |
| 4790 | adev->mode_info.funcs = &dm_display_funcs; |
| 4791 | |
| 4792 | /* |
| 4793 | * Note: Do NOT change adev->audio_endpt_rreg and |
| 4794 | * adev->audio_endpt_wreg because they are initialised in |
| 4795 | * amdgpu_device_init() |
| 4796 | */ |
| 4797 | #if defined(CONFIG_DEBUG_KERNEL_DC) |
| 4798 | device_create_file(0 |
| 4799 | adev_to_drm(adev)->dev,0 |
| 4800 | &dev_attr_s3_debug)0; |
| 4801 | #endif |
| 4802 | |
| 4803 | return 0; |
| 4804 | } |
| 4805 | |
| 4806 | static bool_Bool modereset_required(struct drm_crtc_state *crtc_state) |
| 4807 | { |
| 4808 | return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state); |
| 4809 | } |
| 4810 | |
| 4811 | static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) |
| 4812 | { |
| 4813 | drm_encoder_cleanup(encoder); |
| 4814 | kfree(encoder); |
| 4815 | } |
| 4816 | |
| 4817 | static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { |
| 4818 | .destroy = amdgpu_dm_encoder_destroy, |
| 4819 | }; |
| 4820 | |
| 4821 | static int |
| 4822 | fill_plane_color_attributes(const struct drm_plane_state *plane_state, |
| 4823 | const enum surface_pixel_format format, |
| 4824 | enum dc_color_space *color_space) |
| 4825 | { |
| 4826 | bool_Bool full_range; |
| 4827 | |
| 4828 | *color_space = COLOR_SPACE_SRGB; |
| 4829 | |
| 4830 | /* DRM color properties only affect non-RGB formats. */ |
| 4831 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
| 4832 | return 0; |
| 4833 | |
| 4834 | full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE); |
| 4835 | |
| 4836 | switch (plane_state->color_encoding) { |
| 4837 | case DRM_COLOR_YCBCR_BT601: |
| 4838 | if (full_range) |
| 4839 | *color_space = COLOR_SPACE_YCBCR601; |
| 4840 | else |
| 4841 | *color_space = COLOR_SPACE_YCBCR601_LIMITED; |
| 4842 | break; |
| 4843 | |
| 4844 | case DRM_COLOR_YCBCR_BT709: |
| 4845 | if (full_range) |
| 4846 | *color_space = COLOR_SPACE_YCBCR709; |
| 4847 | else |
| 4848 | *color_space = COLOR_SPACE_YCBCR709_LIMITED; |
| 4849 | break; |
| 4850 | |
| 4851 | case DRM_COLOR_YCBCR_BT2020: |
| 4852 | if (full_range) |
| 4853 | *color_space = COLOR_SPACE_2020_YCBCR; |
| 4854 | else |
| 4855 | return -EINVAL22; |
| 4856 | break; |
| 4857 | |
| 4858 | default: |
| 4859 | return -EINVAL22; |
| 4860 | } |
| 4861 | |
| 4862 | return 0; |
| 4863 | } |
| 4864 | |
| 4865 | static int |
| 4866 | fill_dc_plane_info_and_addr(struct amdgpu_device *adev, |
| 4867 | const struct drm_plane_state *plane_state, |
| 4868 | const u64 tiling_flags, |
| 4869 | struct dc_plane_info *plane_info, |
| 4870 | struct dc_plane_address *address, |
| 4871 | bool_Bool tmz_surface, |
| 4872 | bool_Bool force_disable_dcc) |
| 4873 | { |
| 4874 | const struct drm_framebuffer *fb = plane_state->fb; |
| 4875 | const struct amdgpu_framebuffer *afb = |
| 4876 | to_amdgpu_framebuffer(plane_state->fb)({ const __typeof( ((struct amdgpu_framebuffer *)0)->base ) *__mptr = (plane_state->fb); (struct amdgpu_framebuffer * )( (char *)__mptr - __builtin_offsetof(struct amdgpu_framebuffer , base) );}); |
| 4877 | int ret; |
| 4878 | |
| 4879 | memset(plane_info, 0, sizeof(*plane_info))__builtin_memset((plane_info), (0), (sizeof(*plane_info))); |
| 4880 | |
| 4881 | switch (fb->format->format) { |
| 4882 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
| 4883 | plane_info->format = |
| 4884 | SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; |
| 4885 | break; |
| 4886 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 4887 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; |
| 4888 | break; |
| 4889 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4890 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4891 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; |
| 4892 | break; |
| 4893 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4894 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4895 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; |
| 4896 | break; |
| 4897 | case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4898 | case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4899 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; |
| 4900 | break; |
| 4901 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4902 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4903 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; |
| 4904 | break; |
| 4905 | case DRM_FORMAT_NV21((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('2') << 16) | ((__u32)('1') << 24)): |
| 4906 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; |
| 4907 | break; |
| 4908 | case DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 4909 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; |
| 4910 | break; |
| 4911 | case DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)): |
| 4912 | plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; |
| 4913 | break; |
| 4914 | case DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4915 | case DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4916 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; |
| 4917 | break; |
| 4918 | case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4919 | case DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4920 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; |
| 4921 | break; |
| 4922 | case DRM_FORMAT_XRGB16161616((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('8') << 24)): |
| 4923 | case DRM_FORMAT_ARGB16161616((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('8') << 24)): |
| 4924 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; |
| 4925 | break; |
| 4926 | case DRM_FORMAT_XBGR16161616((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('8') << 24)): |
| 4927 | case DRM_FORMAT_ABGR16161616((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('8') << 24)): |
| 4928 | plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; |
| 4929 | break; |
| 4930 | default: |
| 4931 | DRM_ERROR(__drm_err("Unsupported screen format %p4cc\n", &fb->format ->format) |
| 4932 | "Unsupported screen format %p4cc\n",__drm_err("Unsupported screen format %p4cc\n", &fb->format ->format) |
| 4933 | &fb->format->format)__drm_err("Unsupported screen format %p4cc\n", &fb->format ->format); |
| 4934 | return -EINVAL22; |
| 4935 | } |
| 4936 | |
| 4937 | switch (plane_state->rotation & DRM_MODE_ROTATE_MASK( (1<<0) | (1<<1) | (1<<2) | (1<<3))) { |
| 4938 | case DRM_MODE_ROTATE_0(1<<0): |
| 4939 | plane_info->rotation = ROTATION_ANGLE_0; |
| 4940 | break; |
| 4941 | case DRM_MODE_ROTATE_90(1<<1): |
| 4942 | plane_info->rotation = ROTATION_ANGLE_90; |
| 4943 | break; |
| 4944 | case DRM_MODE_ROTATE_180(1<<2): |
| 4945 | plane_info->rotation = ROTATION_ANGLE_180; |
| 4946 | break; |
| 4947 | case DRM_MODE_ROTATE_270(1<<3): |
| 4948 | plane_info->rotation = ROTATION_ANGLE_270; |
| 4949 | break; |
| 4950 | default: |
| 4951 | plane_info->rotation = ROTATION_ANGLE_0; |
| 4952 | break; |
| 4953 | } |
| 4954 | |
| 4955 | |
| 4956 | plane_info->visible = true1; |
| 4957 | plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; |
| 4958 | |
| 4959 | plane_info->layer_index = plane_state->normalized_zpos; |
| 4960 | |
| 4961 | ret = fill_plane_color_attributes(plane_state, plane_info->format, |
| 4962 | &plane_info->color_space); |
| 4963 | if (ret) |
| 4964 | return ret; |
| 4965 | |
| 4966 | ret = fill_plane_buffer_attributes(adev, afb, plane_info->format, |
| 4967 | plane_info->rotation, tiling_flags, |
| 4968 | &plane_info->tiling_info, |
| 4969 | &plane_info->plane_size, |
| 4970 | &plane_info->dcc, address, |
| 4971 | tmz_surface, force_disable_dcc); |
| 4972 | if (ret) |
| 4973 | return ret; |
| 4974 | |
| 4975 | fill_blending_from_plane_state( |
| 4976 | plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha, |
| 4977 | &plane_info->global_alpha, &plane_info->global_alpha_value); |
| 4978 | |
| 4979 | return 0; |
| 4980 | } |
| 4981 | |
| 4982 | static int fill_dc_plane_attributes(struct amdgpu_device *adev, |
| 4983 | struct dc_plane_state *dc_plane_state, |
| 4984 | struct drm_plane_state *plane_state, |
| 4985 | struct drm_crtc_state *crtc_state) |
| 4986 | { |
| 4987 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr = (crtc_state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct dm_crtc_state, base) );}); |
| 4988 | struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb; |
| 4989 | struct dc_scaling_info scaling_info; |
| 4990 | struct dc_plane_info plane_info; |
| 4991 | int ret; |
| 4992 | bool_Bool force_disable_dcc = false0; |
| 4993 | |
| 4994 | ret = fill_dc_scaling_info(adev, plane_state, &scaling_info); |
| 4995 | if (ret) |
| 4996 | return ret; |
| 4997 | |
| 4998 | dc_plane_state->src_rect = scaling_info.src_rect; |
| 4999 | dc_plane_state->dst_rect = scaling_info.dst_rect; |
| 5000 | dc_plane_state->clip_rect = scaling_info.clip_rect; |
| 5001 | dc_plane_state->scaling_quality = scaling_info.scaling_quality; |
| 5002 | |
| 5003 | force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend; |
| 5004 | ret = fill_dc_plane_info_and_addr(adev, plane_state, |
| 5005 | afb->tiling_flags, |
| 5006 | &plane_info, |
| 5007 | &dc_plane_state->address, |
| 5008 | afb->tmz_surface, |
| 5009 | force_disable_dcc); |
| 5010 | if (ret) |
| 5011 | return ret; |
| 5012 | |
| 5013 | dc_plane_state->format = plane_info.format; |
| 5014 | dc_plane_state->color_space = plane_info.color_space; |
| 5015 | dc_plane_state->format = plane_info.format; |
| 5016 | dc_plane_state->plane_size = plane_info.plane_size; |
| 5017 | dc_plane_state->rotation = plane_info.rotation; |
| 5018 | dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror; |
| 5019 | dc_plane_state->stereo_format = plane_info.stereo_format; |
| 5020 | dc_plane_state->tiling_info = plane_info.tiling_info; |
| 5021 | dc_plane_state->visible = plane_info.visible; |
| 5022 | dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha; |
| 5023 | dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha; |
| 5024 | dc_plane_state->global_alpha = plane_info.global_alpha; |
| 5025 | dc_plane_state->global_alpha_value = plane_info.global_alpha_value; |
| 5026 | dc_plane_state->dcc = plane_info.dcc; |
| 5027 | dc_plane_state->layer_index = plane_info.layer_index; |
| 5028 | dc_plane_state->flip_int_enabled = true1; |
| 5029 | |
| 5030 | /* |
| 5031 | * Always set input transfer function, since plane state is refreshed |
| 5032 | * every time. |
| 5033 | */ |
| 5034 | ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); |
| 5035 | if (ret) |
| 5036 | return ret; |
| 5037 | |
| 5038 | return 0; |
| 5039 | } |
| 5040 | |
| 5041 | static inline void fill_dc_dirty_rect(struct drm_plane *plane, |
| 5042 | struct rect *dirty_rect, int32_t x, |
| 5043 | int32_t y, int32_t width, int32_t height, |
| 5044 | int *i, bool_Bool ffu) |
| 5045 | { |
| 5046 | WARN_ON(*i >= DC_MAX_DIRTY_RECTS)({ int __ret = !!(*i >= 3); if (__ret) printf("WARNING %s failed at %s:%d\n" , "*i >= 3", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 5046); __builtin_expect(!!(__ret), 0); }); |
| 5047 | |
| 5048 | dirty_rect->x = x; |
| 5049 | dirty_rect->y = y; |
| 5050 | dirty_rect->width = width; |
| 5051 | dirty_rect->height = height; |
| 5052 | |
| 5053 | if (ffu) |
| 5054 | drm_dbg(plane->dev,__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n" , plane->base.id, width, height) |
| 5055 | "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n" , plane->base.id, width, height) |
| 5056 | plane->base.id, width, height)__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n" , plane->base.id, width, height); |
| 5057 | else |
| 5058 | drm_dbg(plane->dev,__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)" , plane->base.id, x, y, width, height) |
| 5059 | "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)" , plane->base.id, x, y, width, height) |
| 5060 | plane->base.id, x, y, width, height)__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)" , plane->base.id, x, y, width, height); |
| 5061 | |
| 5062 | (*i)++; |
| 5063 | } |
| 5064 | |
| 5065 | /** |
| 5066 | * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates |
| 5067 | * |
| 5068 | * @plane: DRM plane containing dirty regions that need to be flushed to the eDP |
| 5069 | * remote fb |
| 5070 | * @old_plane_state: Old state of @plane |
| 5071 | * @new_plane_state: New state of @plane |
| 5072 | * @crtc_state: New state of CRTC connected to the @plane |
| 5073 | * @flip_addrs: DC flip tracking struct, which also tracts dirty rects |
| 5074 | * |
| 5075 | * For PSR SU, DC informs the DMUB uController of dirty rectangle regions |
| 5076 | * (referred to as "damage clips" in DRM nomenclature) that require updating on |
| 5077 | * the eDP remote buffer. The responsibility of specifying the dirty regions is |
| 5078 | * amdgpu_dm's. |
| 5079 | * |
| 5080 | * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the |
| 5081 | * plane with regions that require flushing to the eDP remote buffer. In |
| 5082 | * addition, certain use cases - such as cursor and multi-plane overlay (MPO) - |
| 5083 | * implicitly provide damage clips without any client support via the plane |
| 5084 | * bounds. |
| 5085 | */ |
| 5086 | static void fill_dc_dirty_rects(struct drm_plane *plane, |
| 5087 | struct drm_plane_state *old_plane_state, |
| 5088 | struct drm_plane_state *new_plane_state, |
| 5089 | struct drm_crtc_state *crtc_state, |
| 5090 | struct dc_flip_addrs *flip_addrs) |
| 5091 | { |
| 5092 | struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr = (crtc_state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct dm_crtc_state, base) );}); |
| 5093 | struct rect *dirty_rects = flip_addrs->dirty_rects; |
| 5094 | uint32_t num_clips; |
| 5095 | struct drm_mode_rect *clips; |
| 5096 | bool_Bool bb_changed; |
| 5097 | bool_Bool fb_changed; |
| 5098 | u32 i = 0; |
| 5099 | |
| 5100 | /* |
| 5101 | * Cursor plane has it's own dirty rect update interface. See |
| 5102 | * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data |
| 5103 | */ |
| 5104 | if (plane->type == DRM_PLANE_TYPE_CURSOR) |
| 5105 | return; |
| 5106 | |
| 5107 | if (new_plane_state->rotation != DRM_MODE_ROTATE_0(1<<0)) |
| 5108 | goto ffu; |
| 5109 | |
| 5110 | num_clips = drm_plane_get_damage_clips_count(new_plane_state); |
| 5111 | clips = drm_plane_get_damage_clips(new_plane_state); |
| 5112 | |
| 5113 | if (!dm_crtc_state->mpo_requested) { |
| 5114 | if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS3) |
| 5115 | goto ffu; |
| 5116 | |
| 5117 | for (; flip_addrs->dirty_rect_count < num_clips; clips++) |
| 5118 | fill_dc_dirty_rect(new_plane_state->plane, |
| 5119 | &dirty_rects[flip_addrs->dirty_rect_count], |
| 5120 | clips->x1, clips->y1, |
| 5121 | clips->x2 - clips->x1, clips->y2 - clips->y1, |
| 5122 | &flip_addrs->dirty_rect_count, |
| 5123 | false0); |
| 5124 | return; |
| 5125 | } |
| 5126 | |
| 5127 | /* |
| 5128 | * MPO is requested. Add entire plane bounding box to dirty rects if |
| 5129 | * flipped to or damaged. |
| 5130 | * |
| 5131 | * If plane is moved or resized, also add old bounding box to dirty |
| 5132 | * rects. |
| 5133 | */ |
| 5134 | fb_changed = old_plane_state->fb->base.id != |
| 5135 | new_plane_state->fb->base.id; |
| 5136 | bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x || |
| 5137 | old_plane_state->crtc_y != new_plane_state->crtc_y || |
| 5138 | old_plane_state->crtc_w != new_plane_state->crtc_w || |
| 5139 | old_plane_state->crtc_h != new_plane_state->crtc_h); |
| 5140 | |
| 5141 | drm_dbg(plane->dev,__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n" , new_plane_state->plane->base.id, bb_changed, fb_changed , num_clips) |
| 5142 | "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n" , new_plane_state->plane->base.id, bb_changed, fb_changed , num_clips) |
| 5143 | new_plane_state->plane->base.id,__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n" , new_plane_state->plane->base.id, bb_changed, fb_changed , num_clips) |
| 5144 | bb_changed, fb_changed, num_clips)__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)-> dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n" , new_plane_state->plane->base.id, bb_changed, fb_changed , num_clips); |
| 5145 | |
| 5146 | if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS3) |
| 5147 | goto ffu; |
| 5148 | |
| 5149 | if (bb_changed) { |
| 5150 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
| 5151 | new_plane_state->crtc_x, |
| 5152 | new_plane_state->crtc_y, |
| 5153 | new_plane_state->crtc_w, |
| 5154 | new_plane_state->crtc_h, &i, false0); |
| 5155 | |
| 5156 | /* Add old plane bounding-box if plane is moved or resized */ |
| 5157 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
| 5158 | old_plane_state->crtc_x, |
| 5159 | old_plane_state->crtc_y, |
| 5160 | old_plane_state->crtc_w, |
| 5161 | old_plane_state->crtc_h, &i, false0); |
| 5162 | } |
| 5163 | |
| 5164 | if (num_clips) { |
| 5165 | for (; i < num_clips; clips++) |
| 5166 | fill_dc_dirty_rect(new_plane_state->plane, |
| 5167 | &dirty_rects[i], clips->x1, |
| 5168 | clips->y1, clips->x2 - clips->x1, |
| 5169 | clips->y2 - clips->y1, &i, false0); |
| 5170 | } else if (fb_changed && !bb_changed) { |
| 5171 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i], |
| 5172 | new_plane_state->crtc_x, |
| 5173 | new_plane_state->crtc_y, |
| 5174 | new_plane_state->crtc_w, |
| 5175 | new_plane_state->crtc_h, &i, false0); |
| 5176 | } |
| 5177 | |
| 5178 | flip_addrs->dirty_rect_count = i; |
| 5179 | return; |
| 5180 | |
| 5181 | ffu: |
| 5182 | fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0, |
| 5183 | dm_crtc_state->base.mode.crtc_hdisplay, |
| 5184 | dm_crtc_state->base.mode.crtc_vdisplay, |
| 5185 | &flip_addrs->dirty_rect_count, true1); |
| 5186 | } |
| 5187 | |
| 5188 | static void update_stream_scaling_settings(const struct drm_display_mode *mode, |
| 5189 | const struct dm_connector_state *dm_state, |
| 5190 | struct dc_stream_state *stream) |
| 5191 | { |
| 5192 | enum amdgpu_rmx_type rmx_type; |
| 5193 | |
| 5194 | struct rect src = { 0 }; /* viewport in composition space*/ |
| 5195 | struct rect dst = { 0 }; /* stream addressable area */ |
| 5196 | |
| 5197 | /* no mode. nothing to be done */ |
| 5198 | if (!mode) |
| 5199 | return; |
| 5200 | |
| 5201 | /* Full screen scaling by default */ |
| 5202 | src.width = mode->hdisplay; |
| 5203 | src.height = mode->vdisplay; |
| 5204 | dst.width = stream->timing.h_addressable; |
| 5205 | dst.height = stream->timing.v_addressable; |
| 5206 | |
| 5207 | if (dm_state) { |
| 5208 | rmx_type = dm_state->scaling; |
| 5209 | if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { |
| 5210 | if (src.width * dst.height < |
| 5211 | src.height * dst.width) { |
| 5212 | /* height needs less upscaling/more downscaling */ |
| 5213 | dst.width = src.width * |
| 5214 | dst.height / src.height; |
| 5215 | } else { |
| 5216 | /* width needs less upscaling/more downscaling */ |
| 5217 | dst.height = src.height * |
| 5218 | dst.width / src.width; |
| 5219 | } |
| 5220 | } else if (rmx_type == RMX_CENTER) { |
| 5221 | dst = src; |
| 5222 | } |
| 5223 | |
| 5224 | dst.x = (stream->timing.h_addressable - dst.width) / 2; |
| 5225 | dst.y = (stream->timing.v_addressable - dst.height) / 2; |
| 5226 | |
| 5227 | if (dm_state->underscan_enable) { |
| 5228 | dst.x += dm_state->underscan_hborder / 2; |
| 5229 | dst.y += dm_state->underscan_vborder / 2; |
| 5230 | dst.width -= dm_state->underscan_hborder; |
| 5231 | dst.height -= dm_state->underscan_vborder; |
| 5232 | } |
| 5233 | } |
| 5234 | |
| 5235 | stream->src = src; |
| 5236 | stream->dst = dst; |
| 5237 | |
| 5238 | DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Destination Rectangle x:%d y:%d width:%d height:%d\n" , dst.x, dst.y, dst.width, dst.height) |
| 5239 | dst.x, dst.y, dst.width, dst.height)___drm_dbg(((void *)0), DRM_UT_KMS, "Destination Rectangle x:%d y:%d width:%d height:%d\n" , dst.x, dst.y, dst.width, dst.height); |
| 5240 | |
| 5241 | } |
| 5242 | |
| 5243 | static enum dc_color_depth |
| 5244 | convert_color_depth_from_display_info(const struct drm_connector *connector, |
| 5245 | bool_Bool is_y420, int requested_bpc) |
| 5246 | { |
| 5247 | u8 bpc; |
| 5248 | |
| 5249 | if (is_y420) { |
| 5250 | bpc = 8; |
| 5251 | |
| 5252 | /* Cap display bpc based on HDMI 2.0 HF-VSDB */ |
| 5253 | if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48(1 << 2)) |
| 5254 | bpc = 16; |
| 5255 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36(1 << 1)) |
| 5256 | bpc = 12; |
| 5257 | else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30(1 << 0)) |
| 5258 | bpc = 10; |
| 5259 | } else { |
| 5260 | bpc = (uint8_t)connector->display_info.bpc; |
| 5261 | /* Assume 8 bpc by default if no bpc is specified. */ |
| 5262 | bpc = bpc ? bpc : 8; |
| 5263 | } |
| 5264 | |
| 5265 | if (requested_bpc > 0) { |
| 5266 | /* |
| 5267 | * Cap display bpc based on the user requested value. |
| 5268 | * |
| 5269 | * The value for state->max_bpc may not correctly updated |
| 5270 | * depending on when the connector gets added to the state |
| 5271 | * or if this was called outside of atomic check, so it |
| 5272 | * can't be used directly. |
| 5273 | */ |
| 5274 | bpc = min_t(u8, bpc, requested_bpc)({ u8 __min_a = (bpc); u8 __min_b = (requested_bpc); __min_a < __min_b ? __min_a : __min_b; }); |
| 5275 | |
| 5276 | /* Round down to the nearest even number. */ |
| 5277 | bpc = bpc - (bpc & 1); |
| 5278 | } |
| 5279 | |
| 5280 | switch (bpc) { |
| 5281 | case 0: |
| 5282 | /* |
| 5283 | * Temporary Work around, DRM doesn't parse color depth for |
| 5284 | * EDID revision before 1.4 |
| 5285 | * TODO: Fix edid parsing |
| 5286 | */ |
| 5287 | return COLOR_DEPTH_888; |
| 5288 | case 6: |
| 5289 | return COLOR_DEPTH_666; |
| 5290 | case 8: |
| 5291 | return COLOR_DEPTH_888; |
| 5292 | case 10: |
| 5293 | return COLOR_DEPTH_101010; |
| 5294 | case 12: |
| 5295 | return COLOR_DEPTH_121212; |
| 5296 | case 14: |
| 5297 | return COLOR_DEPTH_141414; |
| 5298 | case 16: |
| 5299 | return COLOR_DEPTH_161616; |
| 5300 | default: |
| 5301 | return COLOR_DEPTH_UNDEFINED; |
| 5302 | } |
| 5303 | } |
| 5304 | |
| 5305 | static enum dc_aspect_ratio |
| 5306 | get_aspect_ratio(const struct drm_display_mode *mode_in) |
| 5307 | { |
| 5308 | /* 1-1 mapping, since both enums follow the HDMI spec. */ |
| 5309 | return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; |
| 5310 | } |
| 5311 | |
| 5312 | static enum dc_color_space |
| 5313 | get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) |
| 5314 | { |
| 5315 | enum dc_color_space color_space = COLOR_SPACE_SRGB; |
| 5316 | |
| 5317 | switch (dc_crtc_timing->pixel_encoding) { |
| 5318 | case PIXEL_ENCODING_YCBCR422: |
| 5319 | case PIXEL_ENCODING_YCBCR444: |
| 5320 | case PIXEL_ENCODING_YCBCR420: |
| 5321 | { |
| 5322 | /* |
| 5323 | * 27030khz is the separation point between HDTV and SDTV |
| 5324 | * according to HDMI spec, we use YCbCr709 and YCbCr601 |
| 5325 | * respectively |
| 5326 | */ |
| 5327 | if (dc_crtc_timing->pix_clk_100hz > 270300) { |
| 5328 | if (dc_crtc_timing->flags.Y_ONLY) |
| 5329 | color_space = |
| 5330 | COLOR_SPACE_YCBCR709_LIMITED; |
| 5331 | else |
| 5332 | color_space = COLOR_SPACE_YCBCR709; |
| 5333 | } else { |
| 5334 | if (dc_crtc_timing->flags.Y_ONLY) |
| 5335 | color_space = |
| 5336 | COLOR_SPACE_YCBCR601_LIMITED; |
| 5337 | else |
| 5338 | color_space = COLOR_SPACE_YCBCR601; |
| 5339 | } |
| 5340 | |
| 5341 | } |
| 5342 | break; |
| 5343 | case PIXEL_ENCODING_RGB: |
| 5344 | color_space = COLOR_SPACE_SRGB; |
| 5345 | break; |
| 5346 | |
| 5347 | default: |
| 5348 | WARN_ON(1)({ int __ret = !!(1); if (__ret) printf("WARNING %s failed at %s:%d\n" , "1", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c" , 5348); __builtin_expect(!!(__ret), 0); }); |
| 5349 | break; |
| 5350 | } |
| 5351 | |
| 5352 | return color_space; |
| 5353 | } |
| 5354 | |
| 5355 | static bool_Bool adjust_colour_depth_from_display_info( |
| 5356 | struct dc_crtc_timing *timing_out, |
| 5357 | const struct drm_display_info *info) |
| 5358 | { |
| 5359 | enum dc_color_depth depth = timing_out->display_color_depth; |
| 5360 | int normalized_clk; |
| 5361 | |
| 5362 | do { |
| 5363 | normalized_clk = timing_out->pix_clk_100hz / 10; |
| 5364 | /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ |
| 5365 | if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) |
| 5366 | normalized_clk /= 2; |
| 5367 | /* Adjusting pix clock following on HDMI spec based on colour depth */ |
| 5368 | switch (depth) { |
| 5369 | case COLOR_DEPTH_888: |
| 5370 | break; |
| 5371 | case COLOR_DEPTH_101010: |
| 5372 | normalized_clk = (normalized_clk * 30) / 24; |
| 5373 | break; |
| 5374 | case COLOR_DEPTH_121212: |
| 5375 | normalized_clk = (normalized_clk * 36) / 24; |
| 5376 | break; |
| 5377 | case COLOR_DEPTH_161616: |
| 5378 | normalized_clk = (normalized_clk * 48) / 24; |
| 5379 | break; |
| 5380 | default: |
| 5381 | /* The above depths are the only ones valid for HDMI. */ |
| 5382 | return false0; |
| 5383 | } |
| 5384 | if (normalized_clk <= info->max_tmds_clock) { |
| 5385 | timing_out->display_color_depth = depth; |
| 5386 | return true1; |
| 5387 | } |
| 5388 | } while (--depth > COLOR_DEPTH_666); |
| 5389 | return false0; |
| 5390 | } |
| 5391 | |
| 5392 | static void fill_stream_properties_from_drm_display_mode( |
| 5393 | struct dc_stream_state *stream, |
| 5394 | const struct drm_display_mode *mode_in, |
| 5395 | const struct drm_connector *connector, |
| 5396 | const struct drm_connector_state *connector_state, |
| 5397 | const struct dc_stream_state *old_stream, |
| 5398 | int requested_bpc) |
| 5399 | { |
| 5400 | struct dc_crtc_timing *timing_out = &stream->timing; |
| 5401 | const struct drm_display_info *info = &connector->display_info; |
| 5402 | struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base ) );}); |
| 5403 | struct hdmi_vendor_infoframe hv_frame; |
| 5404 | struct hdmi_avi_infoframe avi_frame; |
| 5405 | |
| 5406 | memset(&hv_frame, 0, sizeof(hv_frame))__builtin_memset((&hv_frame), (0), (sizeof(hv_frame))); |
| 5407 | memset(&avi_frame, 0, sizeof(avi_frame))__builtin_memset((&avi_frame), (0), (sizeof(avi_frame))); |
| 5408 | |
| 5409 | timing_out->h_border_left = 0; |
| 5410 | timing_out->h_border_right = 0; |
| 5411 | timing_out->v_border_top = 0; |
| 5412 | timing_out->v_border_bottom = 0; |
| 5413 | /* TODO: un-hardcode */ |
| 5414 | if (drm_mode_is_420_only(info, mode_in) |
| 5415 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
| 5416 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
| 5417 | else if (drm_mode_is_420_also(info, mode_in) |
| 5418 | && aconnector->force_yuv420_output) |
| 5419 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
| 5420 | else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444(1<<1)) |
| 5421 | && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) |
| 5422 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; |
| 5423 | else |
| 5424 | timing_out->pixel_encoding = PIXEL_ENCODING_RGB; |
| 5425 | |
| 5426 | timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; |
| 5427 | timing_out->display_color_depth = convert_color_depth_from_display_info( |
| 5428 | connector, |
| 5429 | (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420), |
| 5430 | requested_bpc); |
| 5431 | timing_out->scan_type = SCANNING_TYPE_NODATA; |
| 5432 | timing_out->hdmi_vic = 0; |
| 5433 | |
| 5434 | if (old_stream) { |
| 5435 | timing_out->vic = old_stream->timing.vic; |
| 5436 | timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY; |
| 5437 | timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY; |
| 5438 | } else { |
| 5439 | timing_out->vic = drm_match_cea_mode(mode_in); |
| 5440 | if (mode_in->flags & DRM_MODE_FLAG_PHSYNC(1<<0)) |
| 5441 | timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; |
| 5442 | if (mode_in->flags & DRM_MODE_FLAG_PVSYNC(1<<2)) |
| 5443 | timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; |
| 5444 | } |
| 5445 | |
| 5446 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
| 5447 | drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); |
| 5448 | timing_out->vic = avi_frame.video_code; |
| 5449 | drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); |
| 5450 | timing_out->hdmi_vic = hv_frame.vic; |
| 5451 | } |
| 5452 | |
| 5453 | if (is_freesync_video_mode(mode_in, aconnector)) { |
| 5454 | timing_out->h_addressable = mode_in->hdisplay; |
| 5455 | timing_out->h_total = mode_in->htotal; |
| 5456 | timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start; |
| 5457 | timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay; |
| 5458 | timing_out->v_total = mode_in->vtotal; |
| 5459 | timing_out->v_addressable = mode_in->vdisplay; |
| 5460 | timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay; |
| 5461 | timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start; |
| 5462 | timing_out->pix_clk_100hz = mode_in->clock * 10; |
| 5463 | } else { |
| 5464 | timing_out->h_addressable = mode_in->crtc_hdisplay; |
| 5465 | timing_out->h_total = mode_in->crtc_htotal; |
| 5466 | timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; |
| 5467 | timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; |
| 5468 | timing_out->v_total = mode_in->crtc_vtotal; |
| 5469 | timing_out->v_addressable = mode_in->crtc_vdisplay; |
| 5470 | timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; |
| 5471 | timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; |
| 5472 | timing_out->pix_clk_100hz = mode_in->crtc_clock * 10; |
| 5473 | } |
| 5474 | |
| 5475 | timing_out->aspect_ratio = get_aspect_ratio(mode_in); |
| 5476 | |
| 5477 | stream->out_transfer_func->type = TF_TYPE_PREDEFINED; |
| 5478 | stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; |
| 5479 | if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { |
| 5480 | if (!adjust_colour_depth_from_display_info(timing_out, info) && |
| 5481 | drm_mode_is_420_also(info, mode_in) && |
| 5482 | timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { |
| 5483 | timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; |
| 5484 | adjust_colour_depth_from_display_info(timing_out, info); |
| 5485 | } |
| 5486 | } |
| 5487 | |
| 5488 | stream->output_color_space = get_output_color_space(timing_out); |
| 5489 | } |
| 5490 | |
| 5491 | static void fill_audio_info(struct audio_info *audio_info, |
| 5492 | const struct drm_connector *drm_connector, |
| 5493 | const struct dc_sink *dc_sink) |
| 5494 | { |
| 5495 | int i = 0; |
| 5496 | int cea_revision = 0; |
| 5497 | const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; |
| 5498 | |
| 5499 | audio_info->manufacture_id = edid_caps->manufacturer_id; |
| 5500 | audio_info->product_id = edid_caps->product_id; |
| 5501 | |
| 5502 | cea_revision = drm_connector->display_info.cea_rev; |
| 5503 | |
| 5504 | strscpy(audio_info->display_name, |
| 5505 | edid_caps->display_name, |
| 5506 | AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS20); |
| 5507 | |
| 5508 | if (cea_revision >= 3) { |
| 5509 | audio_info->mode_count = edid_caps->audio_mode_count; |
| 5510 | |
| 5511 | for (i = 0; i < audio_info->mode_count; ++i) { |
| 5512 | audio_info->modes[i].format_code = |
| 5513 | (enum audio_format_code) |
| 5514 | (edid_caps->audio_modes[i].format_code); |
| 5515 | audio_info->modes[i].channel_count = |
| 5516 | edid_caps->audio_modes[i].channel_count; |
| 5517 | audio_info->modes[i].sample_rates.all = |
| 5518 | edid_caps->audio_modes[i].sample_rate; |
| 5519 | audio_info->modes[i].sample_size = |
| 5520 | edid_caps->audio_modes[i].sample_size; |
| 5521 | } |
| 5522 | } |
| 5523 | |
| 5524 | audio_info->flags.all = edid_caps->speaker_flags; |
| 5525 | |
| 5526 | /* TODO: We only check for the progressive mode, check for interlace mode too */ |
| 5527 | if (drm_connector->latency_present[0]) { |
| 5528 | audio_info->video_latency = drm_connector->video_latency[0]; |
| 5529 | audio_info->audio_latency = drm_connector->audio_latency[0]; |
| 5530 | } |
| 5531 | |
| 5532 | /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ |
| 5533 | |
| 5534 | } |
| 5535 | |
| 5536 | static void |
| 5537 | copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, |
| 5538 | struct drm_display_mode *dst_mode) |
| 5539 | { |
| 5540 | dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; |
| 5541 | dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; |
| 5542 | dst_mode->crtc_clock = src_mode->crtc_clock; |
| 5543 | dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; |
| 5544 | dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; |
| 5545 | dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; |
| 5546 | dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; |
| 5547 | dst_mode->crtc_htotal = src_mode->crtc_htotal; |
| 5548 | dst_mode->crtc_hskew = src_mode->crtc_hskew; |
| 5549 | dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; |
| 5550 | dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; |
| 5551 | dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; |
| 5552 | dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; |
| 5553 | dst_mode->crtc_vtotal = src_mode->crtc_vtotal; |
| 5554 | } |
| 5555 | |
| 5556 | static void |
| 5557 | decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, |
| 5558 | const struct drm_display_mode *native_mode, |
| 5559 | bool_Bool scale_enabled) |
| 5560 | { |
| 5561 | if (scale_enabled) { |
| 5562 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); |
| 5563 | } else if (native_mode->clock == drm_mode->clock && |
| 5564 | native_mode->htotal == drm_mode->htotal && |
| 5565 | native_mode->vtotal == drm_mode->vtotal) { |
| 5566 | copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); |
| 5567 | } else { |
| 5568 | /* no scaling nor amdgpu inserted, no need to patch */ |
| 5569 | } |
| 5570 | } |
| 5571 | |
| 5572 | static struct dc_sink * |
| 5573 | create_fake_sink(struct amdgpu_dm_connector *aconnector) |
| 5574 | { |
| 5575 | struct dc_sink_init_data sink_init_data = { 0 }; |
| 5576 | struct dc_sink *sink = NULL((void *)0); |
| 5577 | |
| 5578 | sink_init_data.link = aconnector->dc_link; |
| 5579 | sink_init_data.sink_signal = aconnector->dc_link->connector_signal; |
| 5580 | |
| 5581 | sink = dc_sink_create(&sink_init_data); |
| 5582 | if (!sink) { |
| 5583 | DRM_ERROR("Failed to create sink!\n")__drm_err("Failed to create sink!\n"); |
| 5584 | return NULL((void *)0); |
| 5585 | } |
| 5586 | sink->sink_signal = SIGNAL_TYPE_VIRTUAL; |
| 5587 | |
| 5588 | return sink; |
| 5589 | } |
| 5590 | |
| 5591 | static void set_multisync_trigger_params( |
| 5592 | struct dc_stream_state *stream) |
| 5593 | { |
| 5594 | struct dc_stream_state *master = NULL((void *)0); |
| 5595 | |
| 5596 | if (stream->triggered_crtc_reset.enabled) { |
| 5597 | master = stream->triggered_crtc_reset.event_source; |
| 5598 | stream->triggered_crtc_reset.event = |
| 5599 | master->timing.flags.VSYNC_POSITIVE_POLARITY ? |
| 5600 | CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING; |
| 5601 | stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL; |
| 5602 | } |
| 5603 | } |
| 5604 | |
| 5605 | static void set_master_stream(struct dc_stream_state *stream_set[], |
| 5606 | int stream_count) |
| 5607 | { |
| 5608 | int j, highest_rfr = 0, master_stream = 0; |
| 5609 | |
| 5610 | for (j = 0; j < stream_count; j++) { |
| 5611 | if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) { |
| 5612 | int refresh_rate = 0; |
| 5613 | |
| 5614 | refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/ |
| 5615 | (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total); |
| 5616 | if (refresh_rate > highest_rfr) { |
| 5617 | highest_rfr = refresh_rate; |
| 5618 | master_stream = j; |
| 5619 | } |
| 5620 | } |
| 5621 | } |
| 5622 | for (j = 0; j < stream_count; j++) { |
| 5623 | if (stream_set[j]) |
| 5624 | stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream]; |
| 5625 | } |
| 5626 | } |
| 5627 | |
| 5628 | static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) |
| 5629 | { |
| 5630 | int i = 0; |
| 5631 | struct dc_stream_state *stream; |
| 5632 | |
| 5633 | if (context->stream_count < 2) |
| 5634 | return; |
| 5635 | for (i = 0; i < context->stream_count ; i++) { |
| 5636 | if (!context->streams[i]) |
| 5637 | continue; |
| 5638 | /* |
| 5639 | * TODO: add a function to read AMD VSDB bits and set |
| 5640 | * crtc_sync_master.multi_sync_enabled flag |
| 5641 | * For now it's set to false |
| 5642 | */ |
| 5643 | } |
| 5644 | |
| 5645 | set_master_stream(context->streams, context->stream_count); |
| 5646 | |
| 5647 | for (i = 0; i < context->stream_count ; i++) { |
| 5648 | stream = context->streams[i]; |
| 5649 | |
| 5650 | if (!stream) |
| 5651 | continue; |
| 5652 | |
| 5653 | set_multisync_trigger_params(stream); |
| 5654 | } |
| 5655 | } |
| 5656 | |
| 5657 | /** |
| 5658 | * DOC: FreeSync Video |
| 5659 | * |
| 5660 | * When a userspace application wants to play a video, the content follows a |
| 5661 | * standard format definition that usually specifies the FPS for that format. |
| 5662 | * The below list illustrates some video format and the expected FPS, |
| 5663 | * respectively: |
| 5664 | * |
| 5665 | * - TV/NTSC (23.976 FPS) |
| 5666 | * - Cinema (24 FPS) |
| 5667 | * - TV/PAL (25 FPS) |
| 5668 | * - TV/NTSC (29.97 FPS) |
| 5669 | * - TV/NTSC (30 FPS) |
| 5670 | * - Cinema HFR (48 FPS) |
| 5671 | * - TV/PAL (50 FPS) |
| 5672 | * - Commonly used (60 FPS) |
| 5673 | * - Multiples of 24 (48,72,96 FPS) |
| 5674 | * |
| 5675 | * The list of standards video format is not huge and can be added to the |
| 5676 | * connector modeset list beforehand. With that, userspace can leverage |
| 5677 | * FreeSync to extends the front porch in order to attain the target refresh |
| 5678 | * rate. Such a switch will happen seamlessly, without screen blanking or |
| 5679 | * reprogramming of the output in any other way. If the userspace requests a |
| 5680 | * modesetting change compatible with FreeSync modes that only differ in the |
| 5681 | * refresh rate, DC will skip the full update and avoid blink during the |
| 5682 | * transition. For example, the video player can change the modesetting from |
| 5683 | * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without |
| 5684 | * causing any display blink. This same concept can be applied to a mode |
| 5685 | * setting change. |
| 5686 | */ |
| 5687 | static struct drm_display_mode * |
| 5688 | get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, |
| 5689 | bool_Bool use_probed_modes) |
| 5690 | { |
| 5691 | struct drm_display_mode *m, *m_pref = NULL((void *)0); |
| 5692 | u16 current_refresh, highest_refresh; |
| 5693 | struct list_head *list_head = use_probed_modes ? |
| 5694 | &aconnector->base.probed_modes : |
| 5695 | &aconnector->base.modes; |
| 5696 | |
| 5697 | if (aconnector->freesync_vid_base.clock != 0) |
| 5698 | return &aconnector->freesync_vid_base; |
| 5699 | |
| 5700 | /* Find the preferred mode */ |
| 5701 | list_for_each_entry(m, list_head, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = ((list_head)->next); (__typeof(*m) *)( (char *)__mptr - __builtin_offsetof(__typeof(*m), head) );}); &m->head != (list_head); m = ({ const __typeof( ((__typeof(*m) *)0)-> head ) *__mptr = (m->head.next); (__typeof(*m) *)( (char * )__mptr - __builtin_offsetof(__typeof(*m), head) );})) { |
| 5702 | if (m->type & DRM_MODE_TYPE_PREFERRED(1<<3)) { |
| 5703 | m_pref = m; |
| 5704 | break; |
| 5705 | } |
| 5706 | } |
| 5707 | |
| 5708 | if (!m_pref) { |
| 5709 | /* Probably an EDID with no preferred mode. Fallback to first entry */ |
| 5710 | m_pref = list_first_entry_or_null((list_empty(&aconnector->base.modes) ? ((void *)0) : ( { const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&aconnector->base.modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );})) |
| 5711 | &aconnector->base.modes, struct drm_display_mode, head)(list_empty(&aconnector->base.modes) ? ((void *)0) : ( { const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&aconnector->base.modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );})); |
| 5712 | if (!m_pref) { |
| 5713 | DRM_DEBUG_DRIVER("No preferred mode found in EDID\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "No preferred mode found in EDID\n" ); |
| 5714 | return NULL((void *)0); |
| 5715 | } |
| 5716 | } |
| 5717 | |
| 5718 | highest_refresh = drm_mode_vrefresh(m_pref); |
| 5719 | |
| 5720 | /* |
| 5721 | * Find the mode with highest refresh rate with same resolution. |
| 5722 | * For some monitors, preferred mode is not the mode with highest |
| 5723 | * supported refresh rate. |
| 5724 | */ |
| 5725 | list_for_each_entry(m, list_head, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = ((list_head)->next); (__typeof(*m) *)( (char *)__mptr - __builtin_offsetof(__typeof(*m), head) );}); &m->head != (list_head); m = ({ const __typeof( ((__typeof(*m) *)0)-> head ) *__mptr = (m->head.next); (__typeof(*m) *)( (char * )__mptr - __builtin_offsetof(__typeof(*m), head) );})) { |
| 5726 | current_refresh = drm_mode_vrefresh(m); |
| 5727 | |
| 5728 | if (m->hdisplay == m_pref->hdisplay && |
| 5729 | m->vdisplay == m_pref->vdisplay && |
| 5730 | highest_refresh < current_refresh) { |
| 5731 | highest_refresh = current_refresh; |
| 5732 | m_pref = m; |
| 5733 | } |
| 5734 | } |
| 5735 | |
| 5736 | drm_mode_copy(&aconnector->freesync_vid_base, m_pref); |
| 5737 | return m_pref; |
| 5738 | } |
| 5739 | |
| 5740 | static bool_Bool is_freesync_video_mode(const struct drm_display_mode *mode, |
| 5741 | struct amdgpu_dm_connector *aconnector) |
| 5742 | { |
| 5743 | struct drm_display_mode *high_mode; |
| 5744 | int timing_diff; |
| 5745 | |
| 5746 | high_mode = get_highest_refresh_rate_mode(aconnector, false0); |
| 5747 | if (!high_mode || !mode) |
| 5748 | return false0; |
| 5749 | |
| 5750 | timing_diff = high_mode->vtotal - mode->vtotal; |
| 5751 | |
| 5752 | if (high_mode->clock == 0 || high_mode->clock != mode->clock || |
| 5753 | high_mode->hdisplay != mode->hdisplay || |
| 5754 | high_mode->vdisplay != mode->vdisplay || |
| 5755 | high_mode->hsync_start != mode->hsync_start || |
| 5756 | high_mode->hsync_end != mode->hsync_end || |
| 5757 | high_mode->htotal != mode->htotal || |
| 5758 | high_mode->hskew != mode->hskew || |
| 5759 | high_mode->vscan != mode->vscan || |
| 5760 | high_mode->vsync_start - mode->vsync_start != timing_diff || |
| 5761 | high_mode->vsync_end - mode->vsync_end != timing_diff) |
| 5762 | return false0; |
| 5763 | else |
| 5764 | return true1; |
| 5765 | } |
| 5766 | |
| 5767 | #if defined(CONFIG_DRM_AMD_DC_DCN1) |
| 5768 | static void update_dsc_caps(struct amdgpu_dm_connector *aconnector, |
| 5769 | struct dc_sink *sink, struct dc_stream_state *stream, |
| 5770 | struct dsc_dec_dpcd_caps *dsc_caps) |
| 5771 | { |
| 5772 | stream->timing.flags.DSC = 0; |
| 5773 | dsc_caps->is_dsc_supported = false0; |
| 5774 | |
| 5775 | if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || |
| 5776 | sink->sink_signal == SIGNAL_TYPE_EDP)) { |
| 5777 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE || |
| 5778 | sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) |
| 5779 | dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc, |
| 5780 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, |
| 5781 | aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, |
| 5782 | dsc_caps); |
| 5783 | } |
| 5784 | } |
| 5785 | |
| 5786 | |
| 5787 | static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector, |
| 5788 | struct dc_sink *sink, struct dc_stream_state *stream, |
| 5789 | struct dsc_dec_dpcd_caps *dsc_caps, |
| 5790 | uint32_t max_dsc_target_bpp_limit_override) |
| 5791 | { |
| 5792 | const struct dc_link_settings *verified_link_cap = NULL((void *)0); |
| 5793 | u32 link_bw_in_kbps; |
| 5794 | u32 edp_min_bpp_x16, edp_max_bpp_x16; |
| 5795 | struct dc *dc = sink->ctx->dc; |
| 5796 | struct dc_dsc_bw_range bw_range = {0}; |
| 5797 | struct dc_dsc_config dsc_cfg = {0}; |
| 5798 | |
| 5799 | verified_link_cap = dc_link_get_link_cap(stream->link); |
| 5800 | link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap); |
| 5801 | edp_min_bpp_x16 = 8 * 16; |
| 5802 | edp_max_bpp_x16 = 8 * 16; |
| 5803 | |
| 5804 | if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel) |
| 5805 | edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel; |
| 5806 | |
| 5807 | if (edp_max_bpp_x16 < edp_min_bpp_x16) |
| 5808 | edp_min_bpp_x16 = edp_max_bpp_x16; |
| 5809 | |
| 5810 | if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0], |
| 5811 | dc->debug.dsc_min_slice_height_override, |
| 5812 | edp_min_bpp_x16, edp_max_bpp_x16, |
| 5813 | dsc_caps, |
| 5814 | &stream->timing, |
| 5815 | &bw_range)) { |
| 5816 | |
| 5817 | if (bw_range.max_kbps < link_bw_in_kbps) { |
| 5818 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], |
| 5819 | dsc_caps, |
| 5820 | dc->debug.dsc_min_slice_height_override, |
| 5821 | max_dsc_target_bpp_limit_override, |
| 5822 | 0, |
| 5823 | &stream->timing, |
| 5824 | &dsc_cfg)) { |
| 5825 | stream->timing.dsc_cfg = dsc_cfg; |
| 5826 | stream->timing.flags.DSC = 1; |
| 5827 | stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16; |
| 5828 | } |
| 5829 | return; |
| 5830 | } |
| 5831 | } |
| 5832 | |
| 5833 | if (dc_dsc_compute_config(dc->res_pool->dscs[0], |
| 5834 | dsc_caps, |
| 5835 | dc->debug.dsc_min_slice_height_override, |
| 5836 | max_dsc_target_bpp_limit_override, |
| 5837 | link_bw_in_kbps, |
| 5838 | &stream->timing, |
| 5839 | &dsc_cfg)) { |
| 5840 | stream->timing.dsc_cfg = dsc_cfg; |
| 5841 | stream->timing.flags.DSC = 1; |
| 5842 | } |
| 5843 | } |
| 5844 | |
| 5845 | |
| 5846 | static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, |
| 5847 | struct dc_sink *sink, struct dc_stream_state *stream, |
| 5848 | struct dsc_dec_dpcd_caps *dsc_caps) |
| 5849 | { |
| 5850 | struct drm_connector *drm_connector = &aconnector->base; |
| 5851 | u32 link_bandwidth_kbps; |
| 5852 | struct dc *dc = sink->ctx->dc; |
| 5853 | u32 max_supported_bw_in_kbps, timing_bw_in_kbps; |
| 5854 | u32 dsc_max_supported_bw_in_kbps; |
| 5855 | u32 max_dsc_target_bpp_limit_override = |
| 5856 | drm_connector->display_info.max_dsc_bpp; |
| 5857 | |
| 5858 | link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, |
| 5859 | dc_link_get_link_cap(aconnector->dc_link)); |
| 5860 | |
| 5861 | /* Set DSC policy according to dsc_clock_en */ |
| 5862 | dc_dsc_policy_set_enable_dsc_when_not_needed( |
| 5863 | aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE); |
| 5864 | |
| 5865 | if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && |
| 5866 | !aconnector->dc_link->panel_config.dsc.disable_dsc_edp && |
| 5867 | dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) { |
| 5868 | |
| 5869 | apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override); |
| 5870 | |
| 5871 | } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) { |
| 5872 | if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { |
| 5873 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], |
| 5874 | dsc_caps, |
| 5875 | aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, |
| 5876 | max_dsc_target_bpp_limit_override, |
| 5877 | link_bandwidth_kbps, |
| 5878 | &stream->timing, |
| 5879 | &stream->timing.dsc_cfg)) { |
| 5880 | stream->timing.flags.DSC = 1; |
| 5881 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: [%s] DSC is selected from SST RX\n" , __func__, drm_connector->name); |
| 5882 | } |
| 5883 | } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { |
| 5884 | timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); |
| 5885 | max_supported_bw_in_kbps = link_bandwidth_kbps; |
| 5886 | dsc_max_supported_bw_in_kbps = link_bandwidth_kbps; |
| 5887 | |
| 5888 | if (timing_bw_in_kbps > max_supported_bw_in_kbps && |
| 5889 | max_supported_bw_in_kbps > 0 && |
| 5890 | dsc_max_supported_bw_in_kbps > 0) |
| 5891 | if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0], |
| 5892 | dsc_caps, |
| 5893 | aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override, |
| 5894 | max_dsc_target_bpp_limit_override, |
| 5895 | dsc_max_supported_bw_in_kbps, |
| 5896 | &stream->timing, |
| 5897 | &stream->timing.dsc_cfg)) { |
| 5898 | stream->timing.flags.DSC = 1; |
| 5899 | DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: [%s] DSC is selected from DP-HDMI PCON\n" , __func__, drm_connector->name) |
| 5900 | __func__, drm_connector->name)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: [%s] DSC is selected from DP-HDMI PCON\n" , __func__, drm_connector->name); |
| 5901 | } |
| 5902 | } |
| 5903 | } |
| 5904 | |
| 5905 | /* Overwrite the stream flag if DSC is enabled through debugfs */ |
| 5906 | if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE) |
| 5907 | stream->timing.flags.DSC = 1; |
| 5908 | |
| 5909 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h) |
| 5910 | stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; |
| 5911 | |
| 5912 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v) |
| 5913 | stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; |
| 5914 | |
| 5915 | if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel) |
| 5916 | stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; |
| 5917 | } |
| 5918 | #endif /* CONFIG_DRM_AMD_DC_DCN */ |
| 5919 | |
| 5920 | static struct dc_stream_state * |
| 5921 | create_stream_for_sink(struct amdgpu_dm_connector *aconnector, |
| 5922 | const struct drm_display_mode *drm_mode, |
| 5923 | const struct dm_connector_state *dm_state, |
| 5924 | const struct dc_stream_state *old_stream, |
| 5925 | int requested_bpc) |
| 5926 | { |
| 5927 | struct drm_display_mode *preferred_mode = NULL((void *)0); |
| 5928 | struct drm_connector *drm_connector; |
| 5929 | const struct drm_connector_state *con_state = |
| 5930 | dm_state ? &dm_state->base : NULL((void *)0); |
| 5931 | struct dc_stream_state *stream = NULL((void *)0); |
| 5932 | struct drm_display_mode mode = *drm_mode; |
| 5933 | struct drm_display_mode saved_mode; |
| 5934 | struct drm_display_mode *freesync_mode = NULL((void *)0); |
| 5935 | bool_Bool native_mode_found = false0; |
| 5936 | bool_Bool recalculate_timing = false0; |
| 5937 | bool_Bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false0; |
| 5938 | int mode_refresh; |
| 5939 | int preferred_refresh = 0; |
| 5940 | #if defined(CONFIG_DRM_AMD_DC_DCN1) |
| 5941 | struct dsc_dec_dpcd_caps dsc_caps; |
| 5942 | #endif |
| 5943 | |
| 5944 | struct dc_sink *sink = NULL((void *)0); |
| 5945 | |
| 5946 | memset(&saved_mode, 0, sizeof(saved_mode))__builtin_memset((&saved_mode), (0), (sizeof(saved_mode)) ); |
| 5947 | |
| 5948 | if (aconnector == NULL((void *)0)) { |
| 5949 | DRM_ERROR("aconnector is NULL!\n")__drm_err("aconnector is NULL!\n"); |
| 5950 | return stream; |
| 5951 | } |
| 5952 | |
| 5953 | drm_connector = &aconnector->base; |
| 5954 | |
| 5955 | if (!aconnector->dc_sink) { |
| 5956 | sink = create_fake_sink(aconnector); |
| 5957 | if (!sink) |
| 5958 | return stream; |
| 5959 | } else { |
| 5960 | sink = aconnector->dc_sink; |
| 5961 | dc_sink_retain(sink); |
| 5962 | } |
| 5963 | |
| 5964 | stream = dc_create_stream_for_sink(sink); |
| 5965 | |
| 5966 | if (stream == NULL((void *)0)) { |
| 5967 | DRM_ERROR("Failed to create stream for sink!\n")__drm_err("Failed to create stream for sink!\n"); |
| 5968 | goto finish; |
| 5969 | } |
| 5970 | |
| 5971 | stream->dm_stream_context = aconnector; |
| 5972 | |
| 5973 | stream->timing.flags.LTE_340MCSC_SCRAMBLE = |
| 5974 | drm_connector->display_info.hdmi.scdc.scrambling.low_rates; |
| 5975 | |
| 5976 | list_for_each_entry(preferred_mode, &aconnector->base.modes, head)for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode ) *)0)->head ) *__mptr = ((&aconnector->base.modes) ->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof (__typeof(*preferred_mode), head) );}); &preferred_mode-> head != (&aconnector->base.modes); preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode) *)0)->head ) * __mptr = (preferred_mode->head.next); (__typeof(*preferred_mode ) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode ), head) );})) { |
| 5977 | /* Search for preferred mode */ |
| 5978 | if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED(1<<3)) { |
| 5979 | native_mode_found = true1; |
| 5980 | break; |
| 5981 | } |
| 5982 | } |
| 5983 | if (!native_mode_found) |
| 5984 | preferred_mode = list_first_entry_or_null((list_empty(&aconnector->base.modes) ? ((void *)0) : ( { const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&aconnector->base.modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );})) |
| 5985 | &aconnector->base.modes,(list_empty(&aconnector->base.modes) ? ((void *)0) : ( { const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&aconnector->base.modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );})) |
| 5986 | struct drm_display_mode,(list_empty(&aconnector->base.modes) ? ((void *)0) : ( { const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&aconnector->base.modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );})) |
| 5987 | head)(list_empty(&aconnector->base.modes) ? ((void *)0) : ( { const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&aconnector->base.modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );})); |