| File: | dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c |
| Warning: | line 1604, column 24 Value stored to 'adev' during its initialization is never read |
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| 1 | /* |
| 2 | * Copyright 2019 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | */ |
| 22 | |
| 23 | #define SWSMU_CODE_LAYER_L1 |
| 24 | |
| 25 | #include <linux/firmware.h> |
| 26 | #include <linux/pci.h> |
| 27 | #include <linux/reboot.h> |
| 28 | |
| 29 | #include "amdgpu.h" |
| 30 | #include "amdgpu_smu.h" |
| 31 | #include "smu_internal.h" |
| 32 | #include "atom.h" |
| 33 | #include "arcturus_ppt.h" |
| 34 | #include "navi10_ppt.h" |
| 35 | #include "sienna_cichlid_ppt.h" |
| 36 | #include "renoir_ppt.h" |
| 37 | #include "vangogh_ppt.h" |
| 38 | #include "aldebaran_ppt.h" |
| 39 | #include "yellow_carp_ppt.h" |
| 40 | #include "cyan_skillfish_ppt.h" |
| 41 | #include "smu_v13_0_0_ppt.h" |
| 42 | #include "smu_v13_0_4_ppt.h" |
| 43 | #include "smu_v13_0_5_ppt.h" |
| 44 | #include "smu_v13_0_7_ppt.h" |
| 45 | #include "amd_pcie.h" |
| 46 | |
| 47 | /* |
| 48 | * DO NOT use these for err/warn/info/debug messages. |
| 49 | * Use dev_err, dev_warn, dev_info and dev_dbg instead. |
| 50 | * They are more MGPU friendly. |
| 51 | */ |
| 52 | #undef pr_err |
| 53 | #undef pr_warn |
| 54 | #undef pr_info |
| 55 | #undef pr_debug |
| 56 | |
| 57 | static const struct amd_pm_funcs swsmu_pm_funcs; |
| 58 | static int smu_force_smuclk_levels(struct smu_context *smu, |
| 59 | enum smu_clk_type clk_type, |
| 60 | uint32_t mask); |
| 61 | static int smu_handle_task(struct smu_context *smu, |
| 62 | enum amd_dpm_forced_level level, |
| 63 | enum amd_pp_task task_id); |
| 64 | static int smu_reset(struct smu_context *smu); |
| 65 | static int smu_set_fan_speed_pwm(void *handle, u32 speed); |
| 66 | static int smu_set_fan_control_mode(void *handle, u32 value); |
| 67 | static int smu_set_power_limit(void *handle, uint32_t limit); |
| 68 | static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); |
| 69 | static int smu_set_gfx_cgpg(struct smu_context *smu, bool_Bool enabled); |
| 70 | static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); |
| 71 | |
| 72 | static int smu_sys_get_pp_feature_mask(void *handle, |
| 73 | char *buf) |
| 74 | { |
| 75 | struct smu_context *smu = handle; |
| 76 | |
| 77 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 78 | return -EOPNOTSUPP45; |
| 79 | |
| 80 | return smu_get_pp_feature_mask(smu, buf)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_pp_feature_mask ? (smu)->ppt_funcs->get_pp_feature_mask(smu, buf) : 0) : -22); |
| 81 | } |
| 82 | |
| 83 | static int smu_sys_set_pp_feature_mask(void *handle, |
| 84 | uint64_t new_mask) |
| 85 | { |
| 86 | struct smu_context *smu = handle; |
| 87 | |
| 88 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 89 | return -EOPNOTSUPP45; |
| 90 | |
| 91 | return smu_set_pp_feature_mask(smu, new_mask)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_pp_feature_mask ? (smu)->ppt_funcs->set_pp_feature_mask(smu, new_mask) : 0) : -22); |
| 92 | } |
| 93 | |
| 94 | int smu_set_residency_gfxoff(struct smu_context *smu, bool_Bool value) |
| 95 | { |
| 96 | if (!smu->ppt_funcs->set_gfx_off_residency) |
| 97 | return -EINVAL22; |
| 98 | |
| 99 | return smu_set_gfx_off_residency(smu, value)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_gfx_off_residency ? (smu)->ppt_funcs->set_gfx_off_residency(smu, value) : 0) : -22); |
| 100 | } |
| 101 | |
| 102 | int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) |
| 103 | { |
| 104 | if (!smu->ppt_funcs->get_gfx_off_residency) |
| 105 | return -EINVAL22; |
| 106 | |
| 107 | return smu_get_gfx_off_residency(smu, value)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_gfx_off_residency ? (smu)->ppt_funcs->get_gfx_off_residency(smu, value) : 0) : -22); |
| 108 | } |
| 109 | |
| 110 | int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) |
| 111 | { |
| 112 | if (!smu->ppt_funcs->get_gfx_off_entrycount) |
| 113 | return -EINVAL22; |
| 114 | |
| 115 | return smu_get_gfx_off_entrycount(smu, value)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_gfx_off_entrycount ? (smu)->ppt_funcs->get_gfx_off_entrycount(smu, value) : 0) : -22); |
| 116 | } |
| 117 | |
| 118 | int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) |
| 119 | { |
| 120 | if (!smu->ppt_funcs->get_gfx_off_status) |
| 121 | return -EINVAL22; |
| 122 | |
| 123 | *value = smu_get_gfx_off_status(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_gfx_off_status ? (smu)->ppt_funcs->get_gfx_off_status(smu) : 0) : -22 ); |
| 124 | |
| 125 | return 0; |
| 126 | } |
| 127 | |
| 128 | int smu_set_soft_freq_range(struct smu_context *smu, |
| 129 | enum smu_clk_type clk_type, |
| 130 | uint32_t min, |
| 131 | uint32_t max) |
| 132 | { |
| 133 | int ret = 0; |
| 134 | |
| 135 | if (smu->ppt_funcs->set_soft_freq_limited_range) |
| 136 | ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, |
| 137 | clk_type, |
| 138 | min, |
| 139 | max); |
| 140 | |
| 141 | return ret; |
| 142 | } |
| 143 | |
| 144 | int smu_get_dpm_freq_range(struct smu_context *smu, |
| 145 | enum smu_clk_type clk_type, |
| 146 | uint32_t *min, |
| 147 | uint32_t *max) |
| 148 | { |
| 149 | int ret = -ENOTSUPP91; |
| 150 | |
| 151 | if (!min && !max) |
| 152 | return -EINVAL22; |
| 153 | |
| 154 | if (smu->ppt_funcs->get_dpm_ultimate_freq) |
| 155 | ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, |
| 156 | clk_type, |
| 157 | min, |
| 158 | max); |
| 159 | |
| 160 | return ret; |
| 161 | } |
| 162 | |
| 163 | int smu_set_gfx_power_up_by_imu(struct smu_context *smu) |
| 164 | { |
| 165 | int ret = 0; |
| 166 | struct amdgpu_device *adev = smu->adev; |
| 167 | |
| 168 | if (smu->ppt_funcs->set_gfx_power_up_by_imu) { |
| 169 | ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); |
| 170 | if (ret) |
| 171 | dev_err(adev->dev, "Failed to enable gfx imu!\n")printf("drm:pid%d:%s *ERROR* " "Failed to enable gfx imu!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 172 | } |
| 173 | return ret; |
| 174 | } |
| 175 | |
| 176 | static u32 smu_get_mclk(void *handle, bool_Bool low) |
| 177 | { |
| 178 | struct smu_context *smu = handle; |
| 179 | uint32_t clk_freq; |
| 180 | int ret = 0; |
| 181 | |
| 182 | ret = smu_get_dpm_freq_range(smu, SMU_UCLK, |
| 183 | low ? &clk_freq : NULL((void *)0), |
| 184 | !low ? &clk_freq : NULL((void *)0)); |
| 185 | if (ret) |
| 186 | return 0; |
| 187 | return clk_freq * 100; |
| 188 | } |
| 189 | |
| 190 | static u32 smu_get_sclk(void *handle, bool_Bool low) |
| 191 | { |
| 192 | struct smu_context *smu = handle; |
| 193 | uint32_t clk_freq; |
| 194 | int ret = 0; |
| 195 | |
| 196 | ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, |
| 197 | low ? &clk_freq : NULL((void *)0), |
| 198 | !low ? &clk_freq : NULL((void *)0)); |
| 199 | if (ret) |
| 200 | return 0; |
| 201 | return clk_freq * 100; |
| 202 | } |
| 203 | |
| 204 | static int smu_set_gfx_imu_enable(struct smu_context *smu) |
| 205 | { |
| 206 | struct amdgpu_device *adev = smu->adev; |
| 207 | |
| 208 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) |
| 209 | return 0; |
| 210 | |
| 211 | if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) |
| 212 | return 0; |
| 213 | |
| 214 | return smu_set_gfx_power_up_by_imu(smu); |
| 215 | } |
| 216 | |
| 217 | static int smu_dpm_set_vcn_enable(struct smu_context *smu, |
| 218 | bool_Bool enable) |
| 219 | { |
| 220 | struct smu_power_context *smu_power = &smu->smu_power; |
| 221 | struct smu_power_gate *power_gate = &smu_power->power_gate; |
| 222 | int ret = 0; |
| 223 | |
| 224 | if (!smu->ppt_funcs->dpm_set_vcn_enable) |
| 225 | return 0; |
| 226 | |
| 227 | if (atomic_read(&power_gate->vcn_gated)({ typeof(*(&power_gate->vcn_gated)) __tmp = *(volatile typeof(*(&power_gate->vcn_gated)) *)&(*(&power_gate ->vcn_gated)); membar_datadep_consumer(); __tmp; }) ^ enable) |
| 228 | return 0; |
| 229 | |
| 230 | ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); |
| 231 | if (!ret) |
| 232 | atomic_set(&power_gate->vcn_gated, !enable)({ typeof(*(&power_gate->vcn_gated)) __tmp = ((!enable )); *(volatile typeof(*(&power_gate->vcn_gated)) *)& (*(&power_gate->vcn_gated)) = __tmp; __tmp; }); |
| 233 | |
| 234 | return ret; |
| 235 | } |
| 236 | |
| 237 | static int smu_dpm_set_jpeg_enable(struct smu_context *smu, |
| 238 | bool_Bool enable) |
| 239 | { |
| 240 | struct smu_power_context *smu_power = &smu->smu_power; |
| 241 | struct smu_power_gate *power_gate = &smu_power->power_gate; |
| 242 | int ret = 0; |
| 243 | |
| 244 | if (!smu->ppt_funcs->dpm_set_jpeg_enable) |
| 245 | return 0; |
| 246 | |
| 247 | if (atomic_read(&power_gate->jpeg_gated)({ typeof(*(&power_gate->jpeg_gated)) __tmp = *(volatile typeof(*(&power_gate->jpeg_gated)) *)&(*(&power_gate ->jpeg_gated)); membar_datadep_consumer(); __tmp; }) ^ enable) |
| 248 | return 0; |
| 249 | |
| 250 | ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); |
| 251 | if (!ret) |
| 252 | atomic_set(&power_gate->jpeg_gated, !enable)({ typeof(*(&power_gate->jpeg_gated)) __tmp = ((!enable )); *(volatile typeof(*(&power_gate->jpeg_gated)) *)& (*(&power_gate->jpeg_gated)) = __tmp; __tmp; }); |
| 253 | |
| 254 | return ret; |
| 255 | } |
| 256 | |
| 257 | /** |
| 258 | * smu_dpm_set_power_gate - power gate/ungate the specific IP block |
| 259 | * |
| 260 | * @handle: smu_context pointer |
| 261 | * @block_type: the IP block to power gate/ungate |
| 262 | * @gate: to power gate if true, ungate otherwise |
| 263 | * |
| 264 | * This API uses no smu->mutex lock protection due to: |
| 265 | * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). |
| 266 | * This is guarded to be race condition free by the caller. |
| 267 | * 2. Or get called on user setting request of power_dpm_force_performance_level. |
| 268 | * Under this case, the smu->mutex lock protection is already enforced on |
| 269 | * the parent API smu_force_performance_level of the call path. |
| 270 | */ |
| 271 | static int smu_dpm_set_power_gate(void *handle, |
| 272 | uint32_t block_type, |
| 273 | bool_Bool gate) |
| 274 | { |
| 275 | struct smu_context *smu = handle; |
| 276 | int ret = 0; |
| 277 | |
| 278 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { |
| 279 | dev_WARN(smu->adev->dev,printf("drm:pid%d:%s *WARNING* " "SMU uninitialized but power %s requested for %u!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate", block_type) |
| 280 | "SMU uninitialized but power %s requested for %u!\n",printf("drm:pid%d:%s *WARNING* " "SMU uninitialized but power %s requested for %u!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate", block_type) |
| 281 | gate ? "gate" : "ungate", block_type)printf("drm:pid%d:%s *WARNING* " "SMU uninitialized but power %s requested for %u!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate", block_type); |
| 282 | return -EOPNOTSUPP45; |
| 283 | } |
| 284 | |
| 285 | switch (block_type) { |
| 286 | /* |
| 287 | * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses |
| 288 | * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. |
| 289 | */ |
| 290 | case AMD_IP_BLOCK_TYPE_UVD: |
| 291 | case AMD_IP_BLOCK_TYPE_VCN: |
| 292 | ret = smu_dpm_set_vcn_enable(smu, !gate); |
| 293 | if (ret) |
| 294 | dev_err(smu->adev->dev, "Failed to power %s VCN!\n",printf("drm:pid%d:%s *ERROR* " "Failed to power %s VCN!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate") |
| 295 | gate ? "gate" : "ungate")printf("drm:pid%d:%s *ERROR* " "Failed to power %s VCN!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate"); |
| 296 | break; |
| 297 | case AMD_IP_BLOCK_TYPE_GFX: |
| 298 | ret = smu_gfx_off_control(smu, gate)((smu)->ppt_funcs ? ((smu)->ppt_funcs->gfx_off_control ? (smu)->ppt_funcs->gfx_off_control(smu, gate) : 0) : - 22); |
| 299 | if (ret) |
| 300 | dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",printf("drm:pid%d:%s *ERROR* " "Failed to %s gfxoff!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__ , gate ? "enable" : "disable") |
| 301 | gate ? "enable" : "disable")printf("drm:pid%d:%s *ERROR* " "Failed to %s gfxoff!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__ , gate ? "enable" : "disable"); |
| 302 | break; |
| 303 | case AMD_IP_BLOCK_TYPE_SDMA: |
| 304 | ret = smu_powergate_sdma(smu, gate)((smu)->ppt_funcs ? ((smu)->ppt_funcs->powergate_sdma ? (smu)->ppt_funcs->powergate_sdma(smu, gate) : 0) : - 22); |
| 305 | if (ret) |
| 306 | dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",printf("drm:pid%d:%s *ERROR* " "Failed to power %s SDMA!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate") |
| 307 | gate ? "gate" : "ungate")printf("drm:pid%d:%s *ERROR* " "Failed to power %s SDMA!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate"); |
| 308 | break; |
| 309 | case AMD_IP_BLOCK_TYPE_JPEG: |
| 310 | ret = smu_dpm_set_jpeg_enable(smu, !gate); |
| 311 | if (ret) |
| 312 | dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",printf("drm:pid%d:%s *ERROR* " "Failed to power %s JPEG!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate") |
| 313 | gate ? "gate" : "ungate")printf("drm:pid%d:%s *ERROR* " "Failed to power %s JPEG!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , gate ? "gate" : "ungate"); |
| 314 | break; |
| 315 | default: |
| 316 | dev_err(smu->adev->dev, "Unsupported block type!\n")printf("drm:pid%d:%s *ERROR* " "Unsupported block type!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 317 | return -EINVAL22; |
| 318 | } |
| 319 | |
| 320 | return ret; |
| 321 | } |
| 322 | |
| 323 | /** |
| 324 | * smu_set_user_clk_dependencies - set user profile clock dependencies |
| 325 | * |
| 326 | * @smu: smu_context pointer |
| 327 | * @clk: enum smu_clk_type type |
| 328 | * |
| 329 | * Enable/Disable the clock dependency for the @clk type. |
| 330 | */ |
| 331 | static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) |
| 332 | { |
| 333 | if (smu->adev->in_suspend) |
| 334 | return; |
| 335 | |
| 336 | if (clk == SMU_MCLK) { |
| 337 | smu->user_dpm_profile.clk_dependency = 0; |
| 338 | smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK)(1UL << (SMU_FCLK)) | BIT(SMU_SOCCLK)(1UL << (SMU_SOCCLK)); |
| 339 | } else if (clk == SMU_FCLK) { |
| 340 | /* MCLK takes precedence over FCLK */ |
| 341 | if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK)(1UL << (SMU_FCLK)) | BIT(SMU_SOCCLK)(1UL << (SMU_SOCCLK)))) |
| 342 | return; |
| 343 | |
| 344 | smu->user_dpm_profile.clk_dependency = 0; |
| 345 | smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK)(1UL << (SMU_MCLK)) | BIT(SMU_SOCCLK)(1UL << (SMU_SOCCLK)); |
| 346 | } else if (clk == SMU_SOCCLK) { |
| 347 | /* MCLK takes precedence over SOCCLK */ |
| 348 | if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK)(1UL << (SMU_FCLK)) | BIT(SMU_SOCCLK)(1UL << (SMU_SOCCLK)))) |
| 349 | return; |
| 350 | |
| 351 | smu->user_dpm_profile.clk_dependency = 0; |
| 352 | smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK)(1UL << (SMU_MCLK)) | BIT(SMU_FCLK)(1UL << (SMU_FCLK)); |
| 353 | } else |
| 354 | /* Add clk dependencies here, if any */ |
| 355 | return; |
| 356 | } |
| 357 | |
| 358 | /** |
| 359 | * smu_restore_dpm_user_profile - reinstate user dpm profile |
| 360 | * |
| 361 | * @smu: smu_context pointer |
| 362 | * |
| 363 | * Restore the saved user power configurations include power limit, |
| 364 | * clock frequencies, fan control mode and fan speed. |
| 365 | */ |
| 366 | static void smu_restore_dpm_user_profile(struct smu_context *smu) |
| 367 | { |
| 368 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); |
| 369 | int ret = 0; |
| 370 | |
| 371 | if (!smu->adev->in_suspend) |
| 372 | return; |
| 373 | |
| 374 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 375 | return; |
| 376 | |
| 377 | /* Enable restore flag */ |
| 378 | smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE(1 << 0); |
| 379 | |
| 380 | /* set the user dpm power limit */ |
| 381 | if (smu->user_dpm_profile.power_limit) { |
| 382 | ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); |
| 383 | if (ret) |
| 384 | dev_err(smu->adev->dev, "Failed to set power limit value\n")printf("drm:pid%d:%s *ERROR* " "Failed to set power limit value\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 385 | } |
| 386 | |
| 387 | /* set the user dpm clock configurations */ |
| 388 | if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { |
| 389 | enum smu_clk_type clk_type; |
| 390 | |
| 391 | for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { |
| 392 | /* |
| 393 | * Iterate over smu clk type and force the saved user clk |
| 394 | * configs, skip if clock dependency is enabled |
| 395 | */ |
| 396 | if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)(1UL << (clk_type))) && |
| 397 | smu->user_dpm_profile.clk_mask[clk_type]) { |
| 398 | ret = smu_force_smuclk_levels(smu, clk_type, |
| 399 | smu->user_dpm_profile.clk_mask[clk_type]); |
| 400 | if (ret) |
| 401 | dev_err(smu->adev->dev,printf("drm:pid%d:%s *ERROR* " "Failed to set clock type = %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , clk_type ) |
| 402 | "Failed to set clock type = %d\n", clk_type)printf("drm:pid%d:%s *ERROR* " "Failed to set clock type = %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , clk_type ); |
| 403 | } |
| 404 | } |
| 405 | } |
| 406 | |
| 407 | /* set the user dpm fan configurations */ |
| 408 | if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || |
| 409 | smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { |
| 410 | ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); |
| 411 | if (ret != -EOPNOTSUPP45) { |
| 412 | smu->user_dpm_profile.fan_speed_pwm = 0; |
| 413 | smu->user_dpm_profile.fan_speed_rpm = 0; |
| 414 | smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; |
| 415 | dev_err(smu->adev->dev, "Failed to set manual fan control mode\n")printf("drm:pid%d:%s *ERROR* " "Failed to set manual fan control mode\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 416 | } |
| 417 | |
| 418 | if (smu->user_dpm_profile.fan_speed_pwm) { |
| 419 | ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); |
| 420 | if (ret != -EOPNOTSUPP45) |
| 421 | dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n")printf("drm:pid%d:%s *ERROR* " "Failed to set manual fan speed in pwm\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 422 | } |
| 423 | |
| 424 | if (smu->user_dpm_profile.fan_speed_rpm) { |
| 425 | ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); |
| 426 | if (ret != -EOPNOTSUPP45) |
| 427 | dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n")printf("drm:pid%d:%s *ERROR* " "Failed to set manual fan speed in rpm\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 428 | } |
| 429 | } |
| 430 | |
| 431 | /* Restore user customized OD settings */ |
| 432 | if (smu->user_dpm_profile.user_od) { |
| 433 | if (smu->ppt_funcs->restore_user_od_settings) { |
| 434 | ret = smu->ppt_funcs->restore_user_od_settings(smu); |
| 435 | if (ret) |
| 436 | dev_err(smu->adev->dev, "Failed to upload customized OD settings\n")printf("drm:pid%d:%s *ERROR* " "Failed to upload customized OD settings\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 437 | } |
| 438 | } |
| 439 | |
| 440 | /* Disable restore flag */ |
| 441 | smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE(1 << 0); |
| 442 | } |
| 443 | |
| 444 | static int smu_get_power_num_states(void *handle, |
| 445 | struct pp_states_info *state_info) |
| 446 | { |
| 447 | if (!state_info) |
| 448 | return -EINVAL22; |
| 449 | |
| 450 | /* not support power state */ |
| 451 | memset(state_info, 0, sizeof(struct pp_states_info))__builtin_memset((state_info), (0), (sizeof(struct pp_states_info ))); |
| 452 | state_info->nums = 1; |
| 453 | state_info->states[0] = POWER_STATE_TYPE_DEFAULT; |
| 454 | |
| 455 | return 0; |
| 456 | } |
| 457 | |
| 458 | bool_Bool is_support_sw_smu(struct amdgpu_device *adev) |
| 459 | { |
| 460 | /* vega20 is 11.0.2, but it's supported via the powerplay code */ |
| 461 | if (adev->asic_type == CHIP_VEGA20) |
| 462 | return false0; |
| 463 | |
| 464 | if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)(((11) << 16) | ((0) << 8) | (0))) |
| 465 | return true1; |
| 466 | |
| 467 | return false0; |
| 468 | } |
| 469 | |
| 470 | bool_Bool is_support_cclk_dpm(struct amdgpu_device *adev) |
| 471 | { |
| 472 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 473 | |
| 474 | if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)((smu)->ppt_funcs ? ((smu)->ppt_funcs->feature_is_enabled ? (smu)->ppt_funcs->feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT ) : 0) : -22)) |
| 475 | return false0; |
| 476 | |
| 477 | return true1; |
| 478 | } |
| 479 | |
| 480 | |
| 481 | static int smu_sys_get_pp_table(void *handle, |
| 482 | char **table) |
| 483 | { |
| 484 | struct smu_context *smu = handle; |
| 485 | struct smu_table_context *smu_table = &smu->smu_table; |
| 486 | |
| 487 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 488 | return -EOPNOTSUPP45; |
| 489 | |
| 490 | if (!smu_table->power_play_table && !smu_table->hardcode_pptable) |
| 491 | return -EINVAL22; |
| 492 | |
| 493 | if (smu_table->hardcode_pptable) |
| 494 | *table = smu_table->hardcode_pptable; |
| 495 | else |
| 496 | *table = smu_table->power_play_table; |
| 497 | |
| 498 | return smu_table->power_play_table_size; |
| 499 | } |
| 500 | |
| 501 | static int smu_sys_set_pp_table(void *handle, |
| 502 | const char *buf, |
| 503 | size_t size) |
| 504 | { |
| 505 | struct smu_context *smu = handle; |
| 506 | struct smu_table_context *smu_table = &smu->smu_table; |
| 507 | ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; |
| 508 | int ret = 0; |
| 509 | |
| 510 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 511 | return -EOPNOTSUPP45; |
| 512 | |
| 513 | if (header->usStructureSize != size) { |
| 514 | dev_err(smu->adev->dev, "pp table size not matched !\n")printf("drm:pid%d:%s *ERROR* " "pp table size not matched !\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 515 | return -EIO5; |
| 516 | } |
| 517 | |
| 518 | if (!smu_table->hardcode_pptable) { |
| 519 | smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL(0x0001 | 0x0004)); |
| 520 | if (!smu_table->hardcode_pptable) |
| 521 | return -ENOMEM12; |
| 522 | } |
| 523 | |
| 524 | memcpy(smu_table->hardcode_pptable, buf, size)__builtin_memcpy((smu_table->hardcode_pptable), (buf), (size )); |
| 525 | smu_table->power_play_table = smu_table->hardcode_pptable; |
| 526 | smu_table->power_play_table_size = size; |
| 527 | |
| 528 | /* |
| 529 | * Special hw_fini action(for Navi1x, the DPMs disablement will be |
| 530 | * skipped) may be needed for custom pptable uploading. |
| 531 | */ |
| 532 | smu->uploading_custom_pp_table = true1; |
| 533 | |
| 534 | ret = smu_reset(smu); |
| 535 | if (ret) |
| 536 | dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret)do { } while(0); |
| 537 | |
| 538 | smu->uploading_custom_pp_table = false0; |
| 539 | |
| 540 | return ret; |
| 541 | } |
| 542 | |
| 543 | static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) |
| 544 | { |
| 545 | struct smu_feature *feature = &smu->smu_feature; |
| 546 | uint32_t allowed_feature_mask[SMU_FEATURE_MAX(64)/32]; |
| 547 | int ret = 0; |
| 548 | |
| 549 | /* |
| 550 | * With SCPM enabled, the allowed featuremasks setting(via |
| 551 | * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. |
| 552 | * That means there is no way to let PMFW knows the settings below. |
| 553 | * Thus, we just assume all the features are allowed under |
| 554 | * such scenario. |
| 555 | */ |
| 556 | if (smu->adev->scpm_enabled) { |
| 557 | bitmap_fill(feature->allowed, SMU_FEATURE_MAX(64)); |
| 558 | return 0; |
| 559 | } |
| 560 | |
| 561 | bitmap_zero(feature->allowed, SMU_FEATURE_MAX(64)); |
| 562 | |
| 563 | ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_allowed_feature_mask ? (smu)->ppt_funcs->get_allowed_feature_mask(smu, allowed_feature_mask , (64)/32) : 0) : -22) |
| 564 | SMU_FEATURE_MAX/32)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_allowed_feature_mask ? (smu)->ppt_funcs->get_allowed_feature_mask(smu, allowed_feature_mask , (64)/32) : 0) : -22); |
| 565 | if (ret) |
| 566 | return ret; |
| 567 | |
| 568 | bitmap_or(feature->allowed, feature->allowed, |
| 569 | (unsigned long *)allowed_feature_mask, |
| 570 | feature->feature_num); |
| 571 | |
| 572 | return ret; |
| 573 | } |
| 574 | |
| 575 | static int smu_set_funcs(struct amdgpu_device *adev) |
| 576 | { |
| 577 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 578 | |
| 579 | if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) |
| 580 | smu->od_enabled = true1; |
| 581 | |
| 582 | switch (adev->ip_versions[MP1_HWIP][0]) { |
| 583 | case IP_VERSION(11, 0, 0)(((11) << 16) | ((0) << 8) | (0)): |
| 584 | case IP_VERSION(11, 0, 5)(((11) << 16) | ((0) << 8) | (5)): |
| 585 | case IP_VERSION(11, 0, 9)(((11) << 16) | ((0) << 8) | (9)): |
| 586 | navi10_set_ppt_funcs(smu); |
| 587 | break; |
| 588 | case IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7)): |
| 589 | case IP_VERSION(11, 0, 11)(((11) << 16) | ((0) << 8) | (11)): |
| 590 | case IP_VERSION(11, 0, 12)(((11) << 16) | ((0) << 8) | (12)): |
| 591 | case IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13)): |
| 592 | sienna_cichlid_set_ppt_funcs(smu); |
| 593 | break; |
| 594 | case IP_VERSION(12, 0, 0)(((12) << 16) | ((0) << 8) | (0)): |
| 595 | case IP_VERSION(12, 0, 1)(((12) << 16) | ((0) << 8) | (1)): |
| 596 | renoir_set_ppt_funcs(smu); |
| 597 | break; |
| 598 | case IP_VERSION(11, 5, 0)(((11) << 16) | ((5) << 8) | (0)): |
| 599 | vangogh_set_ppt_funcs(smu); |
| 600 | break; |
| 601 | case IP_VERSION(13, 0, 1)(((13) << 16) | ((0) << 8) | (1)): |
| 602 | case IP_VERSION(13, 0, 3)(((13) << 16) | ((0) << 8) | (3)): |
| 603 | case IP_VERSION(13, 0, 8)(((13) << 16) | ((0) << 8) | (8)): |
| 604 | yellow_carp_set_ppt_funcs(smu); |
| 605 | break; |
| 606 | case IP_VERSION(13, 0, 4)(((13) << 16) | ((0) << 8) | (4)): |
| 607 | case IP_VERSION(13, 0, 11)(((13) << 16) | ((0) << 8) | (11)): |
| 608 | smu_v13_0_4_set_ppt_funcs(smu); |
| 609 | break; |
| 610 | case IP_VERSION(13, 0, 5)(((13) << 16) | ((0) << 8) | (5)): |
| 611 | smu_v13_0_5_set_ppt_funcs(smu); |
| 612 | break; |
| 613 | case IP_VERSION(11, 0, 8)(((11) << 16) | ((0) << 8) | (8)): |
| 614 | cyan_skillfish_set_ppt_funcs(smu); |
| 615 | break; |
| 616 | case IP_VERSION(11, 0, 2)(((11) << 16) | ((0) << 8) | (2)): |
| 617 | adev->pm.pp_feature &= ~PP_GFXOFF_MASK; |
| 618 | arcturus_set_ppt_funcs(smu); |
| 619 | /* OD is not supported on Arcturus */ |
| 620 | smu->od_enabled =false0; |
| 621 | break; |
| 622 | case IP_VERSION(13, 0, 2)(((13) << 16) | ((0) << 8) | (2)): |
| 623 | aldebaran_set_ppt_funcs(smu); |
| 624 | /* Enable pp_od_clk_voltage node */ |
| 625 | smu->od_enabled = true1; |
| 626 | break; |
| 627 | case IP_VERSION(13, 0, 0)(((13) << 16) | ((0) << 8) | (0)): |
| 628 | case IP_VERSION(13, 0, 10)(((13) << 16) | ((0) << 8) | (10)): |
| 629 | smu_v13_0_0_set_ppt_funcs(smu); |
| 630 | break; |
| 631 | case IP_VERSION(13, 0, 7)(((13) << 16) | ((0) << 8) | (7)): |
| 632 | smu_v13_0_7_set_ppt_funcs(smu); |
| 633 | break; |
| 634 | default: |
| 635 | return -EINVAL22; |
| 636 | } |
| 637 | |
| 638 | return 0; |
| 639 | } |
| 640 | |
| 641 | static int smu_early_init(void *handle) |
| 642 | { |
| 643 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 644 | struct smu_context *smu; |
| 645 | |
| 646 | smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL(0x0001 | 0x0004)); |
| 647 | if (!smu) |
| 648 | return -ENOMEM12; |
| 649 | |
| 650 | smu->adev = adev; |
| 651 | smu->pm_enabled = !!amdgpu_dpm; |
| 652 | smu->is_apu = false0; |
| 653 | smu->smu_baco.state = SMU_BACO_STATE_EXIT; |
| 654 | smu->smu_baco.platform_support = false0; |
| 655 | smu->user_dpm_profile.fan_mode = -1; |
| 656 | |
| 657 | rw_init(&smu->message_lock, "smuml")_rw_init_flags(&smu->message_lock, "smuml", 0, ((void * )0)); |
| 658 | |
| 659 | adev->powerplay.pp_handle = smu; |
| 660 | adev->powerplay.pp_funcs = &swsmu_pm_funcs; |
| 661 | |
| 662 | return smu_set_funcs(adev); |
| 663 | } |
| 664 | |
| 665 | static int smu_set_default_dpm_table(struct smu_context *smu) |
| 666 | { |
| 667 | struct smu_power_context *smu_power = &smu->smu_power; |
| 668 | struct smu_power_gate *power_gate = &smu_power->power_gate; |
| 669 | int vcn_gate, jpeg_gate; |
| 670 | int ret = 0; |
| 671 | |
| 672 | if (!smu->ppt_funcs->set_default_dpm_table) |
| 673 | return 0; |
| 674 | |
| 675 | vcn_gate = atomic_read(&power_gate->vcn_gated)({ typeof(*(&power_gate->vcn_gated)) __tmp = *(volatile typeof(*(&power_gate->vcn_gated)) *)&(*(&power_gate ->vcn_gated)); membar_datadep_consumer(); __tmp; }); |
| 676 | jpeg_gate = atomic_read(&power_gate->jpeg_gated)({ typeof(*(&power_gate->jpeg_gated)) __tmp = *(volatile typeof(*(&power_gate->jpeg_gated)) *)&(*(&power_gate ->jpeg_gated)); membar_datadep_consumer(); __tmp; }); |
| 677 | |
| 678 | ret = smu_dpm_set_vcn_enable(smu, true1); |
| 679 | if (ret) |
| 680 | return ret; |
| 681 | |
| 682 | ret = smu_dpm_set_jpeg_enable(smu, true1); |
| 683 | if (ret) |
| 684 | goto err_out; |
| 685 | |
| 686 | ret = smu->ppt_funcs->set_default_dpm_table(smu); |
| 687 | if (ret) |
| 688 | dev_err(smu->adev->dev,printf("drm:pid%d:%s *ERROR* " "Failed to setup default dpm clock tables!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 689 | "Failed to setup default dpm clock tables!\n")printf("drm:pid%d:%s *ERROR* " "Failed to setup default dpm clock tables!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 690 | |
| 691 | smu_dpm_set_jpeg_enable(smu, !jpeg_gate); |
| 692 | err_out: |
| 693 | smu_dpm_set_vcn_enable(smu, !vcn_gate); |
| 694 | return ret; |
| 695 | } |
| 696 | |
| 697 | static int smu_apply_default_config_table_settings(struct smu_context *smu) |
| 698 | { |
| 699 | struct amdgpu_device *adev = smu->adev; |
| 700 | int ret = 0; |
| 701 | |
| 702 | ret = smu_get_default_config_table_settings(smu,((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_default_config_table_settings ? (smu)->ppt_funcs->get_default_config_table_settings( smu, &adev->pm.config_table) : -45) : -22) |
| 703 | &adev->pm.config_table)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_default_config_table_settings ? (smu)->ppt_funcs->get_default_config_table_settings( smu, &adev->pm.config_table) : -45) : -22); |
| 704 | if (ret) |
| 705 | return ret; |
| 706 | |
| 707 | return smu_set_config_table(smu, &adev->pm.config_table)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_config_table ? (smu)->ppt_funcs->set_config_table(smu, &adev-> pm.config_table) : -45) : -22); |
| 708 | } |
| 709 | |
| 710 | static int smu_late_init(void *handle) |
| 711 | { |
| 712 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 713 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 714 | int ret = 0; |
| 715 | |
| 716 | smu_set_fine_grain_gfx_freq_parameters(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_fine_grain_gfx_freq_parameters ? (smu)->ppt_funcs->set_fine_grain_gfx_freq_parameters (smu) : 0) : -22); |
| 717 | |
| 718 | if (!smu->pm_enabled) |
| 719 | return 0; |
| 720 | |
| 721 | ret = smu_post_init(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->post_init ? ( smu)->ppt_funcs->post_init(smu) : 0) : -22); |
| 722 | if (ret) { |
| 723 | dev_err(adev->dev, "Failed to post smu init!\n")printf("drm:pid%d:%s *ERROR* " "Failed to post smu init!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 724 | return ret; |
| 725 | } |
| 726 | |
| 727 | /* |
| 728 | * Explicitly notify PMFW the power mode the system in. Since |
| 729 | * the PMFW may boot the ASIC with a different mode. |
| 730 | * For those supporting ACDC switch via gpio, PMFW will |
| 731 | * handle the switch automatically. Driver involvement |
| 732 | * is unnecessary. |
| 733 | */ |
| 734 | if (!smu->dc_controlled_by_gpio) { |
| 735 | ret = smu_set_power_source(smu,((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_power_source ? (smu)->ppt_funcs->set_power_source(smu, adev->pm. ac_power ? SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC) : 0) : - 22) |
| 736 | adev->pm.ac_power ? SMU_POWER_SOURCE_AC :((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_power_source ? (smu)->ppt_funcs->set_power_source(smu, adev->pm. ac_power ? SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC) : 0) : - 22) |
| 737 | SMU_POWER_SOURCE_DC)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_power_source ? (smu)->ppt_funcs->set_power_source(smu, adev->pm. ac_power ? SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC) : 0) : - 22); |
| 738 | if (ret) { |
| 739 | dev_err(adev->dev, "Failed to switch to %s mode!\n",printf("drm:pid%d:%s *ERROR* " "Failed to switch to %s mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> pm.ac_power ? "AC" : "DC") |
| 740 | adev->pm.ac_power ? "AC" : "DC")printf("drm:pid%d:%s *ERROR* " "Failed to switch to %s mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> pm.ac_power ? "AC" : "DC"); |
| 741 | return ret; |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)(((13) << 16) | ((0) << 8) | (1))) || |
| 746 | (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)(((13) << 16) | ((0) << 8) | (3)))) |
| 747 | return 0; |
| 748 | |
| 749 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) || smu->od_enabled) { |
| 750 | ret = smu_set_default_od_settings(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings(smu) : 0) : -22); |
| 751 | if (ret) { |
| 752 | dev_err(adev->dev, "Failed to setup default OD settings!\n")printf("drm:pid%d:%s *ERROR* " "Failed to setup default OD settings!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 753 | return ret; |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | ret = smu_populate_umd_state_clk(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk(smu) : 0) : -22); |
| 758 | if (ret) { |
| 759 | dev_err(adev->dev, "Failed to populate UMD state clocks!\n")printf("drm:pid%d:%s *ERROR* " "Failed to populate UMD state clocks!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 760 | return ret; |
| 761 | } |
| 762 | |
| 763 | ret = smu_get_asic_power_limits(smu,((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit(smu, &smu-> current_power_limit, &smu->default_power_limit, &smu ->max_power_limit) : 0) : -22) |
| 764 | &smu->current_power_limit,((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit(smu, &smu-> current_power_limit, &smu->default_power_limit, &smu ->max_power_limit) : 0) : -22) |
| 765 | &smu->default_power_limit,((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit(smu, &smu-> current_power_limit, &smu->default_power_limit, &smu ->max_power_limit) : 0) : -22) |
| 766 | &smu->max_power_limit)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit(smu, &smu-> current_power_limit, &smu->default_power_limit, &smu ->max_power_limit) : 0) : -22); |
| 767 | if (ret) { |
| 768 | dev_err(adev->dev, "Failed to get asic power limits!\n")printf("drm:pid%d:%s *ERROR* " "Failed to get asic power limits!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 769 | return ret; |
| 770 | } |
| 771 | |
| 772 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) |
| 773 | smu_get_unique_id(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_unique_id ? (smu)->ppt_funcs->get_unique_id(smu) : 0) : -22); |
| 774 | |
| 775 | smu_get_fan_parameters(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_fan_parameters ? (smu)->ppt_funcs->get_fan_parameters(smu) : 0) : -22 ); |
| 776 | |
| 777 | smu_handle_task(smu, |
| 778 | smu->smu_dpm.dpm_level, |
| 779 | AMD_PP_TASK_COMPLETE_INIT); |
| 780 | |
| 781 | ret = smu_apply_default_config_table_settings(smu); |
| 782 | if (ret && (ret != -EOPNOTSUPP45)) { |
| 783 | dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n")printf("drm:pid%d:%s *ERROR* " "Failed to apply default DriverSmuConfig settings!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 784 | return ret; |
| 785 | } |
| 786 | |
| 787 | smu_restore_dpm_user_profile(smu); |
| 788 | |
| 789 | return 0; |
| 790 | } |
| 791 | |
| 792 | static int smu_init_fb_allocations(struct smu_context *smu) |
| 793 | { |
| 794 | struct amdgpu_device *adev = smu->adev; |
| 795 | struct smu_table_context *smu_table = &smu->smu_table; |
| 796 | struct smu_table *tables = smu_table->tables; |
| 797 | struct smu_table *driver_table = &(smu_table->driver_table); |
| 798 | uint32_t max_table_size = 0; |
| 799 | int ret, i; |
| 800 | |
| 801 | /* VRAM allocation for tool table */ |
| 802 | if (tables[SMU_TABLE_PMSTATUSLOG].size) { |
| 803 | ret = amdgpu_bo_create_kernel(adev, |
| 804 | tables[SMU_TABLE_PMSTATUSLOG].size, |
| 805 | tables[SMU_TABLE_PMSTATUSLOG].align, |
| 806 | tables[SMU_TABLE_PMSTATUSLOG].domain, |
| 807 | &tables[SMU_TABLE_PMSTATUSLOG].bo, |
| 808 | &tables[SMU_TABLE_PMSTATUSLOG].mc_address, |
| 809 | &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); |
| 810 | if (ret) { |
| 811 | dev_err(adev->dev, "VRAM allocation for tool table failed!\n")printf("drm:pid%d:%s *ERROR* " "VRAM allocation for tool table failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 812 | return ret; |
| 813 | } |
| 814 | } |
| 815 | |
| 816 | /* VRAM allocation for driver table */ |
| 817 | for (i = 0; i < SMU_TABLE_COUNT; i++) { |
| 818 | if (tables[i].size == 0) |
| 819 | continue; |
| 820 | |
| 821 | if (i == SMU_TABLE_PMSTATUSLOG) |
| 822 | continue; |
| 823 | |
| 824 | if (max_table_size < tables[i].size) |
| 825 | max_table_size = tables[i].size; |
| 826 | } |
| 827 | |
| 828 | driver_table->size = max_table_size; |
| 829 | driver_table->align = PAGE_SIZE(1 << 12); |
| 830 | driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM0x4; |
| 831 | |
| 832 | ret = amdgpu_bo_create_kernel(adev, |
| 833 | driver_table->size, |
| 834 | driver_table->align, |
| 835 | driver_table->domain, |
| 836 | &driver_table->bo, |
| 837 | &driver_table->mc_address, |
| 838 | &driver_table->cpu_addr); |
| 839 | if (ret) { |
| 840 | dev_err(adev->dev, "VRAM allocation for driver table failed!\n")printf("drm:pid%d:%s *ERROR* " "VRAM allocation for driver table failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 841 | if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) |
| 842 | amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, |
| 843 | &tables[SMU_TABLE_PMSTATUSLOG].mc_address, |
| 844 | &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); |
| 845 | } |
| 846 | |
| 847 | return ret; |
| 848 | } |
| 849 | |
| 850 | static int smu_fini_fb_allocations(struct smu_context *smu) |
| 851 | { |
| 852 | struct smu_table_context *smu_table = &smu->smu_table; |
| 853 | struct smu_table *tables = smu_table->tables; |
| 854 | struct smu_table *driver_table = &(smu_table->driver_table); |
| 855 | |
| 856 | if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) |
| 857 | amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, |
| 858 | &tables[SMU_TABLE_PMSTATUSLOG].mc_address, |
| 859 | &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); |
| 860 | |
| 861 | amdgpu_bo_free_kernel(&driver_table->bo, |
| 862 | &driver_table->mc_address, |
| 863 | &driver_table->cpu_addr); |
| 864 | |
| 865 | return 0; |
| 866 | } |
| 867 | |
| 868 | /** |
| 869 | * smu_alloc_memory_pool - allocate memory pool in the system memory |
| 870 | * |
| 871 | * @smu: amdgpu_device pointer |
| 872 | * |
| 873 | * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr |
| 874 | * and DramLogSetDramAddr can notify it changed. |
| 875 | * |
| 876 | * Returns 0 on success, error on failure. |
| 877 | */ |
| 878 | static int smu_alloc_memory_pool(struct smu_context *smu) |
| 879 | { |
| 880 | struct amdgpu_device *adev = smu->adev; |
| 881 | struct smu_table_context *smu_table = &smu->smu_table; |
| 882 | struct smu_table *memory_pool = &smu_table->memory_pool; |
| 883 | uint64_t pool_size = smu->pool_size; |
| 884 | int ret = 0; |
| 885 | |
| 886 | if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) |
| 887 | return ret; |
| 888 | |
| 889 | memory_pool->size = pool_size; |
| 890 | memory_pool->align = PAGE_SIZE(1 << 12); |
| 891 | memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT0x2; |
| 892 | |
| 893 | switch (pool_size) { |
| 894 | case SMU_MEMORY_POOL_SIZE_256_MB: |
| 895 | case SMU_MEMORY_POOL_SIZE_512_MB: |
| 896 | case SMU_MEMORY_POOL_SIZE_1_GB: |
| 897 | case SMU_MEMORY_POOL_SIZE_2_GB: |
| 898 | ret = amdgpu_bo_create_kernel(adev, |
| 899 | memory_pool->size, |
| 900 | memory_pool->align, |
| 901 | memory_pool->domain, |
| 902 | &memory_pool->bo, |
| 903 | &memory_pool->mc_address, |
| 904 | &memory_pool->cpu_addr); |
| 905 | if (ret) |
| 906 | dev_err(adev->dev, "VRAM allocation for dramlog failed!\n")printf("drm:pid%d:%s *ERROR* " "VRAM allocation for dramlog failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 907 | break; |
| 908 | default: |
| 909 | break; |
| 910 | } |
| 911 | |
| 912 | return ret; |
| 913 | } |
| 914 | |
| 915 | static int smu_free_memory_pool(struct smu_context *smu) |
| 916 | { |
| 917 | struct smu_table_context *smu_table = &smu->smu_table; |
| 918 | struct smu_table *memory_pool = &smu_table->memory_pool; |
| 919 | |
| 920 | if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) |
| 921 | return 0; |
| 922 | |
| 923 | amdgpu_bo_free_kernel(&memory_pool->bo, |
| 924 | &memory_pool->mc_address, |
| 925 | &memory_pool->cpu_addr); |
| 926 | |
| 927 | memset(memory_pool, 0, sizeof(struct smu_table))__builtin_memset((memory_pool), (0), (sizeof(struct smu_table ))); |
| 928 | |
| 929 | return 0; |
| 930 | } |
| 931 | |
| 932 | static int smu_alloc_dummy_read_table(struct smu_context *smu) |
| 933 | { |
| 934 | struct smu_table_context *smu_table = &smu->smu_table; |
| 935 | struct smu_table *dummy_read_1_table = |
| 936 | &smu_table->dummy_read_1_table; |
| 937 | struct amdgpu_device *adev = smu->adev; |
| 938 | int ret = 0; |
| 939 | |
| 940 | dummy_read_1_table->size = 0x40000; |
| 941 | dummy_read_1_table->align = PAGE_SIZE(1 << 12); |
| 942 | dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM0x4; |
| 943 | |
| 944 | ret = amdgpu_bo_create_kernel(adev, |
| 945 | dummy_read_1_table->size, |
| 946 | dummy_read_1_table->align, |
| 947 | dummy_read_1_table->domain, |
| 948 | &dummy_read_1_table->bo, |
| 949 | &dummy_read_1_table->mc_address, |
| 950 | &dummy_read_1_table->cpu_addr); |
| 951 | if (ret) |
| 952 | dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n")printf("drm:pid%d:%s *ERROR* " "VRAM allocation for dummy read table failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 953 | |
| 954 | return ret; |
| 955 | } |
| 956 | |
| 957 | static void smu_free_dummy_read_table(struct smu_context *smu) |
| 958 | { |
| 959 | struct smu_table_context *smu_table = &smu->smu_table; |
| 960 | struct smu_table *dummy_read_1_table = |
| 961 | &smu_table->dummy_read_1_table; |
| 962 | |
| 963 | |
| 964 | amdgpu_bo_free_kernel(&dummy_read_1_table->bo, |
| 965 | &dummy_read_1_table->mc_address, |
| 966 | &dummy_read_1_table->cpu_addr); |
| 967 | |
| 968 | memset(dummy_read_1_table, 0, sizeof(struct smu_table))__builtin_memset((dummy_read_1_table), (0), (sizeof(struct smu_table ))); |
| 969 | } |
| 970 | |
| 971 | static int smu_smc_table_sw_init(struct smu_context *smu) |
| 972 | { |
| 973 | int ret; |
| 974 | |
| 975 | /** |
| 976 | * Create smu_table structure, and init smc tables such as |
| 977 | * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. |
| 978 | */ |
| 979 | ret = smu_init_smc_tables(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->init_smc_tables ? (smu)->ppt_funcs->init_smc_tables(smu) : 0) : -22); |
| 980 | if (ret) { |
| 981 | dev_err(smu->adev->dev, "Failed to init smc tables!\n")printf("drm:pid%d:%s *ERROR* " "Failed to init smc tables!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 982 | return ret; |
| 983 | } |
| 984 | |
| 985 | /** |
| 986 | * Create smu_power_context structure, and allocate smu_dpm_context and |
| 987 | * context size to fill the smu_power_context data. |
| 988 | */ |
| 989 | ret = smu_init_power(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->init_power ? ( smu)->ppt_funcs->init_power(smu) : 0) : -22); |
| 990 | if (ret) { |
| 991 | dev_err(smu->adev->dev, "Failed to init smu_init_power!\n")printf("drm:pid%d:%s *ERROR* " "Failed to init smu_init_power!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 992 | return ret; |
| 993 | } |
| 994 | |
| 995 | /* |
| 996 | * allocate vram bos to store smc table contents. |
| 997 | */ |
| 998 | ret = smu_init_fb_allocations(smu); |
| 999 | if (ret) |
| 1000 | return ret; |
| 1001 | |
| 1002 | ret = smu_alloc_memory_pool(smu); |
| 1003 | if (ret) |
| 1004 | return ret; |
| 1005 | |
| 1006 | ret = smu_alloc_dummy_read_table(smu); |
| 1007 | if (ret) |
| 1008 | return ret; |
| 1009 | |
| 1010 | ret = smu_i2c_init(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->i2c_init ? (smu )->ppt_funcs->i2c_init(smu) : 0) : -22); |
| 1011 | if (ret) |
| 1012 | return ret; |
| 1013 | |
| 1014 | return 0; |
| 1015 | } |
| 1016 | |
| 1017 | static int smu_smc_table_sw_fini(struct smu_context *smu) |
| 1018 | { |
| 1019 | int ret; |
| 1020 | |
| 1021 | smu_i2c_fini(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->i2c_fini ? (smu )->ppt_funcs->i2c_fini(smu) : 0) : -22); |
| 1022 | |
| 1023 | smu_free_dummy_read_table(smu); |
| 1024 | |
| 1025 | ret = smu_free_memory_pool(smu); |
| 1026 | if (ret) |
| 1027 | return ret; |
| 1028 | |
| 1029 | ret = smu_fini_fb_allocations(smu); |
| 1030 | if (ret) |
| 1031 | return ret; |
| 1032 | |
| 1033 | ret = smu_fini_power(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->fini_power ? ( smu)->ppt_funcs->fini_power(smu) : 0) : -22); |
| 1034 | if (ret) { |
| 1035 | dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n")printf("drm:pid%d:%s *ERROR* " "Failed to init smu_fini_power!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1036 | return ret; |
| 1037 | } |
| 1038 | |
| 1039 | ret = smu_fini_smc_tables(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->fini_smc_tables ? (smu)->ppt_funcs->fini_smc_tables(smu) : 0) : -22); |
| 1040 | if (ret) { |
| 1041 | dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n")printf("drm:pid%d:%s *ERROR* " "Failed to smu_fini_smc_tables!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1042 | return ret; |
| 1043 | } |
| 1044 | |
| 1045 | return 0; |
| 1046 | } |
| 1047 | |
| 1048 | static void smu_throttling_logging_work_fn(struct work_struct *work) |
| 1049 | { |
| 1050 | struct smu_context *smu = container_of(work, struct smu_context,({ const __typeof( ((struct smu_context *)0)->throttling_logging_work ) *__mptr = (work); (struct smu_context *)( (char *)__mptr - __builtin_offsetof(struct smu_context, throttling_logging_work ) );}) |
| 1051 | throttling_logging_work)({ const __typeof( ((struct smu_context *)0)->throttling_logging_work ) *__mptr = (work); (struct smu_context *)( (char *)__mptr - __builtin_offsetof(struct smu_context, throttling_logging_work ) );}); |
| 1052 | |
| 1053 | smu_log_thermal_throttling(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->log_thermal_throttling_event ? (smu)->ppt_funcs->log_thermal_throttling_event(smu) : 0) : -22); |
| 1054 | } |
| 1055 | |
| 1056 | static void smu_interrupt_work_fn(struct work_struct *work) |
| 1057 | { |
| 1058 | struct smu_context *smu = container_of(work, struct smu_context,({ const __typeof( ((struct smu_context *)0)->interrupt_work ) *__mptr = (work); (struct smu_context *)( (char *)__mptr - __builtin_offsetof(struct smu_context, interrupt_work) );}) |
| 1059 | interrupt_work)({ const __typeof( ((struct smu_context *)0)->interrupt_work ) *__mptr = (work); (struct smu_context *)( (char *)__mptr - __builtin_offsetof(struct smu_context, interrupt_work) );}); |
| 1060 | |
| 1061 | if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) |
| 1062 | smu->ppt_funcs->interrupt_work(smu); |
| 1063 | } |
| 1064 | |
| 1065 | static void smu_swctf_delayed_work_handler(struct work_struct *work) |
| 1066 | { |
| 1067 | struct smu_context *smu = |
| 1068 | container_of(work, struct smu_context, swctf_delayed_work.work)({ const __typeof( ((struct smu_context *)0)->swctf_delayed_work .work ) *__mptr = (work); (struct smu_context *)( (char *)__mptr - __builtin_offsetof(struct smu_context, swctf_delayed_work. work) );}); |
| 1069 | struct smu_temperature_range *range = |
| 1070 | &smu->thermal_range; |
| 1071 | struct amdgpu_device *adev = smu->adev; |
| 1072 | uint32_t hotspot_tmp, size; |
| 1073 | |
| 1074 | /* |
| 1075 | * If the hotspot temperature is confirmed as below SW CTF setting point |
| 1076 | * after the delay enforced, nothing will be done. |
| 1077 | * Otherwise, a graceful shutdown will be performed to prevent further damage. |
| 1078 | */ |
| 1079 | if (range->software_shutdown_temp && |
| 1080 | smu->ppt_funcs->read_sensor && |
| 1081 | !smu->ppt_funcs->read_sensor(smu, |
| 1082 | AMDGPU_PP_SENSOR_HOTSPOT_TEMP, |
| 1083 | &hotspot_tmp, |
| 1084 | &size) && |
| 1085 | hotspot_tmp / 1000 < range->software_shutdown_temp) |
| 1086 | return; |
| 1087 | |
| 1088 | dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: GPU over temperature range(SW CTF) detected!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1089 | dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: System is going to shutdown due to GPU SW CTF!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1090 | orderly_poweroff(true1); |
| 1091 | } |
| 1092 | |
| 1093 | static int smu_sw_init(void *handle) |
| 1094 | { |
| 1095 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1096 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 1097 | int ret; |
| 1098 | |
| 1099 | smu->pool_size = adev->pm.smu_prv_buffer_size; |
| 1100 | smu->smu_feature.feature_num = SMU_FEATURE_MAX(64); |
| 1101 | bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX(64)); |
| 1102 | bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX(64)); |
| 1103 | |
| 1104 | INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); |
| 1105 | INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); |
| 1106 | atomic64_set(&smu->throttle_int_counter, 0)({ typeof(*(&smu->throttle_int_counter)) __tmp = ((0)) ; *(volatile typeof(*(&smu->throttle_int_counter)) *)& (*(&smu->throttle_int_counter)) = __tmp; __tmp; }); |
| 1107 | smu->watermarks_bitmap = 0; |
| 1108 | smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; |
| 1109 | smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; |
| 1110 | |
| 1111 | atomic_set(&smu->smu_power.power_gate.vcn_gated, 1)({ typeof(*(&smu->smu_power.power_gate.vcn_gated)) __tmp = ((1)); *(volatile typeof(*(&smu->smu_power.power_gate .vcn_gated)) *)&(*(&smu->smu_power.power_gate.vcn_gated )) = __tmp; __tmp; }); |
| 1112 | atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1)({ typeof(*(&smu->smu_power.power_gate.jpeg_gated)) __tmp = ((1)); *(volatile typeof(*(&smu->smu_power.power_gate .jpeg_gated)) *)&(*(&smu->smu_power.power_gate.jpeg_gated )) = __tmp; __tmp; }); |
| 1113 | |
| 1114 | smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; |
| 1115 | smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; |
| 1116 | smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; |
| 1117 | smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; |
| 1118 | smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; |
| 1119 | smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; |
| 1120 | smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; |
| 1121 | smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; |
| 1122 | |
| 1123 | smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; |
| 1124 | smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; |
| 1125 | smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; |
| 1126 | smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; |
| 1127 | smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; |
| 1128 | smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; |
| 1129 | smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; |
| 1130 | smu->display_config = &adev->pm.pm_display_cfg; |
| 1131 | |
| 1132 | smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; |
| 1133 | smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; |
| 1134 | |
| 1135 | ret = smu_init_microcode(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->init_microcode ? (smu)->ppt_funcs->init_microcode(smu) : 0) : -22); |
| 1136 | if (ret) { |
| 1137 | dev_err(adev->dev, "Failed to load smu firmware!\n")printf("drm:pid%d:%s *ERROR* " "Failed to load smu firmware!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1138 | return ret; |
| 1139 | } |
| 1140 | |
| 1141 | INIT_DELAYED_WORK(&smu->swctf_delayed_work, |
| 1142 | smu_swctf_delayed_work_handler); |
| 1143 | |
| 1144 | ret = smu_smc_table_sw_init(smu); |
| 1145 | if (ret) { |
| 1146 | dev_err(adev->dev, "Failed to sw init smc table!\n")printf("drm:pid%d:%s *ERROR* " "Failed to sw init smc table!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1147 | return ret; |
| 1148 | } |
| 1149 | |
| 1150 | /* get boot_values from vbios to set revision, gfxclk, and etc. */ |
| 1151 | ret = smu_get_vbios_bootup_values(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_vbios_bootup_values ? (smu)->ppt_funcs->get_vbios_bootup_values(smu) : 0) : -22); |
| 1152 | if (ret) { |
| 1153 | dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n")printf("drm:pid%d:%s *ERROR* " "Failed to get VBIOS boot clock values!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1154 | return ret; |
| 1155 | } |
| 1156 | |
| 1157 | ret = smu_init_pptable_microcode(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->init_pptable_microcode ? (smu)->ppt_funcs->init_pptable_microcode(smu) : 0) : -22); |
| 1158 | if (ret) { |
| 1159 | dev_err(adev->dev, "Failed to setup pptable firmware!\n")printf("drm:pid%d:%s *ERROR* " "Failed to setup pptable firmware!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1160 | return ret; |
| 1161 | } |
| 1162 | |
| 1163 | ret = smu_register_irq_handler(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->register_irq_handler ? (smu)->ppt_funcs->register_irq_handler(smu) : 0) : - 22); |
| 1164 | if (ret) { |
| 1165 | dev_err(adev->dev, "Failed to register smc irq handler!\n")printf("drm:pid%d:%s *ERROR* " "Failed to register smc irq handler!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1166 | return ret; |
| 1167 | } |
| 1168 | |
| 1169 | /* If there is no way to query fan control mode, fan control is not supported */ |
| 1170 | if (!smu->ppt_funcs->get_fan_control_mode) |
| 1171 | smu->adev->pm.no_fan = true1; |
| 1172 | |
| 1173 | return 0; |
| 1174 | } |
| 1175 | |
| 1176 | static int smu_sw_fini(void *handle) |
| 1177 | { |
| 1178 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1179 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 1180 | int ret; |
| 1181 | |
| 1182 | ret = smu_smc_table_sw_fini(smu); |
| 1183 | if (ret) { |
| 1184 | dev_err(adev->dev, "Failed to sw fini smc table!\n")printf("drm:pid%d:%s *ERROR* " "Failed to sw fini smc table!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1185 | return ret; |
| 1186 | } |
| 1187 | |
| 1188 | smu_fini_microcode(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->fini_microcode ? (smu)->ppt_funcs->fini_microcode(smu) : 0) : -22); |
| 1189 | |
| 1190 | return 0; |
| 1191 | } |
| 1192 | |
| 1193 | static int smu_get_thermal_temperature_range(struct smu_context *smu) |
| 1194 | { |
| 1195 | struct amdgpu_device *adev = smu->adev; |
| 1196 | struct smu_temperature_range *range = |
| 1197 | &smu->thermal_range; |
| 1198 | int ret = 0; |
| 1199 | |
| 1200 | if (!smu->ppt_funcs->get_thermal_temperature_range) |
| 1201 | return 0; |
| 1202 | |
| 1203 | ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); |
| 1204 | if (ret) |
| 1205 | return ret; |
| 1206 | |
| 1207 | adev->pm.dpm.thermal.min_temp = range->min; |
| 1208 | adev->pm.dpm.thermal.max_temp = range->max; |
| 1209 | adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; |
| 1210 | adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; |
| 1211 | adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; |
| 1212 | adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; |
| 1213 | adev->pm.dpm.thermal.min_mem_temp = range->mem_min; |
| 1214 | adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; |
| 1215 | adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; |
| 1216 | |
| 1217 | return ret; |
| 1218 | } |
| 1219 | |
| 1220 | static int smu_smc_hw_setup(struct smu_context *smu) |
| 1221 | { |
| 1222 | struct smu_feature *feature = &smu->smu_feature; |
| 1223 | struct amdgpu_device *adev = smu->adev; |
| 1224 | uint8_t pcie_gen = 0, pcie_width = 0; |
| 1225 | uint64_t features_supported; |
| 1226 | int ret = 0; |
| 1227 | |
| 1228 | switch (adev->ip_versions[MP1_HWIP][0]) { |
| 1229 | case IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7)): |
| 1230 | case IP_VERSION(11, 0, 11)(((11) << 16) | ((0) << 8) | (11)): |
| 1231 | case IP_VERSION(11, 5, 0)(((11) << 16) | ((5) << 8) | (0)): |
| 1232 | case IP_VERSION(11, 0, 12)(((11) << 16) | ((0) << 8) | (12)): |
| 1233 | if (adev->in_suspend && smu_is_dpm_running(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running(smu) : 0) : -22)) { |
| 1234 | dev_info(adev->dev, "dpm has been enabled\n")do { } while(0); |
| 1235 | ret = smu_system_features_control(smu, true)((smu)->ppt_funcs ? ((smu)->ppt_funcs->system_features_control ? (smu)->ppt_funcs->system_features_control(smu, 1) : 0 ) : -22); |
| 1236 | if (ret) |
| 1237 | dev_err(adev->dev, "Failed system features control!\n")printf("drm:pid%d:%s *ERROR* " "Failed system features control!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1238 | return ret; |
| 1239 | } |
| 1240 | break; |
| 1241 | default: |
| 1242 | break; |
| 1243 | } |
| 1244 | |
| 1245 | ret = smu_init_display_count(smu, 0)((smu)->ppt_funcs ? ((smu)->ppt_funcs->init_display_count ? (smu)->ppt_funcs->init_display_count(smu, 0) : 0) : - 22); |
| 1246 | if (ret) { |
| 1247 | dev_info(adev->dev, "Failed to pre-set display count as 0!\n")do { } while(0); |
| 1248 | return ret; |
| 1249 | } |
| 1250 | |
| 1251 | ret = smu_set_driver_table_location(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_driver_table_location ? (smu)->ppt_funcs->set_driver_table_location(smu) : 0 ) : -22); |
| 1252 | if (ret) { |
| 1253 | dev_err(adev->dev, "Failed to SetDriverDramAddr!\n")printf("drm:pid%d:%s *ERROR* " "Failed to SetDriverDramAddr!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1254 | return ret; |
| 1255 | } |
| 1256 | |
| 1257 | /* |
| 1258 | * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. |
| 1259 | */ |
| 1260 | ret = smu_set_tool_table_location(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_tool_table_location ? (smu)->ppt_funcs->set_tool_table_location(smu) : 0) : -22); |
| 1261 | if (ret) { |
| 1262 | dev_err(adev->dev, "Failed to SetToolsDramAddr!\n")printf("drm:pid%d:%s *ERROR* " "Failed to SetToolsDramAddr!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1263 | return ret; |
| 1264 | } |
| 1265 | |
| 1266 | /* |
| 1267 | * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify |
| 1268 | * pool location. |
| 1269 | */ |
| 1270 | ret = smu_notify_memory_pool_location(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->notify_memory_pool_location ? (smu)->ppt_funcs->notify_memory_pool_location(smu) : 0) : -22); |
| 1271 | if (ret) { |
| 1272 | dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n")printf("drm:pid%d:%s *ERROR* " "Failed to SetDramLogDramAddr!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1273 | return ret; |
| 1274 | } |
| 1275 | |
| 1276 | ret = smu_setup_pptable(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->setup_pptable ? (smu)->ppt_funcs->setup_pptable(smu) : 0) : -22); |
| 1277 | if (ret) { |
| 1278 | dev_err(adev->dev, "Failed to setup pptable!\n")printf("drm:pid%d:%s *ERROR* " "Failed to setup pptable!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1279 | return ret; |
| 1280 | } |
| 1281 | |
| 1282 | /* smu_dump_pptable(smu); */ |
| 1283 | |
| 1284 | /* |
| 1285 | * With SCPM enabled, PSP is responsible for the PPTable transferring |
| 1286 | * (to SMU). Driver involvement is not needed and permitted. |
| 1287 | */ |
| 1288 | if (!adev->scpm_enabled) { |
| 1289 | /* |
| 1290 | * Copy pptable bo in the vram to smc with SMU MSGs such as |
| 1291 | * SetDriverDramAddr and TransferTableDram2Smu. |
| 1292 | */ |
| 1293 | ret = smu_write_pptable(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->write_pptable ? (smu)->ppt_funcs->write_pptable(smu) : 0) : -22); |
| 1294 | if (ret) { |
| 1295 | dev_err(adev->dev, "Failed to transfer pptable to SMC!\n")printf("drm:pid%d:%s *ERROR* " "Failed to transfer pptable to SMC!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1296 | return ret; |
| 1297 | } |
| 1298 | } |
| 1299 | |
| 1300 | /* issue Run*Btc msg */ |
| 1301 | ret = smu_run_btc(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->run_btc ? (smu )->ppt_funcs->run_btc(smu) : 0) : -22); |
| 1302 | if (ret) |
| 1303 | return ret; |
| 1304 | |
| 1305 | /* |
| 1306 | * With SCPM enabled, these actions(and relevant messages) are |
| 1307 | * not needed and permitted. |
| 1308 | */ |
| 1309 | if (!adev->scpm_enabled) { |
| 1310 | ret = smu_feature_set_allowed_mask(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_allowed_mask ? (smu)->ppt_funcs->set_allowed_mask(smu) : 0) : -22); |
| 1311 | if (ret) { |
| 1312 | dev_err(adev->dev, "Failed to set driver allowed features mask!\n")printf("drm:pid%d:%s *ERROR* " "Failed to set driver allowed features mask!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1313 | return ret; |
| 1314 | } |
| 1315 | } |
| 1316 | |
| 1317 | ret = smu_system_features_control(smu, true)((smu)->ppt_funcs ? ((smu)->ppt_funcs->system_features_control ? (smu)->ppt_funcs->system_features_control(smu, 1) : 0 ) : -22); |
| 1318 | if (ret) { |
| 1319 | dev_err(adev->dev, "Failed to enable requested dpm features!\n")printf("drm:pid%d:%s *ERROR* " "Failed to enable requested dpm features!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1320 | return ret; |
| 1321 | } |
| 1322 | |
| 1323 | ret = smu_feature_get_enabled_mask(smu, &features_supported)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_enabled_mask ? (smu)->ppt_funcs->get_enabled_mask(smu, &features_supported ) : -45) : -22); |
| 1324 | if (ret) { |
| 1325 | dev_err(adev->dev, "Failed to retrieve supported dpm features!\n")printf("drm:pid%d:%s *ERROR* " "Failed to retrieve supported dpm features!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1326 | return ret; |
| 1327 | } |
| 1328 | bitmap_copy(feature->supported, |
| 1329 | (unsigned long *)&features_supported, |
| 1330 | feature->feature_num); |
| 1331 | |
| 1332 | if (!smu_is_dpm_running(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running(smu) : 0) : -22)) |
| 1333 | dev_info(adev->dev, "dpm has been disabled\n")do { } while(0); |
| 1334 | |
| 1335 | /* |
| 1336 | * Set initialized values (get from vbios) to dpm tables context such as |
| 1337 | * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each |
| 1338 | * type of clks. |
| 1339 | */ |
| 1340 | ret = smu_set_default_dpm_table(smu); |
| 1341 | if (ret) { |
| 1342 | dev_err(adev->dev, "Failed to setup default dpm clock tables!\n")printf("drm:pid%d:%s *ERROR* " "Failed to setup default dpm clock tables!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1343 | return ret; |
| 1344 | } |
| 1345 | |
| 1346 | if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN40x00080000) |
| 1347 | pcie_gen = 3; |
| 1348 | else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN30x00040000) |
| 1349 | pcie_gen = 2; |
| 1350 | else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN20x00020000) |
| 1351 | pcie_gen = 1; |
| 1352 | else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN10x00010000) |
| 1353 | pcie_gen = 0; |
| 1354 | |
| 1355 | /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 |
| 1356 | * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 |
| 1357 | * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 |
| 1358 | */ |
| 1359 | if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X160x00200000) |
| 1360 | pcie_width = 6; |
| 1361 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X120x00100000) |
| 1362 | pcie_width = 5; |
| 1363 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X80x00080000) |
| 1364 | pcie_width = 4; |
| 1365 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X40x00040000) |
| 1366 | pcie_width = 3; |
| 1367 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X20x00020000) |
| 1368 | pcie_width = 2; |
| 1369 | else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X10x00010000) |
| 1370 | pcie_width = 1; |
| 1371 | ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width)((smu)->ppt_funcs ? ((smu)->ppt_funcs->update_pcie_parameters ? (smu)->ppt_funcs->update_pcie_parameters(smu, pcie_gen , pcie_width) : 0) : -22); |
| 1372 | if (ret) { |
| 1373 | dev_err(adev->dev, "Attempt to override pcie params failed!\n")printf("drm:pid%d:%s *ERROR* " "Attempt to override pcie params failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1374 | return ret; |
| 1375 | } |
| 1376 | |
| 1377 | ret = smu_get_thermal_temperature_range(smu); |
| 1378 | if (ret) { |
| 1379 | dev_err(adev->dev, "Failed to get thermal temperature ranges!\n")printf("drm:pid%d:%s *ERROR* " "Failed to get thermal temperature ranges!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1380 | return ret; |
| 1381 | } |
| 1382 | |
| 1383 | ret = smu_enable_thermal_alert(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->enable_thermal_alert ? (smu)->ppt_funcs->enable_thermal_alert(smu) : 0) : - 22); |
| 1384 | if (ret) { |
| 1385 | dev_err(adev->dev, "Failed to enable thermal alert!\n")printf("drm:pid%d:%s *ERROR* " "Failed to enable thermal alert!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1386 | return ret; |
| 1387 | } |
| 1388 | |
| 1389 | ret = smu_notify_display_change(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->notify_display_change ? (smu)->ppt_funcs->notify_display_change(smu) : 0) : - 22); |
| 1390 | if (ret) { |
| 1391 | dev_err(adev->dev, "Failed to notify display change!\n")printf("drm:pid%d:%s *ERROR* " "Failed to notify display change!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1392 | return ret; |
| 1393 | } |
| 1394 | |
| 1395 | /* |
| 1396 | * Set min deep sleep dce fclk with bootup value from vbios via |
| 1397 | * SetMinDeepSleepDcefclk MSG. |
| 1398 | */ |
| 1399 | ret = smu_set_min_dcef_deep_sleep(smu,((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep(smu, smu-> smu_table.boot_values.dcefclk / 100) : 0) : -22) |
| 1400 | smu->smu_table.boot_values.dcefclk / 100)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep(smu, smu-> smu_table.boot_values.dcefclk / 100) : 0) : -22); |
| 1401 | |
| 1402 | return ret; |
| 1403 | } |
| 1404 | |
| 1405 | static int smu_start_smc_engine(struct smu_context *smu) |
| 1406 | { |
| 1407 | struct amdgpu_device *adev = smu->adev; |
| 1408 | int ret = 0; |
| 1409 | |
| 1410 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { |
| 1411 | if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)(((11) << 16) | ((0) << 8) | (0))) { |
| 1412 | if (smu->ppt_funcs->load_microcode) { |
| 1413 | ret = smu->ppt_funcs->load_microcode(smu); |
| 1414 | if (ret) |
| 1415 | return ret; |
| 1416 | } |
| 1417 | } |
| 1418 | } |
| 1419 | |
| 1420 | if (smu->ppt_funcs->check_fw_status) { |
| 1421 | ret = smu->ppt_funcs->check_fw_status(smu); |
| 1422 | if (ret) { |
| 1423 | dev_err(adev->dev, "SMC is not ready\n")printf("drm:pid%d:%s *ERROR* " "SMC is not ready\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__); |
| 1424 | return ret; |
| 1425 | } |
| 1426 | } |
| 1427 | |
| 1428 | /* |
| 1429 | * Send msg GetDriverIfVersion to check if the return value is equal |
| 1430 | * with DRIVER_IF_VERSION of smc header. |
| 1431 | */ |
| 1432 | ret = smu_check_fw_version(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->check_fw_version ? (smu)->ppt_funcs->check_fw_version(smu) : 0) : -22); |
| 1433 | if (ret) |
| 1434 | return ret; |
| 1435 | |
| 1436 | return ret; |
| 1437 | } |
| 1438 | |
| 1439 | static int smu_hw_init(void *handle) |
| 1440 | { |
| 1441 | int ret; |
| 1442 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1443 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 1444 | |
| 1445 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) && !amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)) { |
| 1446 | smu->pm_enabled = false0; |
| 1447 | return 0; |
| 1448 | } |
| 1449 | |
| 1450 | ret = smu_start_smc_engine(smu); |
| 1451 | if (ret) { |
| 1452 | dev_err(adev->dev, "SMC engine is not correctly up!\n")printf("drm:pid%d:%s *ERROR* " "SMC engine is not correctly up!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1453 | return ret; |
| 1454 | } |
| 1455 | |
| 1456 | if (smu->is_apu) { |
| 1457 | ret = smu_set_gfx_imu_enable(smu); |
| 1458 | if (ret) |
| 1459 | return ret; |
| 1460 | smu_dpm_set_vcn_enable(smu, true1); |
| 1461 | smu_dpm_set_jpeg_enable(smu, true1); |
| 1462 | smu_set_gfx_cgpg(smu, true1); |
| 1463 | } |
| 1464 | |
| 1465 | if (!smu->pm_enabled) |
| 1466 | return 0; |
| 1467 | |
| 1468 | ret = smu_get_driver_allowed_feature_mask(smu); |
| 1469 | if (ret) |
| 1470 | return ret; |
| 1471 | |
| 1472 | ret = smu_smc_hw_setup(smu); |
| 1473 | if (ret) { |
| 1474 | dev_err(adev->dev, "Failed to setup smc hw!\n")printf("drm:pid%d:%s *ERROR* " "Failed to setup smc hw!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1475 | return ret; |
| 1476 | } |
| 1477 | |
| 1478 | /* |
| 1479 | * Move maximum sustainable clock retrieving here considering |
| 1480 | * 1. It is not needed on resume(from S3). |
| 1481 | * 2. DAL settings come between .hw_init and .late_init of SMU. |
| 1482 | * And DAL needs to know the maximum sustainable clocks. Thus |
| 1483 | * it cannot be put in .late_init(). |
| 1484 | */ |
| 1485 | ret = smu_init_max_sustainable_clocks(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->init_max_sustainable_clocks ? (smu)->ppt_funcs->init_max_sustainable_clocks(smu) : 0) : -22); |
| 1486 | if (ret) { |
| 1487 | dev_err(adev->dev, "Failed to init max sustainable clocks!\n")printf("drm:pid%d:%s *ERROR* " "Failed to init max sustainable clocks!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1488 | return ret; |
| 1489 | } |
| 1490 | |
| 1491 | adev->pm.dpm_enabled = true1; |
| 1492 | |
| 1493 | dev_info(adev->dev, "SMU is initialized successfully!\n")do { } while(0); |
| 1494 | |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
| 1498 | static int smu_disable_dpms(struct smu_context *smu) |
| 1499 | { |
| 1500 | struct amdgpu_device *adev = smu->adev; |
| 1501 | int ret = 0; |
| 1502 | bool_Bool use_baco = !smu->is_apu && |
| 1503 | ((amdgpu_in_reset(adev) && |
| 1504 | (amdgpu_asic_reset_method(adev)(adev)->asic_funcs->reset_method((adev)) == AMD_RESET_METHOD_BACO)) || |
| 1505 | ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)(adev)->asic_funcs->supports_baco((adev)))); |
| 1506 | |
| 1507 | /* |
| 1508 | * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) |
| 1509 | * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. |
| 1510 | */ |
| 1511 | switch (adev->ip_versions[MP1_HWIP][0]) { |
| 1512 | case IP_VERSION(13, 0, 0)(((13) << 16) | ((0) << 8) | (0)): |
| 1513 | case IP_VERSION(13, 0, 7)(((13) << 16) | ((0) << 8) | (7)): |
| 1514 | return 0; |
| 1515 | default: |
| 1516 | break; |
| 1517 | } |
| 1518 | |
| 1519 | /* |
| 1520 | * For custom pptable uploading, skip the DPM features |
| 1521 | * disable process on Navi1x ASICs. |
| 1522 | * - As the gfx related features are under control of |
| 1523 | * RLC on those ASICs. RLC reinitialization will be |
| 1524 | * needed to reenable them. That will cost much more |
| 1525 | * efforts. |
| 1526 | * |
| 1527 | * - SMU firmware can handle the DPM reenablement |
| 1528 | * properly. |
| 1529 | */ |
| 1530 | if (smu->uploading_custom_pp_table) { |
| 1531 | switch (adev->ip_versions[MP1_HWIP][0]) { |
| 1532 | case IP_VERSION(11, 0, 0)(((11) << 16) | ((0) << 8) | (0)): |
| 1533 | case IP_VERSION(11, 0, 5)(((11) << 16) | ((0) << 8) | (5)): |
| 1534 | case IP_VERSION(11, 0, 9)(((11) << 16) | ((0) << 8) | (9)): |
| 1535 | case IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7)): |
| 1536 | case IP_VERSION(11, 0, 11)(((11) << 16) | ((0) << 8) | (11)): |
| 1537 | case IP_VERSION(11, 5, 0)(((11) << 16) | ((5) << 8) | (0)): |
| 1538 | case IP_VERSION(11, 0, 12)(((11) << 16) | ((0) << 8) | (12)): |
| 1539 | case IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13)): |
| 1540 | return 0; |
| 1541 | default: |
| 1542 | break; |
| 1543 | } |
| 1544 | } |
| 1545 | |
| 1546 | /* |
| 1547 | * For Sienna_Cichlid, PMFW will handle the features disablement properly |
| 1548 | * on BACO in. Driver involvement is unnecessary. |
| 1549 | */ |
| 1550 | if (use_baco) { |
| 1551 | switch (adev->ip_versions[MP1_HWIP][0]) { |
| 1552 | case IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7)): |
| 1553 | case IP_VERSION(11, 0, 0)(((11) << 16) | ((0) << 8) | (0)): |
| 1554 | case IP_VERSION(11, 0, 5)(((11) << 16) | ((0) << 8) | (5)): |
| 1555 | case IP_VERSION(11, 0, 9)(((11) << 16) | ((0) << 8) | (9)): |
| 1556 | case IP_VERSION(13, 0, 7)(((13) << 16) | ((0) << 8) | (7)): |
| 1557 | return 0; |
| 1558 | default: |
| 1559 | break; |
| 1560 | } |
| 1561 | } |
| 1562 | |
| 1563 | /* |
| 1564 | * For SMU 13.0.4/11, PMFW will handle the features disablement properly |
| 1565 | * for gpu reset and S0i3 cases. Driver involvement is unnecessary. |
| 1566 | */ |
| 1567 | if (amdgpu_in_reset(adev) || adev->in_s0ix) { |
| 1568 | switch (adev->ip_versions[MP1_HWIP][0]) { |
| 1569 | case IP_VERSION(13, 0, 4)(((13) << 16) | ((0) << 8) | (4)): |
| 1570 | case IP_VERSION(13, 0, 11)(((13) << 16) | ((0) << 8) | (11)): |
| 1571 | return 0; |
| 1572 | default: |
| 1573 | break; |
| 1574 | } |
| 1575 | } |
| 1576 | |
| 1577 | /* |
| 1578 | * For gpu reset, runpm and hibernation through BACO, |
| 1579 | * BACO feature has to be kept enabled. |
| 1580 | */ |
| 1581 | if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)((smu)->ppt_funcs ? ((smu)->ppt_funcs->feature_is_enabled ? (smu)->ppt_funcs->feature_is_enabled(smu, SMU_FEATURE_BACO_BIT ) : 0) : -22)) { |
| 1582 | ret = smu_disable_all_features_with_exception(smu,((smu)->ppt_funcs ? ((smu)->ppt_funcs->disable_all_features_with_exception ? (smu)->ppt_funcs->disable_all_features_with_exception (smu, SMU_FEATURE_BACO_BIT) : 0) : -22) |
| 1583 | SMU_FEATURE_BACO_BIT)((smu)->ppt_funcs ? ((smu)->ppt_funcs->disable_all_features_with_exception ? (smu)->ppt_funcs->disable_all_features_with_exception (smu, SMU_FEATURE_BACO_BIT) : 0) : -22); |
| 1584 | if (ret) |
| 1585 | dev_err(adev->dev, "Failed to disable smu features except BACO.\n")printf("drm:pid%d:%s *ERROR* " "Failed to disable smu features except BACO.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1586 | } else { |
| 1587 | /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ |
| 1588 | if (!adev->scpm_enabled) { |
| 1589 | ret = smu_system_features_control(smu, false)((smu)->ppt_funcs ? ((smu)->ppt_funcs->system_features_control ? (smu)->ppt_funcs->system_features_control(smu, 0) : 0 ) : -22); |
| 1590 | if (ret) |
| 1591 | dev_err(adev->dev, "Failed to disable smu features.\n")printf("drm:pid%d:%s *ERROR* " "Failed to disable smu features.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1592 | } |
| 1593 | } |
| 1594 | |
| 1595 | if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2)(((9) << 16) | ((4) << 8) | (2)) && |
| 1596 | adev->gfx.rlc.funcs->stop) |
| 1597 | adev->gfx.rlc.funcs->stop(adev); |
| 1598 | |
| 1599 | return ret; |
| 1600 | } |
| 1601 | |
| 1602 | static int smu_smc_hw_cleanup(struct smu_context *smu) |
| 1603 | { |
| 1604 | struct amdgpu_device *adev = smu->adev; |
Value stored to 'adev' during its initialization is never read | |
| 1605 | int ret = 0; |
| 1606 | |
| 1607 | cancel_work_sync(&smu->throttling_logging_work); |
| 1608 | cancel_work_sync(&smu->interrupt_work); |
| 1609 | |
| 1610 | ret = smu_disable_thermal_alert(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->disable_thermal_alert ? (smu)->ppt_funcs->disable_thermal_alert(smu) : 0) : - 22); |
| 1611 | if (ret) { |
| 1612 | dev_err(adev->dev, "Fail to disable thermal alert!\n")printf("drm:pid%d:%s *ERROR* " "Fail to disable thermal alert!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1613 | return ret; |
| 1614 | } |
| 1615 | |
| 1616 | cancel_delayed_work_sync(&smu->swctf_delayed_work); |
| 1617 | |
| 1618 | ret = smu_disable_dpms(smu); |
| 1619 | if (ret) { |
| 1620 | dev_err(adev->dev, "Fail to disable dpm features!\n")printf("drm:pid%d:%s *ERROR* " "Fail to disable dpm features!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1621 | return ret; |
| 1622 | } |
| 1623 | |
| 1624 | return 0; |
| 1625 | } |
| 1626 | |
| 1627 | static int smu_hw_fini(void *handle) |
| 1628 | { |
| 1629 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1630 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 1631 | |
| 1632 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))&& !amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)) |
| 1633 | return 0; |
| 1634 | |
| 1635 | smu_dpm_set_vcn_enable(smu, false0); |
| 1636 | smu_dpm_set_jpeg_enable(smu, false0); |
| 1637 | |
| 1638 | adev->vcn.cur_state = AMD_PG_STATE_GATE; |
| 1639 | adev->jpeg.cur_state = AMD_PG_STATE_GATE; |
| 1640 | |
| 1641 | if (!smu->pm_enabled) |
| 1642 | return 0; |
| 1643 | |
| 1644 | adev->pm.dpm_enabled = false0; |
| 1645 | |
| 1646 | return smu_smc_hw_cleanup(smu); |
| 1647 | } |
| 1648 | |
| 1649 | static void smu_late_fini(void *handle) |
| 1650 | { |
| 1651 | struct amdgpu_device *adev = handle; |
| 1652 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 1653 | |
| 1654 | kfree(smu); |
| 1655 | } |
| 1656 | |
| 1657 | static int smu_reset(struct smu_context *smu) |
| 1658 | { |
| 1659 | struct amdgpu_device *adev = smu->adev; |
| 1660 | int ret; |
| 1661 | |
| 1662 | ret = smu_hw_fini(adev); |
| 1663 | if (ret) |
| 1664 | return ret; |
| 1665 | |
| 1666 | ret = smu_hw_init(adev); |
| 1667 | if (ret) |
| 1668 | return ret; |
| 1669 | |
| 1670 | ret = smu_late_init(adev); |
| 1671 | if (ret) |
| 1672 | return ret; |
| 1673 | |
| 1674 | return 0; |
| 1675 | } |
| 1676 | |
| 1677 | static int smu_suspend(void *handle) |
| 1678 | { |
| 1679 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1680 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 1681 | int ret; |
| 1682 | uint64_t count; |
| 1683 | |
| 1684 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))&& !amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)) |
| 1685 | return 0; |
| 1686 | |
| 1687 | if (!smu->pm_enabled) |
| 1688 | return 0; |
| 1689 | |
| 1690 | adev->pm.dpm_enabled = false0; |
| 1691 | |
| 1692 | ret = smu_smc_hw_cleanup(smu); |
| 1693 | if (ret) |
| 1694 | return ret; |
| 1695 | |
| 1696 | smu->watermarks_bitmap &= ~(WATERMARKS_LOADED(1 << 1)); |
| 1697 | |
| 1698 | smu_set_gfx_cgpg(smu, false0); |
| 1699 | |
| 1700 | /* |
| 1701 | * pwfw resets entrycount when device is suspended, so we save the |
| 1702 | * last value to be used when we resume to keep it consistent |
| 1703 | */ |
| 1704 | ret = smu_get_entrycount_gfxoff(smu, &count); |
| 1705 | if (!ret) |
| 1706 | adev->gfx.gfx_off_entrycount = count; |
| 1707 | |
| 1708 | return 0; |
| 1709 | } |
| 1710 | |
| 1711 | static int smu_resume(void *handle) |
| 1712 | { |
| 1713 | int ret; |
| 1714 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 1715 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 1716 | |
| 1717 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))&& !amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)) |
| 1718 | return 0; |
| 1719 | |
| 1720 | if (!smu->pm_enabled) |
| 1721 | return 0; |
| 1722 | |
| 1723 | dev_info(adev->dev, "SMU is resuming...\n")do { } while(0); |
| 1724 | |
| 1725 | ret = smu_start_smc_engine(smu); |
| 1726 | if (ret) { |
| 1727 | dev_err(adev->dev, "SMC engine is not correctly up!\n")printf("drm:pid%d:%s *ERROR* " "SMC engine is not correctly up!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1728 | return ret; |
| 1729 | } |
| 1730 | |
| 1731 | ret = smu_smc_hw_setup(smu); |
| 1732 | if (ret) { |
| 1733 | dev_err(adev->dev, "Failed to setup smc hw!\n")printf("drm:pid%d:%s *ERROR* " "Failed to setup smc hw!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1734 | return ret; |
| 1735 | } |
| 1736 | |
| 1737 | ret = smu_set_gfx_imu_enable(smu); |
| 1738 | if (ret) |
| 1739 | return ret; |
| 1740 | |
| 1741 | smu_set_gfx_cgpg(smu, true1); |
| 1742 | |
| 1743 | smu->disable_uclk_switch = 0; |
| 1744 | |
| 1745 | adev->pm.dpm_enabled = true1; |
| 1746 | |
| 1747 | dev_info(adev->dev, "SMU is resumed successfully!\n")do { } while(0); |
| 1748 | |
| 1749 | return 0; |
| 1750 | } |
| 1751 | |
| 1752 | static int smu_display_configuration_change(void *handle, |
| 1753 | const struct amd_pp_display_configuration *display_config) |
| 1754 | { |
| 1755 | struct smu_context *smu = handle; |
| 1756 | int index = 0; |
| 1757 | int num_of_active_display = 0; |
| 1758 | |
| 1759 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 1760 | return -EOPNOTSUPP45; |
| 1761 | |
| 1762 | if (!display_config) |
| 1763 | return -EINVAL22; |
| 1764 | |
| 1765 | smu_set_min_dcef_deep_sleep(smu,((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep(smu, display_config ->min_dcef_deep_sleep_set_clk / 100) : 0) : -22) |
| 1766 | display_config->min_dcef_deep_sleep_set_clk / 100)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep(smu, display_config ->min_dcef_deep_sleep_set_clk / 100) : 0) : -22); |
| 1767 | |
| 1768 | for (index = 0; index < display_config->num_path_including_non_display; index++) { |
| 1769 | if (display_config->displays[index].controller_id != 0) |
| 1770 | num_of_active_display++; |
| 1771 | } |
| 1772 | |
| 1773 | return 0; |
| 1774 | } |
| 1775 | |
| 1776 | static int smu_set_clockgating_state(void *handle, |
| 1777 | enum amd_clockgating_state state) |
| 1778 | { |
| 1779 | return 0; |
| 1780 | } |
| 1781 | |
| 1782 | static int smu_set_powergating_state(void *handle, |
| 1783 | enum amd_powergating_state state) |
| 1784 | { |
| 1785 | return 0; |
| 1786 | } |
| 1787 | |
| 1788 | static int smu_enable_umd_pstate(void *handle, |
| 1789 | enum amd_dpm_forced_level *level) |
| 1790 | { |
| 1791 | uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | |
| 1792 | AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | |
| 1793 | AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | |
| 1794 | AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; |
| 1795 | |
| 1796 | struct smu_context *smu = (struct smu_context*)(handle); |
| 1797 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); |
| 1798 | |
| 1799 | if (!smu->is_apu && !smu_dpm_ctx->dpm_context) |
| 1800 | return -EINVAL22; |
| 1801 | |
| 1802 | if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { |
| 1803 | /* enter umd pstate, save current level, disable gfx cg*/ |
| 1804 | if (*level & profile_mode_mask) { |
| 1805 | smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; |
| 1806 | smu_gpo_control(smu, false)((smu)->ppt_funcs ? ((smu)->ppt_funcs->gpo_control ? (smu)->ppt_funcs->gpo_control(smu, 0) : 0) : -22); |
| 1807 | smu_gfx_ulv_control(smu, false)((smu)->ppt_funcs ? ((smu)->ppt_funcs->gfx_ulv_control ? (smu)->ppt_funcs->gfx_ulv_control(smu, 0) : 0) : -22 ); |
| 1808 | smu_deep_sleep_control(smu, false)((smu)->ppt_funcs ? ((smu)->ppt_funcs->deep_sleep_control ? (smu)->ppt_funcs->deep_sleep_control(smu, 0) : 0) : - 22); |
| 1809 | amdgpu_asic_update_umd_stable_pstate(smu->adev, true)((smu->adev)->asic_funcs->update_umd_stable_pstate ? (smu->adev)->asic_funcs->update_umd_stable_pstate(( smu->adev), (1)) : 0); |
| 1810 | } |
| 1811 | } else { |
| 1812 | /* exit umd pstate, restore level, enable gfx cg*/ |
| 1813 | if (!(*level & profile_mode_mask)) { |
| 1814 | if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) |
| 1815 | *level = smu_dpm_ctx->saved_dpm_level; |
| 1816 | amdgpu_asic_update_umd_stable_pstate(smu->adev, false)((smu->adev)->asic_funcs->update_umd_stable_pstate ? (smu->adev)->asic_funcs->update_umd_stable_pstate(( smu->adev), (0)) : 0); |
| 1817 | smu_deep_sleep_control(smu, true)((smu)->ppt_funcs ? ((smu)->ppt_funcs->deep_sleep_control ? (smu)->ppt_funcs->deep_sleep_control(smu, 1) : 0) : - 22); |
| 1818 | smu_gfx_ulv_control(smu, true)((smu)->ppt_funcs ? ((smu)->ppt_funcs->gfx_ulv_control ? (smu)->ppt_funcs->gfx_ulv_control(smu, 1) : 0) : -22 ); |
| 1819 | smu_gpo_control(smu, true)((smu)->ppt_funcs ? ((smu)->ppt_funcs->gpo_control ? (smu)->ppt_funcs->gpo_control(smu, 1) : 0) : -22); |
| 1820 | } |
| 1821 | } |
| 1822 | |
| 1823 | return 0; |
| 1824 | } |
| 1825 | |
| 1826 | static int smu_bump_power_profile_mode(struct smu_context *smu, |
| 1827 | long *param, |
| 1828 | uint32_t param_size) |
| 1829 | { |
| 1830 | int ret = 0; |
| 1831 | |
| 1832 | if (smu->ppt_funcs->set_power_profile_mode) |
| 1833 | ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); |
| 1834 | |
| 1835 | return ret; |
| 1836 | } |
| 1837 | |
| 1838 | static int smu_adjust_power_state_dynamic(struct smu_context *smu, |
| 1839 | enum amd_dpm_forced_level level, |
| 1840 | bool_Bool skip_display_settings) |
| 1841 | { |
| 1842 | int ret = 0; |
| 1843 | int index = 0; |
| 1844 | long workload; |
| 1845 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); |
| 1846 | |
| 1847 | if (!skip_display_settings) { |
| 1848 | ret = smu_display_config_changed(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->display_config_changed ? (smu)->ppt_funcs->display_config_changed(smu) : 0) : -22); |
| 1849 | if (ret) { |
| 1850 | dev_err(smu->adev->dev, "Failed to change display config!")printf("drm:pid%d:%s *ERROR* " "Failed to change display config!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1851 | return ret; |
| 1852 | } |
| 1853 | } |
| 1854 | |
| 1855 | ret = smu_apply_clocks_adjust_rules(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->apply_clocks_adjust_rules ? (smu)->ppt_funcs->apply_clocks_adjust_rules(smu) : 0 ) : -22); |
| 1856 | if (ret) { |
| 1857 | dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!")printf("drm:pid%d:%s *ERROR* " "Failed to apply clocks adjust rules!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1858 | return ret; |
| 1859 | } |
| 1860 | |
| 1861 | if (!skip_display_settings) { |
| 1862 | ret = smu_notify_smc_display_config(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->notify_smc_display_config ? (smu)->ppt_funcs->notify_smc_display_config(smu) : 0 ) : -22); |
| 1863 | if (ret) { |
| 1864 | dev_err(smu->adev->dev, "Failed to notify smc display config!")printf("drm:pid%d:%s *ERROR* " "Failed to notify smc display config!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1865 | return ret; |
| 1866 | } |
| 1867 | } |
| 1868 | |
| 1869 | if (smu_dpm_ctx->dpm_level != level) { |
| 1870 | ret = smu_asic_set_performance_level(smu, level)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_performance_level ? (smu)->ppt_funcs->set_performance_level(smu, level) : -22) : -22); |
| 1871 | if (ret) { |
| 1872 | dev_err(smu->adev->dev, "Failed to set performance level!")printf("drm:pid%d:%s *ERROR* " "Failed to set performance level!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1873 | return ret; |
| 1874 | } |
| 1875 | |
| 1876 | /* update the saved copy */ |
| 1877 | smu_dpm_ctx->dpm_level = level; |
| 1878 | } |
| 1879 | |
| 1880 | if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && |
| 1881 | smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { |
| 1882 | index = fls(smu->workload_mask); |
| 1883 | index = index > 0 && index <= WORKLOAD_POLICY_MAX7 ? index - 1 : 0; |
| 1884 | workload = smu->workload_setting[index]; |
| 1885 | |
| 1886 | if (smu->power_profile_mode != workload) |
| 1887 | smu_bump_power_profile_mode(smu, &workload, 0); |
| 1888 | } |
| 1889 | |
| 1890 | return ret; |
| 1891 | } |
| 1892 | |
| 1893 | static int smu_handle_task(struct smu_context *smu, |
| 1894 | enum amd_dpm_forced_level level, |
| 1895 | enum amd_pp_task task_id) |
| 1896 | { |
| 1897 | int ret = 0; |
| 1898 | |
| 1899 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 1900 | return -EOPNOTSUPP45; |
| 1901 | |
| 1902 | switch (task_id) { |
| 1903 | case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: |
| 1904 | ret = smu_pre_display_config_changed(smu)((smu)->ppt_funcs ? ((smu)->ppt_funcs->pre_display_config_changed ? (smu)->ppt_funcs->pre_display_config_changed(smu) : 0 ) : -22); |
| 1905 | if (ret) |
| 1906 | return ret; |
| 1907 | ret = smu_adjust_power_state_dynamic(smu, level, false0); |
| 1908 | break; |
| 1909 | case AMD_PP_TASK_COMPLETE_INIT: |
| 1910 | case AMD_PP_TASK_READJUST_POWER_STATE: |
| 1911 | ret = smu_adjust_power_state_dynamic(smu, level, true1); |
| 1912 | break; |
| 1913 | default: |
| 1914 | break; |
| 1915 | } |
| 1916 | |
| 1917 | return ret; |
| 1918 | } |
| 1919 | |
| 1920 | static int smu_handle_dpm_task(void *handle, |
| 1921 | enum amd_pp_task task_id, |
| 1922 | enum amd_pm_state_type *user_state) |
| 1923 | { |
| 1924 | struct smu_context *smu = handle; |
| 1925 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; |
| 1926 | |
| 1927 | return smu_handle_task(smu, smu_dpm->dpm_level, task_id); |
| 1928 | |
| 1929 | } |
| 1930 | |
| 1931 | static int smu_switch_power_profile(void *handle, |
| 1932 | enum PP_SMC_POWER_PROFILE type, |
| 1933 | bool_Bool en) |
| 1934 | { |
| 1935 | struct smu_context *smu = handle; |
| 1936 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); |
| 1937 | long workload; |
| 1938 | uint32_t index; |
| 1939 | |
| 1940 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 1941 | return -EOPNOTSUPP45; |
| 1942 | |
| 1943 | if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) |
| 1944 | return -EINVAL22; |
| 1945 | |
| 1946 | if (!en) { |
| 1947 | smu->workload_mask &= ~(1 << smu->workload_prority[type]); |
| 1948 | index = fls(smu->workload_mask); |
| 1949 | index = index > 0 && index <= WORKLOAD_POLICY_MAX7 ? index - 1 : 0; |
| 1950 | workload = smu->workload_setting[index]; |
| 1951 | } else { |
| 1952 | smu->workload_mask |= (1 << smu->workload_prority[type]); |
| 1953 | index = fls(smu->workload_mask); |
| 1954 | index = index <= WORKLOAD_POLICY_MAX7 ? index - 1 : 0; |
| 1955 | workload = smu->workload_setting[index]; |
| 1956 | } |
| 1957 | |
| 1958 | if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && |
| 1959 | smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) |
| 1960 | smu_bump_power_profile_mode(smu, &workload, 0); |
| 1961 | |
| 1962 | return 0; |
| 1963 | } |
| 1964 | |
| 1965 | static enum amd_dpm_forced_level smu_get_performance_level(void *handle) |
| 1966 | { |
| 1967 | struct smu_context *smu = handle; |
| 1968 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); |
| 1969 | |
| 1970 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 1971 | return -EOPNOTSUPP45; |
| 1972 | |
| 1973 | if (!smu->is_apu && !smu_dpm_ctx->dpm_context) |
| 1974 | return -EINVAL22; |
| 1975 | |
| 1976 | return smu_dpm_ctx->dpm_level; |
| 1977 | } |
| 1978 | |
| 1979 | static int smu_force_performance_level(void *handle, |
| 1980 | enum amd_dpm_forced_level level) |
| 1981 | { |
| 1982 | struct smu_context *smu = handle; |
| 1983 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); |
| 1984 | int ret = 0; |
| 1985 | |
| 1986 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 1987 | return -EOPNOTSUPP45; |
| 1988 | |
| 1989 | if (!smu->is_apu && !smu_dpm_ctx->dpm_context) |
| 1990 | return -EINVAL22; |
| 1991 | |
| 1992 | ret = smu_enable_umd_pstate(smu, &level); |
| 1993 | if (ret) |
| 1994 | return ret; |
| 1995 | |
| 1996 | ret = smu_handle_task(smu, level, |
| 1997 | AMD_PP_TASK_READJUST_POWER_STATE); |
| 1998 | |
| 1999 | /* reset user dpm clock state */ |
| 2000 | if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { |
| 2001 | memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask))__builtin_memset((smu->user_dpm_profile.clk_mask), (0), (sizeof (smu->user_dpm_profile.clk_mask))); |
| 2002 | smu->user_dpm_profile.clk_dependency = 0; |
| 2003 | } |
| 2004 | |
| 2005 | return ret; |
| 2006 | } |
| 2007 | |
| 2008 | static int smu_set_display_count(void *handle, uint32_t count) |
| 2009 | { |
| 2010 | struct smu_context *smu = handle; |
| 2011 | |
| 2012 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2013 | return -EOPNOTSUPP45; |
| 2014 | |
| 2015 | return smu_init_display_count(smu, count)((smu)->ppt_funcs ? ((smu)->ppt_funcs->init_display_count ? (smu)->ppt_funcs->init_display_count(smu, count) : 0 ) : -22); |
| 2016 | } |
| 2017 | |
| 2018 | static int smu_force_smuclk_levels(struct smu_context *smu, |
| 2019 | enum smu_clk_type clk_type, |
| 2020 | uint32_t mask) |
| 2021 | { |
| 2022 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); |
| 2023 | int ret = 0; |
| 2024 | |
| 2025 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2026 | return -EOPNOTSUPP45; |
| 2027 | |
| 2028 | if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { |
| 2029 | dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n")do { } while(0); |
| 2030 | return -EINVAL22; |
| 2031 | } |
| 2032 | |
| 2033 | if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { |
| 2034 | ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); |
| 2035 | if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE(1 << 0))) { |
| 2036 | smu->user_dpm_profile.clk_mask[clk_type] = mask; |
| 2037 | smu_set_user_clk_dependencies(smu, clk_type); |
| 2038 | } |
| 2039 | } |
| 2040 | |
| 2041 | return ret; |
| 2042 | } |
| 2043 | |
| 2044 | static int smu_force_ppclk_levels(void *handle, |
| 2045 | enum pp_clock_type type, |
| 2046 | uint32_t mask) |
| 2047 | { |
| 2048 | struct smu_context *smu = handle; |
| 2049 | enum smu_clk_type clk_type; |
| 2050 | |
| 2051 | switch (type) { |
| 2052 | case PP_SCLK: |
| 2053 | clk_type = SMU_SCLK; break; |
| 2054 | case PP_MCLK: |
| 2055 | clk_type = SMU_MCLK; break; |
| 2056 | case PP_PCIE: |
| 2057 | clk_type = SMU_PCIE; break; |
| 2058 | case PP_SOCCLK: |
| 2059 | clk_type = SMU_SOCCLK; break; |
| 2060 | case PP_FCLK: |
| 2061 | clk_type = SMU_FCLK; break; |
| 2062 | case PP_DCEFCLK: |
| 2063 | clk_type = SMU_DCEFCLK; break; |
| 2064 | case PP_VCLK: |
| 2065 | clk_type = SMU_VCLK; break; |
| 2066 | case PP_DCLK: |
| 2067 | clk_type = SMU_DCLK; break; |
| 2068 | case OD_SCLK: |
| 2069 | clk_type = SMU_OD_SCLK; break; |
| 2070 | case OD_MCLK: |
| 2071 | clk_type = SMU_OD_MCLK; break; |
| 2072 | case OD_VDDC_CURVE: |
| 2073 | clk_type = SMU_OD_VDDC_CURVE; break; |
| 2074 | case OD_RANGE: |
| 2075 | clk_type = SMU_OD_RANGE; break; |
| 2076 | default: |
| 2077 | return -EINVAL22; |
| 2078 | } |
| 2079 | |
| 2080 | return smu_force_smuclk_levels(smu, clk_type, mask); |
| 2081 | } |
| 2082 | |
| 2083 | /* |
| 2084 | * On system suspending or resetting, the dpm_enabled |
| 2085 | * flag will be cleared. So that those SMU services which |
| 2086 | * are not supported will be gated. |
| 2087 | * However, the mp1 state setting should still be granted |
| 2088 | * even if the dpm_enabled cleared. |
| 2089 | */ |
| 2090 | static int smu_set_mp1_state(void *handle, |
| 2091 | enum pp_mp1_state mp1_state) |
| 2092 | { |
| 2093 | struct smu_context *smu = handle; |
| 2094 | int ret = 0; |
| 2095 | |
| 2096 | if (!smu->pm_enabled) |
| 2097 | return -EOPNOTSUPP45; |
| 2098 | |
| 2099 | if (smu->ppt_funcs && |
| 2100 | smu->ppt_funcs->set_mp1_state) |
| 2101 | ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); |
| 2102 | |
| 2103 | return ret; |
| 2104 | } |
| 2105 | |
| 2106 | static int smu_set_df_cstate(void *handle, |
| 2107 | enum pp_df_cstate state) |
| 2108 | { |
| 2109 | struct smu_context *smu = handle; |
| 2110 | int ret = 0; |
| 2111 | |
| 2112 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2113 | return -EOPNOTSUPP45; |
| 2114 | |
| 2115 | if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) |
| 2116 | return 0; |
| 2117 | |
| 2118 | ret = smu->ppt_funcs->set_df_cstate(smu, state); |
| 2119 | if (ret) |
| 2120 | dev_err(smu->adev->dev, "[SetDfCstate] failed!\n")printf("drm:pid%d:%s *ERROR* " "[SetDfCstate] failed!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__); |
| 2121 | |
| 2122 | return ret; |
| 2123 | } |
| 2124 | |
| 2125 | int smu_allow_xgmi_power_down(struct smu_context *smu, bool_Bool en) |
| 2126 | { |
| 2127 | int ret = 0; |
| 2128 | |
| 2129 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2130 | return -EOPNOTSUPP45; |
| 2131 | |
| 2132 | if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) |
| 2133 | return 0; |
| 2134 | |
| 2135 | ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); |
| 2136 | if (ret) |
| 2137 | dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n")printf("drm:pid%d:%s *ERROR* " "[AllowXgmiPowerDown] failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 2138 | |
| 2139 | return ret; |
| 2140 | } |
| 2141 | |
| 2142 | int smu_write_watermarks_table(struct smu_context *smu) |
| 2143 | { |
| 2144 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2145 | return -EOPNOTSUPP45; |
| 2146 | |
| 2147 | return smu_set_watermarks_table(smu, NULL)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table(smu, ((void * )0)) : 0) : -22); |
| 2148 | } |
| 2149 | |
| 2150 | static int smu_set_watermarks_for_clock_ranges(void *handle, |
| 2151 | struct pp_smu_wm_range_sets *clock_ranges) |
| 2152 | { |
| 2153 | struct smu_context *smu = handle; |
| 2154 | |
| 2155 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2156 | return -EOPNOTSUPP45; |
| 2157 | |
| 2158 | if (smu->disable_watermark) |
| 2159 | return 0; |
| 2160 | |
| 2161 | return smu_set_watermarks_table(smu, clock_ranges)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table(smu, clock_ranges ) : 0) : -22); |
| 2162 | } |
| 2163 | |
| 2164 | int smu_set_ac_dc(struct smu_context *smu) |
| 2165 | { |
| 2166 | int ret = 0; |
| 2167 | |
| 2168 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2169 | return -EOPNOTSUPP45; |
| 2170 | |
| 2171 | /* controlled by firmware */ |
| 2172 | if (smu->dc_controlled_by_gpio) |
| 2173 | return 0; |
| 2174 | |
| 2175 | ret = smu_set_power_source(smu,((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_power_source ? (smu)->ppt_funcs->set_power_source(smu, smu->adev ->pm.ac_power ? SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC) : 0) : -22) |
| 2176 | smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_power_source ? (smu)->ppt_funcs->set_power_source(smu, smu->adev ->pm.ac_power ? SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC) : 0) : -22) |
| 2177 | SMU_POWER_SOURCE_DC)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_power_source ? (smu)->ppt_funcs->set_power_source(smu, smu->adev ->pm.ac_power ? SMU_POWER_SOURCE_AC : SMU_POWER_SOURCE_DC) : 0) : -22); |
| 2178 | if (ret) |
| 2179 | dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",printf("drm:pid%d:%s *ERROR* " "Failed to switch to %s mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , smu-> adev->pm.ac_power ? "AC" : "DC") |
| 2180 | smu->adev->pm.ac_power ? "AC" : "DC")printf("drm:pid%d:%s *ERROR* " "Failed to switch to %s mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , smu-> adev->pm.ac_power ? "AC" : "DC"); |
| 2181 | |
| 2182 | return ret; |
| 2183 | } |
| 2184 | |
| 2185 | const struct amd_ip_funcs smu_ip_funcs = { |
| 2186 | .name = "smu", |
| 2187 | .early_init = smu_early_init, |
| 2188 | .late_init = smu_late_init, |
| 2189 | .sw_init = smu_sw_init, |
| 2190 | .sw_fini = smu_sw_fini, |
| 2191 | .hw_init = smu_hw_init, |
| 2192 | .hw_fini = smu_hw_fini, |
| 2193 | .late_fini = smu_late_fini, |
| 2194 | .suspend = smu_suspend, |
| 2195 | .resume = smu_resume, |
| 2196 | .is_idle = NULL((void *)0), |
| 2197 | .check_soft_reset = NULL((void *)0), |
| 2198 | .wait_for_idle = NULL((void *)0), |
| 2199 | .soft_reset = NULL((void *)0), |
| 2200 | .set_clockgating_state = smu_set_clockgating_state, |
| 2201 | .set_powergating_state = smu_set_powergating_state, |
| 2202 | }; |
| 2203 | |
| 2204 | const struct amdgpu_ip_block_version smu_v11_0_ip_block = |
| 2205 | { |
| 2206 | .type = AMD_IP_BLOCK_TYPE_SMC, |
| 2207 | .major = 11, |
| 2208 | .minor = 0, |
| 2209 | .rev = 0, |
| 2210 | .funcs = &smu_ip_funcs, |
| 2211 | }; |
| 2212 | |
| 2213 | const struct amdgpu_ip_block_version smu_v12_0_ip_block = |
| 2214 | { |
| 2215 | .type = AMD_IP_BLOCK_TYPE_SMC, |
| 2216 | .major = 12, |
| 2217 | .minor = 0, |
| 2218 | .rev = 0, |
| 2219 | .funcs = &smu_ip_funcs, |
| 2220 | }; |
| 2221 | |
| 2222 | const struct amdgpu_ip_block_version smu_v13_0_ip_block = |
| 2223 | { |
| 2224 | .type = AMD_IP_BLOCK_TYPE_SMC, |
| 2225 | .major = 13, |
| 2226 | .minor = 0, |
| 2227 | .rev = 0, |
| 2228 | .funcs = &smu_ip_funcs, |
| 2229 | }; |
| 2230 | |
| 2231 | static int smu_load_microcode(void *handle) |
| 2232 | { |
| 2233 | struct smu_context *smu = handle; |
| 2234 | struct amdgpu_device *adev = smu->adev; |
| 2235 | int ret = 0; |
| 2236 | |
| 2237 | if (!smu->pm_enabled) |
| 2238 | return -EOPNOTSUPP45; |
| 2239 | |
| 2240 | /* This should be used for non PSP loading */ |
| 2241 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) |
| 2242 | return 0; |
| 2243 | |
| 2244 | if (smu->ppt_funcs->load_microcode) { |
| 2245 | ret = smu->ppt_funcs->load_microcode(smu); |
| 2246 | if (ret) { |
| 2247 | dev_err(adev->dev, "Load microcode failed\n")printf("drm:pid%d:%s *ERROR* " "Load microcode failed\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__); |
| 2248 | return ret; |
| 2249 | } |
| 2250 | } |
| 2251 | |
| 2252 | if (smu->ppt_funcs->check_fw_status) { |
| 2253 | ret = smu->ppt_funcs->check_fw_status(smu); |
| 2254 | if (ret) { |
| 2255 | dev_err(adev->dev, "SMC is not ready\n")printf("drm:pid%d:%s *ERROR* " "SMC is not ready\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__); |
| 2256 | return ret; |
| 2257 | } |
| 2258 | } |
| 2259 | |
| 2260 | return ret; |
| 2261 | } |
| 2262 | |
| 2263 | static int smu_set_gfx_cgpg(struct smu_context *smu, bool_Bool enabled) |
| 2264 | { |
| 2265 | int ret = 0; |
| 2266 | |
| 2267 | if (smu->ppt_funcs->set_gfx_cgpg) |
| 2268 | ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); |
| 2269 | |
| 2270 | return ret; |
| 2271 | } |
| 2272 | |
| 2273 | static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) |
| 2274 | { |
| 2275 | struct smu_context *smu = handle; |
| 2276 | int ret = 0; |
| 2277 | |
| 2278 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2279 | return -EOPNOTSUPP45; |
| 2280 | |
| 2281 | if (!smu->ppt_funcs->set_fan_speed_rpm) |
| 2282 | return -EOPNOTSUPP45; |
| 2283 | |
| 2284 | if (speed == U32_MAX0xffffffffU) |
| 2285 | return -EINVAL22; |
| 2286 | |
| 2287 | ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); |
| 2288 | if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE(1 << 0))) { |
| 2289 | smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM(1 << 1); |
| 2290 | smu->user_dpm_profile.fan_speed_rpm = speed; |
| 2291 | |
| 2292 | /* Override custom PWM setting as they cannot co-exist */ |
| 2293 | smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM(1 << 2); |
| 2294 | smu->user_dpm_profile.fan_speed_pwm = 0; |
| 2295 | } |
| 2296 | |
| 2297 | return ret; |
| 2298 | } |
| 2299 | |
| 2300 | /** |
| 2301 | * smu_get_power_limit - Request one of the SMU Power Limits |
| 2302 | * |
| 2303 | * @handle: pointer to smu context |
| 2304 | * @limit: requested limit is written back to this variable |
| 2305 | * @pp_limit_level: &pp_power_limit_level which limit of the power to return |
| 2306 | * @pp_power_type: &pp_power_type type of power |
| 2307 | * Return: 0 on success, <0 on error |
| 2308 | * |
| 2309 | */ |
| 2310 | int smu_get_power_limit(void *handle, |
| 2311 | uint32_t *limit, |
| 2312 | enum pp_power_limit_level pp_limit_level, |
| 2313 | enum pp_power_type pp_power_type) |
| 2314 | { |
| 2315 | struct smu_context *smu = handle; |
| 2316 | struct amdgpu_device *adev = smu->adev; |
| 2317 | enum smu_ppt_limit_level limit_level; |
| 2318 | uint32_t limit_type; |
| 2319 | int ret = 0; |
| 2320 | |
| 2321 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2322 | return -EOPNOTSUPP45; |
| 2323 | |
| 2324 | switch(pp_power_type) { |
| 2325 | case PP_PWR_TYPE_SUSTAINED: |
| 2326 | limit_type = SMU_DEFAULT_PPT_LIMIT; |
| 2327 | break; |
| 2328 | case PP_PWR_TYPE_FAST: |
| 2329 | limit_type = SMU_FAST_PPT_LIMIT; |
| 2330 | break; |
| 2331 | default: |
| 2332 | return -EOPNOTSUPP45; |
| 2333 | break; |
| 2334 | } |
| 2335 | |
| 2336 | switch(pp_limit_level){ |
| 2337 | case PP_PWR_LIMIT_CURRENT: |
| 2338 | limit_level = SMU_PPT_LIMIT_CURRENT; |
| 2339 | break; |
| 2340 | case PP_PWR_LIMIT_DEFAULT: |
| 2341 | limit_level = SMU_PPT_LIMIT_DEFAULT; |
| 2342 | break; |
| 2343 | case PP_PWR_LIMIT_MAX: |
| 2344 | limit_level = SMU_PPT_LIMIT_MAX; |
| 2345 | break; |
| 2346 | case PP_PWR_LIMIT_MIN: |
| 2347 | default: |
| 2348 | return -EOPNOTSUPP45; |
| 2349 | break; |
| 2350 | } |
| 2351 | |
| 2352 | if (limit_type != SMU_DEFAULT_PPT_LIMIT) { |
| 2353 | if (smu->ppt_funcs->get_ppt_limit) |
| 2354 | ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); |
| 2355 | } else { |
| 2356 | switch (limit_level) { |
| 2357 | case SMU_PPT_LIMIT_CURRENT: |
| 2358 | switch (adev->ip_versions[MP1_HWIP][0]) { |
| 2359 | case IP_VERSION(13, 0, 2)(((13) << 16) | ((0) << 8) | (2)): |
| 2360 | case IP_VERSION(11, 0, 7)(((11) << 16) | ((0) << 8) | (7)): |
| 2361 | case IP_VERSION(11, 0, 11)(((11) << 16) | ((0) << 8) | (11)): |
| 2362 | case IP_VERSION(11, 0, 12)(((11) << 16) | ((0) << 8) | (12)): |
| 2363 | case IP_VERSION(11, 0, 13)(((11) << 16) | ((0) << 8) | (13)): |
| 2364 | ret = smu_get_asic_power_limits(smu,((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit(smu, &smu-> current_power_limit, ((void *)0), ((void *)0)) : 0) : -22) |
| 2365 | &smu->current_power_limit,((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit(smu, &smu-> current_power_limit, ((void *)0), ((void *)0)) : 0) : -22) |
| 2366 | NULL,((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit(smu, &smu-> current_power_limit, ((void *)0), ((void *)0)) : 0) : -22) |
| 2367 | NULL)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit(smu, &smu-> current_power_limit, ((void *)0), ((void *)0)) : 0) : -22); |
| 2368 | break; |
| 2369 | default: |
| 2370 | break; |
| 2371 | } |
| 2372 | *limit = smu->current_power_limit; |
| 2373 | break; |
| 2374 | case SMU_PPT_LIMIT_DEFAULT: |
| 2375 | *limit = smu->default_power_limit; |
| 2376 | break; |
| 2377 | case SMU_PPT_LIMIT_MAX: |
| 2378 | *limit = smu->max_power_limit; |
| 2379 | break; |
| 2380 | default: |
| 2381 | break; |
| 2382 | } |
| 2383 | } |
| 2384 | |
| 2385 | return ret; |
| 2386 | } |
| 2387 | |
| 2388 | static int smu_set_power_limit(void *handle, uint32_t limit) |
| 2389 | { |
| 2390 | struct smu_context *smu = handle; |
| 2391 | uint32_t limit_type = limit >> 24; |
| 2392 | int ret = 0; |
| 2393 | |
| 2394 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2395 | return -EOPNOTSUPP45; |
| 2396 | |
| 2397 | limit &= (1<<24)-1; |
| 2398 | if (limit_type != SMU_DEFAULT_PPT_LIMIT) |
| 2399 | if (smu->ppt_funcs->set_power_limit) |
| 2400 | return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); |
| 2401 | |
| 2402 | if (limit > smu->max_power_limit) { |
| 2403 | dev_err(smu->adev->dev,printf("drm:pid%d:%s *ERROR* " "New power limit (%d) is over the max allowed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , limit, smu->max_power_limit) |
| 2404 | "New power limit (%d) is over the max allowed %d\n",printf("drm:pid%d:%s *ERROR* " "New power limit (%d) is over the max allowed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , limit, smu->max_power_limit) |
| 2405 | limit, smu->max_power_limit)printf("drm:pid%d:%s *ERROR* " "New power limit (%d) is over the max allowed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , limit, smu->max_power_limit); |
| 2406 | return -EINVAL22; |
| 2407 | } |
| 2408 | |
| 2409 | if (!limit) |
| 2410 | limit = smu->current_power_limit; |
| 2411 | |
| 2412 | if (smu->ppt_funcs->set_power_limit) { |
| 2413 | ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); |
| 2414 | if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE(1 << 0))) |
| 2415 | smu->user_dpm_profile.power_limit = limit; |
| 2416 | } |
| 2417 | |
| 2418 | return ret; |
| 2419 | } |
| 2420 | |
| 2421 | static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) |
| 2422 | { |
| 2423 | int ret = 0; |
| 2424 | |
| 2425 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2426 | return -EOPNOTSUPP45; |
| 2427 | |
| 2428 | if (smu->ppt_funcs->print_clk_levels) |
| 2429 | ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); |
| 2430 | |
| 2431 | return ret; |
| 2432 | } |
| 2433 | |
| 2434 | static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) |
| 2435 | { |
| 2436 | enum smu_clk_type clk_type; |
| 2437 | |
| 2438 | switch (type) { |
| 2439 | case PP_SCLK: |
| 2440 | clk_type = SMU_SCLK; break; |
| 2441 | case PP_MCLK: |
| 2442 | clk_type = SMU_MCLK; break; |
| 2443 | case PP_PCIE: |
| 2444 | clk_type = SMU_PCIE; break; |
| 2445 | case PP_SOCCLK: |
| 2446 | clk_type = SMU_SOCCLK; break; |
| 2447 | case PP_FCLK: |
| 2448 | clk_type = SMU_FCLK; break; |
| 2449 | case PP_DCEFCLK: |
| 2450 | clk_type = SMU_DCEFCLK; break; |
| 2451 | case PP_VCLK: |
| 2452 | clk_type = SMU_VCLK; break; |
| 2453 | case PP_DCLK: |
| 2454 | clk_type = SMU_DCLK; break; |
| 2455 | case OD_SCLK: |
| 2456 | clk_type = SMU_OD_SCLK; break; |
| 2457 | case OD_MCLK: |
| 2458 | clk_type = SMU_OD_MCLK; break; |
| 2459 | case OD_VDDC_CURVE: |
| 2460 | clk_type = SMU_OD_VDDC_CURVE; break; |
| 2461 | case OD_RANGE: |
| 2462 | clk_type = SMU_OD_RANGE; break; |
| 2463 | case OD_VDDGFX_OFFSET: |
| 2464 | clk_type = SMU_OD_VDDGFX_OFFSET; break; |
| 2465 | case OD_CCLK: |
| 2466 | clk_type = SMU_OD_CCLK; break; |
| 2467 | default: |
| 2468 | clk_type = SMU_CLK_COUNT; break; |
| 2469 | } |
| 2470 | |
| 2471 | return clk_type; |
| 2472 | } |
| 2473 | |
| 2474 | static int smu_print_ppclk_levels(void *handle, |
| 2475 | enum pp_clock_type type, |
| 2476 | char *buf) |
| 2477 | { |
| 2478 | struct smu_context *smu = handle; |
| 2479 | enum smu_clk_type clk_type; |
| 2480 | |
| 2481 | clk_type = smu_convert_to_smuclk(type); |
| 2482 | if (clk_type == SMU_CLK_COUNT) |
| 2483 | return -EINVAL22; |
| 2484 | |
| 2485 | return smu_print_smuclk_levels(smu, clk_type, buf); |
| 2486 | } |
| 2487 | |
| 2488 | static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) |
| 2489 | { |
| 2490 | struct smu_context *smu = handle; |
| 2491 | enum smu_clk_type clk_type; |
| 2492 | |
| 2493 | clk_type = smu_convert_to_smuclk(type); |
| 2494 | if (clk_type == SMU_CLK_COUNT) |
| 2495 | return -EINVAL22; |
| 2496 | |
| 2497 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2498 | return -EOPNOTSUPP45; |
| 2499 | |
| 2500 | if (!smu->ppt_funcs->emit_clk_levels) |
| 2501 | return -ENOENT2; |
| 2502 | |
| 2503 | return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); |
| 2504 | |
| 2505 | } |
| 2506 | |
| 2507 | static int smu_od_edit_dpm_table(void *handle, |
| 2508 | enum PP_OD_DPM_TABLE_COMMAND type, |
| 2509 | long *input, uint32_t size) |
| 2510 | { |
| 2511 | struct smu_context *smu = handle; |
| 2512 | int ret = 0; |
| 2513 | |
| 2514 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2515 | return -EOPNOTSUPP45; |
| 2516 | |
| 2517 | if (smu->ppt_funcs->od_edit_dpm_table) { |
| 2518 | ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); |
| 2519 | } |
| 2520 | |
| 2521 | return ret; |
| 2522 | } |
| 2523 | |
| 2524 | static int smu_read_sensor(void *handle, |
| 2525 | int sensor, |
| 2526 | void *data, |
| 2527 | int *size_arg) |
| 2528 | { |
| 2529 | struct smu_context *smu = handle; |
| 2530 | struct smu_umd_pstate_table *pstate_table = |
| 2531 | &smu->pstate_table; |
| 2532 | int ret = 0; |
| 2533 | uint32_t *size, size_val; |
| 2534 | |
| 2535 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2536 | return -EOPNOTSUPP45; |
| 2537 | |
| 2538 | if (!data || !size_arg) |
| 2539 | return -EINVAL22; |
| 2540 | |
| 2541 | size_val = *size_arg; |
| 2542 | size = &size_val; |
| 2543 | |
| 2544 | if (smu->ppt_funcs->read_sensor) |
| 2545 | if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) |
| 2546 | goto unlock; |
| 2547 | |
| 2548 | switch (sensor) { |
| 2549 | case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: |
| 2550 | *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; |
| 2551 | *size = 4; |
| 2552 | break; |
| 2553 | case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: |
| 2554 | *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; |
| 2555 | *size = 4; |
| 2556 | break; |
| 2557 | case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: |
| 2558 | *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; |
| 2559 | *size = 4; |
| 2560 | break; |
| 2561 | case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: |
| 2562 | *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; |
| 2563 | *size = 4; |
| 2564 | break; |
| 2565 | case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: |
| 2566 | ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data)((smu)->ppt_funcs ? ((smu)->ppt_funcs->get_enabled_mask ? (smu)->ppt_funcs->get_enabled_mask(smu, (uint64_t *) data) : -45) : -22); |
| 2567 | *size = 8; |
| 2568 | break; |
| 2569 | case AMDGPU_PP_SENSOR_UVD_POWER: |
| 2570 | *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)((smu)->ppt_funcs ? ((smu)->ppt_funcs->feature_is_enabled ? (smu)->ppt_funcs->feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT ) : 0) : -22) ? 1 : 0; |
| 2571 | *size = 4; |
| 2572 | break; |
| 2573 | case AMDGPU_PP_SENSOR_VCE_POWER: |
| 2574 | *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT)((smu)->ppt_funcs ? ((smu)->ppt_funcs->feature_is_enabled ? (smu)->ppt_funcs->feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT ) : 0) : -22) ? 1 : 0; |
| 2575 | *size = 4; |
| 2576 | break; |
| 2577 | case AMDGPU_PP_SENSOR_VCN_POWER_STATE: |
| 2578 | *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated)({ typeof(*(&smu->smu_power.power_gate.vcn_gated)) __tmp = *(volatile typeof(*(&smu->smu_power.power_gate.vcn_gated )) *)&(*(&smu->smu_power.power_gate.vcn_gated)); membar_datadep_consumer (); __tmp; }) ? 0: 1; |
| 2579 | *size = 4; |
| 2580 | break; |
| 2581 | case AMDGPU_PP_SENSOR_MIN_FAN_RPM: |
| 2582 | *(uint32_t *)data = 0; |
| 2583 | *size = 4; |
| 2584 | break; |
| 2585 | default: |
| 2586 | *size = 0; |
| 2587 | ret = -EOPNOTSUPP45; |
| 2588 | break; |
| 2589 | } |
| 2590 | |
| 2591 | unlock: |
| 2592 | // assign uint32_t to int |
| 2593 | *size_arg = size_val; |
| 2594 | |
| 2595 | return ret; |
| 2596 | } |
| 2597 | |
| 2598 | static int smu_get_power_profile_mode(void *handle, char *buf) |
| 2599 | { |
| 2600 | struct smu_context *smu = handle; |
| 2601 | |
| 2602 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || |
| 2603 | !smu->ppt_funcs->get_power_profile_mode) |
| 2604 | return -EOPNOTSUPP45; |
| 2605 | if (!buf) |
| 2606 | return -EINVAL22; |
| 2607 | |
| 2608 | return smu->ppt_funcs->get_power_profile_mode(smu, buf); |
| 2609 | } |
| 2610 | |
| 2611 | static int smu_set_power_profile_mode(void *handle, |
| 2612 | long *param, |
| 2613 | uint32_t param_size) |
| 2614 | { |
| 2615 | struct smu_context *smu = handle; |
| 2616 | |
| 2617 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || |
| 2618 | !smu->ppt_funcs->set_power_profile_mode) |
| 2619 | return -EOPNOTSUPP45; |
| 2620 | |
| 2621 | return smu_bump_power_profile_mode(smu, param, param_size); |
| 2622 | } |
| 2623 | |
| 2624 | static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) |
| 2625 | { |
| 2626 | struct smu_context *smu = handle; |
| 2627 | |
| 2628 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2629 | return -EOPNOTSUPP45; |
| 2630 | |
| 2631 | if (!smu->ppt_funcs->get_fan_control_mode) |
| 2632 | return -EOPNOTSUPP45; |
| 2633 | |
| 2634 | if (!fan_mode) |
| 2635 | return -EINVAL22; |
| 2636 | |
| 2637 | *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); |
| 2638 | |
| 2639 | return 0; |
| 2640 | } |
| 2641 | |
| 2642 | static int smu_set_fan_control_mode(void *handle, u32 value) |
| 2643 | { |
| 2644 | struct smu_context *smu = handle; |
| 2645 | int ret = 0; |
| 2646 | |
| 2647 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2648 | return -EOPNOTSUPP45; |
| 2649 | |
| 2650 | if (!smu->ppt_funcs->set_fan_control_mode) |
| 2651 | return -EOPNOTSUPP45; |
| 2652 | |
| 2653 | if (value == U32_MAX0xffffffffU) |
| 2654 | return -EINVAL22; |
| 2655 | |
| 2656 | ret = smu->ppt_funcs->set_fan_control_mode(smu, value); |
| 2657 | if (ret) |
| 2658 | goto out; |
| 2659 | |
| 2660 | if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE(1 << 0))) { |
| 2661 | smu->user_dpm_profile.fan_mode = value; |
| 2662 | |
| 2663 | /* reset user dpm fan speed */ |
| 2664 | if (value != AMD_FAN_CTRL_MANUAL) { |
| 2665 | smu->user_dpm_profile.fan_speed_pwm = 0; |
| 2666 | smu->user_dpm_profile.fan_speed_rpm = 0; |
| 2667 | smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM(1 << 1) | SMU_CUSTOM_FAN_SPEED_PWM(1 << 2)); |
| 2668 | } |
| 2669 | } |
| 2670 | |
| 2671 | out: |
| 2672 | return ret; |
| 2673 | } |
| 2674 | |
| 2675 | static int smu_get_fan_speed_pwm(void *handle, u32 *speed) |
| 2676 | { |
| 2677 | struct smu_context *smu = handle; |
| 2678 | int ret = 0; |
| 2679 | |
| 2680 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2681 | return -EOPNOTSUPP45; |
| 2682 | |
| 2683 | if (!smu->ppt_funcs->get_fan_speed_pwm) |
| 2684 | return -EOPNOTSUPP45; |
| 2685 | |
| 2686 | if (!speed) |
| 2687 | return -EINVAL22; |
| 2688 | |
| 2689 | ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); |
| 2690 | |
| 2691 | return ret; |
| 2692 | } |
| 2693 | |
| 2694 | static int smu_set_fan_speed_pwm(void *handle, u32 speed) |
| 2695 | { |
| 2696 | struct smu_context *smu = handle; |
| 2697 | int ret = 0; |
| 2698 | |
| 2699 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2700 | return -EOPNOTSUPP45; |
| 2701 | |
| 2702 | if (!smu->ppt_funcs->set_fan_speed_pwm) |
| 2703 | return -EOPNOTSUPP45; |
| 2704 | |
| 2705 | if (speed == U32_MAX0xffffffffU) |
| 2706 | return -EINVAL22; |
| 2707 | |
| 2708 | ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); |
| 2709 | if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE(1 << 0))) { |
| 2710 | smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM(1 << 2); |
| 2711 | smu->user_dpm_profile.fan_speed_pwm = speed; |
| 2712 | |
| 2713 | /* Override custom RPM setting as they cannot co-exist */ |
| 2714 | smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM(1 << 1); |
| 2715 | smu->user_dpm_profile.fan_speed_rpm = 0; |
| 2716 | } |
| 2717 | |
| 2718 | return ret; |
| 2719 | } |
| 2720 | |
| 2721 | static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) |
| 2722 | { |
| 2723 | struct smu_context *smu = handle; |
| 2724 | int ret = 0; |
| 2725 | |
| 2726 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2727 | return -EOPNOTSUPP45; |
| 2728 | |
| 2729 | if (!smu->ppt_funcs->get_fan_speed_rpm) |
| 2730 | return -EOPNOTSUPP45; |
| 2731 | |
| 2732 | if (!speed) |
| 2733 | return -EINVAL22; |
| 2734 | |
| 2735 | ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); |
| 2736 | |
| 2737 | return ret; |
| 2738 | } |
| 2739 | |
| 2740 | static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) |
| 2741 | { |
| 2742 | struct smu_context *smu = handle; |
| 2743 | |
| 2744 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2745 | return -EOPNOTSUPP45; |
| 2746 | |
| 2747 | return smu_set_min_dcef_deep_sleep(smu, clk)((smu)->ppt_funcs ? ((smu)->ppt_funcs->set_min_dcef_deep_sleep ? (smu)->ppt_funcs->set_min_dcef_deep_sleep(smu, clk) : 0) : -22); |
| 2748 | } |
| 2749 | |
| 2750 | static int smu_get_clock_by_type_with_latency(void *handle, |
| 2751 | enum amd_pp_clock_type type, |
| 2752 | struct pp_clock_levels_with_latency *clocks) |
| 2753 | { |
| 2754 | struct smu_context *smu = handle; |
| 2755 | enum smu_clk_type clk_type; |
| 2756 | int ret = 0; |
| 2757 | |
| 2758 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2759 | return -EOPNOTSUPP45; |
| 2760 | |
| 2761 | if (smu->ppt_funcs->get_clock_by_type_with_latency) { |
| 2762 | switch (type) { |
| 2763 | case amd_pp_sys_clock: |
| 2764 | clk_type = SMU_GFXCLK; |
| 2765 | break; |
| 2766 | case amd_pp_mem_clock: |
| 2767 | clk_type = SMU_MCLK; |
| 2768 | break; |
| 2769 | case amd_pp_dcef_clock: |
| 2770 | clk_type = SMU_DCEFCLK; |
| 2771 | break; |
| 2772 | case amd_pp_disp_clock: |
| 2773 | clk_type = SMU_DISPCLK; |
| 2774 | break; |
| 2775 | default: |
| 2776 | dev_err(smu->adev->dev, "Invalid clock type!\n")printf("drm:pid%d:%s *ERROR* " "Invalid clock type!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__); |
| 2777 | return -EINVAL22; |
| 2778 | } |
| 2779 | |
| 2780 | ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); |
| 2781 | } |
| 2782 | |
| 2783 | return ret; |
| 2784 | } |
| 2785 | |
| 2786 | static int smu_display_clock_voltage_request(void *handle, |
| 2787 | struct pp_display_clock_request *clock_req) |
| 2788 | { |
| 2789 | struct smu_context *smu = handle; |
| 2790 | int ret = 0; |
| 2791 | |
| 2792 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2793 | return -EOPNOTSUPP45; |
| 2794 | |
| 2795 | if (smu->ppt_funcs->display_clock_voltage_request) |
| 2796 | ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); |
| 2797 | |
| 2798 | return ret; |
| 2799 | } |
| 2800 | |
| 2801 | |
| 2802 | static int smu_display_disable_memory_clock_switch(void *handle, |
| 2803 | bool_Bool disable_memory_clock_switch) |
| 2804 | { |
| 2805 | struct smu_context *smu = handle; |
| 2806 | int ret = -EINVAL22; |
| 2807 | |
| 2808 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2809 | return -EOPNOTSUPP45; |
| 2810 | |
| 2811 | if (smu->ppt_funcs->display_disable_memory_clock_switch) |
| 2812 | ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); |
| 2813 | |
| 2814 | return ret; |
| 2815 | } |
| 2816 | |
| 2817 | static int smu_set_xgmi_pstate(void *handle, |
| 2818 | uint32_t pstate) |
| 2819 | { |
| 2820 | struct smu_context *smu = handle; |
| 2821 | int ret = 0; |
| 2822 | |
| 2823 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2824 | return -EOPNOTSUPP45; |
| 2825 | |
| 2826 | if (smu->ppt_funcs->set_xgmi_pstate) |
| 2827 | ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); |
| 2828 | |
| 2829 | if(ret) |
| 2830 | dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n")printf("drm:pid%d:%s *ERROR* " "Failed to set XGMI pstate!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 2831 | |
| 2832 | return ret; |
| 2833 | } |
| 2834 | |
| 2835 | static int smu_get_baco_capability(void *handle, bool_Bool *cap) |
| 2836 | { |
| 2837 | struct smu_context *smu = handle; |
| 2838 | |
| 2839 | *cap = false0; |
| 2840 | |
| 2841 | if (!smu->pm_enabled) |
| 2842 | return 0; |
| 2843 | |
| 2844 | if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) |
| 2845 | *cap = smu->ppt_funcs->baco_is_support(smu); |
| 2846 | |
| 2847 | return 0; |
| 2848 | } |
| 2849 | |
| 2850 | static int smu_baco_set_state(void *handle, int state) |
| 2851 | { |
| 2852 | struct smu_context *smu = handle; |
| 2853 | int ret = 0; |
| 2854 | |
| 2855 | if (!smu->pm_enabled) |
| 2856 | return -EOPNOTSUPP45; |
| 2857 | |
| 2858 | if (state == 0) { |
| 2859 | if (smu->ppt_funcs->baco_exit) |
| 2860 | ret = smu->ppt_funcs->baco_exit(smu); |
| 2861 | } else if (state == 1) { |
| 2862 | if (smu->ppt_funcs->baco_enter) |
| 2863 | ret = smu->ppt_funcs->baco_enter(smu); |
| 2864 | } else { |
| 2865 | return -EINVAL22; |
| 2866 | } |
| 2867 | |
| 2868 | if (ret) |
| 2869 | dev_err(smu->adev->dev, "Failed to %s BACO state!\n",printf("drm:pid%d:%s *ERROR* " "Failed to %s BACO state!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , (state )?"enter":"exit") |
| 2870 | (state)?"enter":"exit")printf("drm:pid%d:%s *ERROR* " "Failed to %s BACO state!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , (state )?"enter":"exit"); |
| 2871 | |
| 2872 | return ret; |
| 2873 | } |
| 2874 | |
| 2875 | bool_Bool smu_mode1_reset_is_support(struct smu_context *smu) |
| 2876 | { |
| 2877 | bool_Bool ret = false0; |
| 2878 | |
| 2879 | if (!smu->pm_enabled) |
| 2880 | return false0; |
| 2881 | |
| 2882 | if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) |
| 2883 | ret = smu->ppt_funcs->mode1_reset_is_support(smu); |
| 2884 | |
| 2885 | return ret; |
| 2886 | } |
| 2887 | |
| 2888 | bool_Bool smu_mode2_reset_is_support(struct smu_context *smu) |
| 2889 | { |
| 2890 | bool_Bool ret = false0; |
| 2891 | |
| 2892 | if (!smu->pm_enabled) |
| 2893 | return false0; |
| 2894 | |
| 2895 | if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) |
| 2896 | ret = smu->ppt_funcs->mode2_reset_is_support(smu); |
| 2897 | |
| 2898 | return ret; |
| 2899 | } |
| 2900 | |
| 2901 | int smu_mode1_reset(struct smu_context *smu) |
| 2902 | { |
| 2903 | int ret = 0; |
| 2904 | |
| 2905 | if (!smu->pm_enabled) |
| 2906 | return -EOPNOTSUPP45; |
| 2907 | |
| 2908 | if (smu->ppt_funcs->mode1_reset) |
| 2909 | ret = smu->ppt_funcs->mode1_reset(smu); |
| 2910 | |
| 2911 | return ret; |
| 2912 | } |
| 2913 | |
| 2914 | static int smu_mode2_reset(void *handle) |
| 2915 | { |
| 2916 | struct smu_context *smu = handle; |
| 2917 | int ret = 0; |
| 2918 | |
| 2919 | if (!smu->pm_enabled) |
| 2920 | return -EOPNOTSUPP45; |
| 2921 | |
| 2922 | if (smu->ppt_funcs->mode2_reset) |
| 2923 | ret = smu->ppt_funcs->mode2_reset(smu); |
| 2924 | |
| 2925 | if (ret) |
| 2926 | dev_err(smu->adev->dev, "Mode2 reset failed!\n")printf("drm:pid%d:%s *ERROR* " "Mode2 reset failed!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__); |
| 2927 | |
| 2928 | return ret; |
| 2929 | } |
| 2930 | |
| 2931 | static int smu_get_max_sustainable_clocks_by_dc(void *handle, |
| 2932 | struct pp_smu_nv_clock_table *max_clocks) |
| 2933 | { |
| 2934 | struct smu_context *smu = handle; |
| 2935 | int ret = 0; |
| 2936 | |
| 2937 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2938 | return -EOPNOTSUPP45; |
| 2939 | |
| 2940 | if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) |
| 2941 | ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); |
| 2942 | |
| 2943 | return ret; |
| 2944 | } |
| 2945 | |
| 2946 | static int smu_get_uclk_dpm_states(void *handle, |
| 2947 | unsigned int *clock_values_in_khz, |
| 2948 | unsigned int *num_states) |
| 2949 | { |
| 2950 | struct smu_context *smu = handle; |
| 2951 | int ret = 0; |
| 2952 | |
| 2953 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2954 | return -EOPNOTSUPP45; |
| 2955 | |
| 2956 | if (smu->ppt_funcs->get_uclk_dpm_states) |
| 2957 | ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); |
| 2958 | |
| 2959 | return ret; |
| 2960 | } |
| 2961 | |
| 2962 | static enum amd_pm_state_type smu_get_current_power_state(void *handle) |
| 2963 | { |
| 2964 | struct smu_context *smu = handle; |
| 2965 | enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; |
| 2966 | |
| 2967 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2968 | return -EOPNOTSUPP45; |
| 2969 | |
| 2970 | if (smu->ppt_funcs->get_current_power_state) |
| 2971 | pm_state = smu->ppt_funcs->get_current_power_state(smu); |
| 2972 | |
| 2973 | return pm_state; |
| 2974 | } |
| 2975 | |
| 2976 | static int smu_get_dpm_clock_table(void *handle, |
| 2977 | struct dpm_clocks *clock_table) |
| 2978 | { |
| 2979 | struct smu_context *smu = handle; |
| 2980 | int ret = 0; |
| 2981 | |
| 2982 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2983 | return -EOPNOTSUPP45; |
| 2984 | |
| 2985 | if (smu->ppt_funcs->get_dpm_clock_table) |
| 2986 | ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); |
| 2987 | |
| 2988 | return ret; |
| 2989 | } |
| 2990 | |
| 2991 | static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) |
| 2992 | { |
| 2993 | struct smu_context *smu = handle; |
| 2994 | |
| 2995 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 2996 | return -EOPNOTSUPP45; |
| 2997 | |
| 2998 | if (!smu->ppt_funcs->get_gpu_metrics) |
| 2999 | return -EOPNOTSUPP45; |
| 3000 | |
| 3001 | return smu->ppt_funcs->get_gpu_metrics(smu, table); |
| 3002 | } |
| 3003 | |
| 3004 | static int smu_enable_mgpu_fan_boost(void *handle) |
| 3005 | { |
| 3006 | struct smu_context *smu = handle; |
| 3007 | int ret = 0; |
| 3008 | |
| 3009 | if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) |
| 3010 | return -EOPNOTSUPP45; |
| 3011 | |
| 3012 | if (smu->ppt_funcs->enable_mgpu_fan_boost) |
| 3013 | ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); |
| 3014 | |
| 3015 | return ret; |
| 3016 | } |
| 3017 | |
| 3018 | static int smu_gfx_state_change_set(void *handle, |
| 3019 | uint32_t state) |
| 3020 | { |
| 3021 | struct smu_context *smu = handle; |
| 3022 | int ret = 0; |
| 3023 | |
| 3024 | if (smu->ppt_funcs->gfx_state_change_set) |
| 3025 | ret = smu->ppt_funcs->gfx_state_change_set(smu, state); |
| 3026 | |
| 3027 | return ret; |
| 3028 | } |
| 3029 | |
| 3030 | int smu_handle_passthrough_sbr(struct smu_context *smu, bool_Bool enable) |
| 3031 | { |
| 3032 | int ret = 0; |
| 3033 | |
| 3034 | if (smu->ppt_funcs->smu_handle_passthrough_sbr) |
| 3035 | ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); |
| 3036 | |
| 3037 | return ret; |
| 3038 | } |
| 3039 | |
| 3040 | int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) |
| 3041 | { |
| 3042 | int ret = -EOPNOTSUPP45; |
| 3043 | |
| 3044 | if (smu->ppt_funcs && |
| 3045 | smu->ppt_funcs->get_ecc_info) |
| 3046 | ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); |
| 3047 | |
| 3048 | return ret; |
| 3049 | |
| 3050 | } |
| 3051 | |
| 3052 | static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) |
| 3053 | { |
| 3054 | struct smu_context *smu = handle; |
| 3055 | struct smu_table_context *smu_table = &smu->smu_table; |
| 3056 | struct smu_table *memory_pool = &smu_table->memory_pool; |
| 3057 | |
| 3058 | if (!addr || !size) |
| 3059 | return -EINVAL22; |
| 3060 | |
| 3061 | *addr = NULL((void *)0); |
| 3062 | *size = 0; |
| 3063 | if (memory_pool->bo) { |
| 3064 | *addr = memory_pool->cpu_addr; |
| 3065 | *size = memory_pool->size; |
| 3066 | } |
| 3067 | |
| 3068 | return 0; |
| 3069 | } |
| 3070 | |
| 3071 | static const struct amd_pm_funcs swsmu_pm_funcs = { |
| 3072 | /* export for sysfs */ |
| 3073 | .set_fan_control_mode = smu_set_fan_control_mode, |
| 3074 | .get_fan_control_mode = smu_get_fan_control_mode, |
| 3075 | .set_fan_speed_pwm = smu_set_fan_speed_pwm, |
| 3076 | .get_fan_speed_pwm = smu_get_fan_speed_pwm, |
| 3077 | .force_clock_level = smu_force_ppclk_levels, |
| 3078 | .print_clock_levels = smu_print_ppclk_levels, |
| 3079 | .emit_clock_levels = smu_emit_ppclk_levels, |
| 3080 | .force_performance_level = smu_force_performance_level, |
| 3081 | .read_sensor = smu_read_sensor, |
| 3082 | .get_performance_level = smu_get_performance_level, |
| 3083 | .get_current_power_state = smu_get_current_power_state, |
| 3084 | .get_fan_speed_rpm = smu_get_fan_speed_rpm, |
| 3085 | .set_fan_speed_rpm = smu_set_fan_speed_rpm, |
| 3086 | .get_pp_num_states = smu_get_power_num_states, |
| 3087 | .get_pp_table = smu_sys_get_pp_table, |
| 3088 | .set_pp_table = smu_sys_set_pp_table, |
| 3089 | .switch_power_profile = smu_switch_power_profile, |
| 3090 | /* export to amdgpu */ |
| 3091 | .dispatch_tasks = smu_handle_dpm_task, |
| 3092 | .load_firmware = smu_load_microcode, |
| 3093 | .set_powergating_by_smu = smu_dpm_set_power_gate, |
| 3094 | .set_power_limit = smu_set_power_limit, |
| 3095 | .get_power_limit = smu_get_power_limit, |
| 3096 | .get_power_profile_mode = smu_get_power_profile_mode, |
| 3097 | .set_power_profile_mode = smu_set_power_profile_mode, |
| 3098 | .odn_edit_dpm_table = smu_od_edit_dpm_table, |
| 3099 | .set_mp1_state = smu_set_mp1_state, |
| 3100 | .gfx_state_change_set = smu_gfx_state_change_set, |
| 3101 | /* export to DC */ |
| 3102 | .get_sclk = smu_get_sclk, |
| 3103 | .get_mclk = smu_get_mclk, |
| 3104 | .display_configuration_change = smu_display_configuration_change, |
| 3105 | .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, |
| 3106 | .display_clock_voltage_request = smu_display_clock_voltage_request, |
| 3107 | .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, |
| 3108 | .set_active_display_count = smu_set_display_count, |
| 3109 | .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, |
| 3110 | .get_asic_baco_capability = smu_get_baco_capability, |
| 3111 | .set_asic_baco_state = smu_baco_set_state, |
| 3112 | .get_ppfeature_status = smu_sys_get_pp_feature_mask, |
| 3113 | .set_ppfeature_status = smu_sys_set_pp_feature_mask, |
| 3114 | .asic_reset_mode_2 = smu_mode2_reset, |
| 3115 | .set_df_cstate = smu_set_df_cstate, |
| 3116 | .set_xgmi_pstate = smu_set_xgmi_pstate, |
| 3117 | .get_gpu_metrics = smu_sys_get_gpu_metrics, |
| 3118 | .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, |
| 3119 | .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, |
| 3120 | .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, |
| 3121 | .get_uclk_dpm_states = smu_get_uclk_dpm_states, |
| 3122 | .get_dpm_clock_table = smu_get_dpm_clock_table, |
| 3123 | .get_smu_prv_buf_details = smu_get_prv_buffer_details, |
| 3124 | }; |
| 3125 | |
| 3126 | int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, |
| 3127 | uint64_t event_arg) |
| 3128 | { |
| 3129 | int ret = -EINVAL22; |
| 3130 | |
| 3131 | if (smu->ppt_funcs->wait_for_event) |
| 3132 | ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); |
| 3133 | |
| 3134 | return ret; |
| 3135 | } |
| 3136 | |
| 3137 | int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) |
| 3138 | { |
| 3139 | |
| 3140 | if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) |
| 3141 | return -EOPNOTSUPP45; |
| 3142 | |
| 3143 | /* Confirm the buffer allocated is of correct size */ |
| 3144 | if (size != smu->stb_context.stb_buf_size) |
| 3145 | return -EINVAL22; |
| 3146 | |
| 3147 | /* |
| 3148 | * No need to lock smu mutex as we access STB directly through MMIO |
| 3149 | * and not going through SMU messaging route (for now at least). |
| 3150 | * For registers access rely on implementation internal locking. |
| 3151 | */ |
| 3152 | return smu->ppt_funcs->stb_collect_info(smu, buf, size); |
| 3153 | } |
| 3154 | |
| 3155 | #if defined(CONFIG_DEBUG_FS) |
| 3156 | |
| 3157 | static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) |
| 3158 | { |
| 3159 | struct amdgpu_device *adev = filp->f_inode->i_private; |
| 3160 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 3161 | unsigned char *buf; |
| 3162 | int r; |
| 3163 | |
| 3164 | buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL(0x0001 | 0x0004)); |
| 3165 | if (!buf) |
| 3166 | return -ENOMEM12; |
| 3167 | |
| 3168 | r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); |
| 3169 | if (r) |
| 3170 | goto out; |
| 3171 | |
| 3172 | filp->private_data = buf; |
| 3173 | |
| 3174 | return 0; |
| 3175 | |
| 3176 | out: |
| 3177 | kvfree(buf); |
| 3178 | return r; |
| 3179 | } |
| 3180 | |
| 3181 | static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, |
| 3182 | loff_t *pos) |
| 3183 | { |
| 3184 | struct amdgpu_device *adev = filp->f_inode->i_private; |
| 3185 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 3186 | |
| 3187 | |
| 3188 | if (!filp->private_data) |
| 3189 | return -EINVAL22; |
| 3190 | |
| 3191 | return simple_read_from_buffer(buf, |
| 3192 | size, |
| 3193 | pos, filp->private_data, |
| 3194 | smu->stb_context.stb_buf_size); |
| 3195 | } |
| 3196 | |
| 3197 | static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) |
| 3198 | { |
| 3199 | kvfree(filp->private_data); |
| 3200 | filp->private_data = NULL((void *)0); |
| 3201 | |
| 3202 | return 0; |
| 3203 | } |
| 3204 | |
| 3205 | /* |
| 3206 | * We have to define not only read method but also |
| 3207 | * open and release because .read takes up to PAGE_SIZE |
| 3208 | * data each time so and so is invoked multiple times. |
| 3209 | * We allocate the STB buffer in .open and release it |
| 3210 | * in .release |
| 3211 | */ |
| 3212 | static const struct file_operations smu_stb_debugfs_fops = { |
| 3213 | .owner = THIS_MODULE((void *)0), |
| 3214 | .open = smu_stb_debugfs_open, |
| 3215 | .read = smu_stb_debugfs_read, |
| 3216 | .release = smu_stb_debugfs_release, |
| 3217 | .llseek = default_llseek, |
| 3218 | }; |
| 3219 | |
| 3220 | #endif |
| 3221 | |
| 3222 | void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) |
| 3223 | { |
| 3224 | #if defined(CONFIG_DEBUG_FS) |
| 3225 | |
| 3226 | struct smu_context *smu = adev->powerplay.pp_handle; |
| 3227 | |
| 3228 | if (!smu || (!smu->stb_context.stb_buf_size)) |
| 3229 | return; |
| 3230 | |
| 3231 | debugfs_create_file_size("amdgpu_smu_stb_dump", |
| 3232 | S_IRUSR, |
| 3233 | adev_to_drm(adev)->primary->debugfs_root, |
| 3234 | adev, |
| 3235 | &smu_stb_debugfs_fops, |
| 3236 | smu->stb_context.stb_buf_size); |
| 3237 | #endif |
| 3238 | } |
| 3239 | |
| 3240 | int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) |
| 3241 | { |
| 3242 | int ret = 0; |
| 3243 | |
| 3244 | if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) |
| 3245 | ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); |
| 3246 | |
| 3247 | return ret; |
| 3248 | } |
| 3249 | |
| 3250 | int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) |
| 3251 | { |
| 3252 | int ret = 0; |
| 3253 | |
| 3254 | if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) |
| 3255 | ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); |
| 3256 | |
| 3257 | return ret; |
| 3258 | } |