/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Bug Summary

File:	src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:	line 1110, column 10 Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AMDGPUISelDAGToDAG.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 1 -fhalf-no-semantic-interposition -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Analysis -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ASMParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/BinaryFormat -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitstream -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /include/llvm/CodeGen -I /include/llvm/CodeGen/PBQP -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Coroutines -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData/Coverage -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/CodeView -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/DWARF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/MSF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/PDB -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Demangle -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/JITLink -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/Orc -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenACC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenMP -I /include/llvm/CodeGen/GlobalISel -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IRReader -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/LTO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Linker -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC/MCParser -I /include/llvm/CodeGen/MIRParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Object -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Option -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Passes -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Scalar -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ADT -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Support -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/Symbolize -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Target -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Utils -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Vectorize -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/IPO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include -I /usr/src/gnu/usr.bin/clang/libLLVM/../include -I /usr/src/gnu/usr.bin/clang/libLLVM/obj -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include -D NDEBUG -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D LLVM_PREFIX="/usr" -D PIC -internal-isystem /usr/include/c++/v1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -ferror-limit 19 -fvisibility-inlines-hidden -fwrapv -D_RET_PROTECTOR -ret-protector -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c++ /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

→

1//===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//==-----------------------------------------------------------------------===//
8//
9/// \file
10/// Defines an instruction selector for the AMDGPU target.
11//
12//===----------------------------------------------------------------------===//

14#include "AMDGPU.h"
15#include "AMDGPUTargetMachine.h"
16#include "SIMachineFunctionInfo.h"
17#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
18#include "llvm/Analysis/ValueTracking.h"
19#include "llvm/CodeGen/FunctionLoweringInfo.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/SelectionDAGISel.h"
22#include "llvm/CodeGen/SelectionDAGNodes.h"
23#include "llvm/IR/IntrinsicsAMDGPU.h"
24#include "llvm/InitializePasses.h"

26#ifdef EXPENSIVE_CHECKS
27#include "llvm/Analysis/LoopInfo.h"
28#include "llvm/IR/Dominators.h"
29#endif

31#define DEBUG_TYPE"isel" "isel"

33using namespace llvm;

35namespace llvm {

37class R600InstrInfo;

39} // end namespace llvm

41//===----------------------------------------------------------------------===//
42// Instruction Selector Implementation
43//===----------------------------------------------------------------------===//

45namespace {

47static bool isNullConstantOrUndef(SDValue V) {
if (V.isUndef())
  return true;

ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
return Const != nullptr && Const->isNullValue();
53}

55static bool getConstantValue(SDValue N, uint32_t &Out) {
// This is only used for packed vectors, where ussing 0 for undef should
// always be good.
if (N.isUndef()) {
  Out = 0;
  return true;
}

if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
  Out = C->getAPIntValue().getSExtValue();
  return true;
}

if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N)) {
  Out = C->getValueAPF().bitcastToAPInt().getSExtValue();
  return true;
}

return false;
74}

76// TODO: Handle undef as zero
77static SDNode *packConstantV2I16(const SDNode *N, SelectionDAG &DAG,
                               bool Negate = false) {
assert(N->getOpcode() == ISD::BUILD_VECTOR && N->getNumOperands() == 2)((void)0);
uint32_t LHSVal, RHSVal;
if (getConstantValue(N->getOperand(0), LHSVal) &&
    getConstantValue(N->getOperand(1), RHSVal)) {
  SDLoc SL(N);
  uint32_t K = Negate ?
    (-LHSVal & 0xffff) | (-RHSVal << 16) :
    (LHSVal & 0xffff) | (RHSVal << 16);
  return DAG.getMachineNode(AMDGPU::S_MOV_B32, SL, N->getValueType(0),
                            DAG.getTargetConstant(K, SL, MVT::i32));
}

return nullptr;
92}

94static SDNode *packNegConstantV2I16(const SDNode *N, SelectionDAG &DAG) {
return packConstantV2I16(N, DAG, true);
96}

98/// AMDGPU specific code to select AMDGPU machine instructions for
99/// SelectionDAG operations.
100class AMDGPUDAGToDAGISel : public SelectionDAGISel {
// Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
// make the right decision when generating code for different targets.
const GCNSubtarget *Subtarget;

// Default FP mode for the current function.
AMDGPU::SIModeRegisterDefaults Mode;

bool EnableLateStructurizeCFG;

// Instructions that will be lowered with a final instruction that zeros the
// high result bits.
bool fp16SrcZerosHighBits(unsigned Opc) const;

114public:
explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr,
                            CodeGenOpt::Level OptLevel = CodeGenOpt::Default)
  : SelectionDAGISel(*TM, OptLevel) {
  EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG;
}
~AMDGPUDAGToDAGISel() override = default;

void getAnalysisUsage(AnalysisUsage &AU) const override {
  AU.addRequired<AMDGPUArgumentUsageInfo>();
  AU.addRequired<LegacyDivergenceAnalysis>();
125#ifdef EXPENSIVE_CHECKS
  AU.addRequired<DominatorTreeWrapperPass>();
  AU.addRequired<LoopInfoWrapperPass>();
128#endif
  SelectionDAGISel::getAnalysisUsage(AU);
}

bool matchLoadD16FromBuildVector(SDNode *N) const;

bool runOnMachineFunction(MachineFunction &MF) override;
void PreprocessISelDAG() override;
void Select(SDNode *N) override;
StringRef getPassName() const override;
void PostprocessISelDAG() override;

140protected:
void SelectBuildVector(SDNode *N, unsigned RegClassID);

143private:
std::pair<SDValue, SDValue> foldFrameIndex(SDValue N) const;
bool isNoNanSrc(SDValue N) const;
bool isInlineImmediate(const SDNode *N, bool Negated = false) const;
bool isNegInlineImmediate(const SDNode *N) const {
  return isInlineImmediate(N, true);
}

bool isInlineImmediate16(int64_t Imm) const {
  return AMDGPU::isInlinableLiteral16(Imm, Subtarget->hasInv2PiInlineImm());
}

bool isInlineImmediate32(int64_t Imm) const {
  return AMDGPU::isInlinableLiteral32(Imm, Subtarget->hasInv2PiInlineImm());
}

bool isInlineImmediate64(int64_t Imm) const {
  return AMDGPU::isInlinableLiteral64(Imm, Subtarget->hasInv2PiInlineImm());
}

bool isInlineImmediate(const APFloat &Imm) const {
  return Subtarget->getInstrInfo()->isInlineConstant(Imm);
}

bool isVGPRImm(const SDNode *N) const;
bool isUniformLoad(const SDNode *N) const;
bool isUniformBr(const SDNode *N) const;

bool isBaseWithConstantOffset64(SDValue Addr, SDValue &LHS,
                                SDValue &RHS) const;

MachineSDNode *buildSMovImm64(SDLoc &DL, uint64_t Val, EVT VT) const;

SDNode *glueCopyToOp(SDNode *N, SDValue NewChain, SDValue Glue) const;
SDNode *glueCopyToM0(SDNode *N, SDValue Val) const;
SDNode *glueCopyToM0LDSInit(SDNode *N) const;

const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
virtual bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
virtual bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
bool isDSOffsetLegal(SDValue Base, unsigned Offset) const;
bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1,
                      unsigned Size) const;
bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
                               SDValue &Offset1) const;
bool SelectDS128Bit8ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
                                SDValue &Offset1) const;
bool SelectDSReadWrite2(SDValue Ptr, SDValue &Base, SDValue &Offset0,
                        SDValue &Offset1, unsigned Size) const;
bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
                 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
                 SDValue &Idxen, SDValue &Addr64) const;
bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
                       SDValue &SOffset, SDValue &Offset) const;
bool SelectMUBUFScratchOffen(SDNode *Parent,
                             SDValue Addr, SDValue &RSrc, SDValue &VAddr,
                             SDValue &SOffset, SDValue &ImmOffset) const;
bool SelectMUBUFScratchOffset(SDNode *Parent,
                              SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
                              SDValue &Offset) const;

bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
                       SDValue &Offset) const;

bool SelectFlatOffsetImpl(SDNode *N, SDValue Addr, SDValue &VAddr,
                          SDValue &Offset, uint64_t FlatVariant) const;
bool SelectFlatOffset(SDNode *N, SDValue Addr, SDValue &VAddr,
                      SDValue &Offset) const;
bool SelectGlobalOffset(SDNode *N, SDValue Addr, SDValue &VAddr,
                        SDValue &Offset) const;
bool SelectScratchOffset(SDNode *N, SDValue Addr, SDValue &VAddr,
                         SDValue &Offset) const;
bool SelectGlobalSAddr(SDNode *N, SDValue Addr, SDValue &SAddr,
                       SDValue &VOffset, SDValue &Offset) const;
bool SelectScratchSAddr(SDNode *N, SDValue Addr, SDValue &SAddr,
                        SDValue &Offset) const;

bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
                      bool &Imm) const;
SDValue Expand32BitAddress(SDValue Addr) const;
bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
                bool &Imm) const;
bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
bool SelectSMRDBufferImm32(SDValue Addr, SDValue &Offset) const;
bool SelectMOVRELOffset(SDValue Index, SDValue &Base, SDValue &Offset) const;

bool SelectVOP3Mods_NNaN(SDValue In, SDValue &Src, SDValue &SrcMods) const;
bool SelectVOP3ModsImpl(SDValue In, SDValue &Src, unsigned &SrcMods,
                        bool AllowAbs = true) const;
bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
bool SelectVOP3BMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
bool SelectVOP3NoMods(SDValue In, SDValue &Src) const;
bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
                     SDValue &Clamp, SDValue &Omod) const;
bool SelectVOP3BMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
                      SDValue &Clamp, SDValue &Omod) const;
bool SelectVOP3NoMods0(SDValue In, SDValue &Src, SDValue &SrcMods,
                       SDValue &Clamp, SDValue &Omod) const;

bool SelectVOP3OMods(SDValue In, SDValue &Src,
                     SDValue &Clamp, SDValue &Omod) const;

bool SelectVOP3PMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;

bool SelectVOP3OpSel(SDValue In, SDValue &Src, SDValue &SrcMods) const;

bool SelectVOP3OpSelMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
bool SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src, unsigned &Mods) const;
bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;

SDValue getHi16Elt(SDValue In) const;

SDValue getMaterializedScalarImm32(int64_t Val, const SDLoc &DL) const;

void SelectADD_SUB_I64(SDNode *N);
void SelectAddcSubb(SDNode *N);
void SelectUADDO_USUBO(SDNode *N);
void SelectDIV_SCALE(SDNode *N);
void SelectMAD_64_32(SDNode *N);
void SelectFMA_W_CHAIN(SDNode *N);
void SelectFMUL_W_CHAIN(SDNode *N);

SDNode *getS_BFE(unsigned Opcode, const SDLoc &DL, SDValue Val,
                 uint32_t Offset, uint32_t Width);
void SelectS_BFEFromShifts(SDNode *N);
void SelectS_BFE(SDNode *N);
bool isCBranchSCC(const SDNode *N) const;
void SelectBRCOND(SDNode *N);
void SelectFMAD_FMA(SDNode *N);
void SelectATOMIC_CMP_SWAP(SDNode *N);
void SelectDSAppendConsume(SDNode *N, unsigned IntrID);
void SelectDS_GWS(SDNode *N, unsigned IntrID);
void SelectInterpP1F16(SDNode *N);
void SelectINTRINSIC_W_CHAIN(SDNode *N);
void SelectINTRINSIC_WO_CHAIN(SDNode *N);
void SelectINTRINSIC_VOID(SDNode *N);

284protected:
// Include the pieces autogenerated from the target description.
286#include "AMDGPUGenDAGISel.inc"
287};

289class R600DAGToDAGISel : public AMDGPUDAGToDAGISel {
const R600Subtarget *Subtarget;

bool isConstantLoad(const MemSDNode *N, int cbID) const;
bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
                                     SDValue& Offset);
296public:
explicit R600DAGToDAGISel(TargetMachine *TM, CodeGenOpt::Level OptLevel) :
    AMDGPUDAGToDAGISel(TM, OptLevel) {}

void Select(SDNode *N) override;

bool SelectADDRIndirect(SDValue Addr, SDValue &Base,
                        SDValue &Offset) override;
bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
                        SDValue &Offset) override;

bool runOnMachineFunction(MachineFunction &MF) override;

void PreprocessISelDAG() override {}

311protected:
// Include the pieces autogenerated from the target description.
313#include "R600GenDAGISel.inc"
314};

316static SDValue stripBitcast(SDValue Val) {
return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
318}

320// Figure out if this is really an extract of the high 16-bits of a dword.
321static bool isExtractHiElt(SDValue In, SDValue &Out) {
In = stripBitcast(In);
15
←
Value assigned to 'In.Node'→

if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
16
←
Calling 'SDValue::getOpcode'→
  if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(In.getOperand(1))) {
    if (!Idx->isOne())
      return false;
    Out = In.getOperand(0);
    return true;
  }
}

if (In.getOpcode() != ISD::TRUNCATE)
  return false;

SDValue Srl = In.getOperand(0);
if (Srl.getOpcode() == ISD::SRL) {
  if (ConstantSDNode *ShiftAmt = dyn_cast<ConstantSDNode>(Srl.getOperand(1))) {
    if (ShiftAmt->getZExtValue() == 16) {
      Out = stripBitcast(Srl.getOperand(0));
      return true;
    }
  }
}

return false;
347}

349// Look through operations that obscure just looking at the low 16-bits of the
350// same register.
351static SDValue stripExtractLoElt(SDValue In) {
if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
  if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(In.getOperand(1))) {
    if (Idx->isNullValue() && In.getValueSizeInBits() <= 32)
      return In.getOperand(0);
  }
}

if (In.getOpcode() == ISD::TRUNCATE) {
  SDValue Src = In.getOperand(0);
  if (Src.getValueType().getSizeInBits() == 32)
    return stripBitcast(Src);
}

return In;
366}

368}  // end anonymous namespace

370INITIALIZE_PASS_BEGIN(AMDGPUDAGToDAGISel, "amdgpu-isel",static void *initializeAMDGPUDAGToDAGISelPassOnce(PassRegistry
 &Registry) {
                    "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)static void *initializeAMDGPUDAGToDAGISelPassOnce(PassRegistry
 &Registry) {
372INITIALIZE_PASS_DEPENDENCY(AMDGPUArgumentUsageInfo)initializeAMDGPUArgumentUsageInfoPass(Registry);
373INITIALIZE_PASS_DEPENDENCY(AMDGPUPerfHintAnalysis)initializeAMDGPUPerfHintAnalysisPass(Registry);
374INITIALIZE_PASS_DEPENDENCY(LegacyDivergenceAnalysis)initializeLegacyDivergenceAnalysisPass(Registry);
375#ifdef EXPENSIVE_CHECKS
376INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)initializeDominatorTreeWrapperPassPass(Registry);
377INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)initializeLoopInfoWrapperPassPass(Registry);
378#endif
379INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "amdgpu-isel",PassInfo *PI = new PassInfo( "AMDGPU DAG->DAG Pattern Instruction Selection"
, "amdgpu-isel", &AMDGPUDAGToDAGISel::ID, PassInfo::NormalCtor_t
(callDefaultCtor<AMDGPUDAGToDAGISel>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
 InitializeAMDGPUDAGToDAGISelPassFlag; void llvm::initializeAMDGPUDAGToDAGISelPass
(PassRegistry &Registry) { llvm::call_once(InitializeAMDGPUDAGToDAGISelPassFlag
, initializeAMDGPUDAGToDAGISelPassOnce, std::ref(Registry)); }
                  "AMDGPU DAG->DAG Pattern Instruction Selection", false, false)PassInfo *PI = new PassInfo( "AMDGPU DAG->DAG Pattern Instruction Selection"
, "amdgpu-isel", &AMDGPUDAGToDAGISel::ID, PassInfo::NormalCtor_t
(callDefaultCtor<AMDGPUDAGToDAGISel>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
 InitializeAMDGPUDAGToDAGISelPassFlag; void llvm::initializeAMDGPUDAGToDAGISelPass
(PassRegistry &Registry) { llvm::call_once(InitializeAMDGPUDAGToDAGISelPassFlag
, initializeAMDGPUDAGToDAGISelPassOnce, std::ref(Registry)); }

382/// This pass converts a legalized DAG into a AMDGPU-specific
383// DAG, ready for instruction scheduling.
384FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
                                      CodeGenOpt::Level OptLevel) {
return new AMDGPUDAGToDAGISel(TM, OptLevel);
387}

389/// This pass converts a legalized DAG into a R600-specific
390// DAG, ready for instruction scheduling.
391FunctionPass *llvm::createR600ISelDag(TargetMachine *TM,
                                    CodeGenOpt::Level OptLevel) {
return new R600DAGToDAGISel(TM, OptLevel);
394}

396bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
397#ifdef EXPENSIVE_CHECKS
DominatorTree & DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
LoopInfo * LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
for (auto &L : LI->getLoopsInPreorder()) {
  assert(L->isLCSSAForm(DT))((void)0);
}
403#endif
Subtarget = &MF.getSubtarget<GCNSubtarget>();
Mode = AMDGPU::SIModeRegisterDefaults(MF.getFunction());
return SelectionDAGISel::runOnMachineFunction(MF);
407}

409bool AMDGPUDAGToDAGISel::fp16SrcZerosHighBits(unsigned Opc) const {
// XXX - only need to list legal operations.
switch (Opc) {
case ISD::FADD:
case ISD::FSUB:
case ISD::FMUL:
case ISD::FDIV:
case ISD::FREM:
case ISD::FCANONICALIZE:
case ISD::UINT_TO_FP:
case ISD::SINT_TO_FP:
case ISD::FABS:
  // Fabs is lowered to a bit operation, but it's an and which will clear the
  // high bits anyway.
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
case ISD::FPOWI:
case ISD::FPOW:
case ISD::FLOG:
case ISD::FLOG2:
case ISD::FLOG10:
case ISD::FEXP:
case ISD::FEXP2:
case ISD::FCEIL:
case ISD::FTRUNC:
case ISD::FRINT:
case ISD::FNEARBYINT:
case ISD::FROUND:
case ISD::FFLOOR:
case ISD::FMINNUM:
case ISD::FMAXNUM:
case AMDGPUISD::FRACT:
case AMDGPUISD::CLAMP:
case AMDGPUISD::COS_HW:
case AMDGPUISD::SIN_HW:
case AMDGPUISD::FMIN3:
case AMDGPUISD::FMAX3:
case AMDGPUISD::FMED3:
case AMDGPUISD::FMAD_FTZ:
case AMDGPUISD::RCP:
case AMDGPUISD::RSQ:
case AMDGPUISD::RCP_IFLAG:
case AMDGPUISD::LDEXP:
  // On gfx10, all 16-bit instructions preserve the high bits.
  return Subtarget->getGeneration() <= AMDGPUSubtarget::GFX9;
case ISD::FP_ROUND:
  // We may select fptrunc (fma/mad) to mad_mixlo, which does not zero the
  // high bits on gfx9.
  // TODO: If we had the source node we could see if the source was fma/mad
  return Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS;
case ISD::FMA:
case ISD::FMAD:
case AMDGPUISD::DIV_FIXUP:
  return Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS;
default:
  // fcopysign, select and others may be lowered to 32-bit bit operations
  // which don't zero the high bits.
  return false;
}
469}

471bool AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(SDNode *N) const {
assert(Subtarget->d16PreservesUnusedBits())((void)0);
MVT VT = N->getValueType(0).getSimpleVT();
if (VT != MVT::v2i16 && VT != MVT::v2f16)
6
←
Taking false branch→
  return false;

SDValue Lo = N->getOperand(0);
SDValue Hi = N->getOperand(1);

LoadSDNode *LdHi = dyn_cast<LoadSDNode>(stripBitcast(Hi));

// build_vector lo, (load ptr) -> load_d16_hi ptr, lo
// build_vector lo, (zextload ptr from i8) -> load_d16_hi_u8 ptr, lo
// build_vector lo, (sextload ptr from i8) -> load_d16_hi_i8 ptr, lo

// Need to check for possible indirect dependencies on the other half of the
// vector to avoid introducing a cycle.
if (LdHi && Hi.hasOneUse() && !LdHi->isPredecessorOf(Lo.getNode())) {
7
←
Assuming 'LdHi' is null→
  SDVTList VTList = CurDAG->getVTList(VT, MVT::Other);

  SDValue TiedIn = CurDAG->getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), VT, Lo);
  SDValue Ops[] = {
    LdHi->getChain(), LdHi->getBasePtr(), TiedIn
  };

  unsigned LoadOp = AMDGPUISD::LOAD_D16_HI;
  if (LdHi->getMemoryVT() == MVT::i8) {
    LoadOp = LdHi->getExtensionType() == ISD::SEXTLOAD ?
      AMDGPUISD::LOAD_D16_HI_I8 : AMDGPUISD::LOAD_D16_HI_U8;
  } else {
    assert(LdHi->getMemoryVT() == MVT::i16)((void)0);
  }

  SDValue NewLoadHi =
    CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdHi), VTList,
                                Ops, LdHi->getMemoryVT(),
                                LdHi->getMemOperand());

  CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewLoadHi);
  CurDAG->ReplaceAllUsesOfValueWith(SDValue(LdHi, 1), NewLoadHi.getValue(1));
  return true;
}

// build_vector (load ptr), hi -> load_d16_lo ptr, hi
// build_vector (zextload ptr from i8), hi -> load_d16_lo_u8 ptr, hi
// build_vector (sextload ptr from i8), hi -> load_d16_lo_i8 ptr, hi
LoadSDNode *LdLo = dyn_cast<LoadSDNode>(stripBitcast(Lo));
if (LdLo7.1
'LdLo' is non-null
1
'LdLo' is non-null
 && Lo.hasOneUse()) {
8
←
Assuming the condition is true→
9
←
Taking true branch→
  SDValue TiedIn = getHi16Elt(Hi);
10
←
Calling 'AMDGPUDAGToDAGISel::getHi16Elt'→
  if (!TiedIn || LdLo->isPredecessorOf(TiedIn.getNode()))
    return false;

  SDVTList VTList = CurDAG->getVTList(VT, MVT::Other);
  unsigned LoadOp = AMDGPUISD::LOAD_D16_LO;
  if (LdLo->getMemoryVT() == MVT::i8) {
    LoadOp = LdLo->getExtensionType() == ISD::SEXTLOAD ?
      AMDGPUISD::LOAD_D16_LO_I8 : AMDGPUISD::LOAD_D16_LO_U8;
  } else {
    assert(LdLo->getMemoryVT() == MVT::i16)((void)0);
  }

  TiedIn = CurDAG->getNode(ISD::BITCAST, SDLoc(N), VT, TiedIn);

  SDValue Ops[] = {
    LdLo->getChain(), LdLo->getBasePtr(), TiedIn
  };

  SDValue NewLoadLo =
    CurDAG->getMemIntrinsicNode(LoadOp, SDLoc(LdLo), VTList,
                                Ops, LdLo->getMemoryVT(),
                                LdLo->getMemOperand());

  CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewLoadLo);
  CurDAG->ReplaceAllUsesOfValueWith(SDValue(LdLo, 1), NewLoadLo.getValue(1));
  return true;
}

return false;
549}

551void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
if (!Subtarget->d16PreservesUnusedBits())
1
Taking false branch→
  return;

SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();

bool MadeChange = false;
while (Position != CurDAG->allnodes_begin()) {
2
←
Loop condition is true.  Entering loop body→
  SDNode *N = &*--Position;
  if (N->use_empty())
3
←
Taking false branch→
    continue;

  switch (N->getOpcode()) {
4
←
Control jumps to 'case BUILD_VECTOR:'  at line 564→
  case ISD::BUILD_VECTOR:
    MadeChange |= matchLoadD16FromBuildVector(N);
5
←
Calling 'AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector'→
    break;
  default:
    break;
  }
}

if (MadeChange) {
  CurDAG->RemoveDeadNodes();
  LLVM_DEBUG(dbgs() << "After PreProcess:\n";do { } while (false)
             CurDAG->dump();)do { } while (false);
}
577}

579bool AMDGPUDAGToDAGISel::isNoNanSrc(SDValue N) const {
if (TM.Options.NoNaNsFPMath)
  return true;

// TODO: Move into isKnownNeverNaN
if (N->getFlags().hasNoNaNs())
  return true;

return CurDAG->isKnownNeverNaN(N);
588}

590bool AMDGPUDAGToDAGISel::isInlineImmediate(const SDNode *N,
                                         bool Negated) const {
if (N->isUndef())
  return true;

const SIInstrInfo *TII = Subtarget->getInstrInfo();
if (Negated) {
  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N))
    return TII->isInlineConstant(-C->getAPIntValue());

  if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
    return TII->isInlineConstant(-C->getValueAPF().bitcastToAPInt());

} else {
  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N))
    return TII->isInlineConstant(C->getAPIntValue());

  if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
    return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt());
}

return false;
612}

614/// Determine the register class for \p OpNo
615/// \returns The register class of the virtual register that will be used for
616/// the given operand number \OpNo or NULL if the register class cannot be
617/// determined.
618const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
                                                        unsigned OpNo) const {
if (!N->isMachineOpcode()) {
  if (N->getOpcode() == ISD::CopyToReg) {
    Register Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
    if (Reg.isVirtual()) {
      MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();
      return MRI.getRegClass(Reg);
    }

    const SIRegisterInfo *TRI
      = static_cast<const GCNSubtarget *>(Subtarget)->getRegisterInfo();
    return TRI->getPhysRegClass(Reg);
  }

  return nullptr;
}

switch (N->getMachineOpcode()) {
default: {
  const MCInstrDesc &Desc =
      Subtarget->getInstrInfo()->get(N->getMachineOpcode());
  unsigned OpIdx = Desc.getNumDefs() + OpNo;
  if (OpIdx >= Desc.getNumOperands())
    return nullptr;
  int RegClass = Desc.OpInfo[OpIdx].RegClass;
  if (RegClass == -1)
    return nullptr;

  return Subtarget->getRegisterInfo()->getRegClass(RegClass);
}
case AMDGPU::REG_SEQUENCE: {
  unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
  const TargetRegisterClass *SuperRC =
      Subtarget->getRegisterInfo()->getRegClass(RCID);

  SDValue SubRegOp = N->getOperand(OpNo + 1);
  unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
  return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
                                                            SubRegIdx);
}
}
660}

662SDNode *AMDGPUDAGToDAGISel::glueCopyToOp(SDNode *N, SDValue NewChain,
                                       SDValue Glue) const {
SmallVector <SDValue, 8> Ops;
Ops.push_back(NewChain); // Replace the chain.
for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
  Ops.push_back(N->getOperand(i));

Ops.push_back(Glue);
return CurDAG->MorphNodeTo(N, N->getOpcode(), N->getVTList(), Ops);
671}

673SDNode *AMDGPUDAGToDAGISel::glueCopyToM0(SDNode *N, SDValue Val) const {
const SITargetLowering& Lowering =
  *static_cast<const SITargetLowering*>(getTargetLowering());

assert(N->getOperand(0).getValueType() == MVT::Other && "Expected chain")((void)0);

SDValue M0 = Lowering.copyToM0(*CurDAG, N->getOperand(0), SDLoc(N), Val);
return glueCopyToOp(N, M0, M0.getValue(1));
681}

683SDNode *AMDGPUDAGToDAGISel::glueCopyToM0LDSInit(SDNode *N) const {
unsigned AS = cast<MemSDNode>(N)->getAddressSpace();
if (AS == AMDGPUAS::LOCAL_ADDRESS) {
  if (Subtarget->ldsRequiresM0Init())
    return glueCopyToM0(N, CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
} else if (AS == AMDGPUAS::REGION_ADDRESS) {
  MachineFunction &MF = CurDAG->getMachineFunction();
  unsigned Value = MF.getInfo<SIMachineFunctionInfo>()->getGDSSize();
  return
      glueCopyToM0(N, CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i32));
}
return N;
695}

697MachineSDNode *AMDGPUDAGToDAGISel::buildSMovImm64(SDLoc &DL, uint64_t Imm,
                                                EVT VT) const {
SDNode *Lo = CurDAG->getMachineNode(
    AMDGPU::S_MOV_B32, DL, MVT::i32,
    CurDAG->getTargetConstant(Imm & 0xFFFFFFFF, DL, MVT::i32));
SDNode *Hi =
    CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
                           CurDAG->getTargetConstant(Imm >> 32, DL, MVT::i32));
const SDValue Ops[] = {
    CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
    SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
    SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)};

return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, VT, Ops);
711}

713void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
EVT VT = N->getValueType(0);
unsigned NumVectorElts = VT.getVectorNumElements();
EVT EltVT = VT.getVectorElementType();
SDLoc DL(N);
SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);

if (NumVectorElts == 1) {
  CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT, N->getOperand(0),
                       RegClass);
  return;
}

assert(NumVectorElts <= 32 && "Vectors with more than 32 elements not "((void)0)
                                "supported yet")((void)0);
// 32 = Max Num Vector Elements
// 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
// 1 = Vector Register Class
SmallVector<SDValue, 32 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);

bool IsGCN = CurDAG->getSubtarget().getTargetTriple().getArch() ==
             Triple::amdgcn;
RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
bool IsRegSeq = true;
unsigned NOps = N->getNumOperands();
for (unsigned i = 0; i < NOps; i++) {
  // XXX: Why is this here?
  if (isa<RegisterSDNode>(N->getOperand(i))) {
    IsRegSeq = false;
    break;
  }
  unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i)
                       : R600RegisterInfo::getSubRegFromChannel(i);
  RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
  RegSeqArgs[1 + (2 * i) + 1] = CurDAG->getTargetConstant(Sub, DL, MVT::i32);
}
if (NOps != NumVectorElts) {
  // Fill in the missing undef elements if this was a scalar_to_vector.
  assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts)((void)0);
  MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
                                                 DL, EltVT);
  for (unsigned i = NOps; i < NumVectorElts; ++i) {
    unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i)
                         : R600RegisterInfo::getSubRegFromChannel(i);
    RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
    RegSeqArgs[1 + (2 * i) + 1] =
        CurDAG->getTargetConstant(Sub, DL, MVT::i32);
  }
}

if (!IsRegSeq)
  SelectCode(N);
CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(), RegSeqArgs);
766}

768void AMDGPUDAGToDAGISel::Select(SDNode *N) {
unsigned int Opc = N->getOpcode();
if (N->isMachineOpcode()) {
  N->setNodeId(-1);
  return;   // Already selected.
}

// isa<MemSDNode> almost works but is slightly too permissive for some DS
// intrinsics.
if (Opc == ISD::LOAD || Opc == ISD::STORE || isa<AtomicSDNode>(N) ||
    (Opc == AMDGPUISD::ATOMIC_INC || Opc == AMDGPUISD::ATOMIC_DEC ||
     Opc == ISD::ATOMIC_LOAD_FADD ||
     Opc == AMDGPUISD::ATOMIC_LOAD_FMIN ||
     Opc == AMDGPUISD::ATOMIC_LOAD_FMAX)) {
  N = glueCopyToM0LDSInit(N);
  SelectCode(N);
  return;
}

switch (Opc) {
default:
  break;
// We are selecting i64 ADD here instead of custom lower it during
// DAG legalization, so we can fold some i64 ADDs used for address
// calculation into the LOAD and STORE instructions.
case ISD::ADDC:
case ISD::ADDE:
case ISD::SUBC:
case ISD::SUBE: {
  if (N->getValueType(0) != MVT::i64)
    break;

  SelectADD_SUB_I64(N);
  return;
}
case ISD::ADDCARRY:
case ISD::SUBCARRY:
  if (N->getValueType(0) != MVT::i32)
    break;

  SelectAddcSubb(N);
  return;
case ISD::UADDO:
case ISD::USUBO: {
  SelectUADDO_USUBO(N);
  return;
}
case AMDGPUISD::FMUL_W_CHAIN: {
  SelectFMUL_W_CHAIN(N);
  return;
}
case AMDGPUISD::FMA_W_CHAIN: {
  SelectFMA_W_CHAIN(N);
  return;
}

case ISD::SCALAR_TO_VECTOR:
case ISD::BUILD_VECTOR: {
  EVT VT = N->getValueType(0);
  unsigned NumVectorElts = VT.getVectorNumElements();
  if (VT.getScalarSizeInBits() == 16) {
    if (Opc == ISD::BUILD_VECTOR && NumVectorElts == 2) {
      if (SDNode *Packed = packConstantV2I16(N, *CurDAG)) {
        ReplaceNode(N, Packed);
        return;
      }
    }

    break;
  }

  assert(VT.getVectorElementType().bitsEq(MVT::i32))((void)0);
  unsigned RegClassID =
      SIRegisterInfo::getSGPRClassForBitWidth(NumVectorElts * 32)->getID();
  SelectBuildVector(N, RegClassID);
  return;
}
case ISD::BUILD_PAIR: {
  SDValue RC, SubReg0, SubReg1;
  SDLoc DL(N);
  if (N->getValueType(0) == MVT::i128) {
    RC = CurDAG->getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32);
    SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
    SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
  } else if (N->getValueType(0) == MVT::i64) {
    RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32);
    SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
    SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);
  } else {
    llvm_unreachable("Unhandled value type for BUILD_PAIR")__builtin_unreachable();
  }
  const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
                          N->getOperand(1), SubReg1 };
  ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
                                        N->getValueType(0), Ops));
  return;
}

case ISD::Constant:
case ISD::ConstantFP: {
  if (N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
    break;

  uint64_t Imm;
  if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
    Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
  else {
    ConstantSDNode *C = cast<ConstantSDNode>(N);
    Imm = C->getZExtValue();
  }

  SDLoc DL(N);
  ReplaceNode(N, buildSMovImm64(DL, Imm, N->getValueType(0)));
  return;
}
case AMDGPUISD::BFE_I32:
case AMDGPUISD::BFE_U32: {
  // There is a scalar version available, but unlike the vector version which
  // has a separate operand for the offset and width, the scalar version packs
  // the width and offset into a single operand. Try to move to the scalar
  // version if the offsets are constant, so that we can try to keep extended
  // loads of kernel arguments in SGPRs.

  // TODO: Technically we could try to pattern match scalar bitshifts of
  // dynamic values, but it's probably not useful.
  ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
  if (!Offset)
    break;

  ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
  if (!Width)
    break;

  bool Signed = Opc == AMDGPUISD::BFE_I32;

  uint32_t OffsetVal = Offset->getZExtValue();
  uint32_t WidthVal = Width->getZExtValue();

  ReplaceNode(N, getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
                          SDLoc(N), N->getOperand(0), OffsetVal, WidthVal));
  return;
}
case AMDGPUISD::DIV_SCALE: {
  SelectDIV_SCALE(N);
  return;
}
case AMDGPUISD::MAD_I64_I32:
case AMDGPUISD::MAD_U64_U32: {
  SelectMAD_64_32(N);
  return;
}
case ISD::CopyToReg: {
  const SITargetLowering& Lowering =
    *static_cast<const SITargetLowering*>(getTargetLowering());
  N = Lowering.legalizeTargetIndependentNode(N, *CurDAG);
  break;
}
case ISD::AND:
case ISD::SRL:
case ISD::SRA:
case ISD::SIGN_EXTEND_INREG:
  if (N->getValueType(0) != MVT::i32)
    break;

  SelectS_BFE(N);
  return;
case ISD::BRCOND:
  SelectBRCOND(N);
  return;
case ISD::FMAD:
case ISD::FMA:
  SelectFMAD_FMA(N);
  return;
case AMDGPUISD::ATOMIC_CMP_SWAP:
  SelectATOMIC_CMP_SWAP(N);
  return;
case AMDGPUISD::CVT_PKRTZ_F16_F32:
case AMDGPUISD::CVT_PKNORM_I16_F32:
case AMDGPUISD::CVT_PKNORM_U16_F32:
case AMDGPUISD::CVT_PK_U16_U32:
case AMDGPUISD::CVT_PK_I16_I32: {
  // Hack around using a legal type if f16 is illegal.
  if (N->getValueType(0) == MVT::i32) {
    MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16;
    N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT),
                            { N->getOperand(0), N->getOperand(1) });
    SelectCode(N);
    return;
  }

  break;
}
case ISD::INTRINSIC_W_CHAIN: {
  SelectINTRINSIC_W_CHAIN(N);
  return;
}
case ISD::INTRINSIC_WO_CHAIN: {
  SelectINTRINSIC_WO_CHAIN(N);
  return;
}
case ISD::INTRINSIC_VOID: {
  SelectINTRINSIC_VOID(N);
  return;
}
}

SelectCode(N);
975}

977bool AMDGPUDAGToDAGISel::isUniformBr(const SDNode *N) const {
const BasicBlock *BB = FuncInfo->MBB->getBasicBlock();
const Instruction *Term = BB->getTerminator();
return Term->getMetadata("amdgpu.uniform") ||
       Term->getMetadata("structurizecfg.uniform");
982}

984static bool getBaseWithOffsetUsingSplitOR(SelectionDAG &DAG, SDValue Addr,
                                        SDValue &N0, SDValue &N1) {
if (Addr.getValueType() == MVT::i64 && Addr.getOpcode() == ISD::BITCAST &&
    Addr.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
  // As we split 64-bit `or` earlier, it's complicated pattern to match, i.e.
  // (i64 (bitcast (v2i32 (build_vector
  //                        (or (extract_vector_elt V, 0), OFFSET),
  //                        (extract_vector_elt V, 1)))))
  SDValue Lo = Addr.getOperand(0).getOperand(0);
  if (Lo.getOpcode() == ISD::OR && DAG.isBaseWithConstantOffset(Lo)) {
    SDValue BaseLo = Lo.getOperand(0);
    SDValue BaseHi = Addr.getOperand(0).getOperand(1);
    // Check that split base (Lo and Hi) are extracted from the same one.
    if (BaseLo.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
        BaseHi.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
        BaseLo.getOperand(0) == BaseHi.getOperand(0) &&
        // Lo is statically extracted from index 0.
        isa<ConstantSDNode>(BaseLo.getOperand(1)) &&
        BaseLo.getConstantOperandVal(1) == 0 &&
        // Hi is statically extracted from index 0.
        isa<ConstantSDNode>(BaseHi.getOperand(1)) &&
        BaseHi.getConstantOperandVal(1) == 1) {
      N0 = BaseLo.getOperand(0).getOperand(0);
      N1 = Lo.getOperand(1);
      return true;
    }
  }
}
return false;
1013}

1015bool AMDGPUDAGToDAGISel::isBaseWithConstantOffset64(SDValue Addr, SDValue &LHS,
                                                  SDValue &RHS) const {
if (CurDAG->isBaseWithConstantOffset(Addr)) {
  LHS = Addr.getOperand(0);
  RHS = Addr.getOperand(1);
  return true;
}

if (getBaseWithOffsetUsingSplitOR(*CurDAG, Addr, LHS, RHS)) {
  assert(LHS && RHS && isa<ConstantSDNode>(RHS))((void)0);
  return true;
}

return false;
1029}

1031StringRef AMDGPUDAGToDAGISel::getPassName() const {
return "AMDGPU DAG->DAG Pattern Instruction Selection";
1033}

1035//===----------------------------------------------------------------------===//
1036// Complex Patterns
1037//===----------------------------------------------------------------------===//

1039bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
                                          SDValue &Offset) {
return false;
1042}

1044bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
                                          SDValue &Offset) {
ConstantSDNode *C;
SDLoc DL(Addr);

if ((C = dyn_cast<ConstantSDNode>(Addr))) {
  Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
  Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
} else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
           (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) {
  Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
  Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
} else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
          (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
  Base = Addr.getOperand(0);
  Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
} else {
  Base = Addr;
  Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
}

return true;
1066}

1068SDValue AMDGPUDAGToDAGISel::getMaterializedScalarImm32(int64_t Val,
                                                     const SDLoc &DL) const {
SDNode *Mov = CurDAG->getMachineNode(
  AMDGPU::S_MOV_B32, DL, MVT::i32,
  CurDAG->getTargetConstant(Val, DL, MVT::i32));
return SDValue(Mov, 0);
1074}

1076// FIXME: Should only handle addcarry/subcarry
1077void AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
SDLoc DL(N);
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);

unsigned Opcode = N->getOpcode();
bool ConsumeCarry = (Opcode == ISD::ADDE || Opcode == ISD::SUBE);
bool ProduceCarry =
    ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC;
bool IsAdd = Opcode == ISD::ADD || Opcode == ISD::ADDC || Opcode == ISD::ADDE;

SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);

SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
                                     DL, MVT::i32, LHS, Sub0);
SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
                                     DL, MVT::i32, LHS, Sub1);

SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
                                     DL, MVT::i32, RHS, Sub0);
SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
                                     DL, MVT::i32, RHS, Sub1);

SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);

static const unsigned OpcMap[2][2][2] = {
    {{AMDGPU::S_SUB_U32, AMDGPU::S_ADD_U32},
     {AMDGPU::V_SUB_CO_U32_e32, AMDGPU::V_ADD_CO_U32_e32}},
    {{AMDGPU::S_SUBB_U32, AMDGPU::S_ADDC_U32},
     {AMDGPU::V_SUBB_U32_e32, AMDGPU::V_ADDC_U32_e32}}};

unsigned Opc = OpcMap[0][N->isDivergent()][IsAdd];
unsigned CarryOpc = OpcMap[1][N->isDivergent()][IsAdd];

SDNode *AddLo;
if (!ConsumeCarry) {
  SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
  AddLo = CurDAG->getMachineNode(Opc, DL, VTList, Args);
} else {
  SDValue Args[] = { SDValue(Lo0, 0), SDValue(Lo1, 0), N->getOperand(2) };
  AddLo = CurDAG->getMachineNode(CarryOpc, DL, VTList, Args);
}
SDValue AddHiArgs[] = {
  SDValue(Hi0, 0),
  SDValue(Hi1, 0),
  SDValue(AddLo, 1)
};
SDNode *AddHi = CurDAG->getMachineNode(CarryOpc, DL, VTList, AddHiArgs);

SDValue RegSequenceArgs[] = {
  CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32),
  SDValue(AddLo,0),
  Sub0,
  SDValue(AddHi,0),
  Sub1,
};
SDNode *RegSequence = CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
                                             MVT::i64, RegSequenceArgs);

if (ProduceCarry) {
  // Replace the carry-use
  ReplaceUses(SDValue(N, 1), SDValue(AddHi, 1));
}

// Replace the remaining uses.
ReplaceNode(N, RegSequence);
1144}

1146void AMDGPUDAGToDAGISel::SelectAddcSubb(SDNode *N) {
SDLoc DL(N);
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue CI = N->getOperand(2);

if (N->isDivergent()) {
  unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64
                                                 : AMDGPU::V_SUBB_U32_e64;
  CurDAG->SelectNodeTo(
      N, Opc, N->getVTList(),
      {LHS, RHS, CI,
       CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
} else {
  unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::S_ADD_CO_PSEUDO
                                                 : AMDGPU::S_SUB_CO_PSEUDO;
  CurDAG->SelectNodeTo(N, Opc, N->getVTList(), {LHS, RHS, CI});
}
1164}

1166void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) {
// The name of the opcodes are misleading. v_add_i32/v_sub_i32 have unsigned
// carry out despite the _i32 name. These were renamed in VI to _U32.
// FIXME: We should probably rename the opcodes here.
bool IsAdd = N->getOpcode() == ISD::UADDO;
bool IsVALU = N->isDivergent();

for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;
     ++UI)
  if (UI.getUse().getResNo() == 1) {
    if ((IsAdd && (UI->getOpcode() != ISD::ADDCARRY)) ||
        (!IsAdd && (UI->getOpcode() != ISD::SUBCARRY))) {
      IsVALU = true;
      break;
    }
  }

if (IsVALU) {
  unsigned Opc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;

  CurDAG->SelectNodeTo(
      N, Opc, N->getVTList(),
      {N->getOperand(0), N->getOperand(1),
       CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
} else {
  unsigned Opc = N->getOpcode() == ISD::UADDO ? AMDGPU::S_UADDO_PSEUDO
                                              : AMDGPU::S_USUBO_PSEUDO;

  CurDAG->SelectNodeTo(N, Opc, N->getVTList(),
                       {N->getOperand(0), N->getOperand(1)});
}
1197}

1199void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
SDLoc SL(N);
//  src0_modifiers, src0,  src1_modifiers, src1, src2_modifiers, src2, clamp, omod
SDValue Ops[10];

SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[6], Ops[7]);
SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
SelectVOP3Mods(N->getOperand(3), Ops[5], Ops[4]);
Ops[8] = N->getOperand(0);
Ops[9] = N->getOperand(4);

CurDAG->SelectNodeTo(N, AMDGPU::V_FMA_F32_e64, N->getVTList(), Ops);
1211}

1213void AMDGPUDAGToDAGISel::SelectFMUL_W_CHAIN(SDNode *N) {
SDLoc SL(N);
//    src0_modifiers, src0,  src1_modifiers, src1, clamp, omod
SDValue Ops[8];

SelectVOP3Mods0(N->getOperand(1), Ops[1], Ops[0], Ops[4], Ops[5]);
SelectVOP3Mods(N->getOperand(2), Ops[3], Ops[2]);
Ops[6] = N->getOperand(0);
Ops[7] = N->getOperand(3);

CurDAG->SelectNodeTo(N, AMDGPU::V_MUL_F32_e64, N->getVTList(), Ops);
1224}

1226// We need to handle this here because tablegen doesn't support matching
1227// instructions with multiple outputs.
1228void AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
SDLoc SL(N);
EVT VT = N->getValueType(0);

assert(VT == MVT::f32 || VT == MVT::f64)((void)0);

unsigned Opc
  = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64_e64 : AMDGPU::V_DIV_SCALE_F32_e64;

// src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp,
// omod
SDValue Ops[8];
SelectVOP3BMods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
SelectVOP3BMods(N->getOperand(1), Ops[3], Ops[2]);
SelectVOP3BMods(N->getOperand(2), Ops[5], Ops[4]);
CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
1244}

1246// We need to handle this here because tablegen doesn't support matching
1247// instructions with multiple outputs.
1248void AMDGPUDAGToDAGISel::SelectMAD_64_32(SDNode *N) {
SDLoc SL(N);
bool Signed = N->getOpcode() == AMDGPUISD::MAD_I64_I32;
unsigned Opc = Signed ? AMDGPU::V_MAD_I64_I32_e64 : AMDGPU::V_MAD_U64_U32_e64;

SDValue Clamp = CurDAG->getTargetConstant(0, SL, MVT::i1);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
                  Clamp };
CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
1257}

1259bool AMDGPUDAGToDAGISel::isDSOffsetLegal(SDValue Base, unsigned Offset) const {
if (!isUInt<16>(Offset))
  return false;

if (!Base || Subtarget->hasUsableDSOffset() ||
    Subtarget->unsafeDSOffsetFoldingEnabled())
  return true;

// On Southern Islands instruction with a negative base value and an offset
// don't seem to work.
return CurDAG->SignBitIsZero(Base);
1270}

1272bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
                                            SDValue &Offset) const {
SDLoc DL(Addr);
if (CurDAG->isBaseWithConstantOffset(Addr)) {
  SDValue N0 = Addr.getOperand(0);
  SDValue N1 = Addr.getOperand(1);
  ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
  if (isDSOffsetLegal(N0, C1->getSExtValue())) {
    // (add n0, c0)
    Base = N0;
    Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
    return true;
  }
} else if (Addr.getOpcode() == ISD::SUB) {
  // sub C, x -> add (sub 0, x), C
  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
    int64_t ByteOffset = C->getSExtValue();
    if (isDSOffsetLegal(SDValue(), ByteOffset)) {
      SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);

      // XXX - This is kind of hacky. Create a dummy sub node so we can check
      // the known bits in isDSOffsetLegal. We need to emit the selected node
      // here, so this is thrown away.
      SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
                                    Zero, Addr.getOperand(1));

      if (isDSOffsetLegal(Sub, ByteOffset)) {
        SmallVector<SDValue, 3> Opnds;
        Opnds.push_back(Zero);
        Opnds.push_back(Addr.getOperand(1));

        // FIXME: Select to VOP3 version for with-carry.
        unsigned SubOp = AMDGPU::V_SUB_CO_U32_e32;
        if (Subtarget->hasAddNoCarry()) {
          SubOp = AMDGPU::V_SUB_U32_e64;
          Opnds.push_back(
              CurDAG->getTargetConstant(0, {}, MVT::i1)); // clamp bit
        }

        MachineSDNode *MachineSub =
            CurDAG->getMachineNode(SubOp, DL, MVT::i32, Opnds);

        Base = SDValue(MachineSub, 0);
        Offset = CurDAG->getTargetConstant(ByteOffset, DL, MVT::i16);
        return true;
      }
    }
  }
} else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
  // If we have a constant address, prefer to put the constant into the
  // offset. This can save moves to load the constant address since multiple
  // operations can share the zero base address register, and enables merging
  // into read2 / write2 instructions.

  SDLoc DL(Addr);

  if (isDSOffsetLegal(SDValue(), CAddr->getZExtValue())) {
    SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
    MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
                               DL, MVT::i32, Zero);
    Base = SDValue(MovZero, 0);
    Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
    return true;
  }
}

// default case
Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i16);
return true;
1342}

1344bool AMDGPUDAGToDAGISel::isDSOffset2Legal(SDValue Base, unsigned Offset0,
                                        unsigned Offset1,
                                        unsigned Size) const {
if (Offset0 % Size != 0 || Offset1 % Size != 0)
  return false;
if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size))
  return false;

if (!Base || Subtarget->hasUsableDSOffset() ||
    Subtarget->unsafeDSOffsetFoldingEnabled())
  return true;

// On Southern Islands instruction with a negative base value and an offset
// don't seem to work.
return CurDAG->SignBitIsZero(Base);
1359}

1361// TODO: If offset is too big, put low 16-bit into offset.
1362bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
                                                 SDValue &Offset0,
                                                 SDValue &Offset1) const {
return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4);
1366}

1368bool AMDGPUDAGToDAGISel::SelectDS128Bit8ByteAligned(SDValue Addr, SDValue &Base,
                                                  SDValue &Offset0,
                                                  SDValue &Offset1) const {
return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 8);
1372}

1374bool AMDGPUDAGToDAGISel::SelectDSReadWrite2(SDValue Addr, SDValue &Base,
                                          SDValue &Offset0, SDValue &Offset1,
                                          unsigned Size) const {
SDLoc DL(Addr);

if (CurDAG->isBaseWithConstantOffset(Addr)) {
  SDValue N0 = Addr.getOperand(0);
  SDValue N1 = Addr.getOperand(1);
  ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
  unsigned OffsetValue0 = C1->getZExtValue();
  unsigned OffsetValue1 = OffsetValue0 + Size;

  // (add n0, c0)
  if (isDSOffset2Legal(N0, OffsetValue0, OffsetValue1, Size)) {
    Base = N0;
    Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8);
    Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8);
    return true;
  }
} else if (Addr.getOpcode() == ISD::SUB) {
  // sub C, x -> add (sub 0, x), C
  if (const ConstantSDNode *C =
          dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
    unsigned OffsetValue0 = C->getZExtValue();
    unsigned OffsetValue1 = OffsetValue0 + Size;

    if (isDSOffset2Legal(SDValue(), OffsetValue0, OffsetValue1, Size)) {
      SDLoc DL(Addr);
      SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);

      // XXX - This is kind of hacky. Create a dummy sub node so we can check
      // the known bits in isDSOffsetLegal. We need to emit the selected node
      // here, so this is thrown away.
      SDValue Sub =
          CurDAG->getNode(ISD::SUB, DL, MVT::i32, Zero, Addr.getOperand(1));

      if (isDSOffset2Legal(Sub, OffsetValue0, OffsetValue1, Size)) {
        SmallVector<SDValue, 3> Opnds;
        Opnds.push_back(Zero);
        Opnds.push_back(Addr.getOperand(1));
        unsigned SubOp = AMDGPU::V_SUB_CO_U32_e32;
        if (Subtarget->hasAddNoCarry()) {
          SubOp = AMDGPU::V_SUB_U32_e64;
          Opnds.push_back(
              CurDAG->getTargetConstant(0, {}, MVT::i1)); // clamp bit
        }

        MachineSDNode *MachineSub = CurDAG->getMachineNode(
            SubOp, DL, MVT::getIntegerVT(Size * 8), Opnds);

        Base = SDValue(MachineSub, 0);
        Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8);
        Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8);
        return true;
      }
    }
  }
} else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
  unsigned OffsetValue0 = CAddr->getZExtValue();
  unsigned OffsetValue1 = OffsetValue0 + Size;

  if (isDSOffset2Legal(SDValue(), OffsetValue0, OffsetValue1, Size)) {
    SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
    MachineSDNode *MovZero =
        CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, DL, MVT::i32, Zero);
    Base = SDValue(MovZero, 0);
    Offset0 = CurDAG->getTargetConstant(OffsetValue0 / Size, DL, MVT::i8);
    Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8);
    return true;
  }
}

// default case

Base = Addr;
Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8);
return true;
1452}

1454bool AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr, SDValue &VAddr,
                                   SDValue &SOffset, SDValue &Offset,
                                   SDValue &Offen, SDValue &Idxen,
                                   SDValue &Addr64) const {
// Subtarget prefers to use flat instruction
// FIXME: This should be a pattern predicate and not reach here
if (Subtarget->useFlatForGlobal())
  return false;

SDLoc DL(Addr);

Idxen = CurDAG->getTargetConstant(0, DL, MVT::i1);
Offen = CurDAG->getTargetConstant(0, DL, MVT::i1);
Addr64 = CurDAG->getTargetConstant(0, DL, MVT::i1);
SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);

ConstantSDNode *C1 = nullptr;
SDValue N0 = Addr;
if (CurDAG->isBaseWithConstantOffset(Addr)) {
  C1 = cast<ConstantSDNode>(Addr.getOperand(1));
  if (isUInt<32>(C1->getZExtValue()))
    N0 = Addr.getOperand(0);
  else
    C1 = nullptr;
}

if (N0.getOpcode() == ISD::ADD) {
  // (add N2, N3) -> addr64, or
  // (add (add N2, N3), C1) -> addr64
  SDValue N2 = N0.getOperand(0);
  SDValue N3 = N0.getOperand(1);
  Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);

  if (N2->isDivergent()) {
    if (N3->isDivergent()) {
      // Both N2 and N3 are divergent. Use N0 (the result of the add) as the
      // addr64, and construct the resource from a 0 address.
      Ptr = SDValue(buildSMovImm64(DL, 0, MVT::v2i32), 0);
      VAddr = N0;
    } else {
      // N2 is divergent, N3 is not.
      Ptr = N3;
      VAddr = N2;
    }
  } else {
    // N2 is not divergent.
    Ptr = N2;
    VAddr = N3;
  }
  Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
} else if (N0->isDivergent()) {
  // N0 is divergent. Use it as the addr64, and construct the resource from a
  // 0 address.
  Ptr = SDValue(buildSMovImm64(DL, 0, MVT::v2i32), 0);
  VAddr = N0;
  Addr64 = CurDAG->getTargetConstant(1, DL, MVT::i1);
} else {
  // N0 -> offset, or
  // (N0 + C1) -> offset
  VAddr = CurDAG->getTargetConstant(0, DL, MVT::i32);
  Ptr = N0;
}

if (!C1) {
  // No offset.
  Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
  return true;
}

if (SIInstrInfo::isLegalMUBUFImmOffset(C1->getZExtValue())) {
  // Legal offset for instruction.
  Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
  return true;
}

// Illegal offset, store it in soffset.
Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
SOffset =
    SDValue(CurDAG->getMachineNode(
                AMDGPU::S_MOV_B32, DL, MVT::i32,
                CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32)),
            0);
return true;
1537}

1539bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
                                         SDValue &VAddr, SDValue &SOffset,
                                         SDValue &Offset) const {
SDValue Ptr, Offen, Idxen, Addr64;

// addr64 bit was removed for volcanic islands.
// FIXME: This should be a pattern predicate and not reach here
if (!Subtarget->hasAddr64())
  return false;

if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64))
  return false;

ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
if (C->getSExtValue()) {
  SDLoc DL(Addr);

  const SITargetLowering& Lowering =
    *static_cast<const SITargetLowering*>(getTargetLowering());

  SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
  return true;
}

return false;
1564}

1566std::pair<SDValue, SDValue> AMDGPUDAGToDAGISel::foldFrameIndex(SDValue N) const {
SDLoc DL(N);

auto *FI = dyn_cast<FrameIndexSDNode>(N);
SDValue TFI =
    FI ? CurDAG->getTargetFrameIndex(FI->getIndex(), FI->getValueType(0)) : N;

// We rebase the base address into an absolute stack address and hence
// use constant 0 for soffset. This value must be retained until
// frame elimination and eliminateFrameIndex will choose the appropriate
// frame register if need be.
return std::make_pair(TFI, CurDAG->getTargetConstant(0, DL, MVT::i32));
1578}

1580bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffen(SDNode *Parent,
                                               SDValue Addr, SDValue &Rsrc,
                                               SDValue &VAddr, SDValue &SOffset,
                                               SDValue &ImmOffset) const {

SDLoc DL(Addr);
MachineFunction &MF = CurDAG->getMachineFunction();
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();

Rsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);

if (ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
  int64_t Imm = CAddr->getSExtValue();
  const int64_t NullPtr =
      AMDGPUTargetMachine::getNullPointerValue(AMDGPUAS::PRIVATE_ADDRESS);
  // Don't fold null pointer.
  if (Imm != NullPtr) {
    SDValue HighBits = CurDAG->getTargetConstant(Imm & ~4095, DL, MVT::i32);
    MachineSDNode *MovHighBits = CurDAG->getMachineNode(
      AMDGPU::V_MOV_B32_e32, DL, MVT::i32, HighBits);
    VAddr = SDValue(MovHighBits, 0);

    SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
    ImmOffset = CurDAG->getTargetConstant(Imm & 4095, DL, MVT::i16);
    return true;
  }
}

if (CurDAG->isBaseWithConstantOffset(Addr)) {
  // (add n0, c1)

  SDValue N0 = Addr.getOperand(0);
  SDValue N1 = Addr.getOperand(1);

  // Offsets in vaddr must be positive if range checking is enabled.
  //
  // The total computation of vaddr + soffset + offset must not overflow.  If
  // vaddr is negative, even if offset is 0 the sgpr offset add will end up
  // overflowing.
  //
  // Prior to gfx9, MUBUF instructions with the vaddr offset enabled would
  // always perform a range check. If a negative vaddr base index was used,
  // this would fail the range check. The overall address computation would
  // compute a valid address, but this doesn't happen due to the range
  // check. For out-of-bounds MUBUF loads, a 0 is returned.
  //
  // Therefore it should be safe to fold any VGPR offset on gfx9 into the
  // MUBUF vaddr, but not on older subtargets which can only do this if the
  // sign bit is known 0.
  ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
  if (SIInstrInfo::isLegalMUBUFImmOffset(C1->getZExtValue()) &&
      (!Subtarget->privateMemoryResourceIsRangeChecked() ||
       CurDAG->SignBitIsZero(N0))) {
    std::tie(VAddr, SOffset) = foldFrameIndex(N0);
    ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
    return true;
  }
}

// (node)
std::tie(VAddr, SOffset) = foldFrameIndex(Addr);
ImmOffset = CurDAG->getTargetConstant(0, DL, MVT::i16);
return true;
1643}

1645static bool IsCopyFromSGPR(const SIRegisterInfo &TRI, SDValue Val) {
if (Val.getOpcode() != ISD::CopyFromReg)
  return false;
auto RC =
    TRI.getPhysRegClass(cast<RegisterSDNode>(Val.getOperand(1))->getReg());
return RC && TRI.isSGPRClass(RC);
1651}

1653bool AMDGPUDAGToDAGISel::SelectMUBUFScratchOffset(SDNode *Parent,
                                                SDValue Addr,
                                                SDValue &SRsrc,
                                                SDValue &SOffset,
                                                SDValue &Offset) const {
const SIRegisterInfo *TRI =
    static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
MachineFunction &MF = CurDAG->getMachineFunction();
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
SDLoc DL(Addr);

// CopyFromReg <sgpr>
if (IsCopyFromSGPR(*TRI, Addr)) {
  SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);
  SOffset = Addr;
  Offset = CurDAG->getTargetConstant(0, DL, MVT::i16);
  return true;
}

ConstantSDNode *CAddr;
if (Addr.getOpcode() == ISD::ADD) {
  // Add (CopyFromReg <sgpr>) <constant>
  CAddr = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
  if (!CAddr || !SIInstrInfo::isLegalMUBUFImmOffset(CAddr->getZExtValue()))
    return false;
  if (!IsCopyFromSGPR(*TRI, Addr.getOperand(0)))
    return false;

  SOffset = Addr.getOperand(0);
} else if ((CAddr = dyn_cast<ConstantSDNode>(Addr)) &&
           SIInstrInfo::isLegalMUBUFImmOffset(CAddr->getZExtValue())) {
  // <constant>
  SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32);
} else {
  return false;
}

SRsrc = CurDAG->getRegister(Info->getScratchRSrcReg(), MVT::v4i32);

Offset = CurDAG->getTargetConstant(CAddr->getZExtValue(), DL, MVT::i16);
return true;
1694}

1696bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
                                         SDValue &SOffset, SDValue &Offset
                                         ) const {
SDValue Ptr, VAddr, Offen, Idxen, Addr64;
const SIInstrInfo *TII =
  static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());

if (!SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64))
  return false;

if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
    !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
    !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
  uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
                  APInt::getAllOnesValue(32).getZExtValue(); // Size
  SDLoc DL(Addr);

  const SITargetLowering& Lowering =
    *static_cast<const SITargetLowering*>(getTargetLowering());

  SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
  return true;
}
return false;
1720}

1722// Find a load or store from corresponding pattern root.
1723// Roots may be build_vector, bitconvert or their combinations.
1724static MemSDNode* findMemSDNode(SDNode *N) {
N = AMDGPUTargetLowering::stripBitcast(SDValue(N,0)).getNode();
if (MemSDNode *MN = dyn_cast<MemSDNode>(N))
  return MN;
assert(isa<BuildVectorSDNode>(N))((void)0);
for (SDValue V : N->op_values())
  if (MemSDNode *MN =
        dyn_cast<MemSDNode>(AMDGPUTargetLowering::stripBitcast(V)))
    return MN;
llvm_unreachable("cannot find MemSDNode in the pattern!")__builtin_unreachable();
1734}

1736bool AMDGPUDAGToDAGISel::SelectFlatOffsetImpl(SDNode *N, SDValue Addr,
                                            SDValue &VAddr, SDValue &Offset,
                                            uint64_t FlatVariant) const {
int64_t OffsetVal = 0;

unsigned AS = findMemSDNode(N)->getAddressSpace();

bool CanHaveFlatSegmentOffsetBug =
    Subtarget->hasFlatSegmentOffsetBug() &&
    FlatVariant == SIInstrFlags::FLAT &&
    (AS == AMDGPUAS::FLAT_ADDRESS || AS == AMDGPUAS::GLOBAL_ADDRESS);

if (Subtarget->hasFlatInstOffsets() && !CanHaveFlatSegmentOffsetBug) {
  SDValue N0, N1;
  if (isBaseWithConstantOffset64(Addr, N0, N1)) {
    int64_t COffsetVal = cast<ConstantSDNode>(N1)->getSExtValue();

    const SIInstrInfo *TII = Subtarget->getInstrInfo();
    if (TII->isLegalFLATOffset(COffsetVal, AS, FlatVariant)) {
      Addr = N0;
      OffsetVal = COffsetVal;
    } else {
      // If the offset doesn't fit, put the low bits into the offset field and
      // add the rest.
      //
      // For a FLAT instruction the hardware decides whether to access
      // global/scratch/shared memory based on the high bits of vaddr,
      // ignoring the offset field, so we have to ensure that when we add
      // remainder to vaddr it still points into the same underlying object.
      // The easiest way to do that is to make sure that we split the offset
      // into two pieces that are both >= 0 or both <= 0.

      SDLoc DL(N);
      uint64_t RemainderOffset;

      std::tie(OffsetVal, RemainderOffset) =
          TII->splitFlatOffset(COffsetVal, AS, FlatVariant);

      SDValue AddOffsetLo =
          getMaterializedScalarImm32(Lo_32(RemainderOffset), DL);
      SDValue Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);

      if (Addr.getValueType().getSizeInBits() == 32) {
        SmallVector<SDValue, 3> Opnds;
        Opnds.push_back(N0);
        Opnds.push_back(AddOffsetLo);
        unsigned AddOp = AMDGPU::V_ADD_CO_U32_e32;
        if (Subtarget->hasAddNoCarry()) {
          AddOp = AMDGPU::V_ADD_U32_e64;
          Opnds.push_back(Clamp);
        }
        Addr = SDValue(CurDAG->getMachineNode(AddOp, DL, MVT::i32, Opnds), 0);
      } else {
        // TODO: Should this try to use a scalar add pseudo if the base address
        // is uniform and saddr is usable?
        SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32);
        SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32);

        SDNode *N0Lo = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
                                              DL, MVT::i32, N0, Sub0);
        SDNode *N0Hi = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
                                              DL, MVT::i32, N0, Sub1);

        SDValue AddOffsetHi =
            getMaterializedScalarImm32(Hi_32(RemainderOffset), DL);

        SDVTList VTs = CurDAG->getVTList(MVT::i32, MVT::i1);

        SDNode *Add =
            CurDAG->getMachineNode(AMDGPU::V_ADD_CO_U32_e64, DL, VTs,
                                   {AddOffsetLo, SDValue(N0Lo, 0), Clamp});

        SDNode *Addc = CurDAG->getMachineNode(
            AMDGPU::V_ADDC_U32_e64, DL, VTs,
            {AddOffsetHi, SDValue(N0Hi, 0), SDValue(Add, 1), Clamp});

        SDValue RegSequenceArgs[] = {
            CurDAG->getTargetConstant(AMDGPU::VReg_64RegClassID, DL, MVT::i32),
            SDValue(Add, 0), Sub0, SDValue(Addc, 0), Sub1};

        Addr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
                                              MVT::i64, RegSequenceArgs),
                       0);
      }
    }
  }
}

VAddr = Addr;
Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i16);
return true;
1827}

1829bool AMDGPUDAGToDAGISel::SelectFlatOffset(SDNode *N, SDValue Addr,
                                        SDValue &VAddr,
                                        SDValue &Offset) const {
return SelectFlatOffsetImpl(N, Addr, VAddr, Offset, SIInstrFlags::FLAT);
1833}

1835bool AMDGPUDAGToDAGISel::SelectGlobalOffset(SDNode *N, SDValue Addr,
                                          SDValue &VAddr,
                                          SDValue &Offset) const {
return SelectFlatOffsetImpl(N, Addr, VAddr, Offset, SIInstrFlags::FlatGlobal);
1839}

1841bool AMDGPUDAGToDAGISel::SelectScratchOffset(SDNode *N, SDValue Addr,
                                           SDValue &VAddr,
                                           SDValue &Offset) const {
return SelectFlatOffsetImpl(N, Addr, VAddr, Offset,
                            SIInstrFlags::FlatScratch);
1846}

1848// If this matches zero_extend i32:x, return x
1849static SDValue matchZExtFromI32(SDValue Op) {
if (Op.getOpcode() != ISD::ZERO_EXTEND)
  return SDValue();

SDValue ExtSrc = Op.getOperand(0);
return (ExtSrc.getValueType() == MVT::i32) ? ExtSrc : SDValue();
1855}

1857// Match (64-bit SGPR base) + (zext vgpr offset) + sext(imm offset)
1858bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N,
                                         SDValue Addr,
                                         SDValue &SAddr,
                                         SDValue &VOffset,
                                         SDValue &Offset) const {
int64_t ImmOffset = 0;

// Match the immediate offset first, which canonically is moved as low as
// possible.

SDValue LHS, RHS;
if (isBaseWithConstantOffset64(Addr, LHS, RHS)) {
  int64_t COffsetVal = cast<ConstantSDNode>(RHS)->getSExtValue();
  const SIInstrInfo *TII = Subtarget->getInstrInfo();

  if (TII->isLegalFLATOffset(COffsetVal, AMDGPUAS::GLOBAL_ADDRESS,
                             SIInstrFlags::FlatGlobal)) {
    Addr = LHS;
    ImmOffset = COffsetVal;
  } else if (!LHS->isDivergent()) {
    if (COffsetVal > 0) {
      SDLoc SL(N);
      // saddr + large_offset -> saddr +
      //                         (voffset = large_offset & ~MaxOffset) +
      //                         (large_offset & MaxOffset);
      int64_t SplitImmOffset, RemainderOffset;
      std::tie(SplitImmOffset, RemainderOffset) = TII->splitFlatOffset(
          COffsetVal, AMDGPUAS::GLOBAL_ADDRESS, SIInstrFlags::FlatGlobal);

      if (isUInt<32>(RemainderOffset)) {
        SDNode *VMov = CurDAG->getMachineNode(
            AMDGPU::V_MOV_B32_e32, SL, MVT::i32,
            CurDAG->getTargetConstant(RemainderOffset, SDLoc(), MVT::i32));
        VOffset = SDValue(VMov, 0);
        SAddr = LHS;
        Offset = CurDAG->getTargetConstant(SplitImmOffset, SDLoc(), MVT::i16);
        return true;
      }
    }

    // We are adding a 64 bit SGPR and a constant. If constant bus limit
    // is 1 we would need to perform 1 or 2 extra moves for each half of
    // the constant and it is better to do a scalar add and then issue a
    // single VALU instruction to materialize zero. Otherwise it is less
    // instructions to perform VALU adds with immediates or inline literals.
    unsigned NumLiterals =
        !TII->isInlineConstant(APInt(32, COffsetVal & 0xffffffff)) +
        !TII->isInlineConstant(APInt(32, COffsetVal >> 32));
    if (Subtarget->getConstantBusLimit(AMDGPU::V_ADD_U32_e64) > NumLiterals)
      return false;
  }
}

// Match the variable offset.
if (Addr.getOpcode() == ISD::ADD) {
  LHS = Addr.getOperand(0);
  RHS = Addr.getOperand(1);

  if (!LHS->isDivergent()) {
    // add (i64 sgpr), (zero_extend (i32 vgpr))
    if (SDValue ZextRHS = matchZExtFromI32(RHS)) {
      SAddr = LHS;
      VOffset = ZextRHS;
    }
  }

  if (!SAddr && !RHS->isDivergent()) {
    // add (zero_extend (i32 vgpr)), (i64 sgpr)
    if (SDValue ZextLHS = matchZExtFromI32(LHS)) {
      SAddr = RHS;
      VOffset = ZextLHS;
    }
  }

  if (SAddr) {
    Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i16);
    return true;
  }
}

if (Addr->isDivergent() || Addr.getOpcode() == ISD::UNDEF ||
    isa<ConstantSDNode>(Addr))
  return false;

// It's cheaper to materialize a single 32-bit zero for vaddr than the two
// moves required to copy a 64-bit SGPR to VGPR.
SAddr = Addr;
SDNode *VMov =
    CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, SDLoc(Addr), MVT::i32,
                           CurDAG->getTargetConstant(0, SDLoc(), MVT::i32));
VOffset = SDValue(VMov, 0);
Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i16);
return true;
1951}

1953static SDValue SelectSAddrFI(SelectionDAG *CurDAG, SDValue SAddr) {
if (auto FI = dyn_cast<FrameIndexSDNode>(SAddr)) {
  SAddr = CurDAG->getTargetFrameIndex(FI->getIndex(), FI->getValueType(0));
} else if (SAddr.getOpcode() == ISD::ADD &&
           isa<FrameIndexSDNode>(SAddr.getOperand(0))) {
  // Materialize this into a scalar move for scalar address to avoid
  // readfirstlane.
  auto FI = cast<FrameIndexSDNode>(SAddr.getOperand(0));
  SDValue TFI = CurDAG->getTargetFrameIndex(FI->getIndex(),
                                            FI->getValueType(0));
  SAddr = SDValue(CurDAG->getMachineNode(AMDGPU::S_ADD_I32, SDLoc(SAddr),
                                         MVT::i32, TFI, SAddr.getOperand(1)),
                  0);
}

return SAddr;
1969}

1971// Match (32-bit SGPR base) + sext(imm offset)
1972bool AMDGPUDAGToDAGISel::SelectScratchSAddr(SDNode *Parent, SDValue Addr,
                                          SDValue &SAddr,
                                          SDValue &Offset) const {
if (Addr->isDivergent())
  return false;

SDLoc DL(Addr);

int64_t COffsetVal = 0;

if (CurDAG->isBaseWithConstantOffset(Addr)) {
  COffsetVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
  SAddr = Addr.getOperand(0);
} else {
  SAddr = Addr;
}

SAddr = SelectSAddrFI(CurDAG, SAddr);

const SIInstrInfo *TII = Subtarget->getInstrInfo();

if (!TII->isLegalFLATOffset(COffsetVal, AMDGPUAS::PRIVATE_ADDRESS,
                            SIInstrFlags::FlatScratch)) {
  int64_t SplitImmOffset, RemainderOffset;
  std::tie(SplitImmOffset, RemainderOffset) = TII->splitFlatOffset(
      COffsetVal, AMDGPUAS::PRIVATE_ADDRESS, SIInstrFlags::FlatScratch);

  COffsetVal = SplitImmOffset;

  SDValue AddOffset =
      SAddr.getOpcode() == ISD::TargetFrameIndex
          ? getMaterializedScalarImm32(Lo_32(RemainderOffset), DL)
          : CurDAG->getTargetConstant(RemainderOffset, DL, MVT::i32);
  SAddr = SDValue(CurDAG->getMachineNode(AMDGPU::S_ADD_I32, DL, MVT::i32,
                                         SAddr, AddOffset),
                  0);
}

Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i16);

return true;
2013}

2015bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
                                        SDValue &Offset, bool &Imm) const {
ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
if (!C) {
  if (ByteOffsetNode.getValueType().isScalarInteger() &&
      ByteOffsetNode.getValueType().getSizeInBits() == 32) {
    Offset = ByteOffsetNode;
    Imm = false;
    return true;
  }
  if (ByteOffsetNode.getOpcode() == ISD::ZERO_EXTEND) {
    if (ByteOffsetNode.getOperand(0).getValueType().getSizeInBits() == 32) {
      Offset = ByteOffsetNode.getOperand(0);
      Imm = false;
      return true;
    }
  }
  return false;
}

SDLoc SL(ByteOffsetNode);
// GFX9 and GFX10 have signed byte immediate offsets.
int64_t ByteOffset = C->getSExtValue();
Optional<int64_t> EncodedOffset =
    AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset, false);
if (EncodedOffset) {
  Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
  Imm = true;
  return true;
}

// SGPR and literal offsets are unsigned.
if (ByteOffset < 0)
  return false;

EncodedOffset = AMDGPU::getSMRDEncodedLiteralOffset32(*Subtarget, ByteOffset);
if (EncodedOffset) {
  Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
  return true;
}

if (!isUInt<32>(ByteOffset) && !isInt<32>(ByteOffset))
  return false;

SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
Offset = SDValue(
    CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, C32Bit), 0);

return true;
2064}

2066SDValue AMDGPUDAGToDAGISel::Expand32BitAddress(SDValue Addr) const {
if (Addr.getValueType() != MVT::i32)
  return Addr;

// Zero-extend a 32-bit address.
SDLoc SL(Addr);

const MachineFunction &MF = CurDAG->getMachineFunction();
const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
unsigned AddrHiVal = Info->get32BitAddressHighBits();
SDValue AddrHi = CurDAG->getTargetConstant(AddrHiVal, SL, MVT::i32);

const SDValue Ops[] = {
  CurDAG->getTargetConstant(AMDGPU::SReg_64_XEXECRegClassID, SL, MVT::i32),
  Addr,
  CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32),
  SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, AddrHi),
          0),
  CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32),
};

return SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, SL, MVT::i64,
                                      Ops), 0);
2089}

2091bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
                                   SDValue &Offset, bool &Imm) const {
SDLoc SL(Addr);

// A 32-bit (address + offset) should not cause unsigned 32-bit integer
// wraparound, because s_load instructions perform the addition in 64 bits.
if ((Addr.getValueType() != MVT::i32 ||
     Addr->getFlags().hasNoUnsignedWrap())) {
  SDValue N0, N1;
  // Extract the base and offset if possible.
  if (CurDAG->isBaseWithConstantOffset(Addr) ||
      Addr.getOpcode() == ISD::ADD) {
    N0 = Addr.getOperand(0);
    N1 = Addr.getOperand(1);
  } else if (getBaseWithOffsetUsingSplitOR(*CurDAG, Addr, N0, N1)) {
    assert(N0 && N1 && isa<ConstantSDNode>(N1))((void)0);
  }
  if (N0 && N1) {
    if (SelectSMRDOffset(N1, Offset, Imm)) {
      SBase = Expand32BitAddress(N0);
      return true;
    }
  }
}
SBase = Expand32BitAddress(Addr);
Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
Imm = true;
return true;
2119}

2121bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
                                     SDValue &Offset) const {
bool Imm = false;
return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
2125}

2127bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase,
                                       SDValue &Offset) const {

assert(Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)((void)0);

bool Imm = false;
if (!SelectSMRD(Addr, SBase, Offset, Imm))
  return false;

return !Imm && isa<ConstantSDNode>(Offset);
2137}

2139bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
                                      SDValue &Offset) const {
bool Imm = false;
return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
       !isa<ConstantSDNode>(Offset);
2144}

2146bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
                                           SDValue &Offset) const {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr)) {
  // The immediate offset for S_BUFFER instructions is unsigned.
  if (auto Imm =
          AMDGPU::getSMRDEncodedOffset(*Subtarget, C->getZExtValue(), true)) {
    Offset = CurDAG->getTargetConstant(*Imm, SDLoc(Addr), MVT::i32);
    return true;
  }
}

return false;
2158}

2160bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm32(SDValue Addr,
                                             SDValue &Offset) const {
assert(Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)((void)0);

if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr)) {
  if (auto Imm = AMDGPU::getSMRDEncodedLiteralOffset32(*Subtarget,
                                                       C->getZExtValue())) {
    Offset = CurDAG->getTargetConstant(*Imm, SDLoc(Addr), MVT::i32);
    return true;
  }
}

return false;
2173}

2175bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
                                          SDValue &Base,
                                          SDValue &Offset) const {
SDLoc DL(Index);

if (CurDAG->isBaseWithConstantOffset(Index)) {
  SDValue N0 = Index.getOperand(0);
  SDValue N1 = Index.getOperand(1);
  ConstantSDNode *C1 = cast<ConstantSDNode>(N1);

  // (add n0, c0)
  // Don't peel off the offset (c0) if doing so could possibly lead
  // the base (n0) to be negative.
  // (or n0, |c0|) can never change a sign given isBaseWithConstantOffset.
  if (C1->getSExtValue() <= 0 || CurDAG->SignBitIsZero(N0) ||
      (Index->getOpcode() == ISD::OR && C1->getSExtValue() >= 0)) {
    Base = N0;
    Offset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i32);
    return true;
  }
}

if (isa<ConstantSDNode>(Index))
  return false;

Base = Index;
Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
return true;
2203}

2205SDNode *AMDGPUDAGToDAGISel::getS_BFE(unsigned Opcode, const SDLoc &DL,
                                   SDValue Val, uint32_t Offset,
                                   uint32_t Width) {
// Transformation function, pack the offset and width of a BFE into
// the format expected by the S_BFE_I32 / S_BFE_U32. In the second
// source, bits [5:0] contain the offset and bits [22:16] the width.
uint32_t PackedVal = Offset | (Width << 16);
SDValue PackedConst = CurDAG->getTargetConstant(PackedVal, DL, MVT::i32);

return CurDAG->getMachineNode(Opcode, DL, MVT::i32, Val, PackedConst);
2215}

2217void AMDGPUDAGToDAGISel::SelectS_BFEFromShifts(SDNode *N) {
// "(a << b) srl c)" ---> "BFE_U32 a, (c-b), (32-c)
// "(a << b) sra c)" ---> "BFE_I32 a, (c-b), (32-c)
// Predicate: 0 < b <= c < 32

const SDValue &Shl = N->getOperand(0);
ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));

if (B && C) {
  uint32_t BVal = B->getZExtValue();
  uint32_t CVal = C->getZExtValue();

  if (0 < BVal && BVal <= CVal && CVal < 32) {
    bool Signed = N->getOpcode() == ISD::SRA;
    unsigned Opcode = Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32;

    ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal,
                            32 - CVal));
    return;
  }
}
SelectCode(N);
2240}

2242void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
switch (N->getOpcode()) {
case ISD::AND:
  if (N->getOperand(0).getOpcode() == ISD::SRL) {
    // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
    // Predicate: isMask(mask)
    const SDValue &Srl = N->getOperand(0);
    ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));

    if (Shift && Mask) {
      uint32_t ShiftVal = Shift->getZExtValue();
      uint32_t MaskVal = Mask->getZExtValue();

      if (isMask_32(MaskVal)) {
        uint32_t WidthVal = countPopulation(MaskVal);

        ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
                                Srl.getOperand(0), ShiftVal, WidthVal));
        return;
      }
    }
  }
  break;
case ISD::SRL:
  if (N->getOperand(0).getOpcode() == ISD::AND) {
    // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
    // Predicate: isMask(mask >> b)
    const SDValue &And = N->getOperand(0);
    ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));

    if (Shift && Mask) {
      uint32_t ShiftVal = Shift->getZExtValue();
      uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;

      if (isMask_32(MaskVal)) {
        uint32_t WidthVal = countPopulation(MaskVal);

        ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_U32, SDLoc(N),
                                And.getOperand(0), ShiftVal, WidthVal));
        return;
      }
    }
  } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
    SelectS_BFEFromShifts(N);
    return;
  }
  break;
case ISD::SRA:
  if (N->getOperand(0).getOpcode() == ISD::SHL) {
    SelectS_BFEFromShifts(N);
    return;
  }
  break;

case ISD::SIGN_EXTEND_INREG: {
  // sext_inreg (srl x, 16), i8 -> bfe_i32 x, 16, 8
  SDValue Src = N->getOperand(0);
  if (Src.getOpcode() != ISD::SRL)
    break;

  const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
  if (!Amt)
    break;

  unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
  ReplaceNode(N, getS_BFE(AMDGPU::S_BFE_I32, SDLoc(N), Src.getOperand(0),
                          Amt->getZExtValue(), Width));
  return;
}
}

SelectCode(N);
2316}

2318bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
assert(N->getOpcode() == ISD::BRCOND)((void)0);
if (!N->hasOneUse())
  return false;

SDValue Cond = N->getOperand(1);
if (Cond.getOpcode() == ISD::CopyToReg)
  Cond = Cond.getOperand(2);

if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse())
  return false;

MVT VT = Cond.getOperand(0).getSimpleValueType();
if (VT == MVT::i32)
  return true;

if (VT == MVT::i64) {
  auto ST = static_cast<const GCNSubtarget *>(Subtarget);

  ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
  return (CC == ISD::SETEQ || CC == ISD::SETNE) && ST->hasScalarCompareEq64();
}

return false;
2342}

2344void AMDGPUDAGToDAGISel::SelectBRCOND(SDNode *N) {
SDValue Cond = N->getOperand(1);

if (Cond.isUndef()) {
  CurDAG->SelectNodeTo(N, AMDGPU::SI_BR_UNDEF, MVT::Other,
                       N->getOperand(2), N->getOperand(0));
  return;
}

const GCNSubtarget *ST = static_cast<const GCNSubtarget *>(Subtarget);
const SIRegisterInfo *TRI = ST->getRegisterInfo();

bool UseSCCBr = isCBranchSCC(N) && isUniformBr(N);
unsigned BrOp = UseSCCBr ? AMDGPU::S_CBRANCH_SCC1 : AMDGPU::S_CBRANCH_VCCNZ;
Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC();
SDLoc SL(N);

if (!UseSCCBr) {
  // This is the case that we are selecting to S_CBRANCH_VCCNZ.  We have not
  // analyzed what generates the vcc value, so we do not know whether vcc
  // bits for disabled lanes are 0.  Thus we need to mask out bits for
  // disabled lanes.
  //
  // For the case that we select S_CBRANCH_SCC1 and it gets
  // changed to S_CBRANCH_VCCNZ in SIFixSGPRCopies, SIFixSGPRCopies calls
  // SIInstrInfo::moveToVALU which inserts the S_AND).
  //
  // We could add an analysis of what generates the vcc value here and omit
  // the S_AND when is unnecessary. But it would be better to add a separate
  // pass after SIFixSGPRCopies to do the unnecessary S_AND removal, so it
  // catches both cases.
  Cond = SDValue(CurDAG->getMachineNode(ST->isWave32() ? AMDGPU::S_AND_B32
                                                       : AMDGPU::S_AND_B64,
                   SL, MVT::i1,
                   CurDAG->getRegister(ST->isWave32() ? AMDGPU::EXEC_LO
                                                      : AMDGPU::EXEC,
                                       MVT::i1),
                  Cond),
                 0);
}

SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond);
CurDAG->SelectNodeTo(N, BrOp, MVT::Other,
                     N->getOperand(2), // Basic Block
                     VCC.getValue(0));
2389}

2391void AMDGPUDAGToDAGISel::SelectFMAD_FMA(SDNode *N) {
MVT VT = N->getSimpleValueType(0);
bool IsFMA = N->getOpcode() == ISD::FMA;
if (VT != MVT::f32 || (!Subtarget->hasMadMixInsts() &&
                       !Subtarget->hasFmaMixInsts()) ||
    ((IsFMA && Subtarget->hasMadMixInsts()) ||
     (!IsFMA && Subtarget->hasFmaMixInsts()))) {
  SelectCode(N);
  return;
}

SDValue Src0 = N->getOperand(0);
SDValue Src1 = N->getOperand(1);
SDValue Src2 = N->getOperand(2);
unsigned Src0Mods, Src1Mods, Src2Mods;

// Avoid using v_mad_mix_f32/v_fma_mix_f32 unless there is actually an operand
// using the conversion from f16.
bool Sel0 = SelectVOP3PMadMixModsImpl(Src0, Src0, Src0Mods);
bool Sel1 = SelectVOP3PMadMixModsImpl(Src1, Src1, Src1Mods);
bool Sel2 = SelectVOP3PMadMixModsImpl(Src2, Src2, Src2Mods);

assert((IsFMA || !Mode.allFP32Denormals()) &&((void)0)
       "fmad selected with denormals enabled")((void)0);
// TODO: We can select this with f32 denormals enabled if all the sources are
// converted from f16 (in which case fmad isn't legal).

if (Sel0 || Sel1 || Sel2) {
  // For dummy operands.
  SDValue Zero = CurDAG->getTargetConstant(0, SDLoc(), MVT::i32);
  SDValue Ops[] = {
    CurDAG->getTargetConstant(Src0Mods, SDLoc(), MVT::i32), Src0,
    CurDAG->getTargetConstant(Src1Mods, SDLoc(), MVT::i32), Src1,
    CurDAG->getTargetConstant(Src2Mods, SDLoc(), MVT::i32), Src2,
    CurDAG->getTargetConstant(0, SDLoc(), MVT::i1),
    Zero, Zero
  };

  CurDAG->SelectNodeTo(N,
                       IsFMA ? AMDGPU::V_FMA_MIX_F32 : AMDGPU::V_MAD_MIX_F32,
                       MVT::f32, Ops);
} else {
  SelectCode(N);
}
2435}

2437// This is here because there isn't a way to use the generated sub0_sub1 as the
2438// subreg index to EXTRACT_SUBREG in tablegen.
2439void AMDGPUDAGToDAGISel::SelectATOMIC_CMP_SWAP(SDNode *N) {
MemSDNode *Mem = cast<MemSDNode>(N);
unsigned AS = Mem->getAddressSpace();
if (AS == AMDGPUAS::FLAT_ADDRESS) {
  SelectCode(N);
  return;
}

MVT VT = N->getSimpleValueType(0);
bool Is32 = (VT == MVT::i32);
SDLoc SL(N);

MachineSDNode *CmpSwap = nullptr;
if (Subtarget->hasAddr64()) {
  SDValue SRsrc, VAddr, SOffset, Offset;

  if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset)) {
    unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN :
      AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN;
    SDValue CmpVal = Mem->getOperand(2);
    SDValue CPol = CurDAG->getTargetConstant(AMDGPU::CPol::GLC, SL, MVT::i32);

    // XXX - Do we care about glue operands?

    SDValue Ops[] = {CmpVal, VAddr, SRsrc, SOffset, Offset, CPol,
                     Mem->getChain()};

    CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
  }
}

if (!CmpSwap) {
  SDValue SRsrc, SOffset, Offset;
  if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset)) {
    unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN :
      AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN;

    SDValue CmpVal = Mem->getOperand(2);
    SDValue CPol = CurDAG->getTargetConstant(AMDGPU::CPol::GLC, SL, MVT::i32);
    SDValue Ops[] = {CmpVal, SRsrc, SOffset, Offset, CPol, Mem->getChain()};

    CmpSwap = CurDAG->getMachineNode(Opcode, SL, Mem->getVTList(), Ops);
  }
}

if (!CmpSwap) {
  SelectCode(N);
  return;
}

MachineMemOperand *MMO = Mem->getMemOperand();
CurDAG->setNodeMemRefs(CmpSwap, {MMO});

unsigned SubReg = Is32 ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
SDValue Extract
  = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0));

ReplaceUses(SDValue(N, 0), Extract);
ReplaceUses(SDValue(N, 1), SDValue(CmpSwap, 1));
CurDAG->RemoveDeadNode(N);
2499}

2501void AMDGPUDAGToDAGISel::SelectDSAppendConsume(SDNode *N, unsigned IntrID) {
// The address is assumed to be uniform, so if it ends up in a VGPR, it will
// be copied to an SGPR with readfirstlane.
unsigned Opc = IntrID == Intrinsic::amdgcn_ds_append ?
  AMDGPU::DS_APPEND : AMDGPU::DS_CONSUME;

SDValue Chain = N->getOperand(0);
SDValue Ptr = N->getOperand(2);
MemIntrinsicSDNode *M = cast<MemIntrinsicSDNode>(N);
MachineMemOperand *MMO = M->getMemOperand();
bool IsGDS = M->getAddressSpace() == AMDGPUAS::REGION_ADDRESS;

SDValue Offset;
if (CurDAG->isBaseWithConstantOffset(Ptr)) {
  SDValue PtrBase = Ptr.getOperand(0);
  SDValue PtrOffset = Ptr.getOperand(1);

  const APInt &OffsetVal = cast<ConstantSDNode>(PtrOffset)->getAPIntValue();
  if (isDSOffsetLegal(PtrBase, OffsetVal.getZExtValue())) {
    N = glueCopyToM0(N, PtrBase);
    Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i32);
  }
}

if (!Offset) {
  N = glueCopyToM0(N, Ptr);
  Offset = CurDAG->getTargetConstant(0, SDLoc(), MVT::i32);
}

SDValue Ops[] = {
  Offset,
  CurDAG->getTargetConstant(IsGDS, SDLoc(), MVT::i32),
  Chain,
  N->getOperand(N->getNumOperands() - 1) // New glue
};

SDNode *Selected = CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
CurDAG->setNodeMemRefs(cast<MachineSDNode>(Selected), {MMO});
2539}

2541static unsigned gwsIntrinToOpcode(unsigned IntrID) {
switch (IntrID) {
case Intrinsic::amdgcn_ds_gws_init:
  return AMDGPU::DS_GWS_INIT;
case Intrinsic::amdgcn_ds_gws_barrier:
  return AMDGPU::DS_GWS_BARRIER;
case Intrinsic::amdgcn_ds_gws_sema_v:
  return AMDGPU::DS_GWS_SEMA_V;
case Intrinsic::amdgcn_ds_gws_sema_br:
  return AMDGPU::DS_GWS_SEMA_BR;
case Intrinsic::amdgcn_ds_gws_sema_p:
  return AMDGPU::DS_GWS_SEMA_P;
case Intrinsic::amdgcn_ds_gws_sema_release_all:
  return AMDGPU::DS_GWS_SEMA_RELEASE_ALL;
default:
  llvm_unreachable("not a gws intrinsic")__builtin_unreachable();
}
2558}

2560void AMDGPUDAGToDAGISel::SelectDS_GWS(SDNode *N, unsigned IntrID) {
if (IntrID == Intrinsic::amdgcn_ds_gws_sema_release_all &&
    !Subtarget->hasGWSSemaReleaseAll()) {
  // Let this error.
  SelectCode(N);
  return;
}

// Chain, intrinsic ID, vsrc, offset
const bool HasVSrc = N->getNumOperands() == 4;
assert(HasVSrc || N->getNumOperands() == 3)((void)0);

SDLoc SL(N);
SDValue BaseOffset = N->getOperand(HasVSrc ? 3 : 2);
int ImmOffset = 0;
MemIntrinsicSDNode *M = cast<MemIntrinsicSDNode>(N);
MachineMemOperand *MMO = M->getMemOperand();

// Don't worry if the offset ends up in a VGPR. Only one lane will have
// effect, so SIFixSGPRCopies will validly insert readfirstlane.

// The resource id offset is computed as (<isa opaque base> + M0[21:16] +
// offset field) % 64. Some versions of the programming guide omit the m0
// part, or claim it's from offset 0.
if (ConstantSDNode *ConstOffset = dyn_cast<ConstantSDNode>(BaseOffset)) {
  // If we have a constant offset, try to use the 0 in m0 as the base.
  // TODO: Look into changing the default m0 initialization value. If the
  // default -1 only set the low 16-bits, we could leave it as-is and add 1 to
  // the immediate offset.
  glueCopyToM0(N, CurDAG->getTargetConstant(0, SL, MVT::i32));
  ImmOffset = ConstOffset->getZExtValue();
} else {
  if (CurDAG->isBaseWithConstantOffset(BaseOffset)) {
    ImmOffset = BaseOffset.getConstantOperandVal(1);
    BaseOffset = BaseOffset.getOperand(0);
  }

  // Prefer to do the shift in an SGPR since it should be possible to use m0
  // as the result directly. If it's already an SGPR, it will be eliminated
  // later.
  SDNode *SGPROffset
    = CurDAG->getMachineNode(AMDGPU::V_READFIRSTLANE_B32, SL, MVT::i32,
                             BaseOffset);
  // Shift to offset in m0
  SDNode *M0Base
    = CurDAG->getMachineNode(AMDGPU::S_LSHL_B32, SL, MVT::i32,
                             SDValue(SGPROffset, 0),
                             CurDAG->getTargetConstant(16, SL, MVT::i32));
  glueCopyToM0(N, SDValue(M0Base, 0));
}

SDValue Chain = N->getOperand(0);
SDValue OffsetField = CurDAG->getTargetConstant(ImmOffset, SL, MVT::i32);

const unsigned Opc = gwsIntrinToOpcode(IntrID);
SmallVector<SDValue, 5> Ops;
if (HasVSrc)
  Ops.push_back(N->getOperand(2));
Ops.push_back(OffsetField);
Ops.push_back(Chain);

SDNode *Selected = CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
CurDAG->setNodeMemRefs(cast<MachineSDNode>(Selected), {MMO});
2623}

2625void AMDGPUDAGToDAGISel::SelectInterpP1F16(SDNode *N) {
if (Subtarget->getLDSBankCount() != 16) {
  // This is a single instruction with a pattern.
  SelectCode(N);
  return;
}

SDLoc DL(N);

// This requires 2 instructions. It is possible to write a pattern to support
// this, but the generated isel emitter doesn't correctly deal with multiple
// output instructions using the same physical register input. The copy to m0
// is incorrectly placed before the second instruction.
//
// TODO: Match source modifiers.
//
// def : Pat <
//   (int_amdgcn_interp_p1_f16
//    (VOP3Mods f32:$src0, i32:$src0_modifiers),
//                             (i32 timm:$attrchan), (i32 timm:$attr),
//                             (i1 timm:$high), M0),
//   (V_INTERP_P1LV_F16 $src0_modifiers, VGPR_32:$src0, timm:$attr,
//       timm:$attrchan, 0,
//       (V_INTERP_MOV_F32 2, timm:$attr, timm:$attrchan), timm:$high)> {
//   let Predicates = [has16BankLDS];
// }

// 16 bank LDS
SDValue ToM0 = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, AMDGPU::M0,
                                    N->getOperand(5), SDValue());

SDVTList VTs = CurDAG->getVTList(MVT::f32, MVT::Other);

SDNode *InterpMov =
  CurDAG->getMachineNode(AMDGPU::V_INTERP_MOV_F32, DL, VTs, {
      CurDAG->getTargetConstant(2, DL, MVT::i32), // P0
      N->getOperand(3),  // Attr
      N->getOperand(2),  // Attrchan
      ToM0.getValue(1) // In glue
});

SDNode *InterpP1LV =
  CurDAG->getMachineNode(AMDGPU::V_INTERP_P1LV_F16, DL, MVT::f32, {
      CurDAG->getTargetConstant(0, DL, MVT::i32), // $src0_modifiers
      N->getOperand(1), // Src0
      N->getOperand(3), // Attr
      N->getOperand(2), // Attrchan
      CurDAG->getTargetConstant(0, DL, MVT::i32), // $src2_modifiers
      SDValue(InterpMov, 0), // Src2 - holds two f16 values selected by high
      N->getOperand(4), // high
      CurDAG->getTargetConstant(0, DL, MVT::i1), // $clamp
      CurDAG->getTargetConstant(0, DL, MVT::i32), // $omod
      SDValue(InterpMov, 1)
});

CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), SDValue(InterpP1LV, 0));
2681}

2683void AMDGPUDAGToDAGISel::SelectINTRINSIC_W_CHAIN(SDNode *N) {
unsigned IntrID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
switch (IntrID) {
case Intrinsic::amdgcn_ds_append:
case Intrinsic::amdgcn_ds_consume: {
  if (N->getValueType(0) != MVT::i32)
    break;
  SelectDSAppendConsume(N, IntrID);
  return;
}
}

SelectCode(N);
2696}

2698void AMDGPUDAGToDAGISel::SelectINTRINSIC_WO_CHAIN(SDNode *N) {
unsigned IntrID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
unsigned Opcode;
switch (IntrID) {
case Intrinsic::amdgcn_wqm:
  Opcode = AMDGPU::WQM;
  break;
case Intrinsic::amdgcn_softwqm:
  Opcode = AMDGPU::SOFT_WQM;
  break;
case Intrinsic::amdgcn_wwm:
case Intrinsic::amdgcn_strict_wwm:
  Opcode = AMDGPU::STRICT_WWM;
  break;
case Intrinsic::amdgcn_strict_wqm:
  Opcode = AMDGPU::STRICT_WQM;
  break;
case Intrinsic::amdgcn_interp_p1_f16:
  SelectInterpP1F16(N);
  return;
default:
  SelectCode(N);
  return;
}

SDValue Src = N->getOperand(1);
CurDAG->SelectNodeTo(N, Opcode, N->getVTList(), {Src});
2725}

2727void AMDGPUDAGToDAGISel::SelectINTRINSIC_VOID(SDNode *N) {
unsigned IntrID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
switch (IntrID) {
case Intrinsic::amdgcn_ds_gws_init:
case Intrinsic::amdgcn_ds_gws_barrier:
case Intrinsic::amdgcn_ds_gws_sema_v:
case Intrinsic::amdgcn_ds_gws_sema_br:
case Intrinsic::amdgcn_ds_gws_sema_p:
case Intrinsic::amdgcn_ds_gws_sema_release_all:
  SelectDS_GWS(N, IntrID);
  return;
default:
  break;
}

SelectCode(N);
2743}

2745bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
                                          unsigned &Mods,
                                          bool AllowAbs) const {
Mods = 0;
Src = In;

if (Src.getOpcode() == ISD::FNEG) {
  Mods |= SISrcMods::NEG;
  Src = Src.getOperand(0);
}

if (AllowAbs && Src.getOpcode() == ISD::FABS) {
  Mods |= SISrcMods::ABS;
  Src = Src.getOperand(0);
}

return true;
2762}

2764bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
                                      SDValue &SrcMods) const {
unsigned Mods;
if (SelectVOP3ModsImpl(In, Src, Mods)) {
  SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
  return true;
}

return false;
2773}

2775bool AMDGPUDAGToDAGISel::SelectVOP3BMods(SDValue In, SDValue &Src,
                                       SDValue &SrcMods) const {
unsigned Mods;
if (SelectVOP3ModsImpl(In, Src, Mods, /* AllowAbs */ false)) {
  SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
  return true;
}

return false;
2784}

2786bool AMDGPUDAGToDAGISel::SelectVOP3Mods_NNaN(SDValue In, SDValue &Src,
                                           SDValue &SrcMods) const {
SelectVOP3Mods(In, Src, SrcMods);
return isNoNanSrc(Src);
2790}

2792bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src) const {
if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG)
  return false;

Src = In;
return true;
2798}

2800bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
                                       SDValue &SrcMods, SDValue &Clamp,
                                       SDValue &Omod) const {
SDLoc DL(In);
Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);

return SelectVOP3Mods(In, Src, SrcMods);
2808}

2810bool AMDGPUDAGToDAGISel::SelectVOP3BMods0(SDValue In, SDValue &Src,
                                        SDValue &SrcMods, SDValue &Clamp,
                                        SDValue &Omod) const {
SDLoc DL(In);
Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);

return SelectVOP3BMods(In, Src, SrcMods);
2818}

2820bool AMDGPUDAGToDAGISel::SelectVOP3OMods(SDValue In, SDValue &Src,
                                       SDValue &Clamp, SDValue &Omod) const {
Src = In;

SDLoc DL(In);
Clamp = CurDAG->getTargetConstant(0, DL, MVT::i1);
Omod = CurDAG->getTargetConstant(0, DL, MVT::i1);

return true;
2829}

2831bool AMDGPUDAGToDAGISel::SelectVOP3PMods(SDValue In, SDValue &Src,
                                       SDValue &SrcMods) const {
unsigned Mods = 0;
Src = In;

if (Src.getOpcode() == ISD::FNEG) {
  Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
  Src = Src.getOperand(0);
}

if (Src.getOpcode() == ISD::BUILD_VECTOR) {
  unsigned VecMods = Mods;

  SDValue Lo = stripBitcast(Src.getOperand(0));
  SDValue Hi = stripBitcast(Src.getOperand(1));

  if (Lo.getOpcode() == ISD::FNEG) {
    Lo = stripBitcast(Lo.getOperand(0));
    Mods ^= SISrcMods::NEG;
  }

  if (Hi.getOpcode() == ISD::FNEG) {
    Hi = stripBitcast(Hi.getOperand(0));
    Mods ^= SISrcMods::NEG_HI;
  }

  if (isExtractHiElt(Lo, Lo))
    Mods |= SISrcMods::OP_SEL_0;

  if (isExtractHiElt(Hi, Hi))
    Mods |= SISrcMods::OP_SEL_1;

  unsigned VecSize = Src.getValueSizeInBits();
  Lo = stripExtractLoElt(Lo);
  Hi = stripExtractLoElt(Hi);

  if (Lo.getValueSizeInBits() > VecSize) {
    Lo = CurDAG->getTargetExtractSubreg(
      (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In),
      MVT::getIntegerVT(VecSize), Lo);
  }

  if (Hi.getValueSizeInBits() > VecSize) {
    Hi = CurDAG->getTargetExtractSubreg(
      (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In),
      MVT::getIntegerVT(VecSize), Hi);
  }

  assert(Lo.getValueSizeInBits() <= VecSize &&((void)0)
         Hi.getValueSizeInBits() <= VecSize)((void)0);

  if (Lo == Hi && !isInlineImmediate(Lo.getNode())) {
    // Really a scalar input. Just select from the low half of the register to
    // avoid packing.

    if (VecSize == 32 || VecSize == Lo.getValueSizeInBits()) {
      Src = Lo;
    } else {
      assert(Lo.getValueSizeInBits() == 32 && VecSize == 64)((void)0);

      SDLoc SL(In);
      SDValue Undef = SDValue(
        CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SL,
                               Lo.getValueType()), 0);
      auto RC = Lo->isDivergent() ? AMDGPU::VReg_64RegClassID
                                  : AMDGPU::SReg_64RegClassID;
      const SDValue Ops[] = {
        CurDAG->getTargetConstant(RC, SL, MVT::i32),
        Lo, CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32),
        Undef, CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32) };

      Src = SDValue(CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SL,
                                           Src.getValueType(), Ops), 0);
    }
    SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
    return true;
  }

  if (VecSize == 64 && Lo == Hi && isa<ConstantFPSDNode>(Lo)) {
    uint64_t Lit = cast<ConstantFPSDNode>(Lo)->getValueAPF()
                    .bitcastToAPInt().getZExtValue();
    if (AMDGPU::isInlinableLiteral32(Lit, Subtarget->hasInv2PiInlineImm())) {
      Src = CurDAG->getTargetConstant(Lit, SDLoc(In), MVT::i64);;
      SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
      return true;
    }
  }

  Mods = VecMods;
}

// Packed instructions do not have abs modifiers.
Mods |= SISrcMods::OP_SEL_1;

SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
return true;
2927}

2929bool AMDGPUDAGToDAGISel::SelectVOP3OpSel(SDValue In, SDValue &Src,
                                       SDValue &SrcMods) const {
Src = In;
// FIXME: Handle op_sel
SrcMods = CurDAG->getTargetConstant(0, SDLoc(In), MVT::i32);
return true;
2935}

2937bool AMDGPUDAGToDAGISel::SelectVOP3OpSelMods(SDValue In, SDValue &Src,
                                           SDValue &SrcMods) const {
// FIXME: Handle op_sel
return SelectVOP3Mods(In, Src, SrcMods);
2941}

2943// The return value is not whether the match is possible (which it always is),
2944// but whether or not it a conversion is really used.
2945bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src,
                                                 unsigned &Mods) const {
Mods = 0;
SelectVOP3ModsImpl(In, Src, Mods);

if (Src.getOpcode() == ISD::FP_EXTEND) {
  Src = Src.getOperand(0);
  assert(Src.getValueType() == MVT::f16)((void)0);
  Src = stripBitcast(Src);

  // Be careful about folding modifiers if we already have an abs. fneg is
  // applied last, so we don't want to apply an earlier fneg.
  if ((Mods & SISrcMods::ABS) == 0) {
    unsigned ModsTmp;
    SelectVOP3ModsImpl(Src, Src, ModsTmp);

    if ((ModsTmp & SISrcMods::NEG) != 0)
      Mods ^= SISrcMods::NEG;

    if ((ModsTmp & SISrcMods::ABS) != 0)
      Mods |= SISrcMods::ABS;
  }

  // op_sel/op_sel_hi decide the source type and source.
  // If the source's op_sel_hi is set, it indicates to do a conversion from fp16.
  // If the sources's op_sel is set, it picks the high half of the source
  // register.

  Mods |= SISrcMods::OP_SEL_1;
  if (isExtractHiElt(Src, Src)) {
    Mods |= SISrcMods::OP_SEL_0;

    // TODO: Should we try to look for neg/abs here?
  }

  return true;
}

return false;
2984}

2986bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixMods(SDValue In, SDValue &Src,
                                             SDValue &SrcMods) const {
unsigned Mods = 0;
SelectVOP3PMadMixModsImpl(In, Src, Mods);
SrcMods = CurDAG->getTargetConstant(Mods, SDLoc(In), MVT::i32);
return true;
2992}

2994SDValue AMDGPUDAGToDAGISel::getHi16Elt(SDValue In) const {
if (In.isUndef())
11
←
Taking false branch→
  return CurDAG->getUNDEF(MVT::i32);

if (ConstantSDNode *C11.1
'C' is null
1
'C' is null
 = dyn_cast<ConstantSDNode>(In)) {
12
←
Taking false branch→
  SDLoc SL(In);
  return CurDAG->getConstant(C->getZExtValue() << 16, SL, MVT::i32);
}

if (ConstantFPSDNode *C12.1
'C' is null
1
'C' is null
 = dyn_cast<ConstantFPSDNode>(In)) {
13
←
Taking false branch→
  SDLoc SL(In);
  return CurDAG->getConstant(
    C->getValueAPF().bitcastToAPInt().getZExtValue() << 16, SL, MVT::i32);
}

SDValue Src;
if (isExtractHiElt(In, Src))
14
←
Calling 'isExtractHiElt'→
  return Src;

return SDValue();
3014}

3016bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
assert(CurDAG->getTarget().getTargetTriple().getArch() == Triple::amdgcn)((void)0);

const SIRegisterInfo *SIRI =
  static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
const SIInstrInfo * SII =
  static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());

unsigned Limit = 0;
bool AllUsesAcceptSReg = true;
for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
  Limit < 10 && U != E; ++U, ++Limit) {
  const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());

  // If the register class is unknown, it could be an unknown
  // register class that needs to be an SGPR, e.g. an inline asm
  // constraint
  if (!RC || SIRI->isSGPRClass(RC))
    return false;

  if (RC != &AMDGPU::VS_32RegClass) {
    AllUsesAcceptSReg = false;
    SDNode * User = *U;
    if (User->isMachineOpcode()) {
      unsigned Opc = User->getMachineOpcode();
      MCInstrDesc Desc = SII->get(Opc);
      if (Desc.isCommutable()) {
        unsigned OpIdx = Desc.getNumDefs() + U.getOperandNo();
        unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
        if (SII->findCommutedOpIndices(Desc, OpIdx, CommuteIdx1)) {
          unsigned CommutedOpNo = CommuteIdx1 - Desc.getNumDefs();
          const TargetRegisterClass *CommutedRC = getOperandRegClass(*U, CommutedOpNo);
          if (CommutedRC == &AMDGPU::VS_32RegClass)
            AllUsesAcceptSReg = true;
        }
      }
    }
    // If "AllUsesAcceptSReg == false" so far we haven't suceeded
    // commuting current user. This means have at least one use
    // that strictly require VGPR. Thus, we will not attempt to commute
    // other user instructions.
    if (!AllUsesAcceptSReg)
      break;
  }
}
return !AllUsesAcceptSReg && (Limit < 10);
3062}

3064bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode * N) const {
auto Ld = cast<LoadSDNode>(N);

return Ld->getAlignment() >= 4 &&
      (
        (
          (
            Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS       ||
            Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT
          )
          &&
          !N->isDivergent()
        )
        ||
        (
          Subtarget->getScalarizeGlobalBehavior() &&
          Ld->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
          Ld->isSimple() &&
          !N->isDivergent() &&
          static_cast<const SITargetLowering *>(
            getTargetLowering())->isMemOpHasNoClobberedMemOperand(N)
        )
      );
3087}

3089void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
const AMDGPUTargetLowering& Lowering =
  *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
bool IsModified = false;
do {
  IsModified = false;

  // Go over all selected nodes and try to fold them a bit more
  SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_begin();
  while (Position != CurDAG->allnodes_end()) {
    SDNode *Node = &*Position++;
    MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(Node);
    if (!MachineNode)
      continue;

    SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
    if (ResNode != Node) {
      if (ResNode)
        ReplaceUses(Node, ResNode);
      IsModified = true;
    }
  }
  CurDAG->RemoveDeadNodes();
} while (IsModified);
3113}

3115bool R600DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<R600Subtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
3118}

3120bool R600DAGToDAGISel::isConstantLoad(const MemSDNode *N, int CbId) const {
if (!N->readMem())
  return false;
if (CbId == -1)
  return N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
         N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT;

return N->getAddressSpace() == AMDGPUAS::CONSTANT_BUFFER_0 + CbId;
3128}

3130bool R600DAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
                                                       SDValue& IntPtr) {
if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
  IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
                                     true);
  return true;
}
return false;
3138}

3140bool R600DAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
  SDValue& BaseReg, SDValue &Offset) {
if (!isa<ConstantSDNode>(Addr)) {
  BaseReg = Addr;
  Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
  return true;
}
return false;
3148}

3150void R600DAGToDAGISel::Select(SDNode *N) {
unsigned int Opc = N->getOpcode();
if (N->isMachineOpcode()) {
  N->setNodeId(-1);
  return;   // Already selected.
}

switch (Opc) {
default: break;
case AMDGPUISD::BUILD_VERTICAL_VECTOR:
case ISD::SCALAR_TO_VECTOR:
case ISD::BUILD_VECTOR: {
  EVT VT = N->getValueType(0);
  unsigned NumVectorElts = VT.getVectorNumElements();
  unsigned RegClassID;
  // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
  // that adds a 128 bits reg copy when going through TwoAddressInstructions
  // pass. We want to avoid 128 bits copies as much as possible because they
  // can't be bundled by our scheduler.
  switch(NumVectorElts) {
  case 2: RegClassID = R600::R600_Reg64RegClassID; break;
  case 4:
    if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
      RegClassID = R600::R600_Reg128VerticalRegClassID;
    else
      RegClassID = R600::R600_Reg128RegClassID;
    break;
  default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR")__builtin_unreachable();
  }
  SelectBuildVector(N, RegClassID);
  return;
}
}

SelectCode(N);
3185}

3187bool R600DAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
                                        SDValue &Offset) {
ConstantSDNode *C;
SDLoc DL(Addr);

if ((C = dyn_cast<ConstantSDNode>(Addr))) {
  Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
  Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
} else if ((Addr.getOpcode() == AMDGPUISD::DWORDADDR) &&
           (C = dyn_cast<ConstantSDNode>(Addr.getOperand(0)))) {
  Base = CurDAG->getRegister(R600::INDIRECT_BASE_ADDR, MVT::i32);
  Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
} else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
          (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
  Base = Addr.getOperand(0);
  Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
} else {
  Base = Addr;
  Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
}

return true;
3209}

3211bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
                                        SDValue &Offset) {
ConstantSDNode *IMMOffset;

if (Addr.getOpcode() == ISD::ADD
    && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
    && isInt<16>(IMMOffset->getZExtValue())) {

    Base = Addr.getOperand(0);
    Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
                                       MVT::i32);
    return true;
// If the pointer address is constant, we can move it to the offset field.
} else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
           && isInt<16>(IMMOffset->getZExtValue())) {
  Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
                                SDLoc(CurDAG->getEntryNode()),
                                R600::ZERO, MVT::i32);
  Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
                                     MVT::i32);
  return true;
}

// Default case, no offset
Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
return true;
3238}

←

/usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG.  These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//

18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H

21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/Register.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DebugLoc.h"
37#include "llvm/IR/Instruction.h"
38#include "llvm/IR/Instructions.h"
39#include "llvm/IR/Metadata.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/Support/AlignOf.h"
42#include "llvm/Support/AtomicOrdering.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/MachineValueType.h"
46#include "llvm/Support/TypeSize.h"
47#include <algorithm>
48#include <cassert>
49#include <climits>
50#include <cstddef>
51#include <cstdint>
52#include <cstring>
53#include <iterator>
54#include <string>
55#include <tuple>

57namespace llvm {

59class APInt;
60class Constant;
61template <typename T> struct DenseMapInfo;
62class GlobalValue;
63class MachineBasicBlock;
64class MachineConstantPoolValue;
65class MCSymbol;
66class raw_ostream;
67class SDNode;
68class SelectionDAG;
69class Type;
70class Value;

72void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
                  bool force = false);

75/// This represents a list of ValueType's that has been intern'd by
76/// a SelectionDAG.  Instances of this simple value class are returned by
77/// SelectionDAG::getVTList(...).
78///
79struct SDVTList {
const EVT *VTs;
unsigned int NumVTs;
82};

84namespace ISD {

/// Node predicates

88/// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the
89/// same constant or undefined, return true and return the constant value in
90/// \p SplatValue.
91bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);

93/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
94/// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to
95/// true, it only checks BUILD_VECTOR.
96bool isConstantSplatVectorAllOnes(const SDNode *N,
                                bool BuildVectorOnly = false);

99/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
100/// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it
101/// only checks BUILD_VECTOR.
102bool isConstantSplatVectorAllZeros(const SDNode *N,
                                 bool BuildVectorOnly = false);

105/// Return true if the specified node is a BUILD_VECTOR where all of the
106/// elements are ~0 or undef.
107bool isBuildVectorAllOnes(const SDNode *N);

109/// Return true if the specified node is a BUILD_VECTOR where all of the
110/// elements are 0 or undef.
111bool isBuildVectorAllZeros(const SDNode *N);

113/// Return true if the specified node is a BUILD_VECTOR node of all
114/// ConstantSDNode or undef.
115bool isBuildVectorOfConstantSDNodes(const SDNode *N);

117/// Return true if the specified node is a BUILD_VECTOR node of all
118/// ConstantFPSDNode or undef.
119bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);

121/// Return true if the node has at least one operand and all operands of the
122/// specified node are ISD::UNDEF.
123bool allOperandsUndef(const SDNode *N);

125} // end namespace ISD

127//===----------------------------------------------------------------------===//
128/// Unlike LLVM values, Selection DAG nodes may return multiple
129/// values as the result of a computation.  Many nodes return multiple values,
130/// from loads (which define a token and a return value) to ADDC (which returns
131/// a result and a carry value), to calls (which may return an arbitrary number
132/// of values).
133///
134/// As such, each use of a SelectionDAG computation must indicate the node that
135/// computes it as well as which return value to use from that node.  This pair
136/// of information is represented with the SDValue value type.
137///
138class SDValue {
friend struct DenseMapInfo<SDValue>;

SDNode *Node = nullptr; // The node defining the value we are using.
unsigned ResNo = 0;     // Which return value of the node we are using.

144public:
SDValue() = default;
SDValue(SDNode *node, unsigned resno);

/// get the index which selects a specific result in the SDNode
unsigned getResNo() const { return ResNo; }

/// get the SDNode which holds the desired result
SDNode *getNode() const { return Node; }

/// set the SDNode
void setNode(SDNode *N) { Node = N; }

inline SDNode *operator->() const { return Node; }

bool operator==(const SDValue &O) const {
  return Node == O.Node && ResNo == O.ResNo;
}
bool operator!=(const SDValue &O) const {
  return !operator==(O);
}
bool operator<(const SDValue &O) const {
  return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
}
explicit operator bool() const {
  return Node != nullptr;
}

SDValue getValue(unsigned R) const {
  return SDValue(Node, R);
}

/// Return true if this node is an operand of N.
bool isOperandOf(const SDNode *N) const;

/// Return the ValueType of the referenced return value.
inline EVT getValueType() const;

/// Return the simple ValueType of the referenced return value.
MVT getSimpleValueType() const {
  return getValueType().getSimpleVT();
}

/// Returns the size of the value in bits.
///
/// If the value type is a scalable vector type, the scalable property will
/// be set and the runtime size will be a positive integer multiple of the
/// base size.
TypeSize getValueSizeInBits() const {
  return getValueType().getSizeInBits();
}

uint64_t getScalarValueSizeInBits() const {
  return getValueType().getScalarType().getFixedSizeInBits();
}

// Forwarding methods - These forward to the corresponding methods in SDNode.
inline unsigned getOpcode() const;
inline unsigned getNumOperands() const;
inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
inline const APInt &getConstantOperandAPInt(unsigned i) const;
inline bool isTargetMemoryOpcode() const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
inline bool isUndef() const;
inline unsigned getMachineOpcode() const;
inline const DebugLoc &getDebugLoc() const;
inline void dump() const;
inline void dump(const SelectionDAG *G) const;
inline void dumpr() const;
inline void dumpr(const SelectionDAG *G) const;

/// Return true if this operand (which must be a chain) reaches the
/// specified operand without crossing any side-effecting instructions.
/// In practice, this looks through token factors and non-volatile loads.
/// In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
bool reachesChainWithoutSideEffects(SDValue Dest,
                                    unsigned Depth = 2) const;

/// Return true if there are no nodes using value ResNo of Node.
inline bool use_empty() const;

/// Return true if there is exactly one node using value ResNo of Node.
inline bool hasOneUse() const;
230};

232template<> struct DenseMapInfo<SDValue> {
static inline SDValue getEmptyKey() {
  SDValue V;
  V.ResNo = -1U;
  return V;
}

static inline SDValue getTombstoneKey() {
  SDValue V;
  V.ResNo = -2U;
  return V;
}

static unsigned getHashValue(const SDValue &Val) {
  return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
          (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
}

static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
  return LHS == RHS;
}
253};

255/// Allow casting operators to work directly on
256/// SDValues as if they were SDNode*'s.
257template<> struct simplify_type<SDValue> {
using SimpleType = SDNode *;

static SimpleType getSimplifiedValue(SDValue &Val) {
  return Val.getNode();
}
263};
264template<> struct simplify_type<const SDValue> {
using SimpleType = /*const*/ SDNode *;

static SimpleType getSimplifiedValue(const SDValue &Val) {
  return Val.getNode();
}
270};

272/// Represents a use of a SDNode. This class holds an SDValue,
273/// which records the SDNode being used and the result number, a
274/// pointer to the SDNode using the value, and Next and Prev pointers,
275/// which link together all the uses of an SDNode.
276///
277class SDUse {
/// Val - The value being used.
SDValue Val;
/// User - The user of this value.
SDNode *User = nullptr;
/// Prev, Next - Pointers to the uses list of the SDNode referred by
/// this operand.
SDUse **Prev = nullptr;
SDUse *Next = nullptr;

287public:
SDUse() = default;
SDUse(const SDUse &U) = delete;
SDUse &operator=(const SDUse &) = delete;

/// Normally SDUse will just implicitly convert to an SDValue that it holds.
operator const SDValue&() const { return Val; }

/// If implicit conversion to SDValue doesn't work, the get() method returns
/// the SDValue.
const SDValue &get() const { return Val; }

/// This returns the SDNode that contains this Use.
SDNode *getUser() { return User; }

/// Get the next SDUse in the use list.
SDUse *getNext() const { return Next; }

/// Convenience function for get().getNode().
SDNode *getNode() const { return Val.getNode(); }
/// Convenience function for get().getResNo().
unsigned getResNo() const { return Val.getResNo(); }
/// Convenience function for get().getValueType().
EVT getValueType() const { return Val.getValueType(); }

/// Convenience function for get().operator==
bool operator==(const SDValue &V) const {
  return Val == V;
}

/// Convenience function for get().operator!=
bool operator!=(const SDValue &V) const {
  return Val != V;
}

/// Convenience function for get().operator<
bool operator<(const SDValue &V) const {
  return Val < V;
}

327private:
friend class SelectionDAG;
friend class SDNode;
// TODO: unfriend HandleSDNode once we fix its operand handling.
friend class HandleSDNode;

void setUser(SDNode *p) { User = p; }

/// Remove this use from its existing use list, assign it the
/// given value, and add it to the new value's node's use list.
inline void set(const SDValue &V);
/// Like set, but only supports initializing a newly-allocated
/// SDUse with a non-null value.
inline void setInitial(const SDValue &V);
/// Like set, but only sets the Node portion of the value,
/// leaving the ResNo portion unmodified.
inline void setNode(SDNode *N);

void addToList(SDUse **List) {
  Next = *List;
  if (Next) Next->Prev = &Next;
  Prev = List;
  *List = this;
}

void removeFromList() {
  *Prev = Next;
  if (Next) Next->Prev = Prev;
}
356};

358/// simplify_type specializations - Allow casting operators to work directly on
359/// SDValues as if they were SDNode*'s.
360template<> struct simplify_type<SDUse> {
using SimpleType = SDNode *;

static SimpleType getSimplifiedValue(SDUse &Val) {
  return Val.getNode();
}
366};

368/// These are IR-level optimization flags that may be propagated to SDNodes.
369/// TODO: This data structure should be shared by the IR optimizer and the
370/// the backend.
371struct SDNodeFlags {
372private:
bool NoUnsignedWrap : 1;
bool NoSignedWrap : 1;
bool Exact : 1;
bool NoNaNs : 1;
bool NoInfs : 1;
bool NoSignedZeros : 1;
bool AllowReciprocal : 1;
bool AllowContract : 1;
bool ApproximateFuncs : 1;
bool AllowReassociation : 1;

// We assume instructions do not raise floating-point exceptions by default,
// and only those marked explicitly may do so.  We could choose to represent
// this via a positive "FPExcept" flags like on the MI level, but having a
// negative "NoFPExcept" flag here (that defaults to true) makes the flag
// intersection logic more straightforward.
bool NoFPExcept : 1;

391public:
/// Default constructor turns off all optimization flags.
SDNodeFlags()
    : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false),
      NoInfs(false), NoSignedZeros(false), AllowReciprocal(false),
      AllowContract(false), ApproximateFuncs(false),
      AllowReassociation(false), NoFPExcept(false) {}

/// Propagate the fast-math-flags from an IR FPMathOperator.
void copyFMF(const FPMathOperator &FPMO) {
  setNoNaNs(FPMO.hasNoNaNs());
  setNoInfs(FPMO.hasNoInfs());
  setNoSignedZeros(FPMO.hasNoSignedZeros());
  setAllowReciprocal(FPMO.hasAllowReciprocal());
  setAllowContract(FPMO.hasAllowContract());
  setApproximateFuncs(FPMO.hasApproxFunc());
  setAllowReassociation(FPMO.hasAllowReassoc());
}

// These are mutators for each flag.
void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; }
void setNoSignedWrap(bool b) { NoSignedWrap = b; }
void setExact(bool b) { Exact = b; }
void setNoNaNs(bool b) { NoNaNs = b; }
void setNoInfs(bool b) { NoInfs = b; }
void setNoSignedZeros(bool b) { NoSignedZeros = b; }
void setAllowReciprocal(bool b) { AllowReciprocal = b; }
void setAllowContract(bool b) { AllowContract = b; }
void setApproximateFuncs(bool b) { ApproximateFuncs = b; }
void setAllowReassociation(bool b) { AllowReassociation = b; }
void setNoFPExcept(bool b) { NoFPExcept = b; }

// These are accessors for each flag.
bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
bool hasNoSignedWrap() const { return NoSignedWrap; }
bool hasExact() const { return Exact; }
bool hasNoNaNs() const { return NoNaNs; }
bool hasNoInfs() const { return NoInfs; }
bool hasNoSignedZeros() const { return NoSignedZeros; }
bool hasAllowReciprocal() const { return AllowReciprocal; }
bool hasAllowContract() const { return AllowContract; }
bool hasApproximateFuncs() const { return ApproximateFuncs; }
bool hasAllowReassociation() const { return AllowReassociation; }
bool hasNoFPExcept() const { return NoFPExcept; }

/// Clear any flags in this flag set that aren't also set in Flags. All
/// flags will be cleared if Flags are undefined.
void intersectWith(const SDNodeFlags Flags) {
  NoUnsignedWrap &= Flags.NoUnsignedWrap;
  NoSignedWrap &= Flags.NoSignedWrap;
  Exact &= Flags.Exact;
  NoNaNs &= Flags.NoNaNs;
  NoInfs &= Flags.NoInfs;
  NoSignedZeros &= Flags.NoSignedZeros;
  AllowReciprocal &= Flags.AllowReciprocal;
  AllowContract &= Flags.AllowContract;
  ApproximateFuncs &= Flags.ApproximateFuncs;
  AllowReassociation &= Flags.AllowReassociation;
  NoFPExcept &= Flags.NoFPExcept;
}
451};

453/// Represents one node in the SelectionDAG.
454///
455class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
456private:
/// The operation that this node performs.
int16_t NodeType;

460protected:
// We define a set of mini-helper classes to help us interpret the bits in our
// SubclassData.  These are designed to fit within a uint16_t so they pack
// with NodeType.

465#if defined(_AIX) && (!defined(__GNUC__4) || defined(__clang__1))
466// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
467// and give the `pack` pragma push semantics.
468#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
469#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
470#else
471#define BEGIN_TWO_BYTE_PACK()
472#define END_TWO_BYTE_PACK()
473#endif

475BEGIN_TWO_BYTE_PACK()
class SDNodeBitfields {
  friend class SDNode;
  friend class MemIntrinsicSDNode;
  friend class MemSDNode;
  friend class SelectionDAG;

  uint16_t HasDebugValue : 1;
  uint16_t IsMemIntrinsic : 1;
  uint16_t IsDivergent : 1;
};
enum { NumSDNodeBits = 3 };

class ConstantSDNodeBitfields {
  friend class ConstantSDNode;

  uint16_t : NumSDNodeBits;

  uint16_t IsOpaque : 1;
};

class MemSDNodeBitfields {
  friend class MemSDNode;
  friend class MemIntrinsicSDNode;
  friend class AtomicSDNode;

  uint16_t : NumSDNodeBits;

  uint16_t IsVolatile : 1;
  uint16_t IsNonTemporal : 1;
  uint16_t IsDereferenceable : 1;
  uint16_t IsInvariant : 1;
};
enum { NumMemSDNodeBits = NumSDNodeBits + 4 };

class LSBaseSDNodeBitfields {
  friend class LSBaseSDNode;
  friend class MaskedLoadStoreSDNode;
  friend class MaskedGatherScatterSDNode;

  uint16_t : NumMemSDNodeBits;

  // This storage is shared between disparate class hierarchies to hold an
  // enumeration specific to the class hierarchy in use.
  //   LSBaseSDNode => enum ISD::MemIndexedMode
  //   MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
  //   MaskedGatherScatterSDNode => enum ISD::MemIndexType
  uint16_t AddressingMode : 3;
};
enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };

class LoadSDNodeBitfields {
  friend class LoadSDNode;
  friend class MaskedLoadSDNode;
  friend class MaskedGatherSDNode;

  uint16_t : NumLSBaseSDNodeBits;

  uint16_t ExtTy : 2; // enum ISD::LoadExtType
  uint16_t IsExpanding : 1;
};

class StoreSDNodeBitfields {
  friend class StoreSDNode;
  friend class MaskedStoreSDNode;
  friend class MaskedScatterSDNode;

  uint16_t : NumLSBaseSDNodeBits;

  uint16_t IsTruncating : 1;
  uint16_t IsCompressing : 1;
};

union {
  char RawSDNodeBits[sizeof(uint16_t)];
  SDNodeBitfields SDNodeBits;
  ConstantSDNodeBitfields ConstantSDNodeBits;
  MemSDNodeBitfields MemSDNodeBits;
  LSBaseSDNodeBitfields LSBaseSDNodeBits;
  LoadSDNodeBitfields LoadSDNodeBits;
  StoreSDNodeBitfields StoreSDNodeBits;
};
557END_TWO_BYTE_PACK()
558#undef BEGIN_TWO_BYTE_PACK
559#undef END_TWO_BYTE_PACK

// RawSDNodeBits must cover the entirety of the union.  This means that all of
// the union's members must have size <= RawSDNodeBits.  We write the RHS as
// "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");

571private:
friend class SelectionDAG;
// TODO: unfriend HandleSDNode once we fix its operand handling.
friend class HandleSDNode;

/// Unique id per SDNode in the DAG.
int NodeId = -1;

/// The values that are used by this operation.
SDUse *OperandList = nullptr;

/// The types of the values this node defines.  SDNode's may
/// define multiple values simultaneously.
const EVT *ValueList;

/// List of uses for this SDNode.
SDUse *UseList = nullptr;

/// The number of entries in the Operand/Value list.
unsigned short NumOperands = 0;
unsigned short NumValues;

// The ordering of the SDNodes. It roughly corresponds to the ordering of the
// original LLVM instructions.
// This is used for turning off scheduling, because we'll forgo
// the normal scheduling algorithms and output the instructions according to
// this ordering.
unsigned IROrder;

/// Source line information.
DebugLoc debugLoc;

/// Return a pointer to the specified value type.
static const EVT *getValueTypeList(EVT VT);

SDNodeFlags Flags;

608public:
/// Unique and persistent id per SDNode in the DAG.
/// Used for debug printing.
uint16_t PersistentId;

//===--------------------------------------------------------------------===//
//  Accessors
//

/// Return the SelectionDAG opcode value for this node. For
/// pre-isel nodes (those for which isMachineOpcode returns false), these
/// are the opcode values in the ISD and <target>ISD namespaces. For
/// post-isel opcodes, see getMachineOpcode.
unsigned getOpcode()  const { return (unsigned short)NodeType; }

/// Test if this node has a target-specific opcode (in the
/// \<target\>ISD namespace).
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }

/// Test if this node has a target-specific opcode that may raise
/// FP exceptions (in the \<target\>ISD namespace and greater than
/// FIRST_TARGET_STRICTFP_OPCODE).  Note that all target memory
/// opcode are currently automatically considered to possibly raise
/// FP exceptions as well.
bool isTargetStrictFPOpcode() const {
  return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
}

/// Test if this node has a target-specific
/// memory-referencing opcode (in the \<target\>ISD namespace and
/// greater than FIRST_TARGET_MEMORY_OPCODE).
bool isTargetMemoryOpcode() const {
  return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
}

/// Return true if the type of the node type undefined.
bool isUndef() const { return NodeType == ISD::UNDEF; }

/// Test if this node is a memory intrinsic (with valid pointer information).
/// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
/// non-memory intrinsics (with chains) that are not really instances of
/// MemSDNode. For such nodes, we need some extra state to determine the
/// proper classof relationship.
bool isMemIntrinsic() const {
  return (NodeType == ISD::INTRINSIC_W_CHAIN ||
          NodeType == ISD::INTRINSIC_VOID) &&
         SDNodeBits.IsMemIntrinsic;
}

/// Test if this node is a strict floating point pseudo-op.
bool isStrictFPOpcode() {
  switch (NodeType) {
    default:
      return false;
    case ISD::STRICT_FP16_TO_FP:
    case ISD::STRICT_FP_TO_FP16:
664#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)               \
    case ISD::STRICT_##DAGN:
666#include "llvm/IR/ConstrainedOps.def"
      return true;
  }
}

/// Test if this node has a post-isel opcode, directly
/// corresponding to a MachineInstr opcode.
bool isMachineOpcode() const { return NodeType < 0; }

/// This may only be called if isMachineOpcode returns
/// true. It returns the MachineInstr opcode value that the node's opcode
/// corresponds to.
unsigned getMachineOpcode() const {
  assert(isMachineOpcode() && "Not a MachineInstr opcode!")((void)0);
  return ~NodeType;
}

bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }

bool isDivergent() const { return SDNodeBits.IsDivergent; }

/// Return true if there are no uses of this node.
bool use_empty() const { return UseList == nullptr; }

/// Return true if there is exactly one use of this node.
bool hasOneUse() const { return hasSingleElement(uses()); }

/// Return the number of uses of this node. This method takes
/// time proportional to the number of uses.
size_t use_size() const { return std::distance(use_begin(), use_end()); }

/// Return the unique node id.
int getNodeId() const { return NodeId; }

/// Set unique node id.
void setNodeId(int Id) { NodeId = Id; }

/// Return the node ordering.
unsigned getIROrder() const { return IROrder; }

/// Set the node ordering.
void setIROrder(unsigned Order) { IROrder = Order; }

/// Return the source location info.
const DebugLoc &getDebugLoc() const { return debugLoc; }

/// Set source location info.  Try to avoid this, putting
/// it in the constructor is preferable.
void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }

/// This class provides iterator support for SDUse
/// operands that use a specific SDNode.
class use_iterator {
  friend class SDNode;

  SDUse *Op = nullptr;

  explicit use_iterator(SDUse *op) : Op(op) {}

public:
  using iterator_category = std::forward_iterator_tag;
  using value_type = SDUse;
  using difference_type = std::ptrdiff_t;
  using pointer = value_type *;
  using reference = value_type &;

  use_iterator() = default;
  use_iterator(const use_iterator &I) : Op(I.Op) {}

  bool operator==(const use_iterator &x) const {
    return Op == x.Op;
  }
  bool operator!=(const use_iterator &x) const {
    return !operator==(x);
  }

  /// Return true if this iterator is at the end of uses list.
  bool atEnd() const { return Op == nullptr; }

  // Iterator traversal: forward iteration only.
  use_iterator &operator++() {          // Preincrement
    assert(Op && "Cannot increment end iterator!")((void)0);
    Op = Op->getNext();
    return *this;
  }

  use_iterator operator++(int) {        // Postincrement
    use_iterator tmp = *this; ++*this; return tmp;
  }

  /// Retrieve a pointer to the current user node.
  SDNode *operator*() const {
    assert(Op && "Cannot dereference end iterator!")((void)0);
    return Op->getUser();
  }

  SDNode *operator->() const { return operator*(); }

  SDUse &getUse() const { return *Op; }

  /// Retrieve the operand # of this use in its user.
  unsigned getOperandNo() const {
    assert(Op && "Cannot dereference end iterator!")((void)0);
    return (unsigned)(Op - Op->getUser()->OperandList);
  }
};

/// Provide iteration support to walk over all uses of an SDNode.
use_iterator use_begin() const {
  return use_iterator(UseList);
}

static use_iterator use_end() { return use_iterator(nullptr); }

inline iterator_range<use_iterator> uses() {
  return make_range(use_begin(), use_end());
}
inline iterator_range<use_iterator> uses() const {
  return make_range(use_begin(), use_end());
}

/// Return true if there are exactly NUSES uses of the indicated value.
/// This method ignores uses of other values defined by this operation.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;

/// Return true if there are any use of the indicated value.
/// This method ignores uses of other values defined by this operation.
bool hasAnyUseOfValue(unsigned Value) const;

/// Return true if this node is the only use of N.
bool isOnlyUserOf(const SDNode *N) const;

/// Return true if this node is an operand of N.
bool isOperandOf(const SDNode *N) const;

/// Return true if this node is a predecessor of N.
/// NOTE: Implemented on top of hasPredecessor and every bit as
/// expensive. Use carefully.
bool isPredecessorOf(const SDNode *N) const {
  return N->hasPredecessor(this);
}

/// Return true if N is a predecessor of this node.
/// N is either an operand of this node, or can be reached by recursively
/// traversing up the operands.
/// NOTE: This is an expensive method. Use it carefully.
bool hasPredecessor(const SDNode *N) const;

/// Returns true if N is a predecessor of any node in Worklist. This
/// helper keeps Visited and Worklist sets externally to allow unions
/// searches to be performed in parallel, caching of results across
/// queries and incremental addition to Worklist. Stops early if N is
/// found but will resume. Remember to clear Visited and Worklists
/// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
/// giving up. The TopologicalPrune flag signals that positive NodeIds are
/// topologically ordered (Operands have strictly smaller node id) and search
/// can be pruned leveraging this.
static bool hasPredecessorHelper(const SDNode *N,
                                 SmallPtrSetImpl<const SDNode *> &Visited,
                                 SmallVectorImpl<const SDNode *> &Worklist,
                                 unsigned int MaxSteps = 0,
                                 bool TopologicalPrune = false) {
  SmallVector<const SDNode *, 8> DeferredNodes;
  if (Visited.count(N))
    return true;

  // Node Id's are assigned in three places: As a topological
  // ordering (> 0), during legalization (results in values set to
  // 0), new nodes (set to -1). If N has a topolgical id then we
  // know that all nodes with ids smaller than it cannot be
  // successors and we need not check them. Filter out all node
  // that can't be matches. We add them to the worklist before exit
  // in case of multiple calls. Note that during selection the topological id
  // may be violated if a node's predecessor is selected before it. We mark
  // this at selection negating the id of unselected successors and
  // restricting topological pruning to positive ids.

  int NId = N->getNodeId();
  // If we Invalidated the Id, reconstruct original NId.
  if (NId < -1)
    NId = -(NId + 1);

  bool Found = false;
  while (!Worklist.empty()) {
    const SDNode *M = Worklist.pop_back_val();
    int MId = M->getNodeId();
    if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
        (MId > 0) && (MId < NId)) {
      DeferredNodes.push_back(M);
      continue;
    }
    for (const SDValue &OpV : M->op_values()) {
      SDNode *Op = OpV.getNode();
      if (Visited.insert(Op).second)
        Worklist.push_back(Op);
      if (Op == N)
        Found = true;
    }
    if (Found)
      break;
    if (MaxSteps != 0 && Visited.size() >= MaxSteps)
      break;
  }
  // Push deferred nodes back on worklist.
  Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
  // If we bailed early, conservatively return found.
  if (MaxSteps != 0 && Visited.size() >= MaxSteps)
    return true;
  return Found;
}

/// Return true if all the users of N are contained in Nodes.
/// NOTE: Requires at least one match, but doesn't require them all.
static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);

/// Return the number of values used by this operation.
unsigned getNumOperands() const { return NumOperands; }

/// Return the maximum number of operands that a SDNode can hold.
static constexpr size_t getMaxNumOperands() {
  return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
}

/// Helper method returns the integer value of a ConstantSDNode operand.
inline uint64_t getConstantOperandVal(unsigned Num) const;

/// Helper method returns the APInt of a ConstantSDNode operand.
inline const APInt &getConstantOperandAPInt(unsigned Num) const;

const SDValue &getOperand(unsigned Num) const {
  assert(Num < NumOperands && "Invalid child # of SDNode!")((void)0);
  return OperandList[Num];
}

using op_iterator = SDUse *;

op_iterator op_begin() const { return OperandList; }
op_iterator op_end() const { return OperandList+NumOperands; }
ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }

/// Iterator for directly iterating over the operand SDValue's.
struct value_op_iterator
    : iterator_adaptor_base<value_op_iterator, op_iterator,
                            std::random_access_iterator_tag, SDValue,
                            ptrdiff_t, value_op_iterator *,
                            value_op_iterator *> {
  explicit value_op_iterator(SDUse *U = nullptr)
    : iterator_adaptor_base(U) {}

  const SDValue &operator*() const { return I->get(); }
};

iterator_range<value_op_iterator> op_values() const {
  return make_range(value_op_iterator(op_begin()),
                    value_op_iterator(op_end()));
}

SDVTList getVTList() const {
  SDVTList X = { ValueList, NumValues };
  return X;
}

/// If this node has a glue operand, return the node
/// to which the glue operand points. Otherwise return NULL.
SDNode *getGluedNode() const {
  if (getNumOperands() != 0 &&
      getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
    return getOperand(getNumOperands()-1).getNode();
  return nullptr;
}

/// If this node has a glue value with a user, return
/// the user (there is at most one). Otherwise return NULL.
SDNode *getGluedUser() const {
  for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
    if (UI.getUse().get().getValueType() == MVT::Glue)
      return *UI;
  return nullptr;
}

SDNodeFlags getFlags() const { return Flags; }
void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }

/// Clear any flags in this node that aren't also set in Flags.
/// If Flags is not in a defined state then this has no effect.
void intersectFlagsWith(const SDNodeFlags Flags);

/// Return the number of values defined/returned by this operator.
unsigned getNumValues() const { return NumValues; }

/// Return the type of a specified result.
EVT getValueType(unsigned ResNo) const {
  assert(ResNo < NumValues && "Illegal result number!")((void)0);
  return ValueList[ResNo];
}

/// Return the type of a specified result as a simple type.
MVT getSimpleValueType(unsigned ResNo) const {
  return getValueType(ResNo).getSimpleVT();
}

/// Returns MVT::getSizeInBits(getValueType(ResNo)).
///
/// If the value type is a scalable vector type, the scalable property will
/// be set and the runtime size will be a positive integer multiple of the
/// base size.
TypeSize getValueSizeInBits(unsigned ResNo) const {
  return getValueType(ResNo).getSizeInBits();
}

using value_iterator = const EVT *;

value_iterator value_begin() const { return ValueList; }
value_iterator value_end() const { return ValueList+NumValues; }
iterator_range<value_iterator> values() const {
  return llvm::make_range(value_begin(), value_end());
}

/// Return the opcode of this operation for printing.
std::string getOperationName(const SelectionDAG *G = nullptr) const;
static const char* getIndexedModeName(ISD::MemIndexedMode AM);
void print_types(raw_ostream &OS, const SelectionDAG *G) const;
void print_details(raw_ostream &OS, const SelectionDAG *G) const;
void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;

/// Print a SelectionDAG node and all children down to
/// the leaves.  The given SelectionDAG allows target-specific nodes
/// to be printed in human-readable form.  Unlike printr, this will
/// print the whole DAG, including children that appear multiple
/// times.
///
void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;

/// Print a SelectionDAG node and children up to
/// depth "depth."  The given SelectionDAG allows target-specific
/// nodes to be printed in human-readable form.  Unlike printr, this
/// will print children that appear multiple times wherever they are
/// used.
///
void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
                     unsigned depth = 100) const;

/// Dump this node, for debugging.
void dump() const;

/// Dump (recursively) this node and its use-def subgraph.
void dumpr() const;

/// Dump this node, for debugging.
/// The given SelectionDAG allows target-specific nodes to be printed
/// in human-readable form.
void dump(const SelectionDAG *G) const;

/// Dump (recursively) this node and its use-def subgraph.
/// The given SelectionDAG allows target-specific nodes to be printed
/// in human-readable form.
void dumpr(const SelectionDAG *G) const;

/// printrFull to dbgs().  The given SelectionDAG allows
/// target-specific nodes to be printed in human-readable form.
/// Unlike dumpr, this will print the whole DAG, including children
/// that appear multiple times.
void dumprFull(const SelectionDAG *G = nullptr) const;

/// printrWithDepth to dbgs().  The given
/// SelectionDAG allows target-specific nodes to be printed in
/// human-readable form.  Unlike dumpr, this will print children
/// that appear multiple times wherever they are used.
///
void dumprWithDepth(const SelectionDAG *G = nullptr,
                    unsigned depth = 100) const;

/// Gather unique data for the node.
void Profile(FoldingSetNodeID &ID) const;

/// This method should only be used by the SDUse class.
void addUse(SDUse &U) { U.addToList(&UseList); }

1046protected:
static SDVTList getSDVTList(EVT VT) {
  SDVTList Ret = { getValueTypeList(VT), 1 };
  return Ret;
}

/// Create an SDNode.
///
/// SDNodes are created without any operands, and never own the operand
/// storage. To add operands, see SelectionDAG::createOperands.
SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
    : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
      IROrder(Order), debugLoc(std::move(dl)) {
  memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((void)0);
  assert(NumValues == VTs.NumVTs &&((void)0)
         "NumValues wasn't wide enough for its operands!")((void)0);
}

/// Release the operands and set this node to have zero operands.
void DropOperands();
1067};

1069/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1070/// into SDNode creation functions.
1071/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1072/// from the original Instruction, and IROrder is the ordinal position of
1073/// the instruction.
1074/// When an SDNode is created after the DAG is being built, both DebugLoc and
1075/// the IROrder are propagated from the original SDNode.
1076/// So SDLoc class provides two constructors besides the default one, one to
1077/// be used by the DAGBuilder, the other to be used by others.
1078class SDLoc {
1079private:
DebugLoc DL;
int IROrder = 0;

1083public:
SDLoc() = default;
SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
SDLoc(const Instruction *I, int Order) : IROrder(Order) {
  assert(Order >= 0 && "bad IROrder")((void)0);
  if (I)
    DL = I->getDebugLoc();
}

unsigned getIROrder() const { return IROrder; }
const DebugLoc &getDebugLoc() const { return DL; }
1095};

1097// Define inline functions from the SDValue class.

1099inline SDValue::SDValue(SDNode *node, unsigned resno)
  : Node(node), ResNo(resno) {
// Explicitly check for !ResNo to avoid use-after-free, because there are
// callers that use SDValue(N, 0) with a deleted N to indicate successful
// combines.
assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&((void)0)
       "Invalid result number for the given node!")((void)0);
assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((void)0);
1107}

1109inline unsigned SDValue::getOpcode() const {
return Node->getOpcode();
17
←
Called C++ object pointer is null
1111}

1113inline EVT SDValue::getValueType() const {
return Node->getValueType(ResNo);
1115}

1117inline unsigned SDValue::getNumOperands() const {
return Node->getNumOperands();
1119}

1121inline const SDValue &SDValue::getOperand(unsigned i) const {
return Node->getOperand(i);
1123}

1125inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
return Node->getConstantOperandVal(i);
1127}

1129inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
return Node->getConstantOperandAPInt(i);
1131}

1133inline bool SDValue::isTargetOpcode() const {
return Node->isTargetOpcode();
1135}

1137inline bool SDValue::isTargetMemoryOpcode() const {
return Node->isTargetMemoryOpcode();
1139}

1141inline bool SDValue::isMachineOpcode() const {
return Node->isMachineOpcode();
1143}

1145inline unsigned SDValue::getMachineOpcode() const {
return Node->getMachineOpcode();
1147}

1149inline bool SDValue::isUndef() const {
return Node->isUndef();
1151}

1153inline bool SDValue::use_empty() const {
return !Node->hasAnyUseOfValue(ResNo);
1155}

1157inline bool SDValue::hasOneUse() const {
return Node->hasNUsesOfValue(1, ResNo);
1159}

1161inline const DebugLoc &SDValue::getDebugLoc() const {
return Node->getDebugLoc();
1163}

1165inline void SDValue::dump() const {
return Node->dump();
1167}

1169inline void SDValue::dump(const SelectionDAG *G) const {
return Node->dump(G);
1171}

1173inline void SDValue::dumpr() const {
return Node->dumpr();
1175}

1177inline void SDValue::dumpr(const SelectionDAG *G) const {
return Node->dumpr(G);
1179}

1181// Define inline functions from the SDUse class.

1183inline void SDUse::set(const SDValue &V) {
if (Val.getNode()) removeFromList();
Val = V;
if (V.getNode()) V.getNode()->addUse(*this);
1187}

1189inline void SDUse::setInitial(const SDValue &V) {
Val = V;
V.getNode()->addUse(*this);
1192}

1194inline void SDUse::setNode(SDNode *N) {
if (Val.getNode()) removeFromList();
Val.setNode(N);
if (N) N->addUse(*this);
1198}

1200/// This class is used to form a handle around another node that
1201/// is persistent and is updated across invocations of replaceAllUsesWith on its
1202/// operand.  This node should be directly created by end-users and not added to
1203/// the AllNodes list.
1204class HandleSDNode : public SDNode {
SDUse Op;

1207public:
explicit HandleSDNode(SDValue X)
  : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
  // HandleSDNodes are never inserted into the DAG, so they won't be
  // auto-numbered. Use ID 65535 as a sentinel.
  PersistentId = 0xffff;

  // Manually set up the operand list. This node type is special in that it's
  // always stack allocated and SelectionDAG does not manage its operands.
  // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
  // be so special.
  Op.setUser(this);
  Op.setInitial(X);
  NumOperands = 1;
  OperandList = &Op;
}
~HandleSDNode();

const SDValue &getValue() const { return Op; }
1226};

1228class AddrSpaceCastSDNode : public SDNode {
1229private:
unsigned SrcAddrSpace;
unsigned DestAddrSpace;

1233public:
AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
                    unsigned SrcAS, unsigned DestAS);

unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
unsigned getDestAddressSpace() const { return DestAddrSpace; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ADDRSPACECAST;
}
1243};

1245/// This is an abstract virtual class for memory operations.
1246class MemSDNode : public SDNode {
1247private:
// VT of in-memory value.
EVT MemoryVT;

1251protected:
/// Memory reference information.
MachineMemOperand *MMO;

1255public:
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
          EVT memvt, MachineMemOperand *MMO);

bool readMem() const { return MMO->isLoad(); }
bool writeMem() const { return MMO->isStore(); }

/// Returns alignment and volatility of the memory access
Align getOriginalAlign() const { return MMO->getBaseAlign(); }
Align getAlign() const { return MMO->getAlign(); }
// FIXME: Remove once transition to getAlign is over.
unsigned getAlignment() const { return MMO->getAlign().value(); }

/// Return the SubclassData value, without HasDebugValue. This contains an
/// encoding of the volatile flag, as well as bits used by subclasses. This
/// function should only be used to compute a FoldingSetNodeID value.
/// The HasDebugValue bit is masked out because CSE map needs to match
/// nodes with debug info with nodes without debug info. Same is about
/// isDivergent bit.
unsigned getRawSubclassData() const {
  uint16_t Data;
  union {
    char RawSDNodeBits[sizeof(uint16_t)];
    SDNodeBitfields SDNodeBits;
  };
  memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
  SDNodeBits.HasDebugValue = 0;
  SDNodeBits.IsDivergent = false;
  memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
  return Data;
}

bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
bool isInvariant() const { return MemSDNodeBits.IsInvariant; }

// Returns the offset from the location of the access.
int64_t getSrcValueOffset() const { return MMO->getOffset(); }

/// Returns the AA info that describes the dereference.
AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }

/// Returns the Ranges that describes the dereference.
const MDNode *getRanges() const { return MMO->getRanges(); }

/// Returns the synchronization scope ID for this memory operation.
SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }

/// Return the atomic ordering requirements for this memory operation. For
/// cmpxchg atomic operations, return the atomic ordering requirements when
/// store occurs.
AtomicOrdering getSuccessOrdering() const {
  return MMO->getSuccessOrdering();
}

/// Return a single atomic ordering that is at least as strong as both the
/// success and failure orderings for an atomic operation.  (For operations
/// other than cmpxchg, this is equivalent to getSuccessOrdering().)
AtomicOrdering getMergedOrdering() const { return MMO->getMergedOrdering(); }

/// Return true if the memory operation ordering is Unordered or higher.
bool isAtomic() const { return MMO->isAtomic(); }

/// Returns true if the memory operation doesn't imply any ordering
/// constraints on surrounding memory operations beyond the normal memory
/// aliasing rules.
bool isUnordered() const { return MMO->isUnordered(); }

/// Returns true if the memory operation is neither atomic or volatile.
bool isSimple() const { return !isAtomic() && !isVolatile(); }

/// Return the type of the in-memory value.
EVT getMemoryVT() const { return MemoryVT; }

/// Return a MachineMemOperand object describing the memory
/// reference performed by operation.
MachineMemOperand *getMemOperand() const { return MMO; }

const MachinePointerInfo &getPointerInfo() const {
  return MMO->getPointerInfo();
}

/// Return the address space for the associated pointer
unsigned getAddressSpace() const {
  return getPointerInfo().getAddrSpace();
}

/// Update this MemSDNode's MachineMemOperand information
/// to reflect the alignment of NewMMO, if it has a greater alignment.
/// This must only be used when the new alignment applies to all users of
/// this MachineMemOperand.
void refineAlignment(const MachineMemOperand *NewMMO) {
  MMO->refineAlignment(NewMMO);
}

const SDValue &getChain() const { return getOperand(0); }

const SDValue &getBasePtr() const {
  switch (getOpcode()) {
  case ISD::STORE:
  case ISD::MSTORE:
    return getOperand(2);
  case ISD::MGATHER:
  case ISD::MSCATTER:
    return getOperand(3);
  default:
    return getOperand(1);
  }
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  // For some targets, we lower some target intrinsics to a MemIntrinsicNode
  // with either an intrinsic or a target opcode.
  switch (N->getOpcode()) {
  case ISD::LOAD:
  case ISD::STORE:
  case ISD::PREFETCH:
  case ISD::ATOMIC_CMP_SWAP:
  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
  case ISD::ATOMIC_SWAP:
  case ISD::ATOMIC_LOAD_ADD:
  case ISD::ATOMIC_LOAD_SUB:
  case ISD::ATOMIC_LOAD_AND:
  case ISD::ATOMIC_LOAD_CLR:
  case ISD::ATOMIC_LOAD_OR:
  case ISD::ATOMIC_LOAD_XOR:
  case ISD::ATOMIC_LOAD_NAND:
  case ISD::ATOMIC_LOAD_MIN:
  case ISD::ATOMIC_LOAD_MAX:
  case ISD::ATOMIC_LOAD_UMIN:
  case ISD::ATOMIC_LOAD_UMAX:
  case ISD::ATOMIC_LOAD_FADD:
  case ISD::ATOMIC_LOAD_FSUB:
  case ISD::ATOMIC_LOAD:
  case ISD::ATOMIC_STORE:
  case ISD::MLOAD:
  case ISD::MSTORE:
  case ISD::MGATHER:
  case ISD::MSCATTER:
    return true;
  default:
    return N->isMemIntrinsic() || N->isTargetMemoryOpcode();
  }
}
1401};

1403/// This is an SDNode representing atomic operations.
1404class AtomicSDNode : public MemSDNode {
1405public:
AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
             EVT MemVT, MachineMemOperand *MMO)
  : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
  assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((void)0)
          MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((void)0);
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getVal() const { return getOperand(2); }

/// Returns true if this SDNode represents cmpxchg atomic operation, false
/// otherwise.
bool isCompareAndSwap() const {
  unsigned Op = getOpcode();
  return Op == ISD::ATOMIC_CMP_SWAP ||
         Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
}

/// For cmpxchg atomic operations, return the atomic ordering requirements
/// when store does not occur.
AtomicOrdering getFailureOrdering() const {
  assert(isCompareAndSwap() && "Must be cmpxchg operation")((void)0);
  return MMO->getFailureOrdering();
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||
         N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
         N->getOpcode() == ISD::ATOMIC_SWAP         ||
         N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_SUB     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_AND     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_CLR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_OR      ||
         N->getOpcode() == ISD::ATOMIC_LOAD_XOR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_NAND    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MIN     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MAX     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMIN    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMAX    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FADD    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FSUB    ||
         N->getOpcode() == ISD::ATOMIC_LOAD         ||
         N->getOpcode() == ISD::ATOMIC_STORE;
}
1452};

1454/// This SDNode is used for target intrinsics that touch
1455/// memory and need an associated MachineMemOperand. Its opcode may be
1456/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1457/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1458class MemIntrinsicSDNode : public MemSDNode {
1459public:
MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
                   SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
    : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
  SDNodeBits.IsMemIntrinsic = true;
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  // We lower some target intrinsics to their target opcode
  // early a node with a target opcode can be of this class
  return N->isMemIntrinsic()             ||
         N->getOpcode() == ISD::PREFETCH ||
         N->isTargetMemoryOpcode();
}
1474};

1476/// This SDNode is used to implement the code generator
1477/// support for the llvm IR shufflevector instruction.  It combines elements
1478/// from two input vectors into a new input vector, with the selection and
1479/// ordering of elements determined by an array of integers, referred to as
1480/// the shuffle mask.  For input vectors of width N, mask indices of 0..N-1
1481/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1482/// An index of -1 is treated as undef, such that the code generator may put
1483/// any value in the corresponding element of the result.
1484class ShuffleVectorSDNode : public SDNode {
// The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
// is freed when the SelectionDAG object is destroyed.
const int *Mask;

1489protected:
friend class SelectionDAG;

ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
    : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}

1495public:
ArrayRef<int> getMask() const {
  EVT VT = getValueType(0);
  return makeArrayRef(Mask, VT.getVectorNumElements());
}

int getMaskElt(unsigned Idx) const {
  assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((void)0);
  return Mask[Idx];
}

bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }

int getSplatIndex() const {
  assert(isSplat() && "Cannot get splat index for non-splat!")((void)0);
  EVT VT = getValueType(0);
  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
    if (Mask[i] >= 0)
      return Mask[i];

  // We can choose any index value here and be correct because all elements
  // are undefined. Return 0 for better potential for callers to simplify.
  return 0;
}

static bool isSplatMask(const int *Mask, EVT VT);

/// Change values in a shuffle permute mask assuming
/// the two vector operands have swapped position.
static void commuteMask(MutableArrayRef<int> Mask) {
  unsigned NumElems = Mask.size();
  for (unsigned i = 0; i != NumElems; ++i) {
    int idx = Mask[i];
    if (idx < 0)
      continue;
    else if (idx < (int)NumElems)
      Mask[i] = idx + NumElems;
    else
      Mask[i] = idx - NumElems;
  }
}

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::VECTOR_SHUFFLE;
}
1540};

1542class ConstantSDNode : public SDNode {
friend class SelectionDAG;

const ConstantInt *Value;

ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
    : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
             getSDVTList(VT)),
      Value(val) {
  ConstantSDNodeBits.IsOpaque = isOpaque;
}

1554public:
const ConstantInt *getConstantIntValue() const { return Value; }
const APInt &getAPIntValue() const { return Value->getValue(); }
uint64_t getZExtValue() const { return Value->getZExtValue(); }
int64_t getSExtValue() const { return Value->getSExtValue(); }
uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX0xffffffffffffffffULL) {
  return Value->getLimitedValue(Limit);
}
MaybeAlign getMaybeAlignValue() const { return Value->getMaybeAlignValue(); }
Align getAlignValue() const { return Value->getAlignValue(); }

bool isOne() const { return Value->isOne(); }
bool isNullValue() const { return Value->isZero(); }
bool isAllOnesValue() const { return Value->isMinusOne(); }
bool isMaxSignedValue() const { return Value->isMaxValue(true); }
bool isMinSignedValue() const { return Value->isMinValue(true); }

bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::Constant ||
         N->getOpcode() == ISD::TargetConstant;
}
1577};

1579uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1581}

1583const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1585}

1587class ConstantFPSDNode : public SDNode {
friend class SelectionDAG;

const ConstantFP *Value;

ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
    : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
             DebugLoc(), getSDVTList(VT)),
      Value(val) {}

1597public:
const APFloat& getValueAPF() const { return Value->getValueAPF(); }
const ConstantFP *getConstantFPValue() const { return Value; }

/// Return true if the value is positive or negative zero.
bool isZero() const { return Value->isZero(); }

/// Return true if the value is a NaN.
bool isNaN() const { return Value->isNaN(); }

/// Return true if the value is an infinity
bool isInfinity() const { return Value->isInfinity(); }

/// Return true if the value is negative.
bool isNegative() const { return Value->isNegative(); }

/// We don't rely on operator== working on double values, as
/// it returns true for things that are clearly not equal, like -0.0 and 0.0.
/// As such, this method can be used to do an exact bit-for-bit comparison of
/// two floating point values.

/// We leave the version with the double argument here because it's just so
/// convenient to write "2.0" and the like.  Without this function we'd
/// have to duplicate its logic everywhere it's called.
bool isExactlyValue(double V) const {
  return Value->getValueAPF().isExactlyValue(V);
}
bool isExactlyValue(const APFloat& V) const;

static bool isValueValidForType(EVT VT, const APFloat& Val);

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ConstantFP ||
         N->getOpcode() == ISD::TargetConstantFP;
}
1632};

1634/// Returns true if \p V is a constant integer zero.
1635bool isNullConstant(SDValue V);

1637/// Returns true if \p V is an FP constant with a value of positive zero.
1638bool isNullFPConstant(SDValue V);

1640/// Returns true if \p V is an integer constant with all bits set.
1641bool isAllOnesConstant(SDValue V);

1643/// Returns true if \p V is a constant integer one.
1644bool isOneConstant(SDValue V);

1646/// Return the non-bitcasted source operand of \p V if it exists.
1647/// If \p V is not a bitcasted value, it is returned as-is.
1648SDValue peekThroughBitcasts(SDValue V);

1650/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1651/// If \p V is not a bitcasted one-use value, it is returned as-is.
1652SDValue peekThroughOneUseBitcasts(SDValue V);

1654/// Return the non-extracted vector source operand of \p V if it exists.
1655/// If \p V is not an extracted subvector, it is returned as-is.
1656SDValue peekThroughExtractSubvectors(SDValue V);

1658/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1659/// constant is canonicalized to be operand 1.
1660bool isBitwiseNot(SDValue V, bool AllowUndefs = false);

1662/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1663ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
                                  bool AllowTruncation = false);

1666/// Returns the SDNode if it is a demanded constant splat BuildVector or
1667/// constant int.
1668ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
                                  bool AllowUndefs = false,
                                  bool AllowTruncation = false);

1672/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1673ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);

1675/// Returns the SDNode if it is a demanded constant splat BuildVector or
1676/// constant float.
1677ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
                                      bool AllowUndefs = false);

1680/// Return true if the value is a constant 0 integer or a splatted vector of
1681/// a constant 0 integer (with no undefs by default).
1682/// Build vector implicit truncation is not an issue for null values.
1683bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);

1685/// Return true if the value is a constant 1 integer or a splatted vector of a
1686/// constant 1 integer (with no undefs).
1687/// Does not permit build vector implicit truncation.
1688bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false);

1690/// Return true if the value is a constant -1 integer or a splatted vector of a
1691/// constant -1 integer (with no undefs).
1692/// Does not permit build vector implicit truncation.
1693bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false);

1695/// Return true if \p V is either a integer or FP constant.
1696inline bool isIntOrFPConstant(SDValue V) {
return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V);
1698}

1700class GlobalAddressSDNode : public SDNode {
friend class SelectionDAG;

const GlobalValue *TheGlobal;
int64_t Offset;
unsigned TargetFlags;

GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
                    const GlobalValue *GA, EVT VT, int64_t o,
                    unsigned TF);

1711public:
const GlobalValue *getGlobal() const { return TheGlobal; }
int64_t getOffset() const { return Offset; }
unsigned getTargetFlags() const { return TargetFlags; }
// Return the address space this GlobalAddress belongs to.
unsigned getAddressSpace() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::GlobalAddress ||
         N->getOpcode() == ISD::TargetGlobalAddress ||
         N->getOpcode() == ISD::GlobalTLSAddress ||
         N->getOpcode() == ISD::TargetGlobalTLSAddress;
}
1724};

1726class FrameIndexSDNode : public SDNode {
friend class SelectionDAG;

int FI;

FrameIndexSDNode(int fi, EVT VT, bool isTarg)
  : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
    0, DebugLoc(), getSDVTList(VT)), FI(fi) {
}

1736public:
int getIndex() const { return FI; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::FrameIndex ||
         N->getOpcode() == ISD::TargetFrameIndex;
}
1743};

1745/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1746/// the offet and size that are started/ended in the underlying FrameIndex.
1747class LifetimeSDNode : public SDNode {
friend class SelectionDAG;
int64_t Size;
int64_t Offset; // -1 if offset is unknown.

LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
               SDVTList VTs, int64_t Size, int64_t Offset)
    : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1755public:
int64_t getFrameIndex() const {
  return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
}

bool hasOffset() const { return Offset >= 0; }
int64_t getOffset() const {
  assert(hasOffset() && "offset is unknown")((void)0);
  return Offset;
}
int64_t getSize() const {
  assert(hasOffset() && "offset is unknown")((void)0);
  return Size;
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LIFETIME_START ||
         N->getOpcode() == ISD::LIFETIME_END;
}
1775};

1777/// This SDNode is used for PSEUDO_PROBE values, which are the function guid and
1778/// the index of the basic block being probed. A pseudo probe serves as a place
1779/// holder and will be removed at the end of compilation. It does not have any
1780/// operand because we do not want the instruction selection to deal with any.
1781class PseudoProbeSDNode : public SDNode {
friend class SelectionDAG;
uint64_t Guid;
uint64_t Index;
uint32_t Attributes;

PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl,
                  SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr)
    : SDNode(Opcode, Order, Dl, VTs), Guid(Guid), Index(Index),
      Attributes(Attr) {}

1792public:
uint64_t getGuid() const { return Guid; }
uint64_t getIndex() const { return Index; }
uint32_t getAttributes() const { return Attributes; }

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::PSEUDO_PROBE;
}
1801};

1803class JumpTableSDNode : public SDNode {
friend class SelectionDAG;

int JTI;
unsigned TargetFlags;

JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
  : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
    0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
}

1814public:
int getIndex() const { return JTI; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::JumpTable ||
         N->getOpcode() == ISD::TargetJumpTable;
}
1822};

1824class ConstantPoolSDNode : public SDNode {
friend class SelectionDAG;

union {
  const Constant *ConstVal;
  MachineConstantPoolValue *MachineCPVal;
} Val;
int Offset;  // It's a MachineConstantPoolValue if top bit is set.
Align Alignment; // Minimum alignment requirement of CP.
unsigned TargetFlags;

ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
                   Align Alignment, unsigned TF)
    : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
             DebugLoc(), getSDVTList(VT)),
      Offset(o), Alignment(Alignment), TargetFlags(TF) {
  assert(Offset >= 0 && "Offset is too large")((void)0);
  Val.ConstVal = c;
}

ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o,
                   Align Alignment, unsigned TF)
    : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
             DebugLoc(), getSDVTList(VT)),
      Offset(o), Alignment(Alignment), TargetFlags(TF) {
  assert(Offset >= 0 && "Offset is too large")((void)0);
  Val.MachineCPVal = v;
  Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
}

1854public:
bool isMachineConstantPoolEntry() const {
  return Offset < 0;
}

const Constant *getConstVal() const {
  assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((void)0);
  return Val.ConstVal;
}

MachineConstantPoolValue *getMachineCPVal() const {
  assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((void)0);
  return Val.MachineCPVal;
}

int getOffset() const {
  return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
}

// Return the alignment of this constant pool object, which is either 0 (for
// default alignment) or the desired value.
Align getAlign() const { return Alignment; }
unsigned getTargetFlags() const { return TargetFlags; }

Type *getType() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ConstantPool ||
         N->getOpcode() == ISD::TargetConstantPool;
}
1884};

1886/// Completely target-dependent object reference.
1887class TargetIndexSDNode : public SDNode {
friend class SelectionDAG;

unsigned TargetFlags;
int Index;
int64_t Offset;

1894public:
TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
    : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
      TargetFlags(TF), Index(Idx), Offset(Ofs) {}

unsigned getTargetFlags() const { return TargetFlags; }
int getIndex() const { return Index; }
int64_t getOffset() const { return Offset; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::TargetIndex;
}
1906};

1908class BasicBlockSDNode : public SDNode {
friend class SelectionDAG;

MachineBasicBlock *MBB;

/// Debug info is meaningful and potentially useful here, but we create
/// blocks out of order when they're jumped to, which makes it a bit
/// harder.  Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
  : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
{}

1920public:
MachineBasicBlock *getBasicBlock() const { return MBB; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BasicBlock;
}
1926};

1928/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1929class BuildVectorSDNode : public SDNode {
1930public:
// These are constructed as SDNodes and then cast to BuildVectorSDNodes.
explicit BuildVectorSDNode() = delete;

/// Check if this is a constant splat, and if so, find the
/// smallest element size that splats the vector.  If MinSplatBits is
/// nonzero, the element size must be at least that large.  Note that the
/// splat element may be the entire vector (i.e., a one element vector).
/// Returns the splat element value in SplatValue.  Any undefined bits in
/// that value are zero, and the corresponding bits in the SplatUndef mask
/// are set.  The SplatBitSize value is set to the splat element size in
/// bits.  HasAnyUndefs is set to true if any bits in the vector are
/// undefined.  isBigEndian describes the endianness of the target.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
                     unsigned &SplatBitSize, bool &HasAnyUndefs,
                     unsigned MinSplatBits = 0,
                     bool isBigEndian = false) const;

/// Returns the demanded splatted value or a null value if this is not a
/// splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
SDValue getSplatValue(const APInt &DemandedElts,
                      BitVector *UndefElements = nullptr) const;

/// Returns the splatted value or a null value if this is not a splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
SDValue getSplatValue(BitVector *UndefElements = nullptr) const;

/// Find the shortest repeating sequence of values in the build vector.
///
/// e.g. { u, X, u, X, u, u, X, u } -> { X }
///      { X, Y, u, Y, u, u, X, u } -> { X, Y }
///
/// Currently this must be a power-of-2 build vector.
/// The DemandedElts mask indicates the elements that must be present,
/// undemanded elements in Sequence may be null (SDValue()). If passed a
/// non-null UndefElements bitvector, it will resize it to match the original
/// vector width and set the bits where elements are undef. If result is
/// false, Sequence will be empty.
bool getRepeatedSequence(const APInt &DemandedElts,
                         SmallVectorImpl<SDValue> &Sequence,
                         BitVector *UndefElements = nullptr) const;

/// Find the shortest repeating sequence of values in the build vector.
///
/// e.g. { u, X, u, X, u, u, X, u } -> { X }
///      { X, Y, u, Y, u, u, X, u } -> { X, Y }
///
/// Currently this must be a power-of-2 build vector.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the original vector width and set the bits where elements are undef.
/// If result is false, Sequence will be empty.
bool getRepeatedSequence(SmallVectorImpl<SDValue> &Sequence,
                         BitVector *UndefElements = nullptr) const;

/// Returns the demanded splatted constant or null if this is not a constant
/// splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantSDNode *
getConstantSplatNode(const APInt &DemandedElts,
                     BitVector *UndefElements = nullptr) const;

/// Returns the splatted constant or null if this is not a constant
/// splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantSDNode *
getConstantSplatNode(BitVector *UndefElements = nullptr) const;

/// Returns the demanded splatted constant FP or null if this is not a
/// constant FP splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantFPSDNode *
getConstantFPSplatNode(const APInt &DemandedElts,
                       BitVector *UndefElements = nullptr) const;

/// Returns the splatted constant FP or null if this is not a constant
/// FP splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantFPSDNode *
getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;

/// If this is a constant FP splat and the splatted constant FP is an
/// exact power or 2, return the log base 2 integer value.  Otherwise,
/// return -1.
///
/// The BitWidth specifies the necessary bit precision.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
                                        uint32_t BitWidth) const;

bool isConstant() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BUILD_VECTOR;
}
2039};

2041/// An SDNode that holds an arbitrary LLVM IR Value. This is
2042/// used when the SelectionDAG needs to make a simple reference to something
2043/// in the LLVM IR representation.
2044///
2045class SrcValueSDNode : public SDNode {
friend class SelectionDAG;

const Value *V;

/// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v)
  : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}

2054public:
/// Return the contained Value.
const Value *getValue() const { return V; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::SRCVALUE;
}
2061};

2063class MDNodeSDNode : public SDNode {
friend class SelectionDAG;

const MDNode *MD;

explicit MDNodeSDNode(const MDNode *md)
: SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
{}

2072public:
const MDNode *getMD() const { return MD; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MDNODE_SDNODE;
}
2078};

2080class RegisterSDNode : public SDNode {
friend class SelectionDAG;

Register Reg;

RegisterSDNode(Register reg, EVT VT)
  : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}

2088public:
Register getReg() const { return Reg; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::Register;
}
2094};

2096class RegisterMaskSDNode : public SDNode {
friend class SelectionDAG;

// The memory for RegMask is not owned by the node.
const uint32_t *RegMask;

RegisterMaskSDNode(const uint32_t *mask)
  : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
    RegMask(mask) {}

2106public:
const uint32_t *getRegMask() const { return RegMask; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::RegisterMask;
}
2112};

2114class BlockAddressSDNode : public SDNode {
friend class SelectionDAG;

const BlockAddress *BA;
int64_t Offset;
unsigned TargetFlags;

BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
                   int64_t o, unsigned Flags)
  : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
           BA(ba), Offset(o), TargetFlags(Flags) {}

2126public:
const BlockAddress *getBlockAddress() const { return BA; }
int64_t getOffset() const { return Offset; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BlockAddress ||
         N->getOpcode() == ISD::TargetBlockAddress;
}
2135};

2137class LabelSDNode : public SDNode {
friend class SelectionDAG;

MCSymbol *Label;

LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
    : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
  assert(LabelSDNode::classof(this) && "not a label opcode")((void)0);
}

2147public:
MCSymbol *getLabel() const { return Label; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::EH_LABEL ||
         N->getOpcode() == ISD::ANNOTATION_LABEL;
}
2154};

2156class ExternalSymbolSDNode : public SDNode {
friend class SelectionDAG;

const char *Symbol;
unsigned TargetFlags;

ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
    : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
             DebugLoc(), getSDVTList(VT)),
      Symbol(Sym), TargetFlags(TF) {}

2167public:
const char *getSymbol() const { return Symbol; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ExternalSymbol ||
         N->getOpcode() == ISD::TargetExternalSymbol;
}
2175};

2177class MCSymbolSDNode : public SDNode {
friend class SelectionDAG;

MCSymbol *Symbol;

MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
    : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}

2185public:
MCSymbol *getMCSymbol() const { return Symbol; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MCSymbol;
}
2191};

2193class CondCodeSDNode : public SDNode {
friend class SelectionDAG;

ISD::CondCode Condition;

explicit CondCodeSDNode(ISD::CondCode Cond)
  : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
    Condition(Cond) {}

2202public:
ISD::CondCode get() const { return Condition; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::CONDCODE;
}
2208};

2210/// This class is used to represent EVT's, which are used
2211/// to parameterize some operations.
2212class VTSDNode : public SDNode {
friend class SelectionDAG;

EVT ValueType;

explicit VTSDNode(EVT VT)
  : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
    ValueType(VT) {}

2221public:
EVT getVT() const { return ValueType; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::VALUETYPE;
}
2227};

2229/// Base class for LoadSDNode and StoreSDNode
2230class LSBaseSDNode : public MemSDNode {
2231public:
LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
             SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
             MachineMemOperand *MMO)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = AM;
  assert(getAddressingMode() == AM && "Value truncated")((void)0);
}

const SDValue &getOffset() const {
  return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
}

/// Return the addressing mode for this load or store:
/// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
ISD::MemIndexedMode getAddressingMode() const {
  return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
}

/// Return true if this is a pre/post inc/dec load/store.
bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }

/// Return true if this is NOT a pre/post inc/dec load/store.
bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LOAD ||
         N->getOpcode() == ISD::STORE;
}
2260};

2262/// This class is used to represent ISD::LOAD nodes.
2263class LoadSDNode : public LSBaseSDNode {
friend class SelectionDAG;

LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
           ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
           MachineMemOperand *MMO)
    : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
  LoadSDNodeBits.ExtTy = ETy;
  assert(readMem() && "Load MachineMemOperand is not a load!")((void)0);
  assert(!writeMem() && "Load MachineMemOperand is a store!")((void)0);
}

2275public:
/// Return whether this is a plain node,
/// or one of the varieties of value-extending loads.
ISD::LoadExtType getExtensionType() const {
  return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getOffset() const { return getOperand(2); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LOAD;
}
2288};

2290/// This class is used to represent ISD::STORE nodes.
2291class StoreSDNode : public LSBaseSDNode {
friend class SelectionDAG;

StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
            ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
            MachineMemOperand *MMO)
    : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
  StoreSDNodeBits.IsTruncating = isTrunc;
  assert(!readMem() && "Store MachineMemOperand is a load!")((void)0);
  assert(writeMem() && "Store MachineMemOperand is not a store!")((void)0);
}

2303public:
/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
void setTruncatingStore(bool Truncating) {
  StoreSDNodeBits.IsTruncating = Truncating;
}

const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); }
const SDValue &getOffset() const { return getOperand(3); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::STORE;
}
2319};

2321/// This base class is used to represent MLOAD and MSTORE nodes
2322class MaskedLoadStoreSDNode : public MemSDNode {
2323public:
friend class SelectionDAG;

MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
                      const DebugLoc &dl, SDVTList VTs,
                      ISD::MemIndexedMode AM, EVT MemVT,
                      MachineMemOperand *MMO)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = AM;
  assert(getAddressingMode() == AM && "Value truncated")((void)0);
}

// MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
// MaskedStoreSDNode (Chain, data, ptr, offset, mask)
// Mask is a vector of i1 elements
const SDValue &getOffset() const {
  return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
}
const SDValue &getMask() const {
  return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
}

/// Return the addressing mode for this load or store:
/// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
ISD::MemIndexedMode getAddressingMode() const {
  return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
}

/// Return true if this is a pre/post inc/dec load/store.
bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }

/// Return true if this is NOT a pre/post inc/dec load/store.
bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MLOAD ||
         N->getOpcode() == ISD::MSTORE;
}
2361};

2363/// This class is used to represent an MLOAD node
2364class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2365public:
friend class SelectionDAG;

MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
                 bool IsExpanding, EVT MemVT, MachineMemOperand *MMO)
    : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
  LoadSDNodeBits.ExtTy = ETy;
  LoadSDNodeBits.IsExpanding = IsExpanding;
}

ISD::LoadExtType getExtensionType() const {
  return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getOffset() const { return getOperand(2); }
const SDValue &getMask() const { return getOperand(3); }
const SDValue &getPassThru() const { return getOperand(4); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MLOAD;
}

bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2390};

2392/// This class is used to represent an MSTORE node
2393class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2394public:
friend class SelectionDAG;

MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                  ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
                  EVT MemVT, MachineMemOperand *MMO)
    : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
  StoreSDNodeBits.IsTruncating = isTrunc;
  StoreSDNodeBits.IsCompressing = isCompressing;
}

/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }

/// Returns true if the op does a compression to the vector before storing.
/// The node contiguously stores the active elements (integers or floats)
/// in src (those with their respective bit set in writemask k) to unaligned
/// memory at base_addr.
bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }

const SDValue &getValue() const { return getOperand(1); }
const SDValue &getBasePtr() const { return getOperand(2); }
const SDValue &getOffset() const { return getOperand(3); }
const SDValue &getMask() const { return getOperand(4); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MSTORE;
}
2424};

2426/// This is a base class used to represent
2427/// MGATHER and MSCATTER nodes
2428///
2429class MaskedGatherScatterSDNode : public MemSDNode {
2430public:
friend class SelectionDAG;

MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
                          const DebugLoc &dl, SDVTList VTs, EVT MemVT,
                          MachineMemOperand *MMO, ISD::MemIndexType IndexType)
    : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
  LSBaseSDNodeBits.AddressingMode = IndexType;
  assert(getIndexType() == IndexType && "Value truncated")((void)0);
}

/// How is Index applied to BasePtr when computing addresses.
ISD::MemIndexType getIndexType() const {
  return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
}
void setIndexType(ISD::MemIndexType IndexType) {
  LSBaseSDNodeBits.AddressingMode = IndexType;
}
bool isIndexScaled() const {
  return (getIndexType() == ISD::SIGNED_SCALED) ||
         (getIndexType() == ISD::UNSIGNED_SCALED);
}
bool isIndexSigned() const {
  return (getIndexType() == ISD::SIGNED_SCALED) ||
         (getIndexType() == ISD::SIGNED_UNSCALED);
}

// In the both nodes address is Op1, mask is Op2:
// MaskedGatherSDNode  (Chain, passthru, mask, base, index, scale)
// MaskedScatterSDNode (Chain, value, mask, base, index, scale)
// Mask is a vector of i1 elements
const SDValue &getBasePtr() const { return getOperand(3); }
const SDValue &getIndex()   const { return getOperand(4); }
const SDValue &getMask()    const { return getOperand(2); }
const SDValue &getScale()   const { return getOperand(5); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MGATHER ||
         N->getOpcode() == ISD::MSCATTER;
}
2470};

2472/// This class is used to represent an MGATHER node
2473///
2474class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2475public:
friend class SelectionDAG;

MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                   EVT MemVT, MachineMemOperand *MMO,
                   ISD::MemIndexType IndexType, ISD::LoadExtType ETy)
    : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
                                IndexType) {
  LoadSDNodeBits.ExtTy = ETy;
}

const SDValue &getPassThru() const { return getOperand(1); }

ISD::LoadExtType getExtensionType() const {
  return ISD::LoadExtType(LoadSDNodeBits.ExtTy);
}

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MGATHER;
}
2495};

2497/// This class is used to represent an MSCATTER node
2498///
2499class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2500public:
friend class SelectionDAG;

MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
                    EVT MemVT, MachineMemOperand *MMO,
                    ISD::MemIndexType IndexType, bool IsTrunc)
    : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
                                IndexType) {
  StoreSDNodeBits.IsTruncating = IsTrunc;
}

/// Return true if the op does a truncation before store.
/// For integers this is the same as doing a TRUNCATE and storing the result.
/// For floats, it is the same as doing an FP_ROUND and storing the result.
bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }

const SDValue &getValue() const { return getOperand(1); }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MSCATTER;
}
2521};

2523/// An SDNode that represents everything that will be needed
2524/// to construct a MachineInstr. These nodes are created during the
2525/// instruction selection proper phase.
2526///
2527/// Note that the only supported way to set the `memoperands` is by calling the
2528/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2529/// inside the DAG rather than in the node.
2530class MachineSDNode : public SDNode {
2531private:
friend class SelectionDAG;

MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
    : SDNode(Opc, Order, DL, VTs) {}

// We use a pointer union between a single `MachineMemOperand` pointer and
// a pointer to an array of `MachineMemOperand` pointers. This is null when
// the number of these is zero, the single pointer variant used when the
// number is one, and the array is used for larger numbers.
//
// The array is allocated via the `SelectionDAG`'s allocator and so will
// always live until the DAG is cleaned up and doesn't require ownership here.
//
// We can't use something simpler like `TinyPtrVector` here because `SDNode`
// subclasses aren't managed in a conforming C++ manner. See the comments on
// `SelectionDAG::MorphNodeTo` which details what all goes on, but the
// constraint here is that these don't manage memory with their constructor or
// destructor and can be initialized to a good state even if they start off
// uninitialized.
PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};

// Note that this could be folded into the above `MemRefs` member if doing so
// is advantageous at some point. We don't need to store this in most cases.
// However, at the moment this doesn't appear to make the allocation any
// smaller and makes the code somewhat simpler to read.
int NumMemRefs = 0;

2559public:
using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;

ArrayRef<MachineMemOperand *> memoperands() const {
  // Special case the common cases.
  if (NumMemRefs == 0)
    return {};
  if (NumMemRefs == 1)
    return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);

  // Otherwise we have an actual array.
  return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
}
mmo_iterator memoperands_begin() const { return memoperands().begin(); }
mmo_iterator memoperands_end() const { return memoperands().end(); }
bool memoperands_empty() const { return memoperands().empty(); }

/// Clear out the memory reference descriptor list.
void clearMemRefs() {
  MemRefs = nullptr;
  NumMemRefs = 0;
}

static bool classof(const SDNode *N) {
  return N->isMachineOpcode();
}
2585};

2587/// An SDNode that records if a register contains a value that is guaranteed to
2588/// be aligned accordingly.
2589class AssertAlignSDNode : public SDNode {
Align Alignment;

2592public:
AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A)
    : SDNode(ISD::AssertAlign, Order, DL, getSDVTList(VT)), Alignment(A) {}

Align getAlign() const { return Alignment; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::AssertAlign;
}
2601};

2603class SDNodeIterator {
const SDNode *Node;
unsigned Operand;

SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}

2609public:
using iterator_category = std::forward_iterator_tag;
using value_type = SDNode;
using difference_type = std::ptrdiff_t;
using pointer = value_type *;
using reference = value_type &;

bool operator==(const SDNodeIterator& x) const {
  return Operand == x.Operand;
}
bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }

pointer operator*() const {
  return Node->getOperand(Operand).getNode();
}
pointer operator->() const { return operator*(); }

SDNodeIterator& operator++() {                // Preincrement
  ++Operand;
  return *this;
}
SDNodeIterator operator++(int) { // Postincrement
  SDNodeIterator tmp = *this; ++*this; return tmp;
}
size_t operator-(SDNodeIterator Other) const {
  assert(Node == Other.Node &&((void)0)
         "Cannot compare iterators of two different nodes!")((void)0);
  return Operand - Other.Operand;
}

static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
static SDNodeIterator end  (const SDNode *N) {
  return SDNodeIterator(N, N->getNumOperands());
}

unsigned getOperand() const { return Operand; }
const SDNode *getNode() const { return Node; }
2646};

2648template <> struct GraphTraits<SDNode*> {
using NodeRef = SDNode *;
using ChildIteratorType = SDNodeIterator;

static NodeRef getEntryNode(SDNode *N) { return N; }

static ChildIteratorType child_begin(NodeRef N) {
  return SDNodeIterator::begin(N);
}

static ChildIteratorType child_end(NodeRef N) {
  return SDNodeIterator::end(N);
}
2661};

2663/// A representation of the largest SDNode, for use in sizeof().
2664///
2665/// This needs to be a union because the largest node differs on 32 bit systems
2666/// with 4 and 8 byte pointer alignment, respectively.
2667using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
                                          BlockAddressSDNode,
                                          GlobalAddressSDNode,
                                          PseudoProbeSDNode>;

2672/// The SDNode class with the greatest alignment requirement.
2673using MostAlignedSDNode = GlobalAddressSDNode;

2675namespace ISD {

/// Returns true if the specified node is a non-extending and unindexed load.
inline bool isNormalLoad(const SDNode *N) {
  const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
  return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
    Ld->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is a non-extending load.
inline bool isNON_EXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
}

/// Returns true if the specified node is a EXTLOAD.
inline bool isEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
}

/// Returns true if the specified node is a SEXTLOAD.
inline bool isSEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
}

/// Returns true if the specified node is a ZEXTLOAD.
inline bool isZEXTLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
}

/// Returns true if the specified node is an unindexed load.
inline bool isUNINDEXEDLoad(const SDNode *N) {
  return isa<LoadSDNode>(N) &&
    cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is a non-truncating
/// and unindexed store.
inline bool isNormalStore(const SDNode *N) {
  const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
  return St && !St->isTruncatingStore() &&
    St->getAddressingMode() == ISD::UNINDEXED;
}

/// Returns true if the specified node is an unindexed store.
inline bool isUNINDEXEDStore(const SDNode *N) {
  return isa<StoreSDNode>(N) &&
    cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}

/// Attempt to match a unary predicate against a scalar/splat constant or
/// every element of a constant BUILD_VECTOR.
/// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
bool matchUnaryPredicate(SDValue Op,
                         std::function<bool(ConstantSDNode *)> Match,
                         bool AllowUndefs = false);

/// Attempt to match a binary predicate against a pair of scalar/splat
/// constants or every element of a pair of constant BUILD_VECTORs.
/// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
/// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match.
bool matchBinaryPredicate(
    SDValue LHS, SDValue RHS,
    std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
    bool AllowUndefs = false, bool AllowTypeMismatch = false);

/// Returns true if the specified value is the overflow result from one
/// of the overflow intrinsic nodes.
inline bool isOverflowIntrOpRes(SDValue Op) {
  unsigned Opc = Op.getOpcode();
  return (Op.getResNo() == 1 &&
          (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
           Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
}

2753} // end namespace ISD

2755} // end namespace llvm

2757#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H