clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name CodeGenRegisters.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/gnu/usr.bin/clang/llvm-tblgen/obj -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/gnu/usr.bin/clang/llvm-tblgen/../../../llvm/llvm/include -I /usr/src/gnu/usr.bin/clang/llvm-tblgen/../include -I /usr/src/gnu/usr.bin/clang/llvm-tblgen/obj -I /usr/src/gnu/usr.bin/clang/llvm-tblgen/obj/../include -D NDEBUG -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D LLVM_PREFIX="/usr" -internal-isystem /usr/include/c++/v1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/usr/src/gnu/usr.bin/clang/llvm-tblgen/obj -ferror-limit 19 -fvisibility-inlines-hidden -fwrapv -stack-protector 2 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c++ /usr/src/gnu/usr.bin/clang/llvm-tblgen/../../../llvm/llvm/utils/TableGen/CodeGenRegisters.cpp
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13 | |
14 | #include "CodeGenRegisters.h" |
15 | #include "CodeGenTarget.h" |
16 | #include "llvm/ADT/ArrayRef.h" |
17 | #include "llvm/ADT/BitVector.h" |
18 | #include "llvm/ADT/DenseMap.h" |
19 | #include "llvm/ADT/IntEqClasses.h" |
20 | #include "llvm/ADT/SetVector.h" |
21 | #include "llvm/ADT/SmallPtrSet.h" |
22 | #include "llvm/ADT/SmallSet.h" |
23 | #include "llvm/ADT/SmallVector.h" |
24 | #include "llvm/ADT/STLExtras.h" |
25 | #include "llvm/ADT/StringExtras.h" |
26 | #include "llvm/ADT/StringRef.h" |
27 | #include "llvm/ADT/Twine.h" |
28 | #include "llvm/Support/Debug.h" |
29 | #include "llvm/Support/MathExtras.h" |
30 | #include "llvm/Support/raw_ostream.h" |
31 | #include "llvm/TableGen/Error.h" |
32 | #include "llvm/TableGen/Record.h" |
33 | #include <algorithm> |
34 | #include <cassert> |
35 | #include <cstdint> |
36 | #include <iterator> |
37 | #include <map> |
38 | #include <queue> |
39 | #include <set> |
40 | #include <string> |
41 | #include <tuple> |
42 | #include <utility> |
43 | #include <vector> |
44 | |
45 | using namespace llvm; |
46 | |
47 | #define DEBUG_TYPE "regalloc-emitter" |
48 | |
49 | |
50 | |
51 | |
52 | |
53 | CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum) |
54 | : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) { |
55 | Name = std::string(R->getName()); |
56 | if (R->getValue("Namespace")) |
57 | Namespace = std::string(R->getValueAsString("Namespace")); |
58 | Size = R->getValueAsInt("Size"); |
59 | Offset = R->getValueAsInt("Offset"); |
60 | } |
61 | |
62 | CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace, |
63 | unsigned Enum) |
64 | : TheDef(nullptr), Name(std::string(N)), Namespace(std::string(Nspace)), |
65 | Size(-1), Offset(-1), EnumValue(Enum), AllSuperRegsCovered(true), |
66 | Artificial(true) {} |
67 | |
68 | std::string CodeGenSubRegIndex::getQualifiedName() const { |
69 | std::string N = getNamespace(); |
70 | if (!N.empty()) |
71 | N += "::"; |
72 | N += getName(); |
73 | return N; |
74 | } |
75 | |
76 | void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { |
77 | if (!TheDef) |
78 | return; |
79 | |
80 | std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); |
81 | if (!Comps.empty()) { |
82 | if (Comps.size() != 2) |
83 | PrintFatalError(TheDef->getLoc(), |
84 | "ComposedOf must have exactly two entries"); |
85 | CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); |
86 | CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); |
87 | CodeGenSubRegIndex *X = A->addComposite(B, this); |
88 | if (X) |
89 | PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries"); |
90 | } |
91 | |
92 | std::vector<Record*> Parts = |
93 | TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); |
94 | if (!Parts.empty()) { |
95 | if (Parts.size() < 2) |
96 | PrintFatalError(TheDef->getLoc(), |
97 | "CoveredBySubRegs must have two or more entries"); |
98 | SmallVector<CodeGenSubRegIndex*, 8> IdxParts; |
99 | for (Record *Part : Parts) |
100 | IdxParts.push_back(RegBank.getSubRegIdx(Part)); |
101 | setConcatenationOf(IdxParts); |
102 | } |
103 | } |
104 | |
105 | LaneBitmask CodeGenSubRegIndex::computeLaneMask() const { |
106 | |
107 | if (LaneMask.any()) |
108 | return LaneMask; |
109 | |
110 | |
111 | LaneMask = LaneBitmask::getAll(); |
112 | |
113 | |
114 | LaneBitmask M; |
115 | for (const auto &C : Composed) |
116 | M |= C.second->computeLaneMask(); |
117 | assert(M.any() && "Missing lane mask, sub-register cycle?"); |
118 | LaneMask = M; |
119 | return LaneMask; |
120 | } |
121 | |
122 | void CodeGenSubRegIndex::setConcatenationOf( |
123 | ArrayRef<CodeGenSubRegIndex*> Parts) { |
124 | if (ConcatenationOf.empty()) |
125 | ConcatenationOf.assign(Parts.begin(), Parts.end()); |
126 | else |
127 | assert(std::equal(Parts.begin(), Parts.end(), |
128 | ConcatenationOf.begin()) && "parts consistent"); |
129 | } |
130 | |
131 | void CodeGenSubRegIndex::computeConcatTransitiveClosure() { |
132 | for (SmallVectorImpl<CodeGenSubRegIndex*>::iterator |
133 | I = ConcatenationOf.begin(); I != ConcatenationOf.end(); ) { |
134 | CodeGenSubRegIndex *SubIdx = *I; |
135 | SubIdx->computeConcatTransitiveClosure(); |
136 | #ifndef NDEBUG |
137 | for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) |
138 | assert(SRI->ConcatenationOf.empty() && "No transitive closure?"); |
139 | #endif |
140 | |
141 | if (SubIdx->ConcatenationOf.empty()) { |
142 | ++I; |
143 | } else { |
144 | I = ConcatenationOf.erase(I); |
145 | I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(), |
146 | SubIdx->ConcatenationOf.end()); |
147 | I += SubIdx->ConcatenationOf.size(); |
148 | } |
149 | } |
150 | } |
151 | |
152 | |
153 | |
154 | |
155 | |
156 | CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum) |
157 | : TheDef(R), EnumValue(Enum), |
158 | CostPerUse(R->getValueAsListOfInts("CostPerUse")), |
159 | CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")), |
160 | HasDisjunctSubRegs(false), SubRegsComplete(false), |
161 | SuperRegsComplete(false), TopoSig(~0u) { |
162 | Artificial = R->getValueAsBit("isArtificial"); |
163 | } |
164 | |
165 | void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { |
166 | std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices"); |
167 | std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs"); |
168 | |
169 | if (SRIs.size() != SRs.size()) |
170 | PrintFatalError(TheDef->getLoc(), |
171 | "SubRegs and SubRegIndices must have the same size"); |
172 | |
173 | for (unsigned i = 0, e = SRIs.size(); i != e; ++i) { |
174 | ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); |
175 | ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); |
176 | } |
177 | |
178 | |
179 | |
180 | |
181 | |
182 | |
183 | if (CoveredBySubRegs && !ExplicitSubRegs.empty()) |
184 | ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this); |
185 | |
186 | |
187 | |
188 | std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases"); |
189 | for (Record *Alias : Aliases) { |
190 | CodeGenRegister *Reg = RegBank.getReg(Alias); |
191 | ExplicitAliases.push_back(Reg); |
192 | Reg->ExplicitAliases.push_back(this); |
193 | } |
194 | } |
195 | |
196 | StringRef CodeGenRegister::getName() const { |
197 | assert(TheDef && "no def"); |
198 | return TheDef->getName(); |
| 20 | | Called C++ object pointer is null |
|
199 | } |
200 | |
201 | namespace { |
202 | |
203 | |
204 | class RegUnitIterator { |
205 | CodeGenRegister::Vec::const_iterator RegI, RegE; |
206 | CodeGenRegister::RegUnitList::iterator UnitI, UnitE; |
207 | |
208 | public: |
209 | RegUnitIterator(const CodeGenRegister::Vec &Regs): |
210 | RegI(Regs.begin()), RegE(Regs.end()) { |
211 | |
212 | if (RegI != RegE) { |
213 | UnitI = (*RegI)->getRegUnits().begin(); |
214 | UnitE = (*RegI)->getRegUnits().end(); |
215 | advance(); |
216 | } |
217 | } |
218 | |
219 | bool isValid() const { return UnitI != UnitE; } |
220 | |
221 | unsigned operator* () const { assert(isValid()); return *UnitI; } |
222 | |
223 | const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; } |
224 | |
225 | |
226 | void operator++() { |
227 | assert(isValid() && "Cannot advance beyond the last operand"); |
228 | ++UnitI; |
229 | advance(); |
230 | } |
231 | |
232 | protected: |
233 | void advance() { |
234 | while (UnitI == UnitE) { |
235 | if (++RegI == RegE) |
236 | break; |
237 | UnitI = (*RegI)->getRegUnits().begin(); |
238 | UnitE = (*RegI)->getRegUnits().end(); |
239 | } |
240 | } |
241 | }; |
242 | |
243 | } |
244 | |
245 | |
246 | static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) { |
247 | return RegUnits.test(Unit); |
248 | } |
249 | |
250 | |
251 | |
252 | bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { |
253 | bool changed = false; |
254 | for (const auto &SubReg : SubRegs) { |
255 | CodeGenRegister *SR = SubReg.second; |
256 | |
257 | changed |= (RegUnits |= SR->RegUnits); |
258 | } |
259 | |
260 | return changed; |
261 | } |
262 | |
263 | const CodeGenRegister::SubRegMap & |
264 | CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { |
265 | |
266 | if (SubRegsComplete) |
| 6 | | Assuming field 'SubRegsComplete' is false | |
|
| |
267 | return SubRegs; |
268 | SubRegsComplete = true; |
269 | |
270 | HasDisjunctSubRegs = ExplicitSubRegs.size() > 1; |
| 8 | | Assuming the condition is false | |
|
271 | |
272 | |
273 | for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { |
| 9 | | Assuming 'i' is equal to 'e' | |
|
| 10 | | Loop condition is false. Execution continues on line 287 | |
|
274 | CodeGenRegister *SR = ExplicitSubRegs[i]; |
275 | CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i]; |
276 | if (!SR->Artificial) |
277 | Idx->Artificial = false; |
278 | if (!SubRegs.insert(std::make_pair(Idx, SR)).second) |
279 | PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() + |
280 | " appears twice in Register " + getName()); |
281 | |
282 | |
283 | SubReg2Idx.insert(std::make_pair(SR, Idx)); |
284 | } |
285 | |
286 | |
287 | SmallPtrSet<CodeGenRegister*, 8> Orphans; |
288 | |
289 | |
290 | |
291 | for (CodeGenRegister *ESR : ExplicitSubRegs) { |
| 11 | | Assuming '__begin1' is equal to '__end1' | |
|
292 | const SubRegMap &Map = ESR->computeSubRegs(RegBank); |
293 | HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs; |
294 | |
295 | for (const auto &SR : Map) { |
296 | if (!SubRegs.insert(SR).second) |
297 | Orphans.insert(SR.second); |
298 | } |
299 | } |
300 | |
301 | |
302 | |
303 | |
304 | |
305 | SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices; |
306 | for (unsigned i = 0; i != Indices.size(); ++i) { |
| 12 | | Assuming the condition is false | |
|
| 13 | | Loop condition is false. Execution continues on line 344 | |
|
307 | CodeGenSubRegIndex *Idx = Indices[i]; |
308 | const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites(); |
309 | CodeGenRegister *SR = SubRegs[Idx]; |
310 | const SubRegMap &Map = SR->computeSubRegs(RegBank); |
311 | |
312 | |
313 | |
314 | for (auto Comp : Comps) { |
315 | SubRegMap::const_iterator SRI = Map.find(Comp.first); |
316 | if (SRI == Map.end()) |
317 | continue; |
318 | |
319 | |
320 | if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second)) |
321 | continue; |
322 | |
323 | SubRegs.insert(std::make_pair(Comp.second, SRI->second)); |
324 | Indices.push_back(Comp.second); |
325 | } |
326 | } |
327 | |
328 | |
329 | |
330 | |
331 | |
332 | |
333 | |
334 | |
335 | |
336 | |
337 | |
338 | |
339 | |
340 | |
341 | |
342 | |
343 | |
344 | while (!Indices.empty() && !Orphans.empty()) { |
345 | CodeGenSubRegIndex *Idx = Indices.pop_back_val(); |
346 | CodeGenRegister *SR = SubRegs[Idx]; |
347 | const SubRegMap &Map = SR->computeSubRegs(RegBank); |
348 | for (const auto &SubReg : Map) |
349 | if (Orphans.erase(SubReg.second)) |
350 | SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second; |
351 | } |
352 | |
353 | |
354 | for (const auto &SubReg : SubRegs) { |
| 14 | | Value assigned to field 'TheDef' | |
|
355 | if (SubReg.second == this) { |
| 15 | | Assuming the condition is true | |
|
| |
356 | ArrayRef<SMLoc> Loc; |
357 | if (TheDef) |
| 17 | | Assuming field 'TheDef' is null | |
|
| |
358 | Loc = TheDef->getLoc(); |
359 | PrintFatalError(Loc, "Register " + getName() + |
| 19 | | Calling 'CodeGenRegister::getName' | |
|
360 | " has itself as a sub-register"); |
361 | } |
362 | |
363 | |
364 | if (!CoveredBySubRegs) |
365 | SubReg.first->AllSuperRegsCovered = false; |
366 | |
367 | |
368 | DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = |
369 | SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first; |
370 | if (Ins->second == SubReg.first) |
371 | continue; |
372 | |
373 | ArrayRef<SMLoc> Loc; |
374 | if (TheDef) |
375 | Loc = TheDef->getLoc(); |
376 | PrintFatalError(Loc, "Sub-register can't have two names: " + |
377 | SubReg.second->getName() + " available as " + |
378 | SubReg.first->getName() + " and " + Ins->second->getName()); |
379 | } |
380 | |
381 | |
382 | |
383 | |
384 | |
385 | for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { |
386 | CodeGenRegister *SR = ExplicitSubRegs[i]; |
387 | if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1 || |
388 | SR->Artificial) |
389 | continue; |
390 | |
391 | |
392 | SmallVector<CodeGenSubRegIndex*, 8> Parts; |
393 | for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) { |
394 | CodeGenSubRegIndex &I = *SR->ExplicitSubRegIndices[j]; |
395 | if (!I.Artificial) |
396 | Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j])); |
397 | } |
398 | |
399 | |
400 | CodeGenSubRegIndex &Idx = *ExplicitSubRegIndices[i]; |
401 | Idx.setConcatenationOf(Parts); |
402 | } |
403 | |
404 | |
405 | |
406 | |
407 | |
408 | |
409 | for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { |
410 | CodeGenRegister *SR = ExplicitSubRegs[i]; |
411 | RegUnits |= SR->RegUnits; |
412 | } |
413 | |
414 | |
415 | |
416 | |
417 | |
418 | |
419 | |
420 | |
421 | |
422 | |
423 | for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) { |
424 | CodeGenRegister *AR = ExplicitAliases[i]; |
425 | |
426 | if (AR->SubRegsComplete) |
427 | continue; |
428 | |
429 | |
430 | unsigned Unit = RegBank.newRegUnit(this, AR); |
431 | RegUnits.set(Unit); |
432 | AR->RegUnits.set(Unit); |
433 | } |
434 | |
435 | |
436 | |
437 | |
438 | if (RegUnits.empty()) |
439 | RegUnits.set(RegBank.newRegUnit(this)); |
440 | |
441 | |
442 | |
443 | NativeRegUnits = RegUnits; |
444 | |
445 | return SubRegs; |
446 | } |
447 | |
448 | |
449 | |
450 | |
451 | |
452 | |
453 | |
454 | |
455 | |
456 | |
457 | |
458 | |
459 | |
460 | |
461 | void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) { |
462 | SmallVector<SubRegMap::value_type, 8> NewSubRegs; |
463 | |
464 | std::queue<std::pair<CodeGenSubRegIndex*,CodeGenRegister*>> SubRegQueue; |
465 | for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : SubRegs) |
466 | SubRegQueue.push(P); |
467 | |
468 | |
469 | |
470 | |
471 | while (!SubRegQueue.empty()) { |
472 | CodeGenSubRegIndex *SubRegIdx; |
473 | const CodeGenRegister *SubReg; |
474 | std::tie(SubRegIdx, SubReg) = SubRegQueue.front(); |
475 | SubRegQueue.pop(); |
476 | |
477 | const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs; |
478 | for (unsigned i = 0, e = Leads.size(); i != e; ++i) { |
479 | CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]); |
480 | |
481 | if (Cand == this || getSubRegIndex(Cand)) |
482 | continue; |
483 | |
484 | assert(!Cand->ExplicitSubRegs.empty() && |
485 | "Super-register has no sub-registers"); |
486 | if (Cand->ExplicitSubRegs.size() == 1) |
487 | continue; |
488 | SmallVector<CodeGenSubRegIndex*, 8> Parts; |
489 | |
490 | |
491 | assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct"); |
492 | assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"); |
493 | for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) { |
494 | if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { |
495 | if (SubRegIdx->ConcatenationOf.empty()) |
496 | Parts.push_back(SubRegIdx); |
497 | else |
498 | append_range(Parts, SubRegIdx->ConcatenationOf); |
499 | } else { |
500 | |
501 | Parts.clear(); |
502 | break; |
503 | } |
504 | } |
505 | |
506 | |
507 | if (Parts.empty()) |
508 | continue; |
509 | |
510 | |
511 | |
512 | CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts); |
513 | std::pair<CodeGenSubRegIndex*,CodeGenRegister*> NewSubReg = |
514 | std::make_pair(Concat, Cand); |
515 | |
516 | if (!SubRegs.insert(NewSubReg).second) |
517 | continue; |
518 | |
519 | |
520 | NewSubRegs.push_back(NewSubReg); |
521 | SubRegQueue.push(NewSubReg); |
522 | SubReg2Idx.insert(std::make_pair(Cand, Concat)); |
523 | } |
524 | } |
525 | |
526 | |
527 | for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) { |
528 | CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first; |
529 | CodeGenRegister *NewSubReg = NewSubRegs[i].second; |
530 | for (auto SubReg : NewSubReg->SubRegs) { |
531 | CodeGenSubRegIndex *SubIdx = getSubRegIndex(SubReg.second); |
532 | if (!SubIdx) |
533 | PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " + |
534 | SubReg.second->getName() + |
535 | " in " + getName()); |
536 | NewIdx->addComposite(SubReg.first, SubIdx); |
537 | } |
538 | } |
539 | } |
540 | |
541 | void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) { |
542 | |
543 | if (SuperRegsComplete) |
544 | return; |
545 | SuperRegsComplete = true; |
546 | |
547 | |
548 | |
549 | for (auto SubReg : SubRegs) |
550 | SubReg.second->computeSuperRegs(RegBank); |
551 | |
552 | |
553 | |
554 | TopoSigId Id; |
555 | for (auto SubReg : SubRegs) { |
556 | |
557 | |
558 | Id.push_back(SubReg.first->EnumValue); |
559 | Id.push_back(SubReg.second->TopoSig); |
560 | |
561 | |
562 | if (!SubReg.second->SuperRegs.empty() && |
563 | SubReg.second->SuperRegs.back() == this) |
564 | continue; |
565 | SubReg.second->SuperRegs.push_back(this); |
566 | } |
567 | TopoSig = RegBank.getTopoSig(Id); |
568 | } |
569 | |
570 | void |
571 | CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, |
572 | CodeGenRegBank &RegBank) const { |
573 | assert(SubRegsComplete && "Must precompute sub-registers"); |
574 | for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { |
575 | CodeGenRegister *SR = ExplicitSubRegs[i]; |
576 | if (OSet.insert(SR)) |
577 | SR->addSubRegsPreOrder(OSet, RegBank); |
578 | } |
579 | |
580 | for (auto SubReg : SubRegs) |
581 | OSet.insert(SubReg.second); |
582 | } |
583 | |
584 | |
585 | unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const { |
586 | unsigned Weight = 0; |
587 | for (unsigned RegUnit : RegUnits) { |
588 | Weight += RegBank.getRegUnit(RegUnit).Weight; |
589 | } |
590 | return Weight; |
591 | } |
592 | |
593 | |
594 | |
595 | |
596 | |
597 | |
598 | |
599 | |
600 | namespace { |
601 | |
602 | struct TupleExpander : SetTheory::Expander { |
603 | |
604 | |
605 | std::vector<std::unique_ptr<Record>> &SynthDefs; |
606 | |
607 | TupleExpander(std::vector<std::unique_ptr<Record>> &SynthDefs) |
608 | : SynthDefs(SynthDefs) {} |
609 | |
610 | void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override { |
611 | std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); |
612 | unsigned Dim = Indices.size(); |
613 | ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); |
614 | if (Dim != SubRegs->size()) |
615 | PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch"); |
616 | if (Dim < 2) |
617 | PrintFatalError(Def->getLoc(), |
618 | "Tuples must have at least 2 sub-registers"); |
619 | |
620 | |
621 | unsigned Length = ~0u; |
622 | SmallVector<SetTheory::RecSet, 4> Lists(Dim); |
623 | for (unsigned i = 0; i != Dim; ++i) { |
624 | ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc()); |
625 | Length = std::min(Length, unsigned(Lists[i].size())); |
626 | } |
627 | |
628 | if (Length == 0) |
629 | return; |
630 | |
631 | |
632 | Record *RegisterCl = Def->getRecords().getClass("Register"); |
633 | RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl); |
634 | std::vector<StringRef> RegNames = |
635 | Def->getValueAsListOfStrings("RegAsmNames"); |
636 | |
637 | |
638 | for (unsigned n = 0; n != Length; ++n) { |
639 | std::string Name; |
640 | Record *Proto = Lists[0][n]; |
641 | std::vector<Init*> Tuple; |
642 | for (unsigned i = 0; i != Dim; ++i) { |
643 | Record *Reg = Lists[i][n]; |
644 | if (i) Name += '_'; |
645 | Name += Reg->getName(); |
646 | Tuple.push_back(DefInit::get(Reg)); |
647 | } |
648 | |
649 | |
650 | ListInit *CostList = Proto->getValueAsListInit("CostPerUse"); |
651 | SmallVector<Init *, 2> CostPerUse; |
652 | CostPerUse.insert(CostPerUse.end(), CostList->begin(), CostList->end()); |
653 | |
654 | StringInit *AsmName = StringInit::get(""); |
655 | if (!RegNames.empty()) { |
656 | if (RegNames.size() <= n) |
657 | PrintFatalError(Def->getLoc(), |
658 | "Register tuple definition missing name for '" + |
659 | Name + "'."); |
660 | AsmName = StringInit::get(RegNames[n]); |
661 | } |
662 | |
663 | |
664 | |
665 | |
666 | SynthDefs.emplace_back( |
667 | std::make_unique<Record>(Name, Def->getLoc(), Def->getRecords())); |
668 | Record *NewReg = SynthDefs.back().get(); |
669 | Elts.insert(NewReg); |
670 | |
671 | |
672 | ArrayRef<std::pair<Record *, SMRange>> Supers = Proto->getSuperClasses(); |
673 | for (const auto &SuperPair : Supers) |
674 | NewReg->addSuperClass(SuperPair.first, SuperPair.second); |
675 | |
676 | |
677 | for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) { |
678 | RecordVal RV = Proto->getValues()[i]; |
679 | |
680 | |
681 | if (NewReg->getValue(RV.getNameInit())) |
682 | continue; |
683 | |
684 | StringRef Field = RV.getName(); |
685 | |
686 | |
687 | if (Field == "SubRegs") |
688 | RV.setValue(ListInit::get(Tuple, RegisterRecTy)); |
689 | |
690 | if (Field == "AsmName") |
691 | RV.setValue(AsmName); |
692 | |
693 | |
694 | if (Field == "CostPerUse") |
695 | RV.setValue(ListInit::get(CostPerUse, CostList->getElementType())); |
696 | |
697 | |
698 | if (Field == "CoveredBySubRegs") |
699 | RV.setValue(BitInit::get(true)); |
700 | |
701 | |
702 | if (Field == "SubRegIndices" || |
703 | Field == "CompositeIndices") { |
704 | NewReg->addValue(*Def->getValue(Field)); |
705 | continue; |
706 | } |
707 | |
708 | |
709 | if (Field == "DwarfNumbers" || |
710 | Field == "DwarfAlias" || |
711 | Field == "Aliases") { |
712 | if (const RecordVal *DefRV = RegisterCl->getValue(Field)) |
713 | NewReg->addValue(*DefRV); |
714 | continue; |
715 | } |
716 | |
717 | |
718 | NewReg->addValue(RV); |
719 | } |
720 | } |
721 | } |
722 | }; |
723 | |
724 | } |
725 | |
726 | |
727 | |
728 | |
729 | |
730 | static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) { |
731 | llvm::sort(M, deref<std::less<>>()); |
732 | M.erase(std::unique(M.begin(), M.end(), deref<std::equal_to<>>()), M.end()); |
733 | } |
734 | |
735 | CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) |
736 | : TheDef(R), Name(std::string(R->getName())), |
737 | TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1) { |
738 | GeneratePressureSet = R->getValueAsBit("GeneratePressureSet"); |
739 | std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); |
740 | if (TypeList.empty()) |
741 | PrintFatalError(R->getLoc(), "RegTypes list must not be empty!"); |
742 | for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { |
743 | Record *Type = TypeList[i]; |
744 | if (!Type->isSubClassOf("ValueType")) |
745 | PrintFatalError(R->getLoc(), |
746 | "RegTypes list member '" + Type->getName() + |
747 | "' does not derive from the ValueType class!"); |
748 | VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes())); |
749 | } |
750 | |
751 | |
752 | const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); |
753 | ListInit *AltOrders = R->getValueAsListInit("AltOrders"); |
754 | Orders.resize(1 + AltOrders->size()); |
755 | |
756 | |
757 | Artificial = true; |
758 | for (unsigned i = 0, e = Elements->size(); i != e; ++i) { |
759 | Orders[0].push_back((*Elements)[i]); |
760 | const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]); |
761 | Members.push_back(Reg); |
762 | Artificial &= Reg->Artificial; |
763 | TopoSigs.set(Reg->getTopoSig()); |
764 | } |
765 | sortAndUniqueRegisters(Members); |
766 | |
767 | |
768 | SetTheory::RecSet Order; |
769 | for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { |
770 | RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); |
771 | Orders[1 + i].append(Order.begin(), Order.end()); |
772 | |
773 | while (!Order.empty()) { |
774 | CodeGenRegister *Reg = RegBank.getReg(Order.back()); |
775 | Order.pop_back(); |
776 | if (!contains(Reg)) |
777 | PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() + |
778 | " is not a class member"); |
779 | } |
780 | } |
781 | |
782 | Namespace = R->getValueAsString("Namespace"); |
783 | |
784 | if (const RecordVal *RV = R->getValue("RegInfos")) |
785 | if (DefInit *DI = dyn_cast_or_null<DefInit>(RV->getValue())) |
786 | RSI = RegSizeInfoByHwMode(DI->getDef(), RegBank.getHwModes()); |
787 | unsigned Size = R->getValueAsInt("Size"); |
788 | assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) && |
789 | "Impossible to determine register size"); |
790 | if (!RSI.hasDefault()) { |
791 | RegSizeInfo RI; |
792 | RI.RegSize = RI.SpillSize = Size ? Size |
793 | : VTs[0].getSimple().getSizeInBits(); |
794 | RI.SpillAlignment = R->getValueAsInt("Alignment"); |
795 | RSI.insertRegSizeForMode(DefaultMode, RI); |
796 | } |
797 | |
798 | CopyCost = R->getValueAsInt("CopyCost"); |
799 | Allocatable = R->getValueAsBit("isAllocatable"); |
800 | AltOrderSelect = R->getValueAsString("AltOrderSelect"); |
801 | int AllocationPriority = R->getValueAsInt("AllocationPriority"); |
802 | if (AllocationPriority < 0 || AllocationPriority > 63) |
803 | PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]"); |
804 | this->AllocationPriority = AllocationPriority; |
805 | } |
806 | |
807 | |
808 | |
809 | |
810 | CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, |
811 | StringRef Name, Key Props) |
812 | : Members(*Props.Members), TheDef(nullptr), Name(std::string(Name)), |
813 | TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), RSI(Props.RSI), |
814 | CopyCost(0), Allocatable(true), AllocationPriority(0) { |
815 | Artificial = true; |
816 | GeneratePressureSet = false; |
817 | for (const auto R : Members) { |
818 | TopoSigs.set(R->getTopoSig()); |
819 | Artificial &= R->Artificial; |
820 | } |
821 | } |
822 | |
823 | |
824 | void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) { |
825 | assert(!getDef() && "Only synthesized classes can inherit properties"); |
826 | assert(!SuperClasses.empty() && "Synthesized class without super class"); |
827 | |
828 | |
829 | CodeGenRegisterClass &Super = *SuperClasses.back(); |
830 | |
831 | |
832 | |
833 | Namespace = Super.Namespace; |
834 | VTs = Super.VTs; |
835 | CopyCost = Super.CopyCost; |
836 | |
837 | Allocatable = any_of(SuperClasses, [&](const CodeGenRegisterClass *S) { |
838 | return S->Allocatable; |
839 | }); |
840 | AltOrderSelect = Super.AltOrderSelect; |
841 | AllocationPriority = Super.AllocationPriority; |
842 | GeneratePressureSet |= Super.GeneratePressureSet; |
843 | |
844 | |
845 | |
846 | Orders.resize(Super.Orders.size()); |
847 | for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) |
848 | for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) |
849 | if (contains(RegBank.getReg(Super.Orders[i][j]))) |
850 | Orders[i].push_back(Super.Orders[i][j]); |
851 | } |
852 | |
853 | bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const { |
854 | return std::binary_search(Members.begin(), Members.end(), Reg, |
855 | deref<std::less<>>()); |
856 | } |
857 | |
858 | unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank& RegBank) const { |
859 | if (TheDef && !TheDef->isValueUnset("Weight")) |
860 | return TheDef->getValueAsInt("Weight"); |
861 | |
862 | if (Members.empty() || Artificial) |
863 | return 0; |
864 | |
865 | return (*Members.begin())->getWeight(RegBank); |
866 | } |
867 | |
868 | namespace llvm { |
869 | |
870 | raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) { |
871 | OS << "{ " << K.RSI; |
872 | for (const auto R : *K.Members) |
873 | OS << ", " << R->getName(); |
874 | return OS << " }"; |
875 | } |
876 | |
877 | } |
878 | |
879 | |
880 | |
881 | bool CodeGenRegisterClass::Key:: |
882 | operator<(const CodeGenRegisterClass::Key &B) const { |
883 | assert(Members && B.Members); |
884 | return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI); |
885 | } |
886 | |
887 | |
888 | |
889 | |
890 | |
891 | |
892 | |
893 | |
894 | |
895 | |
896 | static bool testSubClass(const CodeGenRegisterClass *A, |
897 | const CodeGenRegisterClass *B) { |
898 | return A->RSI.isSubClassOf(B->RSI) && |
899 | std::includes(A->getMembers().begin(), A->getMembers().end(), |
900 | B->getMembers().begin(), B->getMembers().end(), |
901 | deref<std::less<>>()); |
902 | } |
903 | |
904 | |
905 | |
906 | |
907 | |
908 | |
909 | |
910 | static bool TopoOrderRC(const CodeGenRegisterClass &PA, |
911 | const CodeGenRegisterClass &PB) { |
912 | auto *A = &PA; |
913 | auto *B = &PB; |
914 | if (A == B) |
915 | return false; |
916 | |
917 | if (A->RSI < B->RSI) |
918 | return true; |
919 | if (A->RSI != B->RSI) |
920 | return false; |
921 | |
922 | |
923 | |
924 | if (A->getMembers().size() > B->getMembers().size()) |
925 | return true; |
926 | if (A->getMembers().size() < B->getMembers().size()) |
927 | return false; |
928 | |
929 | |
930 | return StringRef(A->getName()) < B->getName(); |
931 | } |
932 | |
933 | std::string CodeGenRegisterClass::getQualifiedName() const { |
934 | if (Namespace.empty()) |
935 | return getName(); |
936 | else |
937 | return (Namespace + "::" + getName()).str(); |
938 | } |
939 | |
940 | |
941 | |
942 | void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) { |
943 | auto &RegClasses = RegBank.getRegClasses(); |
944 | |
945 | |
946 | for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { |
947 | CodeGenRegisterClass &RC = *I; |
948 | RC.SubClasses.resize(RegClasses.size()); |
949 | RC.SubClasses.set(RC.EnumValue); |
950 | if (RC.Artificial) |
951 | continue; |
952 | |
953 | |
954 | for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) { |
955 | CodeGenRegisterClass &SubRC = *I2; |
956 | if (RC.SubClasses.test(SubRC.EnumValue)) |
957 | continue; |
958 | if (!testSubClass(&RC, &SubRC)) |
959 | continue; |
960 | |
961 | |
962 | RC.SubClasses |= SubRC.SubClasses; |
963 | } |
964 | |
965 | |
966 | for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2) |
967 | RC.SubClasses.set(I2->EnumValue); |
968 | } |
969 | |
970 | |
971 | for (auto &RC : RegClasses) { |
972 | const BitVector &SC = RC.getSubClasses(); |
973 | auto I = RegClasses.begin(); |
974 | for (int s = 0, next_s = SC.find_first(); next_s != -1; |
975 | next_s = SC.find_next(s)) { |
976 | std::advance(I, next_s - s); |
977 | s = next_s; |
978 | if (&*I == &RC) |
979 | continue; |
980 | I->SuperClasses.push_back(&RC); |
981 | } |
982 | } |
983 | |
984 | |
985 | |
986 | |
987 | for (auto &RC : RegClasses) |
988 | if (!RC.getDef()) |
989 | RC.inheritProperties(RegBank); |
990 | } |
991 | |
992 | Optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>> |
993 | CodeGenRegisterClass::getMatchingSubClassWithSubRegs( |
994 | CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const { |
995 | auto SizeOrder = [this](const CodeGenRegisterClass *A, |
996 | const CodeGenRegisterClass *B) { |
997 | |
998 | |
999 | if (A == B) |
1000 | return false; |
1001 | if (A->getMembers().size() == B->getMembers().size()) |
1002 | return A == this; |
1003 | return A->getMembers().size() > B->getMembers().size(); |
1004 | }; |
1005 | |
1006 | auto &RegClasses = RegBank.getRegClasses(); |
1007 | |
1008 | |
1009 | |
1010 | CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx); |
1011 | if (!BiggestSuperRegRC) |
1012 | return None; |
1013 | BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses(); |
1014 | std::vector<CodeGenRegisterClass *> SuperRegRCs; |
1015 | for (auto &RC : RegClasses) |
1016 | if (SuperRegRCsBV[RC.EnumValue]) |
1017 | SuperRegRCs.emplace_back(&RC); |
1018 | llvm::stable_sort(SuperRegRCs, SizeOrder); |
1019 | |
1020 | assert(SuperRegRCs.front() == BiggestSuperRegRC && |
1021 | "Biggest class wasn't first"); |
1022 | |
1023 | |
1024 | std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses; |
1025 | for (auto &RC: RegClasses) { |
1026 | BitVector SuperRegClassesBV(RegClasses.size()); |
1027 | RC.getSuperRegClasses(SubIdx, SuperRegClassesBV); |
1028 | if (SuperRegClassesBV.any()) |
1029 | SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV)); |
1030 | } |
1031 | llvm::sort(SuperRegClasses, |
1032 | [&](const std::pair<CodeGenRegisterClass *, BitVector> &A, |
1033 | const std::pair<CodeGenRegisterClass *, BitVector> &B) { |
1034 | return SizeOrder(A.first, B.first); |
1035 | }); |
1036 | |
1037 | |
1038 | |
1039 | |
1040 | |
1041 | |
1042 | |
1043 | |
1044 | |
1045 | |
1046 | CodeGenRegisterClass *ChosenSuperRegClass = nullptr; |
1047 | CodeGenRegisterClass *SubRegRC = nullptr; |
1048 | for (auto *SuperRegRC : SuperRegRCs) { |
1049 | for (const auto &SuperRegClassPair : SuperRegClasses) { |
1050 | const BitVector &SuperRegClassBV = SuperRegClassPair.second; |
1051 | if (SuperRegClassBV[SuperRegRC->EnumValue]) { |
1052 | SubRegRC = SuperRegClassPair.first; |
1053 | ChosenSuperRegClass = SuperRegRC; |
1054 | |
1055 | |
1056 | |
1057 | |
1058 | |
1059 | |
1060 | |
1061 | |
1062 | |
1063 | |
1064 | if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size()) |
1065 | return std::make_pair(ChosenSuperRegClass, SubRegRC); |
1066 | } |
1067 | } |
1068 | |
1069 | |
1070 | |
1071 | if (ChosenSuperRegClass) |
1072 | return std::make_pair(ChosenSuperRegClass, SubRegRC); |
1073 | } |
1074 | |
1075 | return None; |
1076 | } |
1077 | |
1078 | void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, |
1079 | BitVector &Out) const { |
1080 | auto FindI = SuperRegClasses.find(SubIdx); |
1081 | if (FindI == SuperRegClasses.end()) |
1082 | return; |
1083 | for (CodeGenRegisterClass *RC : FindI->second) |
1084 | Out.set(RC->EnumValue); |
1085 | } |
1086 | |
1087 | |
1088 | void CodeGenRegisterClass::buildRegUnitSet(const CodeGenRegBank &RegBank, |
1089 | std::vector<unsigned> &RegUnits) const { |
1090 | std::vector<unsigned> TmpUnits; |
1091 | for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI) { |
1092 | const RegUnit &RU = RegBank.getRegUnit(*UnitI); |
1093 | if (!RU.Artificial) |
1094 | TmpUnits.push_back(*UnitI); |
1095 | } |
1096 | llvm::sort(TmpUnits); |
1097 | std::unique_copy(TmpUnits.begin(), TmpUnits.end(), |
1098 | std::back_inserter(RegUnits)); |
1099 | } |
1100 | |
1101 | |
1102 | |
1103 | |
1104 | |
1105 | CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records, |
1106 | const CodeGenHwModes &Modes) : CGH(Modes) { |
1107 | |
1108 | Sets.addFieldExpander("RegisterClass", "MemberList"); |
1109 | Sets.addFieldExpander("CalleeSavedRegs", "SaveList"); |
1110 | Sets.addExpander("RegisterTuples", |
1111 | std::make_unique<TupleExpander>(SynthDefs)); |
1112 | |
1113 | |
1114 | |
1115 | std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex"); |
1116 | llvm::sort(SRIs, LessRecord()); |
1117 | for (unsigned i = 0, e = SRIs.size(); i != e; ++i) |
| 1 | Assuming 'i' is equal to 'e' | |
|
| 2 | | Loop condition is false. Execution continues on line 1120 | |
|
1118 | getSubRegIdx(SRIs[i]); |
1119 | |
1120 | for (auto &Idx : SubRegIndices) |
1121 | Idx.updateComponents(*this); |
1122 | |
1123 | |
1124 | std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); |
1125 | llvm::sort(Regs, LessRecordRegister()); |
1126 | |
1127 | for (unsigned i = 0, e = Regs.size(); i != e; ++i) |
| 3 | | Assuming 'i' is equal to 'e' | |
|
| 4 | | Loop condition is false. Execution continues on line 1132 | |
|
1128 | getReg(Regs[i]); |
1129 | |
1130 | |
1131 | std::vector<Record*> Tups = |
1132 | Records.getAllDerivedDefinitions("RegisterTuples"); |
1133 | |
1134 | for (Record *R : Tups) { |
1135 | std::vector<Record *> TupRegs = *Sets.expand(R); |
1136 | llvm::sort(TupRegs, LessRecordRegister()); |
1137 | for (Record *RC : TupRegs) |
1138 | getReg(RC); |
1139 | } |
1140 | |
1141 | |
1142 | |
1143 | for (auto &Reg : Registers) |
1144 | Reg.buildObjectGraph(*this); |
1145 | |
1146 | |
1147 | for (auto &Reg : Registers) |
1148 | |
1149 | |
1150 | |
1151 | |
1152 | RegistersByName.insert( |
1153 | std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg)); |
1154 | |
1155 | |
1156 | |
1157 | for (auto &Reg : Registers) |
1158 | Reg.computeSubRegs(*this); |
| 5 | | Calling 'CodeGenRegister::computeSubRegs' | |
|
1159 | |
1160 | |
1161 | |
1162 | for (CodeGenSubRegIndex &SRI : SubRegIndices) { |
1163 | SRI.computeConcatTransitiveClosure(); |
1164 | if (!SRI.ConcatenationOf.empty()) |
1165 | ConcatIdx.insert(std::make_pair( |
1166 | SmallVector<CodeGenSubRegIndex*,8>(SRI.ConcatenationOf.begin(), |
1167 | SRI.ConcatenationOf.end()), &SRI)); |
1168 | } |
1169 | |
1170 | |
1171 | for (auto &Reg : Registers) |
1172 | if (Reg.CoveredBySubRegs) |
1173 | Reg.computeSecondarySubRegs(*this); |
1174 | |
1175 | |
1176 | |
1177 | for (auto &Reg : Registers) |
1178 | Reg.computeSuperRegs(*this); |
1179 | |
1180 | |
1181 | |
1182 | for (auto &Reg : Registers) { |
1183 | if (Reg.Artificial) |
1184 | continue; |
1185 | for (auto P : Reg.getSubRegs()) { |
1186 | const CodeGenRegister *SR = P.second; |
1187 | if (!SR->Artificial) |
1188 | P.first->Artificial = false; |
1189 | } |
1190 | } |
1191 | |
1192 | |
1193 | |
1194 | NumNativeRegUnits = RegUnits.size(); |
1195 | |
1196 | |
1197 | std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass"); |
1198 | if (RCs.empty()) |
1199 | PrintFatalError("No 'RegisterClass' subclasses defined!"); |
1200 | |
1201 | |
1202 | for (auto *R : RCs) { |
1203 | RegClasses.emplace_back(*this, R); |
1204 | CodeGenRegisterClass &RC = RegClasses.back(); |
1205 | if (!RC.Artificial) |
1206 | addToMaps(&RC); |
1207 | } |
1208 | |
1209 | |
1210 | computeInferredRegisterClasses(); |
1211 | |
1212 | |
1213 | RegClasses.sort(TopoOrderRC); |
1214 | unsigned i = 0; |
1215 | for (auto &RC : RegClasses) |
1216 | RC.EnumValue = i++; |
1217 | CodeGenRegisterClass::computeSubClasses(*this); |
1218 | } |
1219 | |
1220 | |
1221 | CodeGenSubRegIndex* |
1222 | CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) { |
1223 | SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1); |
1224 | return &SubRegIndices.back(); |
1225 | } |
1226 | |
1227 | CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) { |
1228 | CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def]; |
1229 | if (Idx) |
1230 | return Idx; |
1231 | SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1); |
1232 | Idx = &SubRegIndices.back(); |
1233 | return Idx; |
1234 | } |
1235 | |
1236 | const CodeGenSubRegIndex * |
1237 | CodeGenRegBank::findSubRegIdx(const Record* Def) const { |
1238 | return Def2SubRegIdx.lookup(Def); |
1239 | } |
1240 | |
1241 | CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { |
1242 | CodeGenRegister *&Reg = Def2Reg[Def]; |
1243 | if (Reg) |
1244 | return Reg; |
1245 | Registers.emplace_back(Def, Registers.size() + 1); |
1246 | Reg = &Registers.back(); |
1247 | return Reg; |
1248 | } |
1249 | |
1250 | void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { |
1251 | if (Record *Def = RC->getDef()) |
1252 | Def2RC.insert(std::make_pair(Def, RC)); |
1253 | |
1254 | |
1255 | |
1256 | CodeGenRegisterClass::Key K(*RC); |
1257 | Key2RC.insert(std::make_pair(K, RC)); |
1258 | } |
1259 | |
1260 | |
1261 | CodeGenRegisterClass* |
1262 | CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, |
1263 | const CodeGenRegister::Vec *Members, |
1264 | StringRef Name) { |
1265 | |
1266 | CodeGenRegisterClass::Key K(Members, RC->RSI); |
1267 | RCKeyMap::const_iterator FoundI = Key2RC.find(K); |
1268 | if (FoundI != Key2RC.end()) |
1269 | return FoundI->second; |
1270 | |
1271 | |
1272 | RegClasses.emplace_back(*this, Name, K); |
1273 | addToMaps(&RegClasses.back()); |
1274 | return &RegClasses.back(); |
1275 | } |
1276 | |
1277 | CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const { |
1278 | if (CodeGenRegisterClass *RC = Def2RC.lookup(Def)) |
1279 | return RC; |
1280 | |
1281 | PrintFatalError(Def->getLoc(), "Not a known RegisterClass!"); |
1282 | } |
1283 | |
1284 | CodeGenSubRegIndex* |
1285 | CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A, |
1286 | CodeGenSubRegIndex *B) { |
1287 | |
1288 | CodeGenSubRegIndex *Comp = A->compose(B); |
1289 | if (Comp) |
1290 | return Comp; |
1291 | |
1292 | |
1293 | std::string Name = A->getName() + "_then_" + B->getName(); |
1294 | Comp = createSubRegIndex(Name, A->getNamespace()); |
1295 | A->addComposite(B, Comp); |
1296 | return Comp; |
1297 | } |
1298 | |
1299 | CodeGenSubRegIndex *CodeGenRegBank:: |
1300 | getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) { |
1301 | assert(Parts.size() > 1 && "Need two parts to concatenate"); |
1302 | #ifndef NDEBUG |
1303 | for (CodeGenSubRegIndex *Idx : Parts) { |
1304 | assert(Idx->ConcatenationOf.empty() && "No transitive closure?"); |
1305 | } |
1306 | #endif |
1307 | |
1308 | |
1309 | CodeGenSubRegIndex *&Idx = ConcatIdx[Parts]; |
1310 | if (Idx) |
1311 | return Idx; |
1312 | |
1313 | |
1314 | std::string Name = Parts.front()->getName(); |
1315 | |
1316 | bool isContinuous = true; |
1317 | unsigned Size = Parts.front()->Size; |
1318 | unsigned LastOffset = Parts.front()->Offset; |
1319 | unsigned LastSize = Parts.front()->Size; |
1320 | for (unsigned i = 1, e = Parts.size(); i != e; ++i) { |
1321 | Name += '_'; |
1322 | Name += Parts[i]->getName(); |
1323 | Size += Parts[i]->Size; |
1324 | if (Parts[i]->Offset != (LastOffset + LastSize)) |
1325 | isContinuous = false; |
1326 | LastOffset = Parts[i]->Offset; |
1327 | LastSize = Parts[i]->Size; |
1328 | } |
1329 | Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); |
1330 | Idx->Size = Size; |
1331 | Idx->Offset = isContinuous ? Parts.front()->Offset : -1; |
1332 | Idx->ConcatenationOf.assign(Parts.begin(), Parts.end()); |
1333 | return Idx; |
1334 | } |
1335 | |
1336 | void CodeGenRegBank::computeComposites() { |
1337 | using RegMap = std::map<const CodeGenRegister*, const CodeGenRegister*>; |
1338 | |
1339 | |
1340 | |
1341 | |
1342 | std::map<const CodeGenSubRegIndex*, RegMap> SubRegAction; |
1343 | for (const CodeGenRegister &R : Registers) { |
1344 | const CodeGenRegister::SubRegMap &SM = R.getSubRegs(); |
1345 | for (std::pair<const CodeGenSubRegIndex*, const CodeGenRegister*> P : SM) |
1346 | SubRegAction[P.first].insert({&R, P.second}); |
1347 | } |
1348 | |
1349 | |
1350 | |
1351 | auto compose = [&SubRegAction] (const CodeGenSubRegIndex *Sub1, |
1352 | const CodeGenSubRegIndex *Sub2) { |
1353 | RegMap C; |
1354 | const RegMap &Img1 = SubRegAction.at(Sub1); |
1355 | const RegMap &Img2 = SubRegAction.at(Sub2); |
1356 | for (std::pair<const CodeGenRegister*, const CodeGenRegister*> P : Img1) { |
1357 | auto F = Img2.find(P.second); |
1358 | if (F != Img2.end()) |
1359 | C.insert({P.first, F->second}); |
1360 | } |
1361 | return C; |
1362 | }; |
1363 | |
1364 | |
1365 | auto agree = [] (const RegMap &Map1, const RegMap &Map2) { |
1366 | |
1367 | |
1368 | |
1369 | if (Map1.empty() || Map2.empty()) |
1370 | return false; |
1371 | for (std::pair<const CodeGenRegister*, const CodeGenRegister*> P : Map1) { |
1372 | auto F = Map2.find(P.first); |
1373 | if (F == Map2.end() || P.second != F->second) |
1374 | return false; |
1375 | } |
1376 | return true; |
1377 | }; |
1378 | |
1379 | using CompositePair = std::pair<const CodeGenSubRegIndex*, |
1380 | const CodeGenSubRegIndex*>; |
1381 | SmallSet<CompositePair,4> UserDefined; |
1382 | for (const CodeGenSubRegIndex &Idx : SubRegIndices) |
1383 | for (auto P : Idx.getComposites()) |
1384 | UserDefined.insert(std::make_pair(&Idx, P.first)); |
1385 | |
1386 | |
1387 | |
1388 | BitVector TopoSigs(getNumTopoSigs()); |
1389 | |
1390 | for (const auto &Reg1 : Registers) { |
1391 | |
1392 | if (TopoSigs.test(Reg1.getTopoSig())) |
1393 | continue; |
1394 | TopoSigs.set(Reg1.getTopoSig()); |
1395 | |
1396 | const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); |
1397 | for (auto I1 : SRM1) { |
1398 | CodeGenSubRegIndex *Idx1 = I1.first; |
1399 | CodeGenRegister *Reg2 = I1.second; |
1400 | |
1401 | if (&Reg1 == Reg2) |
1402 | continue; |
1403 | const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); |
1404 | |
1405 | for (auto I2 : SRM2) { |
1406 | CodeGenSubRegIndex *Idx2 = I2.first; |
1407 | CodeGenRegister *Reg3 = I2.second; |
1408 | |
1409 | if (Reg2 == Reg3) |
1410 | continue; |
1411 | |
1412 | CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3); |
1413 | assert(Idx3 && "Sub-register doesn't have an index"); |
1414 | |
1415 | |
1416 | if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3)) { |
1417 | |
1418 | if (!UserDefined.count({Idx1, Idx2}) || |
1419 | agree(compose(Idx1, Idx2), SubRegAction.at(Idx3))) |
1420 | PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() + |
1421 | " and " + Idx2->getQualifiedName() + |
1422 | " compose ambiguously as " + Prev->getQualifiedName() + |
1423 | " or " + Idx3->getQualifiedName()); |
1424 | } |
1425 | } |
1426 | } |
1427 | } |
1428 | } |
1429 | |
1430 | |
1431 | |
1432 | |
1433 | |
1434 | |
1435 | |
1436 | |
1437 | void CodeGenRegBank::computeSubRegLaneMasks() { |
1438 | |
1439 | unsigned Bit = 0; |
1440 | |
1441 | CoveringLanes = LaneBitmask::getAll(); |
1442 | for (auto &Idx : SubRegIndices) { |
1443 | if (Idx.getComposites().empty()) { |
1444 | if (Bit > LaneBitmask::BitWidth) { |
1445 | PrintFatalError( |
1446 | Twine("Ran out of lanemask bits to represent subregister ") |
1447 | + Idx.getName()); |
1448 | } |
1449 | Idx.LaneMask = LaneBitmask::getLane(Bit); |
1450 | ++Bit; |
1451 | } else { |
1452 | Idx.LaneMask = LaneBitmask::getNone(); |
1453 | } |
1454 | } |
1455 | |
1456 | |
1457 | |
1458 | |
1459 | |
1460 | |
1461 | |
1462 | |
1463 | for (const auto &Idx : SubRegIndices) { |
1464 | const auto &Composites = Idx.getComposites(); |
1465 | auto &LaneTransforms = Idx.CompositionLaneMaskTransform; |
1466 | |
1467 | if (Composites.empty()) { |
1468 | |
1469 | |
1470 | |
1471 | unsigned DstBit = Idx.LaneMask.getHighestLane(); |
1472 | assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) && |
1473 | "Must be a leaf subregister"); |
1474 | MaskRolPair MaskRol = { LaneBitmask::getLane(0), (uint8_t)DstBit }; |
1475 | LaneTransforms.push_back(MaskRol); |
1476 | } else { |
1477 | |
1478 | |
1479 | |
1480 | |
1481 | unsigned NextBit = 0; |
1482 | for (auto &Idx2 : SubRegIndices) { |
1483 | |
1484 | if (!Idx2.getComposites().empty()) |
1485 | continue; |
1486 | |
1487 | unsigned SrcBit = NextBit; |
1488 | LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit); |
1489 | if (NextBit < LaneBitmask::BitWidth-1) |
1490 | ++NextBit; |
1491 | assert(Idx2.LaneMask == SrcMask); |
1492 | |
1493 | |
1494 | auto C = Composites.find(&Idx2); |
1495 | if (C == Composites.end()) |
1496 | continue; |
1497 | const CodeGenSubRegIndex *Composite = C->second; |
1498 | |
1499 | assert(Composite->getComposites().empty()); |
1500 | |
1501 | |
1502 | unsigned DstBit = Composite->LaneMask.getHighestLane(); |
1503 | int Shift = DstBit - SrcBit; |
1504 | uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift |
1505 | : LaneBitmask::BitWidth + Shift; |
1506 | for (auto &I : LaneTransforms) { |
1507 | if (I.RotateLeft == RotateLeft) { |
1508 | I.Mask |= SrcMask; |
1509 | SrcMask = LaneBitmask::getNone(); |
1510 | } |
1511 | } |
1512 | if (SrcMask.any()) { |
1513 | MaskRolPair MaskRol = { SrcMask, RotateLeft }; |
1514 | LaneTransforms.push_back(MaskRol); |
1515 | } |
1516 | } |
1517 | } |
1518 | |
1519 | |
1520 | |
1521 | |
1522 | if (LaneTransforms.size() == 1) |
1523 | LaneTransforms[0].Mask = LaneBitmask::getAll(); |
1524 | |
1525 | |
1526 | |
1527 | |
1528 | if (LaneTransforms.size() == 0) { |
1529 | MaskRolPair P = { LaneBitmask::getAll(), 0 }; |
1530 | LaneTransforms.push_back(P); |
1531 | } |
1532 | } |
1533 | |
1534 | |
1535 | |
1536 | |
1537 | |
1538 | for (const auto &Idx : SubRegIndices) { |
1539 | LaneBitmask Mask = Idx.computeLaneMask(); |
1540 | |
1541 | |
1542 | if (!Idx.AllSuperRegsCovered) |
1543 | CoveringLanes &= ~Mask; |
1544 | } |
1545 | |
1546 | |
1547 | for (auto &RegClass : RegClasses) { |
1548 | LaneBitmask LaneMask; |
1549 | for (const auto &SubRegIndex : SubRegIndices) { |
1550 | if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) |
1551 | continue; |
1552 | LaneMask |= SubRegIndex.LaneMask; |
1553 | } |
1554 | |
1555 | |
1556 | |
1557 | if (LaneMask.none()) |
1558 | LaneMask = LaneBitmask::getLane(0); |
1559 | |
1560 | RegClass.LaneMask = LaneMask; |
1561 | } |
1562 | } |
1563 | |
1564 | namespace { |
1565 | |
1566 | |
1567 | |
1568 | |
1569 | |
1570 | |
1571 | |
1572 | |
1573 | |
1574 | |
1575 | |
1576 | |
1577 | |
1578 | |
1579 | |
1580 | |
1581 | |
1582 | struct UberRegSet { |
1583 | CodeGenRegister::Vec Regs; |
1584 | unsigned Weight = 0; |
1585 | CodeGenRegister::RegUnitList SingularDeterminants; |
1586 | |
1587 | UberRegSet() = default; |
1588 | }; |
1589 | |
1590 | } |
1591 | |
1592 | |
1593 | |
1594 | |
1595 | |
1596 | static void computeUberSets(std::vector<UberRegSet> &UberSets, |
1597 | std::vector<UberRegSet*> &RegSets, |
1598 | CodeGenRegBank &RegBank) { |
1599 | const auto &Registers = RegBank.getRegisters(); |
1600 | |
1601 | |
1602 | assert(Registers.size() == Registers.back().EnumValue && |
1603 | "register enum value mismatch"); |
1604 | |
1605 | |
1606 | IntEqClasses UberSetIDs(Registers.size()+1); |
1607 | std::set<unsigned> AllocatableRegs; |
1608 | for (auto &RegClass : RegBank.getRegClasses()) { |
1609 | if (!RegClass.Allocatable) |
1610 | continue; |
1611 | |
1612 | const CodeGenRegister::Vec &Regs = RegClass.getMembers(); |
1613 | if (Regs.empty()) |
1614 | continue; |
1615 | |
1616 | unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue); |
1617 | assert(USetID && "register number 0 is invalid"); |
1618 | |
1619 | AllocatableRegs.insert((*Regs.begin())->EnumValue); |
1620 | for (auto I = std::next(Regs.begin()), E = Regs.end(); I != E; ++I) { |
1621 | AllocatableRegs.insert((*I)->EnumValue); |
1622 | UberSetIDs.join(USetID, (*I)->EnumValue); |
1623 | } |
1624 | } |
1625 | |
1626 | for (const auto &Reg : Registers) { |
1627 | unsigned RegNum = Reg.EnumValue; |
1628 | if (AllocatableRegs.count(RegNum)) |
1629 | continue; |
1630 | |
1631 | UberSetIDs.join(0, RegNum); |
1632 | } |
1633 | UberSetIDs.compress(); |
1634 | |
1635 | |
1636 | unsigned ZeroID = UberSetIDs[0]; |
1637 | |
1638 | |
1639 | |
1640 | UberSets.resize(UberSetIDs.getNumClasses()); |
1641 | unsigned i = 0; |
1642 | for (const CodeGenRegister &Reg : Registers) { |
1643 | unsigned USetID = UberSetIDs[Reg.EnumValue]; |
1644 | if (!USetID) |
1645 | USetID = ZeroID; |
1646 | else if (USetID == ZeroID) |
1647 | USetID = 0; |
1648 | |
1649 | UberRegSet *USet = &UberSets[USetID]; |
1650 | USet->Regs.push_back(&Reg); |
1651 | sortAndUniqueRegisters(USet->Regs); |
1652 | RegSets[i++] = USet; |
1653 | } |
1654 | } |
1655 | |
1656 | |
1657 | static void computeUberWeights(std::vector<UberRegSet> &UberSets, |
1658 | CodeGenRegBank &RegBank) { |
1659 | |
1660 | for (std::vector<UberRegSet>::iterator I = std::next(UberSets.begin()), |
1661 | E = UberSets.end(); I != E; ++I) { |
1662 | |
1663 | |
1664 | const CodeGenRegister *Reg = nullptr; |
1665 | unsigned MaxWeight = 0, Weight = 0; |
1666 | for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) { |
1667 | if (Reg != UnitI.getReg()) { |
1668 | if (Weight > MaxWeight) |
1669 | MaxWeight = Weight; |
1670 | Reg = UnitI.getReg(); |
1671 | Weight = 0; |
1672 | } |
1673 | if (!RegBank.getRegUnit(*UnitI).Artificial) { |
1674 | unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight; |
1675 | if (!UWeight) { |
1676 | UWeight = 1; |
1677 | RegBank.increaseRegUnitWeight(*UnitI, UWeight); |
1678 | } |
1679 | Weight += UWeight; |
1680 | } |
1681 | } |
1682 | if (Weight > MaxWeight) |
1683 | MaxWeight = Weight; |
1684 | if (I->Weight != MaxWeight) { |
1685 | LLVM_DEBUG(dbgs() << "UberSet " << I - UberSets.begin() << " Weight " |
1686 | << MaxWeight; |
1687 | for (auto &Unit |
1688 | : I->Regs) dbgs() |
1689 | << " " << Unit->getName(); |
1690 | dbgs() << "\n"); |
1691 | |
1692 | I->Weight = MaxWeight; |
1693 | } |
1694 | |
1695 | |
1696 | for (const auto R : I->Regs) { |
1697 | if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == I->Weight) { |
1698 | I->SingularDeterminants |= R->getRegUnits(); |
1699 | } |
1700 | } |
1701 | } |
1702 | } |
1703 | |
1704 | |
1705 | |
1706 | |
1707 | |
1708 | |
1709 | |
1710 | |
1711 | |
1712 | |
1713 | |
1714 | static bool normalizeWeight(CodeGenRegister *Reg, |
1715 | std::vector<UberRegSet> &UberSets, |
1716 | std::vector<UberRegSet*> &RegSets, |
1717 | BitVector &NormalRegs, |
1718 | CodeGenRegister::RegUnitList &NormalUnits, |
1719 | CodeGenRegBank &RegBank) { |
1720 | NormalRegs.resize(std::max(Reg->EnumValue + 1, NormalRegs.size())); |
1721 | if (NormalRegs.test(Reg->EnumValue)) |
1722 | return false; |
1723 | NormalRegs.set(Reg->EnumValue); |
1724 | |
1725 | bool Changed = false; |
1726 | const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); |
1727 | for (auto SRI : SRM) { |
1728 | if (SRI.second == Reg) |
1729 | continue; |
1730 | |
1731 | Changed |= normalizeWeight(SRI.second, UberSets, RegSets, NormalRegs, |
1732 | NormalUnits, RegBank); |
1733 | } |
1734 | |
1735 | |
1736 | |
1737 | if (Reg->inheritRegUnits(RegBank)) |
1738 | computeUberWeights(UberSets, RegBank); |
1739 | |
1740 | |
1741 | UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)]; |
1742 | |
1743 | unsigned RegWeight = Reg->getWeight(RegBank); |
1744 | if (UberSet->Weight > RegWeight) { |
1745 | |
1746 | |
1747 | |
1748 | unsigned AdjustUnit = *Reg->getRegUnits().begin(); |
1749 | if (Reg->getRegUnits().count() != 1 |
1750 | || hasRegUnit(NormalUnits, AdjustUnit) |
1751 | || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) { |
1752 | |
1753 | AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight); |
1754 | Reg->adoptRegUnit(AdjustUnit); |
1755 | |
1756 | } |
1757 | else { |
1758 | |
1759 | if (!RegBank.getRegUnit(AdjustUnit).Artificial) |
1760 | RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight); |
1761 | |
1762 | computeUberWeights(UberSets, RegBank); |
1763 | } |
1764 | Changed = true; |
1765 | } |
1766 | |
1767 | |
1768 | NormalUnits |= Reg->getRegUnits(); |
1769 | |
1770 | return Changed; |
1771 | } |
1772 | |
1773 | |
1774 | |
1775 | |
1776 | |
1777 | void CodeGenRegBank::computeRegUnitWeights() { |
1778 | std::vector<UberRegSet> UberSets; |
1779 | std::vector<UberRegSet*> RegSets(Registers.size()); |
1780 | computeUberSets(UberSets, RegSets, *this); |
1781 | |
1782 | |
1783 | computeUberWeights(UberSets, *this); |
1784 | |
1785 | |
1786 | |
1787 | unsigned NumIters = 0; |
1788 | for (bool Changed = true; Changed; ++NumIters) { |
1789 | assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights"); |
1790 | Changed = false; |
1791 | for (auto &Reg : Registers) { |
1792 | CodeGenRegister::RegUnitList NormalUnits; |
1793 | BitVector NormalRegs; |
1794 | Changed |= normalizeWeight(&Reg, UberSets, RegSets, NormalRegs, |
1795 | NormalUnits, *this); |
1796 | } |
1797 | } |
1798 | } |
1799 | |
1800 | |
1801 | |
1802 | static std::vector<RegUnitSet>::const_iterator |
1803 | findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets, |
1804 | const RegUnitSet &Set) { |
1805 | std::vector<RegUnitSet>::const_iterator |
1806 | I = UniqueSets.begin(), E = UniqueSets.end(); |
1807 | for(;I != E; ++I) { |
1808 | if (I->Units == Set.Units) |
1809 | break; |
1810 | } |
1811 | return I; |
1812 | } |
1813 | |
1814 | |
1815 | static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet, |
1816 | const std::vector<unsigned> &RUSuperSet) { |
1817 | return std::includes(RUSuperSet.begin(), RUSuperSet.end(), |
1818 | RUSubSet.begin(), RUSubSet.end()); |
1819 | } |
1820 | |
1821 | |
1822 | |
1823 | |
1824 | |
1825 | |
1826 | |
1827 | |
1828 | |
1829 | |
1830 | |
1831 | |
1832 | |
1833 | |
1834 | |
1835 | |
1836 | |
1837 | |
1838 | void CodeGenRegBank::pruneUnitSets() { |
1839 | assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets"); |
1840 | |
1841 | |
1842 | std::vector<unsigned> SuperSetIDs; |
1843 | for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); |
1844 | SubIdx != EndIdx; ++SubIdx) { |
1845 | const RegUnitSet &SubSet = RegUnitSets[SubIdx]; |
1846 | unsigned SuperIdx = 0; |
1847 | for (; SuperIdx != EndIdx; ++SuperIdx) { |
1848 | if (SuperIdx == SubIdx) |
1849 | continue; |
1850 | |
1851 | unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight; |
1852 | const RegUnitSet &SuperSet = RegUnitSets[SuperIdx]; |
1853 | if (isRegUnitSubSet(SubSet.Units, SuperSet.Units) |
1854 | && (SubSet.Units.size() + 3 > SuperSet.Units.size()) |
1855 | && UnitWeight == RegUnits[SuperSet.Units[0]].Weight |
1856 | && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) { |
1857 | LLVM_DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx |
1858 | << "\n"); |
1859 | |
1860 | |
1861 | |
1862 | |
1863 | if (RegUnitSets[SubIdx].Name.size() < RegUnitSets[SuperIdx].Name.size()) |
1864 | RegUnitSets[SuperIdx].Name = RegUnitSets[SubIdx].Name; |
1865 | break; |
1866 | } |
1867 | } |
1868 | if (SuperIdx == EndIdx) |
1869 | SuperSetIDs.push_back(SubIdx); |
1870 | } |
1871 | |
1872 | std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size()); |
1873 | for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) { |
1874 | unsigned SuperIdx = SuperSetIDs[i]; |
1875 | PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name; |
1876 | PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units); |
1877 | } |
1878 | RegUnitSets.swap(PrunedUnitSets); |
1879 | } |
1880 | |
1881 | |
1882 | |
1883 | |
1884 | |
1885 | |
1886 | |
1887 | |
1888 | void CodeGenRegBank::computeRegUnitSets() { |
1889 | assert(RegUnitSets.empty() && "dirty RegUnitSets"); |
1890 | |
1891 | |
1892 | auto &RegClasses = getRegClasses(); |
1893 | for (auto &RC : RegClasses) { |
1894 | if (!RC.Allocatable || RC.Artificial || !RC.GeneratePressureSet) |
1895 | continue; |
1896 | |
1897 | |
1898 | RegUnitSets.resize(RegUnitSets.size() + 1); |
1899 | RegUnitSets.back().Name = RC.getName(); |
1900 | |
1901 | |
1902 | RC.buildRegUnitSet(*this, RegUnitSets.back().Units); |
1903 | |
1904 | |
1905 | std::vector<RegUnitSet>::const_iterator SetI = |
1906 | findRegUnitSet(RegUnitSets, RegUnitSets.back()); |
1907 | if (SetI != std::prev(RegUnitSets.end())) |
1908 | RegUnitSets.pop_back(); |
1909 | } |
1910 | |
1911 | LLVM_DEBUG(dbgs() << "\nBefore pruning:\n"; for (unsigned USIdx = 0, |
1912 | USEnd = RegUnitSets.size(); |
1913 | USIdx < USEnd; ++USIdx) { |
1914 | dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":"; |
1915 | for (auto &U : RegUnitSets[USIdx].Units) |
1916 | printRegUnitName(U); |
1917 | dbgs() << "\n"; |
1918 | }); |
1919 | |
1920 | |
1921 | pruneUnitSets(); |
1922 | |
1923 | LLVM_DEBUG(dbgs() << "\nBefore union:\n"; for (unsigned USIdx = 0, |
1924 | USEnd = RegUnitSets.size(); |
1925 | USIdx < USEnd; ++USIdx) { |
1926 | dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":"; |
1927 | for (auto &U : RegUnitSets[USIdx].Units) |
1928 | printRegUnitName(U); |
1929 | dbgs() << "\n"; |
1930 | } dbgs() << "\nUnion sets:\n"); |
1931 | |
1932 | |
1933 | unsigned NumRegUnitSubSets = RegUnitSets.size(); |
1934 | for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { |
1935 | |
1936 | |
1937 | |
1938 | assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference"); |
1939 | |
1940 | |
1941 | for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1; |
1942 | SearchIdx != EndIdx; ++SearchIdx) { |
1943 | std::set<unsigned> Intersection; |
1944 | std::set_intersection(RegUnitSets[Idx].Units.begin(), |
1945 | RegUnitSets[Idx].Units.end(), |
1946 | RegUnitSets[SearchIdx].Units.begin(), |
1947 | RegUnitSets[SearchIdx].Units.end(), |
1948 | std::inserter(Intersection, Intersection.begin())); |
1949 | if (Intersection.empty()) |
1950 | continue; |
1951 | |
1952 | |
1953 | RegUnitSets.resize(RegUnitSets.size() + 1); |
1954 | RegUnitSets.back().Name = |
1955 | RegUnitSets[Idx].Name + "_with_" + RegUnitSets[SearchIdx].Name; |
1956 | |
1957 | std::set_union(RegUnitSets[Idx].Units.begin(), |
1958 | RegUnitSets[Idx].Units.end(), |
1959 | RegUnitSets[SearchIdx].Units.begin(), |
1960 | RegUnitSets[SearchIdx].Units.end(), |
1961 | std::inserter(RegUnitSets.back().Units, |
1962 | RegUnitSets.back().Units.begin())); |
1963 | |
1964 | |
1965 | std::vector<RegUnitSet>::const_iterator SetI = |
1966 | findRegUnitSet(RegUnitSets, RegUnitSets.back()); |
1967 | if (SetI != std::prev(RegUnitSets.end())) |
1968 | RegUnitSets.pop_back(); |
1969 | else { |
1970 | LLVM_DEBUG(dbgs() << "UnitSet " << RegUnitSets.size() - 1 << " " |
1971 | << RegUnitSets.back().Name << ":"; |
1972 | for (auto &U |
1973 | : RegUnitSets.back().Units) printRegUnitName(U); |
1974 | dbgs() << "\n";); |
1975 | } |
1976 | } |
1977 | } |
1978 | |
1979 | |
1980 | pruneUnitSets(); |
1981 | |
1982 | LLVM_DEBUG( |
1983 | dbgs() << "\n"; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); |
1984 | USIdx < USEnd; ++USIdx) { |
1985 | dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":"; |
1986 | for (auto &U : RegUnitSets[USIdx].Units) |
1987 | printRegUnitName(U); |
1988 | dbgs() << "\n"; |
1989 | }); |
1990 | |
1991 | |
1992 | RegClassUnitSets.resize(RegClasses.size()); |
1993 | int RCIdx = -1; |
1994 | for (auto &RC : RegClasses) { |
1995 | ++RCIdx; |
1996 | if (!RC.Allocatable) |
1997 | continue; |
1998 | |
1999 | |
2000 | std::vector<unsigned> RCRegUnits; |
2001 | RC.buildRegUnitSet(*this, RCRegUnits); |
2002 | |
2003 | |
2004 | if (RCRegUnits.empty()) |
2005 | continue; |
2006 | |
2007 | LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units:\n"; |
2008 | for (auto U |
2009 | : RCRegUnits) printRegUnitName(U); |
2010 | dbgs() << "\n UnitSetIDs:"); |
2011 | |
2012 | |
2013 | for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); |
2014 | USIdx != USEnd; ++USIdx) { |
2015 | if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) { |
2016 | LLVM_DEBUG(dbgs() << " " << USIdx); |
2017 | RegClassUnitSets[RCIdx].push_back(USIdx); |
2018 | } |
2019 | } |
2020 | LLVM_DEBUG(dbgs() << "\n"); |
2021 | assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass"); |
2022 | } |
2023 | |
2024 | |
2025 | |
2026 | |
2027 | |
2028 | for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits; |
2029 | UnitIdx < UnitEnd; ++UnitIdx) { |
2030 | std::vector<unsigned> RUSets; |
2031 | for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) { |
2032 | RegUnitSet &RUSet = RegUnitSets[i]; |
2033 | if (!is_contained(RUSet.Units, UnitIdx)) |
2034 | continue; |
2035 | RUSets.push_back(i); |
2036 | } |
2037 | unsigned RCUnitSetsIdx = 0; |
2038 | for (unsigned e = RegClassUnitSets.size(); |
2039 | RCUnitSetsIdx != e; ++RCUnitSetsIdx) { |
2040 | if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) { |
2041 | break; |
2042 | } |
2043 | } |
2044 | RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx; |
2045 | if (RCUnitSetsIdx == RegClassUnitSets.size()) { |
2046 | |
2047 | RegClassUnitSets.resize(RCUnitSetsIdx + 1); |
2048 | RegClassUnitSets[RCUnitSetsIdx].swap(RUSets); |
2049 | } |
2050 | } |
2051 | } |
2052 | |
2053 | void CodeGenRegBank::computeRegUnitLaneMasks() { |
2054 | for (auto &Register : Registers) { |
2055 | |
2056 | const auto &RegUnits = Register.getRegUnits(); |
2057 | CodeGenRegister::RegUnitLaneMaskList |
2058 | RegUnitLaneMasks(RegUnits.count(), LaneBitmask::getNone()); |
2059 | |
2060 | typedef CodeGenRegister::SubRegMap SubRegMap; |
2061 | const SubRegMap &SubRegs = Register.getSubRegs(); |
2062 | for (auto S : SubRegs) { |
2063 | CodeGenRegister *SubReg = S.second; |
2064 | |
2065 | |
2066 | if (!SubReg->getSubRegs().empty()) |
2067 | continue; |
2068 | CodeGenSubRegIndex *SubRegIndex = S.first; |
2069 | const CodeGenRegister *SubRegister = S.second; |
2070 | LaneBitmask LaneMask = SubRegIndex->LaneMask; |
2071 | |
2072 | for (unsigned SUI : SubRegister->getRegUnits()) { |
2073 | bool Found = false; |
2074 | unsigned u = 0; |
2075 | for (unsigned RU : RegUnits) { |
2076 | if (SUI == RU) { |
2077 | RegUnitLaneMasks[u] |= LaneMask; |
2078 | assert(!Found); |
2079 | Found = true; |
2080 | } |
2081 | ++u; |
2082 | } |
2083 | (void)Found; |
2084 | assert(Found); |
2085 | } |
2086 | } |
2087 | Register.setRegUnitLaneMasks(RegUnitLaneMasks); |
2088 | } |
2089 | } |
2090 | |
2091 | void CodeGenRegBank::computeDerivedInfo() { |
2092 | computeComposites(); |
2093 | computeSubRegLaneMasks(); |
2094 | |
2095 | |
2096 | |
2097 | computeRegUnitWeights(); |
2098 | |
2099 | |
2100 | |
2101 | computeRegUnitSets(); |
2102 | |
2103 | computeRegUnitLaneMasks(); |
2104 | |
2105 | |
2106 | for (CodeGenRegisterClass &RC : RegClasses) { |
2107 | RC.HasDisjunctSubRegs = false; |
2108 | RC.CoveredBySubRegs = true; |
2109 | for (const CodeGenRegister *Reg : RC.getMembers()) { |
2110 | RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; |
2111 | RC.CoveredBySubRegs &= Reg->CoveredBySubRegs; |
2112 | } |
2113 | } |
2114 | |
2115 | |
2116 | for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) |
2117 | RegUnitSets[Idx].Weight = getRegUnitSetWeight(RegUnitSets[Idx].Units); |
2118 | |
2119 | |
2120 | RegUnitSetOrder.reserve(RegUnitSets.size()); |
2121 | for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) |
2122 | RegUnitSetOrder.push_back(Idx); |
2123 | |
2124 | llvm::stable_sort(RegUnitSetOrder, [this](unsigned ID1, unsigned ID2) { |
2125 | return getRegPressureSet(ID1).Units.size() < |
2126 | getRegPressureSet(ID2).Units.size(); |
2127 | }); |
2128 | for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { |
2129 | RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx; |
2130 | } |
2131 | } |
2132 | |
2133 | |
2134 | |
2135 | |
2136 | |
2137 | |
2138 | |
2139 | void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) { |
2140 | assert(!RegClasses.empty()); |
2141 | |
2142 | |
2143 | for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end()); |
2144 | I != std::next(E); ++I) { |
2145 | CodeGenRegisterClass *RC1 = RC; |
2146 | CodeGenRegisterClass *RC2 = &*I; |
2147 | if (RC1 == RC2) |
2148 | continue; |
2149 | |
2150 | |
2151 | const CodeGenRegister::Vec &Memb1 = RC1->getMembers(); |
2152 | const CodeGenRegister::Vec &Memb2 = RC2->getMembers(); |
2153 | CodeGenRegister::Vec Intersection; |
2154 | std::set_intersection(Memb1.begin(), Memb1.end(), Memb2.begin(), |
2155 | Memb2.end(), |
2156 | std::inserter(Intersection, Intersection.begin()), |
2157 | deref<std::less<>>()); |
2158 | |
2159 | |
2160 | if (Intersection.empty()) |
2161 | continue; |
2162 | |
2163 | |
2164 | |
2165 | if (RC2->RSI.hasStricterSpillThan(RC1->RSI)) |
2166 | std::swap(RC1, RC2); |
2167 | |
2168 | getOrCreateSubClass(RC1, &Intersection, |
2169 | RC1->getName() + "_and_" + RC2->getName()); |
2170 | } |
2171 | } |
2172 | |
2173 | |
2174 | |
2175 | |
2176 | |
2177 | |
2178 | |
2179 | void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { |
2180 | |
2181 | typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec, |
2182 | deref<std::less<>>> |
2183 | SubReg2SetMap; |
2184 | |
2185 | |
2186 | SubReg2SetMap SRSets; |
2187 | for (const auto R : RC->getMembers()) { |
2188 | if (R->Artificial) |
2189 | continue; |
2190 | const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); |
2191 | for (auto I : SRM) { |
2192 | if (!I.first->Artificial) |
2193 | SRSets[I.first].push_back(R); |
2194 | } |
2195 | } |
2196 | |
2197 | for (auto I : SRSets) |
2198 | sortAndUniqueRegisters(I.second); |
2199 | |
2200 | |
2201 | |
2202 | for (const auto &SubIdx : SubRegIndices) { |
2203 | if (SubIdx.Artificial) |
2204 | continue; |
2205 | SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx); |
2206 | |
2207 | if (I == SRSets.end()) |
2208 | continue; |
2209 | |
2210 | if (I->second.size() == RC->getMembers().size()) { |
2211 | RC->setSubClassWithSubReg(&SubIdx, RC); |
2212 | continue; |
2213 | } |
2214 | |
2215 | CodeGenRegisterClass *SubRC = |
2216 | getOrCreateSubClass(RC, &I->second, |
2217 | RC->getName() + "_with_" + I->first->getName()); |
2218 | RC->setSubClassWithSubReg(&SubIdx, SubRC); |
2219 | } |
2220 | } |
2221 | |
2222 | |
2223 | |
2224 | |
2225 | |
2226 | |
2227 | |
2228 | |
2229 | void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC, |
2230 | std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) { |
2231 | SmallVector<std::pair<const CodeGenRegister*, |
2232 | const CodeGenRegister*>, 16> SSPairs; |
2233 | BitVector TopoSigs(getNumTopoSigs()); |
2234 | |
2235 | |
2236 | for (auto &SubIdx : SubRegIndices) { |
2237 | |
2238 | |
2239 | |
2240 | if (RC->getSubClassWithSubReg(&SubIdx) != RC) |
2241 | continue; |
2242 | |
2243 | |
2244 | SSPairs.clear(); |
2245 | TopoSigs.reset(); |
2246 | for (const auto Super : RC->getMembers()) { |
2247 | const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second; |
2248 | assert(Sub && "Missing sub-register"); |
2249 | SSPairs.push_back(std::make_pair(Super, Sub)); |
2250 | TopoSigs.set(Sub->getTopoSig()); |
2251 | } |
2252 | |
2253 | |
2254 | |
2255 | |
2256 | |
2257 | assert(!RegClasses.empty()); |
2258 | for (auto I = FirstSubRegRC, E = std::prev(RegClasses.end()); |
2259 | I != std::next(E); ++I) { |
2260 | CodeGenRegisterClass &SubRC = *I; |
2261 | if (SubRC.Artificial) |
2262 | continue; |
2263 | |
2264 | if (!TopoSigs.anyCommon(SubRC.getTopoSigs())) |
2265 | continue; |
2266 | |
2267 | CodeGenRegister::Vec SubSetVec; |
2268 | for (unsigned i = 0, e = SSPairs.size(); i != e; ++i) |
2269 | if (SubRC.contains(SSPairs[i].second)) |
2270 | SubSetVec.push_back(SSPairs[i].first); |
2271 | |
2272 | if (SubSetVec.empty()) |
2273 | continue; |
2274 | |
2275 | |
2276 | sortAndUniqueRegisters(SubSetVec); |
2277 | if (SubSetVec.size() == SSPairs.size()) { |
2278 | SubRC.addSuperRegClass(&SubIdx, RC); |
2279 | continue; |
2280 | } |
2281 | |
2282 | |
2283 | |
2284 | getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" + |
2285 | SubIdx.getName() + "_in_" + |
2286 | SubRC.getName()); |
2287 | } |
2288 | } |
2289 | } |
2290 | |
2291 | |
2292 | |
2293 | |
2294 | void CodeGenRegBank::computeInferredRegisterClasses() { |
2295 | assert(!RegClasses.empty()); |
2296 | |
2297 | |
2298 | |
2299 | |
2300 | |
2301 | |
2302 | auto FirstNewRC = std::prev(RegClasses.end()); |
2303 | |
2304 | |
2305 | |
2306 | for (auto I = RegClasses.begin(), E = RegClasses.end(); I != E; ++I) { |
2307 | CodeGenRegisterClass *RC = &*I; |
2308 | if (RC->Artificial) |
2309 | continue; |
2310 | |
2311 | |
2312 | inferSubClassWithSubReg(RC); |
2313 | |
2314 | |
2315 | inferCommonSubClass(RC); |
2316 | |
2317 | |
2318 | inferMatchingSuperRegClass(RC); |
2319 | |
2320 | |
2321 | |
2322 | |
2323 | |
2324 | |
2325 | |
2326 | if (I == FirstNewRC) { |
2327 | auto NextNewRC = std::prev(RegClasses.end()); |
2328 | for (auto I2 = RegClasses.begin(), E2 = std::next(FirstNewRC); I2 != E2; |
2329 | ++I2) |
2330 | inferMatchingSuperRegClass(&*I2, E2); |
2331 | FirstNewRC = NextNewRC; |
2332 | } |
2333 | } |
2334 | } |
2335 | |
2336 | |
2337 | |
2338 | |
2339 | |
2340 | |
2341 | const CodeGenRegisterClass* |
2342 | CodeGenRegBank::getRegClassForRegister(Record *R) { |
2343 | const CodeGenRegister *Reg = getReg(R); |
2344 | const CodeGenRegisterClass *FoundRC = nullptr; |
2345 | for (const auto &RC : getRegClasses()) { |
2346 | if (!RC.contains(Reg)) |
2347 | continue; |
2348 | |
2349 | |
2350 | |
2351 | if (!FoundRC) { |
2352 | FoundRC = &RC; |
2353 | continue; |
2354 | } |
2355 | |
2356 | |
2357 | if (RC.getValueTypes() != FoundRC->getValueTypes()) |
2358 | return nullptr; |
2359 | |
2360 | |
2361 | |
2362 | |
2363 | if (RC.hasSubClass(FoundRC)) { |
2364 | FoundRC = &RC; |
2365 | continue; |
2366 | } |
2367 | |
2368 | |
2369 | |
2370 | |
2371 | if (FoundRC->hasSubClass(&RC)) |
2372 | continue; |
2373 | |
2374 | |
2375 | |
2376 | return nullptr; |
2377 | } |
2378 | return FoundRC; |
2379 | } |
2380 | |
2381 | const CodeGenRegisterClass * |
2382 | CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord, |
2383 | ValueTypeByHwMode *VT) { |
2384 | const CodeGenRegister *Reg = getReg(RegRecord); |
2385 | const CodeGenRegisterClass *BestRC = nullptr; |
2386 | for (const auto &RC : getRegClasses()) { |
2387 | if ((!VT || RC.hasType(*VT)) && |
2388 | RC.contains(Reg) && (!BestRC || BestRC->hasSubClass(&RC))) |
2389 | BestRC = &RC; |
2390 | } |
2391 | |
2392 | assert(BestRC && "Couldn't find the register class"); |
2393 | return BestRC; |
2394 | } |
2395 | |
2396 | BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { |
2397 | SetVector<const CodeGenRegister*> Set; |
2398 | |
2399 | |
2400 | for (unsigned i = 0, e = Regs.size(); i != e; ++i) { |
2401 | CodeGenRegister *Reg = getReg(Regs[i]); |
2402 | if (Set.insert(Reg)) |
2403 | |
2404 | |
2405 | Reg->addSubRegsPreOrder(Set, *this); |
2406 | } |
2407 | |
2408 | |
2409 | for (unsigned i = 0; i != Set.size(); ++i) { |
2410 | const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs(); |
2411 | for (unsigned j = 0, e = SR.size(); j != e; ++j) { |
2412 | const CodeGenRegister *Super = SR[j]; |
2413 | if (!Super->CoveredBySubRegs || Set.count(Super)) |
2414 | continue; |
2415 | |
2416 | bool AllSubsInSet = true; |
2417 | const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); |
2418 | for (auto I : SRM) |
2419 | if (!Set.count(I.second)) { |
2420 | AllSubsInSet = false; |
2421 | break; |
2422 | } |
2423 | |
2424 | |
2425 | if (AllSubsInSet) |
2426 | Set.insert(Super); |
2427 | } |
2428 | } |
2429 | |
2430 | |
2431 | BitVector BV(Registers.size() + 1); |
2432 | for (unsigned i = 0, e = Set.size(); i != e; ++i) |
2433 | BV.set(Set[i]->EnumValue); |
2434 | return BV; |
2435 | } |
2436 | |
2437 | void CodeGenRegBank::printRegUnitName(unsigned Unit) const { |
2438 | if (Unit < NumNativeRegUnits) |
2439 | dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName(); |
2440 | else |
2441 | dbgs() << " #" << Unit; |
2442 | } |