/usr/src/gnu/usr.bin/clang/libclangCodeGen/../../../llvm/clang/lib/CodeGen/TargetInfo.cpp

Bug Summary

File:	src/gnu/usr.bin/clang/libclangCodeGen/../../../llvm/clang/lib/CodeGen/TargetInfo.cpp
Warning:	line 3808, column 7 Called C++ object pointer is null
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name TargetInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/gnu/usr.bin/clang/libclangCodeGen/obj -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/gnu/usr.bin/clang/libclangCodeGen/../../../llvm/clang/include -I /usr/src/gnu/usr.bin/clang/libclangCodeGen/../../../llvm/llvm/include -I /usr/src/gnu/usr.bin/clang/libclangCodeGen/../include -I /usr/src/gnu/usr.bin/clang/libclangCodeGen/obj -I /usr/src/gnu/usr.bin/clang/libclangCodeGen/obj/../include -D NDEBUG -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D LLVM_PREFIX="/usr" -internal-isystem /usr/include/c++/v1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/usr/src/gnu/usr.bin/clang/libclangCodeGen/obj -ferror-limit 19 -fvisibility-inlines-hidden -fwrapv -stack-protector 2 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c++ /usr/src/gnu/usr.bin/clang/libclangCodeGen/../../../llvm/clang/lib/CodeGen/TargetInfo.cpp
1//===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// These classes wrap the information about a call or function
10// definition used to handle ABI compliancy.
11//
12//===----------------------------------------------------------------------===//

14#include "TargetInfo.h"
15#include "ABIInfo.h"
16#include "CGBlocks.h"
17#include "CGCXXABI.h"
18#include "CGValue.h"
19#include "CodeGenFunction.h"
20#include "clang/AST/Attr.h"
21#include "clang/AST/RecordLayout.h"
22#include "clang/Basic/CodeGenOptions.h"
23#include "clang/Basic/DiagnosticFrontend.h"
24#include "clang/Basic/Builtins.h"
25#include "clang/CodeGen/CGFunctionInfo.h"
26#include "clang/CodeGen/SwiftCallingConv.h"
27#include "llvm/ADT/SmallBitVector.h"
28#include "llvm/ADT/StringExtras.h"
29#include "llvm/ADT/StringSwitch.h"
30#include "llvm/ADT/Triple.h"
31#include "llvm/ADT/Twine.h"
32#include "llvm/IR/DataLayout.h"
33#include "llvm/IR/IntrinsicsNVPTX.h"
34#include "llvm/IR/IntrinsicsS390.h"
35#include "llvm/IR/Type.h"
36#include "llvm/Support/raw_ostream.h"
37#include <algorithm> // std::sort

39using namespace clang;
40using namespace CodeGen;

42// Helper for coercing an aggregate argument or return value into an integer
43// array of the same size (including padding) and alignment.  This alternate
44// coercion happens only for the RenderScript ABI and can be removed after
45// runtimes that rely on it are no longer supported.
46//
47// RenderScript assumes that the size of the argument / return value in the IR
48// is the same as the size of the corresponding qualified type. This helper
49// coerces the aggregate type into an array of the same size (including
50// padding).  This coercion is used in lieu of expansion of struct members or
51// other canonical coercions that return a coerced-type of larger size.
52//
53// Ty          - The argument / return value type
54// Context     - The associated ASTContext
55// LLVMContext - The associated LLVMContext
56static ABIArgInfo coerceToIntArray(QualType Ty,
                                 ASTContext &Context,
                                 llvm::LLVMContext &LLVMContext) {
// Alignment and Size are measured in bits.
const uint64_t Size = Context.getTypeSize(Ty);
const uint64_t Alignment = Context.getTypeAlign(Ty);
llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
65}

67static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder,
                             llvm::Value *Array,
                             llvm::Value *Value,
                             unsigned FirstIndex,
                             unsigned LastIndex) {
// Alternatively, we could emit this as a loop in the source.
for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
  llvm::Value *Cell =
      Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
  Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
}
78}

80static bool isAggregateTypeForABI(QualType T) {
return !CodeGenFunction::hasScalarEvaluationKind(T) ||
       T->isMemberFunctionPointerType();
83}

85ABIArgInfo ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByVal,
                                          bool Realign,
                                          llvm::Type *Padding) const {
return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty), ByVal,
                               Realign, Padding);
90}

92ABIArgInfo
93ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const {
return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
                                    /*ByVal*/ false, Realign);
96}

98Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
                           QualType Ty) const {
return Address::invalid();
101}

103bool ABIInfo::isPromotableIntegerTypeForABI(QualType Ty) const {
if (Ty->isPromotableIntegerType())
  return true;

if (const auto *EIT = Ty->getAs<ExtIntType>())
  if (EIT->getNumBits() < getContext().getTypeSize(getContext().IntTy))
    return true;

return false;
112}

114ABIInfo::~ABIInfo() {}

116/// Does the given lowering require more than the given number of
117/// registers when expanded?
118///
119/// This is intended to be the basis of a reasonable basic implementation
120/// of should{Pass,Return}IndirectlyForSwift.
121///
122/// For most targets, a limit of four total registers is reasonable; this
123/// limits the amount of code required in order to move around the value
124/// in case it wasn't produced immediately prior to the call by the caller
125/// (or wasn't produced in exactly the right registers) or isn't used
126/// immediately within the callee.  But some targets may need to further
127/// limit the register count due to an inability to support that many
128/// return registers.
129static bool occupiesMoreThan(CodeGenTypes &cgt,
                           ArrayRef<llvm::Type*> scalarTypes,
                           unsigned maxAllRegisters) {
unsigned intCount = 0, fpCount = 0;
for (llvm::Type *type : scalarTypes) {
  if (type->isPointerTy()) {
    intCount++;
  } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
    auto ptrWidth = cgt.getTarget().getPointerWidth(0);
    intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
  } else {
    assert(type->isVectorTy() || type->isFloatingPointTy())((void)0);
    fpCount++;
  }
}

return (intCount + fpCount > maxAllRegisters);
146}

148bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
                                           llvm::Type *eltTy,
                                           unsigned numElts) const {
// The default implementation of this assumes that the target guarantees
// 128-bit SIMD support but nothing more.
return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
154}

156static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT,
                                            CGCXXABI &CXXABI) {
const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
if (!RD) {
  if (!RT->getDecl()->canPassInRegisters())
    return CGCXXABI::RAA_Indirect;
  return CGCXXABI::RAA_Default;
}
return CXXABI.getRecordArgABI(RD);
165}

167static CGCXXABI::RecordArgABI getRecordArgABI(QualType T,
                                            CGCXXABI &CXXABI) {
const RecordType *RT = T->getAs<RecordType>();
if (!RT)
  return CGCXXABI::RAA_Default;
return getRecordArgABI(RT, CXXABI);
173}

175static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
                             const ABIInfo &Info) {
QualType Ty = FI.getReturnType();

if (const auto *RT = Ty->getAs<RecordType>())
  if (!isa<CXXRecordDecl>(RT->getDecl()) &&
      !RT->getDecl()->canPassInRegisters()) {
    FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
    return true;
  }

return CXXABI.classifyReturnType(FI);
187}

189/// Pass transparent unions as if they were the type of the first element. Sema
190/// should ensure that all elements of the union have the same "machine type".
191static QualType useFirstFieldIfTransparentUnion(QualType Ty) {
if (const RecordType *UT = Ty->getAsUnionType()) {
  const RecordDecl *UD = UT->getDecl();
  if (UD->hasAttr<TransparentUnionAttr>()) {
    assert(!UD->field_empty() && "sema created an empty transparent union")((void)0);
    return UD->field_begin()->getType();
  }
}
return Ty;
200}

202CGCXXABI &ABIInfo::getCXXABI() const {
return CGT.getCXXABI();
204}

206ASTContext &ABIInfo::getContext() const {
return CGT.getContext();
208}

210llvm::LLVMContext &ABIInfo::getVMContext() const {
return CGT.getLLVMContext();
212}

214const llvm::DataLayout &ABIInfo::getDataLayout() const {
return CGT.getDataLayout();
216}

218const TargetInfo &ABIInfo::getTarget() const {
return CGT.getTarget();
220}

222const CodeGenOptions &ABIInfo::getCodeGenOpts() const {
return CGT.getCodeGenOpts();
224}

226bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }

228bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
return false;
230}

232bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
                                              uint64_t Members) const {
return false;
235}

237LLVM_DUMP_METHOD__attribute__((noinline)) void ABIArgInfo::dump() const {
raw_ostream &OS = llvm::errs();
OS << "(ABIArgInfo Kind=";
switch (TheKind) {
case Direct:
  OS << "Direct Type=";
  if (llvm::Type *Ty = getCoerceToType())
    Ty->print(OS);
  else
    OS << "null";
  break;
case Extend:
  OS << "Extend";
  break;
case Ignore:
  OS << "Ignore";
  break;
case InAlloca:
  OS << "InAlloca Offset=" << getInAllocaFieldIndex();
  break;
case Indirect:
  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
     << " ByVal=" << getIndirectByVal()
     << " Realign=" << getIndirectRealign();
  break;
case IndirectAliased:
  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
     << " AadrSpace=" << getIndirectAddrSpace()
     << " Realign=" << getIndirectRealign();
  break;
case Expand:
  OS << "Expand";
  break;
case CoerceAndExpand:
  OS << "CoerceAndExpand Type=";
  getCoerceAndExpandType()->print(OS);
  break;
}
OS << ")\n";
276}

278// Dynamically round a pointer up to a multiple of the given alignment.
279static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF,
                                                llvm::Value *Ptr,
                                                CharUnits Align) {
llvm::Value *PtrAsInt = Ptr;
// OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
      llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
         llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
                                      Ptr->getType(),
                                      Ptr->getName() + ".aligned");
return PtrAsInt;
293}

295/// Emit va_arg for a platform using the common void* representation,
296/// where arguments are simply emitted in an array of slots on the stack.
297///
298/// This version implements the core direct-value passing rules.
299///
300/// \param SlotSize - The size and alignment of a stack slot.
301///   Each argument will be allocated to a multiple of this number of
302///   slots, and all the slots will be aligned to this value.
303/// \param AllowHigherAlign - The slot alignment is not a cap;
304///   an argument type with an alignment greater than the slot size
305///   will be emitted on a higher-alignment address, potentially
306///   leaving one or more empty slots behind as padding.  If this
307///   is false, the returned address might be less-aligned than
308///   DirectAlign.
309static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF,
                                    Address VAListAddr,
                                    llvm::Type *DirectTy,
                                    CharUnits DirectSize,
                                    CharUnits DirectAlign,
                                    CharUnits SlotSize,
                                    bool AllowHigherAlign) {
// Cast the element type to i8* if necessary.  Some platforms define
// va_list as a struct containing an i8* instead of just an i8*.
if (VAListAddr.getElementType() != CGF.Int8PtrTy)
  VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);

llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");

// If the CC aligns values higher than the slot size, do so if needed.
Address Addr = Address::invalid();
if (AllowHigherAlign && DirectAlign > SlotSize) {
  Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
                                               DirectAlign);
} else {
  Addr = Address(Ptr, SlotSize);
}

// Advance the pointer past the argument, then store that back.
CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
Address NextPtr =
    CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next");
CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr);

// If the argument is smaller than a slot, and this is a big-endian
// target, the argument will be right-adjusted in its slot.
if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
    !DirectTy->isStructTy()) {
  Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
}

Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
return Addr;
347}

349/// Emit va_arg for a platform using the common void* representation,
350/// where arguments are simply emitted in an array of slots on the stack.
351///
352/// \param IsIndirect - Values of this type are passed indirectly.
353/// \param ValueInfo - The size and alignment of this type, generally
354///   computed with getContext().getTypeInfoInChars(ValueTy).
355/// \param SlotSizeAndAlign - The size and alignment of a stack slot.
356///   Each argument will be allocated to a multiple of this number of
357///   slots, and all the slots will be aligned to this value.
358/// \param AllowHigherAlign - The slot alignment is not a cap;
359///   an argument type with an alignment greater than the slot size
360///   will be emitted on a higher-alignment address, potentially
361///   leaving one or more empty slots behind as padding.
362static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr,
                              QualType ValueTy, bool IsIndirect,
                              TypeInfoChars ValueInfo,
                              CharUnits SlotSizeAndAlign,
                              bool AllowHigherAlign) {
// The size and alignment of the value that was passed directly.
CharUnits DirectSize, DirectAlign;
if (IsIndirect) {
  DirectSize = CGF.getPointerSize();
  DirectAlign = CGF.getPointerAlign();
} else {
  DirectSize = ValueInfo.Width;
  DirectAlign = ValueInfo.Align;
}

// Cast the address we've calculated to the right type.
llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
if (IsIndirect)
  DirectTy = DirectTy->getPointerTo(0);

Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
                                      DirectSize, DirectAlign,
                                      SlotSizeAndAlign,
                                      AllowHigherAlign);

if (IsIndirect) {
  Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.Align);
}

return Addr;

393}

395static Address emitMergePHI(CodeGenFunction &CGF,
                          Address Addr1, llvm::BasicBlock *Block1,
                          Address Addr2, llvm::BasicBlock *Block2,
                          const llvm::Twine &Name = "") {
assert(Addr1.getType() == Addr2.getType())((void)0);
llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
PHI->addIncoming(Addr1.getPointer(), Block1);
PHI->addIncoming(Addr2.getPointer(), Block2);
CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
return Address(PHI, Align);
405}

407TargetCodeGenInfo::~TargetCodeGenInfo() = default;

409// If someone can figure out a general rule for this, that would be great.
410// It's probably just doomed to be platform-dependent, though.
411unsigned TargetCodeGenInfo::getSizeOfUnwindException() const {
// Verified for:
//   x86-64     FreeBSD, Linux, Darwin
//   x86-32     FreeBSD, Linux, Darwin
//   PowerPC    Linux, Darwin
//   ARM        Darwin (*not* EABI)
//   AArch64    Linux
return 32;
419}

421bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args,
                                   const FunctionNoProtoType *fnType) const {
// The following conventions are known to require this to be false:
//   x86_stdcall
//   MIPS
// For everything else, we just prefer false unless we opt out.
return false;
428}

430void
431TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib,
                                           llvm::SmallString<24> &Opt) const {
// This assumes the user is passing a library name like "rt" instead of a
// filename like "librt.a/so", and that they don't care whether it's static or
// dynamic.
Opt = "-l";
Opt += Lib;
438}

440unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const {
// OpenCL kernels are called via an explicit runtime API with arguments
// set with clSetKernelArg(), not as normal sub-functions.
// Return SPIR_KERNEL by default as the kernel calling convention to
// ensure the fingerprint is fixed such way that each OpenCL argument
// gets one matching argument in the produced kernel function argument
// list to enable feasible implementation of clSetKernelArg() with
// aggregates etc. In case we would use the default C calling conv here,
// clSetKernelArg() might break depending on the target-specific
// conventions; different targets might split structs passed as values
// to multiple function arguments etc.
return llvm::CallingConv::SPIR_KERNEL;
452}

454llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
  llvm::PointerType *T, QualType QT) const {
return llvm::ConstantPointerNull::get(T);
457}

459LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
                                                 const VarDecl *D) const {
assert(!CGM.getLangOpts().OpenCL &&((void)0)
       !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&((void)0)
       "Address space agnostic languages only")((void)0);
return D ? D->getType().getAddressSpace() : LangAS::Default;
465}

467llvm::Value *TargetCodeGenInfo::performAddrSpaceCast(
  CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
  LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
// Since target may map different address spaces in AST to the same address
// space, an address space conversion may end up as a bitcast.
if (auto *C = dyn_cast<llvm::Constant>(Src))
  return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
// Try to preserve the source's name to make IR more readable.
return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(
    Src, DestTy, Src->hasName() ? Src->getName() + ".ascast" : "");
477}

479llvm::Constant *
480TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src,
                                      LangAS SrcAddr, LangAS DestAddr,
                                      llvm::Type *DestTy) const {
// Since target may map different address spaces in AST to the same address
// space, an address space conversion may end up as a bitcast.
return llvm::ConstantExpr::getPointerCast(Src, DestTy);
486}

488llvm::SyncScope::ID
489TargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts,
                                    SyncScope Scope,
                                    llvm::AtomicOrdering Ordering,
                                    llvm::LLVMContext &Ctx) const {
return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */
494}

496static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);

498/// isEmptyField - Return true iff a the field is "empty", that is it
499/// is an unnamed bit-field or an (array of) empty record(s).
500static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
                       bool AllowArrays) {
if (FD->isUnnamedBitfield())
  return true;

QualType FT = FD->getType();

// Constant arrays of empty records count as empty, strip them off.
// Constant arrays of zero length always count as empty.
bool WasArray = false;
if (AllowArrays)
  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
    if (AT->getSize() == 0)
      return true;
    FT = AT->getElementType();
    // The [[no_unique_address]] special case below does not apply to
    // arrays of C++ empty records, so we need to remember this fact.
    WasArray = true;
  }

const RecordType *RT = FT->getAs<RecordType>();
if (!RT)
  return false;

// C++ record fields are never empty, at least in the Itanium ABI.
//
// FIXME: We should use a predicate for whether this behavior is true in the
// current ABI.
//
// The exception to the above rule are fields marked with the
// [[no_unique_address]] attribute (since C++20).  Those do count as empty
// according to the Itanium ABI.  The exception applies only to records,
// not arrays of records, so we must also check whether we stripped off an
// array type above.
if (isa<CXXRecordDecl>(RT->getDecl()) &&
    (WasArray || !FD->hasAttr<NoUniqueAddressAttr>()))
  return false;

return isEmptyRecord(Context, FT, AllowArrays);
539}

541/// isEmptyRecord - Return true iff a structure contains only empty
542/// fields. Note that a structure with a flexible array member is not
543/// considered empty.
544static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
const RecordType *RT = T->getAs<RecordType>();
if (!RT)
  return false;
const RecordDecl *RD = RT->getDecl();
if (RD->hasFlexibleArrayMember())
  return false;

// If this is a C++ record, check the bases first.
if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
  for (const auto &I : CXXRD->bases())
    if (!isEmptyRecord(Context, I.getType(), true))
      return false;

for (const auto *I : RD->fields())
  if (!isEmptyField(Context, I, AllowArrays))
    return false;
return true;
562}

564/// isSingleElementStruct - Determine if a structure is a "single
565/// element struct", i.e. it has exactly one non-empty field or
566/// exactly one field which is itself a single element
567/// struct. Structures with flexible array members are never
568/// considered single element structs.
569///
570/// \return The field declaration for the single non-empty field, if
571/// it exists.
572static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
const RecordType *RT = T->getAs<RecordType>();
if (!RT)
  return nullptr;

const RecordDecl *RD = RT->getDecl();
if (RD->hasFlexibleArrayMember())
  return nullptr;

const Type *Found = nullptr;

// If this is a C++ record, check the bases first.
if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
  for (const auto &I : CXXRD->bases()) {
    // Ignore empty records.
    if (isEmptyRecord(Context, I.getType(), true))
      continue;

    // If we already found an element then this isn't a single-element struct.
    if (Found)
      return nullptr;

    // If this is non-empty and not a single element struct, the composite
    // cannot be a single element struct.
    Found = isSingleElementStruct(I.getType(), Context);
    if (!Found)
      return nullptr;
  }
}

// Check for single element.
for (const auto *FD : RD->fields()) {
  QualType FT = FD->getType();

  // Ignore empty fields.
  if (isEmptyField(Context, FD, true))
    continue;

  // If we already found an element then this isn't a single-element
  // struct.
  if (Found)
    return nullptr;

  // Treat single element arrays as the element.
  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
    if (AT->getSize().getZExtValue() != 1)
      break;
    FT = AT->getElementType();
  }

  if (!isAggregateTypeForABI(FT)) {
    Found = FT.getTypePtr();
  } else {
    Found = isSingleElementStruct(FT, Context);
    if (!Found)
      return nullptr;
  }
}

// We don't consider a struct a single-element struct if it has
// padding beyond the element type.
if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
  return nullptr;

return Found;
637}

639namespace {
640Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
                     const ABIArgInfo &AI) {
// This default implementation defers to the llvm backend's va_arg
// instruction. It can handle only passing arguments directly
// (typically only handled in the backend for primitive types), or
// aggregates passed indirectly by pointer (NOTE: if the "byval"
// flag has ABI impact in the callee, this implementation cannot
// work.)

// Only a few cases are covered here at the moment -- those needed
// by the default abi.
llvm::Value *Val;

if (AI.isIndirect()) {
  assert(!AI.getPaddingType() &&((void)0)
         "Unexpected PaddingType seen in arginfo in generic VAArg emitter!")((void)0);
  assert(((void)0)
      !AI.getIndirectRealign() &&((void)0)
      "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!")((void)0);

  auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
  CharUnits TyAlignForABI = TyInfo.Align;

  llvm::Type *BaseTy =
      llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
  llvm::Value *Addr =
      CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
  return Address(Addr, TyAlignForABI);
} else {
  assert((AI.isDirect() || AI.isExtend()) &&((void)0)
         "Unexpected ArgInfo Kind in generic VAArg emitter!")((void)0);

  assert(!AI.getInReg() &&((void)0)
         "Unexpected InReg seen in arginfo in generic VAArg emitter!")((void)0);
  assert(!AI.getPaddingType() &&((void)0)
         "Unexpected PaddingType seen in arginfo in generic VAArg emitter!")((void)0);
  assert(!AI.getDirectOffset() &&((void)0)
         "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!")((void)0);
  assert(!AI.getCoerceToType() &&((void)0)
         "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!")((void)0);

  Address Temp = CGF.CreateMemTemp(Ty, "varet");
  Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
  CGF.Builder.CreateStore(Val, Temp);
  return Temp;
}
686}

688/// DefaultABIInfo - The default implementation for ABI specific
689/// details. This implementation provides information which results in
690/// self-consistent and sensible LLVM IR generation, but does not
691/// conform to any particular ABI.
692class DefaultABIInfo : public ABIInfo {
693public:
DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}

ABIArgInfo classifyReturnType(QualType RetTy) const;
ABIArgInfo classifyArgumentType(QualType RetTy) const;

void computeInfo(CGFunctionInfo &FI) const override {
  if (!getCXXABI().classifyReturnType(FI))
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
  for (auto &I : FI.arguments())
    I.info = classifyArgumentType(I.type);
}

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override {
  return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
}
710};

712class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
713public:
DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
    : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(CGT)) {}
716};

718ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const {
Ty = useFirstFieldIfTransparentUnion(Ty);

if (isAggregateTypeForABI(Ty)) {
  // Records with non-trivial destructors/copy-constructors should not be
  // passed by value.
  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
    return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);

  return getNaturalAlignIndirect(Ty);
}

// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = Ty->getAs<EnumType>())
  Ty = EnumTy->getDecl()->getIntegerType();

ASTContext &Context = getContext();
if (const auto *EIT = Ty->getAs<ExtIntType>())
  if (EIT->getNumBits() >
      Context.getTypeSize(Context.getTargetInfo().hasInt128Type()
                              ? Context.Int128Ty
                              : Context.LongLongTy))
    return getNaturalAlignIndirect(Ty);

return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
                                          : ABIArgInfo::getDirect());
744}

746ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const {
if (RetTy->isVoidType())
  return ABIArgInfo::getIgnore();

if (isAggregateTypeForABI(RetTy))
  return getNaturalAlignIndirect(RetTy);

// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
  RetTy = EnumTy->getDecl()->getIntegerType();

if (const auto *EIT = RetTy->getAs<ExtIntType>())
  if (EIT->getNumBits() >
      getContext().getTypeSize(getContext().getTargetInfo().hasInt128Type()
                                   ? getContext().Int128Ty
                                   : getContext().LongLongTy))
    return getNaturalAlignIndirect(RetTy);

return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
                                             : ABIArgInfo::getDirect());
766}

768//===----------------------------------------------------------------------===//
769// WebAssembly ABI Implementation
770//
771// This is a very simple ABI that relies a lot on DefaultABIInfo.
772//===----------------------------------------------------------------------===//

774class WebAssemblyABIInfo final : public SwiftABIInfo {
775public:
enum ABIKind {
  MVP = 0,
  ExperimentalMV = 1,
};

781private:
DefaultABIInfo defaultInfo;
ABIKind Kind;

785public:
explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind)
    : SwiftABIInfo(CGT), defaultInfo(CGT), Kind(Kind) {}

789private:
ABIArgInfo classifyReturnType(QualType RetTy) const;
ABIArgInfo classifyArgumentType(QualType Ty) const;

// DefaultABIInfo's classifyReturnType and classifyArgumentType are
// non-virtual, but computeInfo and EmitVAArg are virtual, so we
// overload them.
void computeInfo(CGFunctionInfo &FI) const override {
  if (!getCXXABI().classifyReturnType(FI))
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
  for (auto &Arg : FI.arguments())
    Arg.info = classifyArgumentType(Arg.type);
}

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override;

bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
                                  bool asReturnValue) const override {
  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
}

bool isSwiftErrorInRegister() const override {
  return false;
}
814};

816class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
817public:
explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
                                      WebAssemblyABIInfo::ABIKind K)
    : TargetCodeGenInfo(std::make_unique<WebAssemblyABIInfo>(CGT, K)) {}

void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                         CodeGen::CodeGenModule &CGM) const override {
  TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
  if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
    if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) {
      llvm::Function *Fn = cast<llvm::Function>(GV);
      llvm::AttrBuilder B;
      B.addAttribute("wasm-import-module", Attr->getImportModule());
      Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
    }
    if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) {
      llvm::Function *Fn = cast<llvm::Function>(GV);
      llvm::AttrBuilder B;
      B.addAttribute("wasm-import-name", Attr->getImportName());
      Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
    }
    if (const auto *Attr = FD->getAttr<WebAssemblyExportNameAttr>()) {
      llvm::Function *Fn = cast<llvm::Function>(GV);
      llvm::AttrBuilder B;
      B.addAttribute("wasm-export-name", Attr->getExportName());
      Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
    }
  }

  if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
    llvm::Function *Fn = cast<llvm::Function>(GV);
    if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype())
      Fn->addFnAttr("no-prototype");
  }
}
852};

854/// Classify argument of given type \p Ty.
855ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const {
Ty = useFirstFieldIfTransparentUnion(Ty);

if (isAggregateTypeForABI(Ty)) {
  // Records with non-trivial destructors/copy-constructors should not be
  // passed by value.
  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
    return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
  // Ignore empty structs/unions.
  if (isEmptyRecord(getContext(), Ty, true))
    return ABIArgInfo::getIgnore();
  // Lower single-element structs to just pass a regular value. TODO: We
  // could do reasonable-size multiple-element structs too, using getExpand(),
  // though watch out for things like bitfields.
  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
    return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
  // For the experimental multivalue ABI, fully expand all other aggregates
  if (Kind == ABIKind::ExperimentalMV) {
    const RecordType *RT = Ty->getAs<RecordType>();
    assert(RT)((void)0);
    bool HasBitField = false;
    for (auto *Field : RT->getDecl()->fields()) {
      if (Field->isBitField()) {
        HasBitField = true;
        break;
      }
    }
    if (!HasBitField)
      return ABIArgInfo::getExpand();
  }
}

// Otherwise just do the default thing.
return defaultInfo.classifyArgumentType(Ty);
889}

891ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const {
if (isAggregateTypeForABI(RetTy)) {
  // Records with non-trivial destructors/copy-constructors should not be
  // returned by value.
  if (!getRecordArgABI(RetTy, getCXXABI())) {
    // Ignore empty structs/unions.
    if (isEmptyRecord(getContext(), RetTy, true))
      return ABIArgInfo::getIgnore();
    // Lower single-element structs to just return a regular value. TODO: We
    // could do reasonable-size multiple-element structs too, using
    // ABIArgInfo::getDirect().
    if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
      return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
    // For the experimental multivalue ABI, return all other aggregates
    if (Kind == ABIKind::ExperimentalMV)
      return ABIArgInfo::getDirect();
  }
}

// Otherwise just do the default thing.
return defaultInfo.classifyReturnType(RetTy);
912}

914Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                                    QualType Ty) const {
bool IsIndirect = isAggregateTypeForABI(Ty) &&
                  !isEmptyRecord(getContext(), Ty, true) &&
                  !isSingleElementStruct(Ty, getContext());
return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
                        getContext().getTypeInfoInChars(Ty),
                        CharUnits::fromQuantity(4),
                        /*AllowHigherAlign=*/true);
923}

925//===----------------------------------------------------------------------===//
926// le32/PNaCl bitcode ABI Implementation
927//
928// This is a simplified version of the x86_32 ABI.  Arguments and return values
929// are always passed on the stack.
930//===----------------------------------------------------------------------===//

932class PNaClABIInfo : public ABIInfo {
public:
PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}

ABIArgInfo classifyReturnType(QualType RetTy) const;
ABIArgInfo classifyArgumentType(QualType RetTy) const;

void computeInfo(CGFunctionInfo &FI) const override;
Address EmitVAArg(CodeGenFunction &CGF,
                  Address VAListAddr, QualType Ty) const override;
942};

944class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
public:
 PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
     : TargetCodeGenInfo(std::make_unique<PNaClABIInfo>(CGT)) {}
948};

950void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
if (!getCXXABI().classifyReturnType(FI))
  FI.getReturnInfo() = classifyReturnType(FI.getReturnType());

for (auto &I : FI.arguments())
  I.info = classifyArgumentType(I.type);
956}

958Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                              QualType Ty) const {
// The PNaCL ABI is a bit odd, in that varargs don't use normal
// function classification. Structs get passed directly for varargs
// functions, through a rewriting transform in
// pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
// this target to actually support a va_arg instructions with an
// aggregate type, unlike other targets.
return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
967}

969/// Classify argument of given type \p Ty.
970ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
if (isAggregateTypeForABI(Ty)) {
  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
    return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
  return getNaturalAlignIndirect(Ty);
} else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
  // Treat an enum type as its underlying type.
  Ty = EnumTy->getDecl()->getIntegerType();
} else if (Ty->isFloatingType()) {
  // Floating-point types don't go inreg.
  return ABIArgInfo::getDirect();
} else if (const auto *EIT = Ty->getAs<ExtIntType>()) {
  // Treat extended integers as integers if <=64, otherwise pass indirectly.
  if (EIT->getNumBits() > 64)
    return getNaturalAlignIndirect(Ty);
  return ABIArgInfo::getDirect();
}

return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
                                          : ABIArgInfo::getDirect());
990}

992ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
if (RetTy->isVoidType())
  return ABIArgInfo::getIgnore();

// In the PNaCl ABI we always return records/structures on the stack.
if (isAggregateTypeForABI(RetTy))
  return getNaturalAlignIndirect(RetTy);

// Treat extended integers as integers if <=64, otherwise pass indirectly.
if (const auto *EIT = RetTy->getAs<ExtIntType>()) {
  if (EIT->getNumBits() > 64)
    return getNaturalAlignIndirect(RetTy);
  return ABIArgInfo::getDirect();
}

// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
  RetTy = EnumTy->getDecl()->getIntegerType();

return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
                                             : ABIArgInfo::getDirect());
1013}

1015/// IsX86_MMXType - Return true if this is an MMX type.
1016bool IsX86_MMXType(llvm::Type *IRType) {
// Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
  IRType->getScalarSizeInBits() != 64;
1021}

1023static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
                                        StringRef Constraint,
                                        llvm::Type* Ty) {
bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
                   .Cases("y", "&y", "^Ym", true)
                   .Default(false);
if (IsMMXCons && Ty->isVectorTy()) {
  if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedSize() !=
      64) {
    // Invalid MMX constraint
    return nullptr;
  }

  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
}

// No operation needed
return Ty;
1041}

1043/// Returns true if this type can be passed in SSE registers with the
1044/// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
1045static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
  if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
    if (BT->getKind() == BuiltinType::LongDouble) {
      if (&Context.getTargetInfo().getLongDoubleFormat() ==
          &llvm::APFloat::x87DoubleExtended())
        return false;
    }
    return true;
  }
} else if (const VectorType *VT = Ty->getAs<VectorType>()) {
  // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
  // registers specially.
  unsigned VecSize = Context.getTypeSize(VT);
  if (VecSize == 128 || VecSize == 256 || VecSize == 512)
    return true;
}
return false;
1063}

1065/// Returns true if this aggregate is small enough to be passed in SSE registers
1066/// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
1067static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
return NumMembers <= 4;
1069}

1071/// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
1072static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
auto AI = ABIArgInfo::getDirect(T);
AI.setInReg(true);
AI.setCanBeFlattened(false);
return AI;
1077}

1079//===----------------------------------------------------------------------===//
1080// X86-32 ABI Implementation
1081//===----------------------------------------------------------------------===//

1083/// Similar to llvm::CCState, but for Clang.
1084struct CCState {
CCState(CGFunctionInfo &FI)
    : IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()) {}

llvm::SmallBitVector IsPreassigned;
unsigned CC = CallingConv::CC_C;
unsigned FreeRegs = 0;
unsigned FreeSSERegs = 0;
1092};

1094/// X86_32ABIInfo - The X86-32 ABI information.
1095class X86_32ABIInfo : public SwiftABIInfo {
enum Class {
  Integer,
  Float
};

static const unsigned MinABIStackAlignInBytes = 4;

bool IsDarwinVectorABI;
bool IsRetSmallStructInRegABI;
bool IsWin32StructABI;
bool IsSoftFloatABI;
bool IsMCUABI;
bool IsLinuxABI;
unsigned DefaultNumRegisterParameters;

static bool isRegisterSize(unsigned Size) {
  return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
}

bool isHomogeneousAggregateBaseType(QualType Ty) const override {
  // FIXME: Assumes vectorcall is in use.
  return isX86VectorTypeForVectorCall(getContext(), Ty);
}

bool isHomogeneousAggregateSmallEnough(const Type *Ty,
                                       uint64_t NumMembers) const override {
  // FIXME: Assumes vectorcall is in use.
  return isX86VectorCallAggregateSmallEnough(NumMembers);
}

bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;

/// getIndirectResult - Give a source type \arg Ty, return a suitable result
/// such that the argument will be passed in memory.
ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;

ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;

/// Return the alignment to use for the given type on the stack.
unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;

Class classify(QualType Ty) const;
ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;

/// Updates the number of available free registers, returns
/// true if any registers were allocated.
bool updateFreeRegs(QualType Ty, CCState &State) const;

bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
                              bool &NeedsPadding) const;
bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;

bool canExpandIndirectArgument(QualType Ty) const;

/// Rewrite the function info so that all memory arguments use
/// inalloca.
void rewriteWithInAlloca(CGFunctionInfo &FI) const;

void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
                         CharUnits &StackOffset, ABIArgInfo &Info,
                         QualType Type) const;
void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const;

1160public:

void computeInfo(CGFunctionInfo &FI) const override;
Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override;

X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
              bool RetSmallStructInRegABI, bool Win32StructABI,
              unsigned NumRegisterParameters, bool SoftFloatABI)
  : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
    IsRetSmallStructInRegABI(RetSmallStructInRegABI),
    IsWin32StructABI(Win32StructABI), IsSoftFloatABI(SoftFloatABI),
    IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
    IsLinuxABI(CGT.getTarget().getTriple().isOSLinux()),
    DefaultNumRegisterParameters(NumRegisterParameters) {}

bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
                                  bool asReturnValue) const override {
  // LLVM's x86-32 lowering currently only assigns up to three
  // integer registers and three fp registers.  Oddly, it'll use up to
  // four vector registers for vectors, but those can overlap with the
  // scalar registers.
  return occupiesMoreThan(CGT, scalars, /*total*/ 3);
}

bool isSwiftErrorInRegister() const override {
  // x86-32 lowering does not support passing swifterror in a register.
  return false;
}
1189};

1191class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1192public:
X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
                        bool RetSmallStructInRegABI, bool Win32StructABI,
                        unsigned NumRegisterParameters, bool SoftFloatABI)
    : TargetCodeGenInfo(std::make_unique<X86_32ABIInfo>(
          CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
          NumRegisterParameters, SoftFloatABI)) {}

static bool isStructReturnInRegABI(
    const llvm::Triple &Triple, const CodeGenOptions &Opts);

void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                         CodeGen::CodeGenModule &CGM) const override;

int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
  // Darwin uses different dwarf register numbers for EH.
  if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
  return 4;
}

bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                             llvm::Value *Address) const override;

llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
                                StringRef Constraint,
                                llvm::Type* Ty) const override {
  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
}

void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
                              std::string &Constraints,
                              std::vector<llvm::Type *> &ResultRegTypes,
                              std::vector<llvm::Type *> &ResultTruncRegTypes,
                              std::vector<LValue> &ResultRegDests,
                              std::string &AsmString,
                              unsigned NumOutputs) const override;

llvm::Constant *
getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
  unsigned Sig = (0xeb << 0) |  // jmp rel8
                 (0x06 << 8) |  //           .+0x08
                 ('v' << 16) |
                 ('2' << 24);
  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
}

StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
  return "movl\t%ebp, %ebp"
         "\t\t// marker for objc_retainAutoreleaseReturnValue";
}
1242};

1244}

1246/// Rewrite input constraint references after adding some output constraints.
1247/// In the case where there is one output and one input and we add one output,
1248/// we need to replace all operand references greater than or equal to 1:
1249///     mov $0, $1
1250///     mov eax, $1
1251/// The result will be:
1252///     mov $0, $2
1253///     mov eax, $2
1254static void rewriteInputConstraintReferences(unsigned FirstIn,
                                           unsigned NumNewOuts,
                                           std::string &AsmString) {
std::string Buf;
llvm::raw_string_ostream OS(Buf);
size_t Pos = 0;
while (Pos < AsmString.size()) {
  size_t DollarStart = AsmString.find('$', Pos);
  if (DollarStart == std::string::npos)
    DollarStart = AsmString.size();
  size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
  if (DollarEnd == std::string::npos)
    DollarEnd = AsmString.size();
  OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
  Pos = DollarEnd;
  size_t NumDollars = DollarEnd - DollarStart;
  if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
    // We have an operand reference.
    size_t DigitStart = Pos;
    if (AsmString[DigitStart] == '{') {
      OS << '{';
      ++DigitStart;
    }
    size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
    if (DigitEnd == std::string::npos)
      DigitEnd = AsmString.size();
    StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
    unsigned OperandIndex;
    if (!OperandStr.getAsInteger(10, OperandIndex)) {
      if (OperandIndex >= FirstIn)
        OperandIndex += NumNewOuts;
      OS << OperandIndex;
    } else {
      OS << OperandStr;
    }
    Pos = DigitEnd;
  }
}
AsmString = std::move(OS.str());
1293}

1295/// Add output constraints for EAX:EDX because they are return registers.
1296void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
  CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
  std::vector<llvm::Type *> &ResultRegTypes,
  std::vector<llvm::Type *> &ResultTruncRegTypes,
  std::vector<LValue> &ResultRegDests, std::string &AsmString,
  unsigned NumOutputs) const {
uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());

// Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
// larger.
if (!Constraints.empty())
  Constraints += ',';
if (RetWidth <= 32) {
  Constraints += "={eax}";
  ResultRegTypes.push_back(CGF.Int32Ty);
} else {
  // Use the 'A' constraint for EAX:EDX.
  Constraints += "=A";
  ResultRegTypes.push_back(CGF.Int64Ty);
}

// Truncate EAX or EAX:EDX to an integer of the appropriate size.
llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
ResultTruncRegTypes.push_back(CoerceTy);

// Coerce the integer by bitcasting the return slot pointer.
ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(CGF),
                                                CoerceTy->getPointerTo()));
ResultRegDests.push_back(ReturnSlot);

rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1327}

1329/// shouldReturnTypeInRegister - Determine if the given type should be
1330/// returned in a register (for the Darwin and MCU ABI).
1331bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
                                             ASTContext &Context) const {
uint64_t Size = Context.getTypeSize(Ty);

// For i386, type must be register sized.
// For the MCU ABI, it only needs to be <= 8-byte
if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
 return false;

if (Ty->isVectorType()) {
  // 64- and 128- bit vectors inside structures are not returned in
  // registers.
  if (Size == 64 || Size == 128)
    return false;

  return true;
}

// If this is a builtin, pointer, enum, complex type, member pointer, or
// member function pointer it is ok.
if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
    Ty->isAnyComplexType() || Ty->isEnumeralType() ||
    Ty->isBlockPointerType() || Ty->isMemberPointerType())
  return true;

// Arrays are treated like records.
if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
  return shouldReturnTypeInRegister(AT->getElementType(), Context);

// Otherwise, it must be a record type.
const RecordType *RT = Ty->getAs<RecordType>();
if (!RT) return false;

// FIXME: Traverse bases here too.

// Structure types are passed in register if all fields would be
// passed in a register.
for (const auto *FD : RT->getDecl()->fields()) {
  // Empty fields are ignored.
  if (isEmptyField(Context, FD, true))
    continue;

  // Check fields recursively.
  if (!shouldReturnTypeInRegister(FD->getType(), Context))
    return false;
}
return true;
1378}

1380static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
// Treat complex types as the element type.
if (const ComplexType *CTy = Ty->getAs<ComplexType>())
  Ty = CTy->getElementType();

// Check for a type which we know has a simple scalar argument-passing
// convention without any padding.  (We're specifically looking for 32
// and 64-bit integer and integer-equivalents, float, and double.)
if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
    !Ty->isEnumeralType() && !Ty->isBlockPointerType())
  return false;

uint64_t Size = Context.getTypeSize(Ty);
return Size == 32 || Size == 64;
1394}

1396static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
                        uint64_t &Size) {
for (const auto *FD : RD->fields()) {
  // Scalar arguments on the stack get 4 byte alignment on x86. If the
  // argument is smaller than 32-bits, expanding the struct will create
  // alignment padding.
  if (!is32Or64BitBasicType(FD->getType(), Context))
    return false;

  // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
  // how to expand them yet, and the predicate for telling if a bitfield still
  // counts as "basic" is more complicated than what we were doing previously.
  if (FD->isBitField())
    return false;

  Size += Context.getTypeSize(FD->getType());
}
return true;
1414}

1416static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
                               uint64_t &Size) {
// Don't do this if there are any non-empty bases.
for (const CXXBaseSpecifier &Base : RD->bases()) {
  if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
                            Size))
    return false;
}
if (!addFieldSizes(Context, RD, Size))
  return false;
return true;
1427}

1429/// Test whether an argument type which is to be passed indirectly (on the
1430/// stack) would have the equivalent layout if it was expanded into separate
1431/// arguments. If so, we prefer to do the latter to avoid inhibiting
1432/// optimizations.
1433bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
// We can only expand structure types.
const RecordType *RT = Ty->getAs<RecordType>();
if (!RT)
  return false;
const RecordDecl *RD = RT->getDecl();
uint64_t Size = 0;
if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
  if (!IsWin32StructABI) {
    // On non-Windows, we have to conservatively match our old bitcode
    // prototypes in order to be ABI-compatible at the bitcode level.
    if (!CXXRD->isCLike())
      return false;
  } else {
    // Don't do this for dynamic classes.
    if (CXXRD->isDynamicClass())
      return false;
  }
  if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
    return false;
} else {
  if (!addFieldSizes(getContext(), RD, Size))
    return false;
}

// We can do this if there was no alignment padding.
return Size == getContext().getTypeSize(Ty);
1460}

1462ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
// If the return value is indirect, then the hidden argument is consuming one
// integer register.
if (State.FreeRegs) {
  --State.FreeRegs;
  if (!IsMCUABI)
    return getNaturalAlignIndirectInReg(RetTy);
}
return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1471}

1473ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy,
                                           CCState &State) const {
if (RetTy->isVoidType())
  return ABIArgInfo::getIgnore();

const Type *Base = nullptr;
uint64_t NumElts = 0;
if ((State.CC == llvm::CallingConv::X86_VectorCall ||
     State.CC == llvm::CallingConv::X86_RegCall) &&
    isHomogeneousAggregate(RetTy, Base, NumElts)) {
  // The LLVM struct type for such an aggregate should lower properly.
  return ABIArgInfo::getDirect();
}

if (const VectorType *VT = RetTy->getAs<VectorType>()) {
  // On Darwin, some vectors are returned in registers.
  if (IsDarwinVectorABI) {
    uint64_t Size = getContext().getTypeSize(RetTy);

    // 128-bit vectors are a special case; they are returned in
    // registers and we need to make sure to pick a type the LLVM
    // backend will like.
    if (Size == 128)
      return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
          llvm::Type::getInt64Ty(getVMContext()), 2));

    // Always return in register if it fits in a general purpose
    // register, or if it is 64 bits and has a single element.
    if ((Size == 8 || Size == 16 || Size == 32) ||
        (Size == 64 && VT->getNumElements() == 1))
      return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
                                                          Size));

    return getIndirectReturnResult(RetTy, State);
  }

  return ABIArgInfo::getDirect();
}

if (isAggregateTypeForABI(RetTy)) {
  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
    // Structures with flexible arrays are always indirect.
    if (RT->getDecl()->hasFlexibleArrayMember())
      return getIndirectReturnResult(RetTy, State);
  }

  // If specified, structs and unions are always indirect.
  if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
    return getIndirectReturnResult(RetTy, State);

  // Ignore empty structs/unions.
  if (isEmptyRecord(getContext(), RetTy, true))
    return ABIArgInfo::getIgnore();

  // Small structures which are register sized are generally returned
  // in a register.
  if (shouldReturnTypeInRegister(RetTy, getContext())) {
    uint64_t Size = getContext().getTypeSize(RetTy);

    // As a special-case, if the struct is a "single-element" struct, and
    // the field is of type "float" or "double", return it in a
    // floating-point register. (MSVC does not apply this special case.)
    // We apply a similar transformation for pointer types to improve the
    // quality of the generated IR.
    if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
      if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
          || SeltTy->hasPointerRepresentation())
        return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));

    // FIXME: We should be able to narrow this integer in cases with dead
    // padding.
    return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
  }

  return getIndirectReturnResult(RetTy, State);
}

// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
  RetTy = EnumTy->getDecl()->getIntegerType();

if (const auto *EIT = RetTy->getAs<ExtIntType>())
  if (EIT->getNumBits() > 64)
    return getIndirectReturnResult(RetTy, State);

return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
                                             : ABIArgInfo::getDirect());
1560}

1562static bool isSIMDVectorType(ASTContext &Context, QualType Ty) {
return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1564}

1566static bool isRecordWithSIMDVectorType(ASTContext &Context, QualType Ty) {
const RecordType *RT = Ty->getAs<RecordType>();
if (!RT)
  return 0;
const RecordDecl *RD = RT->getDecl();

// If this is a C++ record, check the bases first.
if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
  for (const auto &I : CXXRD->bases())
    if (!isRecordWithSIMDVectorType(Context, I.getType()))
      return false;

for (const auto *i : RD->fields()) {
  QualType FT = i->getType();

  if (isSIMDVectorType(Context, FT))
    return true;

  if (isRecordWithSIMDVectorType(Context, FT))
    return true;
}

return false;
1589}

1591unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
                                               unsigned Align) const {
// Otherwise, if the alignment is less than or equal to the minimum ABI
// alignment, just use the default; the backend will handle this.
if (Align <= MinABIStackAlignInBytes)
  return 0; // Use default alignment.

if (IsLinuxABI) {
  // Exclude other System V OS (e.g Darwin, PS4 and FreeBSD) since we don't
  // want to spend any effort dealing with the ramifications of ABI breaks.
  //
  // If the vector type is __m128/__m256/__m512, return the default alignment.
  if (Ty->isVectorType() && (Align == 16 || Align == 32 || Align == 64))
    return Align;
}
// On non-Darwin, the stack type alignment is always 4.
if (!IsDarwinVectorABI) {
  // Set explicit alignment, since we may need to realign the top.
  return MinABIStackAlignInBytes;
}

// Otherwise, if the type contains an SSE vector type, the alignment is 16.
if (Align >= 16 && (isSIMDVectorType(getContext(), Ty) ||
                    isRecordWithSIMDVectorType(getContext(), Ty)))
  return 16;

return MinABIStackAlignInBytes;
1618}

1620ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
                                          CCState &State) const {
if (!ByVal) {
  if (State.FreeRegs) {
    --State.FreeRegs; // Non-byval indirects just use one pointer.
    if (!IsMCUABI)
      return getNaturalAlignIndirectInReg(Ty);
  }
  return getNaturalAlignIndirect(Ty, false);
}

// Compute the byval alignment.
unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
if (StackAlign == 0)
  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);

// If the stack alignment is less than the type alignment, realign the
// argument.
bool Realign = TypeAlign > StackAlign;
return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign),
                               /*ByVal=*/true, Realign);
1642}

1644X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
const Type *T = isSingleElementStruct(Ty, getContext());
if (!T)
  T = Ty.getTypePtr();

if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
  BuiltinType::Kind K = BT->getKind();
  if (K == BuiltinType::Float || K == BuiltinType::Double)
    return Float;
}
return Integer;
1655}

1657bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
if (!IsSoftFloatABI) {
  Class C = classify(Ty);
  if (C == Float)
    return false;
}

unsigned Size = getContext().getTypeSize(Ty);
unsigned SizeInRegs = (Size + 31) / 32;

if (SizeInRegs == 0)
  return false;

if (!IsMCUABI) {
  if (SizeInRegs > State.FreeRegs) {
    State.FreeRegs = 0;
    return false;
  }
} else {
  // The MCU psABI allows passing parameters in-reg even if there are
  // earlier parameters that are passed on the stack. Also,
  // it does not allow passing >8-byte structs in-register,
  // even if there are 3 free registers available.
  if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
    return false;
}

State.FreeRegs -= SizeInRegs;
return true;
1686}

1688bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
                                           bool &InReg,
                                           bool &NeedsPadding) const {
// On Windows, aggregates other than HFAs are never passed in registers, and
// they do not consume register slots. Homogenous floating-point aggregates
// (HFAs) have already been dealt with at this point.
if (IsWin32StructABI && isAggregateTypeForABI(Ty))
  return false;

NeedsPadding = false;
InReg = !IsMCUABI;

if (!updateFreeRegs(Ty, State))
  return false;

if (IsMCUABI)
  return true;

if (State.CC == llvm::CallingConv::X86_FastCall ||
    State.CC == llvm::CallingConv::X86_VectorCall ||
    State.CC == llvm::CallingConv::X86_RegCall) {
  if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
    NeedsPadding = true;

  return false;
}

return true;
1716}

1718bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
if (!updateFreeRegs(Ty, State))
  return false;

if (IsMCUABI)
  return false;

if (State.CC == llvm::CallingConv::X86_FastCall ||
    State.CC == llvm::CallingConv::X86_VectorCall ||
    State.CC == llvm::CallingConv::X86_RegCall) {
  if (getContext().getTypeSize(Ty) > 32)
    return false;

  return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
      Ty->isReferenceType());
}

return true;
1736}

1738void X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const {
// Vectorcall x86 works subtly different than in x64, so the format is
// a bit different than the x64 version.  First, all vector types (not HVAs)
// are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers.
// This differs from the x64 implementation, where the first 6 by INDEX get
// registers.
// In the second pass over the arguments, HVAs are passed in the remaining
// vector registers if possible, or indirectly by address. The address will be
// passed in ECX/EDX if available. Any other arguments are passed according to
// the usual fastcall rules.
MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
for (int I = 0, E = Args.size(); I < E; ++I) {
  const Type *Base = nullptr;
  uint64_t NumElts = 0;
  const QualType &Ty = Args[I].type;
  if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
      isHomogeneousAggregate(Ty, Base, NumElts)) {
    if (State.FreeSSERegs >= NumElts) {
      State.FreeSSERegs -= NumElts;
      Args[I].info = ABIArgInfo::getDirectInReg();
      State.IsPreassigned.set(I);
    }
  }
}
1762}

1764ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
                                             CCState &State) const {
// FIXME: Set alignment on indirect arguments.
bool IsFastCall = State.CC == llvm::CallingConv::X86_FastCall;
bool IsRegCall = State.CC == llvm::CallingConv::X86_RegCall;
bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall;

Ty = useFirstFieldIfTransparentUnion(Ty);
TypeInfo TI = getContext().getTypeInfo(Ty);

// Check with the C++ ABI first.
const RecordType *RT = Ty->getAs<RecordType>();
if (RT) {
  CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI());
  if (RAA == CGCXXABI::RAA_Indirect) {
    return getIndirectResult(Ty, false, State);
  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
    // The field index doesn't matter, we'll fix it up later.
    return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
  }
}

// Regcall uses the concept of a homogenous vector aggregate, similar
// to other targets.
const Type *Base = nullptr;
uint64_t NumElts = 0;
if ((IsRegCall || IsVectorCall) &&
    isHomogeneousAggregate(Ty, Base, NumElts)) {
  if (State.FreeSSERegs >= NumElts) {
    State.FreeSSERegs -= NumElts;

    // Vectorcall passes HVAs directly and does not flatten them, but regcall
    // does.
    if (IsVectorCall)
      return getDirectX86Hva();

    if (Ty->isBuiltinType() || Ty->isVectorType())
      return ABIArgInfo::getDirect();
    return ABIArgInfo::getExpand();
  }
  return getIndirectResult(Ty, /*ByVal=*/false, State);
}

if (isAggregateTypeForABI(Ty)) {
  // Structures with flexible arrays are always indirect.
  // FIXME: This should not be byval!
  if (RT && RT->getDecl()->hasFlexibleArrayMember())
    return getIndirectResult(Ty, true, State);

  // Ignore empty structs/unions on non-Windows.
  if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
    return ABIArgInfo::getIgnore();

  llvm::LLVMContext &LLVMContext = getVMContext();
  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
  bool NeedsPadding = false;
  bool InReg;
  if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
    unsigned SizeInRegs = (TI.Width + 31) / 32;
    SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
    llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
    if (InReg)
      return ABIArgInfo::getDirectInReg(Result);
    else
      return ABIArgInfo::getDirect(Result);
  }
  llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;

  // Pass over-aligned aggregates on Windows indirectly. This behavior was
  // added in MSVC 2015.
  if (IsWin32StructABI && TI.AlignIsRequired && TI.Align > 32)
    return getIndirectResult(Ty, /*ByVal=*/false, State);

  // Expand small (<= 128-bit) record types when we know that the stack layout
  // of those arguments will match the struct. This is important because the
  // LLVM backend isn't smart enough to remove byval, which inhibits many
  // optimizations.
  // Don't do this for the MCU if there are still free integer registers
  // (see X86_64 ABI for full explanation).
  if (TI.Width <= 4 * 32 && (!IsMCUABI || State.FreeRegs == 0) &&
      canExpandIndirectArgument(Ty))
    return ABIArgInfo::getExpandWithPadding(
        IsFastCall || IsVectorCall || IsRegCall, PaddingType);

  return getIndirectResult(Ty, true, State);
}

if (const VectorType *VT = Ty->getAs<VectorType>()) {
  // On Windows, vectors are passed directly if registers are available, or
  // indirectly if not. This avoids the need to align argument memory. Pass
  // user-defined vector types larger than 512 bits indirectly for simplicity.
  if (IsWin32StructABI) {
    if (TI.Width <= 512 && State.FreeSSERegs > 0) {
      --State.FreeSSERegs;
      return ABIArgInfo::getDirectInReg();
    }
    return getIndirectResult(Ty, /*ByVal=*/false, State);
  }

  // On Darwin, some vectors are passed in memory, we handle this by passing
  // it as an i8/i16/i32/i64.
  if (IsDarwinVectorABI) {
    if ((TI.Width == 8 || TI.Width == 16 || TI.Width == 32) ||
        (TI.Width == 64 && VT->getNumElements() == 1))
      return ABIArgInfo::getDirect(
          llvm::IntegerType::get(getVMContext(), TI.Width));
  }

  if (IsX86_MMXType(CGT.ConvertType(Ty)))
    return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));

  return ABIArgInfo::getDirect();
}


if (const EnumType *EnumTy = Ty->getAs<EnumType>())
  Ty = EnumTy->getDecl()->getIntegerType();

bool InReg = shouldPrimitiveUseInReg(Ty, State);

if (isPromotableIntegerTypeForABI(Ty)) {
  if (InReg)
    return ABIArgInfo::getExtendInReg(Ty);
  return ABIArgInfo::getExtend(Ty);
}

if (const auto * EIT = Ty->getAs<ExtIntType>()) {
  if (EIT->getNumBits() <= 64) {
    if (InReg)
      return ABIArgInfo::getDirectInReg();
    return ABIArgInfo::getDirect();
  }
  return getIndirectResult(Ty, /*ByVal=*/false, State);
}

if (InReg)
  return ABIArgInfo::getDirectInReg();
return ABIArgInfo::getDirect();
1902}

1904void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
CCState State(FI);
if (IsMCUABI)
  State.FreeRegs = 3;
else if (State.CC == llvm::CallingConv::X86_FastCall) {
  State.FreeRegs = 2;
  State.FreeSSERegs = 3;
} else if (State.CC == llvm::CallingConv::X86_VectorCall) {
  State.FreeRegs = 2;
  State.FreeSSERegs = 6;
} else if (FI.getHasRegParm())
  State.FreeRegs = FI.getRegParm();
else if (State.CC == llvm::CallingConv::X86_RegCall) {
  State.FreeRegs = 5;
  State.FreeSSERegs = 8;
} else if (IsWin32StructABI) {
  // Since MSVC 2015, the first three SSE vectors have been passed in
  // registers. The rest are passed indirectly.
  State.FreeRegs = DefaultNumRegisterParameters;
  State.FreeSSERegs = 3;
} else
  State.FreeRegs = DefaultNumRegisterParameters;

if (!::classifyReturnType(getCXXABI(), FI, *this)) {
  FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
} else if (FI.getReturnInfo().isIndirect()) {
  // The C++ ABI is not aware of register usage, so we have to check if the
  // return value was sret and put it in a register ourselves if appropriate.
  if (State.FreeRegs) {
    --State.FreeRegs;  // The sret parameter consumes a register.
    if (!IsMCUABI)
      FI.getReturnInfo().setInReg(true);
  }
}

// The chain argument effectively gives us another free register.
if (FI.isChainCall())
  ++State.FreeRegs;

// For vectorcall, do a first pass over the arguments, assigning FP and vector
// arguments to XMM registers as available.
if (State.CC == llvm::CallingConv::X86_VectorCall)
  runVectorCallFirstPass(FI, State);

bool UsedInAlloca = false;
MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
for (int I = 0, E = Args.size(); I < E; ++I) {
  // Skip arguments that have already been assigned.
  if (State.IsPreassigned.test(I))
    continue;

  Args[I].info = classifyArgumentType(Args[I].type, State);
  UsedInAlloca |= (Args[I].info.getKind() == ABIArgInfo::InAlloca);
}

// If we needed to use inalloca for any argument, do a second pass and rewrite
// all the memory arguments to use inalloca.
if (UsedInAlloca)
  rewriteWithInAlloca(FI);
1963}

1965void
1966X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
                                 CharUnits &StackOffset, ABIArgInfo &Info,
                                 QualType Type) const {
// Arguments are always 4-byte-aligned.
CharUnits WordSize = CharUnits::fromQuantity(4);
assert(StackOffset.isMultipleOf(WordSize) && "unaligned inalloca struct")((void)0);

// sret pointers and indirect things will require an extra pointer
// indirection, unless they are byval. Most things are byval, and will not
// require this indirection.
bool IsIndirect = false;
if (Info.isIndirect() && !Info.getIndirectByVal())
  IsIndirect = true;
Info = ABIArgInfo::getInAlloca(FrameFields.size(), IsIndirect);
llvm::Type *LLTy = CGT.ConvertTypeForMem(Type);
if (IsIndirect)
  LLTy = LLTy->getPointerTo(0);
FrameFields.push_back(LLTy);
StackOffset += IsIndirect ? WordSize : getContext().getTypeSizeInChars(Type);

// Insert padding bytes to respect alignment.
CharUnits FieldEnd = StackOffset;
StackOffset = FieldEnd.alignTo(WordSize);
if (StackOffset != FieldEnd) {
  CharUnits NumBytes = StackOffset - FieldEnd;
  llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
  Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
  FrameFields.push_back(Ty);
}
1995}

1997static bool isArgInAlloca(const ABIArgInfo &Info) {
// Leave ignored and inreg arguments alone.
switch (Info.getKind()) {
case ABIArgInfo::InAlloca:
  return true;
case ABIArgInfo::Ignore:
case ABIArgInfo::IndirectAliased:
  return false;
case ABIArgInfo::Indirect:
case ABIArgInfo::Direct:
case ABIArgInfo::Extend:
  return !Info.getInReg();
case ABIArgInfo::Expand:
case ABIArgInfo::CoerceAndExpand:
  // These are aggregate types which are never passed in registers when
  // inalloca is involved.
  return true;
}
llvm_unreachable("invalid enum")__builtin_unreachable();
2016}

2018void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
assert(IsWin32StructABI && "inalloca only supported on win32")((void)0);

// Build a packed struct type for all of the arguments in memory.
SmallVector<llvm::Type *, 6> FrameFields;

// The stack alignment is always 4.
CharUnits StackAlign = CharUnits::fromQuantity(4);

CharUnits StackOffset;
CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();

// Put 'this' into the struct before 'sret', if necessary.
bool IsThisCall =
    FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
ABIArgInfo &Ret = FI.getReturnInfo();
if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
    isArgInAlloca(I->info)) {
  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
  ++I;
}

// Put the sret parameter into the inalloca struct if it's in memory.
if (Ret.isIndirect() && !Ret.getInReg()) {
  addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType());
  // On Windows, the hidden sret parameter is always returned in eax.
  Ret.setInAllocaSRet(IsWin32StructABI);
}

// Skip the 'this' parameter in ecx.
if (IsThisCall)
  ++I;

// Put arguments passed in memory into the struct.
for (; I != E; ++I) {
  if (isArgInAlloca(I->info))
    addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
}

FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
                                      /*isPacked=*/true),
                StackAlign);
2060}

2062Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
                               Address VAListAddr, QualType Ty) const {

auto TypeInfo = getContext().getTypeInfoInChars(Ty);

// x86-32 changes the alignment of certain arguments on the stack.
//
// Just messing with TypeInfo like this works because we never pass
// anything indirectly.
TypeInfo.Align = CharUnits::fromQuantity(
              getTypeStackAlignInBytes(Ty, TypeInfo.Align.getQuantity()));

return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
                        TypeInfo, CharUnits::fromQuantity(4),
                        /*AllowHigherAlign*/ true);
2077}

2079bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
assert(Triple.getArch() == llvm::Triple::x86)((void)0);

switch (Opts.getStructReturnConvention()) {
case CodeGenOptions::SRCK_Default:
  break;
case CodeGenOptions::SRCK_OnStack:  // -fpcc-struct-return
  return false;
case CodeGenOptions::SRCK_InRegs:  // -freg-struct-return
  return true;
}

if (Triple.isOSDarwin() || Triple.isOSIAMCU())
  return true;

switch (Triple.getOS()) {
case llvm::Triple::DragonFly:
case llvm::Triple::FreeBSD:
case llvm::Triple::OpenBSD:
case llvm::Triple::Win32:
  return true;
default:
  return false;
}
2104}

2106static void addX86InterruptAttrs(const FunctionDecl *FD, llvm::GlobalValue *GV,
                               CodeGen::CodeGenModule &CGM) {
if (!FD->hasAttr<AnyX86InterruptAttr>())
  return;

llvm::Function *Fn = cast<llvm::Function>(GV);
Fn->setCallingConv(llvm::CallingConv::X86_INTR);
if (FD->getNumParams() == 0)
  return;

auto PtrTy = cast<PointerType>(FD->getParamDecl(0)->getType());
llvm::Type *ByValTy = CGM.getTypes().ConvertType(PtrTy->getPointeeType());
llvm::Attribute NewAttr = llvm::Attribute::getWithByValType(
  Fn->getContext(), ByValTy);
Fn->addParamAttr(0, NewAttr);
2121}

2123void X86_32TargetCodeGenInfo::setTargetAttributes(
  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
if (GV->isDeclaration())
  return;
if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
    llvm::Function *Fn = cast<llvm::Function>(GV);
    Fn->addFnAttr("stackrealign");
  }

  addX86InterruptAttrs(FD, GV, CGM);
}
2135}

2137bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
                                             CodeGen::CodeGenFunction &CGF,
                                             llvm::Value *Address) const {
CodeGen::CGBuilderTy &Builder = CGF.Builder;

llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);

// 0-7 are the eight integer registers;  the order is different
//   on Darwin (for EH), but the range is the same.
// 8 is %eip.
AssignToArrayRange(Builder, Address, Four8, 0, 8);

if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
  // 12-16 are st(0..4).  Not sure why we stop at 4.
  // These have size 16, which is sizeof(long double) on
  // platforms with 8-byte alignment for that type.
  llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
  AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);

} else {
  // 9 is %eflags, which doesn't get a size on Darwin for some
  // reason.
  Builder.CreateAlignedStore(
      Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
                             CharUnits::One());

  // 11-16 are st(0..5).  Not sure why we stop at 5.
  // These have size 12, which is sizeof(long double) on
  // platforms with 4-byte alignment for that type.
  llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
  AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
}

return false;
2171}

2173//===----------------------------------------------------------------------===//
2174// X86-64 ABI Implementation
2175//===----------------------------------------------------------------------===//


2178namespace {
2179/// The AVX ABI level for X86 targets.
2180enum class X86AVXABILevel {
None,
AVX,
AVX512
2184};

2186/// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2187static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
switch (AVXLevel) {
case X86AVXABILevel::AVX512:
  return 512;
case X86AVXABILevel::AVX:
  return 256;
case X86AVXABILevel::None:
  return 128;
}
llvm_unreachable("Unknown AVXLevel")__builtin_unreachable();
2197}

2199/// X86_64ABIInfo - The X86_64 ABI information.
2200class X86_64ABIInfo : public SwiftABIInfo {
enum Class {
  Integer = 0,
  SSE,
  SSEUp,
  X87,
  X87Up,
  ComplexX87,
  NoClass,
  Memory
};

/// merge - Implement the X86_64 ABI merging algorithm.
///
/// Merge an accumulating classification \arg Accum with a field
/// classification \arg Field.
///
/// \param Accum - The accumulating classification. This should
/// always be either NoClass or the result of a previous merge
/// call. In addition, this should never be Memory (the caller
/// should just return Memory for the aggregate).
static Class merge(Class Accum, Class Field);

/// postMerge - Implement the X86_64 ABI post merging algorithm.
///
/// Post merger cleanup, reduces a malformed Hi and Lo pair to
/// final MEMORY or SSE classes when necessary.
///
/// \param AggregateSize - The size of the current aggregate in
/// the classification process.
///
/// \param Lo - The classification for the parts of the type
/// residing in the low word of the containing object.
///
/// \param Hi - The classification for the parts of the type
/// residing in the higher words of the containing object.
///
void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;

/// classify - Determine the x86_64 register classes in which the
/// given type T should be passed.
///
/// \param Lo - The classification for the parts of the type
/// residing in the low word of the containing object.
///
/// \param Hi - The classification for the parts of the type
/// residing in the high word of the containing object.
///
/// \param OffsetBase - The bit offset of this type in the
/// containing object.  Some parameters are classified different
/// depending on whether they straddle an eightbyte boundary.
///
/// \param isNamedArg - Whether the argument in question is a "named"
/// argument, as used in AMD64-ABI 3.5.7.
///
/// If a word is unused its result will be NoClass; if a type should
/// be passed in Memory then at least the classification of \arg Lo
/// will be Memory.
///
/// The \arg Lo class will be NoClass iff the argument is ignored.
///
/// If the \arg Lo class is ComplexX87, then the \arg Hi class will
/// also be ComplexX87.
void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
              bool isNamedArg) const;

llvm::Type *GetByteVectorType(QualType Ty) const;
llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
                               unsigned IROffset, QualType SourceTy,
                               unsigned SourceOffset) const;
llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
                                   unsigned IROffset, QualType SourceTy,
                                   unsigned SourceOffset) const;

/// getIndirectResult - Give a source type \arg Ty, return a suitable result
/// such that the argument will be returned in memory.
ABIArgInfo getIndirectReturnResult(QualType Ty) const;

/// getIndirectResult - Give a source type \arg Ty, return a suitable result
/// such that the argument will be passed in memory.
///
/// \param freeIntRegs - The number of free integer registers remaining
/// available.
ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;

ABIArgInfo classifyReturnType(QualType RetTy) const;

ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
                                unsigned &neededInt, unsigned &neededSSE,
                                bool isNamedArg) const;

ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
                                     unsigned &NeededSSE) const;

ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
                                         unsigned &NeededSSE) const;

bool IsIllegalVectorType(QualType Ty) const;

/// The 0.98 ABI revision clarified a lot of ambiguities,
/// unfortunately in ways that were not always consistent with
/// certain previous compilers.  In particular, platforms which
/// required strict binary compatibility with older versions of GCC
/// may need to exempt themselves.
bool honorsRevision0_98() const {
  return !getTarget().getTriple().isOSDarwin();
}

/// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
/// classify it as INTEGER (for compatibility with older clang compilers).
bool classifyIntegerMMXAsSSE() const {
  // Clang <= 3.8 did not do this.
  if (getContext().getLangOpts().getClangABICompat() <=
      LangOptions::ClangABI::Ver3_8)
    return false;

  const llvm::Triple &Triple = getTarget().getTriple();
  if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
    return false;
  if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
    return false;
  return true;
}

// GCC classifies vectors of __int128 as memory.
bool passInt128VectorsInMem() const {
  // Clang <= 9.0 did not do this.
  if (getContext().getLangOpts().getClangABICompat() <=
      LangOptions::ClangABI::Ver9)
    return false;

  const llvm::Triple &T = getTarget().getTriple();
  return T.isOSLinux() || T.isOSNetBSD();
}

X86AVXABILevel AVXLevel;
// Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
// 64-bit hardware.
bool Has64BitPointers;

2340public:
X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
    SwiftABIInfo(CGT), AVXLevel(AVXLevel),
    Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
}

bool isPassedUsingAVXType(QualType type) const {
  unsigned neededInt, neededSSE;
  // The freeIntRegs argument doesn't matter here.
  ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
                                         /*isNamedArg*/true);
  if (info.isDirect()) {
    llvm::Type *ty = info.getCoerceToType();
    if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
      return vectorTy->getPrimitiveSizeInBits().getFixedSize() > 128;
  }
  return false;
}

void computeInfo(CGFunctionInfo &FI) const override;

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override;
Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
                    QualType Ty) const override;

bool has64BitPointers() const {
  return Has64BitPointers;
}

bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
                                  bool asReturnValue) const override {
  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
}
bool isSwiftErrorInRegister() const override {
  return true;
}
2377};

2379/// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2380class WinX86_64ABIInfo : public SwiftABIInfo {
2381public:
WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
    : SwiftABIInfo(CGT), AVXLevel(AVXLevel),
      IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}

void computeInfo(CGFunctionInfo &FI) const override;

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override;

bool isHomogeneousAggregateBaseType(QualType Ty) const override {
  // FIXME: Assumes vectorcall is in use.
  return isX86VectorTypeForVectorCall(getContext(), Ty);
}

bool isHomogeneousAggregateSmallEnough(const Type *Ty,
                                       uint64_t NumMembers) const override {
  // FIXME: Assumes vectorcall is in use.
  return isX86VectorCallAggregateSmallEnough(NumMembers);
}

bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
                                  bool asReturnValue) const override {
  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
}

bool isSwiftErrorInRegister() const override {
  return true;
}

2411private:
ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
                    bool IsVectorCall, bool IsRegCall) const;
ABIArgInfo reclassifyHvaArgForVectorCall(QualType Ty, unsigned &FreeSSERegs,
                                         const ABIArgInfo &current) const;

X86AVXABILevel AVXLevel;

bool IsMingw64;
2420};

2422class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2423public:
X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
    : TargetCodeGenInfo(std::make_unique<X86_64ABIInfo>(CGT, AVXLevel)) {}

const X86_64ABIInfo &getABIInfo() const {
  return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
}

/// Disable tail call on x86-64. The epilogue code before the tail jump blocks
/// autoreleaseRV/retainRV and autoreleaseRV/unsafeClaimRV optimizations.
bool markARCOptimizedReturnCallsAsNoTail() const override { return true; }

int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
  return 7;
}

bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                             llvm::Value *Address) const override {
  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);

  // 0-15 are the 16 integer registers.
  // 16 is %rip.
  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
  return false;
}

llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
                                StringRef Constraint,
                                llvm::Type* Ty) const override {
  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
}

bool isNoProtoCallVariadic(const CallArgList &args,
                           const FunctionNoProtoType *fnType) const override {
  // The default CC on x86-64 sets %al to the number of SSA
  // registers used, and GCC sets this when calling an unprototyped
  // function, so we override the default behavior.  However, don't do
  // that when AVX types are involved: the ABI explicitly states it is
  // undefined, and it doesn't work in practice because of how the ABI
  // defines varargs anyway.
  if (fnType->getCallConv() == CC_C) {
    bool HasAVXType = false;
    for (CallArgList::const_iterator
           it = args.begin(), ie = args.end(); it != ie; ++it) {
      if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
        HasAVXType = true;
        break;
      }
    }

    if (!HasAVXType)
      return true;
  }

  return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
}

llvm::Constant *
getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
  unsigned Sig = (0xeb << 0) | // jmp rel8
                 (0x06 << 8) | //           .+0x08
                 ('v' << 16) |
                 ('2' << 24);
  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
}

void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                         CodeGen::CodeGenModule &CGM) const override {
  if (GV->isDeclaration())
    return;
  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
    if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
      llvm::Function *Fn = cast<llvm::Function>(GV);
      Fn->addFnAttr("stackrealign");
    }

    addX86InterruptAttrs(FD, GV, CGM);
  }
}

void checkFunctionCallABI(CodeGenModule &CGM, SourceLocation CallLoc,
                          const FunctionDecl *Caller,
                          const FunctionDecl *Callee,
                          const CallArgList &Args) const override;
2507};

2509static void initFeatureMaps(const ASTContext &Ctx,
                          llvm::StringMap<bool> &CallerMap,
                          const FunctionDecl *Caller,
                          llvm::StringMap<bool> &CalleeMap,
                          const FunctionDecl *Callee) {
if (CalleeMap.empty() && CallerMap.empty()) {
  // The caller is potentially nullptr in the case where the call isn't in a
  // function.  In this case, the getFunctionFeatureMap ensures we just get
  // the TU level setting (since it cannot be modified by 'target'..
  Ctx.getFunctionFeatureMap(CallerMap, Caller);
  Ctx.getFunctionFeatureMap(CalleeMap, Callee);
}
2521}

2523static bool checkAVXParamFeature(DiagnosticsEngine &Diag,
                               SourceLocation CallLoc,
                               const llvm::StringMap<bool> &CallerMap,
                               const llvm::StringMap<bool> &CalleeMap,
                               QualType Ty, StringRef Feature,
                               bool IsArgument) {
bool CallerHasFeat = CallerMap.lookup(Feature);
bool CalleeHasFeat = CalleeMap.lookup(Feature);
if (!CallerHasFeat && !CalleeHasFeat)
  return Diag.Report(CallLoc, diag::warn_avx_calling_convention)
         << IsArgument << Ty << Feature;

// Mixing calling conventions here is very clearly an error.
if (!CallerHasFeat || !CalleeHasFeat)
  return Diag.Report(CallLoc, diag::err_avx_calling_convention)
         << IsArgument << Ty << Feature;

// Else, both caller and callee have the required feature, so there is no need
// to diagnose.
return false;
2543}

2545static bool checkAVXParam(DiagnosticsEngine &Diag, ASTContext &Ctx,
                        SourceLocation CallLoc,
                        const llvm::StringMap<bool> &CallerMap,
                        const llvm::StringMap<bool> &CalleeMap, QualType Ty,
                        bool IsArgument) {
uint64_t Size = Ctx.getTypeSize(Ty);
if (Size > 256)
  return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty,
                              "avx512f", IsArgument);

if (Size > 128)
  return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, "avx",
                              IsArgument);

return false;
2560}

2562void X86_64TargetCodeGenInfo::checkFunctionCallABI(
  CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDecl *Caller,
  const FunctionDecl *Callee, const CallArgList &Args) const {
llvm::StringMap<bool> CallerMap;
llvm::StringMap<bool> CalleeMap;
unsigned ArgIndex = 0;

// We need to loop through the actual call arguments rather than the the
// function's parameters, in case this variadic.
for (const CallArg &Arg : Args) {
  // The "avx" feature changes how vectors >128 in size are passed. "avx512f"
  // additionally changes how vectors >256 in size are passed. Like GCC, we
  // warn when a function is called with an argument where this will change.
  // Unlike GCC, we also error when it is an obvious ABI mismatch, that is,
  // the caller and callee features are mismatched.
  // Unfortunately, we cannot do this diagnostic in SEMA, since the callee can
  // change its ABI with attribute-target after this call.
  if (Arg.getType()->isVectorType() &&
      CGM.getContext().getTypeSize(Arg.getType()) > 128) {
    initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee);
    QualType Ty = Arg.getType();
    // The CallArg seems to have desugared the type already, so for clearer
    // diagnostics, replace it with the type in the FunctionDecl if possible.
    if (ArgIndex < Callee->getNumParams())
      Ty = Callee->getParamDecl(ArgIndex)->getType();

    if (checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap,
                      CalleeMap, Ty, /*IsArgument*/ true))
      return;
  }
  ++ArgIndex;
}

// Check return always, as we don't have a good way of knowing in codegen
// whether this value is used, tail-called, etc.
if (Callee->getReturnType()->isVectorType() &&
    CGM.getContext().getTypeSize(Callee->getReturnType()) > 128) {
  initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee);
  checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap,
                CalleeMap, Callee->getReturnType(),
                /*IsArgument*/ false);
}
2604}

2606static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
// If the argument does not end in .lib, automatically add the suffix.
// If the argument contains a space, enclose it in quotes.
// This matches the behavior of MSVC.
bool Quote = (Lib.find(' ') != StringRef::npos);
std::string ArgStr = Quote ? "\"" : "";
ArgStr += Lib;
if (!Lib.endswith_insensitive(".lib") && !Lib.endswith_insensitive(".a"))
  ArgStr += ".lib";
ArgStr += Quote ? "\"" : "";
return ArgStr;
2617}

2619class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2620public:
WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
      bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
      unsigned NumRegisterParameters)
  : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
      Win32StructABI, NumRegisterParameters, false) {}

void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                         CodeGen::CodeGenModule &CGM) const override;

void getDependentLibraryOption(llvm::StringRef Lib,
                               llvm::SmallString<24> &Opt) const override {
  Opt = "/DEFAULTLIB:";
  Opt += qualifyWindowsLibrary(Lib);
}

void getDetectMismatchOption(llvm::StringRef Name,
                             llvm::StringRef Value,
                             llvm::SmallString<32> &Opt) const override {
  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
}
2641};

2643static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                                        CodeGen::CodeGenModule &CGM) {
if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {

  if (CGM.getCodeGenOpts().StackProbeSize != 4096)
    Fn->addFnAttr("stack-probe-size",
                  llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
  if (CGM.getCodeGenOpts().NoStackArgProbe)
    Fn->addFnAttr("no-stack-arg-probe");
}
2653}

2655void WinX86_32TargetCodeGenInfo::setTargetAttributes(
  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
if (GV->isDeclaration())
  return;
addStackProbeTargetAttributes(D, GV, CGM);
2661}

2663class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2664public:
WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
                           X86AVXABILevel AVXLevel)
    : TargetCodeGenInfo(std::make_unique<WinX86_64ABIInfo>(CGT, AVXLevel)) {}

void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                         CodeGen::CodeGenModule &CGM) const override;

int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
  return 7;
}

bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                             llvm::Value *Address) const override {
  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);

  // 0-15 are the 16 integer registers.
  // 16 is %rip.
  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
  return false;
}

void getDependentLibraryOption(llvm::StringRef Lib,
                               llvm::SmallString<24> &Opt) const override {
  Opt = "/DEFAULTLIB:";
  Opt += qualifyWindowsLibrary(Lib);
}

void getDetectMismatchOption(llvm::StringRef Name,
                             llvm::StringRef Value,
                             llvm::SmallString<32> &Opt) const override {
  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
}
2697};

2699void WinX86_64TargetCodeGenInfo::setTargetAttributes(
  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
if (GV->isDeclaration())
  return;
if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
    llvm::Function *Fn = cast<llvm::Function>(GV);
    Fn->addFnAttr("stackrealign");
  }

  addX86InterruptAttrs(FD, GV, CGM);
}

addStackProbeTargetAttributes(D, GV, CGM);
2714}
2715}

2717void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
                            Class &Hi) const {
// AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
//
// (a) If one of the classes is Memory, the whole argument is passed in
//     memory.
//
// (b) If X87UP is not preceded by X87, the whole argument is passed in
//     memory.
//
// (c) If the size of the aggregate exceeds two eightbytes and the first
//     eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
//     argument is passed in memory. NOTE: This is necessary to keep the
//     ABI working for processors that don't support the __m256 type.
//
// (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
//
// Some of these are enforced by the merging logic.  Others can arise
// only with unions; for example:
//   union { _Complex double; unsigned; }
//
// Note that clauses (b) and (c) were added in 0.98.
//
if (Hi == Memory)
  Lo = Memory;
if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
  Lo = Memory;
if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
  Lo = Memory;
if (Hi == SSEUp && Lo != SSE)
  Hi = SSE;
2748}

2750X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
// AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
// classified recursively so that always two fields are
// considered. The resulting class is calculated according to
// the classes of the fields in the eightbyte:
//
// (a) If both classes are equal, this is the resulting class.
//
// (b) If one of the classes is NO_CLASS, the resulting class is
// the other class.
//
// (c) If one of the classes is MEMORY, the result is the MEMORY
// class.
//
// (d) If one of the classes is INTEGER, the result is the
// INTEGER.
//
// (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
// MEMORY is used as class.
//
// (f) Otherwise class SSE is used.

// Accum should never be memory (we should have returned) or
// ComplexX87 (because this cannot be passed in a structure).
assert((Accum != Memory && Accum != ComplexX87) &&((void)0)
       "Invalid accumulated classification during merge.")((void)0);
if (Accum == Field || Field == NoClass)
  return Accum;
if (Field == Memory)
  return Memory;
if (Accum == NoClass)
  return Field;
if (Accum == Integer || Field == Integer)
  return Integer;
if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
    Accum == X87 || Accum == X87Up)
  return Memory;
return SSE;
2788}

2790void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
                           Class &Lo, Class &Hi, bool isNamedArg) const {
// FIXME: This code can be simplified by introducing a simple value class for
// Class pairs with appropriate constructor methods for the various
// situations.

// FIXME: Some of the split computations are wrong; unaligned vectors
// shouldn't be passed in registers for example, so there is no chance they
// can straddle an eightbyte. Verify & simplify.

Lo = Hi = NoClass;

Class &Current = OffsetBase < 64 ? Lo : Hi;
Current = Memory;

if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
  BuiltinType::Kind k = BT->getKind();

  if (k == BuiltinType::Void) {
    Current = NoClass;
  } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
    Lo = Integer;
    Hi = Integer;
  } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
    Current = Integer;
  } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
    Current = SSE;
  } else if (k == BuiltinType::LongDouble) {
    const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
    if (LDF == &llvm::APFloat::IEEEquad()) {
      Lo = SSE;
      Hi = SSEUp;
    } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
      Lo = X87;
      Hi = X87Up;
    } else if (LDF == &llvm::APFloat::IEEEdouble()) {
      Current = SSE;
    } else
      llvm_unreachable("unexpected long double representation!")__builtin_unreachable();
  }
  // FIXME: _Decimal32 and _Decimal64 are SSE.
  // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
  return;
}

if (const EnumType *ET = Ty->getAs<EnumType>()) {
  // Classify the underlying integer type.
  classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
  return;
}

if (Ty->hasPointerRepresentation()) {
  Current = Integer;
  return;
}

if (Ty->isMemberPointerType()) {
  if (Ty->isMemberFunctionPointerType()) {
    if (Has64BitPointers) {
      // If Has64BitPointers, this is an {i64, i64}, so classify both
      // Lo and Hi now.
      Lo = Hi = Integer;
    } else {
      // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
      // straddles an eightbyte boundary, Hi should be classified as well.
      uint64_t EB_FuncPtr = (OffsetBase) / 64;
      uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
      if (EB_FuncPtr != EB_ThisAdj) {
        Lo = Hi = Integer;
      } else {
        Current = Integer;
      }
    }
  } else {
    Current = Integer;
  }
  return;
}

if (const VectorType *VT = Ty->getAs<VectorType>()) {
  uint64_t Size = getContext().getTypeSize(VT);
  if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
    // gcc passes the following as integer:
    // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
    // 2 bytes - <2 x char>, <1 x short>
    // 1 byte  - <1 x char>
    Current = Integer;

    // If this type crosses an eightbyte boundary, it should be
    // split.
    uint64_t EB_Lo = (OffsetBase) / 64;
    uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
    if (EB_Lo != EB_Hi)
      Hi = Lo;
  } else if (Size == 64) {
    QualType ElementType = VT->getElementType();

    // gcc passes <1 x double> in memory. :(
    if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
      return;

    // gcc passes <1 x long long> as SSE but clang used to unconditionally
    // pass them as integer.  For platforms where clang is the de facto
    // platform compiler, we must continue to use integer.
    if (!classifyIntegerMMXAsSSE() &&
        (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
         ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
         ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
         ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
      Current = Integer;
    else
      Current = SSE;

    // If this type crosses an eightbyte boundary, it should be
    // split.
    if (OffsetBase && OffsetBase != 64)
      Hi = Lo;
  } else if (Size == 128 ||
             (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
    QualType ElementType = VT->getElementType();

    // gcc passes 256 and 512 bit <X x __int128> vectors in memory. :(
    if (passInt128VectorsInMem() && Size != 128 &&
        (ElementType->isSpecificBuiltinType(BuiltinType::Int128) ||
         ElementType->isSpecificBuiltinType(BuiltinType::UInt128)))
      return;

    // Arguments of 256-bits are split into four eightbyte chunks. The
    // least significant one belongs to class SSE and all the others to class
    // SSEUP. The original Lo and Hi design considers that types can't be
    // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
    // This design isn't correct for 256-bits, but since there're no cases
    // where the upper parts would need to be inspected, avoid adding
    // complexity and just consider Hi to match the 64-256 part.
    //
    // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
    // registers if they are "named", i.e. not part of the "..." of a
    // variadic function.
    //
    // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
    // split into eight eightbyte chunks, one SSE and seven SSEUP.
    Lo = SSE;
    Hi = SSEUp;
  }
  return;
}

if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
  QualType ET = getContext().getCanonicalType(CT->getElementType());

  uint64_t Size = getContext().getTypeSize(Ty);
  if (ET->isIntegralOrEnumerationType()) {
    if (Size <= 64)
      Current = Integer;
    else if (Size <= 128)
      Lo = Hi = Integer;
  } else if (ET == getContext().FloatTy) {
    Current = SSE;
  } else if (ET == getContext().DoubleTy) {
    Lo = Hi = SSE;
  } else if (ET == getContext().LongDoubleTy) {
    const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
    if (LDF == &llvm::APFloat::IEEEquad())
      Current = Memory;
    else if (LDF == &llvm::APFloat::x87DoubleExtended())
      Current = ComplexX87;
    else if (LDF == &llvm::APFloat::IEEEdouble())
      Lo = Hi = SSE;
    else
      llvm_unreachable("unexpected long double representation!")__builtin_unreachable();
  }

  // If this complex type crosses an eightbyte boundary then it
  // should be split.
  uint64_t EB_Real = (OffsetBase) / 64;
  uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
  if (Hi == NoClass && EB_Real != EB_Imag)
    Hi = Lo;

  return;
}

if (const auto *EITy = Ty->getAs<ExtIntType>()) {
  if (EITy->getNumBits() <= 64)
    Current = Integer;
  else if (EITy->getNumBits() <= 128)
    Lo = Hi = Integer;
  // Larger values need to get passed in memory.
  return;
}

if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
  // Arrays are treated like structures.

  uint64_t Size = getContext().getTypeSize(Ty);

  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
  // than eight eightbytes, ..., it has class MEMORY.
  if (Size > 512)
    return;

  // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
  // fields, it has class MEMORY.
  //
  // Only need to check alignment of array base.
  if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
    return;

  // Otherwise implement simplified merge. We could be smarter about
  // this, but it isn't worth it and would be harder to verify.
  Current = NoClass;
  uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
  uint64_t ArraySize = AT->getSize().getZExtValue();

  // The only case a 256-bit wide vector could be used is when the array
  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
  // to work for sizes wider than 128, early check and fallback to memory.
  //
  if (Size > 128 &&
      (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
    return;

  for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
    Class FieldLo, FieldHi;
    classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
    Lo = merge(Lo, FieldLo);
    Hi = merge(Hi, FieldHi);
    if (Lo == Memory || Hi == Memory)
      break;
  }

  postMerge(Size, Lo, Hi);
  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.")((void)0);
  return;
}

if (const RecordType *RT = Ty->getAs<RecordType>()) {
  uint64_t Size = getContext().getTypeSize(Ty);

  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
  // than eight eightbytes, ..., it has class MEMORY.
  if (Size > 512)
    return;

  // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
  // copy constructor or a non-trivial destructor, it is passed by invisible
  // reference.
  if (getRecordArgABI(RT, getCXXABI()))
    return;

  const RecordDecl *RD = RT->getDecl();

  // Assume variable sized types are passed in memory.
  if (RD->hasFlexibleArrayMember())
    return;

  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);

  // Reset Lo class, this will be recomputed.
  Current = NoClass;

  // If this is a C++ record, classify the bases first.
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
    for (const auto &I : CXXRD->bases()) {
      assert(!I.isVirtual() && !I.getType()->isDependentType() &&((void)0)
             "Unexpected base class!")((void)0);
      const auto *Base =
          cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());

      // Classify this field.
      //
      // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
      // single eightbyte, each is classified separately. Each eightbyte gets
      // initialized to class NO_CLASS.
      Class FieldLo, FieldHi;
      uint64_t Offset =
        OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
      classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
      Lo = merge(Lo, FieldLo);
      Hi = merge(Hi, FieldHi);
      if (Lo == Memory || Hi == Memory) {
        postMerge(Size, Lo, Hi);
        return;
      }
    }
  }

  // Classify the fields one at a time, merging the results.
  unsigned idx = 0;
  bool UseClang11Compat = getContext().getLangOpts().getClangABICompat() <=
                              LangOptions::ClangABI::Ver11 ||
                          getContext().getTargetInfo().getTriple().isPS4();
  bool IsUnion = RT->isUnionType() && !UseClang11Compat;

  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
         i != e; ++i, ++idx) {
    uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
    bool BitField = i->isBitField();

    // Ignore padding bit-fields.
    if (BitField && i->isUnnamedBitfield())
      continue;

    // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
    // eight eightbytes, or it contains unaligned fields, it has class MEMORY.
    //
    // The only case a 256-bit or a 512-bit wide vector could be used is when
    // the struct contains a single 256-bit or 512-bit element. Early check
    // and fallback to memory.
    //
    // FIXME: Extended the Lo and Hi logic properly to work for size wider
    // than 128.
    if (Size > 128 &&
        ((!IsUnion && Size != getContext().getTypeSize(i->getType())) ||
         Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
      Lo = Memory;
      postMerge(Size, Lo, Hi);
      return;
    }
    // Note, skip this test for bit-fields, see below.
    if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
      Lo = Memory;
      postMerge(Size, Lo, Hi);
      return;
    }

    // Classify this field.
    //
    // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
    // exceeds a single eightbyte, each is classified
    // separately. Each eightbyte gets initialized to class
    // NO_CLASS.
    Class FieldLo, FieldHi;

    // Bit-fields require special handling, they do not force the
    // structure to be passed in memory even if unaligned, and
    // therefore they can straddle an eightbyte.
    if (BitField) {
      assert(!i->isUnnamedBitfield())((void)0);
      uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
      uint64_t Size = i->getBitWidthValue(getContext());

      uint64_t EB_Lo = Offset / 64;
      uint64_t EB_Hi = (Offset + Size - 1) / 64;

      if (EB_Lo) {
        assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.")((void)0);
        FieldLo = NoClass;
        FieldHi = Integer;
      } else {
        FieldLo = Integer;
        FieldHi = EB_Hi ? Integer : NoClass;
      }
    } else
      classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
    Lo = merge(Lo, FieldLo);
    Hi = merge(Hi, FieldHi);
    if (Lo == Memory || Hi == Memory)
      break;
  }

  postMerge(Size, Lo, Hi);
}
3153}

3155ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
// If this is a scalar LLVM value then assume LLVM will pass it in the right
// place naturally.
if (!isAggregateTypeForABI(Ty)) {
  // Treat an enum type as its underlying type.
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
    Ty = EnumTy->getDecl()->getIntegerType();

  if (Ty->isExtIntType())
    return getNaturalAlignIndirect(Ty);

  return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
                                            : ABIArgInfo::getDirect());
}

return getNaturalAlignIndirect(Ty);
3171}

3173bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
  uint64_t Size = getContext().getTypeSize(VecTy);
  unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
  if (Size <= 64 || Size > LargestVector)
    return true;
  QualType EltTy = VecTy->getElementType();
  if (passInt128VectorsInMem() &&
      (EltTy->isSpecificBuiltinType(BuiltinType::Int128) ||
       EltTy->isSpecificBuiltinType(BuiltinType::UInt128)))
    return true;
}

return false;
3187}

3189ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
                                          unsigned freeIntRegs) const {
// If this is a scalar LLVM value then assume LLVM will pass it in the right
// place naturally.
//
// This assumption is optimistic, as there could be free registers available
// when we need to pass this argument in memory, and LLVM could try to pass
// the argument in the free register. This does not seem to happen currently,
// but this code would be much safer if we could mark the argument with
// 'onstack'. See PR12193.
if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty) &&
    !Ty->isExtIntType()) {
  // Treat an enum type as its underlying type.
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
    Ty = EnumTy->getDecl()->getIntegerType();

  return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
                                            : ABIArgInfo::getDirect());
}

if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
  return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);

// Compute the byval alignment. We specify the alignment of the byval in all
// cases so that the mid-level optimizer knows the alignment of the byval.
unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);

// Attempt to avoid passing indirect results using byval when possible. This
// is important for good codegen.
//
// We do this by coercing the value into a scalar type which the backend can
// handle naturally (i.e., without using byval).
//
// For simplicity, we currently only do this when we have exhausted all of the
// free integer registers. Doing this when there are free integer registers
// would require more care, as we would have to ensure that the coerced value
// did not claim the unused register. That would require either reording the
// arguments to the function (so that any subsequent inreg values came first),
// or only doing this optimization when there were no following arguments that
// might be inreg.
//
// We currently expect it to be rare (particularly in well written code) for
// arguments to be passed on the stack when there are still free integer
// registers available (this would typically imply large structs being passed
// by value), so this seems like a fair tradeoff for now.
//
// We can revisit this if the backend grows support for 'onstack' parameter
// attributes. See PR12193.
if (freeIntRegs == 0) {
  uint64_t Size = getContext().getTypeSize(Ty);

  // If this type fits in an eightbyte, coerce it into the matching integral
  // type, which will end up on the stack (with alignment 8).
  if (Align == 8 && Size <= 64)
    return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
                                                        Size));
}

return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align));
3248}

3250/// The ABI specifies that a value should be passed in a full vector XMM/YMM
3251/// register. Pick an LLVM IR type that will be passed as a vector register.
3252llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
// Wrapper structs/arrays that only contain vectors are passed just like
// vectors; strip them off if present.
if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
  Ty = QualType(InnerTy, 0);

llvm::Type *IRType = CGT.ConvertType(Ty);
if (isa<llvm::VectorType>(IRType)) {
  // Don't pass vXi128 vectors in their native type, the backend can't
  // legalize them.
  if (passInt128VectorsInMem() &&
      cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy(128)) {
    // Use a vXi64 vector.
    uint64_t Size = getContext().getTypeSize(Ty);
    return llvm::FixedVectorType::get(llvm::Type::getInt64Ty(getVMContext()),
                                      Size / 64);
  }

  return IRType;
}

if (IRType->getTypeID() == llvm::Type::FP128TyID)
  return IRType;

// We couldn't find the preferred IR vector type for 'Ty'.
uint64_t Size = getContext().getTypeSize(Ty);
assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!")((void)0);


// Return a LLVM IR vector type based on the size of 'Ty'.
return llvm::FixedVectorType::get(llvm::Type::getDoubleTy(getVMContext()),
                                  Size / 64);
3284}

3286/// BitsContainNoUserData - Return true if the specified [start,end) bit range
3287/// is known to either be off the end of the specified type or being in
3288/// alignment padding.  The user type specified is known to be at most 128 bits
3289/// in size, and have passed through X86_64ABIInfo::classify with a successful
3290/// classification that put one of the two halves in the INTEGER class.
3291///
3292/// It is conservatively correct to return false.
3293static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
                                unsigned EndBit, ASTContext &Context) {
// If the bytes being queried are off the end of the type, there is no user
// data hiding here.  This handles analysis of builtins, vectors and other
// types that don't contain interesting padding.
unsigned TySize = (unsigned)Context.getTypeSize(Ty);
if (TySize <= StartBit)
  return true;

if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
  unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
  unsigned NumElts = (unsigned)AT->getSize().getZExtValue();

  // Check each element to see if the element overlaps with the queried range.
  for (unsigned i = 0; i != NumElts; ++i) {
    // If the element is after the span we care about, then we're done..
    unsigned EltOffset = i*EltSize;
    if (EltOffset >= EndBit) break;

    unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
    if (!BitsContainNoUserData(AT->getElementType(), EltStart,
                               EndBit-EltOffset, Context))
      return false;
  }
  // If it overlaps no elements, then it is safe to process as padding.
  return true;
}

if (const RecordType *RT = Ty->getAs<RecordType>()) {
  const RecordDecl *RD = RT->getDecl();
  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);

  // If this is a C++ record, check the bases first.
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
    for (const auto &I : CXXRD->bases()) {
      assert(!I.isVirtual() && !I.getType()->isDependentType() &&((void)0)
             "Unexpected base class!")((void)0);
      const auto *Base =
          cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());

      // If the base is after the span we care about, ignore it.
      unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
      if (BaseOffset >= EndBit) continue;

      unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
      if (!BitsContainNoUserData(I.getType(), BaseStart,
                                 EndBit-BaseOffset, Context))
        return false;
    }
  }

  // Verify that no field has data that overlaps the region of interest.  Yes
  // this could be sped up a lot by being smarter about queried fields,
  // however we're only looking at structs up to 16 bytes, so we don't care
  // much.
  unsigned idx = 0;
  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
       i != e; ++i, ++idx) {
    unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);

    // If we found a field after the region we care about, then we're done.
    if (FieldOffset >= EndBit) break;

    unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
    if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
                               Context))
      return false;
  }

  // If nothing in this record overlapped the area of interest, then we're
  // clean.
  return true;
}

return false;
3368}

3370/// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3371/// float member at the specified offset.  For example, {int,{float}} has a
3372/// float at offset 4.  It is conservatively correct for this routine to return
3373/// false.
3374static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
                                const llvm::DataLayout &TD) {
// Base case if we find a float.
if (IROffset == 0 && IRType->isFloatTy())
  return true;

// If this is a struct, recurse into the field at the specified offset.
if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
  const llvm::StructLayout *SL = TD.getStructLayout(STy);
  unsigned Elt = SL->getElementContainingOffset(IROffset);
  IROffset -= SL->getElementOffset(Elt);
  return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
}

// If this is an array, recurse into the field at the specified offset.
if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
  llvm::Type *EltTy = ATy->getElementType();
  unsigned EltSize = TD.getTypeAllocSize(EltTy);
  IROffset -= IROffset/EltSize*EltSize;
  return ContainsFloatAtOffset(EltTy, IROffset, TD);
}

return false;
3397}


3400/// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3401/// low 8 bytes of an XMM register, corresponding to the SSE class.
3402llvm::Type *X86_64ABIInfo::
3403GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
                 QualType SourceTy, unsigned SourceOffset) const {
// The only three choices we have are either double, <2 x float>, or float. We
// pass as float if the last 4 bytes is just padding.  This happens for
// structs that contain 3 floats.
if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
                          SourceOffset*8+64, getContext()))
  return llvm::Type::getFloatTy(getVMContext());

// We want to pass as <2 x float> if the LLVM IR type contains a float at
// offset+0 and offset+4.  Walk the LLVM IR type to find out if this is the
// case.
if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
    ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
  return llvm::FixedVectorType::get(llvm::Type::getFloatTy(getVMContext()),
                                    2);

return llvm::Type::getDoubleTy(getVMContext());
3421}


3424/// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3425/// an 8-byte GPR.  This means that we either have a scalar or we are talking
3426/// about the high or low part of an up-to-16-byte struct.  This routine picks
3427/// the best LLVM IR type to represent this, which may be i64 or may be anything
3428/// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3429/// etc).
3430///
3431/// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3432/// the source type.  IROffset is an offset in bytes into the LLVM IR type that
3433/// the 8-byte value references.  PrefType may be null.
3434///
3435/// SourceTy is the source-level type for the entire argument.  SourceOffset is
3436/// an offset into this that we're processing (which is always either 0 or 8).
3437///
3438llvm::Type *X86_64ABIInfo::
3439GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
                     QualType SourceTy, unsigned SourceOffset) const {
// If we're dealing with an un-offset LLVM IR type, then it means that we're
// returning an 8-byte unit starting with it.  See if we can safely use it.
if (IROffset == 0) {
  // Pointers and int64's always fill the 8-byte unit.
  if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
      IRType->isIntegerTy(64))
    return IRType;

  // If we have a 1/2/4-byte integer, we can use it only if the rest of the
  // goodness in the source type is just tail padding.  This is allowed to
  // kick in for struct {double,int} on the int, but not on
  // struct{double,int,int} because we wouldn't return the second int.  We
  // have to do this analysis on the source type because we can't depend on
  // unions being lowered a specific way etc.
  if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
      IRType->isIntegerTy(32) ||
      (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
    unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
        cast<llvm::IntegerType>(IRType)->getBitWidth();

    if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
                              SourceOffset*8+64, getContext()))
      return IRType;
  }
}

if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
  // If this is a struct, recurse into the field at the specified offset.
  const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
  if (IROffset < SL->getSizeInBytes()) {
    unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
    IROffset -= SL->getElementOffset(FieldIdx);

    return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
                                  SourceTy, SourceOffset);
  }
}

if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
  llvm::Type *EltTy = ATy->getElementType();
  unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
  unsigned EltOffset = IROffset/EltSize*EltSize;
  return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
                                SourceOffset);
}

// Okay, we don't have any better idea of what to pass, so we pass this in an
// integer register that isn't too big to fit the rest of the struct.
unsigned TySizeInBytes =
  (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();

assert(TySizeInBytes != SourceOffset && "Empty field?")((void)0);

// It is always safe to classify this as an integer type up to i64 that
// isn't larger than the structure.
return llvm::IntegerType::get(getVMContext(),
                              std::min(TySizeInBytes-SourceOffset, 8U)*8);
3498}


3501/// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3502/// be used as elements of a two register pair to pass or return, return a
3503/// first class aggregate to represent them.  For example, if the low part of
3504/// a by-value argument should be passed as i32* and the high part as float,
3505/// return {i32*, float}.
3506static llvm::Type *
3507GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
                         const llvm::DataLayout &TD) {
// In order to correctly satisfy the ABI, we need to the high part to start
// at offset 8.  If the high and low parts we inferred are both 4-byte types
// (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
// the second element at offset 8.  Check for this:
unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
unsigned HiAlign = TD.getABITypeAlignment(Hi);
unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!")((void)0);

// To handle this, we have to increase the size of the low part so that the
// second element will start at an 8 byte offset.  We can't increase the size
// of the second element because it might make us access off the end of the
// struct.
if (HiStart != 8) {
  // There are usually two sorts of types the ABI generation code can produce
  // for the low part of a pair that aren't 8 bytes in size: float or
  // i8/i16/i32.  This can also include pointers when they are 32-bit (X32 and
  // NaCl).
  // Promote these to a larger type.
  if (Lo->isFloatTy())
    Lo = llvm::Type::getDoubleTy(Lo->getContext());
  else {
    assert((Lo->isIntegerTy() || Lo->isPointerTy())((void)0)
           && "Invalid/unknown lo type")((void)0);
    Lo = llvm::Type::getInt64Ty(Lo->getContext());
  }
}

llvm::StructType *Result = llvm::StructType::get(Lo, Hi);

// Verify that the second element is at an 8-byte offset.
assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&((void)0)
       "Invalid x86-64 argument pair!")((void)0);
return Result;
3543}

3545ABIArgInfo X86_64ABIInfo::
3546classifyReturnType(QualType RetTy) const {
// AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
// classification algorithm.
X86_64ABIInfo::Class Lo, Hi;
classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);

// Check some invariants.
assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.")((void)0);
assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.")((void)0);

llvm::Type *ResType = nullptr;
switch (Lo) {
case NoClass:
  if (Hi == NoClass)
    return ABIArgInfo::getIgnore();
  // If the low part is just padding, it takes no register, leave ResType
  // null.
  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&((void)0)
         "Unknown missing lo part")((void)0);
  break;

case SSEUp:
case X87Up:
  llvm_unreachable("Invalid classification for lo word.")__builtin_unreachable();

  // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
  // hidden argument.
case Memory:
  return getIndirectReturnResult(RetTy);

  // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
  // available register of the sequence %rax, %rdx is used.
case Integer:
  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);

  // If we have a sign or zero extended integer, make sure to return Extend
  // so that the parameter gets the right LLVM IR attributes.
  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
    // Treat an enum type as its underlying type.
    if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
      RetTy = EnumTy->getDecl()->getIntegerType();

    if (RetTy->isIntegralOrEnumerationType() &&
        isPromotableIntegerTypeForABI(RetTy))
      return ABIArgInfo::getExtend(RetTy);
  }
  break;

  // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
  // available SSE register of the sequence %xmm0, %xmm1 is used.
case SSE:
  ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
  break;

  // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
  // returned on the X87 stack in %st0 as 80-bit x87 number.
case X87:
  ResType = llvm::Type::getX86_FP80Ty(getVMContext());
  break;

  // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
  // part of the value is returned in %st0 and the imaginary part in
  // %st1.
case ComplexX87:
  assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.")((void)0);
  ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
                                  llvm::Type::getX86_FP80Ty(getVMContext()));
  break;
}

llvm::Type *HighPart = nullptr;
switch (Hi) {
  // Memory was handled previously and X87 should
  // never occur as a hi class.
case Memory:
case X87:
  llvm_unreachable("Invalid classification for hi word.")__builtin_unreachable();

case ComplexX87: // Previously handled.
case NoClass:
  break;

case Integer:
  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
  if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
    return ABIArgInfo::getDirect(HighPart, 8);
  break;
case SSE:
  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
  if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
    return ABIArgInfo::getDirect(HighPart, 8);
  break;

  // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
  // is passed in the next available eightbyte chunk if the last used
  // vector register.
  //
  // SSEUP should always be preceded by SSE, just widen.
case SSEUp:
  assert(Lo == SSE && "Unexpected SSEUp classification.")((void)0);
  ResType = GetByteVectorType(RetTy);
  break;

  // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
  // returned together with the previous X87 value in %st0.
case X87Up:
  // If X87Up is preceded by X87, we don't need to do
  // anything. However, in some cases with unions it may not be
  // preceded by X87. In such situations we follow gcc and pass the
  // extra bits in an SSE reg.
  if (Lo != X87) {
    HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
    if (Lo == NoClass)  // Return HighPart at offset 8 in memory.
      return ABIArgInfo::getDirect(HighPart, 8);
  }
  break;
}

// If a high part was specified, merge it together with the low part.  It is
// known to pass in the high eightbyte of the result.  We do this by forming a
// first class struct aggregate with the high and low part: {low, high}
if (HighPart)
  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());

return ABIArgInfo::getDirect(ResType);
3671}

3673ABIArgInfo X86_64ABIInfo::classifyArgumentType(
QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
bool isNamedArg)
const
3677{
Ty = useFirstFieldIfTransparentUnion(Ty);

X86_64ABIInfo::Class Lo, Hi;
classify(Ty, 0, Lo, Hi, isNamedArg);

// Check some invariants.
// FIXME: Enforce these by construction.
assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.")((void)0);
assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.")((void)0);

neededInt = 0;
neededSSE = 0;
llvm::Type *ResType = nullptr;
switch (Lo) {
case NoClass:
  if (Hi == NoClass)
    return ABIArgInfo::getIgnore();
  // If the low part is just padding, it takes no register, leave ResType
  // null.
  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&((void)0)
         "Unknown missing lo part")((void)0);
  break;

  // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
  // on the stack.
case Memory:

  // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
  // COMPLEX_X87, it is passed in memory.
case X87:
case ComplexX87:
  if (getRecordArgABI(Ty, getCXXABI()) == CGCXXABI::RAA_Indirect)
    ++neededInt;
  return getIndirectResult(Ty, freeIntRegs);

case SSEUp:
case X87Up:
  llvm_unreachable("Invalid classification for lo word.")__builtin_unreachable();

  // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
  // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
  // and %r9 is used.
case Integer:
  ++neededInt;

  // Pick an 8-byte type based on the preferred type.
  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);

  // If we have a sign or zero extended integer, make sure to return Extend
  // so that the parameter gets the right LLVM IR attributes.
  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
    // Treat an enum type as its underlying type.
    if (const EnumType *EnumTy = Ty->getAs<EnumType>())
      Ty = EnumTy->getDecl()->getIntegerType();

    if (Ty->isIntegralOrEnumerationType() &&
        isPromotableIntegerTypeForABI(Ty))
      return ABIArgInfo::getExtend(Ty);
  }

  break;

  // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
  // available SSE register is used, the registers are taken in the
  // order from %xmm0 to %xmm7.
case SSE: {
  llvm::Type *IRType = CGT.ConvertType(Ty);
  ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
  ++neededSSE;
  break;
}
}

llvm::Type *HighPart = nullptr;
switch (Hi) {
  // Memory was handled previously, ComplexX87 and X87 should
  // never occur as hi classes, and X87Up must be preceded by X87,
  // which is passed in memory.
case Memory:
case X87:
case ComplexX87:
  llvm_unreachable("Invalid classification for hi word.")__builtin_unreachable();

case NoClass: break;

case Integer:
  ++neededInt;
  // Pick an 8-byte type based on the preferred type.
  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);

  if (Lo == NoClass)  // Pass HighPart at offset 8 in memory.
    return ABIArgInfo::getDirect(HighPart, 8);
  break;

  // X87Up generally doesn't occur here (long double is passed in
  // memory), except in situations involving unions.
case X87Up:
case SSE:
  HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);

  if (Lo == NoClass)  // Pass HighPart at offset 8 in memory.
    return ABIArgInfo::getDirect(HighPart, 8);

  ++neededSSE;
  break;

  // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
  // eightbyte is passed in the upper half of the last used SSE
  // register.  This only happens when 128-bit vectors are passed.
case SSEUp:
  assert(Lo == SSE && "Unexpected SSEUp classification")((void)0);
  ResType = GetByteVectorType(Ty);
  break;
}

// If a high part was specified, merge it together with the low part.  It is
// known to pass in the high eightbyte of the result.  We do this by forming a
// first class struct aggregate with the high and low part: {low, high}
if (HighPart)
  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());

return ABIArgInfo::getDirect(ResType);
3800}

3802ABIArgInfo
3803X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
                                           unsigned &NeededSSE) const {
auto RT = Ty->getAs<RecordType>();
12
←
Assuming the object is not a 'RecordType'→
13
←
'RT' initialized to a null pointer value→
assert(RT && "classifyRegCallStructType only valid with struct types")((void)0);

if (RT->getDecl()->hasFlexibleArrayMember())
14
←
Called C++ object pointer is null
  return getIndirectReturnResult(Ty);

// Sum up bases
if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
  if (CXXRD->isDynamicClass()) {
    NeededInt = NeededSSE = 0;
    return getIndirectReturnResult(Ty);
  }

  for (const auto &I : CXXRD->bases())
    if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
            .isIndirect()) {
      NeededInt = NeededSSE = 0;
      return getIndirectReturnResult(Ty);
    }
}

// Sum up members
for (const auto *FD : RT->getDecl()->fields()) {
  if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
    if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
            .isIndirect()) {
      NeededInt = NeededSSE = 0;
      return getIndirectReturnResult(Ty);
    }
  } else {
    unsigned LocalNeededInt, LocalNeededSSE;
    if (classifyArgumentType(FD->getType(), UINT_MAX(2147483647 *2U +1U), LocalNeededInt,
                             LocalNeededSSE, true)
            .isIndirect()) {
      NeededInt = NeededSSE = 0;
      return getIndirectReturnResult(Ty);
    }
    NeededInt += LocalNeededInt;
    NeededSSE += LocalNeededSSE;
  }
}

return ABIArgInfo::getDirect();
3848}

3850ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
                                                  unsigned &NeededInt,
                                                  unsigned &NeededSSE) const {

NeededInt = 0;
NeededSSE = 0;

return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
11
←
Calling 'X86_64ABIInfo::classifyRegCallStructTypeImpl'→
3858}

3860void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {

const unsigned CallingConv = FI.getCallingConvention();
// It is possible to force Win64 calling convention on any x86_64 target by
// using __attribute__((ms_abi)). In such case to correctly emit Win64
// compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
if (CallingConv == llvm::CallingConv::Win64) {
1
Assuming 'CallingConv' is not equal to Win64→
2
←
Taking false branch→
  WinX86_64ABIInfo Win64ABIInfo(CGT, AVXLevel);
  Win64ABIInfo.computeInfo(FI);
  return;
}

bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3
←
Assuming 'CallingConv' is equal to X86_RegCall→

// Keep track of the number of assigned registers.
unsigned FreeIntRegs = IsRegCall3.1
'IsRegCall' is true
 ? 11 : 6;
4
←
'?' condition is true→
unsigned FreeSSERegs = IsRegCall4.1
'IsRegCall' is true
 ? 16 : 8;
5
←
'?' condition is true→
unsigned NeededInt, NeededSSE;

if (!::classifyReturnType(getCXXABI(), FI, *this)) {
6
←
Assuming the condition is true→
7
←
Taking true branch→
  if (IsRegCall7.1
'IsRegCall' is true
 && FI.getReturnType()->getTypePtr()->isRecordType() &&
9
←
Taking true branch→
      !FI.getReturnType()->getTypePtr()->isUnionType()) {
8
←
Assuming the condition is true→
    FI.getReturnInfo() =
        classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
10
←
Calling 'X86_64ABIInfo::classifyRegCallStructType'→
    if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
      FreeIntRegs -= NeededInt;
      FreeSSERegs -= NeededSSE;
    } else {
      FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
    }
  } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>() &&
             getContext().getCanonicalType(FI.getReturnType()
                                               ->getAs<ComplexType>()
                                               ->getElementType()) ==
                 getContext().LongDoubleTy)
    // Complex Long Double Type is passed in Memory when Regcall
    // calling convention is used.
    FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
  else
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
}

// If the return value is indirect, then the hidden argument is consuming one
// integer register.
if (FI.getReturnInfo().isIndirect())
  --FreeIntRegs;

// The chain argument effectively gives us another free register.
if (FI.isChainCall())
  ++FreeIntRegs;

unsigned NumRequiredArgs = FI.getNumRequiredArgs();
// AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
// get assigned (in left-to-right order) for passing as follows...
unsigned ArgNo = 0;
for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
     it != ie; ++it, ++ArgNo) {
  bool IsNamedArg = ArgNo < NumRequiredArgs;

  if (IsRegCall && it->type->isStructureOrClassType())
    it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
  else
    it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
                                    NeededSSE, IsNamedArg);

  // AMD64-ABI 3.2.3p3: If there are no registers available for any
  // eightbyte of an argument, the whole argument is passed on the
  // stack. If registers have already been assigned for some
  // eightbytes of such an argument, the assignments get reverted.
  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
    FreeIntRegs -= NeededInt;
    FreeSSERegs -= NeededSSE;
  } else {
    it->info = getIndirectResult(it->type, FreeIntRegs);
  }
}
3936}

3938static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF,
                                       Address VAListAddr, QualType Ty) {
Address overflow_arg_area_p =
    CGF.Builder.CreateStructGEP(VAListAddr, 2, "overflow_arg_area_p");
llvm::Value *overflow_arg_area =
  CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");

// AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
// byte boundary if alignment needed by type exceeds 8 byte boundary.
// It isn't stated explicitly in the standard, but in practice we use
// alignment greater than 16 where necessary.
CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
if (Align > CharUnits::fromQuantity(8)) {
  overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
                                                    Align);
}

// AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
llvm::Value *Res =
  CGF.Builder.CreateBitCast(overflow_arg_area,
                            llvm::PointerType::getUnqual(LTy));

// AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
// l->overflow_arg_area + sizeof(type).
// AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
// an 8 byte boundary.

uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
llvm::Value *Offset =
    llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7)  & ~7);
overflow_arg_area = CGF.Builder.CreateGEP(CGF.Int8Ty, overflow_arg_area,
                                          Offset, "overflow_arg_area.next");
CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);

// AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
return Address(Res, Align);
3975}

3977Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                               QualType Ty) const {
// Assume that va_list type is correct; should be pointer to LLVM type:
// struct {
//   i32 gp_offset;
//   i32 fp_offset;
//   i8* overflow_arg_area;
//   i8* reg_save_area;
// };
unsigned neededInt, neededSSE;

Ty = getContext().getCanonicalType(Ty);
ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
                                     /*isNamedArg*/false);

// AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
// in the registers. If not go to step 7.
if (!neededInt && !neededSSE)
  return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);

// AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
// general purpose registers needed to pass type and num_fp to hold
// the number of floating point registers needed.

// AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
// registers. In the case: l->gp_offset > 48 - num_gp * 8 or
// l->fp_offset > 304 - num_fp * 16 go to step 7.
//
// NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
// register save space).

llvm::Value *InRegs = nullptr;
Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
if (neededInt) {
  gp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "gp_offset_p");
  gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
  InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
  InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
}

if (neededSSE) {
  fp_offset_p = CGF.Builder.CreateStructGEP(VAListAddr, 1, "fp_offset_p");
  fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
  llvm::Value *FitsInFP =
    llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
  FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
  InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
}

llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);

// Emit code to load the value if it was passed in registers.

CGF.EmitBlock(InRegBlock);

// AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
// an offset of l->gp_offset and/or l->fp_offset. This may require
// copying to a temporary location in case the parameter is passed
// in different register classes or requires an alignment greater
// than 8 for general purpose registers and 16 for XMM registers.
//
// FIXME: This really results in shameful code when we end up needing to
// collect arguments from different places; often what should result in a
// simple assembling of a structure from scattered addresses has many more
// loads than necessary. Can we clean this up?
llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
    CGF.Builder.CreateStructGEP(VAListAddr, 3), "reg_save_area");

Address RegAddr = Address::invalid();
if (neededInt && neededSSE) {
  // FIXME: Cleanup.
  assert(AI.isDirect() && "Unexpected ABI info for mixed regs")((void)0);
  llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
  Address Tmp = CGF.CreateMemTemp(Ty);
  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
  assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs")((void)0);
  llvm::Type *TyLo = ST->getElementType(0);
  llvm::Type *TyHi = ST->getElementType(1);
  assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&((void)0)
         "Unexpected ABI info for mixed regs")((void)0);
  llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
  llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
  llvm::Value *GPAddr =
      CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, gp_offset);
  llvm::Value *FPAddr =
      CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, fp_offset);
  llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
  llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;

  // Copy the first element.
  // FIXME: Our choice of alignment here and below is probably pessimistic.
  llvm::Value *V = CGF.Builder.CreateAlignedLoad(
      TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
      CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));

  // Copy the second element.
  V = CGF.Builder.CreateAlignedLoad(
      TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
      CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));

  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
} else if (neededInt) {
  RegAddr = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, gp_offset),
                    CharUnits::fromQuantity(8));
  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);

  // Copy to a temporary if necessary to ensure the appropriate alignment.
  auto TInfo = getContext().getTypeInfoInChars(Ty);
  uint64_t TySize = TInfo.Width.getQuantity();
  CharUnits TyAlign = TInfo.Align;

  // Copy into a temporary if the type is more aligned than the
  // register save area.
  if (TyAlign.getQuantity() > 8) {
    Address Tmp = CGF.CreateMemTemp(Ty);
    CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
    RegAddr = Tmp;
  }

} else if (neededSSE == 1) {
  RegAddr = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea, fp_offset),
                    CharUnits::fromQuantity(16));
  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
} else {
  assert(neededSSE == 2 && "Invalid number of needed registers!")((void)0);
  // SSE registers are spaced 16 bytes apart in the register save
  // area, we need to collect the two eightbytes together.
  // The ABI isn't explicit about this, but it seems reasonable
  // to assume that the slots are 16-byte aligned, since the stack is
  // naturally 16-byte aligned and the prologue is expected to store
  // all the SSE registers to the RSA.
  Address RegAddrLo = Address(CGF.Builder.CreateGEP(CGF.Int8Ty, RegSaveArea,
                                                    fp_offset),
                              CharUnits::fromQuantity(16));
  Address RegAddrHi =
    CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
                                           CharUnits::fromQuantity(16));
  llvm::Type *ST = AI.canHaveCoerceToType()
                       ? AI.getCoerceToType()
                       : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
  llvm::Value *V;
  Address Tmp = CGF.CreateMemTemp(Ty);
  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
  V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
      RegAddrLo, ST->getStructElementType(0)));
  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 0));
  V = CGF.Builder.CreateLoad(CGF.Builder.CreateElementBitCast(
      RegAddrHi, ST->getStructElementType(1)));
  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1));

  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
}

// AMD64-ABI 3.5.7p5: Step 5. Set:
// l->gp_offset = l->gp_offset + num_gp * 8
// l->fp_offset = l->fp_offset + num_fp * 16.
if (neededInt) {
  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
                          gp_offset_p);
}
if (neededSSE) {
  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
                          fp_offset_p);
}
CGF.EmitBranch(ContBlock);

// Emit code to load the value if it was passed in memory.

CGF.EmitBlock(InMemBlock);
Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);

// Return the appropriate result.

CGF.EmitBlock(ContBlock);
Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
                               "vaarg.addr");
return ResAddr;
4163}

4165Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
                                 QualType Ty) const {
// MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
// not 1, 2, 4, or 8 bytes, must be passed by reference."
uint64_t Width = getContext().getTypeSize(Ty);
bool IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);

return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
                        CGF.getContext().getTypeInfoInChars(Ty),
                        CharUnits::fromQuantity(8),
                        /*allowHigherAlign*/ false);
4176}

4178ABIArgInfo WinX86_64ABIInfo::reclassifyHvaArgForVectorCall(
  QualType Ty, unsigned &FreeSSERegs, const ABIArgInfo &current) const {
const Type *Base = nullptr;
uint64_t NumElts = 0;

if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
    isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
  FreeSSERegs -= NumElts;
  return getDirectX86Hva();
}
return current;
4189}

4191ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
                                    bool IsReturnType, bool IsVectorCall,
                                    bool IsRegCall) const {

if (Ty->isVoidType())
  return ABIArgInfo::getIgnore();

if (const EnumType *EnumTy = Ty->getAs<EnumType>())
  Ty = EnumTy->getDecl()->getIntegerType();

TypeInfo Info = getContext().getTypeInfo(Ty);
uint64_t Width = Info.Width;
CharUnits Align = getContext().toCharUnitsFromBits(Info.Align);

const RecordType *RT = Ty->getAs<RecordType>();
if (RT) {
  if (!IsReturnType) {
    if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()))
      return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
  }

  if (RT->getDecl()->hasFlexibleArrayMember())
    return getNaturalAlignIndirect(Ty, /*ByVal=*/false);

}

const Type *Base = nullptr;
uint64_t NumElts = 0;
// vectorcall adds the concept of a homogenous vector aggregate, similar to
// other targets.
if ((IsVectorCall || IsRegCall) &&
    isHomogeneousAggregate(Ty, Base, NumElts)) {
  if (IsRegCall) {
    if (FreeSSERegs >= NumElts) {
      FreeSSERegs -= NumElts;
      if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
        return ABIArgInfo::getDirect();
      return ABIArgInfo::getExpand();
    }
    return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
  } else if (IsVectorCall) {
    if (FreeSSERegs >= NumElts &&
        (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
      FreeSSERegs -= NumElts;
      return ABIArgInfo::getDirect();
    } else if (IsReturnType) {
      return ABIArgInfo::getExpand();
    } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
      // HVAs are delayed and reclassified in the 2nd step.
      return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
    }
  }
}

if (Ty->isMemberPointerType()) {
  // If the member pointer is represented by an LLVM int or ptr, pass it
  // directly.
  llvm::Type *LLTy = CGT.ConvertType(Ty);
  if (LLTy->isPointerTy() || LLTy->isIntegerTy())
    return ABIArgInfo::getDirect();
}

if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
  // not 1, 2, 4, or 8 bytes, must be passed by reference."
  if (Width > 64 || !llvm::isPowerOf2_64(Width))
    return getNaturalAlignIndirect(Ty, /*ByVal=*/false);

  // Otherwise, coerce it to a small integer.
  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
}

if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
  switch (BT->getKind()) {
  case BuiltinType::Bool:
    // Bool type is always extended to the ABI, other builtin types are not
    // extended.
    return ABIArgInfo::getExtend(Ty);

  case BuiltinType::LongDouble:
    // Mingw64 GCC uses the old 80 bit extended precision floating point
    // unit. It passes them indirectly through memory.
    if (IsMingw64) {
      const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
      if (LDF == &llvm::APFloat::x87DoubleExtended())
        return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
    }
    break;

  case BuiltinType::Int128:
  case BuiltinType::UInt128:
    // If it's a parameter type, the normal ABI rule is that arguments larger
    // than 8 bytes are passed indirectly. GCC follows it. We follow it too,
    // even though it isn't particularly efficient.
    if (!IsReturnType)
      return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);

    // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
    // Clang matches them for compatibility.
    return ABIArgInfo::getDirect(llvm::FixedVectorType::get(
        llvm::Type::getInt64Ty(getVMContext()), 2));

  default:
    break;
  }
}

if (Ty->isExtIntType()) {
  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
  // not 1, 2, 4, or 8 bytes, must be passed by reference."
  // However, non-power-of-two _ExtInts will be passed as 1,2,4 or 8 bytes
  // anyway as long is it fits in them, so we don't have to check the power of
  // 2.
  if (Width <= 64)
    return ABIArgInfo::getDirect();
  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
}

return ABIArgInfo::getDirect();
4310}

4312void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
const unsigned CC = FI.getCallingConvention();
bool IsVectorCall = CC == llvm::CallingConv::X86_VectorCall;
bool IsRegCall = CC == llvm::CallingConv::X86_RegCall;

// If __attribute__((sysv_abi)) is in use, use the SysV argument
// classification rules.
if (CC == llvm::CallingConv::X86_64_SysV) {
  X86_64ABIInfo SysVABIInfo(CGT, AVXLevel);
  SysVABIInfo.computeInfo(FI);
  return;
}

unsigned FreeSSERegs = 0;
if (IsVectorCall) {
  // We can use up to 4 SSE return registers with vectorcall.
  FreeSSERegs = 4;
} else if (IsRegCall) {
  // RegCall gives us 16 SSE registers.
  FreeSSERegs = 16;
}

if (!getCXXABI().classifyReturnType(FI))
  FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
                                IsVectorCall, IsRegCall);

if (IsVectorCall) {
  // We can use up to 6 SSE register parameters with vectorcall.
  FreeSSERegs = 6;
} else if (IsRegCall) {
  // RegCall gives us 16 SSE registers, we can reuse the return registers.
  FreeSSERegs = 16;
}

unsigned ArgNum = 0;
unsigned ZeroSSERegs = 0;
for (auto &I : FI.arguments()) {
  // Vectorcall in x64 only permits the first 6 arguments to be passed as
  // XMM/YMM registers. After the sixth argument, pretend no vector
  // registers are left.
  unsigned *MaybeFreeSSERegs =
      (IsVectorCall && ArgNum >= 6) ? &ZeroSSERegs : &FreeSSERegs;
  I.info =
      classify(I.type, *MaybeFreeSSERegs, false, IsVectorCall, IsRegCall);
  ++ArgNum;
}

if (IsVectorCall) {
  // For vectorcall, assign aggregate HVAs to any free vector registers in a
  // second pass.
  for (auto &I : FI.arguments())
    I.info = reclassifyHvaArgForVectorCall(I.type, FreeSSERegs, I.info);
}
4365}

4367Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                                  QualType Ty) const {
// MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
// not 1, 2, 4, or 8 bytes, must be passed by reference."
uint64_t Width = getContext().getTypeSize(Ty);
bool IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);

return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
                        CGF.getContext().getTypeInfoInChars(Ty),
                        CharUnits::fromQuantity(8),
                        /*allowHigherAlign*/ false);
4378}

4380static bool PPC_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                                      llvm::Value *Address, bool Is64Bit,
                                      bool IsAIX) {
// This is calculated from the LLVM and GCC tables and verified
// against gcc output.  AFAIK all PPC ABIs use the same encoding.

CodeGen::CGBuilderTy &Builder = CGF.Builder;

llvm::IntegerType *i8 = CGF.Int8Ty;
llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);

// 0-31: r0-31, the 4-byte or 8-byte general-purpose registers
AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 0, 31);

// 32-63: fp0-31, the 8-byte floating-point registers
AssignToArrayRange(Builder, Address, Eight8, 32, 63);

// 64-67 are various 4-byte or 8-byte special-purpose registers:
// 64: mq
// 65: lr
// 66: ctr
// 67: ap
AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 64, 67);

// 68-76 are various 4-byte special-purpose registers:
// 68-75 cr0-7
// 76: xer
AssignToArrayRange(Builder, Address, Four8, 68, 76);

// 77-108: v0-31, the 16-byte vector registers
AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);

// 109: vrsave
// 110: vscr
AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 109, 110);

// AIX does not utilize the rest of the registers.
if (IsAIX)
  return false;

// 111: spe_acc
// 112: spefscr
// 113: sfp
AssignToArrayRange(Builder, Address, Is64Bit ? Eight8 : Four8, 111, 113);

if (!Is64Bit)
  return false;

// TODO: Need to verify if these registers are used on 64 bit AIX with Power8
// or above CPU.
// 64-bit only registers:
// 114: tfhar
// 115: tfiar
// 116: texasr
AssignToArrayRange(Builder, Address, Eight8, 114, 116);

return false;
4439}

4441// AIX
4442namespace {
4443/// AIXABIInfo - The AIX XCOFF ABI information.
4444class AIXABIInfo : public ABIInfo {
const bool Is64Bit;
const unsigned PtrByteSize;
CharUnits getParamTypeAlignment(QualType Ty) const;

4449public:
AIXABIInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
    : ABIInfo(CGT), Is64Bit(Is64Bit), PtrByteSize(Is64Bit ? 8 : 4) {}

bool isPromotableTypeForABI(QualType Ty) const;

ABIArgInfo classifyReturnType(QualType RetTy) const;
ABIArgInfo classifyArgumentType(QualType Ty) const;

void computeInfo(CGFunctionInfo &FI) const override {
  if (!getCXXABI().classifyReturnType(FI))
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());

  for (auto &I : FI.arguments())
    I.info = classifyArgumentType(I.type);
}

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override;
4468};

4470class AIXTargetCodeGenInfo : public TargetCodeGenInfo {
const bool Is64Bit;

4473public:
AIXTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool Is64Bit)
    : TargetCodeGenInfo(std::make_unique<AIXABIInfo>(CGT, Is64Bit)),
      Is64Bit(Is64Bit) {}
int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
  return 1; // r1 is the dedicated stack pointer
}

bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                             llvm::Value *Address) const override;
4483};
4484} // namespace

4486// Return true if the ABI requires Ty to be passed sign- or zero-
4487// extended to 32/64 bits.
4488bool AIXABIInfo::isPromotableTypeForABI(QualType Ty) const {
// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = Ty->getAs<EnumType>())
  Ty = EnumTy->getDecl()->getIntegerType();

// Promotable integer types are required to be promoted by the ABI.
if (Ty->isPromotableIntegerType())
  return true;

if (!Is64Bit)
  return false;

// For 64 bit mode, in addition to the usual promotable integer types, we also
// need to extend all 32-bit types, since the ABI requires promotion to 64
// bits.
if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
  switch (BT->getKind()) {
  case BuiltinType::Int:
  case BuiltinType::UInt:
    return true;
  default:
    break;
  }

return false;
4513}

4515ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy) const {
if (RetTy->isAnyComplexType())
  return ABIArgInfo::getDirect();

if (RetTy->isVectorType())
  return ABIArgInfo::getDirect();

if (RetTy->isVoidType())
  return ABIArgInfo::getIgnore();

if (isAggregateTypeForABI(RetTy))
  return getNaturalAlignIndirect(RetTy);

return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
                                      : ABIArgInfo::getDirect());
4530}

4532ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
Ty = useFirstFieldIfTransparentUnion(Ty);

if (Ty->isAnyComplexType())
  return ABIArgInfo::getDirect();

if (Ty->isVectorType())
  return ABIArgInfo::getDirect();

if (isAggregateTypeForABI(Ty)) {
  // Records with non-trivial destructors/copy-constructors should not be
  // passed by value.
  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
    return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);

  CharUnits CCAlign = getParamTypeAlignment(Ty);
  CharUnits TyAlign = getContext().getTypeAlignInChars(Ty);

  return ABIArgInfo::getIndirect(CCAlign, /*ByVal*/ true,
                                 /*Realign*/ TyAlign > CCAlign);
}

return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
                                   : ABIArgInfo::getDirect());
4556}

4558CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
// Complex types are passed just like their elements.
if (const ComplexType *CTy = Ty->getAs<ComplexType>())
  Ty = CTy->getElementType();

if (Ty->isVectorType())
  return CharUnits::fromQuantity(16);

// If the structure contains a vector type, the alignment is 16.
if (isRecordWithSIMDVectorType(getContext(), Ty))
  return CharUnits::fromQuantity(16);

return CharUnits::fromQuantity(PtrByteSize);
4571}

4573Address AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                            QualType Ty) const {
if (Ty->isAnyComplexType())
  llvm::report_fatal_error("complex type is not supported on AIX yet");

auto TypeInfo = getContext().getTypeInfoInChars(Ty);
TypeInfo.Align = getParamTypeAlignment(Ty);

CharUnits SlotSize = CharUnits::fromQuantity(PtrByteSize);

return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, TypeInfo,
                        SlotSize, /*AllowHigher*/ true);
4585}

4587bool AIXTargetCodeGenInfo::initDwarfEHRegSizeTable(
  CodeGen::CodeGenFunction &CGF, llvm::Value *Address) const {
return PPC_initDwarfEHRegSizeTable(CGF, Address, Is64Bit, /*IsAIX*/ true);
4590}

4592// PowerPC-32
4593namespace {
4594/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4595class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
bool IsSoftFloatABI;
bool IsRetSmallStructInRegABI;

CharUnits getParamTypeAlignment(QualType Ty) const;

4601public:
PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI,
                   bool RetSmallStructInRegABI)
    : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),
      IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}

ABIArgInfo classifyReturnType(QualType RetTy) const;

void computeInfo(CGFunctionInfo &FI) const override {
  if (!getCXXABI().classifyReturnType(FI))
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
  for (auto &I : FI.arguments())
    I.info = classifyArgumentType(I.type);
}

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override;
4618};

4620class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4621public:
PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI,
                       bool RetSmallStructInRegABI)
    : TargetCodeGenInfo(std::make_unique<PPC32_SVR4_ABIInfo>(
          CGT, SoftFloatABI, RetSmallStructInRegABI)) {}

static bool isStructReturnInRegABI(const llvm::Triple &Triple,
                                   const CodeGenOptions &Opts);

int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
  // This is recovered from gcc output.
  return 1; // r1 is the dedicated stack pointer
}

bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                             llvm::Value *Address) const override;
4637};
4638}

4640CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
// Complex types are passed just like their elements.
if (const ComplexType *CTy = Ty->getAs<ComplexType>())
  Ty = CTy->getElementType();

if (Ty->isVectorType())
  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
                                                                     : 4);

// For single-element float/vector structs, we consider the whole type
// to have the same alignment requirements as its single element.
const Type *AlignTy = nullptr;
if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
  const BuiltinType *BT = EltType->getAs<BuiltinType>();
  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
      (BT && BT->isFloatingPoint()))
    AlignTy = EltType;
}

if (AlignTy)
  return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
return CharUnits::fromQuantity(4);
4662}

4664ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
uint64_t Size;

// -msvr4-struct-return puts small aggregates in GPR3 and GPR4.
if (isAggregateTypeForABI(RetTy) && IsRetSmallStructInRegABI &&
    (Size = getContext().getTypeSize(RetTy)) <= 64) {
  // System V ABI (1995), page 3-22, specified:
  // > A structure or union whose size is less than or equal to 8 bytes
  // > shall be returned in r3 and r4, as if it were first stored in the
  // > 8-byte aligned memory area and then the low addressed word were
  // > loaded into r3 and the high-addressed word into r4.  Bits beyond
  // > the last member of the structure or union are not defined.
  //
  // GCC for big-endian PPC32 inserts the pad before the first member,
  // not "beyond the last member" of the struct.  To stay compatible
  // with GCC, we coerce the struct to an integer of the same size.
  // LLVM will extend it and return i32 in r3, or i64 in r3:r4.
  if (Size == 0)
    return ABIArgInfo::getIgnore();
  else {
    llvm::Type *CoerceTy = llvm::Type::getIntNTy(getVMContext(), Size);
    return ABIArgInfo::getDirect(CoerceTy);
  }
}

return DefaultABIInfo::classifyReturnType(RetTy);
4690}

4692// TODO: this implementation is now likely redundant with
4693// DefaultABIInfo::EmitVAArg.
4694Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
                                    QualType Ty) const {
if (getTarget().getTriple().isOSDarwin()) {
  auto TI = getContext().getTypeInfoInChars(Ty);
  TI.Align = getParamTypeAlignment(Ty);

  CharUnits SlotSize = CharUnits::fromQuantity(4);
  return emitVoidPtrVAArg(CGF, VAList, Ty,
                          classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
                          /*AllowHigherAlign=*/true);
}

const unsigned OverflowLimit = 8;
if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
  // TODO: Implement this. For now ignore.
  (void)CTy;
  return Address::invalid(); // FIXME?
}

// struct __va_list_tag {
//   unsigned char gpr;
//   unsigned char fpr;
//   unsigned short reserved;
//   void *overflow_arg_area;
//   void *reg_save_area;
// };

bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
bool isInt = !Ty->isFloatingType();
bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;

// All aggregates are passed indirectly?  That doesn't seem consistent
// with the argument-lowering code.
bool isIndirect = isAggregateTypeForABI(Ty);

CGBuilderTy &Builder = CGF.Builder;

// The calling convention either uses 1-2 GPRs or 1 FPR.
Address NumRegsAddr = Address::invalid();
if (isInt || IsSoftFloatABI) {
  NumRegsAddr = Builder.CreateStructGEP(VAList, 0, "gpr");
} else {
  NumRegsAddr = Builder.CreateStructGEP(VAList, 1, "fpr");
}

llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");

// "Align" the register count when TY is i64.
if (isI64 || (isF64 && IsSoftFloatABI)) {
  NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
  NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
}

llvm::Value *CC =
    Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");

llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");

Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);

llvm::Type *DirectTy = CGF.ConvertType(Ty);
if (isIndirect) DirectTy = DirectTy->getPointerTo(0);

// Case 1: consume registers.
Address RegAddr = Address::invalid();
{
  CGF.EmitBlock(UsingRegs);

  Address RegSaveAreaPtr = Builder.CreateStructGEP(VAList, 4);
  RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
                    CharUnits::fromQuantity(8));
  assert(RegAddr.getElementType() == CGF.Int8Ty)((void)0);

  // Floating-point registers start after the general-purpose registers.
  if (!(isInt || IsSoftFloatABI)) {
    RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
                                                 CharUnits::fromQuantity(32));
  }

  // Get the address of the saved value by scaling the number of
  // registers we've used by the number of
  CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
  llvm::Value *RegOffset =
    Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
  RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
                                          RegAddr.getPointer(), RegOffset),
                    RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
  RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);

  // Increase the used-register count.
  NumRegs =
    Builder.CreateAdd(NumRegs,
                      Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
  Builder.CreateStore(NumRegs, NumRegsAddr);

  CGF.EmitBranch(Cont);
}

// Case 2: consume space in the overflow area.
Address MemAddr = Address::invalid();
{
  CGF.EmitBlock(UsingOverflow);

  Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);

  // Everything in the overflow area is rounded up to a size of at least 4.
  CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);

  CharUnits Size;
  if (!isIndirect) {
    auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
    Size = TypeInfo.Width.alignTo(OverflowAreaAlign);
  } else {
    Size = CGF.getPointerSize();
  }

  Address OverflowAreaAddr = Builder.CreateStructGEP(VAList, 3);
  Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
                       OverflowAreaAlign);
  // Round up address of argument to alignment
  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
  if (Align > OverflowAreaAlign) {
    llvm::Value *Ptr = OverflowArea.getPointer();
    OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
                                                         Align);
  }

  MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);

  // Increase the overflow area.
  OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
  Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
  CGF.EmitBranch(Cont);
}

CGF.EmitBlock(Cont);

// Merge the cases with a phi.
Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
                              "vaarg.addr");

// Load the pointer if the argument was passed indirectly.
if (isIndirect) {
  Result = Address(Builder.CreateLoad(Result, "aggr"),
                   getContext().getTypeAlignInChars(Ty));
}

return Result;
4844}

4846bool PPC32TargetCodeGenInfo::isStructReturnInRegABI(
  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
assert(Triple.isPPC32())((void)0);

switch (Opts.getStructReturnConvention()) {
case CodeGenOptions::SRCK_Default:
  break;
case CodeGenOptions::SRCK_OnStack: // -maix-struct-return
  return false;
case CodeGenOptions::SRCK_InRegs: // -msvr4-struct-return
  return true;
}

if (Triple.isOSBinFormatELF() && !Triple.isOSLinux())
  return true;

return false;
4863}

4865bool
4866PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                                              llvm::Value *Address) const {
return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ false,
                                   /*IsAIX*/ false);
4870}

4872// PowerPC-64

4874namespace {
4875/// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4876class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4877public:
enum ABIKind {
  ELFv1 = 0,
  ELFv2
};

4883private:
static const unsigned GPRBits = 64;
ABIKind Kind;
bool IsSoftFloatABI;

4888public:
PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind,
                   bool SoftFloatABI)
    : SwiftABIInfo(CGT), Kind(Kind), IsSoftFloatABI(SoftFloatABI) {}

bool isPromotableTypeForABI(QualType Ty) const;
CharUnits getParamTypeAlignment(QualType Ty) const;

ABIArgInfo classifyReturnType(QualType RetTy) const;
ABIArgInfo classifyArgumentType(QualType Ty) const;

bool isHomogeneousAggregateBaseType(QualType Ty) const override;
bool isHomogeneousAggregateSmallEnough(const Type *Ty,
                                       uint64_t Members) const override;

// TODO: We can add more logic to computeInfo to improve performance.
// Example: For aggregate arguments that fit in a register, we could
// use getDirectInReg (as is done below for structs containing a single
// floating-point value) to avoid pushing them to memory on function
// entry.  This would require changing the logic in PPCISelLowering
// when lowering the parameters in the caller and args in the callee.
void computeInfo(CGFunctionInfo &FI) const override {
  if (!getCXXABI().classifyReturnType(FI))
    FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
  for (auto &I : FI.arguments()) {
    // We rely on the default argument classification for the most part.
    // One exception:  An aggregate containing a single floating-point
    // or vector item must be passed in a register if one is available.
    const Type *T = isSingleElementStruct(I.type, getContext());
    if (T) {
      const BuiltinType *BT = T->getAs<BuiltinType>();
      if ((T->isVectorType() && getContext().getTypeSize(T) == 128) ||
          (BT && BT->isFloatingPoint())) {
        QualType QT(T, 0);
        I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
        continue;
      }
    }
    I.info = classifyArgumentType(I.type);
  }
}

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override;

bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
                                  bool asReturnValue) const override {
  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
}

bool isSwiftErrorInRegister() const override {
  return false;
}
4941};

4943class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {

4945public:
PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
                             PPC64_SVR4_ABIInfo::ABIKind Kind,
                             bool SoftFloatABI)
    : TargetCodeGenInfo(
          std::make_unique<PPC64_SVR4_ABIInfo>(CGT, Kind, SoftFloatABI)) {}

int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
  // This is recovered from gcc output.
  return 1; // r1 is the dedicated stack pointer
}

bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                             llvm::Value *Address) const override;
4959};

4961class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4962public:
PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}

int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
  // This is recovered from gcc output.
  return 1; // r1 is the dedicated stack pointer
}

bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                             llvm::Value *Address) const override;
4972};

4974}

4976// Return true if the ABI requires Ty to be passed sign- or zero-
4977// extended to 64 bits.
4978bool
4979PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = Ty->getAs<EnumType>())
  Ty = EnumTy->getDecl()->getIntegerType();

// Promotable integer types are required to be promoted by the ABI.
if (isPromotableIntegerTypeForABI(Ty))
  return true;

// In addition to the usual promotable integer types, we also need to
// extend all 32-bit types, since the ABI requires promotion to 64 bits.
if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
  switch (BT->getKind()) {
  case BuiltinType::Int:
  case BuiltinType::UInt:
    return true;
  default:
    break;
  }

if (const auto *EIT = Ty->getAs<ExtIntType>())
  if (EIT->getNumBits() < 64)
    return true;

return false;
5004}

5006/// isAlignedParamType - Determine whether a type requires 16-byte or
5007/// higher alignment in the parameter area.  Always returns at least 8.
5008CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
// Complex types are passed just like their elements.
if (const ComplexType *CTy = Ty->getAs<ComplexType>())
  Ty = CTy->getElementType();

// Only vector types of size 16 bytes need alignment (larger types are
// passed via reference, smaller types are not aligned).
if (Ty->isVectorType()) {
  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
} else if (Ty->isRealFloatingType() &&
           &getContext().getFloatTypeSemantics(Ty) ==
               &llvm::APFloat::IEEEquad()) {
  // According to ABI document section 'Optional Save Areas': If extended
  // precision floating-point values in IEEE BINARY 128 QUADRUPLE PRECISION
  // format are supported, map them to a single quadword, quadword aligned.
  return CharUnits::fromQuantity(16);
}

// For single-element float/vector structs, we consider the whole type
// to have the same alignment requirements as its single element.
const Type *AlignAsType = nullptr;
const Type *EltType = isSingleElementStruct(Ty, getContext());
if (EltType) {
  const BuiltinType *BT = EltType->getAs<BuiltinType>();
  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
      (BT && BT->isFloatingPoint()))
    AlignAsType = EltType;
}

// Likewise for ELFv2 homogeneous aggregates.
const Type *Base = nullptr;
uint64_t Members = 0;
if (!AlignAsType && Kind == ELFv2 &&
    isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
  AlignAsType = Base;

// With special case aggregates, only vector base types need alignment.
if (AlignAsType) {
  return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
}

// Otherwise, we only need alignment for any aggregate type that
// has an alignment requirement of >= 16 bytes.
if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
  return CharUnits::fromQuantity(16);
}

return CharUnits::fromQuantity(8);
5056}

5058/// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
5059/// aggregate.  Base is set to the base element type, and Members is set
5060/// to the number of base elements.
5061bool ABIInfo::isHomogeneousAggregate(QualType Ty, const Type *&Base,
                                   uint64_t &Members) const {
if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
  uint64_t NElements = AT->getSize().getZExtValue();
  if (NElements == 0)
    return false;
  if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
    return false;
  Members *= NElements;
} else if (const RecordType *RT = Ty->getAs<RecordType>()) {
  const RecordDecl *RD = RT->getDecl();
  if (RD->hasFlexibleArrayMember())
    return false;

  Members = 0;

  // If this is a C++ record, check the properties of the record such as
  // bases and ABI specific restrictions
  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
    if (!getCXXABI().isPermittedToBeHomogeneousAggregate(CXXRD))
      return false;

    for (const auto &I : CXXRD->bases()) {
      // Ignore empty records.
      if (isEmptyRecord(getContext(), I.getType(), true))
        continue;

      uint64_t FldMembers;
      if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
        return false;

      Members += FldMembers;
    }
  }

  for (const auto *FD : RD->fields()) {
    // Ignore (non-zero arrays of) empty records.
    QualType FT = FD->getType();
    while (const ConstantArrayType *AT =
           getContext().getAsConstantArrayType(FT)) {
      if (AT->getSize().getZExtValue() == 0)
        return false;
      FT = AT->getElementType();
    }
    if (isEmptyRecord(getContext(), FT, true))
      continue;

    // For compatibility with GCC, ignore empty bitfields in C++ mode.
    if (getContext().getLangOpts().CPlusPlus &&
        FD->isZeroLengthBitField(getContext()))
      continue;

    uint64_t FldMembers;
    if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
      return false;

    Members = (RD->isUnion() ?
               std::max(Members, FldMembers) : Members + FldMembers);
  }

  if (!Base)
    return false;

  // Ensure there is no padding.
  if (getContext().getTypeSize(Base) * Members !=
      getContext().getTypeSize(Ty))
    return false;
} else {
  Members = 1;
  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
    Members = 2;
    Ty = CT->getElementType();
  }

  // Most ABIs only support float, double, and some vector type widths.
  if (!isHomogeneousAggregateBaseType(Ty))
    return false;

  // The base type must be the same for all members.  Types that
  // agree in both total size and mode (float vs. vector) are
  // treated as being equivalent here.
  const Type *TyPtr = Ty.getTypePtr();
  if (!Base) {
    Base = TyPtr;
    // If it's a non-power-of-2 vector, its size is already a power-of-2,
    // so make sure to widen it explicitly.
    if (const VectorType *VT = Base->getAs<VectorType>()) {
      QualType EltTy = VT->getElementType();
      unsigned NumElements =
          getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
      Base = getContext()
                 .getVectorType(EltTy, NumElements, VT->getVectorKind())
                 .getTypePtr();
    }
  }

  if (Base->isVectorType() != TyPtr->isVectorType() ||
      getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
    return false;
}
return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
5162}

5164bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
// Homogeneous aggregates for ELFv2 must have base types of float,
// double, long double, or 128-bit vectors.
if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
  if (BT->getKind() == BuiltinType::Float ||
      BT->getKind() == BuiltinType::Double ||
      BT->getKind() == BuiltinType::LongDouble ||
      (getContext().getTargetInfo().hasFloat128Type() &&
        (BT->getKind() == BuiltinType::Float128))) {
    if (IsSoftFloatABI)
      return false;
    return true;
  }
}
if (const VectorType *VT = Ty->getAs<VectorType>()) {
  if (getContext().getTypeSize(VT) == 128)
    return true;
}
return false;
5183}

5185bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
  const Type *Base, uint64_t Members) const {
// Vector and fp128 types require one register, other floating point types
// require one or two registers depending on their size.
uint32_t NumRegs =
    ((getContext().getTargetInfo().hasFloat128Type() &&
        Base->isFloat128Type()) ||
      Base->isVectorType()) ? 1
                            : (getContext().getTypeSize(Base) + 63) / 64;

// Homogeneous Aggregates may occupy at most 8 registers.
return Members * NumRegs <= 8;
5197}

5199ABIArgInfo
5200PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
Ty = useFirstFieldIfTransparentUnion(Ty);

if (Ty->isAnyComplexType())
  return ABIArgInfo::getDirect();

// Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
// or via reference (larger than 16 bytes).
if (Ty->isVectorType()) {
  uint64_t Size = getContext().getTypeSize(Ty);
  if (Size > 128)
    return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
  else if (Size < 128) {
    llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
    return ABIArgInfo::getDirect(CoerceTy);
  }
}

if (const auto *EIT = Ty->getAs<ExtIntType>())
  if (EIT->getNumBits() > 128)
    return getNaturalAlignIndirect(Ty, /*ByVal=*/true);

if (isAggregateTypeForABI(Ty)) {
  if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
    return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);

  uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
  uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();

  // ELFv2 homogeneous aggregates are passed as array types.
  const Type *Base = nullptr;
  uint64_t Members = 0;
  if (Kind == ELFv2 &&
      isHomogeneousAggregate(Ty, Base, Members)) {
    llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
    llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
    return ABIArgInfo::getDirect(CoerceTy);
  }

  // If an aggregate may end up fully in registers, we do not
  // use the ByVal method, but pass the aggregate as array.
  // This is usually beneficial since we avoid forcing the
  // back-end to store the argument to memory.
  uint64_t Bits = getContext().getTypeSize(Ty);
  if (Bits > 0 && Bits <= 8 * GPRBits) {
    llvm::Type *CoerceTy;

    // Types up to 8 bytes are passed as integer type (which will be
    // properly aligned in the argument save area doubleword).
    if (Bits <= GPRBits)
      CoerceTy =
          llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
    // Larger types are passed as arrays, with the base type selected
    // according to the required alignment in the save area.
    else {
      uint64_t RegBits = ABIAlign * 8;
      uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
      llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
      CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
    }

    return ABIArgInfo::getDirect(CoerceTy);
  }

  // All other aggregates are passed ByVal.
  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(ABIAlign),
                                 /*ByVal=*/true,
                                 /*Realign=*/TyAlign > ABIAlign);
}

return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
                                   : ABIArgInfo::getDirect());
5272}

5274ABIArgInfo
5275PPC64_SVR4_ABIInfo::classifyReturnType(QualType RetTy) const {
if (RetTy->isVoidType())
  return ABIArgInfo::getIgnore();

if (RetTy->isAnyComplexType())
  return ABIArgInfo::getDirect();

// Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
// or via reference (larger than 16 bytes).
if (RetTy->isVectorType()) {
  uint64_t Size = getContext().getTypeSize(RetTy);
  if (Size > 128)
    return getNaturalAlignIndirect(RetTy);
  else if (Size < 128) {
    llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
    return ABIArgInfo::getDirect(CoerceTy);
  }
}

if (const auto *EIT = RetTy->getAs<ExtIntType>())
  if (EIT->getNumBits() > 128)
    return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);

if (isAggregateTypeForABI(RetTy)) {
  // ELFv2 homogeneous aggregates are returned as array types.
  const Type *Base = nullptr;
  uint64_t Members = 0;
  if (Kind == ELFv2 &&
      isHomogeneousAggregate(RetTy, Base, Members)) {
    llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
    llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
    return ABIArgInfo::getDirect(CoerceTy);
  }

  // ELFv2 small aggregates are returned in up to two registers.
  uint64_t Bits = getContext().getTypeSize(RetTy);
  if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
    if (Bits == 0)
      return ABIArgInfo::getIgnore();

    llvm::Type *CoerceTy;
    if (Bits > GPRBits) {
      CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
      CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
    } else
      CoerceTy =
          llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
    return ABIArgInfo::getDirect(CoerceTy);
  }

  // All other aggregates are returned indirectly.
  return getNaturalAlignIndirect(RetTy);
}

return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
                                      : ABIArgInfo::getDirect());
5331}

5333// Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
5334Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                                    QualType Ty) const {
auto TypeInfo = getContext().getTypeInfoInChars(Ty);
TypeInfo.Align = getParamTypeAlignment(Ty);

CharUnits SlotSize = CharUnits::fromQuantity(8);

// If we have a complex type and the base type is smaller than 8 bytes,
// the ABI calls for the real and imaginary parts to be right-adjusted
// in separate doublewords.  However, Clang expects us to produce a
// pointer to a structure with the two parts packed tightly.  So generate
// loads of the real and imaginary parts relative to the va_list pointer,
// and store them to a temporary structure.
if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
  CharUnits EltSize = TypeInfo.Width / 2;
  if (EltSize < SlotSize) {
    Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
                                          SlotSize * 2, SlotSize,
                                          SlotSize, /*AllowHigher*/ true);

    Address RealAddr = Addr;
    Address ImagAddr = RealAddr;
    if (CGF.CGM.getDataLayout().isBigEndian()) {
      RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
                                                        SlotSize - EltSize);
      ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
                                                    2 * SlotSize - EltSize);
    } else {
      ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
    }

    llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
    RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
    ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
    llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
    llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");

    Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
    CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
                           /*init*/ true);
    return Temp;
  }
}

// Otherwise, just use the general rule.
return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
                        TypeInfo, SlotSize, /*AllowHigher*/ true);
5381}

5383bool
5384PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
CodeGen::CodeGenFunction &CGF,
llvm::Value *Address) const {
return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
                                   /*IsAIX*/ false);
5389}

5391bool
5392PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
                                              llvm::Value *Address) const {
return PPC_initDwarfEHRegSizeTable(CGF, Address, /*Is64Bit*/ true,
                                   /*IsAIX*/ false);
5396}

5398//===----------------------------------------------------------------------===//
5399// AArch64 ABI Implementation
5400//===----------------------------------------------------------------------===//

5402namespace {

5404class AArch64ABIInfo : public SwiftABIInfo {
5405public:
enum ABIKind {
  AAPCS = 0,
  DarwinPCS,
  Win64
};

5412private:
ABIKind Kind;

5415public:
AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
  : SwiftABIInfo(CGT), Kind(Kind) {}

5419private:
ABIKind getABIKind() const { return Kind; }
bool isDarwinPCS() const { return Kind == DarwinPCS; }

ABIArgInfo classifyReturnType(QualType RetTy, bool IsVariadic) const;
ABIArgInfo classifyArgumentType(QualType RetTy, bool IsVariadic,
                                unsigned CallingConvention) const;
ABIArgInfo coerceIllegalVector(QualType Ty) const;
bool isHomogeneousAggregateBaseType(QualType Ty) const override;
bool isHomogeneousAggregateSmallEnough(const Type *Ty,
                                       uint64_t Members) const override;

bool isIllegalVectorType(QualType Ty) const;

void computeInfo(CGFunctionInfo &FI) const override {
  if (!::classifyReturnType(getCXXABI(), FI, *this))
    FI.getReturnInfo() =
        classifyReturnType(FI.getReturnType(), FI.isVariadic());

  for (auto &it : FI.arguments())
    it.info = classifyArgumentType(it.type, FI.isVariadic(),
                                   FI.getCallingConvention());
}

Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
                        CodeGenFunction &CGF) const;

Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
                       CodeGenFunction &CGF) const;

Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
                  QualType Ty) const override {
  llvm::Type *BaseTy = CGF.ConvertType(Ty);
  if (isa<llvm::ScalableVectorType>(BaseTy))
    llvm::report_fatal_error("Passing SVE types to variadic functions is "
                             "currently not supported");

  return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
                       : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
                                       : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
}

Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
                    QualType Ty) const override;

bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
                                  bool asReturnValue) const override {
  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
}
bool isSwiftErrorInRegister() const override {
  return true;
}

bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
                               unsigned elts) const override;

bool allowBFloatArgsAndRet() const override {
  return getTarget().hasBFloat16Type();
}
5478};

5480class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
5481public:
AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
    : TargetCodeGenInfo(std::make_unique<AArch64ABIInfo>(CGT, Kind)) {}

StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
  return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
}

int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
  return 31;
}

bool doesReturnSlotInterfereWithArgs() const override { return false; }

void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                         CodeGen::CodeGenModule &CGM) const override {
  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
  if (!FD)
    return;

  const auto *TA = FD->getAttr<TargetAttr>();
  if (TA == nullptr)
    return;

  ParsedTargetAttr Attr = TA->parse();
  if (Attr.BranchProtection.empty())
    return;

  TargetInfo::BranchProtectionInfo BPI;
  StringRef Error;
  (void)CGM.getTarget().validateBranchProtection(Attr.BranchProtection,
                                                 BPI, Error);
  assert(Error.empty())((void)0);

  auto *Fn = cast<llvm::Function>(GV);
  static const char *SignReturnAddrStr[] = {"none", "non-leaf", "all"};
  Fn->addFnAttr("sign-return-address", SignReturnAddrStr[static_cast<int>(BPI.SignReturnAddr)]);

  if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
    Fn->addFnAttr("sign-return-address-key",
                  BPI.SignKey == LangOptions::SignReturnAddressKeyKind::AKey
                      ? "a_key"
                      : "b_key");
  }

  Fn->addFnAttr("branch-target-enforcement",
                BPI.BranchTargetEnforcement ? "true" : "false");
}

bool isScalarizableAsmOperand(CodeGen::CodeGenFunction &CGF,
                              llvm::Type *Ty) const override {
  if (CGF.getTarget().hasFeature("ls64")) {
    auto *ST = dyn_cast<llvm::StructType>(Ty);
    if (ST && ST->getNumElements() == 1) {
      auto *AT = dyn_cast<llvm::ArrayType>(ST->getElementType(0));
      if (AT && AT->getNumElements() == 8 &&
          AT->getElementType()->isIntegerTy(64))
        return true;
    }
  }
  return TargetCodeGenInfo::isScalarizableAsmOperand(CGF, Ty);
}
5543};

5545class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
5546public:
WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
    : AArch64TargetCodeGenInfo(CGT, K) {}

void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                         CodeGen::CodeGenModule &CGM) const override;

void getDependentLibraryOption(llvm::StringRef Lib,
                               llvm::SmallString<24> &Opt) const override {
  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
}

void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
                             llvm::SmallString<32> &Opt) const override {
  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
}
5562};

5564void WindowsAArch64TargetCodeGenInfo::setTargetAttributes(
  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
AArch64TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
if (GV->isDeclaration())
  return;
addStackProbeTargetAttributes(D, GV, CGM);
5570}
5571}

5573ABIArgInfo AArch64ABIInfo::coerceIllegalVector(QualType Ty) const {
assert(Ty->isVectorType() && "expected vector type!")((void)0);

const auto *VT = Ty->castAs<VectorType>();
if (VT->getVectorKind() == VectorType::SveFixedLengthPredicateVector) {
  assert(VT->getElementType()->isBuiltinType() && "expected builtin type!")((void)0);
  assert(VT->getElementType()->castAs<BuiltinType>()->getKind() ==((void)0)
             BuiltinType::UChar &&((void)0)
         "unexpected builtin type for SVE predicate!")((void)0);
  return ABIArgInfo::getDirect(llvm::ScalableVectorType::get(
      llvm::Type::getInt1Ty(getVMContext()), 16));
}

if (VT->getVectorKind() == VectorType::SveFixedLengthDataVector) {
  assert(VT->getElementType()->isBuiltinType() && "expected builtin type!")((void)0);

  const auto *BT = VT->getElementType()->castAs<BuiltinType>();
  llvm::ScalableVectorType *ResType = nullptr;
  switch (BT->getKind()) {
  default:
    llvm_unreachable("unexpected builtin type for SVE vector!")__builtin_unreachable();
  case BuiltinType::SChar:
  case BuiltinType::UChar:
    ResType = llvm::ScalableVectorType::get(
        llvm::Type::getInt8Ty(getVMContext()), 16);
    break;
  case BuiltinType::Short:
  case BuiltinType::UShort:
    ResType = llvm::ScalableVectorType::get(
        llvm::Type::getInt16Ty(getVMContext()), 8);
    break;
  case BuiltinType::Int:
  case BuiltinType::UInt:
    ResType = llvm::ScalableVectorType::get(
        llvm::Type::getInt32Ty(getVMContext()), 4);
    break;
  case BuiltinType::Long:
  case BuiltinType::ULong:
    ResType = llvm::ScalableVectorType::get(
        llvm::Type::getInt64Ty(getVMContext()), 2);
    break;
  case BuiltinType::Half:
    ResType = llvm::ScalableVectorType::get(
        llvm::Type::getHalfTy(getVMContext()), 8);
    break;
  case BuiltinType::Float:
    ResType = llvm::ScalableVectorType::get(
        llvm::Type::getFloatTy(getVMContext()), 4);
    break;
  case BuiltinType::Double:
    ResType = llvm::ScalableVectorType::get(
        llvm::Type::getDoubleTy(getVMContext()), 2);
    break;
  case BuiltinType::BFloat16:
    ResType = llvm::ScalableVectorType::get(
        llvm::Type::getBFloatTy(getVMContext()), 8);
    break;
  }
  return ABIArgInfo::getDirect(ResType);
}

uint64_t Size = getContext().getTypeSize(Ty);
// Android promotes <2 x i8> to i16, not i32
if (isAndroid() && (Size <= 16)) {
  llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
  return ABIArgInfo::getDirect(ResType);
}
if (Size <= 32) {
  llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
  return ABIArgInfo::getDirect(ResType);
}
if (Size == 64) {
  auto *ResType =
      llvm::FixedVectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
  return ABIArgInfo::getDirect(ResType);
}
if (Size == 128) {
  auto *ResType =
      llvm::FixedVectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
  return ABIArgInfo::getDirect(ResType);
}
return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5655}

5657ABIArgInfo
5658AArch64ABIInfo::classifyArgumentType(QualType Ty, bool IsVariadic,
                                   unsigned CallingConvention) const {
Ty = useFirstFieldIfTransparentUnion(Ty);

// Handle illegal vector types here.
if (isIllegalVectorType(Ty))
  return coerceIllegalVector(Ty);

if (!isAggregateTypeForABI(Ty)) {
  // Treat an enum type as its underlying type.
  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
    Ty = EnumTy->getDecl()->getIntegerType();

  if (const auto *EIT = Ty->getAs<ExtIntType>())
    if (EIT->getNumBits() > 128)
      return getNaturalAlignIndirect(Ty);

  return (isPromotableIntegerTypeForABI(Ty) && isDarwinPCS()
              ? ABIArgInfo::getExtend(Ty)
              : ABIArgInfo::getDirect());
}

// Structures with either a non-trivial destructor or a non-trivial
// copy constructor are always indirect.
if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
                                   CGCXXABI::RAA_DirectInMemory);
}

// Empty records are always ignored on Darwin, but actually passed in C++ mode
// elsewhere for GNU compatibility.
uint64_t Size = getContext().getTypeSize(Ty);
bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
if (IsEmpty || Size == 0) {
  if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
    return ABIArgInfo::getIgnore();

  // GNU C mode. The only argument that gets ignored is an empty one with size
  // 0.
  if (IsEmpty && Size == 0)
    return ABIArgInfo::getIgnore();
  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
}

// Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
const Type *Base = nullptr;
uint64_t Members = 0;
bool IsWin64 = Kind == Win64 || CallingConvention == llvm::CallingConv::Win64;
bool IsWinVariadic = IsWin64 && IsVariadic;
// In variadic functions on Windows, all composite types are treated alike,
// no special handling of HFAs/HVAs.
if (!IsWinVariadic && isHomogeneousAggregate(Ty, Base, Members)) {
  if (Kind != AArch64ABIInfo::AAPCS)
    return ABIArgInfo::getDirect(
        llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));

  // For alignment adjusted HFAs, cap the argument alignment to 16, leave it
  // default otherwise.
  unsigned Align =
      getContext().getTypeUnadjustedAlignInChars(Ty).getQuantity();
  unsigned BaseAlign = getContext().getTypeAlignInChars(Base).getQuantity();
  Align = (Align > BaseAlign && Align >= 16) ? 16 : 0;
  return ABIArgInfo::getDirect(
      llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members), 0,
      nullptr, true, Align);
}

// Aggregates <= 16 bytes are passed directly in registers or on the stack.
if (Size <= 128) {
  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
  // same size and alignment.
  if (getTarget().isRenderScriptTarget()) {
    return coerceToIntArray(Ty, getContext(), getVMContext());
  }
  unsigned Alignment;
  if (Kind == AArch64ABIInfo::AAPCS) {
    Alignment = getContext().getTypeUnadjustedAlign(Ty);
    Alignment = Alignment < 128 ? 64 : 128;
  } else {
    Alignment = std::max(getContext().getTypeAlign(Ty),
                         (unsigned)getTarget().getPointerWidth(0));
  }
  Size = llvm::alignTo(Size, Alignment);

  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
  // For aggregates with 16-byte alignment, we use i128.
  llvm::Type *BaseTy = llvm::Type::getIntNTy(getVMContext(), Alignment);
  return ABIArgInfo::getDirect(
      Size == Alignment ? BaseTy
                        : llvm::ArrayType::get(BaseTy, Size / Alignment));
}

return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5751}

5753ABIArgInfo AArch64ABIInfo::classifyReturnType(QualType RetTy,
                                            bool IsVariadic) const {
if (RetTy->isVoidType())
  return ABIArgInfo::getIgnore();

if (const auto *VT = RetTy->getAs<VectorType>()) {
  if (VT->getVectorKind() == VectorType::SveFixedLengthDataVector ||
      VT->getVectorKind() == VectorType::SveFixedLengthPredicateVector)
    return coerceIllegalVector(RetTy);
}

// Large vector types should be returned via memory.
if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
  return getNaturalAlignIndirect(RetTy);

if (!isAggregateTypeForABI(RetTy)) {
  // Treat an enum type as its underlying type.
  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
    RetTy = EnumTy->getDecl()->getIntegerType();

  if (const auto *EIT = RetTy->getAs<ExtIntType>())
    if (EIT->getNumBits() > 128)
      return getNaturalAlignIndirect(RetTy);

  return (isPromotableIntegerTypeForABI(RetTy) && isDarwinPCS()
              ? ABIArgInfo::getExtend(RetTy)
              : ABIArgInfo::getDirect());
}

uint64_t Size = getContext().getTypeSize(RetTy);
if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
  return ABIArgInfo::getIgnore();

const Type *Base = nullptr;
uint64_t Members = 0;
if (isHomogeneousAggregate(RetTy, Base, Members) &&
    !(getTarget().getTriple().getArch() == llvm::Triple::aarch64_32 &&
      IsVariadic))
  // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
  return ABIArgInfo::getDirect();

// Aggregates <= 16 bytes are returned directly in registers or on the stack.
if (Size <= 128) {
  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
  // same size and alignment.
  if (getTarget().isRenderScriptTarget()) {
    return coerceToIntArray(RetTy, getContext(), getVMContext());
  }

  if (Size <= 64 && getDataLayout().isLittleEndian()) {
    // Composite types are returned in lower bits of a 64-bit register for LE,
    // and in higher bits for BE. However, integer types are always returned
    // in lower bits for both LE and BE, and they are not rounded up to
    // 64-bits. We can skip rounding up of composite types for LE, but not for
    // BE, otherwise composite types will be indistinguishable from integer
    // types.
    return ABIArgInfo::getDirect(
        llvm::IntegerType::get(getVMContext(), Size));
  }

  unsigned Alignment = getContext().getTypeAlign(RetTy);
  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes

  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
  // For aggregates with 16-byte alignment, we use i128.
  if (Alignment < 128 && Size == 128) {
    llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
    return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
  }
  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
}

return getNaturalAlignIndirect(RetTy);
5826}

5828/// isIllegalVectorType - check whether the vector type is legal for AArch64.
5829bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
if (const VectorType *VT = Ty->getAs<VectorType>()) {
  // Check whether VT is a fixed-length SVE vector. These types are
  // represented as scalable vectors in function args/return and must be
  // coerced from fixed vectors.
  if (VT->getVectorKind() == VectorType::SveFixedLengthDataVector ||
      VT->getVectorKind() == VectorType::SveFixedLengthPredicateVector)
    return true;

  // Check whether VT is legal.
  unsigned NumElements = VT->getNumElements();
  uint64_t Size = getContext().getTypeSize(VT);
  // NumElements should be power of 2.
  if (!llvm::isPowerOf2_32(NumElements))
    return true;

  // arm64_32 has to be compatible with the ARM logic here, which allows huge
  // vectors for some reason.
  llvm::Triple Triple = getTarget().getTriple();
  if (Triple.getArch() == llvm::Triple::aarch64_32 &&
      Triple.isOSBinFormatMachO())
    return Size <= 32;

  return Size != 64 && (Size != 128 || NumElements == 1);
}
return false;
5855}

5857bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
                                             llvm::Type *eltTy,
                                             unsigned elts) const {
if (!llvm::isPowerOf2_32(elts))
  return false;
if (totalSize.getQuantity() != 8 &&
    (totalSize.getQuantity() != 16 || elts == 1))
  return false;
return true;
5866}

5868bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
// Homogeneous aggregates for AAPCS64 must have base types of a floating
// point type or a short-vector type. This is the same as the 32-bit ABI,
// but with the difference that any floating-point type is allowed,
// including __fp16.
if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
  if (BT->isFloatingPoint())
    return true;
} else if (const VectorType *VT = Ty->getAs<VectorType>()) {
  unsigned VecSize = getContext().getTypeSize(VT);
  if (VecSize == 64 || VecSize == 128)
    return true;
}
return false;
5882}

5884bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
                                                     uint64_t Members) const {
return Members <= 4;
5887}

5889Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
                                     CodeGenFunction &CGF) const {
ABIArgInfo AI = classifyArgumentType(Ty, /*IsVariadic=*/true,
                                     CGF.CurFnInfo->getCallingConvention());
bool IsIndirect = AI.isIndirect();

llvm::Type *BaseTy = CGF.ConvertType(Ty);
if (IsIndirect)
  BaseTy = llvm::PointerType::getUnqual(BaseTy);
else if (AI.getCoerceToType())
  BaseTy = AI.getCoerceToType();

unsigned NumRegs = 1;
if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
  BaseTy = ArrTy->getElementType();
  NumRegs = ArrTy->getNumElements();
}
bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();

// The AArch64 va_list type and handling is specified in the Procedure Call
// Standard, section B.4:
//
// struct {
//   void *__stack;
//   void *__gr_top;
//   void *__vr_top;
//   int __gr_offs;
//   int __vr_offs;
// };

llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");

CharUnits TySize = getContext().getTypeSizeInChars(Ty);
CharUnits TyAlign = getContext().getTypeUnadjustedAlignInChars(Ty);

Address reg_offs_p = Address::invalid();
llvm::Value *reg_offs = nullptr;
int reg_top_index;
int RegSize = IsIndirect ? 8 : TySize.getQuantity();
if (!IsFPR) {
  // 3 is the field number of __gr_offs
  reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 3, "gr_offs_p");
  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
  reg_top_index = 1; // field number for __gr_top
  RegSize = llvm::alignTo(RegSize, 8);
} else {
  // 4 is the field number of __vr_offs.
  reg_offs_p = CGF.Builder.CreateStructGEP(VAListAddr, 4, "vr_offs_p");
  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
  reg_top_index = 2; // field number for __vr_top
  RegSize = 16 * NumRegs;
}

//=======================================
// Find out where argument was passed
//=======================================

// If reg_offs >= 0 we're already using the stack for this type of
// argument. We don't want to keep updating reg_offs (in case it overflows,
// though anyone passing 2GB of arguments, each at most 16 bytes, deserves
// whatever they get).
llvm::Value *UsingStack = nullptr;
UsingStack = CGF.Builder.CreateICmpSGE(
    reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));

CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);

// Otherwise, at least some kind of argument could go in these registers, the
// question is whether this particular type is too big.
CGF.EmitBlock(MaybeRegBlock);

// Integer arguments may need to correct register alignment (for example a
// "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
// align __gr_offs to calculate the potential address.
if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
  int Align = TyAlign.getQuantity();

  reg_offs = CGF.Builder.CreateAdd(
      reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
      "align_regoffs");
  reg_offs = CGF.Builder.CreateAnd(
      reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
      "aligned_regoffs");
}

// Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
// The fact that this is done unconditionally reflects the fact that
// allocating an argument to the stack also uses up all the remaining
// registers of the appropriate kind.
llvm::Value *NewOffset = nullptr;
NewOffset = CGF.Builder.CreateAdd(
    reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
CGF.Builder.CreateStore(NewOffset, reg_offs_p);

// Now we're in a position to decide whether this argument really was in
// registers or not.
llvm::Value *InRegs = nullptr;
InRegs = CGF.Builder.CreateICmpSLE(
    NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");

CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);

//=======================================
// Argument was in registers
//=======================================

// Now we emit the code for if the argument was originally passed in
// registers. First start the appropriate block:
CGF.EmitBlock(InRegBlock);

llvm::Value *reg_top = nullptr;
Address reg_top_p =
    CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index, "reg_top_p");
reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
Address BaseAddr(CGF.Builder.CreateInBoundsGEP(CGF.Int8Ty, reg_top, reg_offs),
                 CharUnits::fromQuantity(IsFPR ? 16 : 8));
Address RegAddr = Address::invalid();
llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);

if (IsIndirect) {
  // If it's been passed indirectly (actually a struct), whatever we find from
  // stored registers or on the stack will actually be a struct **.
  MemTy = llvm::PointerType::getUnqual(MemTy);
}

const Type *Base = nullptr;
uint64_t NumMembers = 0;
bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
if (IsHFA && NumMembers > 1) {
  // Homogeneous aggregates passed in registers will have their elements split
  // and stored 16-bytes apart regardless of size (they're notionally in qN,
  // qN+1, ...). We reload and store into a temporary local variable
  // contiguously.
  assert(!IsIndirect && "Homogeneous aggregates should be passed directly")((void)0);
  auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
  llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
  llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
  Address Tmp = CGF.CreateTempAlloca(HFATy,
                                     std::max(TyAlign, BaseTyInfo.Align));

  // On big-endian platforms, the value will be right-aligned in its slot.
  int Offset = 0;
  if (CGF.CGM.getDataLayout().isBigEndian() &&
      BaseTyInfo.Width.getQuantity() < 16)
    Offset = 16 - BaseTyInfo.Width.getQuantity();

  for (unsigned i = 0; i < NumMembers; ++i) {
    CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
    Address LoadAddr =
      CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
    LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);

    Address StoreAddr = CGF.Builder.CreateConstArrayGEP(Tmp, i);

    llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
    CGF.Builder.CreateStore(Elem, StoreAddr);
  }

  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
} else {
  // Otherwise the object is contiguous in memory.

  // It might be right-aligned in its slot.
  CharUnits SlotSize = BaseAddr.getAlignment();
  if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
      (IsHFA || !isAggregateTypeForABI(Ty)) &&
      TySize < SlotSize) {
    CharUnits Offset = SlotSize - TySize;
    BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
  }

  RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
}

CGF.EmitBranch(ContBlock);

//=======================================
// Argument was on the stack
//=======================================
CGF.EmitBlock(OnStackBlock);

Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0, "stack_p");
llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");

// Again, stack arguments may need realignment. In this case both integer and
// floating-point ones might be affected.
if (!IsIndirect && TyAlign.getQuantity() > 8) {
  int Align = TyAlign.getQuantity();

  OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);

  OnStackPtr = CGF.Builder.CreateAdd(
      OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
      "align_stack");
  OnStackPtr = CGF.Builder.CreateAnd(
      OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
      "align_stack");

  OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
}
Address OnStackAddr(OnStackPtr,
                    std::max(CharUnits::fromQuantity(8), TyAlign));

// All stack slots are multiples of 8 bytes.
CharUnits StackSlotSize = CharUnits::fromQuantity(8);
CharUnits StackSize;
if (IsIndirect)
  StackSize = StackSlotSize;
else
  StackSize = TySize.alignTo(StackSlotSize);

llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
llvm::Value *NewStack = CGF.Builder.CreateInBoundsGEP(
    CGF.Int8Ty, OnStackPtr, StackSizeC, "new_stack");

// Write the new value of __stack for the next call to va_arg
CGF.Builder.CreateStore(NewStack, stack_p);

if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
    TySize < StackSlotSize) {
  CharUnits Offset = StackSlotSize - TySize;
  OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
}

OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);

CGF.EmitBranch(ContBlock);

//=======================================
// Tidy up
//=======================================
CGF.EmitBlock(ContBlock);

Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
                               On