/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c

Bug Summary

File:	src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c
Warning:	line 4633, column 17 Assigned value is garbage or undefined
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name tc-i386.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model pic -pic-level 1 -pic-is-pie -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/gnu/usr.bin/binutils-2.17/obj/gas -resource-dir /usr/local/lib/clang/13.0.0 -D HAVE_CONFIG_H -I . -I /usr/src/gnu/usr.bin/binutils-2.17/gas -I . -D _GNU_SOURCE -I . -I /usr/src/gnu/usr.bin/binutils-2.17/gas -I ../bfd -I /usr/src/gnu/usr.bin/binutils-2.17/gas/config -I /usr/src/gnu/usr.bin/binutils-2.17/gas/../include -I /usr/src/gnu/usr.bin/binutils-2.17/gas/.. -I /usr/src/gnu/usr.bin/binutils-2.17/gas/../bfd -I /usr/src/gnu/usr.bin/binutils-2.17/gas/../intl -I ../intl -D LOCALEDIR="/usr/share/locale" -D PIE_DEFAULT=1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-null-pointer-arithmetic -fdebug-compilation-dir=/usr/src/gnu/usr.bin/binutils-2.17/obj/gas -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c /usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c
1/* i386.c -- Assemble code for the Intel 80386
 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
 2000, 2001, 2002, 2003, 2004, 2005, 2006
 Free Software Foundation, Inc.

 This file is part of GAS, the GNU Assembler.

 GAS is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.

 GAS is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.

 You should have received a copy of the GNU General Public License
 along with GAS; see the file COPYING.  If not, write to the Free
 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
 02110-1301, USA.  */

23/* Intel 80386 machine specific gas.
 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
 x86_64 support by Jan Hubicka (jh@suse.cz)
 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
 Bugs & suggestions are completely welcome.  This is free software.
 Please help us make it better.  */

30#include "as.h"
31#include "safe-ctype.h"
32#include "subsegs.h"
33#include "dwarf2dbg.h"
34#include "dw2gencfi.h"
35#include "opcode/i386.h"
36#include "elf/x86-64.h"

38#ifndef REGISTER_WARNINGS1
39#define REGISTER_WARNINGS1 1
40#endif

42#ifndef INFER_ADDR_PREFIX1
43#define INFER_ADDR_PREFIX1 1
44#endif

46#ifndef SCALE1_WHEN_NO_INDEX1
47/* Specifying a scale factor besides 1 when there is no index is
 futile.  eg. `mov (%ebx,2),%al' does exactly the same as
 `mov (%ebx),%al'.  To slavishly follow what the programmer
 specified, set SCALE1_WHEN_NO_INDEX to 0.  */
51#define SCALE1_WHEN_NO_INDEX1 1
52#endif

54#ifndef DEFAULT_ARCH"x86_64"
55#define DEFAULT_ARCH"x86_64" "i386"
56#endif

58#ifndef INLINE__inline__
59#if __GNUC__4 >= 2
60#define INLINE__inline__ __inline__
61#else
62#define INLINE__inline__
63#endif
64#endif

66static INLINE__inline__ unsigned int mode_from_disp_size PARAMS ((unsigned int))(unsigned int);
67static INLINE__inline__ int fits_in_signed_byte PARAMS ((offsetT))(offsetT);
68static INLINE__inline__ int fits_in_unsigned_byte PARAMS ((offsetT))(offsetT);
69static INLINE__inline__ int fits_in_unsigned_word PARAMS ((offsetT))(offsetT);
70static INLINE__inline__ int fits_in_signed_word PARAMS ((offsetT))(offsetT);
71static INLINE__inline__ int fits_in_unsigned_long PARAMS ((offsetT))(offsetT);
72static INLINE__inline__ int fits_in_signed_long PARAMS ((offsetT))(offsetT);
73static int smallest_imm_type PARAMS ((offsetT))(offsetT);
74static offsetT offset_in_range PARAMS ((offsetT, int))(offsetT, int);
75static int add_prefix PARAMS ((unsigned int))(unsigned int);
76static void set_code_flag PARAMS ((int))(int);
77static void set_16bit_gcc_code_flag PARAMS ((int))(int);
78static void set_intel_syntax PARAMS ((int))(int);
79static void set_cpu_arch PARAMS ((int))(int);
80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int))(int);
82#endif
83static void signed_cons PARAMS ((int))(int);
84static char *output_invalid PARAMS ((int c))(int c);
85static int i386_operand PARAMS ((char *operand_string))(char *operand_string);
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float))(char *operand_string, int got_a_float);
87static const reg_entry *parse_register PARAMS ((char *reg_string,(char *reg_string, char **end_op)
				char **end_op))(char *reg_string, char **end_op);
89static char *parse_insn PARAMS ((char *, char *))(char *, char *);
90static char *parse_operands PARAMS ((char *, const char *))(char *, const char *);
91static void swap_operands PARAMS ((void))(void);
92static void optimize_imm PARAMS ((void))(void);
93static void optimize_disp PARAMS ((void))(void);
94static int match_template PARAMS ((void))(void);
95static int check_string PARAMS ((void))(void);
96static int process_suffix PARAMS ((void))(void);
97static int check_byte_reg PARAMS ((void))(void);
98static int check_long_reg PARAMS ((void))(void);
99static int check_qword_reg PARAMS ((void))(void);
100static int check_word_reg PARAMS ((void))(void);
101static int finalize_imm PARAMS ((void))(void);
102static int process_operands PARAMS ((void))(void);
103static const seg_entry *build_modrm_byte PARAMS ((void))(void);
104static void output_insn PARAMS ((void))(void);
105static void output_branch PARAMS ((void))(void);
106static void output_jump PARAMS ((void))(void);
107static void output_interseg_jump PARAMS ((void))(void);
108static void output_imm PARAMS ((fragS *insn_start_frag,(fragS *insn_start_frag, offsetT insn_start_off)
		offsetT insn_start_off))(fragS *insn_start_frag, offsetT insn_start_off);
110static void output_disp PARAMS ((fragS *insn_start_frag,(fragS *insn_start_frag, offsetT insn_start_off)
		 offsetT insn_start_off))(fragS *insn_start_frag, offsetT insn_start_off);
112#ifndef I386COFF
113static void s_bss PARAMS ((int))(int);
114#endif
115#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
116static void handle_large_common (int small ATTRIBUTE_UNUSED__attribute__ ((__unused__)));
117#endif

119static const char *default_arch = DEFAULT_ARCH"x86_64";

121/* 'md_assemble ()' gathers together information and puts it into a
 i386_insn.  */

124union i386_op
{
  expressionS *disps;
  expressionS *imms;
  const reg_entry *regs;
};

131struct _i386_insn
{
  /* TM holds the template for the insn were currently assembling.  */
  template tm;

  /* SUFFIX holds the instruction mnemonic suffix if given.
     (e.g. 'l' for 'movl')  */
  char suffix;

  /* OPERANDS gives the number of given operands.  */
  unsigned int operands;

  /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
     of given register, displacement, memory operands and immediate
     operands.  */
  unsigned int reg_operands, disp_operands, mem_operands, imm_operands;

  /* TYPES [i] is the type (see above #defines) which tells us how to
     use OP[i] for the corresponding operand.  */
  unsigned int types[MAX_OPERANDS3];

  /* Displacement expression, immediate expression, or register for each
     operand.  */
  union i386_op op[MAX_OPERANDS3];

  /* Flags for operands.  */
  unsigned int flags[MAX_OPERANDS3];
158#define Operand_PCrel1 1

  /* Relocation type for operand */
  enum bfd_reloc_code_real reloc[MAX_OPERANDS3];

  /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
     the base index byte below.  */
  const reg_entry *base_reg;
  const reg_entry *index_reg;
  unsigned int log2_scale_factor;

  /* SEG gives the seg_entries of this insn.  They are zero unless
     explicit segment overrides are given.  */
  const seg_entry *seg[2];

  /* PREFIX holds all the given prefix opcodes (usually null).
     PREFIXES is the number of prefix opcodes.  */
  unsigned int prefixes;
  unsigned char prefix[MAX_PREFIXES6];

  /* RM and SIB are the modrm byte and the sib byte where the
     addressing modes of this insn are encoded.  */

  modrm_byte rm;
  rex_byte rex;
  sib_byte sib;
};

186typedef struct _i386_insn i386_insn;

188/* List of chars besides those in app.c:symbol_chars that can start an
 operand.  Used to prevent the scrubber eating vital white-space.  */
190const char extra_symbol_chars[] = "*%-(["
191#ifdef LEX_AT
"@"
193#endif
194#ifdef LEX_QM
"?"
196#endif
;

199#if (defined (TE_I386AIX)				\
   || ((defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF))	\
&& !defined (TE_GNU)				\
&& !defined (TE_LINUX)				\
 && !defined (TE_NETWARE)			\
&& !defined (TE_FreeBSD)			\
&& !defined (TE_NetBSD)			\
&& !defined (TE_OpenBSD1)))
207/* This array holds the chars that always start a comment.  If the
 pre-processor is disabled, these aren't very useful.  The option
 --divide will remove '/' from this list.  */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
212#define PREFIX_SEPARATOR'/' '\\'

214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR'/' '/'
217#endif

219/* This array holds the chars that only start a comment at the beginning of
 a line.  If the line seems to have the form '# 123 filename'
 .line and .file directives will appear in the pre-processed output.
 Note that input_file.c hand checks for '#' at the beginning of the
 first line of the input file.  This is because the compiler outputs
 #NO_APP at the beginning of its output.
 Also note that comments started like this one will always work if
 '/' isn't otherwise defined.  */
227const char line_comment_chars[] = "#/";

229const char line_separator_chars[] = ";";

231/* Chars that can be used to separate mant from exp in floating point
 nums.  */
233const char EXP_CHARS[] = "eE";

235/* Chars that mean this number is a floating point constant
 As in 0f12.456
 or    0d1.2345e12.  */
238const char FLT_CHARS[] = "fFdDxX";

240/* Tables for lexical analysis.  */
241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];

247/* Lexical macros.  */
248#define is_mnemonic_char(x)(mnemonic_chars[(unsigned char) x]) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x)(operand_chars[(unsigned char) x]) (operand_chars[(unsigned char) x])
250#define is_register_char(x)(register_chars[(unsigned char) x]) (register_chars[(unsigned char) x])
251#define is_space_char(x)((x) == ' ') ((x) == ' ')
252#define is_identifier_char(x)(identifier_chars[(unsigned char) x]) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x)(digit_chars[(unsigned char) x]) (digit_chars[(unsigned char) x])

255/* All non-digit non-letter characters that may occur in an operand.  */
256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";

258/* md_assemble() always leaves the strings it's passed unaltered.  To
 effect this we maintain a stack of saved characters that we've smashed
 with '\0's (indicating end of strings for various sub-fields of the
 assembler instruction).  */
262static char save_stack[32];
263static char *save_stack_p;
264#define END_STRING_AND_SAVE(s)do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) \
do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s)do { *(s) = *--save_stack_p; } while (0) \
do { *(s) = *--save_stack_p; } while (0)

269/* The instruction we're assembling.  */
270static i386_insn i;

272/* Possible templates for current insn.  */
273static const templates *current_templates;

275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max.  */
276static expressionS disp_expressions[2], im_expressions[2];

278/* Current operand we are working on.  */
279static int this_operand;

281/* We support four different modes.  FLAG_CODE variable is used to distinguish
 these.  */

284enum flag_code {
CODE_32BIT,
CODE_16BIT,
CODE_64BIT };
288#define NUM_FLAG_CODE((int) CODE_64BIT + 1) ((int) CODE_64BIT + 1)

290static enum flag_code flag_code;
291static unsigned int object_64bit;
292static int use_rela_relocations = 0;

294/* The names used to print error messages.  */
295static const char *flag_code_names[] =
{
  "32",
  "16",
  "64"
};

302/* 1 for intel syntax,
 0 if att syntax.  */
304static int intel_syntax = 0;

306/* 1 if register prefix % not required.  */
307static int allow_naked_reg = 0;

309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
 leave, push, and pop instructions so that gcc has the same stack
 frame as in 32 bit mode.  */
312static char stackop_size = '\0';

314/* Non-zero to optimize code alignment.  */
315int optimize_align_code = 1;

317/* Non-zero to quieten some warnings.  */
318static int quiet_warnings = 0;

320/* CPU name.  */
321static const char *cpu_arch_name = NULL((void*)0);
322static const char *cpu_sub_arch_name = NULL((void*)0);

324/* CPU feature flags.  */
325static unsigned int cpu_arch_flags = CpuUnknownFlags(0x1|0x2|0x4|0x8|0x10|0x20|0x40 |0x80|0x400|0x800|0x1000|0x2000
|0x4000|0x20000|0x100000 |0x8000|0x10000|0x100|0x200|0x40000|
0x80000|0x200000 |0x400000|0x800000|0x1000000|0x2000000|0x4000000
) | CpuNo640x10000000;

327/* If set, conditional jumps are not automatically promoted to handle
 larger than a byte offset.  */
329static unsigned int no_cond_jump_promotion = 0;

331/* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
332static symbolS *GOT_symbol;

334/* The dwarf2 return column, adjusted for 32 or 64 bit.  */
335unsigned int x86_dwarf2_return_column;

337/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
338int x86_cie_data_alignment;

340/* Interface to relax_segment.
 There are 3 major relax states for 386 jump insns because the
 different types of jumps add different sizes to frags when we're
 figuring out what sort of jump to choose to reach a given label.  */

345/* Types.  */
346#define UNCOND_JUMP0 0
347#define COND_JUMP1 1
348#define COND_JUMP862 2

350/* Sizes.  */
351#define CODE161	1
352#define SMALL0	0
353#define SMALL16(0 | 1) (SMALL0 | CODE161)
354#define BIG2	2
355#define BIG16(2 | 1)	(BIG2 | CODE161)

357#ifndef INLINE__inline__
358#ifdef __GNUC__4
359#define INLINE__inline__ __inline__
360#else
361#define INLINE__inline__
362#endif
363#endif

365#define ENCODE_RELAX_STATE(type, size)((relax_substateT) (((type) << 2) | (size))) \
((relax_substateT) (((type) << 2) | (size)))
367#define TYPE_FROM_RELAX_STATE(s)((s) >> 2) \
((s) >> 2)
369#define DISP_SIZE_FROM_RELAX_STATE(s)((((s) & 3) == 2 ? 4 : (((s) & 3) == (2 | 1) ? 2 : 1)
)) \
  ((((s) & 3) == BIG2 ? 4 : (((s) & 3) == BIG16(2 | 1) ? 2 : 1)))

372/* This table is used by relax_frag to promote short jumps to long
 ones where necessary.  SMALL (short) jumps may be promoted to BIG
 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long).  We
 don't allow a short jump in a 32 bit code segment to be promoted to
 a 16 bit offset jump because it's slower (requires data size
 prefix), and doesn't work, unless the destination is in the bottom
 64k of the code segment (The top 16 bits of eip are zeroed).  */

380const relax_typeS md_relax_table[] =
381{
/* The fields are:
   1) most positive reach of this state,
   2) most negative reach of this state,
   3) how many bytes this mode will have in the variable part of the frag
   4) which index into the table to try if we can't fit into this one.  */

/* UNCOND_JUMP states.  */
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)((relax_substateT) (((0) << 2) | (2)))},
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)((relax_substateT) (((0) << 2) | ((2 | 1))))},
/* dword jmp adds 4 bytes to frag:
   0 extra opcode bytes, 4 displacement bytes.  */
{0, 0, 4, 0},
/* word jmp adds 2 byte2 to frag:
   0 extra opcode bytes, 2 displacement bytes.  */
{0, 0, 2, 0},

/* COND_JUMP states.  */
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)((relax_substateT) (((1) << 2) | (2)))},
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)((relax_substateT) (((1) << 2) | ((2 | 1))))},
/* dword conditionals adds 5 bytes to frag:
   1 extra opcode byte, 4 displacement bytes.  */
{0, 0, 5, 0},
/* word conditionals add 3 bytes to frag:
   1 extra opcode byte, 2 displacement bytes.  */
{0, 0, 3, 0},

/* COND_JUMP86 states.  */
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)((relax_substateT) (((2) << 2) | (2)))},
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)((relax_substateT) (((2) << 2) | ((2 | 1))))},
/* dword conditionals adds 5 bytes to frag:
   1 extra opcode byte, 4 displacement bytes.  */
{0, 0, 5, 0},
/* word conditionals add 4 bytes to frag:
   1 displacement byte and a 3 byte long branch insn.  */
{0, 0, 4, 0}
417};

419static const arch_entry cpu_arch[] = {
{"i8086",	Cpu0860x1 },
{"i186",	Cpu0860x1|Cpu1860x2 },
{"i286",	Cpu0860x1|Cpu1860x2|Cpu2860x4 },
{"i386",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8 },
{"i486",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10 },
{"i586",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20 },
{"i686",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40 },
{"pentium",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20 },
{"pentiumpro",Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40 },
{"pentiumii",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuMMX0x800 },
{"pentiumiii",Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000 },
{"pentium4",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuP40x80|CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000|CpuSSE20x4000 },
{"prescott",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuP40x80|CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000|CpuSSE20x4000|CpuPNI0x20000 },
{"k6",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|CpuK60x100|CpuMMX0x800 },
{"k6_2",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|CpuK60x100|CpuMMX0x800|Cpu3dnow0x8000 },
{"athlon",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuK60x100|CpuAthlon0x200|CpuMMX0x800|CpuMMX20x1000|Cpu3dnow0x8000|Cpu3dnowA0x10000 },
{"sledgehammer",Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuK60x100|CpuAthlon0x200|CpuSledgehammer0x400|CpuMMX0x800|CpuMMX20x1000|Cpu3dnow0x8000|Cpu3dnowA0x10000|CpuSSE0x2000|CpuSSE20x4000 },
{"opteron",	Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuK60x100|CpuAthlon0x200|CpuSledgehammer0x400|CpuMMX0x800|CpuMMX20x1000|Cpu3dnow0x8000|Cpu3dnowA0x10000|CpuSSE0x2000|CpuSSE20x4000 },
{".mmx",	CpuMMX0x800 },
{".sse",	CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000 },
{".sse2",	CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000|CpuSSE20x4000 },
{".sse3",	CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000|CpuSSE20x4000|CpuSSE30x20000 },
{".3dnow",	CpuMMX0x800|Cpu3dnow0x8000 },
{".3dnowa",	CpuMMX0x800|CpuMMX20x1000|Cpu3dnow0x8000|Cpu3dnowA0x10000 },
{".padlock",	CpuPadLock0x40000 },
{".pacifica",	CpuSVME0x80000 },
{".svme",	CpuSVME0x80000 },
{NULL((void*)0), 0 }
448};

450const pseudo_typeS md_pseudo_table[] =
451{
452#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
{"align", s_align_bytes, 0},
454#else
{"align", s_align_ptwo, 0},
456#endif
{"arch", set_cpu_arch, 0},
458#ifndef I386COFF
{"bss", s_bss, 0},
460#endif
{"ffloat", float_cons, 'f'},
{"dfloat", float_cons, 'd'},
{"tfloat", float_cons, 'x'},
{"value", cons, 2},
{"slong", signed_cons, 4},
{"noopt", s_ignore, 0},
{"optim", s_ignore, 0},
{"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
{"code16", set_code_flag, CODE_16BIT},
{"code32", set_code_flag, CODE_32BIT},
{"code64", set_code_flag, CODE_64BIT},
{"intel_syntax", set_intel_syntax, 1},
{"att_syntax", set_intel_syntax, 0},
474#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
{"largecomm", handle_large_common, 0},
476#else
{"file", (void (*) PARAMS ((int))(int)) dwarf2_directive_file, 0},
{"loc", dwarf2_directive_loc, 0},
{"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
480#endif
481#ifdef TE_PE
{"secrel32", pe_directive_secrel, 0},
483#endif
{0, 0, 0}
485};

487/* For interface with expression ().  */
488extern char *input_line_pointer;

490/* Hash table for instruction mnemonic lookup.  */
491static struct hash_control *op_hash;

493/* Hash table for register lookup.  */
494static struct hash_control *reg_hash;
495
496void
497i386_align_code (fragP, count)
   fragS *fragP;
   int count;
500{
/* Various efficient no-op patterns for aligning code labels.
   Note: Don't try to assemble the instructions in the comments.
   0L and 0w are not legal.  */
static const char f32_1[] =
  {0x90};					/* nop			*/
static const char f32_2[] =
  {0x89,0xf6};				/* movl %esi,%esi	*/
static const char f32_15[] =
  {0xeb,0x0d,0xCC,0xCC,0xCC,0xCC,0xCC,	/* jmp .+15; lotsa int3	*/
   0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC};
static const char f16_3[] =
  {0x8d,0x74,0x00};				/* lea 0(%esi),%esi	*/
static const char f16_4[] =
  {0x8d,0xb4,0x00,0x00};			/* lea 0w(%si),%si	*/
static const char f16_5[] =
  {0x90,					/* nop			*/
   0x8d,0xb4,0x00,0x00};			/* lea 0w(%si),%si	*/
static const char f16_6[] =
  {0x89,0xf6,					/* mov %si,%si		*/
   0x8d,0xbd,0x00,0x00};			/* lea 0w(%di),%di	*/
static const char f16_7[] =
  {0x8d,0x74,0x00,				/* lea 0(%si),%si	*/
   0x8d,0xbd,0x00,0x00};			/* lea 0w(%di),%di	*/
static const char f16_8[] =
  {0x8d,0xb4,0x00,0x00,			/* lea 0w(%si),%si	*/
   0x8d,0xbd,0x00,0x00};			/* lea 0w(%di),%di	*/
static const char f64_2[] =
  {0x66,0x90};        /* data16, nop*/
static const char *const f32_patt[] = {
  f32_1, f32_2, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15,
  f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
};
static const char *const f16_patt[] = {
  f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
  f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
};
static const char *const f64_patt[] = {
  f32_1, f64_2, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15,
  f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
};

if (count <= 0 || count > 15)
  return;

if (flag_code == CODE_64BIT)
  {
    memcpy(fragP->fr_literal + fragP->fr_fix,
           f64_patt[count -1], count);
    if (count > 2)
        /* Adjust jump offset */
        fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
  }
else
  if (flag_code == CODE_16BIT)
    {
memcpy (fragP->fr_literal + fragP->fr_fix,
f16_patt[count - 1], count);
if (count > 8)
 /* Adjust jump offset.  */
 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
    }
  else
   { 
    memcpy (fragP->fr_literal + fragP->fr_fix,
     f32_patt[count - 1], count);
    if (count > 2)
        /* Adjust jump offset */
        fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
   }
fragP->fr_var = count;
571}

573static INLINE__inline__ unsigned int
574mode_from_disp_size (t)
   unsigned int t;
576{
return (t & Disp80x1000) ? 1 : (t & (Disp160x2000 | Disp320x4000 | Disp32S0x8000)) ? 2 : 0;
578}

580static INLINE__inline__ int
581fits_in_signed_byte (num)
   offsetT num;
583{
return (num >= -128) && (num <= 127);
585}

587static INLINE__inline__ int
588fits_in_unsigned_byte (num)
   offsetT num;
590{
return (num & 0xff) == num;
592}

594static INLINE__inline__ int
595fits_in_unsigned_word (num)
   offsetT num;
597{
return (num & 0xffff) == num;
599}

601static INLINE__inline__ int
602fits_in_signed_word (num)
   offsetT num;
604{
return (-32768 <= num) && (num <= 32767);
606}
607static INLINE__inline__ int
608fits_in_signed_long (num)
   offsetT num ATTRIBUTE_UNUSED__attribute__ ((__unused__));
610{
611#ifndef BFD64
return 1;
613#else
return (!(-((offsetT) 1 << 31) & num)
 || (-((offsetT) 1 << 31) & num) == -((offsetT) 1 << 31));
616#endif
617}				/* fits_in_signed_long() */
618static INLINE__inline__ int
619fits_in_unsigned_long (num)
   offsetT num ATTRIBUTE_UNUSED__attribute__ ((__unused__));
621{
622#ifndef BFD64
return 1;
624#else
return (num & (((offsetT) 2 << 31) - 1)) == num;
626#endif
627}				/* fits_in_unsigned_long() */

629static int
630smallest_imm_type (num)
   offsetT num;
632{
if (cpu_arch_flags != (Cpu0860x1 | Cpu1860x2 | Cpu2860x4 | Cpu3860x8 | Cpu4860x10 | CpuNo640x10000000))
  {
    /* This code is disabled on the 486 because all the Imm1 forms
in the opcode table are slower on the i486.  They're the
versions with the implicitly specified single-position
displacement, which has another syntax if you really want to
use that form.  */
    if (num == 1)
return Imm10x400 | Imm80x10 | Imm8S0x20 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200;
  }
return (fits_in_signed_byte (num)
 ? (Imm8S0x20 | Imm80x10 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200)
 : fits_in_unsigned_byte (num)
 ? (Imm80x10 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200)
 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
 ? (Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200)
 : fits_in_signed_long (num)
 ? (Imm320x80 | Imm32S0x100 | Imm640x200)
 : fits_in_unsigned_long (num)
 ? (Imm320x80 | Imm640x200)
 : Imm640x200);
654}

656static offsetT
657offset_in_range (val, size)
   offsetT val;
   int size;
660{
addressT mask;

switch (size)
  {
  case 1: mask = ((addressT) 1 <<  8) - 1; break;
  case 2: mask = ((addressT) 1 << 16) - 1; break;
  case 4: mask = ((addressT) 2 << 31) - 1; break;
668#ifdef BFD64
  case 8: mask = ((addressT) 2 << 63) - 1; break;
670#endif
  default: abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 671, __PRETTY_FUNCTION__);
  }

/* If BFD64, sign extend val.  */
if (!use_rela_relocations)
  if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
    val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);

if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
  {
    char buf1[40], buf2[40];

    sprint_value (buf1, val);
    sprint_value (buf2, val & mask);
    as_warn (_("%s shortened to %s")("%s shortened to %s"), buf1, buf2);
  }
return val & mask;
688}

690/* Returns 0 if attempting to add a prefix where one from the same
 class already exists, 1 if non rep/repne added, 2 if rep/repne
 added.  */
693static int
694add_prefix (prefix)
   unsigned int prefix;
696{
int ret = 1;
unsigned int q;

if (prefix >= REX_OPCODE0x40 && prefix < REX_OPCODE0x40 + 16
    && flag_code == CODE_64BIT)
  {
    if ((i.prefix[REX_PREFIX5] & prefix & REX_MODE648)
 || ((i.prefix[REX_PREFIX5] & (REX_EXTX4 | REX_EXTY2 | REX_EXTZ1))
     && (prefix & (REX_EXTX4 | REX_EXTY2 | REX_EXTZ1))))
ret = 0;
    q = REX_PREFIX5;
  }
else
  {
    switch (prefix)
{
default:
 abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 714, __PRETTY_FUNCTION__);

case CS_PREFIX_OPCODE0x2e:
case DS_PREFIX_OPCODE0x3e:
case ES_PREFIX_OPCODE0x26:
case FS_PREFIX_OPCODE0x64:
case GS_PREFIX_OPCODE0x65:
case SS_PREFIX_OPCODE0x36:
 q = SEG_PREFIX4;
 break;

case REPNE_PREFIX_OPCODE0xf2:
case REPE_PREFIX_OPCODE0xf3:
 ret = 2;
 /* fall thru */
case LOCK_PREFIX_OPCODE0xf0:
 q = LOCKREP_PREFIX1;
 break;

case FWAIT_OPCODE0x9b:
 q = WAIT_PREFIX0;
 break;

case ADDR_PREFIX_OPCODE0x67:
 q = ADDR_PREFIX2;
 break;

case DATA_PREFIX_OPCODE0x66:
 q = DATA_PREFIX3;
 break;
}
    if (i.prefix[q] != 0)
ret = 0;
  }

if (ret)
  {
    if (!i.prefix[q])
++i.prefixes;
    i.prefix[q] |= prefix;
  }
else
  as_bad (_("same type of prefix used twice")("same type of prefix used twice"));

return ret;
759}

761static void
762set_code_flag (value)
   int value;
764{
flag_code = value;
cpu_arch_flags &= ~(Cpu640x8000000 | CpuNo640x10000000);
cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu640x8000000 : CpuNo640x10000000);
if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer0x400))
  {
    as_bad (_("64bit mode not supported on this CPU.")("64bit mode not supported on this CPU."));
  }
if (value == CODE_32BIT && !(cpu_arch_flags & Cpu3860x8))
  {
    as_bad (_("32bit mode not supported on this CPU.")("32bit mode not supported on this CPU."));
  }
stackop_size = '\0';
777}

779static void
780set_16bit_gcc_code_flag (new_code_flag)
   int new_code_flag;
782{
flag_code = new_code_flag;
cpu_arch_flags &= ~(Cpu640x8000000 | CpuNo640x10000000);
cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu640x8000000 : CpuNo640x10000000);
stackop_size = LONG_MNEM_SUFFIX'l';
787}

789static void
790set_intel_syntax (syntax_flag)
   int syntax_flag;
792{
/* Find out if register prefixing is specified.  */
int ask_naked_reg = 0;

SKIP_WHITESPACE ()((*input_line_pointer == ' ') ? ++input_line_pointer : 0);
if (!is_end_of_line[(unsigned char) *input_line_pointer])
  {
    char *string = input_line_pointer;
    int e = get_symbol_end ();

    if (strcmp (string, "prefix") == 0)
ask_naked_reg = 1;
    else if (strcmp (string, "noprefix") == 0)
ask_naked_reg = -1;
    else
as_bad (_("bad argument to syntax directive.")("bad argument to syntax directive."));
    *input_line_pointer = e;
  }
demand_empty_rest_of_line ();

intel_syntax = syntax_flag;

if (ask_naked_reg == 0)
  allow_naked_reg = (intel_syntax
       && (bfd_get_symbol_leading_char (stdoutput)((stdoutput)->xvec->symbol_leading_char) != '\0'));
else
  allow_naked_reg = (ask_naked_reg < 0);

identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
identifier_chars['$'] = intel_syntax ? '$' : 0;
822}

824static void
825set_cpu_arch (dummy)
   int dummy ATTRIBUTE_UNUSED__attribute__ ((__unused__));
827{
SKIP_WHITESPACE ()((*input_line_pointer == ' ') ? ++input_line_pointer : 0);

if (!is_end_of_line[(unsigned char) *input_line_pointer])
  {
    char *string = input_line_pointer;
    int e = get_symbol_end ();
    int i;

    for (i = 0; cpu_arch[i].name; i++)
{
 if (strcmp (string, cpu_arch[i].name) == 0)
   {
     if (*string != '.')
{
  cpu_arch_name = cpu_arch[i].name;
  cpu_sub_arch_name = NULL((void*)0);
  cpu_arch_flags = (cpu_arch[i].flags
		    | (flag_code == CODE_64BIT ? Cpu640x8000000 : CpuNo640x10000000));
  break;
}
     if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
{
  cpu_sub_arch_name = cpu_arch[i].name;
  cpu_arch_flags |= cpu_arch[i].flags;
}
     *input_line_pointer = e;
     demand_empty_rest_of_line ();
     return;
   }
}
    if (!cpu_arch[i].name)
as_bad (_("no such architecture: `%s'")("no such architecture: `%s'"), string);

    *input_line_pointer = e;
  }
else
  as_bad (_("missing cpu architecture")("missing cpu architecture"));

no_cond_jump_promotion = 0;
if (*input_line_pointer == ','
    && !is_end_of_line[(unsigned char) input_line_pointer[1]])
  {
    char *string = ++input_line_pointer;
    int e = get_symbol_end ();

    if (strcmp (string, "nojumps") == 0)
no_cond_jump_promotion = 1;
    else if (strcmp (string, "jumps") == 0)
;
    else
as_bad (_("no such architecture modifier: `%s'")("no such architecture modifier: `%s'"), string);

    *input_line_pointer = e;
  }

demand_empty_rest_of_line ();
884}

886unsigned long
887i386_mach ()
888{
if (!strcmp (default_arch, "x86_64"))
  return bfd_mach_x86_6464;
else if (!strcmp (default_arch, "i386"))
  return bfd_mach_i386_i3861;
else
  as_fatal (_("Unknown architecture")("Unknown architecture"));
895}
896
897void
898md_begin ()
899{
const char *hash_err;

/* Initialize op_hash hash table.  */
op_hash = hash_new ();

{
  const template *optab;
  templates *core_optab;

  /* Setup for loop.  */
  optab = i386_optab;
  core_optab = (templates *) xmalloc (sizeof (templates));
  core_optab->start = optab;

  while (1)
    {
++optab;
if (optab->name == NULL((void*)0)
   || strcmp (optab->name, (optab - 1)->name) != 0)
 {
   /* different name --> ship out current template list;
      add to hash table; & begin anew.  */
   core_optab->end = optab;
   hash_err = hash_insert (op_hash,
		    (optab - 1)->name,
		    (PTRvoid *) core_optab);
   if (hash_err)
     {
as_fatal (_("Internal Error:  Can't hash %s: %s")("Internal Error:  Can't hash %s: %s"),
	  (optab - 1)->name,
	  hash_err);
     }
   if (optab->name == NULL((void*)0))
     break;
   core_optab = (templates *) xmalloc (sizeof (templates));
   core_optab->start = optab;
 }
    }
}

/* Initialize reg_hash hash table.  */
reg_hash = hash_new ();
{
  const reg_entry *regtab;

  for (regtab = i386_regtab;
regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
regtab++)
    {
hash_err = hash_insert (reg_hash, regtab->reg_name, (PTRvoid *) regtab);
if (hash_err)
 as_fatal (_("Internal Error:  Can't hash %s: %s")("Internal Error:  Can't hash %s: %s"),
    regtab->reg_name,
    hash_err);
    }
}

/* Fill in lexical tables:  mnemonic_chars, operand_chars.  */
{
  int c;
  char *p;

  for (c = 0; c < 256; c++)
    {
if (ISDIGIT (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isdigit
)))
 {
   digit_chars[c] = c;
   mnemonic_chars[c] = c;
   register_chars[c] = c;
   operand_chars[c] = c;
 }
else if (ISLOWER (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_islower
)))
 {
   mnemonic_chars[c] = c;
   register_chars[c] = c;
   operand_chars[c] = c;
 }
else if (ISUPPER (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isupper
)))
 {
   mnemonic_chars[c] = TOLOWER (c)_sch_tolower[(c) & 0xff];
   register_chars[c] = mnemonic_chars[c];
   operand_chars[c] = c;
 }

if (ISALPHA (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isalpha
)) || ISDIGIT (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isdigit
)))
 identifier_chars[c] = c;
else if (c >= 128)
 {
   identifier_chars[c] = c;
   operand_chars[c] = c;
 }
    }

993#ifdef LEX_AT
  identifier_chars['@'] = '@';
995#endif
996#ifdef LEX_QM
  identifier_chars['?'] = '?';
  operand_chars['?'] = '?';
999#endif
  digit_chars['-'] = '-';
  mnemonic_chars['-'] = '-';
  identifier_chars['_'] = '_';
  identifier_chars['.'] = '.';

  for (p = operand_special_chars; *p != '\0'; p++)
    operand_chars[(unsigned char) *p] = *p;
}

1009#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
if (IS_ELF1)
  {
    record_alignment (text_section, 2);
    record_alignment (data_section, 2);
    record_alignment (bss_section, 2);
  }
1016#endif

if (flag_code == CODE_64BIT)
  {
    x86_dwarf2_return_column = 16;
    x86_cie_data_alignment = -8;
  }
else
  {
    x86_dwarf2_return_column = 8;
    x86_cie_data_alignment = -4;
  }
1028}

1030void
1031i386_print_statistics (file)
   FILE *file;
1033{
hash_print_statistics (file, "i386 opcode", op_hash);
hash_print_statistics (file, "i386 register", reg_hash);
1036}
1037
1038#ifdef DEBUG386

1040/* Debugging routines for md_assemble.  */
1041static void pi PARAMS ((char *, i386_insn *))(char *, i386_insn *);
1042static void pte PARAMS ((template *))(template *);
1043static void pt PARAMS ((unsigned int))(unsigned int);
1044static void pe PARAMS ((expressionS *))(expressionS *);
1045static void ps PARAMS ((symbolS *))(symbolS *);

1047static void
1048pi (line, x)
   char *line;
   i386_insn *x;
1051{
unsigned int i;

fprintf (stdout(&__sF[1]), "%s: template ", line);
pte (&x->tm);
fprintf (stdout(&__sF[1]), "  address: base %s  index %s  scale %x\n",
  x->base_reg ? x->base_reg->reg_name : "none",
  x->index_reg ? x->index_reg->reg_name : "none",
  x->log2_scale_factor);
fprintf (stdout(&__sF[1]), "  modrm:  mode %x  reg %x  reg/mem %x\n",
  x->rm.mode, x->rm.reg, x->rm.regmem);
fprintf (stdout(&__sF[1]), "  sib:  base %x  index %x  scale %x\n",
  x->sib.base, x->sib.index, x->sib.scale);
fprintf (stdout(&__sF[1]), "  rex: 64bit %x  extX %x  extY %x  extZ %x\n",
  (x->rex & REX_MODE648) != 0,
  (x->rex & REX_EXTX4) != 0,
  (x->rex & REX_EXTY2) != 0,
  (x->rex & REX_EXTZ1) != 0);
for (i = 0; i < x->operands; i++)
  {
    fprintf (stdout(&__sF[1]), "    #%d:  ", i + 1);
    pt (x->types[i]);
    fprintf (stdout(&__sF[1]), "\n");
    if (x->types[i]
 & (Reg(0x1|0x2|0x4|0x8) | SReg20x1000000 | SReg30x2000000 | Control0x80000 | Debug0x100000 | Test0x200000 | RegMMX0x10000000 | RegXMM0x20000000))
fprintf (stdout(&__sF[1]), "%s\n", x->op[i].regs->reg_name);
    if (x->types[i] & Imm(0x10|0x20|0x40|0x100|0x80|0x200))
pe (x->op[i].imms);
    if (x->types[i] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000))
pe (x->op[i].disps);
  }
1082}

1084static void
1085pte (t)
   template *t;
1087{
unsigned int i;
fprintf (stdout(&__sF[1]), " %d operands ", t->operands);
fprintf (stdout(&__sF[1]), "opcode %x ", t->base_opcode);
if (t->extension_opcode != None0xffff)
  fprintf (stdout(&__sF[1]), "ext %x ", t->extension_opcode);
if (t->opcode_modifier & D0x2)
  fprintf (stdout(&__sF[1]), "D");
if (t->opcode_modifier & W0x1)
  fprintf (stdout(&__sF[1]), "W");
fprintf (stdout(&__sF[1]), "\n");
for (i = 0; i < t->operands; i++)
  {
    fprintf (stdout(&__sF[1]), "    #%d type ", i + 1);
    pt (t->operand_types[i]);
    fprintf (stdout(&__sF[1]), "\n");
  }
1104}

1106static void
1107pe (e)
   expressionS *e;
1109{
fprintf (stdout(&__sF[1]), "    operation     %d\n", e->X_op);
fprintf (stdout(&__sF[1]), "    add_number    %ld (%lx)\n",
  (long) e->X_add_number, (long) e->X_add_number);
if (e->X_add_symbol)
  {
    fprintf (stdout(&__sF[1]), "    add_symbol    ");
    ps (e->X_add_symbol);
    fprintf (stdout(&__sF[1]), "\n");
  }
if (e->X_op_symbol)
  {
    fprintf (stdout(&__sF[1]), "    op_symbol    ");
    ps (e->X_op_symbol);
    fprintf (stdout(&__sF[1]), "\n");
  }
1125}

1127static void
1128ps (s)
   symbolS *s;
1130{
fprintf (stdout(&__sF[1]), "%s type %s%s",
  S_GET_NAME (s),
  S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
  segment_name (S_GET_SEGMENT (s))((S_GET_SEGMENT (s))->name + 0));
1135}

1137static struct type_name
{
  unsigned int mask;
  char *tname;
}
1142const type_names[] =
1143{
{ Reg80x1, "r8" },
{ Reg160x2, "r16" },
{ Reg320x4, "r32" },
{ Reg640x8, "r64" },
{ Imm80x10, "i8" },
{ Imm8S0x20, "i8s" },
{ Imm160x40, "i16" },
{ Imm320x80, "i32" },
{ Imm32S0x100, "i32s" },
{ Imm640x200, "i64" },
{ Imm10x400, "i1" },
{ BaseIndex0x800, "BaseIndex" },
{ Disp80x1000, "d8" },
{ Disp160x2000, "d16" },
{ Disp320x4000, "d32" },
{ Disp32S0x8000, "d32s" },
{ Disp640x10000, "d64" },
{ InOutPortReg0x20000, "InOutPortReg" },
{ ShiftCount0x40000, "ShiftCount" },
{ Control0x80000, "control reg" },
{ Test0x200000, "test reg" },
{ Debug0x100000, "debug reg" },
{ FloatReg0x400000, "FReg" },
{ FloatAcc0x800000, "FAcc" },
{ SReg20x1000000, "SReg2" },
{ SReg30x2000000, "SReg3" },
{ Acc0x4000000, "Acc" },
{ JumpAbsolute0x8000000, "Jump Absolute" },
{ RegMMX0x10000000, "rMMX" },
{ RegXMM0x20000000, "rXMM" },
{ EsSeg0x40000000, "es" },
{ 0, "" }
1176};

1178static void
1179pt (t)
   unsigned int t;
1181{
const struct type_name *ty;

for (ty = type_names; ty->mask; ty++)
  if (t & ty->mask)
    fprintf (stdout(&__sF[1]), "%s, ", ty->tname);
fflush (stdout(&__sF[1]));
1188}

1190#endif /* DEBUG386 */
1191
1192static bfd_reloc_code_real_type
1193reloc (unsigned int size,
   int pcrel,
   int sign,
   bfd_reloc_code_real_type other)
1197{
if (other != NO_RELOCBFD_RELOC_NONE)
  {
    reloc_howto_type *reloc;

    if (size == 8)
switch (other)
 {
   case BFD_RELOC_X86_64_GOT32:
     return BFD_RELOC_X86_64_GOT64;
     break;
   case BFD_RELOC_X86_64_PLTOFF64:
     return BFD_RELOC_X86_64_PLTOFF64;
     break;
   case BFD_RELOC_X86_64_GOTPC32:
     other = BFD_RELOC_X86_64_GOTPC64;
     break;
   case BFD_RELOC_X86_64_GOTPCREL:
     other = BFD_RELOC_X86_64_GOTPCREL64;
     break;
   case BFD_RELOC_X86_64_TPOFF32:
     other = BFD_RELOC_X86_64_TPOFF64;
     break;
   case BFD_RELOC_X86_64_DTPOFF32:
     other = BFD_RELOC_X86_64_DTPOFF64;
     break;
   default:
     break;
 }

    /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
    if (size == 4 && flag_code != CODE_64BIT)
sign = -1;

    reloc = bfd_reloc_type_lookup (stdoutput, other);
    if (!reloc)
as_bad (_("unknown relocation (%u)")("unknown relocation (%u)"), other);
    else if (size != bfd_get_reloc_size (reloc))
as_bad (_("%u-byte relocation cannot be applied to %u-byte field")("%u-byte relocation cannot be applied to %u-byte field"),
bfd_get_reloc_size (reloc),
size);
    else if (pcrel && !reloc->pc_relative)
as_bad (_("non-pc-relative relocation for pc-relative field")("non-pc-relative relocation for pc-relative field"));
    else if ((reloc->complain_on_overflow == complain_overflow_signed
&& !sign)
      || (reloc->complain_on_overflow == complain_overflow_unsigned
&& sign > 0))
as_bad (_("relocated field and relocation type differ in signedness")("relocated field and relocation type differ in signedness"));
    else
return other;
    return NO_RELOCBFD_RELOC_NONE;
  }

if (pcrel)
  {
    if (!sign)
as_bad (_("there are no unsigned pc-relative relocations")("there are no unsigned pc-relative relocations"));
    switch (size)
{
case 1: return BFD_RELOC_8_PCREL;
case 2: return BFD_RELOC_16_PCREL;
case 4: return BFD_RELOC_32_PCREL;
case 8: return BFD_RELOC_64_PCREL;
}
    as_bad (_("cannot do %u byte pc-relative relocation")("cannot do %u byte pc-relative relocation"), size);
  }
else
  {
    if (sign > 0)
switch (size)
 {
 case 4: return BFD_RELOC_X86_64_32S;
 }
    else
switch (size)
 {
 case 1: return BFD_RELOC_8;
 case 2: return BFD_RELOC_16;
 case 4: return BFD_RELOC_32;
 case 8: return BFD_RELOC_64;
 }
    as_bad (_("cannot do %s %u byte relocation")("cannot do %s %u byte relocation"),
     sign > 0 ? "signed" : "unsigned", size);
  }

abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 1282, __PRETTY_FUNCTION__);
return BFD_RELOC_NONE;
1284}

1286/* Here we decide which fixups can be adjusted to make them relative to
 the beginning of the section instead of the symbol.  Basically we need
 to make sure that the dynamic relocations are done correctly, so in
 some cases we force the original symbol to be used.  */

1291int
1292tc_i386_fix_adjustable (fixP)
   fixS *fixP ATTRIBUTE_UNUSED__attribute__ ((__unused__));
1294{
1295#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
if (!IS_ELF1)
  return 1;

/* Don't adjust pc-relative references to merge sections in 64-bit
   mode.  */
if (use_rela_relocations
    && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE0x1000000) != 0
    && fixP->fx_pcrel)
  return 0;

/* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
   and changed later by validate_fix.  */
if (GOT_symbol && fixP->fx_subsy == GOT_symbol
    && fixP->fx_r_type == BFD_RELOC_32_PCREL)
  return 0;

/* adjust_reloc_syms doesn't know about the GOT.  */
if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
    || fixP->fx_r_type == BFD_RELOC_386_PLT32
    || fixP->fx_r_type == BFD_RELOC_386_GOT32
    || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
    || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
    || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
    || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
    || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
    || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
    || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
    || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
    || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
    || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
    || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
    || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
    || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
    || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
    || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
    || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
    || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
    || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
    || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
    || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
    || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
    || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
    || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
    || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
    || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
  return 0;
1342#endif
return 1;
1344}

1346static int intel_float_operand PARAMS ((const char *mnemonic))(const char *mnemonic);

1348static int
1349intel_float_operand (mnemonic)
   const char *mnemonic;
1351{
/* Note that the value returned is meaningful only for opcodes with (memory)
   operands, hence the code here is free to improperly handle opcodes that
   have no operands (for better performance and smaller code). */

if (mnemonic[0] != 'f')
  return 0; /* non-math */

switch (mnemonic[1])
  {
  /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
     the fs segment override prefix not currently handled because no
     call path can make opcodes without operands get here */
  case 'i':
    return 2 /* integer op */;
  case 'l':
    if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
return 3; /* fldcw/fldenv */
    break;
  case 'n':
    if (mnemonic[2] != 'o' /* fnop */)
return 3; /* non-waiting control op */
    break;
  case 'r':
    if (mnemonic[2] == 's')
return 3; /* frstor/frstpm */
    break;
  case 's':
    if (mnemonic[2] == 'a')
return 3; /* fsave */
    if (mnemonic[2] == 't')
{
 switch (mnemonic[3])
   {
   case 'c': /* fstcw */
   case 'd': /* fstdw */
   case 'e': /* fstenv */
   case 's': /* fsts[gw] */
     return 3;
   }
}
    break;
  case 'x':
    if (mnemonic[2] == 'r' || mnemonic[2] == 's')
return 0; /* fxsave/fxrstor are not really math ops */
    break;
  }

return 1;
1400}

1402/* This is the guts of the machine-dependent assembler.  LINE points to a
 machine dependent instruction.  This function is supposed to emit
 the frags/bytes it assembles to.  */

1406void
1407md_assemble (line)
   char *line;
1409{
int j;
char mnemonic[MAX_MNEM_SIZE16];

/* Initialize globals.  */
memset (&i, '\0', sizeof (i));
for (j = 0; j < MAX_OPERANDS3; j++)
  i.reloc[j] = NO_RELOCBFD_RELOC_NONE;
memset (disp_expressions, '\0', sizeof (disp_expressions));
memset (im_expressions, '\0', sizeof (im_expressions));
save_stack_p = save_stack;

/* First parse an instruction mnemonic & call i386_operand for the operands.
   We assume that the scrubber has arranged it so that line[0] is the valid
   start of a (possibly prefixed) mnemonic.  */

line = parse_insn (line, mnemonic);
if (line == NULL((void*)0))
  return;

line = parse_operands (line, mnemonic);
if (line == NULL((void*)0))
  return;

/* Now we've parsed the mnemonic into a set of templates, and have the
   operands at hand.  */

/* All intel opcodes have reversed operands except for "bound" and
   "enter".  We also don't reverse intersegment "jmp" and "call"
   instructions with 2 immediate operands so that the immediate segment
   precedes the offset, as it does when in AT&T mode.  "enter" and the
   intersegment "jmp" and "call" instructions are the only ones that
   have two immediate operands.  */
if (intel_syntax && i.operands > 1
    && (strcmp (mnemonic, "bound") != 0)
    && (strcmp (mnemonic, "invlpga") != 0)
    && !((i.types[0] & Imm(0x10|0x20|0x40|0x100|0x80|0x200)) && (i.types[1] & Imm(0x10|0x20|0x40|0x100|0x80|0x200))))
  swap_operands ();

if (i.imm_operands)
  optimize_imm ();

/* Don't optimize displacement for movabs since it only takes 64bit
   displacement.  */
if (i.disp_operands
    && (flag_code != CODE_64BIT
 || strcmp (mnemonic, "movabs") != 0))
  optimize_disp ();

/* Next, we find a template that matches the given insn,
   making sure the overlap of the given operands types is consistent
   with the template operand types.  */

if (!match_template ())
  return;

if (intel_syntax)
  {
    /* Undo SYSV386_COMPAT brokenness when in Intel mode.  See i386.h  */
    if (SYSV386_COMPAT1
 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
i.tm.base_opcode ^= FloatR0x8;

    /* Zap movzx and movsx suffix.  The suffix may have been set from
"word ptr" or "byte ptr" on the source operand, but we'll use
the suffix later to choose the destination register.  */
    if ((i.tm.base_opcode & ~9) == 0x0fb6)
{
 if (i.reg_operands < 2
     && !i.suffix
     && (~i.tm.opcode_modifier
  & (No_bSuf0x40000
     | No_wSuf0x80000
     | No_lSuf0x100000
     | No_sSuf0x200000
     | No_xSuf0x800000
     | No_qSuf0x400000)))
   as_bad (_("ambiguous operand size for `%s'")("ambiguous operand size for `%s'"), i.tm.name);

 i.suffix = 0;
}
  }

if (i.tm.opcode_modifier & FWait0x1000000)
  if (!add_prefix (FWAIT_OPCODE0x9b))
    return;

/* Check string instruction segment overrides.  */
if ((i.tm.opcode_modifier & IsString0x2000000) != 0 && i.mem_operands != 0)
  {
    if (!check_string ())
return;
  }

if (!process_suffix ())
  return;

/* Make still unresolved immediate matches conform to size of immediate
   given in i.suffix.  */
if (!finalize_imm ())
  return;

if (i.types[0] & Imm10x400)
  i.imm_operands = 0;	/* kludge for shift insns.  */
if (i.types[0] & ImplicitRegister(0x20000|0x40000|0x4000000|0x800000))
  i.reg_operands--;
if (i.types[1] & ImplicitRegister(0x20000|0x40000|0x4000000|0x800000))
  i.reg_operands--;
if (i.types[2] & ImplicitRegister(0x20000|0x40000|0x4000000|0x800000))
  i.reg_operands--;

if (i.tm.opcode_modifier & ImmExt0x10000000)
  {
    expressionS *exp;

    if ((i.tm.cpu_flags & (CpuPNI0x20000|CpuXSAVE0x400000|CpuSMAP0x4000000)) && i.operands > 0)
{
 /* These Intel Prescott New Instructions have the fixed
    operands with an opcode suffix which is coded in the same
    place as an 8-bit immediate field would be. Here we check
    those operands and remove them afterwards.  */
 unsigned int x;

 for (x = 0; x < i.operands; x++)
   if (i.op[x].regs->reg_num != x)
     as_bad (_("can't use register '%%%s' as operand %d in '%s'.")("can't use register '%%%s' as operand %d in '%s'."),
	i.op[x].regs->reg_name, x + 1, i.tm.name);
 i.operands = 0;
}

    /* These AMD 3DNow! and Intel Katmai New Instructions have an
opcode suffix which is coded in the same place as an 8-bit
immediate field would be.  Here we fake an 8-bit immediate
operand from the opcode suffix stored in tm.extension_opcode.  */

    assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS)((void) ((i.imm_operands == 0 && i.operands <= 2 &&
< 3) ? 0 : (as_assert ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 1544, __PRETTY_FUNCTION__), 0)));

    exp = &im_expressions[i.imm_operands++];
    i.op[i.operands].imms = exp;
    i.types[i.operands++] = Imm80x10;
    exp->X_op = O_constant;
    exp->X_add_number = i.tm.extension_opcode;
    i.tm.extension_opcode = None0xffff;
  }

/* For insns with operands there are more diddles to do to the opcode.  */
if (i.operands)
  {
    if (!process_operands ())
return;
  }
else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh0x80000000) != 0)
  {
    /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.  */
    as_warn (_("translating to `%sp'")("translating to `%sp'"), i.tm.name);
  }

/* Handle conversion of 'int $3' --> special int3 insn.  */
if (i.tm.base_opcode == INT_OPCODE0xcd && i.op[0].imms->X_add_number == 3)
  {
    i.tm.base_opcode = INT3_OPCODE0xcc;
    i.imm_operands = 0;
  }

if ((i.tm.opcode_modifier & (Jump0x40 | JumpByte0x100 | JumpDword0x80))
    && i.op[0].disps->X_op == O_constant)
  {
    /* Convert "jmp constant" (and "call constant") to a jump (call) to
the absolute address given by the constant.  Since ix86 jumps and
calls are pc relative, we need to generate a reloc.  */
    i.op[0].disps->X_add_symbol = &abs_symbol;
    i.op[0].disps->X_op = O_symbol;
  }

if ((i.tm.opcode_modifier & Rex640x40000000) != 0)
  i.rex |= REX_MODE648;

/* For 8 bit registers we need an empty rex prefix.  Also if the
   instruction already has a prefix, we need to convert old
   registers to new ones.  */

if (((i.types[0] & Reg80x1) != 0
     && (i.op[0].regs->reg_flags & RegRex640x2) != 0)
    || ((i.types[1] & Reg80x1) != 0
 && (i.op[1].regs->reg_flags & RegRex640x2) != 0)
    || (((i.types[0] & Reg80x1) != 0 || (i.types[1] & Reg80x1) != 0)
 && i.rex != 0))
  {
    int x;

    i.rex |= REX_OPCODE0x40;
    for (x = 0; x < 2; x++)
{
 /* Look for 8 bit operand that uses old registers.  */
 if ((i.types[x] & Reg80x1) != 0
     && (i.op[x].regs->reg_flags & RegRex640x2) == 0)
   {
     /* In case it is "hi" register, give up.  */
     if (i.op[x].regs->reg_num > 3)
as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.")("can't encode register '%%%s' in an instruction requiring REX prefix."
),
	i.op[x].regs->reg_name);

     /* Otherwise it is equivalent to the extended register.
 Since the encoding doesn't change this is merely
 cosmetic cleanup for debug output.  */

     i.op[x].regs = i.op[x].regs + 8;
   }
}
  }

if (i.rex != 0)
  add_prefix (REX_OPCODE0x40 | i.rex);

/* We are ready to output the insn.  */
output_insn ();
1625}

1627static char *
1628parse_insn (line, mnemonic)
   char *line;
   char *mnemonic;
1631{
char *l = line;
char *token_start = l;
char *mnem_p;
int supported;
const template *t;

/* Non-zero if we found a prefix only acceptable with string insns.  */
const char *expecting_string_instruction = NULL((void*)0);

while (1)
  {
    mnem_p = mnemonic;
    while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
{
 mnem_p++;
 if (mnem_p >= mnemonic + MAX_MNEM_SIZE16)
   {
     as_bad (_("no such instruction: `%s'")("no such instruction: `%s'"), token_start);
     return NULL((void*)0);
   }
 l++;
}
    if (!is_space_char (*l)((*l) == ' ')
 && *l != END_OF_INSN'\0'
 && (intel_syntax
     || (*l != PREFIX_SEPARATOR'/'
  && *l != ',')))
{
 as_bad (_("invalid character %s in mnemonic")("invalid character %s in mnemonic"),
  output_invalid (*l));
 return NULL((void*)0);
}
    if (token_start == l)
{
 if (!intel_syntax && *l == PREFIX_SEPARATOR'/')
   as_bad (_("expecting prefix; got nothing")("expecting prefix; got nothing"));
 else
   as_bad (_("expecting mnemonic; got nothing")("expecting mnemonic; got nothing"));
 return NULL((void*)0);
}

    /* Look up instruction (or prefix) via hash table.  */
    current_templates = hash_find (op_hash, mnemonic);

    if (*l != END_OF_INSN'\0'
 && (!is_space_char (*l)((*l) == ' ') || l[1] != END_OF_INSN'\0')
 && current_templates
 && (current_templates->start->opcode_modifier & IsPrefix0x8000000))
{
 if (current_templates->start->cpu_flags
     & (flag_code != CODE_64BIT ? Cpu640x8000000 : CpuNo640x10000000))
   {
     as_bad ((flag_code != CODE_64BIT
       ? _("`%s' is only supported in 64-bit mode")("`%s' is only supported in 64-bit mode")
       : _("`%s' is not supported in 64-bit mode")("`%s' is not supported in 64-bit mode")),
      current_templates->start->name);
     return NULL((void*)0);
   }
 /* If we are in 16-bit mode, do not allow addr16 or data16.
    Similarly, in 32-bit mode, do not allow addr32 or data32.  */
 if ((current_templates->start->opcode_modifier & (Size160x2000 | Size320x4000))
     && flag_code != CODE_64BIT
     && (((current_templates->start->opcode_modifier & Size320x4000) != 0)
  ^ (flag_code == CODE_16BIT)))
   {
     as_bad (_("redundant %s prefix")("redundant %s prefix"),
      current_templates->start->name);
     return NULL((void*)0);
   }
 /* Add prefix, checking for repeated prefixes.  */
 switch (add_prefix (current_templates->start->base_opcode))
   {
   case 0:
     return NULL((void*)0);
   case 2:
     expecting_string_instruction = current_templates->start->name;
     break;
   }
 /* Skip past PREFIX_SEPARATOR and reset token_start.  */
 token_start = ++l;
}
    else
break;
  }

if (!current_templates)
  {
    /* See if we can get a match by trimming off a suffix.  */
    switch (mnem_p[-1])
{
case WORD_MNEM_SUFFIX'w':
 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
   i.suffix = SHORT_MNEM_SUFFIX's';
 else
case BYTE_MNEM_SUFFIX'b':
case QWORD_MNEM_SUFFIX'q':
 i.suffix = mnem_p[-1];
 mnem_p[-1] = '\0';
 current_templates = hash_find (op_hash, mnemonic);
 break;
case SHORT_MNEM_SUFFIX's':
case LONG_MNEM_SUFFIX'l':
 if (!intel_syntax)
   {
     i.suffix = mnem_p[-1];
     mnem_p[-1] = '\0';
     current_templates = hash_find (op_hash, mnemonic);
   }
 break;

 /* Intel Syntax.  */
case 'd':
 if (intel_syntax)
   {
     if (intel_float_operand (mnemonic) == 1)
i.suffix = SHORT_MNEM_SUFFIX's';
     else
i.suffix = LONG_MNEM_SUFFIX'l';
     mnem_p[-1] = '\0';
     current_templates = hash_find (op_hash, mnemonic);
   }
 break;
}
    if (!current_templates)
{
 as_bad (_("no such instruction: `%s'")("no such instruction: `%s'"), token_start);
 return NULL((void*)0);
}
  }

if (current_templates->start->opcode_modifier & (Jump0x40 | JumpByte0x100))
  {
    /* Check for a branch hint.  We allow ",pt" and ",pn" for
predict taken and predict not taken respectively.
I'm not sure that branch hints actually do anything on loop
and jcxz insns (JumpByte) for current Pentium4 chips.  They
may work in the future and it doesn't hurt to accept them
now.  */
    if (l[0] == ',' && l[1] == 'p')
{
 if (l[2] == 't')
   {
     if (!add_prefix (DS_PREFIX_OPCODE0x3e))
return NULL((void*)0);
     l += 3;
   }
 else if (l[2] == 'n')
   {
     if (!add_prefix (CS_PREFIX_OPCODE0x2e))
return NULL((void*)0);
     l += 3;
   }
}
  }
/* Any other comma loses.  */
if (*l == ',')
  {
    as_bad (_("invalid character %s in mnemonic")("invalid character %s in mnemonic"),
     output_invalid (*l));
    return NULL((void*)0);
  }

/* Check if instruction is supported on specified architecture.  */
supported = 0;
for (t = current_templates->start; t < current_templates->end; ++t)
  {
    if (!((t->cpu_flags & ~(Cpu640x8000000 | CpuNo640x10000000))
   & ~(cpu_arch_flags & ~(Cpu640x8000000 | CpuNo640x10000000))))
 supported |= 1;
    if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo640x10000000 : Cpu640x8000000)))
 supported |= 2;
  }
if (!(supported & 2))
  {
    as_bad (flag_code == CODE_64BIT
     ? _("`%s' is not supported in 64-bit mode")("`%s' is not supported in 64-bit mode")
     : _("`%s' is only supported in 64-bit mode")("`%s' is only supported in 64-bit mode"),
     current_templates->start->name);
    return NULL((void*)0);
  }
if (!(supported & 1))
  {
    as_warn (_("`%s' is not supported on `%s%s'")("`%s' is not supported on `%s%s'"),
      current_templates->start->name,
      cpu_arch_name,
      cpu_sub_arch_name ? cpu_sub_arch_name : "");
  }
else if ((Cpu3860x8 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
  {
    as_warn (_("use .code16 to ensure correct addressing mode")("use .code16 to ensure correct addressing mode"));
  }

/* Check for rep/repne without a string instruction.  */
if (expecting_string_instruction)
  {
    static templates override;

    for (t = current_templates->start; t < current_templates->end; ++t)
if (t->opcode_modifier & IsString0x2000000)
 break;
    if (t >= current_templates->end)
{
 as_bad (_("expecting string instruction after `%s'")("expecting string instruction after `%s'"),
       expecting_string_instruction);
 return NULL((void*)0);
}
    for (override.start = t; t < current_templates->end; ++t)
if (!(t->opcode_modifier & IsString0x2000000))
 break;
    override.end = t;
    current_templates = &override;
  }

return l;
1846}

1848static char *
1849parse_operands (l, mnemonic)
   char *l;
   const char *mnemonic;
1852{
char *token_start;

/* 1 if operand is pending after ','.  */
unsigned int expecting_operand = 0;

/* Non-zero if operand parens not balanced.  */
unsigned int paren_not_balanced;

while (*l != END_OF_INSN'\0')
  {
    /* Skip optional white space before operand.  */
    if (is_space_char (*l)((*l) == ' '))
++l;
    if (!is_operand_char (*l)(operand_chars[(unsigned char) *l]) && *l != END_OF_INSN'\0')
{
 as_bad (_("invalid character %s before operand %d")("invalid character %s before operand %d"),
  output_invalid (*l),
  i.operands + 1);
 return NULL((void*)0);
}
    token_start = l;	/* after white space */
    paren_not_balanced = 0;
    while (paren_not_balanced || *l != ',')
{
 if (*l == END_OF_INSN'\0')
   {
     if (paren_not_balanced)
{
  if (!intel_syntax)
    as_bad (_("unbalanced parenthesis in operand %d.")("unbalanced parenthesis in operand %d."),
	    i.operands + 1);
  else
    as_bad (_("unbalanced brackets in operand %d.")("unbalanced brackets in operand %d."),
	    i.operands + 1);
  return NULL((void*)0);
}
     else
break;	/* we are done */
   }
 else if (!is_operand_char (*l)(operand_chars[(unsigned char) *l]) && !is_space_char (*l)((*l) == ' '))
   {
     as_bad (_("invalid character %s in operand %d")("invalid character %s in operand %d"),
      output_invalid (*l),
      i.operands + 1);
     return NULL((void*)0);
   }
 if (!intel_syntax)
   {
     if (*l == '(')
++paren_not_balanced;
     if (*l == ')')
--paren_not_balanced;
   }
 else
   {
     if (*l == '[')
++paren_not_balanced;
     if (*l == ']')
--paren_not_balanced;
   }
 l++;
}
    if (l != token_start)
{			/* Yes, we've read in another operand.  */
 unsigned int operand_ok;
 this_operand = i.operands++;
 if (i.operands > MAX_OPERANDS3)
   {
     as_bad (_("spurious operands; (%d operands/instruction max)")("spurious operands; (%d operands/instruction max)"),
      MAX_OPERANDS3);
     return NULL((void*)0);
   }
 /* Now parse operand adding info to 'i' as we go along.  */
 END_STRING_AND_SAVE (l)do { *save_stack_p++ = *(l); *(l) = '\0'; } while (0);

 if (intel_syntax)
   operand_ok =
     i386_intel_operand (token_start,
		  intel_float_operand (mnemonic));
 else
   operand_ok = i386_operand (token_start);

 RESTORE_END_STRING (l)do { *(l) = *--save_stack_p; } while (0);
 if (!operand_ok)
   return NULL((void*)0);
}
    else
{
 if (expecting_operand)
   {
   expecting_operand_after_comma:
     as_bad (_("expecting operand after ','; got nothing")("expecting operand after ','; got nothing"));
     return NULL((void*)0);
   }
 if (*l == ',')
   {
     as_bad (_("expecting operand before ','; got nothing")("expecting operand before ','; got nothing"));
     return NULL((void*)0);
   }
}

    /* Now *l must be either ',' or END_OF_INSN.  */
    if (*l == ',')
{
 if (*++l == END_OF_INSN'\0')
   {
     /* Just skip it, if it's \n complain.  */
     goto expecting_operand_after_comma;
   }
 expecting_operand = 1;
}
  }
return l;
1966}

1968static void
1969swap_operands ()
1970{
union i386_op temp_op;
unsigned int temp_type;
enum bfd_reloc_code_real temp_reloc;
int xchg1 = 0;
int xchg2 = 0;

if (i.operands == 2)
  {
    xchg1 = 0;
    xchg2 = 1;
  }
else if (i.operands == 3)
  {
    xchg1 = 0;
    xchg2 = 2;
  }
temp_type = i.types[xchg2];
i.types[xchg2] = i.types[xchg1];
i.types[xchg1] = temp_type;
temp_op = i.op[xchg2];
i.op[xchg2] = i.op[xchg1];
i.op[xchg1] = temp_op;
temp_reloc = i.reloc[xchg2];
i.reloc[xchg2] = i.reloc[xchg1];
i.reloc[xchg1] = temp_reloc;

if (i.mem_operands == 2)
  {
    const seg_entry *temp_seg;
    temp_seg = i.seg[0];
    i.seg[0] = i.seg[1];
    i.seg[1] = temp_seg;
  }
2004}

2006/* Try to ensure constant immediates are represented in the smallest
 opcode possible.  */
2008static void
2009optimize_imm ()
2010{
char guess_suffix = 0;
int op;

if (i.suffix)
  guess_suffix = i.suffix;
else if (i.reg_operands)
  {
    /* Figure out a suffix from the last register operand specified.
We can't do this properly yet, ie. excluding InOutPortReg,
but the following works for instructions with immediates.
In any case, we can't set i.suffix yet.  */
    for (op = i.operands; --op >= 0;)
if (i.types[op] & Reg(0x1|0x2|0x4|0x8))
 {
   if (i.types[op] & Reg80x1)
     guess_suffix = BYTE_MNEM_SUFFIX'b';
   else if (i.types[op] & Reg160x2)
     guess_suffix = WORD_MNEM_SUFFIX'w';
   else if (i.types[op] & Reg320x4)
     guess_suffix = LONG_MNEM_SUFFIX'l';
   else if (i.types[op] & Reg640x8)
     guess_suffix = QWORD_MNEM_SUFFIX'q';
   break;
 }
  }
else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX3] != 0))
  guess_suffix = WORD_MNEM_SUFFIX'w';

for (op = i.operands; --op >= 0;)
  if (i.types[op] & Imm(0x10|0x20|0x40|0x100|0x80|0x200))
    {
switch (i.op[op].imms->X_op)
 {
 case O_constant:
   /* If a suffix is given, this operand may be shortened.  */
   switch (guess_suffix)
     {
     case LONG_MNEM_SUFFIX'l':
i.types[op] |= Imm320x80 | Imm640x200;
break;
     case WORD_MNEM_SUFFIX'w':
i.types[op] |= Imm160x40 | Imm32S0x100 | Imm320x80 | Imm640x200;
break;
     case BYTE_MNEM_SUFFIX'b':
i.types[op] |= Imm160x40 | Imm80x10 | Imm8S0x20 | Imm32S0x100 | Imm320x80 | Imm640x200;
break;
     }

   /* If this operand is at most 16 bits, convert it
      to a signed 16 bit number before trying to see
      whether it will fit in an even smaller size.
      This allows a 16-bit operand such as $0xffe0 to
      be recognised as within Imm8S range.  */
   if ((i.types[op] & Imm160x40)
&& (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
     {
i.op[op].imms->X_add_number =
  (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
     }
   if ((i.types[op] & Imm320x80)
&& ((i.op[op].imms->X_add_number & ~(offsetT) 0xffffffffL)
    == 0))
     {
i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
				^ ((offsetT) 1 << 31))
			       - ((offsetT) 1 << 31));
     }
   i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);

   /* We must avoid matching of Imm32 templates when 64bit
      only immediate is available.  */
   if (guess_suffix == QWORD_MNEM_SUFFIX'q')
     i.types[op] &= ~Imm320x80;
   break;

 case O_absent:
 case O_register:
   abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 2088, __PRETTY_FUNCTION__);

   /* Symbols and expressions.  */
 default:
   /* Convert symbolic operand to proper sizes for matching, but don't
      prevent matching a set of insns that only supports sizes other
      than those matching the insn suffix.  */
   {
     unsigned int mask, allowed = 0;
     const template *t;

     for (t = current_templates->start; t < current_templates->end; ++t)
       allowed |= t->operand_types[op];
     switch (guess_suffix)
{
case QWORD_MNEM_SUFFIX'q':
  mask = Imm640x200 | Imm32S0x100;
  break;
case LONG_MNEM_SUFFIX'l':
  mask = Imm320x80;
  break;
case WORD_MNEM_SUFFIX'w':
  mask = Imm160x40;
  break;
case BYTE_MNEM_SUFFIX'b':
  mask = Imm80x10;
  break;
default:
  mask = 0;
  break;
}
if (mask & allowed)
  i.types[op] &= mask;
   }
   break;
 }
    }
2125}

2127/* Try to use the smallest displacement type too.  */
2128static void
2129optimize_disp ()
2130{
int op;

for (op = i.operands; --op >= 0;)
  if (i.types[op] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000))
    {
if (i.op[op].disps->X_op == O_constant)
 {
   offsetT disp = i.op[op].disps->X_add_number;

   if ((i.types[op] & Disp160x2000)
&& (disp & ~(offsetT) 0xffff) == 0)
     {
/* If this operand is at most 16 bits, convert
   to a signed 16 bit number and don't use 64bit
   displacement.  */
disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
i.types[op] &= ~Disp640x10000;
     }
   if ((i.types[op] & Disp320x4000)
&& (disp & ~(offsetT) 0xffffffffL) == 0)
     {
/* If this operand is at most 32 bits, convert
   to a signed 32 bit number and don't use 64bit
   displacement.  */
disp &= (offsetT) 0xffffffffL;
disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
i.types[op] &= ~Disp640x10000;
     }
   if (!disp && (i.types[op] & BaseIndex0x800))
     {
i.types[op] &= ~Disp(0x1000|0x2000|0x4000|0x8000|0x10000);
i.op[op].disps = 0;
i.disp_operands--;
     }
   else if (flag_code == CODE_64BIT)
     {
if (fits_in_signed_long (disp))
  {
    i.types[op] &= ~Disp640x10000;
    i.types[op] |= Disp32S0x8000;
  }
if (fits_in_unsigned_long (disp))
  i.types[op] |= Disp320x4000;
     }
   if ((i.types[op] & (Disp320x4000 | Disp32S0x8000 | Disp160x2000))
&& fits_in_signed_byte (disp))
     i.types[op] |= Disp80x1000;
 }
else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
 {
   fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
	 i.op[op].disps, 0, i.reloc[op]);
   i.types[op] &= ~Disp(0x1000|0x2000|0x4000|0x8000|0x10000);
 }
else
 /* We only support 64bit displacement on constants.  */
 i.types[op] &= ~Disp640x10000;
    }
2190}

2192static int
2193match_template ()
2194{
/* Points to template once we've found it.  */
const template *t;
unsigned int overlap0, overlap1, overlap2;
unsigned int found_reverse_match;
int suffix_check;

2201#define MATCH(overlap, given, template)((overlap & ~0x8000000) && (((given) & (0x800
 | 0x8000000)) == ((overlap) & (0x800 | 0x8000000))))				\
((overlap & ~JumpAbsolute0x8000000)					\
 && (((given) & (BaseIndex0x800 | JumpAbsolute0x8000000))			\
     == ((overlap) & (BaseIndex0x800 | JumpAbsolute0x8000000))))

/* If given types r0 and r1 are registers they must be of the same type
   unless the expected operand type register overlap is null.
   Note that Acc in a template matches every size of reg.  */
2209#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1)(((g0) & (0x1|0x2|0x4|0x8)) == 0 || ((g1) & (0x1|0x2|
0x4|0x8)) == 0 || ((g0) & (0x1|0x2|0x4|0x8)) == ((g1) &
 (0x1|0x2|0x4|0x8)) || ((((m0) & 0x4000000) ? (0x1|0x2|0x4
|0x8) : (t0)) & (((m1) & 0x4000000) ? (0x1|0x2|0x4|0x8
) : (t1)) & (0x1|0x2|0x4|0x8)) == 0 )	\
(((g0) & Reg(0x1|0x2|0x4|0x8)) == 0 || ((g1) & Reg(0x1|0x2|0x4|0x8)) == 0			\
 || ((g0) & Reg(0x1|0x2|0x4|0x8)) == ((g1) & Reg(0x1|0x2|0x4|0x8))				\
 || ((((m0) & Acc0x4000000) ? Reg(0x1|0x2|0x4|0x8) : (t0)) & (((m1) & Acc0x4000000) ? Reg(0x1|0x2|0x4|0x8) : (t1)) & Reg(0x1|0x2|0x4|0x8)) == 0 )

overlap0 = 0;
overlap1 = 0;
overlap2 = 0;
found_reverse_match = 0;
suffix_check = (i.suffix == BYTE_MNEM_SUFFIX'b'
  ? No_bSuf0x40000
  : (i.suffix == WORD_MNEM_SUFFIX'w'
     ? No_wSuf0x80000
     : (i.suffix == SHORT_MNEM_SUFFIX's'
	? No_sSuf0x200000
	: (i.suffix == LONG_MNEM_SUFFIX'l'
	   ? No_lSuf0x100000
	   : (i.suffix == QWORD_MNEM_SUFFIX'q'
	      ? No_qSuf0x400000
	      : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX'x'
		 ? No_xSuf0x800000 : 0))))));

for (t = current_templates->start; t < current_templates->end; t++)
  {
    /* Must have right number of operands.  */
    if (i.operands != t->operands)
continue;

    /* Check the suffix, except for some instructions in intel mode.  */
    if ((t->opcode_modifier & suffix_check)
 && !(intel_syntax
      && (t->opcode_modifier & IgnoreSize0x10000)))
continue;

    /* In general, don't allow 64-bit operands in 32-bit mode.  */
    if (i.suffix == QWORD_MNEM_SUFFIX'q'
 && flag_code != CODE_64BIT
 && (intel_syntax
     ? (!(t->opcode_modifier & IgnoreSize0x10000)
 && !intel_float_operand (t->name))
     : intel_float_operand (t->name) != 2)
 && (!(t->operand_types[0] & (RegMMX0x10000000 | RegXMM0x20000000))
     || !(t->operand_types[t->operands > 1] & (RegMMX0x10000000 | RegXMM0x20000000)))
 && (t->base_opcode != 0x0fc7
     || t->extension_opcode != 1 /* cmpxchg8b */))
continue;

    /* Do not verify operands when there are none.  */
    else if (!t->operands)
{
 if (t->cpu_flags & ~cpu_arch_flags)
   continue;
 /* We've found a match; break out of loop.  */
 break;
}

    overlap0 = i.types[0] & t->operand_types[0];
    switch (t->operands)
{
case 1:
 if (!MATCH (overlap0, i.types[0], t->operand_types[0])((overlap0 & ~0x8000000) && (((i.types[0]) & (
0x800 | 0x8000000)) == ((overlap0) & (0x800 | 0x8000000))
)))
   continue;
 break;
case 2:
case 3:
 overlap1 = i.types[1] & t->operand_types[1];
 if (!MATCH (overlap0, i.types[0], t->operand_types[0])((overlap0 & ~0x8000000) && (((i.types[0]) & (
0x800 | 0x8000000)) == ((overlap0) & (0x800 | 0x8000000))
))
     || !MATCH (overlap1, i.types[1], t->operand_types[1])((overlap1 & ~0x8000000) && (((i.types[1]) & (
0x800 | 0x8000000)) == ((overlap1) & (0x800 | 0x8000000))
))
     /* monitor in SSE3 is a very special case.  The first
 register and the second register may have differnet
 sizes.  */
     || !((t->base_opcode == 0x0f01
    && t->extension_opcode == 0xc8)
   || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2
|0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[0])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[1])) & (0x1|0x2|0x4|0x8)) == 0 )
				 t->operand_types[0],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2
|0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[0])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[1])) & (0x1|0x2|0x4|0x8)) == 0 )
				 overlap1, i.types[1],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2
|0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[0])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[1])) & (0x1|0x2|0x4|0x8)) == 0 )
				 t->operand_types[1])(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2
|0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[0])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[1])) & (0x1|0x2|0x4|0x8)) == 0 )))
   {
     /* Check if other direction is valid ...  */
     if ((t->opcode_modifier & (D0x2 | FloatD0x400)) == 0)
continue;

     /* Try reversing direction of operands.  */
     overlap0 = i.types[0] & t->operand_types[1];
     overlap1 = i.types[1] & t->operand_types[0];
     if (!MATCH (overlap0, i.types[0], t->operand_types[1])((overlap0 & ~0x8000000) && (((i.types[0]) & (
0x800 | 0x8000000)) == ((overlap0) & (0x800 | 0x8000000))
))
  || !MATCH (overlap1, i.types[1], t->operand_types[0])((overlap1 & ~0x8000000) && (((i.types[1]) & (
0x800 | 0x8000000)) == ((overlap1) & (0x800 | 0x8000000))
))
  || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2
|0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[1])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[0])) & (0x1|0x2|0x4|0x8)) == 0 )
				 t->operand_types[1],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2
|0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[1])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[0])) & (0x1|0x2|0x4|0x8)) == 0 )
				 overlap1, i.types[1],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2
|0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[1])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[0])) & (0x1|0x2|0x4|0x8)) == 0 )
				 t->operand_types[0])(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2
|0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[1])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[0])) & (0x1|0x2|0x4|0x8)) == 0 ))
{
  /* Does not match either direction.  */
  continue;
}
     /* found_reverse_match holds which of D or FloatDR
 we've found.  */
     found_reverse_match = t->opcode_modifier & (D0x2 | FloatDR0x400);
   }
 /* Found a forward 2 operand match here.  */
 else if (t->operands == 3)
   {
     /* Here we make use of the fact that there are no
 reverse match 3 operand instructions, and all 3
 operand instructions only need to be checked for
 register consistency between operands 2 and 3.  */
     overlap2 = i.types[2] & t->operand_types[2];
     if (!MATCH (overlap2, i.types[2], t->operand_types[2])((overlap2 & ~0x8000000) && (((i.types[2]) & (
0x800 | 0x8000000)) == ((overlap2) & (0x800 | 0x8000000))
))
  || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],(((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[2])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2
|0x4|0x8)) == ((i.types[2]) & (0x1|0x2|0x4|0x8)) || ((((overlap1
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[1])) & (((overlap2) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[2])) & (0x1|0x2|0x4|0x8)) == 0 )
				 t->operand_types[1],(((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[2])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2
|0x4|0x8)) == ((i.types[2]) & (0x1|0x2|0x4|0x8)) || ((((overlap1
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[1])) & (((overlap2) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[2])) & (0x1|0x2|0x4|0x8)) == 0 )
				 overlap2, i.types[2],(((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[2])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2
|0x4|0x8)) == ((i.types[2]) & (0x1|0x2|0x4|0x8)) || ((((overlap1
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[1])) & (((overlap2) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[2])) & (0x1|0x2|0x4|0x8)) == 0 )
				 t->operand_types[2])(((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[2])
 & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2
|0x4|0x8)) == ((i.types[2]) & (0x1|0x2|0x4|0x8)) || ((((overlap1
) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types
[1])) & (((overlap2) & 0x4000000) ? (0x1|0x2|0x4|0x8)
 : (t->operand_types[2])) & (0x1|0x2|0x4|0x8)) == 0 ))

continue;
   }
 /* Found either forward/reverse 2 or 3 operand match here:
    slip through to break.  */
}
    if (t->cpu_flags & ~cpu_arch_flags)
{
 found_reverse_match = 0;
 continue;
}
    /* We've found a match; break out of loop.  */
    break;
  }

if (t == current_templates->end)
  {
    /* We found no match.  */
    as_bad (_("suffix or operands invalid for `%s'")("suffix or operands invalid for `%s'"),
     current_templates->start->name);
    return 0;
  }

if (!quiet_warnings)
  {
    if (!intel_syntax
 && ((i.types[0] & JumpAbsolute0x8000000)
     != (t->operand_types[0] & JumpAbsolute0x8000000)))
{
 as_warn (_("indirect %s without `*'")("indirect %s without `*'"), t->name);
}

    if ((t->opcode_modifier & (IsPrefix0x8000000 | IgnoreSize0x10000))
 == (IsPrefix0x8000000 | IgnoreSize0x10000))
{
 /* Warn them that a data or address size prefix doesn't
    affect assembly of the next line of code.  */
 as_warn (_("stand-alone `%s' prefix")("stand-alone `%s' prefix"), t->name);
}
  }

/* Copy the template we found.  */
i.tm = *t;
if (found_reverse_match)
  {
    /* If we found a reverse match we must alter the opcode
direction bit.  found_reverse_match holds bits to change
(different for int & float insns).  */

    i.tm.base_opcode ^= found_reverse_match;

    i.tm.operand_types[0] = t->operand_types[1];
    i.tm.operand_types[1] = t->operand_types[0];
  }

return 1;
2377}

2379static int
2380check_string ()
2381{
int mem_op = (i.types[0] & AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000)) ? 0 : 1;
if ((i.tm.operand_types[mem_op] & EsSeg0x40000000) != 0)
  {
    if (i.seg[0] != NULL((void*)0) && i.seg[0] != &es)
{
 as_bad (_("`%s' operand %d must use `%%es' segment")("`%s' operand %d must use `%%es' segment"),
  i.tm.name,
  mem_op + 1);
 return 0;
}
    /* There's only ever one segment override allowed per instruction.
This instruction possibly has a legal segment override on the
second operand, so copy the segment to where non-string
instructions store it, allowing common code.  */
    i.seg[0] = i.seg[1];
  }
else if ((i.tm.operand_types[mem_op + 1] & EsSeg0x40000000) != 0)
  {
    if (i.seg[1] != NULL((void*)0) && i.seg[1] != &es)
{
 as_bad (_("`%s' operand %d must use `%%es' segment")("`%s' operand %d must use `%%es' segment"),
  i.tm.name,
  mem_op + 2);
 return 0;
}
  }
return 1;
2409}

2411static int
2412process_suffix (void)
2413{
/* If matched instruction specifies an explicit instruction mnemonic
   suffix, use it.  */
if (i.tm.opcode_modifier & (Size160x2000 | Size320x4000 | Size640x8000))
  {
    if (i.tm.opcode_modifier & Size160x2000)
i.suffix = WORD_MNEM_SUFFIX'w';
    else if (i.tm.opcode_modifier & Size640x8000)
i.suffix = QWORD_MNEM_SUFFIX'q';
    else
i.suffix = LONG_MNEM_SUFFIX'l';
  }
else if (i.reg_operands)
  {
    /* If there's no instruction mnemonic suffix we try to invent one
based on register operands.  */
    if (!i.suffix)
{
 /* We take i.suffix from the last register operand specified,
    Destination register type is more significant than source
    register type.  */
 int op;

 for (op = i.operands; --op >= 0;)
   if ((i.types[op] & Reg(0x1|0x2|0x4|0x8))
&& !(i.tm.operand_types[op] & InOutPortReg0x20000))
     {
i.suffix = ((i.types[op] & Reg80x1) ? BYTE_MNEM_SUFFIX'b' :
	    (i.types[op] & Reg160x2) ? WORD_MNEM_SUFFIX'w' :
	    (i.types[op] & Reg640x8) ? QWORD_MNEM_SUFFIX'q' :
	    LONG_MNEM_SUFFIX'l');
break;
     }
}
    else if (i.suffix == BYTE_MNEM_SUFFIX'b')
{
 if (!check_byte_reg ())
   return 0;
}
    else if (i.suffix == LONG_MNEM_SUFFIX'l')
{
 if (!check_long_reg ())
   return 0;
}
    else if (i.suffix == QWORD_MNEM_SUFFIX'q')
{
 if (!check_qword_reg ())
   return 0;
}
    else if (i.suffix == WORD_MNEM_SUFFIX'w')
{
 if (!check_word_reg ())
   return 0;
}
    else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize0x10000))
/* Do nothing if the instruction is going to ignore the prefix.  */
;
    else
abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 2471, __PRETTY_FUNCTION__);
  }
else if ((i.tm.opcode_modifier & DefaultSize0x20000)
  && !i.suffix
  /* exclude fldenv/frstor/fsave/fstenv */
  && (i.tm.opcode_modifier & No_sSuf0x200000))
  {
    i.suffix = stackop_size;
  }
else if (intel_syntax
  && !i.suffix
  && ((i.tm.operand_types[0] & JumpAbsolute0x8000000)
   || (i.tm.opcode_modifier & (JumpByte0x100|JumpInterSegment0x200))
   || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
&& i.tm.extension_opcode <= 3)))
  {
    switch (flag_code)
{
case CODE_64BIT:
 if (!(i.tm.opcode_modifier & No_qSuf0x400000))
   {
     i.suffix = QWORD_MNEM_SUFFIX'q';
     break;
   }
case CODE_32BIT:
 if (!(i.tm.opcode_modifier & No_lSuf0x100000))
   i.suffix = LONG_MNEM_SUFFIX'l';
 break;
case CODE_16BIT:
 if (!(i.tm.opcode_modifier & No_wSuf0x80000))
   i.suffix = WORD_MNEM_SUFFIX'w';
 break;
}
  }

if (!i.suffix)
  {
    if (!intel_syntax)
{
 if (i.tm.opcode_modifier & W0x1)
   {
     as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")("no instruction mnemonic suffix given and no register operands; can't size instruction"
));
     return 0;
   }
}
    else
{
 unsigned int suffixes = ~i.tm.opcode_modifier
		  & (No_bSuf0x40000
		     | No_wSuf0x80000
		     | No_lSuf0x100000
		     | No_sSuf0x200000
		     | No_xSuf0x800000
		     | No_qSuf0x400000);

 if ((i.tm.opcode_modifier & W0x1)
     || ((suffixes & (suffixes - 1))
  && !(i.tm.opcode_modifier & (DefaultSize0x20000 | IgnoreSize0x10000))))
   {
     as_bad (_("ambiguous operand size for `%s'")("ambiguous operand size for `%s'"), i.tm.name);
     return 0;
   }
}
  }

/* Change the opcode based on the operand size given by i.suffix;
   We don't need to change things for byte insns.  */

if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX'b')
  {
    /* It's not a byte, select word/dword operation.  */
    if (i.tm.opcode_modifier & W0x1)
{
 if (i.tm.opcode_modifier & ShortForm0x10)
   i.tm.base_opcode |= 8;
 else
   i.tm.base_opcode |= 1;
}

    /* Now select between word & dword operations via the operand
size prefix, except for instructions that will ignore this
prefix anyway.  */
    if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
{
 /* monitor in SSE3 is a very special case. The default size
    of AX is the size of mode. The address size override
    prefix will change the size of AX.  */
 if (i.op->regs[0].reg_type &
     (flag_code == CODE_32BIT ? Reg160x2 : Reg320x4))
   if (!add_prefix (ADDR_PREFIX_OPCODE0x67))
     return 0;
}
    else if (i.suffix != QWORD_MNEM_SUFFIX'q'
      && i.suffix != LONG_DOUBLE_MNEM_SUFFIX'x'
      && !(i.tm.opcode_modifier & (IgnoreSize0x10000 | FloatMF0x20))
      && ((i.suffix == LONG_MNEM_SUFFIX'l') == (flag_code == CODE_16BIT)
   || (flag_code == CODE_64BIT
       && (i.tm.opcode_modifier & JumpByte0x100))))
{
 unsigned int prefix = DATA_PREFIX_OPCODE0x66;

 if (i.tm.opcode_modifier & JumpByte0x100) /* jcxz, loop */
   prefix = ADDR_PREFIX_OPCODE0x67;

 if (!add_prefix (prefix))
   return 0;
}

    /* Set mode64 for an operand.  */
    if (i.suffix == QWORD_MNEM_SUFFIX'q'
 && flag_code == CODE_64BIT
 && (i.tm.opcode_modifier & NoRex640x20000000) == 0)
i.rex |= REX_MODE648;

    /* Size floating point instruction.  */
    if (i.suffix == LONG_MNEM_SUFFIX'l')
if (i.tm.opcode_modifier & FloatMF0x20)
 i.tm.base_opcode ^= 4;
  }

return 1;
2592}

2594static int
2595check_byte_reg (void)
2596{
int op;

for (op = i.operands; --op >= 0;)
  {
    /* If this is an eight bit register, it's OK.  If it's the 16 or
32 bit version of an eight bit register, we will just use the
low portion, and that's OK too.  */
    if (i.types[op] & Reg80x1)
continue;

    /* movzx and movsx should not generate this warning.  */
    if (intel_syntax
 && (i.tm.base_opcode == 0xfb7
     || i.tm.base_opcode == 0xfb6
     || i.tm.base_opcode == 0x63
     || i.tm.base_opcode == 0xfbe
     || i.tm.base_opcode == 0xfbf))
continue;

    if ((i.types[op] & WordReg(0x2|0x4|0x8)) && i.op[op].regs->reg_num < 4)
{
 /* Prohibit these changes in the 64bit mode, since the
    lowering is more complicated.  */
 if (flag_code == CODE_64BIT
     && (i.tm.operand_types[op] & InOutPortReg0x20000) == 0)
   {
     as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"),
      i.op[op].regs->reg_name,
      i.suffix);
     return 0;
   }
2628#if REGISTER_WARNINGS1
 if (!quiet_warnings
     && (i.tm.operand_types[op] & InOutPortReg0x20000) == 0)
   as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix")("using `%%%s' instead of `%%%s' due to `%c' suffix"),
     (i.op[op].regs + (i.types[op] & Reg160x2
		       ? REGNAM_AL1 - REGNAM_AX25
		       : REGNAM_AL1 - REGNAM_EAX41))->reg_name,
     i.op[op].regs->reg_name,
     i.suffix);
2637#endif
 continue;
}
    /* Any other register is bad.  */
    if (i.types[op] & (Reg(0x1|0x2|0x4|0x8) | RegMMX0x10000000 | RegXMM0x20000000
	 | SReg20x1000000 | SReg30x2000000
	 | Control0x80000 | Debug0x100000 | Test0x200000
	 | FloatReg0x400000 | FloatAcc0x800000))
{
 as_bad (_("`%%%s' not allowed with `%s%c'")("`%%%s' not allowed with `%s%c'"),
  i.op[op].regs->reg_name,
  i.tm.name,
  i.suffix);
 return 0;
}
  }
return 1;
2654}

2656static int
2657check_long_reg ()
2658{
int op;

for (op = i.operands; --op >= 0;)
  /* Reject eight bit registers, except where the template requires
     them. (eg. movzb)  */
  if ((i.types[op] & Reg80x1) != 0
&& (i.tm.operand_types[op] & (Reg160x2 | Reg320x4 | Acc0x4000000)) != 0)
    {
as_bad (_("`%%%s' not allowed with `%s%c'")("`%%%s' not allowed with `%s%c'"),
i.op[op].regs->reg_name,
i.tm.name,
i.suffix);
return 0;
    }
/* Warn if the e prefix on a general reg is missing.  */
  else if ((!quiet_warnings || flag_code == CODE_64BIT)
    && (i.types[op] & Reg160x2) != 0
    && (i.tm.operand_types[op] & (Reg320x4 | Acc0x4000000)) != 0)
    {
/* Prohibit these changes in the 64bit mode, since the
  lowering is more complicated.  */
if (flag_code == CODE_64BIT)
 {
   as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"),
    i.op[op].regs->reg_name,
    i.suffix);
   return 0;
 }
2687#if REGISTER_WARNINGS1
else
 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix")("using `%%%s' instead of `%%%s' due to `%c' suffix"),
   (i.op[op].regs + REGNAM_EAX41 - REGNAM_AX25)->reg_name,
   i.op[op].regs->reg_name,
   i.suffix);
2693#endif
    }
/* Warn if the r prefix on a general reg is missing.  */
  else if ((i.types[op] & Reg640x8) != 0
    && (i.tm.operand_types[op] & (Reg320x4 | Acc0x4000000)) != 0)
    {
as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"),
i.op[op].regs->reg_name,
i.suffix);
return 0;
    }
return 1;
2705}

2707static int
2708check_qword_reg ()
2709{
int op;

for (op = i.operands; --op >= 0; )
  /* Reject eight bit registers, except where the template requires
     them. (eg. movzb)  */
  if ((i.types[op] & Reg80x1) != 0
&& (i.tm.operand_types[op] & (Reg160x2 | Reg320x4 | Acc0x4000000)) != 0)
    {
as_bad (_("`%%%s' not allowed with `%s%c'")("`%%%s' not allowed with `%s%c'"),
i.op[op].regs->reg_name,
i.tm.name,
i.suffix);
return 0;
    }
/* Warn if the e prefix on a general reg is missing.  */
  else if (((i.types[op] & Reg160x2) != 0
     || (i.types[op] & Reg320x4) != 0)
    && (i.tm.operand_types[op] & (Reg320x4 | Acc0x4000000)) != 0)
    {
/* Prohibit these changes in the 64bit mode, since the
  lowering is more complicated.  */
as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"),
i.op[op].regs->reg_name,
i.suffix);
return 0;
    }
return 1;
2737}

2739static int
2740check_word_reg ()
2741{
int op;
for (op = i.operands; --op >= 0;)
  /* Reject eight bit registers, except where the template requires
     them. (eg. movzb)  */
  if ((i.types[op] & Reg80x1) != 0
&& (i.tm.operand_types[op] & (Reg160x2 | Reg320x4 | Acc0x4000000)) != 0)
    {
as_bad (_("`%%%s' not allowed with `%s%c'")("`%%%s' not allowed with `%s%c'"),
i.op[op].regs->reg_name,
i.tm.name,
i.suffix);
return 0;
    }
/* Warn if the e prefix on a general reg is present.  */
  else if ((!quiet_warnings || flag_code == CODE_64BIT)
    && (i.types[op] & Reg320x4) != 0
    && (i.tm.operand_types[op] & (Reg160x2 | Acc0x4000000)) != 0)
    {
/* Prohibit these changes in the 64bit mode, since the
  lowering is more complicated.  */
if (flag_code == CODE_64BIT)
 {
   as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"),
    i.op[op].regs->reg_name,
    i.suffix);
   return 0;
 }
else
2770#if REGISTER_WARNINGS1
 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix")("using `%%%s' instead of `%%%s' due to `%c' suffix"),
   (i.op[op].regs + REGNAM_AX25 - REGNAM_EAX41)->reg_name,
   i.op[op].regs->reg_name,
   i.suffix);
2775#endif
    }
return 1;
2778}

2780static int
2781finalize_imm ()
2782{
unsigned int overlap0, overlap1, overlap2;

overlap0 = i.types[0] & i.tm.operand_types[0];
if ((overlap0 & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200))
    && overlap0 != Imm80x10 && overlap0 != Imm8S0x20
    && overlap0 != Imm160x40 && overlap0 != Imm32S0x100
    && overlap0 != Imm320x80 && overlap0 != Imm640x200)
  {
    if (i.suffix)
{
 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX'b'
       ? Imm80x10 | Imm8S0x20
       : (i.suffix == WORD_MNEM_SUFFIX'w'
	  ? Imm160x40
	  : (i.suffix == QWORD_MNEM_SUFFIX'q'
	     ? Imm640x200 | Imm32S0x100
	     : Imm320x80)));
}
    else if (overlap0 == (Imm160x40 | Imm32S0x100 | Imm320x80)
      || overlap0 == (Imm160x40 | Imm320x80)
      || overlap0 == (Imm160x40 | Imm32S0x100))
{
 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX3] != 0)
      ? Imm160x40 : Imm32S0x100);
}
    if (overlap0 != Imm80x10 && overlap0 != Imm8S0x20
 && overlap0 != Imm160x40 && overlap0 != Imm32S0x100
 && overlap0 != Imm320x80 && overlap0 != Imm640x200)
{
 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")("no instruction mnemonic suffix given; can't determine immediate size"
));
 return 0;
}
  }
i.types[0] = overlap0;

overlap1 = i.types[1] & i.tm.operand_types[1];
if ((overlap1 & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm32S0x100 | Imm320x80 | Imm640x200))
    && overlap1 != Imm80x10 && overlap1 != Imm8S0x20
    && overlap1 != Imm160x40 && overlap1 != Imm32S0x100
    && overlap1 != Imm320x80 && overlap1 != Imm640x200)
  {
    if (i.suffix)
{
 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX'b'
       ? Imm80x10 | Imm8S0x20
       : (i.suffix == WORD_MNEM_SUFFIX'w'
	  ? Imm160x40
	  : (i.suffix == QWORD_MNEM_SUFFIX'q'
	     ? Imm640x200 | Imm32S0x100
	     : Imm320x80)));
}
    else if (overlap1 == (Imm160x40 | Imm320x80 | Imm32S0x100)
      || overlap1 == (Imm160x40 | Imm320x80)
      || overlap1 == (Imm160x40 | Imm32S0x100))
{
 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX3] != 0)
      ? Imm160x40 : Imm32S0x100);
}
    if (overlap1 != Imm80x10 && overlap1 != Imm8S0x20
 && overlap1 != Imm160x40 && overlap1 != Imm32S0x100
 && overlap1 != Imm320x80 && overlap1 != Imm640x200)
{
 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c")("no instruction mnemonic suffix given; can't determine immediate size %x %c"
),overlap1, i.suffix);
 return 0;
}
  }
i.types[1] = overlap1;

overlap2 = i.types[2] & i.tm.operand_types[2];
assert ((overlap2 & Imm) == 0)((void) (((overlap2 & (0x10|0x20|0x40|0x100|0x80|0x200)) ==
 0) ? 0 : (as_assert ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 2852, __PRETTY_FUNCTION__), 0)));
i.types[2] = overlap2;

return 1;
2856}

2858static int
2859process_operands ()
2860{
/* Default segment register this instruction will use for memory
   accesses.  0 means unknown.  This is only for optimizing out
   unnecessary segment overrides.  */
const seg_entry *default_seg = 0;

/* The imul $imm, %reg instruction is converted into
   imul $imm, %reg, %reg, and the clr %reg instruction
   is converted into xor %reg, %reg.  */
if (i.tm.opcode_modifier & regKludge0x4000000)
  {
    unsigned int first_reg_op = (i.types[0] & Reg(0x1|0x2|0x4|0x8)) ? 0 : 1;
    /* Pretend we saw the extra register operand.  */
    assert (i.op[first_reg_op + 1].regs == 0)((void) ((i.op[first_reg_op + 1].regs == 0) ? 0 : (as_assert (
"/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c", 2873
, __PRETTY_FUNCTION__), 0)));
    i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
    i.types[first_reg_op + 1] = i.types[first_reg_op];
    i.reg_operands = 2;
  }

if (i.tm.opcode_modifier & ShortForm0x10)
  {
    /* The register or float register operand is in operand 0 or 1.  */
    unsigned int op = (i.types[0] & (Reg(0x1|0x2|0x4|0x8) | FloatReg0x400000)) ? 0 : 1;
    /* Register goes in low 3 bits of opcode.  */
    i.tm.base_opcode |= i.op[op].regs->reg_num;
    if ((i.op[op].regs->reg_flags & RegRex0x1) != 0)
i.rex |= REX_EXTZ1;
    if (!quiet_warnings && (i.tm.opcode_modifier & Ugh0x80000000) != 0)
{
 /* Warn about some common errors, but press on regardless.
    The first case can be generated by gcc (<= 2.8.1).  */
 if (i.operands == 2)
   {
     /* Reversed arguments on faddp, fsubp, etc.  */
     as_warn (_("translating to `%s %%%s,%%%s'")("translating to `%s %%%s,%%%s'"), i.tm.name,
       i.op[1].regs->reg_name,
       i.op[0].regs->reg_name);
   }
 else
   {
     /* Extraneous `l' suffix on fp insn.  */
     as_warn (_("translating to `%s %%%s'")("translating to `%s %%%s'"), i.tm.name,
       i.op[0].regs->reg_name);
   }
}
  }
else if (i.tm.opcode_modifier & Modrm0x4)
  {
    /* The opcode is completed (modulo i.tm.extension_opcode which
must be put into the modrm byte).  Now, we make the modrm and
index base bytes based on all the info we've collected.  */

    default_seg = build_modrm_byte ();
  }
else if (i.tm.opcode_modifier & (Seg2ShortForm0x800 | Seg3ShortForm0x1000))
  {
    if (i.tm.base_opcode == POP_SEG_SHORT0x07
 && i.op[0].regs->reg_num == 1)
{
 as_bad (_("you can't `pop %%cs'")("you can't `pop %%cs'"));
 return 0;
}
    i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
    if ((i.op[0].regs->reg_flags & RegRex0x1) != 0)
i.rex |= REX_EXTZ1;
  }
else if ((i.tm.base_opcode & ~(D0x2 | W0x1)) == MOV_AX_DISP320xa0)
  {
    default_seg = &ds;
  }
else if ((i.tm.opcode_modifier & IsString0x2000000) != 0)
  {
    /* For the string instructions that allow a segment override
on one of their operands, the default segment is ds.  */
    default_seg = &ds;
  }

if ((i.tm.base_opcode == 0x8d /* lea */
     || (i.tm.cpu_flags & CpuSVME0x80000))
    && i.seg[0] && !quiet_warnings)
  as_warn (_("segment override on `%s' is ineffectual")("segment override on `%s' is ineffectual"), i.tm.name);

/* If a segment was explicitly specified, and the specified segment
   is not the default, use an opcode prefix to select it.  If we
   never figured out what the default segment is, then default_seg
   will be zero at this point, and the specified segment prefix will
   always be used.  */
if ((i.seg[0]) && (i.seg[0] != default_seg))
  {
    if (!add_prefix (i.seg[0]->seg_prefix))
return 0;
  }
return 1;
2953}

2955static const seg_entry *
2956build_modrm_byte ()
2957{
const seg_entry *default_seg = 0;

/* i.reg_operands MUST be the number of real register operands;
   implicit registers do not count.  */
if (i.reg_operands == 2)
  {
    unsigned int source, dest;
    source = ((i.types[0]
 & (Reg(0x1|0x2|0x4|0x8) | RegMMX0x10000000 | RegXMM0x20000000
    | SReg20x1000000 | SReg30x2000000
    | Control0x80000 | Debug0x100000 | Test0x200000))
? 0 : 1);
    dest = source + 1;

    i.rm.mode = 3;
    /* One of the register operands will be encoded in the i.tm.reg
field, the other in the combined i.tm.mode and i.tm.regmem
fields.  If no form of this instruction supports a memory
destination operand, then we assume the source operand may
sometimes be a memory operand and so we need to store the
destination in the i.rm.reg field.  */
    if ((i.tm.operand_types[dest] & AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000)) == 0)
{
 i.rm.reg = i.op[dest].regs->reg_num;
 i.rm.regmem = i.op[source].regs->reg_num;
 if ((i.op[dest].regs->reg_flags & RegRex0x1) != 0)
   i.rex |= REX_EXTX4;
 if ((i.op[source].regs->reg_flags & RegRex0x1) != 0)
   i.rex |= REX_EXTZ1;
}
    else
{
 i.rm.reg = i.op[source].regs->reg_num;
 i.rm.regmem = i.op[dest].regs->reg_num;
 if ((i.op[dest].regs->reg_flags & RegRex0x1) != 0)
   i.rex |= REX_EXTZ1;
 if ((i.op[source].regs->reg_flags & RegRex0x1) != 0)
   i.rex |= REX_EXTX4;
}
    if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX4 | REX_EXTZ1)))
{
 if (!((i.types[0] | i.types[1]) & Control0x80000))
   abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 3000, __PRETTY_FUNCTION__);
 i.rex &= ~(REX_EXTX4 | REX_EXTZ1);
 add_prefix (LOCK_PREFIX_OPCODE0xf0);
}
  }
else
  {			/* If it's not 2 reg operands...  */
    if (i.mem_operands)
{
 unsigned int fake_zero_displacement = 0;
 unsigned int op = ((i.types[0] & AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000))
	     ? 0
	     : (i.types[1] & AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000)) ? 1 : 2);

 default_seg = &ds;

 if (i.base_reg == 0)
   {
     i.rm.mode = 0;
     if (!i.disp_operands)
fake_zero_displacement = 1;
     if (i.index_reg == 0)
{
  /* Operand is just <disp>  */
  if (flag_code == CODE_64BIT)
    {
      /* 64bit mode overwrites the 32bit absolute
	 addressing by RIP relative addressing and
	 absolute addressing is encoded by one of the
	 redundant SIB forms.  */
      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING4;
      i.sib.base = NO_BASE_REGISTER5;
      i.sib.index = NO_INDEX_REGISTER4;
      i.types[op] = ((i.prefix[ADDR_PREFIX2] == 0) ? Disp32S0x8000 : Disp320x4000);
    }
  else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX2] != 0))
    {
      i.rm.regmem = NO_BASE_REGISTER_166;
      i.types[op] = Disp160x2000;
    }
  else
    {
      i.rm.regmem = NO_BASE_REGISTER5;
      i.types[op] = Disp320x4000;
    }
}
     else /* !i.base_reg && i.index_reg  */
{
  i.sib.index = i.index_reg->reg_num;
  i.sib.base = NO_BASE_REGISTER5;
  i.sib.scale = i.log2_scale_factor;
  i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING4;
  i.types[op] &= ~Disp(0x1000|0x2000|0x4000|0x8000|0x10000);
  if (flag_code != CODE_64BIT)
    i.types[op] |= Disp320x4000;	/* Must be 32 bit */
  else
    i.types[op] |= Disp32S0x8000;
  if ((i.index_reg->reg_flags & RegRex0x1) != 0)
    i.rex |= REX_EXTY2;
}
   }
 /* RIP addressing for 64bit mode.  */
 else if (i.base_reg->reg_type == BaseIndex0x800)
   {
     i.rm.regmem = NO_BASE_REGISTER5;
     i.types[op] &= ~ Disp(0x1000|0x2000|0x4000|0x8000|0x10000);
     i.types[op] |= Disp32S0x8000;
     i.flags[op] = Operand_PCrel1;
     if (! i.disp_operands)
fake_zero_displacement = 1;
   }
 else if (i.base_reg->reg_type & Reg160x2)
   {
     switch (i.base_reg->reg_num)
{
case 3: /* (%bx)  */
  if (i.index_reg == 0)
    i.rm.regmem = 7;
  else /* (%bx,%si) -> 0, or (%bx,%di) -> 1  */
    i.rm.regmem = i.index_reg->reg_num - 6;
  break;
case 5: /* (%bp)  */
  default_seg = &ss;
  if (i.index_reg == 0)
    {
      i.rm.regmem = 6;
      if ((i.types[op] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)) == 0)
	{
	  /* fake (%bp) into 0(%bp)  */
	  i.types[op] |= Disp80x1000;
	  fake_zero_displacement = 1;
	}
    }
  else /* (%bp,%si) -> 2, or (%bp,%di) -> 3  */
    i.rm.regmem = i.index_reg->reg_num - 6 + 2;
  break;
default: /* (%si) -> 4 or (%di) -> 5  */
  i.rm.regmem = i.base_reg->reg_num - 6 + 4;
}
     i.rm.mode = mode_from_disp_size (i.types[op]);
   }
 else /* i.base_reg and 32/64 bit mode  */
   {
     if (flag_code == CODE_64BIT
  && (i.types[op] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)))
i.types[op] = (i.types[op] & Disp80x1000) | (i.prefix[ADDR_PREFIX2] == 0 ? Disp32S0x8000 : Disp320x4000);

     i.rm.regmem = i.base_reg->reg_num;
     if ((i.base_reg->reg_flags & RegRex0x1) != 0)
i.rex |= REX_EXTZ1;
     i.sib.base = i.base_reg->reg_num;
     /* x86-64 ignores REX prefix bit here to avoid decoder
 complications.  */
     if ((i.base_reg->reg_num & 7) == EBP_REG_NUM5)
{
  default_seg = &ss;
  if (i.disp_operands == 0)
    {
      fake_zero_displacement = 1;
      i.types[op] |= Disp80x1000;
    }
}
     else if (i.base_reg->reg_num == ESP_REG_NUM4)
{
  default_seg = &ss;
}
     i.sib.scale = i.log2_scale_factor;
     if (i.index_reg == 0)
{
  /* <disp>(%esp) becomes two byte modrm with no index
     register.  We've already stored the code for esp
     in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
     Any base register besides %esp will not use the
     extra modrm byte.  */
  i.sib.index = NO_INDEX_REGISTER4;
3135#if !SCALE1_WHEN_NO_INDEX1
  /* Another case where we force the second modrm byte.  */
  if (i.log2_scale_factor)
    i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING4;
3139#endif
}
     else
{
  i.sib.index = i.index_reg->reg_num;
  i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING4;
  if ((i.index_reg->reg_flags & RegRex0x1) != 0)
    i.rex |= REX_EXTY2;
}

     if (i.disp_operands
  && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
      || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
i.rm.mode = 0;
     else
i.rm.mode = mode_from_disp_size (i.types[op]);
   }

 if (fake_zero_displacement)
   {
     /* Fakes a zero displacement assuming that i.types[op]
 holds the correct displacement size.  */
     expressionS *exp;

     assert (i.op[op].disps == 0)((void) ((i.op[op].disps == 0) ? 0 : (as_assert ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 3163, __PRETTY_FUNCTION__), 0)));
     exp = &disp_expressions[i.disp_operands++];
     i.op[op].disps = exp;
     exp->X_op = O_constant;
     exp->X_add_number = 0;
     exp->X_add_symbol = (symbolS *) 0;
     exp->X_op_symbol = (symbolS *) 0;
   }
}

    /* Fill in i.rm.reg or i.rm.regmem field with register operand
(if any) based on i.tm.extension_opcode.  Again, we must be
careful to make sure that segment/control/debug/test/MMX
registers are coded into the i.rm.reg field.  */
    if (i.reg_operands)
{
 unsigned int op =
   ((i.types[0]
     & (Reg(0x1|0x2|0x4|0x8) | RegMMX0x10000000 | RegXMM0x20000000
 | SReg20x1000000 | SReg30x2000000
 | Control0x80000 | Debug0x100000 | Test0x200000))
    ? 0
    : ((i.types[1]
 & (Reg(0x1|0x2|0x4|0x8) | RegMMX0x10000000 | RegXMM0x20000000
    | SReg20x1000000 | SReg30x2000000
    | Control0x80000 | Debug0x100000 | Test0x200000))
? 1
: 2));
 /* If there is an extension opcode to put here, the register
    number must be put into the regmem field.  */
 if (i.tm.extension_opcode != None0xffff)
   {
     i.rm.regmem = i.op[op].regs->reg_num;
     if ((i.op[op].regs->reg_flags & RegRex0x1) != 0)
i.rex |= REX_EXTZ1;
   }
 else
   {
     i.rm.reg = i.op[op].regs->reg_num;
     if ((i.op[op].regs->reg_flags & RegRex0x1) != 0)
i.rex |= REX_EXTX4;
   }

 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
    must set it to 3 to indicate this is a register operand
    in the regmem field.  */
 if (!i.mem_operands)
   i.rm.mode = 3;
}

    /* Fill in i.rm.reg field with extension opcode (if any).  */
    if (i.tm.extension_opcode != None0xffff)
i.rm.reg = i.tm.extension_opcode;
  }
return default_seg;
3218}

3220static void
3221output_branch ()
3222{
char *p;
int code16;
int prefix;
relax_substateT subtype;
symbolS *sym;
offsetT off;

code16 = 0;
if (flag_code == CODE_16BIT)
  code16 = CODE161;

prefix = 0;
if (i.prefix[DATA_PREFIX3] != 0)
  {
    prefix = 1;
    i.prefixes -= 1;
    code16 ^= CODE161;
  }
/* Pentium4 branch hints.  */
if (i.prefix[SEG_PREFIX4] == CS_PREFIX_OPCODE0x2e /* not taken */
    || i.prefix[SEG_PREFIX4] == DS_PREFIX_OPCODE0x3e /* taken */)
  {
    prefix++;
    i.prefixes--;
  }
if (i.prefix[REX_PREFIX5] != 0)
  {
    prefix++;
    i.prefixes--;
  }

if (i.prefixes != 0 && !intel_syntax)
  as_warn (_("skipping prefixes on this instruction")("skipping prefixes on this instruction"));

/* It's always a symbol;  End frag & setup for relax.
   Make sure there is enough room in this frag for the largest
   instruction we may generate in md_convert_frag.  This is 2
   bytes for the opcode and room for the prefix and largest
   displacement.  */
frag_grow (prefix + 2 + 4);
/* Prefix and 1 opcode byte go in fr_fix.  */
p = frag_more (prefix + 1);
if (i.prefix[DATA_PREFIX3] != 0)
  *p++ = DATA_PREFIX_OPCODE0x66;
if (i.prefix[SEG_PREFIX4] == CS_PREFIX_OPCODE0x2e
    || i.prefix[SEG_PREFIX4] == DS_PREFIX_OPCODE0x3e)
  *p++ = i.prefix[SEG_PREFIX4];
if (i.prefix[REX_PREFIX5] != 0)
  *p++ = i.prefix[REX_PREFIX5];
*p = i.tm.base_opcode;

if ((unsigned char) *p == JUMP_PC_RELATIVE0xeb)
  subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL)((relax_substateT) (((0) << 2) | (0)));
else if ((cpu_arch_flags & Cpu3860x8) != 0)
  subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL)((relax_substateT) (((1) << 2) | (0)));
else
  subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL)((relax_substateT) (((2) << 2) | (0)));
subtype |= code16;

sym = i.op[0].disps->X_add_symbol;
off = i.op[0].disps->X_add_number;

if (i.op[0].disps->X_op != O_constant
    && i.op[0].disps->X_op != O_symbol)
  {
    /* Handle complex expressions.  */
    sym = make_expr_symbol (i.op[0].disps);
    off = 0;
  }

/* 1 possible extra opcode + 4 byte displacement go in var part.
   Pass reloc in fr_var.  */
frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3296}

3298static void
3299output_jump ()
3300{
char *p;
int size;
fixS *fixP;

if (i.tm.opcode_modifier & JumpByte0x100)
  {
    /* This is a loop or jecxz type instruction.  */
    size = 1;
    if (i.prefix[ADDR_PREFIX2] != 0)
{
 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE)frag_append_1_char (0x67);
 i.prefixes -= 1;
}
    /* Pentium4 branch hints.  */
    if (i.prefix[SEG_PREFIX4] == CS_PREFIX_OPCODE0x2e /* not taken */
 || i.prefix[SEG_PREFIX4] == DS_PREFIX_OPCODE0x3e /* taken */)
{
 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX])frag_append_1_char (i.prefix[4]);
 i.prefixes--;
}
  }
else
  {
    int code16;

    code16 = 0;
    if (flag_code == CODE_16BIT)
code16 = CODE161;

    if (i.prefix[DATA_PREFIX3] != 0)
{
 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE)frag_append_1_char (0x66);
 i.prefixes -= 1;
 code16 ^= CODE161;
}

    size = 4;
    if (code16)
size = 2;
  }

if (i.prefix[REX_PREFIX5] != 0)
  {
    FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX])frag_append_1_char (i.prefix[5]);
    i.prefixes -= 1;
  }

if (i.prefixes != 0 && !intel_syntax)
  as_warn (_("skipping prefixes on this instruction")("skipping prefixes on this instruction"));

p = frag_more (1 + size);
*p++ = i.tm.base_opcode;

fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
      i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));

/* All jumps handled here are signed, but don't use a signed limit
   check for 32 and 16 bit jumps as we want to allow wrap around at
   4G and 64k respectively.  */
if (size == 1)
  fixP->fx_signed = 1;
3362}

3364static void
3365output_interseg_jump ()
3366{
char *p;
int size;
int prefix;
int code16;

code16 = 0;
if (flag_code == CODE_16BIT)
  code16 = CODE161;

prefix = 0;
if (i.prefix[DATA_PREFIX3] != 0)
  {
    prefix = 1;
    i.prefixes -= 1;
    code16 ^= CODE161;
  }
if (i.prefix[REX_PREFIX5] != 0)
  {
    prefix++;
    i.prefixes -= 1;
  }

size = 4;
if (code16)
  size = 2;

if (i.prefixes != 0 && !intel_syntax)
  as_warn (_("skipping prefixes on this instruction")("skipping prefixes on this instruction"));

/* 1 opcode; 2 segment; offset  */
p = frag_more (prefix + 1 + 2 + size);

if (i.prefix[DATA_PREFIX3] != 0)
  *p++ = DATA_PREFIX_OPCODE0x66;

if (i.prefix[REX_PREFIX5] != 0)
  *p++ = i.prefix[REX_PREFIX5];

*p++ = i.tm.base_opcode;
if (i.op[1].imms->X_op == O_constant)
  {
    offsetT n = i.op[1].imms->X_add_number;

    if (size == 2
 && !fits_in_unsigned_word (n)
 && !fits_in_signed_word (n))
{
 as_bad (_("16-bit jump out of range")("16-bit jump out of range"));
 return;
}
    md_number_to_charsnumber_to_chars_littleendian (p, n, size);
  }
else
  fix_new_exp (frag_now, p - frag_now->fr_literal, size,
 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
if (i.op[0].imms->X_op != O_constant)
  as_bad (_("can't handle non absolute segment in `%s'")("can't handle non absolute segment in `%s'"),
   i.tm.name);
md_number_to_charsnumber_to_chars_littleendian (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3426}

3428static void
3429output_insn ()
3430{
fragS *insn_start_frag;
offsetT insn_start_off;

/* Tie dwarf2 debug info to the address at the start of the insn.
   We can't do this after the insn has been output as the current
   frag may have been closed off.  eg. by frag_var.  */
dwarf2_emit_insn (0);

insn_start_frag = frag_now;
insn_start_off = frag_now_fix ();

/* Output jumps.  */
if (i.tm.opcode_modifier & Jump0x40)
  output_branch ();
else if (i.tm.opcode_modifier & (JumpByte0x100 | JumpDword0x80))
  output_jump ();
else if (i.tm.opcode_modifier & JumpInterSegment0x200)
  output_interseg_jump ();
else
  {
    /* Output normal instructions here.  */
    char *p;
    unsigned char *q;
    unsigned int prefix;

    /* All opcodes on i386 have either 1 or 2 bytes.  Merom New
Instructions have 3 bytes.  We may use one more higher byte
to specify a prefix the instruction requires.  */
    if ((i.tm.cpu_flags & (CpuMNI0x200000|CpuAES0x800000|CpuPCLMUL0x1000000)) != 0)
{
 if (i.tm.base_opcode & 0xff000000)
   {
     prefix = (i.tm.base_opcode >> 24) & 0xff;
     goto check_prefix;
   }
}
    else if ((i.tm.base_opcode & ~3) == 0x660f3880) {
      /* INVEPT, INVVPID, and INVPCID are 3 byte instructions with a
         mandatory prefix. */
      prefix = (i.tm.base_opcode >> 24) & 0xff;
      add_prefix (prefix);
    }
    else if ((i.tm.base_opcode & 0xff0000) != 0)
{
 prefix = (i.tm.base_opcode >> 16) & 0xff;
 if ((i.tm.cpu_flags & CpuPadLock0x40000) != 0)
   {
3478check_prefix:
     if (prefix != REPE_PREFIX_OPCODE0xf3
  || i.prefix[LOCKREP_PREFIX1] != REPE_PREFIX_OPCODE0xf3)
add_prefix (prefix);
   }
 else
   add_prefix (prefix);
}

    /* The prefix bytes.  */
    for (q = i.prefix;
  q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
  q++)
{
 if (*q)
   {
     p = frag_more (1);
     md_number_to_charsnumber_to_chars_littleendian (p, (valueT) *q, 1);
   }
}

    /* Now the opcode; be careful about word order here!  */
    if (fits_in_unsigned_byte (i.tm.base_opcode))
{
 FRAG_APPEND_1_CHAR (i.tm.base_opcode)frag_append_1_char (i.tm.base_opcode);
}
    else
{
 if ((i.tm.cpu_flags & (CpuMNI0x200000|CpuAES0x800000|CpuPCLMUL0x1000000)) != 0)
   {
     p = frag_more (3);
     *p++ = (i.tm.base_opcode >> 16) & 0xff;
   }
        else if ((i.tm.base_opcode & ~3) == 0x660f3880)
   {
     p = frag_more (3);
     *p++ = (i.tm.base_opcode >> 16) & 0xff;
   }
 else
   p = frag_more (2);

 /* Put out high byte first: can't use md_number_to_chars!  */
 *p++ = (i.tm.base_opcode >> 8) & 0xff;
 *p = i.tm.base_opcode & 0xff;
}

    /* Now the modrm byte and sib byte (if present).  */
    if (i.tm.opcode_modifier & Modrm0x4)
{
 p = frag_more (1);
 md_number_to_charsnumber_to_chars_littleendian (p,
	      (valueT) (i.rm.regmem << 0
			| i.rm.reg << 3
			| i.rm.mode << 6),
	      1);
 /* If i.rm.regmem == ESP (4)
    && i.rm.mode != (Register mode)
    && not 16 bit
    ==> need second modrm byte.  */
 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING4
     && i.rm.mode != 3
     && !(i.base_reg && (i.base_reg->reg_type & Reg160x2) != 0))
   {
     p = frag_more (1);
     md_number_to_charsnumber_to_chars_littleendian (p,
		  (valueT) (i.sib.base << 0
			    | i.sib.index << 3
			    | i.sib.scale << 6),
		  1);
   }
}

    if (i.disp_operands)
output_disp (insn_start_frag, insn_start_off);

    if (i.imm_operands)
output_imm (insn_start_frag, insn_start_off);
  }

3557#ifdef DEBUG386
if (flag_debug)
  {
    pi ("" /*line*/, &i);
  }
3562#endif /* DEBUG386  */
3563}

3565static void
3566output_disp (insn_start_frag, insn_start_off)
  fragS *insn_start_frag;
  offsetT insn_start_off;
3569{
char *p;
unsigned int n;

for (n = 0; n < i.operands; n++)
  {
    if (i.types[n] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000))
{
 if (i.op[n].disps->X_op == O_constant)
   {
     int size;
     offsetT val;

     size = 4;
     if (i.types[n] & (Disp80x1000 | Disp160x2000 | Disp640x10000))
{
  size = 2;
  if (i.types[n] & Disp80x1000)
    size = 1;
  if (i.types[n] & Disp640x10000)
    size = 8;
}
     val = offset_in_range (i.op[n].disps->X_add_number,
		     size);
     p = frag_more (size);
     md_number_to_charsnumber_to_chars_littleendian (p, val, size);
   }
 else
   {
     enum bfd_reloc_code_real reloc_type;
     int size = 4;
     int sign = 0;
     int pcrel = (i.flags[n] & Operand_PCrel1) != 0;

     /* The PC relative address is computed relative
 to the instruction boundary, so in case immediate
 fields follows, we need to adjust the value.  */
     if (pcrel && i.imm_operands)
{
  int imm_size = 4;
  unsigned int n1;

  for (n1 = 0; n1 < i.operands; n1++)
    if (i.types[n1] & Imm(0x10|0x20|0x40|0x100|0x80|0x200))
      {
	if (i.types[n1] & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm640x200))
	  {
	    imm_size = 2;
	    if (i.types[n1] & (Imm80x10 | Imm8S0x20))
	      imm_size = 1;
	    if (i.types[n1] & Imm640x200)
	      imm_size = 8;
	  }
	break;
      }
  /* We should find the immediate.  */
  if (n1 == i.operands)
    abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 3626, __PRETTY_FUNCTION__);
  i.op[n].disps->X_add_number -= imm_size;
}

     if (i.types[n] & Disp32S0x8000)
sign = 1;

     if (i.types[n] & (Disp160x2000 | Disp640x10000))
{
  size = 2;
  if (i.types[n] & Disp640x10000)
    size = 8;
}

     p = frag_more (size);
     reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
     if (GOT_symbol
  && GOT_symbol == i.op[n].disps->X_add_symbol
  && (((reloc_type == BFD_RELOC_32
	|| reloc_type == BFD_RELOC_X86_64_32S
	|| (reloc_type == BFD_RELOC_64
	    && object_64bit))
       && (i.op[n].disps->X_op == O_symbol
	   || (i.op[n].disps->X_op == O_add
	       && ((symbol_get_value_expression
		    (i.op[n].disps->X_op_symbol)->X_op)
		   == O_subtract))))
      || reloc_type == BFD_RELOC_32_PCREL))
{
  offsetT add;

  if (insn_start_frag == frag_now)
    add = (p - frag_now->fr_literal) - insn_start_off;
  else
    {
      fragS *fr;

      add = insn_start_frag->fr_fix - insn_start_off;
      for (fr = insn_start_frag->fr_next;
	   fr && fr != frag_now; fr = fr->fr_next)
	add += fr->fr_fix;
      add += p - frag_now->fr_literal;
    }

  if (!object_64bit)
    {
      reloc_type = BFD_RELOC_386_GOTPC;
      i.op[n].imms->X_add_number += add;
    }
  else if (reloc_type == BFD_RELOC_64)
    reloc_type = BFD_RELOC_X86_64_GOTPC64;
  else
    /* Don't do the adjustment for x86-64, as there
       the pcrel addressing is relative to the _next_
       insn, and that is taken care of in other code.  */
    reloc_type = BFD_RELOC_X86_64_GOTPC32;
}
     fix_new_exp (frag_now, p - frag_now->fr_literal, size,
	   i.op[n].disps, pcrel, reloc_type);
   }
}
  }
3688}

3690static void
3691output_imm (insn_start_frag, insn_start_off)
  fragS *insn_start_frag;
  offsetT insn_start_off;
3694{
char *p;
unsigned int n;

for (n = 0; n < i.operands; n++)
  {
    if (i.types[n] & Imm(0x10|0x20|0x40|0x100|0x80|0x200))
{
 if (i.op[n].imms->X_op == O_constant)
   {
     int size;
     offsetT val;

     size = 4;
     if (i.types[n] & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm640x200))
{
  size = 2;
  if (i.types[n] & (Imm80x10 | Imm8S0x20))
    size = 1;
  else if (i.types[n] & Imm640x200)
    size = 8;
}
     val = offset_in_range (i.op[n].imms->X_add_number,
		     size);
     p = frag_more (size);
     md_number_to_charsnumber_to_chars_littleendian (p, val, size);
   }
 else
   {
     /* Not absolute_section.
 Need a 32-bit fixup (don't support 8bit
 non-absolute imms).  Try to support other
 sizes ...  */
     enum bfd_reloc_code_real reloc_type;
     int size = 4;
     int sign = 0;

     if ((i.types[n] & (Imm32S0x100))
  && (i.suffix == QWORD_MNEM_SUFFIX'q'
      || (!i.suffix && (i.tm.opcode_modifier & No_lSuf0x100000))))
sign = 1;
     if (i.types[n] & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm640x200))
{
  size = 2;
  if (i.types[n] & (Imm80x10 | Imm8S0x20))
    size = 1;
  if (i.types[n] & Imm640x200)
    size = 8;
}

     p = frag_more (size);
     reloc_type = reloc (size, 0, sign, i.reloc[n]);

     /*   This is tough to explain.  We end up with this one if we
      * have operands that look like
      * "_GLOBAL_OFFSET_TABLE_+[.-.L284]".  The goal here is to
      * obtain the absolute address of the GOT, and it is strongly
      * preferable from a performance point of view to avoid using
      * a runtime relocation for this.  The actual sequence of
      * instructions often look something like:
      *
      *	call	.L66
      * .L66:
      *	popl	%ebx
      *	addl	$_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
      *
      *   The call and pop essentially return the absolute address
      * of the label .L66 and store it in %ebx.  The linker itself
      * will ultimately change the first operand of the addl so
      * that %ebx points to the GOT, but to keep things simple, the
      * .o file must have this operand set so that it generates not
      * the absolute address of .L66, but the absolute address of
      * itself.  This allows the linker itself simply treat a GOTPC
      * relocation as asking for a pcrel offset to the GOT to be
      * added in, and the addend of the relocation is stored in the
      * operand field for the instruction itself.
      *
      *   Our job here is to fix the operand so that it would add
      * the correct offset so that %ebx would point to itself.  The
      * thing that is tricky is that .-.L66 will point to the
      * beginning of the instruction, so we need to further modify
      * the operand so that it will point to itself.  There are
      * other cases where you have something like:
      *
      *	.long	$_GLOBAL_OFFSET_TABLE_+[.-.L66]
      *
      * and here no correction would be required.  Internally in
      * the assembler we treat operands of this form as not being
      * pcrel since the '.' is explicitly mentioned, and I wonder
      * whether it would simplify matters to do it this way.  Who
      * knows.  In earlier versions of the PIC patches, the
      * pcrel_adjust field was used to store the correction, but
      * since the expression is not pcrel, I felt it would be
      * confusing to do it this way.  */

     if ((reloc_type == BFD_RELOC_32
   || reloc_type == BFD_RELOC_X86_64_32S
   || reloc_type == BFD_RELOC_64)
  && GOT_symbol
  && GOT_symbol == i.op[n].imms->X_add_symbol
  && (i.op[n].imms->X_op == O_symbol
      || (i.op[n].imms->X_op == O_add
	  && ((symbol_get_value_expression
	       (i.op[n].imms->X_op_symbol)->X_op)
	      == O_subtract))))
{
  offsetT add;

  if (insn_start_frag == frag_now)
    add = (p - frag_now->fr_literal) - insn_start_off;
  else
    {
      fragS *fr;

      add = insn_start_frag->fr_fix - insn_start_off;
      for (fr = insn_start_frag->fr_next;
	   fr && fr != frag_now; fr = fr->fr_next)
	add += fr->fr_fix;
      add += p - frag_now->fr_literal;
    }

  if (!object_64bit)
    reloc_type = BFD_RELOC_386_GOTPC;
  else if (size == 4)
    reloc_type = BFD_RELOC_X86_64_GOTPC32;
  else if (size == 8)
    reloc_type = BFD_RELOC_X86_64_GOTPC64;
  i.op[n].imms->X_add_number += add;
}
     fix_new_exp (frag_now, p - frag_now->fr_literal, size,
	   i.op[n].imms, 0, reloc_type);
   }
}
  }
3828}
3829
3830/* x86_cons_fix_new is called via the expression parsing code when a
 reloc is needed.  We use this hook to get the correct .got reloc.  */
3832static enum bfd_reloc_code_real got_reloc = NO_RELOCBFD_RELOC_NONE;
3833static int cons_sign = -1;

3835void
3836x86_cons_fix_new (fragS *frag,
   unsigned int off,
   unsigned int len,
   expressionS *exp)
3840{
enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);

got_reloc = NO_RELOCBFD_RELOC_NONE;

3845#ifdef TE_PE
if (exp->X_op == O_secrel)
  {
    exp->X_op = O_symbol;
    r = BFD_RELOC_32_SECREL;
  }
3851#endif

fix_new_exp (frag, off, len, exp, 0, r);
3854}

3856#if (!defined (OBJ_ELF1) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3857# define lex_got(reloc, adjust, types) NULL((void*)0)
3858#else
3859/* Parse operands of the form
 <symbol>@GOTOFF+<nnn>
 and similar .plt or .got references.

 If we find one, set up the correct relocation in RELOC and copy the
 input string, minus the `@GOTOFF' into a malloc'd buffer for
 parsing by the calling routine.  Return this buffer, and if ADJUST
 is non-null set it to the length of the string we removed from the
 input line.  Otherwise return NULL.  */
3868static char *
3869lex_got (enum bfd_reloc_code_real *reloc,
   int *adjust,
   unsigned int *types)
3872{
/* Some of the relocations depend on the size of what field is to
   be relocated.  But in our callers i386_immediate and i386_displacement
   we don't yet know the operand size (this will be set by insn
   matching).  Hence we record the word32 relocation here,
   and adjust the reloc according to the real size in reloc().  */
static const struct {
  const char *str;
  const enum bfd_reloc_code_real rel[2];
  const unsigned int types64;
} gotrel[] = {
  { "PLTOFF",   { 0,                        BFD_RELOC_X86_64_PLTOFF64 }, Imm640x200 },
  { "PLT",      { BFD_RELOC_386_PLT32,      BFD_RELOC_X86_64_PLT32    }, Imm320x80|Imm32S0x100|Disp320x4000 },
  { "GOTPLT",   { 0,                        BFD_RELOC_X86_64_GOTPLT64 }, Imm640x200|Disp640x10000 },
  { "GOTOFF",   { BFD_RELOC_386_GOTOFF,     BFD_RELOC_X86_64_GOTOFF64 }, Imm640x200|Disp640x10000 },
  { "GOTPCREL", { 0,                        BFD_RELOC_X86_64_GOTPCREL }, Imm320x80|Imm32S0x100|Disp320x4000 },
  { "TLSGD",    { BFD_RELOC_386_TLS_GD,     BFD_RELOC_X86_64_TLSGD    }, Imm320x80|Imm32S0x100|Disp320x4000 },
  { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,    0                         }, 0 },
  { "TLSLD",    { 0,                        BFD_RELOC_X86_64_TLSLD    }, Imm320x80|Imm32S0x100|Disp320x4000 },
  { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,  BFD_RELOC_X86_64_GOTTPOFF }, Imm320x80|Imm32S0x100|Disp320x4000 },
  { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,  BFD_RELOC_X86_64_TPOFF32  }, Imm320x80|Imm32S0x100|Imm640x200|Disp320x4000|Disp640x10000 },
  { "NTPOFF",   { BFD_RELOC_386_TLS_LE,     0                         }, 0 },
  { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm320x80|Imm32S0x100|Imm640x200|Disp320x4000|Disp640x10000 },
  { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,  0                         }, 0 },
  { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,     0                         }, 0 },
  { "GOT",      { BFD_RELOC_386_GOT32,      BFD_RELOC_X86_64_GOT32    }, Imm320x80|Imm32S0x100|Disp320x4000|Imm640x200 },
  { "TLSDESC",  { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm320x80|Imm32S0x100|Disp320x4000 },
  { "TLSCALL",  { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm320x80|Imm32S0x100|Disp320x4000 }
};
char *cp;
unsigned int j;

if (!IS_ELF1)
  return NULL((void*)0);

for (cp = input_line_pointer; *cp != '@'; cp++)
  if (is_end_of_line[(unsigned char) *cp])
    return NULL((void*)0);

for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
  {
    int len;

    len = strlen (gotrel[j].str);
    if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
{
 if (gotrel[j].rel[object_64bit] != 0)
   {
     int first, second;
     char *tmpbuf, *past_reloc;

     *reloc = gotrel[j].rel[object_64bit];
     if (adjust)
*adjust = len;

     if (types)
{
  if (flag_code != CODE_64BIT)
    *types = Imm320x80|Disp320x4000;
  else
    *types = gotrel[j].types64;
}

     if (GOT_symbol == NULL((void*)0))
GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_");

     /* Replace the relocation token with ' ', so that
 errors like foo@GOTOFF1 will be detected.  */

     /* The length of the first part of our input line.  */
     first = cp - input_line_pointer;

     /* The second part goes from after the reloc token until
 (and including) an end_of_line char.  Don't use strlen
 here as the end_of_line char may not be a NUL.  */
     past_reloc = cp + 1 + len;
     for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
;
     second = cp - past_reloc;

     /* Allocate and copy string.  The trailing NUL shouldn't
 be necessary, but be safe.  */
     tmpbuf = xmalloc (first + second + 2);
     memcpy (tmpbuf, input_line_pointer, first);
     tmpbuf[first] = ' ';
     memcpy (tmpbuf + first + 1, past_reloc, second);
     tmpbuf[first + second + 1] = '\0';
     return tmpbuf;
   }

 as_bad (_("@%s reloc is not supported with %d-bit output format")("@%s reloc is not supported with %d-bit output format"),
  gotrel[j].str, 1 << (5 + object_64bit));
 return NULL((void*)0);
}
  }

/* Might be a symbol version string.  Don't as_bad here.  */
return NULL((void*)0);
3970}

3972void
3973x86_cons (exp, size)
   expressionS *exp;
   int size;
3976{
if (size == 4 || (object_64bit && size == 8))
  {
    /* Handle @GOTOFF and the like in an expression.  */
    char *save;
    char *gotfree_input_line;
    int adjust;

    save = input_line_pointer;
    gotfree_input_line = lex_got (&got_reloc, &adjust, NULL((void*)0));
    if (gotfree_input_line)
input_line_pointer = gotfree_input_line;

    expression (exp)expr (0, exp, expr_normal);

    if (gotfree_input_line)
{
 /* expression () has merrily parsed up to the end of line,
    or a comma - in the wrong buffer.  Transfer how far
    input_line_pointer has moved to the right buffer.  */
 input_line_pointer = (save
		+ (input_line_pointer - gotfree_input_line)
		+ adjust);
 free (gotfree_input_line);
}
  }
else
  expression (exp)expr (0, exp, expr_normal);
4004}
4005#endif

4007static void signed_cons (int size)
4008{
if (flag_code == CODE_64BIT)
  cons_sign = 1;
cons (size);
cons_sign = -1;
4013}

4015#ifdef TE_PE
4016static void
4017pe_directive_secrel (dummy)
   int dummy ATTRIBUTE_UNUSED__attribute__ ((__unused__));
4019{
expressionS exp;

do
  {
    expression (&exp)expr (0, &exp, expr_normal);
    if (exp.X_op == O_symbol)
exp.X_op = O_secrel;

    emit_expr (&exp, 4);
  }
while (*input_line_pointer++ == ',');

input_line_pointer--;
demand_empty_rest_of_line ();
4034}
4035#endif

4037static int i386_immediate PARAMS ((char *))(char *);

4039static int
4040i386_immediate (imm_start)
   char *imm_start;
4042{
char *save_input_line_pointer;
char *gotfree_input_line;
segT exp_seg = 0;
expressionS *exp;
unsigned int types = ~0U;

if (i.imm_operands == MAX_IMMEDIATE_OPERANDS2)
  {
    as_bad (_("only 1 or 2 immediate operands are allowed")("only 1 or 2 immediate operands are allowed"));
    return 0;
  }

exp = &im_expressions[i.imm_operands++];
i.op[this_operand].imms = exp;

if (is_space_char (*imm_start)((*imm_start) == ' '))
  ++imm_start;

save_input_line_pointer = input_line_pointer;
input_line_pointer = imm_start;

gotfree_input_line = lex_got (&i.reloc[this_operand], NULL((void*)0), &types);
if (gotfree_input_line)
  input_line_pointer = gotfree_input_line;

exp_seg = expression (exp)expr (0, exp, expr_normal);

SKIP_WHITESPACE ()((*input_line_pointer == ' ') ? ++input_line_pointer : 0);
if (*input_line_pointer)
  as_bad (_("junk `%s' after expression")("junk `%s' after expression"), input_line_pointer);

input_line_pointer = save_input_line_pointer;
if (gotfree_input_line)
  free (gotfree_input_line);

if (exp->X_op == O_absent || exp->X_op == O_big)
  {
    /* Missing or bad expr becomes absolute 0.  */
    as_bad (_("missing or invalid immediate expression `%s' taken as 0")("missing or invalid immediate expression `%s' taken as 0"),
     imm_start);
    exp->X_op = O_constant;
    exp->X_add_number = 0;
    exp->X_add_symbol = (symbolS *) 0;
    exp->X_op_symbol = (symbolS *) 0;
  }
else if (exp->X_op == O_constant)
  {
    /* Size it properly later.  */
    i.types[this_operand] |= Imm640x200;
    /* If BFD64, sign extend val.  */
    if (!use_rela_relocations)
if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
  }
4097#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
else if (OUTPUT_FLAVORbfd_target_elf_flavour == bfd_target_aout_flavour
  && exp_seg != absolute_section((asection *) &bfd_abs_section)
  && exp_seg != text_section
  && exp_seg != data_section
  && exp_seg != bss_section
  && exp_seg != undefined_section((asection *) &bfd_und_section)
  && !bfd_is_com_section (exp_seg)(((exp_seg)->flags & 0x1000) != 0))
  {
    as_bad (_("unimplemented segment %s in operand")("unimplemented segment %s in operand"), exp_seg->name);
    return 0;
  }
4109#endif
else
  {
    /* This is an address.  The size of the address will be
determined later, depending on destination register,
suffix, or the default for the section.  */
    i.types[this_operand] |= Imm80x10 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200;
    i.types[this_operand] &= types;
  }

return 1;
4120}

4122static char *i386_scale PARAMS ((char *))(char *);

4124static char *
4125i386_scale (scale)
   char *scale;
4127{
offsetT val;
char *save = input_line_pointer;

input_line_pointer = scale;
val = get_absolute_expression ();

switch (val)
  {
  case 1:
    i.log2_scale_factor = 0;
    break;
  case 2:
    i.log2_scale_factor = 1;
    break;
  case 4:
    i.log2_scale_factor = 2;
    break;
  case 8:
    i.log2_scale_factor = 3;
    break;
  default:
    {
char sep = *input_line_pointer;

*input_line_pointer = '\0';
as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'")("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
scale);
*input_line_pointer = sep;
input_line_pointer = save;
return NULL((void*)0);
    }
  }
if (i.log2_scale_factor != 0 && i.index_reg == 0)
  {
    as_warn (_("scale factor of %d without an index register")("scale factor of %d without an index register"),
      1 << i.log2_scale_factor);
4164#if SCALE1_WHEN_NO_INDEX1
    i.log2_scale_factor = 0;
4166#endif
  }
scale = input_line_pointer;
input_line_pointer = save;
return scale;
4171}

4173static int i386_displacement PARAMS ((char *, char *))(char *, char *);

4175static int
4176i386_displacement (disp_start, disp_end)
   char *disp_start;
   char *disp_end;
4179{
expressionS *exp;
segT exp_seg = 0;
char *save_input_line_pointer;
char *gotfree_input_line;
int bigdisp, override;
unsigned int types = Disp(0x1000|0x2000|0x4000|0x8000|0x10000);

if ((i.types[this_operand] & JumpAbsolute0x8000000)
    || !(current_templates->start->opcode_modifier & (Jump0x40 | JumpDword0x80)))
  {
    bigdisp = Disp320x4000;
    override = (i.prefix[ADDR_PREFIX2] != 0);
  }
else
  {
    /* For PC-relative branches, the width of the displacement
is dependent upon data size, not address size.  */
    bigdisp = 0;
    override = (i.prefix[DATA_PREFIX3] != 0);
  }
if (flag_code == CODE_64BIT)
  {
    if (!bigdisp)
bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX'w')
  ? Disp160x2000
  : Disp32S0x8000 | Disp320x4000;
    else if (!override)
bigdisp = Disp640x10000 | Disp32S0x8000 | Disp320x4000;
  }
else
  {
    if (!bigdisp)
{
 if (!override)
   override = (i.suffix == (flag_code != CODE_16BIT
		     ? WORD_MNEM_SUFFIX'w'
		     : LONG_MNEM_SUFFIX'l'));
 bigdisp = Disp320x4000;
}
    if ((flag_code == CODE_16BIT) ^ override)
bigdisp = Disp160x2000;
  }
i.types[this_operand] |= bigdisp;

exp = &disp_expressions[i.disp_operands];
i.op[this_operand].disps = exp;
i.disp_operands++;
save_input_line_pointer = input_line_pointer;
input_line_pointer = disp_start;
END_STRING_AND_SAVE (disp_end)do { *save_stack_p++ = *(disp_end); *(disp_end) = '\0'; } while
 (0);

4231#ifndef GCC_ASM_O_HACK0
4232#define GCC_ASM_O_HACK0 0
4233#endif
4234#if GCC_ASM_O_HACK0
END_STRING_AND_SAVE (disp_end + 1)do { *save_stack_p++ = *(disp_end + 1); *(disp_end + 1) = '\0'
; } while (0);
if ((i.types[this_operand] & BaseIndex0x800) != 0
    && displacement_string_end[-1] == '+')
  {
    /* This hack is to avoid a warning when using the "o"
constraint within gcc asm statements.
For instance:

#define _set_tssldt_desc(n,addr,limit,type) \
__asm__ __volatile__ ( \
"movw %w2,%0\n\t" \
"movw %w1,2+%0\n\t" \
"rorl $16,%1\n\t" \
"movb %b1,4+%0\n\t" \
"movb %4,5+%0\n\t" \
"movb $0,6+%0\n\t" \
"movb %h1,7+%0\n\t" \
"rorl $16,%1" \
: "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))

This works great except that the output assembler ends
up looking a bit weird if it turns out that there is
no offset.  You end up producing code that looks like:

#APP
movw $235,(%eax)
movw %dx,2+(%eax)
rorl $16,%edx
movb %dl,4+(%eax)
movb $137,5+(%eax)
movb $0,6+(%eax)
movb %dh,7+(%eax)
rorl $16,%edx
#NO_APP

So here we provide the missing zero.  */

    *displacement_string_end = '0';
  }
4274#endif
gotfree_input_line = lex_got (&i.reloc[this_operand], NULL((void*)0), &types);
if (gotfree_input_line)
  input_line_pointer = gotfree_input_line;

exp_seg = expression (exp)expr (0, exp, expr_normal);

SKIP_WHITESPACE ()((*input_line_pointer == ' ') ? ++input_line_pointer : 0);
if (*input_line_pointer)
  as_bad (_("junk `%s' after expression")("junk `%s' after expression"), input_line_pointer);
4284#if GCC_ASM_O_HACK0
RESTORE_END_STRING (disp_end + 1)do { *(disp_end + 1) = *--save_stack_p; } while (0);
4286#endif
RESTORE_END_STRING (disp_end)do { *(disp_end) = *--save_stack_p; } while (0);
input_line_pointer = save_input_line_pointer;
if (gotfree_input_line)
  free (gotfree_input_line);

/* We do this to make sure that the section symbol is in
   the symbol table.  We will ultimately change the relocation
   to be relative to the beginning of the section.  */
if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
    || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
    || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
  {
    if (exp->X_op != O_symbol)
{
 as_bad (_("bad expression used with @%s")("bad expression used with @%s"),
  (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
   ? "GOTPCREL"
   : "GOTOFF"));
 return 0;
}

    if (S_IS_LOCAL (exp->X_add_symbol)
 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section((asection *) &bfd_und_section))
section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
    exp->X_op = O_subtract;
    exp->X_op_symbol = GOT_symbol;
    if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
i.reloc[this_operand] = BFD_RELOC_32_PCREL;
    else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
i.reloc[this_operand] = BFD_RELOC_64;
    else
i.reloc[this_operand] = BFD_RELOC_32;
  }

if (exp->X_op == O_absent || exp->X_op == O_big)
  {
    /* Missing or bad expr becomes absolute 0.  */
    as_bad (_("missing or invalid displacement expression `%s' taken as 0")("missing or invalid displacement expression `%s' taken as 0"
),
     disp_start);
    exp->X_op = O_constant;
    exp->X_add_number = 0;
    exp->X_add_symbol = (symbolS *) 0;
    exp->X_op_symbol = (symbolS *) 0;
  }

4332#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
if (exp->X_op != O_constant
    && OUTPUT_FLAVORbfd_target_elf_flavour == bfd_target_aout_flavour
    && exp_seg != absolute_section((asection *) &bfd_abs_section)
    && exp_seg != text_section
    && exp_seg != data_section
    && exp_seg != bss_section
    && exp_seg != undefined_section((asection *) &bfd_und_section)
    && !bfd_is_com_section (exp_seg)(((exp_seg)->flags & 0x1000) != 0))
  {
    as_bad (_("unimplemented segment %s in operand")("unimplemented segment %s in operand"), exp_seg->name);
    return 0;
  }
4345#endif

if (!(i.types[this_operand] & ~Disp(0x1000|0x2000|0x4000|0x8000|0x10000)))
  i.types[this_operand] &= types;

return 1;
4351}

4353static int i386_index_check PARAMS ((const char *))(const char *);

4355/* Make sure the memory operand we've been dealt is valid.
 Return 1 on success, 0 on a failure.  */

4358static int
4359i386_index_check (operand_string)
   const char *operand_string;
4361{
int ok;
4363#if INFER_ADDR_PREFIX1
int fudged = 0;

tryprefix:
4367#endif
ok = 1;
if ((current_templates->start->cpu_flags & CpuSVME0x80000)
    && current_templates->end[-1].operand_types[0] == AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000))
  {
    /* Memory operands of SVME insns are special in that they only allow
rAX as their memory address and ignore any segment override.  */
    unsigned RegXX;

    /* SKINIT is even more restrictive: it always requires EAX.  */
    if (strcmp (current_templates->start->name, "skinit") == 0)
RegXX = Reg320x4;
    else if (flag_code == CODE_64BIT)
RegXX = i.prefix[ADDR_PREFIX2] == 0 ? Reg640x8 : Reg320x4;
    else
RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX2] != 0)
? Reg160x2
: Reg320x4;
    if (!i.base_reg
 || !(i.base_reg->reg_type & Acc0x4000000)
 || !(i.base_reg->reg_type & RegXX)
 || i.index_reg
 || (i.types[0] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)))
ok = 0;
  }
else if (flag_code == CODE_64BIT)
   {
     unsigned RegXX = (i.prefix[ADDR_PREFIX2] == 0 ? Reg640x8 : Reg320x4);

     if ((i.base_reg
   && ((i.base_reg->reg_type & RegXX) == 0)
   && (i.base_reg->reg_type != BaseIndex0x800
|| i.index_reg))
  || (i.index_reg
      && ((i.index_reg->reg_type & (RegXX | BaseIndex0x800))
   != (RegXX | BaseIndex0x800))))
ok = 0;
  }
else
  {
    if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX2] != 0))
{
 /* 16bit checks.  */
 if ((i.base_reg
      && ((i.base_reg->reg_type & (Reg160x2 | BaseIndex0x800 | RegRex0x1))
   != (Reg160x2 | BaseIndex0x800)))
     || (i.index_reg
  && (((i.index_reg->reg_type & (Reg160x2 | BaseIndex0x800))
       != (Reg160x2 | BaseIndex0x800))
      || !(i.base_reg
	   && i.base_reg->reg_num < 6
	   && i.index_reg->reg_num >= 6
	   && i.log2_scale_factor == 0))))
   ok = 0;
}
    else
{
 /* 32bit checks.  */
 if ((i.base_reg
      && (i.base_reg->reg_type & (Reg320x4 | RegRex0x1)) != Reg320x4)
     || (i.index_reg
  && ((i.index_reg->reg_type & (Reg320x4 | BaseIndex0x800 | RegRex0x1))
      != (Reg320x4 | BaseIndex0x800))))
   ok = 0;
}
  }
if (!ok)
  {
4435#if INFER_ADDR_PREFIX1
    if (i.prefix[ADDR_PREFIX2] == 0)
{
 i.prefix[ADDR_PREFIX2] = ADDR_PREFIX_OPCODE0x67;
 i.prefixes += 1;
 /* Change the size of any displacement too.  At most one of
    Disp16 or Disp32 is set.
    FIXME.  There doesn't seem to be any real need for separate
    Disp16 and Disp32 flags.  The same goes for Imm16 and Imm32.
    Removing them would probably clean up the code quite a lot.  */
 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp160x2000 | Disp320x4000)))
    i.types[this_operand] ^= (Disp160x2000 | Disp320x4000);
 fudged = 1;
 goto tryprefix;
}
    if (fudged)
as_bad (_("`%s' is not a valid base/index expression")("`%s' is not a valid base/index expression"),
operand_string);
    else
4454#endif
as_bad (_("`%s' is not a valid %s bit base/index expression")("`%s' is not a valid %s bit base/index expression"),
operand_string,
flag_code_names[flag_code]);
  }
return ok;
4460}

4462/* Parse OPERAND_STRING into the i386_insn structure I.  Returns non-zero
 on error.  */

4465static int
4466i386_operand (operand_string)
   char *operand_string;
4468{
const reg_entry *r;
char *end_op;
1
'end_op' declared without an initial value→
char *op_string = operand_string;

if (is_space_char (*op_string)((*op_string) == ' '))
2
←
Assuming the condition is false→
3
←
Taking false branch→
  ++op_string;

/* We check for an absolute prefix (differentiating,
   for example, 'jmp pc_relative_label' from 'jmp *absolute_label'.  */
if (*op_string == ABSOLUTE_PREFIX'*')
4
←
Assuming the condition is false→
5
←
Taking false branch→
  {
    ++op_string;
    if (is_space_char (*op_string)((*op_string) == ' '))
++op_string;
    i.types[this_operand] |= JumpAbsolute0x8000000;
  }

/* Check if operand is a register.  */
if ((r = parse_register (op_string, &end_op)) != NULL((void*)0))
6
←
Calling 'parse_register'→
14
←
Returning from 'parse_register'→
15
←
Taking false branch→
  {
    /* Check for a segment override by searching for ':' after a
segment register.  */
    op_string = end_op;
    if (is_space_char (*op_string)((*op_string) == ' '))
++op_string;
    if (*op_string == ':' && (r->reg_type & (SReg20x1000000 | SReg30x2000000)))
{
 switch (r->reg_num)
   {
   case 0:
     i.seg[i.mem_operands] = &es;
     break;
   case 1:
     i.seg[i.mem_operands] = &cs;
     break;
   case 2:
     i.seg[i.mem_operands] = &ss;
     break;
   case 3:
     i.seg[i.mem_operands] = &ds;
     break;
   case 4:
     i.seg[i.mem_operands] = &fs;
     break;
   case 5:
     i.seg[i.mem_operands] = &gs;
     break;
   }

 /* Skip the ':' and whitespace.  */
 ++op_string;
 if (is_space_char (*op_string)((*op_string) == ' '))
   ++op_string;

 if (!is_digit_char (*op_string)(digit_chars[(unsigned char) *op_string])
     && !is_identifier_char (*op_string)(identifier_chars[(unsigned char) *op_string])
     && *op_string != '('
     && *op_string != ABSOLUTE_PREFIX'*')
   {
     as_bad (_("bad memory operand `%s'")("bad memory operand `%s'"), op_string);
     return 0;
   }
 /* Handle case of %es:*foo.  */
 if (*op_string == ABSOLUTE_PREFIX'*')
   {
     ++op_string;
     if (is_space_char (*op_string)((*op_string) == ' '))
++op_string;
     i.types[this_operand] |= JumpAbsolute0x8000000;
   }
 goto do_memory_reference;
}
    if (*op_string)
{
 as_bad (_("junk `%s' after register")("junk `%s' after register"), op_string);
 return 0;
}
    i.types[this_operand] |= r->reg_type & ~BaseIndex0x800;
    i.op[this_operand].regs = r;
    i.reg_operands++;
  }
else if (*op_string == REGISTER_PREFIX'%')
16
←
Assuming the condition is false→
17
←
Taking false branch→
  {
    as_bad (_("bad register name `%s'")("bad register name `%s'"), op_string);
    return 0;
  }
else if (*op_string == IMMEDIATE_PREFIX'$')
18
←
Assuming the condition is false→
19
←
Taking false branch→
  {
    ++op_string;
    if (i.types[this_operand] & JumpAbsolute0x8000000)
{
 as_bad (_("immediate operand illegal with absolute jump")("immediate operand illegal with absolute jump"));
 return 0;
}
    if (!i386_immediate (op_string))
return 0;
  }
else if (is_digit_char (*op_string)(digit_chars[(unsigned char) *op_string])
20
←
Assuming the condition is true→
  || is_identifier_char (*op_string)(identifier_chars[(unsigned char) *op_string])
  || *op_string == '(')
  {
    /* This is a memory reference of some sort.  */
    char *base_string;

    /* Start and end of displacement string expression (if found).  */
    char *displacement_string_start;
    char *displacement_string_end;

  do_memory_reference:
    if ((i.mem_operands == 1
21
←
Assuming field 'mem_operands' is not equal to 1→
23
←
Taking false branch→
  && (current_templates->start->opcode_modifier & IsString0x2000000) == 0)
 || i.mem_operands == 2)
22
←
Assuming field 'mem_operands' is not equal to 2→
{
 as_bad (_("too many memory references for `%s'")("too many memory references for `%s'"),
  current_templates->start->name);
 return 0;
}

    /* Check for base index form.  We detect the base index form by
looking for an ')' at the end of the operand, searching
for the '(' matching it, and finding a REGISTER_PREFIX or ','
after the '('.  */
    base_string = op_string + strlen (op_string);

    --base_string;
    if (is_space_char (*base_string)((*base_string) == ' '))
24
←
Assuming the condition is false→
25
←
Taking false branch→
--base_string;

    /* If we only have a displacement, set-up for it to be parsed later.  */
    displacement_string_start = op_string;
    displacement_string_end = base_string + 1;

    if (*base_string == ')')
26
←
Assuming the condition is true→
27
←
Taking true branch→
{
 char *temp_string;
 unsigned int parens_balanced = 1;
 /* We've already checked that the number of left & right ()'s are
    equal, so this loop will not be infinite.  */
 do
32
←
Loop condition is false.  Exiting loop→
   {
     base_string--;
     if (*base_string == ')')
28
←
Assuming the condition is false→
29
←
Taking false branch→
parens_balanced++;
     if (*base_string == '(')
30
←
Assuming the condition is true→
31
←
Taking true branch→
parens_balanced--;
   }
 while (parens_balanced);

 temp_string = base_string;

 /* Skip past '(' and whitespace.  */
 ++base_string;
 if (is_space_char (*base_string)((*base_string) == ' '))
33
←
Assuming the condition is false→
34
←
Taking false branch→
   ++base_string;

 if (*base_string == ','
35
←
Assuming the condition is true→
     || ((i.base_reg = parse_register (base_string, &end_op)) != NULL((void*)0)))
   {
     displacement_string_end = temp_string;

     i.types[this_operand] |= BaseIndex0x800;

     if (i.base_reg)
36
←
Assuming field 'base_reg' is non-null→
37
←
Taking true branch→
{
  base_string = end_op;
38
←
Assigned value is garbage or undefined
  if (is_space_char (*base_string)((*base_string) == ' '))
    ++base_string;
}

     /* There may be an index reg or scale factor here.  */
     if (*base_string == ',')
{
  ++base_string;
  if (is_space_char (*base_string)((*base_string) == ' '))
    ++base_string;

  if ((i.index_reg = parse_register (base_string, &end_op)) != NULL((void*)0))
    {
      base_string = end_op;
      if (is_space_char (*base_string)((*base_string) == ' '))
	++base_string;
      if (*base_string == ',')
	{
	  ++base_string;
	  if (is_space_char (*base_string)((*base_string) == ' '))
	    ++base_string;
	}
      else if (*base_string != ')')
	{
	  as_bad (_("expecting `,' or `)' after index register in `%s'")("expecting `,' or `)' after index register in `%s'"),
		  operand_string);
	  return 0;
	}
    }
  else if (*base_string == REGISTER_PREFIX'%')
    {
      as_bad (_("bad register name `%s'")("bad register name `%s'"), base_string);
      return 0;
    }

  /* Check for scale factor.  */
  if (*base_string != ')')
    {
      char *end_scale = i386_scale (base_string);

      if (!end_scale)
	return 0;

      base_string = end_scale;
      if (is_space_char (*base_string)((*base_string) == ' '))
	++base_string;
      if (*base_string != ')')
	{
	  as_bad (_("expecting `)' after scale factor in `%s'")("expecting `)' after scale factor in `%s'"),
		  operand_string);
	  return 0;
	}
    }
  else if (!i.index_reg)
    {
      as_bad (_("expecting index register or scale factor after `,'; got '%c'")("expecting index register or scale factor after `,'; got '%c'"
),
	      *base_string);
      return 0;
    }
}
     else if (*base_string != ')')
{
  as_bad (_("expecting `,' or `)' after base register in `%s'")("expecting `,' or `)' after base register in `%s'"),
	  operand_string);
  return 0;
}
   }
 else if (*base_string == REGISTER_PREFIX'%')
   {
     as_bad (_("bad register name `%s'")("bad register name `%s'"), base_string);
     return 0;
   }
}

    /* If there's an expression beginning the operand, parse it,
assuming displacement_string_start and
displacement_string_end are meaningful.  */
    if (displacement_string_start != displacement_string_end)
{
 if (!i386_displacement (displacement_string_start,
		  displacement_string_end))
   return 0;
}

    /* Special case for (%dx) while doing input/output op.  */
    if (i.base_reg
 && i.base_reg->reg_type == (Reg160x2 | InOutPortReg0x20000)
 && i.index_reg == 0
 && i.log2_scale_factor == 0
 && i.seg[i.mem_operands] == 0
 && (i.types[this_operand] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)) == 0)
{
 i.types[this_operand] = InOutPortReg0x20000;
 return 1;
}

    if (i386_index_check (operand_string) == 0)
return 0;
    i.mem_operands++;
  }
else
  {
    /* It's not a memory operand; argh!  */
    as_bad (_("invalid char %s beginning operand %d `%s'")("invalid char %s beginning operand %d `%s'"),
     output_invalid (*op_string),
     this_operand + 1,
     op_string);
    return 0;
  }
return 1;			/* Normal return.  */
4744}
4745
4746/* md_estimate_size_before_relax()

 Called just before relax() for rs_machine_dependent frags.  The x86
 assembler uses these frags to handle variable size jump
 instructions.

 Any symbol that is now undefined will not become defined.
 Return the correct fr_subtype in the frag.
 Return the initial "guess for variable size of frag" to caller.
 The guess is actually the growth beyond the fixed part.  Whatever
 we do to grow the fixed or variable part contributes to our
 returned value.  */

4759int
4760md_estimate_size_before_relax (fragP, segment)
   fragS *fragP;
   segT segment;
4763{
/* We've already got fragP->fr_subtype right;  all we have to do is
   check for un-relaxable symbols.  On an ELF system, we can't relax
   an externally visible symbol, because it may be overridden by a
   shared library.  */
if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4769#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
    || (IS_ELF1
 && (S_IS_EXTERNAL (fragP->fr_symbol)
     || S_IS_WEAK (fragP->fr_symbol)))
4773#endif
    )
  {
    /* Symbol is undefined in this segment, or we need to keep a
reloc so that weak symbols can be overridden.  */
    int size = (fragP->fr_subtype & CODE161) ? 2 : 4;
    enum bfd_reloc_code_real reloc_type;
    unsigned char *opcode;
    int old_fr_fix;

    if (fragP->fr_var != NO_RELOCBFD_RELOC_NONE)
reloc_type = fragP->fr_var;
    else if (size == 2)
reloc_type = BFD_RELOC_16_PCREL;
    else
reloc_type = BFD_RELOC_32_PCREL;

    old_fr_fix = fragP->fr_fix;
    opcode = (unsigned char *) fragP->fr_opcode;

    switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)((fragP->fr_subtype) >> 2))
{
case UNCOND_JUMP0:
 /* Make jmp (0xeb) a (d)word displacement jump.  */
 opcode[0] = 0xe9;
 fragP->fr_fix += size;
 fix_new (fragP, old_fr_fix, size,
   fragP->fr_symbol,
   fragP->fr_offset, 1,
   reloc_type);
 break;

case COND_JUMP862:
 if (size == 2
     && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOCBFD_RELOC_NONE))
   {
     /* Negate the condition, and branch past an
 unconditional jump.  */
     opcode[0] ^= 1;
     opcode[1] = 3;
     /* Insert an unconditional jump.  */
     opcode[2] = 0xe9;
     /* We added two extra opcode bytes, and have a two byte
 offset.  */
     fragP->fr_fix += 2 + 2;
     fix_new (fragP, old_fr_fix + 2, 2,
       fragP->fr_symbol,
       fragP->fr_offset, 1,
       reloc_type);
     break;
   }
 /* Fall through.  */

case COND_JUMP1:
 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOCBFD_RELOC_NONE)
   {
     fixS *fixP;

     fragP->fr_fix += 1;
     fixP = fix_new (fragP, old_fr_fix, 1,
	      fragP->fr_symbol,
	      fragP->fr_offset, 1,
	      BFD_RELOC_8_PCREL);
     fixP->fx_signed = 1;
     break;
   }

 /* This changes the byte-displacement jump 0x7N
    to the (d)word-displacement jump 0x0f,0x8N.  */
 opcode[1] = opcode[0] + 0x10;
 opcode[0] = TWO_BYTE_OPCODE_ESCAPE0x0f;
 /* We've added an opcode byte.  */
 fragP->fr_fix += 1 + size;
 fix_new (fragP, old_fr_fix + 1, size,
   fragP->fr_symbol,
   fragP->fr_offset, 1,
   reloc_type);
 break;

default:
 BAD_CASE (fragP->fr_subtype){ as_fatal (("Case value %ld unexpected at line %d of file \"%s\"\n"
), (long) fragP->fr_subtype, 4853, "/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
); };
 break;
}
    frag_wane (fragP);
    return fragP->fr_fix - old_fr_fix;
  }

/* Guess size depending on current relax state.  Initially the relax
   state will correspond to a short jump and we return 1, because
   the variable part of the frag (the branch offset) is one byte
   long.  However, we can relax a section more than once and in that
   case we must either set fr_subtype back to the unrelaxed state,
   or return the value for the appropriate branch.  */
return md_relax_table[fragP->fr_subtype].rlx_length;
4867}

4869/* Called after relax() is finished.

 In:	Address of frag.
fr_type == rs_machine_dependent.
fr_subtype is what the address relaxed to.

 Out:	Any fixSs and constants are set up.
Caller will turn frag into a ".space 0".  */

4878void
4879md_convert_frag (abfd, sec, fragP)
   bfd *abfd ATTRIBUTE_UNUSED__attribute__ ((__unused__));
   segT sec ATTRIBUTE_UNUSED__attribute__ ((__unused__));
   fragS *fragP;
4883{
unsigned char *opcode;
unsigned char *where_to_put_displacement = NULL((void*)0);
offsetT target_address;
offsetT opcode_address;
unsigned int extension = 0;
offsetT displacement_from_opcode_start;

opcode = (unsigned char *) fragP->fr_opcode;

/* Address we want to reach in file space.  */
target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;

/* Address opcode resides at in file space.  */
opcode_address = fragP->fr_address + fragP->fr_fix;

/* Displacement from opcode start to fill into instruction.  */
displacement_from_opcode_start = target_address - opcode_address;

if ((fragP->fr_subtype & BIG2) == 0)
  {
    /* Don't have to change opcode.  */
    extension = 1;		/* 1 opcode + 1 displacement  */
    where_to_put_displacement = &opcode[1];
  }
else
  {
    if (no_cond_jump_promotion
 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype)((fragP->fr_subtype) >> 2) != UNCOND_JUMP0)
as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")("long jump required"));

    switch (fragP->fr_subtype)
{
case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)((relax_substateT) (((0) << 2) | (2))):
 extension = 4;		/* 1 opcode + 4 displacement  */
 opcode[0] = 0xe9;
 where_to_put_displacement = &opcode[1];
 break;

case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)((relax_substateT) (((0) << 2) | ((2 | 1)))):
 extension = 2;		/* 1 opcode + 2 displacement  */
 opcode[0] = 0xe9;
 where_to_put_displacement = &opcode[1];
 break;

case ENCODE_RELAX_STATE (COND_JUMP, BIG)((relax_substateT) (((1) << 2) | (2))):
case ENCODE_RELAX_STATE (COND_JUMP86, BIG)((relax_substateT) (((2) << 2) | (2))):
 extension = 5;		/* 2 opcode + 4 displacement  */
 opcode[1] = opcode[0] + 0x10;
 opcode[0] = TWO_BYTE_OPCODE_ESCAPE0x0f;
 where_to_put_displacement = &opcode[2];
 break;

case ENCODE_RELAX_STATE (COND_JUMP, BIG16)((relax_substateT) (((1) << 2) | ((2 | 1)))):
 extension = 3;		/* 2 opcode + 2 displacement  */
 opcode[1] = opcode[0] + 0x10;
 opcode[0] = TWO_BYTE_OPCODE_ESCAPE0x0f;
 where_to_put_displacement = &opcode[2];
 break;

case ENCODE_RELAX_STATE (COND_JUMP86, BIG16)((relax_substateT) (((2) << 2) | ((2 | 1)))):
 extension = 4;
 opcode[0] ^= 1;
 opcode[1] = 3;
 opcode[2] = 0xe9;
 where_to_put_displacement = &opcode[3];
 break;

default:
 BAD_CASE (fragP->fr_subtype){ as_fatal (("Case value %ld unexpected at line %d of file \"%s\"\n"
), (long) fragP->fr_subtype, 4952, "/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
); };
 break;
}
  }

/* If size if less then four we are sure that the operand fits,
   but if it's 4, then it could be that the displacement is larger
   then -/+ 2GB.  */
if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)((((fragP->fr_subtype) & 3) == 2 ? 4 : (((fragP->fr_subtype
) & 3) == (2 | 1) ? 2 : 1))) == 4
    && object_64bit
    && ((addressT) (displacement_from_opcode_start - extension
                    + ((addressT) 1 << 31))
        > (((addressT) 2 << 31) - 1)))
  {
    as_bad_where (fragP->fr_file, fragP->fr_line,
    _("jump target out of range")("jump target out of range"));
    /* Make us emit 0.  */
    displacement_from_opcode_start = extension;
  }
/* Now put displacement after opcode.  */
md_number_to_charsnumber_to_chars_littleendian ((char *) where_to_put_displacement,
      (valueT) (displacement_from_opcode_start - extension),
      DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)((((fragP->fr_subtype) & 3) == 2 ? 4 : (((fragP->fr_subtype
) & 3) == (2 | 1) ? 2 : 1))));
fragP->fr_fix += extension;
4976}
4977
4978/* Size of byte displacement jmp.  */
4979int md_short_jump_size = 2;

4981/* Size of dword displacement jmp.  */
4982int md_long_jump_size = 5;

4984void
4985md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
   char *ptr;
   addressT from_addr, to_addr;
   fragS *frag ATTRIBUTE_UNUSED__attribute__ ((__unused__));
   symbolS *to_symbol ATTRIBUTE_UNUSED__attribute__ ((__unused__));
4990{
offsetT offset;

offset = to_addr - (from_addr + 2);
/* Opcode for byte-disp jump.  */
md_number_to_charsnumber_to_chars_littleendian (ptr, (valueT) 0xeb, 1);
md_number_to_charsnumber_to_chars_littleendian (ptr + 1, (valueT) offset, 1);
4997}

4999void
5000md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
   char *ptr;
   addressT from_addr, to_addr;
   fragS *frag ATTRIBUTE_UNUSED__attribute__ ((__unused__));
   symbolS *to_symbol ATTRIBUTE_UNUSED__attribute__ ((__unused__));
5005{
offsetT offset;

offset = to_addr - (from_addr + 5);
md_number_to_charsnumber_to_chars_littleendian (ptr, (valueT) 0xe9, 1);
md_number_to_charsnumber_to_chars_littleendian (ptr + 1, (valueT) offset, 4);
5011}
5012
5013/* Apply a fixup (fixS) to segment data, once it has been determined
 by our caller that we have all the info we need to fix it up.

 On the 386, immediates, displacements, and data pointers are all in
 the same (little-endian) format, so we don't need to care about which
 we are handling.  */

5020void
5021md_apply_fix (fixP, valP, seg)
   /* The fix we're to put in.  */
   fixS *fixP;
   /* Pointer to the value of the bits.  */
   valueT *valP;
   /* Segment fix is from.  */
   segT seg ATTRIBUTE_UNUSED__attribute__ ((__unused__));
5028{
char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
valueT value = *valP;

5032#if !defined (TE_Mach)
if (fixP->fx_pcrel)
  {
    switch (fixP->fx_r_type)
{
default:
 break;

case BFD_RELOC_64:
 fixP->fx_r_type = BFD_RELOC_64_PCREL;
 break;
case BFD_RELOC_32:
case BFD_RELOC_X86_64_32S:
 fixP->fx_r_type = BFD_RELOC_32_PCREL;
 break;
case BFD_RELOC_16:
 fixP->fx_r_type = BFD_RELOC_16_PCREL;
 break;
case BFD_RELOC_8:
 fixP->fx_r_type = BFD_RELOC_8_PCREL;
 break;
}
  }

if (fixP->fx_addsy != NULL((void*)0)
    && (fixP->fx_r_type == BFD_RELOC_32_PCREL
 || fixP->fx_r_type == BFD_RELOC_64_PCREL
 || fixP->fx_r_type == BFD_RELOC_16_PCREL
 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
    && !use_rela_relocations)
  {
    /* This is a hack.  There should be a better way to handle this.
This covers for the fact that bfd_install_relocation will
subtract the current location (for partial_inplace, PC relative
relocations); see more below.  */
5067#ifndef OBJ_AOUT
    if (IS_ELF1
5069#ifdef TE_PE
 || OUTPUT_FLAVORbfd_target_elf_flavour == bfd_target_coff_flavour
5071#endif
 )
value += fixP->fx_where + fixP->fx_frag->fr_address;
5074#endif
5075#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
    if (IS_ELF1)
{
 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);

 if ((sym_seg == seg
      || (symbol_section_p (fixP->fx_addsy)
   && sym_seg != absolute_section((asection *) &bfd_abs_section)))
     && !generic_force_reloc (fixP))
   {
     /* Yes, we add the values in twice.  This is because
 bfd_install_relocation subtracts them out again.  I think
 bfd_install_relocation is broken, but I don't dare change
 it.  FIXME.  */
     value += fixP->fx_where + fixP->fx_frag->fr_address;
   }
}
5092#endif
5093#if defined (OBJ_COFF) && defined (TE_PE)
    /* For some reason, the PE format does not store a
section address offset for a PC relative symbol.  */
    if (S_GET_SEGMENT (fixP->fx_addsy) != seg
 || S_IS_WEAK (fixP->fx_addsy))
value += md_pcrel_from (fixP);
5099#endif
  }

/* Fix a few things - the dynamic linker expects certain values here,
   and we must not disappoint it.  */
5104#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
if (IS_ELF1 && fixP->fx_addsy)
  switch (fixP->fx_r_type)
    {
    case BFD_RELOC_386_PLT32:
    case BFD_RELOC_X86_64_PLT32:
/* Make the jump instruction point to the address of the operand.  At
  runtime we merely add the offset to the actual PLT entry.  */
value = -4;
break;

    case BFD_RELOC_386_TLS_GD:
    case BFD_RELOC_386_TLS_LDM:
    case BFD_RELOC_386_TLS_IE_32:
    case BFD_RELOC_386_TLS_IE:
    case BFD_RELOC_386_TLS_GOTIE:
    case BFD_RELOC_386_TLS_GOTDESC:
    case BFD_RELOC_X86_64_TLSGD:
    case BFD_RELOC_X86_64_TLSLD:
    case BFD_RELOC_X86_64_GOTTPOFF:
    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
value = 0; /* Fully resolved at runtime.  No addend.  */
/* Fallthrough */
    case BFD_RELOC_386_TLS_LE:
    case BFD_RELOC_386_TLS_LDO_32:
    case BFD_RELOC_386_TLS_LE_32:
    case BFD_RELOC_X86_64_DTPOFF32:
    case BFD_RELOC_X86_64_DTPOFF64:
    case BFD_RELOC_X86_64_TPOFF32:
    case BFD_RELOC_X86_64_TPOFF64:
S_SET_THREAD_LOCAL (fixP->fx_addsy);
break;

    case BFD_RELOC_386_TLS_DESC_CALL:
    case BFD_RELOC_X86_64_TLSDESC_CALL:
value = 0; /* Fully resolved at runtime.  No addend.  */
S_SET_THREAD_LOCAL (fixP->fx_addsy);
fixP->fx_done = 0;
return;

    case BFD_RELOC_386_GOT32:
    case BFD_RELOC_X86_64_GOT32:
value = 0; /* Fully resolved at runtime.  No addend.  */
break;

    case BFD_RELOC_VTABLE_INHERIT:
    case BFD_RELOC_VTABLE_ENTRY:
fixP->fx_done = 0;
return;

    default:
break;
    }
5157#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)  */
*valP = value;
5159#endif /* !defined (TE_Mach)  */

/* Are we finished with this relocation now?  */
if (fixP->fx_addsy == NULL((void*)0))
  fixP->fx_done = 1;
else if (use_rela_relocations)
  {
    fixP->fx_no_overflow = 1;
    /* Remember value for tc_gen_reloc.  */
    fixP->fx_addnumber = value;
    value = 0;
  }

md_number_to_charsnumber_to_chars_littleendian (p, value, fixP->fx_size);
5173}
5174
5175#define MAX_LITTLENUMS6 6

5177/* Turn the string pointed to by litP into a floating point constant
 of type TYPE, and emit the appropriate bytes.  The number of
 LITTLENUMS emitted is stored in *SIZEP.  An error message is
 returned, or NULL on OK.  */

5182char *
5183md_atof (type, litP, sizeP)
   int type;
   char *litP;
   int *sizeP;
5187{
int prec;
LITTLENUM_TYPE words[MAX_LITTLENUMS6];
LITTLENUM_TYPE *wordP;
char *t;

switch (type)
  {
  case 'f':
  case 'F':
    prec = 2;
    break;

  case 'd':
  case 'D':
    prec = 4;
    break;

  case 'x':
  case 'X':
    prec = 5;
    break;

  default:
    *sizeP = 0;
    return _("Bad call to md_atof ()")("Bad call to md_atof ()");
  }
t = atof_ieee (input_line_pointer, type, words);
if (t)
  input_line_pointer = t;

*sizeP = prec * sizeof (LITTLENUM_TYPE);
/* This loops outputs the LITTLENUMs in REVERSE order; in accord with
   the bigendian 386.  */
for (wordP = words + prec - 1; prec--;)
  {
    md_number_to_charsnumber_to_chars_littleendian (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
    litP += sizeof (LITTLENUM_TYPE);
  }
return 0;
5227}
5228
5229static char output_invalid_buf[8];

5231static char *
5232output_invalid (c)
   int c;
5234{
if (ISPRINT (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isprint
)))
  sprintf (output_invalid_buf, "'%c'", c);
else
  sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
return output_invalid_buf;
5240}

5242/* REG_STRING starts *before* REGISTER_PREFIX.  */

5244static const reg_entry *
5245parse_real_register (char *reg_string, char **end_op)
5246{
char *s = reg_string;
char *p;
char reg_name_given[MAX_REG_NAME_SIZE8 + 1];
const reg_entry *r;

/* Skip possible REGISTER_PREFIX and possible whitespace.  */
if (*s == REGISTER_PREFIX'%')
  ++s;

if (is_space_char (*s)((*s) == ' '))
  ++s;

p = reg_name_given;
while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
  {
    if (p >= reg_name_given + MAX_REG_NAME_SIZE8)
return (const reg_entry *) NULL((void*)0);
    s++;
  }

/* For naked regs, make sure that we are not dealing with an identifier.
   This prevents confusing an identifier like `eax_var' with register
   `eax'.  */
if (allow_naked_reg && identifier_chars[(unsigned char) *s])
  return (const reg_entry *) NULL((void*)0);

*end_op = s;

r = (const reg_entry *) hash_find (reg_hash, reg_name_given);

/* Handle floating point regs, allowing spaces in the (i) part.  */
if (r == i386_regtab /* %st is first entry of table  */)
  {
    if (is_space_char (*s)((*s) == ' '))
++s;
    if (*s == '(')
{
 ++s;
 if (is_space_char (*s)((*s) == ' '))
   ++s;
 if (*s >= '0' && *s <= '7')
   {
     r = &i386_float_regtab[*s - '0'];
     ++s;
     if (is_space_char (*s)((*s) == ' '))
++s;
     if (*s == ')')
{
  *end_op = s + 1;
  return r;
}
   }
 /* We have "%st(" then garbage.  */
 return (const reg_entry *) NULL((void*)0);
}
  }

if (r != NULL((void*)0)
    && ((r->reg_flags & (RegRex640x2 | RegRex0x1)) | (r->reg_type & Reg640x8)) != 0
    && (r->reg_type != Control0x80000 || !(cpu_arch_flags & CpuSledgehammer0x400))
    && flag_code != CODE_64BIT)
  return (const reg_entry *) NULL((void*)0);

return r;
5311}

5313/* REG_STRING starts *before* REGISTER_PREFIX.  */

5315static const reg_entry *
5316parse_register (char *reg_string, char **end_op)
5317{
const reg_entry *r;

if (*reg_string == REGISTER_PREFIX'%' || allow_naked_reg)
7
←
Assuming the condition is false→
8
←
Assuming 'allow_naked_reg' is 0→
9
←
Taking false branch→
  r = parse_real_register (reg_string, end_op);
else
  r = NULL((void*)0);
if (!r9.1
'r' is null
)
10
←
Taking true branch→
  {
    char *save = input_line_pointer;
    char c;
    symbolS *symbolP;

    input_line_pointer = reg_string;
    c = get_symbol_end ();
    symbolP = symbol_find (reg_string);
11
←
Value assigned to 'i.base_reg', which participates in a condition later→
    if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
12
←
Assuming 'symbolP' is null→
{
 const expressionS *e = symbol_get_value_expression (symbolP);

 know (e->X_op == O_register);
 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
 r = i386_regtab + e->X_add_number;
 *end_op = input_line_pointer;
}
    *input_line_pointer = c;
    input_line_pointer = save;
  }
return r;
13
←
Returning without writing to '*end_op'→
5346}

5348int
5349i386_parse_name (char *name, expressionS *e, char *nextcharP)
5350{
const reg_entry *r;
char *end = input_line_pointer;

*end = *nextcharP;
r = parse_register (name, &input_line_pointer);
if (r && end <= input_line_pointer)
  {
    *nextcharP = *input_line_pointer;
    *input_line_pointer = 0;
    e->X_op = O_register;
    e->X_add_number = r - i386_regtab;
    return 1;
  }
input_line_pointer = end;
*end = 0;
return 0;
5367}

5369void
5370md_operand (expressionS *e)
5371{
if (*input_line_pointer == REGISTER_PREFIX'%')
  {
    char *end;
    const reg_entry *r = parse_real_register (input_line_pointer, &end);

    if (r)
{
 e->X_op = O_register;
 e->X_add_number = r - i386_regtab;
 input_line_pointer = end;
}
  }
5384}

5386
5387#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
5388const char *md_shortopts = "kVQ:sqn";
5389#else
5390const char *md_shortopts = "qn";
5391#endif

5393#define OPTION_32(190 + 0) (OPTION_MD_BASE190 + 0)
5394#define OPTION_64(190 + 1) (OPTION_MD_BASE190 + 1)
5395#define OPTION_DIVIDE(190 + 2) (OPTION_MD_BASE190 + 2)

5397struct option md_longopts[] = {
{"32", no_argument0, NULL((void*)0), OPTION_32(190 + 0)},
5399#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
{"64", no_argument0, NULL((void*)0), OPTION_64(190 + 1)},
5401#endif
{"divide", no_argument0, NULL((void*)0), OPTION_DIVIDE(190 + 2)},
{NULL((void*)0), no_argument0, NULL((void*)0), 0}
5404};
5405size_t md_longopts_size = sizeof (md_longopts);

5407int
5408md_parse_option (c, arg)
   int c;
   char *arg ATTRIBUTE_UNUSED__attribute__ ((__unused__));
5411{
switch (c)
  {
  case 'n':
    optimize_align_code = 0;
    break;

  case 'q':
    quiet_warnings = 1;
    break;

5422#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
    /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
should be emitted or not.  FIXME: Not implemented.  */
  case 'Q':
    break;

    /* -V: SVR4 argument to print version ID.  */
  case 'V':
    print_version_id ();
    break;

    /* -k: Ignore for FreeBSD compatibility.  */
  case 'k':
    break;

  case 's':
    /* -s: On i386 Solaris, this tells the native assembler to use
.stab instead of .stab.excl.  We always use .stab anyhow.  */
    break;

  case OPTION_64(190 + 1):
    {
const char **list, **l;

list = bfd_target_list ();
for (l = list; *l != NULL((void*)0); l++)
 if (strcmp (*l, "elf64-x86-64") == 0)
   {
     default_arch = "x86_64";
     break;
   }
if (*l == NULL((void*)0))
 as_fatal (_("No compiled in support for x86_64")("No compiled in support for x86_64"));
free (list);
    }
    break;
5458#endif

  case OPTION_32(190 + 0):
    default_arch = "i386";
    break;

  case OPTION_DIVIDE(190 + 2):
5465#ifdef SVR4_COMMENT_CHARS
    {
char *n, *t;
const char *s;

n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
t = n;
for (s = i386_comment_chars; *s != '\0'; s++)
 if (*s != '/')
   *t++ = *s;
*t = '\0';
i386_comment_chars = n;
    }
5478#endif
    break;

  default:
    return 0;
  }
return 1;
5485}

5487void
5488md_show_usage (stream)
   FILE *stream;
5490{
5491#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
fprintf (stream, _("\("  -Q                      ignored\n  -V                      print assembler version number\n  -k                      ignored\n"
)
-Q                      ignored\n\("  -Q                      ignored\n  -V                      print assembler version number\n  -k                      ignored\n"
)
-V                      print assembler version number\n\("  -Q                      ignored\n  -V                      print assembler version number\n  -k                      ignored\n"
)
-k                      ignored\n")("  -Q                      ignored\n  -V                      print assembler version number\n  -k                      ignored\n"
));
5496#endif
fprintf (stream, _("\("  -n                      Do not optimize code alignment\n  -q                      quieten some warnings\n"
)
-n                      Do not optimize code alignment\n\("  -n                      Do not optimize code alignment\n  -q                      quieten some warnings\n"
)
-q                      quieten some warnings\n")("  -n                      Do not optimize code alignment\n  -q                      quieten some warnings\n"
));
5500#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
fprintf (stream, _("\("  -s                      ignored\n")
-s                      ignored\n")("  -s                      ignored\n"));
5503#endif
5504#ifdef SVR4_COMMENT_CHARS
fprintf (stream, _("\("  --divide                do not treat `/' as a comment character\n"
)
--divide                do not treat `/' as a comment character\n")("  --divide                do not treat `/' as a comment character\n"
));
5507#else
fprintf (stream, _("\("  --divide                ignored\n")
--divide                ignored\n")("  --divide                ignored\n"));
5510#endif
5511}

5513#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
   || defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF))

5516/* Pick the target format to use.  */

5518const char *
5519i386_target_format ()
5520{
if (!strcmp (default_arch, "x86_64"))
  set_code_flag (CODE_64BIT);
else if (!strcmp (default_arch, "i386"))
  set_code_flag (CODE_32BIT);
else
  as_fatal (_("Unknown architecture")("Unknown architecture"));
switch (OUTPUT_FLAVORbfd_target_elf_flavour)
  {
5529#ifdef OBJ_MAYBE_AOUT
  case bfd_target_aout_flavour:
    return AOUT_TARGET_FORMAT"a.out-i386-netbsd";
5532#endif
5533#ifdef OBJ_MAYBE_COFF
  case bfd_target_coff_flavour:
    return "coff-i386";
5536#endif
5537#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF1)
  case bfd_target_elf_flavour:
    {
if (flag_code == CODE_64BIT)
 {
   object_64bit = 1;
   use_rela_relocations = 1;
 }
return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT"elf32-i386";
    }
5547#endif
  default:
    abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 5549, __PRETTY_FUNCTION__);
    return NULL((void*)0);
  }
5552}

5554#endif /* OBJ_MAYBE_ more than one  */

5556#if (defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF))
5557void i386_elf_emit_arch_note ()
5558{
if (IS_ELF1 && cpu_arch_name != NULL((void*)0))
  {
    char *p;
    asection *seg = now_seg;
    subsegT subseg = now_subseg;
    Elf_Internal_Note i_note;
    Elf_External_Note e_note;
    asection *note_secp;
    int len;

    /* Create the .note section.  */
    note_secp = subseg_new (".note", 0);
    bfd_set_section_flags (stdoutput,
	     note_secp,
	     SEC_HAS_CONTENTS0x100 | SEC_READONLY0x008);

    /* Process the arch string.  */
    len = strlen (cpu_arch_name);

    i_note.namesz = len + 1;
    i_note.descsz = 0;
    i_note.type = NT_ARCH2;
    p = frag_more (sizeof (e_note.namesz));
    md_number_to_charsnumber_to_chars_littleendian (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
    p = frag_more (sizeof (e_note.descsz));
    md_number_to_charsnumber_to_chars_littleendian (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
    p = frag_more (sizeof (e_note.type));
    md_number_to_charsnumber_to_chars_littleendian (p, (valueT) i_note.type, sizeof (e_note.type));
    p = frag_more (len + 1);
    strcpy (p, cpu_arch_name);

    frag_align (2, 0, 0);

    subseg_set (seg, subseg);
  }
5594}
5595#endif
5596
5597symbolS *
5598md_undefined_symbol (name)
   char *name;
5600{
if (name[0] == GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_"[0]
    && name[1] == GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_"[1]
    && name[2] == GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_"[2]
    && strcmp (name, GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_") == 0)
  {
    if (!GOT_symbol)
{
 if (symbol_find (name))
   as_bad (_("GOT already in symbol table")("GOT already in symbol table"));
 GOT_symbol = symbol_new (name, undefined_section((asection *) &bfd_und_section),
		   (valueT) 0, &zero_address_frag);
};
    return GOT_symbol;
  }
return 0;
5616}

5618/* Round up a section size to the appropriate boundary.  */

5620valueT
5621md_section_align (segment, size)
   segT segment ATTRIBUTE_UNUSED__attribute__ ((__unused__));
   valueT size;
5624{
5625#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
if (OUTPUT_FLAVORbfd_target_elf_flavour == bfd_target_aout_flavour)
  {
    /* For a.out, force the section size to be aligned.  If we don't do
this, BFD will align it for us, but it will not write out the
final bytes of the section.  This may be a bug in BFD, but it is
easier to fix it here since that is how the other a.out targets
work.  */
    int align;

    align = bfd_get_section_alignment (stdoutput, segment)((segment)->alignment_power + 0);
    size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
  }
5638#endif

return size;
5641}

5643/* On the i386, PC-relative offsets are relative to the start of the
 next instruction.  That is, the address of the offset, plus its
 size, since the offset is always the last part of the insn.  */

5647long
5648md_pcrel_from (fixP)
   fixS *fixP;
5650{
return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5652}

5654#ifndef I386COFF

5656static void
5657s_bss (ignore)
   int ignore ATTRIBUTE_UNUSED__attribute__ ((__unused__));
5659{
int temp;

5662#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
if (IS_ELF1)
  obj_elf_section_change_hook ();
5665#endif
temp = get_absolute_expression ();
subseg_set (bss_section, (subsegT) temp);
demand_empty_rest_of_line ();
5669}

5671#endif

5673void
5674i386_validate_fix (fixp)
   fixS *fixp;
5676{
if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
  {
    if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
{
 if (!object_64bit)
   abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 5682, __PRETTY_FUNCTION__);
 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
}
    else
{
 if (!object_64bit)
   fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
 else
   fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
}
    fixp->fx_subsy = 0;
  }
5694}

5696arelent *
5697tc_gen_reloc (section, fixp)
   asection *section ATTRIBUTE_UNUSED__attribute__ ((__unused__));
   fixS *fixp;
5700{
arelent *rel;
bfd_reloc_code_real_type code;

switch (fixp->fx_r_type)
  {
  case BFD_RELOC_X86_64_PLT32:
  case BFD_RELOC_X86_64_GOT32:
  case BFD_RELOC_X86_64_GOTPCREL:
  case BFD_RELOC_386_PLT32:
  case BFD_RELOC_386_GOT32:
  case BFD_RELOC_386_GOTOFF:
  case BFD_RELOC_386_GOTPC:
  case BFD_RELOC_386_TLS_GD:
  case BFD_RELOC_386_TLS_LDM:
  case BFD_RELOC_386_TLS_LDO_32:
  case BFD_RELOC_386_TLS_IE_32:
  case BFD_RELOC_386_TLS_IE:
  case BFD_RELOC_386_TLS_GOTIE:
  case BFD_RELOC_386_TLS_LE_32:
  case BFD_RELOC_386_TLS_LE:
  case BFD_RELOC_386_TLS_GOTDESC:
  case BFD_RELOC_386_TLS_DESC_CALL:
  case BFD_RELOC_X86_64_TLSGD:
  case BFD_RELOC_X86_64_TLSLD:
  case BFD_RELOC_X86_64_DTPOFF32:
  case BFD_RELOC_X86_64_DTPOFF64:
  case BFD_RELOC_X86_64_GOTTPOFF:
  case BFD_RELOC_X86_64_TPOFF32:
  case BFD_RELOC_X86_64_TPOFF64:
  case BFD_RELOC_X86_64_GOTOFF64:
  case BFD_RELOC_X86_64_GOTPC32:
  case BFD_RELOC_X86_64_GOT64:
  case BFD_RELOC_X86_64_GOTPCREL64:
  case BFD_RELOC_X86_64_GOTPC64:
  case BFD_RELOC_X86_64_GOTPLT64:
  case BFD_RELOC_X86_64_PLTOFF64:
  case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
  case BFD_RELOC_X86_64_TLSDESC_CALL:
  case BFD_RELOC_RVA:
  case BFD_RELOC_VTABLE_ENTRY:
  case BFD_RELOC_VTABLE_INHERIT:
5742#ifdef TE_PE
  case BFD_RELOC_32_SECREL:
5744#endif
    code = fixp->fx_r_type;
    break;
  case BFD_RELOC_X86_64_32S:
    if (!fixp->fx_pcrel)
{
 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32.  */
 code = fixp->fx_r_type;
 break;
}
  default:
    if (fixp->fx_pcrel)
{
 switch (fixp->fx_size)
   {
   default:
     as_bad_where (fixp->fx_file, fixp->fx_line,
	    _("can not do %d byte pc-relative relocation")("can not do %d byte pc-relative relocation"),
	    fixp->fx_size);
     code = BFD_RELOC_32_PCREL;
     break;
   case 1: code = BFD_RELOC_8_PCREL;  break;
   case 2: code = BFD_RELOC_16_PCREL; break;
   case 4: code = BFD_RELOC_32_PCREL; break;
5768#ifdef BFD64
   case 8: code = BFD_RELOC_64_PCREL; break;
5770#endif
   }
}
    else
{
 switch (fixp->fx_size)
   {
   default:
     as_bad_where (fixp->fx_file, fixp->fx_line,
	    _("can not do %d byte relocation")("can not do %d byte relocation"),
	    fixp->fx_size);
     code = BFD_RELOC_32;
     break;
   case 1: code = BFD_RELOC_8;  break;
   case 2: code = BFD_RELOC_16; break;
   case 4: code = BFD_RELOC_32; break;
5786#ifdef BFD64
   case 8: code = BFD_RELOC_64; break;
5788#endif
   }
}
    break;
  }

if ((code == BFD_RELOC_32
     || code == BFD_RELOC_32_PCREL
     || code == BFD_RELOC_X86_64_32S)
    && GOT_symbol
    && fixp->fx_addsy == GOT_symbol)
  {
    if (!object_64bit)
code = BFD_RELOC_386_GOTPC;
    else
code = BFD_RELOC_X86_64_GOTPC32;
  }
if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
    && GOT_symbol
    && fixp->fx_addsy == GOT_symbol)
  {
    code = BFD_RELOC_X86_64_GOTPC64;
  }

rel = (arelent *) xmalloc (sizeof (arelent));
rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
*rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);

rel->address = fixp->fx_frag->fr_address + fixp->fx_where;

if (!use_rela_relocations)
  {
    /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
vtable entry to be used in the relocation's section offset.  */
    if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
rel->address = fixp->fx_offset;

    rel->addend = 0;
  }
/* Use the rela in 64bit mode.  */
else
  {
    if (!fixp->fx_pcrel)
rel->addend = fixp->fx_offset;
    else
switch (code)
 {
 case BFD_RELOC_X86_64_PLT32:
 case BFD_RELOC_X86_64_GOT32:
 case BFD_RELOC_X86_64_GOTPCREL:
 case BFD_RELOC_X86_64_TLSGD:
 case BFD_RELOC_X86_64_TLSLD:
 case BFD_RELOC_X86_64_GOTTPOFF:
 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
 case BFD_RELOC_X86_64_TLSDESC_CALL:
   rel->addend = fixp->fx_offset - fixp->fx_size;
   break;
 default:
   rel->addend = (section->vma
	   - fixp->fx_size
	   + fixp->fx_addnumber
	   + md_pcrel_from (fixp));
   break;
 }
  }

rel->howto = bfd_reloc_type_lookup (stdoutput, code);
if (rel->howto == NULL((void*)0))
  {
    as_bad_where (fixp->fx_file, fixp->fx_line,
    _("cannot represent relocation type %s")("cannot represent relocation type %s"),
    bfd_get_reloc_code_name (code));
    /* Set howto to a garbage value so that we can keep going.  */
    rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
    assert (rel->howto != NULL)((void) ((rel->howto != ((void*)0)) ? 0 : (as_assert ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c"
, 5862, __PRETTY_FUNCTION__), 0)));
  }

return rel;
5866}

5868
5869/* Parse operands using Intel syntax. This implements a recursive descent
 parser based on the BNF grammar published in Appendix B of the MASM 6.1
 Programmer's Guide.

 FIXME: We do not recognize the full operand grammar defined in the MASM
 documentation.  In particular, all the structure/union and
 high-level macro operands are missing.

 Uppercase words are terminals, lower case words are non-terminals.
 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
 bars '|' denote choices. Most grammar productions are implemented in
 functions called 'intel_<production>'.

 Initial production is 'expr'.

  addOp		+ | -

  alpha		[a-zA-Z]

  binOp		& | AND | \| | OR | ^ | XOR

  byteRegister	AL | AH | BL | BH | CL | CH | DL | DH

  constant		digits [[ radixOverride ]]

  dataType		BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD

  digits		decdigit
	| digits decdigit
	| digits hexdigit

  decdigit		[0-9]

  e04			e04 addOp e05
	| e05

  e05			e05 binOp e06
	| e06

  e06			e06 mulOp e09
	| e09

  e09			OFFSET e10
	| SHORT e10
	| + e10
	| - e10
	| ~ e10
	| NOT e10
	| e09 PTR e10
	| e09 : e10
	| e10

  e10			e10 [ expr ]
	| e11

  e11			( expr )
	| [ expr ]
	| constant
	| dataType
	| id
	| $
	| register

=> expr		expr cmpOp e04
	| e04

  gpRegister		AX | EAX | BX | EBX | CX | ECX | DX | EDX
	| BP | EBP | SP | ESP | DI | EDI | SI | ESI

  hexdigit		a | b | c | d | e | f
	| A | B | C | D | E | F

  id			alpha
	| id alpha
	| id decdigit

  mulOp		* | / | % | MOD | << | SHL | >> | SHR

  quote		" | '

  register		specialRegister
	| gpRegister
	| byteRegister

  segmentRegister	CS | DS | ES | FS | GS | SS

  specialRegister	CR0 | CR2 | CR3 | CR4
	| DR0 | DR1 | DR2 | DR3 | DR6 | DR7
	| TR3 | TR4 | TR5 | TR6 | TR7

  We simplify the grammar in obvious places (e.g., register parsing is
  done by calling parse_register) and eliminate immediate left recursion
  to implement a recursive-descent parser.

  expr	e04 expr'

  expr'	cmpOp e04 expr'
| Empty

  e04		e05 e04'

  e04'	addOp e05 e04'
| Empty

  e05		e06 e05'

  e05'	binOp e06 e05'
| Empty

  e06		e09 e06'

  e06'	mulOp e09 e06'
| Empty

  e09		OFFSET e10 e09'
| SHORT e10'
| + e10'
| - e10'
| ~ e10'
| NOT e10'
| e10 e09'

  e09'	PTR e10 e09'
| : e10 e09'
| Empty

  e10		e11 e10'

  e10'	[ expr ] e10'
| Empty

  e11		( expr )
| [ expr ]
| BYTE
| WORD
| DWORD
| FWORD
| QWORD
| TBYTE
| OWORD
| XMMWORD
| .
| $
| register
| id
| constant  */

6016/* Parsing structure for the intel syntax parser. Used to implement the
 semantic actions for the operand grammar.  */
6018struct intel_parser_s
{
  char *op_string;		/* The string being parsed.  */
  int got_a_float;		/* Whether the operand is a float.  */
  int op_modifier;		/* Operand modifier.  */
  int is_mem;			/* 1 if operand is memory reference.  */
  int in_offset;			/* >=1 if parsing operand of offset.  */
  int in_bracket;			/* >=1 if parsing operand in brackets.  */
  const reg_entry *reg;	/* Last register reference found.  */
  char *disp;			/* Displacement string being built.  */
  char *next_operand;		/* Resume point when splitting operands.  */
};

6031static struct intel_parser_s intel_parser;

6033/* Token structure for parsing intel syntax.  */
6034struct intel_token
{
  int code;			/* Token code.  */
  const reg_entry *reg;	/* Register entry for register tokens.  */
  char *str;			/* String representation.  */
};

6041static struct intel_token cur_token, prev_token;

6043/* Token codes for the intel parser. Since T_SHORT is already used
 by COFF, undefine it first to prevent a warning.  */
6045#define T_NIL-1		-1
6046#define T_CONST1		1
6047#define T_REG2		2
6048#define T_BYTE3		3
6049#define T_WORD4		4
6050#define T_DWORD5		5
6051#define T_FWORD6		6
6052#define T_QWORD7		7
6053#define T_TBYTE8		8
6054#define T_XMMWORD9	9
6055#undef  T_SHORT10
6056#define T_SHORT10		10
6057#define T_OFFSET11	11
6058#define T_PTR12		12
6059#define T_ID13		13
6060#define T_SHL14		14
6061#define T_SHR15		15

6063/* Prototypes for intel parser functions.  */
6064static int intel_match_token	PARAMS ((int code))(int code);
6065static void intel_get_token	PARAMS ((void))(void);
6066static void intel_putback_token	PARAMS ((void))(void);
6067static int intel_expr		PARAMS ((void))(void);
6068static int intel_e04		PARAMS ((void))(void);
6069static int intel_e05		PARAMS ((void))(void);
6070static int intel_e06		PARAMS ((void))(void);
6071static int intel_e09		PARAMS ((void))(void);
6072static int intel_bracket_expr	PARAMS ((void))(void);
6073static int intel_e10		PARAMS ((void))(void);
6074static int intel_e11		PARAMS ((void))(void);

6076static int
6077i386_intel_operand (operand_string, got_a_float)
   char *operand_string;
   int got_a_float;
6080{
int ret;
char *p;

p = intel_parser.op_string = xstrdup (operand_string);
intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);

for (;;)
  {
    /* Initialize token holders.  */
    cur_token.code = prev_token.code = T_NIL-1;
    cur_token.reg = prev_token.reg = NULL((void*)0);
    cur_token.str = prev_token.str = NULL((void*)0);

    /* Initialize parser structure.  */
    intel_parser.got_a_float = got_a_float;
    intel_parser.op_modifier = 0;
    intel_parser.is_mem = 0;
    intel_parser.in_offset = 0;
    intel_parser.in_bracket = 0;
    intel_parser.reg = NULL((void*)0);
    intel_parser.disp[0] = '\0';
    intel_parser.next_operand = NULL((void*)0);

    /* Read the first token and start the parser.  */
    intel_get_token ();
    ret = intel_expr ();

    if (!ret)
break;

    if (cur_token.code != T_NIL-1)
{
 as_bad (_("invalid operand for '%s' ('%s' unexpected)")("invalid operand for '%s' ('%s' unexpected)"),
  current_templates->start->name, cur_token.str);
 ret = 0;
}
    /* If we found a memory reference, hand it over to i386_displacement
to fill in the rest of the operand fields.  */
    else if (intel_parser.is_mem)
{
 if ((i.mem_operands == 1
      && (current_templates->start->opcode_modifier & IsString0x2000000) == 0)
     || i.mem_operands == 2)
   {
     as_bad (_("too many memory references for '%s'")("too many memory references for '%s'"),
      current_templates->start->name);
     ret = 0;
   }
 else
   {
     char *s = intel_parser.disp;
     i.mem_operands++;

     if (!quiet_warnings && intel_parser.is_mem < 0)
/* See the comments in intel_bracket_expr.  */
as_warn (_("Treating `%s' as memory reference")("Treating `%s' as memory reference"), operand_string);

     /* Add the displacement expression.  */
     if (*s != '\0')
ret = i386_displacement (s, s + strlen (s));
     if (ret)
{
  /* Swap base and index in 16-bit memory operands like
     [si+bx]. Since i386_index_check is also used in AT&T
     mode we have to do that here.  */
  if (i.base_reg
      && i.index_reg
      && (i.base_reg->reg_type & Reg160x2)
      && (i.index_reg->reg_type & Reg160x2)
      && i.base_reg->reg_num >= 6
      && i.index_reg->reg_num < 6)
    {
      const reg_entry *base = i.index_reg;

      i.index_reg = i.base_reg;
      i.base_reg = base;
    }
  ret = i386_index_check (operand_string);
}
   }
}

    /* Constant and OFFSET expressions are handled by i386_immediate.  */
    else if ((intel_parser.op_modifier & (1 << T_OFFSET11))
      || intel_parser.reg == NULL((void*)0))
ret = i386_immediate (intel_parser.disp);

    if (intel_parser.next_operand && this_operand >= MAX_OPERANDS3 - 1)
      ret = 0;
    if (!ret || !intel_parser.next_operand)
break;
    intel_parser.op_string = intel_parser.next_operand;
    this_operand = i.operands++;
  }

free (p);
free (intel_parser.disp);

return ret;
6180}

6182#define NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) (!!i.base_reg + !!i.index_reg)

6184/* expr	e04 expr'

 expr'  cmpOp e04 expr'
| Empty  */
6188static int
6189intel_expr ()
6190{
/* XXX Implement the comparison operators.  */
return intel_e04 ();
6193}

6195/* e04	e05 e04'

 e04'	addOp e05 e04'
| Empty  */
6199static int
6200intel_e04 ()
6201{
int nregs = -1;

for (;;)
  {
    if (!intel_e05())
return 0;

    if (nregs >= 0 && NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs)
i.base_reg = i386_regtab + REGNAM_AL1; /* al is invalid as base */

    if (cur_token.code == '+')
nregs = -1;
    else if (cur_token.code == '-')
nregs = NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg);
    else
return 1;

    strcat (intel_parser.disp, cur_token.str);
    intel_match_token (cur_token.code);
  }
6222}

6224/* e05	e06 e05'

 e05'	binOp e06 e05'
| Empty  */
6228static int
6229intel_e05 ()
6230{
int nregs = ~NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg);

for (;;)
  {
    if (!intel_e06())
return 0;

    if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
{
 char str[2];

 str[0] = cur_token.code;
 str[1] = 0;
 strcat (intel_parser.disp, str);
}
    else
break;

    intel_match_token (cur_token.code);

    if (nregs < 0)
nregs = ~nregs;
  }
if (nregs >= 0 && NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs)
  i.base_reg = i386_regtab + REGNAM_AL1 + 1; /* cl is invalid as base */
return 1;
6257}

6259/* e06	e09 e06'

 e06'	mulOp e09 e06'
| Empty  */
6263static int
6264intel_e06 ()
6265{
int nregs = ~NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg);

for (;;)
  {
    if (!intel_e09())
return 0;

    if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
{
 char str[2];

 str[0] = cur_token.code;
 str[1] = 0;
 strcat (intel_parser.disp, str);
}
    else if (cur_token.code == T_SHL14)
strcat (intel_parser.disp, "<<");
    else if (cur_token.code == T_SHR15)
strcat (intel_parser.disp, ">>");
    else
break;

   intel_match_token (cur_token.code);

    if (nregs < 0)
nregs = ~nregs;
  }
if (nregs >= 0 && NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs)
  i.base_reg = i386_regtab + REGNAM_AL1 + 2; /* dl is invalid as base */
return 1;
6296}

6298/* e09	OFFSET e09
| SHORT e09
| + e09
| - e09
| ~ e09
| NOT e09
| e10 e09'

 e09'	PTR e10 e09'
| : e10 e09'
| Empty */
6309static int
6310intel_e09 ()
6311{
int nregs = ~NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg);
int in_offset = 0;

for (;;)
  {
    /* Don't consume constants here.  */
    if (cur_token.code == '+' || cur_token.code == '-')
{
 /* Need to look one token ahead - if the next token
    is a constant, the current token is its sign.  */
 int next_code;

 intel_match_token (cur_token.code);
 next_code = cur_token.code;
 intel_putback_token ();
 if (next_code == T_CONST1)
   break;
}

    /* e09  OFFSET e09  */
    if (cur_token.code == T_OFFSET11)
{
 if (!in_offset++)
   ++intel_parser.in_offset;
}

    /* e09  SHORT e09  */
    else if (cur_token.code == T_SHORT10)
intel_parser.op_modifier |= 1 << T_SHORT10;

    /* e09  + e09  */
    else if (cur_token.code == '+')
strcat (intel_parser.disp, "+");

    /* e09  - e09
     | ~ e09
     | NOT e09  */
    else if (cur_token.code == '-' || cur_token.code == '~')
{
 char str[2];

 if (nregs < 0)
   nregs = ~nregs;
 str[0] = cur_token.code;
 str[1] = 0;
 strcat (intel_parser.disp, str);
}

    /* e09  e10 e09'  */
    else
break;

    intel_match_token (cur_token.code);
  }

for (;;)
  {
    if (!intel_e10 ())
return 0;

    /* e09'  PTR e10 e09' */
    if (cur_token.code == T_PTR12)
{
 char suffix;

 if (prev_token.code == T_BYTE3)
   suffix = BYTE_MNEM_SUFFIX'b';

 else if (prev_token.code == T_WORD4)
   {
     if (current_templates->start->name[0] == 'l'
  && current_templates->start->name[2] == 's'
  && current_templates->start->name[3] == 0)
suffix = BYTE_MNEM_SUFFIX'b'; /* so it will cause an error */
     else if (intel_parser.got_a_float == 2)	/* "fi..." */
suffix = SHORT_MNEM_SUFFIX's';
     else
suffix = WORD_MNEM_SUFFIX'w';
   }

 else if (prev_token.code == T_DWORD5)
   {
     if (current_templates->start->name[0] == 'l'
  && current_templates->start->name[2] == 's'
  && current_templates->start->name[3] == 0)
suffix = WORD_MNEM_SUFFIX'w';
     else if (flag_code == CODE_16BIT
       && (current_templates->start->opcode_modifier
	   & (Jump0x40 | JumpDword0x80)))
suffix = LONG_DOUBLE_MNEM_SUFFIX'x';
     else if (intel_parser.got_a_float == 1)	/* "f..." */
suffix = SHORT_MNEM_SUFFIX's';
     else
suffix = LONG_MNEM_SUFFIX'l';
   }

 else if (prev_token.code == T_FWORD6)
   {
     if (current_templates->start->name[0] == 'l'
  && current_templates->start->name[2] == 's'
  && current_templates->start->name[3] == 0)
suffix = LONG_MNEM_SUFFIX'l';
     else if (!intel_parser.got_a_float)
{
  if (flag_code == CODE_16BIT)
    add_prefix (DATA_PREFIX_OPCODE0x66);
  suffix = LONG_DOUBLE_MNEM_SUFFIX'x';
}
     else
suffix = BYTE_MNEM_SUFFIX'b'; /* so it will cause an error */
   }

 else if (prev_token.code == T_QWORD7)
   {
     if (intel_parser.got_a_float == 1)	/* "f..." */
suffix = LONG_MNEM_SUFFIX'l';
     else
suffix = QWORD_MNEM_SUFFIX'q';
   }

 else if (prev_token.code == T_TBYTE8)
   {
     if (intel_parser.got_a_float == 1)
suffix = LONG_DOUBLE_MNEM_SUFFIX'x';
     else
suffix = BYTE_MNEM_SUFFIX'b'; /* so it will cause an error */
   }

 else if (prev_token.code == T_XMMWORD9)
   {
     /* XXX ignored for now, but accepted since gcc uses it */
     suffix = 0;
   }

 else
   {
     as_bad (_("Unknown operand modifier `%s'")("Unknown operand modifier `%s'"), prev_token.str);
     return 0;
   }

 /* Operands for jump/call using 'ptr' notation denote absolute
    addresses.  */
 if (current_templates->start->opcode_modifier & (Jump0x40 | JumpDword0x80))
   i.types[this_operand] |= JumpAbsolute0x8000000;

 if (current_templates->start->base_opcode == 0x8d /* lea */)
   ;
 else if (!i.suffix)
   i.suffix = suffix;
 else if (i.suffix != suffix)
   {
     as_bad (_("Conflicting operand modifiers")("Conflicting operand modifiers"));
     return 0;
   }

}

    /* e09'  : e10 e09'  */
    else if (cur_token.code == ':')
{
 if (prev_token.code != T_REG2)
   {
     /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
 segment/group identifier (which we don't have), using comma
 as the operand separator there is even less consistent, since
 there all branches only have a single operand.  */
     if (this_operand != 0
  || intel_parser.in_offset
  || intel_parser.in_bracket
  || (!(current_templates->start->opcode_modifier
	& (Jump0x40|JumpDword0x80|JumpInterSegment0x200))
      && !(current_templates->start->operand_types[0]
	   & JumpAbsolute0x8000000)))
return intel_match_token (T_NIL-1);
     /* Remember the start of the 2nd operand and terminate 1st
 operand here.
 XXX This isn't right, yet (when SSSS:OOOO is right operand of
 another expression), but it gets at least the simplest case
 (a plain number or symbol on the left side) right.  */
     intel_parser.next_operand = intel_parser.op_string;
     *--intel_parser.op_string = '\0';
     return intel_match_token (':');
   }
}

    /* e09'  Empty  */
    else
break;

    intel_match_token (cur_token.code);

  }

if (in_offset)
  {
    --intel_parser.in_offset;
    if (nregs < 0)
nregs = ~nregs;
    if (NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs)
{
 as_bad (_("Invalid operand to `OFFSET'")("Invalid operand to `OFFSET'"));
 return 0;
}
    intel_parser.op_modifier |= 1 << T_OFFSET11;
  }

if (nregs >= 0 && NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs)
  i.base_reg = i386_regtab + REGNAM_AL1 + 3; /* bl is invalid as base */
return 1;
6521}

6523static int
6524intel_bracket_expr ()
6525{
int was_offset = intel_parser.op_modifier & (1 << T_OFFSET11);
const char *start = intel_parser.op_string;
int len;

if (i.op[this_operand].regs)
  return intel_match_token (T_NIL-1);

intel_match_token ('[');

/* Mark as a memory operand only if it's not already known to be an
   offset expression.  If it's an offset expression, we need to keep
   the brace in.  */
if (!intel_parser.in_offset)
  {
    ++intel_parser.in_bracket;

    /* Operands for jump/call inside brackets denote absolute addresses.  */
    if (current_templates->start->opcode_modifier & (Jump0x40 | JumpDword0x80))
i.types[this_operand] |= JumpAbsolute0x8000000;

    /* Unfortunately gas always diverged from MASM in a respect that can't
be easily fixed without risking to break code sequences likely to be
encountered (the testsuite even check for this): MASM doesn't consider
an expression inside brackets unconditionally as a memory reference.
When that is e.g. a constant, an offset expression, or the sum of the
two, this is still taken as a constant load. gas, however, always
treated these as memory references. As a compromise, we'll try to make
offset expressions inside brackets work the MASM way (since that's
less likely to be found in real world code), but make constants alone
continue to work the traditional gas way. In either case, issue a
warning.  */
    intel_parser.op_modifier &= ~was_offset;
  }
else
    strcat (intel_parser.disp, "[");

/* Add a '+' to the displacement string if necessary.  */
if (*intel_parser.disp != '\0'
    && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
  strcat (intel_parser.disp, "+");

if (intel_expr ()
    && (len = intel_parser.op_string - start - 1,
 intel_match_token (']')))
  {
    /* Preserve brackets when the operand is an offset expression.  */
    if (intel_parser.in_offset)
strcat (intel_parser.disp, "]");
    else
{
 --intel_parser.in_bracket;
 if (i.base_reg || i.index_reg)
   intel_parser.is_mem = 1;
 if (!intel_parser.is_mem)
   {
     if (!(intel_parser.op_modifier & (1 << T_OFFSET11)))
/* Defer the warning until all of the operand was parsed.  */
intel_parser.is_mem = -1;
     else if (!quiet_warnings)
as_warn (_("`[%.*s]' taken to mean just `%.*s'")("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
   }
}
    intel_parser.op_modifier |= was_offset;

    return 1;
  }
return 0;
6593}

6595/* e10	e11 e10'

 e10'	[ expr ] e10'
| Empty  */
6599static int
6600intel_e10 ()
6601{
if (!intel_e11 ())
  return 0;

while (cur_token.code == '[')
  {
    if (!intel_bracket_expr ())
return 0;
  }

return 1;
6612}

6614/* e11	( expr )
| [ expr ]
| BYTE
| WORD
| DWORD
| FWORD
| QWORD
| TBYTE
| OWORD
| XMMWORD
| $
| .
| register
| id
| constant  */
6629static int
6630intel_e11 ()
6631{
switch (cur_token.code)
  {
  /* e11  ( expr ) */
  case '(':
    intel_match_token ('(');
    strcat (intel_parser.disp, "(");

    if (intel_expr () && intel_match_token (')'))
{
 strcat (intel_parser.disp, ")");
 return 1;
}
    return 0;

  /* e11  [ expr ] */
  case '[':
    return intel_bracket_expr ();

  /* e11  $
   | .  */
  case '.':
    strcat (intel_parser.disp, cur_token.str);
    intel_match_token (cur_token.code);

    /* Mark as a memory operand only if it's not already known to be an
offset expression.  */
    if (!intel_parser.in_offset)
intel_parser.is_mem = 1;

    return 1;

  /* e11  register  */
  case T_REG2:
    {
const reg_entry *reg = intel_parser.reg = cur_token.reg;

intel_match_token (T_REG2);

/* Check for segment change.  */
if (cur_token.code == ':')
 {
   if (!(reg->reg_type & (SReg20x1000000 | SReg30x2000000)))
     {
as_bad (_("`%s' is not a valid segment register")("`%s' is not a valid segment register"), reg->reg_name);
return 0;
     }
   else if (i.seg[i.mem_operands])
     as_warn (_("Extra segment override ignored")("Extra segment override ignored"));
   else
     {
if (!intel_parser.in_offset)
  intel_parser.is_mem = 1;
switch (reg->reg_num)
  {
  case 0:
    i.seg[i.mem_operands] = &es;
    break;
  case 1:
    i.seg[i.mem_operands] = &cs;
    break;
  case 2:
    i.seg[i.mem_operands] = &ss;
    break;
  case 3:
    i.seg[i.mem_operands] = &ds;
    break;
  case 4:
    i.seg[i.mem_operands] = &fs;
    break;
  case 5:
    i.seg[i.mem_operands] = &gs;
    break;
  }
     }
 }

/* Not a segment register. Check for register scaling.  */
else if (cur_token.code == '*')
 {
   if (!intel_parser.in_bracket)
     {
as_bad (_("Register scaling only allowed in memory operands")("Register scaling only allowed in memory operands"));
return 0;
     }

   if (reg->reg_type & Reg160x2) /* Disallow things like [si*1]. */
     reg = i386_regtab + REGNAM_AX25 + 4; /* sp is invalid as index */
   else if (i.index_reg)
     reg = i386_regtab + REGNAM_EAX41 + 4; /* esp is invalid as index */

   /* What follows must be a valid scale.  */
   intel_match_token ('*');
   i.index_reg = reg;
   i.types[this_operand] |= BaseIndex0x800;

   /* Set the scale after setting the register (otherwise,
      i386_scale will complain)  */
   if (cur_token.code == '+' || cur_token.code == '-')
     {
char *str, sign = cur_token.code;
intel_match_token (cur_token.code);
if (cur_token.code != T_CONST1)
  {
    as_bad (_("Syntax error: Expecting a constant, got `%s'")("Syntax error: Expecting a constant, got `%s'"),
	    cur_token.str);
    return 0;
  }
str = (char *) xmalloc (strlen (cur_token.str) + 2);
strcpy (str + 1, cur_token.str);
*str = sign;
if (!i386_scale (str))
  return 0;
free (str);
     }
   else if (!i386_scale (cur_token.str))
     return 0;
   intel_match_token (cur_token.code);
 }

/* No scaling. If this is a memory operand, the register is either a
  base register (first occurrence) or an index register (second
  occurrence).  */
else if (intel_parser.in_bracket)
 {

   if (!i.base_reg)
     i.base_reg = reg;
   else if (!i.index_reg)
     i.index_reg = reg;
   else
     {
as_bad (_("Too many register references in memory operand")("Too many register references in memory operand"));
return 0;
     }

   i.types[this_operand] |= BaseIndex0x800;
 }

/* It's neither base nor index.  */
else if (!intel_parser.in_offset && !intel_parser.is_mem)
 {
   i.types[this_operand] |= reg->reg_type & ~BaseIndex0x800;
   i.op[this_operand].regs = reg;
   i.reg_operands++;
 }
else
 {
   as_bad (_("Invalid use of register")("Invalid use of register"));
   return 0;
 }

/* Since registers are not part of the displacement string (except
  when we're parsing offset operands), we may need to remove any
  preceding '+' from the displacement string.  */
if (*intel_parser.disp != '\0'
   && !intel_parser.in_offset)
 {
   char *s = intel_parser.disp;
   s += strlen (s) - 1;
   if (*s == '+')
     *s = '\0';
 }

return 1;
    }

  /* e11  BYTE
   | WORD
   | DWORD
   | FWORD
   | QWORD
   | TBYTE
   | OWORD
   | XMMWORD  */
  case T_BYTE3:
  case T_WORD4:
  case T_DWORD5:
  case T_FWORD6:
  case T_QWORD7:
  case T_TBYTE8:
  case T_XMMWORD9:
    intel_match_token (cur_token.code);

    if (cur_token.code == T_PTR12)
return 1;

    /* It must have been an identifier.  */
    intel_putback_token ();
    cur_token.code = T_ID13;
    /* FALLTHRU */

  /* e11  id
   | constant  */
  case T_ID13:
    if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
{
 symbolS *symbolP;

 /* The identifier represents a memory reference only if it's not
    preceded by an offset modifier and if it's not an equate.  */
 symbolP = symbol_find(cur_token.str);
 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section((asection *) &bfd_abs_section))
   intel_parser.is_mem = 1;
}
/* FALLTHRU */

  case T_CONST1:
  case '-':
  case '+':
    {
char *save_str, sign = 0;

/* Allow constants that start with `+' or `-'.  */
if (cur_token.code == '-' || cur_token.code == '+')
 {
   sign = cur_token.code;
   intel_match_token (cur_token.code);
   if (cur_token.code != T_CONST1)
     {
as_bad (_("Syntax error: Expecting a constant, got `%s'")("Syntax error: Expecting a constant, got `%s'"),
	cur_token.str);
return 0;
     }
 }

save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
strcpy (save_str + !!sign, cur_token.str);
if (sign)
 *save_str = sign;

/* Get the next token to check for register scaling.  */
intel_match_token (cur_token.code);

/* Check if this constant is a scaling factor for an index register.  */
if (cur_token.code == '*')
 {
   if (intel_match_token ('*') && cur_token.code == T_REG2)
     {
const reg_entry *reg = cur_token.reg;

if (!intel_parser.in_bracket)
  {
    as_bad (_("Register scaling only allowed in memory operands")("Register scaling only allowed in memory operands"));
    return 0;
  }

if (reg->reg_type & Reg160x2) /* Disallow things like [1*si]. */
  reg = i386_regtab + REGNAM_AX25 + 4; /* sp is invalid as index */
else if (i.index_reg)
  reg = i386_regtab + REGNAM_EAX41 + 4; /* esp is invalid as index */

/* The constant is followed by `* reg', so it must be
   a valid scale.  */
i.index_reg = reg;
i.types[this_operand] |= BaseIndex0x800;

/* Set the scale after setting the register (otherwise,
   i386_scale will complain)  */
if (!i386_scale (save_str))
  return 0;
intel_match_token (T_REG2);

/* Since registers are not part of the displacement
   string, we may need to remove any preceding '+' from
   the displacement string.  */
if (*intel_parser.disp != '\0')
  {
    char *s = intel_parser.disp;
    s += strlen (s) - 1;
    if (*s == '+')
      *s = '\0';
  }

free (save_str);

return 1;
     }

   /* The constant was not used for register scaling. Since we have
      already consumed the token following `*' we now need to put it
      back in the stream.  */
   intel_putback_token ();
 }

/* Add the constant to the displacement string.  */
strcat (intel_parser.disp, save_str);
free (save_str);

return 1;
    }
  }

as_bad (_("Unrecognized token '%s'")("Unrecognized token '%s'"), cur_token.str);
return 0;
6926}

6928/* Match the given token against cur_token. If they match, read the next
 token from the operand string.  */
6930static int
6931intel_match_token (code)
   int code;
6933{
if (cur_token.code == code)
  {
    intel_get_token ();
    return 1;
  }
else
  {
    as_bad (_("Unexpected token `%s'")("Unexpected token `%s'"), cur_token.str);
    return 0;
  }
6944}

6946/* Read a new token from intel_parser.op_string and store it in cur_token.  */
6947static void
6948intel_get_token ()
6949{
char *end_op;
const reg_entry *reg;
struct intel_token new_token;

new_token.code = T_NIL-1;
new_token.reg = NULL((void*)0);
new_token.str = NULL((void*)0);

/* Free the memory allocated to the previous token and move
   cur_token to prev_token.  */
if (prev_token.str)
  free (prev_token.str);

prev_token = cur_token;

/* Skip whitespace.  */
while (is_space_char (*intel_parser.op_string)((*intel_parser.op_string) == ' '))
  intel_parser.op_string++;

/* Return an empty token if we find nothing else on the line.  */
if (*intel_parser.op_string == '\0')
  {
    cur_token = new_token;
    return;
  }

/* The new token cannot be larger than the remainder of the operand
   string.  */
new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
new_token.str[0] = '\0';

if (strchr ("0123456789", *intel_parser.op_string))
  {
    char *p = new_token.str;
    char *q = intel_parser.op_string;
    new_token.code = T_CONST1;

    /* Allow any kind of identifier char to encompass floating point and
hexadecimal numbers.  */
    while (is_identifier_char (*q)(identifier_chars[(unsigned char) *q]))
*p++ = *q++;
    *p = '\0';

    /* Recognize special symbol names [0-9][bf].  */
    if (strlen (intel_parser.op_string) == 2
 && (intel_parser.op_string[1] == 'b'
     || intel_parser.op_string[1] == 'f'))
new_token.code = T_ID13;
  }

else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL((void*)0))
  {
    size_t len = end_op - intel_parser.op_string;

    new_token.code = T_REG2;
    new_token.reg = reg;

    memcpy (new_token.str, intel_parser.op_string, len);
    new_token.str[len] = '\0';
  }

else if (is_identifier_char (*intel_parser.op_string)(identifier_chars[(unsigned char) *intel_parser.op_string]))
  {
    char *p = new_token.str;
    char *q = intel_parser.op_string;

    /* A '.' or '$' followed by an identifier char is an identifier.
Otherwise, it's operator '.' followed by an expression.  */
    if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))(identifier_chars[(unsigned char) *(q + 1)]))
{
 new_token.code = '.';
 new_token.str[0] = '.';
 new_token.str[1] = '\0';
}
    else
{
 while (is_identifier_char (*q)(identifier_chars[(unsigned char) *q]) || *q == '@')
   *p++ = *q++;
 *p = '\0';

 if (strcasecmp (new_token.str, "NOT") == 0)
   new_token.code = '~';

 else if (strcasecmp (new_token.str, "MOD") == 0)
   new_token.code = '%';

 else if (strcasecmp (new_token.str, "AND") == 0)
   new_token.code = '&';

 else if (strcasecmp (new_token.str, "OR") == 0)
   new_token.code = '|';

 else if (strcasecmp (new_token.str, "XOR") == 0)
   new_token.code = '^';

 else if (strcasecmp (new_token.str, "SHL") == 0)
   new_token.code = T_SHL14;

 else if (strcasecmp (new_token.str, "SHR") == 0)
   new_token.code = T_SHR15;

 else if (strcasecmp (new_token.str, "BYTE") == 0)
   new_token.code = T_BYTE3;

 else if (strcasecmp (new_token.str, "WORD") == 0)
   new_token.code = T_WORD4;

 else if (strcasecmp (new_token.str, "DWORD") == 0)
   new_token.code = T_DWORD5;

 else if (strcasecmp (new_token.str, "FWORD") == 0)
   new_token.code = T_FWORD6;

 else if (strcasecmp (new_token.str, "QWORD") == 0)
   new_token.code = T_QWORD7;

 else if (strcasecmp (new_token.str, "TBYTE") == 0
   /* XXX remove (gcc still uses it) */
   || strcasecmp (new_token.str, "XWORD") == 0)
   new_token.code = T_TBYTE8;

 else if (strcasecmp (new_token.str, "XMMWORD") == 0
   || strcasecmp (new_token.str, "OWORD") == 0)
   new_token.code = T_XMMWORD9;

 else if (strcasecmp (new_token.str, "PTR") == 0)
   new_token.code = T_PTR12;

 else if (strcasecmp (new_token.str, "SHORT") == 0)
   new_token.code = T_SHORT10;

 else if (strcasecmp (new_token.str, "OFFSET") == 0)
   {
     new_token.code = T_OFFSET11;

     /* ??? This is not mentioned in the MASM grammar but gcc
     makes use of it with -mintel-syntax.  OFFSET may be
     followed by FLAT:  */
     if (strncasecmp (q, " FLAT:", 6) == 0)
strcat (new_token.str, " FLAT:");
   }

 /* ??? This is not mentioned in the MASM grammar.  */
 else if (strcasecmp (new_token.str, "FLAT") == 0)
   {
     new_token.code = T_OFFSET11;
     if (*q == ':')
strcat (new_token.str, ":");
     else
as_bad (_("`:' expected")("`:' expected"));
   }

 else
   new_token.code = T_ID13;
}
  }

else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
  {
    new_token.code = *intel_parser.op_string;
    new_token.str[0] = *intel_parser.op_string;
    new_token.str[1] = '\0';
  }

else if (strchr ("<>", *intel_parser.op_string)
  && *intel_parser.op_string == *(intel_parser.op_string + 1))
  {
    new_token.code = *intel_parser.op_string == '<' ? T_SHL14 : T_SHR15;
    new_token.str[0] = *intel_parser.op_string;
    new_token.str[1] = *intel_parser.op_string;
    new_token.str[2] = '\0';
  }

else
  as_bad (_("Unrecognized token `%s'")("Unrecognized token `%s'"), intel_parser.op_string);

intel_parser.op_string += strlen (new_token.str);
cur_token = new_token;
7128}

7130/* Put cur_token back into the token stream and make cur_token point to
 prev_token.  */
7132static void
7133intel_putback_token ()
7134{
if (cur_token.code != T_NIL-1)
  {
    intel_parser.op_string -= strlen (cur_token.str);
    free (cur_token.str);
  }
cur_token = prev_token;

/* Forget prev_token.  */
prev_token.code = T_NIL-1;
prev_token.reg = NULL((void*)0);
prev_token.str = NULL((void*)0);
7146}

7148int
7149tc_x86_regname_to_dw2regnum (const char *regname)
7150{
unsigned int regnum;
unsigned int regnames_count;
static const char *const regnames_32[] =
  {
    "eax", "ecx", "edx", "ebx",
    "esp", "ebp", "esi", "edi",
    "eip", "eflags", NULL((void*)0),
    "st0", "st1", "st2", "st3",
    "st4", "st5", "st6", "st7",
    NULL((void*)0), NULL((void*)0),
    "xmm0", "xmm1", "xmm2", "xmm3",
    "xmm4", "xmm5", "xmm6", "xmm7",
    "mm0", "mm1", "mm2", "mm3",
    "mm4", "mm5", "mm6", "mm7",
    "fcw", "fsw", "mxcsr",
    "es", "cs", "ss", "ds", "fs", "gs", NULL((void*)0), NULL((void*)0),
    "tr", "ldtr"
  };
static const char *const regnames_64[] =
  {
    "rax", "rdx", "rcx", "rbx",
    "rsi", "rdi", "rbp", "rsp",
    "r8",  "r9",  "r10", "r11",
    "r12", "r13", "r14", "r15",
    "rip",
    "xmm0",  "xmm1",  "xmm2",  "xmm3",
    "xmm4",  "xmm5",  "xmm6",  "xmm7",
    "xmm8",  "xmm9",  "xmm10", "xmm11",
    "xmm12", "xmm13", "xmm14", "xmm15",
    "st0", "st1", "st2", "st3",
    "st4", "st5", "st6", "st7",
    "mm0", "mm1", "mm2", "mm3",
    "mm4", "mm5", "mm6", "mm7",
    "rflags",
    "es", "cs", "ss", "ds", "fs", "gs", NULL((void*)0), NULL((void*)0),
    "fs.base", "gs.base", NULL((void*)0), NULL((void*)0),
    "tr", "ldtr",
    "mxcsr", "fcw", "fsw"
  };
const char *const *regnames;

if (flag_code == CODE_64BIT)
  {
    regnames = regnames_64;
    regnames_count = ARRAY_SIZE (regnames_64)(sizeof (regnames_64) / sizeof ((regnames_64)[0]));
  }
else
  {
    regnames = regnames_32;
    regnames_count = ARRAY_SIZE (regnames_32)(sizeof (regnames_32) / sizeof ((regnames_32)[0]));
  }

for (regnum = 0; regnum < regnames_count; regnum++)
  if (regnames[regnum] != NULL((void*)0)
&& strcmp (regname, regnames[regnum]) == 0)
    return regnum;

return -1;
7209}

7211void
7212tc_x86_frame_initial_instructions (void)
7213{
static unsigned int sp_regno;

if (!sp_regno)
  sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
			    ? "rsp" : "esp");

cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7222}

7224int
7225i386_elf_section_type (const char *str, size_t len)
7226{
if (flag_code == CODE_64BIT
    && len == sizeof ("unwind") - 1
    && strncmp (str, "unwind", 6) == 0)
  return SHT_X86_64_UNWIND0x70000001;

return -1;
7233}

7235#ifdef TE_PE
7236void
7237tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7238{
expressionS expr;

expr.X_op = O_secrel;
expr.X_add_symbol = symbol;
expr.X_add_number = 0;
emit_expr (&expr, size);
7245}
7246#endif

7248#if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)
7249/* For ELF on x86-64, add support for SHF_X86_64_LARGE.  */

7251int
7252x86_64_section_letter (int letter, char **ptr_msg)
7253{
if (flag_code == CODE_64BIT)
  {
    if (letter == 'l')
return SHF_X86_64_LARGE0x10000000;

    *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string")("Bad .section directive: want a,l,w,x,M,S,G,T in string");
   }
else
 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string")("Bad .section directive: want a,w,x,M,S,G,T in string");
return -1;
7264}

7266int
7267x86_64_section_word (char *str, size_t len)
7268{
if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
  return SHF_X86_64_LARGE0x10000000;

return -1;
7273}

7275static void
7276handle_large_common (int small ATTRIBUTE_UNUSED__attribute__ ((__unused__)))
7277{
if (flag_code != CODE_64BIT)
  {
    s_comm_internal (0, elf_common_parse);
    as_warn (_(".largecomm supported only in 64bit mode, producing .comm")(".largecomm supported only in 64bit mode, producing .comm"));
  }
else
  {
    static segT lbss_section;
    asection *saved_com_section_ptr = elf_com_section_ptr;
    asection *saved_bss_section = bss_section;

    if (lbss_section == NULL((void*)0))
{
 flagword applicable;
 segT seg = now_seg;
 subsegT subseg = now_subseg;

 /* The .lbss section is for local .largecomm symbols.  */
 lbss_section = subseg_new (".lbss", 0);
 applicable = bfd_applicable_section_flags (stdoutput)((stdoutput)->xvec->section_flags);
 bfd_set_section_flags (stdoutput, lbss_section,
		 applicable & SEC_ALLOC0x001);
 seg_info (lbss_section)->bss = 1;

 subseg_set (seg, subseg);
}

    elf_com_section_ptr = &_bfd_elf_large_com_section;
    bss_section = lbss_section;

    s_comm_internal (0, elf_common_parse);

    elf_com_section_ptr = saved_com_section_ptr;
    bss_section = saved_bss_section;
  }
7313}
7314#endif /* OBJ_ELF || OBJ_MAYBE_ELF */