Bug Summary

File:dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
Warning:line 1460, column 2
Value stored to 'result' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name polaris10_smumgr.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "pp_debug.h"
27#include "smumgr.h"
28#include "smu74.h"
29#include "smu_ucode_xfer_vi.h"
30#include "polaris10_smumgr.h"
31#include "smu74_discrete.h"
32#include "smu/smu_7_1_3_d.h"
33#include "smu/smu_7_1_3_sh_mask.h"
34#include "gmc/gmc_8_1_d.h"
35#include "gmc/gmc_8_1_sh_mask.h"
36#include "oss/oss_3_0_d.h"
37#include "gca/gfx_8_0_d.h"
38#include "bif/bif_5_0_d.h"
39#include "bif/bif_5_0_sh_mask.h"
40#include "ppatomctrl.h"
41#include "cgs_common.h"
42#include "smu7_ppsmc.h"
43#include "smu7_smumgr.h"
44
45#include "smu7_dyn_defaults.h"
46
47#include "smu7_hwmgr.h"
48#include "hardwaremanager.h"
49#include "atombios.h"
50#include "pppcielanes.h"
51
52#include "dce/dce_10_0_d.h"
53#include "dce/dce_10_0_sh_mask.h"
54
55#define POLARIS10_SMC_SIZE0x20000 0x20000
56#define POWERTUNE_DEFAULT_SET_MAX1 1
57#define VDDC_VDDCI_DELTA200 200
58#define MC_CG_ARB_FREQ_F10x0b 0x0b
59
60static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX1] = {
61 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
62 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
65 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
66};
67
68static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE8] = {
69 {VCO_2_43, POSTDIV_DIV_BY_164, 75, 160, 112},
70 {VCO_3_61, POSTDIV_DIV_BY_164, 112, 224, 160},
71 {VCO_2_43, POSTDIV_DIV_BY_83, 75, 160, 112},
72 {VCO_3_61, POSTDIV_DIV_BY_83, 112, 224, 160},
73 {VCO_2_43, POSTDIV_DIV_BY_42, 75, 160, 112},
74 {VCO_3_61, POSTDIV_DIV_BY_42, 112, 216, 160},
75 {VCO_2_43, POSTDIV_DIV_BY_21, 75, 160, 108},
76 {VCO_3_61, POSTDIV_DIV_BY_21, 112, 216, 160} };
77
78#define PPPOLARIS10_TARGETACTIVITY_DFLT50 50
79
80static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
81 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
82 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
83 { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
84 { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
85 { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
86 { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
87 { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
88 { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
89 { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
90 { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
91};
92
93static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
94 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
95
96static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
97{
98 int result = 0;
99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
100
101 if (0 != smu_data->avfs_btc_param) {
102 if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc((uint16_t) 0x26C), smu_data->avfs_btc_param,
103 NULL((void *)0))) {
104 pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed")do { } while(0);
105 result = -1;
106 }
107 }
108 if (smu_data->avfs_btc_param > 1) {
109 /* Soft-Reset to reset the engine before loading uCode */
110 /* halt */
111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000)(((struct cgs_device *)hwmgr->device)->ops->write_register
(hwmgr->device,0x208d,0x50000000))
;
112 /* reset everything */
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff)(((struct cgs_device *)hwmgr->device)->ops->write_register
(hwmgr->device,0x2008,0xffffffff))
;
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0)(((struct cgs_device *)hwmgr->device)->ops->write_register
(hwmgr->device,0x2008,0))
;
115 }
116 return result;
117}
118
119
120static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
121{
122 uint32_t vr_config;
123 uint32_t dpm_table_start;
124
125 uint16_t u16_boot_mvdd;
126 uint32_t graphics_level_address, vr_config_address, graphics_level_size;
127
128 graphics_level_size = sizeof(avfs_graphics_level_polaris10);
129 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE)(__uint16_t)(__builtin_constant_p(1300 * 4) ? (__uint16_t)(((
__uint16_t)(1300 * 4) & 0xffU) << 8 | ((__uint16_t)
(1300 * 4) & 0xff00U) >> 8) : __swap16md(1300 * 4))
;
130
131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,do { if (!(0 == smu7_read_smc_sram_dword(hwmgr, 0x20000 + __builtin_offsetof
(SMU74_Firmware_Header, DpmTable), &dpm_table_start, 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table"
); return -1; } } while (0)
132 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),do { if (!(0 == smu7_read_smc_sram_dword(hwmgr, 0x20000 + __builtin_offsetof
(SMU74_Firmware_Header, DpmTable), &dpm_table_start, 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table"
); return -1; } } while (0)
133 &dpm_table_start, 0x40000),do { if (!(0 == smu7_read_smc_sram_dword(hwmgr, 0x20000 + __builtin_offsetof
(SMU74_Firmware_Header, DpmTable), &dpm_table_start, 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table"
); return -1; } } while (0)
134 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",do { if (!(0 == smu7_read_smc_sram_dword(hwmgr, 0x20000 + __builtin_offsetof
(SMU74_Firmware_Header, DpmTable), &dpm_table_start, 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table"
); return -1; } } while (0)
135 return -1)do { if (!(0 == smu7_read_smc_sram_dword(hwmgr, 0x20000 + __builtin_offsetof
(SMU74_Firmware_Header, DpmTable), &dpm_table_start, 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table"
); return -1; } } while (0)
;
136
137 /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
138 vr_config = 0x01000500; /* Real value:0x50001 */
139
140 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig)__builtin_offsetof(SMU74_Discrete_DpmTable, VRConfig);
141
142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address
, (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000))) { printk
("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC"
); return -1; } } while (0)
143 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address
, (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000))) { printk
("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC"
); return -1; } } while (0)
144 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address
, (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000))) { printk
("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC"
); return -1; } } while (0)
145 return -1)do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address
, (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000))) { printk
("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC"
); return -1; } } while (0)
;
146
147 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
148
149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_graphics_level_polaris10), graphics_level_size
, 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!"
); return -1; } } while (0)
150 (uint8_t *)(&avfs_graphics_level_polaris10),do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_graphics_level_polaris10), graphics_level_size
, 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!"
); return -1; } } while (0)
151 graphics_level_size, 0x40000),do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_graphics_level_polaris10), graphics_level_size
, 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!"
); return -1; } } while (0)
152 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_graphics_level_polaris10), graphics_level_size
, 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!"
); return -1; } } while (0)
153 return -1)do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_graphics_level_polaris10), graphics_level_size
, 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!"
); return -1; } } while (0)
;
154
155 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
156
157 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10
), 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!"
); return -1; } } while (0)
158 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10
), 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!"
); return -1; } } while (0)
159 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10
), 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!"
); return -1; } } while (0)
160 return -1)do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10
), 0x40000))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!"
); return -1; } } while (0)
;
161
162 /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
163
164 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd)__builtin_offsetof(SMU74_Discrete_DpmTable, BootMVdd);
165
166 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!"
); return -1; } } while (0)
167 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!"
); return -1; } } while (0)
168 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!"
); return -1; } } while (0)
169 return -1)do { if (!(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address
, (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!"
); return -1; } } while (0)
;
170
171 return 0;
172}
173
174
175static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
176{
177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
178
179 if (!hwmgr->avfs_supported)
180 return 0;
181
182 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),do { if (!(0 == polaris10_setup_graphics_level_structure(hwmgr
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU"
); return -22; } } while (0)
183 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",do { if (!(0 == polaris10_setup_graphics_level_structure(hwmgr
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU"
); return -22; } } while (0)
184 return -EINVAL)do { if (!(0 == polaris10_setup_graphics_level_structure(hwmgr
))) { printk("\0014" "amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU"
); return -22; } } while (0)
;
185
186 if (smu_data->avfs_btc_param > 1) {
187 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.")do { } while(0);
188 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),do { if (!(0 == smu7_setup_pwr_virus(hwmgr))) { printk("\0014"
"amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS "
); return -22; } } while (0)
189 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",do { if (!(0 == smu7_setup_pwr_virus(hwmgr))) { printk("\0014"
"amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS "
); return -22; } } while (0)
190 return -EINVAL)do { if (!(0 == smu7_setup_pwr_virus(hwmgr))) { printk("\0014"
"amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS "
); return -22; } } while (0)
;
191 }
192
193 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),do { if (!(0 == polaris10_perform_btc(hwmgr))) { printk("\0014"
"amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled"
); return -22; } } while (0)
194 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",do { if (!(0 == polaris10_perform_btc(hwmgr))) { printk("\0014"
"amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled"
); return -22; } } while (0)
195 return -EINVAL)do { if (!(0 == polaris10_perform_btc(hwmgr))) { printk("\0014"
"amdgpu: " "%s\n", "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled"
); return -22; } } while (0)
;
196
197 return 0;
198}
199
200static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
201{
202 int result = 0;
203
204 /* Wait for smc boot up */
205 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
206
207 /* Assert reset */
208 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((1) << 0x0)))))
209 SMC_SYSCON_RESET_CNTL, rst_reg, 1)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((1) << 0x0)))))
;
210
211 result = smu7_upload_smu_firmware_image(hwmgr);
212 if (result != 0)
213 return result;
214
215 /* Clear status */
216 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xe0003088,0))
;
217
218 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000004,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000004))) & ~0x1) | (0x1 &
((0) << 0x0)))))
219 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000004,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000004))) & ~0x1) | (0x1 &
((0) << 0x0)))))
;
220
221 /* De-assert reset */
222 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((0) << 0x0)))))
223 SMC_SYSCON_RESET_CNTL, rst_reg, 0)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((0) << 0x0)))))
;
224
225
226 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1)phm_wait_on_indirect_register(hwmgr, 0x1AC, 0xc0000004, (1) <<
0x10, 0x10000)
;
227
228
229 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
230 smu7_send_msg_to_smc_offset(hwmgr);
231
232 /* Wait done bit to be set */
233 /* Check pass/failed indicator */
234
235 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0)phm_wait_for_indirect_register_unequal(hwmgr, 0x1AC, 0xe0003088
, (0) << 0x0, 0x1)
;
236
237 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xe0003088))) & 0x2) >>
0x1)
238 SMU_STATUS, SMU_PASS)((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xe0003088))) & 0x2) >>
0x1)
)
239 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "SMU Firmware start failed!"
); return -1; } } while (0)
;
240
241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x3f000,0))
;
242
243 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((1) << 0x0)))))
244 SMC_SYSCON_RESET_CNTL, rst_reg, 1)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((1) << 0x0)))))
;
245
246 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((0) << 0x0)))))
247 SMC_SYSCON_RESET_CNTL, rst_reg, 0)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((0) << 0x0)))))
;
248
249 /* Wait for firmware to initialize */
250 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1)phm_wait_on_indirect_register(hwmgr, 0x1AC, 0x3f000, (1) <<
0x0, 0x1)
;
251
252 return result;
253}
254
255static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
256{
257 int result = 0;
258
259 /* wait for smc boot up */
260 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0)phm_wait_for_indirect_register_unequal(hwmgr, 0x1AC, 0xc0000004
, (0) << 0x7, 0x80)
;
261
262 /* Clear firmware interrupt enable flag */
263 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
264 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x3f000,0))
265 ixFIRMWARE_FLAGS, 0)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x3f000,0))
;
266
267 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((1) << 0x0)))))
268 SMC_SYSCON_RESET_CNTL,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((1) << 0x0)))))
269 rst_reg, 1)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((1) << 0x0)))))
;
270
271 result = smu7_upload_smu_firmware_image(hwmgr);
272 if (result != 0)
273 return result;
274
275 /* Set smc instruct start point at 0x0 */
276 smu7_program_jump_on_start(hwmgr);
277
278 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000004,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000004))) & ~0x1) | (0x1 &
((0) << 0x0)))))
279 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000004,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000004))) & ~0x1) | (0x1 &
((0) << 0x0)))))
;
280
281 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((0) << 0x0)))))
282 SMC_SYSCON_RESET_CNTL, rst_reg, 0)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x80000000,((((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,0x80000000))) & ~0x1) | (0x1 &
((0) << 0x0)))))
;
283
284 /* Wait for firmware to initialize */
285
286 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,phm_wait_on_indirect_register(hwmgr, 0x1AC, 0x3f000, (1) <<
0x0, 0x1)
287 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1)phm_wait_on_indirect_register(hwmgr, 0x1AC, 0x3f000, (1) <<
0x0, 0x1)
;
288
289 return result;
290}
291
292static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
293{
294 int result = 0;
295 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
296
297 /* Only start SMC if SMC RAM is not running */
298 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
299 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xe00030a4))) & 0x10000
) >> 0x10)
);
300 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xe00030a4))) & 0x20000
) >> 0x11)
);
301
302 /* Check if SMU is running in protected mode */
303 if (smu_data->protected_mode == 0)
304 result = polaris10_start_smu_in_non_protection_mode(hwmgr);
305 else
306 result = polaris10_start_smu_in_protection_mode(hwmgr);
307
308 if (result != 0)
309 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Failed to load SMU ucode."
); return result; } } while (0)
;
310
311 polaris10_avfs_event_mgr(hwmgr);
312 }
313
314 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
315 smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION0x20000 + offsetof(SMU74_Firmware_Header, SoftRegisters)__builtin_offsetof(SMU74_Firmware_Header, SoftRegisters),
316 &(smu_data->smu7_data.soft_regs_start), 0x40000);
317
318 result = smu7_request_smu_load_fw(hwmgr);
319
320 return result;
321}
322
323static bool_Bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
324{
325 uint32_t efuse;
326
327 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4))(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0100000 + (49*4)))
;
328 efuse &= 0x00000001;
329 if (efuse)
330 return true1;
331
332 return false0;
333}
334
335static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
336{
337 struct polaris10_smumgr *smu_data;
338
339 smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL(0x0001 | 0x0004));
340 if (smu_data == NULL((void *)0))
341 return -ENOMEM12;
342
343 hwmgr->smu_backend = smu_data;
344
345 if (smu7_init(hwmgr)) {
346 kfree(smu_data);
347 return -EINVAL22;
348 }
349
350 return 0;
351}
352
353static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
354 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
355 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
356{
357 uint32_t i;
358 uint16_t vddci;
359 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
360
361 *voltage = *mvdd = 0;
362
363 /* clock - voltage dependency table is empty table */
364 if (dep_table->count == 0)
365 return -EINVAL22;
366
367 for (i = 0; i < dep_table->count; i++) {
368 /* find first sclk bigger than request */
369 if (dep_table->entries[i].clk >= clock) {
370 *voltage |= (dep_table->entries[i].vddc *
371 VOLTAGE_SCALE4) << VDDC_SHIFT0;
372 if (SMU7_VOLTAGE_CONTROL_NONE0x0 == data->vddci_control)
373 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
374 VOLTAGE_SCALE4) << VDDCI_SHIFT15;
375 else if (dep_table->entries[i].vddci)
376 *voltage |= (dep_table->entries[i].vddci *
377 VOLTAGE_SCALE4) << VDDCI_SHIFT15;
378 else {
379 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
380 (dep_table->entries[i].vddc -
381 (uint16_t)VDDC_VDDCI_DELTA200));
382 *voltage |= (vddci * VOLTAGE_SCALE4) << VDDCI_SHIFT15;
383 }
384
385 if (SMU7_VOLTAGE_CONTROL_NONE0x0 == data->mvdd_control)
386 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
387 VOLTAGE_SCALE4;
388 else if (dep_table->entries[i].mvdd)
389 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
390 VOLTAGE_SCALE4;
391
392 *voltage |= 1 << PHASES_SHIFT30;
393 return 0;
394 }
395 }
396
397 /* sclk is bigger than max sclk in the dependence table */
398 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE4) << VDDC_SHIFT0;
399
400 if (SMU7_VOLTAGE_CONTROL_NONE0x0 == data->vddci_control)
401 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
402 VOLTAGE_SCALE4) << VDDCI_SHIFT15;
403 else if (dep_table->entries[i-1].vddci) {
404 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
405 (dep_table->entries[i].vddc -
406 (uint16_t)VDDC_VDDCI_DELTA200));
407 *voltage |= (vddci * VOLTAGE_SCALE4) << VDDCI_SHIFT15;
408 }
409
410 if (SMU7_VOLTAGE_CONTROL_NONE0x0 == data->mvdd_control)
411 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE4;
412 else if (dep_table->entries[i].mvdd)
413 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE4;
414
415 return 0;
416}
417
418static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
419{
420 uint32_t tmp;
421 tmp = raw_setting * 4096 / 100;
422 return (uint16_t)tmp;
423}
424
425static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
426{
427 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
428
429 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
430 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
431 struct phm_ppt_v1_information *table_info =
432 (struct phm_ppt_v1_information *)(hwmgr->pptable);
433 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
434 struct pp_advance_fan_control_parameters *fan_table =
435 &hwmgr->thermal_controller.advanceFanControlParameters;
436 int i, j, k;
437 const uint16_t *pdef1;
438 const uint16_t *pdef2;
439
440 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128))(__uint16_t)(__builtin_constant_p((uint16_t)(cac_dtp_table->
usTDP * 128)) ? (__uint16_t)(((__uint16_t)((uint16_t)(cac_dtp_table
->usTDP * 128)) & 0xffU) << 8 | ((__uint16_t)((uint16_t
)(cac_dtp_table->usTDP * 128)) & 0xff00U) >> 8) :
__swap16md((uint16_t)(cac_dtp_table->usTDP * 128)))
;
441 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128))(__uint16_t)(__builtin_constant_p((uint16_t)(cac_dtp_table->
usTDP * 128)) ? (__uint16_t)(((__uint16_t)((uint16_t)(cac_dtp_table
->usTDP * 128)) & 0xffU) << 8 | ((__uint16_t)((uint16_t
)(cac_dtp_table->usTDP * 128)) & 0xff00U) >> 8) :
__swap16md((uint16_t)(cac_dtp_table->usTDP * 128)))
;
442
443 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,do { if (!(cac_dtp_table->usTargetOperatingTemp <= 255)
) { printk("\0014" "amdgpu: " "%s\n", "Target Operating Temp is out of Range!"
); ; } } while (0)
444 "Target Operating Temp is out of Range!",do { if (!(cac_dtp_table->usTargetOperatingTemp <= 255)
) { printk("\0014" "amdgpu: " "%s\n", "Target Operating Temp is out of Range!"
); ; } } while (0)
445 )do { if (!(cac_dtp_table->usTargetOperatingTemp <= 255)
) { printk("\0014" "amdgpu: " "%s\n", "Target Operating Temp is out of Range!"
); ; } } while (0)
;
446
447 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US((__uint16_t)(__builtin_constant_p(cac_dtp_table->usTargetOperatingTemp
* 256) ? (__uint16_t)(((__uint16_t)(cac_dtp_table->usTargetOperatingTemp
* 256) & 0xffU) << 8 | ((__uint16_t)(cac_dtp_table
->usTargetOperatingTemp * 256) & 0xff00U) >> 8) :
__swap16md(cac_dtp_table->usTargetOperatingTemp * 256))
448 cac_dtp_table->usTargetOperatingTemp * 256)(__uint16_t)(__builtin_constant_p(cac_dtp_table->usTargetOperatingTemp
* 256) ? (__uint16_t)(((__uint16_t)(cac_dtp_table->usTargetOperatingTemp
* 256) & 0xffU) << 8 | ((__uint16_t)(cac_dtp_table
->usTargetOperatingTemp * 256) & 0xff00U) >> 8) :
__swap16md(cac_dtp_table->usTargetOperatingTemp * 256))
;
449 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US((__uint16_t)(__builtin_constant_p(cac_dtp_table->usTemperatureLimitHotspot
* 256) ? (__uint16_t)(((__uint16_t)(cac_dtp_table->usTemperatureLimitHotspot
* 256) & 0xffU) << 8 | ((__uint16_t)(cac_dtp_table
->usTemperatureLimitHotspot * 256) & 0xff00U) >>
8) : __swap16md(cac_dtp_table->usTemperatureLimitHotspot *
256))
450 cac_dtp_table->usTemperatureLimitHotspot * 256)(__uint16_t)(__builtin_constant_p(cac_dtp_table->usTemperatureLimitHotspot
* 256) ? (__uint16_t)(((__uint16_t)(cac_dtp_table->usTemperatureLimitHotspot
* 256) & 0xffU) << 8 | ((__uint16_t)(cac_dtp_table
->usTemperatureLimitHotspot * 256) & 0xff00U) >>
8) : __swap16md(cac_dtp_table->usTemperatureLimitHotspot *
256))
;
451 table->FanGainEdge = PP_HOST_TO_SMC_US((__uint16_t)(__builtin_constant_p(scale_fan_gain_settings(fan_table
->usFanGainEdge)) ? (__uint16_t)(((__uint16_t)(scale_fan_gain_settings
(fan_table->usFanGainEdge)) & 0xffU) << 8 | ((__uint16_t
)(scale_fan_gain_settings(fan_table->usFanGainEdge)) &
0xff00U) >> 8) : __swap16md(scale_fan_gain_settings(fan_table
->usFanGainEdge)))
452 scale_fan_gain_settings(fan_table->usFanGainEdge))(__uint16_t)(__builtin_constant_p(scale_fan_gain_settings(fan_table
->usFanGainEdge)) ? (__uint16_t)(((__uint16_t)(scale_fan_gain_settings
(fan_table->usFanGainEdge)) & 0xffU) << 8 | ((__uint16_t
)(scale_fan_gain_settings(fan_table->usFanGainEdge)) &
0xff00U) >> 8) : __swap16md(scale_fan_gain_settings(fan_table
->usFanGainEdge)))
;
453 table->FanGainHotspot = PP_HOST_TO_SMC_US((__uint16_t)(__builtin_constant_p(scale_fan_gain_settings(fan_table
->usFanGainHotspot)) ? (__uint16_t)(((__uint16_t)(scale_fan_gain_settings
(fan_table->usFanGainHotspot)) & 0xffU) << 8 | (
(__uint16_t)(scale_fan_gain_settings(fan_table->usFanGainHotspot
)) & 0xff00U) >> 8) : __swap16md(scale_fan_gain_settings
(fan_table->usFanGainHotspot)))
454 scale_fan_gain_settings(fan_table->usFanGainHotspot))(__uint16_t)(__builtin_constant_p(scale_fan_gain_settings(fan_table
->usFanGainHotspot)) ? (__uint16_t)(((__uint16_t)(scale_fan_gain_settings
(fan_table->usFanGainHotspot)) & 0xffU) << 8 | (
(__uint16_t)(scale_fan_gain_settings(fan_table->usFanGainHotspot
)) & 0xff00U) >> 8) : __swap16md(scale_fan_gain_settings
(fan_table->usFanGainHotspot)))
;
455
456 pdef1 = defaults->BAPMTI_R;
457 pdef2 = defaults->BAPMTI_RC;
458
459 for (i = 0; i < SMU74_DTE_ITERATIONS5; i++) {
460 for (j = 0; j < SMU74_DTE_SOURCES3; j++) {
461 for (k = 0; k < SMU74_DTE_SINKS1; k++) {
462 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1)(__uint16_t)(__builtin_constant_p(*pdef1) ? (__uint16_t)(((__uint16_t
)(*pdef1) & 0xffU) << 8 | ((__uint16_t)(*pdef1) &
0xff00U) >> 8) : __swap16md(*pdef1))
;
463 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2)(__uint16_t)(__builtin_constant_p(*pdef2) ? (__uint16_t)(((__uint16_t
)(*pdef2) & 0xffU) << 8 | ((__uint16_t)(*pdef2) &
0xff00U) >> 8) : __swap16md(*pdef2))
;
464 pdef1++;
465 pdef2++;
466 }
467 }
468 }
469
470 return 0;
471}
472
473static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
474{
475 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
476 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
477
478 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
479 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
480 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
481 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
482
483 return 0;
484}
485
486static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
487{
488 uint16_t tdc_limit;
489 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
490 struct phm_ppt_v1_information *table_info =
491 (struct phm_ppt_v1_information *)(hwmgr->pptable);
492 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
493
494 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
495 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
496 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit)((tdc_limit) = (__uint16_t)(__builtin_constant_p(tdc_limit) ?
(__uint16_t)(((__uint16_t)(tdc_limit) & 0xffU) << 8
| ((__uint16_t)(tdc_limit) & 0xff00U) >> 8) : __swap16md
(tdc_limit)))
;
497 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
498 defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
499 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
500
501 return 0;
502}
503
504static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
505{
506 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
507 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
508 uint32_t temp;
509
510 if (smu7_read_smc_sram_dword(hwmgr,
511 fuse_table_offset +
512 offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl)__builtin_offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
513 (uint32_t *)&temp, SMC_RAM_END0x40000))
514 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!"
); return -22; } } while (0)
515 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!"
); return -22; } } while (0)
516 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!"
); return -22; } } while (0)
;
517 else {
518 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
519 smu_data->power_tune_table.LPMLTemperatureMin =
520 (uint8_t)((temp >> 16) & 0xff);
521 smu_data->power_tune_table.LPMLTemperatureMax =
522 (uint8_t)((temp >> 8) & 0xff);
523 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
524 }
525 return 0;
526}
527
528static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
529{
530 int i;
531 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
532
533 /* Currently not used. Set all to zero. */
534 for (i = 0; i < 16; i++)
535 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
536
537 return 0;
538}
539
540static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
541{
542 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
543
544/* TO DO move to hwmgr */
545 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
546 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
547 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
548 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
549
550 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US((__uint16_t)(__builtin_constant_p(hwmgr->thermal_controller
.advanceFanControlParameters.usFanOutputSensitivity) ? (__uint16_t
)(((__uint16_t)(hwmgr->thermal_controller.advanceFanControlParameters
.usFanOutputSensitivity) & 0xffU) << 8 | ((__uint16_t
)(hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
) & 0xff00U) >> 8) : __swap16md(hwmgr->thermal_controller
.advanceFanControlParameters.usFanOutputSensitivity))
551 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)(__uint16_t)(__builtin_constant_p(hwmgr->thermal_controller
.advanceFanControlParameters.usFanOutputSensitivity) ? (__uint16_t
)(((__uint16_t)(hwmgr->thermal_controller.advanceFanControlParameters
.usFanOutputSensitivity) & 0xffU) << 8 | ((__uint16_t
)(hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
) & 0xff00U) >> 8) : __swap16md(hwmgr->thermal_controller
.advanceFanControlParameters.usFanOutputSensitivity))
;
552 return 0;
553}
554
555static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
556{
557 int i;
558 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
559
560 /* Currently not used. Set all to zero. */
561 for (i = 0; i < 16; i++)
562 smu_data->power_tune_table.GnbLPML[i] = 0;
563
564 return 0;
565}
566
567static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
568{
569 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
570 struct phm_ppt_v1_information *table_info =
571 (struct phm_ppt_v1_information *)(hwmgr->pptable);
572 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
573 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
574 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
575
576 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
577 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
578
579 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
580 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd)((hi_sidd) = (__uint16_t)(__builtin_constant_p(hi_sidd) ? (__uint16_t
)(((__uint16_t)(hi_sidd) & 0xffU) << 8 | ((__uint16_t
)(hi_sidd) & 0xff00U) >> 8) : __swap16md(hi_sidd)))
;
581 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
582 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd)((lo_sidd) = (__uint16_t)(__builtin_constant_p(lo_sidd) ? (__uint16_t
)(((__uint16_t)(lo_sidd) & 0xffU) << 8 | ((__uint16_t
)(lo_sidd) & 0xff00U) >> 8) : __swap16md(lo_sidd)))
;
583
584 return 0;
585}
586
587static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
588{
589 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
590 uint32_t pm_fuse_table_offset;
591
592 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
593 PHM_PlatformCaps_PowerContainment)) {
594 if (smu7_read_smc_sram_dword(hwmgr,
595 SMU7_FIRMWARE_HEADER_LOCATION0x20000 +
596 offsetof(SMU74_Firmware_Header, PmFuseTable)__builtin_offsetof(SMU74_Firmware_Header, PmFuseTable),
597 &pm_fuse_table_offset, SMC_RAM_END0x40000))
598 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to get pm_fuse_table_offset Failed!"
); return -22; } } while (0)
599 "Attempt to get pm_fuse_table_offset Failed!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to get pm_fuse_table_offset Failed!"
); return -22; } } while (0)
600 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to get pm_fuse_table_offset Failed!"
); return -22; } } while (0)
;
601
602 if (polaris10_populate_svi_load_line(hwmgr))
603 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate SviLoadLine Failed!"
); return -22; } } while (0)
604 "Attempt to populate SviLoadLine Failed!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate SviLoadLine Failed!"
); return -22; } } while (0)
605 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate SviLoadLine Failed!"
); return -22; } } while (0)
;
606
607 if (polaris10_populate_tdc_limit(hwmgr))
608 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate TDCLimit Failed!"
); return -22; } } while (0)
609 "Attempt to populate TDCLimit Failed!", return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate TDCLimit Failed!"
); return -22; } } while (0)
;
610
611 if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
612 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate TdcWaterfallCtl, "
"LPMLTemperature Min and Max Failed!"); return -22; } } while
(0)
613 "Attempt to populate TdcWaterfallCtl, "do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate TdcWaterfallCtl, "
"LPMLTemperature Min and Max Failed!"); return -22; } } while
(0)
614 "LPMLTemperature Min and Max Failed!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate TdcWaterfallCtl, "
"LPMLTemperature Min and Max Failed!"); return -22; } } while
(0)
615 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate TdcWaterfallCtl, "
"LPMLTemperature Min and Max Failed!"); return -22; } } while
(0)
;
616
617 if (0 != polaris10_populate_temperature_scaler(hwmgr))
618 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate LPMLTemperatureScaler Failed!"
); return -22; } } while (0)
619 "Attempt to populate LPMLTemperatureScaler Failed!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate LPMLTemperatureScaler Failed!"
); return -22; } } while (0)
620 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate LPMLTemperatureScaler Failed!"
); return -22; } } while (0)
;
621
622 if (polaris10_populate_fuzzy_fan(hwmgr))
623 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate Fuzzy Fan Control parameters Failed!"
); return -22; } } while (0)
624 "Attempt to populate Fuzzy Fan Control parameters Failed!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate Fuzzy Fan Control parameters Failed!"
); return -22; } } while (0)
625 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate Fuzzy Fan Control parameters Failed!"
); return -22; } } while (0)
;
626
627 if (polaris10_populate_gnb_lpml(hwmgr))
628 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate GnbLPML Failed!"
); return -22; } } while (0)
629 "Attempt to populate GnbLPML Failed!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate GnbLPML Failed!"
); return -22; } } while (0)
630 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate GnbLPML Failed!"
); return -22; } } while (0)
;
631
632 if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
633 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
"Sidd Failed!"); return -22; } } while (0)
634 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
"Sidd Failed!"); return -22; } } while (0)
635 "Sidd Failed!", return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
"Sidd Failed!"); return -22; } } while (0)
;
636
637 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
638 (uint8_t *)&smu_data->power_tune_table,
639 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END0x40000))
640 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to download PmFuseTable Failed!"
); return -22; } } while (0)
641 "Attempt to download PmFuseTable Failed!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to download PmFuseTable Failed!"
); return -22; } } while (0)
642 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Attempt to download PmFuseTable Failed!"
); return -22; } } while (0)
;
643 }
644 return 0;
645}
646
647static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
648 SMU74_Discrete_DpmTable *table)
649{
650 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
651 uint32_t count, level;
652
653 if (SMU7_VOLTAGE_CONTROL_BY_GPIO0x1 == data->mvdd_control) {
654 count = data->mvdd_voltage_table.count;
655 if (count > SMU_MAX_SMIO_LEVELS4)
656 count = SMU_MAX_SMIO_LEVELS4;
657 for (level = 0; level < count; level++) {
658 table->SmioTable2.Pattern[level].Voltage =
659 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE)(__uint16_t)(__builtin_constant_p(data->mvdd_voltage_table
.entries[level].value * 4) ? (__uint16_t)(((__uint16_t)(data->
mvdd_voltage_table.entries[level].value * 4) & 0xffU) <<
8 | ((__uint16_t)(data->mvdd_voltage_table.entries[level]
.value * 4) & 0xff00U) >> 8) : __swap16md(data->
mvdd_voltage_table.entries[level].value * 4))
;
660 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
661 table->SmioTable2.Pattern[level].Smio =
662 (uint8_t) level;
663 table->Smio[level] |=
664 data->mvdd_voltage_table.entries[level].smio_low;
665 }
666 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
667
668 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count)(__uint32_t)(__builtin_constant_p(count) ? (__uint32_t)(((__uint32_t
)(count) & 0xff) << 24 | ((__uint32_t)(count) &
0xff00) << 8 | ((__uint32_t)(count) & 0xff0000) >>
8 | ((__uint32_t)(count) & 0xff000000) >> 24) : __swap32md
(count))
;
669 }
670
671 return 0;
672}
673
674static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
675 struct SMU74_Discrete_DpmTable *table)
676{
677 uint32_t count, level;
678 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
679
680 count = data->vddci_voltage_table.count;
681
682 if (SMU7_VOLTAGE_CONTROL_BY_GPIO0x1 == data->vddci_control) {
683 if (count > SMU_MAX_SMIO_LEVELS4)
684 count = SMU_MAX_SMIO_LEVELS4;
685 for (level = 0; level < count; ++level) {
686 table->SmioTable1.Pattern[level].Voltage =
687 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE)(__uint16_t)(__builtin_constant_p(data->vddci_voltage_table
.entries[level].value * 4) ? (__uint16_t)(((__uint16_t)(data->
vddci_voltage_table.entries[level].value * 4) & 0xffU) <<
8 | ((__uint16_t)(data->vddci_voltage_table.entries[level
].value * 4) & 0xff00U) >> 8) : __swap16md(data->
vddci_voltage_table.entries[level].value * 4))
;
688 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
689
690 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
691 }
692 }
693
694 table->SmioMask1 = data->vddci_voltage_table.mask_low;
695
696 return 0;
697}
698
699static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
700 struct SMU74_Discrete_DpmTable *table)
701{
702 uint32_t count;
703 uint8_t index;
704 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
705 struct phm_ppt_v1_information *table_info =
706 (struct phm_ppt_v1_information *)(hwmgr->pptable);
707 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
708 table_info->vddc_lookup_table;
709 /* tables is already swapped, so in order to use the value from it,
710 * we need to swap it back.
711 * We are populating vddc CAC data to BapmVddc table
712 * in split and merged mode
713 */
714 for (count = 0; count < lookup_table->count; count++) {
715 index = phm_get_voltage_index(lookup_table,
716 data->vddc_voltage_table.entries[count].value);
717 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
718 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
719 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
720 }
721
722 return 0;
723}
724
725static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
726 struct SMU74_Discrete_DpmTable *table)
727{
728 polaris10_populate_smc_vddci_table(hwmgr, table);
729 polaris10_populate_smc_mvdd_table(hwmgr, table);
730 polaris10_populate_cac_table(hwmgr, table);
731
732 return 0;
733}
734
735static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
736 struct SMU74_Discrete_Ulv *state)
737{
738 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
739 struct phm_ppt_v1_information *table_info =
740 (struct phm_ppt_v1_information *)(hwmgr->pptable);
741
742 state->CcPwrDynRm = 0;
743 state->CcPwrDynRm1 = 0;
744
745 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
746 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
747 VOLTAGE_VID_OFFSET_SCALE2100 / VOLTAGE_VID_OFFSET_SCALE1625);
748
749 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
750 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
751 else
752 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
753
754 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm)((state->CcPwrDynRm) = (__uint32_t)(__builtin_constant_p(state
->CcPwrDynRm) ? (__uint32_t)(((__uint32_t)(state->CcPwrDynRm
) & 0xff) << 24 | ((__uint32_t)(state->CcPwrDynRm
) & 0xff00) << 8 | ((__uint32_t)(state->CcPwrDynRm
) & 0xff0000) >> 8 | ((__uint32_t)(state->CcPwrDynRm
) & 0xff000000) >> 24) : __swap32md(state->CcPwrDynRm
)))
;
755 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1)((state->CcPwrDynRm1) = (__uint32_t)(__builtin_constant_p(
state->CcPwrDynRm1) ? (__uint32_t)(((__uint32_t)(state->
CcPwrDynRm1) & 0xff) << 24 | ((__uint32_t)(state->
CcPwrDynRm1) & 0xff00) << 8 | ((__uint32_t)(state->
CcPwrDynRm1) & 0xff0000) >> 8 | ((__uint32_t)(state
->CcPwrDynRm1) & 0xff000000) >> 24) : __swap32md
(state->CcPwrDynRm1)))
;
756 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset)((state->VddcOffset) = (__uint16_t)(__builtin_constant_p(state
->VddcOffset) ? (__uint16_t)(((__uint16_t)(state->VddcOffset
) & 0xffU) << 8 | ((__uint16_t)(state->VddcOffset
) & 0xff00U) >> 8) : __swap16md(state->VddcOffset
)))
;
757
758 return 0;
759}
760
761static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
762 struct SMU74_Discrete_DpmTable *table)
763{
764 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
765}
766
767static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
768 struct SMU74_Discrete_DpmTable *table)
769{
770 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
771 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
772 struct smu7_dpm_table *dpm_table = &data->dpm_table;
773 int i;
774
775 /* Index (dpm_table->pcie_speed_table.count)
776 * is reserved for PCIE boot level. */
777 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
778 table->LinkLevel[i].PcieGenSpeed =
779 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
780 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
781 dpm_table->pcie_speed_table.dpm_levels[i].param1);
782 table->LinkLevel[i].EnabledForActivity = 1;
783 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
784 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5)(__uint32_t)(__builtin_constant_p(5) ? (__uint32_t)(((__uint32_t
)(5) & 0xff) << 24 | ((__uint32_t)(5) & 0xff00)
<< 8 | ((__uint32_t)(5) & 0xff0000) >> 8 | (
(__uint32_t)(5) & 0xff000000) >> 24) : __swap32md(5
))
;
785 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30)(__uint32_t)(__builtin_constant_p(30) ? (__uint32_t)(((__uint32_t
)(30) & 0xff) << 24 | ((__uint32_t)(30) & 0xff00
) << 8 | ((__uint32_t)(30) & 0xff0000) >> 8 |
((__uint32_t)(30) & 0xff000000) >> 24) : __swap32md
(30))
;
786 }
787
788 smu_data->smc_state_table.LinkLevelCount =
789 (uint8_t)dpm_table->pcie_speed_table.count;
790
791/* To Do move to hwmgr */
792 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
793 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
794
795 return 0;
796}
797
798
799static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
800 SMU74_Discrete_DpmTable *table)
801{
802 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
803 uint32_t i, ref_clk;
804
805 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
806
807 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev)((struct amdgpu_device *)hwmgr->adev)->asic_funcs->get_xclk
(((struct amdgpu_device *)hwmgr->adev))
;
808
809 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
810 for (i = 0; i < NUM_SCLK_RANGE8; i++) {
811 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
812 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
813 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
814
815 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
816 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
817
818 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc)((table->SclkFcwRangeTable[i].fcw_pcc) = (__uint16_t)(__builtin_constant_p
(table->SclkFcwRangeTable[i].fcw_pcc) ? (__uint16_t)(((__uint16_t
)(table->SclkFcwRangeTable[i].fcw_pcc) & 0xffU) <<
8 | ((__uint16_t)(table->SclkFcwRangeTable[i].fcw_pcc) &
0xff00U) >> 8) : __swap16md(table->SclkFcwRangeTable
[i].fcw_pcc)))
;
819 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper)((table->SclkFcwRangeTable[i].fcw_trans_upper) = (__uint16_t
)(__builtin_constant_p(table->SclkFcwRangeTable[i].fcw_trans_upper
) ? (__uint16_t)(((__uint16_t)(table->SclkFcwRangeTable[i]
.fcw_trans_upper) & 0xffU) << 8 | ((__uint16_t)(table
->SclkFcwRangeTable[i].fcw_trans_upper) & 0xff00U) >>
8) : __swap16md(table->SclkFcwRangeTable[i].fcw_trans_upper
)))
;
820 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower)((table->SclkFcwRangeTable[i].fcw_trans_lower) = (__uint16_t
)(__builtin_constant_p(table->SclkFcwRangeTable[i].fcw_trans_lower
) ? (__uint16_t)(((__uint16_t)(table->SclkFcwRangeTable[i]
.fcw_trans_lower) & 0xffU) << 8 | ((__uint16_t)(table
->SclkFcwRangeTable[i].fcw_trans_lower) & 0xff00U) >>
8) : __swap16md(table->SclkFcwRangeTable[i].fcw_trans_lower
)))
;
821 }
822 return;
823 }
824
825 for (i = 0; i < NUM_SCLK_RANGE8; i++) {
826 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
827 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
828
829 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
830 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
831 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
832
833 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
834 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
835
836 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc)((table->SclkFcwRangeTable[i].fcw_pcc) = (__uint16_t)(__builtin_constant_p
(table->SclkFcwRangeTable[i].fcw_pcc) ? (__uint16_t)(((__uint16_t
)(table->SclkFcwRangeTable[i].fcw_pcc) & 0xffU) <<
8 | ((__uint16_t)(table->SclkFcwRangeTable[i].fcw_pcc) &
0xff00U) >> 8) : __swap16md(table->SclkFcwRangeTable
[i].fcw_pcc)))
;
837 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper)((table->SclkFcwRangeTable[i].fcw_trans_upper) = (__uint16_t
)(__builtin_constant_p(table->SclkFcwRangeTable[i].fcw_trans_upper
) ? (__uint16_t)(((__uint16_t)(table->SclkFcwRangeTable[i]
.fcw_trans_upper) & 0xffU) << 8 | ((__uint16_t)(table
->SclkFcwRangeTable[i].fcw_trans_upper) & 0xff00U) >>
8) : __swap16md(table->SclkFcwRangeTable[i].fcw_trans_upper
)))
;
838 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower)((table->SclkFcwRangeTable[i].fcw_trans_lower) = (__uint16_t
)(__builtin_constant_p(table->SclkFcwRangeTable[i].fcw_trans_lower
) ? (__uint16_t)(((__uint16_t)(table->SclkFcwRangeTable[i]
.fcw_trans_lower) & 0xffU) << 8 | ((__uint16_t)(table
->SclkFcwRangeTable[i].fcw_trans_lower) & 0xff00U) >>
8) : __swap16md(table->SclkFcwRangeTable[i].fcw_trans_lower
)))
;
839 }
840}
841
842static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
843 uint32_t clock, SMU_SclkSetting *sclk_setting)
844{
845 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
846 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
847 struct pp_atomctrl_clock_dividers_ai dividers;
848 uint32_t ref_clock;
849 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
850 uint8_t i;
851 int result;
852 uint64_t temp;
853
854 sclk_setting->SclkFrequency = clock;
855 /* get the engine clock dividers for this clock value */
856 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
857 if (result == 0) {
858 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
859 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
860 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
861 sclk_setting->PllRange = dividers.ucSclkPllRange;
862 sclk_setting->Sclk_slew_rate = 0x400;
863 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
864 sclk_setting->Pcc_down_slew_rate = 0xffff;
865 sclk_setting->SSc_En = dividers.ucSscEnable;
866 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
867 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
868 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
869 return result;
870 }
871
872 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev)((struct amdgpu_device *)hwmgr->adev)->asic_funcs->get_xclk
(((struct amdgpu_device *)hwmgr->adev))
;
873
874 for (i = 0; i < NUM_SCLK_RANGE8; i++) {
875 if (clock > smu_data->range_table[i].trans_lower_frequency
876 && clock <= smu_data->range_table[i].trans_upper_frequency) {
877 sclk_setting->PllRange = i;
878 break;
879 }
880 }
881
882 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
883 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
884 temp <<= 0x10;
885 do_div(temp, ref_clock)({ uint32_t __base = (ref_clock); uint32_t __rem = ((uint64_t
)(temp)) % __base; (temp) = ((uint64_t)(temp)) / __base; __rem
; })
;
886 sclk_setting->Fcw_frac = temp & 0xffff;
887
888 pcc_target_percent = 10; /* Hardcode 10% for now. */
889 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
890 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
891
892 ss_target_percent = 2; /* Hardcode 2% for now. */
893 sclk_setting->SSc_En = 0;
894 if (ss_target_percent) {
895 sclk_setting->SSc_En = 1;
896 ss_target_freq = clock - (clock * ss_target_percent / 100);
897 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
898 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
899 temp <<= 0x10;
900 do_div(temp, ref_clock)({ uint32_t __base = (ref_clock); uint32_t __rem = ((uint64_t
)(temp)) % __base; (temp) = ((uint64_t)(temp)) / __base; __rem
; })
;
901 sclk_setting->Fcw1_frac = temp & 0xffff;
902 }
903
904 return 0;
905}
906
907static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
908 uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
909{
910 int result;
911 /* PP_Clocks minClocks; */
912 uint32_t mvdd;
913 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
914 struct phm_ppt_v1_information *table_info =
915 (struct phm_ppt_v1_information *)(hwmgr->pptable);
916 SMU_SclkSetting curr_sclk_setting = { 0 };
917 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL((void *)0);
918
919 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
920
921 if (hwmgr->od_enabled)
922 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
923 else
924 vdd_dep_table = table_info->vdd_dep_on_sclk;
925
926 /* populate graphics levels */
927 result = polaris10_get_dependency_volt_by_clk(hwmgr,
928 vdd_dep_table, clock,
929 &level->MinVoltage, &mvdd);
930
931 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find VDDC voltage value for " "VDDC engine clock dependency table"
); return result; } } while (0)
932 "can not find VDDC voltage value for "do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find VDDC voltage value for " "VDDC engine clock dependency table"
); return result; } } while (0)
933 "VDDC engine clock dependency table",do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find VDDC voltage value for " "VDDC engine clock dependency table"
); return result; } } while (0)
934 return result)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find VDDC voltage value for " "VDDC engine clock dependency table"
); return result; } } while (0)
;
935 level->ActivityLevel = data->current_profile_setting.sclk_activity;
936
937 level->CcPwrDynRm = 0;
938 level->CcPwrDynRm1 = 0;
939 level->EnabledForActivity = 0;
940 level->EnabledForThrottle = 1;
941 level->UpHyst = data->current_profile_setting.sclk_up_hyst;
942 level->DownHyst = data->current_profile_setting.sclk_down_hyst;
943 level->VoltageDownHyst = 0;
944 level->PowerThrottle = 0;
945 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
946
947 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
948 level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
949 hwmgr->display_config->min_core_set_clock_in_sr);
950
951 /* Default to slow, highest DPM level will be
952 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
953 */
954 if (data->update_up_hyst)
955 level->UpHyst = (uint8_t)data->up_hyst;
956 if (data->update_down_hyst)
957 level->DownHyst = (uint8_t)data->down_hyst;
958
959 level->SclkSetting = curr_sclk_setting;
960
961 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage)((level->MinVoltage) = (__uint32_t)(__builtin_constant_p(level
->MinVoltage) ? (__uint32_t)(((__uint32_t)(level->MinVoltage
) & 0xff) << 24 | ((__uint32_t)(level->MinVoltage
) & 0xff00) << 8 | ((__uint32_t)(level->MinVoltage
) & 0xff0000) >> 8 | ((__uint32_t)(level->MinVoltage
) & 0xff000000) >> 24) : __swap32md(level->MinVoltage
)))
;
962 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm)((level->CcPwrDynRm) = (__uint32_t)(__builtin_constant_p(level
->CcPwrDynRm) ? (__uint32_t)(((__uint32_t)(level->CcPwrDynRm
) & 0xff) << 24 | ((__uint32_t)(level->CcPwrDynRm
) & 0xff00) << 8 | ((__uint32_t)(level->CcPwrDynRm
) & 0xff0000) >> 8 | ((__uint32_t)(level->CcPwrDynRm
) & 0xff000000) >> 24) : __swap32md(level->CcPwrDynRm
)))
;
963 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1)((level->CcPwrDynRm1) = (__uint32_t)(__builtin_constant_p(
level->CcPwrDynRm1) ? (__uint32_t)(((__uint32_t)(level->
CcPwrDynRm1) & 0xff) << 24 | ((__uint32_t)(level->
CcPwrDynRm1) & 0xff00) << 8 | ((__uint32_t)(level->
CcPwrDynRm1) & 0xff0000) >> 8 | ((__uint32_t)(level
->CcPwrDynRm1) & 0xff000000) >> 24) : __swap32md
(level->CcPwrDynRm1)))
;
964 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel)((level->ActivityLevel) = (__uint16_t)(__builtin_constant_p
(level->ActivityLevel) ? (__uint16_t)(((__uint16_t)(level->
ActivityLevel) & 0xffU) << 8 | ((__uint16_t)(level->
ActivityLevel) & 0xff00U) >> 8) : __swap16md(level->
ActivityLevel)))
;
965 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency)((level->SclkSetting.SclkFrequency) = (__uint32_t)(__builtin_constant_p
(level->SclkSetting.SclkFrequency) ? (__uint32_t)(((__uint32_t
)(level->SclkSetting.SclkFrequency) & 0xff) << 24
| ((__uint32_t)(level->SclkSetting.SclkFrequency) & 0xff00
) << 8 | ((__uint32_t)(level->SclkSetting.SclkFrequency
) & 0xff0000) >> 8 | ((__uint32_t)(level->SclkSetting
.SclkFrequency) & 0xff000000) >> 24) : __swap32md(level
->SclkSetting.SclkFrequency)))
;
966 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int)((level->SclkSetting.Fcw_int) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Fcw_int) ? (__uint16_t)(((__uint16_t)(
level->SclkSetting.Fcw_int) & 0xffU) << 8 | ((__uint16_t
)(level->SclkSetting.Fcw_int) & 0xff00U) >> 8) :
__swap16md(level->SclkSetting.Fcw_int)))
;
967 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac)((level->SclkSetting.Fcw_frac) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Fcw_frac) ? (__uint16_t)(((__uint16_t)
(level->SclkSetting.Fcw_frac) & 0xffU) << 8 | ((
__uint16_t)(level->SclkSetting.Fcw_frac) & 0xff00U) >>
8) : __swap16md(level->SclkSetting.Fcw_frac)))
;
968 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int)((level->SclkSetting.Pcc_fcw_int) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Pcc_fcw_int) ? (__uint16_t)(((__uint16_t
)(level->SclkSetting.Pcc_fcw_int) & 0xffU) << 8 |
((__uint16_t)(level->SclkSetting.Pcc_fcw_int) & 0xff00U
) >> 8) : __swap16md(level->SclkSetting.Pcc_fcw_int)
))
;
969 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate)((level->SclkSetting.Sclk_slew_rate) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Sclk_slew_rate) ? (__uint16_t)(((__uint16_t
)(level->SclkSetting.Sclk_slew_rate) & 0xffU) <<
8 | ((__uint16_t)(level->SclkSetting.Sclk_slew_rate) &
0xff00U) >> 8) : __swap16md(level->SclkSetting.Sclk_slew_rate
)))
;
970 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate)((level->SclkSetting.Pcc_up_slew_rate) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Pcc_up_slew_rate) ? (__uint16_t)(((__uint16_t
)(level->SclkSetting.Pcc_up_slew_rate) & 0xffU) <<
8 | ((__uint16_t)(level->SclkSetting.Pcc_up_slew_rate) &
0xff00U) >> 8) : __swap16md(level->SclkSetting.Pcc_up_slew_rate
)))
;
971 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate)((level->SclkSetting.Pcc_down_slew_rate) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Pcc_down_slew_rate) ? (__uint16_t)(((__uint16_t
)(level->SclkSetting.Pcc_down_slew_rate) & 0xffU) <<
8 | ((__uint16_t)(level->SclkSetting.Pcc_down_slew_rate) &
0xff00U) >> 8) : __swap16md(level->SclkSetting.Pcc_down_slew_rate
)))
;
972 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int)((level->SclkSetting.Fcw1_int) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Fcw1_int) ? (__uint16_t)(((__uint16_t)
(level->SclkSetting.Fcw1_int) & 0xffU) << 8 | ((
__uint16_t)(level->SclkSetting.Fcw1_int) & 0xff00U) >>
8) : __swap16md(level->SclkSetting.Fcw1_int)))
;
973 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac)((level->SclkSetting.Fcw1_frac) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Fcw1_frac) ? (__uint16_t)(((__uint16_t
)(level->SclkSetting.Fcw1_frac) & 0xffU) << 8 | (
(__uint16_t)(level->SclkSetting.Fcw1_frac) & 0xff00U) >>
8) : __swap16md(level->SclkSetting.Fcw1_frac)))
;
974 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate)((level->SclkSetting.Sclk_ss_slew_rate) = (__uint16_t)(__builtin_constant_p
(level->SclkSetting.Sclk_ss_slew_rate) ? (__uint16_t)(((__uint16_t
)(level->SclkSetting.Sclk_ss_slew_rate) & 0xffU) <<
8 | ((__uint16_t)(level->SclkSetting.Sclk_ss_slew_rate) &
0xff00U) >> 8) : __swap16md(level->SclkSetting.Sclk_ss_slew_rate
)))
;
975 return 0;
976}
977
978static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
979{
980 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
981 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
982 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
983 struct phm_ppt_v1_information *table_info =
984 (struct phm_ppt_v1_information *)(hwmgr->pptable);
985 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
986 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
987 int result = 0;
988 uint32_t array = smu_data->smu7_data.dpm_table_start +
989 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
990 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
991 SMU74_MAX_LEVELS_GRAPHICS8;
992 struct SMU74_Discrete_GraphicsLevel *levels =
993 smu_data->smc_state_table.GraphicsLevel;
994 uint32_t i, max_entry;
995 uint8_t hightest_pcie_level_enabled = 0,
996 lowest_pcie_level_enabled = 0,
997 mid_pcie_level_enabled = 0,
998 count = 0;
999
1000 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1001
1002 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1003
1004 result = polaris10_populate_single_graphic_level(hwmgr,
1005 dpm_table->sclk_table.dpm_levels[i].value,
1006 &(smu_data->smc_state_table.GraphicsLevel[i]));
1007 if (result)
1008 return result;
1009
1010 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1011 if (i > 1)
1012 levels[i].DeepSleepDivId = 0;
1013 }
1014 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1015 PHM_PlatformCaps_SPLLShutdownSupport))
1016 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1017
1018 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1019 smu_data->smc_state_table.GraphicsDpmLevelCount =
1020 (uint8_t)dpm_table->sclk_table.count;
1021 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1022 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1023
1024
1025 if (pcie_table != NULL((void *)0)) {
1026 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),do { if (!((1 <= pcie_entry_cnt))) { printk("\0014" "amdgpu: "
"%s\n", "There must be 1 or more PCIE levels defined in PPTable."
); return -22; } } while (0)
1027 "There must be 1 or more PCIE levels defined in PPTable.",do { if (!((1 <= pcie_entry_cnt))) { printk("\0014" "amdgpu: "
"%s\n", "There must be 1 or more PCIE levels defined in PPTable."
); return -22; } } while (0)
1028 return -EINVAL)do { if (!((1 <= pcie_entry_cnt))) { printk("\0014" "amdgpu: "
"%s\n", "There must be 1 or more PCIE levels defined in PPTable."
); return -22; } } while (0)
;
1029 max_entry = pcie_entry_cnt - 1;
1030 for (i = 0; i < dpm_table->sclk_table.count; i++)
1031 levels[i].pcieDpmLevel =
1032 (uint8_t) ((i < max_entry) ? i : max_entry);
1033 } else {
1034 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1035 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1036 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1037 hightest_pcie_level_enabled++;
1038
1039 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1040 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1041 (1 << lowest_pcie_level_enabled)) == 0))
1042 lowest_pcie_level_enabled++;
1043
1044 while ((count < hightest_pcie_level_enabled) &&
1045 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1046 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1047 count++;
1048
1049 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1050 hightest_pcie_level_enabled ?
1051 (lowest_pcie_level_enabled + 1 + count) :
1052 hightest_pcie_level_enabled;
1053
1054 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1055 for (i = 2; i < dpm_table->sclk_table.count; i++)
1056 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1057
1058 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1059 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1060
1061 /* set pcieDpmLevel to mid_pcie_level_enabled */
1062 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1063 }
1064 /* level count will send to smc once at init smc table and never change */
1065 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1066 (uint32_t)array_size, SMC_RAM_END0x40000);
1067
1068 return result;
1069}
1070
1071
1072static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1073 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1074{
1075 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1076 struct phm_ppt_v1_information *table_info =
1077 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1078 int result = 0;
1079 uint32_t mclk_stutter_mode_threshold = 40000;
1080 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL((void *)0);
1081
1082
1083 if (hwmgr->od_enabled)
1084 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1085 else
1086 vdd_dep_table = table_info->vdd_dep_on_mclk;
1087
1088 if (vdd_dep_table) {
1089 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1090 vdd_dep_table, clock,
1091 &mem_level->MinVoltage, &mem_level->MinMvdd);
1092 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find MinVddc voltage value from memory " "VDDC voltage dependency table"
); return result; } } while (0)
1093 "can not find MinVddc voltage value from memory "do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find MinVddc voltage value from memory " "VDDC voltage dependency table"
); return result; } } while (0)
1094 "VDDC voltage dependency table", return result)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find MinVddc voltage value from memory " "VDDC voltage dependency table"
); return result; } } while (0)
;
1095 }
1096
1097 mem_level->MclkFrequency = clock;
1098 mem_level->EnabledForThrottle = 1;
1099 mem_level->EnabledForActivity = 0;
1100 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1101 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1102 mem_level->VoltageDownHyst = 0;
1103 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1104 mem_level->StutterEnable = false0;
1105 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW0;
1106
1107 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1108 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1109
1110 if (mclk_stutter_mode_threshold &&
1111 (clock <= mclk_stutter_mode_threshold) &&
1112 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,((((((struct cgs_device *)hwmgr->device)->ops->read_register
(hwmgr->device,0x1b35))) & 0x1) >> 0x0)
1113 STUTTER_ENABLE)((((((struct cgs_device *)hwmgr->device)->ops->read_register
(hwmgr->device,0x1b35))) & 0x1) >> 0x0)
& 0x1))
1114 mem_level->StutterEnable = true1;
1115
1116 if (!result) {
1117 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd)((mem_level->MinMvdd) = (__uint32_t)(__builtin_constant_p(
mem_level->MinMvdd) ? (__uint32_t)(((__uint32_t)(mem_level
->MinMvdd) & 0xff) << 24 | ((__uint32_t)(mem_level
->MinMvdd) & 0xff00) << 8 | ((__uint32_t)(mem_level
->MinMvdd) & 0xff0000) >> 8 | ((__uint32_t)(mem_level
->MinMvdd) & 0xff000000) >> 24) : __swap32md(mem_level
->MinMvdd)))
;
1118 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency)((mem_level->MclkFrequency) = (__uint32_t)(__builtin_constant_p
(mem_level->MclkFrequency) ? (__uint32_t)(((__uint32_t)(mem_level
->MclkFrequency) & 0xff) << 24 | ((__uint32_t)(mem_level
->MclkFrequency) & 0xff00) << 8 | ((__uint32_t)(
mem_level->MclkFrequency) & 0xff0000) >> 8 | ((__uint32_t
)(mem_level->MclkFrequency) & 0xff000000) >> 24)
: __swap32md(mem_level->MclkFrequency)))
;
1119 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel)((mem_level->ActivityLevel) = (__uint16_t)(__builtin_constant_p
(mem_level->ActivityLevel) ? (__uint16_t)(((__uint16_t)(mem_level
->ActivityLevel) & 0xffU) << 8 | ((__uint16_t)(mem_level
->ActivityLevel) & 0xff00U) >> 8) : __swap16md(mem_level
->ActivityLevel)))
;
1120 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage)((mem_level->MinVoltage) = (__uint32_t)(__builtin_constant_p
(mem_level->MinVoltage) ? (__uint32_t)(((__uint32_t)(mem_level
->MinVoltage) & 0xff) << 24 | ((__uint32_t)(mem_level
->MinVoltage) & 0xff00) << 8 | ((__uint32_t)(mem_level
->MinVoltage) & 0xff0000) >> 8 | ((__uint32_t)(mem_level
->MinVoltage) & 0xff000000) >> 24) : __swap32md(
mem_level->MinVoltage)))
;
1121 }
1122 return result;
1123}
1124
1125static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1126{
1127 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1128 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1129 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1130 int result;
1131 /* populate MCLK dpm table to SMU7 */
1132 uint32_t array = smu_data->smu7_data.dpm_table_start +
1133 offsetof(SMU74_Discrete_DpmTable, MemoryLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1134 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1135 SMU74_MAX_LEVELS_MEMORY4;
1136 struct SMU74_Discrete_MemoryLevel *levels =
1137 smu_data->smc_state_table.MemoryLevel;
1138 uint32_t i;
1139
1140 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1141 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),do { if (!((0 != dpm_table->mclk_table.dpm_levels[i].value
))) { printk("\0014" "amdgpu: " "%s\n", "can not populate memory level as memory clock is zero"
); return -22; } } while (0)
1142 "can not populate memory level as memory clock is zero",do { if (!((0 != dpm_table->mclk_table.dpm_levels[i].value
))) { printk("\0014" "amdgpu: " "%s\n", "can not populate memory level as memory clock is zero"
); return -22; } } while (0)
1143 return -EINVAL)do { if (!((0 != dpm_table->mclk_table.dpm_levels[i].value
))) { printk("\0014" "amdgpu: " "%s\n", "can not populate memory level as memory clock is zero"
); return -22; } } while (0)
;
1144 result = polaris10_populate_single_memory_level(hwmgr,
1145 dpm_table->mclk_table.dpm_levels[i].value,
1146 &levels[i]);
1147 if (i == dpm_table->mclk_table.count - 1) {
1148 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH1;
1149 levels[i].EnabledForActivity = 1;
1150 }
1151 if (result)
1152 return result;
1153 }
1154
1155 /* In order to prevent MC activity from stutter mode to push DPM up,
1156 * the UVD change complements this by putting the MCLK in
1157 * a higher state by default such that we are not affected by
1158 * up threshold or and MCLK DPM latency.
1159 */
1160 levels[0].ActivityLevel = 0x1f;
1161 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel)((levels[0].ActivityLevel) = (__uint16_t)(__builtin_constant_p
(levels[0].ActivityLevel) ? (__uint16_t)(((__uint16_t)(levels
[0].ActivityLevel) & 0xffU) << 8 | ((__uint16_t)(levels
[0].ActivityLevel) & 0xff00U) >> 8) : __swap16md(levels
[0].ActivityLevel)))
;
1162
1163 smu_data->smc_state_table.MemoryDpmLevelCount =
1164 (uint8_t)dpm_table->mclk_table.count;
1165 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1166 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1167
1168 /* level count will send to smc once at init smc table and never change */
1169 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1170 (uint32_t)array_size, SMC_RAM_END0x40000);
1171
1172 return result;
1173}
1174
1175static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1176 uint32_t mclk, SMIO_Pattern *smio_pat)
1177{
1178 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1179 struct phm_ppt_v1_information *table_info =
1180 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1181 uint32_t i = 0;
1182
1183 if (SMU7_VOLTAGE_CONTROL_NONE0x0 != data->mvdd_control) {
1184 /* find mvdd value which clock is more than request */
1185 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1186 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1187 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1188 break;
1189 }
1190 }
1191 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,do { if (!(i < table_info->vdd_dep_on_mclk->count)) {
printk("\0014" "amdgpu: " "%s\n", "MVDD Voltage is outside the supported range."
); return -22; } } while (0)
1192 "MVDD Voltage is outside the supported range.",do { if (!(i < table_info->vdd_dep_on_mclk->count)) {
printk("\0014" "amdgpu: " "%s\n", "MVDD Voltage is outside the supported range."
); return -22; } } while (0)
1193 return -EINVAL)do { if (!(i < table_info->vdd_dep_on_mclk->count)) {
printk("\0014" "amdgpu: " "%s\n", "MVDD Voltage is outside the supported range."
); return -22; } } while (0)
;
1194 } else
1195 return -EINVAL22;
1196
1197 return 0;
1198}
1199
1200static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1201 SMU74_Discrete_DpmTable *table)
1202{
1203 int result = 0;
1204 uint32_t sclk_frequency;
1205 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1206 struct phm_ppt_v1_information *table_info =
1207 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1208 SMIO_Pattern vol_level;
1209 uint32_t mvdd;
1210
1211 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC0x01;
1212
1213 /* Get MinVoltage and Frequency from DPM0,
1214 * already converted to SMC_UL */
1215 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1216 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1217 table_info->vdd_dep_on_sclk,
1218 sclk_frequency,
1219 &table->ACPILevel.MinVoltage, &mvdd);
1220 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Cannot find ACPI VDDC voltage value " "in Clock Dependency Table"
); ; } } while (0)
1221 "Cannot find ACPI VDDC voltage value "do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Cannot find ACPI VDDC voltage value " "in Clock Dependency Table"
); ; } } while (0)
1222 "in Clock Dependency Table",do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Cannot find ACPI VDDC voltage value " "in Clock Dependency Table"
); ; } } while (0)
1223 )do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Cannot find ACPI VDDC voltage value " "in Clock Dependency Table"
); ; } } while (0)
;
1224
1225 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1226 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result)do { if (!(result == 0)) { printk("\0014" "amdgpu: " "%s\n", "Error retrieving Engine Clock dividers from VBIOS."
); return result; } } while (0)
;
1227
1228 table->ACPILevel.DeepSleepDivId = 0;
1229 table->ACPILevel.CcPwrDynRm = 0;
1230 table->ACPILevel.CcPwrDynRm1 = 0;
1231
1232 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags)((table->ACPILevel.Flags) = (__uint32_t)(__builtin_constant_p
(table->ACPILevel.Flags) ? (__uint32_t)(((__uint32_t)(table
->ACPILevel.Flags) & 0xff) << 24 | ((__uint32_t)
(table->ACPILevel.Flags) & 0xff00) << 8 | ((__uint32_t
)(table->ACPILevel.Flags) & 0xff0000) >> 8 | ((__uint32_t
)(table->ACPILevel.Flags) & 0xff000000) >> 24) :
__swap32md(table->ACPILevel.Flags)))
;
1233 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage)((table->ACPILevel.MinVoltage) = (__uint32_t)(__builtin_constant_p
(table->ACPILevel.MinVoltage) ? (__uint32_t)(((__uint32_t)
(table->ACPILevel.MinVoltage) & 0xff) << 24 | ((
__uint32_t)(table->ACPILevel.MinVoltage) & 0xff00) <<
8 | ((__uint32_t)(table->ACPILevel.MinVoltage) & 0xff0000
) >> 8 | ((__uint32_t)(table->ACPILevel.MinVoltage) &
0xff000000) >> 24) : __swap32md(table->ACPILevel.MinVoltage
)))
;
1234 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm)((table->ACPILevel.CcPwrDynRm) = (__uint32_t)(__builtin_constant_p
(table->ACPILevel.CcPwrDynRm) ? (__uint32_t)(((__uint32_t)
(table->ACPILevel.CcPwrDynRm) & 0xff) << 24 | ((
__uint32_t)(table->ACPILevel.CcPwrDynRm) & 0xff00) <<
8 | ((__uint32_t)(table->ACPILevel.CcPwrDynRm) & 0xff0000
) >> 8 | ((__uint32_t)(table->ACPILevel.CcPwrDynRm) &
0xff000000) >> 24) : __swap32md(table->ACPILevel.CcPwrDynRm
)))
;
1235 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1)((table->ACPILevel.CcPwrDynRm1) = (__uint32_t)(__builtin_constant_p
(table->ACPILevel.CcPwrDynRm1) ? (__uint32_t)(((__uint32_t
)(table->ACPILevel.CcPwrDynRm1) & 0xff) << 24 | (
(__uint32_t)(table->ACPILevel.CcPwrDynRm1) & 0xff00) <<
8 | ((__uint32_t)(table->ACPILevel.CcPwrDynRm1) & 0xff0000
) >> 8 | ((__uint32_t)(table->ACPILevel.CcPwrDynRm1)
& 0xff000000) >> 24) : __swap32md(table->ACPILevel
.CcPwrDynRm1)))
;
1236
1237 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency)((table->ACPILevel.SclkSetting.SclkFrequency) = (__uint32_t
)(__builtin_constant_p(table->ACPILevel.SclkSetting.SclkFrequency
) ? (__uint32_t)(((__uint32_t)(table->ACPILevel.SclkSetting
.SclkFrequency) & 0xff) << 24 | ((__uint32_t)(table
->ACPILevel.SclkSetting.SclkFrequency) & 0xff00) <<
8 | ((__uint32_t)(table->ACPILevel.SclkSetting.SclkFrequency
) & 0xff0000) >> 8 | ((__uint32_t)(table->ACPILevel
.SclkSetting.SclkFrequency) & 0xff000000) >> 24) : __swap32md
(table->ACPILevel.SclkSetting.SclkFrequency)))
;
1238 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int)((table->ACPILevel.SclkSetting.Fcw_int) = (__uint16_t)(__builtin_constant_p
(table->ACPILevel.SclkSetting.Fcw_int) ? (__uint16_t)(((__uint16_t
)(table->ACPILevel.SclkSetting.Fcw_int) & 0xffU) <<
8 | ((__uint16_t)(table->ACPILevel.SclkSetting.Fcw_int) &
0xff00U) >> 8) : __swap16md(table->ACPILevel.SclkSetting
.Fcw_int)))
;
1239 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac)((table->ACPILevel.SclkSetting.Fcw_frac) = (__uint16_t)(__builtin_constant_p
(table->ACPILevel.SclkSetting.Fcw_frac) ? (__uint16_t)(((__uint16_t
)(table->ACPILevel.SclkSetting.Fcw_frac) & 0xffU) <<
8 | ((__uint16_t)(table->ACPILevel.SclkSetting.Fcw_frac) &
0xff00U) >> 8) : __swap16md(table->ACPILevel.SclkSetting
.Fcw_frac)))
;
1240 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int)((table->ACPILevel.SclkSetting.Pcc_fcw_int) = (__uint16_t)
(__builtin_constant_p(table->ACPILevel.SclkSetting.Pcc_fcw_int
) ? (__uint16_t)(((__uint16_t)(table->ACPILevel.SclkSetting
.Pcc_fcw_int) & 0xffU) << 8 | ((__uint16_t)(table->
ACPILevel.SclkSetting.Pcc_fcw_int) & 0xff00U) >> 8)
: __swap16md(table->ACPILevel.SclkSetting.Pcc_fcw_int)))
;
1241 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate)((table->ACPILevel.SclkSetting.Sclk_slew_rate) = (__uint16_t
)(__builtin_constant_p(table->ACPILevel.SclkSetting.Sclk_slew_rate
) ? (__uint16_t)(((__uint16_t)(table->ACPILevel.SclkSetting
.Sclk_slew_rate) & 0xffU) << 8 | ((__uint16_t)(table
->ACPILevel.SclkSetting.Sclk_slew_rate) & 0xff00U) >>
8) : __swap16md(table->ACPILevel.SclkSetting.Sclk_slew_rate
)))
;
1242 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate)((table->ACPILevel.SclkSetting.Pcc_up_slew_rate) = (__uint16_t
)(__builtin_constant_p(table->ACPILevel.SclkSetting.Pcc_up_slew_rate
) ? (__uint16_t)(((__uint16_t)(table->ACPILevel.SclkSetting
.Pcc_up_slew_rate) & 0xffU) << 8 | ((__uint16_t)(table
->ACPILevel.SclkSetting.Pcc_up_slew_rate) & 0xff00U) >>
8) : __swap16md(table->ACPILevel.SclkSetting.Pcc_up_slew_rate
)))
;
1243 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate)((table->ACPILevel.SclkSetting.Pcc_down_slew_rate) = (__uint16_t
)(__builtin_constant_p(table->ACPILevel.SclkSetting.Pcc_down_slew_rate
) ? (__uint16_t)(((__uint16_t)(table->ACPILevel.SclkSetting
.Pcc_down_slew_rate) & 0xffU) << 8 | ((__uint16_t)(
table->ACPILevel.SclkSetting.Pcc_down_slew_rate) & 0xff00U
) >> 8) : __swap16md(table->ACPILevel.SclkSetting.Pcc_down_slew_rate
)))
;
1244 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int)((table->ACPILevel.SclkSetting.Fcw1_int) = (__uint16_t)(__builtin_constant_p
(table->ACPILevel.SclkSetting.Fcw1_int) ? (__uint16_t)(((__uint16_t
)(table->ACPILevel.SclkSetting.Fcw1_int) & 0xffU) <<
8 | ((__uint16_t)(table->ACPILevel.SclkSetting.Fcw1_int) &
0xff00U) >> 8) : __swap16md(table->ACPILevel.SclkSetting
.Fcw1_int)))
;
1245 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac)((table->ACPILevel.SclkSetting.Fcw1_frac) = (__uint16_t)(__builtin_constant_p
(table->ACPILevel.SclkSetting.Fcw1_frac) ? (__uint16_t)(((
__uint16_t)(table->ACPILevel.SclkSetting.Fcw1_frac) & 0xffU
) << 8 | ((__uint16_t)(table->ACPILevel.SclkSetting.
Fcw1_frac) & 0xff00U) >> 8) : __swap16md(table->
ACPILevel.SclkSetting.Fcw1_frac)))
;
1246 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate)((table->ACPILevel.SclkSetting.Sclk_ss_slew_rate) = (__uint16_t
)(__builtin_constant_p(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate
) ? (__uint16_t)(((__uint16_t)(table->ACPILevel.SclkSetting
.Sclk_ss_slew_rate) & 0xffU) << 8 | ((__uint16_t)(table
->ACPILevel.SclkSetting.Sclk_ss_slew_rate) & 0xff00U) >>
8) : __swap16md(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate
)))
;
1247
1248
1249 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1250 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1251 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1252 table_info->vdd_dep_on_mclk,
1253 table->MemoryACPILevel.MclkFrequency,
1254 &table->MemoryACPILevel.MinVoltage, &mvdd);
1255 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Cannot find ACPI VDDCI voltage value " "in Clock Dependency Table"
); ; } } while (0)
1256 "Cannot find ACPI VDDCI voltage value "do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Cannot find ACPI VDDCI voltage value " "in Clock Dependency Table"
); ; } } while (0)
1257 "in Clock Dependency Table",do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Cannot find ACPI VDDCI voltage value " "in Clock Dependency Table"
); ; } } while (0)
1258 )do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Cannot find ACPI VDDCI voltage value " "in Clock Dependency Table"
); ; } } while (0)
;
1259
1260 if (!((SMU7_VOLTAGE_CONTROL_NONE0x0 == data->mvdd_control) ||
1261 (data->mclk_dpm_key_disabled)))
1262 polaris10_populate_mvdd_value(hwmgr,
1263 data->dpm_table.mclk_table.dpm_levels[0].value,
1264 &vol_level);
1265
1266 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1267 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage)(__uint32_t)(__builtin_constant_p(vol_level.Voltage) ? (__uint32_t
)(((__uint32_t)(vol_level.Voltage) & 0xff) << 24 | (
(__uint32_t)(vol_level.Voltage) & 0xff00) << 8 | ((
__uint32_t)(vol_level.Voltage) & 0xff0000) >> 8 | (
(__uint32_t)(vol_level.Voltage) & 0xff000000) >> 24
) : __swap32md(vol_level.Voltage))
;
1268 else
1269 table->MemoryACPILevel.MinMvdd = 0;
1270
1271 table->MemoryACPILevel.StutterEnable = false0;
1272
1273 table->MemoryACPILevel.EnabledForThrottle = 0;
1274 table->MemoryACPILevel.EnabledForActivity = 0;
1275 table->MemoryACPILevel.UpHyst = 0;
1276 table->MemoryACPILevel.DownHyst = 100;
1277 table->MemoryACPILevel.VoltageDownHyst = 0;
1278 table->MemoryACPILevel.ActivityLevel =
1279 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity)(__uint16_t)(__builtin_constant_p(data->current_profile_setting
.mclk_activity) ? (__uint16_t)(((__uint16_t)(data->current_profile_setting
.mclk_activity) & 0xffU) << 8 | ((__uint16_t)(data->
current_profile_setting.mclk_activity) & 0xff00U) >>
8) : __swap16md(data->current_profile_setting.mclk_activity
))
;
1280
1281 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency)((table->MemoryACPILevel.MclkFrequency) = (__uint32_t)(__builtin_constant_p
(table->MemoryACPILevel.MclkFrequency) ? (__uint32_t)(((__uint32_t
)(table->MemoryACPILevel.MclkFrequency) & 0xff) <<
24 | ((__uint32_t)(table->MemoryACPILevel.MclkFrequency) &
0xff00) << 8 | ((__uint32_t)(table->MemoryACPILevel
.MclkFrequency) & 0xff0000) >> 8 | ((__uint32_t)(table
->MemoryACPILevel.MclkFrequency) & 0xff000000) >>
24) : __swap32md(table->MemoryACPILevel.MclkFrequency)))
;
1282 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage)((table->MemoryACPILevel.MinVoltage) = (__uint32_t)(__builtin_constant_p
(table->MemoryACPILevel.MinVoltage) ? (__uint32_t)(((__uint32_t
)(table->MemoryACPILevel.MinVoltage) & 0xff) << 24
| ((__uint32_t)(table->MemoryACPILevel.MinVoltage) & 0xff00
) << 8 | ((__uint32_t)(table->MemoryACPILevel.MinVoltage
) & 0xff0000) >> 8 | ((__uint32_t)(table->MemoryACPILevel
.MinVoltage) & 0xff000000) >> 24) : __swap32md(table
->MemoryACPILevel.MinVoltage)))
;
1283
1284 return result;
1285}
1286
1287static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1288 SMU74_Discrete_DpmTable *table)
1289{
1290 int result = -EINVAL22;
1291 uint8_t count;
1292 struct pp_atomctrl_clock_dividers_vi dividers;
1293 struct phm_ppt_v1_information *table_info =
1294 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1295 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1296 table_info->mm_dep_table;
1297 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1298 uint32_t vddci;
1299
1300 table->VceLevelCount = (uint8_t)(mm_table->count);
1301 table->VceBootLevel = 0;
1302
1303 for (count = 0; count < table->VceLevelCount; count++) {
1304 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1305 table->VceLevel[count].MinVoltage = 0;
1306 table->VceLevel[count].MinVoltage |=
1307 (mm_table->entries[count].vddc * VOLTAGE_SCALE4) << VDDC_SHIFT0;
1308
1309 if (SMU7_VOLTAGE_CONTROL_BY_GPIO0x1 == data->vddci_control)
1310 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1311 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA200);
1312 else if (SMU7_VOLTAGE_CONTROL_BY_SVID20x2 == data->vddci_control)
1313 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA200;
1314 else
1315 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE4) << VDDCI_SHIFT15;
1316
1317
1318 table->VceLevel[count].MinVoltage |=
1319 (vddci * VOLTAGE_SCALE4) << VDDCI_SHIFT15;
1320 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT30;
1321
1322 /*retrieve divider value for VBIOS */
1323 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1324 table->VceLevel[count].Frequency, &dividers);
1325 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find divide id for VCE engine clock"); return result
; } } while (0)
1326 "can not find divide id for VCE engine clock",do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find divide id for VCE engine clock"); return result
; } } while (0)
1327 return result)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find divide id for VCE engine clock"); return result
; } } while (0)
;
1328
1329 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1330
1331 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency)((table->VceLevel[count].Frequency) = (__uint32_t)(__builtin_constant_p
(table->VceLevel[count].Frequency) ? (__uint32_t)(((__uint32_t
)(table->VceLevel[count].Frequency) & 0xff) << 24
| ((__uint32_t)(table->VceLevel[count].Frequency) & 0xff00
) << 8 | ((__uint32_t)(table->VceLevel[count].Frequency
) & 0xff0000) >> 8 | ((__uint32_t)(table->VceLevel
[count].Frequency) & 0xff000000) >> 24) : __swap32md
(table->VceLevel[count].Frequency)))
;
1332 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage)((table->VceLevel[count].MinVoltage) = (__uint32_t)(__builtin_constant_p
(table->VceLevel[count].MinVoltage) ? (__uint32_t)(((__uint32_t
)(table->VceLevel[count].MinVoltage) & 0xff) << 24
| ((__uint32_t)(table->VceLevel[count].MinVoltage) & 0xff00
) << 8 | ((__uint32_t)(table->VceLevel[count].MinVoltage
) & 0xff0000) >> 8 | ((__uint32_t)(table->VceLevel
[count].MinVoltage) & 0xff000000) >> 24) : __swap32md
(table->VceLevel[count].MinVoltage)))
;
1333 }
1334 return result;
1335}
1336
1337static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1338 int32_t eng_clock, int32_t mem_clock,
1339 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1340{
1341 uint32_t dram_timing;
1342 uint32_t dram_timing2;
1343 uint32_t burst_time;
1344 int result;
1345
1346 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1347 eng_clock, mem_clock);
1348 PP_ASSERT_WITH_CODE(result == 0,do { if (!(result == 0)) { printk("\0014" "amdgpu: " "%s\n", "Error calling VBIOS to set DRAM_TIMING."
); return result; } } while (0)
1349 "Error calling VBIOS to set DRAM_TIMING.", return result)do { if (!(result == 0)) { printk("\0014" "amdgpu: " "%s\n", "Error calling VBIOS to set DRAM_TIMING."
); return result; } } while (0)
;
1350
1351 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING)(((struct cgs_device *)hwmgr->device)->ops->read_register
(hwmgr->device,0x9dd))
;
1352 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2)(((struct cgs_device *)hwmgr->device)->ops->read_register
(hwmgr->device,0x9de))
;
1353 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0)((((((struct cgs_device *)hwmgr->device)->ops->read_register
(hwmgr->device,0xa02))) & 0x1f) >> 0x0)
;
1354
1355
1356 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing)(__uint32_t)(__builtin_constant_p(dram_timing) ? (__uint32_t)
(((__uint32_t)(dram_timing) & 0xff) << 24 | ((__uint32_t
)(dram_timing) & 0xff00) << 8 | ((__uint32_t)(dram_timing
) & 0xff0000) >> 8 | ((__uint32_t)(dram_timing) &
0xff000000) >> 24) : __swap32md(dram_timing))
;
1357 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2)(__uint32_t)(__builtin_constant_p(dram_timing2) ? (__uint32_t
)(((__uint32_t)(dram_timing2) & 0xff) << 24 | ((__uint32_t
)(dram_timing2) & 0xff00) << 8 | ((__uint32_t)(dram_timing2
) & 0xff0000) >> 8 | ((__uint32_t)(dram_timing2) &
0xff000000) >> 24) : __swap32md(dram_timing2))
;
1358 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1359
1360 return 0;
1361}
1362
1363static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1364{
1365 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1366 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1367 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1368 uint32_t i, j;
1369 int result = 0;
1370
1371 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1372 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1373 result = polaris10_populate_memory_timing_parameters(hwmgr,
1374 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1375 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1376 &arb_regs.entries[i][j]);
1377 if (result == 0)
1378 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1379 if (result != 0)
1380 return result;
1381 }
1382 }
1383
1384 result = smu7_copy_bytes_to_smc(
1385 hwmgr,
1386 smu_data->smu7_data.arb_table_start,
1387 (uint8_t *)&arb_regs,
1388 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1389 SMC_RAM_END0x40000);
1390 return result;
1391}
1392
1393static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1394 struct SMU74_Discrete_DpmTable *table)
1395{
1396 int result = -EINVAL22;
1397 uint8_t count;
1398 struct pp_atomctrl_clock_dividers_vi dividers;
1399 struct phm_ppt_v1_information *table_info =
1400 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1401 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1402 table_info->mm_dep_table;
1403 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1404 uint32_t vddci;
1405
1406 table->UvdLevelCount = (uint8_t)(mm_table->count);
1407 table->UvdBootLevel = 0;
1408
1409 for (count = 0; count < table->UvdLevelCount; count++) {
1410 table->UvdLevel[count].MinVoltage = 0;
1411 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1412 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1413 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1414 VOLTAGE_SCALE4) << VDDC_SHIFT0;
1415
1416 if (SMU7_VOLTAGE_CONTROL_BY_GPIO0x1 == data->vddci_control)
1417 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1418 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA200);
1419 else if (SMU7_VOLTAGE_CONTROL_BY_SVID20x2 == data->vddci_control)
1420 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA200;
1421 else
1422 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE4) << VDDCI_SHIFT15;
1423
1424 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE4) << VDDCI_SHIFT15;
1425 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT30;
1426
1427 /* retrieve divider value for VBIOS */
1428 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1429 table->UvdLevel[count].VclkFrequency, &dividers);
1430 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find divide id for Vclk clock"); return result; } }
while (0)
1431 "can not find divide id for Vclk clock", return result)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find divide id for Vclk clock"); return result; } }
while (0)
;
1432
1433 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1434
1435 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1436 table->UvdLevel[count].DclkFrequency, &dividers);
1437 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find divide id for Dclk clock"); return result; } }
while (0)
1438 "can not find divide id for Dclk clock", return result)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "can not find divide id for Dclk clock"); return result; } }
while (0)
;
1439
1440 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1441
1442 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency)((table->UvdLevel[count].VclkFrequency) = (__uint32_t)(__builtin_constant_p
(table->UvdLevel[count].VclkFrequency) ? (__uint32_t)(((__uint32_t
)(table->UvdLevel[count].VclkFrequency) & 0xff) <<
24 | ((__uint32_t)(table->UvdLevel[count].VclkFrequency) &
0xff00) << 8 | ((__uint32_t)(table->UvdLevel[count]
.VclkFrequency) & 0xff0000) >> 8 | ((__uint32_t)(table
->UvdLevel[count].VclkFrequency) & 0xff000000) >>
24) : __swap32md(table->UvdLevel[count].VclkFrequency)))
;
1443 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency)((table->UvdLevel[count].DclkFrequency) = (__uint32_t)(__builtin_constant_p
(table->UvdLevel[count].DclkFrequency) ? (__uint32_t)(((__uint32_t
)(table->UvdLevel[count].DclkFrequency) & 0xff) <<
24 | ((__uint32_t)(table->UvdLevel[count].DclkFrequency) &
0xff00) << 8 | ((__uint32_t)(table->UvdLevel[count]
.DclkFrequency) & 0xff0000) >> 8 | ((__uint32_t)(table
->UvdLevel[count].DclkFrequency) & 0xff000000) >>
24) : __swap32md(table->UvdLevel[count].DclkFrequency)))
;
1444 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage)((table->UvdLevel[count].MinVoltage) = (__uint32_t)(__builtin_constant_p
(table->UvdLevel[count].MinVoltage) ? (__uint32_t)(((__uint32_t
)(table->UvdLevel[count].MinVoltage) & 0xff) << 24
| ((__uint32_t)(table->UvdLevel[count].MinVoltage) & 0xff00
) << 8 | ((__uint32_t)(table->UvdLevel[count].MinVoltage
) & 0xff0000) >> 8 | ((__uint32_t)(table->UvdLevel
[count].MinVoltage) & 0xff000000) >> 24) : __swap32md
(table->UvdLevel[count].MinVoltage)))
;
1445 }
1446
1447 return result;
1448}
1449
1450static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1451 struct SMU74_Discrete_DpmTable *table)
1452{
1453 int result = 0;
1454 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1455
1456 table->GraphicsBootLevel = 0;
1457 table->MemoryBootLevel = 0;
1458
1459 /* find boot level from dpm table */
1460 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
Value stored to 'result' is never read
1461 data->vbios_boot_state.sclk_bootup_value,
1462 (uint32_t *)&(table->GraphicsBootLevel));
1463
1464 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1465 data->vbios_boot_state.mclk_bootup_value,
1466 (uint32_t *)&(table->MemoryBootLevel));
1467
1468 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1469 VOLTAGE_SCALE4;
1470 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1471 VOLTAGE_SCALE4;
1472 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1473 VOLTAGE_SCALE4;
1474
1475 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc)((table->BootVddc) = (__uint16_t)(__builtin_constant_p(table
->BootVddc) ? (__uint16_t)(((__uint16_t)(table->BootVddc
) & 0xffU) << 8 | ((__uint16_t)(table->BootVddc)
& 0xff00U) >> 8) : __swap16md(table->BootVddc))
)
;
1476 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci)((table->BootVddci) = (__uint16_t)(__builtin_constant_p(table
->BootVddci) ? (__uint16_t)(((__uint16_t)(table->BootVddci
) & 0xffU) << 8 | ((__uint16_t)(table->BootVddci
) & 0xff00U) >> 8) : __swap16md(table->BootVddci
)))
;
1477 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd)((table->BootMVdd) = (__uint16_t)(__builtin_constant_p(table
->BootMVdd) ? (__uint16_t)(((__uint16_t)(table->BootMVdd
) & 0xffU) << 8 | ((__uint16_t)(table->BootMVdd)
& 0xff00U) >> 8) : __swap16md(table->BootMVdd))
)
;
1478
1479 return 0;
1480}
1481
1482static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1483{
1484 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1485 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1486 struct phm_ppt_v1_information *table_info =
1487 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1488 uint8_t count, level;
1489
1490 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1491
1492 for (level = 0; level < count; level++) {
1493 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1494 hw_data->vbios_boot_state.sclk_bootup_value) {
1495 smu_data->smc_state_table.GraphicsBootLevel = level;
1496 break;
1497 }
1498 }
1499
1500 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1501 for (level = 0; level < count; level++) {
1502 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1503 hw_data->vbios_boot_state.mclk_bootup_value) {
1504 smu_data->smc_state_table.MemoryBootLevel = level;
1505 break;
1506 }
1507 }
1508
1509 return 0;
1510}
1511
1512static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1513{
1514 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1515 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1516
1517 uint8_t i, stretch_amount, volt_offset = 0;
1518 struct phm_ppt_v1_information *table_info =
1519 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1520 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1521 table_info->vdd_dep_on_sclk;
1522
1523 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1524
1525 /* Read SMU_Eefuse to read and calculate RO and determine
1526 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1527 */
1528 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0100000 + (67 * 4)))
1529 ixSMU_EFUSE_0 + (67 * 4))(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0100000 + (67 * 4)))
;
1530 efuse &= 0xFF000000;
1531 efuse = efuse >> 24;
1532
1533 if (hwmgr->chip_id == CHIP_POLARIS10) {
1534 if (hwmgr->is_kicker) {
1535 min = 1200;
1536 max = 2500;
1537 } else {
1538 min = 1000;
1539 max = 2300;
1540 }
1541 } else if (hwmgr->chip_id == CHIP_POLARIS11) {
1542 if (hwmgr->is_kicker) {
1543 min = 900;
1544 max = 2100;
1545 } else {
1546 min = 1100;
1547 max = 2100;
1548 }
1549 } else {
1550 min = 1100;
1551 max = 2100;
1552 }
1553
1554 ro = efuse * (max - min) / 255 + min;
1555
1556 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1557 for (i = 0; i < sclk_table->count; i++) {
1558 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1559 sclk_table->entries[i].cks_enable << i;
1560 if (hwmgr->chip_id == CHIP_POLARIS10) {
1561 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
1562 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1563 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1564 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1565 } else {
1566 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
1567 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1568 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1569 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1570 }
1571
1572 if (volt_without_cks >= volt_with_cks)
1573 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1574 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1575
1576 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1577 }
1578
1579 smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1580 /* Populate CKS Lookup Table */
1581 if (stretch_amount == 0 || stretch_amount > 5) {
1582 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1583 PHM_PlatformCaps_ClockStretcher);
1584 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Stretch Amount in PPTable not supported"
); return -22; } } while (0)
1585 "Stretch Amount in PPTable not supported",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Stretch Amount in PPTable not supported"
); return -22; } } while (0)
1586 return -EINVAL)do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "Stretch Amount in PPTable not supported"
); return -22; } } while (0)
;
1587 }
1588
1589 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL)(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0200350))
;
1590 value &= 0xFFFFFFFE;
1591 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0200350,value))
;
1592
1593 return 0;
1594}
1595
1596static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1597 struct SMU74_Discrete_DpmTable *table)
1598{
1599 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1600 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1601 uint16_t config;
1602
1603 config = VR_MERGED_WITH_VDDC0;
1604 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT8);
1605
1606 /* Set Vddc Voltage Controller */
1607 if (SMU7_VOLTAGE_CONTROL_BY_SVID20x2 == data->voltage_control) {
1608 config = VR_SVI2_PLANE_11;
1609 table->VRConfig |= config;
1610 } else {
1611 PP_ASSERT_WITH_CODE(false,do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "VDDC should be on SVI2 control in merged mode!"
); ; } } while (0)
1612 "VDDC should be on SVI2 control in merged mode!",do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "VDDC should be on SVI2 control in merged mode!"
); ; } } while (0)
1613 )do { if (!(0)) { printk("\0014" "amdgpu: " "%s\n", "VDDC should be on SVI2 control in merged mode!"
); ; } } while (0)
;
1614 }
1615 /* Set Vddci Voltage Controller */
1616 if (SMU7_VOLTAGE_CONTROL_BY_SVID20x2 == data->vddci_control) {
1617 config = VR_SVI2_PLANE_22; /* only in merged mode */
1618 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT16);
1619 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO0x1 == data->vddci_control) {
1620 config = VR_SMIO_PATTERN_13;
1621 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT16);
1622 } else {
1623 config = VR_STATIC_VOLTAGE5;
1624 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT16);
1625 }
1626 /* Set Mvdd Voltage Controller */
1627 if (SMU7_VOLTAGE_CONTROL_BY_SVID20x2 == data->mvdd_control) {
1628 config = VR_SVI2_PLANE_22;
1629 table->VRConfig |= (config << VRCONF_MVDD_SHIFT24);
1630 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,smu_data->smu7_data.soft_regs_start
+ __builtin_offsetof(SMU74_SoftRegisters, AllowMvddSwitch),0x1
))
1631 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,smu_data->smu7_data.soft_regs_start
+ __builtin_offsetof(SMU74_SoftRegisters, AllowMvddSwitch),0x1
))
;
1632 } else {
1633 config = VR_STATIC_VOLTAGE5;
1634 table->VRConfig |= (config << VRCONF_MVDD_SHIFT24);
1635 }
1636
1637 return 0;
1638}
1639
1640
1641static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1642{
1643 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1644 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1645 struct amdgpu_device *adev = hwmgr->adev;
1646
1647 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1648 int result = 0;
1649 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1650 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1651 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1652 uint32_t tmp, i;
1653
1654 struct phm_ppt_v1_information *table_info =
1655 (struct phm_ppt_v1_information *)hwmgr->pptable;
1656 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1657 table_info->vdd_dep_on_sclk;
1658
1659
1660 if (!hwmgr->avfs_supported)
1661 return 0;
1662
1663 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1664
1665 if (0 == result) {
1666 if (((adev->pdev->device == 0x67ef) &&
1667 ((adev->pdev->revision == 0xe0) ||
1668 (adev->pdev->revision == 0xe5))) ||
1669 ((adev->pdev->device == 0x67ff) &&
1670 ((adev->pdev->revision == 0xcf) ||
1671 (adev->pdev->revision == 0xef) ||
1672 (adev->pdev->revision == 0xff)))) {
1673 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1674 if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) ||
1675 (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) {
1676 if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) &&
1677 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) &&
1678 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) &&
1679 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) &&
1680 (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) &&
1681 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) {
1682 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF718F1D4;
1683 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x323FD;
1684 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x1E455;
1685 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1686 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0;
1687 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x23;
1688 }
1689 }
1690 } else if (hwmgr->chip_id == CHIP_POLARIS12 && !hwmgr->is_kicker) {
1691 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1692 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF6B024DD;
1693 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x3005E;
1694 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x18A5F;
1695 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
1696 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
1697 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x3B;
1698 } else if (((adev->pdev->device == 0x67df) &&
1699 ((adev->pdev->revision == 0xe0) ||
1700 (adev->pdev->revision == 0xe3) ||
1701 (adev->pdev->revision == 0xe4) ||
1702 (adev->pdev->revision == 0xe5) ||
1703 (adev->pdev->revision == 0xe7) ||
1704 (adev->pdev->revision == 0xef))) ||
1705 ((adev->pdev->device == 0x6fdf) &&
1706 ((adev->pdev->revision == 0xef) ||
1707 (adev->pdev->revision == 0xff)))) {
1708 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1709 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF843B66B;
1710 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x59CB5;
1711 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0xFFFF287F;
1712 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1713 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
1714 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x58;
1715 }
1716 }
1717
1718 if (0 == result) {
1719 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0)(__uint32_t)(__builtin_constant_p(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0
))
;
1720 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1)(__uint32_t)(__builtin_constant_p(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1
))
;
1721 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2)(__uint32_t)(__builtin_constant_p(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2
))
;
1722 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0)(__uint32_t)(__builtin_constant_p(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0
))
;
1723 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1)(__uint32_t)(__builtin_constant_p(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1
))
;
1724 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2)(__uint32_t)(__builtin_constant_p(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2
))
;
1725 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1)(__uint32_t)(__builtin_constant_p(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1
))
;
1726 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2)(__uint16_t)(__builtin_constant_p(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2
) ? (__uint16_t)(((__uint16_t)(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2
) & 0xffU) << 8 | ((__uint16_t)(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2
) & 0xff00U) >> 8) : __swap16md(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2
))
;
1727 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b)(__uint32_t)(__builtin_constant_p(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b
))
;
1728 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1729 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1730 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1)(__uint32_t)(__builtin_constant_p(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1
))
;
1731 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2)(__uint16_t)(__builtin_constant_p(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2
) ? (__uint16_t)(((__uint16_t)(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2
) & 0xffU) << 8 | ((__uint16_t)(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2
) & 0xff00U) >> 8) : __swap16md(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2
))
;
1732 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b)(__uint32_t)(__builtin_constant_p(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b
))
;
1733 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1734 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1735 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv)(__uint16_t)(__builtin_constant_p(avfs_params.usMaxVoltage_0_25mv
) ? (__uint16_t)(((__uint16_t)(avfs_params.usMaxVoltage_0_25mv
) & 0xffU) << 8 | ((__uint16_t)(avfs_params.usMaxVoltage_0_25mv
) & 0xff00U) >> 8) : __swap16md(avfs_params.usMaxVoltage_0_25mv
))
;
1736 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0)(__uint32_t)(__builtin_constant_p(avfs_params.ulAVFS_meanNsigma_Acontant0
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant0
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant0
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant0
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant0
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulAVFS_meanNsigma_Acontant0
))
;
1737 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1)(__uint32_t)(__builtin_constant_p(avfs_params.ulAVFS_meanNsigma_Acontant1
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant1
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant1
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant1
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant1
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulAVFS_meanNsigma_Acontant1
))
;
1738 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2)(__uint32_t)(__builtin_constant_p(avfs_params.ulAVFS_meanNsigma_Acontant2
) ? (__uint32_t)(((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant2
) & 0xff) << 24 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant2
) & 0xff00) << 8 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant2
) & 0xff0000) >> 8 | ((__uint32_t)(avfs_params.ulAVFS_meanNsigma_Acontant2
) & 0xff000000) >> 24) : __swap32md(avfs_params.ulAVFS_meanNsigma_Acontant2
))
;
1739 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma)(__uint16_t)(__builtin_constant_p(avfs_params.usAVFS_meanNsigma_DC_tol_sigma
) ? (__uint16_t)(((__uint16_t)(avfs_params.usAVFS_meanNsigma_DC_tol_sigma
) & 0xffU) << 8 | ((__uint16_t)(avfs_params.usAVFS_meanNsigma_DC_tol_sigma
) & 0xff00U) >> 8) : __swap16md(avfs_params.usAVFS_meanNsigma_DC_tol_sigma
))
;
1740 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean)(__uint16_t)(__builtin_constant_p(avfs_params.usAVFS_meanNsigma_Platform_mean
) ? (__uint16_t)(((__uint16_t)(avfs_params.usAVFS_meanNsigma_Platform_mean
) & 0xffU) << 8 | ((__uint16_t)(avfs_params.usAVFS_meanNsigma_Platform_mean
) & 0xff00U) >> 8) : __swap16md(avfs_params.usAVFS_meanNsigma_Platform_mean
))
;
1741 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor)(__uint16_t)(__builtin_constant_p(avfs_params.usPSM_Age_ComFactor
) ? (__uint16_t)(((__uint16_t)(avfs_params.usPSM_Age_ComFactor
) & 0xffU) << 8 | ((__uint16_t)(avfs_params.usPSM_Age_ComFactor
) & 0xff00U) >> 8) : __swap16md(avfs_params.usPSM_Age_ComFactor
))
;
1742 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma)(__uint16_t)(__builtin_constant_p(avfs_params.usAVFS_meanNsigma_Platform_sigma
) ? (__uint16_t)(((__uint16_t)(avfs_params.usAVFS_meanNsigma_Platform_sigma
) & 0xffU) << 8 | ((__uint16_t)(avfs_params.usAVFS_meanNsigma_Platform_sigma
) & 0xff00U) >> 8) : __swap16md(avfs_params.usAVFS_meanNsigma_Platform_sigma
))
;
1743
1744 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1745 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1746 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100)(__uint16_t)(__builtin_constant_p((uint16_t)(sclk_table->entries
[i].sclk_offset) / 100) ? (__uint16_t)(((__uint16_t)((uint16_t
)(sclk_table->entries[i].sclk_offset) / 100) & 0xffU) <<
8 | ((__uint16_t)((uint16_t)(sclk_table->entries[i].sclk_offset
) / 100) & 0xff00U) >> 8) : __swap16md((uint16_t)(sclk_table
->entries[i].sclk_offset) / 100))
;
1747 }
1748
1749 result = smu7_read_smc_sram_dword(hwmgr,
1750 SMU7_FIRMWARE_HEADER_LOCATION0x20000 + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma)__builtin_offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1751 &tmp, SMC_RAM_END0x40000);
1752
1753 smu7_copy_bytes_to_smc(hwmgr,
1754 tmp,
1755 (uint8_t *)&AVFS_meanNsigma,
1756 sizeof(AVFS_meanNsigma_t),
1757 SMC_RAM_END0x40000);
1758
1759 result = smu7_read_smc_sram_dword(hwmgr,
1760 SMU7_FIRMWARE_HEADER_LOCATION0x20000 + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable)__builtin_offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable
)
,
1761 &tmp, SMC_RAM_END0x40000);
1762 smu7_copy_bytes_to_smc(hwmgr,
1763 tmp,
1764 (uint8_t *)&AVFS_SclkOffset,
1765 sizeof(AVFS_Sclk_Offset_t),
1766 SMC_RAM_END0x40000);
1767
1768 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT0) |
1769 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT1) |
1770 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT2) |
1771 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT3);
1772 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true1 : false0;
1773 }
1774 return result;
1775}
1776
1777static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
1778{
1779 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1780 uint32_t tmp;
1781 int result;
1782
1783 /* This is a read-modify-write on the first byte of the ARB table.
1784 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
1785 * is the field 'current'.
1786 * This solution is ugly, but we never write the whole table only
1787 * individual fields in it.
1788 * In reality this field should not be in that structure
1789 * but in a soft register.
1790 */
1791 result = smu7_read_smc_sram_dword(hwmgr,
1792 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END0x40000);
1793
1794 if (result)
1795 return result;
1796
1797 tmp &= 0x00FFFFFF;
1798 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F10x0b) << 24;
1799
1800 return smu7_write_smc_sram_dword(hwmgr,
1801 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END0x40000);
1802}
1803
1804static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1805{
1806 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1807 struct phm_ppt_v1_information *table_info =
1808 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1809
1810 if (table_info &&
1811 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX1 &&
1812 table_info->cac_dtp_table->usPowerTuneDataSetID)
1813 smu_data->power_tune_defaults =
1814 &polaris10_power_tune_data_set_array
1815 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
1816 else
1817 smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
1818
1819}
1820
1821static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1822{
1823 int result;
1824 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1825 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1826
1827 struct phm_ppt_v1_information *table_info =
1828 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1829 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1830 uint8_t i;
1831 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1832 pp_atomctrl_clock_dividers_vi dividers;
1833
1834 polaris10_initialize_power_tune_defaults(hwmgr);
1835
1836 if (SMU7_VOLTAGE_CONTROL_NONE0x0 != hw_data->voltage_control)
1837 polaris10_populate_smc_voltage_tables(hwmgr, table);
1838
1839 table->SystemFlags = 0;
1840 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1841 PHM_PlatformCaps_AutomaticDCTransition))
1842 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC0x01;
1843
1844 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1845 PHM_PlatformCaps_StepVddc))
1846 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC0x02;
1847
1848 if (hw_data->is_memory_gddr5)
1849 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR50x04;
1850
1851 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1852 result = polaris10_populate_ulv_state(hwmgr, table);
1853 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize ULV state!"
); return result; } } while (0)
1854 "Failed to initialize ULV state!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize ULV state!"
); return result; } } while (0)
;
1855 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc020015c,0x00040035))
1856 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc020015c,0x00040035))
;
1857 }
1858
1859 result = polaris10_populate_smc_link_level(hwmgr, table);
1860 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Link Level!"
); return result; } } while (0)
1861 "Failed to initialize Link Level!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Link Level!"
); return result; } } while (0)
;
1862
1863 result = polaris10_populate_all_graphic_levels(hwmgr);
1864 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Graphics Level!"
); return result; } } while (0)
1865 "Failed to initialize Graphics Level!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Graphics Level!"
); return result; } } while (0)
;
1866
1867 result = polaris10_populate_all_memory_levels(hwmgr);
1868 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Memory Level!"
); return result; } } while (0)
1869 "Failed to initialize Memory Level!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Memory Level!"
); return result; } } while (0)
;
1870
1871 result = polaris10_populate_smc_acpi_level(hwmgr, table);
1872 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize ACPI Level!"
); return result; } } while (0)
1873 "Failed to initialize ACPI Level!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize ACPI Level!"
); return result; } } while (0)
;
1874
1875 result = polaris10_populate_smc_vce_level(hwmgr, table);
1876 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize VCE Level!"
); return result; } } while (0)
1877 "Failed to initialize VCE Level!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize VCE Level!"
); return result; } } while (0)
;
1878
1879 /* Since only the initial state is completely set up at this point
1880 * (the other states are just copies of the boot state) we only
1881 * need to populate the ARB settings for the initial state.
1882 */
1883 result = polaris10_program_memory_timing_parameters(hwmgr);
1884 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to Write ARB settings for the initial state."
); return result; } } while (0)
1885 "Failed to Write ARB settings for the initial state.", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to Write ARB settings for the initial state."
); return result; } } while (0)
;
1886
1887 result = polaris10_populate_smc_uvd_level(hwmgr, table);
1888 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize UVD Level!"
); return result; } } while (0)
1889 "Failed to initialize UVD Level!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize UVD Level!"
); return result; } } while (0)
;
1890
1891 result = polaris10_populate_smc_boot_level(hwmgr, table);
1892 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Boot Level!"
); return result; } } while (0)
1893 "Failed to initialize Boot Level!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Boot Level!"
); return result; } } while (0)
;
1894
1895 result = polaris10_populate_smc_initailial_state(hwmgr);
1896 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Boot State!"
); return result; } } while (0)
1897 "Failed to initialize Boot State!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to initialize Boot State!"
); return result; } } while (0)
;
1898
1899 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
1900 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate BAPM Parameters!"
); return result; } } while (0)
1901 "Failed to populate BAPM Parameters!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate BAPM Parameters!"
); return result; } } while (0)
;
1902
1903 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1904 PHM_PlatformCaps_ClockStretcher)) {
1905 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
1906 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate Clock Stretcher Data Table!"
); return result; } } while (0)
1907 "Failed to populate Clock Stretcher Data Table!",do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate Clock Stretcher Data Table!"
); return result; } } while (0)
1908 return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate Clock Stretcher Data Table!"
); return result; } } while (0)
;
1909 }
1910
1911 result = polaris10_populate_avfs_parameters(hwmgr);
1912 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate AVFS Parameters!"
); return result;; } } while (0)
;
1913
1914 table->CurrSclkPllRange = 0xff;
1915 table->GraphicsVoltageChangeEnable = 1;
1916 table->GraphicsThermThrottleEnable = 1;
1917 table->GraphicsInterval = 1;
1918 table->VoltageInterval = 1;
1919 table->ThermalInterval = 1;
1920 table->TemperatureLimitHigh =
1921 table_info->cac_dtp_table->usTargetOperatingTemp *
1922 SMU7_Q88_FORMAT_CONVERSION_UNIT256;
1923 table->TemperatureLimitLow =
1924 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
1925 SMU7_Q88_FORMAT_CONVERSION_UNIT256;
1926 table->MemoryVoltageChangeEnable = 1;
1927 table->MemoryInterval = 1;
1928 table->VoltageResponseTime = 0;
1929 table->PhaseResponseTime = 0;
1930 table->MemoryThermThrottleEnable = 1;
1931 table->PCIeBootLinkLevel = 0;
1932 table->PCIeGenInterval = 1;
1933 table->VRConfig = 0;
1934
1935 result = polaris10_populate_vr_config(hwmgr, table);
1936 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate VRConfig setting!"
); return result; } } while (0)
1937 "Failed to populate VRConfig setting!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate VRConfig setting!"
); return result; } } while (0)
;
1938 hw_data->vr_config = table->VRConfig;
1939 table->ThermGpio = 17;
1940 table->SclkStepSize = 0x4000;
1941
1942 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID61, &gpio_pin)) {
1943 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
1944 } else {
1945 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN0x7F;
1946 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1947 PHM_PlatformCaps_RegulatorHot);
1948 }
1949
1950 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID60,
1951 &gpio_pin)) {
1952 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
1953 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1954 PHM_PlatformCaps_AutomaticDCTransition);
1955 } else {
1956 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN0x7F;
1957 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1958 PHM_PlatformCaps_AutomaticDCTransition);
1959 }
1960
1961 /* Thermal Output GPIO */
1962 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID65,
1963 &gpio_pin)) {
1964 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1965 PHM_PlatformCaps_ThermalOutGPIO);
1966
1967 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
1968
1969 /* For porlarity read GPIOPAD_A with assigned Gpio pin
1970 * since VBIOS will program this register to set 'inactive state',
1971 * driver can then determine 'active state' from this and
1972 * program SMU with correct polarity
1973 */
1974 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)(((struct cgs_device *)hwmgr->device)->ops->read_register
(hwmgr->device,0x183))
1975 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
1976 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY0x1;
1977
1978 /* if required, combine VRHot/PCC with thermal out GPIO */
1979 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
1980 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
1981 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT0x2;
1982 } else {
1983 table->ThermOutGpio = 17;
1984 table->ThermOutPolarity = 1;
1985 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE0x0;
1986 }
1987
1988 /* Populate BIF_SCLK levels into SMC DPM table */
1989 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
1990 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
1991 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Can not find DFS divide id for Sclk"); return result; } } while
(0)
;
1992
1993 if (i == 0)
1994 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider))(__uint16_t)(__builtin_constant_p((USHORT)(dividers.pll_post_divider
)) ? (__uint16_t)(((__uint16_t)((USHORT)(dividers.pll_post_divider
)) & 0xffU) << 8 | ((__uint16_t)((USHORT)(dividers.
pll_post_divider)) & 0xff00U) >> 8) : __swap16md((USHORT
)(dividers.pll_post_divider)))
;
1995 else
1996 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider))(__uint16_t)(__builtin_constant_p((USHORT)(dividers.pll_post_divider
)) ? (__uint16_t)(((__uint16_t)((USHORT)(dividers.pll_post_divider
)) & 0xffU) << 8 | ((__uint16_t)((USHORT)(dividers.
pll_post_divider)) & 0xff00U) >> 8) : __swap16md((USHORT
)(dividers.pll_post_divider)))
;
1997 }
1998
1999 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO32; i++)
2000 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i])(__uint32_t)(__builtin_constant_p(table->Smio[i]) ? (__uint32_t
)(((__uint32_t)(table->Smio[i]) & 0xff) << 24 | (
(__uint32_t)(table->Smio[i]) & 0xff00) << 8 | ((
__uint32_t)(table->Smio[i]) & 0xff0000) >> 8 | (
(__uint32_t)(table->Smio[i]) & 0xff000000) >> 24
) : __swap32md(table->Smio[i]))
;
2001
2002 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags)((table->SystemFlags) = (__uint32_t)(__builtin_constant_p(
table->SystemFlags) ? (__uint32_t)(((__uint32_t)(table->
SystemFlags) & 0xff) << 24 | ((__uint32_t)(table->
SystemFlags) & 0xff00) << 8 | ((__uint32_t)(table->
SystemFlags) & 0xff0000) >> 8 | ((__uint32_t)(table
->SystemFlags) & 0xff000000) >> 24) : __swap32md
(table->SystemFlags)))
;
2003 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig)((table->VRConfig) = (__uint32_t)(__builtin_constant_p(table
->VRConfig) ? (__uint32_t)(((__uint32_t)(table->VRConfig
) & 0xff) << 24 | ((__uint32_t)(table->VRConfig)
& 0xff00) << 8 | ((__uint32_t)(table->VRConfig)
& 0xff0000) >> 8 | ((__uint32_t)(table->VRConfig
) & 0xff000000) >> 24) : __swap32md(table->VRConfig
)))
;
2004 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1)((table->SmioMask1) = (__uint32_t)(__builtin_constant_p(table
->SmioMask1) ? (__uint32_t)(((__uint32_t)(table->SmioMask1
) & 0xff) << 24 | ((__uint32_t)(table->SmioMask1
) & 0xff00) << 8 | ((__uint32_t)(table->SmioMask1
) & 0xff0000) >> 8 | ((__uint32_t)(table->SmioMask1
) & 0xff000000) >> 24) : __swap32md(table->SmioMask1
)))
;
2005 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2)((table->SmioMask2) = (__uint32_t)(__builtin_constant_p(table
->SmioMask2) ? (__uint32_t)(((__uint32_t)(table->SmioMask2
) & 0xff) << 24 | ((__uint32_t)(table->SmioMask2
) & 0xff00) << 8 | ((__uint32_t)(table->SmioMask2
) & 0xff0000) >> 8 | ((__uint32_t)(table->SmioMask2
) & 0xff000000) >> 24) : __swap32md(table->SmioMask2
)))
;
2006 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize)((table->SclkStepSize) = (__uint32_t)(__builtin_constant_p
(table->SclkStepSize) ? (__uint32_t)(((__uint32_t)(table->
SclkStepSize) & 0xff) << 24 | ((__uint32_t)(table->
SclkStepSize) & 0xff00) << 8 | ((__uint32_t)(table->
SclkStepSize) & 0xff0000) >> 8 | ((__uint32_t)(table
->SclkStepSize) & 0xff000000) >> 24) : __swap32md
(table->SclkStepSize)))
;
2007 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange)((table->CurrSclkPllRange) = (__uint32_t)(__builtin_constant_p
(table->CurrSclkPllRange) ? (__uint32_t)(((__uint32_t)(table
->CurrSclkPllRange) & 0xff) << 24 | ((__uint32_t
)(table->CurrSclkPllRange) & 0xff00) << 8 | ((__uint32_t
)(table->CurrSclkPllRange) & 0xff0000) >> 8 | ((
__uint32_t)(table->CurrSclkPllRange) & 0xff000000) >>
24) : __swap32md(table->CurrSclkPllRange)))
;
2008 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh)((table->TemperatureLimitHigh) = (__uint16_t)(__builtin_constant_p
(table->TemperatureLimitHigh) ? (__uint16_t)(((__uint16_t)
(table->TemperatureLimitHigh) & 0xffU) << 8 | ((
__uint16_t)(table->TemperatureLimitHigh) & 0xff00U) >>
8) : __swap16md(table->TemperatureLimitHigh)))
;
2009 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow)((table->TemperatureLimitLow) = (__uint16_t)(__builtin_constant_p
(table->TemperatureLimitLow) ? (__uint16_t)(((__uint16_t)(
table->TemperatureLimitLow) & 0xffU) << 8 | ((__uint16_t
)(table->TemperatureLimitLow) & 0xff00U) >> 8) :
__swap16md(table->TemperatureLimitLow)))
;
2010 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime)((table->VoltageResponseTime) = (__uint16_t)(__builtin_constant_p
(table->VoltageResponseTime) ? (__uint16_t)(((__uint16_t)(
table->VoltageResponseTime) & 0xffU) << 8 | ((__uint16_t
)(table->VoltageResponseTime) & 0xff00U) >> 8) :
__swap16md(table->VoltageResponseTime)))
;
2011 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime)((table->PhaseResponseTime) = (__uint16_t)(__builtin_constant_p
(table->PhaseResponseTime) ? (__uint16_t)(((__uint16_t)(table
->PhaseResponseTime) & 0xffU) << 8 | ((__uint16_t
)(table->PhaseResponseTime) & 0xff00U) >> 8) : __swap16md
(table->PhaseResponseTime)))
;
2012
2013 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2014 result = smu7_copy_bytes_to_smc(hwmgr,
2015 smu_data->smu7_data.dpm_table_start +
2016 offsetof(SMU74_Discrete_DpmTable, SystemFlags)__builtin_offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2017 (uint8_t *)&(table->SystemFlags),
2018 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2019 SMC_RAM_END0x40000);
2020 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to upload dpm data to SMC memory!"
); return result; } } while (0)
2021 "Failed to upload dpm data to SMC memory!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to upload dpm data to SMC memory!"
); return result; } } while (0)
;
2022
2023 result = polaris10_init_arb_table_index(hwmgr);
2024 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to upload arb data to SMC memory!"
); return result; } } while (0)
2025 "Failed to upload arb data to SMC memory!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to upload arb data to SMC memory!"
); return result; } } while (0)
;
2026
2027 result = polaris10_populate_pm_fuses(hwmgr);
2028 PP_ASSERT_WITH_CODE(0 == result,do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate PM fuses to SMC memory!"
); return result; } } while (0)
2029 "Failed to populate PM fuses to SMC memory!", return result)do { if (!(0 == result)) { printk("\0014" "amdgpu: " "%s\n", "Failed to populate PM fuses to SMC memory!"
); return result; } } while (0)
;
2030
2031 return 0;
2032}
2033
2034static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2035{
2036 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2037
2038 if (data->need_update_smu7_dpm_table &
2039 (DPMTABLE_OD_UPDATE_SCLK0x00000001 + DPMTABLE_OD_UPDATE_MCLK0x00000002))
2040 return polaris10_program_memory_timing_parameters(hwmgr);
2041
2042 return 0;
2043}
2044
2045int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2046{
2047 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2048
2049 if (!hwmgr->avfs_supported)
2050 return 0;
2051
2052 smum_send_msg_to_smc_with_parameter(hwmgr,
2053 PPSMC_MSG_SetGBDroopSettings((uint16_t) 0x305), data->avfs_vdroop_override_setting,
2054 NULL((void *)0));
2055
2056 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs((uint16_t) 0x26A), NULL((void *)0));
2057
2058 /* Apply avfs cks-off voltages to avoid the overshoot
2059 * when switching to the highest sclk frequency
2060 */
2061 if (data->apply_avfs_cks_off_voltage)
2062 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage((uint16_t) 0x415), NULL((void *)0));
2063
2064 return 0;
2065}
2066
2067static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2068{
2069 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2070 SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE0 };
2071 uint32_t duty100;
2072 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2073 uint16_t fdo_min, slope1, slope2;
2074 uint32_t reference_clock;
2075 int res;
2076 uint64_t tmp64;
2077
2078 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2079 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2080 PHM_PlatformCaps_MicrocodeFanControl);
2081 return 0;
2082 }
2083
2084 if (smu_data->smu7_data.fan_table_start == 0) {
2085 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2086 PHM_PlatformCaps_MicrocodeFanControl);
2087 return 0;
2088 }
2089
2090 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0300068))) & 0xff) >>
0x0)
2091 CG_FDO_CTRL1, FMAX_DUTY100)((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0300068))) & 0xff) >>
0x0)
;
2092
2093 if (duty100 == 0) {
2094 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2095 PHM_PlatformCaps_MicrocodeFanControl);
2096 return 0;
2097 }
2098
2099 /* use hardware fan control */
2100 if (hwmgr->thermal_controller.use_hw_fan_control)
2101 return 0;
2102
2103 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2104 usPWMMin * duty100;
2105 do_div(tmp64, 10000)({ uint32_t __base = (10000); uint32_t __rem = ((uint64_t)(tmp64
)) % __base; (tmp64) = ((uint64_t)(tmp64)) / __base; __rem; }
)
;
2106 fdo_min = (uint16_t)tmp64;
2107
2108 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2109 hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2110 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2111 hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2112
2113 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2114 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2115 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2116 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2117
2118 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2119 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2120
2121 fan_table.TempMin = cpu_to_be16((50 + hwmgr->(__uint16_t)(__builtin_constant_p((50 + hwmgr-> thermal_controller
.advanceFanControlParameters.usTMin) / 100) ? (__uint16_t)(((
__uint16_t)((50 + hwmgr-> thermal_controller.advanceFanControlParameters
.usTMin) / 100) & 0xffU) << 8 | ((__uint16_t)((50 +
hwmgr-> thermal_controller.advanceFanControlParameters.usTMin
) / 100) & 0xff00U) >> 8) : __swap16md((50 + hwmgr->
thermal_controller.advanceFanControlParameters.usTMin) / 100
))
2122 thermal_controller.advanceFanControlParameters.usTMin) / 100)(__uint16_t)(__builtin_constant_p((50 + hwmgr-> thermal_controller
.advanceFanControlParameters.usTMin) / 100) ? (__uint16_t)(((
__uint16_t)((50 + hwmgr-> thermal_controller.advanceFanControlParameters
.usTMin) / 100) & 0xffU) << 8 | ((__uint16_t)((50 +
hwmgr-> thermal_controller.advanceFanControlParameters.usTMin
) / 100) & 0xff00U) >> 8) : __swap16md((50 + hwmgr->
thermal_controller.advanceFanControlParameters.usTMin) / 100
))
;
2123 fan_table.TempMed = cpu_to_be16((50 + hwmgr->(__uint16_t)(__builtin_constant_p((50 + hwmgr-> thermal_controller
.advanceFanControlParameters.usTMed) / 100) ? (__uint16_t)(((
__uint16_t)((50 + hwmgr-> thermal_controller.advanceFanControlParameters
.usTMed) / 100) & 0xffU) << 8 | ((__uint16_t)((50 +
hwmgr-> thermal_controller.advanceFanControlParameters.usTMed
) / 100) & 0xff00U) >> 8) : __swap16md((50 + hwmgr->
thermal_controller.advanceFanControlParameters.usTMed) / 100
))
2124 thermal_controller.advanceFanControlParameters.usTMed) / 100)(__uint16_t)(__builtin_constant_p((50 + hwmgr-> thermal_controller
.advanceFanControlParameters.usTMed) / 100) ? (__uint16_t)(((
__uint16_t)((50 + hwmgr-> thermal_controller.advanceFanControlParameters
.usTMed) / 100) & 0xffU) << 8 | ((__uint16_t)((50 +
hwmgr-> thermal_controller.advanceFanControlParameters.usTMed
) / 100) & 0xff00U) >> 8) : __swap16md((50 + hwmgr->
thermal_controller.advanceFanControlParameters.usTMed) / 100
))
;
2125 fan_table.TempMax = cpu_to_be16((50 + hwmgr->(__uint16_t)(__builtin_constant_p((50 + hwmgr-> thermal_controller
.advanceFanControlParameters.usTMax) / 100) ? (__uint16_t)(((
__uint16_t)((50 + hwmgr-> thermal_controller.advanceFanControlParameters
.usTMax) / 100) & 0xffU) << 8 | ((__uint16_t)((50 +
hwmgr-> thermal_controller.advanceFanControlParameters.usTMax
) / 100) & 0xff00U) >> 8) : __swap16md((50 + hwmgr->
thermal_controller.advanceFanControlParameters.usTMax) / 100
))
2126 thermal_controller.advanceFanControlParameters.usTMax) / 100)(__uint16_t)(__builtin_constant_p((50 + hwmgr-> thermal_controller
.advanceFanControlParameters.usTMax) / 100) ? (__uint16_t)(((
__uint16_t)((50 + hwmgr-> thermal_controller.advanceFanControlParameters
.usTMax) / 100) & 0xffU) << 8 | ((__uint16_t)((50 +
hwmgr-> thermal_controller.advanceFanControlParameters.usTMax
) / 100) & 0xff00U) >> 8) : __swap16md((50 + hwmgr->
thermal_controller.advanceFanControlParameters.usTMax) / 100
))
;
2127
2128 fan_table.Slope1 = cpu_to_be16(slope1)(__uint16_t)(__builtin_constant_p(slope1) ? (__uint16_t)(((__uint16_t
)(slope1) & 0xffU) << 8 | ((__uint16_t)(slope1) &
0xff00U) >> 8) : __swap16md(slope1))
;
2129 fan_table.Slope2 = cpu_to_be16(slope2)(__uint16_t)(__builtin_constant_p(slope2) ? (__uint16_t)(((__uint16_t
)(slope2) & 0xffU) << 8 | ((__uint16_t)(slope2) &
0xff00U) >> 8) : __swap16md(slope2))
;
2130
2131 fan_table.FdoMin = cpu_to_be16(fdo_min)(__uint16_t)(__builtin_constant_p(fdo_min) ? (__uint16_t)(((__uint16_t
)(fdo_min) & 0xffU) << 8 | ((__uint16_t)(fdo_min) &
0xff00U) >> 8) : __swap16md(fdo_min))
;
2132
2133 fan_table.HystDown = cpu_to_be16(hwmgr->(__uint16_t)(__builtin_constant_p(hwmgr-> thermal_controller
.advanceFanControlParameters.ucTHyst) ? (__uint16_t)(((__uint16_t
)(hwmgr-> thermal_controller.advanceFanControlParameters.ucTHyst
) & 0xffU) << 8 | ((__uint16_t)(hwmgr-> thermal_controller
.advanceFanControlParameters.ucTHyst) & 0xff00U) >>
8) : __swap16md(hwmgr-> thermal_controller.advanceFanControlParameters
.ucTHyst))
2134 thermal_controller.advanceFanControlParameters.ucTHyst)(__uint16_t)(__builtin_constant_p(hwmgr-> thermal_controller
.advanceFanControlParameters.ucTHyst) ? (__uint16_t)(((__uint16_t
)(hwmgr-> thermal_controller.advanceFanControlParameters.ucTHyst
) & 0xffU) << 8 | ((__uint16_t)(hwmgr-> thermal_controller
.advanceFanControlParameters.ucTHyst) & 0xff00U) >>
8) : __swap16md(hwmgr-> thermal_controller.advanceFanControlParameters
.ucTHyst))
;
2135
2136 fan_table.HystUp = cpu_to_be16(1)(__uint16_t)(__builtin_constant_p(1) ? (__uint16_t)(((__uint16_t
)(1) & 0xffU) << 8 | ((__uint16_t)(1) & 0xff00U
) >> 8) : __swap16md(1))
;
2137
2138 fan_table.HystSlope = cpu_to_be16(1)(__uint16_t)(__builtin_constant_p(1) ? (__uint16_t)(((__uint16_t
)(1) & 0xffU) << 8 | ((__uint16_t)(1) & 0xff00U
) >> 8) : __swap16md(1))
;
2139
2140 fan_table.TempRespLim = cpu_to_be16(5)(__uint16_t)(__builtin_constant_p(5) ? (__uint16_t)(((__uint16_t
)(5) & 0xffU) << 8 | ((__uint16_t)(5) & 0xff00U
) >> 8) : __swap16md(5))
;
2141
2142 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev)((struct amdgpu_device *)hwmgr->adev)->asic_funcs->get_xclk
(((struct amdgpu_device *)hwmgr->adev))
;
2143
2144 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->(__uint32_t)(__builtin_constant_p((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) ? (__uint32_t)(((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff) << 24 | ((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff00) << 8 | ((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff0000) >> 8 | ((__uint32_t)((hwmgr->
thermal_controller.advanceFanControlParameters.ulCycleDelay *
reference_clock) / 1600) & 0xff000000) >> 24) : __swap32md
((hwmgr-> thermal_controller.advanceFanControlParameters.ulCycleDelay
* reference_clock) / 1600))
2145 thermal_controller.advanceFanControlParameters.ulCycleDelay *(__uint32_t)(__builtin_constant_p((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) ? (__uint32_t)(((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff) << 24 | ((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff00) << 8 | ((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff0000) >> 8 | ((__uint32_t)((hwmgr->
thermal_controller.advanceFanControlParameters.ulCycleDelay *
reference_clock) / 1600) & 0xff000000) >> 24) : __swap32md
((hwmgr-> thermal_controller.advanceFanControlParameters.ulCycleDelay
* reference_clock) / 1600))
2146 reference_clock) / 1600)(__uint32_t)(__builtin_constant_p((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) ? (__uint32_t)(((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff) << 24 | ((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff00) << 8 | ((__uint32_t)((hwmgr-> thermal_controller
.advanceFanControlParameters.ulCycleDelay * reference_clock) /
1600) & 0xff0000) >> 8 | ((__uint32_t)((hwmgr->
thermal_controller.advanceFanControlParameters.ulCycleDelay *
reference_clock) / 1600) & 0xff000000) >> 24) : __swap32md
((hwmgr-> thermal_controller.advanceFanControlParameters.ulCycleDelay
* reference_clock) / 1600))
;
2147
2148 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100)(__uint16_t)(__builtin_constant_p((uint16_t)duty100) ? (__uint16_t
)(((__uint16_t)((uint16_t)duty100) & 0xffU) << 8 | (
(__uint16_t)((uint16_t)duty100) & 0xff00U) >> 8) : __swap16md
((uint16_t)duty100))
;
2149
2150 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0300010))) & 0xff00000
) >> 0x14)
2151 hwmgr->device, CGS_IND_REG__SMC,((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0300010))) & 0xff00000
) >> 0x14)
2152 CG_MULT_THERMAL_CTRL, TEMP_SEL)((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0xc0300010))) & 0xff00000
) >> 0x14)
;
2153
2154 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2155 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2156 SMC_RAM_END0x40000);
2157
2158 if (!res && hwmgr->thermal_controller.
2159 advanceFanControlParameters.ucMinimumPWMLimit)
2160 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2161 PPSMC_MSG_SetFanMinPwm((uint16_t) 0x209),
2162 hwmgr->thermal_controller.
2163 advanceFanControlParameters.ucMinimumPWMLimit,
2164 NULL((void *)0));
2165
2166 if (!res && hwmgr->thermal_controller.
2167 advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2168 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2169 PPSMC_MSG_SetFanSclkTarget((uint16_t) 0x206),
2170 hwmgr->thermal_controller.
2171 advanceFanControlParameters.ulMinFanSCLKAcousticLimit,
2172 NULL((void *)0));
2173
2174 if (res)
2175 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2176 PHM_PlatformCaps_MicrocodeFanControl);
2177
2178 return 0;
2179}
2180
2181static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2182{
2183 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2184 uint32_t mm_boot_level_offset, mm_boot_level_value;
2185 struct phm_ppt_v1_information *table_info =
2186 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2187
2188 smu_data->smc_state_table.UvdBootLevel = 0;
2189 if (table_info->mm_dep_table->count > 0)
2190 smu_data->smc_state_table.UvdBootLevel =
2191 (uint8_t) (table_info->mm_dep_table->count - 1);
2192 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,__builtin_offsetof(SMU74_Discrete_DpmTable, UvdBootLevel)
2193 UvdBootLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2194 mm_boot_level_offset /= 4;
2195 mm_boot_level_offset *= 4;
2196 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,mm_boot_level_offset))
2197 CGS_IND_REG__SMC, mm_boot_level_offset)(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,mm_boot_level_offset))
;
2198 mm_boot_level_value &= 0x00FFFFFF;
2199 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2200 cgs_write_ind_register(hwmgr->device,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,mm_boot_level_offset,mm_boot_level_value
))
2201 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,mm_boot_level_offset,mm_boot_level_value
))
;
2202
2203 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2204 PHM_PlatformCaps_UVDDPM) ||
2205 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2206 PHM_PlatformCaps_StablePState))
2207 smum_send_msg_to_smc_with_parameter(hwmgr,
2208 PPSMC_MSG_UVDDPM_SetEnabledMask((uint16_t) 0x12D),
2209 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2210 NULL((void *)0));
2211 return 0;
2212}
2213
2214static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2215{
2216 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2217 uint32_t mm_boot_level_offset, mm_boot_level_value;
2218 struct phm_ppt_v1_information *table_info =
2219 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2220
2221 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2222 PHM_PlatformCaps_StablePState))
2223 smu_data->smc_state_table.VceBootLevel =
2224 (uint8_t) (table_info->mm_dep_table->count - 1);
2225 else
2226 smu_data->smc_state_table.VceBootLevel = 0;
2227
2228 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2229 offsetof(SMU74_Discrete_DpmTable, VceBootLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2230 mm_boot_level_offset /= 4;
2231 mm_boot_level_offset *= 4;
2232 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,mm_boot_level_offset))
2233 CGS_IND_REG__SMC, mm_boot_level_offset)(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,mm_boot_level_offset))
;
2234 mm_boot_level_value &= 0xFF00FFFF;
2235 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2236 cgs_write_ind_register(hwmgr->device,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,mm_boot_level_offset,mm_boot_level_value
))
2237 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,mm_boot_level_offset,mm_boot_level_value
))
;
2238
2239 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2240 smum_send_msg_to_smc_with_parameter(hwmgr,
2241 PPSMC_MSG_VCEDPM_SetEnabledMask((uint16_t) 0x12E),
2242 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
2243 NULL((void *)0));
2244 return 0;
2245}
2246
2247static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2248{
2249 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2250 struct phm_ppt_v1_information *table_info =
2251 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2252 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2253 int max_entry, i;
2254
2255 max_entry = (SMU74_MAX_LEVELS_LINK8 < pcie_table->count) ?
2256 SMU74_MAX_LEVELS_LINK8 :
2257 pcie_table->count;
2258 /* Setup BIF_SCLK levels */
2259 for (i = 0; i < max_entry; i++)
2260 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
2261 return 0;
2262}
2263
2264static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2265{
2266 switch (type) {
2267 case SMU_UVD_TABLE:
2268 polaris10_update_uvd_smc_table(hwmgr);
2269 break;
2270 case SMU_VCE_TABLE:
2271 polaris10_update_vce_smc_table(hwmgr);
2272 break;
2273 case SMU_BIF_TABLE:
2274 polaris10_update_bif_smc_table(hwmgr);
2275 default:
2276 break;
2277 }
2278 return 0;
2279}
2280
2281static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2282{
2283 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2284 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2285
2286 int result = 0;
2287 uint32_t low_sclk_interrupt_threshold = 0;
2288
2289 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2290 PHM_PlatformCaps_SclkThrottleLowNotification)
2291 && (data->low_sclk_interrupt_threshold != 0)) {
2292 low_sclk_interrupt_threshold =
2293 data->low_sclk_interrupt_threshold;
2294
2295 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold)((low_sclk_interrupt_threshold) = (__uint32_t)(__builtin_constant_p
(low_sclk_interrupt_threshold) ? (__uint32_t)(((__uint32_t)(low_sclk_interrupt_threshold
) & 0xff) << 24 | ((__uint32_t)(low_sclk_interrupt_threshold
) & 0xff00) << 8 | ((__uint32_t)(low_sclk_interrupt_threshold
) & 0xff0000) >> 8 | ((__uint32_t)(low_sclk_interrupt_threshold
) & 0xff000000) >> 24) : __swap32md(low_sclk_interrupt_threshold
)))
;
2296
2297 result = smu7_copy_bytes_to_smc(
2298 hwmgr,
2299 smu_data->smu7_data.dpm_table_start +
2300 offsetof(SMU74_Discrete_DpmTable,__builtin_offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold
)
2301 LowSclkInterruptThreshold)__builtin_offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold
)
,
2302 (uint8_t *)&low_sclk_interrupt_threshold,
2303 sizeof(uint32_t),
2304 SMC_RAM_END0x40000);
2305 }
2306 PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to update SCLK threshold!"); return result; } } while
(0)
2307 "Failed to update SCLK threshold!", return result)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to update SCLK threshold!"); return result; } } while
(0)
;
2308
2309 result = polaris10_program_mem_timing_parameters(hwmgr);
2310 PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to program memory timing parameters!"); ; } } while
(0)
2311 "Failed to program memory timing parameters!",do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to program memory timing parameters!"); ; } } while
(0)
2312 )do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to program memory timing parameters!"); ; } } while
(0)
;
2313
2314 return result;
2315}
2316
2317static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2318{
2319 switch (type) {
2320 case SMU_SoftRegisters:
2321 switch (member) {
2322 case HandshakeDisables:
2323 return offsetof(SMU74_SoftRegisters, HandshakeDisables)__builtin_offsetof(SMU74_SoftRegisters, HandshakeDisables);
2324 case VoltageChangeTimeout:
2325 return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout)__builtin_offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
2326 case AverageGraphicsActivity:
2327 return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity)__builtin_offsetof(SMU74_SoftRegisters, AverageGraphicsActivity
)
;
2328 case AverageMemoryActivity:
2329 return offsetof(SMU74_SoftRegisters, AverageMemoryActivity)__builtin_offsetof(SMU74_SoftRegisters, AverageMemoryActivity
)
;
2330 case PreVBlankGap:
2331 return offsetof(SMU74_SoftRegisters, PreVBlankGap)__builtin_offsetof(SMU74_SoftRegisters, PreVBlankGap);
2332 case VBlankTimeout:
2333 return offsetof(SMU74_SoftRegisters, VBlankTimeout)__builtin_offsetof(SMU74_SoftRegisters, VBlankTimeout);
2334 case UcodeLoadStatus:
2335 return offsetof(SMU74_SoftRegisters, UcodeLoadStatus)__builtin_offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
2336 case DRAM_LOG_ADDR_H:
2337 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H)__builtin_offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
2338 case DRAM_LOG_ADDR_L:
2339 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L)__builtin_offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
2340 case DRAM_LOG_PHY_ADDR_H:
2341 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H)__builtin_offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2342 case DRAM_LOG_PHY_ADDR_L:
2343 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L)__builtin_offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2344 case DRAM_LOG_BUFF_SIZE:
2345 return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE)__builtin_offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2346 }
2347 break;
2348 case SMU_Discrete_DpmTable:
2349 switch (member) {
2350 case UvdBootLevel:
2351 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2352 case VceBootLevel:
2353 return offsetof(SMU74_Discrete_DpmTable, VceBootLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2354 case LowSclkInterruptThreshold:
2355 return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold)__builtin_offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold
)
;
2356 }
2357 break;
2358 }
2359 pr_warn("can't get the offset of type %x member %x\n", type, member)printk("\0014" "amdgpu: " "can't get the offset of type %x member %x\n"
, type, member)
;
2360 return 0;
2361}
2362
2363static uint32_t polaris10_get_mac_definition(uint32_t value)
2364{
2365 switch (value) {
2366 case SMU_MAX_LEVELS_GRAPHICS:
2367 return SMU74_MAX_LEVELS_GRAPHICS8;
2368 case SMU_MAX_LEVELS_MEMORY:
2369 return SMU74_MAX_LEVELS_MEMORY4;
2370 case SMU_MAX_LEVELS_LINK:
2371 return SMU74_MAX_LEVELS_LINK8;
2372 case SMU_MAX_ENTRIES_SMIO:
2373 return SMU74_MAX_ENTRIES_SMIO32;
2374 case SMU_MAX_LEVELS_VDDC:
2375 return SMU74_MAX_LEVELS_VDDC16;
2376 case SMU_MAX_LEVELS_VDDGFX:
2377 return SMU74_MAX_LEVELS_VDDGFX16;
2378 case SMU_MAX_LEVELS_VDDCI:
2379 return SMU74_MAX_LEVELS_VDDCI8;
2380 case SMU_MAX_LEVELS_MVDD:
2381 return SMU74_MAX_LEVELS_MVDD4;
2382 case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
2383 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE0x00000100;
2384 }
2385
2386 pr_warn("can't get the mac of %x\n", value)printk("\0014" "amdgpu: " "can't get the mac of %x\n", value);
2387 return 0;
2388}
2389
2390static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2391{
2392 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2393 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2394 uint32_t tmp;
2395 int result;
2396 bool_Bool error = false0;
2397
2398 result = smu7_read_smc_sram_dword(hwmgr,
2399 SMU7_FIRMWARE_HEADER_LOCATION0x20000 +
2400 offsetof(SMU74_Firmware_Header, DpmTable)__builtin_offsetof(SMU74_Firmware_Header, DpmTable),
2401 &tmp, SMC_RAM_END0x40000);
2402
2403 if (0 == result)
2404 smu_data->smu7_data.dpm_table_start = tmp;
2405
2406 error |= (0 != result);
2407
2408 result = smu7_read_smc_sram_dword(hwmgr,
2409 SMU7_FIRMWARE_HEADER_LOCATION0x20000 +
2410 offsetof(SMU74_Firmware_Header, SoftRegisters)__builtin_offsetof(SMU74_Firmware_Header, SoftRegisters),
2411 &tmp, SMC_RAM_END0x40000);
2412
2413 if (!result) {
2414 data->soft_regs_start = tmp;
2415 smu_data->smu7_data.soft_regs_start = tmp;
2416 }
2417
2418 error |= (0 != result);
2419
2420 result = smu7_read_smc_sram_dword(hwmgr,
2421 SMU7_FIRMWARE_HEADER_LOCATION0x20000 +
2422 offsetof(SMU74_Firmware_Header, mcRegisterTable)__builtin_offsetof(SMU74_Firmware_Header, mcRegisterTable),
2423 &tmp, SMC_RAM_END0x40000);
2424
2425 if (!result)
2426 smu_data->smu7_data.mc_reg_table_start = tmp;
2427
2428 result = smu7_read_smc_sram_dword(hwmgr,
2429 SMU7_FIRMWARE_HEADER_LOCATION0x20000 +
2430 offsetof(SMU74_Firmware_Header, FanTable)__builtin_offsetof(SMU74_Firmware_Header, FanTable),
2431 &tmp, SMC_RAM_END0x40000);
2432
2433 if (!result)
2434 smu_data->smu7_data.fan_table_start = tmp;
2435
2436 error |= (0 != result);
2437
2438 result = smu7_read_smc_sram_dword(hwmgr,
2439 SMU7_FIRMWARE_HEADER_LOCATION0x20000 +
2440 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable)__builtin_offsetof(SMU74_Firmware_Header, mcArbDramTimingTable
)
,
2441 &tmp, SMC_RAM_END0x40000);
2442
2443 if (!result)
2444 smu_data->smu7_data.arb_table_start = tmp;
2445
2446 error |= (0 != result);
2447
2448 result = smu7_read_smc_sram_dword(hwmgr,
2449 SMU7_FIRMWARE_HEADER_LOCATION0x20000 +
2450 offsetof(SMU74_Firmware_Header, Version)__builtin_offsetof(SMU74_Firmware_Header, Version),
2451 &tmp, SMC_RAM_END0x40000);
2452
2453 if (!result)
2454 hwmgr->microcode_version_info.SMC = tmp;
2455
2456 error |= (0 != result);
2457
2458 return error ? -1 : 0;
2459}
2460
2461static bool_Bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2462{
2463 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x3f010))) & 0x2000) >>
0xd)
2464 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)((((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,0x3f010))) & 0x2000) >>
0xd)
)
2465 ? true1 : false0;
2466}
2467
2468static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
2469 void *profile_setting)
2470{
2471 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2472 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2473 (hwmgr->smu_backend);
2474 struct profile_mode_setting *setting;
2475 struct SMU74_Discrete_GraphicsLevel *levels =
2476 smu_data->smc_state_table.GraphicsLevel;
2477 uint32_t array = smu_data->smu7_data.dpm_table_start +
2478 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
2479
2480 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2481 offsetof(SMU74_Discrete_DpmTable, MemoryLevel)__builtin_offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
2482 struct SMU74_Discrete_MemoryLevel *mclk_levels =
2483 smu_data->smc_state_table.MemoryLevel;
2484 uint32_t i;
2485 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2486
2487 if (profile_setting == NULL((void *)0))
2488 return -EINVAL22;
2489
2490 setting = (struct profile_mode_setting *)profile_setting;
2491
2492 if (setting->bupdate_sclk) {
2493 if (!data->sclk_dpm_key_disabled)
2494 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel((uint16_t) 0x189), NULL((void *)0));
2495 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2496 if (levels[i].ActivityLevel !=
2497 cpu_to_be16(setting->sclk_activity)(__uint16_t)(__builtin_constant_p(setting->sclk_activity) ?
(__uint16_t)(((__uint16_t)(setting->sclk_activity) & 0xffU
) << 8 | ((__uint16_t)(setting->sclk_activity) &
0xff00U) >> 8) : __swap16md(setting->sclk_activity)
)
) {
2498 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity)(__uint16_t)(__builtin_constant_p(setting->sclk_activity) ?
(__uint16_t)(((__uint16_t)(setting->sclk_activity) & 0xffU
) << 8 | ((__uint16_t)(setting->sclk_activity) &
0xff00U) >> 8) : __swap16md(setting->sclk_activity)
)
;
2499
2500 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2501 + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel)__builtin_offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel
)
;
2502 offset = clk_activity_offset & ~0x3;
2503 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset))(__uint32_t)(__builtin_constant_p((((struct cgs_device *)hwmgr
->device)->ops->read_ind_register(hwmgr->device,CGS_IND_REG__SMC
,offset))) ? (__uint32_t)(((__uint32_t)((((struct cgs_device *
)hwmgr->device)->ops->read_ind_register(hwmgr->device
,CGS_IND_REG__SMC,offset))) & 0xff) << 24 | ((__uint32_t
)((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,offset))) & 0xff00) <<
8 | ((__uint32_t)((((struct cgs_device *)hwmgr->device)->
ops->read_ind_register(hwmgr->device,CGS_IND_REG__SMC,offset
))) & 0xff0000) >> 8 | ((__uint32_t)((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,offset))) & 0xff000000) >> 24
) : __swap32md((((struct cgs_device *)hwmgr->device)->ops
->read_ind_register(hwmgr->device,CGS_IND_REG__SMC,offset
))))
;
2504 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2505 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp))(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,offset,(__uint32_t)(__builtin_constant_p
(tmp) ? (__uint32_t)(((__uint32_t)(tmp) & 0xff) << 24
| ((__uint32_t)(tmp) & 0xff00) << 8 | ((__uint32_t
)(tmp) & 0xff0000) >> 8 | ((__uint32_t)(tmp) & 0xff000000
) >> 24) : __swap32md(tmp))))
;
2506
2507 }
2508 if (levels[i].UpHyst != setting->sclk_up_hyst ||
2509 levels[i].DownHyst != setting->sclk_down_hyst) {
2510 levels[i].UpHyst = setting->sclk_up_hyst;
2511 levels[i].DownHyst = setting->sclk_down_hyst;
2512 up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2513 + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst)__builtin_offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
2514 down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2515 + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst)__builtin_offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
2516 offset = up_hyst_offset & ~0x3;
2517 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset))(__uint32_t)(__builtin_constant_p((((struct cgs_device *)hwmgr
->device)->ops->read_ind_register(hwmgr->device,CGS_IND_REG__SMC
,offset))) ? (__uint32_t)(((__uint32_t)((((struct cgs_device *
)hwmgr->device)->ops->read_ind_register(hwmgr->device
,CGS_IND_REG__SMC,offset))) & 0xff) << 24 | ((__uint32_t
)((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,offset))) & 0xff00) <<
8 | ((__uint32_t)((((struct cgs_device *)hwmgr->device)->
ops->read_ind_register(hwmgr->device,CGS_IND_REG__SMC,offset
))) & 0xff0000) >> 8 | ((__uint32_t)((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,offset))) & 0xff000000) >> 24
) : __swap32md((((struct cgs_device *)hwmgr->device)->ops
->read_ind_register(hwmgr->device,CGS_IND_REG__SMC,offset
))))
;
2518 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2519 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2520 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp))(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,offset,(__uint32_t)(__builtin_constant_p
(tmp) ? (__uint32_t)(((__uint32_t)(tmp) & 0xff) << 24
| ((__uint32_t)(tmp) & 0xff00) << 8 | ((__uint32_t
)(tmp) & 0xff0000) >> 8 | ((__uint32_t)(tmp) & 0xff000000
) >> 24) : __swap32md(tmp))))
;
2521 }
2522 }
2523 if (!data->sclk_dpm_key_disabled)
2524 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel((uint16_t) 0x18A), NULL((void *)0));
2525 }
2526
2527 if (setting->bupdate_mclk) {
2528 if (!data->mclk_dpm_key_disabled)
2529 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel((uint16_t) 0x18B), NULL((void *)0));
2530 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2531 if (mclk_levels[i].ActivityLevel !=
2532 cpu_to_be16(setting->mclk_activity)(__uint16_t)(__builtin_constant_p(setting->mclk_activity) ?
(__uint16_t)(((__uint16_t)(setting->mclk_activity) & 0xffU
) << 8 | ((__uint16_t)(setting->mclk_activity) &
0xff00U) >> 8) : __swap16md(setting->mclk_activity)
)
) {
2533 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity)(__uint16_t)(__builtin_constant_p(setting->mclk_activity) ?
(__uint16_t)(((__uint16_t)(setting->mclk_activity) & 0xffU
) << 8 | ((__uint16_t)(setting->mclk_activity) &
0xff00U) >> 8) : __swap16md(setting->mclk_activity)
)
;
2534
2535 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2536 + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel)__builtin_offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
2537 offset = clk_activity_offset & ~0x3;
2538 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset))(__uint32_t)(__builtin_constant_p((((struct cgs_device *)hwmgr
->device)->ops->read_ind_register(hwmgr->device,CGS_IND_REG__SMC
,offset))) ? (__uint32_t)(((__uint32_t)((((struct cgs_device *
)hwmgr->device)->ops->read_ind_register(hwmgr->device
,CGS_IND_REG__SMC,offset))) & 0xff) << 24 | ((__uint32_t
)((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,offset))) & 0xff00) <<
8 | ((__uint32_t)((((struct cgs_device *)hwmgr->device)->
ops->read_ind_register(hwmgr->device,CGS_IND_REG__SMC,offset
))) & 0xff0000) >> 8 | ((__uint32_t)((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,offset))) & 0xff000000) >> 24
) : __swap32md((((struct cgs_device *)hwmgr->device)->ops
->read_ind_register(hwmgr->device,CGS_IND_REG__SMC,offset
))))
;
2539 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2540 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp))(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,offset,(__uint32_t)(__builtin_constant_p
(tmp) ? (__uint32_t)(((__uint32_t)(tmp) & 0xff) << 24
| ((__uint32_t)(tmp) & 0xff00) << 8 | ((__uint32_t
)(tmp) & 0xff0000) >> 8 | ((__uint32_t)(tmp) & 0xff000000
) >> 24) : __swap32md(tmp))))
;
2541
2542 }
2543 if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2544 mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2545 mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2546 mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2547 up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2548 + offsetof(SMU74_Discrete_MemoryLevel, UpHyst)__builtin_offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
2549 down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2550 + offsetof(SMU74_Discrete_MemoryLevel, DownHyst)__builtin_offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
2551 offset = up_hyst_offset & ~0x3;
2552 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset))(__uint32_t)(__builtin_constant_p((((struct cgs_device *)hwmgr
->device)->ops->read_ind_register(hwmgr->device,CGS_IND_REG__SMC
,offset))) ? (__uint32_t)(((__uint32_t)((((struct cgs_device *
)hwmgr->device)->ops->read_ind_register(hwmgr->device
,CGS_IND_REG__SMC,offset))) & 0xff) << 24 | ((__uint32_t
)((((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,offset))) & 0xff00) <<
8 | ((__uint32_t)((((struct cgs_device *)hwmgr->device)->
ops->read_ind_register(hwmgr->device,CGS_IND_REG__SMC,offset
))) & 0xff0000) >> 8 | ((__uint32_t)((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__SMC,offset))) & 0xff000000) >> 24
) : __swap32md((((struct cgs_device *)hwmgr->device)->ops
->read_ind_register(hwmgr->device,CGS_IND_REG__SMC,offset
))))
;
2553 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2554 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2555 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp))(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,offset,(__uint32_t)(__builtin_constant_p
(tmp) ? (__uint32_t)(((__uint32_t)(tmp) & 0xff) << 24
| ((__uint32_t)(tmp) & 0xff00) << 8 | ((__uint32_t
)(tmp) & 0xff0000) >> 8 | ((__uint32_t)(tmp) & 0xff000000
) >> 24) : __swap32md(tmp))))
;
2556 }
2557 }
2558 if (!data->mclk_dpm_key_disabled)
2559 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel((uint16_t) 0x18C), NULL((void *)0));
2560 }
2561 return 0;
2562}
2563
2564const struct pp_smumgr_func polaris10_smu_funcs = {
2565 .name = "polaris10_smu",
2566 .smu_init = polaris10_smu_init,
2567 .smu_fini = smu7_smu_fini,
2568 .start_smu = polaris10_start_smu,
2569 .check_fw_load_finish = smu7_check_fw_load_finish,
2570 .request_smu_load_fw = smu7_reload_firmware,
2571 .request_smu_load_specific_fw = NULL((void *)0),
2572 .send_msg_to_smc = smu7_send_msg_to_smc,
2573 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2574 .get_argument = smu7_get_argument,
2575 .download_pptable_settings = NULL((void *)0),
2576 .upload_pptable_settings = NULL((void *)0),
2577 .update_smc_table = polaris10_update_smc_table,
2578 .get_offsetof = polaris10_get_offsetof,
2579 .process_firmware_header = polaris10_process_firmware_header,
2580 .init_smc_table = polaris10_init_smc_table,
2581 .update_sclk_threshold = polaris10_update_sclk_threshold,
2582 .thermal_avfs_enable = polaris10_thermal_avfs_enable,
2583 .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
2584 .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
2585 .populate_all_memory_levels = polaris10_populate_all_memory_levels,
2586 .get_mac_definition = polaris10_get_mac_definition,
2587 .is_dpm_running = polaris10_is_dpm_running,
2588 .is_hw_avfs_present = polaris10_is_hw_avfs_present,
2589 .update_dpm_settings = polaris10_update_dpm_settings,
2590};