Bug Summary

File:dev/ic/elink3.c
Warning:line 1361, column 2
Value stored to 'len' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name elink3.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/ic/elink3.c
1/* $OpenBSD: elink3.c,v 1.98 2020/12/12 11:48:52 jan Exp $ */
2/* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */
3
4/*
5 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan@NetBSD.org>
6 * Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Herb Peyerl.
20 * 4. The name of Herb Peyerl may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "bpfilter.h"
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/mbuf.h>
40#include <sys/socket.h>
41#include <sys/ioctl.h>
42#include <sys/errno.h>
43#include <sys/syslog.h>
44#include <sys/selinfo.h>
45#include <sys/timeout.h>
46#include <sys/device.h>
47
48#include <net/if.h>
49#include <net/if_media.h>
50
51#include <netinet/in.h>
52#include <netinet/if_ether.h>
53
54#if NBPFILTER1 > 0
55#include <net/bpf.h>
56#endif
57
58#include <machine/cpu.h>
59#include <machine/bus.h>
60
61#include <dev/mii/mii.h>
62#include <dev/mii/miivar.h>
63
64#include <dev/ic/elink3var.h>
65#include <dev/ic/elink3reg.h>
66
67/*
68 * Structure to map media-present bits in boards to
69 * ifmedia codes and printable media names. Used for table-driven
70 * ifmedia initialization.
71 */
72struct ep_media {
73 int epm_eeprom_data; /* bitmask for eeprom config */
74 int epm_conn; /* sc->ep_connectors code for medium */
75 char *epm_name; /* name of medium */
76 uint64_t epm_ifmedia; /* ifmedia word for medium */
77 int epm_ifdata;
78};
79
80/*
81 * ep_media table for Vortex/Demon/Boomerang:
82 * map from media-present bits in register RESET_OPTIONS+2
83 * to ifmedia "media words" and printable names.
84 *
85 * XXX indexed directly by INTERNAL_CONFIG default_media field,
86 * (i.e., EPMEDIA_ constants) forcing order of entries.
87 * Note that 3 is reserved.
88 */
89const struct ep_media ep_vortex_media[] = {
90 { EP_PCI_UTP(1<<3), EPC_UTP0x08, "utp", IFM_ETHER0x0000000000000100ULL|IFM_10_T3,
91 EPMEDIA_10BASE_T(u_short) 0x00 },
92 { EP_PCI_AUI(1<<5), EPC_AUI0x01, "aui", IFM_ETHER0x0000000000000100ULL|IFM_10_55,
93 EPMEDIA_AUI(u_short) 0x01 },
94 { 0, 0, "reserved", IFM_NONE2ULL, EPMEDIA_RESV1(u_short) 0x02 },
95 { EP_PCI_BNC(1<<4), EPC_BNC0x02, "bnc", IFM_ETHER0x0000000000000100ULL|IFM_10_24,
96 EPMEDIA_10BASE_2(u_short) 0x03 },
97 { EP_PCI_100BASE_TX(1<<1), EPC_100TX0x10, "100-TX", IFM_ETHER0x0000000000000100ULL|IFM_100_TX6,
98 EPMEDIA_100BASE_TX(u_short) 0x04 },
99 { EP_PCI_100BASE_FX(1<<2), EPC_100FX0x20, "100-FX", IFM_ETHER0x0000000000000100ULL|IFM_100_FX7,
100 EPMEDIA_100BASE_FX(u_short) 0x05 },
101 { EP_PCI_100BASE_MII(1<<6),EPC_MII0x40, "mii", IFM_ETHER0x0000000000000100ULL|IFM_100_TX6,
102 EPMEDIA_MII(u_short) 0x06 },
103 { EP_PCI_100BASE_T4(1<<0), EPC_100T40x80, "100-T4", IFM_ETHER0x0000000000000100ULL|IFM_100_T48,
104 EPMEDIA_100BASE_T4(u_short) 0x07 }
105};
106
107/*
108 * ep_media table for 3c509/3c509b/3c579/3c589:
109 * map from media-present bits in register CNFG_CNTRL
110 * (window 0, offset ?) to ifmedia "media words" and printable names.
111 */
112struct ep_media ep_isa_media[] = {
113 { EP_W0_CC_UTP(1<<9), EPC_UTP0x08, "utp", IFM_ETHER0x0000000000000100ULL|IFM_10_T3, EPMEDIA_10BASE_T(u_short) 0x00 },
114 { EP_W0_CC_AUI(1<<13), EPC_AUI0x01, "aui", IFM_ETHER0x0000000000000100ULL|IFM_10_55, EPMEDIA_AUI(u_short) 0x01 },
115 { EP_W0_CC_BNC(1<<12), EPC_BNC0x02, "bnc", IFM_ETHER0x0000000000000100ULL|IFM_10_24, EPMEDIA_10BASE_2(u_short) 0x03 },
116};
117
118/* Map vortex reset_options bits to if_media codes. */
119const uint64_t ep_default_to_media[] = {
120 IFM_ETHER0x0000000000000100ULL | IFM_10_T3,
121 IFM_ETHER0x0000000000000100ULL | IFM_10_55,
122 0, /* reserved by 3Com */
123 IFM_ETHER0x0000000000000100ULL | IFM_10_24,
124 IFM_ETHER0x0000000000000100ULL | IFM_100_TX6,
125 IFM_ETHER0x0000000000000100ULL | IFM_100_FX7,
126 IFM_ETHER0x0000000000000100ULL | IFM_100_TX6, /* XXX really MII: need to talk to PHY */
127 IFM_ETHER0x0000000000000100ULL | IFM_100_T48,
128};
129
130struct cfdriver ep_cd = {
131 NULL((void *)0), "ep", DV_IFNET
132};
133
134void ep_vortex_probemedia(struct ep_softc *sc);
135void ep_isa_probemedia(struct ep_softc *sc);
136
137void eptxstat(struct ep_softc *);
138int epstatus(struct ep_softc *);
139int epioctl(struct ifnet *, u_long, caddr_t);
140void epstart(struct ifnet *);
141void epwatchdog(struct ifnet *);
142void epreset(struct ep_softc *);
143void epread(struct ep_softc *);
144struct mbuf *epget(struct ep_softc *, int);
145void epmbuffill(void *);
146void epmbufempty(struct ep_softc *);
147void epsetfilter(struct ep_softc *);
148void ep_roadrunner_mii_enable(struct ep_softc *);
149int epsetmedia(struct ep_softc *, int);
150
151/* ifmedia callbacks */
152int ep_media_change(struct ifnet *);
153void ep_media_status(struct ifnet *, struct ifmediareq *);
154
155/* MII callbacks */
156int ep_mii_readreg(struct device *, int, int);
157void ep_mii_writereg(struct device *, int, int, int);
158void ep_statchg(struct device *);
159
160void ep_mii_setbit(struct ep_softc *, u_int16_t);
161void ep_mii_clrbit(struct ep_softc *, u_int16_t);
162u_int16_t ep_mii_readbit(struct ep_softc *, u_int16_t);
163void ep_mii_sync(struct ep_softc *);
164void ep_mii_sendbits(struct ep_softc *, u_int32_t, int);
165
166int epbusyeeprom(struct ep_softc *);
167u_int16_t ep_read_eeprom(struct ep_softc *, u_int16_t);
168
169static inline void ep_reset_cmd(struct ep_softc *sc, u_int cmd,u_int arg);
170static inline void ep_finish_reset(bus_space_tag_t, bus_space_handle_t);
171static inline void ep_discard_rxtop(bus_space_tag_t, bus_space_handle_t);
172static __inline int ep_w1_reg(struct ep_softc *, int);
173
174/*
175 * Issue a (reset) command, and be sure it has completed.
176 * Used for global reset, TX_RESET, RX_RESET.
177 */
178static inline void
179ep_reset_cmd(struct ep_softc *sc, u_int cmd, u_int arg)
180{
181 bus_space_tag_t iot = sc->sc_iot;
182 bus_space_handle_t ioh = sc->sc_ioh;
183
184 bus_space_write_2(iot, ioh, cmd, arg)((iot)->write_2((ioh), (cmd), (arg)));
185 ep_finish_reset(iot, ioh);
186}
187
188/*
189 * Wait for any pending reset to complete.
190 */
191static inline void
192ep_finish_reset(bus_space_tag_t iot, bus_space_handle_t ioh)
193{
194 int i;
195
196 for (i = 0; i < 10000; i++) {
197 if ((bus_space_read_2(iot, ioh, EP_STATUS)((iot)->read_2((ioh), (0x0e))) &
198 S_COMMAND_IN_PROGRESS(u_short) (0x1000)) == 0)
199 break;
200 DELAY(10)(*delay_func)(10);
201 }
202}
203
204static inline void
205ep_discard_rxtop(bus_space_tag_t iot, bus_space_handle_t ioh)
206{
207 int i;
208
209 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK)((iot)->write_2((ioh), (0x0e), ((u_short) (0x8<<11))
))
;
210
211 /*
212 * Spin for about 1 msec, to avoid forcing a DELAY() between
213 * every received packet (adding latency and limiting pkt-recv rate).
214 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations
215 * is about right.
216 */
217 for (i = 0; i < 8000; i++) {
218 if ((bus_space_read_2(iot, ioh, EP_STATUS)((iot)->read_2((ioh), (0x0e))) &
219 S_COMMAND_IN_PROGRESS(u_short) (0x1000)) == 0)
220 return;
221 }
222
223 /* not fast enough, do DELAY()s */
224 ep_finish_reset(iot, ioh);
225}
226
227/*
228 * Some chips (i.e., 3c574 RoadRunner) have Window 1 registers offset.
229 */
230static __inline int
231ep_w1_reg(struct ep_softc *sc, int reg)
232{
233 switch (sc->ep_chipset) {
234 case EP_CHIPSET_ROADRUNNER0x05:
235 switch (reg) {
236 case EP_W1_FREE_TX0x0c:
237 case EP_W1_RUNNER_RDCTL0x16:
238 case EP_W1_RUNNER_WRCTL0x1c:
239 return (reg);
240 }
241 return (reg + 0x10);
242 }
243 return (reg);
244}
245
246/*
247 * Back-end attach and configure.
248 */
249void
250epconfig(struct ep_softc *sc, u_short chipset, u_int8_t *enaddr)
251{
252 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
253 bus_space_tag_t iot = sc->sc_iot;
254 bus_space_handle_t ioh = sc->sc_ioh;
255 u_int16_t i;
256
257 sc->ep_chipset = chipset;
258
259 /*
260 * We could have been groveling around in other register
261 * windows in the front-end; make sure we're in window 0
262 * to read the EEPROM.
263 */
264 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)))
;
265
266 if (enaddr == NULL((void *)0)) {
267 /*
268 * Read the station address from the eeprom.
269 */
270 for (i = 0; i < 3; i++) {
271 u_int16_t x = ep_read_eeprom(sc, i);
272
273 sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8;
274 sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x;
275 }
276 } else {
277 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN6);
278 }
279
280 printf(" address %s", ether_sprintf(sc->sc_arpcom.ac_enaddr));
281 if (sc->ep_flags & EP_FLAGS_MII0x4000)
282 printf("\n");
283 else
284 printf(", ");
285
286 /*
287 * Vortex-based (3c59x pci,eisa) cards allow FDDI-sized (4500) byte
288 * packets. Commands only take an 11-bit parameter, and 11 bits
289 * isn't enough to hold a full-size packet length.
290 * Commands to these cards implicitly upshift a packet size
291 * or threshold by 2 bits.
292 * To detect cards with large-packet support, we probe by setting
293 * the transmit threshold register, then change windows and
294 * read back the threshold register directly, and see if the
295 * threshold value was shifted or not.
296 */
297 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| 2047)))
298 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE )((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| 2047)))
;
299 GO_WINDOW(5)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|5)))
;
300 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH)((iot)->read_2((ioh), (0x02)));
301 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
;
302 switch (i) {
303 case EP_LARGEWIN_PROBE2047:
304 case (EP_LARGEWIN_PROBE2047 & EP_LARGEWIN_MASK0xffc):
305 sc->txashift = 0;
306 break;
307
308 case (EP_LARGEWIN_PROBE2047 << 2):
309 sc->txashift = 2;
310 /* XXX does the 3c515 support Vortex-style RESET_OPTIONS? */
311 break;
312
313 default:
314 printf("wrote %x to TX_AVAIL_THRESH, read back %x. "
315 "Interface disabled\n", EP_THRESH_DISABLE2047, (int) i);
316 return;
317 }
318
319 timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc);
320
321 /*
322 * Ensure Tx-available interrupts are enabled for
323 * start the interface.
324 * XXX should be in epinit()?
325 */
326 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| (1600 >> sc->txashift))))
327 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift))((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| (1600 >> sc->txashift))))
;
328
329 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ16);
330 ifp->if_softc = sc;
331 ifp->if_start = epstart;
332 ifp->if_ioctl = epioctl;
333 ifp->if_watchdog = epwatchdog;
334 ifp->if_flags =
335 IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
336 /* 64 packets are around 100ms on 10Mbps */
337 ifq_set_maxlen(&ifp->if_snd, 64)((&ifp->if_snd)->ifq_maxlen = (64));
338
339 if_attach(ifp);
340 ether_ifattach(ifp);
341
342 /*
343 * Finish configuration:
344 * determine chipset if the front-end couldn't do so,
345 * show board details, set media.
346 */
347
348 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)))
;
349
350 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change,
351 ep_media_status);
352 sc->sc_mii.mii_ifp = ifp;
353 sc->sc_mii.mii_readreg = ep_mii_readreg;
354 sc->sc_mii.mii_writereg = ep_mii_writereg;
355 sc->sc_mii.mii_statchg = ep_statchg;
356
357 /*
358 * If we've got an indirect (ISA, PCMCIA?) board, the chipset
359 * is unknown. If the board has large-packet support, it's a
360 * Vortex/Boomerang, otherwise it's a 3c509.
361 * XXX use eeprom capability word instead?
362 */
363 if (sc->ep_chipset == EP_CHIPSET_UNKNOWN0x00 && sc->txashift) {
364 printf("warning: unknown chipset, possibly 3c515?\n");
365#ifdef notyet
366 sc->sc_chipset = EP_CHIPSET_VORTEX0x02;
367#endif /* notyet */
368 }
369
370 /*
371 * Ascertain which media types are present and inform ifmedia.
372 */
373 switch (sc->ep_chipset) {
374 case EP_CHIPSET_ROADRUNNER0x05:
375 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
376 ep_roadrunner_mii_enable(sc);
377 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)))
;
378 }
379 /* FALLTHROUGH */
380
381 case EP_CHIPSET_BOOMERANG0x03:
382 /*
383 * If the device has MII, probe it. We won't be using
384 * any `native' media in this case, only PHYs. If
385 * we don't, just treat the Boomerang like the Vortex.
386 */
387 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
388 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff,
389 MII_PHY_ANY-1, MII_OFFSET_ANY-1, 0);
390 if (LIST_FIRST(&sc->sc_mii.mii_phys)((&sc->sc_mii.mii_phys)->lh_first) == NULL((void *)0)) {
391 ifmedia_add(&sc->sc_mii.mii_media,
392 IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL, 0, NULL((void *)0));
393 ifmedia_set(&sc->sc_mii.mii_media,
394 IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL);
395 } else {
396 ifmedia_set(&sc->sc_mii.mii_media,
397 IFM_ETHER0x0000000000000100ULL|IFM_AUTO0ULL);
398 }
399 break;
400 }
401 /* FALLTHROUGH */
402
403 /* on a direct bus, the attach routine can tell, but check anyway. */
404 case EP_CHIPSET_VORTEX0x02:
405 case EP_CHIPSET_BOOMERANG20x04:
406 ep_vortex_probemedia(sc);
407 break;
408
409 /* on ISA we can't yet tell 3c509 from 3c515. Assume the former. */
410 case EP_CHIPSET_3C5090x01:
411 default:
412 ep_isa_probemedia(sc);
413 break;
414 }
415
416 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* Window 1 is operating window */
417
418 sc->tx_start_thresh = 20; /* probably a good starting point. */
419
420 ep_reset_cmd(sc, EP_COMMAND0x0e, RX_RESET(u_short) (0x5<<11));
421 ep_reset_cmd(sc, EP_COMMAND0x0e, TX_RESET(u_short) (0xb<<11));
422}
423
424int
425ep_detach(struct device *self)
426{
427 struct ep_softc *sc = (struct ep_softc *)self;
428 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
429
430 if (sc->ep_flags & EP_FLAGS_MII0x4000)
431 mii_detach(&sc->sc_mii, MII_PHY_ANY-1, MII_OFFSET_ANY-1);
432
433 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY((uint64_t) -1));
434
435 ether_ifdetach(ifp);
436 if_detach(ifp);
437
438 return (0);
439}
440
441/*
442 * Find supported media on 3c509-generation hardware that doesn't have
443 * a "reset_options" register in window 3.
444 * Use the config_cntrl register in window 0 instead.
445 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards
446 * that implement CONFIG_CTRL. We don't have a good way to set the
447 * default active medium; punt to ifconfig instead.
448 *
449 * XXX what about 3c515, pcmcia 10/100?
450 */
451void
452ep_isa_probemedia(struct ep_softc *sc)
453{
454 bus_space_tag_t iot = sc->sc_iot;
455 bus_space_handle_t ioh = sc->sc_ioh;
456 struct ifmedia *ifm = &sc->sc_mii.mii_media;
457 int conn, i;
458 u_int16_t ep_w0_config, port;
459
460 conn = 0;
461 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)))
;
462 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL)((iot)->read_2((ioh), (0x04)));
463 for (i = 0; i < nitems(ep_isa_media)(sizeof((ep_isa_media)) / sizeof((ep_isa_media)[0])); i++) {
464 struct ep_media * epm = ep_isa_media + i;
465
466 if ((ep_w0_config & epm->epm_eeprom_data) != 0) {
467 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0);
468 if (conn)
469 printf("/");
470 printf("%s", epm->epm_name);
471 conn |= epm->epm_conn;
472 }
473 }
474 sc->ep_connectors = conn;
475
476 /* get default medium from EEPROM */
477 if (epbusyeeprom(sc))
478 return; /* XXX why is eeprom busy? */
479 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND,((iot)->write_2((ioh), (0x0a), ((1<<7) | 0x8)))
480 READ_EEPROM | EEPROM_ADDR_CFG)((iot)->write_2((ioh), (0x0a), ((1<<7) | 0x8)));
481 if (epbusyeeprom(sc))
482 return; /* XXX why is eeprom busy? */
483 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA)((iot)->read_2((ioh), (0x0c)));
484 port = port >> 14;
485
486 printf(" (default %s)\n", ep_vortex_media[port].epm_name);
487
488 /* tell ifconfig what currently-active media is. */
489 ifmedia_set(ifm, ep_default_to_media[port]);
490
491 /* XXX autoselect not yet implemented */
492}
493
494
495/*
496 * Find media present on large-packet-capable elink3 devices.
497 * Show onboard configuration of large-packet-capable elink3 devices
498 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0.
499 * Use media and card-version info in window 3 instead.
500 *
501 * XXX how much of this works with 3c515, pcmcia 10/100?
502 */
503void
504ep_vortex_probemedia(struct ep_softc *sc)
505{
506 bus_space_tag_t iot = sc->sc_iot;
507 bus_space_handle_t ioh = sc->sc_ioh;
508 struct ifmedia *ifm = &sc->sc_mii.mii_media;
509 u_int config1, conn;
510 int reset_options;
511 int default_media; /* 3-bit encoding of default (EEPROM) media */
512 int autoselect; /* boolean: should default to autoselect */
513 const char *medium_name;
514 register int i;
515
516 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)))
;
517 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2)((iot)->read_2((ioh), (0x00 + 2)));
518 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS)((iot)->read_1((ioh), (0x08)));
519 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)))
;
520
521 default_media = (config1 & CONFIG_MEDIAMASK(u_short) 0x0070) >> CONFIG_MEDIAMASK_SHIFT(u_short) 4;
522 autoselect = (config1 & CONFIG_AUTOSELECT(u_short) 0x0100) >> CONFIG_AUTOSELECT_SHIFT(u_short) 8;
523
524 /* set available media options */
525 conn = 0;
526 for (i = 0; i < nitems(ep_vortex_media)(sizeof((ep_vortex_media)) / sizeof((ep_vortex_media)[0])); i++) {
527 const struct ep_media *epm = ep_vortex_media + i;
528
529 if ((reset_options & epm->epm_eeprom_data) != 0) {
530 if (conn)
531 printf("/");
532 printf("%s", epm->epm_name);
533 conn |= epm->epm_conn;
534 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0);
535 }
536 }
537
538 sc->ep_connectors = conn;
539
540 /* Show eeprom's idea of default media. */
541 medium_name = (default_media > nitems(ep_vortex_media)(sizeof((ep_vortex_media)) / sizeof((ep_vortex_media)[0])) - 1)
542 ? "(unknown/impossible media)"
543 : ep_vortex_media[default_media].epm_name;
544 printf(" default %s%s",
545 medium_name, (autoselect) ? "/autoselect" : "");
546/* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/
547
548#ifdef notyet
549 /*
550 * Set default: either the active interface the card
551 * reads from the EEPROM, or if autoselect is true,
552 * whatever we find is actually connected.
553 *
554 * XXX autoselect not yet implemented.
555 */
556#endif /* notyet */
557
558 /* tell ifconfig what currently-active media is. */
559 ifmedia_set(ifm, ep_default_to_media[default_media]);
560}
561
562/*
563 * Bring device up.
564 *
565 * The order in here seems important. Otherwise we may not receive
566 * interrupts. ?!
567 */
568void
569epinit(struct ep_softc *sc)
570{
571 register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
572 bus_space_tag_t iot = sc->sc_iot;
573 bus_space_handle_t ioh = sc->sc_ioh;
574 int i;
575
576 /* make sure any pending reset has completed before touching board */
577 ep_finish_reset(iot, ioh);
578
579 /* cancel any pending I/O */
580 epstop(sc);
581
582 if (sc->bustype != EP_BUS_PCI0x3) {
583 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)))
;
584 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0)((iot)->write_2((ioh), (0x04), (0)));
585 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ)((iot)->write_2((ioh), (0x04), (0x0001)));
586 }
587
588 if (sc->bustype == EP_BUS_PCMCIA0x1) {
589 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00)((iot)->write_2((ioh), (0x08), (0x3f00)));
590 }
591
592 GO_WINDOW(2)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|2)))
;
593 for (i = 0; i < 6; i++) /* Reload the ether_addr. */
594 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i,((iot)->write_1((ioh), (0x00 + i), (sc->sc_arpcom.ac_enaddr
[i])))
595 sc->sc_arpcom.ac_enaddr[i])((iot)->write_1((ioh), (0x00 + i), (sc->sc_arpcom.ac_enaddr
[i])))
;
596
597 if (sc->bustype == EP_BUS_PCI0x3 || sc->bustype == EP_BUS_EISA0x2)
598 /*
599 * Reset the station-address receive filter.
600 * A bug workaround for busmastering (Vortex, Demon) cards.
601 */
602 for (i = 0; i < 6; i++)
603 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0)((iot)->write_1((ioh), (0x06 + i), (0)));
604
605 ep_reset_cmd(sc, EP_COMMAND0x0e, RX_RESET(u_short) (0x5<<11));
606 ep_reset_cmd(sc, EP_COMMAND0x0e, TX_RESET(u_short) (0xb<<11));
607
608 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* Window 1 is operating window */
609 for (i = 0; i < 31; i++)
610 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS))((iot)->read_1((ioh), (ep_w1_reg(sc, 0x0b))));
611
612 /* Set threshold for for Tx-space available interrupt. */
613 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| (1600 >> sc->txashift))))
614 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift))((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| (1600 >> sc->txashift))))
;
615
616 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER0x05) {
617 /* Enable options in the PCMCIA LAN COR register, via
618 * RoadRunner Window 1.
619 *
620 * XXX MAGIC CONSTANTS!
621 */
622 u_int16_t cor;
623
624 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11))((iot)->write_2((ioh), (0x16), ((1 << 11))));
625
626 cor = bus_space_read_2(iot, ioh, 0)((iot)->read_2((ioh), (0))) & ~0x30;
627 bus_space_write_2(iot, ioh, 0, cor)((iot)->write_2((ioh), (0), (cor)));
628
629 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0)((iot)->write_2((ioh), (0x1c), (0)));
630 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0)((iot)->write_2((ioh), (0x16), (0)));
631
632 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
633 ep_roadrunner_mii_enable(sc);
634 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
;
635 }
636 }
637
638 /* Enable interrupts. */
639 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK |((iot)->write_2((ioh), (0x0e), ((u_short) (0x0f<<11)
| (u_short) (0x0002) | (u_short) (0x0010) | (u_short) (0x0004
) | (u_short) (0x0008))))
640 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL)((iot)->write_2((ioh), (0x0e), ((u_short) (0x0f<<11)
| (u_short) (0x0002) | (u_short) (0x0010) | (u_short) (0x0004
) | (u_short) (0x0008))))
;
641 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK |((iot)->write_2((ioh), (0x0e), ((u_short) (0x0e<<11)
| (u_short) (0x0002) | (u_short) (0x0010) | (u_short) (0x0004
) | (u_short) (0x0008))))
642 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL)((iot)->write_2((ioh), (0x0e), ((u_short) (0x0e<<11)
| (u_short) (0x0002) | (u_short) (0x0010) | (u_short) (0x0004
) | (u_short) (0x0008))))
;
643
644 /*
645 * Attempt to get rid of any stray interrupts that occurred during
646 * configuration. On the i386 this isn't possible because one may
647 * already be queued. However, a single stray interrupt is
648 * unimportant.
649 */
650 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff)((iot)->write_2((ioh), (0x0e), ((u_short) (0x6800) | 0xff)
))
;
651
652 epsetfilter(sc);
653 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data);
654
655 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x4<<11))
))
;
656 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x9<<11))
))
;
657
658 epmbuffill(sc);
659
660 /* Interface is now `running', with no output active. */
661 ifp->if_flags |= IFF_RUNNING0x40;
662 ifq_clr_oactive(&ifp->if_snd);
663
664 /* Attempt to start output, if any. */
665 epstart(ifp);
666}
667
668/*
669 * Set multicast receive filter.
670 * elink3 hardware has no selective multicast filter in hardware.
671 * Enable reception of all multicasts and filter in software.
672 */
673void
674epsetfilter(struct ep_softc *sc)
675{
676 register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
677
678 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* Window 1 is operating window */
679 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER |((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x10<<11) | (u_short) (0x01) | (u_short) (0x04) | ((
ifp->if_flags & 0x8000) ? (u_short) (0x02) : 0 ) | ((ifp
->if_flags & 0x100) ? (u_short) (0x08) : 0 ))))
680 FIL_INDIVIDUAL | FIL_BRDCST |((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x10<<11) | (u_short) (0x01) | (u_short) (0x04) | ((
ifp->if_flags & 0x8000) ? (u_short) (0x02) : 0 ) | ((ifp
->if_flags & 0x100) ? (u_short) (0x08) : 0 ))))
681 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) |((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x10<<11) | (u_short) (0x01) | (u_short) (0x04) | ((
ifp->if_flags & 0x8000) ? (u_short) (0x02) : 0 ) | ((ifp
->if_flags & 0x100) ? (u_short) (0x08) : 0 ))))
682 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 ))((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x10<<11) | (u_short) (0x01) | (u_short) (0x04) | ((
ifp->if_flags & 0x8000) ? (u_short) (0x02) : 0 ) | ((ifp
->if_flags & 0x100) ? (u_short) (0x08) : 0 ))))
;
683}
684
685
686int
687ep_media_change(struct ifnet *ifp)
688{
689 register struct ep_softc *sc = ifp->if_softc;
690
691 return epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data);
692}
693
694/*
695 * Reset and enable the MII on the RoadRunner.
696 */
697void
698ep_roadrunner_mii_enable(struct ep_softc *sc)
699{
700 bus_space_tag_t iot = sc->sc_iot;
701 bus_space_handle_t ioh = sc->sc_ioh;
702
703 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)))
;
704 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,((iot)->write_2((ioh), (0x08), ((1<<6)|0x8000)))
705 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII)((iot)->write_2((ioh), (0x08), ((1<<6)|0x8000)));
706 delay(1000)(*delay_func)(1000);
707 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,((iot)->write_2((ioh), (0x08), ((1<<6)|0x4000|0x8000
)))
708 EP_PCI_100BASE_MII|EP_RUNNER_MII_RESET|EP_RUNNER_ENABLE_MII)((iot)->write_2((ioh), (0x08), ((1<<6)|0x4000|0x8000
)))
;
709 ep_reset_cmd(sc, EP_COMMAND0x0e, TX_RESET(u_short) (0xb<<11));
710 ep_reset_cmd(sc, EP_COMMAND0x0e, RX_RESET(u_short) (0x5<<11));
711 delay(1000)(*delay_func)(1000);
712 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,((iot)->write_2((ioh), (0x08), ((1<<6)|0x8000)))
713 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII)((iot)->write_2((ioh), (0x08), ((1<<6)|0x8000)));
714}
715
716/*
717 * Set active media to a specific given EPMEDIA_<> value.
718 * For vortex/demon/boomerang cards, update media field in w3_internal_config,
719 * and power on selected transceiver.
720 * For 3c509-generation cards (3c509/3c579/3c589/3c509B),
721 * update media field in w0_address_config, and power on selected xcvr.
722 */
723int
724epsetmedia(struct ep_softc *sc, int medium)
725{
726 bus_space_tag_t iot = sc->sc_iot;
727 bus_space_handle_t ioh = sc->sc_ioh;
728 int w4_media;
729 int config0, config1;
730
731 /*
732 * you can `ifconfig (link0|-link0) ep0' to get the following
733 * behaviour:
734 * -link0 disable AUI/UTP. enable BNC.
735 * link0 disable BNC. enable AUI.
736 * link1 if the card has a UTP connector, and link0 is
737 * set too, then you get the UTP port.
738 */
739
740 /*
741 * First, change the media-control bits in EP_W4_MEDIA_TYPE.
742 */
743
744 /* Turn everything off. First turn off linkbeat and UTP. */
745 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)))
;
746 w4_media = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE)((iot)->read_2((ioh), (0x0a)));
747 w4_media = w4_media & ~(ENABLE_UTP(0x40|0x80)|SQE_ENABLE0x08);
748 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, w4_media)((iot)->write_2((ioh), (0x0a), (w4_media)));
749
750 /* Turn off coax */
751 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER)((iot)->write_2((ioh), (0x0e), ((u_short) (0x17<<11)
)))
;
752 delay(1000)(*delay_func)(1000);
753
754 /* If the device has MII, select it, and then tell the
755 * PHY which media to use.
756 */
757 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
758 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)))
;
759
760 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER0x05) {
761 int resopt;
762
763 resopt = bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x08)))
764 EP_W3_RESET_OPTIONS)((iot)->read_2((ioh), (0x08)));
765 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,((iot)->write_2((ioh), (0x08), (resopt | 0x8000)))
766 resopt | EP_RUNNER_ENABLE_MII)((iot)->write_2((ioh), (0x08), (resopt | 0x8000)));
767 }
768
769 config0 = (u_int)bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x00)))
770 EP_W3_INTERNAL_CONFIG)((iot)->read_2((ioh), (0x00)));
771 config1 = (u_int)bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x00 + 2)))
772 EP_W3_INTERNAL_CONFIG + 2)((iot)->read_2((ioh), (0x00 + 2)));
773
774 config1 = config1 & ~CONFIG_MEDIAMASK(u_short) 0x0070;
775 config1 |= (EPMEDIA_MII(u_short) 0x06 << CONFIG_MEDIAMASK_SHIFT(u_short) 4);
776
777 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0)((iot)->write_2((ioh), (0x00), (config0)));
778 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1)((iot)->write_2((ioh), (0x00 + 2), (config1)));
779 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* back to operating window */
780
781 mii_mediachg(&sc->sc_mii);
782 return (0);
783 }
784
785 /*
786 * Now turn on the selected media/transceiver.
787 */
788 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)))
;
789 switch (medium) {
790 case EPMEDIA_10BASE_T(u_short) 0x00:
791 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, (ENABLE_UTP |((iot)->write_2((ioh), (0x0a), (((0x40|0x80) | (sc->bustype
== 0x1 ? 0x0001 : 0)))))
792 (sc->bustype == EP_BUS_PCMCIA ? MEDIA_LED : 0)))((iot)->write_2((ioh), (0x0a), (((0x40|0x80) | (sc->bustype
== 0x1 ? 0x0001 : 0)))))
;
793 break;
794
795 case EPMEDIA_10BASE_2(u_short) 0x03:
796 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER)((iot)->write_2((ioh), (0x0e), ((u_short) (0x2<<11))
))
;
797 DELAY(1000)(*delay_func)(1000); /* 50ms not enough? */
798 break;
799
800 /* XXX following only for new-generation cards */
801 case EPMEDIA_100BASE_TX(u_short) 0x04:
802 case EPMEDIA_100BASE_FX(u_short) 0x05:
803 case EPMEDIA_100BASE_T4(u_short) 0x07: /* XXX check documentation */
804 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE,((iot)->write_2((ioh), (0x0a), (w4_media | 0x80)))
805 w4_media | LINKBEAT_ENABLE)((iot)->write_2((ioh), (0x0a), (w4_media | 0x80)));
806 DELAY(1000)(*delay_func)(1000); /* not strictly necessary? */
807 break;
808
809 case EPMEDIA_AUI(u_short) 0x01:
810 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE,((iot)->write_2((ioh), (0x0a), (w4_media | 0x08)))
811 w4_media | SQE_ENABLE)((iot)->write_2((ioh), (0x0a), (w4_media | 0x08)));
812 DELAY(1000)(*delay_func)(1000); /* not strictly necessary? */
813 break;
814 case EPMEDIA_MII(u_short) 0x06:
815 break;
816 default:
817#if defined(EP_DEBUG)
818 printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium);
819#endif
820 break;
821
822 }
823
824 /*
825 * Tell the chip which PHY [sic] to use.
826 */
827 switch (sc->ep_chipset) {
828 case EP_CHIPSET_VORTEX0x02:
829 case EP_CHIPSET_BOOMERANG20x04:
830 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)))
;
831 config0 = (u_int)bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x00)))
832 EP_W3_INTERNAL_CONFIG)((iot)->read_2((ioh), (0x00)));
833 config1 = (u_int)bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x00 + 2)))
834 EP_W3_INTERNAL_CONFIG + 2)((iot)->read_2((ioh), (0x00 + 2)));
835
836#if defined(EP_DEBUG)
837 printf("%s: read 0x%x, 0x%x from EP_W3_CONFIG register\n",
838 sc->sc_dev.dv_xname, config0, config1);
839#endif
840 config1 = config1 & ~CONFIG_MEDIAMASK(u_short) 0x0070;
841 config1 |= (medium << CONFIG_MEDIAMASK_SHIFT(u_short) 4);
842
843#if defined(EP_DEBUG)
844 printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n",
845 sc->sc_dev.dv_xname, medium, config1);
846#endif
847 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0)((iot)->write_2((ioh), (0x00), (config0)));
848 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1)((iot)->write_2((ioh), (0x00 + 2), (config1)));
849 break;
850
851 default:
852 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)))
;
853 config0 = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG)((iot)->read_2((ioh), (0x06)));
854 config0 &= 0x3fff;
855 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,((iot)->write_2((ioh), (0x06), (config0 | (medium <<
14))))
856 config0 | (medium << 14))((iot)->write_2((ioh), (0x06), (config0 | (medium <<
14))))
;
857 DELAY(1000)(*delay_func)(1000);
858 break;
859 }
860
861 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* Window 1 is operating window */
862 return (0);
863}
864
865
866/*
867 * Get currently-selected media from card.
868 * (if_media callback, may be called before interface is brought up).
869 */
870void
871ep_media_status(struct ifnet *ifp, struct ifmediareq *req)
872{
873 register struct ep_softc *sc = ifp->if_softc;
874 bus_space_tag_t iot = sc->sc_iot;
875 bus_space_handle_t ioh = sc->sc_ioh;
876 u_int config1;
877 u_int ep_mediastatus;
878
879 /*
880 * If we have MII, go ask the PHY what's going on.
881 */
882 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
883 mii_pollstat(&sc->sc_mii);
884 req->ifm_active = sc->sc_mii.mii_media_active;
885 req->ifm_status = sc->sc_mii.mii_media_status;
886 return;
887 }
888
889 /* XXX read from softc when we start autosensing media */
890 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media;
891
892 switch (sc->ep_chipset) {
893 case EP_CHIPSET_VORTEX0x02:
894 case EP_CHIPSET_BOOMERANG0x03:
895 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)))
;
896 delay(5000)(*delay_func)(5000);
897
898 config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2)((iot)->read_2((ioh), (0x00 + 2)));
899 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
;
900
901 config1 =
902 (config1 & CONFIG_MEDIAMASK(u_short) 0x0070) >> CONFIG_MEDIAMASK_SHIFT(u_short) 4;
903 req->ifm_active = ep_default_to_media[config1];
904
905 /* XXX check full-duplex bits? */
906
907 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)))
;
908 req->ifm_status = IFM_AVALID0x0000000000000001ULL; /* XXX */
909 ep_mediastatus = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE)((iot)->read_2((ioh), (0x0a)));
910 if (ep_mediastatus & LINKBEAT_DETECT0x800)
911 req->ifm_status |= IFM_ACTIVE0x0000000000000002ULL; /* XXX automedia */
912
913 break;
914
915 case EP_CHIPSET_UNKNOWN0x00:
916 case EP_CHIPSET_3C5090x01:
917 req->ifm_status = 0; /* XXX */
918 break;
919
920 default:
921 printf("%s: media_status on unknown chipset 0x%x\n",
922 ifp->if_xname, sc->ep_chipset);
923 break;
924 }
925
926 /* XXX look for softc heartbeat for other chips or media */
927
928 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
;
929 return;
930}
931
932
933
934/*
935 * Start outputting on the interface.
936 * Always called as splnet().
937 */
938void
939epstart(struct ifnet *ifp)
940{
941 register struct ep_softc *sc = ifp->if_softc;
942 bus_space_tag_t iot = sc->sc_iot;
943 bus_space_handle_t ioh = sc->sc_ioh;
944 struct mbuf *m, *m0;
945 caddr_t data;
946 int sh, len, pad, txreg;
947
948 /* Don't transmit if interface is busy or not running */
949 if (!(ifp->if_flags & IFF_RUNNING0x40) || ifq_is_oactive(&ifp->if_snd))
950 return;
951
952startagain:
953 /* Sneak a peek at the next packet */
954 m0 = ifq_deq_begin(&ifp->if_snd);
955 if (m0 == NULL((void *)0))
956 return;
957
958 /* We need to use m->m_pkthdr.len, so require the header */
959 if ((m0->m_flagsm_hdr.mh_flags & M_PKTHDR0x0002) == 0)
960 panic("epstart: no header mbuf");
961 len = m0->m_pkthdrM_dat.MH.MH_pkthdr.len;
962
963 pad = (4 - len) & 3;
964
965 /*
966 * The 3c509 automatically pads short packets to minimum ethernet
967 * length, but we drop packets that are too large. Perhaps we should
968 * truncate them instead?
969 */
970 if (len + pad > ETHER_MAX_LEN1518) {
971 /* packet is obviously too large: toss it */
972 ++ifp->if_oerrorsif_data.ifi_oerrors;
973 ifq_deq_commit(&ifp->if_snd, m0);
974 m_freem(m0);
975 goto readcheck;
976 }
977
978 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX))((iot)->read_2((ioh), (ep_w1_reg(sc, 0x0c)))) <
979 len + pad + 4) {
980 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| ((len + pad + 4) >> sc->txashift))))
981 SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift))((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| ((len + pad + 4) >> sc->txashift))))
;
982 /* not enough room in FIFO */
983 ifq_deq_rollback(&ifp->if_snd, m0);
984 ifq_set_oactive(&ifp->if_snd);
985 return;
986 } else {
987 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| 2047)))
988 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| 2047)))
;
989 }
990
991 ifq_deq_commit(&ifp->if_snd, m0);
992 if (m0 == NULL((void *)0))
993 return;
994
995 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH |((iot)->write_2((ioh), (0x0e), ((u_short) (0x13<<11)
| ((len / 4 + sc->tx_start_thresh) ))))
996 ((len / 4 + sc->tx_start_thresh) /*>> sc->txashift*/))((iot)->write_2((ioh), (0x0e), ((u_short) (0x13<<11)
| ((len / 4 + sc->tx_start_thresh) ))))
;
997
998#if NBPFILTER1 > 0
999 if (ifp->if_bpf)
1000 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT(1 << 1));
1001#endif
1002
1003 /*
1004 * Do the output at splhigh() so that an interrupt from another device
1005 * won't cause a FIFO underrun.
1006 */
1007 sh = splhigh()splraise(0xd);
1008
1009 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_10x00);
1010
1011 bus_space_write_2(iot, ioh, txreg, len)((iot)->write_2((ioh), (txreg), (len)));
1012 bus_space_write_2(iot, ioh, txreg, 0xffff)((iot)->write_2((ioh), (txreg), (0xffff))); /* Second is meaningless */
1013 if (EP_IS_BUS_32(sc->bustype)((sc->bustype) & 0x2)) {
1014 for (m = m0; m; ) {
1015 data = mtod(m, u_int8_t *)((u_int8_t *)((m)->m_hdr.mh_data));
1016 if (m->m_lenm_hdr.mh_len > 3 && ALIGNED_POINTER(data, uint32_t)1) {
1017 bus_space_write_raw_multi_4(iot, ioh, txreg,((iot)->write_multi_4((ioh), (txreg), (const u_int32_t *)(
data), (m->m_hdr.mh_len & ~3) >> 2))
1018 data, m->m_len & ~3)((iot)->write_multi_4((ioh), (txreg), (const u_int32_t *)(
data), (m->m_hdr.mh_len & ~3) >> 2))
;
1019 if (m->m_lenm_hdr.mh_len & 3)
1020 bus_space_write_multi_1(iot, ioh, txreg,((iot)->write_multi_1((ioh), (txreg), (data + (m->m_hdr
.mh_len & ~3)), (m->m_hdr.mh_len & 3)))
1021 data + (m->m_len & ~3),((iot)->write_multi_1((ioh), (txreg), (data + (m->m_hdr
.mh_len & ~3)), (m->m_hdr.mh_len & 3)))
1022 m->m_len & 3)((iot)->write_multi_1((ioh), (txreg), (data + (m->m_hdr
.mh_len & ~3)), (m->m_hdr.mh_len & 3)))
;
1023 } else
1024 bus_space_write_multi_1(iot, ioh, txreg,((iot)->write_multi_1((ioh), (txreg), (data), (m->m_hdr
.mh_len)))
1025 data, m->m_len)((iot)->write_multi_1((ioh), (txreg), (data), (m->m_hdr
.mh_len)))
;
1026 m0 = m_free(m);
1027 m = m0;
1028 }
1029 } else {
1030 for (m = m0; m; ) {
1031 data = mtod(m, u_int8_t *)((u_int8_t *)((m)->m_hdr.mh_data));
1032 if (m->m_lenm_hdr.mh_len > 1 && ALIGNED_POINTER(data, uint16_t)1) {
1033 bus_space_write_raw_multi_2(iot, ioh, txreg,((iot)->write_multi_2((ioh), (txreg), (const u_int16_t *)(
data), (m->m_hdr.mh_len & ~1) >> 1))
1034 data, m->m_len & ~1)((iot)->write_multi_2((ioh), (txreg), (const u_int16_t *)(
data), (m->m_hdr.mh_len & ~1) >> 1))
;
1035 if (m->m_lenm_hdr.mh_len & 1)
1036 bus_space_write_1(iot, ioh, txreg,((iot)->write_1((ioh), (txreg), (*(data + m->m_hdr.mh_len
- 1))))
1037 *(data + m->m_len - 1))((iot)->write_1((ioh), (txreg), (*(data + m->m_hdr.mh_len
- 1))))
;
1038 } else
1039 bus_space_write_multi_1(iot, ioh, txreg,((iot)->write_multi_1((ioh), (txreg), (data), (m->m_hdr
.mh_len)))
1040 data, m->m_len)((iot)->write_multi_1((ioh), (txreg), (data), (m->m_hdr
.mh_len)))
;
1041 m0 = m_free(m);
1042 m = m0;
1043 }
1044 }
1045 while (pad--)
1046 bus_space_write_1(iot, ioh, txreg, 0)((iot)->write_1((ioh), (txreg), (0)));
1047
1048 splx(sh)spllower(sh);
1049
1050readcheck:
1051 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS))((iot)->read_2((ioh), (ep_w1_reg(sc, 0x08)))) &
1052 ERR_INCOMPLETE(u_short) (0x8000)) == 0) {
1053 /* We received a complete packet. */
1054 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS)((iot)->read_2((ioh), (0x0e)));
1055
1056 if ((status & S_INTR_LATCH(u_short) (0x0001)) == 0) {
1057 /*
1058 * No interrupt, read the packet and continue
1059 * Is this supposed to happen? Is my motherboard
1060 * completely busted?
1061 */
1062 epread(sc);
1063 } else
1064 /* Got an interrupt, return to get it serviced. */
1065 return;
1066 } else {
1067 /* Check if we are stuck and reset [see XXX comment] */
1068 if (epstatus(sc)) {
1069#ifdef EP_DEBUG
1070 if (ifp->if_flags & IFF_DEBUG0x4)
1071 printf("%s: adapter reset\n",
1072 sc->sc_dev.dv_xname);
1073#endif
1074 epreset(sc);
1075 }
1076 }
1077
1078 goto startagain;
1079}
1080
1081
1082/*
1083 * XXX: The 3c509 card can get in a mode where both the fifo status bit
1084 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set
1085 * We detect this situation and we reset the adapter.
1086 * It happens at times when there is a lot of broadcast traffic
1087 * on the cable (once in a blue moon).
1088 */
1089int
1090epstatus(struct ep_softc *sc)
1091{
1092 bus_space_tag_t iot = sc->sc_iot;
1093 bus_space_handle_t ioh = sc->sc_ioh;
1094 u_int16_t fifost;
1095
1096 /*
1097 * Check the FIFO status and act accordingly
1098 */
1099 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)))
;
1100 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG)((iot)->read_2((ioh), (0x04)));
1101 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
;
1102
1103 if (fifost & FIFOS_RX_UNDERRUN(u_short) 0x2000) {
1104#ifdef EP_DEBUG
1105 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1106 printf("%s: RX underrun\n", sc->sc_dev.dv_xname);
1107#endif
1108 epreset(sc);
1109 return 0;
1110 }
1111
1112 if (fifost & FIFOS_RX_STATUS_OVERRUN(u_short) 0x1000) {
1113#ifdef EP_DEBUG
1114 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1115 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname);
1116#endif
1117 return 1;
1118 }
1119
1120 if (fifost & FIFOS_RX_OVERRUN(u_short) 0x0800) {
1121#ifdef EP_DEBUG
1122 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1123 printf("%s: RX overrun\n", sc->sc_dev.dv_xname);
1124#endif
1125 return 1;
1126 }
1127
1128 if (fifost & FIFOS_TX_OVERRUN(u_short) 0x0400) {
1129#ifdef EP_DEBUG
1130 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1131 printf("%s: TX overrun\n", sc->sc_dev.dv_xname);
1132#endif
1133 epreset(sc);
1134 return 0;
1135 }
1136
1137 return 0;
1138}
1139
1140
1141void
1142eptxstat(struct ep_softc *sc)
1143{
1144 bus_space_tag_t iot = sc->sc_iot;
1145 bus_space_handle_t ioh = sc->sc_ioh;
1146 int i;
1147
1148 /*
1149 * We need to read+write TX_STATUS until we get a 0 status
1150 * in order to turn off the interrupt flag.
1151 */
1152 while ((i = bus_space_read_1(iot, ioh,((iot)->read_1((ioh), (ep_w1_reg(sc, 0x0b))))
1153 ep_w1_reg(sc, EP_W1_TX_STATUS))((iot)->read_1((ioh), (ep_w1_reg(sc, 0x0b))))) & TXS_COMPLETE0x80) {
1154 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS),((iot)->write_1((ioh), (ep_w1_reg(sc, 0x0b)), (0x0)))
1155 0x0)((iot)->write_1((ioh), (ep_w1_reg(sc, 0x0b)), (0x0)));
1156
1157 if (i & TXS_JABBER0x20) {
1158 ++sc->sc_arpcom.ac_if.if_oerrorsif_data.ifi_oerrors;
1159#ifdef EP_DEBUG
1160 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1161 printf("%s: jabber (%x)\n",
1162 sc->sc_dev.dv_xname, i);
1163#endif
1164 epreset(sc);
1165 } else if (i & TXS_UNDERRUN0x10) {
1166 ++sc->sc_arpcom.ac_if.if_oerrorsif_data.ifi_oerrors;
1167#ifdef EP_DEBUG
1168 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1169 printf("%s: fifo underrun (%x) @%d\n",
1170 sc->sc_dev.dv_xname, i,
1171 sc->tx_start_thresh);
1172#endif
1173 if (sc->tx_succ_ok < 100)
1174 sc->tx_start_thresh = min(ETHER_MAX_LEN1518,
1175 sc->tx_start_thresh + 20);
1176 sc->tx_succ_ok = 0;
1177 epreset(sc);
1178 } else if (i & TXS_MAX_COLLISION0x08) {
1179 ++sc->sc_arpcom.ac_if.if_collisionsif_data.ifi_collisions;
1180 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x9<<11))
))
;
1181 ifq_clr_oactive(&sc->sc_arpcom.ac_if.if_snd);
1182 } else
1183 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127;
1184 }
1185}
1186
1187int
1188epintr(void *arg)
1189{
1190 register struct ep_softc *sc = arg;
1191 bus_space_tag_t iot = sc->sc_iot;
1192 bus_space_handle_t ioh = sc->sc_ioh;
1193 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1194 u_int16_t status;
1195 int ret = 0;
1196
1197 for (;;) {
1198 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH)((iot)->write_2((ioh), (0x0e), ((u_short) ((u_short) (0x6800
)|0x01))))
;
1199
1200 status = bus_space_read_2(iot, ioh, EP_STATUS)((iot)->read_2((ioh), (0x0e)));
1201
1202 if ((status & (S_TX_COMPLETE(u_short) (0x0004) | S_TX_AVAIL(u_short) (0x0008) |
1203 S_RX_COMPLETE(u_short) (0x0010) | S_CARD_FAILURE(u_short) (0x0002))) == 0)
1204 break;
1205
1206 ret = 1;
1207
1208 /*
1209 * Acknowledge any interrupts. It's important that we do this
1210 * first, since there would otherwise be a race condition.
1211 * Due to the i386 interrupt queueing, we may get spurious
1212 * interrupts occasionally.
1213 */
1214 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status)((iot)->write_2((ioh), (0x0e), ((u_short) (0x6800) | status
)))
;
1215
1216 if (status & S_RX_COMPLETE(u_short) (0x0010))
1217 epread(sc);
1218 if (status & S_TX_AVAIL(u_short) (0x0008)) {
1219 ifq_clr_oactive(&ifp->if_snd);
1220 epstart(ifp);
1221 }
1222 if (status & S_CARD_FAILURE(u_short) (0x0002)) {
1223 epreset(sc);
1224 return (1);
1225 }
1226 if (status & S_TX_COMPLETE(u_short) (0x0004)) {
1227 eptxstat(sc);
1228 epstart(ifp);
1229 }
1230 }
1231
1232 /* no more interrupts */
1233 return (ret);
1234}
1235
1236void
1237epread(struct ep_softc *sc)
1238{
1239 bus_space_tag_t iot = sc->sc_iot;
1240 bus_space_handle_t ioh = sc->sc_ioh;
1241 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1242 struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
1243 struct mbuf *m;
1244 int len, error = 0;
1245
1246 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS))((iot)->read_2((ioh), (ep_w1_reg(sc, 0x08))));
1247
1248again:
1249#ifdef EP_DEBUG
1250 if (ifp->if_flags & IFF_DEBUG0x4) {
1251 int err = len & ERR_MASK(u_short) (0x7800);
1252 char *s = NULL((void *)0);
1253
1254 if (len & ERR_INCOMPLETE(u_short) (0x8000))
1255 s = "incomplete packet";
1256 else if (err == ERR_OVERRUN(u_short) (0x4000))
1257 s = "packet overrun";
1258 else if (err == ERR_RUNT(u_short) (0x5800))
1259 s = "runt packet";
1260 else if (err == ERR_ALIGNMENT(u_short) (0x6000))
1261 s = "bad alignment";
1262 else if (err == ERR_CRC(u_short) (0x6800))
1263 s = "bad crc";
1264 else if (err == ERR_OVERSIZE(u_short) (0x4800))
1265 s = "oversized packet";
1266 else if (err == ERR_DRIBBLE(u_short) (0x1000))
1267 s = "dribble bits";
1268
1269 if (s)
1270 printf("%s: %s\n", sc->sc_dev.dv_xname, s);
1271 }
1272#endif
1273
1274 if (len & ERR_INCOMPLETE(u_short) (0x8000))
1275 goto done;
1276
1277 if (len & ERR_RX(u_short) (0x4000)) {
1278 ++ifp->if_ierrorsif_data.ifi_ierrors;
1279 error = 1;
1280 goto done;
1281 }
1282
1283 len &= RX_BYTES_MASK(u_short) (0x07ff); /* Lower 11 bits = RX bytes. */
1284
1285 /* Pull packet off interface. */
1286 m = epget(sc, len);
1287 if (m == NULL((void *)0)) {
1288 ifp->if_ierrorsif_data.ifi_ierrors++;
1289 error = 1;
1290 goto done;
1291 }
1292
1293 ml_enqueue(&ml, m);
1294
1295 /*
1296 * In periods of high traffic we can actually receive enough
1297 * packets so that the fifo overrun bit will be set at this point,
1298 * even though we just read a packet. In this case we
1299 * are not going to receive any more interrupts. We check for
1300 * this condition and read again until the fifo is not full.
1301 * We could simplify this test by not using epstatus(), but
1302 * rechecking the RX_STATUS register directly. This test could
1303 * result in unnecessary looping in cases where there is a new
1304 * packet but the fifo is not full, but it will not fix the
1305 * stuck behavior.
1306 *
1307 * Even with this improvement, we still get packet overrun errors
1308 * which are hurting performance. Maybe when I get some more time
1309 * I'll modify epread() so that it can handle RX_EARLY interrupts.
1310 */
1311 if (epstatus(sc)) {
1312 len = bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (ep_w1_reg(sc, 0x08))))
1313 ep_w1_reg(sc, EP_W1_RX_STATUS))((iot)->read_2((ioh), (ep_w1_reg(sc, 0x08))));
1314 /* Check if we are stuck and reset [see XXX comment] */
1315 if (len & ERR_INCOMPLETE(u_short) (0x8000)) {
1316#ifdef EP_DEBUG
1317 if (ifp->if_flags & IFF_DEBUG0x4)
1318 printf("%s: adapter reset\n",
1319 sc->sc_dev.dv_xname);
1320#endif
1321 epreset(sc);
1322 goto done;
1323 }
1324 goto again;
1325 }
1326done:
1327 if (error)
1328 ep_discard_rxtop(iot, ioh);
1329 if_input(ifp, &ml);
1330}
1331
1332struct mbuf *
1333epget(struct ep_softc *sc, int totlen)
1334{
1335 bus_space_tag_t iot = sc->sc_iot;
1336 bus_space_handle_t ioh = sc->sc_ioh;
1337 struct mbuf *m;
1338 caddr_t data;
1339 int len, pad, off, sh, rxreg;
1340
1341 splassert(IPL_NET)do { if (splassert_ctl > 0) { splassert_check(0x7, __func__
); } } while (0)
;
1342
1343 m = sc->mb[sc->next_mb];
1344 sc->mb[sc->next_mb] = NULL((void *)0);
1345 if (m == NULL((void *)0)) {
1346 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES)m_clget((((void *)0)), (0x0002), ((1 << 11)));
1347 /* If the queue is no longer full, refill. */
1348 if (!timeout_pending(&sc->sc_epmbuffill_tmo)((&sc->sc_epmbuffill_tmo)->to_flags & 0x02))
1349 timeout_add(&sc->sc_epmbuffill_tmo, 1);
1350 }
1351 if (!m)
1352 return (NULL((void *)0));
1353
1354 sc->next_mb = (sc->next_mb + 1) % MAX_MBS8;
1355
1356 len = MCLBYTES(1 << 11);
1357 m->m_pkthdrM_dat.MH.MH_pkthdr.len = totlen;
1358 m->m_lenm_hdr.mh_len = totlen;
1359 pad = ALIGN(sizeof(struct ether_header))(((unsigned long)(sizeof(struct ether_header)) + (sizeof(long
) - 1)) &~(sizeof(long) - 1))
- sizeof(struct ether_header);
1360 m->m_datam_hdr.mh_data += pad;
1361 len -= pad;
Value stored to 'len' is never read
1362
1363 /*
1364 * We read the packet at splhigh() so that an interrupt from another
1365 * device doesn't cause the card's buffer to overflow while we're
1366 * reading it. We may still lose packets at other times.
1367 */
1368 sh = splhigh()splraise(0xd);
1369
1370 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_10x00);
1371
1372 off = 0;
1373 while (totlen) {
1374 len = min(totlen, m_trailingspace(m));
1375 if (len == 0)
1376 panic("ep_get: packet does not fit in MCLBYTES");
1377
1378 data = mtod(m, u_int8_t *)((u_int8_t *)((m)->m_hdr.mh_data));
1379 if (EP_IS_BUS_32(sc->bustype)((sc->bustype) & 0x2))
1380 pad = 4 - ((u_long)(data + off) & 0x3);
1381 else
1382 pad = (u_long)(data + off) & 0x1;
1383
1384 if (pad) {
1385 if (pad < len)
1386 pad = len;
1387 bus_space_read_multi_1(iot, ioh, rxreg,((iot)->read_multi_1((ioh), (rxreg), (data + off), (pad)))
1388 data + off, pad)((iot)->read_multi_1((ioh), (rxreg), (data + off), (pad)));
1389 len = pad;
1390 } else if (EP_IS_BUS_32(sc->bustype)((sc->bustype) & 0x2) && len > 3 &&
1391 ALIGNED_POINTER(data, uint32_t)1) {
1392 len &= ~3;
1393 bus_space_read_raw_multi_4(iot, ioh, rxreg,((iot)->read_multi_4((ioh), (rxreg), (u_int32_t *)(data + off
), (len) >> 2))
1394 data + off, len)((iot)->read_multi_4((ioh), (rxreg), (u_int32_t *)(data + off
), (len) >> 2))
;
1395 } else if (len > 1 && ALIGNED_POINTER(data, uint16_t)1) {
1396 len &= ~1;
1397 bus_space_read_raw_multi_2(iot, ioh, rxreg,((iot)->read_multi_2((ioh), (rxreg), (u_int16_t *)(data + off
), (len) >> 1))
1398 data + off, len)((iot)->read_multi_2((ioh), (rxreg), (u_int16_t *)(data + off
), (len) >> 1))
;
1399 } else
1400 bus_space_read_multi_1(iot, ioh, rxreg,((iot)->read_multi_1((ioh), (rxreg), (data + off), (len)))
1401 data + off, len)((iot)->read_multi_1((ioh), (rxreg), (data + off), (len)));
1402
1403 off += len;
1404 totlen -= len;
1405 }
1406
1407 ep_discard_rxtop(iot, ioh);
1408
1409 splx(sh)spllower(sh);
1410
1411 return m;
1412}
1413
1414int
1415epioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1416{
1417 struct ep_softc *sc = ifp->if_softc;
1418 struct ifreq *ifr = (struct ifreq *)data;
1419 int s, error = 0;
1420
1421 s = splnet()splraise(0x7);
1422
1423 switch (cmd) {
1424 case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12)))
:
1425 ifp->if_flags |= IFF_UP0x1;
1426 if (!(ifp->if_flags & IFF_RUNNING0x40))
1427 epinit(sc);
1428 break;
1429
1430 case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16)))
:
1431 if (ifp->if_flags & IFF_UP0x1) {
1432 if (ifp->if_flags & IFF_RUNNING0x40)
1433 error = ENETRESET52;
1434 else
1435 epinit(sc);
1436 } else {
1437 if (ifp->if_flags & IFF_RUNNING0x40)
1438 epstop(sc);
1439 }
1440 break;
1441
1442 case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
8) | ((55)))
:
1443 case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
8) | ((56)))
:
1444 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1445 break;
1446
1447 default:
1448 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data);
1449 }
1450
1451 if (error == ENETRESET52) {
1452 if (ifp->if_flags & IFF_RUNNING0x40)
1453 epreset(sc);
1454 error = 0;
1455 }
1456
1457 splx(s)spllower(s);
1458 return (error);
1459}
1460
1461void
1462epreset(struct ep_softc *sc)
1463{
1464 int s;
1465
1466 s = splnet()splraise(0x7);
1467 epinit(sc);
1468 splx(s)spllower(s);
1469}
1470
1471void
1472epwatchdog(struct ifnet *ifp)
1473{
1474 struct ep_softc *sc = ifp->if_softc;
1475
1476 log(LOG_ERR3, "%s: device timeout\n", sc->sc_dev.dv_xname);
1477 ++sc->sc_arpcom.ac_if.if_oerrorsif_data.ifi_oerrors;
1478
1479 epreset(sc);
1480}
1481
1482void
1483epstop(struct ep_softc *sc)
1484{
1485 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1486 bus_space_tag_t iot = sc->sc_iot;
1487 bus_space_handle_t ioh = sc->sc_ioh;
1488
1489 ifp->if_flags &= ~IFF_RUNNING0x40;
1490 ifq_clr_oactive(&ifp->if_snd);
1491
1492 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
1493 mii_down(&sc->sc_mii);
1494 }
1495
1496 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER0x05) {
1497 /* Clear the FIFO buffer count, thus halting
1498 * any currently-running transactions.
1499 */
1500 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* sanity */
1501 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0)((iot)->write_2((ioh), (0x1c), (0)));
1502 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0)((iot)->write_2((ioh), (0x16), (0)));
1503 }
1504
1505 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x3<<11))
))
;
1506 ep_discard_rxtop(iot, ioh);
1507
1508 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0xa<<11))
))
;
1509 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER)((iot)->write_2((ioh), (0x0e), ((u_short) (0x17<<11)
)))
;
1510
1511 ep_reset_cmd(sc, EP_COMMAND0x0e, RX_RESET(u_short) (0x5<<11));
1512 ep_reset_cmd(sc, EP_COMMAND0x0e, TX_RESET(u_short) (0xb<<11));
1513
1514 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH)((iot)->write_2((ioh), (0x0e), ((u_short) ((u_short) (0x6800
)|0x01))))
;
1515 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK)((iot)->write_2((ioh), (0x0e), ((u_short) (0x0f<<11)
)))
;
1516 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK)((iot)->write_2((ioh), (0x0e), ((u_short) (0x0e<<11)
)))
;
1517 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER)((iot)->write_2((ioh), (0x0e), ((u_short) (0x10<<11)
)))
;
1518
1519 epmbufempty(sc);
1520}
1521
1522/*
1523 * We get eeprom data from the id_port given an offset into the
1524 * eeprom. Basically; after the ID_sequence is sent to all of
1525 * the cards; they enter the ID_CMD state where they will accept
1526 * command requests. 0x80-0xbf loads the eeprom data. We then
1527 * read the port 16 times and with every read; the cards check
1528 * for contention (ie: if one card writes a 0 bit and another
1529 * writes a 1 bit then the host sees a 0. At the end of the cycle;
1530 * each card compares the data on the bus; if there is a difference
1531 * then that card goes into ID_WAIT state again). In the meantime;
1532 * one bit of data is returned in the AX register which is conveniently
1533 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one
1534 * bit of data with each read.
1535 *
1536 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT!
1537 */
1538u_int16_t
1539epreadeeprom(bus_space_tag_t iot, bus_space_handle_t ioh, int offset)
1540{
1541 u_int16_t data = 0;
1542 int i;
1543
1544 bus_space_write_1(iot, ioh, 0, 0x80 + offset)((iot)->write_1((ioh), (0), (0x80 + offset)));
1545 delay(1000)(*delay_func)(1000);
1546 for (i = 0; i < 16; i++)
1547 data = (data << 1) | (bus_space_read_2(iot, ioh, 0)((iot)->read_2((ioh), (0))) & 1);
1548 return (data);
1549}
1550
1551int
1552epbusyeeprom(struct ep_softc *sc)
1553{
1554 bus_space_tag_t iot = sc->sc_iot;
1555 bus_space_handle_t ioh = sc->sc_ioh;
1556 int i = 100, j;
1557
1558 while (i--) {
1559 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND)((iot)->read_2((ioh), (0x0a)));
1560 if (j & EEPROM_BUSY(1<<15))
1561 delay(100)(*delay_func)(100);
1562 else
1563 break;
1564 }
1565 if (!i) {
1566 printf("\n%s: eeprom failed to come ready\n",
1567 sc->sc_dev.dv_xname);
1568 return (1);
1569 }
1570 if (sc->bustype != EP_BUS_PCMCIA0x1 && sc->bustype != EP_BUS_PCI0x3 &&
1571 (j & EEPROM_TST_MODE(1<<14))) {
1572 printf("\n%s: erase pencil mark, or disable PnP mode!\n",
1573 sc->sc_dev.dv_xname);
1574 return (1);
1575 }
1576 return (0);
1577}
1578
1579u_int16_t
1580ep_read_eeprom(struct ep_softc *sc, u_int16_t offset)
1581{
1582 u_int16_t readcmd;
1583
1584 /*
1585 * RoadRunner has a larger EEPROM, so a different read command
1586 * is required.
1587 */
1588 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER0x05)
1589 readcmd = READ_EEPROM_RR0x200;
1590 else
1591 readcmd = READ_EEPROM(1<<7);
1592
1593 if (epbusyeeprom(sc))
1594 return (0); /* XXX why is eeprom busy? */
1595 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_COMMAND,((sc->sc_iot)->write_2((sc->sc_ioh), (0x0a), (readcmd
| offset)))
1596 readcmd | offset)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0a), (readcmd
| offset)))
;
1597 if (epbusyeeprom(sc))
1598 return (0); /* XXX why is eeprom busy? */
1599
1600 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_DATA)((sc->sc_iot)->read_2((sc->sc_ioh), (0x0c))));
1601}
1602
1603void
1604epmbuffill(void *v)
1605{
1606 struct ep_softc *sc = v;
1607 int s, i;
1608
1609 s = splnet()splraise(0x7);
1610 for (i = 0; i < MAX_MBS8; i++) {
1611 if (sc->mb[i] == NULL((void *)0)) {
1612 sc->mb[i] = MCLGETL(NULL, M_DONTWAIT, MCLBYTES)m_clget((((void *)0)), (0x0002), ((1 << 11)));
1613 if (sc->mb[i] == NULL((void *)0))
1614 break;
1615 }
1616 }
1617 /* If the queue was not filled, try again. */
1618 if (i < MAX_MBS8)
1619 timeout_add(&sc->sc_epmbuffill_tmo, 1);
1620 splx(s)spllower(s);
1621}
1622
1623void
1624epmbufempty(struct ep_softc *sc)
1625{
1626 int s, i;
1627
1628 s = splnet()splraise(0x7);
1629 for (i = 0; i<MAX_MBS8; i++) {
1630 if (sc->mb[i]) {
1631 m_freem(sc->mb[i]);
1632 sc->mb[i] = NULL((void *)0);
1633 }
1634 }
1635 sc->next_mb = 0;
1636 timeout_del(&sc->sc_epmbuffill_tmo);
1637 splx(s)spllower(s);
1638}
1639
1640void
1641ep_mii_setbit(struct ep_softc *sc, u_int16_t bit)
1642{
1643 u_int16_t val;
1644
1645 /* We assume we're already in Window 4 */
1646 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT)((sc->sc_iot)->read_2((sc->sc_ioh), (0x08)));
1647 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT,((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (val | bit
)))
1648 val | bit)((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (val | bit
)))
;
1649}
1650
1651void
1652ep_mii_clrbit(struct ep_softc *sc, u_int16_t bit)
1653{
1654 u_int16_t val;
1655
1656 /* We assume we're already in Window 4 */
1657 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT)((sc->sc_iot)->read_2((sc->sc_ioh), (0x08)));
1658 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT,((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (val &
~bit)))
1659 val & ~bit)((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (val &
~bit)))
;
1660}
1661
1662u_int16_t
1663ep_mii_readbit(struct ep_softc *sc, u_int16_t bit)
1664{
1665
1666 /* We assume we're already in Window 4 */
1667 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT)((sc->sc_iot)->read_2((sc->sc_ioh), (0x08))) &
1668 bit);
1669}
1670
1671void
1672ep_mii_sync(struct ep_softc *sc)
1673{
1674 int i;
1675
1676 /* We assume we're already in Window 4 */
1677 ep_mii_clrbit(sc, PHYSMGMT_DIR0x0004);
1678 for (i = 0; i < 32; i++) {
1679 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1680 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1681 }
1682}
1683
1684void
1685ep_mii_sendbits(struct ep_softc *sc, u_int32_t data, int nbits)
1686{
1687 int i;
1688
1689 /* We assume we're already in Window 4 */
1690 ep_mii_setbit(sc, PHYSMGMT_DIR0x0004);
1691 for (i = 1 << (nbits - 1); i; i = i >> 1) {
1692 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1693 ep_mii_readbit(sc, PHYSMGMT_CLK0x0001);
1694 if (data & i)
1695 ep_mii_setbit(sc, PHYSMGMT_DATA0x0002);
1696 else
1697 ep_mii_clrbit(sc, PHYSMGMT_DATA0x0002);
1698 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1699 ep_mii_readbit(sc, PHYSMGMT_CLK0x0001);
1700 }
1701}
1702
1703int
1704ep_mii_readreg(struct device *self, int phy, int reg)
1705{
1706 struct ep_softc *sc = (struct ep_softc *)self;
1707 int val = 0, i, err;
1708
1709 /*
1710 * Read the PHY register by manually driving the MII control lines.
1711 */
1712
1713 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)))
;
1714
1715 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (0)));
1716
1717 ep_mii_sync(sc);
1718 ep_mii_sendbits(sc, MII_COMMAND_START0x01, 2);
1719 ep_mii_sendbits(sc, MII_COMMAND_READ0x02, 2);
1720 ep_mii_sendbits(sc, phy, 5);
1721 ep_mii_sendbits(sc, reg, 5);
1722
1723 ep_mii_clrbit(sc, PHYSMGMT_DIR0x0004);
1724 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1725 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1726 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1727
1728 err = ep_mii_readbit(sc, PHYSMGMT_DATA0x0002);
1729 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1730
1731 /* Even if an error occurs, must still clock out the cycle. */
1732 for (i = 0; i < 16; i++) {
1733 val <<= 1;
1734 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1735 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA0x0002))
1736 val |= 1;
1737 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1738 }
1739 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1740 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1741
1742 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* back to operating window */
1743
1744 return (err ? 0 : val);
1745}
1746
1747void
1748ep_mii_writereg(struct device *self, int phy, int reg, int val)
1749{
1750 struct ep_softc *sc = (struct ep_softc *)self;
1751
1752 /*
1753 * Write the PHY register by manually driving the MII control lines.
1754 */
1755
1756 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)))
;
1757
1758 ep_mii_sync(sc);
1759 ep_mii_sendbits(sc, MII_COMMAND_START0x01, 2);
1760 ep_mii_sendbits(sc, MII_COMMAND_WRITE0x01, 2);
1761 ep_mii_sendbits(sc, phy, 5);
1762 ep_mii_sendbits(sc, reg, 5);
1763 ep_mii_sendbits(sc, MII_COMMAND_ACK0x02, 2);
1764 ep_mii_sendbits(sc, val, 16);
1765
1766 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1767 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1768
1769 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* back to operating window */
1770}
1771
1772void
1773ep_statchg(struct device *self)
1774{
1775 struct ep_softc *sc = (struct ep_softc *)self;
1776 bus_space_tag_t iot = sc->sc_iot;
1777 bus_space_handle_t ioh = sc->sc_ioh;
1778 int mctl;
1779
1780 /* XXX Update ifp->if_baudrate */
1781
1782 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)))
;
1783 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL)((iot)->read_2((ioh), (0x06)));
1784 if (sc->sc_mii.mii_media_active & IFM_FDX0x0000010000000000ULL)
1785 mctl |= MAC_CONTROL_FDX0x20;
1786 else
1787 mctl &= ~MAC_CONTROL_FDX0x20;
1788 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl)((iot)->write_2((ioh), (0x06), (mctl)));
1789 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)))
; /* back to operating window */
1790}