Bug Summary

File:dev/pci/drm/amd/amdgpu/sdma_v2_4.c
Warning:line 995, column 3
Value stored to 'tmp' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name sdma_v2_4.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <linux/delay.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32#include "vi.h"
33#include "vid.h"
34
35#include "oss/oss_2_4_d.h"
36#include "oss/oss_2_4_sh_mask.h"
37
38#include "gmc/gmc_7_1_d.h"
39#include "gmc/gmc_7_1_sh_mask.h"
40
41#include "gca/gfx_8_0_d.h"
42#include "gca/gfx_8_0_enum.h"
43#include "gca/gfx_8_0_sh_mask.h"
44
45#include "bif/bif_5_0_d.h"
46#include "bif/bif_5_0_sh_mask.h"
47
48#include "iceland_sdma_pkt_open.h"
49
50#include "ivsrcid/ivsrcid_vislands30.h"
51
52static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
53static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
54static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
55static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
56
57MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
58MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
59
60static const u32 sdma_offsets[SDMA_MAX_INSTANCE2] =
61{
62 SDMA0_REGISTER_OFFSET0x0,
63 SDMA1_REGISTER_OFFSET0x200
64};
65
66static const u32 golden_settings_iceland_a11[] =
67{
68 mmSDMA0_CHICKEN_BITS0x3405, 0xfc910007, 0x00810007,
69 mmSDMA0_CLK_CTRL0x3403, 0xff000fff, 0x00000000,
70 mmSDMA1_CHICKEN_BITS0x3605, 0xfc910007, 0x00810007,
71 mmSDMA1_CLK_CTRL0x3603, 0xff000fff, 0x00000000,
72};
73
74static const u32 iceland_mgcg_cgcg_init[] =
75{
76 mmSDMA0_CLK_CTRL0x3403, 0xff000ff0, 0x00000100,
77 mmSDMA1_CLK_CTRL0x3603, 0xff000ff0, 0x00000100
78};
79
80/*
81 * sDMA - System DMA
82 * Starting with CIK, the GPU has new asynchronous
83 * DMA engines. These engines are used for compute
84 * and gfx. There are two DMA engines (SDMA0, SDMA1)
85 * and each one supports 1 ring buffer used for gfx
86 * and 2 queues used for compute.
87 *
88 * The programming model is very similar to the CP
89 * (ring buffer, IBs, etc.), but sDMA has it's own
90 * packet format that is different from the PM4 format
91 * used by the CP. sDMA supports copying data, writing
92 * embedded data, solid fills, and a number of other
93 * things. It also has support for tiling/detiling of
94 * buffers.
95 */
96
97static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
98{
99 switch (adev->asic_type) {
100 case CHIP_TOPAZ:
101 amdgpu_device_program_register_sequence(adev,
102 iceland_mgcg_cgcg_init,
103 ARRAY_SIZE(iceland_mgcg_cgcg_init)(sizeof((iceland_mgcg_cgcg_init)) / sizeof((iceland_mgcg_cgcg_init
)[0])));
104 amdgpu_device_program_register_sequence(adev,
105 golden_settings_iceland_a11,
106 ARRAY_SIZE(golden_settings_iceland_a11)(sizeof((golden_settings_iceland_a11)) / sizeof((golden_settings_iceland_a11
)[0])));
107 break;
108 default:
109 break;
110 }
111}
112
113static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
114{
115 int i;
116 for (i = 0; i < adev->sdma.num_instances; i++) {
117 release_firmware(adev->sdma.instance[i].fw);
118 adev->sdma.instance[i].fw = NULL((void *)0);
119 }
120}
121
122/**
123 * sdma_v2_4_init_microcode - load ucode images from disk
124 *
125 * @adev: amdgpu_device pointer
126 *
127 * Use the firmware interface to load the ucode images into
128 * the driver (not loaded into hw).
129 * Returns 0 on success, error on failure.
130 */
131static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
132{
133 const char *chip_name;
134 char fw_name[30];
135 int err = 0, i;
136 struct amdgpu_firmware_info *info = NULL((void *)0);
137 const struct common_firmware_header *header = NULL((void *)0);
138 const struct sdma_firmware_header_v1_0 *hdr;
139
140 DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n");
141
142 switch (adev->asic_type) {
143 case CHIP_TOPAZ:
144 chip_name = "topaz";
145 break;
146 default: BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v2_4.c"
, 146); } while (0);
147 }
148
149 for (i = 0; i < adev->sdma.num_instances; i++) {
150 if (i == 0)
151 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
152 else
153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
154 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
155 if (err)
156 goto out;
157 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
158 if (err)
159 goto out;
160 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
161 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version));
162 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version)((__uint32_t)(hdr->ucode_feature_version));
163 if (adev->sdma.instance[i].feature_version >= 20)
164 adev->sdma.instance[i].burst_nop = true1;
165
166 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
167 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
168 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
169 info->fw = adev->sdma.instance[i].fw;
170 header = (const struct common_firmware_header *)info->fw->data;
171 adev->firmware.fw_size +=
172 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
173 }
174 }
175
176out:
177 if (err) {
178 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name)printk("\0013" "amdgpu: " "sdma_v2_4: Failed to load firmware \"%s\"\n"
, fw_name);
179 for (i = 0; i < adev->sdma.num_instances; i++) {
180 release_firmware(adev->sdma.instance[i].fw);
181 adev->sdma.instance[i].fw = NULL((void *)0);
182 }
183 }
184 return err;
185}
186
187/**
188 * sdma_v2_4_ring_get_rptr - get the current read pointer
189 *
190 * @ring: amdgpu ring pointer
191 *
192 * Get the current rptr from the hardware (VI+).
193 */
194static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
195{
196 /* XXX check if swapping is necessary on BE */
197 return ring->adev->wb.wb[ring->rptr_offs] >> 2;
198}
199
200/**
201 * sdma_v2_4_ring_get_wptr - get the current write pointer
202 *
203 * @ring: amdgpu ring pointer
204 *
205 * Get the current wptr from the hardware (VI+).
206 */
207static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
208{
209 struct amdgpu_device *adev = ring->adev;
210 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me])amdgpu_device_rreg(adev, (0x3484 + sdma_offsets[ring->me])
, 0) >> 2;
211
212 return wptr;
213}
214
215/**
216 * sdma_v2_4_ring_set_wptr - commit the write pointer
217 *
218 * @ring: amdgpu ring pointer
219 *
220 * Write the wptr back to the hardware (VI+).
221 */
222static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
223{
224 struct amdgpu_device *adev = ring->adev;
225
226 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2)amdgpu_device_wreg(adev, (0x3484 + sdma_offsets[ring->me])
, (((u32)(ring->wptr)) << 2), 0);
227}
228
229static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
230{
231 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
232 int i;
233
234 for (i = 0; i < count; i++)
235 if (sdma && sdma->burst_nop && (i == 0))
236 amdgpu_ring_write(ring, ring->funcs->nop |
237 SDMA_PKT_NOP_HEADER_COUNT(count - 1)(((count - 1) & 0x00003FFF) << 16));
238 else
239 amdgpu_ring_write(ring, ring->funcs->nop);
240}
241
242/**
243 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
244 *
245 * @ring: amdgpu ring pointer
246 * @ib: IB object to schedule
247 *
248 * Schedule an IB in the DMA ring (VI).
249 */
250static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
251 struct amdgpu_job *job,
252 struct amdgpu_ib *ib,
253 uint32_t flags)
254{
255 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
256
257 /* IB packet must end on a 8 DW boundary */
258 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)((u32)(ring->wptr))) & 7);
259
260 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT)(((4) & 0x000000FF) << 0) |
261 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)(((vmid & 0xf) & 0x0000000F) << 16));
262 /* base must be 32 byte aligned */
263 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)) & 0xffffffe0);
264 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
265 amdgpu_ring_write(ring, ib->length_dw);
266 amdgpu_ring_write(ring, 0);
267 amdgpu_ring_write(ring, 0);
268
269}
270
271/**
272 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
273 *
274 * @ring: amdgpu ring pointer
275 *
276 * Emit an hdp flush packet on the requested DMA ring.
277 */
278static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
279{
280 u32 ref_and_mask = 0;
281
282 if (ring->me == 0)
283 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1)(((ref_and_mask) & ~0x400) | (0x400 & ((1) << 0xa
)));
284 else
285 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1)(((ref_and_mask) & ~0x800) | (0x800 & ((1) << 0xb
)));
286
287 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
288 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1)(((1) & 0x00000001) << 26) |
289 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28)); /* == */
290 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE0x1538 << 2);
291 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ0x1537 << 2);
292 amdgpu_ring_write(ring, ref_and_mask); /* reference */
293 amdgpu_ring_write(ring, ref_and_mask); /* mask */
294 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
295 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0)); /* retry count, poll interval */
296}
297
298/**
299 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
300 *
301 * @ring: amdgpu ring pointer
302 * @fence: amdgpu fence object
303 *
304 * Add a DMA fence packet to the ring to write
305 * the fence seq number and DMA trap packet to generate
306 * an interrupt if needed (VI).
307 */
308static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
309 unsigned flags)
310{
311 bool_Bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT(1 << 0);
312 /* write the fence */
313 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0));
314 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
315 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
316 amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));
317
318 /* optionally write high bits as well */
319 if (write64bit) {
320 addr += 4;
321 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0));
322 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
323 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
324 amdgpu_ring_write(ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
325 }
326
327 /* generate an interrupt */
328 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)(((6) & 0x000000FF) << 0));
329 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)(((0) & 0x0FFFFFFF) << 0));
330}
331
332/**
333 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
334 *
335 * @adev: amdgpu_device pointer
336 *
337 * Stop the gfx async dma ring buffers (VI).
338 */
339static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
340{
341 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
342 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
343 u32 rb_cntl, ib_cntl;
344 int i;
345
346 if ((adev->mman.buffer_funcs_ring == sdma0) ||
347 (adev->mman.buffer_funcs_ring == sdma1))
348 amdgpu_ttm_set_buffer_funcs_status(adev, false0);
349
350 for (i = 0; i < adev->sdma.num_instances; i++) {
351 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3480 + sdma_offsets[i]), 0);
352 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0)(((rb_cntl) & ~0x1) | (0x1 & ((0) << 0x0)));
353 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl)amdgpu_device_wreg(adev, (0x3480 + sdma_offsets[i]), (rb_cntl
), 0);
354 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x348a + sdma_offsets[i]), 0);
355 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0)(((ib_cntl) & ~0x1) | (0x1 & ((0) << 0x0)));
356 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl)amdgpu_device_wreg(adev, (0x348a + sdma_offsets[i]), (ib_cntl
), 0);
357 }
358}
359
360/**
361 * sdma_v2_4_rlc_stop - stop the compute async dma engines
362 *
363 * @adev: amdgpu_device pointer
364 *
365 * Stop the compute async dma queues (VI).
366 */
367static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
368{
369 /* XXX todo */
370}
371
372/**
373 * sdma_v2_4_enable - stop the async dma engines
374 *
375 * @adev: amdgpu_device pointer
376 * @enable: enable/disable the DMA MEs.
377 *
378 * Halt or unhalt the async dma engines (VI).
379 */
380static void sdma_v2_4_enable(struct amdgpu_device *adev, bool_Bool enable)
381{
382 u32 f32_cntl;
383 int i;
384
385 if (!enable) {
386 sdma_v2_4_gfx_stop(adev);
387 sdma_v2_4_rlc_stop(adev);
388 }
389
390 for (i = 0; i < adev->sdma.num_instances; i++) {
391 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3412 + sdma_offsets[i]), 0);
392 if (enable)
393 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0)(((f32_cntl) & ~0x1) | (0x1 & ((0) << 0x0)));
394 else
395 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1)(((f32_cntl) & ~0x1) | (0x1 & ((1) << 0x0)));
396 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl)amdgpu_device_wreg(adev, (0x3412 + sdma_offsets[i]), (f32_cntl
), 0);
397 }
398}
399
400/**
401 * sdma_v2_4_gfx_resume - setup and start the async dma engines
402 *
403 * @adev: amdgpu_device pointer
404 *
405 * Set up the gfx DMA ring buffers and enable them (VI).
406 * Returns 0 for success, error for failure.
407 */
408static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
409{
410 struct amdgpu_ring *ring;
411 u32 rb_cntl, ib_cntl;
412 u32 rb_bufsz;
413 u32 wb_offset;
414 int i, j, r;
415
416 for (i = 0; i < adev->sdma.num_instances; i++) {
417 ring = &adev->sdma.instance[i].ring;
418 wb_offset = (ring->rptr_offs * 4);
419
420 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
421 for (j = 0; j < 16; j++) {
422 vi_srbm_select(adev, 0, 0, 0, j);
423 /* SDMA GFX */
424 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x34a7 + sdma_offsets[i]), (0), 0);
425 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x34a8 + sdma_offsets[i]), (0), 0);
426 }
427 vi_srbm_select(adev, 0, 0, 0, 0);
428 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
429
430 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3406 + sdma_offsets[i]), (adev->
gfx.config.gb_addr_config & 0x70), 0)
431 adev->gfx.config.gb_addr_config & 0x70)amdgpu_device_wreg(adev, (0x3406 + sdma_offsets[i]), (adev->
gfx.config.gb_addr_config & 0x70), 0);
432
433 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x3409 + sdma_offsets[i]), (0), 0);
434
435 /* Set ring buffer size in dwords */
436 rb_bufsz = order_base_2(ring->ring_size / 4)drm_order(ring->ring_size / 4);
437 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3480 + sdma_offsets[i]), 0);
438 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz)(((rb_cntl) & ~0x3e) | (0x3e & ((rb_bufsz) << 0x1
)));
439#ifdef __BIG_ENDIAN
440 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1)(((rb_cntl) & ~0x200) | (0x200 & ((1) << 0x9)));
441 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,(((rb_cntl) & ~0x2000) | (0x2000 & ((1) << 0xd)
))
442 RPTR_WRITEBACK_SWAP_ENABLE, 1)(((rb_cntl) & ~0x2000) | (0x2000 & ((1) << 0xd)
));
443#endif
444 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl)amdgpu_device_wreg(adev, (0x3480 + sdma_offsets[i]), (rb_cntl
), 0);
445
446 /* Initialize the ring buffer's read and write pointers */
447 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x3483 + sdma_offsets[i]), (0), 0);
448 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x3484 + sdma_offsets[i]), (0), 0);
449 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x348b + sdma_offsets[i]), (0), 0);
450 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x348c + sdma_offsets[i]), (0), 0);
451
452 /* set the wb address whether it's enabled or not */
453 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3488 + sdma_offsets[i]), (((u32)(
((adev->wb.gpu_addr + wb_offset) >> 16) >> 16)
) & 0xFFFFFFFF), 0)
454 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF)amdgpu_device_wreg(adev, (0x3488 + sdma_offsets[i]), (((u32)(
((adev->wb.gpu_addr + wb_offset) >> 16) >> 16)
) & 0xFFFFFFFF), 0);
455 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3489 + sdma_offsets[i]), (((u32)(
adev->wb.gpu_addr + wb_offset)) & 0xFFFFFFFC), 0)
456 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)amdgpu_device_wreg(adev, (0x3489 + sdma_offsets[i]), (((u32)(
adev->wb.gpu_addr + wb_offset)) & 0xFFFFFFFC), 0);
457
458 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1)(((rb_cntl) & ~0x1000) | (0x1000 & ((1) << 0xc)
));
459
460 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8)amdgpu_device_wreg(adev, (0x3481 + sdma_offsets[i]), (ring->
gpu_addr >> 8), 0);
461 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40)amdgpu_device_wreg(adev, (0x3482 + sdma_offsets[i]), (ring->
gpu_addr >> 40), 0);
462
463 ring->wptr = 0;
464 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2)amdgpu_device_wreg(adev, (0x3484 + sdma_offsets[i]), (((u32)(
ring->wptr)) << 2), 0);
465
466 /* enable DMA RB */
467 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1)(((rb_cntl) & ~0x1) | (0x1 & ((1) << 0x0)));
468 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl)amdgpu_device_wreg(adev, (0x3480 + sdma_offsets[i]), (rb_cntl
), 0);
469
470 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x348a + sdma_offsets[i]), 0);
471 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1)(((ib_cntl) & ~0x1) | (0x1 & ((1) << 0x0)));
472#ifdef __BIG_ENDIAN
473 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1)(((ib_cntl) & ~0x10) | (0x10 & ((1) << 0x4)));
474#endif
475 /* enable DMA IBs */
476 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl)amdgpu_device_wreg(adev, (0x348a + sdma_offsets[i]), (ib_cntl
), 0);
477
478 ring->sched.ready = true1;
479 }
480
481 sdma_v2_4_enable(adev, true1);
482 for (i = 0; i < adev->sdma.num_instances; i++) {
483 ring = &adev->sdma.instance[i].ring;
484 r = amdgpu_ring_test_helper(ring);
485 if (r)
486 return r;
487
488 if (adev->mman.buffer_funcs_ring == ring)
489 amdgpu_ttm_set_buffer_funcs_status(adev, true1);
490 }
491
492 return 0;
493}
494
495/**
496 * sdma_v2_4_rlc_resume - setup and start the async dma engines
497 *
498 * @adev: amdgpu_device pointer
499 *
500 * Set up the compute DMA queues and enable them (VI).
501 * Returns 0 for success, error for failure.
502 */
503static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
504{
505 /* XXX todo */
506 return 0;
507}
508
509
510/**
511 * sdma_v2_4_start - setup and start the async dma engines
512 *
513 * @adev: amdgpu_device pointer
514 *
515 * Set up the DMA engines and enable them (VI).
516 * Returns 0 for success, error for failure.
517 */
518static int sdma_v2_4_start(struct amdgpu_device *adev)
519{
520 int r;
521
522 /* halt the engine before programing */
523 sdma_v2_4_enable(adev, false0);
524
525 /* start the gfx rings and rlc compute queues */
526 r = sdma_v2_4_gfx_resume(adev);
527 if (r)
528 return r;
529 r = sdma_v2_4_rlc_resume(adev);
530 if (r)
531 return r;
532
533 return 0;
534}
535
536/**
537 * sdma_v2_4_ring_test_ring - simple async dma engine test
538 *
539 * @ring: amdgpu_ring structure holding ring information
540 *
541 * Test the DMA engine by writing using it to write an
542 * value to memory. (VI).
543 * Returns 0 for success, error for failure.
544 */
545static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
546{
547 struct amdgpu_device *adev = ring->adev;
548 unsigned i;
549 unsigned index;
550 int r;
551 u32 tmp;
552 u64 gpu_addr;
553
554 r = amdgpu_device_wb_get(adev, &index);
555 if (r)
556 return r;
557
558 gpu_addr = adev->wb.gpu_addr + (index * 4);
559 tmp = 0xCAFEDEAD;
560 adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp));
561
562 r = amdgpu_ring_alloc(ring, 5);
563 if (r)
564 goto error_free_wb;
565
566 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
567 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8));
568 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)((u32)(gpu_addr)));
569 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)));
570 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)(((1) & 0x003FFFFF) << 0));
571 amdgpu_ring_write(ring, 0xDEADBEEF);
572 amdgpu_ring_commit(ring);
573
574 for (i = 0; i < adev->usec_timeout; i++) {
575 tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index]));
576 if (tmp == 0xDEADBEEF)
577 break;
578 udelay(1);
579 }
580
581 if (i >= adev->usec_timeout)
582 r = -ETIMEDOUT60;
583
584error_free_wb:
585 amdgpu_device_wb_free(adev, index);
586 return r;
587}
588
589/**
590 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
591 *
592 * @ring: amdgpu_ring structure holding ring information
593 *
594 * Test a simple IB in the DMA ring (VI).
595 * Returns 0 on success, error on failure.
596 */
597static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
598{
599 struct amdgpu_device *adev = ring->adev;
600 struct amdgpu_ib ib;
601 struct dma_fence *f = NULL((void *)0);
602 unsigned index;
603 u32 tmp = 0;
604 u64 gpu_addr;
605 long r;
606
607 r = amdgpu_device_wb_get(adev, &index);
608 if (r)
609 return r;
610
611 gpu_addr = adev->wb.gpu_addr + (index * 4);
612 tmp = 0xCAFEDEAD;
613 adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp));
614 memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib)));
615 r = amdgpu_ib_get(adev, NULL((void *)0), 256,
616 AMDGPU_IB_POOL_DIRECT, &ib);
617 if (r)
618 goto err0;
619
620 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
621 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8);
622 ib.ptr[1] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
623 ib.ptr[2] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
624 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)(((1) & 0x003FFFFF) << 0);
625 ib.ptr[4] = 0xDEADBEEF;
626 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
627 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
628 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
629 ib.length_dw = 8;
630
631 r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f);
632 if (r)
633 goto err1;
634
635 r = dma_fence_wait_timeout(f, false0, timeout);
636 if (r == 0) {
637 r = -ETIMEDOUT60;
638 goto err1;
639 } else if (r < 0) {
640 goto err1;
641 }
642 tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index]));
643 if (tmp == 0xDEADBEEF)
644 r = 0;
645 else
646 r = -EINVAL22;
647
648err1:
649 amdgpu_ib_free(adev, &ib, NULL((void *)0));
650 dma_fence_put(f);
651err0:
652 amdgpu_device_wb_free(adev, index);
653 return r;
654}
655
656/**
657 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
658 *
659 * @ib: indirect buffer to fill with commands
660 * @pe: addr of the page entry
661 * @src: src addr to copy from
662 * @count: number of page entries to update
663 *
664 * Update PTEs by copying them from the GART using sDMA (CIK).
665 */
666static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
667 uint64_t pe, uint64_t src,
668 unsigned count)
669{
670 unsigned bytes = count * 8;
671
672 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) |
673 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8);
674 ib->ptr[ib->length_dw++] = bytes;
675 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
676 ib->ptr[ib->length_dw++] = lower_32_bits(src)((u32)(src));
677 ib->ptr[ib->length_dw++] = upper_32_bits(src)((u32)(((src) >> 16) >> 16));
678 ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe));
679 ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));
680}
681
682/**
683 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
684 *
685 * @ib: indirect buffer to fill with commands
686 * @pe: addr of the page entry
687 * @value: dst addr to write into pe
688 * @count: number of page entries to update
689 * @incr: increase next addr by incr bytes
690 *
691 * Update PTEs by writing them manually using sDMA (CIK).
692 */
693static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
694 uint64_t value, unsigned count,
695 uint32_t incr)
696{
697 unsigned ndw = count * 2;
698
699 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) |
700 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8);
701 ib->ptr[ib->length_dw++] = pe;
702 ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));
703 ib->ptr[ib->length_dw++] = ndw;
704 for (; ndw > 0; ndw -= 2) {
705 ib->ptr[ib->length_dw++] = lower_32_bits(value)((u32)(value));
706 ib->ptr[ib->length_dw++] = upper_32_bits(value)((u32)(((value) >> 16) >> 16));
707 value += incr;
708 }
709}
710
711/**
712 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
713 *
714 * @ib: indirect buffer to fill with commands
715 * @pe: addr of the page entry
716 * @addr: dst addr to write into pe
717 * @count: number of page entries to update
718 * @incr: increase next addr by incr bytes
719 * @flags: access flags
720 *
721 * Update the page tables using sDMA (CIK).
722 */
723static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
724 uint64_t addr, unsigned count,
725 uint32_t incr, uint64_t flags)
726{
727 /* for physically contiguous pages (vram) */
728 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE)(((12) & 0x000000FF) << 0);
729 ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); /* dst addr */
730 ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16));
731 ib->ptr[ib->length_dw++] = lower_32_bits(flags)((u32)(flags)); /* mask */
732 ib->ptr[ib->length_dw++] = upper_32_bits(flags)((u32)(((flags) >> 16) >> 16));
733 ib->ptr[ib->length_dw++] = lower_32_bits(addr)((u32)(addr)); /* value */
734 ib->ptr[ib->length_dw++] = upper_32_bits(addr)((u32)(((addr) >> 16) >> 16));
735 ib->ptr[ib->length_dw++] = incr; /* increment size */
736 ib->ptr[ib->length_dw++] = 0;
737 ib->ptr[ib->length_dw++] = count; /* number of entries */
738}
739
740/**
741 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
742 *
743 * @ib: indirect buffer to fill with padding
744 *
745 */
746static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
747{
748 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
749 u32 pad_count;
750 int i;
751
752 pad_count = (-ib->length_dw) & 7;
753 for (i = 0; i < pad_count; i++)
754 if (sdma && sdma->burst_nop && (i == 0))
755 ib->ptr[ib->length_dw++] =
756 SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0) |
757 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1)(((pad_count - 1) & 0x00003FFF) << 16);
758 else
759 ib->ptr[ib->length_dw++] =
760 SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0);
761}
762
763/**
764 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
765 *
766 * @ring: amdgpu_ring pointer
767 *
768 * Make sure all previous operations are completed (CIK).
769 */
770static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
771{
772 uint32_t seq = ring->fence_drv.sync_seq;
773 uint64_t addr = ring->fence_drv.gpu_addr;
774
775 /* wait for idle */
776 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
777 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) |
778 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28) | /* equal */
779 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)(((1) & 0x00000001) << 31));
780 amdgpu_ring_write(ring, addr & 0xfffffffc);
781 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)) & 0xffffffff);
782 amdgpu_ring_write(ring, seq); /* reference */
783 amdgpu_ring_write(ring, 0xffffffff); /* mask */
784 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
785 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)(((4) & 0x0000FFFF) << 0)); /* retry count, poll interval */
786}
787
788/**
789 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
790 *
791 * @ring: amdgpu_ring pointer
792 * @vm: amdgpu_vm pointer
793 *
794 * Update the page table base and flush the VM TLB
795 * using sDMA (VI).
796 */
797static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
798 unsigned vmid, uint64_t pd_addr)
799{
800 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr)(ring)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((ring
), (vmid), (pd_addr));
801
802 /* wait for flush */
803 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) |
804 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) |
805 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)(((0) & 0x00000007) << 28)); /* always */
806 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST0x51e << 2);
807 amdgpu_ring_write(ring, 0);
808 amdgpu_ring_write(ring, 0); /* reference */
809 amdgpu_ring_write(ring, 0); /* mask */
810 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) |
811 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0)); /* retry count, poll interval */
812}
813
814static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
815 uint32_t reg, uint32_t val)
816{
817 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE)(((14) & 0x000000FF) << 0) |
818 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)(((0xf) & 0x0000000F) << 28));
819 amdgpu_ring_write(ring, reg);
820 amdgpu_ring_write(ring, val);
821}
822
823static int sdma_v2_4_early_init(void *handle)
824{
825 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
826
827 adev->sdma.num_instances = SDMA_MAX_INSTANCE2;
828
829 sdma_v2_4_set_ring_funcs(adev);
830 sdma_v2_4_set_buffer_funcs(adev);
831 sdma_v2_4_set_vm_pte_funcs(adev);
832 sdma_v2_4_set_irq_funcs(adev);
833
834 return 0;
835}
836
837static int sdma_v2_4_sw_init(void *handle)
838{
839 struct amdgpu_ring *ring;
840 int r, i;
841 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
842
843 /* SDMA trap event */
844 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_SDMA_TRAP0x000000e0,
845 &adev->sdma.trap_irq);
846 if (r)
847 return r;
848
849 /* SDMA Privileged inst */
850 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, 241,
851 &adev->sdma.illegal_inst_irq);
852 if (r)
853 return r;
854
855 /* SDMA Privileged inst */
856 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE0x000000f7,
857 &adev->sdma.illegal_inst_irq);
858 if (r)
859 return r;
860
861 r = sdma_v2_4_init_microcode(adev);
862 if (r) {
863 DRM_ERROR("Failed to load sdma firmware!\n")__drm_err("Failed to load sdma firmware!\n");
864 return r;
865 }
866
867 for (i = 0; i < adev->sdma.num_instances; i++) {
868 ring = &adev->sdma.instance[i].ring;
869 ring->ring_obj = NULL((void *)0);
870 ring->use_doorbell = false0;
871 snprintf(ring->name, sizeof(ring->name), "sdma%d", i);
872 r = amdgpu_ring_init(adev, ring, 1024,
873 &adev->sdma.trap_irq,
874 (i == 0) ?
875 AMDGPU_SDMA_IRQ_INSTANCE0 :
876 AMDGPU_SDMA_IRQ_INSTANCE1,
877 AMDGPU_RING_PRIO_DEFAULT1);
878 if (r)
879 return r;
880 }
881
882 return r;
883}
884
885static int sdma_v2_4_sw_fini(void *handle)
886{
887 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
888 int i;
889
890 for (i = 0; i < adev->sdma.num_instances; i++)
891 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
892
893 sdma_v2_4_free_microcode(adev);
894 return 0;
895}
896
897static int sdma_v2_4_hw_init(void *handle)
898{
899 int r;
900 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
901
902 sdma_v2_4_init_golden_registers(adev);
903
904 r = sdma_v2_4_start(adev);
905 if (r)
906 return r;
907
908 return r;
909}
910
911static int sdma_v2_4_hw_fini(void *handle)
912{
913 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
914
915 sdma_v2_4_enable(adev, false0);
916
917 return 0;
918}
919
920static int sdma_v2_4_suspend(void *handle)
921{
922 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
923
924 return sdma_v2_4_hw_fini(adev);
925}
926
927static int sdma_v2_4_resume(void *handle)
928{
929 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
930
931 return sdma_v2_4_hw_init(adev);
932}
933
934static bool_Bool sdma_v2_4_is_idle(void *handle)
935{
936 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
937 u32 tmp = RREG32(mmSRBM_STATUS2)amdgpu_device_rreg(adev, (0x393), 0);
938
939 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK0x20 |
940 SRBM_STATUS2__SDMA1_BUSY_MASK0x40))
941 return false0;
942
943 return true1;
944}
945
946static int sdma_v2_4_wait_for_idle(void *handle)
947{
948 unsigned i;
949 u32 tmp;
950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
951
952 for (i = 0; i < adev->usec_timeout; i++) {
953 tmp = RREG32(mmSRBM_STATUS2)amdgpu_device_rreg(adev, (0x393), 0) & (SRBM_STATUS2__SDMA_BUSY_MASK0x20 |
954 SRBM_STATUS2__SDMA1_BUSY_MASK0x40);
955
956 if (!tmp)
957 return 0;
958 udelay(1);
959 }
960 return -ETIMEDOUT60;
961}
962
963static int sdma_v2_4_soft_reset(void *handle)
964{
965 u32 srbm_soft_reset = 0;
966 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
967 u32 tmp = RREG32(mmSRBM_STATUS2)amdgpu_device_rreg(adev, (0x393), 0);
968
969 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK0x20) {
970 /* sdma0 */
971 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3412 + 0x0), 0);
972 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
973 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp)amdgpu_device_wreg(adev, (0x3412 + 0x0), (tmp), 0);
974 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK0x100000;
975 }
976 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK0x40) {
977 /* sdma1 */
978 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3412 + 0x200), 0);
979 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
980 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp)amdgpu_device_wreg(adev, (0x3412 + 0x200), (tmp), 0);
981 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK0x40;
982 }
983
984 if (srbm_soft_reset) {
985 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
986 tmp |= srbm_soft_reset;
987 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
988 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
989 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
990
991 udelay(50);
992
993 tmp &= ~srbm_soft_reset;
994 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
995 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
Value stored to 'tmp' is never read
996
997 /* Wait a little for things to settle down */
998 udelay(50);
999 }
1000
1001 return 0;
1002}
1003
1004static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1005 struct amdgpu_irq_src *src,
1006 unsigned type,
1007 enum amdgpu_interrupt_state state)
1008{
1009 u32 sdma_cntl;
1010
1011 switch (type) {
1012 case AMDGPU_SDMA_IRQ_INSTANCE0:
1013 switch (state) {
1014 case AMDGPU_IRQ_STATE_DISABLE:
1015 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3404 + 0x0), 0);
1016 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0)(((sdma_cntl) & ~0x1) | (0x1 & ((0) << 0x0)));
1017 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl)amdgpu_device_wreg(adev, (0x3404 + 0x0), (sdma_cntl), 0);
1018 break;
1019 case AMDGPU_IRQ_STATE_ENABLE:
1020 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3404 + 0x0), 0);
1021 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1)(((sdma_cntl) & ~0x1) | (0x1 & ((1) << 0x0)));
1022 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl)amdgpu_device_wreg(adev, (0x3404 + 0x0), (sdma_cntl), 0);
1023 break;
1024 default:
1025 break;
1026 }
1027 break;
1028 case AMDGPU_SDMA_IRQ_INSTANCE1:
1029 switch (state) {
1030 case AMDGPU_IRQ_STATE_DISABLE:
1031 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3404 + 0x200), 0);
1032 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0)(((sdma_cntl) & ~0x1) | (0x1 & ((0) << 0x0)));
1033 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl)amdgpu_device_wreg(adev, (0x3404 + 0x200), (sdma_cntl), 0);
1034 break;
1035 case AMDGPU_IRQ_STATE_ENABLE:
1036 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3404 + 0x200), 0);
1037 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1)(((sdma_cntl) & ~0x1) | (0x1 & ((1) << 0x0)));
1038 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl)amdgpu_device_wreg(adev, (0x3404 + 0x200), (sdma_cntl), 0);
1039 break;
1040 default:
1041 break;
1042 }
1043 break;
1044 default:
1045 break;
1046 }
1047 return 0;
1048}
1049
1050static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1051 struct amdgpu_irq_src *source,
1052 struct amdgpu_iv_entry *entry)
1053{
1054 u8 instance_id, queue_id;
1055
1056 instance_id = (entry->ring_id & 0x3) >> 0;
1057 queue_id = (entry->ring_id & 0xc) >> 2;
1058 DRM_DEBUG("IH: SDMA trap\n")__drm_dbg(DRM_UT_CORE, "IH: SDMA trap\n");
1059 switch (instance_id) {
1060 case 0:
1061 switch (queue_id) {
1062 case 0:
1063 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1064 break;
1065 case 1:
1066 /* XXX compute */
1067 break;
1068 case 2:
1069 /* XXX compute */
1070 break;
1071 }
1072 break;
1073 case 1:
1074 switch (queue_id) {
1075 case 0:
1076 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1077 break;
1078 case 1:
1079 /* XXX compute */
1080 break;
1081 case 2:
1082 /* XXX compute */
1083 break;
1084 }
1085 break;
1086 }
1087 return 0;
1088}
1089
1090static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1091 struct amdgpu_irq_src *source,
1092 struct amdgpu_iv_entry *entry)
1093{
1094 u8 instance_id, queue_id;
1095
1096 DRM_ERROR("Illegal instruction in SDMA command stream\n")__drm_err("Illegal instruction in SDMA command stream\n");
1097 instance_id = (entry->ring_id & 0x3) >> 0;
1098 queue_id = (entry->ring_id & 0xc) >> 2;
1099
1100 if (instance_id <= 1 && queue_id == 0)
1101 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1102 return 0;
1103}
1104
1105static int sdma_v2_4_set_clockgating_state(void *handle,
1106 enum amd_clockgating_state state)
1107{
1108 /* XXX handled via the smc on VI */
1109 return 0;
1110}
1111
1112static int sdma_v2_4_set_powergating_state(void *handle,
1113 enum amd_powergating_state state)
1114{
1115 return 0;
1116}
1117
1118static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1119 .name = "sdma_v2_4",
1120 .early_init = sdma_v2_4_early_init,
1121 .late_init = NULL((void *)0),
1122 .sw_init = sdma_v2_4_sw_init,
1123 .sw_fini = sdma_v2_4_sw_fini,
1124 .hw_init = sdma_v2_4_hw_init,
1125 .hw_fini = sdma_v2_4_hw_fini,
1126 .suspend = sdma_v2_4_suspend,
1127 .resume = sdma_v2_4_resume,
1128 .is_idle = sdma_v2_4_is_idle,
1129 .wait_for_idle = sdma_v2_4_wait_for_idle,
1130 .soft_reset = sdma_v2_4_soft_reset,
1131 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1132 .set_powergating_state = sdma_v2_4_set_powergating_state,
1133};
1134
1135static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1136 .type = AMDGPU_RING_TYPE_SDMA,
1137 .align_mask = 0xf,
1138 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0),
1139 .support_64bit_ptrs = false0,
1140 .get_rptr = sdma_v2_4_ring_get_rptr,
1141 .get_wptr = sdma_v2_4_ring_get_wptr,
1142 .set_wptr = sdma_v2_4_ring_set_wptr,
1143 .emit_frame_size =
1144 6 + /* sdma_v2_4_ring_emit_hdp_flush */
1145 3 + /* hdp invalidate */
1146 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1147 VI_FLUSH_GPU_TLB_NUM_WREG3 * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1148 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1149 .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1150 .emit_ib = sdma_v2_4_ring_emit_ib,
1151 .emit_fence = sdma_v2_4_ring_emit_fence,
1152 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1153 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1154 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1155 .test_ring = sdma_v2_4_ring_test_ring,
1156 .test_ib = sdma_v2_4_ring_test_ib,
1157 .insert_nop = sdma_v2_4_ring_insert_nop,
1158 .pad_ib = sdma_v2_4_ring_pad_ib,
1159 .emit_wreg = sdma_v2_4_ring_emit_wreg,
1160};
1161
1162static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1163{
1164 int i;
1165
1166 for (i = 0; i < adev->sdma.num_instances; i++) {
1167 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1168 adev->sdma.instance[i].ring.me = i;
1169 }
1170}
1171
1172static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1173 .set = sdma_v2_4_set_trap_irq_state,
1174 .process = sdma_v2_4_process_trap_irq,
1175};
1176
1177static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1178 .process = sdma_v2_4_process_illegal_inst_irq,
1179};
1180
1181static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1182{
1183 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1184 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1185 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1186}
1187
1188/**
1189 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1190 *
1191 * @ring: amdgpu_ring structure holding ring information
1192 * @src_offset: src GPU address
1193 * @dst_offset: dst GPU address
1194 * @byte_count: number of bytes to xfer
1195 *
1196 * Copy GPU buffers using the DMA engine (VI).
1197 * Used by the amdgpu ttm implementation to move pages if
1198 * registered as the asic copy callback.
1199 */
1200static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1201 uint64_t src_offset,
1202 uint64_t dst_offset,
1203 uint32_t byte_count,
1204 bool_Bool tmz)
1205{
1206 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) |
1207 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8);
1208 ib->ptr[ib->length_dw++] = byte_count;
1209 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1210 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset)((u32)(src_offset));
1211 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset)((u32)(((src_offset) >> 16) >> 16));
1212 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset));
1213 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16));
1214}
1215
1216/**
1217 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1218 *
1219 * @ring: amdgpu_ring structure holding ring information
1220 * @src_data: value to write to buffer
1221 * @dst_offset: dst GPU address
1222 * @byte_count: number of bytes to xfer
1223 *
1224 * Fill GPU buffers using the DMA engine (VI).
1225 */
1226static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1227 uint32_t src_data,
1228 uint64_t dst_offset,
1229 uint32_t byte_count)
1230{
1231 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)(((11) & 0x000000FF) << 0);
1232 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset));
1233 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16));
1234 ib->ptr[ib->length_dw++] = src_data;
1235 ib->ptr[ib->length_dw++] = byte_count;
1236}
1237
1238static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1239 .copy_max_bytes = 0x1fffff,
1240 .copy_num_dw = 7,
1241 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1242
1243 .fill_max_bytes = 0x1fffff,
1244 .fill_num_dw = 7,
1245 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1246};
1247
1248static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1249{
1250 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1251 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1252}
1253
1254static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1255 .copy_pte_num_dw = 7,
1256 .copy_pte = sdma_v2_4_vm_copy_pte,
1257
1258 .write_pte = sdma_v2_4_vm_write_pte,
1259 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1260};
1261
1262static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1263{
1264 unsigned i;
1265
1266 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1267 for (i = 0; i < adev->sdma.num_instances; i++) {
1268 adev->vm_manager.vm_pte_scheds[i] =
1269 &adev->sdma.instance[i].ring.sched;
1270 }
1271 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1272}
1273
1274const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1275{
1276 .type = AMD_IP_BLOCK_TYPE_SDMA,
1277 .major = 2,
1278 .minor = 4,
1279 .rev = 0,
1280 .funcs = &sdma_v2_4_ip_funcs,
1281};