Bug Summary

File:dev/sdmmc/sdhc.c
Warning:line 832, column 9
Although the value stored to 'state' is used in the enclosing expression, the value is never actually read from 'state'

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name sdhc.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/sdmmc/sdhc.c
1/* $OpenBSD: sdhc.c,v 1.71 2021/09/11 22:42:12 mglocker Exp $ */
2
3/*
4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/*
20 * SD Host Controller driver based on the SD Host Controller Standard
21 * Simplified Specification Version 1.00 (www.sdcard.org).
22 */
23
24#include <sys/param.h>
25#include <sys/device.h>
26#include <sys/kernel.h>
27#include <sys/malloc.h>
28#include <sys/proc.h>
29#include <sys/systm.h>
30#include <sys/time.h>
31
32#include <dev/sdmmc/sdhcreg.h>
33#include <dev/sdmmc/sdhcvar.h>
34#include <dev/sdmmc/sdmmcchip.h>
35#include <dev/sdmmc/sdmmcreg.h>
36#include <dev/sdmmc/sdmmcvar.h>
37#include <dev/sdmmc/sdmmc_ioreg.h>
38
39/* Timeouts in seconds */
40#define SDHC_COMMAND_TIMEOUT1 1
41#define SDHC_BUFFER_TIMEOUT1 1
42#define SDHC_TRANSFER_TIMEOUT1 1
43#define SDHC_DMA_TIMEOUT3 3
44
45struct sdhc_host {
46 struct sdhc_softc *sc; /* host controller device */
47 struct device *sdmmc; /* generic SD/MMC device */
48 bus_space_tag_t iot; /* host register set tag */
49 bus_space_handle_t ioh; /* host register set handle */
50 u_int16_t version; /* specification version */
51 u_int clkbase; /* base clock frequency in KHz */
52 int maxblklen; /* maximum block length */
53 int flags; /* flags for this host */
54 u_int32_t ocr; /* OCR value from capabilities */
55 u_int8_t regs[14]; /* host controller state */
56 u_int16_t intr_status; /* soft interrupt status */
57 u_int16_t intr_error_status; /* soft error status */
58
59 bus_dmamap_t adma_map;
60 bus_dma_segment_t adma_segs[1];
61 caddr_t adma2;
62
63 uint16_t block_size;
64 uint16_t block_count;
65 uint16_t transfer_mode;
66};
67
68/* flag values */
69#define SHF_USE_DMA0x0001 0x0001
70#define SHF_USE_DMA640x0002 0x0002
71#define SHF_USE_32BIT_ACCESS0x0004 0x0004
72
73#define HREAD1(hp, reg)(sdhc_read_1((hp), (reg))) \
74 (sdhc_read_1((hp), (reg)))
75#define HREAD2(hp, reg)(sdhc_read_2((hp), (reg))) \
76 (sdhc_read_2((hp), (reg)))
77#define HREAD4(hp, reg)((((hp)->iot)->read_4(((hp)->ioh), ((reg))))) \
78 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))(((hp)->iot)->read_4(((hp)->ioh), ((reg)))))
79#define HWRITE1(hp, reg, val)sdhc_write_1((hp), (reg), (val)) \
80 sdhc_write_1((hp), (reg), (val))
81#define HWRITE2(hp, reg, val)sdhc_write_2((hp), (reg), (val)) \
82 sdhc_write_2((hp), (reg), (val))
83#define HWRITE4(hp, reg, val)(((hp)->iot)->write_4(((hp)->ioh), ((reg)), ((val)))
) \
84 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))(((hp)->iot)->write_4(((hp)->ioh), ((reg)), ((val)))
)
85#define HCLR1(hp, reg, bits)sdhc_write_1(((hp)), ((reg)), ((sdhc_read_1(((hp)), ((reg))))
& ~(bits))) \
86 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))sdhc_write_1(((hp)), ((reg)), ((sdhc_read_1(((hp)), ((reg))))
& ~(bits)))
87#define HCLR2(hp, reg, bits)sdhc_write_2(((hp)), ((reg)), ((sdhc_read_2(((hp)), ((reg))))
& ~(bits))) \
88 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))sdhc_write_2(((hp)), ((reg)), ((sdhc_read_2(((hp)), ((reg))))
& ~(bits)))
89#define HSET1(hp, reg, bits)sdhc_write_1(((hp)), ((reg)), ((sdhc_read_1(((hp)), ((reg))))
| (bits))) \
90 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))sdhc_write_1(((hp)), ((reg)), ((sdhc_read_1(((hp)), ((reg))))
| (bits)))
91#define HSET2(hp, reg, bits)sdhc_write_2(((hp)), ((reg)), ((sdhc_read_2(((hp)), ((reg))))
| (bits))) \
92 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))sdhc_write_2(((hp)), ((reg)), ((sdhc_read_2(((hp)), ((reg))))
| (bits)))
93
94int sdhc_host_reset(sdmmc_chipset_handle_t);
95u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t);
96int sdhc_host_maxblklen(sdmmc_chipset_handle_t);
97int sdhc_card_detect(sdmmc_chipset_handle_t);
98int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t);
99int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int);
100int sdhc_bus_width(sdmmc_chipset_handle_t, int);
101void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int);
102void sdhc_card_intr_ack(sdmmc_chipset_handle_t);
103int sdhc_signal_voltage(sdmmc_chipset_handle_t, int);
104void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *);
105int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *);
106int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t);
107int sdhc_soft_reset(struct sdhc_host *, int);
108int sdhc_wait_intr_cold(struct sdhc_host *, int, int);
109int sdhc_wait_intr(struct sdhc_host *, int, int);
110void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *);
111void sdhc_read_data(struct sdhc_host *, u_char *, int);
112void sdhc_write_data(struct sdhc_host *, u_char *, int);
113int sdhc_hibernate_init(sdmmc_chipset_handle_t, void *);
114
115#ifdef SDHC_DEBUG
116int sdhcdebug = 0;
117#define DPRINTF(n,s)do {} while(0) do { if ((n) <= sdhcdebug) printf s; } while (0)
118void sdhc_dump_regs(struct sdhc_host *);
119#else
120#define DPRINTF(n,s)do {} while(0) do {} while(0)
121#endif
122
123struct sdmmc_chip_functions sdhc_functions = {
124 .host_reset = sdhc_host_reset,
125 .host_ocr = sdhc_host_ocr,
126 .host_maxblklen = sdhc_host_maxblklen,
127 .card_detect = sdhc_card_detect,
128 .bus_power = sdhc_bus_power,
129 .bus_clock = sdhc_bus_clock,
130 .bus_width = sdhc_bus_width,
131 .exec_command = sdhc_exec_command,
132 .card_intr_mask = sdhc_card_intr_mask,
133 .card_intr_ack = sdhc_card_intr_ack,
134 .signal_voltage = sdhc_signal_voltage,
135 .hibernate_init = sdhc_hibernate_init,
136};
137
138struct cfdriver sdhc_cd = {
139 NULL((void *)0), "sdhc", DV_DULL
140};
141
142/*
143 * Some controllers live on a bus that only allows 32-bit
144 * transactions. In that case we use a RMW cycle for 8-bit and 16-bit
145 * register writes. However that doesn't work for the Transfer Mode
146 * register as this register lives in the same 32-bit word as the
147 * Command register and writing the Command register triggers SD
148 * command generation. We avoid this issue by using a shadow variable
149 * for the Transfer Mode register that we write out when we write the
150 * Command register.
151 *
152 * The Arasan controller controller integrated on the Broadcom SoCs
153 * used in the Raspberry Pi has an interesting bug where writing the
154 * same 32-bit register twice doesn't work. This means that we lose
155 * writes to the Block Sine and/or Block Count register. We work
156 * around that issue by using shadow variables as well.
157 */
158
159uint8_t
160sdhc_read_1(struct sdhc_host *hp, bus_size_t offset)
161{
162 uint32_t reg;
163
164 if (hp->flags & SHF_USE_32BIT_ACCESS0x0004) {
165 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3)((hp->iot)->read_4((hp->ioh), (offset & ~3)));
166 return (reg >> ((offset & 3) * 8)) & 0xff;
167 }
168
169 return bus_space_read_1(hp->iot, hp->ioh, offset)((hp->iot)->read_1((hp->ioh), (offset)));
170}
171
172uint16_t
173sdhc_read_2(struct sdhc_host *hp, bus_size_t offset)
174{
175 uint32_t reg;
176
177 if (hp->flags & SHF_USE_32BIT_ACCESS0x0004) {
178 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2)((hp->iot)->read_4((hp->ioh), (offset & ~2)));
179 return (reg >> ((offset & 2) * 8)) & 0xffff;
180 }
181
182 return bus_space_read_2(hp->iot, hp->ioh, offset)((hp->iot)->read_2((hp->ioh), (offset)));
183}
184
185void
186sdhc_write_1(struct sdhc_host *hp, bus_size_t offset, uint8_t value)
187{
188 uint32_t reg;
189
190 if (hp->flags & SHF_USE_32BIT_ACCESS0x0004) {
191 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3)((hp->iot)->read_4((hp->ioh), (offset & ~3)));
192 reg &= ~(0xff << ((offset & 3) * 8));
193 reg |= (value << ((offset & 3) * 8));
194 bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg)((hp->iot)->write_4((hp->ioh), (offset & ~3), (reg
)));
195 return;
196 }
197
198 bus_space_write_1(hp->iot, hp->ioh, offset, value)((hp->iot)->write_1((hp->ioh), (offset), (value)));
199}
200
201void
202sdhc_write_2(struct sdhc_host *hp, bus_size_t offset, uint16_t value)
203{
204 uint32_t reg;
205
206 if (hp->flags & SHF_USE_32BIT_ACCESS0x0004) {
207 switch (offset) {
208 case SDHC_BLOCK_SIZE0x04:
209 hp->block_size = value;
210 return;
211 case SDHC_BLOCK_COUNT0x06:
212 hp->block_count = value;
213 return;
214 case SDHC_TRANSFER_MODE0x0c:
215 hp->transfer_mode = value;
216 return;
217 case SDHC_COMMAND0x0e:
218 bus_space_write_4(hp->iot, hp->ioh, SDHC_BLOCK_SIZE,((hp->iot)->write_4((hp->ioh), (0x04), ((hp->block_count
<< 16) | hp->block_size)))
219 (hp->block_count << 16) | hp->block_size)((hp->iot)->write_4((hp->ioh), (0x04), ((hp->block_count
<< 16) | hp->block_size)));
220 bus_space_write_4(hp->iot, hp->ioh, SDHC_TRANSFER_MODE,((hp->iot)->write_4((hp->ioh), (0x0c), ((value <<
16) | hp->transfer_mode)))
221 (value << 16) | hp->transfer_mode)((hp->iot)->write_4((hp->ioh), (0x0c), ((value <<
16) | hp->transfer_mode)));
222 return;
223 }
224
225 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2)((hp->iot)->read_4((hp->ioh), (offset & ~2)));
226 reg &= ~(0xffff << ((offset & 2) * 8));
227 reg |= (value << ((offset & 2) * 8));
228 bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg)((hp->iot)->write_4((hp->ioh), (offset & ~2), (reg
)));
229 return;
230 }
231
232 bus_space_write_2(hp->iot, hp->ioh, offset, value)((hp->iot)->write_2((hp->ioh), (offset), (value)));
233}
234
235/*
236 * Called by attachment driver. For each SD card slot there is one SD
237 * host controller standard register set. (1.3)
238 */
239int
240sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
241 bus_space_handle_t ioh, bus_size_t iosize, int usedma, u_int32_t caps)
242{
243 struct sdmmcbus_attach_args saa;
244 struct sdhc_host *hp;
245 int error = 1;
246 int max_clock;
247
248 /* Allocate one more host structure. */
249 sc->sc_nhosts++;
250 hp = malloc(sizeof(*hp), M_DEVBUF2, M_WAITOK0x0001 | M_ZERO0x0008);
251 sc->sc_host[sc->sc_nhosts - 1] = hp;
252
253 if (ISSET(sc->sc_flags, SDHC_F_32BIT_ACCESS)((sc->sc_flags) & ((1 << 3))))
254 SET(hp->flags, SHF_USE_32BIT_ACCESS)((hp->flags) |= (0x0004));
255
256 /* Fill in the new host structure. */
257 hp->sc = sc;
258 hp->iot = iot;
259 hp->ioh = ioh;
260
261 /* Store specification version. */
262 hp->version = HREAD2(hp, SDHC_HOST_CTL_VERSION)(sdhc_read_2((hp), (0xfe)));
263
264 /*
265 * Reset the host controller and enable interrupts.
266 */
267 (void)sdhc_host_reset(hp);
268
269 /* Determine host capabilities. */
270 if (caps == 0)
271 caps = HREAD4(hp, SDHC_CAPABILITIES)((((hp)->iot)->read_4(((hp)->ioh), ((0x40)))));
272
273 /* Use DMA if the host system and the controller support it. */
274 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)((caps) & ((1<<19)))) {
275 SET(hp->flags, SHF_USE_DMA)((hp->flags) |= (0x0001));
276 if (ISSET(caps, SDHC_64BIT_DMA_SUPP)((caps) & ((1<<28))))
277 SET(hp->flags, SHF_USE_DMA64)((hp->flags) |= (0x0002));
278 }
279
280 /*
281 * Determine the base clock frequency. (2.2.24)
282 */
283 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
284 /* SDHC 3.0 supports 10-255 MHz. */
285 max_clock = 255000;
286 if (SDHC_BASE_FREQ_KHZ_V3(caps)((((caps) >> 8) & 0xff) * 1000) != 0)
287 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps)((((caps) >> 8) & 0xff) * 1000);
288 } else {
289 /* SDHC 1.0/2.0 supports only 10-63 MHz. */
290 max_clock = 63000;
291 if (SDHC_BASE_FREQ_KHZ(caps)((((caps) >> 8) & 0x3f) * 1000) != 0)
292 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps)((((caps) >> 8) & 0x3f) * 1000);
293 }
294 if (hp->clkbase == 0) {
295 /* Make sure we can clock down to 400 kHz. */
296 max_clock = 400 * SDHC_SDCLK_DIV_MAX_V32046;
297 hp->clkbase = sc->sc_clkbase;
298 }
299 if (hp->clkbase == 0) {
300 /* The attachment driver must tell us. */
301 printf("%s: base clock frequency unknown\n",
302 sc->sc_dev.dv_xname);
303 goto err;
304 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) {
305 printf("%s: base clock frequency out of range: %u MHz\n",
306 sc->sc_dev.dv_xname, hp->clkbase / 1000);
307 goto err;
308 }
309
310 printf("%s: SDHC %d.0, %d MHz base clock\n", DEVNAME(sc)((sc)->sc_dev.dv_xname),
311 SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) + 1, hp->clkbase / 1000);
312
313 /*
314 * XXX Set the data timeout counter value according to
315 * capabilities. (2.2.15)
316 */
317
318 /*
319 * Determine SD bus voltage levels supported by the controller.
320 */
321 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)((caps) & ((1<<26))))
322 SET(hp->ocr, MMC_OCR_1_65V_1_95V)((hp->ocr) |= ((1<<7)));
323 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)((caps) & ((1<<25))))
324 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V)((hp->ocr) |= ((1<<17) | (1<<18)));
325 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)((caps) & ((1<<24))))
326 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V)((hp->ocr) |= ((1<<20) | (1<<21)));
327
328 /*
329 * Determine the maximum block length supported by the host
330 * controller. (2.2.24)
331 */
332 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT16) & SDHC_MAX_BLK_LEN_MASK0x3) {
333 case SDHC_MAX_BLK_LEN_5120:
334 hp->maxblklen = 512;
335 break;
336 case SDHC_MAX_BLK_LEN_10241:
337 hp->maxblklen = 1024;
338 break;
339 case SDHC_MAX_BLK_LEN_20482:
340 hp->maxblklen = 2048;
341 break;
342 default:
343 hp->maxblklen = 1;
344 break;
345 }
346
347 if (ISSET(hp->flags, SHF_USE_DMA)((hp->flags) & (0x0001))) {
348 int rseg;
349
350 /* Allocate ADMA2 descriptor memory */
351 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((1 <<
12)), ((1 << 12)), ((1 << 12)), (hp->adma_segs
), (1), (&rseg), (0x0000 | 0x1000))
352 PAGE_SIZE, hp->adma_segs, 1, &rseg,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((1 <<
12)), ((1 << 12)), ((1 << 12)), (hp->adma_segs
), (1), (&rseg), (0x0000 | 0x1000))
353 BUS_DMA_WAITOK | BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((1 <<
12)), ((1 << 12)), ((1 << 12)), (hp->adma_segs
), (1), (&rseg), (0x0000 | 0x1000));
354 if (error)
355 goto adma_done;
356 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (hp->
adma_segs), (rseg), ((1 << 12)), (&hp->adma2), (
0x0000 | 0x0004))
357 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (hp->
adma_segs), (rseg), ((1 << 12)), (&hp->adma2), (
0x0000 | 0x0004));
358 if (error) {
359 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (hp->
adma_segs), (rseg));
360 goto adma_done;
361 }
362 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
12)), (1), ((1 << 12)), (0), (0x0000), (&hp->adma_map
))
363 0, BUS_DMA_WAITOK, &hp->adma_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
12)), (1), ((1 << 12)), (0), (0x0000), (&hp->adma_map
));
364 if (error) {
365 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (hp->
adma2), ((1 << 12)));
366 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (hp->
adma_segs), (rseg));
367 goto adma_done;
368 }
369 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (hp->
adma_map), (hp->adma2), ((1 << 12)), (((void *)0)), (
0x0000 | 0x0400))
370 hp->adma2, PAGE_SIZE, NULL,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (hp->
adma_map), (hp->adma2), ((1 << 12)), (((void *)0)), (
0x0000 | 0x0400))
371 BUS_DMA_WAITOK | BUS_DMA_WRITE)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (hp->
adma_map), (hp->adma2), ((1 << 12)), (((void *)0)), (
0x0000 | 0x0400));
372 if (error) {
373 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (hp
->adma_map));
374 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (hp->
adma2), ((1 << 12)));
375 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (hp->
adma_segs), (rseg));
376 goto adma_done;
377 }
378
379 adma_done:
380 if (error) {
381 printf("%s: can't allocate DMA descriptor table\n",
382 DEVNAME(hp->sc)((hp->sc)->sc_dev.dv_xname));
383 CLR(hp->flags, SHF_USE_DMA)((hp->flags) &= ~(0x0001));
384 }
385 }
386
387 /*
388 * Attach the generic SD/MMC bus driver. (The bus driver must
389 * not invoke any chipset functions before it is attached.)
390 */
391 bzero(&saa, sizeof(saa))__builtin_bzero((&saa), (sizeof(saa)));
392 saa.saa_busname = "sdmmc";
393 saa.sct = &sdhc_functions;
394 saa.sch = hp;
395 saa.caps = SMC_CAPS_4BIT_MODE0x0002;
396 saa.dmat = sc->sc_dmat;
397 if (ISSET(hp->flags, SHF_USE_DMA)((hp->flags) & (0x0001)))
398 saa.caps |= SMC_CAPS_DMA0x0004;
399
400 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)((caps) & ((1<<21))))
401 saa.caps |= SMC_CAPS_SD_HIGHSPEED0x0100;
402 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)((caps) & ((1<<21))))
403 saa.caps |= SMC_CAPS_MMC_HIGHSPEED0x0200;
404
405 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
406 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2)((((hp)->iot)->read_4(((hp)->ioh), ((0x44)))));
407
408 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)((caps) & ((1<<18))))
409 saa.caps |= SMC_CAPS_8BIT_MODE0x0040;
410
411 if (ISSET(caps2, SDHC_DDR50_SUPP)((caps2) & ((1<<2))))
412 saa.caps |= SMC_CAPS_MMC_DDR520x2000;
413 }
414
415 if (ISSET(sc->sc_flags, SDHC_F_NODDR50)((sc->sc_flags) & ((1 << 1))))
416 saa.caps &= ~SMC_CAPS_MMC_DDR520x2000;
417
418 if (ISSET(sc->sc_flags, SDHC_F_NONREMOVABLE)((sc->sc_flags) & ((1 << 2))))
419 saa.caps |= SMC_CAPS_NONREMOVABLE0x10000;
420
421 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL)config_found_sm((&sc->sc_dev), (&saa), (((void *)0
)), ((void *)0));
422 if (hp->sdmmc == NULL((void *)0)) {
423 error = 0;
424 goto err;
425 }
426
427 return 0;
428
429err:
430 free(hp, M_DEVBUF2, sizeof *hp);
431 sc->sc_host[sc->sc_nhosts - 1] = NULL((void *)0);
432 sc->sc_nhosts--;
433 return (error);
434}
435
436int
437sdhc_activate(struct device *self, int act)
438{
439 struct sdhc_softc *sc = (struct sdhc_softc *)self;
440 struct sdhc_host *hp;
441 int n, i, rv = 0;
442
443 switch (act) {
444 case DVACT_SUSPEND3:
445 rv = config_activate_children(self, act);
446
447 /* Save the host controller state. */
448 for (n = 0; n < sc->sc_nhosts; n++) {
449 hp = sc->sc_host[n];
450 for (i = 0; i < sizeof hp->regs; i++)
451 hp->regs[i] = HREAD1(hp, i)(sdhc_read_1((hp), (i)));
452 }
453 break;
454 case DVACT_RESUME4:
455 /* Restore the host controller state. */
456 for (n = 0; n < sc->sc_nhosts; n++) {
457 hp = sc->sc_host[n];
458 (void)sdhc_host_reset(hp);
459 for (i = 0; i < sizeof hp->regs; i++)
460 HWRITE1(hp, i, hp->regs[i])sdhc_write_1((hp), (i), (hp->regs[i]));
461 }
462 rv = config_activate_children(self, act);
463 break;
464 case DVACT_POWERDOWN6:
465 rv = config_activate_children(self, act);
466 sdhc_shutdown(self);
467 break;
468 default:
469 rv = config_activate_children(self, act);
470 break;
471 }
472 return (rv);
473}
474
475/*
476 * Shutdown hook established by or called from attachment driver.
477 */
478void
479sdhc_shutdown(void *arg)
480{
481 struct sdhc_softc *sc = arg;
482 struct sdhc_host *hp;
483 int i;
484
485 /* XXX chip locks up if we don't disable it before reboot. */
486 for (i = 0; i < sc->sc_nhosts; i++) {
487 hp = sc->sc_host[i];
488 (void)sdhc_host_reset(hp);
489 }
490}
491
492/*
493 * Reset the host controller. Called during initialization, when
494 * cards are removed, upon resume, and during error recovery.
495 */
496int
497sdhc_host_reset(sdmmc_chipset_handle_t sch)
498{
499 struct sdhc_host *hp = sch;
500 u_int16_t imask;
501 int error;
502 int s;
503
504 s = splsdmmc()splraise(0x6);
505
506 /* Disable all interrupts. */
507 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0)sdhc_write_2((hp), (0x38), (0));
508
509 /*
510 * Reset the entire host controller and wait up to 100ms for
511 * the controller to clear the reset bit.
512 */
513 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL(1<<0))) != 0) {
514 splx(s)spllower(s);
515 return (error);
516 }
517
518 /* Set data timeout counter value to max for now. */
519 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX)sdhc_write_1((hp), (0x2e), (0x0e));
520
521 /* Enable interrupts. */
522 imask = SDHC_CARD_REMOVAL(1<<7) | SDHC_CARD_INSERTION(1<<6) |
523 SDHC_BUFFER_READ_READY(1<<5) | SDHC_BUFFER_WRITE_READY(1<<4) |
524 SDHC_DMA_INTERRUPT(1<<3) | SDHC_BLOCK_GAP_EVENT(1<<2) |
525 SDHC_TRANSFER_COMPLETE(1<<1) | SDHC_COMMAND_COMPLETE(1<<0);
526
527 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask)sdhc_write_2((hp), (0x34), (imask));
528 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK)sdhc_write_2((hp), (0x36), (0x03ff));
529 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask)sdhc_write_2((hp), (0x38), (imask));
530 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK)sdhc_write_2((hp), (0x3a), (0x03ff));
531
532 splx(s)spllower(s);
533 return 0;
534}
535
536u_int32_t
537sdhc_host_ocr(sdmmc_chipset_handle_t sch)
538{
539 struct sdhc_host *hp = sch;
540 return hp->ocr;
541}
542
543int
544sdhc_host_maxblklen(sdmmc_chipset_handle_t sch)
545{
546 struct sdhc_host *hp = sch;
547 return hp->maxblklen;
548}
549
550/*
551 * Return non-zero if the card is currently inserted.
552 */
553int
554sdhc_card_detect(sdmmc_chipset_handle_t sch)
555{
556 struct sdhc_host *hp = sch;
557
558 if (hp->sc->sc_card_detect)
559 return hp->sc->sc_card_detect(hp->sc);
560
561 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED)((((((hp)->iot)->read_4(((hp)->ioh), ((0x24)))))) &
((1<<16))) ?
562 1 : 0;
563}
564
565/*
566 * Set or change SD bus voltage and enable or disable SD bus power.
567 * Return zero on success.
568 */
569int
570sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr)
571{
572 struct sdhc_host *hp = sch;
573 u_int8_t vdd;
574 int s;
575
576 s = splsdmmc()splraise(0x6);
577
578 /*
579 * Disable bus power before voltage change.
580 */
581 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0(1 << 0)))
582 HWRITE1(hp, SDHC_POWER_CTL, 0)sdhc_write_1((hp), (0x29), (0));
583
584 /* If power is disabled, reset the host and return now. */
585 if (ocr == 0) {
586 splx(s)spllower(s);
587 (void)sdhc_host_reset(hp);
588 return 0;
589 }
590
591 /*
592 * Select the maximum voltage according to capabilities.
593 */
594 ocr &= hp->ocr;
595 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)((ocr) & ((1<<20)|(1<<21))))
596 vdd = SDHC_VOLTAGE_3_3V0x07;
597 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)((ocr) & ((1<<17)|(1<<18))))
598 vdd = SDHC_VOLTAGE_3_0V0x06;
599 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)((ocr) & ((1<<7))))
600 vdd = SDHC_VOLTAGE_1_8V0x05;
601 else {
602 /* Unsupported voltage level requested. */
603 splx(s)spllower(s);
604 return EINVAL22;
605 }
606
607 /*
608 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus
609 * voltage ramp until power rises.
610 */
611 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) |sdhc_write_1((hp), (0x29), ((vdd << 1) | (1<<0)))
612 SDHC_BUS_POWER)sdhc_write_1((hp), (0x29), ((vdd << 1) | (1<<0)));
613 sdmmc_delay(10000);
614
615 /*
616 * The host system may not power the bus due to battery low,
617 * etc. In that case, the host controller should clear the
618 * bus power bit.
619 */
620 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)(((sdhc_read_1((hp), (0x29)))) & ((1<<0)))) {
621 splx(s)spllower(s);
622 return ENXIO6;
623 }
624
625 splx(s)spllower(s);
626 return 0;
627}
628
629/*
630 * Return the smallest possible base clock frequency divisor value
631 * for the CLOCK_CTL register to produce `freq' (KHz).
632 */
633static int
634sdhc_clock_divisor(struct sdhc_host *hp, u_int freq)
635{
636 int max_div = SDHC_SDCLK_DIV_MAX256;
637 int div;
638
639 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32)
640 max_div = SDHC_SDCLK_DIV_MAX_V32046;
641
642 for (div = 1; div <= max_div; div *= 2)
643 if ((hp->clkbase / div) <= freq)
644 return (div / 2);
645 /* No divisor found. */
646 return -1;
647}
648
649/*
650 * Set or change SDCLK frequency or disable the SD clock.
651 * Return zero on success.
652 */
653int
654sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)
655{
656 struct sdhc_host *hp = sch;
657 struct sdhc_softc *sc = hp->sc;
658 int s;
659 int div;
660 int sdclk;
661 int timo;
662 int error = 0;
663
664 s = splsdmmc()splraise(0x6);
665
666 if (hp->sc->sc_bus_clock_pre)
667 hp->sc->sc_bus_clock_pre(hp->sc, freq, timing);
668
669#ifdef DIAGNOSTIC1
670 /* Must not stop the clock if commands are in progress. */
671 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK)((((((hp)->iot)->read_4(((hp)->ioh), ((0x24)))))) &
(0x0003)) &&
672 sdhc_card_detect(hp))
673 printf("sdhc_sdclk_frequency_select: command in progress\n");
674#endif
675
676 /*
677 * Stop SD clock before changing the frequency.
678 */
679 HWRITE2(hp, SDHC_CLOCK_CTL, 0)sdhc_write_2((hp), (0x2c), (0));
680 if (freq == SDMMC_SDCLK_OFF0)
681 goto ret;
682
683 if (!ISSET(sc->sc_flags, SDHC_F_NO_HS_BIT)((sc->sc_flags) & ((1 << 4)))) {
684 if (timing == SDMMC_TIMING_LEGACY0)
685 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) & ~((1<<2))));
686 else
687 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) | ((1<<2))));
688 }
689
690 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
691 switch (timing) {
692 case SDMMC_TIMING_MMC_DDR524:
693 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK)sdhc_write_2(((hp)), ((0x3e)), ((sdhc_read_2(((hp)), ((0x3e))
)) & ~(0x7)));
694 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50)sdhc_write_2(((hp)), ((0x3e)), ((sdhc_read_2(((hp)), ((0x3e))
)) | (4)));
695 break;
696 }
697 }
698
699 /*
700 * Set the minimum base clock frequency divisor.
701 */
702 if ((div = sdhc_clock_divisor(hp, freq)) < 0) {
703 /* Invalid base clock frequency or `freq' value. */
704 error = EINVAL22;
705 goto ret;
706 }
707 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32)
708 sdclk = SDHC_SDCLK_DIV_V3(div)((((div) & 0xff) << 8) | (((div) & 0x300) >>
2));
709 else
710 sdclk = SDHC_SDCLK_DIV(div)(((div) & 0xff) << 8);
711 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk)sdhc_write_2((hp), (0x2c), (sdclk));
712
713 /*
714 * Start internal clock. Wait 10ms for stabilization.
715 */
716 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE)sdhc_write_2(((hp)), ((0x2c)), ((sdhc_read_2(((hp)), ((0x2c))
)) | ((1<<0))));
717 for (timo = 1000; timo > 0; timo--) {
718 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)(((sdhc_read_2((hp), (0x2c)))) & ((1<<1))))
719 break;
720 sdmmc_delay(10);
721 }
722 if (timo == 0) {
723 error = ETIMEDOUT60;
724 goto ret;
725 }
726
727 /*
728 * Enable SD clock.
729 */
730 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE)sdhc_write_2(((hp)), ((0x2c)), ((sdhc_read_2(((hp)), ((0x2c))
)) | ((1<<2))));
731
732 if (hp->sc->sc_bus_clock_post)
733 hp->sc->sc_bus_clock_post(hp->sc, freq, timing);
734
735ret:
736 splx(s)spllower(s);
737 return error;
738}
739
740int
741sdhc_bus_width(sdmmc_chipset_handle_t sch, int width)
742{
743 struct sdhc_host *hp = (struct sdhc_host *)sch;
744 int reg;
745 int s;
746
747 if (width != 1 && width != 4 && width != 8)
748 return EINVAL22;
749
750 s = splsdmmc()splraise(0x6);
751
752 reg = HREAD1(hp, SDHC_HOST_CTL)(sdhc_read_1((hp), (0x28)));
753 reg &= ~SDHC_4BIT_MODE(1<<1);
754 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
755 reg &= ~SDHC_8BIT_MODE(1<<5);
756 }
757 if (width == 4) {
758 reg |= SDHC_4BIT_MODE(1<<1);
759 } else if (width == 8) {
760 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3)(((((hp->version) >> 0) & 0xff) >= 2) ? (void
)0 : __assert("diagnostic ", "/usr/src/sys/dev/sdmmc/sdhc.c",
760, "SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3")
);
761 reg |= SDHC_8BIT_MODE(1<<5);
762 }
763 HWRITE1(hp, SDHC_HOST_CTL, reg)sdhc_write_1((hp), (0x28), (reg));
764
765 splx(s)spllower(s);
766
767 return 0;
768}
769
770void
771sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)
772{
773 struct sdhc_host *hp = sch;
774
775 if (enable) {
776 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) | ((1<<8))));
777 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x38)), ((sdhc_read_2(((hp)), ((0x38))
)) | ((1<<8))));
778 } else {
779 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x38)), ((sdhc_read_2(((hp)), ((0x38))
)) & ~((1<<8))));
780 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) & ~((1<<8))));
781 }
782}
783
784void
785sdhc_card_intr_ack(sdmmc_chipset_handle_t sch)
786{
787 struct sdhc_host *hp = sch;
788
789 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) | ((1<<8))));
790}
791
792int
793sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage)
794{
795 struct sdhc_host *hp = sch;
796
797 if (hp->sc->sc_signal_voltage)
798 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage);
799
800 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) < SDHC_SPEC_V32)
801 return EINVAL22;
802
803 switch (signal_voltage) {
804 case SDMMC_SIGNAL_VOLTAGE_1801:
805 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN)sdhc_write_2(((hp)), ((0x3e)), ((sdhc_read_2(((hp)), ((0x3e))
)) | ((1<<3))));
806 break;
807 case SDMMC_SIGNAL_VOLTAGE_3300:
808 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN)sdhc_write_2(((hp)), ((0x3e)), ((sdhc_read_2(((hp)), ((0x3e))
)) & ~((1<<3))));
809 break;
810 default:
811 return EINVAL22;
812 }
813
814 /* Regulator output shall be stable within 5 ms. */
815 sdmmc_delay(5000);
816
817 /* Host controller clears this bit if 1.8V signalling fails. */
818 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_1801 &&
819 !ISSET(HREAD2(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)(((sdhc_read_2((hp), (0x3e)))) & ((1<<3))))
820 return EIO5;
821
822 return 0;
823}
824
825int
826sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value)
827{
828 u_int32_t state;
829 int timeout;
830
831 for (timeout = 10; timeout > 0; timeout--) {
832 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)((((hp)->iot)->read_4(((hp)->ioh), ((0x24)))))) & mask)
Although the value stored to 'state' is used in the enclosing expression, the value is never actually read from 'state'
833 == value)
834 return 0;
835 sdmmc_delay(10000);
836 }
837 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc),do {} while(0)
838 value, state, SDHC_PRESENT_STATE_BITS))do {} while(0);
839 return ETIMEDOUT60;
840}
841
842void
843sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
844{
845 struct sdhc_host *hp = sch;
846 int error;
847
848 /*
849 * Start the MMC command, or mark `cmd' as failed and return.
850 */
851 error = sdhc_start_command(hp, cmd);
852 if (error != 0) {
853 cmd->c_error = error;
854 SET(cmd->c_flags, SCF_ITSDONE)((cmd->c_flags) |= (0x0001));
855 return;
856 }
857
858 /*
859 * Wait until the command phase is done, or until the command
860 * is marked done for any other reason.
861 */
862 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE(1<<0),
863 SDHC_COMMAND_TIMEOUT1)) {
864 cmd->c_error = ETIMEDOUT60;
865 SET(cmd->c_flags, SCF_ITSDONE)((cmd->c_flags) |= (0x0001));
866 return;
867 }
868
869 /*
870 * The host controller removes bits [0:7] from the response
871 * data (CRC) and we pass the data up unchanged to the bus
872 * driver (without padding).
873 */
874 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)((cmd->c_flags) & (0x1000))) {
875 if (ISSET(cmd->c_flags, SCF_RSP_136)((cmd->c_flags) & (0x0200))) {
876 u_char *p = (u_char *)cmd->c_resp;
877 int i;
878
879 for (i = 0; i < 15; i++)
880 *p++ = HREAD1(hp, SDHC_RESPONSE + i)(sdhc_read_1((hp), (0x10 + i)));
881 } else
882 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE)((((hp)->iot)->read_4(((hp)->ioh), ((0x10)))));
883 }
884
885 /*
886 * If the command has data to transfer in any direction,
887 * execute the transfer now.
888 */
889 if (cmd->c_error == 0 && cmd->c_data != NULL((void *)0))
890 sdhc_transfer_data(hp, cmd);
891
892 /* Turn off the LED. */
893 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) & ~((1<<0))));
894
895 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n",do {} while(0)
896 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error))do {} while(0);
897 SET(cmd->c_flags, SCF_ITSDONE)((cmd->c_flags) |= (0x0001));
898}
899
900int
901sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
902{
903 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2;
904 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2;
905 struct sdhc_softc *sc = hp->sc;
906 u_int16_t blksize = 0;
907 u_int16_t blkcount = 0;
908 u_int16_t mode;
909 u_int16_t command;
910 int error;
911 int seg;
912 int s;
913
914 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x\n",do {} while(0)
915 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data,do {} while(0)
916 cmd->c_datalen, cmd->c_flags))do {} while(0);
917
918 /*
919 * The maximum block length for commands should be the minimum
920 * of the host buffer size and the card buffer size. (1.7.2)
921 */
922
923 /* Fragment the data into proper blocks. */
924 if (cmd->c_datalen > 0) {
925 blksize = MIN(cmd->c_datalen, cmd->c_blklen)(((cmd->c_datalen)<(cmd->c_blklen))?(cmd->c_datalen
):(cmd->c_blklen));
926 blkcount = cmd->c_datalen / blksize;
927 if (cmd->c_datalen % blksize > 0) {
928 /* XXX: Split this command. (1.7.4) */
929 printf("%s: data not a multiple of %d bytes\n",
930 DEVNAME(hp->sc)((hp->sc)->sc_dev.dv_xname), blksize);
931 return EINVAL22;
932 }
933 }
934
935 /* Check limit imposed by 9-bit block count. (1.7.2) */
936 if (blkcount > SDHC_BLOCK_COUNT_MAX512) {
937 printf("%s: too much data\n", DEVNAME(hp->sc)((hp->sc)->sc_dev.dv_xname));
938 return EINVAL22;
939 }
940
941 /* Prepare transfer mode register value. (2.2.5) */
942 mode = 0;
943 if (ISSET(cmd->c_flags, SCF_CMD_READ)((cmd->c_flags) & (0x0040)))
944 mode |= SDHC_READ_MODE(1<<4);
945 if (blkcount > 0) {
946 mode |= SDHC_BLOCK_COUNT_ENABLE(1<<1);
947 if (blkcount > 1) {
948 mode |= SDHC_MULTI_BLOCK_MODE(1<<5);
949 if (cmd->c_opcode != SD_IO_RW_EXTENDED53)
950 mode |= SDHC_AUTO_CMD12_ENABLE(1<<2);
951 }
952 }
953 if (cmd->c_dmamap && cmd->c_datalen > 0 &&
954 ISSET(hp->flags, SHF_USE_DMA)((hp->flags) & (0x0001)))
955 mode |= SDHC_DMA_ENABLE(1<<0);
956
957 /*
958 * Prepare command register value. (2.2.6)
959 */
960 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK0x3f) <<
961 SDHC_COMMAND_INDEX_SHIFT8;
962
963 if (ISSET(cmd->c_flags, SCF_RSP_CRC)((cmd->c_flags) & (0x0400)))
964 command |= SDHC_CRC_CHECK_ENABLE(1<<3);
965 if (ISSET(cmd->c_flags, SCF_RSP_IDX)((cmd->c_flags) & (0x0800)))
966 command |= SDHC_INDEX_CHECK_ENABLE(1<<4);
967 if (cmd->c_data != NULL((void *)0))
968 command |= SDHC_DATA_PRESENT_SELECT(1<<5);
969
970 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)((cmd->c_flags) & (0x1000)))
971 command |= SDHC_NO_RESPONSE(0<<0);
972 else if (ISSET(cmd->c_flags, SCF_RSP_136)((cmd->c_flags) & (0x0200)))
973 command |= SDHC_RESP_LEN_136(1<<0);
974 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)((cmd->c_flags) & (0x0100)))
975 command |= SDHC_RESP_LEN_48_CHK_BUSY(3<<0);
976 else
977 command |= SDHC_RESP_LEN_48(2<<0);
978
979 /* Wait until command and data inhibit bits are clear. (1.5) */
980 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK0x0003, 0)) != 0)
981 return error;
982
983 s = splsdmmc()splraise(0x6);
984
985 /* Alert the user not to remove the card. */
986 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) | ((1<<0))));
987
988 /* Set DMA start address if SHF_USE_DMA is set. */
989 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)((hp->flags) & (0x0001))) {
990 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) {
991 bus_addr_t paddr =
992 cmd->c_dmamap->dm_segs[seg].ds_addr;
993 uint16_t len =
994 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ?
995 0 : cmd->c_dmamap->dm_segs[seg].ds_len;
996 uint16_t attr;
997
998 attr = SDHC_ADMA2_VALID(1<<0) | SDHC_ADMA2_ACT_TRANS(2<<4);
999 if (seg == cmd->c_dmamap->dm_nsegs - 1)
1000 attr |= SDHC_ADMA2_END(1<<1);
1001
1002 if (ISSET(hp->flags, SHF_USE_DMA64)((hp->flags) & (0x0002))) {
1003 desc64[seg].attribute = htole16(attr)((__uint16_t)(attr));
1004 desc64[seg].length = htole16(len)((__uint16_t)(len));
1005 desc64[seg].address_lo =
1006 htole32((uint64_t)paddr & 0xffffffff)((__uint32_t)((uint64_t)paddr & 0xffffffff));
1007 desc64[seg].address_hi =
1008 htole32((uint64_t)paddr >> 32)((__uint32_t)((uint64_t)paddr >> 32));
1009 } else {
1010 desc32[seg].attribute = htole16(attr)((__uint16_t)(attr));
1011 desc32[seg].length = htole16(len)((__uint16_t)(len));
1012 desc32[seg].address = htole32(paddr)((__uint32_t)(paddr));
1013 }
1014 }
1015
1016 if (ISSET(hp->flags, SHF_USE_DMA64)((hp->flags) & (0x0002)))
1017 desc64[cmd->c_dmamap->dm_nsegs].attribute = htole16(0)((__uint16_t)(0));
1018 else
1019 desc32[cmd->c_dmamap->dm_nsegs].attribute = htole16(0)((__uint16_t)(0));
1020
1021 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (hp->
adma_map), (0), ((1 << 12)), (0x04))
1022 BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (hp->
adma_map), (0), ((1 << 12)), (0x04));
1023
1024 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) & ~((3<<3))));
1025 if (ISSET(hp->flags, SHF_USE_DMA64)((hp->flags) & (0x0002)))
1026 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) | ((3<<3))));
1027 else
1028 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) | ((2<<3))));
1029
1030 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR,(((hp)->iot)->write_4(((hp)->ioh), ((0x58)), ((hp->
adma_map->dm_segs[0].ds_addr))))
1031 hp->adma_map->dm_segs[0].ds_addr)(((hp)->iot)->write_4(((hp)->ioh), ((0x58)), ((hp->
adma_map->dm_segs[0].ds_addr))));
1032 } else
1033 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) & ~((3<<3))));
1034
1035 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n",do {} while(0)
1036 DEVNAME(hp->sc), command, mode, blksize, blkcount))do {} while(0);
1037
1038 /*
1039 * Start a CPU data transfer. Writing to the high order byte
1040 * of the SDHC_COMMAND register triggers the SD command. (1.5)
1041 */
1042 HWRITE2(hp, SDHC_TRANSFER_MODE, mode)sdhc_write_2((hp), (0x0c), (mode));
1043 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize)sdhc_write_2((hp), (0x04), (blksize));
1044 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount)sdhc_write_2((hp), (0x06), (blkcount));
1045 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg)(((hp)->iot)->write_4(((hp)->ioh), ((0x08)), ((cmd->
c_arg))));
1046 HWRITE2(hp, SDHC_COMMAND, command)sdhc_write_2((hp), (0x0e), (command));
1047
1048 splx(s)spllower(s);
1049 return 0;
1050}
1051
1052void
1053sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
1054{
1055 struct sdhc_softc *sc = hp->sc;
1056 u_char *datap = cmd->c_data;
1057 int i, datalen;
1058 int mask;
1059 int error;
1060
1061 if (cmd->c_dmamap) {
1062 int status;
1063
1064 error = 0;
1065 for (;;) {
1066 status = sdhc_wait_intr(hp,
1067 SDHC_DMA_INTERRUPT(1<<3)|SDHC_TRANSFER_COMPLETE(1<<1),
1068 SDHC_DMA_TIMEOUT3);
1069 if (status & SDHC_TRANSFER_COMPLETE(1<<1))
1070 break;
1071 if (!status) {
1072 error = ETIMEDOUT60;
1073 break;
1074 }
1075 }
1076
1077 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (hp->
adma_map), (0), ((1 << 12)), (0x08))
1078 BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (hp->
adma_map), (0), ((1 << 12)), (0x08));
1079 goto done;
1080 }
1081
1082 mask = ISSET(cmd->c_flags, SCF_CMD_READ)((cmd->c_flags) & (0x0040)) ?
1083 SDHC_BUFFER_READ_ENABLE(1<<11) : SDHC_BUFFER_WRITE_ENABLE(1<<10);
1084 error = 0;
1085 datalen = cmd->c_datalen;
1086
1087 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc),do {} while(0)
1088 MMC_R1(cmd->c_resp), datalen))do {} while(0);
1089
1090#ifdef SDHC_DEBUG
1091 /* XXX I forgot why I wanted to know when this happens :-( */
1092 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) &&
1093 ISSET(MMC_R1(cmd->c_resp), 0xcb00)((((cmd->c_resp)[0])) & (0xcb00)))
1094 printf("%s: CMD52/53 error response flags %#x\n",
1095 DEVNAME(hp->sc)((hp->sc)->sc_dev.dv_xname), MMC_R1(cmd->c_resp)((cmd->c_resp)[0]) & 0xff00);
1096#endif
1097
1098 while (datalen > 0) {
1099 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY(1<<5)|
1100 SDHC_BUFFER_WRITE_READY(1<<4), SDHC_BUFFER_TIMEOUT1)) {
1101 error = ETIMEDOUT60;
1102 break;
1103 }
1104
1105 if ((error = sdhc_wait_state(hp, mask, mask)) != 0)
1106 break;
1107
1108 i = MIN(datalen, cmd->c_blklen)(((datalen)<(cmd->c_blklen))?(datalen):(cmd->c_blklen
));
1109 if (ISSET(cmd->c_flags, SCF_CMD_READ)((cmd->c_flags) & (0x0040)))
1110 sdhc_read_data(hp, datap, i);
1111 else
1112 sdhc_write_data(hp, datap, i);
1113
1114 datap += i;
1115 datalen -= i;
1116 }
1117
1118 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE(1<<1),
1119 SDHC_TRANSFER_TIMEOUT1))
1120 error = ETIMEDOUT60;
1121
1122done:
1123 if (error != 0)
1124 cmd->c_error = error;
1125 SET(cmd->c_flags, SCF_ITSDONE)((cmd->c_flags) |= (0x0001));
1126
1127 DPRINTF(1,("%s: data transfer done (error=%d)\n",do {} while(0)
1128 DEVNAME(hp->sc), cmd->c_error))do {} while(0);
1129}
1130
1131void
1132sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen)
1133{
1134 while (datalen > 3) {
1135 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA)((((hp)->iot)->read_4(((hp)->ioh), ((0x20)))));
1136 datap += 4;
1137 datalen -= 4;
1138 }
1139 if (datalen > 0) {
1140 u_int32_t rv = HREAD4(hp, SDHC_DATA)((((hp)->iot)->read_4(((hp)->ioh), ((0x20)))));
1141 do {
1142 *datap++ = rv & 0xff;
1143 rv = rv >> 8;
1144 } while (--datalen > 0);
1145 }
1146}
1147
1148void
1149sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen)
1150{
1151 while (datalen > 3) {
1152 DPRINTF(3,("%08x\n", *(u_int32_t *)datap))do {} while(0);
1153 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap))(((hp)->iot)->write_4(((hp)->ioh), ((0x20)), ((*((u_int32_t
*)datap)))));
1154 datap += 4;
1155 datalen -= 4;
1156 }
1157 if (datalen > 0) {
1158 u_int32_t rv = *datap++;
1159 if (datalen > 1)
1160 rv |= *datap++ << 8;
1161 if (datalen > 2)
1162 rv |= *datap++ << 16;
1163 DPRINTF(3,("rv %08x\n", rv))do {} while(0);
1164 HWRITE4(hp, SDHC_DATA, rv)(((hp)->iot)->write_4(((hp)->ioh), ((0x20)), ((rv)))
);
1165 }
1166}
1167
1168/* Prepare for another command. */
1169int
1170sdhc_soft_reset(struct sdhc_host *hp, int mask)
1171{
1172 int timo;
1173
1174 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask))do {} while(0);
1175
1176 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask)sdhc_write_1((hp), (0x2f), (mask));
1177 for (timo = 10; timo > 0; timo--) {
1178 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)(((sdhc_read_1((hp), (0x2f)))) & (mask)))
1179 break;
1180 sdmmc_delay(10000);
1181 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0)sdhc_write_1((hp), (0x2f), (0));
1182 }
1183 if (timo == 0) {
1184 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc),do {} while(0)
1185 HREAD1(hp, SDHC_SOFTWARE_RESET)))do {} while(0);
1186 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0)sdhc_write_1((hp), (0x2f), (0));
1187 return (ETIMEDOUT60);
1188 }
1189
1190 return (0);
1191}
1192
1193int
1194sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs)
1195{
1196 int status, usecs;
1197
1198 mask |= SDHC_ERROR_INTERRUPT(1<<15);
1199 usecs = secs * 1000000;
1200 status = hp->intr_status;
1201 while ((status & mask) == 0) {
1202
1203 status = HREAD2(hp, SDHC_NINTR_STATUS)(sdhc_read_2((hp), (0x30)));
1204 if (ISSET(status, SDHC_NINTR_STATUS_MASK)((status) & (0x91ff))) {
1205 HWRITE2(hp, SDHC_NINTR_STATUS, status)sdhc_write_2((hp), (0x30), (status));
1206 if (ISSET(status, SDHC_ERROR_INTERRUPT)((status) & ((1<<15)))) {
1207 uint16_t error;
1208 error = HREAD2(hp, SDHC_EINTR_STATUS)(sdhc_read_2((hp), (0x32)));
1209 HWRITE2(hp, SDHC_EINTR_STATUS, error)sdhc_write_2((hp), (0x32), (error));
1210 hp->intr_status |= status;
1211
1212 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR|((error) & ((1<<0)| (1<<4)))
1213 SDHC_DATA_TIMEOUT_ERROR)((error) & ((1<<0)| (1<<4))))
1214 break;
1215 }
1216
1217 if (ISSET(status, SDHC_BUFFER_READ_READY |((status) & ((1<<5) | (1<<4) | (1<<0) |
(1<<1)))
1218 SDHC_BUFFER_WRITE_READY | SDHC_COMMAND_COMPLETE |((status) & ((1<<5) | (1<<4) | (1<<0) |
(1<<1)))
1219 SDHC_TRANSFER_COMPLETE)((status) & ((1<<5) | (1<<4) | (1<<0) |
(1<<1)))) {
1220 hp->intr_status |= status;
1221 break;
1222 }
1223
1224 if (ISSET(status, SDHC_CARD_INTERRUPT)((status) & ((1<<8)))) {
1225 HSET2(hp, SDHC_NINTR_STATUS_EN,sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) | ((1<<8))))
1226 SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) | ((1<<8))));
1227 }
1228
1229 continue;
1230 }
1231
1232 delay(1)(*delay_func)(1);
1233 if (usecs-- == 0) {
1234 status |= SDHC_ERROR_INTERRUPT(1<<15);
1235 break;
1236 }
1237 }
1238
1239 hp->intr_status &= ~(status & mask);
1240 return (status & mask);
1241}
1242
1243int
1244sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs)
1245{
1246 int status;
1247 int s;
1248
1249 if (cold)
1250 return (sdhc_wait_intr_cold(hp, mask, secs));
1251
1252 mask |= SDHC_ERROR_INTERRUPT(1<<15);
1253
1254 s = splsdmmc()splraise(0x6);
1255 status = hp->intr_status & mask;
1256 while (status == 0) {
1257 if (tsleep_nsec(&hp->intr_status, PWAIT32, "hcintr",
1258 SEC_TO_NSEC(secs)) == EWOULDBLOCK35) {
1259 status |= SDHC_ERROR_INTERRUPT(1<<15);
1260 break;
1261 }
1262 status = hp->intr_status & mask;
1263 }
1264 hp->intr_status &= ~status;
1265
1266 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status,do {} while(0)
1267 hp->intr_error_status))do {} while(0);
1268
1269 /* Command timeout has higher priority than command complete. */
1270 if (ISSET(status, SDHC_ERROR_INTERRUPT)((status) & ((1<<15)))) {
1271 hp->intr_error_status = 0;
1272 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT(1<<2)|SDHC_RESET_CMD(1<<1));
1273 status = 0;
1274 }
1275
1276 splx(s)spllower(s);
1277 return status;
1278}
1279
1280/*
1281 * Established by attachment driver at interrupt priority IPL_SDMMC.
1282 */
1283int
1284sdhc_intr(void *arg)
1285{
1286 struct sdhc_softc *sc = arg;
1287 int host;
1288 int done = 0;
1289
1290 /* We got an interrupt, but we don't know from which slot. */
1291 for (host = 0; host < sc->sc_nhosts; host++) {
1292 struct sdhc_host *hp = sc->sc_host[host];
1293 u_int16_t status;
1294
1295 if (hp == NULL((void *)0))
1296 continue;
1297
1298 /* Find out which interrupts are pending. */
1299 status = HREAD2(hp, SDHC_NINTR_STATUS)(sdhc_read_2((hp), (0x30)));
1300 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)((status) & (0x91ff)))
1301 continue; /* no interrupt for us */
1302
1303 /* Acknowledge the interrupts we are about to handle. */
1304 HWRITE2(hp, SDHC_NINTR_STATUS, status)sdhc_write_2((hp), (0x30), (status));
1305 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc),do {} while(0)
1306 status, SDHC_NINTR_STATUS_BITS))do {} while(0);
1307
1308 /* Claim this interrupt. */
1309 done = 1;
1310
1311 /*
1312 * Service error interrupts.
1313 */
1314 if (ISSET(status, SDHC_ERROR_INTERRUPT)((status) & ((1<<15)))) {
1315 u_int16_t error;
1316
1317 /* Acknowledge error interrupts. */
1318 error = HREAD2(hp, SDHC_EINTR_STATUS)(sdhc_read_2((hp), (0x32)));
1319 HWRITE2(hp, SDHC_EINTR_STATUS, error)sdhc_write_2((hp), (0x32), (error));
1320 DPRINTF(2,("%s: error interrupt, status=%b\n",do {} while(0)
1321 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS))do {} while(0);
1322
1323 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR|((error) & ((1<<0)| (1<<4)))
1324 SDHC_DATA_TIMEOUT_ERROR)((error) & ((1<<0)| (1<<4)))) {
1325 hp->intr_error_status |= error;
1326 hp->intr_status |= status;
1327 wakeup(&hp->intr_status);
1328 }
1329 }
1330
1331 /*
1332 * Wake up the sdmmc event thread to scan for cards.
1333 */
1334 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)((status) & ((1<<7)|(1<<6))))
1335 sdmmc_needs_discover(hp->sdmmc);
1336
1337 /*
1338 * Wake up the blocking process to service command
1339 * related interrupt(s).
1340 */
1341 if (ISSET(status, SDHC_BUFFER_READ_READY|((status) & ((1<<5)| (1<<4)|(1<<0)| (1<<
1)))
1342 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE|((status) & ((1<<5)| (1<<4)|(1<<0)| (1<<
1)))
1343 SDHC_TRANSFER_COMPLETE)((status) & ((1<<5)| (1<<4)|(1<<0)| (1<<
1)))) {
1344 hp->intr_status |= status;
1345 wakeup(&hp->intr_status);
1346 }
1347
1348 /*
1349 * Service SD card interrupts.
1350 */
1351 if (ISSET(status, SDHC_CARD_INTERRUPT)((status) & ((1<<8)))) {
1352 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc)))do {} while(0);
1353 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) & ~((1<<8))));
1354 sdmmc_card_intr(hp->sdmmc);
1355 }
1356 }
1357 return done;
1358}
1359
1360void
1361sdhc_needs_discover(struct sdhc_softc *sc)
1362{
1363 int host;
1364
1365 for (host = 0; host < sc->sc_nhosts; host++)
1366 sdmmc_needs_discover(sc->sc_host[host]->sdmmc);
1367}
1368
1369#ifdef SDHC_DEBUG
1370void
1371sdhc_dump_regs(struct sdhc_host *hp)
1372{
1373 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE0x24,
1374 HREAD4(hp, SDHC_PRESENT_STATE)((((hp)->iot)->read_4(((hp)->ioh), ((0x24))))), SDHC_PRESENT_STATE_BITS"\20\31CL\30D3L\27D2L\26D1L\25D0L\24WPS\23CD\22CSS\21CI" "\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC");
1375 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL0x29,
1376 HREAD1(hp, SDHC_POWER_CTL)(sdhc_read_1((hp), (0x29))));
1377 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS0x30,
1378 HREAD2(hp, SDHC_NINTR_STATUS)(sdhc_read_2((hp), (0x30))));
1379 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS0x32,
1380 HREAD2(hp, SDHC_EINTR_STATUS)(sdhc_read_2((hp), (0x32))));
1381 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN0x34,
1382 HREAD2(hp, SDHC_NINTR_STATUS_EN)(sdhc_read_2((hp), (0x34))));
1383 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN0x36,
1384 HREAD2(hp, SDHC_EINTR_STATUS_EN)(sdhc_read_2((hp), (0x36))));
1385 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN0x38,
1386 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)(sdhc_read_2((hp), (0x38))));
1387 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN0x3a,
1388 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)(sdhc_read_2((hp), (0x3a))));
1389 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES0x40,
1390 HREAD4(hp, SDHC_CAPABILITIES)((((hp)->iot)->read_4(((hp)->ioh), ((0x40))))));
1391 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES0x48,
1392 HREAD4(hp, SDHC_MAX_CAPABILITIES)((((hp)->iot)->read_4(((hp)->ioh), ((0x48))))));
1393}
1394#endif
1395
1396int
1397sdhc_hibernate_init(sdmmc_chipset_handle_t sch, void *fake_softc)
1398{
1399 struct sdhc_host *hp, *fhp;
1400 fhp = fake_softc;
1401 hp = sch;
1402 *fhp = *hp;
1403
1404 return (0);
1405}