Bug Summary

File:dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
Warning:line 397, column 2
Value stored to 'misc0' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name dce_stream_encoder.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/delay.h>
27
28#include "dc_bios_types.h"
29#include "dce_stream_encoder.h"
30#include "reg_helper.h"
31#include "hw_shared.h"
32
33#define DC_LOGGERenc110->base.ctx->logger \
34 enc110->base.ctx->logger
35
36
37#define REG(reg)(enc110->regs->reg)\
38 (enc110->regs->reg)
39
40#undef FN
41#define FN(reg_name, field_name)enc110->se_shift->field_name, enc110->se_mask->field_name \
42 enc110->se_shift->field_name, enc110->se_mask->field_name
43
44#define VBI_LINE_00 0
45#define DP_BLANK_MAX_RETRY20 20
46#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M340000 340000
47
48#ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK0x00000010L
49 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK0x00000010L 0x00000010L
50 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK0x00000300L 0x00000300L
51 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT0x00000004 0x00000004
52 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT0x00000008 0x00000008
53#endif
54
55enum {
56 DP_MST_UPDATE_MAX_RETRY = 50
57};
58
59#define DCE110_SE(audio)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (audio); (struct dce110_stream_encoder *)( (char
*)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );})\
60 container_of(audio, struct dce110_stream_encoder, base)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (audio); (struct dce110_stream_encoder *)( (char
*)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );})
61
62#define CTXenc110->base.ctx \
63 enc110->base.ctx
64
65static void dce110_update_generic_info_packet(
66 struct dce110_stream_encoder *enc110,
67 uint32_t packet_index,
68 const struct dc_info_packet *info_packet)
69{
70 uint32_t regval;
71 /* TODOFPGA Figure out a proper number for max_retries polling for lock
72 * use 50 for now.
73 */
74 uint32_t max_retries = 50;
75
76 /*we need turn on clock before programming AFMT block*/
77 if (REG(AFMT_CNTL)(enc110->regs->AFMT_CNTL))
78 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_CNTL), 1, enc110->se_shift->AFMT_AUDIO_CLOCK_EN, enc110
->se_mask->AFMT_AUDIO_CLOCK_EN, 1);
79
80 if (REG(AFMT_VBI_PACKET_CONTROL1)(enc110->regs->AFMT_VBI_PACKET_CONTROL1)) {
81 if (packet_index >= 8)
82 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c"
, 82); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
83
84 /* poll dig_update_lock is not locked -> asic internal signal
85 * assume otg master lock will unlock it
86 */
87/* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
88 0, 10, max_retries);*/
89
90 /* check if HW reading GSP memory */
91 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,generic_reg_wait(enc110->base.ctx, (enc110->regs->AFMT_VBI_PACKET_CONTROL
), enc110->se_shift->AFMT_GENERIC_CONFLICT, enc110->
se_mask->AFMT_GENERIC_CONFLICT, 0, 10, max_retries, __func__
, 92)
92 0, 10, max_retries)generic_reg_wait(enc110->base.ctx, (enc110->regs->AFMT_VBI_PACKET_CONTROL
), enc110->se_shift->AFMT_GENERIC_CONFLICT, enc110->
se_mask->AFMT_GENERIC_CONFLICT, 0, 10, max_retries, __func__
, 92);
93
94 /* HW does is not reading GSP memory not reading too long ->
95 * something wrong. clear GPS memory access and notify?
96 * hw SW is writing to GSP memory
97 */
98 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL), 1, enc110->se_shift->AFMT_GENERIC_CONFLICT_CLR
, enc110->se_mask->AFMT_GENERIC_CONFLICT_CLR, 1);
99 }
100 /* choose which generic packet to use */
101 {
102 regval = REG_READ(AFMT_VBI_PACKET_CONTROL)dm_read_reg_func(enc110->base.ctx, (enc110->regs->AFMT_VBI_PACKET_CONTROL
), __func__);
103 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL), 1, enc110->se_shift->AFMT_GENERIC_INDEX
, enc110->se_mask->AFMT_GENERIC_INDEX, packet_index)
104 AFMT_GENERIC_INDEX, packet_index)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL), 1, enc110->se_shift->AFMT_GENERIC_INDEX
, enc110->se_mask->AFMT_GENERIC_INDEX, packet_index);
105 }
106
107 /* write generic packet header
108 * (4th byte is for GENERIC0 only) */
109 {
110 REG_SET_4(AFMT_GENERIC_HDR, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
AFMT_GENERIC_HDR), 0, 4, enc110->se_shift->AFMT_GENERIC_HB0
, enc110->se_mask->AFMT_GENERIC_HB0, info_packet->hb0
, enc110->se_shift->AFMT_GENERIC_HB1, enc110->se_mask
->AFMT_GENERIC_HB1, info_packet->hb1, enc110->se_shift
->AFMT_GENERIC_HB2, enc110->se_mask->AFMT_GENERIC_HB2
, info_packet->hb2, enc110->se_shift->AFMT_GENERIC_HB3
, enc110->se_mask->AFMT_GENERIC_HB3, info_packet->hb3
)
111 AFMT_GENERIC_HB0, info_packet->hb0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
AFMT_GENERIC_HDR), 0, 4, enc110->se_shift->AFMT_GENERIC_HB0
, enc110->se_mask->AFMT_GENERIC_HB0, info_packet->hb0
, enc110->se_shift->AFMT_GENERIC_HB1, enc110->se_mask
->AFMT_GENERIC_HB1, info_packet->hb1, enc110->se_shift
->AFMT_GENERIC_HB2, enc110->se_mask->AFMT_GENERIC_HB2
, info_packet->hb2, enc110->se_shift->AFMT_GENERIC_HB3
, enc110->se_mask->AFMT_GENERIC_HB3, info_packet->hb3
)
112 AFMT_GENERIC_HB1, info_packet->hb1,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
AFMT_GENERIC_HDR), 0, 4, enc110->se_shift->AFMT_GENERIC_HB0
, enc110->se_mask->AFMT_GENERIC_HB0, info_packet->hb0
, enc110->se_shift->AFMT_GENERIC_HB1, enc110->se_mask
->AFMT_GENERIC_HB1, info_packet->hb1, enc110->se_shift
->AFMT_GENERIC_HB2, enc110->se_mask->AFMT_GENERIC_HB2
, info_packet->hb2, enc110->se_shift->AFMT_GENERIC_HB3
, enc110->se_mask->AFMT_GENERIC_HB3, info_packet->hb3
)
113 AFMT_GENERIC_HB2, info_packet->hb2,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
AFMT_GENERIC_HDR), 0, 4, enc110->se_shift->AFMT_GENERIC_HB0
, enc110->se_mask->AFMT_GENERIC_HB0, info_packet->hb0
, enc110->se_shift->AFMT_GENERIC_HB1, enc110->se_mask
->AFMT_GENERIC_HB1, info_packet->hb1, enc110->se_shift
->AFMT_GENERIC_HB2, enc110->se_mask->AFMT_GENERIC_HB2
, info_packet->hb2, enc110->se_shift->AFMT_GENERIC_HB3
, enc110->se_mask->AFMT_GENERIC_HB3, info_packet->hb3
)
114 AFMT_GENERIC_HB3, info_packet->hb3)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
AFMT_GENERIC_HDR), 0, 4, enc110->se_shift->AFMT_GENERIC_HB0
, enc110->se_mask->AFMT_GENERIC_HB0, info_packet->hb0
, enc110->se_shift->AFMT_GENERIC_HB1, enc110->se_mask
->AFMT_GENERIC_HB1, info_packet->hb1, enc110->se_shift
->AFMT_GENERIC_HB2, enc110->se_mask->AFMT_GENERIC_HB2
, info_packet->hb2, enc110->se_shift->AFMT_GENERIC_HB3
, enc110->se_mask->AFMT_GENERIC_HB3, info_packet->hb3
);
115 }
116
117 /* write generic packet contents
118 * (we never use last 4 bytes)
119 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
120 {
121 const uint32_t *content =
122 (const uint32_t *) &info_packet->sb[0];
123
124 REG_WRITE(AFMT_GENERIC_0, *content++)dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_GENERIC_0
), *content++, __func__);
125 REG_WRITE(AFMT_GENERIC_1, *content++)dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_GENERIC_1
), *content++, __func__);
126 REG_WRITE(AFMT_GENERIC_2, *content++)dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_GENERIC_2
), *content++, __func__);
127 REG_WRITE(AFMT_GENERIC_3, *content++)dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_GENERIC_3
), *content++, __func__);
128 REG_WRITE(AFMT_GENERIC_4, *content++)dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_GENERIC_4
), *content++, __func__);
129 REG_WRITE(AFMT_GENERIC_5, *content++)dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_GENERIC_5
), *content++, __func__);
130 REG_WRITE(AFMT_GENERIC_6, *content++)dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_GENERIC_6
), *content++, __func__);
131 REG_WRITE(AFMT_GENERIC_7, *content)dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_GENERIC_7
), *content, __func__);
132 }
133
134 if (!REG(AFMT_VBI_PACKET_CONTROL1)(enc110->regs->AFMT_VBI_PACKET_CONTROL1)) {
135 /* force double-buffered packet update */
136 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL), 2, enc110->se_shift->AFMT_GENERIC0_UPDATE
, enc110->se_mask->AFMT_GENERIC0_UPDATE, (packet_index ==
0), enc110->se_shift->AFMT_GENERIC2_UPDATE, enc110->
se_mask->AFMT_GENERIC2_UPDATE, (packet_index == 2))
137 AFMT_GENERIC0_UPDATE, (packet_index == 0),generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL), 2, enc110->se_shift->AFMT_GENERIC0_UPDATE
, enc110->se_mask->AFMT_GENERIC0_UPDATE, (packet_index ==
0), enc110->se_shift->AFMT_GENERIC2_UPDATE, enc110->
se_mask->AFMT_GENERIC2_UPDATE, (packet_index == 2))
138 AFMT_GENERIC2_UPDATE, (packet_index == 2))generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL), 2, enc110->se_shift->AFMT_GENERIC0_UPDATE
, enc110->se_mask->AFMT_GENERIC0_UPDATE, (packet_index ==
0), enc110->se_shift->AFMT_GENERIC2_UPDATE, enc110->
se_mask->AFMT_GENERIC2_UPDATE, (packet_index == 2));
139 }
140#if defined(CONFIG_DRM_AMD_DC_DCN1)
141 if (REG(AFMT_VBI_PACKET_CONTROL1)(enc110->regs->AFMT_VBI_PACKET_CONTROL1)) {
142 switch (packet_index) {
143 case 0:
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC0_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC0_FRAME_UPDATE, 1)
145 AFMT_GENERIC0_FRAME_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC0_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC0_FRAME_UPDATE, 1);
146 break;
147 case 1:
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC1_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC1_FRAME_UPDATE, 1)
149 AFMT_GENERIC1_FRAME_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC1_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC1_FRAME_UPDATE, 1);
150 break;
151 case 2:
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC2_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC2_FRAME_UPDATE, 1)
153 AFMT_GENERIC2_FRAME_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC2_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC2_FRAME_UPDATE, 1);
154 break;
155 case 3:
156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC3_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC3_FRAME_UPDATE, 1)
157 AFMT_GENERIC3_FRAME_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC3_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC3_FRAME_UPDATE, 1);
158 break;
159 case 4:
160 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC4_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC4_FRAME_UPDATE, 1)
161 AFMT_GENERIC4_FRAME_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC4_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC4_FRAME_UPDATE, 1);
162 break;
163 case 5:
164 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC5_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC5_FRAME_UPDATE, 1)
165 AFMT_GENERIC5_FRAME_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC5_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC5_FRAME_UPDATE, 1);
166 break;
167 case 6:
168 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC6_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC6_FRAME_UPDATE, 1)
169 AFMT_GENERIC6_FRAME_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC6_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC6_FRAME_UPDATE, 1);
170 break;
171 case 7:
172 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC7_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC7_FRAME_UPDATE, 1)
173 AFMT_GENERIC7_FRAME_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_VBI_PACKET_CONTROL1), 1, enc110->se_shift->AFMT_GENERIC7_FRAME_UPDATE
, enc110->se_mask->AFMT_GENERIC7_FRAME_UPDATE, 1);
174 break;
175 default:
176 break;
177 }
178 }
179#endif
180}
181
182static void dce110_update_hdmi_info_packet(
183 struct dce110_stream_encoder *enc110,
184 uint32_t packet_index,
185 const struct dc_info_packet *info_packet)
186{
187 uint32_t cont, send, line;
188
189 if (info_packet->valid) {
190 dce110_update_generic_info_packet(
191 enc110,
192 packet_index,
193 info_packet);
194
195 /* enable transmission of packet(s) -
196 * packet transmission begins on the next frame */
197 cont = 1;
198 /* send packet(s) every frame */
199 send = 1;
200 /* select line number to send packets on */
201 line = 2;
202 } else {
203 cont = 0;
204 send = 0;
205 line = 0;
206 }
207
208 /* choose which generic packet control to use */
209 switch (packet_index) {
210 case 0:
211 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
212 HDMI_GENERIC0_CONT, cont,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
213 HDMI_GENERIC0_SEND, send,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
214 HDMI_GENERIC0_LINE, line)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line);
215 break;
216 case 1:
217 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
218 HDMI_GENERIC1_CONT, cont,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
219 HDMI_GENERIC1_SEND, send,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
220 HDMI_GENERIC1_LINE, line)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line);
221 break;
222 case 2:
223 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
224 HDMI_GENERIC0_CONT, cont,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
225 HDMI_GENERIC0_SEND, send,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
226 HDMI_GENERIC0_LINE, line)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line);
227 break;
228 case 3:
229 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
230 HDMI_GENERIC1_CONT, cont,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
231 HDMI_GENERIC1_SEND, send,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
232 HDMI_GENERIC1_LINE, line)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line);
233 break;
234#if defined(CONFIG_DRM_AMD_DC_DCN1)
235 case 4:
236 if (REG(HDMI_GENERIC_PACKET_CONTROL2)(enc110->regs->HDMI_GENERIC_PACKET_CONTROL2))
237 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
238 HDMI_GENERIC0_CONT, cont,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
239 HDMI_GENERIC0_SEND, send,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
240 HDMI_GENERIC0_LINE, line)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line);
241 break;
242 case 5:
243 if (REG(HDMI_GENERIC_PACKET_CONTROL2)(enc110->regs->HDMI_GENERIC_PACKET_CONTROL2))
244 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
245 HDMI_GENERIC1_CONT, cont,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
246 HDMI_GENERIC1_SEND, send,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
247 HDMI_GENERIC1_LINE, line)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line);
248 break;
249 case 6:
250 if (REG(HDMI_GENERIC_PACKET_CONTROL3)(enc110->regs->HDMI_GENERIC_PACKET_CONTROL3))
251 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
252 HDMI_GENERIC0_CONT, cont,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
253 HDMI_GENERIC0_SEND, send,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line)
254 HDMI_GENERIC0_LINE, line)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 3, enc110->se_shift->HDMI_GENERIC0_CONT
, enc110->se_mask->HDMI_GENERIC0_CONT, cont, enc110->
se_shift->HDMI_GENERIC0_SEND, enc110->se_mask->HDMI_GENERIC0_SEND
, send, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->
se_mask->HDMI_GENERIC0_LINE, line);
255 break;
256 case 7:
257 if (REG(HDMI_GENERIC_PACKET_CONTROL3)(enc110->regs->HDMI_GENERIC_PACKET_CONTROL3))
258 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
259 HDMI_GENERIC1_CONT, cont,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
260 HDMI_GENERIC1_SEND, send,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line)
261 HDMI_GENERIC1_LINE, line)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 3, enc110->se_shift->HDMI_GENERIC1_CONT
, enc110->se_mask->HDMI_GENERIC1_CONT, cont, enc110->
se_shift->HDMI_GENERIC1_SEND, enc110->se_mask->HDMI_GENERIC1_SEND
, send, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->
se_mask->HDMI_GENERIC1_LINE, line);
262 break;
263#endif
264 default:
265 /* invalid HW packet index */
266 DC_LOG_WARNING(printk("\0014" "[" "drm" "] " "Invalid HW packet index: %s()\n"
, __func__)
267 "Invalid HW packet index: %s()\n",printk("\0014" "[" "drm" "] " "Invalid HW packet index: %s()\n"
, __func__)
268 __func__)printk("\0014" "[" "drm" "] " "Invalid HW packet index: %s()\n"
, __func__);
269 return;
270 }
271}
272
273/* setup stream encoder in dp mode */
274static void dce110_stream_encoder_dp_set_stream_attribute(
275 struct stream_encoder *enc,
276 struct dc_crtc_timing *crtc_timing,
277 enum dc_color_space output_color_space,
278 bool_Bool use_vsc_sdp_for_colorimetry,
279 uint32_t enable_sdp_splitting)
280{
281#if defined(CONFIG_DRM_AMD_DC_DCN1)
282 uint32_t h_active_start;
283 uint32_t v_active_start;
284 uint32_t misc0 = 0;
285 uint32_t misc1 = 0;
286 uint32_t h_blank;
287 uint32_t h_back_porch;
288 uint8_t synchronous_clock = 0; /* asynchronous mode */
289 uint8_t colorimetry_bpc;
290 uint8_t dynamic_range_rgb = 0; /*full range*/
291 uint8_t dynamic_range_ycbcr = 1; /*bt709*/
292#endif
293
294 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
295 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
296 if (hw_crtc_timing.flags.INTERLACE) {
297 /*the input timing is in VESA spec format with Interlace flag =1*/
298 hw_crtc_timing.v_total /= 2;
299 hw_crtc_timing.v_border_top /= 2;
300 hw_crtc_timing.v_addressable /= 2;
301 hw_crtc_timing.v_border_bottom /= 2;
302 hw_crtc_timing.v_front_porch /= 2;
303 hw_crtc_timing.v_sync_width /= 2;
304 }
305 /* set pixel encoding */
306 switch (hw_crtc_timing.pixel_encoding) {
307 case PIXEL_ENCODING_YCBCR422:
308 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_YCBCR422
)
309 DP_PIXEL_ENCODING_TYPE_YCBCR422)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_YCBCR422
);
310 break;
311 case PIXEL_ENCODING_YCBCR444:
312 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_YCBCR444
)
313 DP_PIXEL_ENCODING_TYPE_YCBCR444)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_YCBCR444
);
314
315 if (hw_crtc_timing.flags.Y_ONLY)
316 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
317 /* HW testing only, no use case yet.
318 * Color depth of Y-only could be
319 * 8, 10, 12, 16 bits */
320 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_Y_ONLY
)
321 DP_PIXEL_ENCODING_TYPE_Y_ONLY)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_Y_ONLY
);
322 /* Note: DP_MSA_MISC1 bit 7 is the indicator
323 * of Y-only mode.
324 * This bit is set in HW if register
325 * DP_PIXEL_ENCODING is programmed to 0x4 */
326 break;
327 case PIXEL_ENCODING_YCBCR420:
328 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_YCBCR420
)
329 DP_PIXEL_ENCODING_TYPE_YCBCR420)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_YCBCR420
);
330 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
331 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_TIMING), 1, enc110->se_shift->DP_VID_M_DOUBLE_VALUE_EN
, enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN, 1);
332
333#if defined(CONFIG_DRM_AMD_DC_DCN1)
334 if (enc110->se_mask->DP_VID_N_MUL)
335 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_TIMING), 1, enc110->se_shift->DP_VID_N_MUL, enc110
->se_mask->DP_VID_N_MUL, 1);
336#endif
337 break;
338 default:
339 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_RGB444
)
340 DP_PIXEL_ENCODING_TYPE_RGB444)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_PIXEL_ENCODING
, enc110->se_mask->DP_PIXEL_ENCODING, DP_PIXEL_ENCODING_TYPE_RGB444
);
341 break;
342 }
343
344#if defined(CONFIG_DRM_AMD_DC_DCN1)
345 if (REG(DP_MSA_MISC)(enc110->regs->DP_MSA_MISC))
346 misc1 = REG_READ(DP_MSA_MISC)dm_read_reg_func(enc110->base.ctx, (enc110->regs->DP_MSA_MISC
), __func__);
347#endif
348
349 /* set color depth */
350
351 switch (hw_crtc_timing.display_color_depth) {
352 case COLOR_DEPTH_666:
353 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, 0)
354 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, 0);
355 break;
356 case COLOR_DEPTH_888:
357 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, DP_COMPONENT_PIXEL_DEPTH_8BPC
)
358 DP_COMPONENT_PIXEL_DEPTH_8BPC)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, DP_COMPONENT_PIXEL_DEPTH_8BPC
);
359 break;
360 case COLOR_DEPTH_101010:
361 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, DP_COMPONENT_PIXEL_DEPTH_10BPC
)
362 DP_COMPONENT_PIXEL_DEPTH_10BPC)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, DP_COMPONENT_PIXEL_DEPTH_10BPC
);
363
364 break;
365 case COLOR_DEPTH_121212:
366 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, DP_COMPONENT_PIXEL_DEPTH_12BPC
)
367 DP_COMPONENT_PIXEL_DEPTH_12BPC)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, DP_COMPONENT_PIXEL_DEPTH_12BPC
);
368 break;
369 default:
370 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, DP_COMPONENT_PIXEL_DEPTH_6BPC
)
371 DP_COMPONENT_PIXEL_DEPTH_6BPC)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 1, enc110->se_shift->DP_COMPONENT_DEPTH
, enc110->se_mask->DP_COMPONENT_DEPTH, DP_COMPONENT_PIXEL_DEPTH_6BPC
);
372 break;
373 }
374
375 /* set dynamic range and YCbCr range */
376
377
378#if defined(CONFIG_DRM_AMD_DC_DCN1)
379 switch (hw_crtc_timing.display_color_depth) {
380 case COLOR_DEPTH_666:
381 colorimetry_bpc = 0;
382 break;
383 case COLOR_DEPTH_888:
384 colorimetry_bpc = 1;
385 break;
386 case COLOR_DEPTH_101010:
387 colorimetry_bpc = 2;
388 break;
389 case COLOR_DEPTH_121212:
390 colorimetry_bpc = 3;
391 break;
392 default:
393 colorimetry_bpc = 0;
394 break;
395 }
396
397 misc0 = misc0 | synchronous_clock;
Value stored to 'misc0' is never read
398 misc0 = colorimetry_bpc << 5;
399
400 if (REG(DP_MSA_TIMING_PARAM1)(enc110->regs->DP_MSA_TIMING_PARAM1)) {
401 switch (output_color_space) {
402 case COLOR_SPACE_SRGB:
403 misc0 = misc0 | 0x0;
404 misc1 = misc1 & ~0x80; /* bit7 = 0*/
405 dynamic_range_rgb = 0; /*full range*/
406 break;
407 case COLOR_SPACE_SRGB_LIMITED:
408 misc0 = misc0 | 0x8; /* bit3=1 */
409 misc1 = misc1 & ~0x80; /* bit7 = 0*/
410 dynamic_range_rgb = 1; /*limited range*/
411 break;
412 case COLOR_SPACE_YCBCR601:
413 case COLOR_SPACE_YCBCR601_LIMITED:
414 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
415 misc1 = misc1 & ~0x80; /* bit7 = 0*/
416 dynamic_range_ycbcr = 0; /*bt601*/
417 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
418 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
419 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
420 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
421 break;
422 case COLOR_SPACE_YCBCR709:
423 case COLOR_SPACE_YCBCR709_LIMITED:
424 case COLOR_SPACE_YCBCR709_BLACK:
425 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
426 misc1 = misc1 & ~0x80; /* bit7 = 0*/
427 dynamic_range_ycbcr = 1; /*bt709*/
428 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
429 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
430 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
431 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
432 break;
433 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
434 dynamic_range_rgb = 1; /*limited range*/
435 break;
436 case COLOR_SPACE_2020_RGB_FULLRANGE:
437 case COLOR_SPACE_2020_YCBCR:
438 case COLOR_SPACE_XR_RGB:
439 case COLOR_SPACE_MSREF_SCRGB:
440 case COLOR_SPACE_ADOBERGB:
441 case COLOR_SPACE_DCIP3:
442 case COLOR_SPACE_XV_YCC_709:
443 case COLOR_SPACE_XV_YCC_601:
444 case COLOR_SPACE_DISPLAYNATIVE:
445 case COLOR_SPACE_DOLBYVISION:
446 case COLOR_SPACE_APPCTRL:
447 case COLOR_SPACE_CUSTOMPOINTS:
448 case COLOR_SPACE_UNKNOWN:
449 /* do nothing */
450 break;
451 }
452 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
453 REG_UPDATE_2(generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 2, enc110->se_shift->DP_DYN_RANGE, enc110
->se_mask->DP_DYN_RANGE, dynamic_range_rgb, enc110->
se_shift->DP_YCBCR_RANGE, enc110->se_mask->DP_YCBCR_RANGE
, dynamic_range_ycbcr)
454 DP_PIXEL_FORMAT,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 2, enc110->se_shift->DP_DYN_RANGE, enc110
->se_mask->DP_DYN_RANGE, dynamic_range_rgb, enc110->
se_shift->DP_YCBCR_RANGE, enc110->se_mask->DP_YCBCR_RANGE
, dynamic_range_ycbcr)
455 DP_DYN_RANGE, dynamic_range_rgb,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 2, enc110->se_shift->DP_DYN_RANGE, enc110
->se_mask->DP_DYN_RANGE, dynamic_range_rgb, enc110->
se_shift->DP_YCBCR_RANGE, enc110->se_mask->DP_YCBCR_RANGE
, dynamic_range_ycbcr)
456 DP_YCBCR_RANGE, dynamic_range_ycbcr)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_PIXEL_FORMAT), 2, enc110->se_shift->DP_DYN_RANGE, enc110
->se_mask->DP_DYN_RANGE, dynamic_range_rgb, enc110->
se_shift->DP_YCBCR_RANGE, enc110->se_mask->DP_YCBCR_RANGE
, dynamic_range_ycbcr);
457
458#if defined(CONFIG_DRM_AMD_DC_DCN1)
459 if (REG(DP_MSA_COLORIMETRY)(enc110->regs->DP_MSA_COLORIMETRY))
460 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_COLORIMETRY), 0, 1, enc110->se_shift->DP_MSA_MISC0
, enc110->se_mask->DP_MSA_MISC0, misc0);
461
462 if (REG(DP_MSA_MISC)(enc110->regs->DP_MSA_MISC))
463 REG_WRITE(DP_MSA_MISC, misc1)dm_write_reg_func(enc110->base.ctx, (enc110->regs->DP_MSA_MISC
), misc1, __func__); /* MSA_MISC1 */
464
465 /* dcn new register
466 * dc_crtc_timing is vesa dmt struct. data from edid
467 */
468 if (REG(DP_MSA_TIMING_PARAM1)(enc110->regs->DP_MSA_TIMING_PARAM1))
469 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM1), 0, 2, enc110->se_shift->DP_MSA_HTOTAL
, enc110->se_mask->DP_MSA_HTOTAL, hw_crtc_timing.h_total
, enc110->se_shift->DP_MSA_VTOTAL, enc110->se_mask->
DP_MSA_VTOTAL, hw_crtc_timing.v_total)
470 DP_MSA_HTOTAL, hw_crtc_timing.h_total,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM1), 0, 2, enc110->se_shift->DP_MSA_HTOTAL
, enc110->se_mask->DP_MSA_HTOTAL, hw_crtc_timing.h_total
, enc110->se_shift->DP_MSA_VTOTAL, enc110->se_mask->
DP_MSA_VTOTAL, hw_crtc_timing.v_total)
471 DP_MSA_VTOTAL, hw_crtc_timing.v_total)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM1), 0, 2, enc110->se_shift->DP_MSA_HTOTAL
, enc110->se_mask->DP_MSA_HTOTAL, hw_crtc_timing.h_total
, enc110->se_shift->DP_MSA_VTOTAL, enc110->se_mask->
DP_MSA_VTOTAL, hw_crtc_timing.v_total);
472#endif
473
474 /* calcuate from vesa timing parameters
475 * h_active_start related to leading edge of sync
476 */
477
478 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
479 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
480
481 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
482 hw_crtc_timing.h_sync_width;
483
484 /* start at begining of left border */
485 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
486
487
488 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
489 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
490 hw_crtc_timing.v_front_porch;
491
492
493#if defined(CONFIG_DRM_AMD_DC_DCN1)
494 /* start at begining of left border */
495 if (REG(DP_MSA_TIMING_PARAM2)(enc110->regs->DP_MSA_TIMING_PARAM2))
496 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM2), 0, 2, enc110->se_shift->DP_MSA_HSTART
, enc110->se_mask->DP_MSA_HSTART, h_active_start, enc110
->se_shift->DP_MSA_VSTART, enc110->se_mask->DP_MSA_VSTART
, v_active_start)
497 DP_MSA_HSTART, h_active_start,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM2), 0, 2, enc110->se_shift->DP_MSA_HSTART
, enc110->se_mask->DP_MSA_HSTART, h_active_start, enc110
->se_shift->DP_MSA_VSTART, enc110->se_mask->DP_MSA_VSTART
, v_active_start)
498 DP_MSA_VSTART, v_active_start)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM2), 0, 2, enc110->se_shift->DP_MSA_HSTART
, enc110->se_mask->DP_MSA_HSTART, h_active_start, enc110
->se_shift->DP_MSA_VSTART, enc110->se_mask->DP_MSA_VSTART
, v_active_start);
499
500 if (REG(DP_MSA_TIMING_PARAM3)(enc110->regs->DP_MSA_TIMING_PARAM3))
501 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)
502 DP_MSA_HSYNCWIDTH,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)
503 hw_crtc_timing.h_sync_width,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)
504 DP_MSA_HSYNCPOLARITY,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)
505 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)
506 DP_MSA_VSYNCWIDTH,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)
507 hw_crtc_timing.v_sync_width,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)
508 DP_MSA_VSYNCPOLARITY,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)
509 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM3), 0, 4, enc110->se_shift->DP_MSA_HSYNCWIDTH
, enc110->se_mask->DP_MSA_HSYNCWIDTH, hw_crtc_timing.h_sync_width
, enc110->se_shift->DP_MSA_HSYNCPOLARITY, enc110->se_mask
->DP_MSA_HSYNCPOLARITY, !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY
, enc110->se_shift->DP_MSA_VSYNCWIDTH, enc110->se_mask
->DP_MSA_VSYNCWIDTH, hw_crtc_timing.v_sync_width, enc110->
se_shift->DP_MSA_VSYNCPOLARITY, enc110->se_mask->DP_MSA_VSYNCPOLARITY
, !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
510
511 /* HWDITH include border or overscan */
512 if (REG(DP_MSA_TIMING_PARAM4)(enc110->regs->DP_MSA_TIMING_PARAM4))
513 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM4), 0, 2, enc110->se_shift->DP_MSA_HWIDTH
, enc110->se_mask->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left
+ hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right
, enc110->se_shift->DP_MSA_VHEIGHT, enc110->se_mask->
DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + hw_crtc_timing.
v_addressable + hw_crtc_timing.v_border_bottom)
514 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM4), 0, 2, enc110->se_shift->DP_MSA_HWIDTH
, enc110->se_mask->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left
+ hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right
, enc110->se_shift->DP_MSA_VHEIGHT, enc110->se_mask->
DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + hw_crtc_timing.
v_addressable + hw_crtc_timing.v_border_bottom)
515 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM4), 0, 2, enc110->se_shift->DP_MSA_HWIDTH
, enc110->se_mask->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left
+ hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right
, enc110->se_shift->DP_MSA_VHEIGHT, enc110->se_mask->
DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + hw_crtc_timing.
v_addressable + hw_crtc_timing.v_border_bottom)
516 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM4), 0, 2, enc110->se_shift->DP_MSA_HWIDTH
, enc110->se_mask->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left
+ hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right
, enc110->se_shift->DP_MSA_VHEIGHT, enc110->se_mask->
DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + hw_crtc_timing.
v_addressable + hw_crtc_timing.v_border_bottom)
517 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSA_TIMING_PARAM4), 0, 2, enc110->se_shift->DP_MSA_HWIDTH
, enc110->se_mask->DP_MSA_HWIDTH, hw_crtc_timing.h_border_left
+ hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right
, enc110->se_shift->DP_MSA_VHEIGHT, enc110->se_mask->
DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + hw_crtc_timing.
v_addressable + hw_crtc_timing.v_border_bottom);
518#endif
519 }
520#endif
521}
522
523static void dce110_stream_encoder_set_stream_attribute_helper(
524 struct dce110_stream_encoder *enc110,
525 struct dc_crtc_timing *crtc_timing)
526{
527 if (enc110->regs->TMDS_CNTL) {
528 switch (crtc_timing->pixel_encoding) {
529 case PIXEL_ENCODING_YCBCR422:
530 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
TMDS_CNTL), 1, enc110->se_shift->TMDS_PIXEL_ENCODING, enc110
->se_mask->TMDS_PIXEL_ENCODING, 1);
531 break;
532 default:
533 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
TMDS_CNTL), 1, enc110->se_shift->TMDS_PIXEL_ENCODING, enc110
->se_mask->TMDS_PIXEL_ENCODING, 0);
534 break;
535 }
536 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
TMDS_CNTL), 1, enc110->se_shift->TMDS_COLOR_FORMAT, enc110
->se_mask->TMDS_COLOR_FORMAT, 0);
537 } else if (enc110->regs->DIG_FE_CNTL) {
538 switch (crtc_timing->pixel_encoding) {
539 case PIXEL_ENCODING_YCBCR422:
540 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DIG_FE_CNTL), 1, enc110->se_shift->TMDS_PIXEL_ENCODING,
enc110->se_mask->TMDS_PIXEL_ENCODING, 1);
541 break;
542 default:
543 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DIG_FE_CNTL), 1, enc110->se_shift->TMDS_PIXEL_ENCODING,
enc110->se_mask->TMDS_PIXEL_ENCODING, 0);
544 break;
545 }
546 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DIG_FE_CNTL), 1, enc110->se_shift->TMDS_COLOR_FORMAT, enc110
->se_mask->TMDS_COLOR_FORMAT, 0);
547 }
548
549}
550
551/* setup stream encoder in hdmi mode */
552static void dce110_stream_encoder_hdmi_set_stream_attribute(
553 struct stream_encoder *enc,
554 struct dc_crtc_timing *crtc_timing,
555 int actual_pix_clk_khz,
556 bool_Bool enable_audio)
557{
558 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
559 struct bp_encoder_control cntl = {0};
560
561 cntl.action = ENCODER_CONTROL_SETUP;
562 cntl.engine_id = enc110->base.id;
563 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
564 cntl.enable_dp_audio = enable_audio;
565 cntl.pixel_clock = actual_pix_clk_khz;
566 cntl.lanes_number = LANE_COUNT_FOUR;
567 cntl.color_depth = crtc_timing->display_color_depth;
568
569 if (enc110->base.bp->funcs->encoder_control(
570 enc110->base.bp, &cntl) != BP_RESULT_OK)
571 return;
572
573 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
574
575 /* setup HDMI engine */
576 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
577 REG_UPDATE_3(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 3, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
578 HDMI_PACKET_GEN_VERSION, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 3, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
579 HDMI_KEEPOUT_MODE, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 3, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
580 HDMI_DEEP_COLOR_ENABLE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 3, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0);
581 } else if (enc110->regs->DIG_FE_CNTL) {
582 REG_UPDATE_5(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
583 HDMI_PACKET_GEN_VERSION, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
584 HDMI_KEEPOUT_MODE, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
585 HDMI_DEEP_COLOR_ENABLE, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
586 HDMI_DATA_SCRAMBLE_EN, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
587 HDMI_CLOCK_CHANNEL_RATE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0);
588 }
589
590 switch (crtc_timing->display_color_depth) {
591 case COLOR_DEPTH_888:
592 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 1, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 0);
593 break;
594 case COLOR_DEPTH_101010:
595 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
596 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 1, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 0)
597 HDMI_DEEP_COLOR_DEPTH, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 1, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 0)
598 HDMI_DEEP_COLOR_ENABLE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 1, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 0);
599 } else {
600 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 1, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1)
601 HDMI_DEEP_COLOR_DEPTH, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 1, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1)
602 HDMI_DEEP_COLOR_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 1, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1);
603 }
604 break;
605 case COLOR_DEPTH_121212:
606 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
607 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 2, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 0)
608 HDMI_DEEP_COLOR_DEPTH, 2,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 2, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 0)
609 HDMI_DEEP_COLOR_ENABLE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 2, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 0);
610 } else {
611 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 2, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1)
612 HDMI_DEEP_COLOR_DEPTH, 2,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 2, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1)
613 HDMI_DEEP_COLOR_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 2, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1);
614 }
615 break;
616 case COLOR_DEPTH_161616:
617 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 3, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1)
618 HDMI_DEEP_COLOR_DEPTH, 3,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 3, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1)
619 HDMI_DEEP_COLOR_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DEEP_COLOR_DEPTH
, enc110->se_mask->HDMI_DEEP_COLOR_DEPTH, 3, enc110->
se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->se_mask->HDMI_DEEP_COLOR_ENABLE
, 1);
620 break;
621 default:
622 break;
623 }
624
625 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
626 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M340000) {
627 /* enable HDMI data scrambler
628 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
629 * Clock channel frequency is 1/4 of character rate.
630 */
631 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN, 1, enc110->
se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->se_mask->
HDMI_CLOCK_CHANNEL_RATE, 1)
632 HDMI_DATA_SCRAMBLE_EN, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN, 1, enc110->
se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->se_mask->
HDMI_CLOCK_CHANNEL_RATE, 1)
633 HDMI_CLOCK_CHANNEL_RATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN, 1, enc110->
se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->se_mask->
HDMI_CLOCK_CHANNEL_RATE, 1);
634 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
635
636 /* TODO: New feature for DCE11, still need to implement */
637
638 /* enable HDMI data scrambler
639 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
640 * Clock channel frequency is the same
641 * as character rate
642 */
643 REG_UPDATE_2(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN, 1, enc110->
se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->se_mask->
HDMI_CLOCK_CHANNEL_RATE, 0)
644 HDMI_DATA_SCRAMBLE_EN, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN, 1, enc110->
se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->se_mask->
HDMI_CLOCK_CHANNEL_RATE, 0)
645 HDMI_CLOCK_CHANNEL_RATE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 2, enc110->se_shift->HDMI_DATA_SCRAMBLE_EN
, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN, 1, enc110->
se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->se_mask->
HDMI_CLOCK_CHANNEL_RATE, 0);
646 }
647 }
648
649 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_VBI_PACKET_CONTROL), 3, enc110->se_shift->HDMI_GC_CONT
, enc110->se_mask->HDMI_GC_CONT, 1, enc110->se_shift
->HDMI_GC_SEND, enc110->se_mask->HDMI_GC_SEND, 1, enc110
->se_shift->HDMI_NULL_SEND, enc110->se_mask->HDMI_NULL_SEND
, 1)
650 HDMI_GC_CONT, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_VBI_PACKET_CONTROL), 3, enc110->se_shift->HDMI_GC_CONT
, enc110->se_mask->HDMI_GC_CONT, 1, enc110->se_shift
->HDMI_GC_SEND, enc110->se_mask->HDMI_GC_SEND, 1, enc110
->se_shift->HDMI_NULL_SEND, enc110->se_mask->HDMI_NULL_SEND
, 1)
651 HDMI_GC_SEND, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_VBI_PACKET_CONTROL), 3, enc110->se_shift->HDMI_GC_CONT
, enc110->se_mask->HDMI_GC_CONT, 1, enc110->se_shift
->HDMI_GC_SEND, enc110->se_mask->HDMI_GC_SEND, 1, enc110
->se_shift->HDMI_NULL_SEND, enc110->se_mask->HDMI_NULL_SEND
, 1)
652 HDMI_NULL_SEND, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_VBI_PACKET_CONTROL), 3, enc110->se_shift->HDMI_GC_CONT
, enc110->se_mask->HDMI_GC_CONT, 1, enc110->se_shift
->HDMI_GC_SEND, enc110->se_mask->HDMI_GC_SEND, 1, enc110
->se_shift->HDMI_NULL_SEND, enc110->se_mask->HDMI_NULL_SEND
, 1);
653
654 /* following belongs to audio */
655 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL0), 1, enc110->se_shift->HDMI_AUDIO_INFO_SEND
, enc110->se_mask->HDMI_AUDIO_INFO_SEND, 1);
656
657 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_INFOFRAME_CONTROL0), 1, enc110->se_shift->AFMT_AUDIO_INFO_UPDATE
, enc110->se_mask->AFMT_AUDIO_INFO_UPDATE, 1);
658
659 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL1), 1, enc110->se_shift->HDMI_AUDIO_INFO_LINE
, enc110->se_mask->HDMI_AUDIO_INFO_LINE, 0 + 2)
660 VBI_LINE_0 + 2)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL1), 1, enc110->se_shift->HDMI_AUDIO_INFO_LINE
, enc110->se_mask->HDMI_AUDIO_INFO_LINE, 0 + 2);
661
662 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GC), 1, enc110->se_shift->HDMI_GC_AVMUTE, enc110->
se_mask->HDMI_GC_AVMUTE, 0);
663
664}
665
666/* setup stream encoder in dvi mode */
667static void dce110_stream_encoder_dvi_set_stream_attribute(
668 struct stream_encoder *enc,
669 struct dc_crtc_timing *crtc_timing,
670 bool_Bool is_dual_link)
671{
672 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
673 struct bp_encoder_control cntl = {0};
674
675 cntl.action = ENCODER_CONTROL_SETUP;
676 cntl.engine_id = enc110->base.id;
677 cntl.signal = is_dual_link ?
678 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
679 cntl.enable_dp_audio = false0;
680 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
681 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
682
683 if (enc110->base.bp->funcs->encoder_control(
684 enc110->base.bp, &cntl) != BP_RESULT_OK)
685 return;
686
687 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)do { if (({ static int __warned; int __ret = !!(!(crtc_timing
->pixel_encoding == PIXEL_ENCODING_RGB)); if (__ret &&
!__warned) { printf("WARNING %s failed at %s:%d\n", "!(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c"
, 687); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
688 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888)do { if (({ static int __warned; int __ret = !!(!(crtc_timing
->display_color_depth == COLOR_DEPTH_888)); if (__ret &&
!__warned) { printf("WARNING %s failed at %s:%d\n", "!(crtc_timing->display_color_depth == COLOR_DEPTH_888)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c"
, 688); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
689 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
690}
691
692/* setup stream encoder in LVDS mode */
693static void dce110_stream_encoder_lvds_set_stream_attribute(
694 struct stream_encoder *enc,
695 struct dc_crtc_timing *crtc_timing)
696{
697 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
698 struct bp_encoder_control cntl = {0};
699
700 cntl.action = ENCODER_CONTROL_SETUP;
701 cntl.engine_id = enc110->base.id;
702 cntl.signal = SIGNAL_TYPE_LVDS;
703 cntl.enable_dp_audio = false0;
704 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
705 cntl.lanes_number = LANE_COUNT_FOUR;
706
707 if (enc110->base.bp->funcs->encoder_control(
708 enc110->base.bp, &cntl) != BP_RESULT_OK)
709 return;
710
711 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)do { if (({ static int __warned; int __ret = !!(!(crtc_timing
->pixel_encoding == PIXEL_ENCODING_RGB)); if (__ret &&
!__warned) { printf("WARNING %s failed at %s:%d\n", "!(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c"
, 711); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
712}
713
714static void dce110_stream_encoder_set_throttled_vcp_size(
715 struct stream_encoder *enc,
716 struct fixed31_32 avg_time_slots_per_mtp)
717{
718 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
719 uint32_t x = dc_fixpt_floor(
720 avg_time_slots_per_mtp);
721 uint32_t y = dc_fixpt_ceil(
722 dc_fixpt_shl(
723 dc_fixpt_sub_int(
724 avg_time_slots_per_mtp,
725 x),
726 26));
727
728 {
729 REG_SET_2(DP_MSE_RATE_CNTL, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSE_RATE_CNTL), 0, 2, enc110->se_shift->DP_MSE_RATE_X
, enc110->se_mask->DP_MSE_RATE_X, x, enc110->se_shift
->DP_MSE_RATE_Y, enc110->se_mask->DP_MSE_RATE_Y, y)
730 DP_MSE_RATE_X, x,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSE_RATE_CNTL), 0, 2, enc110->se_shift->DP_MSE_RATE_X
, enc110->se_mask->DP_MSE_RATE_X, x, enc110->se_shift
->DP_MSE_RATE_Y, enc110->se_mask->DP_MSE_RATE_Y, y)
731 DP_MSE_RATE_Y, y)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_MSE_RATE_CNTL), 0, 2, enc110->se_shift->DP_MSE_RATE_X
, enc110->se_mask->DP_MSE_RATE_X, x, enc110->se_shift
->DP_MSE_RATE_Y, enc110->se_mask->DP_MSE_RATE_Y, y);
732 }
733
734 /* wait for update to be completed on the link */
735 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
736 /* is reset to 0 (not pending) */
737 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,generic_reg_wait(enc110->base.ctx, (enc110->regs->DP_MSE_RATE_UPDATE
), enc110->se_shift->DP_MSE_RATE_UPDATE_PENDING, enc110
->se_mask->DP_MSE_RATE_UPDATE_PENDING, 0, 10, DP_MST_UPDATE_MAX_RETRY
, __func__, 739)
738 0,generic_reg_wait(enc110->base.ctx, (enc110->regs->DP_MSE_RATE_UPDATE
), enc110->se_shift->DP_MSE_RATE_UPDATE_PENDING, enc110
->se_mask->DP_MSE_RATE_UPDATE_PENDING, 0, 10, DP_MST_UPDATE_MAX_RETRY
, __func__, 739)
739 10, DP_MST_UPDATE_MAX_RETRY)generic_reg_wait(enc110->base.ctx, (enc110->regs->DP_MSE_RATE_UPDATE
), enc110->se_shift->DP_MSE_RATE_UPDATE_PENDING, enc110
->se_mask->DP_MSE_RATE_UPDATE_PENDING, 0, 10, DP_MST_UPDATE_MAX_RETRY
, __func__, 739);
740}
741
742static void dce110_stream_encoder_update_hdmi_info_packets(
743 struct stream_encoder *enc,
744 const struct encoder_info_frame *info_frame)
745{
746 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
747
748 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
749 enc110->se_mask->HDMI_AVI_INFO_SEND) {
750
751 if (info_frame->avi.valid) {
752 const uint32_t *content =
753 (const uint32_t *) &info_frame->avi.sb[0];
754 /*we need turn on clock before programming AFMT block*/
755 if (REG(AFMT_CNTL)(enc110->regs->AFMT_CNTL))
756 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_CNTL), 1, enc110->se_shift->AFMT_AUDIO_CLOCK_EN, enc110
->se_mask->AFMT_AUDIO_CLOCK_EN, 1);
757
758 REG_WRITE(AFMT_AVI_INFO0, content[0])dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_AVI_INFO0
), content[0], __func__);
759
760 REG_WRITE(AFMT_AVI_INFO1, content[1])dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_AVI_INFO1
), content[1], __func__);
761
762 REG_WRITE(AFMT_AVI_INFO2, content[2])dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_AVI_INFO2
), content[2], __func__);
763
764 REG_WRITE(AFMT_AVI_INFO3, content[3])dm_write_reg_func(enc110->base.ctx, (enc110->regs->AFMT_AVI_INFO3
), content[3], __func__);
765
766 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AVI_INFO3), 1, enc110->se_shift->AFMT_AVI_INFO_VERSION
, enc110->se_mask->AFMT_AVI_INFO_VERSION, info_frame->
avi.hb1)
767 info_frame->avi.hb1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AVI_INFO3), 1, enc110->se_shift->AFMT_AVI_INFO_VERSION
, enc110->se_mask->AFMT_AVI_INFO_VERSION, info_frame->
avi.hb1);
768
769 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL0), 2, enc110->se_shift->HDMI_AVI_INFO_SEND
, enc110->se_mask->HDMI_AVI_INFO_SEND, 1, enc110->se_shift
->HDMI_AVI_INFO_CONT, enc110->se_mask->HDMI_AVI_INFO_CONT
, 1)
770 HDMI_AVI_INFO_SEND, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL0), 2, enc110->se_shift->HDMI_AVI_INFO_SEND
, enc110->se_mask->HDMI_AVI_INFO_SEND, 1, enc110->se_shift
->HDMI_AVI_INFO_CONT, enc110->se_mask->HDMI_AVI_INFO_CONT
, 1)
771 HDMI_AVI_INFO_CONT, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL0), 2, enc110->se_shift->HDMI_AVI_INFO_SEND
, enc110->se_mask->HDMI_AVI_INFO_SEND, 1, enc110->se_shift
->HDMI_AVI_INFO_CONT, enc110->se_mask->HDMI_AVI_INFO_CONT
, 1);
772
773 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL1), 1, enc110->se_shift->HDMI_AVI_INFO_LINE
, enc110->se_mask->HDMI_AVI_INFO_LINE, 0 + 2)
774 VBI_LINE_0 + 2)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL1), 1, enc110->se_shift->HDMI_AVI_INFO_LINE
, enc110->se_mask->HDMI_AVI_INFO_LINE, 0 + 2);
775
776 } else {
777 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL0), 2, enc110->se_shift->HDMI_AVI_INFO_SEND
, enc110->se_mask->HDMI_AVI_INFO_SEND, 0, enc110->se_shift
->HDMI_AVI_INFO_CONT, enc110->se_mask->HDMI_AVI_INFO_CONT
, 0)
778 HDMI_AVI_INFO_SEND, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL0), 2, enc110->se_shift->HDMI_AVI_INFO_SEND
, enc110->se_mask->HDMI_AVI_INFO_SEND, 0, enc110->se_shift
->HDMI_AVI_INFO_CONT, enc110->se_mask->HDMI_AVI_INFO_CONT
, 0)
779 HDMI_AVI_INFO_CONT, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_INFOFRAME_CONTROL0), 2, enc110->se_shift->HDMI_AVI_INFO_SEND
, enc110->se_mask->HDMI_AVI_INFO_SEND, 0, enc110->se_shift
->HDMI_AVI_INFO_CONT, enc110->se_mask->HDMI_AVI_INFO_CONT
, 0);
780 }
781 }
782
783 if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
784 enc110->se_mask->HDMI_AVI_INFO_SEND) {
785 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
786 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
787 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
788 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
789 }
790
791#if defined(CONFIG_DRM_AMD_DC_DCN1)
792 if (enc110->se_mask->HDMI_DB_DISABLE) {
793 /* for bring up, disable dp double TODO */
794 if (REG(HDMI_DB_CONTROL)(enc110->regs->HDMI_DB_CONTROL))
795 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_DB_CONTROL), 1, enc110->se_shift->HDMI_DB_DISABLE,
enc110->se_mask->HDMI_DB_DISABLE, 1);
796
797 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
798 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
799 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
800 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
801 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
802 }
803#endif
804}
805
806static void dce110_stream_encoder_stop_hdmi_info_packets(
807 struct stream_encoder *enc)
808{
809 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
810
811 /* stop generic packets 0 & 1 on HDMI */
812 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 0, 6, enc110->se_shift->
HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0, enc110->se_shift
->HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0)
813 HDMI_GENERIC1_CONT, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 0, 6, enc110->se_shift->
HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0, enc110->se_shift
->HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0)
814 HDMI_GENERIC1_LINE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 0, 6, enc110->se_shift->
HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0, enc110->se_shift
->HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0)
815 HDMI_GENERIC1_SEND, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 0, 6, enc110->se_shift->
HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0, enc110->se_shift
->HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0)
816 HDMI_GENERIC0_CONT, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 0, 6, enc110->se_shift->
HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0, enc110->se_shift
->HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0)
817 HDMI_GENERIC0_LINE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 0, 6, enc110->se_shift->
HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0, enc110->se_shift
->HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0)
818 HDMI_GENERIC0_SEND, 0)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL0), 0, 6, enc110->se_shift->
HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0, enc110->se_shift
->HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0);
819
820 /* stop generic packets 2 & 3 on HDMI */
821 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
822 HDMI_GENERIC0_CONT, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
823 HDMI_GENERIC0_LINE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
824 HDMI_GENERIC0_SEND, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
825 HDMI_GENERIC1_CONT, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
826 HDMI_GENERIC1_LINE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
827 HDMI_GENERIC1_SEND, 0)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL1), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0);
828
829#if defined(CONFIG_DRM_AMD_DC_DCN1)
830 /* stop generic packets 2 & 3 on HDMI */
831 if (REG(HDMI_GENERIC_PACKET_CONTROL2)(enc110->regs->HDMI_GENERIC_PACKET_CONTROL2))
832 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
833 HDMI_GENERIC0_CONT, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
834 HDMI_GENERIC0_LINE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
835 HDMI_GENERIC0_SEND, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
836 HDMI_GENERIC1_CONT, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
837 HDMI_GENERIC1_LINE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
838 HDMI_GENERIC1_SEND, 0)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL2), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0);
839
840 if (REG(HDMI_GENERIC_PACKET_CONTROL3)(enc110->regs->HDMI_GENERIC_PACKET_CONTROL3))
841 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
842 HDMI_GENERIC0_CONT, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
843 HDMI_GENERIC0_LINE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
844 HDMI_GENERIC0_SEND, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
845 HDMI_GENERIC1_CONT, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
846 HDMI_GENERIC1_LINE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0)
847 HDMI_GENERIC1_SEND, 0)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
HDMI_GENERIC_PACKET_CONTROL3), 0, 6, enc110->se_shift->
HDMI_GENERIC0_CONT, enc110->se_mask->HDMI_GENERIC0_CONT
, 0, enc110->se_shift->HDMI_GENERIC0_LINE, enc110->se_mask
->HDMI_GENERIC0_LINE, 0, enc110->se_shift->HDMI_GENERIC0_SEND
, enc110->se_mask->HDMI_GENERIC0_SEND, 0, enc110->se_shift
->HDMI_GENERIC1_CONT, enc110->se_mask->HDMI_GENERIC1_CONT
, 0, enc110->se_shift->HDMI_GENERIC1_LINE, enc110->se_mask
->HDMI_GENERIC1_LINE, 0, enc110->se_shift->HDMI_GENERIC1_SEND
, enc110->se_mask->HDMI_GENERIC1_SEND, 0);
848#endif
849}
850
851static void dce110_stream_encoder_update_dp_info_packets(
852 struct stream_encoder *enc,
853 const struct encoder_info_frame *info_frame)
854{
855 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
856 uint32_t value = 0;
857
858 if (info_frame->vsc.valid)
859 dce110_update_generic_info_packet(
860 enc110,
861 0, /* packetIndex */
862 &info_frame->vsc);
863
864 if (info_frame->spd.valid)
865 dce110_update_generic_info_packet(
866 enc110,
867 2, /* packetIndex */
868 &info_frame->spd);
869
870 if (info_frame->hdrsmd.valid)
871 dce110_update_generic_info_packet(
872 enc110,
873 3, /* packetIndex */
874 &info_frame->hdrsmd);
875
876 /* enable/disable transmission of packet(s).
877 * If enabled, packet transmission begins on the next frame
878 */
879 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 1, enc110->se_shift->DP_SEC_GSP0_ENABLE, enc110
->se_mask->DP_SEC_GSP0_ENABLE, info_frame->vsc.valid
);
880 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 1, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110
->se_mask->DP_SEC_GSP2_ENABLE, info_frame->spd.valid
);
881 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 1, enc110->se_shift->DP_SEC_GSP3_ENABLE, enc110
->se_mask->DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid
);
882
883 /* This bit is the master enable bit.
884 * When enabling secondary stream engine,
885 * this master bit must also be set.
886 * This register shared with audio info frame.
887 * Therefore we need to enable master bit
888 * if at least on of the fields is not 0
889 */
890 value = REG_READ(DP_SEC_CNTL)dm_read_reg_func(enc110->base.ctx, (enc110->regs->DP_SEC_CNTL
), __func__);
891 if (value)
892 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 1, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 1);
893}
894
895static void dce110_stream_encoder_stop_dp_info_packets(
896 struct stream_encoder *enc)
897{
898 /* stop generic packets on DP */
899 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
900 uint32_t value = 0;
901
902 if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
903 REG_SET_7(DP_SEC_CNTL, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 0, 7, enc110->se_shift->DP_SEC_GSP0_ENABLE
, enc110->se_mask->DP_SEC_GSP0_ENABLE, 0, enc110->se_shift
->DP_SEC_GSP1_ENABLE, enc110->se_mask->DP_SEC_GSP1_ENABLE
, 0, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110->se_mask
->DP_SEC_GSP2_ENABLE, 0, enc110->se_shift->DP_SEC_GSP3_ENABLE
, enc110->se_mask->DP_SEC_GSP3_ENABLE, 0, enc110->se_shift
->DP_SEC_AVI_ENABLE, enc110->se_mask->DP_SEC_AVI_ENABLE
, 0, enc110->se_shift->DP_SEC_MPG_ENABLE, enc110->se_mask
->DP_SEC_MPG_ENABLE, 0, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 0)
904 DP_SEC_GSP0_ENABLE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 0, 7, enc110->se_shift->DP_SEC_GSP0_ENABLE
, enc110->se_mask->DP_SEC_GSP0_ENABLE, 0, enc110->se_shift
->DP_SEC_GSP1_ENABLE, enc110->se_mask->DP_SEC_GSP1_ENABLE
, 0, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110->se_mask
->DP_SEC_GSP2_ENABLE, 0, enc110->se_shift->DP_SEC_GSP3_ENABLE
, enc110->se_mask->DP_SEC_GSP3_ENABLE, 0, enc110->se_shift
->DP_SEC_AVI_ENABLE, enc110->se_mask->DP_SEC_AVI_ENABLE
, 0, enc110->se_shift->DP_SEC_MPG_ENABLE, enc110->se_mask
->DP_SEC_MPG_ENABLE, 0, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 0)
905 DP_SEC_GSP1_ENABLE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 0, 7, enc110->se_shift->DP_SEC_GSP0_ENABLE
, enc110->se_mask->DP_SEC_GSP0_ENABLE, 0, enc110->se_shift
->DP_SEC_GSP1_ENABLE, enc110->se_mask->DP_SEC_GSP1_ENABLE
, 0, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110->se_mask
->DP_SEC_GSP2_ENABLE, 0, enc110->se_shift->DP_SEC_GSP3_ENABLE
, enc110->se_mask->DP_SEC_GSP3_ENABLE, 0, enc110->se_shift
->DP_SEC_AVI_ENABLE, enc110->se_mask->DP_SEC_AVI_ENABLE
, 0, enc110->se_shift->DP_SEC_MPG_ENABLE, enc110->se_mask
->DP_SEC_MPG_ENABLE, 0, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 0)
906 DP_SEC_GSP2_ENABLE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 0, 7, enc110->se_shift->DP_SEC_GSP0_ENABLE
, enc110->se_mask->DP_SEC_GSP0_ENABLE, 0, enc110->se_shift
->DP_SEC_GSP1_ENABLE, enc110->se_mask->DP_SEC_GSP1_ENABLE
, 0, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110->se_mask
->DP_SEC_GSP2_ENABLE, 0, enc110->se_shift->DP_SEC_GSP3_ENABLE
, enc110->se_mask->DP_SEC_GSP3_ENABLE, 0, enc110->se_shift
->DP_SEC_AVI_ENABLE, enc110->se_mask->DP_SEC_AVI_ENABLE
, 0, enc110->se_shift->DP_SEC_MPG_ENABLE, enc110->se_mask
->DP_SEC_MPG_ENABLE, 0, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 0)
907 DP_SEC_GSP3_ENABLE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 0, 7, enc110->se_shift->DP_SEC_GSP0_ENABLE
, enc110->se_mask->DP_SEC_GSP0_ENABLE, 0, enc110->se_shift
->DP_SEC_GSP1_ENABLE, enc110->se_mask->DP_SEC_GSP1_ENABLE
, 0, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110->se_mask
->DP_SEC_GSP2_ENABLE, 0, enc110->se_shift->DP_SEC_GSP3_ENABLE
, enc110->se_mask->DP_SEC_GSP3_ENABLE, 0, enc110->se_shift
->DP_SEC_AVI_ENABLE, enc110->se_mask->DP_SEC_AVI_ENABLE
, 0, enc110->se_shift->DP_SEC_MPG_ENABLE, enc110->se_mask
->DP_SEC_MPG_ENABLE, 0, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 0)
908 DP_SEC_AVI_ENABLE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 0, 7, enc110->se_shift->DP_SEC_GSP0_ENABLE
, enc110->se_mask->DP_SEC_GSP0_ENABLE, 0, enc110->se_shift
->DP_SEC_GSP1_ENABLE, enc110->se_mask->DP_SEC_GSP1_ENABLE
, 0, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110->se_mask
->DP_SEC_GSP2_ENABLE, 0, enc110->se_shift->DP_SEC_GSP3_ENABLE
, enc110->se_mask->DP_SEC_GSP3_ENABLE, 0, enc110->se_shift
->DP_SEC_AVI_ENABLE, enc110->se_mask->DP_SEC_AVI_ENABLE
, 0, enc110->se_shift->DP_SEC_MPG_ENABLE, enc110->se_mask
->DP_SEC_MPG_ENABLE, 0, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 0)
909 DP_SEC_MPG_ENABLE, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 0, 7, enc110->se_shift->DP_SEC_GSP0_ENABLE
, enc110->se_mask->DP_SEC_GSP0_ENABLE, 0, enc110->se_shift
->DP_SEC_GSP1_ENABLE, enc110->se_mask->DP_SEC_GSP1_ENABLE
, 0, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110->se_mask
->DP_SEC_GSP2_ENABLE, 0, enc110->se_shift->DP_SEC_GSP3_ENABLE
, enc110->se_mask->DP_SEC_GSP3_ENABLE, 0, enc110->se_shift
->DP_SEC_AVI_ENABLE, enc110->se_mask->DP_SEC_AVI_ENABLE
, 0, enc110->se_shift->DP_SEC_MPG_ENABLE, enc110->se_mask
->DP_SEC_MPG_ENABLE, 0, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 0)
910 DP_SEC_STREAM_ENABLE, 0)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 0, 7, enc110->se_shift->DP_SEC_GSP0_ENABLE
, enc110->se_mask->DP_SEC_GSP0_ENABLE, 0, enc110->se_shift
->DP_SEC_GSP1_ENABLE, enc110->se_mask->DP_SEC_GSP1_ENABLE
, 0, enc110->se_shift->DP_SEC_GSP2_ENABLE, enc110->se_mask
->DP_SEC_GSP2_ENABLE, 0, enc110->se_shift->DP_SEC_GSP3_ENABLE
, enc110->se_mask->DP_SEC_GSP3_ENABLE, 0, enc110->se_shift
->DP_SEC_AVI_ENABLE, enc110->se_mask->DP_SEC_AVI_ENABLE
, 0, enc110->se_shift->DP_SEC_MPG_ENABLE, enc110->se_mask
->DP_SEC_MPG_ENABLE, 0, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 0);
911 }
912
913 /* this register shared with audio info frame.
914 * therefore we need to keep master enabled
915 * if at least one of the fields is not 0 */
916 value = REG_READ(DP_SEC_CNTL)dm_read_reg_func(enc110->base.ctx, (enc110->regs->DP_SEC_CNTL
), __func__);
917 if (value)
918 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 1, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 1);
919
920}
921
922static void dce110_stream_encoder_dp_blank(
923 struct stream_encoder *enc)
924{
925 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
926 uint32_t reg1 = 0;
927 uint32_t max_retries = DP_BLANK_MAX_RETRY20 * 10;
928
929 /* Note: For CZ, we are changing driver default to disable
930 * stream deferred to next VBLANK. If results are positive, we
931 * will make the same change to all DCE versions. There are a
932 * handful of panels that cannot handle disable stream at
933 * HBLANK and will result in a white line flash across the
934 * screen on stream disable. */
935 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1)generic_reg_get(enc110->base.ctx, (enc110->regs->DP_VID_STREAM_CNTL
), enc110->se_shift->DP_VID_STREAM_ENABLE, enc110->se_mask
->DP_VID_STREAM_ENABLE, &reg1);
936 if ((reg1 & 0x1) == 0)
937 /*stream not enabled*/
938 return;
939 /* Specify the video stream disable point
940 * (2 = start of the next vertical blank) */
941 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_STREAM_CNTL), 1, enc110->se_shift->DP_VID_STREAM_DIS_DEFER
, enc110->se_mask->DP_VID_STREAM_DIS_DEFER, 2);
942 /* Larger delay to wait until VBLANK - use max retry of
943 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
944 * a little more because we may not trust delay accuracy.
945 */
946 max_retries = DP_BLANK_MAX_RETRY20 * 150;
947
948 /* disable DP stream */
949 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_STREAM_CNTL), 1, enc110->se_shift->DP_VID_STREAM_ENABLE
, enc110->se_mask->DP_VID_STREAM_ENABLE, 0);
950
951 /* the encoder stops sending the video stream
952 * at the start of the vertical blanking.
953 * Poll for DP_VID_STREAM_STATUS == 0
954 */
955
956 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,generic_reg_wait(enc110->base.ctx, (enc110->regs->DP_VID_STREAM_CNTL
), enc110->se_shift->DP_VID_STREAM_STATUS, enc110->se_mask
->DP_VID_STREAM_STATUS, 0, 10, max_retries, __func__, 958)
957 0,generic_reg_wait(enc110->base.ctx, (enc110->regs->DP_VID_STREAM_CNTL
), enc110->se_shift->DP_VID_STREAM_STATUS, enc110->se_mask
->DP_VID_STREAM_STATUS, 0, 10, max_retries, __func__, 958)
958 10, max_retries)generic_reg_wait(enc110->base.ctx, (enc110->regs->DP_VID_STREAM_CNTL
), enc110->se_shift->DP_VID_STREAM_STATUS, enc110->se_mask
->DP_VID_STREAM_STATUS, 0, 10, max_retries, __func__, 958);
959
960 /* Tell the DP encoder to ignore timing from CRTC, must be done after
961 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
962 * complete, stream status will be stuck in video stream enabled state,
963 * i.e. DP_VID_STREAM_STATUS stuck at 1.
964 */
965
966 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_STEER_FIFO), 1, enc110->se_shift->DP_STEER_FIFO_RESET
, enc110->se_mask->DP_STEER_FIFO_RESET, 1);
967}
968
969/* output video stream to link encoder */
970static void dce110_stream_encoder_dp_unblank(
971 struct stream_encoder *enc,
972 const struct encoder_unblank_param *param)
973{
974 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
975
976 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
977 uint32_t n_vid = 0x8000;
978 uint32_t m_vid;
979
980 /* M / N = Fstream / Flink
981 * m_vid / n_vid = pixel rate / link rate
982 */
983
984 uint64_t m_vid_l = n_vid;
985
986 m_vid_l *= param->timing.pix_clk_100hz / 10;
987 m_vid_l = div_u64(m_vid_l,
988 param->link_settings.link_rate
989 * LINK_RATE_REF_FREQ_IN_KHZ);
990
991 m_vid = (uint32_t) m_vid_l;
992
993 /* enable auto measurement */
994
995 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_TIMING), 1, enc110->se_shift->DP_VID_M_N_GEN_EN,
enc110->se_mask->DP_VID_M_N_GEN_EN, 0);
996
997 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
998 * therefore program initial value for Mvid and Nvid
999 */
1000
1001 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_N), 1, enc110->se_shift->DP_VID_N, enc110->se_mask
->DP_VID_N, n_vid);
1002
1003 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_M), 1, enc110->se_shift->DP_VID_M, enc110->se_mask
->DP_VID_M, m_vid);
1004
1005 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_TIMING), 1, enc110->se_shift->DP_VID_M_N_GEN_EN,
enc110->se_mask->DP_VID_M_N_GEN_EN, 1);
1006 }
1007
1008 /* set DIG_START to 0x1 to resync FIFO */
1009
1010 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DIG_FE_CNTL), 1, enc110->se_shift->DIG_START, enc110->
se_mask->DIG_START, 1);
1011
1012 /* switch DP encoder to CRTC data */
1013
1014 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_STEER_FIFO), 1, enc110->se_shift->DP_STEER_FIFO_RESET
, enc110->se_mask->DP_STEER_FIFO_RESET, 0);
1015
1016 /* wait 100us for DIG/DP logic to prime
1017 * (i.e. a few video lines)
1018 */
1019 udelay(100);
1020
1021 /* the hardware would start sending video at the start of the next DP
1022 * frame (i.e. rising edge of the vblank).
1023 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1024 * register has no effect on enable transition! HW always guarantees
1025 * VID_STREAM enable at start of next frame, and this is not
1026 * programmable
1027 */
1028
1029 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_VID_STREAM_CNTL), 1, enc110->se_shift->DP_VID_STREAM_ENABLE
, enc110->se_mask->DP_VID_STREAM_ENABLE, 1);
1030}
1031
1032static void dce110_stream_encoder_set_avmute(
1033 struct stream_encoder *enc,
1034 bool_Bool enable)
1035{
1036 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1037 unsigned int value = enable ? 1 : 0;
1038
1039 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_GC), 1, enc110->se_shift->HDMI_GC_AVMUTE, enc110->
se_mask->HDMI_GC_AVMUTE, value);
1040}
1041
1042
1043static void dce110_reset_hdmi_stream_attribute(
1044 struct stream_encoder *enc)
1045{
1046 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1047 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
1048 REG_UPDATE_5(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
1049 HDMI_PACKET_GEN_VERSION, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
1050 HDMI_KEEPOUT_MODE, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
1051 HDMI_DEEP_COLOR_ENABLE, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
1052 HDMI_DATA_SCRAMBLE_EN, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0)
1053 HDMI_CLOCK_CHANNEL_RATE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 5, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0, enc110->se_shift->
HDMI_DATA_SCRAMBLE_EN, enc110->se_mask->HDMI_DATA_SCRAMBLE_EN
, 0, enc110->se_shift->HDMI_CLOCK_CHANNEL_RATE, enc110->
se_mask->HDMI_CLOCK_CHANNEL_RATE, 0);
1054 else
1055 REG_UPDATE_3(HDMI_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 3, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
1056 HDMI_PACKET_GEN_VERSION, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 3, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
1057 HDMI_KEEPOUT_MODE, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 3, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0)
1058 HDMI_DEEP_COLOR_ENABLE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_CONTROL), 3, enc110->se_shift->HDMI_PACKET_GEN_VERSION
, enc110->se_mask->HDMI_PACKET_GEN_VERSION, 1, enc110->
se_shift->HDMI_KEEPOUT_MODE, enc110->se_mask->HDMI_KEEPOUT_MODE
, 1, enc110->se_shift->HDMI_DEEP_COLOR_ENABLE, enc110->
se_mask->HDMI_DEEP_COLOR_ENABLE, 0);
1059}
1060
1061#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT0x8000 0x8000
1062#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC1 1
1063
1064#include "include/audio_types.h"
1065
1066/**
1067* speakersToChannels
1068*
1069* @brief
1070* translate speakers to channels
1071*
1072* FL - Front Left
1073* FR - Front Right
1074* RL - Rear Left
1075* RR - Rear Right
1076* RC - Rear Center
1077* FC - Front Center
1078* FLC - Front Left Center
1079* FRC - Front Right Center
1080* RLC - Rear Left Center
1081* RRC - Rear Right Center
1082* LFE - Low Freq Effect
1083*
1084* FC
1085* FLC FRC
1086* FL FR
1087*
1088* LFE
1089* ()
1090*
1091*
1092* RL RR
1093* RLC RRC
1094* RC
1095*
1096* ch 8 7 6 5 4 3 2 1
1097* 0b00000011 - - - - - - FR FL
1098* 0b00000111 - - - - - LFE FR FL
1099* 0b00001011 - - - - FC - FR FL
1100* 0b00001111 - - - - FC LFE FR FL
1101* 0b00010011 - - - RC - - FR FL
1102* 0b00010111 - - - RC - LFE FR FL
1103* 0b00011011 - - - RC FC - FR FL
1104* 0b00011111 - - - RC FC LFE FR FL
1105* 0b00110011 - - RR RL - - FR FL
1106* 0b00110111 - - RR RL - LFE FR FL
1107* 0b00111011 - - RR RL FC - FR FL
1108* 0b00111111 - - RR RL FC LFE FR FL
1109* 0b01110011 - RC RR RL - - FR FL
1110* 0b01110111 - RC RR RL - LFE FR FL
1111* 0b01111011 - RC RR RL FC - FR FL
1112* 0b01111111 - RC RR RL FC LFE FR FL
1113* 0b11110011 RRC RLC RR RL - - FR FL
1114* 0b11110111 RRC RLC RR RL - LFE FR FL
1115* 0b11111011 RRC RLC RR RL FC - FR FL
1116* 0b11111111 RRC RLC RR RL FC LFE FR FL
1117* 0b11000011 FRC FLC - - - - FR FL
1118* 0b11000111 FRC FLC - - - LFE FR FL
1119* 0b11001011 FRC FLC - - FC - FR FL
1120* 0b11001111 FRC FLC - - FC LFE FR FL
1121* 0b11010011 FRC FLC - RC - - FR FL
1122* 0b11010111 FRC FLC - RC - LFE FR FL
1123* 0b11011011 FRC FLC - RC FC - FR FL
1124* 0b11011111 FRC FLC - RC FC LFE FR FL
1125* 0b11110011 FRC FLC RR RL - - FR FL
1126* 0b11110111 FRC FLC RR RL - LFE FR FL
1127* 0b11111011 FRC FLC RR RL FC - FR FL
1128* 0b11111111 FRC FLC RR RL FC LFE FR FL
1129*
1130* @param
1131* speakers - speaker information as it comes from CEA audio block
1132*/
1133/* translate speakers to channels */
1134
1135union audio_cea_channels {
1136 uint8_t all;
1137 struct audio_cea_channels_bits {
1138 uint32_t FL:1;
1139 uint32_t FR:1;
1140 uint32_t LFE:1;
1141 uint32_t FC:1;
1142 uint32_t RL_RC:1;
1143 uint32_t RR:1;
1144 uint32_t RC_RLC_FLC:1;
1145 uint32_t RRC_FRC:1;
1146 } channels;
1147};
1148
1149/* 25.2MHz/1.001*/
1150/* 25.2MHz/1.001*/
1151/* 25.2MHz*/
1152/* 27MHz */
1153/* 27MHz*1.001*/
1154/* 27MHz*1.001*/
1155/* 54MHz*/
1156/* 54MHz*1.001*/
1157/* 74.25MHz/1.001*/
1158/* 74.25MHz*/
1159/* 148.5MHz/1.001*/
1160/* 148.5MHz*/
1161
1162static const struct audio_clock_info audio_clock_info_table[16] = {
1163 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1164 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1165 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1166 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1167 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1168 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1169 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1170 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1171 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1172 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1173 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1174 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1175 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1176 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1177 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1178 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1179};
1180
1181static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1182 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1183 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1184 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1185 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1186 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1187 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1188 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1189 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1190 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1191 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1192 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1193 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1194 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1195 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1196};
1197
1198static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1199 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1200 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1201 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1202 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1203 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1204 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1205 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1206 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1207 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1208 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1209 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1210 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1211 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1212 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1213
1214
1215};
1216
1217static union audio_cea_channels speakers_to_channels(
1218 struct audio_speaker_flags speaker_flags)
1219{
1220 union audio_cea_channels cea_channels = {0};
1221
1222 /* these are one to one */
1223 cea_channels.channels.FL = speaker_flags.FL_FR;
1224 cea_channels.channels.FR = speaker_flags.FL_FR;
1225 cea_channels.channels.LFE = speaker_flags.LFE;
1226 cea_channels.channels.FC = speaker_flags.FC;
1227
1228 /* if Rear Left and Right exist move RC speaker to channel 7
1229 * otherwise to channel 5
1230 */
1231 if (speaker_flags.RL_RR) {
1232 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1233 cea_channels.channels.RR = speaker_flags.RL_RR;
1234 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1235 } else {
1236 cea_channels.channels.RL_RC = speaker_flags.RC;
1237 }
1238
1239 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1240 if (speaker_flags.FLC_FRC) {
1241 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1242 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1243 } else {
1244 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1245 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1246 }
1247
1248 return cea_channels;
1249}
1250
1251static uint32_t calc_max_audio_packets_per_line(
1252 const struct audio_crtc_info *crtc_info)
1253{
1254 uint32_t max_packets_per_line;
1255
1256 max_packets_per_line =
1257 crtc_info->h_total - crtc_info->h_active;
1258
1259 if (crtc_info->pixel_repetition)
1260 max_packets_per_line *= crtc_info->pixel_repetition;
1261
1262 /* for other hdmi features */
1263 max_packets_per_line -= 58;
1264 /* for Control Period */
1265 max_packets_per_line -= 16;
1266 /* Number of Audio Packets per Line */
1267 max_packets_per_line /= 32;
1268
1269 return max_packets_per_line;
1270}
1271
1272static void get_audio_clock_info(
1273 enum dc_color_depth color_depth,
1274 uint32_t crtc_pixel_clock_100Hz,
1275 uint32_t actual_pixel_clock_100Hz,
1276 struct audio_clock_info *audio_clock_info)
1277{
1278 const struct audio_clock_info *clock_info;
1279 uint32_t index;
1280 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1281 uint32_t audio_array_size;
1282
1283 switch (color_depth) {
1284 case COLOR_DEPTH_161616:
1285 clock_info = audio_clock_info_table_48bpc;
1286 audio_array_size = ARRAY_SIZE((sizeof((audio_clock_info_table_48bpc)) / sizeof((audio_clock_info_table_48bpc
)[0]))
1287 audio_clock_info_table_48bpc)(sizeof((audio_clock_info_table_48bpc)) / sizeof((audio_clock_info_table_48bpc
)[0]));
1288 break;
1289 case COLOR_DEPTH_121212:
1290 clock_info = audio_clock_info_table_36bpc;
1291 audio_array_size = ARRAY_SIZE((sizeof((audio_clock_info_table_36bpc)) / sizeof((audio_clock_info_table_36bpc
)[0]))
1292 audio_clock_info_table_36bpc)(sizeof((audio_clock_info_table_36bpc)) / sizeof((audio_clock_info_table_36bpc
)[0]));
1293 break;
1294 default:
1295 clock_info = audio_clock_info_table;
1296 audio_array_size = ARRAY_SIZE((sizeof((audio_clock_info_table)) / sizeof((audio_clock_info_table
)[0]))
1297 audio_clock_info_table)(sizeof((audio_clock_info_table)) / sizeof((audio_clock_info_table
)[0]));
1298 break;
1299 }
1300
1301 if (clock_info != NULL((void *)0)) {
1302 /* search for exact pixel clock in table */
1303 for (index = 0; index < audio_array_size; index++) {
1304 if (clock_info[index].pixel_clock_in_10khz >
1305 crtc_pixel_clock_in_10khz)
1306 break; /* not match */
1307 else if (clock_info[index].pixel_clock_in_10khz ==
1308 crtc_pixel_clock_in_10khz) {
1309 /* match found */
1310 *audio_clock_info = clock_info[index];
1311 return;
1312 }
1313 }
1314 }
1315
1316 /* not found */
1317 if (actual_pixel_clock_100Hz == 0)
1318 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1319
1320 /* See HDMI spec the table entry under
1321 * pixel clock of "Other". */
1322 audio_clock_info->pixel_clock_in_10khz =
1323 actual_pixel_clock_100Hz / 100;
1324 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1325 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1326 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1327
1328 audio_clock_info->n_32khz = 4096;
1329 audio_clock_info->n_44khz = 6272;
1330 audio_clock_info->n_48khz = 6144;
1331}
1332
1333static void dce110_se_audio_setup(
1334 struct stream_encoder *enc,
1335 unsigned int az_inst,
1336 struct audio_info *audio_info)
1337{
1338 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1339
1340 uint32_t channels = 0;
1341
1342 ASSERT(audio_info)do { if (({ static int __warned; int __ret = !!(!(audio_info)
); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(audio_info)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_stream_encoder.c"
, 1342); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
1343 if (audio_info == NULL((void *)0))
1344 /* This should not happen.it does so we don't get BSOD*/
1345 return;
1346
1347 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1348
1349 /* setup the audio stream source select (audio -> dig mapping) */
1350 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_SRC_CONTROL), 0, 1, enc110->se_shift->AFMT_AUDIO_SRC_SELECT
, enc110->se_mask->AFMT_AUDIO_SRC_SELECT, az_inst);
1351
1352 /* Channel allocation */
1353 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL2), 1, enc110->se_shift->AFMT_AUDIO_CHANNEL_ENABLE
, enc110->se_mask->AFMT_AUDIO_CHANNEL_ENABLE, channels);
1354}
1355
1356static void dce110_se_setup_hdmi_audio(
1357 struct stream_encoder *enc,
1358 const struct audio_crtc_info *crtc_info)
1359{
1360 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1361
1362 struct audio_clock_info audio_clock_info = {0};
1363 uint32_t max_packets_per_line;
1364
1365 /* For now still do calculation, although this field is ignored when
1366 above HDMI_PACKET_GEN_VERSION set to 1 */
1367 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1368
1369 /* HDMI_AUDIO_PACKET_CONTROL */
1370 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_AUDIO_PACKET_CONTROL), 2, enc110->se_shift->HDMI_AUDIO_PACKETS_PER_LINE
, enc110->se_mask->HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line
, enc110->se_shift->HDMI_AUDIO_DELAY_EN, enc110->se_mask
->HDMI_AUDIO_DELAY_EN, 1)
1371 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_AUDIO_PACKET_CONTROL), 2, enc110->se_shift->HDMI_AUDIO_PACKETS_PER_LINE
, enc110->se_mask->HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line
, enc110->se_shift->HDMI_AUDIO_DELAY_EN, enc110->se_mask
->HDMI_AUDIO_DELAY_EN, 1)
1372 HDMI_AUDIO_DELAY_EN, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_AUDIO_PACKET_CONTROL), 2, enc110->se_shift->HDMI_AUDIO_PACKETS_PER_LINE
, enc110->se_mask->HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line
, enc110->se_shift->HDMI_AUDIO_DELAY_EN, enc110->se_mask
->HDMI_AUDIO_DELAY_EN, 1);
1373
1374 /* AFMT_AUDIO_PACKET_CONTROL */
1375 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL), 1, enc110->se_shift->AFMT_60958_CS_UPDATE
, enc110->se_mask->AFMT_60958_CS_UPDATE, 1);
1376
1377 /* AFMT_AUDIO_PACKET_CONTROL2 */
1378 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL2), 2, enc110->se_shift->AFMT_AUDIO_LAYOUT_OVRD
, enc110->se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc110->
se_shift->AFMT_60958_OSF_OVRD, enc110->se_mask->AFMT_60958_OSF_OVRD
, 0)
1379 AFMT_AUDIO_LAYOUT_OVRD, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL2), 2, enc110->se_shift->AFMT_AUDIO_LAYOUT_OVRD
, enc110->se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc110->
se_shift->AFMT_60958_OSF_OVRD, enc110->se_mask->AFMT_60958_OSF_OVRD
, 0)
1380 AFMT_60958_OSF_OVRD, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL2), 2, enc110->se_shift->AFMT_AUDIO_LAYOUT_OVRD
, enc110->se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc110->
se_shift->AFMT_60958_OSF_OVRD, enc110->se_mask->AFMT_60958_OSF_OVRD
, 0);
1381
1382 /* HDMI_ACR_PACKET_CONTROL */
1383 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_PACKET_CONTROL), 3, enc110->se_shift->HDMI_ACR_AUTO_SEND
, enc110->se_mask->HDMI_ACR_AUTO_SEND, 1, enc110->se_shift
->HDMI_ACR_SOURCE, enc110->se_mask->HDMI_ACR_SOURCE,
0, enc110->se_shift->HDMI_ACR_AUDIO_PRIORITY, enc110->
se_mask->HDMI_ACR_AUDIO_PRIORITY, 0)
1384 HDMI_ACR_AUTO_SEND, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_PACKET_CONTROL), 3, enc110->se_shift->HDMI_ACR_AUTO_SEND
, enc110->se_mask->HDMI_ACR_AUTO_SEND, 1, enc110->se_shift
->HDMI_ACR_SOURCE, enc110->se_mask->HDMI_ACR_SOURCE,
0, enc110->se_shift->HDMI_ACR_AUDIO_PRIORITY, enc110->
se_mask->HDMI_ACR_AUDIO_PRIORITY, 0)
1385 HDMI_ACR_SOURCE, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_PACKET_CONTROL), 3, enc110->se_shift->HDMI_ACR_AUTO_SEND
, enc110->se_mask->HDMI_ACR_AUTO_SEND, 1, enc110->se_shift
->HDMI_ACR_SOURCE, enc110->se_mask->HDMI_ACR_SOURCE,
0, enc110->se_shift->HDMI_ACR_AUDIO_PRIORITY, enc110->
se_mask->HDMI_ACR_AUDIO_PRIORITY, 0)
1386 HDMI_ACR_AUDIO_PRIORITY, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_PACKET_CONTROL), 3, enc110->se_shift->HDMI_ACR_AUTO_SEND
, enc110->se_mask->HDMI_ACR_AUTO_SEND, 1, enc110->se_shift
->HDMI_ACR_SOURCE, enc110->se_mask->HDMI_ACR_SOURCE,
0, enc110->se_shift->HDMI_ACR_AUDIO_PRIORITY, enc110->
se_mask->HDMI_ACR_AUDIO_PRIORITY, 0);
1387
1388 /* Program audio clock sample/regeneration parameters */
1389 get_audio_clock_info(crtc_info->color_depth,
1390 crtc_info->requested_pixel_clock_100Hz,
1391 crtc_info->calculated_pixel_clock_100Hz,
1392 &audio_clock_info);
1393 DC_LOG_HW_AUDIO(do { } while(0)
1394 "\n%s:Input::requested_pixel_clock_100Hz = %d" \do { } while(0)
1395 "calculated_pixel_clock_100Hz = %d \n", __func__, \do { } while(0)
1396 crtc_info->requested_pixel_clock_100Hz, \do { } while(0)
1397 crtc_info->calculated_pixel_clock_100Hz)do { } while(0);
1398
1399 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1400 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_32_0), 1, enc110->se_shift->HDMI_ACR_CTS_32, enc110
->se_mask->HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1401
1402 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1403 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_32_1), 1, enc110->se_shift->HDMI_ACR_N_32, enc110
->se_mask->HDMI_ACR_N_32, audio_clock_info.n_32khz);
1404
1405 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1406 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_44_0), 1, enc110->se_shift->HDMI_ACR_CTS_44, enc110
->se_mask->HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1407
1408 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1409 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_44_1), 1, enc110->se_shift->HDMI_ACR_N_44, enc110
->se_mask->HDMI_ACR_N_44, audio_clock_info.n_44khz);
1410
1411 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1412 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_48_0), 1, enc110->se_shift->HDMI_ACR_CTS_48, enc110
->se_mask->HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1413
1414 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1415 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
HDMI_ACR_48_1), 1, enc110->se_shift->HDMI_ACR_N_48, enc110
->se_mask->HDMI_ACR_N_48, audio_clock_info.n_48khz);
1416
1417 /* Video driver cannot know in advance which sample rate will
1418 be used by HD Audio driver
1419 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1420 programmed below in interruppt callback */
1421
1422 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1423 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1424 REG_UPDATE_2(AFMT_60958_0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_0), 2, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_L
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_L, 1, enc110
->se_shift->AFMT_60958_CS_CLOCK_ACCURACY, enc110->se_mask
->AFMT_60958_CS_CLOCK_ACCURACY, 0)
1425 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_0), 2, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_L
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_L, 1, enc110
->se_shift->AFMT_60958_CS_CLOCK_ACCURACY, enc110->se_mask
->AFMT_60958_CS_CLOCK_ACCURACY, 0)
1426 AFMT_60958_CS_CLOCK_ACCURACY, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_0), 2, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_L
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_L, 1, enc110
->se_shift->AFMT_60958_CS_CLOCK_ACCURACY, enc110->se_mask
->AFMT_60958_CS_CLOCK_ACCURACY, 0);
1427
1428 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1429 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_1), 1, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_R
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1430
1431 /*AFMT_60958_2 now keep this settings until
1432 * Programming guide comes out*/
1433 REG_UPDATE_6(AFMT_60958_2,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_2), 6, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc110
->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc110->
se_mask->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc110->se_shift
->AFMT_60958_CS_CHANNEL_NUMBER_4, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc110
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc110->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc110->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc110->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1434 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_2), 6, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc110
->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc110->
se_mask->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc110->se_shift
->AFMT_60958_CS_CHANNEL_NUMBER_4, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc110
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc110->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc110->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc110->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1435 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_2), 6, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc110
->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc110->
se_mask->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc110->se_shift
->AFMT_60958_CS_CHANNEL_NUMBER_4, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc110
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc110->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc110->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc110->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1436 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_2), 6, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc110
->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc110->
se_mask->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc110->se_shift
->AFMT_60958_CS_CHANNEL_NUMBER_4, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc110
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc110->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc110->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc110->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1437 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_2), 6, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc110
->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc110->
se_mask->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc110->se_shift
->AFMT_60958_CS_CHANNEL_NUMBER_4, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc110
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc110->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc110->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc110->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1438 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_2), 6, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc110
->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc110->
se_mask->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc110->se_shift
->AFMT_60958_CS_CHANNEL_NUMBER_4, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc110
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc110->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc110->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc110->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8)
1439 AFMT_60958_CS_CHANNEL_NUMBER_7, 8)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_2), 6, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_2
, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_2, 3, enc110
->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_3, enc110->
se_mask->AFMT_60958_CS_CHANNEL_NUMBER_3, 4, enc110->se_shift
->AFMT_60958_CS_CHANNEL_NUMBER_4, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_4
, 5, enc110->se_shift->AFMT_60958_CS_CHANNEL_NUMBER_5, enc110
->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_5, 6, enc110->
se_shift->AFMT_60958_CS_CHANNEL_NUMBER_6, enc110->se_mask
->AFMT_60958_CS_CHANNEL_NUMBER_6, 7, enc110->se_shift->
AFMT_60958_CS_CHANNEL_NUMBER_7, enc110->se_mask->AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1440}
1441
1442static void dce110_se_setup_dp_audio(
1443 struct stream_encoder *enc)
1444{
1445 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1446
1447 /* --- DP Audio packet configurations --- */
1448
1449 /* ATP Configuration */
1450 REG_SET(DP_SEC_AUD_N, 0,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_AUD_N), 0, 1, enc110->se_shift->DP_SEC_AUD_N, enc110
->se_mask->DP_SEC_AUD_N, 0x8000)
1451 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_AUD_N), 0, 1, enc110->se_shift->DP_SEC_AUD_N, enc110
->se_mask->DP_SEC_AUD_N, 0x8000);
1452
1453 /* Async/auto-calc timestamp mode */
1454 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_TIMESTAMP), 0, 1, enc110->se_shift->DP_SEC_TIMESTAMP_MODE
, enc110->se_mask->DP_SEC_TIMESTAMP_MODE, 1)
1455 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC)generic_reg_set_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_TIMESTAMP), 0, 1, enc110->se_shift->DP_SEC_TIMESTAMP_MODE
, enc110->se_mask->DP_SEC_TIMESTAMP_MODE, 1);
1456
1457 /* --- The following are the registers
1458 * copied from the SetupHDMI --- */
1459
1460 /* AFMT_AUDIO_PACKET_CONTROL */
1461 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL), 1, enc110->se_shift->AFMT_60958_CS_UPDATE
, enc110->se_mask->AFMT_60958_CS_UPDATE, 1);
1462
1463 /* AFMT_AUDIO_PACKET_CONTROL2 */
1464 /* Program the ATP and AIP next */
1465 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL2), 2, enc110->se_shift->AFMT_AUDIO_LAYOUT_OVRD
, enc110->se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc110->
se_shift->AFMT_60958_OSF_OVRD, enc110->se_mask->AFMT_60958_OSF_OVRD
, 0)
1466 AFMT_AUDIO_LAYOUT_OVRD, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL2), 2, enc110->se_shift->AFMT_AUDIO_LAYOUT_OVRD
, enc110->se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc110->
se_shift->AFMT_60958_OSF_OVRD, enc110->se_mask->AFMT_60958_OSF_OVRD
, 0)
1467 AFMT_60958_OSF_OVRD, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL2), 2, enc110->se_shift->AFMT_AUDIO_LAYOUT_OVRD
, enc110->se_mask->AFMT_AUDIO_LAYOUT_OVRD, 0, enc110->
se_shift->AFMT_60958_OSF_OVRD, enc110->se_mask->AFMT_60958_OSF_OVRD
, 0);
1468
1469 /* AFMT_INFOFRAME_CONTROL0 */
1470 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_INFOFRAME_CONTROL0), 1, enc110->se_shift->AFMT_AUDIO_INFO_UPDATE
, enc110->se_mask->AFMT_AUDIO_INFO_UPDATE, 1);
1471
1472 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1473 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_60958_0), 1, enc110->se_shift->AFMT_60958_CS_CLOCK_ACCURACY
, enc110->se_mask->AFMT_60958_CS_CLOCK_ACCURACY, 0);
1474}
1475
1476static void dce110_se_enable_audio_clock(
1477 struct stream_encoder *enc,
1478 bool_Bool enable)
1479{
1480 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1481
1482 if (REG(AFMT_CNTL)(enc110->regs->AFMT_CNTL) == 0)
1483 return; /* DCE8/10 does not have this register */
1484
1485 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_CNTL), 1, enc110->se_shift->AFMT_AUDIO_CLOCK_EN, enc110
->se_mask->AFMT_AUDIO_CLOCK_EN, !!enable);
1486
1487 /* wait for AFMT clock to turn on,
1488 * expectation: this should complete in 1-2 reads
1489 *
1490 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1491 *
1492 * TODO: wait for clock_on does not work well. May need HW
1493 * program sequence. But audio seems work normally even without wait
1494 * for clock_on status change
1495 */
1496}
1497
1498static void dce110_se_enable_dp_audio(
1499 struct stream_encoder *enc)
1500{
1501 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1502
1503 /* Enable Audio packets */
1504 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 1, enc110->se_shift->DP_SEC_ASP_ENABLE, enc110
->se_mask->DP_SEC_ASP_ENABLE, 1);
1505
1506 /* Program the ATP and AIP next */
1507 REG_UPDATE_2(DP_SEC_CNTL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 2, enc110->se_shift->DP_SEC_ATP_ENABLE, enc110
->se_mask->DP_SEC_ATP_ENABLE, 1, enc110->se_shift->
DP_SEC_AIP_ENABLE, enc110->se_mask->DP_SEC_AIP_ENABLE, 1
)
1508 DP_SEC_ATP_ENABLE, 1,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 2, enc110->se_shift->DP_SEC_ATP_ENABLE, enc110
->se_mask->DP_SEC_ATP_ENABLE, 1, enc110->se_shift->
DP_SEC_AIP_ENABLE, enc110->se_mask->DP_SEC_AIP_ENABLE, 1
)
1509 DP_SEC_AIP_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 2, enc110->se_shift->DP_SEC_ATP_ENABLE, enc110
->se_mask->DP_SEC_ATP_ENABLE, 1, enc110->se_shift->
DP_SEC_AIP_ENABLE, enc110->se_mask->DP_SEC_AIP_ENABLE, 1
);
1510
1511 /* Program STREAM_ENABLE after all the other enables. */
1512 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 1, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 1);
1513}
1514
1515static void dce110_se_disable_dp_audio(
1516 struct stream_encoder *enc)
1517{
1518 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1519 uint32_t value = 0;
1520
1521 /* Disable Audio packets */
1522 REG_UPDATE_5(DP_SEC_CNTL,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 5, enc110->se_shift->DP_SEC_ASP_ENABLE, enc110
->se_mask->DP_SEC_ASP_ENABLE, 0, enc110->se_shift->
DP_SEC_ATP_ENABLE, enc110->se_mask->DP_SEC_ATP_ENABLE, 0
, enc110->se_shift->DP_SEC_AIP_ENABLE, enc110->se_mask
->DP_SEC_AIP_ENABLE, 0, enc110->se_shift->DP_SEC_ACM_ENABLE
, enc110->se_mask->DP_SEC_ACM_ENABLE, 0, enc110->se_shift
->DP_SEC_STREAM_ENABLE, enc110->se_mask->DP_SEC_STREAM_ENABLE
, 0)
1523 DP_SEC_ASP_ENABLE, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 5, enc110->se_shift->DP_SEC_ASP_ENABLE, enc110
->se_mask->DP_SEC_ASP_ENABLE, 0, enc110->se_shift->
DP_SEC_ATP_ENABLE, enc110->se_mask->DP_SEC_ATP_ENABLE, 0
, enc110->se_shift->DP_SEC_AIP_ENABLE, enc110->se_mask
->DP_SEC_AIP_ENABLE, 0, enc110->se_shift->DP_SEC_ACM_ENABLE
, enc110->se_mask->DP_SEC_ACM_ENABLE, 0, enc110->se_shift
->DP_SEC_STREAM_ENABLE, enc110->se_mask->DP_SEC_STREAM_ENABLE
, 0)
1524 DP_SEC_ATP_ENABLE, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 5, enc110->se_shift->DP_SEC_ASP_ENABLE, enc110
->se_mask->DP_SEC_ASP_ENABLE, 0, enc110->se_shift->
DP_SEC_ATP_ENABLE, enc110->se_mask->DP_SEC_ATP_ENABLE, 0
, enc110->se_shift->DP_SEC_AIP_ENABLE, enc110->se_mask
->DP_SEC_AIP_ENABLE, 0, enc110->se_shift->DP_SEC_ACM_ENABLE
, enc110->se_mask->DP_SEC_ACM_ENABLE, 0, enc110->se_shift
->DP_SEC_STREAM_ENABLE, enc110->se_mask->DP_SEC_STREAM_ENABLE
, 0)
1525 DP_SEC_AIP_ENABLE, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 5, enc110->se_shift->DP_SEC_ASP_ENABLE, enc110
->se_mask->DP_SEC_ASP_ENABLE, 0, enc110->se_shift->
DP_SEC_ATP_ENABLE, enc110->se_mask->DP_SEC_ATP_ENABLE, 0
, enc110->se_shift->DP_SEC_AIP_ENABLE, enc110->se_mask
->DP_SEC_AIP_ENABLE, 0, enc110->se_shift->DP_SEC_ACM_ENABLE
, enc110->se_mask->DP_SEC_ACM_ENABLE, 0, enc110->se_shift
->DP_SEC_STREAM_ENABLE, enc110->se_mask->DP_SEC_STREAM_ENABLE
, 0)
1526 DP_SEC_ACM_ENABLE, 0,generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 5, enc110->se_shift->DP_SEC_ASP_ENABLE, enc110
->se_mask->DP_SEC_ASP_ENABLE, 0, enc110->se_shift->
DP_SEC_ATP_ENABLE, enc110->se_mask->DP_SEC_ATP_ENABLE, 0
, enc110->se_shift->DP_SEC_AIP_ENABLE, enc110->se_mask
->DP_SEC_AIP_ENABLE, 0, enc110->se_shift->DP_SEC_ACM_ENABLE
, enc110->se_mask->DP_SEC_ACM_ENABLE, 0, enc110->se_shift
->DP_SEC_STREAM_ENABLE, enc110->se_mask->DP_SEC_STREAM_ENABLE
, 0)
1527 DP_SEC_STREAM_ENABLE, 0)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 5, enc110->se_shift->DP_SEC_ASP_ENABLE, enc110
->se_mask->DP_SEC_ASP_ENABLE, 0, enc110->se_shift->
DP_SEC_ATP_ENABLE, enc110->se_mask->DP_SEC_ATP_ENABLE, 0
, enc110->se_shift->DP_SEC_AIP_ENABLE, enc110->se_mask
->DP_SEC_AIP_ENABLE, 0, enc110->se_shift->DP_SEC_ACM_ENABLE
, enc110->se_mask->DP_SEC_ACM_ENABLE, 0, enc110->se_shift
->DP_SEC_STREAM_ENABLE, enc110->se_mask->DP_SEC_STREAM_ENABLE
, 0);
1528
1529 /* This register shared with encoder info frame. Therefore we need to
1530 keep master enabled if at least on of the fields is not 0 */
1531 value = REG_READ(DP_SEC_CNTL)dm_read_reg_func(enc110->base.ctx, (enc110->regs->DP_SEC_CNTL
), __func__);
1532 if (value != 0)
1533 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DP_SEC_CNTL), 1, enc110->se_shift->DP_SEC_STREAM_ENABLE
, enc110->se_mask->DP_SEC_STREAM_ENABLE, 1);
1534
1535}
1536
1537void dce110_se_audio_mute_control(
1538 struct stream_encoder *enc,
1539 bool_Bool mute)
1540{
1541 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1542
1543 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
AFMT_AUDIO_PACKET_CONTROL), 1, enc110->se_shift->AFMT_AUDIO_SAMPLE_SEND
, enc110->se_mask->AFMT_AUDIO_SAMPLE_SEND, !mute);
1544}
1545
1546void dce110_se_dp_audio_setup(
1547 struct stream_encoder *enc,
1548 unsigned int az_inst,
1549 struct audio_info *info)
1550{
1551 dce110_se_audio_setup(enc, az_inst, info);
1552}
1553
1554void dce110_se_dp_audio_enable(
1555 struct stream_encoder *enc)
1556{
1557 dce110_se_enable_audio_clock(enc, true1);
1558 dce110_se_setup_dp_audio(enc);
1559 dce110_se_enable_dp_audio(enc);
1560}
1561
1562void dce110_se_dp_audio_disable(
1563 struct stream_encoder *enc)
1564{
1565 dce110_se_disable_dp_audio(enc);
1566 dce110_se_enable_audio_clock(enc, false0);
1567}
1568
1569void dce110_se_hdmi_audio_setup(
1570 struct stream_encoder *enc,
1571 unsigned int az_inst,
1572 struct audio_info *info,
1573 struct audio_crtc_info *audio_crtc_info)
1574{
1575 dce110_se_enable_audio_clock(enc, true1);
1576 dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1577 dce110_se_audio_setup(enc, az_inst, info);
1578}
1579
1580void dce110_se_hdmi_audio_disable(
1581 struct stream_encoder *enc)
1582{
1583 dce110_se_enable_audio_clock(enc, false0);
1584}
1585
1586
1587static void setup_stereo_sync(
1588 struct stream_encoder *enc,
1589 int tg_inst, bool_Bool enable)
1590{
1591 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1592 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DIG_FE_CNTL), 1, enc110->se_shift->DIG_STEREOSYNC_SELECT
, enc110->se_mask->DIG_STEREOSYNC_SELECT, tg_inst);
1593 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DIG_FE_CNTL), 1, enc110->se_shift->DIG_STEREOSYNC_GATE_EN
, enc110->se_mask->DIG_STEREOSYNC_GATE_EN, !enable);
1594}
1595
1596static void dig_connect_to_otg(
1597 struct stream_encoder *enc,
1598 int tg_inst)
1599{
1600 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1601
1602 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst)generic_reg_update_ex(enc110->base.ctx, (enc110->regs->
DIG_FE_CNTL), 1, enc110->se_shift->DIG_SOURCE_SELECT, enc110
->se_mask->DIG_SOURCE_SELECT, tg_inst);
1603}
1604
1605static unsigned int dig_source_otg(
1606 struct stream_encoder *enc)
1607{
1608 uint32_t tg_inst = 0;
1609 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc)({ const __typeof( ((struct dce110_stream_encoder *)0)->base
) *__mptr = (enc); (struct dce110_stream_encoder *)( (char *
)__mptr - __builtin_offsetof(struct dce110_stream_encoder, base
) );});
1610
1611 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst)generic_reg_get(enc110->base.ctx, (enc110->regs->DIG_FE_CNTL
), enc110->se_shift->DIG_SOURCE_SELECT, enc110->se_mask
->DIG_SOURCE_SELECT, &tg_inst);
1612
1613 return tg_inst;
1614}
1615
1616static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1617 .dp_set_stream_attribute =
1618 dce110_stream_encoder_dp_set_stream_attribute,
1619 .hdmi_set_stream_attribute =
1620 dce110_stream_encoder_hdmi_set_stream_attribute,
1621 .dvi_set_stream_attribute =
1622 dce110_stream_encoder_dvi_set_stream_attribute,
1623 .lvds_set_stream_attribute =
1624 dce110_stream_encoder_lvds_set_stream_attribute,
1625 .set_throttled_vcp_size =
1626 dce110_stream_encoder_set_throttled_vcp_size,
1627 .update_hdmi_info_packets =
1628 dce110_stream_encoder_update_hdmi_info_packets,
1629 .stop_hdmi_info_packets =
1630 dce110_stream_encoder_stop_hdmi_info_packets,
1631 .update_dp_info_packets =
1632 dce110_stream_encoder_update_dp_info_packets,
1633 .stop_dp_info_packets =
1634 dce110_stream_encoder_stop_dp_info_packets,
1635 .dp_blank =
1636 dce110_stream_encoder_dp_blank,
1637 .dp_unblank =
1638 dce110_stream_encoder_dp_unblank,
1639 .audio_mute_control = dce110_se_audio_mute_control,
1640
1641 .dp_audio_setup = dce110_se_dp_audio_setup,
1642 .dp_audio_enable = dce110_se_dp_audio_enable,
1643 .dp_audio_disable = dce110_se_dp_audio_disable,
1644
1645 .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1646 .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1647 .setup_stereo_sync = setup_stereo_sync,
1648 .set_avmute = dce110_stream_encoder_set_avmute,
1649 .dig_connect_to_otg = dig_connect_to_otg,
1650 .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
1651 .dig_source_otg = dig_source_otg,
1652};
1653
1654void dce110_stream_encoder_construct(
1655 struct dce110_stream_encoder *enc110,
1656 struct dc_context *ctx,
1657 struct dc_bios *bp,
1658 enum engine_id eng_id,
1659 const struct dce110_stream_enc_registers *regs,
1660 const struct dce_stream_encoder_shift *se_shift,
1661 const struct dce_stream_encoder_mask *se_mask)
1662{
1663 enc110->base.funcs = &dce110_str_enc_funcs;
1664 enc110->base.ctx = ctx;
1665 enc110->base.id = eng_id;
1666 enc110->base.bp = bp;
1667 enc110->regs = regs;
1668 enc110->se_shift = se_shift;
1669 enc110->se_mask = se_mask;
1670}