Bug Summary

File:dev/pci/drm/radeon/radeon_combios.c
Warning:line 2913, column 3
Value stored to 'rev' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name radeon_combios.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/radeon/radeon_combios.c
1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27
28#include <linux/pci.h>
29
30#include <drm/drm_device.h>
31#include <drm/radeon_drm.h>
32
33#include "radeon.h"
34#include "atom.h"
35
36#if defined(CONFIG_PPC_PMAC) && defined(__linux__)
37/* not sure which of these are needed */
38#include <asm/machdep.h>
39#include <asm/pmac_feature.h>
40#include <asm/prom.h>
41#elif defined(CONFIG_PPC_PMAC)
42#include <linux/of.h>
43#endif /* CONFIG_PPC_PMAC */
44
45/* from radeon_legacy_encoder.c */
46extern void
47radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
48 uint32_t supported_device);
49
50/* old legacy ATI BIOS routines */
51
52/* COMBIOS table offsets */
53enum radeon_combios_table_offset {
54 /* absolute offset tables */
55 COMBIOS_ASIC_INIT_1_TABLE,
56 COMBIOS_BIOS_SUPPORT_TABLE,
57 COMBIOS_DAC_PROGRAMMING_TABLE,
58 COMBIOS_MAX_COLOR_DEPTH_TABLE,
59 COMBIOS_CRTC_INFO_TABLE,
60 COMBIOS_PLL_INFO_TABLE,
61 COMBIOS_TV_INFO_TABLE,
62 COMBIOS_DFP_INFO_TABLE,
63 COMBIOS_HW_CONFIG_INFO_TABLE,
64 COMBIOS_MULTIMEDIA_INFO_TABLE,
65 COMBIOS_TV_STD_PATCH_TABLE,
66 COMBIOS_LCD_INFO_TABLE,
67 COMBIOS_MOBILE_INFO_TABLE,
68 COMBIOS_PLL_INIT_TABLE,
69 COMBIOS_MEM_CONFIG_TABLE,
70 COMBIOS_SAVE_MASK_TABLE,
71 COMBIOS_HARDCODED_EDID_TABLE,
72 COMBIOS_ASIC_INIT_2_TABLE,
73 COMBIOS_CONNECTOR_INFO_TABLE,
74 COMBIOS_DYN_CLK_1_TABLE,
75 COMBIOS_RESERVED_MEM_TABLE,
76 COMBIOS_EXT_TMDS_INFO_TABLE,
77 COMBIOS_MEM_CLK_INFO_TABLE,
78 COMBIOS_EXT_DAC_INFO_TABLE,
79 COMBIOS_MISC_INFO_TABLE,
80 COMBIOS_CRT_INFO_TABLE,
81 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
82 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
83 COMBIOS_FAN_SPEED_INFO_TABLE,
84 COMBIOS_OVERDRIVE_INFO_TABLE,
85 COMBIOS_OEM_INFO_TABLE,
86 COMBIOS_DYN_CLK_2_TABLE,
87 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
88 COMBIOS_I2C_INFO_TABLE,
89 /* relative offset tables */
90 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
91 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
92 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
93 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
94 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
95 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
96 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
97 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
98 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
99 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
100 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
101};
102
103enum radeon_combios_ddc {
104 DDC_NONE_DETECTED,
105 DDC_MONID,
106 DDC_DVI,
107 DDC_VGA,
108 DDC_CRT2,
109 DDC_LCD,
110 DDC_GPIO,
111};
112
113enum radeon_combios_connector {
114 CONNECTOR_NONE_LEGACY,
115 CONNECTOR_PROPRIETARY_LEGACY,
116 CONNECTOR_CRT_LEGACY,
117 CONNECTOR_DVI_I_LEGACY,
118 CONNECTOR_DVI_D_LEGACY,
119 CONNECTOR_CTV_LEGACY,
120 CONNECTOR_STV_LEGACY,
121 CONNECTOR_UNSUPPORTED_LEGACY
122};
123
124static const int legacy_connector_convert[] = {
125 DRM_MODE_CONNECTOR_Unknown0,
126 DRM_MODE_CONNECTOR_DVID3,
127 DRM_MODE_CONNECTOR_VGA1,
128 DRM_MODE_CONNECTOR_DVII2,
129 DRM_MODE_CONNECTOR_DVID3,
130 DRM_MODE_CONNECTOR_Composite5,
131 DRM_MODE_CONNECTOR_SVIDEO6,
132 DRM_MODE_CONNECTOR_Unknown0,
133};
134
135static uint16_t combios_get_table_offset(struct drm_device *dev,
136 enum radeon_combios_table_offset table)
137{
138 struct radeon_device *rdev = dev->dev_private;
139 int rev, size;
140 uint16_t offset = 0, check_offset;
141
142 if (!rdev->bios)
143 return 0;
144
145 switch (table) {
146 /* absolute offset tables */
147 case COMBIOS_ASIC_INIT_1_TABLE:
148 check_offset = 0xc;
149 break;
150 case COMBIOS_BIOS_SUPPORT_TABLE:
151 check_offset = 0x14;
152 break;
153 case COMBIOS_DAC_PROGRAMMING_TABLE:
154 check_offset = 0x2a;
155 break;
156 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
157 check_offset = 0x2c;
158 break;
159 case COMBIOS_CRTC_INFO_TABLE:
160 check_offset = 0x2e;
161 break;
162 case COMBIOS_PLL_INFO_TABLE:
163 check_offset = 0x30;
164 break;
165 case COMBIOS_TV_INFO_TABLE:
166 check_offset = 0x32;
167 break;
168 case COMBIOS_DFP_INFO_TABLE:
169 check_offset = 0x34;
170 break;
171 case COMBIOS_HW_CONFIG_INFO_TABLE:
172 check_offset = 0x36;
173 break;
174 case COMBIOS_MULTIMEDIA_INFO_TABLE:
175 check_offset = 0x38;
176 break;
177 case COMBIOS_TV_STD_PATCH_TABLE:
178 check_offset = 0x3e;
179 break;
180 case COMBIOS_LCD_INFO_TABLE:
181 check_offset = 0x40;
182 break;
183 case COMBIOS_MOBILE_INFO_TABLE:
184 check_offset = 0x42;
185 break;
186 case COMBIOS_PLL_INIT_TABLE:
187 check_offset = 0x46;
188 break;
189 case COMBIOS_MEM_CONFIG_TABLE:
190 check_offset = 0x48;
191 break;
192 case COMBIOS_SAVE_MASK_TABLE:
193 check_offset = 0x4a;
194 break;
195 case COMBIOS_HARDCODED_EDID_TABLE:
196 check_offset = 0x4c;
197 break;
198 case COMBIOS_ASIC_INIT_2_TABLE:
199 check_offset = 0x4e;
200 break;
201 case COMBIOS_CONNECTOR_INFO_TABLE:
202 check_offset = 0x50;
203 break;
204 case COMBIOS_DYN_CLK_1_TABLE:
205 check_offset = 0x52;
206 break;
207 case COMBIOS_RESERVED_MEM_TABLE:
208 check_offset = 0x54;
209 break;
210 case COMBIOS_EXT_TMDS_INFO_TABLE:
211 check_offset = 0x58;
212 break;
213 case COMBIOS_MEM_CLK_INFO_TABLE:
214 check_offset = 0x5a;
215 break;
216 case COMBIOS_EXT_DAC_INFO_TABLE:
217 check_offset = 0x5c;
218 break;
219 case COMBIOS_MISC_INFO_TABLE:
220 check_offset = 0x5e;
221 break;
222 case COMBIOS_CRT_INFO_TABLE:
223 check_offset = 0x60;
224 break;
225 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
226 check_offset = 0x62;
227 break;
228 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
229 check_offset = 0x64;
230 break;
231 case COMBIOS_FAN_SPEED_INFO_TABLE:
232 check_offset = 0x66;
233 break;
234 case COMBIOS_OVERDRIVE_INFO_TABLE:
235 check_offset = 0x68;
236 break;
237 case COMBIOS_OEM_INFO_TABLE:
238 check_offset = 0x6a;
239 break;
240 case COMBIOS_DYN_CLK_2_TABLE:
241 check_offset = 0x6c;
242 break;
243 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
244 check_offset = 0x6e;
245 break;
246 case COMBIOS_I2C_INFO_TABLE:
247 check_offset = 0x70;
248 break;
249 /* relative offset tables */
250 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
251 check_offset =
252 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
253 if (check_offset) {
254 rev = RBIOS8(check_offset)(rdev->bios[check_offset]);
255 if (rev > 0) {
256 check_offset = RBIOS16(check_offset + 0x3)((rdev->bios[check_offset + 0x3]) | ((rdev->bios[(check_offset
+ 0x3)+1]) << 8))
;
257 if (check_offset)
258 offset = check_offset;
259 }
260 }
261 break;
262 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
263 check_offset =
264 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
265 if (check_offset) {
266 rev = RBIOS8(check_offset)(rdev->bios[check_offset]);
267 if (rev > 0) {
268 check_offset = RBIOS16(check_offset + 0x5)((rdev->bios[check_offset + 0x5]) | ((rdev->bios[(check_offset
+ 0x5)+1]) << 8))
;
269 if (check_offset)
270 offset = check_offset;
271 }
272 }
273 break;
274 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
275 check_offset =
276 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
277 if (check_offset) {
278 rev = RBIOS8(check_offset)(rdev->bios[check_offset]);
279 if (rev > 0) {
280 check_offset = RBIOS16(check_offset + 0x7)((rdev->bios[check_offset + 0x7]) | ((rdev->bios[(check_offset
+ 0x7)+1]) << 8))
;
281 if (check_offset)
282 offset = check_offset;
283 }
284 }
285 break;
286 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
287 check_offset =
288 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
289 if (check_offset) {
290 rev = RBIOS8(check_offset)(rdev->bios[check_offset]);
291 if (rev == 2) {
292 check_offset = RBIOS16(check_offset + 0x9)((rdev->bios[check_offset + 0x9]) | ((rdev->bios[(check_offset
+ 0x9)+1]) << 8))
;
293 if (check_offset)
294 offset = check_offset;
295 }
296 }
297 break;
298 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
299 check_offset =
300 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
301 if (check_offset) {
302 while (RBIOS8(check_offset++)(rdev->bios[check_offset++]));
303 check_offset += 2;
304 if (check_offset)
305 offset = check_offset;
306 }
307 break;
308 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
309 check_offset =
310 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
311 if (check_offset) {
312 check_offset = RBIOS16(check_offset + 0x11)((rdev->bios[check_offset + 0x11]) | ((rdev->bios[(check_offset
+ 0x11)+1]) << 8))
;
313 if (check_offset)
314 offset = check_offset;
315 }
316 break;
317 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
318 check_offset =
319 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
320 if (check_offset) {
321 check_offset = RBIOS16(check_offset + 0x13)((rdev->bios[check_offset + 0x13]) | ((rdev->bios[(check_offset
+ 0x13)+1]) << 8))
;
322 if (check_offset)
323 offset = check_offset;
324 }
325 break;
326 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
327 check_offset =
328 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
329 if (check_offset) {
330 check_offset = RBIOS16(check_offset + 0x15)((rdev->bios[check_offset + 0x15]) | ((rdev->bios[(check_offset
+ 0x15)+1]) << 8))
;
331 if (check_offset)
332 offset = check_offset;
333 }
334 break;
335 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
336 check_offset =
337 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
338 if (check_offset) {
339 check_offset = RBIOS16(check_offset + 0x17)((rdev->bios[check_offset + 0x17]) | ((rdev->bios[(check_offset
+ 0x17)+1]) << 8))
;
340 if (check_offset)
341 offset = check_offset;
342 }
343 break;
344 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
345 check_offset =
346 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
347 if (check_offset) {
348 check_offset = RBIOS16(check_offset + 0x2)((rdev->bios[check_offset + 0x2]) | ((rdev->bios[(check_offset
+ 0x2)+1]) << 8))
;
349 if (check_offset)
350 offset = check_offset;
351 }
352 break;
353 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
356 if (check_offset) {
357 check_offset = RBIOS16(check_offset + 0x4)((rdev->bios[check_offset + 0x4]) | ((rdev->bios[(check_offset
+ 0x4)+1]) << 8))
;
358 if (check_offset)
359 offset = check_offset;
360 }
361 break;
362 default:
363 check_offset = 0;
364 break;
365 }
366
367 size = RBIOS8(rdev->bios_header_start + 0x6)(rdev->bios[rdev->bios_header_start + 0x6]);
368 /* check absolute offset tables */
369 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
370 offset = RBIOS16(rdev->bios_header_start + check_offset)((rdev->bios[rdev->bios_header_start + check_offset]) |
((rdev->bios[(rdev->bios_header_start + check_offset)+
1]) << 8))
;
371
372 return offset;
373}
374
375bool_Bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
376{
377 int edid_info, size;
378 struct edid *edid;
379 unsigned char *raw;
380 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
381 if (!edid_info)
382 return false0;
383
384 raw = rdev->bios + edid_info;
385 size = EDID_LENGTH128 * (raw[0x7e] + 1);
386 edid = kmalloc(size, GFP_KERNEL(0x0001 | 0x0004));
387 if (edid == NULL((void *)0))
388 return false0;
389
390 memcpy((unsigned char *)edid, raw, size)__builtin_memcpy(((unsigned char *)edid), (raw), (size));
391
392 if (!drm_edid_is_valid(edid)) {
393 kfree(edid);
394 return false0;
395 }
396
397 rdev->mode_info.bios_hardcoded_edid = edid;
398 rdev->mode_info.bios_hardcoded_edid_size = size;
399 return true1;
400}
401
402/* this is used for atom LCDs as well */
403struct edid *
404radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
405{
406 struct edid *edid;
407
408 if (rdev->mode_info.bios_hardcoded_edid) {
409 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL(0x0001 | 0x0004));
410 if (edid) {
411 memcpy((unsigned char *)edid,__builtin_memcpy(((unsigned char *)edid), ((unsigned char *)rdev
->mode_info.bios_hardcoded_edid), (rdev->mode_info.bios_hardcoded_edid_size
))
412 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,__builtin_memcpy(((unsigned char *)edid), ((unsigned char *)rdev
->mode_info.bios_hardcoded_edid), (rdev->mode_info.bios_hardcoded_edid_size
))
413 rdev->mode_info.bios_hardcoded_edid_size)__builtin_memcpy(((unsigned char *)edid), ((unsigned char *)rdev
->mode_info.bios_hardcoded_edid), (rdev->mode_info.bios_hardcoded_edid_size
))
;
414 return edid;
415 }
416 }
417 return NULL((void *)0);
418}
419
420#ifdef __clang__1
421static inline struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
422 enum radeon_combios_ddc ddc,
423 u32 clk_mask,
424 u32 data_mask)
425#else
426static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
427 enum radeon_combios_ddc ddc,
428 u32 clk_mask,
429 u32 data_mask)
430#endif
431{
432 struct radeon_i2c_bus_rec i2c;
433 int ddc_line = 0;
434
435 /* ddc id = mask reg
436 * DDC_NONE_DETECTED = none
437 * DDC_DVI = RADEON_GPIO_DVI_DDC
438 * DDC_VGA = RADEON_GPIO_VGA_DDC
439 * DDC_LCD = RADEON_GPIOPAD_MASK
440 * DDC_GPIO = RADEON_MDGPIO_MASK
441 * r1xx
442 * DDC_MONID = RADEON_GPIO_MONID
443 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
444 * r200
445 * DDC_MONID = RADEON_GPIO_MONID
446 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
447 * r300/r350
448 * DDC_MONID = RADEON_GPIO_DVI_DDC
449 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
450 * rv2xx/rv3xx
451 * DDC_MONID = RADEON_GPIO_MONID
452 * DDC_CRT2 = RADEON_GPIO_MONID
453 * rs3xx/rs4xx
454 * DDC_MONID = RADEON_GPIOPAD_MASK
455 * DDC_CRT2 = RADEON_GPIO_MONID
456 */
457 switch (ddc) {
458 case DDC_NONE_DETECTED:
459 default:
460 ddc_line = 0;
461 break;
462 case DDC_DVI:
463 ddc_line = RADEON_GPIO_DVI_DDC0x0064;
464 break;
465 case DDC_VGA:
466 ddc_line = RADEON_GPIO_VGA_DDC0x0060;
467 break;
468 case DDC_LCD:
469 ddc_line = RADEON_GPIOPAD_MASK0x0198;
470 break;
471 case DDC_GPIO:
472 ddc_line = RADEON_MDGPIO_MASK0x01a8;
473 break;
474 case DDC_MONID:
475 if (rdev->family == CHIP_RS300 ||
476 rdev->family == CHIP_RS400 ||
477 rdev->family == CHIP_RS480)
478 ddc_line = RADEON_GPIOPAD_MASK0x0198;
479 else if (rdev->family == CHIP_R300 ||
480 rdev->family == CHIP_R350) {
481 ddc_line = RADEON_GPIO_DVI_DDC0x0064;
482 ddc = DDC_DVI;
483 } else
484 ddc_line = RADEON_GPIO_MONID0x0068;
485 break;
486 case DDC_CRT2:
487 if (rdev->family == CHIP_R200 ||
488 rdev->family == CHIP_R300 ||
489 rdev->family == CHIP_R350) {
490 ddc_line = RADEON_GPIO_DVI_DDC0x0064;
491 ddc = DDC_DVI;
492 } else if (rdev->family == CHIP_RS300 ||
493 rdev->family == CHIP_RS400 ||
494 rdev->family == CHIP_RS480)
495 ddc_line = RADEON_GPIO_MONID0x0068;
496 else if (rdev->family >= CHIP_RV350) {
497 ddc_line = RADEON_GPIO_MONID0x0068;
498 ddc = DDC_MONID;
499 } else
500 ddc_line = RADEON_GPIO_CRT2_DDC0x006c;
501 break;
502 }
503
504 if (ddc_line == RADEON_GPIOPAD_MASK0x0198) {
505 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK0x0198;
506 i2c.mask_data_reg = RADEON_GPIOPAD_MASK0x0198;
507 i2c.a_clk_reg = RADEON_GPIOPAD_A0x019c;
508 i2c.a_data_reg = RADEON_GPIOPAD_A0x019c;
509 i2c.en_clk_reg = RADEON_GPIOPAD_EN0x01a0;
510 i2c.en_data_reg = RADEON_GPIOPAD_EN0x01a0;
511 i2c.y_clk_reg = RADEON_GPIOPAD_Y0x01a4;
512 i2c.y_data_reg = RADEON_GPIOPAD_Y0x01a4;
513 } else if (ddc_line == RADEON_MDGPIO_MASK0x01a8) {
514 i2c.mask_clk_reg = RADEON_MDGPIO_MASK0x01a8;
515 i2c.mask_data_reg = RADEON_MDGPIO_MASK0x01a8;
516 i2c.a_clk_reg = RADEON_MDGPIO_A0x01ac;
517 i2c.a_data_reg = RADEON_MDGPIO_A0x01ac;
518 i2c.en_clk_reg = RADEON_MDGPIO_EN0x01b0;
519 i2c.en_data_reg = RADEON_MDGPIO_EN0x01b0;
520 i2c.y_clk_reg = RADEON_MDGPIO_Y0x01b4;
521 i2c.y_data_reg = RADEON_MDGPIO_Y0x01b4;
522 } else {
523 i2c.mask_clk_reg = ddc_line;
524 i2c.mask_data_reg = ddc_line;
525 i2c.a_clk_reg = ddc_line;
526 i2c.a_data_reg = ddc_line;
527 i2c.en_clk_reg = ddc_line;
528 i2c.en_data_reg = ddc_line;
529 i2c.y_clk_reg = ddc_line;
530 i2c.y_data_reg = ddc_line;
531 }
532
533 if (clk_mask && data_mask) {
534 /* system specific masks */
535 i2c.mask_clk_mask = clk_mask;
536 i2c.mask_data_mask = data_mask;
537 i2c.a_clk_mask = clk_mask;
538 i2c.a_data_mask = data_mask;
539 i2c.en_clk_mask = clk_mask;
540 i2c.en_data_mask = data_mask;
541 i2c.y_clk_mask = clk_mask;
542 i2c.y_data_mask = data_mask;
543 } else if ((ddc_line == RADEON_GPIOPAD_MASK0x0198) ||
544 (ddc_line == RADEON_MDGPIO_MASK0x01a8)) {
545 /* default gpiopad masks */
546 i2c.mask_clk_mask = (0x20 << 8);
547 i2c.mask_data_mask = 0x80;
548 i2c.a_clk_mask = (0x20 << 8);
549 i2c.a_data_mask = 0x80;
550 i2c.en_clk_mask = (0x20 << 8);
551 i2c.en_data_mask = 0x80;
552 i2c.y_clk_mask = (0x20 << 8);
553 i2c.y_data_mask = 0x80;
554 } else {
555 /* default masks for ddc pads */
556 i2c.mask_clk_mask = RADEON_GPIO_MASK_1(1 << 25);
557 i2c.mask_data_mask = RADEON_GPIO_MASK_0(1 << 24);
558 i2c.a_clk_mask = RADEON_GPIO_A_1(1 << 1);
559 i2c.a_data_mask = RADEON_GPIO_A_0(1 << 0);
560 i2c.en_clk_mask = RADEON_GPIO_EN_1(1 << 17);
561 i2c.en_data_mask = RADEON_GPIO_EN_0(1 << 16);
562 i2c.y_clk_mask = RADEON_GPIO_Y_1(1 << 9);
563 i2c.y_data_mask = RADEON_GPIO_Y_0(1 << 8);
564 }
565
566 switch (rdev->family) {
567 case CHIP_R100:
568 case CHIP_RV100:
569 case CHIP_RS100:
570 case CHIP_RV200:
571 case CHIP_RS200:
572 case CHIP_RS300:
573 switch (ddc_line) {
574 case RADEON_GPIO_DVI_DDC0x0064:
575 i2c.hw_capable = true1;
576 break;
577 default:
578 i2c.hw_capable = false0;
579 break;
580 }
581 break;
582 case CHIP_R200:
583 switch (ddc_line) {
584 case RADEON_GPIO_DVI_DDC0x0064:
585 case RADEON_GPIO_MONID0x0068:
586 i2c.hw_capable = true1;
587 break;
588 default:
589 i2c.hw_capable = false0;
590 break;
591 }
592 break;
593 case CHIP_RV250:
594 case CHIP_RV280:
595 switch (ddc_line) {
596 case RADEON_GPIO_VGA_DDC0x0060:
597 case RADEON_GPIO_DVI_DDC0x0064:
598 case RADEON_GPIO_CRT2_DDC0x006c:
599 i2c.hw_capable = true1;
600 break;
601 default:
602 i2c.hw_capable = false0;
603 break;
604 }
605 break;
606 case CHIP_R300:
607 case CHIP_R350:
608 switch (ddc_line) {
609 case RADEON_GPIO_VGA_DDC0x0060:
610 case RADEON_GPIO_DVI_DDC0x0064:
611 i2c.hw_capable = true1;
612 break;
613 default:
614 i2c.hw_capable = false0;
615 break;
616 }
617 break;
618 case CHIP_RV350:
619 case CHIP_RV380:
620 case CHIP_RS400:
621 case CHIP_RS480:
622 switch (ddc_line) {
623 case RADEON_GPIO_VGA_DDC0x0060:
624 case RADEON_GPIO_DVI_DDC0x0064:
625 i2c.hw_capable = true1;
626 break;
627 case RADEON_GPIO_MONID0x0068:
628 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
629 * reliably on some pre-r4xx hardware; not sure why.
630 */
631 i2c.hw_capable = false0;
632 break;
633 default:
634 i2c.hw_capable = false0;
635 break;
636 }
637 break;
638 default:
639 i2c.hw_capable = false0;
640 break;
641 }
642 i2c.mm_i2c = false0;
643
644 i2c.i2c_id = ddc;
645 i2c.hpd = RADEON_HPD_NONE;
646
647 if (ddc_line)
648 i2c.valid = true1;
649 else
650 i2c.valid = false0;
651
652 return i2c;
653}
654
655static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
656{
657 struct drm_device *dev = rdev->ddev;
658 struct radeon_i2c_bus_rec i2c;
659 u16 offset;
660 u8 id, blocks, clk, data;
661 int i;
662
663 i2c.valid = false0;
664
665 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
666 if (offset) {
667 blocks = RBIOS8(offset + 2)(rdev->bios[offset + 2]);
668 for (i = 0; i < blocks; i++) {
669 id = RBIOS8(offset + 3 + (i * 5) + 0)(rdev->bios[offset + 3 + (i * 5) + 0]);
670 if (id == 136) {
671 clk = RBIOS8(offset + 3 + (i * 5) + 3)(rdev->bios[offset + 3 + (i * 5) + 3]);
672 data = RBIOS8(offset + 3 + (i * 5) + 4)(rdev->bios[offset + 3 + (i * 5) + 4]);
673 /* gpiopad */
674 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
675 (1 << clk), (1 << data));
676 break;
677 }
678 }
679 }
680 return i2c;
681}
682
683void radeon_combios_i2c_init(struct radeon_device *rdev)
684{
685 struct drm_device *dev = rdev->ddev;
686 struct radeon_i2c_bus_rec i2c;
687
688 /* actual hw pads
689 * r1xx/rs2xx/rs3xx
690 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
691 * r200
692 * 0x60, 0x64, 0x68, mm
693 * r300/r350
694 * 0x60, 0x64, mm
695 * rv2xx/rv3xx/rs4xx
696 * 0x60, 0x64, 0x68, gpiopads, mm
697 */
698
699 /* 0x60 */
700 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
701 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
702 /* 0x64 */
703 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
704 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
705
706 /* mm i2c */
707 i2c.valid = true1;
708 i2c.hw_capable = true1;
709 i2c.mm_i2c = true1;
710 i2c.i2c_id = 0xa0;
711 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
712
713 if (rdev->family == CHIP_R300 ||
714 rdev->family == CHIP_R350) {
715 /* only 2 sw i2c pads */
716 } else if (rdev->family == CHIP_RS300 ||
717 rdev->family == CHIP_RS400 ||
718 rdev->family == CHIP_RS480) {
719 /* 0x68 */
720 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
721 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
722
723 /* gpiopad */
724 i2c = radeon_combios_get_i2c_info_from_table(rdev);
725 if (i2c.valid)
726 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
727 } else if ((rdev->family == CHIP_R200) ||
728 (rdev->family >= CHIP_R300)) {
729 /* 0x68 */
730 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
731 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
732 } else {
733 /* 0x68 */
734 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
735 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
736 /* 0x6c */
737 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
738 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
739 }
740}
741
742bool_Bool radeon_combios_get_clock_info(struct drm_device *dev)
743{
744 struct radeon_device *rdev = dev->dev_private;
745 uint16_t pll_info;
746 struct radeon_pll *p1pll = &rdev->clock.p1pll;
747 struct radeon_pll *p2pll = &rdev->clock.p2pll;
748 struct radeon_pll *spll = &rdev->clock.spll;
749 struct radeon_pll *mpll = &rdev->clock.mpll;
750 int8_t rev;
751 uint16_t sclk, mclk;
752
753 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
754 if (pll_info) {
755 rev = RBIOS8(pll_info)(rdev->bios[pll_info]);
756
757 /* pixel clocks */
758 p1pll->reference_freq = RBIOS16(pll_info + 0xe)((rdev->bios[pll_info + 0xe]) | ((rdev->bios[(pll_info +
0xe)+1]) << 8))
;
759 p1pll->reference_div = RBIOS16(pll_info + 0x10)((rdev->bios[pll_info + 0x10]) | ((rdev->bios[(pll_info
+ 0x10)+1]) << 8))
;
760 p1pll->pll_out_min = RBIOS32(pll_info + 0x12)((((rdev->bios[pll_info + 0x12]) | ((rdev->bios[(pll_info
+ 0x12)+1]) << 8))) | (((rdev->bios[(pll_info + 0x12
)+2]) | ((rdev->bios[((pll_info + 0x12)+2)+1]) << 8)
) << 16))
;
761 p1pll->pll_out_max = RBIOS32(pll_info + 0x16)((((rdev->bios[pll_info + 0x16]) | ((rdev->bios[(pll_info
+ 0x16)+1]) << 8))) | (((rdev->bios[(pll_info + 0x16
)+2]) | ((rdev->bios[((pll_info + 0x16)+2)+1]) << 8)
) << 16))
;
762 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
763 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
764
765 if (rev > 9) {
766 p1pll->pll_in_min = RBIOS32(pll_info + 0x36)((((rdev->bios[pll_info + 0x36]) | ((rdev->bios[(pll_info
+ 0x36)+1]) << 8))) | (((rdev->bios[(pll_info + 0x36
)+2]) | ((rdev->bios[((pll_info + 0x36)+2)+1]) << 8)
) << 16))
;
767 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a)((((rdev->bios[pll_info + 0x3a]) | ((rdev->bios[(pll_info
+ 0x3a)+1]) << 8))) | (((rdev->bios[(pll_info + 0x3a
)+2]) | ((rdev->bios[((pll_info + 0x3a)+2)+1]) << 8)
) << 16))
;
768 } else {
769 p1pll->pll_in_min = 40;
770 p1pll->pll_in_max = 500;
771 }
772 *p2pll = *p1pll;
773
774 /* system clock */
775 spll->reference_freq = RBIOS16(pll_info + 0x1a)((rdev->bios[pll_info + 0x1a]) | ((rdev->bios[(pll_info
+ 0x1a)+1]) << 8))
;
776 spll->reference_div = RBIOS16(pll_info + 0x1c)((rdev->bios[pll_info + 0x1c]) | ((rdev->bios[(pll_info
+ 0x1c)+1]) << 8))
;
777 spll->pll_out_min = RBIOS32(pll_info + 0x1e)((((rdev->bios[pll_info + 0x1e]) | ((rdev->bios[(pll_info
+ 0x1e)+1]) << 8))) | (((rdev->bios[(pll_info + 0x1e
)+2]) | ((rdev->bios[((pll_info + 0x1e)+2)+1]) << 8)
) << 16))
;
778 spll->pll_out_max = RBIOS32(pll_info + 0x22)((((rdev->bios[pll_info + 0x22]) | ((rdev->bios[(pll_info
+ 0x22)+1]) << 8))) | (((rdev->bios[(pll_info + 0x22
)+2]) | ((rdev->bios[((pll_info + 0x22)+2)+1]) << 8)
) << 16))
;
779
780 if (rev > 10) {
781 spll->pll_in_min = RBIOS32(pll_info + 0x48)((((rdev->bios[pll_info + 0x48]) | ((rdev->bios[(pll_info
+ 0x48)+1]) << 8))) | (((rdev->bios[(pll_info + 0x48
)+2]) | ((rdev->bios[((pll_info + 0x48)+2)+1]) << 8)
) << 16))
;
782 spll->pll_in_max = RBIOS32(pll_info + 0x4c)((((rdev->bios[pll_info + 0x4c]) | ((rdev->bios[(pll_info
+ 0x4c)+1]) << 8))) | (((rdev->bios[(pll_info + 0x4c
)+2]) | ((rdev->bios[((pll_info + 0x4c)+2)+1]) << 8)
) << 16))
;
783 } else {
784 /* ??? */
785 spll->pll_in_min = 40;
786 spll->pll_in_max = 500;
787 }
788
789 /* memory clock */
790 mpll->reference_freq = RBIOS16(pll_info + 0x26)((rdev->bios[pll_info + 0x26]) | ((rdev->bios[(pll_info
+ 0x26)+1]) << 8))
;
791 mpll->reference_div = RBIOS16(pll_info + 0x28)((rdev->bios[pll_info + 0x28]) | ((rdev->bios[(pll_info
+ 0x28)+1]) << 8))
;
792 mpll->pll_out_min = RBIOS32(pll_info + 0x2a)((((rdev->bios[pll_info + 0x2a]) | ((rdev->bios[(pll_info
+ 0x2a)+1]) << 8))) | (((rdev->bios[(pll_info + 0x2a
)+2]) | ((rdev->bios[((pll_info + 0x2a)+2)+1]) << 8)
) << 16))
;
793 mpll->pll_out_max = RBIOS32(pll_info + 0x2e)((((rdev->bios[pll_info + 0x2e]) | ((rdev->bios[(pll_info
+ 0x2e)+1]) << 8))) | (((rdev->bios[(pll_info + 0x2e
)+2]) | ((rdev->bios[((pll_info + 0x2e)+2)+1]) << 8)
) << 16))
;
794
795 if (rev > 10) {
796 mpll->pll_in_min = RBIOS32(pll_info + 0x5a)((((rdev->bios[pll_info + 0x5a]) | ((rdev->bios[(pll_info
+ 0x5a)+1]) << 8))) | (((rdev->bios[(pll_info + 0x5a
)+2]) | ((rdev->bios[((pll_info + 0x5a)+2)+1]) << 8)
) << 16))
;
797 mpll->pll_in_max = RBIOS32(pll_info + 0x5e)((((rdev->bios[pll_info + 0x5e]) | ((rdev->bios[(pll_info
+ 0x5e)+1]) << 8))) | (((rdev->bios[(pll_info + 0x5e
)+2]) | ((rdev->bios[((pll_info + 0x5e)+2)+1]) << 8)
) << 16))
;
798 } else {
799 /* ??? */
800 mpll->pll_in_min = 40;
801 mpll->pll_in_max = 500;
802 }
803
804 /* default sclk/mclk */
805 sclk = RBIOS16(pll_info + 0xa)((rdev->bios[pll_info + 0xa]) | ((rdev->bios[(pll_info +
0xa)+1]) << 8))
;
806 mclk = RBIOS16(pll_info + 0x8)((rdev->bios[pll_info + 0x8]) | ((rdev->bios[(pll_info +
0x8)+1]) << 8))
;
807 if (sclk == 0)
808 sclk = 200 * 100;
809 if (mclk == 0)
810 mclk = 200 * 100;
811
812 rdev->clock.default_sclk = sclk;
813 rdev->clock.default_mclk = mclk;
814
815 if (RBIOS32(pll_info + 0x16)((((rdev->bios[pll_info + 0x16]) | ((rdev->bios[(pll_info
+ 0x16)+1]) << 8))) | (((rdev->bios[(pll_info + 0x16
)+2]) | ((rdev->bios[((pll_info + 0x16)+2)+1]) << 8)
) << 16))
)
816 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16)((((rdev->bios[pll_info + 0x16]) | ((rdev->bios[(pll_info
+ 0x16)+1]) << 8))) | (((rdev->bios[(pll_info + 0x16
)+2]) | ((rdev->bios[((pll_info + 0x16)+2)+1]) << 8)
) << 16))
;
817 else
818 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
819
820 return true1;
821 }
822 return false0;
823}
824
825bool_Bool radeon_combios_sideport_present(struct radeon_device *rdev)
826{
827 struct drm_device *dev = rdev->ddev;
828 u16 igp_info;
829
830 /* sideport is AMD only */
831 if (rdev->family == CHIP_RS400)
832 return false0;
833
834 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
835
836 if (igp_info) {
837 if (RBIOS16(igp_info + 0x4)((rdev->bios[igp_info + 0x4]) | ((rdev->bios[(igp_info +
0x4)+1]) << 8))
)
838 return true1;
839 }
840 return false0;
841}
842
843static const uint32_t default_primarydac_adj[CHIP_LAST] = {
844 0x00000808, /* r100 */
845 0x00000808, /* rv100 */
846 0x00000808, /* rs100 */
847 0x00000808, /* rv200 */
848 0x00000808, /* rs200 */
849 0x00000808, /* r200 */
850 0x00000808, /* rv250 */
851 0x00000000, /* rs300 */
852 0x00000808, /* rv280 */
853 0x00000808, /* r300 */
854 0x00000808, /* r350 */
855 0x00000808, /* rv350 */
856 0x00000808, /* rv380 */
857 0x00000808, /* r420 */
858 0x00000808, /* r423 */
859 0x00000808, /* rv410 */
860 0x00000000, /* rs400 */
861 0x00000000, /* rs480 */
862};
863
864static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
865 struct radeon_encoder_primary_dac *p_dac)
866{
867 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
868 return;
869}
870
871struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
872 radeon_encoder
873 *encoder)
874{
875 struct drm_device *dev = encoder->base.dev;
876 struct radeon_device *rdev = dev->dev_private;
877 uint16_t dac_info;
878 uint8_t rev, bg, dac;
879 struct radeon_encoder_primary_dac *p_dac = NULL((void *)0);
880 int found = 0;
881
882 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
883 GFP_KERNEL(0x0001 | 0x0004));
884
885 if (!p_dac)
886 return NULL((void *)0);
887
888 /* check CRT table */
889 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
890 if (dac_info) {
891 rev = RBIOS8(dac_info)(rdev->bios[dac_info]) & 0x3;
892 if (rev < 2) {
893 bg = RBIOS8(dac_info + 0x2)(rdev->bios[dac_info + 0x2]) & 0xf;
894 dac = (RBIOS8(dac_info + 0x2)(rdev->bios[dac_info + 0x2]) >> 4) & 0xf;
895 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
896 } else {
897 bg = RBIOS8(dac_info + 0x2)(rdev->bios[dac_info + 0x2]) & 0xf;
898 dac = RBIOS8(dac_info + 0x3)(rdev->bios[dac_info + 0x3]) & 0xf;
899 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
900 }
901 /* if the values are zeros, use the table */
902 if ((dac == 0) || (bg == 0))
903 found = 0;
904 else
905 found = 1;
906 }
907
908 /* quirks */
909 /* Radeon 7000 (RV100) */
910 if (((dev->pdev->device == 0x5159) &&
911 (dev->pdev->subsystem_vendor == 0x174B) &&
912 (dev->pdev->subsystem_device == 0x7c28)) ||
913 /* Radeon 9100 (R200) */
914 ((dev->pdev->device == 0x514D) &&
915 (dev->pdev->subsystem_vendor == 0x174B) &&
916 (dev->pdev->subsystem_device == 0x7149))) {
917 /* vbios value is bad, use the default */
918 found = 0;
919 }
920
921 if (!found) /* fallback to defaults */
922 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
923
924 return p_dac;
925}
926
927enum radeon_tv_std
928radeon_combios_get_tv_info(struct radeon_device *rdev)
929{
930 struct drm_device *dev = rdev->ddev;
931 uint16_t tv_info;
932 enum radeon_tv_std tv_std = TV_STD_NTSC;
933
934 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
935 if (tv_info) {
936 if (RBIOS8(tv_info + 6)(rdev->bios[tv_info + 6]) == 'T') {
937 switch (RBIOS8(tv_info + 7)(rdev->bios[tv_info + 7]) & 0xf) {
938 case 1:
939 tv_std = TV_STD_NTSC;
940 DRM_DEBUG_KMS("Default TV standard: NTSC\n")__drm_dbg(DRM_UT_KMS, "Default TV standard: NTSC\n");
941 break;
942 case 2:
943 tv_std = TV_STD_PAL;
944 DRM_DEBUG_KMS("Default TV standard: PAL\n")__drm_dbg(DRM_UT_KMS, "Default TV standard: PAL\n");
945 break;
946 case 3:
947 tv_std = TV_STD_PAL_M;
948 DRM_DEBUG_KMS("Default TV standard: PAL-M\n")__drm_dbg(DRM_UT_KMS, "Default TV standard: PAL-M\n");
949 break;
950 case 4:
951 tv_std = TV_STD_PAL_60;
952 DRM_DEBUG_KMS("Default TV standard: PAL-60\n")__drm_dbg(DRM_UT_KMS, "Default TV standard: PAL-60\n");
953 break;
954 case 5:
955 tv_std = TV_STD_NTSC_J;
956 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n")__drm_dbg(DRM_UT_KMS, "Default TV standard: NTSC-J\n");
957 break;
958 case 6:
959 tv_std = TV_STD_SCART_PAL;
960 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n")__drm_dbg(DRM_UT_KMS, "Default TV standard: SCART-PAL\n");
961 break;
962 default:
963 tv_std = TV_STD_NTSC;
964 DRM_DEBUG_KMS__drm_dbg(DRM_UT_KMS, "Unknown TV standard; defaulting to NTSC\n"
)
965 ("Unknown TV standard; defaulting to NTSC\n")__drm_dbg(DRM_UT_KMS, "Unknown TV standard; defaulting to NTSC\n"
)
;
966 break;
967 }
968
969 switch ((RBIOS8(tv_info + 9)(rdev->bios[tv_info + 9]) >> 2) & 0x3) {
970 case 0:
971 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n")__drm_dbg(DRM_UT_KMS, "29.498928713 MHz TV ref clk\n");
972 break;
973 case 1:
974 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n")__drm_dbg(DRM_UT_KMS, "28.636360000 MHz TV ref clk\n");
975 break;
976 case 2:
977 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n")__drm_dbg(DRM_UT_KMS, "14.318180000 MHz TV ref clk\n");
978 break;
979 case 3:
980 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n")__drm_dbg(DRM_UT_KMS, "27.000000000 MHz TV ref clk\n");
981 break;
982 default:
983 break;
984 }
985 }
986 }
987 return tv_std;
988}
989
990static const uint32_t default_tvdac_adj[CHIP_LAST] = {
991 0x00000000, /* r100 */
992 0x00280000, /* rv100 */
993 0x00000000, /* rs100 */
994 0x00880000, /* rv200 */
995 0x00000000, /* rs200 */
996 0x00000000, /* r200 */
997 0x00770000, /* rv250 */
998 0x00290000, /* rs300 */
999 0x00560000, /* rv280 */
1000 0x00780000, /* r300 */
1001 0x00770000, /* r350 */
1002 0x00780000, /* rv350 */
1003 0x00780000, /* rv380 */
1004 0x01080000, /* r420 */
1005 0x01080000, /* r423 */
1006 0x01080000, /* rv410 */
1007 0x00780000, /* rs400 */
1008 0x00780000, /* rs480 */
1009};
1010
1011static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1012 struct radeon_encoder_tv_dac *tv_dac)
1013{
1014 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1015 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1016 tv_dac->ps2_tvdac_adj = 0x00880000;
1017 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1018 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1019 return;
1020}
1021
1022struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1023 radeon_encoder
1024 *encoder)
1025{
1026 struct drm_device *dev = encoder->base.dev;
1027 struct radeon_device *rdev = dev->dev_private;
1028 uint16_t dac_info;
1029 uint8_t rev, bg, dac;
1030 struct radeon_encoder_tv_dac *tv_dac = NULL((void *)0);
1031 int found = 0;
1032
1033 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL(0x0001 | 0x0004));
1034 if (!tv_dac)
1035 return NULL((void *)0);
1036
1037 /* first check TV table */
1038 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1039 if (dac_info) {
1040 rev = RBIOS8(dac_info + 0x3)(rdev->bios[dac_info + 0x3]);
1041 if (rev > 4) {
1042 bg = RBIOS8(dac_info + 0xc)(rdev->bios[dac_info + 0xc]) & 0xf;
1043 dac = RBIOS8(dac_info + 0xd)(rdev->bios[dac_info + 0xd]) & 0xf;
1044 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1045
1046 bg = RBIOS8(dac_info + 0xe)(rdev->bios[dac_info + 0xe]) & 0xf;
1047 dac = RBIOS8(dac_info + 0xf)(rdev->bios[dac_info + 0xf]) & 0xf;
1048 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1049
1050 bg = RBIOS8(dac_info + 0x10)(rdev->bios[dac_info + 0x10]) & 0xf;
1051 dac = RBIOS8(dac_info + 0x11)(rdev->bios[dac_info + 0x11]) & 0xf;
1052 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1053 /* if the values are all zeros, use the table */
1054 if (tv_dac->ps2_tvdac_adj)
1055 found = 1;
1056 } else if (rev > 1) {
1057 bg = RBIOS8(dac_info + 0xc)(rdev->bios[dac_info + 0xc]) & 0xf;
1058 dac = (RBIOS8(dac_info + 0xc)(rdev->bios[dac_info + 0xc]) >> 4) & 0xf;
1059 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1060
1061 bg = RBIOS8(dac_info + 0xd)(rdev->bios[dac_info + 0xd]) & 0xf;
1062 dac = (RBIOS8(dac_info + 0xd)(rdev->bios[dac_info + 0xd]) >> 4) & 0xf;
1063 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1064
1065 bg = RBIOS8(dac_info + 0xe)(rdev->bios[dac_info + 0xe]) & 0xf;
1066 dac = (RBIOS8(dac_info + 0xe)(rdev->bios[dac_info + 0xe]) >> 4) & 0xf;
1067 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1068 /* if the values are all zeros, use the table */
1069 if (tv_dac->ps2_tvdac_adj)
1070 found = 1;
1071 }
1072 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1073 }
1074 if (!found) {
1075 /* then check CRT table */
1076 dac_info =
1077 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1078 if (dac_info) {
1079 rev = RBIOS8(dac_info)(rdev->bios[dac_info]) & 0x3;
1080 if (rev < 2) {
1081 bg = RBIOS8(dac_info + 0x3)(rdev->bios[dac_info + 0x3]) & 0xf;
1082 dac = (RBIOS8(dac_info + 0x3)(rdev->bios[dac_info + 0x3]) >> 4) & 0xf;
1083 tv_dac->ps2_tvdac_adj =
1084 (bg << 16) | (dac << 20);
1085 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1086 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1087 /* if the values are all zeros, use the table */
1088 if (tv_dac->ps2_tvdac_adj)
1089 found = 1;
1090 } else {
1091 bg = RBIOS8(dac_info + 0x4)(rdev->bios[dac_info + 0x4]) & 0xf;
1092 dac = RBIOS8(dac_info + 0x5)(rdev->bios[dac_info + 0x5]) & 0xf;
1093 tv_dac->ps2_tvdac_adj =
1094 (bg << 16) | (dac << 20);
1095 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1096 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1097 /* if the values are all zeros, use the table */
1098 if (tv_dac->ps2_tvdac_adj)
1099 found = 1;
1100 }
1101 } else {
1102 DRM_INFO("No TV DAC info found in BIOS\n")printk("\0016" "[" "drm" "] " "No TV DAC info found in BIOS\n"
)
;
1103 }
1104 }
1105
1106 if (!found) /* fallback to defaults */
1107 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1108
1109 return tv_dac;
1110}
1111
1112static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1113 radeon_device
1114 *rdev)
1115{
1116 struct radeon_encoder_lvds *lvds = NULL((void *)0);
1117 uint32_t fp_vert_stretch, fp_horz_stretch;
1118 uint32_t ppll_div_sel, ppll_val;
1119 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL)r100_mm_rreg(rdev, (0x02ec), 0);
1120
1121 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL(0x0001 | 0x0004));
1122
1123 if (!lvds)
1124 return NULL((void *)0);
1125
1126 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH)r100_mm_rreg(rdev, (0x0290), 0);
1127 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH)r100_mm_rreg(rdev, (0x028c), 0);
1128
1129 /* These should be fail-safe defaults, fingers crossed */
1130 lvds->panel_pwr_delay = 200;
1131 lvds->panel_vcc_delay = 2000;
1132
1133 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL)r100_mm_rreg(rdev, (0x02d0), 0);
1134 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT16) & 0xf;
1135 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT20) & 0xf;
1136
1137 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE(1 << 25))
1138 lvds->native_mode.vdisplay =
1139 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE(0xfff << 12)) >>
1140 RADEON_VERT_PANEL_SHIFT12) + 1;
1141 else
1142 lvds->native_mode.vdisplay =
1143 (RREG32(RADEON_CRTC_V_TOTAL_DISP)r100_mm_rreg(rdev, (0x0208), 0) >> 16) + 1;
1144
1145 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE(1 << 25))
1146 lvds->native_mode.hdisplay =
1147 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE(0x1ff << 16)) >>
1148 RADEON_HORZ_PANEL_SHIFT16) + 1) * 8;
1149 else
1150 lvds->native_mode.hdisplay =
1151 ((RREG32(RADEON_CRTC_H_TOTAL_DISP)r100_mm_rreg(rdev, (0x0200), 0) >> 16) + 1) * 8;
1152
1153 if ((lvds->native_mode.hdisplay < 640) ||
1154 (lvds->native_mode.vdisplay < 480)) {
1155 lvds->native_mode.hdisplay = 640;
1156 lvds->native_mode.vdisplay = 480;
1157 }
1158
1159 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1)ioread8((rdev->rmmio) + (0x0008 + 1)) & 0x3;
1160 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel)rdev->pll_rreg(rdev, (0x0004 + ppll_div_sel));
1161 if ((ppll_val & 0x000707ff) == 0x1bb)
1162 lvds->use_bios_dividers = false0;
1163 else {
1164 lvds->panel_ref_divider =
1165 RREG32_PLL(RADEON_PPLL_REF_DIV)rdev->pll_rreg(rdev, (0x0003)) & 0x3ff;
1166 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1167 lvds->panel_fb_divider = ppll_val & 0x7ff;
1168
1169 if ((lvds->panel_ref_divider != 0) &&
1170 (lvds->panel_fb_divider > 3))
1171 lvds->use_bios_dividers = true1;
1172 }
1173 lvds->panel_vcc_delay = 200;
1174
1175 DRM_INFO("Panel info derived from registers\n")printk("\0016" "[" "drm" "] " "Panel info derived from registers\n"
)
;
1176 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,printk("\0016" "[" "drm" "] " "Panel Size %dx%d\n", lvds->
native_mode.hdisplay, lvds->native_mode.vdisplay)
1177 lvds->native_mode.vdisplay)printk("\0016" "[" "drm" "] " "Panel Size %dx%d\n", lvds->
native_mode.hdisplay, lvds->native_mode.vdisplay)
;
1178
1179 return lvds;
1180}
1181
1182struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1183 *encoder)
1184{
1185 struct drm_device *dev = encoder->base.dev;
1186 struct radeon_device *rdev = dev->dev_private;
1187 uint16_t lcd_info;
1188 uint32_t panel_setup;
1189 char stmp[30];
1190 int tmp, i;
1191 struct radeon_encoder_lvds *lvds = NULL((void *)0);
1192
1193 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1194
1195 if (lcd_info) {
1196 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL(0x0001 | 0x0004));
1197
1198 if (!lvds)
1199 return NULL((void *)0);
1200
1201 for (i = 0; i < 24; i++)
1202 stmp[i] = RBIOS8(lcd_info + i + 1)(rdev->bios[lcd_info + i + 1]);
1203 stmp[24] = 0;
1204
1205 DRM_INFO("Panel ID String: %s\n", stmp)printk("\0016" "[" "drm" "] " "Panel ID String: %s\n", stmp);
1206
1207 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19)((rdev->bios[lcd_info + 0x19]) | ((rdev->bios[(lcd_info
+ 0x19)+1]) << 8))
;
1208 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b)((rdev->bios[lcd_info + 0x1b]) | ((rdev->bios[(lcd_info
+ 0x1b)+1]) << 8))
;
1209
1210 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,printk("\0016" "[" "drm" "] " "Panel Size %dx%d\n", lvds->
native_mode.hdisplay, lvds->native_mode.vdisplay)
1211 lvds->native_mode.vdisplay)printk("\0016" "[" "drm" "] " "Panel Size %dx%d\n", lvds->
native_mode.hdisplay, lvds->native_mode.vdisplay)
;
1212
1213 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c)((rdev->bios[lcd_info + 0x2c]) | ((rdev->bios[(lcd_info
+ 0x2c)+1]) << 8))
;
1214 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000)({ u16 __min_a = (lvds->panel_vcc_delay); u16 __min_b = (2000
); __min_a < __min_b ? __min_a : __min_b; })
;
1215
1216 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24)(rdev->bios[lcd_info + 0x24]);
1217 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38)((rdev->bios[lcd_info + 0x38]) | ((rdev->bios[(lcd_info
+ 0x38)+1]) << 8))
& 0xf;
1218 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38)((rdev->bios[lcd_info + 0x38]) | ((rdev->bios[(lcd_info
+ 0x38)+1]) << 8))
>> 4) & 0xf;
1219
1220 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e)((rdev->bios[lcd_info + 0x2e]) | ((rdev->bios[(lcd_info
+ 0x2e)+1]) << 8))
;
1221 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30)(rdev->bios[lcd_info + 0x30]);
1222 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31)((rdev->bios[lcd_info + 0x31]) | ((rdev->bios[(lcd_info
+ 0x31)+1]) << 8))
;
1223 if ((lvds->panel_ref_divider != 0) &&
1224 (lvds->panel_fb_divider > 3))
1225 lvds->use_bios_dividers = true1;
1226
1227 panel_setup = RBIOS32(lcd_info + 0x39)((((rdev->bios[lcd_info + 0x39]) | ((rdev->bios[(lcd_info
+ 0x39)+1]) << 8))) | (((rdev->bios[(lcd_info + 0x39
)+2]) | ((rdev->bios[((lcd_info + 0x39)+2)+1]) << 8)
) << 16))
;
1228 lvds->lvds_gen_cntl = 0xff00;
1229 if (panel_setup & 0x1)
1230 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT(1 << 3);
1231
1232 if ((panel_setup >> 4) & 0x1)
1233 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE(1 << 2);
1234
1235 switch ((panel_setup >> 8) & 0x7) {
1236 case 0:
1237 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM(0 << 4);
1238 break;
1239 case 1:
1240 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY(1 << 4);
1241 break;
1242 case 2:
1243 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY(2 << 4);
1244 break;
1245 default:
1246 break;
1247 }
1248
1249 if ((panel_setup >> 16) & 0x1)
1250 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW(1 << 20);
1251
1252 if ((panel_setup >> 17) & 0x1)
1253 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW(1 << 21);
1254
1255 if ((panel_setup >> 18) & 0x1)
1256 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW(1 << 22);
1257
1258 if ((panel_setup >> 23) & 0x1)
1259 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL(1 << 17);
1260
1261 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1262
1263 for (i = 0; i < 32; i++) {
1264 tmp = RBIOS16(lcd_info + 64 + i * 2)((rdev->bios[lcd_info + 64 + i * 2]) | ((rdev->bios[(lcd_info
+ 64 + i * 2)+1]) << 8))
;
1265 if (tmp == 0)
1266 break;
1267
1268 if ((RBIOS16(tmp)((rdev->bios[tmp]) | ((rdev->bios[(tmp)+1]) << 8)
)
== lvds->native_mode.hdisplay) &&
1269 (RBIOS16(tmp + 2)((rdev->bios[tmp + 2]) | ((rdev->bios[(tmp + 2)+1]) <<
8))
== lvds->native_mode.vdisplay)) {
1270 u32 hss = (RBIOS16(tmp + 21)((rdev->bios[tmp + 21]) | ((rdev->bios[(tmp + 21)+1]) <<
8))
- RBIOS16(tmp + 19)((rdev->bios[tmp + 19]) | ((rdev->bios[(tmp + 19)+1]) <<
8))
- 1) * 8;
1271
1272 if (hss > lvds->native_mode.hdisplay)
1273 hss = (10 - 1) * 8;
1274
1275 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1276 (RBIOS16(tmp + 17)((rdev->bios[tmp + 17]) | ((rdev->bios[(tmp + 17)+1]) <<
8))
- RBIOS16(tmp + 19)((rdev->bios[tmp + 19]) | ((rdev->bios[(tmp + 19)+1]) <<
8))
) * 8;
1277 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1278 hss;
1279 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1280 (RBIOS8(tmp + 23)(rdev->bios[tmp + 23]) * 8);
1281
1282 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1283 (RBIOS16(tmp + 24)((rdev->bios[tmp + 24]) | ((rdev->bios[(tmp + 24)+1]) <<
8))
- RBIOS16(tmp + 26)((rdev->bios[tmp + 26]) | ((rdev->bios[(tmp + 26)+1]) <<
8))
);
1284 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1285 ((RBIOS16(tmp + 28)((rdev->bios[tmp + 28]) | ((rdev->bios[(tmp + 28)+1]) <<
8))
& 0x7ff) - RBIOS16(tmp + 26)((rdev->bios[tmp + 26]) | ((rdev->bios[(tmp + 26)+1]) <<
8))
);
1286 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1287 ((RBIOS16(tmp + 28)((rdev->bios[tmp + 28]) | ((rdev->bios[(tmp + 28)+1]) <<
8))
& 0xf800) >> 11);
1288
1289 lvds->native_mode.clock = RBIOS16(tmp + 9)((rdev->bios[tmp + 9]) | ((rdev->bios[(tmp + 9)+1]) <<
8))
* 10;
1290 lvds->native_mode.flags = 0;
1291 /* set crtc values */
1292 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V(1 << 0));
1293
1294 }
1295 }
1296 } else {
1297 DRM_INFO("No panel info found in BIOS\n")printk("\0016" "[" "drm" "] " "No panel info found in BIOS\n"
)
;
1298 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1299 }
1300
1301 if (lvds)
1302 encoder->native_mode = lvds->native_mode;
1303 return lvds;
1304}
1305
1306static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1307 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1308 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1309 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1310 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1311 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1312 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1313 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1314 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1315 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1316 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1317 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1318 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1319 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1320 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1321 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1322 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1323 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1324 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1325};
1326
1327bool_Bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1328 struct radeon_encoder_int_tmds *tmds)
1329{
1330 struct drm_device *dev = encoder->base.dev;
1331 struct radeon_device *rdev = dev->dev_private;
1332 int i;
1333
1334 for (i = 0; i < 4; i++) {
1335 tmds->tmds_pll[i].value =
1336 default_tmds_pll[rdev->family][i].value;
1337 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1338 }
1339
1340 return true1;
1341}
1342
1343bool_Bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1344 struct radeon_encoder_int_tmds *tmds)
1345{
1346 struct drm_device *dev = encoder->base.dev;
1347 struct radeon_device *rdev = dev->dev_private;
1348 uint16_t tmds_info;
1349 int i, n;
1350 uint8_t ver;
1351
1352 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1353
1354 if (tmds_info) {
1355 ver = RBIOS8(tmds_info)(rdev->bios[tmds_info]);
1356 DRM_DEBUG_KMS("DFP table revision: %d\n", ver)__drm_dbg(DRM_UT_KMS, "DFP table revision: %d\n", ver);
1357 if (ver == 3) {
1358 n = RBIOS8(tmds_info + 5)(rdev->bios[tmds_info + 5]) + 1;
1359 if (n > 4)
1360 n = 4;
1361 for (i = 0; i < n; i++) {
1362 tmds->tmds_pll[i].value =
1363 RBIOS32(tmds_info + i * 10 + 0x08)((((rdev->bios[tmds_info + i * 10 + 0x08]) | ((rdev->bios
[(tmds_info + i * 10 + 0x08)+1]) << 8))) | (((rdev->
bios[(tmds_info + i * 10 + 0x08)+2]) | ((rdev->bios[((tmds_info
+ i * 10 + 0x08)+2)+1]) << 8)) << 16))
;
1364 tmds->tmds_pll[i].freq =
1365 RBIOS16(tmds_info + i * 10 + 0x10)((rdev->bios[tmds_info + i * 10 + 0x10]) | ((rdev->bios
[(tmds_info + i * 10 + 0x10)+1]) << 8))
;
1366 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",__drm_dbg(DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n", tmds->
tmds_pll[i].freq, tmds->tmds_pll[i].value)
1367 tmds->tmds_pll[i].freq,__drm_dbg(DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n", tmds->
tmds_pll[i].freq, tmds->tmds_pll[i].value)
1368 tmds->tmds_pll[i].value)__drm_dbg(DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n", tmds->
tmds_pll[i].freq, tmds->tmds_pll[i].value)
;
1369 }
1370 } else if (ver == 4) {
1371 int stride = 0;
1372 n = RBIOS8(tmds_info + 5)(rdev->bios[tmds_info + 5]) + 1;
1373 if (n > 4)
1374 n = 4;
1375 for (i = 0; i < n; i++) {
1376 tmds->tmds_pll[i].value =
1377 RBIOS32(tmds_info + stride + 0x08)((((rdev->bios[tmds_info + stride + 0x08]) | ((rdev->bios
[(tmds_info + stride + 0x08)+1]) << 8))) | (((rdev->
bios[(tmds_info + stride + 0x08)+2]) | ((rdev->bios[((tmds_info
+ stride + 0x08)+2)+1]) << 8)) << 16))
;
1378 tmds->tmds_pll[i].freq =
1379 RBIOS16(tmds_info + stride + 0x10)((rdev->bios[tmds_info + stride + 0x10]) | ((rdev->bios
[(tmds_info + stride + 0x10)+1]) << 8))
;
1380 if (i == 0)
1381 stride += 10;
1382 else
1383 stride += 6;
1384 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",__drm_dbg(DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n", tmds->
tmds_pll[i].freq, tmds->tmds_pll[i].value)
1385 tmds->tmds_pll[i].freq,__drm_dbg(DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n", tmds->
tmds_pll[i].freq, tmds->tmds_pll[i].value)
1386 tmds->tmds_pll[i].value)__drm_dbg(DRM_UT_KMS, "TMDS PLL From COMBIOS %u %x\n", tmds->
tmds_pll[i].freq, tmds->tmds_pll[i].value)
;
1387 }
1388 }
1389 } else {
1390 DRM_INFO("No TMDS info found in BIOS\n")printk("\0016" "[" "drm" "] " "No TMDS info found in BIOS\n");
1391 return false0;
1392 }
1393 return true1;
1394}
1395
1396bool_Bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1397 struct radeon_encoder_ext_tmds *tmds)
1398{
1399 struct drm_device *dev = encoder->base.dev;
1400 struct radeon_device *rdev = dev->dev_private;
1401 struct radeon_i2c_bus_rec i2c_bus;
1402
1403 /* default for macs */
1404 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1405 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1406
1407 /* XXX some macs have duallink chips */
1408 switch (rdev->mode_info.connector_table) {
1409 case CT_POWERBOOK_EXTERNAL:
1410 case CT_MINI_EXTERNAL:
1411 default:
1412 tmds->dvo_chip = DVO_SIL164;
1413 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1414 break;
1415 }
1416
1417 return true1;
1418}
1419
1420bool_Bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1421 struct radeon_encoder_ext_tmds *tmds)
1422{
1423 struct drm_device *dev = encoder->base.dev;
1424 struct radeon_device *rdev = dev->dev_private;
1425 uint16_t offset;
1426 uint8_t ver;
1427 enum radeon_combios_ddc gpio;
1428 struct radeon_i2c_bus_rec i2c_bus;
1429
1430 tmds->i2c_bus = NULL((void *)0);
1431 if (rdev->flags & RADEON_IS_IGP) {
1432 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1433 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1434 tmds->dvo_chip = DVO_SIL164;
1435 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1436 } else {
1437 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1438 if (offset) {
1439 ver = RBIOS8(offset)(rdev->bios[offset]);
1440 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver)__drm_dbg(DRM_UT_KMS, "External TMDS Table revision: %d\n", ver
)
;
1441 tmds->slave_addr = RBIOS8(offset + 4 + 2)(rdev->bios[offset + 4 + 2]);
1442 tmds->slave_addr >>= 1; /* 7 bit addressing */
1443 gpio = RBIOS8(offset + 4 + 3)(rdev->bios[offset + 4 + 3]);
1444 if (gpio == DDC_LCD) {
1445 /* MM i2c */
1446 i2c_bus.valid = true1;
1447 i2c_bus.hw_capable = true1;
1448 i2c_bus.mm_i2c = true1;
1449 i2c_bus.i2c_id = 0xa0;
1450 } else
1451 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1452 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1453 }
1454 }
1455
1456 if (!tmds->i2c_bus) {
1457 DRM_INFO("No valid Ext TMDS info found in BIOS\n")printk("\0016" "[" "drm" "] " "No valid Ext TMDS info found in BIOS\n"
)
;
1458 return false0;
1459 }
1460
1461 return true1;
1462}
1463
1464bool_Bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1465{
1466 struct radeon_device *rdev = dev->dev_private;
1467 struct radeon_i2c_bus_rec ddc_i2c;
1468 struct radeon_hpd hpd;
1469
1470 rdev->mode_info.connector_table = radeon_connector_table;
1471 if (rdev->mode_info.connector_table == CT_NONE) {
1472#ifdef CONFIG_PPC_PMAC
1473 if (of_machine_is_compatible("PowerBook3,3")) {
1474 /* powerbook with VGA */
1475 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1476 } else if (of_machine_is_compatible("PowerBook3,4") ||
1477 of_machine_is_compatible("PowerBook3,5")) {
1478 /* powerbook with internal tmds */
1479 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1480 } else if (of_machine_is_compatible("PowerBook5,1") ||
1481 of_machine_is_compatible("PowerBook5,2") ||
1482 of_machine_is_compatible("PowerBook5,3") ||
1483 of_machine_is_compatible("PowerBook5,4") ||
1484 of_machine_is_compatible("PowerBook5,5")) {
1485 /* powerbook with external single link tmds (sil164) */
1486 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1487 } else if (of_machine_is_compatible("PowerBook5,6")) {
1488 /* powerbook with external dual or single link tmds */
1489 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1490 } else if (of_machine_is_compatible("PowerBook5,7") ||
1491 of_machine_is_compatible("PowerBook5,8") ||
1492 of_machine_is_compatible("PowerBook5,9")) {
1493 /* PowerBook6,2 ? */
1494 /* powerbook with external dual link tmds (sil1178?) */
1495 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1496 } else if (of_machine_is_compatible("PowerBook4,1") ||
1497 of_machine_is_compatible("PowerBook4,2") ||
1498 of_machine_is_compatible("PowerBook4,3") ||
1499 of_machine_is_compatible("PowerBook6,3") ||
1500 of_machine_is_compatible("PowerBook6,5") ||
1501 of_machine_is_compatible("PowerBook6,7")) {
1502 /* ibook */
1503 rdev->mode_info.connector_table = CT_IBOOK;
1504 } else if (of_machine_is_compatible("PowerMac3,5")) {
1505 /* PowerMac G4 Silver radeon 7500 */
1506 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1507 } else if (of_machine_is_compatible("PowerMac4,4")) {
1508 /* emac */
1509 rdev->mode_info.connector_table = CT_EMAC;
1510 } else if (of_machine_is_compatible("PowerMac10,1")) {
1511 /* mini with internal tmds */
1512 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1513 } else if (of_machine_is_compatible("PowerMac10,2")) {
1514 /* mini with external tmds */
1515 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1516 } else if (of_machine_is_compatible("PowerMac12,1")) {
1517 /* PowerMac8,1 ? */
1518 /* imac g5 isight */
1519 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1520 } else if ((rdev->pdev->device == 0x4a48) &&
1521 (rdev->pdev->subsystem_vendor == 0x1002) &&
1522 (rdev->pdev->subsystem_device == 0x4a48)) {
1523 /* Mac X800 */
1524 rdev->mode_info.connector_table = CT_MAC_X800;
1525 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1526 of_machine_is_compatible("PowerMac7,3")) &&
1527 (rdev->pdev->device == 0x4150) &&
1528 (rdev->pdev->subsystem_vendor == 0x1002) &&
1529 (rdev->pdev->subsystem_device == 0x4150)) {
1530 /* Mac G5 tower 9600 */
1531 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1532 } else if ((rdev->pdev->device == 0x4c66) &&
1533 (rdev->pdev->subsystem_vendor == 0x1002) &&
1534 (rdev->pdev->subsystem_device == 0x4c66)) {
1535 /* SAM440ep RV250 embedded board */
1536 rdev->mode_info.connector_table = CT_SAM440EP;
1537 } else
1538#endif /* CONFIG_PPC_PMAC */
1539#ifdef CONFIG_PPC64
1540 if (ASIC_IS_RN50(rdev)((rdev->pdev->device == 0x515e) || (rdev->pdev->device
== 0x5969))
)
1541 rdev->mode_info.connector_table = CT_RN50_POWER;
1542 else
1543#endif
1544 rdev->mode_info.connector_table = CT_GENERIC;
1545 }
1546
1547 switch (rdev->mode_info.connector_table) {
1548 case CT_GENERIC:
1549 DRM_INFO("Connector Table: %d (generic)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (generic)\n"
, rdev->mode_info.connector_table)
1550 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (generic)\n"
, rdev->mode_info.connector_table)
;
1551 /* these are the most common settings */
1552 if (rdev->flags & RADEON_SINGLE_CRTC) {
1553 /* VGA - primary dac */
1554 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1555 hpd.hpd = RADEON_HPD_NONE;
1556 radeon_add_legacy_encoder(dev,
1557 radeon_get_encoder_enum(dev,
1558 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1559 1),
1560 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
1561 radeon_add_legacy_connector(dev, 0,
1562 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1563 DRM_MODE_CONNECTOR_VGA1,
1564 &ddc_i2c,
1565 CONNECTOR_OBJECT_ID_VGA0x05,
1566 &hpd);
1567 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1568 /* LVDS */
1569 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1570 hpd.hpd = RADEON_HPD_NONE;
1571 radeon_add_legacy_encoder(dev,
1572 radeon_get_encoder_enum(dev,
1573 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1574 0),
1575 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ));
1576 radeon_add_legacy_connector(dev, 0,
1577 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1578 DRM_MODE_CONNECTOR_LVDS7,
1579 &ddc_i2c,
1580 CONNECTOR_OBJECT_ID_LVDS0x0E,
1581 &hpd);
1582
1583 /* VGA - primary dac */
1584 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1585 hpd.hpd = RADEON_HPD_NONE;
1586 radeon_add_legacy_encoder(dev,
1587 radeon_get_encoder_enum(dev,
1588 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1589 1),
1590 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
1591 radeon_add_legacy_connector(dev, 1,
1592 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1593 DRM_MODE_CONNECTOR_VGA1,
1594 &ddc_i2c,
1595 CONNECTOR_OBJECT_ID_VGA0x05,
1596 &hpd);
1597 } else {
1598 /* DVI-I - tv dac, int tmds */
1599 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1600 hpd.hpd = RADEON_HPD_1;
1601 radeon_add_legacy_encoder(dev,
1602 radeon_get_encoder_enum(dev,
1603 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
1604 0),
1605 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
1606 radeon_add_legacy_encoder(dev,
1607 radeon_get_encoder_enum(dev,
1608 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1609 2),
1610 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
1611 radeon_add_legacy_connector(dev, 0,
1612 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) |
1613 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1614 DRM_MODE_CONNECTOR_DVII2,
1615 &ddc_i2c,
1616 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
1617 &hpd);
1618
1619 /* VGA - primary dac */
1620 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1621 hpd.hpd = RADEON_HPD_NONE;
1622 radeon_add_legacy_encoder(dev,
1623 radeon_get_encoder_enum(dev,
1624 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1625 1),
1626 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
1627 radeon_add_legacy_connector(dev, 1,
1628 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1629 DRM_MODE_CONNECTOR_VGA1,
1630 &ddc_i2c,
1631 CONNECTOR_OBJECT_ID_VGA0x05,
1632 &hpd);
1633 }
1634
1635 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1636 /* TV - tv dac */
1637 ddc_i2c.valid = false0;
1638 hpd.hpd = RADEON_HPD_NONE;
1639 radeon_add_legacy_encoder(dev,
1640 radeon_get_encoder_enum(dev,
1641 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1642 2),
1643 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1644 radeon_add_legacy_connector(dev, 2,
1645 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1646 DRM_MODE_CONNECTOR_SVIDEO6,
1647 &ddc_i2c,
1648 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1649 &hpd);
1650 }
1651 break;
1652 case CT_IBOOK:
1653 DRM_INFO("Connector Table: %d (ibook)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (ibook)\n"
, rdev->mode_info.connector_table)
1654 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (ibook)\n"
, rdev->mode_info.connector_table)
;
1655 /* LVDS */
1656 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1657 hpd.hpd = RADEON_HPD_NONE;
1658 radeon_add_legacy_encoder(dev,
1659 radeon_get_encoder_enum(dev,
1660 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1661 0),
1662 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ));
1663 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1664 DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c,
1665 CONNECTOR_OBJECT_ID_LVDS0x0E,
1666 &hpd);
1667 /* VGA - TV DAC */
1668 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1669 hpd.hpd = RADEON_HPD_NONE;
1670 radeon_add_legacy_encoder(dev,
1671 radeon_get_encoder_enum(dev,
1672 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1673 2),
1674 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
1675 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1676 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
1677 CONNECTOR_OBJECT_ID_VGA0x05,
1678 &hpd);
1679 /* TV - TV DAC */
1680 ddc_i2c.valid = false0;
1681 hpd.hpd = RADEON_HPD_NONE;
1682 radeon_add_legacy_encoder(dev,
1683 radeon_get_encoder_enum(dev,
1684 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1685 2),
1686 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1687 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1688 DRM_MODE_CONNECTOR_SVIDEO6,
1689 &ddc_i2c,
1690 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1691 &hpd);
1692 break;
1693 case CT_POWERBOOK_EXTERNAL:
1694 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook external tmds)\n"
, rdev->mode_info.connector_table)
1695 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook external tmds)\n"
, rdev->mode_info.connector_table)
;
1696 /* LVDS */
1697 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1698 hpd.hpd = RADEON_HPD_NONE;
1699 radeon_add_legacy_encoder(dev,
1700 radeon_get_encoder_enum(dev,
1701 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1702 0),
1703 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ));
1704 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1705 DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c,
1706 CONNECTOR_OBJECT_ID_LVDS0x0E,
1707 &hpd);
1708 /* DVI-I - primary dac, ext tmds */
1709 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1710 hpd.hpd = RADEON_HPD_2; /* ??? */
1711 radeon_add_legacy_encoder(dev,
1712 radeon_get_encoder_enum(dev,
1713 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ),
1714 0),
1715 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ));
1716 radeon_add_legacy_encoder(dev,
1717 radeon_get_encoder_enum(dev,
1718 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1719 1),
1720 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
1721 /* XXX some are SL */
1722 radeon_add_legacy_connector(dev, 1,
1723 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ) |
1724 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1725 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
1726 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I0x02,
1727 &hpd);
1728 /* TV - TV DAC */
1729 ddc_i2c.valid = false0;
1730 hpd.hpd = RADEON_HPD_NONE;
1731 radeon_add_legacy_encoder(dev,
1732 radeon_get_encoder_enum(dev,
1733 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1734 2),
1735 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1736 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1737 DRM_MODE_CONNECTOR_SVIDEO6,
1738 &ddc_i2c,
1739 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1740 &hpd);
1741 break;
1742 case CT_POWERBOOK_INTERNAL:
1743 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook internal tmds)\n"
, rdev->mode_info.connector_table)
1744 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook internal tmds)\n"
, rdev->mode_info.connector_table)
;
1745 /* LVDS */
1746 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1747 hpd.hpd = RADEON_HPD_NONE;
1748 radeon_add_legacy_encoder(dev,
1749 radeon_get_encoder_enum(dev,
1750 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1751 0),
1752 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ));
1753 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1754 DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c,
1755 CONNECTOR_OBJECT_ID_LVDS0x0E,
1756 &hpd);
1757 /* DVI-I - primary dac, int tmds */
1758 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1759 hpd.hpd = RADEON_HPD_1; /* ??? */
1760 radeon_add_legacy_encoder(dev,
1761 radeon_get_encoder_enum(dev,
1762 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
1763 0),
1764 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
1765 radeon_add_legacy_encoder(dev,
1766 radeon_get_encoder_enum(dev,
1767 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1768 1),
1769 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
1770 radeon_add_legacy_connector(dev, 1,
1771 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) |
1772 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1773 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
1774 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
1775 &hpd);
1776 /* TV - TV DAC */
1777 ddc_i2c.valid = false0;
1778 hpd.hpd = RADEON_HPD_NONE;
1779 radeon_add_legacy_encoder(dev,
1780 radeon_get_encoder_enum(dev,
1781 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1782 2),
1783 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1784 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1785 DRM_MODE_CONNECTOR_SVIDEO6,
1786 &ddc_i2c,
1787 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1788 &hpd);
1789 break;
1790 case CT_POWERBOOK_VGA:
1791 DRM_INFO("Connector Table: %d (powerbook vga)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook vga)\n"
, rdev->mode_info.connector_table)
1792 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (powerbook vga)\n"
, rdev->mode_info.connector_table)
;
1793 /* LVDS */
1794 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1795 hpd.hpd = RADEON_HPD_NONE;
1796 radeon_add_legacy_encoder(dev,
1797 radeon_get_encoder_enum(dev,
1798 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1799 0),
1800 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ));
1801 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
1802 DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c,
1803 CONNECTOR_OBJECT_ID_LVDS0x0E,
1804 &hpd);
1805 /* VGA - primary dac */
1806 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1807 hpd.hpd = RADEON_HPD_NONE;
1808 radeon_add_legacy_encoder(dev,
1809 radeon_get_encoder_enum(dev,
1810 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1811 1),
1812 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
1813 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1814 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
1815 CONNECTOR_OBJECT_ID_VGA0x05,
1816 &hpd);
1817 /* TV - TV DAC */
1818 ddc_i2c.valid = false0;
1819 hpd.hpd = RADEON_HPD_NONE;
1820 radeon_add_legacy_encoder(dev,
1821 radeon_get_encoder_enum(dev,
1822 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1823 2),
1824 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1825 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1826 DRM_MODE_CONNECTOR_SVIDEO6,
1827 &ddc_i2c,
1828 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1829 &hpd);
1830 break;
1831 case CT_MINI_EXTERNAL:
1832 DRM_INFO("Connector Table: %d (mini external tmds)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mini external tmds)\n"
, rdev->mode_info.connector_table)
1833 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mini external tmds)\n"
, rdev->mode_info.connector_table)
;
1834 /* DVI-I - tv dac, ext tmds */
1835 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1836 hpd.hpd = RADEON_HPD_2; /* ??? */
1837 radeon_add_legacy_encoder(dev,
1838 radeon_get_encoder_enum(dev,
1839 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ),
1840 0),
1841 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ));
1842 radeon_add_legacy_encoder(dev,
1843 radeon_get_encoder_enum(dev,
1844 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1845 2),
1846 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
1847 /* XXX are any DL? */
1848 radeon_add_legacy_connector(dev, 0,
1849 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ) |
1850 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1851 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
1852 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
1853 &hpd);
1854 /* TV - TV DAC */
1855 ddc_i2c.valid = false0;
1856 hpd.hpd = RADEON_HPD_NONE;
1857 radeon_add_legacy_encoder(dev,
1858 radeon_get_encoder_enum(dev,
1859 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1860 2),
1861 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1862 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1863 DRM_MODE_CONNECTOR_SVIDEO6,
1864 &ddc_i2c,
1865 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1866 &hpd);
1867 break;
1868 case CT_MINI_INTERNAL:
1869 DRM_INFO("Connector Table: %d (mini internal tmds)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mini internal tmds)\n"
, rdev->mode_info.connector_table)
1870 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mini internal tmds)\n"
, rdev->mode_info.connector_table)
;
1871 /* DVI-I - tv dac, int tmds */
1872 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1873 hpd.hpd = RADEON_HPD_1; /* ??? */
1874 radeon_add_legacy_encoder(dev,
1875 radeon_get_encoder_enum(dev,
1876 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
1877 0),
1878 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
1879 radeon_add_legacy_encoder(dev,
1880 radeon_get_encoder_enum(dev,
1881 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1882 2),
1883 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
1884 radeon_add_legacy_connector(dev, 0,
1885 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) |
1886 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1887 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
1888 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
1889 &hpd);
1890 /* TV - TV DAC */
1891 ddc_i2c.valid = false0;
1892 hpd.hpd = RADEON_HPD_NONE;
1893 radeon_add_legacy_encoder(dev,
1894 radeon_get_encoder_enum(dev,
1895 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1896 2),
1897 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1898 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1899 DRM_MODE_CONNECTOR_SVIDEO6,
1900 &ddc_i2c,
1901 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1902 &hpd);
1903 break;
1904 case CT_IMAC_G5_ISIGHT:
1905 DRM_INFO("Connector Table: %d (imac g5 isight)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (imac g5 isight)\n"
, rdev->mode_info.connector_table)
1906 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (imac g5 isight)\n"
, rdev->mode_info.connector_table)
;
1907 /* DVI-D - int tmds */
1908 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1909 hpd.hpd = RADEON_HPD_1; /* ??? */
1910 radeon_add_legacy_encoder(dev,
1911 radeon_get_encoder_enum(dev,
1912 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
1913 0),
1914 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
1915 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
1916 DRM_MODE_CONNECTOR_DVID3, &ddc_i2c,
1917 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D0x03,
1918 &hpd);
1919 /* VGA - tv dac */
1920 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1921 hpd.hpd = RADEON_HPD_NONE;
1922 radeon_add_legacy_encoder(dev,
1923 radeon_get_encoder_enum(dev,
1924 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1925 2),
1926 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
1927 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1928 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
1929 CONNECTOR_OBJECT_ID_VGA0x05,
1930 &hpd);
1931 /* TV - TV DAC */
1932 ddc_i2c.valid = false0;
1933 hpd.hpd = RADEON_HPD_NONE;
1934 radeon_add_legacy_encoder(dev,
1935 radeon_get_encoder_enum(dev,
1936 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1937 2),
1938 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1939 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1940 DRM_MODE_CONNECTOR_SVIDEO6,
1941 &ddc_i2c,
1942 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1943 &hpd);
1944 break;
1945 case CT_EMAC:
1946 DRM_INFO("Connector Table: %d (emac)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (emac)\n",
rdev->mode_info.connector_table)
1947 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (emac)\n",
rdev->mode_info.connector_table)
;
1948 /* VGA - primary dac */
1949 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1950 hpd.hpd = RADEON_HPD_NONE;
1951 radeon_add_legacy_encoder(dev,
1952 radeon_get_encoder_enum(dev,
1953 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1954 1),
1955 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
1956 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1957 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
1958 CONNECTOR_OBJECT_ID_VGA0x05,
1959 &hpd);
1960 /* VGA - tv dac */
1961 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1962 hpd.hpd = RADEON_HPD_NONE;
1963 radeon_add_legacy_encoder(dev,
1964 radeon_get_encoder_enum(dev,
1965 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1966 2),
1967 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
1968 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
1969 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
1970 CONNECTOR_OBJECT_ID_VGA0x05,
1971 &hpd);
1972 /* TV - TV DAC */
1973 ddc_i2c.valid = false0;
1974 hpd.hpd = RADEON_HPD_NONE;
1975 radeon_add_legacy_encoder(dev,
1976 radeon_get_encoder_enum(dev,
1977 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1978 2),
1979 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
1980 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
1981 DRM_MODE_CONNECTOR_SVIDEO6,
1982 &ddc_i2c,
1983 CONNECTOR_OBJECT_ID_SVIDEO0x07,
1984 &hpd);
1985 break;
1986 case CT_RN50_POWER:
1987 DRM_INFO("Connector Table: %d (rn50-power)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (rn50-power)\n"
, rdev->mode_info.connector_table)
1988 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (rn50-power)\n"
, rdev->mode_info.connector_table)
;
1989 /* VGA - primary dac */
1990 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1991 hpd.hpd = RADEON_HPD_NONE;
1992 radeon_add_legacy_encoder(dev,
1993 radeon_get_encoder_enum(dev,
1994 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1995 1),
1996 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
1997 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
1998 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
1999 CONNECTOR_OBJECT_ID_VGA0x05,
2000 &hpd);
2001 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2002 hpd.hpd = RADEON_HPD_NONE;
2003 radeon_add_legacy_encoder(dev,
2004 radeon_get_encoder_enum(dev,
2005 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2006 2),
2007 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
2008 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2009 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
2010 CONNECTOR_OBJECT_ID_VGA0x05,
2011 &hpd);
2012 break;
2013 case CT_MAC_X800:
2014 DRM_INFO("Connector Table: %d (mac x800)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mac x800)\n"
, rdev->mode_info.connector_table)
2015 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mac x800)\n"
, rdev->mode_info.connector_table)
;
2016 /* DVI - primary dac, internal tmds */
2017 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2018 hpd.hpd = RADEON_HPD_1; /* ??? */
2019 radeon_add_legacy_encoder(dev,
2020 radeon_get_encoder_enum(dev,
2021 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
2022 0),
2023 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
2024 radeon_add_legacy_encoder(dev,
2025 radeon_get_encoder_enum(dev,
2026 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2027 1),
2028 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
2029 radeon_add_legacy_connector(dev, 0,
2030 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) |
2031 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2032 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
2033 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
2034 &hpd);
2035 /* DVI - tv dac, dvo */
2036 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2037 hpd.hpd = RADEON_HPD_2; /* ??? */
2038 radeon_add_legacy_encoder(dev,
2039 radeon_get_encoder_enum(dev,
2040 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ),
2041 0),
2042 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ));
2043 radeon_add_legacy_encoder(dev,
2044 radeon_get_encoder_enum(dev,
2045 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2046 2),
2047 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
2048 radeon_add_legacy_connector(dev, 1,
2049 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ) |
2050 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2051 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
2052 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I0x02,
2053 &hpd);
2054 break;
2055 case CT_MAC_G5_9600:
2056 DRM_INFO("Connector Table: %d (mac g5 9600)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mac g5 9600)\n"
, rdev->mode_info.connector_table)
2057 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mac g5 9600)\n"
, rdev->mode_info.connector_table)
;
2058 /* DVI - tv dac, dvo */
2059 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2060 hpd.hpd = RADEON_HPD_1; /* ??? */
2061 radeon_add_legacy_encoder(dev,
2062 radeon_get_encoder_enum(dev,
2063 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ),
2064 0),
2065 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ));
2066 radeon_add_legacy_encoder(dev,
2067 radeon_get_encoder_enum(dev,
2068 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2069 2),
2070 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
2071 radeon_add_legacy_connector(dev, 0,
2072 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ) |
2073 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2074 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
2075 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
2076 &hpd);
2077 /* ADC - primary dac, internal tmds */
2078 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2079 hpd.hpd = RADEON_HPD_2; /* ??? */
2080 radeon_add_legacy_encoder(dev,
2081 radeon_get_encoder_enum(dev,
2082 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
2083 0),
2084 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
2085 radeon_add_legacy_encoder(dev,
2086 radeon_get_encoder_enum(dev,
2087 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2088 1),
2089 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
2090 radeon_add_legacy_connector(dev, 1,
2091 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) |
2092 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2093 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
2094 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
2095 &hpd);
2096 /* TV - TV DAC */
2097 ddc_i2c.valid = false0;
2098 hpd.hpd = RADEON_HPD_NONE;
2099 radeon_add_legacy_encoder(dev,
2100 radeon_get_encoder_enum(dev,
2101 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2102 2),
2103 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
2104 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2105 DRM_MODE_CONNECTOR_SVIDEO6,
2106 &ddc_i2c,
2107 CONNECTOR_OBJECT_ID_SVIDEO0x07,
2108 &hpd);
2109 break;
2110 case CT_SAM440EP:
2111 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (SAM440ep embedded board)\n"
, rdev->mode_info.connector_table)
2112 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (SAM440ep embedded board)\n"
, rdev->mode_info.connector_table)
;
2113 /* LVDS */
2114 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2115 hpd.hpd = RADEON_HPD_NONE;
2116 radeon_add_legacy_encoder(dev,
2117 radeon_get_encoder_enum(dev,
2118 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
2119 0),
2120 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ));
2121 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
2122 DRM_MODE_CONNECTOR_LVDS7, &ddc_i2c,
2123 CONNECTOR_OBJECT_ID_LVDS0x0E,
2124 &hpd);
2125 /* DVI-I - secondary dac, int tmds */
2126 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2127 hpd.hpd = RADEON_HPD_1; /* ??? */
2128 radeon_add_legacy_encoder(dev,
2129 radeon_get_encoder_enum(dev,
2130 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
2131 0),
2132 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
2133 radeon_add_legacy_encoder(dev,
2134 radeon_get_encoder_enum(dev,
2135 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2136 2),
2137 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
2138 radeon_add_legacy_connector(dev, 1,
2139 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) |
2140 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2141 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
2142 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
2143 &hpd);
2144 /* VGA - primary dac */
2145 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2146 hpd.hpd = RADEON_HPD_NONE;
2147 radeon_add_legacy_encoder(dev,
2148 radeon_get_encoder_enum(dev,
2149 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2150 1),
2151 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
2152 radeon_add_legacy_connector(dev, 2,
2153 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2154 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
2155 CONNECTOR_OBJECT_ID_VGA0x05,
2156 &hpd);
2157 /* TV - TV DAC */
2158 ddc_i2c.valid = false0;
2159 hpd.hpd = RADEON_HPD_NONE;
2160 radeon_add_legacy_encoder(dev,
2161 radeon_get_encoder_enum(dev,
2162 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2163 2),
2164 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
2165 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2166 DRM_MODE_CONNECTOR_SVIDEO6,
2167 &ddc_i2c,
2168 CONNECTOR_OBJECT_ID_SVIDEO0x07,
2169 &hpd);
2170 break;
2171 case CT_MAC_G4_SILVER:
2172 DRM_INFO("Connector Table: %d (mac g4 silver)\n",printk("\0016" "[" "drm" "] " "Connector Table: %d (mac g4 silver)\n"
, rdev->mode_info.connector_table)
2173 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector Table: %d (mac g4 silver)\n"
, rdev->mode_info.connector_table)
;
2174 /* DVI-I - tv dac, int tmds */
2175 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2176 hpd.hpd = RADEON_HPD_1; /* ??? */
2177 radeon_add_legacy_encoder(dev,
2178 radeon_get_encoder_enum(dev,
2179 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
2180 0),
2181 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
2182 radeon_add_legacy_encoder(dev,
2183 radeon_get_encoder_enum(dev,
2184 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2185 2),
2186 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
2187 radeon_add_legacy_connector(dev, 0,
2188 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ) |
2189 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2190 DRM_MODE_CONNECTOR_DVII2, &ddc_i2c,
2191 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
2192 &hpd);
2193 /* VGA - primary dac */
2194 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2195 hpd.hpd = RADEON_HPD_NONE;
2196 radeon_add_legacy_encoder(dev,
2197 radeon_get_encoder_enum(dev,
2198 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2199 1),
2200 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
2201 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2202 DRM_MODE_CONNECTOR_VGA1, &ddc_i2c,
2203 CONNECTOR_OBJECT_ID_VGA0x05,
2204 &hpd);
2205 /* TV - TV DAC */
2206 ddc_i2c.valid = false0;
2207 hpd.hpd = RADEON_HPD_NONE;
2208 radeon_add_legacy_encoder(dev,
2209 radeon_get_encoder_enum(dev,
2210 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2211 2),
2212 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
2213 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2214 DRM_MODE_CONNECTOR_SVIDEO6,
2215 &ddc_i2c,
2216 CONNECTOR_OBJECT_ID_SVIDEO0x07,
2217 &hpd);
2218 break;
2219 default:
2220 DRM_INFO("Connector table: %d (invalid)\n",printk("\0016" "[" "drm" "] " "Connector table: %d (invalid)\n"
, rdev->mode_info.connector_table)
2221 rdev->mode_info.connector_table)printk("\0016" "[" "drm" "] " "Connector table: %d (invalid)\n"
, rdev->mode_info.connector_table)
;
2222 return false0;
2223 }
2224
2225 radeon_link_encoder_connector(dev);
2226
2227 return true1;
2228}
2229
2230static bool_Bool radeon_apply_legacy_quirks(struct drm_device *dev,
2231 int bios_index,
2232 enum radeon_combios_connector
2233 *legacy_connector,
2234 struct radeon_i2c_bus_rec *ddc_i2c,
2235 struct radeon_hpd *hpd)
2236{
2237
2238 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2239 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2240 if (dev->pdev->device == 0x515e &&
2241 dev->pdev->subsystem_vendor == 0x1014) {
2242 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2243 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC0x006c)
2244 return false0;
2245 }
2246
2247 /* X300 card with extra non-existent DVI port */
2248 if (dev->pdev->device == 0x5B60 &&
2249 dev->pdev->subsystem_vendor == 0x17af &&
2250 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2251 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2252 return false0;
2253 }
2254
2255 return true1;
2256}
2257
2258static bool_Bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2259{
2260 /* Acer 5102 has non-existent TV port */
2261 if (dev->pdev->device == 0x5975 &&
2262 dev->pdev->subsystem_vendor == 0x1025 &&
2263 dev->pdev->subsystem_device == 0x009f)
2264 return false0;
2265
2266 /* HP dc5750 has non-existent TV port */
2267 if (dev->pdev->device == 0x5974 &&
2268 dev->pdev->subsystem_vendor == 0x103c &&
2269 dev->pdev->subsystem_device == 0x280a)
2270 return false0;
2271
2272 /* MSI S270 has non-existent TV port */
2273 if (dev->pdev->device == 0x5955 &&
2274 dev->pdev->subsystem_vendor == 0x1462 &&
2275 dev->pdev->subsystem_device == 0x0131)
2276 return false0;
2277
2278 return true1;
2279}
2280
2281static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2282{
2283 struct radeon_device *rdev = dev->dev_private;
2284 uint32_t ext_tmds_info;
2285
2286 if (rdev->flags & RADEON_IS_IGP) {
2287 if (is_dvi_d)
2288 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D0x03;
2289 else
2290 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01;
2291 }
2292 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2293 if (ext_tmds_info) {
2294 uint8_t rev = RBIOS8(ext_tmds_info)(rdev->bios[ext_tmds_info]);
2295 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5)(rdev->bios[ext_tmds_info + 4 + 5]);
2296 if (rev >= 3) {
2297 if (is_dvi_d)
2298 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D0x04;
2299 else
2300 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I0x02;
2301 } else {
2302 if (flags & 1) {
2303 if (is_dvi_d)
2304 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D0x04;
2305 else
2306 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I0x02;
2307 }
2308 }
2309 }
2310 if (is_dvi_d)
2311 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D0x03;
2312 else
2313 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01;
2314}
2315
2316bool_Bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2317{
2318 struct radeon_device *rdev = dev->dev_private;
2319 uint32_t conn_info, entry, devices;
2320 uint16_t tmp, connector_object_id;
2321 enum radeon_combios_ddc ddc_type;
2322 enum radeon_combios_connector connector;
2323 int i = 0;
2324 struct radeon_i2c_bus_rec ddc_i2c;
2325 struct radeon_hpd hpd;
2326
2327 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2328 if (conn_info) {
2329 for (i = 0; i < 4; i++) {
2330 entry = conn_info + 2 + i * 2;
2331
2332 if (!RBIOS16(entry)((rdev->bios[entry]) | ((rdev->bios[(entry)+1]) <<
8))
)
2333 break;
2334
2335 tmp = RBIOS16(entry)((rdev->bios[entry]) | ((rdev->bios[(entry)+1]) <<
8))
;
2336
2337 connector = (tmp >> 12) & 0xf;
2338
2339 ddc_type = (tmp >> 8) & 0xf;
2340 if (ddc_type == 5)
2341 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2342 else
2343 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2344
2345 switch (connector) {
2346 case CONNECTOR_PROPRIETARY_LEGACY:
2347 case CONNECTOR_DVI_I_LEGACY:
2348 case CONNECTOR_DVI_D_LEGACY:
2349 if ((tmp >> 4) & 0x1)
2350 hpd.hpd = RADEON_HPD_2;
2351 else
2352 hpd.hpd = RADEON_HPD_1;
2353 break;
2354 default:
2355 hpd.hpd = RADEON_HPD_NONE;
2356 break;
2357 }
2358
2359 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2360 &ddc_i2c, &hpd))
2361 continue;
2362
2363 switch (connector) {
2364 case CONNECTOR_PROPRIETARY_LEGACY:
2365 if ((tmp >> 4) & 0x1)
2366 devices = ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 );
2367 else
2368 devices = ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 );
2369 radeon_add_legacy_encoder(dev,
2370 radeon_get_encoder_enum
2371 (dev, devices, 0),
2372 devices);
2373 radeon_add_legacy_connector(dev, i, devices,
2374 legacy_connector_convert
2375 [connector],
2376 &ddc_i2c,
2377 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D0x03,
2378 &hpd);
2379 break;
2380 case CONNECTOR_CRT_LEGACY:
2381 if (tmp & 0x1) {
2382 devices = ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 );
2383 radeon_add_legacy_encoder(dev,
2384 radeon_get_encoder_enum
2385 (dev,
2386 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2387 2),
2388 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
2389 } else {
2390 devices = ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 );
2391 radeon_add_legacy_encoder(dev,
2392 radeon_get_encoder_enum
2393 (dev,
2394 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2395 1),
2396 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
2397 }
2398 radeon_add_legacy_connector(dev,
2399 i,
2400 devices,
2401 legacy_connector_convert
2402 [connector],
2403 &ddc_i2c,
2404 CONNECTOR_OBJECT_ID_VGA0x05,
2405 &hpd);
2406 break;
2407 case CONNECTOR_DVI_I_LEGACY:
2408 devices = 0;
2409 if (tmp & 0x1) {
2410 devices |= ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 );
2411 radeon_add_legacy_encoder(dev,
2412 radeon_get_encoder_enum
2413 (dev,
2414 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ),
2415 2),
2416 ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ));
2417 } else {
2418 devices |= ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 );
2419 radeon_add_legacy_encoder(dev,
2420 radeon_get_encoder_enum
2421 (dev,
2422 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2423 1),
2424 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
2425 }
2426 /* RV100 board with external TDMS bit mis-set.
2427 * Actually uses internal TMDS, clear the bit.
2428 */
2429 if (dev->pdev->device == 0x5159 &&
2430 dev->pdev->subsystem_vendor == 0x1014 &&
2431 dev->pdev->subsystem_device == 0x029A) {
2432 tmp &= ~(1 << 4);
2433 }
2434 if ((tmp >> 4) & 0x1) {
2435 devices |= ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 );
2436 radeon_add_legacy_encoder(dev,
2437 radeon_get_encoder_enum
2438 (dev,
2439 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ),
2440 0),
2441 ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ));
2442 connector_object_id = combios_check_dl_dvi(dev, 0);
2443 } else {
2444 devices |= ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 );
2445 radeon_add_legacy_encoder(dev,
2446 radeon_get_encoder_enum
2447 (dev,
2448 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
2449 0),
2450 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
2451 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01;
2452 }
2453 radeon_add_legacy_connector(dev,
2454 i,
2455 devices,
2456 legacy_connector_convert
2457 [connector],
2458 &ddc_i2c,
2459 connector_object_id,
2460 &hpd);
2461 break;
2462 case CONNECTOR_DVI_D_LEGACY:
2463 if ((tmp >> 4) & 0x1) {
2464 devices = ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 );
2465 connector_object_id = combios_check_dl_dvi(dev, 1);
2466 } else {
2467 devices = ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 );
2468 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01;
2469 }
2470 radeon_add_legacy_encoder(dev,
2471 radeon_get_encoder_enum
2472 (dev, devices, 0),
2473 devices);
2474 radeon_add_legacy_connector(dev, i, devices,
2475 legacy_connector_convert
2476 [connector],
2477 &ddc_i2c,
2478 connector_object_id,
2479 &hpd);
2480 break;
2481 case CONNECTOR_CTV_LEGACY:
2482 case CONNECTOR_STV_LEGACY:
2483 radeon_add_legacy_encoder(dev,
2484 radeon_get_encoder_enum
2485 (dev,
2486 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2487 2),
2488 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
2489 radeon_add_legacy_connector(dev, i,
2490 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2491 legacy_connector_convert
2492 [connector],
2493 &ddc_i2c,
2494 CONNECTOR_OBJECT_ID_SVIDEO0x07,
2495 &hpd);
2496 break;
2497 default:
2498 DRM_ERROR("Unknown connector type: %d\n",__drm_err("Unknown connector type: %d\n", connector)
2499 connector)__drm_err("Unknown connector type: %d\n", connector);
2500 continue;
2501 }
2502
2503 }
2504 } else {
2505 uint16_t tmds_info =
2506 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2507 if (tmds_info) {
2508 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n")__drm_dbg(DRM_UT_KMS, "Found DFP table, assuming DVI connector\n"
)
;
2509
2510 radeon_add_legacy_encoder(dev,
2511 radeon_get_encoder_enum(dev,
2512 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2513 1),
2514 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
2515 radeon_add_legacy_encoder(dev,
2516 radeon_get_encoder_enum(dev,
2517 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
2518 0),
2519 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ));
2520
2521 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2522 hpd.hpd = RADEON_HPD_1;
2523 radeon_add_legacy_connector(dev,
2524 0,
2525 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ) |
2526 ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ),
2527 DRM_MODE_CONNECTOR_DVII2,
2528 &ddc_i2c,
2529 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I0x01,
2530 &hpd);
2531 } else {
2532 uint16_t crt_info =
2533 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2534 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n")__drm_dbg(DRM_UT_KMS, "Found CRT table, assuming VGA connector\n"
)
;
2535 if (crt_info) {
2536 radeon_add_legacy_encoder(dev,
2537 radeon_get_encoder_enum(dev,
2538 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2539 1),
2540 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ));
2541 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2542 hpd.hpd = RADEON_HPD_NONE;
2543 radeon_add_legacy_connector(dev,
2544 0,
2545 ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ),
2546 DRM_MODE_CONNECTOR_VGA1,
2547 &ddc_i2c,
2548 CONNECTOR_OBJECT_ID_VGA0x05,
2549 &hpd);
2550 } else {
2551 DRM_DEBUG_KMS("No connector info found\n")__drm_dbg(DRM_UT_KMS, "No connector info found\n");
2552 return false0;
2553 }
2554 }
2555 }
2556
2557 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2558 uint16_t lcd_info =
2559 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2560 if (lcd_info) {
2561 uint16_t lcd_ddc_info =
2562 combios_get_table_offset(dev,
2563 COMBIOS_LCD_DDC_INFO_TABLE);
2564
2565 radeon_add_legacy_encoder(dev,
2566 radeon_get_encoder_enum(dev,
2567 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
2568 0),
2569 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ));
2570
2571 if (lcd_ddc_info) {
2572 ddc_type = RBIOS8(lcd_ddc_info + 2)(rdev->bios[lcd_ddc_info + 2]);
2573 switch (ddc_type) {
2574 case DDC_LCD:
2575 ddc_i2c =
2576 combios_setup_i2c_bus(rdev,
2577 DDC_LCD,
2578 RBIOS32(lcd_ddc_info + 3)((((rdev->bios[lcd_ddc_info + 3]) | ((rdev->bios[(lcd_ddc_info
+ 3)+1]) << 8))) | (((rdev->bios[(lcd_ddc_info + 3)
+2]) | ((rdev->bios[((lcd_ddc_info + 3)+2)+1]) << 8)
) << 16))
,
2579 RBIOS32(lcd_ddc_info + 7)((((rdev->bios[lcd_ddc_info + 7]) | ((rdev->bios[(lcd_ddc_info
+ 7)+1]) << 8))) | (((rdev->bios[(lcd_ddc_info + 7)
+2]) | ((rdev->bios[((lcd_ddc_info + 7)+2)+1]) << 8)
) << 16))
);
2580 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2581 break;
2582 case DDC_GPIO:
2583 ddc_i2c =
2584 combios_setup_i2c_bus(rdev,
2585 DDC_GPIO,
2586 RBIOS32(lcd_ddc_info + 3)((((rdev->bios[lcd_ddc_info + 3]) | ((rdev->bios[(lcd_ddc_info
+ 3)+1]) << 8))) | (((rdev->bios[(lcd_ddc_info + 3)
+2]) | ((rdev->bios[((lcd_ddc_info + 3)+2)+1]) << 8)
) << 16))
,
2587 RBIOS32(lcd_ddc_info + 7)((((rdev->bios[lcd_ddc_info + 7]) | ((rdev->bios[(lcd_ddc_info
+ 7)+1]) << 8))) | (((rdev->bios[(lcd_ddc_info + 7)
+2]) | ((rdev->bios[((lcd_ddc_info + 7)+2)+1]) << 8)
) << 16))
);
2588 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2589 break;
2590 default:
2591 ddc_i2c =
2592 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2593 break;
2594 }
2595 DRM_DEBUG_KMS("LCD DDC Info Table found!\n")__drm_dbg(DRM_UT_KMS, "LCD DDC Info Table found!\n");
2596 } else
2597 ddc_i2c.valid = false0;
2598
2599 hpd.hpd = RADEON_HPD_NONE;
2600 radeon_add_legacy_connector(dev,
2601 5,
2602 ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ),
2603 DRM_MODE_CONNECTOR_LVDS7,
2604 &ddc_i2c,
2605 CONNECTOR_OBJECT_ID_LVDS0x0E,
2606 &hpd);
2607 }
2608 }
2609
2610 /* check TV table */
2611 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2612 uint32_t tv_info =
2613 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2614 if (tv_info) {
2615 if (RBIOS8(tv_info + 6)(rdev->bios[tv_info + 6]) == 'T') {
2616 if (radeon_apply_legacy_tv_quirks(dev)) {
2617 hpd.hpd = RADEON_HPD_NONE;
2618 ddc_i2c.valid = false0;
2619 radeon_add_legacy_encoder(dev,
2620 radeon_get_encoder_enum
2621 (dev,
2622 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2623 2),
2624 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ));
2625 radeon_add_legacy_connector(dev, 6,
2626 ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ),
2627 DRM_MODE_CONNECTOR_SVIDEO6,
2628 &ddc_i2c,
2629 CONNECTOR_OBJECT_ID_SVIDEO0x07,
2630 &hpd);
2631 }
2632 }
2633 }
2634 }
2635
2636 radeon_link_encoder_connector(dev);
2637
2638 return true1;
2639}
2640
2641static const char *thermal_controller_names[] = {
2642 "NONE",
2643 "lm63",
2644 "adm1032",
2645};
2646
2647void radeon_combios_get_power_modes(struct radeon_device *rdev)
2648{
2649 struct drm_device *dev = rdev->ddev;
2650 u16 offset, misc, misc2 = 0;
2651 u8 rev, tmp;
2652 int state_index = 0;
2653 struct radeon_i2c_bus_rec i2c_bus;
2654
2655 rdev->pm.default_power_state_index = -1;
2656
2657 /* allocate 2 power states */
2658 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state),
2659 GFP_KERNEL(0x0001 | 0x0004));
2660 if (rdev->pm.power_state) {
2661 /* allocate 1 clock mode per state */
2662 rdev->pm.power_state[0].clock_info =
2663 kcalloc(1, sizeof(struct radeon_pm_clock_info),
2664 GFP_KERNEL(0x0001 | 0x0004));
2665 rdev->pm.power_state[1].clock_info =
2666 kcalloc(1, sizeof(struct radeon_pm_clock_info),
2667 GFP_KERNEL(0x0001 | 0x0004));
2668 if (!rdev->pm.power_state[0].clock_info ||
2669 !rdev->pm.power_state[1].clock_info)
2670 goto pm_failed;
2671 } else
2672 goto pm_failed;
2673
2674 /* check for a thermal chip */
2675 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2676 if (offset) {
2677 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2678
2679 rev = RBIOS8(offset)(rdev->bios[offset]);
2680
2681 if (rev == 0) {
2682 thermal_controller = RBIOS8(offset + 3)(rdev->bios[offset + 3]);
2683 gpio = RBIOS8(offset + 4)(rdev->bios[offset + 4]) & 0x3f;
2684 i2c_addr = RBIOS8(offset + 5)(rdev->bios[offset + 5]);
2685 } else if (rev == 1) {
2686 thermal_controller = RBIOS8(offset + 4)(rdev->bios[offset + 4]);
2687 gpio = RBIOS8(offset + 5)(rdev->bios[offset + 5]) & 0x3f;
2688 i2c_addr = RBIOS8(offset + 6)(rdev->bios[offset + 6]);
2689 } else if (rev == 2) {
2690 thermal_controller = RBIOS8(offset + 4)(rdev->bios[offset + 4]);
2691 gpio = RBIOS8(offset + 5)(rdev->bios[offset + 5]) & 0x3f;
2692 i2c_addr = RBIOS8(offset + 6)(rdev->bios[offset + 6]);
2693 clk_bit = RBIOS8(offset + 0xa)(rdev->bios[offset + 0xa]);
2694 data_bit = RBIOS8(offset + 0xb)(rdev->bios[offset + 0xb]);
2695 }
2696 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2697 DRM_INFO("Possible %s thermal controller at 0x%02x\n",printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n"
, thermal_controller_names[thermal_controller], i2c_addr >>
1)
2698 thermal_controller_names[thermal_controller],printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n"
, thermal_controller_names[thermal_controller], i2c_addr >>
1)
2699 i2c_addr >> 1)printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n"
, thermal_controller_names[thermal_controller], i2c_addr >>
1)
;
2700 if (gpio == DDC_LCD) {
2701 /* MM i2c */
2702 i2c_bus.valid = true1;
2703 i2c_bus.hw_capable = true1;
2704 i2c_bus.mm_i2c = true1;
2705 i2c_bus.i2c_id = 0xa0;
2706 } else if (gpio == DDC_GPIO)
2707 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2708 else
2709 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2710 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2711#ifdef notyet
2712 if (rdev->pm.i2c_bus) {
2713 struct i2c_board_info info = { };
2714 const char *name = thermal_controller_names[thermal_controller];
2715 info.addr = i2c_addr >> 1;
2716 strlcpy(info.type, name, sizeof(info.type));
2717 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2718 }
2719#endif
2720 }
2721 } else {
2722 /* boards with a thermal chip, but no overdrive table */
2723
2724 /* Asus 9600xt has an f75375 on the monid bus */
2725 if ((dev->pdev->device == 0x4152) &&
2726 (dev->pdev->subsystem_vendor == 0x1043) &&
2727 (dev->pdev->subsystem_device == 0xc002)) {
2728 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2729 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2730#ifdef notyet
2731 if (rdev->pm.i2c_bus) {
2732 struct i2c_board_info info = { };
2733 const char *name = "f75375";
2734 info.addr = 0x28;
2735 strlcpy(info.type, name, sizeof(info.type));
2736 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2737 DRM_INFO("Possible %s thermal controller at 0x%02x\n",printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n"
, name, info.addr)
2738 name, info.addr)printk("\0016" "[" "drm" "] " "Possible %s thermal controller at 0x%02x\n"
, name, info.addr)
;
2739 }
2740#endif
2741 }
2742 }
2743
2744 if (rdev->flags & RADEON_IS_MOBILITY) {
2745 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2746 if (offset) {
2747 rev = RBIOS8(offset)(rdev->bios[offset]);
2748 /* power mode 0 tends to be the only valid one */
2749 rdev->pm.power_state[state_index].num_clock_modes = 1;
2750 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2)((((rdev->bios[offset + 0x5 + 0x2]) | ((rdev->bios[(offset
+ 0x5 + 0x2)+1]) << 8))) | (((rdev->bios[(offset + 0x5
+ 0x2)+2]) | ((rdev->bios[((offset + 0x5 + 0x2)+2)+1]) <<
8)) << 16))
;
2751 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6)((((rdev->bios[offset + 0x5 + 0x6]) | ((rdev->bios[(offset
+ 0x5 + 0x6)+1]) << 8))) | (((rdev->bios[(offset + 0x5
+ 0x6)+2]) | ((rdev->bios[((offset + 0x5 + 0x6)+2)+1]) <<
8)) << 16))
;
2752 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2753 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2754 goto default_mode;
2755 rdev->pm.power_state[state_index].type =
2756 POWER_STATE_TYPE_BATTERY;
2757 misc = RBIOS16(offset + 0x5 + 0x0)((rdev->bios[offset + 0x5 + 0x0]) | ((rdev->bios[(offset
+ 0x5 + 0x0)+1]) << 8))
;
2758 if (rev > 4)
2759 misc2 = RBIOS16(offset + 0x5 + 0xe)((rdev->bios[offset + 0x5 + 0xe]) | ((rdev->bios[(offset
+ 0x5 + 0xe)+1]) << 8))
;
2760 rdev->pm.power_state[state_index].misc = misc;
2761 rdev->pm.power_state[state_index].misc2 = misc2;
2762 if (misc & 0x4) {
2763 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2764 if (misc & 0x8)
2765 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2766 true1;
2767 else
2768 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2769 false0;
2770 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true1;
2771 if (rev < 6) {
2772 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2773 RBIOS16(offset + 0x5 + 0xb)((rdev->bios[offset + 0x5 + 0xb]) | ((rdev->bios[(offset
+ 0x5 + 0xb)+1]) << 8))
* 4;
2774 tmp = RBIOS8(offset + 0x5 + 0xd)(rdev->bios[offset + 0x5 + 0xd]);
2775 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2776 } else {
2777 u8 entries = RBIOS8(offset + 0x5 + 0xb)(rdev->bios[offset + 0x5 + 0xb]);
2778 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc)((rdev->bios[offset + 0x5 + 0xc]) | ((rdev->bios[(offset
+ 0x5 + 0xc)+1]) << 8))
;
2779 if (entries && voltage_table_offset) {
2780 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2781 RBIOS16(voltage_table_offset)((rdev->bios[voltage_table_offset]) | ((rdev->bios[(voltage_table_offset
)+1]) << 8))
* 4;
2782 tmp = RBIOS8(voltage_table_offset + 0x2)(rdev->bios[voltage_table_offset + 0x2]);
2783 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2784 } else
2785 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false0;
2786 }
2787 switch ((misc2 & 0x700) >> 8) {
2788 case 0:
2789 default:
2790 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2791 break;
2792 case 1:
2793 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2794 break;
2795 case 2:
2796 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2797 break;
2798 case 3:
2799 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2800 break;
2801 case 4:
2802 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2803 break;
2804 }
2805 } else
2806 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2807 if (rev > 6)
2808 rdev->pm.power_state[state_index].pcie_lanes =
2809 RBIOS8(offset + 0x5 + 0x10)(rdev->bios[offset + 0x5 + 0x10]);
2810 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY(1 << 0);
2811 state_index++;
2812 } else {
2813 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2814 }
2815 } else {
2816 /* XXX figure out some good default low power mode for desktop cards */
2817 }
2818
2819default_mode:
2820 /* add the default mode */
2821 rdev->pm.power_state[state_index].type =
2822 POWER_STATE_TYPE_DEFAULT;
2823 rdev->pm.power_state[state_index].num_clock_modes = 1;
2824 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2825 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2826 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2827 if ((state_index > 0) &&
2828 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2829 rdev->pm.power_state[state_index].clock_info[0].voltage =
2830 rdev->pm.power_state[0].clock_info[0].voltage;
2831 else
2832 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2833 rdev->pm.power_state[state_index].pcie_lanes = 16;
2834 rdev->pm.power_state[state_index].flags = 0;
2835 rdev->pm.default_power_state_index = state_index;
2836 rdev->pm.num_power_states = state_index + 1;
2837
2838 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2839 rdev->pm.current_clock_mode_index = 0;
2840 return;
2841
2842pm_failed:
2843 rdev->pm.default_power_state_index = state_index;
2844 rdev->pm.num_power_states = 0;
2845
2846 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2847 rdev->pm.current_clock_mode_index = 0;
2848}
2849
2850void radeon_external_tmds_setup(struct drm_encoder *encoder)
2851{
2852 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );})
;
2853 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2854
2855 if (!tmds)
2856 return;
2857
2858 switch (tmds->dvo_chip) {
2859 case DVO_SIL164:
2860 /* sil 164 */
2861 radeon_i2c_put_byte(tmds->i2c_bus,
2862 tmds->slave_addr,
2863 0x08, 0x30);
2864 radeon_i2c_put_byte(tmds->i2c_bus,
2865 tmds->slave_addr,
2866 0x09, 0x00);
2867 radeon_i2c_put_byte(tmds->i2c_bus,
2868 tmds->slave_addr,
2869 0x0a, 0x90);
2870 radeon_i2c_put_byte(tmds->i2c_bus,
2871 tmds->slave_addr,
2872 0x0c, 0x89);
2873 radeon_i2c_put_byte(tmds->i2c_bus,
2874 tmds->slave_addr,
2875 0x08, 0x3b);
2876 break;
2877 case DVO_SIL1178:
2878 /* sil 1178 - untested */
2879 /*
2880 * 0x0f, 0x44
2881 * 0x0f, 0x4c
2882 * 0x0e, 0x01
2883 * 0x0a, 0x80
2884 * 0x09, 0x30
2885 * 0x0c, 0xc9
2886 * 0x0d, 0x70
2887 * 0x08, 0x32
2888 * 0x08, 0x33
2889 */
2890 break;
2891 default:
2892 break;
2893 }
2894
2895}
2896
2897bool_Bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2898{
2899 struct drm_device *dev = encoder->dev;
2900 struct radeon_device *rdev = dev->dev_private;
2901 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );})
;
2902 uint16_t offset;
2903 uint8_t blocks, slave_addr, rev;
2904 uint32_t index, id;
2905 uint32_t reg, val, and_mask, or_mask;
2906 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2907
2908 if (!tmds)
2909 return false0;
2910
2911 if (rdev->flags & RADEON_IS_IGP) {
2912 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2913 rev = RBIOS8(offset)(rdev->bios[offset]);
Value stored to 'rev' is never read
2914 if (offset) {
2915 rev = RBIOS8(offset)(rdev->bios[offset]);
2916 if (rev > 1) {
2917 blocks = RBIOS8(offset + 3)(rdev->bios[offset + 3]);
2918 index = offset + 4;
2919 while (blocks > 0) {
2920 id = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))
;
2921 index += 2;
2922 switch (id >> 13) {
2923 case 0:
2924 reg = (id & 0x1fff) * 4;
2925 val = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index
)+2)+1]) << 8)) << 16))
;
2926 index += 4;
2927 WREG32(reg, val)r100_mm_wreg(rdev, (reg), (val), 0);
2928 break;
2929 case 2:
2930 reg = (id & 0x1fff) * 4;
2931 and_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index
)+2)+1]) << 8)) << 16))
;
2932 index += 4;
2933 or_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index
)+2)+1]) << 8)) << 16))
;
2934 index += 4;
2935 val = RREG32(reg)r100_mm_rreg(rdev, (reg), 0);
2936 val = (val & and_mask) | or_mask;
2937 WREG32(reg, val)r100_mm_wreg(rdev, (reg), (val), 0);
2938 break;
2939 case 3:
2940 val = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))
;
2941 index += 2;
2942 udelay(val);
2943 break;
2944 case 4:
2945 val = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))
;
2946 index += 2;
2947 mdelay(val);
2948 break;
2949 case 6:
2950 slave_addr = id & 0xff;
2951 slave_addr >>= 1; /* 7 bit addressing */
2952 index++;
2953 reg = RBIOS8(index)(rdev->bios[index]);
2954 index++;
2955 val = RBIOS8(index)(rdev->bios[index]);
2956 index++;
2957 radeon_i2c_put_byte(tmds->i2c_bus,
2958 slave_addr,
2959 reg, val);
2960 break;
2961 default:
2962 DRM_ERROR("Unknown id %d\n", id >> 13)__drm_err("Unknown id %d\n", id >> 13);
2963 break;
2964 }
2965 blocks--;
2966 }
2967 return true1;
2968 }
2969 }
2970 } else {
2971 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2972 if (offset) {
2973 index = offset + 10;
2974 id = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))
;
2975 while (id != 0xffff) {
2976 index += 2;
2977 switch (id >> 13) {
2978 case 0:
2979 reg = (id & 0x1fff) * 4;
2980 val = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index
)+2)+1]) << 8)) << 16))
;
2981 WREG32(reg, val)r100_mm_wreg(rdev, (reg), (val), 0);
2982 break;
2983 case 2:
2984 reg = (id & 0x1fff) * 4;
2985 and_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index
)+2)+1]) << 8)) << 16))
;
2986 index += 4;
2987 or_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index
)+2)+1]) << 8)) << 16))
;
2988 index += 4;
2989 val = RREG32(reg)r100_mm_rreg(rdev, (reg), 0);
2990 val = (val & and_mask) | or_mask;
2991 WREG32(reg, val)r100_mm_wreg(rdev, (reg), (val), 0);
2992 break;
2993 case 4:
2994 val = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))
;
2995 index += 2;
2996 udelay(val);
2997 break;
2998 case 5:
2999 reg = id & 0x1fff;
3000 and_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index
)+2)+1]) << 8)) << 16))
;
3001 index += 4;
3002 or_mask = RBIOS32(index)((((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))) | (((rdev->bios[(index)+2]) | ((rdev->bios[((index
)+2)+1]) << 8)) << 16))
;
3003 index += 4;
3004 val = RREG32_PLL(reg)rdev->pll_rreg(rdev, (reg));
3005 val = (val & and_mask) | or_mask;
3006 WREG32_PLL(reg, val)rdev->pll_wreg(rdev, (reg), (val));
3007 break;
3008 case 6:
3009 reg = id & 0x1fff;
3010 val = RBIOS8(index)(rdev->bios[index]);
3011 index += 1;
3012 radeon_i2c_put_byte(tmds->i2c_bus,
3013 tmds->slave_addr,
3014 reg, val);
3015 break;
3016 default:
3017 DRM_ERROR("Unknown id %d\n", id >> 13)__drm_err("Unknown id %d\n", id >> 13);
3018 break;
3019 }
3020 id = RBIOS16(index)((rdev->bios[index]) | ((rdev->bios[(index)+1]) <<
8))
;
3021 }
3022 return true1;
3023 }
3024 }
3025 return false0;
3026}
3027
3028static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3029{
3030 struct radeon_device *rdev = dev->dev_private;
3031
3032 if (offset) {
3033 while (RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))
) {
3034 uint16_t cmd = ((RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))
& 0xe000) >> 13);
3035 uint32_t addr = (RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))
& 0x1fff);
3036 uint32_t val, and_mask, or_mask;
3037 uint32_t tmp;
3038
3039 offset += 2;
3040 switch (cmd) {
3041 case 0:
3042 val = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset
)+2)+1]) << 8)) << 16))
;
3043 offset += 4;
3044 WREG32(addr, val)r100_mm_wreg(rdev, (addr), (val), 0);
3045 break;
3046 case 1:
3047 val = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset
)+2)+1]) << 8)) << 16))
;
3048 offset += 4;
3049 WREG32(addr, val)r100_mm_wreg(rdev, (addr), (val), 0);
3050 break;
3051 case 2:
3052 and_mask = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset
)+2)+1]) << 8)) << 16))
;
3053 offset += 4;
3054 or_mask = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset
)+2)+1]) << 8)) << 16))
;
3055 offset += 4;
3056 tmp = RREG32(addr)r100_mm_rreg(rdev, (addr), 0);
3057 tmp &= and_mask;
3058 tmp |= or_mask;
3059 WREG32(addr, tmp)r100_mm_wreg(rdev, (addr), (tmp), 0);
3060 break;
3061 case 3:
3062 and_mask = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset
)+2)+1]) << 8)) << 16))
;
3063 offset += 4;
3064 or_mask = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset
)+2)+1]) << 8)) << 16))
;
3065 offset += 4;
3066 tmp = RREG32(addr)r100_mm_rreg(rdev, (addr), 0);
3067 tmp &= and_mask;
3068 tmp |= or_mask;
3069 WREG32(addr, tmp)r100_mm_wreg(rdev, (addr), (tmp), 0);
3070 break;
3071 case 4:
3072 val = RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))
;
3073 offset += 2;
3074 udelay(val);
3075 break;
3076 case 5:
3077 val = RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))
;
3078 offset += 2;
3079 switch (addr) {
3080 case 8:
3081 while (val--) {
3082 if (!
3083 (RREG32_PLLrdev->pll_rreg(rdev, (0x0014))
3084 (RADEON_CLK_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0014)) &
3085 RADEON_MC_BUSY(1 << 16)))
3086 break;
3087 }
3088 break;
3089 case 9:
3090 while (val--) {
3091 if ((RREG32(RADEON_MC_STATUS)r100_mm_rreg(rdev, (0x0150), 0) &
3092 RADEON_MC_IDLE(1 << 2)))
3093 break;
3094 }
3095 break;
3096 default:
3097 break;
3098 }
3099 break;
3100 default:
3101 break;
3102 }
3103 }
3104 }
3105}
3106
3107static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3108{
3109 struct radeon_device *rdev = dev->dev_private;
3110
3111 if (offset) {
3112 while (RBIOS8(offset)(rdev->bios[offset])) {
3113 uint8_t cmd = ((RBIOS8(offset)(rdev->bios[offset]) & 0xc0) >> 6);
3114 uint8_t addr = (RBIOS8(offset)(rdev->bios[offset]) & 0x3f);
3115 uint32_t val, shift, tmp;
3116 uint32_t and_mask, or_mask;
3117
3118 offset++;
3119 switch (cmd) {
3120 case 0:
3121 val = RBIOS32(offset)((((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))) | (((rdev->bios[(offset)+2]) | ((rdev->bios[((offset
)+2)+1]) << 8)) << 16))
;
3122 offset += 4;
3123 WREG32_PLL(addr, val)rdev->pll_wreg(rdev, (addr), (val));
3124 break;
3125 case 1:
3126 shift = RBIOS8(offset)(rdev->bios[offset]) * 8;
3127 offset++;
3128 and_mask = RBIOS8(offset)(rdev->bios[offset]) << shift;
3129 and_mask |= ~(0xff << shift);
3130 offset++;
3131 or_mask = RBIOS8(offset)(rdev->bios[offset]) << shift;
3132 offset++;
3133 tmp = RREG32_PLL(addr)rdev->pll_rreg(rdev, (addr));
3134 tmp &= and_mask;
3135 tmp |= or_mask;
3136 WREG32_PLL(addr, tmp)rdev->pll_wreg(rdev, (addr), (tmp));
3137 break;
3138 case 2:
3139 case 3:
3140 tmp = 1000;
3141 switch (addr) {
3142 case 1:
3143 udelay(150);
3144 break;
3145 case 2:
3146 mdelay(1);
3147 break;
3148 case 3:
3149 while (tmp--) {
3150 if (!
3151 (RREG32_PLLrdev->pll_rreg(rdev, (0x0014))
3152 (RADEON_CLK_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0014)) &
3153 RADEON_MC_BUSY(1 << 16)))
3154 break;
3155 }
3156 break;
3157 case 4:
3158 while (tmp--) {
3159 if (RREG32_PLLrdev->pll_rreg(rdev, (0x0014))
3160 (RADEON_CLK_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0014)) &
3161 RADEON_DLL_READY(1 << 19))
3162 break;
3163 }
3164 break;
3165 case 5:
3166 tmp =
3167 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0014));
3168 if (tmp & RADEON_CG_NO1_DEBUG_0(1 << 24)) {
3169#if 0
3170 uint32_t mclk_cntl =
3171 RREG32_PLLrdev->pll_rreg(rdev, (0x0012))
3172 (RADEON_MCLK_CNTL)rdev->pll_rreg(rdev, (0x0012));
3173 mclk_cntl &= 0xffff0000;
3174 /*mclk_cntl |= 0x00001111;*//* ??? */
3175 WREG32_PLL(RADEON_MCLK_CNTL,rdev->pll_wreg(rdev, (0x0012), (mclk_cntl))
3176 mclk_cntl)rdev->pll_wreg(rdev, (0x0012), (mclk_cntl));
3177 mdelay(10);
3178#endif
3179 WREG32_PLLrdev->pll_wreg(rdev, (0x0014), (tmp & ~(1 << 24)
))
3180 (RADEON_CLK_PWRMGT_CNTL,rdev->pll_wreg(rdev, (0x0014), (tmp & ~(1 << 24)
))
3181 tmp &rdev->pll_wreg(rdev, (0x0014), (tmp & ~(1 << 24)
))
3182 ~RADEON_CG_NO1_DEBUG_0)rdev->pll_wreg(rdev, (0x0014), (tmp & ~(1 << 24)
))
;
3183 mdelay(10);
3184 }
3185 break;
3186 default:
3187 break;
3188 }
3189 break;
3190 default:
3191 break;
3192 }
3193 }
3194 }
3195}
3196
3197static void combios_parse_ram_reset_table(struct drm_device *dev,
3198 uint16_t offset)
3199{
3200 struct radeon_device *rdev = dev->dev_private;
3201 uint32_t tmp;
3202
3203 if (offset) {
3204 uint8_t val = RBIOS8(offset)(rdev->bios[offset]);
3205 while (val != 0xff) {
3206 offset++;
3207
3208 if (val == 0x0f) {
3209 uint32_t channel_complete_mask;
3210
3211 if (ASIC_IS_R300(rdev)((rdev->family == CHIP_R300) || (rdev->family == CHIP_RV350
) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV380
) || (rdev->family == CHIP_R420) || (rdev->family == CHIP_R423
) || (rdev->family == CHIP_RV410) || (rdev->family == CHIP_RS400
) || (rdev->family == CHIP_RS480))
)
3212 channel_complete_mask =
3213 R300_MEM_PWRUP_COMPLETE0x0f;
3214 else
3215 channel_complete_mask =
3216 RADEON_MEM_PWRUP_COMPLETE0x03;
3217 tmp = 20000;
3218 while (tmp--) {
3219 if ((RREG32(RADEON_MEM_STR_CNTL)r100_mm_rreg(rdev, (0x0150), 0) &
3220 channel_complete_mask) ==
3221 channel_complete_mask)
3222 break;
3223 }
3224 } else {
3225 uint32_t or_mask = RBIOS16(offset)((rdev->bios[offset]) | ((rdev->bios[(offset)+1]) <<
8))
;
3226 offset += 2;
3227
3228 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG)r100_mm_rreg(rdev, (0x0158), 0);
3229 tmp &= RADEON_SDRAM_MODE_MASK0xffff0000;
3230 tmp |= or_mask;
3231 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp)r100_mm_wreg(rdev, (0x0158), (tmp), 0);
3232
3233 or_mask = val << 24;
3234 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG)r100_mm_rreg(rdev, (0x0158), 0);
3235 tmp &= RADEON_B3MEM_RESET_MASK0x6fffffff;
3236 tmp |= or_mask;
3237 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp)r100_mm_wreg(rdev, (0x0158), (tmp), 0);
3238 }
3239 val = RBIOS8(offset)(rdev->bios[offset]);
3240 }
3241 }
3242}
3243
3244static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3245 int mem_addr_mapping)
3246{
3247 struct radeon_device *rdev = dev->dev_private;
3248 uint32_t mem_cntl;
3249 uint32_t mem_size;
3250 uint32_t addr = 0;
3251
3252 mem_cntl = RREG32(RADEON_MEM_CNTL)r100_mm_rreg(rdev, (0x0140), 0);
3253 if (mem_cntl & RV100_HALF_MODE(1 << 3))
3254 ram /= 2;
3255 mem_size = ram;
3256 mem_cntl &= ~(0xff << 8);
3257 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3258 WREG32(RADEON_MEM_CNTL, mem_cntl)r100_mm_wreg(rdev, (0x0140), (mem_cntl), 0);
3259 RREG32(RADEON_MEM_CNTL)r100_mm_rreg(rdev, (0x0140), 0);
3260
3261 /* sdram reset ? */
3262
3263 /* something like this???? */
3264 while (ram--) {
3265 addr = ram * 1024 * 1024;
3266 /* write to each page */
3267 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef)r100_mm_wreg(rdev, ((addr) | (1 << 31)), (0xdeadbeef), 1
)
;
3268 /* read back and verify */
3269 if (RREG32_IDX((addr) | RADEON_MM_APER)r100_mm_rreg(rdev, ((addr) | (1 << 31)), 1) != 0xdeadbeef)
3270 return 0;
3271 }
3272
3273 return mem_size;
3274}
3275
3276static void combios_write_ram_size(struct drm_device *dev)
3277{
3278 struct radeon_device *rdev = dev->dev_private;
3279 uint8_t rev;
3280 uint16_t offset;
3281 uint32_t mem_size = 0;
3282 uint32_t mem_cntl = 0;
3283
3284 /* should do something smarter here I guess... */
3285 if (rdev->flags & RADEON_IS_IGP)
3286 return;
3287
3288 /* first check detected mem table */
3289 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3290 if (offset) {
3291 rev = RBIOS8(offset)(rdev->bios[offset]);
3292 if (rev < 3) {
3293 mem_cntl = RBIOS32(offset + 1)((((rdev->bios[offset + 1]) | ((rdev->bios[(offset + 1)
+1]) << 8))) | (((rdev->bios[(offset + 1)+2]) | ((rdev
->bios[((offset + 1)+2)+1]) << 8)) << 16))
;
3294 mem_size = RBIOS16(offset + 5)((rdev->bios[offset + 5]) | ((rdev->bios[(offset + 5)+1
]) << 8))
;
3295 if ((rdev->family < CHIP_R200) &&
3296 !ASIC_IS_RN50(rdev)((rdev->pdev->device == 0x515e) || (rdev->pdev->device
== 0x5969))
)
3297 WREG32(RADEON_MEM_CNTL, mem_cntl)r100_mm_wreg(rdev, (0x0140), (mem_cntl), 0);
3298 }
3299 }
3300
3301 if (!mem_size) {
3302 offset =
3303 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3304 if (offset) {
3305 rev = RBIOS8(offset - 1)(rdev->bios[offset - 1]);
3306 if (rev < 1) {
3307 if ((rdev->family < CHIP_R200)
3308 && !ASIC_IS_RN50(rdev)((rdev->pdev->device == 0x515e) || (rdev->pdev->device
== 0x5969))
) {
3309 int ram = 0;
3310 int mem_addr_mapping = 0;
3311
3312 while (RBIOS8(offset)(rdev->bios[offset])) {
3313 ram = RBIOS8(offset)(rdev->bios[offset]);
3314 mem_addr_mapping =
3315 RBIOS8(offset + 1)(rdev->bios[offset + 1]);
3316 if (mem_addr_mapping != 0x25)
3317 ram *= 2;
3318 mem_size =
3319 combios_detect_ram(dev, ram,
3320 mem_addr_mapping);
3321 if (mem_size)
3322 break;
3323 offset += 2;
3324 }
3325 } else
3326 mem_size = RBIOS8(offset)(rdev->bios[offset]);
3327 } else {
3328 mem_size = RBIOS8(offset)(rdev->bios[offset]);
3329 mem_size *= 2; /* convert to MB */
3330 }
3331 }
3332 }
3333
3334 mem_size *= (1024 * 1024); /* convert to bytes */
3335 WREG32(RADEON_CONFIG_MEMSIZE, mem_size)r100_mm_wreg(rdev, (0x00f8), (mem_size), 0);
3336}
3337
3338void radeon_combios_asic_init(struct drm_device *dev)
3339{
3340 struct radeon_device *rdev = dev->dev_private;
3341 uint16_t table;
3342
3343 /* port hardcoded mac stuff from radeonfb */
3344 if (rdev->bios == NULL((void *)0))
3345 return;
3346
3347 /* ASIC INIT 1 */
3348 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3349 if (table)
3350 combios_parse_mmio_table(dev, table);
3351
3352 /* PLL INIT */
3353 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3354 if (table)
3355 combios_parse_pll_table(dev, table);
3356
3357 /* ASIC INIT 2 */
3358 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3359 if (table)
3360 combios_parse_mmio_table(dev, table);
3361
3362 if (!(rdev->flags & RADEON_IS_IGP)) {
3363 /* ASIC INIT 4 */
3364 table =
3365 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3366 if (table)
3367 combios_parse_mmio_table(dev, table);
3368
3369 /* RAM RESET */
3370 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3371 if (table)
3372 combios_parse_ram_reset_table(dev, table);
3373
3374 /* ASIC INIT 3 */
3375 table =
3376 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3377 if (table)
3378 combios_parse_mmio_table(dev, table);
3379
3380 /* write CONFIG_MEMSIZE */
3381 combios_write_ram_size(dev);
3382 }
3383
3384 /* quirk for rs4xx HP nx6125 laptop to make it resume
3385 * - it hangs on resume inside the dynclk 1 table.
3386 */
3387 if (rdev->family == CHIP_RS480 &&
3388 rdev->pdev->subsystem_vendor == 0x103c &&
3389 rdev->pdev->subsystem_device == 0x308b)
3390 return;
3391
3392 /* quirk for rs4xx HP dv5000 laptop to make it resume
3393 * - it hangs on resume inside the dynclk 1 table.
3394 */
3395 if (rdev->family == CHIP_RS480 &&
3396 rdev->pdev->subsystem_vendor == 0x103c &&
3397 rdev->pdev->subsystem_device == 0x30a4)
3398 return;
3399
3400 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3401 * - it hangs on resume inside the dynclk 1 table.
3402 */
3403 if (rdev->family == CHIP_RS480 &&
3404 rdev->pdev->subsystem_vendor == 0x103c &&
3405 rdev->pdev->subsystem_device == 0x30ae)
3406 return;
3407
3408 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3409 * - it hangs on resume inside the dynclk 1 table.
3410 */
3411 if (rdev->family == CHIP_RS480 &&
3412 rdev->pdev->subsystem_vendor == 0x103c &&
3413 rdev->pdev->subsystem_device == 0x280a)
3414 return;
3415 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume
3416 * - it hangs on resume inside the dynclk 1 table.
3417 */
3418 if (rdev->family == CHIP_RS400 &&
3419 rdev->pdev->subsystem_vendor == 0x1179 &&
3420 rdev->pdev->subsystem_device == 0xff31)
3421 return;
3422
3423 /* DYN CLK 1 */
3424 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3425 if (table)
3426 combios_parse_pll_table(dev, table);
3427
3428}
3429
3430void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3431{
3432 struct radeon_device *rdev = dev->dev_private;
3433 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3434
3435 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH)r100_mm_rreg(rdev, (0x0010), 0);
3436 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0);
3437 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH)r100_mm_rreg(rdev, (0x002c), 0);
3438
3439 /* let the bios control the backlight */
3440 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN(1 << 26);
3441
3442 /* tell the bios not to handle mode switching */
3443 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS(1 << 30) |
3444 RADEON_ACC_MODE_CHANGE(1 << 2));
3445
3446 /* tell the bios a driver is loaded */
3447 bios_7_scratch |= RADEON_DRV_LOADED(1 << 12);
3448
3449 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch)r100_mm_wreg(rdev, (0x0010), (bios_0_scratch), 0);
3450 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch)r100_mm_wreg(rdev, (0x0028), (bios_6_scratch), 0);
3451 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch)r100_mm_wreg(rdev, (0x002c), (bios_7_scratch), 0);
3452}
3453
3454void radeon_combios_output_lock(struct drm_encoder *encoder, bool_Bool lock)
3455{
3456 struct drm_device *dev = encoder->dev;
3457 struct radeon_device *rdev = dev->dev_private;
3458 uint32_t bios_6_scratch;
3459
3460 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0);
3461
3462 if (lock)
3463 bios_6_scratch |= RADEON_DRIVER_CRITICAL(1 << 27);
3464 else
3465 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL(1 << 27);
3466
3467 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch)r100_mm_wreg(rdev, (0x0028), (bios_6_scratch), 0);
3468}
3469
3470void
3471radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3472 struct drm_encoder *encoder,
3473 bool_Bool connected)
3474{
3475 struct drm_device *dev = connector->dev;
3476 struct radeon_device *rdev = dev->dev_private;
3477 struct radeon_connector *radeon_connector =
3478 to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
- __builtin_offsetof(struct radeon_connector, base) );})
;
3479 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );})
;
3480 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH)r100_mm_rreg(rdev, (0x0020), 0);
3481 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH)r100_mm_rreg(rdev, (0x0024), 0);
3482
3483 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )) &&
3484 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 ))) {
3485 if (connected) {
3486 DRM_DEBUG_KMS("TV1 connected\n")__drm_dbg(DRM_UT_KMS, "TV1 connected\n");
3487 /* fix me */
3488 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO(2 << 4);
3489 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3490 bios_5_scratch |= RADEON_TV1_ON(1 << 2);
3491 bios_5_scratch |= RADEON_ACC_REQ_TV1(1 << 18);
3492 } else {
3493 DRM_DEBUG_KMS("TV1 disconnected\n")__drm_dbg(DRM_UT_KMS, "TV1 disconnected\n");
3494 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK(3 << 4);
3495 bios_5_scratch &= ~RADEON_TV1_ON(1 << 2);
3496 bios_5_scratch &= ~RADEON_ACC_REQ_TV1(1 << 18);
3497 }
3498 }
3499 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )) &&
3500 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 ))) {
3501 if (connected) {
3502 DRM_DEBUG_KMS("LCD1 connected\n")__drm_dbg(DRM_UT_KMS, "LCD1 connected\n");
3503 bios_4_scratch |= RADEON_LCD1_ATTACHED(1 << 2);
3504 bios_5_scratch |= RADEON_LCD1_ON(1 << 0);
3505 bios_5_scratch |= RADEON_ACC_REQ_LCD1(1 << 16);
3506 } else {
3507 DRM_DEBUG_KMS("LCD1 disconnected\n")__drm_dbg(DRM_UT_KMS, "LCD1 disconnected\n");
3508 bios_4_scratch &= ~RADEON_LCD1_ATTACHED(1 << 2);
3509 bios_5_scratch &= ~RADEON_LCD1_ON(1 << 0);
3510 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1(1 << 16);
3511 }
3512 }
3513 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )) &&
3514 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 ))) {
3515 if (connected) {
3516 DRM_DEBUG_KMS("CRT1 connected\n")__drm_dbg(DRM_UT_KMS, "CRT1 connected\n");
3517 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR(2 << 0);
3518 bios_5_scratch |= RADEON_CRT1_ON(1 << 1);
3519 bios_5_scratch |= RADEON_ACC_REQ_CRT1(1 << 17);
3520 } else {
3521 DRM_DEBUG_KMS("CRT1 disconnected\n")__drm_dbg(DRM_UT_KMS, "CRT1 disconnected\n");
3522 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK(3 << 0);
3523 bios_5_scratch &= ~RADEON_CRT1_ON(1 << 1);
3524 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1(1 << 17);
3525 }
3526 }
3527 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )) &&
3528 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 ))) {
3529 if (connected) {
3530 DRM_DEBUG_KMS("CRT2 connected\n")__drm_dbg(DRM_UT_KMS, "CRT2 connected\n");
3531 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR(2 << 8);
3532 bios_5_scratch |= RADEON_CRT2_ON(1 << 5);
3533 bios_5_scratch |= RADEON_ACC_REQ_CRT2(1 << 21);
3534 } else {
3535 DRM_DEBUG_KMS("CRT2 disconnected\n")__drm_dbg(DRM_UT_KMS, "CRT2 disconnected\n");
3536 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK(3 << 8);
3537 bios_5_scratch &= ~RADEON_CRT2_ON(1 << 5);
3538 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2(1 << 21);
3539 }
3540 }
3541 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )) &&
3542 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 ))) {
3543 if (connected) {
3544 DRM_DEBUG_KMS("DFP1 connected\n")__drm_dbg(DRM_UT_KMS, "DFP1 connected\n");
3545 bios_4_scratch |= RADEON_DFP1_ATTACHED(1 << 3);
3546 bios_5_scratch |= RADEON_DFP1_ON(1 << 3);
3547 bios_5_scratch |= RADEON_ACC_REQ_DFP1(1 << 19);
3548 } else {
3549 DRM_DEBUG_KMS("DFP1 disconnected\n")__drm_dbg(DRM_UT_KMS, "DFP1 disconnected\n");
3550 bios_4_scratch &= ~RADEON_DFP1_ATTACHED(1 << 3);
3551 bios_5_scratch &= ~RADEON_DFP1_ON(1 << 3);
3552 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1(1 << 19);
3553 }
3554 }
3555 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )) &&
3556 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 ))) {
3557 if (connected) {
3558 DRM_DEBUG_KMS("DFP2 connected\n")__drm_dbg(DRM_UT_KMS, "DFP2 connected\n");
3559 bios_4_scratch |= RADEON_DFP2_ATTACHED(1 << 11);
3560 bios_5_scratch |= RADEON_DFP2_ON(1 << 7);
3561 bios_5_scratch |= RADEON_ACC_REQ_DFP2(1 << 23);
3562 } else {
3563 DRM_DEBUG_KMS("DFP2 disconnected\n")__drm_dbg(DRM_UT_KMS, "DFP2 disconnected\n");
3564 bios_4_scratch &= ~RADEON_DFP2_ATTACHED(1 << 11);
3565 bios_5_scratch &= ~RADEON_DFP2_ON(1 << 7);
3566 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2(1 << 23);
3567 }
3568 }
3569 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch)r100_mm_wreg(rdev, (0x0020), (bios_4_scratch), 0);
3570 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch)r100_mm_wreg(rdev, (0x0024), (bios_5_scratch), 0);
3571}
3572
3573void
3574radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3575{
3576 struct drm_device *dev = encoder->dev;
3577 struct radeon_device *rdev = dev->dev_private;
3578 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );})
;
3579 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH)r100_mm_rreg(rdev, (0x0024), 0);
3580
3581 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT(0x1L << 0x00000002 )) {
3582 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK(1 << 10);
3583 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT10);
3584 }
3585 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT(0x1L << 0x00000000 )) {
3586 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK(1 << 9);
3587 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT9);
3588 }
3589 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT(0x1L << 0x00000004 )) {
3590 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK(1 << 12);
3591 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT12);
3592 }
3593 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT(0x1L << 0x00000001 )) {
3594 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK(1 << 8);
3595 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT8);
3596 }
3597 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT(0x1L << 0x00000003 )) {
3598 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK(1 << 11);
3599 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT11);
3600 }
3601 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT(0x1L << 0x00000007 )) {
3602 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK(1 << 14);
3603 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT14);
3604 }
3605 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch)r100_mm_wreg(rdev, (0x0024), (bios_5_scratch), 0);
3606}
3607
3608void
3609radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool_Bool on)
3610{
3611 struct drm_device *dev = encoder->dev;
3612 struct radeon_device *rdev = dev->dev_private;
3613 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder)({ const __typeof( ((struct radeon_encoder *)0)->base ) *__mptr
= (encoder); (struct radeon_encoder *)( (char *)__mptr - __builtin_offsetof
(struct radeon_encoder, base) );})
;
3614 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH)r100_mm_rreg(rdev, (0x0028), 0);
3615
3616 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT((0x1L << 0x00000002 )))) {
3617 if (on)
3618 bios_6_scratch |= RADEON_TV_DPMS_ON(1 << 22);
3619 else
3620 bios_6_scratch &= ~RADEON_TV_DPMS_ON(1 << 22);
3621 }
3622 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 )))) {
3623 if (on)
3624 bios_6_scratch |= RADEON_CRT_DPMS_ON(1 << 21);
3625 else
3626 bios_6_scratch &= ~RADEON_CRT_DPMS_ON(1 << 21);
3627 }
3628 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
3629 if (on)
3630 bios_6_scratch |= RADEON_LCD_DPMS_ON(1 << 20);
3631 else
3632 bios_6_scratch &= ~RADEON_LCD_DPMS_ON(1 << 20);
3633 }
3634 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
<< 0x0000000B ) | (0x1L << 0x00000006 ))
)) {
3635 if (on)
3636 bios_6_scratch |= RADEON_DFP_DPMS_ON(1 << 23);
3637 else
3638 bios_6_scratch &= ~RADEON_DFP_DPMS_ON(1 << 23);
3639 }
3640 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch)r100_mm_wreg(rdev, (0x0028), (bios_6_scratch), 0);
3641}