Bug Summary

File:dev/pci/drm/amd/amdgpu/vce_v3_0.c
Warning:line 668, column 3
Value stored to 'tmp' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name vce_v3_0.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/vce_v3_0.c
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28#include <linux/firmware.h>
29
30#include "amdgpu.h"
31#include "amdgpu_vce.h"
32#include "vid.h"
33#include "vce/vce_3_0_d.h"
34#include "vce/vce_3_0_sh_mask.h"
35#include "oss/oss_3_0_d.h"
36#include "oss/oss_3_0_sh_mask.h"
37#include "gca/gfx_8_0_d.h"
38#include "smu/smu_7_1_2_d.h"
39#include "smu/smu_7_1_2_sh_mask.h"
40#include "gca/gfx_8_0_sh_mask.h"
41#include "ivsrcid/ivsrcid_vislands30.h"
42
43
44#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT0x04 0x04
45#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK0x10 0x10
46#define GRBM_GFX_INDEX__VCE_ALL_PIPE0x07 0x07
47
48#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR00x8616 0x8616
49#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR10x8617 0x8617
50#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR20x8618 0x8618
51#define mmGRBM_GFX_INDEX_DEFAULT0xE0000000 0xE0000000
52
53#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK0x02 0x02
54
55#define VCE_V3_0_FW_SIZE(384 * 1024) (384 * 1024)
56#define VCE_V3_0_STACK_SIZE(64 * 1024) (64 * 1024)
57#define VCE_V3_0_DATA_SIZE((16 * 1024 * 16) + (52 * 1024)) ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES16) + (52 * 1024))
58
59#define FW_52_8_3((52 << 24) | (8 << 16) | (3 << 8)) ((52 << 24) | (8 << 16) | (3 << 8))
60
61#define GET_VCE_INSTANCE(i)((i) << 0x04 | 0x07) ((i) << GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT0x04 \
62 | GRBM_GFX_INDEX__VCE_ALL_PIPE0x07)
63
64static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
65static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
66static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
67static int vce_v3_0_wait_for_idle(void *handle);
68static int vce_v3_0_set_clockgating_state(void *handle,
69 enum amd_clockgating_state state);
70/**
71 * vce_v3_0_ring_get_rptr - get read pointer
72 *
73 * @ring: amdgpu_ring pointer
74 *
75 * Returns the current hardware read pointer
76 */
77static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
78{
79 struct amdgpu_device *adev = ring->adev;
80 u32 v;
81
82 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
83 if (adev->vce.harvest_config == 0 ||
84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1(1 << 1))
85 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0))amdgpu_device_wreg(adev, (0xc200), (((0) << 0x04 | 0x07
)), 0);
86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0(1 << 0))
87 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1))amdgpu_device_wreg(adev, (0xc200), (((1) << 0x04 | 0x07
)), 0);
88
89 if (ring->me == 0)
90 v = RREG32(mmVCE_RB_RPTR)amdgpu_device_rreg(adev, (0x8063), 0);
91 else if (ring->me == 1)
92 v = RREG32(mmVCE_RB_RPTR2)amdgpu_device_rreg(adev, (0x805e), 0);
93 else
94 v = RREG32(mmVCE_RB_RPTR3)amdgpu_device_rreg(adev, (0x80d7), 0);
95
96 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT)amdgpu_device_wreg(adev, (0xc200), (0xE0000000), 0);
97 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
98
99 return v;
100}
101
102/**
103 * vce_v3_0_ring_get_wptr - get write pointer
104 *
105 * @ring: amdgpu_ring pointer
106 *
107 * Returns the current hardware write pointer
108 */
109static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
110{
111 struct amdgpu_device *adev = ring->adev;
112 u32 v;
113
114 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
115 if (adev->vce.harvest_config == 0 ||
116 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1(1 << 1))
117 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0))amdgpu_device_wreg(adev, (0xc200), (((0) << 0x04 | 0x07
)), 0);
118 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0(1 << 0))
119 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1))amdgpu_device_wreg(adev, (0xc200), (((1) << 0x04 | 0x07
)), 0);
120
121 if (ring->me == 0)
122 v = RREG32(mmVCE_RB_WPTR)amdgpu_device_rreg(adev, (0x8064), 0);
123 else if (ring->me == 1)
124 v = RREG32(mmVCE_RB_WPTR2)amdgpu_device_rreg(adev, (0x805f), 0);
125 else
126 v = RREG32(mmVCE_RB_WPTR3)amdgpu_device_rreg(adev, (0x80d8), 0);
127
128 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT)amdgpu_device_wreg(adev, (0xc200), (0xE0000000), 0);
129 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
130
131 return v;
132}
133
134/**
135 * vce_v3_0_ring_set_wptr - set write pointer
136 *
137 * @ring: amdgpu_ring pointer
138 *
139 * Commits the write pointer to the hardware
140 */
141static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
142{
143 struct amdgpu_device *adev = ring->adev;
144
145 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
146 if (adev->vce.harvest_config == 0 ||
147 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1(1 << 1))
148 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0))amdgpu_device_wreg(adev, (0xc200), (((0) << 0x04 | 0x07
)), 0);
149 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0(1 << 0))
150 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1))amdgpu_device_wreg(adev, (0xc200), (((1) << 0x04 | 0x07
)), 0);
151
152 if (ring->me == 0)
153 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x8064), (((u32)(ring->wptr))), 0
);
154 else if (ring->me == 1)
155 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x805f), (((u32)(ring->wptr))), 0
);
156 else
157 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x80d8), (((u32)(ring->wptr))), 0
);
158
159 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT)amdgpu_device_wreg(adev, (0xc200), (0xE0000000), 0);
160 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
161}
162
163static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool_Bool override)
164{
165 WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0)amdgpu_device_wreg(adev, (0x809f), ((amdgpu_device_rreg(adev,
(0x809f), 0) & ~0x10000) | (override ? 1 : 0) << 0x10
), 0);
166}
167
168static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
169 bool_Bool gated)
170{
171 u32 data;
172
173 /* Set Override to disable Clock Gating */
174 vce_v3_0_override_vce_clock_gating(adev, true1);
175
176 /* This function enables MGCG which is controlled by firmware.
177 With the clocks in the gated state the core is still
178 accessible but the firmware will throttle the clocks on the
179 fly as necessary.
180 */
181 if (!gated) {
182 data = RREG32(mmVCE_CLOCK_GATING_B)amdgpu_device_rreg(adev, (0x80bf), 0);
183 data |= 0x1ff;
184 data &= ~0xef0000;
185 WREG32(mmVCE_CLOCK_GATING_B, data)amdgpu_device_wreg(adev, (0x80bf), (data), 0);
186
187 data = RREG32(mmVCE_UENC_CLOCK_GATING)amdgpu_device_rreg(adev, (0x81ef), 0);
188 data |= 0x3ff000;
189 data &= ~0xffc00000;
190 WREG32(mmVCE_UENC_CLOCK_GATING, data)amdgpu_device_wreg(adev, (0x81ef), (data), 0);
191
192 data = RREG32(mmVCE_UENC_CLOCK_GATING_2)amdgpu_device_rreg(adev, (0x8210), 0);
193 data |= 0x2;
194 data &= ~0x00010000;
195 WREG32(mmVCE_UENC_CLOCK_GATING_2, data)amdgpu_device_wreg(adev, (0x8210), (data), 0);
196
197 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING)amdgpu_device_rreg(adev, (0x81f0), 0);
198 data |= 0x37f;
199 WREG32(mmVCE_UENC_REG_CLOCK_GATING, data)amdgpu_device_wreg(adev, (0x81f0), (data), 0);
200
201 data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL)amdgpu_device_rreg(adev, (0x8390), 0);
202 data |= VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK0x1 |
203 VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK0x2 |
204 VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK0x4 |
205 0x8;
206 WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data)amdgpu_device_wreg(adev, (0x8390), (data), 0);
207 } else {
208 data = RREG32(mmVCE_CLOCK_GATING_B)amdgpu_device_rreg(adev, (0x80bf), 0);
209 data &= ~0x80010;
210 data |= 0xe70008;
211 WREG32(mmVCE_CLOCK_GATING_B, data)amdgpu_device_wreg(adev, (0x80bf), (data), 0);
212
213 data = RREG32(mmVCE_UENC_CLOCK_GATING)amdgpu_device_rreg(adev, (0x81ef), 0);
214 data |= 0xffc00000;
215 WREG32(mmVCE_UENC_CLOCK_GATING, data)amdgpu_device_wreg(adev, (0x81ef), (data), 0);
216
217 data = RREG32(mmVCE_UENC_CLOCK_GATING_2)amdgpu_device_rreg(adev, (0x8210), 0);
218 data |= 0x10000;
219 WREG32(mmVCE_UENC_CLOCK_GATING_2, data)amdgpu_device_wreg(adev, (0x8210), (data), 0);
220
221 data = RREG32(mmVCE_UENC_REG_CLOCK_GATING)amdgpu_device_rreg(adev, (0x81f0), 0);
222 data &= ~0x3ff;
223 WREG32(mmVCE_UENC_REG_CLOCK_GATING, data)amdgpu_device_wreg(adev, (0x81f0), (data), 0);
224
225 data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL)amdgpu_device_rreg(adev, (0x8390), 0);
226 data &= ~(VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK0x1 |
227 VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK0x2 |
228 VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK0x4 |
229 0x8);
230 WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data)amdgpu_device_wreg(adev, (0x8390), (data), 0);
231 }
232 vce_v3_0_override_vce_clock_gating(adev, false0);
233}
234
235static int vce_v3_0_firmware_loaded(struct amdgpu_device *adev)
236{
237 int i, j;
238
239 for (i = 0; i < 10; ++i) {
240 for (j = 0; j < 100; ++j) {
241 uint32_t status = RREG32(mmVCE_STATUS)amdgpu_device_rreg(adev, (0x8001), 0);
242
243 if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK0x02)
244 return 0;
245 mdelay(10);
246 }
247
248 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n")__drm_err("VCE not responding, trying to reset the ECPU!!!\n"
);
249 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1)amdgpu_device_wreg(adev, (0x8048), ((amdgpu_device_rreg(adev,
(0x8048), 0) & ~0x1) | (1) << 0x0), 0);
250 mdelay(10);
251 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0)amdgpu_device_wreg(adev, (0x8048), ((amdgpu_device_rreg(adev,
(0x8048), 0) & ~0x1) | (0) << 0x0), 0);
252 mdelay(10);
253 }
254
255 return -ETIMEDOUT60;
256}
257
258/**
259 * vce_v3_0_start - start VCE block
260 *
261 * @adev: amdgpu_device pointer
262 *
263 * Setup and start the VCE block
264 */
265static int vce_v3_0_start(struct amdgpu_device *adev)
266{
267 struct amdgpu_ring *ring;
268 int idx, r;
269
270 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
271 for (idx = 0; idx < 2; ++idx) {
272 if (adev->vce.harvest_config & (1 << idx))
273 continue;
274
275 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx))amdgpu_device_wreg(adev, (0xc200), (((idx) << 0x04 | 0x07
)), 0);
276
277 /* Program instance 0 reg space for two instances or instance 0 case
278 program instance 1 reg space for only instance 1 available case */
279 if (idx != 1 || adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0(1 << 0)) {
280 ring = &adev->vce.ring[0];
281 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x8063), (((u32)(ring->wptr))), 0
);
282 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x8064), (((u32)(ring->wptr))), 0
);
283 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr)amdgpu_device_wreg(adev, (0x8060), (ring->gpu_addr), 0);
284 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, (0x8061), (((u32)(((ring->gpu_addr
) >> 16) >> 16))), 0);
285 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4)amdgpu_device_wreg(adev, (0x8062), (ring->ring_size / 4), 0
);
286
287 ring = &adev->vce.ring[1];
288 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x805e), (((u32)(ring->wptr))), 0
);
289 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x805f), (((u32)(ring->wptr))), 0
);
290 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr)amdgpu_device_wreg(adev, (0x805b), (ring->gpu_addr), 0);
291 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, (0x805c), (((u32)(((ring->gpu_addr
) >> 16) >> 16))), 0);
292 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4)amdgpu_device_wreg(adev, (0x805d), (ring->ring_size / 4), 0
);
293
294 ring = &adev->vce.ring[2];
295 WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x80d7), (((u32)(ring->wptr))), 0
);
296 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x80d8), (((u32)(ring->wptr))), 0
);
297 WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr)amdgpu_device_wreg(adev, (0x80d4), (ring->gpu_addr), 0);
298 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, (0x80d5), (((u32)(((ring->gpu_addr
) >> 16) >> 16))), 0);
299 WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4)amdgpu_device_wreg(adev, (0x80d6), (ring->ring_size / 4), 0
);
300 }
301
302 vce_v3_0_mc_resume(adev, idx);
303 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1)amdgpu_device_wreg(adev, (0x8001), ((amdgpu_device_rreg(adev,
(0x8001), 0) & ~0x1) | (1) << 0x0), 0);
304
305 if (adev->asic_type >= CHIP_STONEY)
306 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x8005), 0); tmp_
&= (~0x200001); tmp_ |= ((1) & ~(~0x200001)); amdgpu_device_wreg
(adev, (0x8005), (tmp_), 0); } while (0);
307 else
308 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1)amdgpu_device_wreg(adev, (0x8005), ((amdgpu_device_rreg(adev,
(0x8005), 0) & ~0x1) | (1) << 0x0), 0);
309
310 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0)amdgpu_device_wreg(adev, (0x8048), ((amdgpu_device_rreg(adev,
(0x8048), 0) & ~0x1) | (0) << 0x0), 0);
311 mdelay(100);
312
313 r = vce_v3_0_firmware_loaded(adev);
314
315 /* clear BUSY flag */
316 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0)amdgpu_device_wreg(adev, (0x8001), ((amdgpu_device_rreg(adev,
(0x8001), 0) & ~0x1) | (0) << 0x0), 0);
317
318 if (r) {
319 DRM_ERROR("VCE not responding, giving up!!!\n")__drm_err("VCE not responding, giving up!!!\n");
320 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
321 return r;
322 }
323 }
324
325 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT)amdgpu_device_wreg(adev, (0xc200), (0xE0000000), 0);
326 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
327
328 return 0;
329}
330
331static int vce_v3_0_stop(struct amdgpu_device *adev)
332{
333 int idx;
334
335 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
336 for (idx = 0; idx < 2; ++idx) {
337 if (adev->vce.harvest_config & (1 << idx))
338 continue;
339
340 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx))amdgpu_device_wreg(adev, (0xc200), (((idx) << 0x04 | 0x07
)), 0);
341
342 if (adev->asic_type >= CHIP_STONEY)
343 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x8005), 0); tmp_
&= (~0x200001); tmp_ |= ((0) & ~(~0x200001)); amdgpu_device_wreg
(adev, (0x8005), (tmp_), 0); } while (0);
344 else
345 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0)amdgpu_device_wreg(adev, (0x8005), ((amdgpu_device_rreg(adev,
(0x8005), 0) & ~0x1) | (0) << 0x0), 0);
346
347 /* hold on ECPU */
348 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1)amdgpu_device_wreg(adev, (0x8048), ((amdgpu_device_rreg(adev,
(0x8048), 0) & ~0x1) | (1) << 0x0), 0);
349
350 /* clear VCE STATUS */
351 WREG32(mmVCE_STATUS, 0)amdgpu_device_wreg(adev, (0x8001), (0), 0);
352 }
353
354 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT)amdgpu_device_wreg(adev, (0xc200), (0xE0000000), 0);
355 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
356
357 return 0;
358}
359
360#define ixVCE_HARVEST_FUSE_MACRO__ADDRESS0xC0014074 0xC0014074
361#define VCE_HARVEST_FUSE_MACRO__SHIFT27 27
362#define VCE_HARVEST_FUSE_MACRO__MASK0x18000000 0x18000000
363
364static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
365{
366 u32 tmp;
367
368 if ((adev->asic_type == CHIP_FIJI) ||
369 (adev->asic_type == CHIP_STONEY))
370 return AMDGPU_VCE_HARVEST_VCE1(1 << 1);
371
372 if (adev->flags & AMD_IS_APU)
373 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS)adev->smc_rreg(adev, (0xC0014074)) &
374 VCE_HARVEST_FUSE_MACRO__MASK0x18000000) >>
375 VCE_HARVEST_FUSE_MACRO__SHIFT27;
376 else
377 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES)adev->smc_rreg(adev, (0xc00c0028)) &
378 CC_HARVEST_FUSES__VCE_DISABLE_MASK0x6) >>
379 CC_HARVEST_FUSES__VCE_DISABLE__SHIFT0x1;
380
381 switch (tmp) {
382 case 1:
383 return AMDGPU_VCE_HARVEST_VCE0(1 << 0);
384 case 2:
385 return AMDGPU_VCE_HARVEST_VCE1(1 << 1);
386 case 3:
387 return AMDGPU_VCE_HARVEST_VCE0(1 << 0) | AMDGPU_VCE_HARVEST_VCE1(1 << 1);
388 default:
389 if ((adev->asic_type == CHIP_POLARIS10) ||
390 (adev->asic_type == CHIP_POLARIS11) ||
391 (adev->asic_type == CHIP_POLARIS12) ||
392 (adev->asic_type == CHIP_VEGAM))
393 return AMDGPU_VCE_HARVEST_VCE1(1 << 1);
394
395 return 0;
396 }
397}
398
399static int vce_v3_0_early_init(void *handle)
400{
401 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
402
403 adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);
404
405 if ((adev->vce.harvest_config &
406 (AMDGPU_VCE_HARVEST_VCE0(1 << 0) | AMDGPU_VCE_HARVEST_VCE1(1 << 1))) ==
407 (AMDGPU_VCE_HARVEST_VCE0(1 << 0) | AMDGPU_VCE_HARVEST_VCE1(1 << 1)))
408 return -ENOENT2;
409
410 adev->vce.num_rings = 3;
411
412 vce_v3_0_set_ring_funcs(adev);
413 vce_v3_0_set_irq_funcs(adev);
414
415 return 0;
416}
417
418static int vce_v3_0_sw_init(void *handle)
419{
420 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
421 struct amdgpu_ring *ring;
422 int r, i;
423
424 /* VCE */
425 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_VCE_TRAP0x000000a7, &adev->vce.irq);
426 if (r)
427 return r;
428
429 r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE(384 * 1024) +
430 (VCE_V3_0_STACK_SIZE(64 * 1024) + VCE_V3_0_DATA_SIZE((16 * 1024 * 16) + (52 * 1024))) * 2);
431 if (r)
432 return r;
433
434 /* 52.8.3 required for 3 ring support */
435 if (adev->vce.fw_version < FW_52_8_3((52 << 24) | (8 << 16) | (3 << 8)))
436 adev->vce.num_rings = 2;
437
438 r = amdgpu_vce_resume(adev);
439 if (r)
440 return r;
441
442 for (i = 0; i < adev->vce.num_rings; i++) {
443 ring = &adev->vce.ring[i];
444 snprintf(ring->name, sizeof(ring->name), "vce%d", i);
445 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
446 AMDGPU_RING_PRIO_DEFAULT1);
447 if (r)
448 return r;
449 }
450
451 r = amdgpu_vce_entity_init(adev);
452
453 return r;
454}
455
456static int vce_v3_0_sw_fini(void *handle)
457{
458 int r;
459 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
460
461 r = amdgpu_vce_suspend(adev);
462 if (r)
463 return r;
464
465 return amdgpu_vce_sw_fini(adev);
466}
467
468static int vce_v3_0_hw_init(void *handle)
469{
470 int r, i;
471 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
472
473 vce_v3_0_override_vce_clock_gating(adev, true1);
474
475 amdgpu_asic_set_vce_clocks(adev, 10000, 10000)(adev)->asic_funcs->set_vce_clocks((adev), (10000), (10000
));
476
477 for (i = 0; i < adev->vce.num_rings; i++) {
478 r = amdgpu_ring_test_helper(&adev->vce.ring[i]);
479 if (r)
480 return r;
481 }
482
483 DRM_INFO("VCE initialized successfully.\n")printk("\0016" "[" "drm" "] " "VCE initialized successfully.\n"
);
484
485 return 0;
486}
487
488static int vce_v3_0_hw_fini(void *handle)
489{
490 int r;
491 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
492
493 r = vce_v3_0_wait_for_idle(handle);
494 if (r)
495 return r;
496
497 vce_v3_0_stop(adev);
498 return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
499}
500
501static int vce_v3_0_suspend(void *handle)
502{
503 int r;
504 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
505
506 r = vce_v3_0_hw_fini(adev);
507 if (r)
508 return r;
509
510 return amdgpu_vce_suspend(adev);
511}
512
513static int vce_v3_0_resume(void *handle)
514{
515 int r;
516 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
517
518 r = amdgpu_vce_resume(adev);
519 if (r)
520 return r;
521
522 return vce_v3_0_hw_init(adev);
523}
524
525static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
526{
527 uint32_t offset, size;
528
529 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16))do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x80be), 0); tmp_
&= (~(1 << 16)); tmp_ |= ((0) & ~(~(1 <<
16))); amdgpu_device_wreg(adev, (0x80be), (tmp_), 0); } while
(0);
530 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x81ef), 0); tmp_
&= (~0xFF9FF000); tmp_ |= ((0x1FF000) & ~(~0xFF9FF000
)); amdgpu_device_wreg(adev, (0x81ef), (tmp_), 0); } while (0
);
531 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x81f0), 0); tmp_
&= (~0x3F); tmp_ |= ((0x3F) & ~(~0x3F)); amdgpu_device_wreg
(adev, (0x81f0), (tmp_), 0); } while (0);
532 WREG32(mmVCE_CLOCK_GATING_B, 0x1FF)amdgpu_device_wreg(adev, (0x80bf), (0x1FF), 0);
533
534 WREG32(mmVCE_LMI_CTRL, 0x00398000)amdgpu_device_wreg(adev, (0x85a6), (0x00398000), 0);
535 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x85bd), 0); tmp_
&= (~0x1); tmp_ |= ((0x0) & ~(~0x1)); amdgpu_device_wreg
(adev, (0x85bd), (tmp_), 0); } while (0);
536 WREG32(mmVCE_LMI_SWAP_CNTL, 0)amdgpu_device_wreg(adev, (0x85ad), (0), 0);
537 WREG32(mmVCE_LMI_SWAP_CNTL1, 0)amdgpu_device_wreg(adev, (0x85ae), (0), 0);
538 WREG32(mmVCE_LMI_VM_CTRL, 0)amdgpu_device_wreg(adev, (0x85a8), (0), 0);
539 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x8005), 0); tmp_
&= (~(0x00100000)); tmp_ |= ((0x00100000) & ~(~(0x00100000
))); amdgpu_device_wreg(adev, (0x8005), (tmp_), 0); } while (
0);
540
541 if (adev->asic_type >= CHIP_STONEY) {
542 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8))amdgpu_device_wreg(adev, (0x8616), ((adev->vce.gpu_addr >>
8)), 0);
543 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8))amdgpu_device_wreg(adev, (0x8617), ((adev->vce.gpu_addr >>
8)), 0);
544 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8))amdgpu_device_wreg(adev, (0x8618), ((adev->vce.gpu_addr >>
8)), 0);
545 } else
546 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8))amdgpu_device_wreg(adev, (0x8597), ((adev->vce.gpu_addr >>
8)), 0);
547 offset = AMDGPU_VCE_FIRMWARE_OFFSET256;
548 size = VCE_V3_0_FW_SIZE(384 * 1024);
549 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff)amdgpu_device_wreg(adev, (0x8009), (offset & 0x7fffffff),
0);
550 WREG32(mmVCE_VCPU_CACHE_SIZE0, size)amdgpu_device_wreg(adev, (0x800a), (size), 0);
551
552 if (idx == 0) {
553 offset += size;
554 size = VCE_V3_0_STACK_SIZE(64 * 1024);
555 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff)amdgpu_device_wreg(adev, (0x800b), (offset & 0x7fffffff),
0);
556 WREG32(mmVCE_VCPU_CACHE_SIZE1, size)amdgpu_device_wreg(adev, (0x800c), (size), 0);
557 offset += size;
558 size = VCE_V3_0_DATA_SIZE((16 * 1024 * 16) + (52 * 1024));
559 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff)amdgpu_device_wreg(adev, (0x800d), (offset & 0x7fffffff),
0);
560 WREG32(mmVCE_VCPU_CACHE_SIZE2, size)amdgpu_device_wreg(adev, (0x800e), (size), 0);
561 } else {
562 offset += size + VCE_V3_0_STACK_SIZE(64 * 1024) + VCE_V3_0_DATA_SIZE((16 * 1024 * 16) + (52 * 1024));
563 size = VCE_V3_0_STACK_SIZE(64 * 1024);
564 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff)amdgpu_device_wreg(adev, (0x800b), (offset & 0xfffffff), 0
);
565 WREG32(mmVCE_VCPU_CACHE_SIZE1, size)amdgpu_device_wreg(adev, (0x800c), (size), 0);
566 offset += size;
567 size = VCE_V3_0_DATA_SIZE((16 * 1024 * 16) + (52 * 1024));
568 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff)amdgpu_device_wreg(adev, (0x800d), (offset & 0xfffffff), 0
);
569 WREG32(mmVCE_VCPU_CACHE_SIZE2, size)amdgpu_device_wreg(adev, (0x800e), (size), 0);
570 }
571
572 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x859d), 0); tmp_
&= (~0x100); tmp_ |= ((0x0) & ~(~0x100)); amdgpu_device_wreg
(adev, (0x859d), (tmp_), 0); } while (0);
573 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1)amdgpu_device_wreg(adev, (0x8540), ((amdgpu_device_rreg(adev,
(0x8540), 0) & ~0x8) | (1) << 0x3), 0);
574}
575
576static bool_Bool vce_v3_0_is_idle(void *handle)
577{
578 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
579 u32 mask = 0;
580
581 mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0(1 << 0)) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK0x80;
582 mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1(1 << 1)) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK0x4000;
583
584 return !(RREG32(mmSRBM_STATUS2)amdgpu_device_rreg(adev, (0x393), 0) & mask);
585}
586
587static int vce_v3_0_wait_for_idle(void *handle)
588{
589 unsigned i;
590 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
591
592 for (i = 0; i < adev->usec_timeout; i++)
593 if (vce_v3_0_is_idle(handle))
594 return 0;
595
596 return -ETIMEDOUT60;
597}
598
599#define VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK0x00000008L 0x00000008L /* AUTO_BUSY */
600#define VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK0x00000010L 0x00000010L /* RB0_BUSY */
601#define VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK0x00000020L 0x00000020L /* RB1_BUSY */
602#define AMDGPU_VCE_STATUS_BUSY_MASK(0x00000008L | 0x00000010L) (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK0x00000008L | \
603 VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK0x00000010L)
604
605static bool_Bool vce_v3_0_check_soft_reset(void *handle)
606{
607 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
608 u32 srbm_soft_reset = 0;
609
610 /* According to VCE team , we should use VCE_STATUS instead
611 * SRBM_STATUS.VCE_BUSY bit for busy status checking.
612 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE
613 * instance's registers are accessed
614 * (0 for 1st instance, 10 for 2nd instance).
615 *
616 *VCE_STATUS
617 *|UENC|ACPI|AUTO ACTIVE|RB1 |RB0 |RB2 | |FW_LOADED|JOB |
618 *|----+----+-----------+----+----+----+----------+---------+----|
619 *|bit8|bit7| bit6 |bit5|bit4|bit3| bit2 | bit1 |bit0|
620 *
621 * VCE team suggest use bit 3--bit 6 for busy status check
622 */
623 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
624 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0))amdgpu_device_wreg(adev, (0xc200), (((0) << 0x04 | 0x07
)), 0);
625 if (RREG32(mmVCE_STATUS)amdgpu_device_rreg(adev, (0x8001), 0) & AMDGPU_VCE_STATUS_BUSY_MASK(0x00000008L | 0x00000010L)) {
626 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1)(((srbm_soft_reset) & ~0x1000000) | (0x1000000 & ((1)
<< 0x18)));
627 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1)(((srbm_soft_reset) & ~0x80000000) | (0x80000000 & ((
1) << 0x1f)));
628 }
629 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1))amdgpu_device_wreg(adev, (0xc200), (((1) << 0x04 | 0x07
)), 0);
630 if (RREG32(mmVCE_STATUS)amdgpu_device_rreg(adev, (0x8001), 0) & AMDGPU_VCE_STATUS_BUSY_MASK(0x00000008L | 0x00000010L)) {
631 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1)(((srbm_soft_reset) & ~0x1000000) | (0x1000000 & ((1)
<< 0x18)));
632 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1)(((srbm_soft_reset) & ~0x80000000) | (0x80000000 & ((
1) << 0x1f)));
633 }
634 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0))amdgpu_device_wreg(adev, (0xc200), (((0) << 0x04 | 0x07
)), 0);
635 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
636
637 if (srbm_soft_reset) {
638 adev->vce.srbm_soft_reset = srbm_soft_reset;
639 return true1;
640 } else {
641 adev->vce.srbm_soft_reset = 0;
642 return false0;
643 }
644}
645
646static int vce_v3_0_soft_reset(void *handle)
647{
648 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
649 u32 srbm_soft_reset;
650
651 if (!adev->vce.srbm_soft_reset)
652 return 0;
653 srbm_soft_reset = adev->vce.srbm_soft_reset;
654
655 if (srbm_soft_reset) {
656 u32 tmp;
657
658 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
659 tmp |= srbm_soft_reset;
660 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
661 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
662 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
663
664 udelay(50);
665
666 tmp &= ~srbm_soft_reset;
667 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
668 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
Value stored to 'tmp' is never read
669
670 /* Wait a little for things to settle down */
671 udelay(50);
672 }
673
674 return 0;
675}
676
677static int vce_v3_0_pre_soft_reset(void *handle)
678{
679 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
680
681 if (!adev->vce.srbm_soft_reset)
682 return 0;
683
684 mdelay(5);
685
686 return vce_v3_0_suspend(adev);
687}
688
689
690static int vce_v3_0_post_soft_reset(void *handle)
691{
692 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
693
694 if (!adev->vce.srbm_soft_reset)
695 return 0;
696
697 mdelay(5);
698
699 return vce_v3_0_resume(adev);
700}
701
702static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
703 struct amdgpu_irq_src *source,
704 unsigned type,
705 enum amdgpu_interrupt_state state)
706{
707 uint32_t val = 0;
708
709 if (state == AMDGPU_IRQ_STATE_ENABLE)
710 val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK0x8;
711
712 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, (0x8540), 0); tmp_
&= (~0x8); tmp_ |= ((val) & ~(~0x8)); amdgpu_device_wreg
(adev, (0x8540), (tmp_), 0); } while (0);
713 return 0;
714}
715
716static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
717 struct amdgpu_irq_src *source,
718 struct amdgpu_iv_entry *entry)
719{
720 DRM_DEBUG("IH: VCE\n")__drm_dbg(DRM_UT_CORE, "IH: VCE\n");
721
722 WREG32_FIELD(VCE_SYS_INT_STATUS, VCE_SYS_INT_TRAP_INTERRUPT_INT, 1)amdgpu_device_wreg(adev, (0x8541), ((amdgpu_device_rreg(adev,
(0x8541), 0) & ~0x8) | (1) << 0x3), 0);
723
724 switch (entry->src_data[0]) {
725 case 0:
726 case 1:
727 case 2:
728 amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
729 break;
730 default:
731 DRM_ERROR("Unhandled interrupt: %d %d\n",__drm_err("Unhandled interrupt: %d %d\n", entry->src_id, entry
->src_data[0])
732 entry->src_id, entry->src_data[0])__drm_err("Unhandled interrupt: %d %d\n", entry->src_id, entry
->src_data[0]);
733 break;
734 }
735
736 return 0;
737}
738
739static int vce_v3_0_set_clockgating_state(void *handle,
740 enum amd_clockgating_state state)
741{
742 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
743 bool_Bool enable = (state == AMD_CG_STATE_GATE);
744 int i;
745
746 if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG(1 << 14)))
747 return 0;
748
749 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
750 for (i = 0; i < 2; i++) {
751 /* Program VCE Instance 0 or 1 if not harvested */
752 if (adev->vce.harvest_config & (1 << i))
753 continue;
754
755 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i))amdgpu_device_wreg(adev, (0xc200), (((i) << 0x04 | 0x07
)), 0);
756
757 if (!enable) {
758 /* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */
759 uint32_t data = RREG32(mmVCE_CLOCK_GATING_A)amdgpu_device_rreg(adev, (0x80be), 0);
760 data &= ~(0xf | 0xff0);
761 data |= ((0x0 << 0) | (0x04 << 4));
762 WREG32(mmVCE_CLOCK_GATING_A, data)amdgpu_device_wreg(adev, (0x80be), (data), 0);
763
764 /* initialize VCE_UENC_CLOCK_GATING: Clock ON/OFF delay */
765 data = RREG32(mmVCE_UENC_CLOCK_GATING)amdgpu_device_rreg(adev, (0x81ef), 0);
766 data &= ~(0xf | 0xff0);
767 data |= ((0x0 << 0) | (0x04 << 4));
768 WREG32(mmVCE_UENC_CLOCK_GATING, data)amdgpu_device_wreg(adev, (0x81ef), (data), 0);
769 }
770
771 vce_v3_0_set_vce_sw_clock_gating(adev, enable);
772 }
773
774 WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT)amdgpu_device_wreg(adev, (0xc200), (0xE0000000), 0);
775 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
776
777 return 0;
778}
779
780static int vce_v3_0_set_powergating_state(void *handle,
781 enum amd_powergating_state state)
782{
783 /* This doesn't actually powergate the VCE block.
784 * That's done in the dpm code via the SMC. This
785 * just re-inits the block as necessary. The actual
786 * gating still happens in the dpm code. We should
787 * revisit this when there is a cleaner line between
788 * the smc and the hw blocks
789 */
790 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
791 int ret = 0;
792
793 if (state == AMD_PG_STATE_GATE) {
794 ret = vce_v3_0_stop(adev);
795 if (ret)
796 goto out;
797 } else {
798 ret = vce_v3_0_start(adev);
799 if (ret)
800 goto out;
801 }
802
803out:
804 return ret;
805}
806
807static void vce_v3_0_get_clockgating_state(void *handle, u32 *flags)
808{
809 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
810 int data;
811
812 mutex_lock(&adev->pm.mutex)rw_enter_write(&adev->pm.mutex);
813
814 if (adev->flags & AMD_IS_APU)
815 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU)adev->smc_rreg(adev, (0xd020029c));
816 else
817 data = RREG32_SMC(ixCURRENT_PG_STATUS)adev->smc_rreg(adev, (0xc020029c));
818
819 if (data & CURRENT_PG_STATUS__VCE_PG_STATUS_MASK0x00000002) {
820 DRM_INFO("Cannot get clockgating state when VCE is powergated.\n")printk("\0016" "[" "drm" "] " "Cannot get clockgating state when VCE is powergated.\n"
);
821 goto out;
822 }
823
824 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0)amdgpu_device_wreg(adev, (0xc200), ((amdgpu_device_rreg(adev,
(0xc200), 0) & ~0x10) | (0) << 0x04), 0);
825
826 /* AMD_CG_SUPPORT_VCE_MGCG */
827 data = RREG32(mmVCE_CLOCK_GATING_A)amdgpu_device_rreg(adev, (0x80be), 0);
828 if (data & (0x04 << 4))
829 *flags |= AMD_CG_SUPPORT_VCE_MGCG(1 << 14);
830
831out:
832 mutex_unlock(&adev->pm.mutex)rw_exit_write(&adev->pm.mutex);
833}
834
835static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
836 struct amdgpu_job *job,
837 struct amdgpu_ib *ib,
838 uint32_t flags)
839{
840 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
841
842 amdgpu_ring_write(ring, VCE_CMD_IB_VM0x00000102);
843 amdgpu_ring_write(ring, vmid);
844 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)));
845 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
846 amdgpu_ring_write(ring, ib->length_dw);
847}
848
849static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
850 unsigned int vmid, uint64_t pd_addr)
851{
852 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB0x00000107);
853 amdgpu_ring_write(ring, vmid);
854 amdgpu_ring_write(ring, pd_addr >> 12);
855
856 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB0x00000108);
857 amdgpu_ring_write(ring, vmid);
858 amdgpu_ring_write(ring, VCE_CMD_END0x00000001);
859}
860
861static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring)
862{
863 uint32_t seq = ring->fence_drv.sync_seq;
864 uint64_t addr = ring->fence_drv.gpu_addr;
865
866 amdgpu_ring_write(ring, VCE_CMD_WAIT_GE0x00000106);
867 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
868 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
869 amdgpu_ring_write(ring, seq);
870}
871
872static const struct amd_ip_funcs vce_v3_0_ip_funcs = {
873 .name = "vce_v3_0",
874 .early_init = vce_v3_0_early_init,
875 .late_init = NULL((void *)0),
876 .sw_init = vce_v3_0_sw_init,
877 .sw_fini = vce_v3_0_sw_fini,
878 .hw_init = vce_v3_0_hw_init,
879 .hw_fini = vce_v3_0_hw_fini,
880 .suspend = vce_v3_0_suspend,
881 .resume = vce_v3_0_resume,
882 .is_idle = vce_v3_0_is_idle,
883 .wait_for_idle = vce_v3_0_wait_for_idle,
884 .check_soft_reset = vce_v3_0_check_soft_reset,
885 .pre_soft_reset = vce_v3_0_pre_soft_reset,
886 .soft_reset = vce_v3_0_soft_reset,
887 .post_soft_reset = vce_v3_0_post_soft_reset,
888 .set_clockgating_state = vce_v3_0_set_clockgating_state,
889 .set_powergating_state = vce_v3_0_set_powergating_state,
890 .get_clockgating_state = vce_v3_0_get_clockgating_state,
891};
892
893static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
894 .type = AMDGPU_RING_TYPE_VCE,
895 .align_mask = 0xf,
896 .nop = VCE_CMD_NO_OP0x00000000,
897 .support_64bit_ptrs = false0,
898 .no_user_fence = true1,
899 .get_rptr = vce_v3_0_ring_get_rptr,
900 .get_wptr = vce_v3_0_ring_get_wptr,
901 .set_wptr = vce_v3_0_ring_set_wptr,
902 .parse_cs = amdgpu_vce_ring_parse_cs,
903 .emit_frame_size =
904 4 + /* vce_v3_0_emit_pipeline_sync */
905 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */
906 .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
907 .emit_ib = amdgpu_vce_ring_emit_ib,
908 .emit_fence = amdgpu_vce_ring_emit_fence,
909 .test_ring = amdgpu_vce_ring_test_ring,
910 .test_ib = amdgpu_vce_ring_test_ib,
911 .insert_nop = amdgpu_ring_insert_nop,
912 .pad_ib = amdgpu_ring_generic_pad_ib,
913 .begin_use = amdgpu_vce_ring_begin_use,
914 .end_use = amdgpu_vce_ring_end_use,
915};
916
917static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
918 .type = AMDGPU_RING_TYPE_VCE,
919 .align_mask = 0xf,
920 .nop = VCE_CMD_NO_OP0x00000000,
921 .support_64bit_ptrs = false0,
922 .no_user_fence = true1,
923 .get_rptr = vce_v3_0_ring_get_rptr,
924 .get_wptr = vce_v3_0_ring_get_wptr,
925 .set_wptr = vce_v3_0_ring_set_wptr,
926 .parse_cs = amdgpu_vce_ring_parse_cs_vm,
927 .emit_frame_size =
928 6 + /* vce_v3_0_emit_vm_flush */
929 4 + /* vce_v3_0_emit_pipeline_sync */
930 6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */
931 .emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */
932 .emit_ib = vce_v3_0_ring_emit_ib,
933 .emit_vm_flush = vce_v3_0_emit_vm_flush,
934 .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync,
935 .emit_fence = amdgpu_vce_ring_emit_fence,
936 .test_ring = amdgpu_vce_ring_test_ring,
937 .test_ib = amdgpu_vce_ring_test_ib,
938 .insert_nop = amdgpu_ring_insert_nop,
939 .pad_ib = amdgpu_ring_generic_pad_ib,
940 .begin_use = amdgpu_vce_ring_begin_use,
941 .end_use = amdgpu_vce_ring_end_use,
942};
943
944static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
945{
946 int i;
947
948 if (adev->asic_type >= CHIP_STONEY) {
949 for (i = 0; i < adev->vce.num_rings; i++) {
950 adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;
951 adev->vce.ring[i].me = i;
952 }
953 DRM_INFO("VCE enabled in VM mode\n")printk("\0016" "[" "drm" "] " "VCE enabled in VM mode\n");
954 } else {
955 for (i = 0; i < adev->vce.num_rings; i++) {
956 adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;
957 adev->vce.ring[i].me = i;
958 }
959 DRM_INFO("VCE enabled in physical mode\n")printk("\0016" "[" "drm" "] " "VCE enabled in physical mode\n"
);
960 }
961}
962
963static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = {
964 .set = vce_v3_0_set_interrupt_state,
965 .process = vce_v3_0_process_interrupt,
966};
967
968static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)
969{
970 adev->vce.irq.num_types = 1;
971 adev->vce.irq.funcs = &vce_v3_0_irq_funcs;
972};
973
974const struct amdgpu_ip_block_version vce_v3_0_ip_block =
975{
976 .type = AMD_IP_BLOCK_TYPE_VCE,
977 .major = 3,
978 .minor = 0,
979 .rev = 0,
980 .funcs = &vce_v3_0_ip_funcs,
981};
982
983const struct amdgpu_ip_block_version vce_v3_1_ip_block =
984{
985 .type = AMD_IP_BLOCK_TYPE_VCE,
986 .major = 3,
987 .minor = 1,
988 .rev = 0,
989 .funcs = &vce_v3_0_ip_funcs,
990};
991
992const struct amdgpu_ip_block_version vce_v3_4_ip_block =
993{
994 .type = AMD_IP_BLOCK_TYPE_VCE,
995 .major = 3,
996 .minor = 4,
997 .rev = 0,
998 .funcs = &vce_v3_0_ip_funcs,
999};