/usr/src/sys/dev/pci/drm/i915/display/intel

Bug Summary

File:	dev/pci/drm/i915/display/intel_psr.c
Warning:	line 1696, column 60 The left operand of '&' is a garbage value
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name intel_psr.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/i915/display/intel_psr.c
1/*
* Copyright © 2014 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/

24#include <drm/drm_atomic_helper.h>

26#include "display/intel_dp.h"

28#include "i915_drv.h"
29#include "intel_atomic.h"
30#include "intel_display_types.h"
31#include "intel_psr.h"
32#include "intel_sprite.h"
33#include "intel_hdmi.h"

35/**
* DOC: Panel Self Refresh (PSR/SRD)
*
* Since Haswell Display controller supports Panel Self-Refresh on display
* panels witch have a remote frame buffer (RFB) implemented according to PSR
* spec in eDP1.3. PSR feature allows the display to go to lower standby states
* when system is idle but display is on as it eliminates display refresh
* request to DDR memory completely as long as the frame buffer for that
* display is unchanged.
*
* Panel Self Refresh must be supported by both Hardware (source) and
* Panel (sink).
*
* PSR saves power by caching the framebuffer in the panel RFB, which allows us
* to power down the link and memory controller. For DSI panels the same idea
* is called "manual mode".
*
* The implementation uses the hardware-based PSR support which automatically
* enters/exits self-refresh mode. The hardware takes care of sending the
* required DP aux message and could even retrain the link (that part isn't
* enabled yet though). The hardware also keeps track of any frontbuffer
* changes to know when to exit self-refresh mode again. Unfortunately that
* part doesn't work too well, hence why the i915 PSR support uses the
* software frontbuffer tracking to make sure it doesn't miss a screen
* update. For this integration intel_psr_invalidate() and intel_psr_flush()
* get called by the frontbuffer tracking code. Note that because of locking
* issues the self-refresh re-enable code is done from a work queue, which
* must be correctly synchronized/cancelled when shutting down the pipe."
*
* DC3CO (DC3 clock off)
*
* On top of PSR2, GEN12 adds a intermediate power savings state that turns
* clock off automatically during PSR2 idle state.
* The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
* entry/exit allows the HW to enter a low-power state even when page flipping
* periodically (for instance a 30fps video playback scenario).
*
* Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
* so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
* frames, if no other flip occurs and the function above is executed, DC3CO is
* disabled and PSR2 is configured to enter deep sleep, resetting again in case
* of another flip.
* Front buffer modifications do not trigger DC3CO activation on purpose as it
* would bring a lot of complexity and most of the moderns systems will only
* use page flips.
*/

82static bool_Bool psr_global_enabled(struct drm_i915_privateinteldrm_softc *i915)
83{
switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK0x0f) {
case I915_PSR_DEBUG_DEFAULT0x00:
return i915->params.enable_psr;
case I915_PSR_DEBUG_DISABLE0x01:
return false0;
default:
return true1;
}
92}

94static bool_Bool intel_psr2_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
	       const struct intel_crtc_state *crtc_state)
96{
/* Cannot enable DSC and PSR2 simultaneously */
drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable &&({ int __ret = !!((crtc_state->dsc.compression_enable &&
 crtc_state->has_psr2)); if (__ret) printf("%s %s: " "%s",
 dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
 "crtc_state->dsc.compression_enable && crtc_state->has_psr2"
 ")"); __builtin_expect(!!(__ret), 0); })
    crtc_state->has_psr2)({ int __ret = !!((crtc_state->dsc.compression_enable &&
 crtc_state->has_psr2)); if (__ret) printf("%s %s: " "%s",
 dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
 "crtc_state->dsc.compression_enable && crtc_state->has_psr2"
 ")"); __builtin_expect(!!(__ret), 0); });

switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK0x0f) {
case I915_PSR_DEBUG_DISABLE0x01:
case I915_PSR_DEBUG_FORCE_PSR10x03:
return false0;
default:
return crtc_state->has_psr2;
}
108}

110static void psr_irq_control(struct drm_i915_privateinteldrm_softc *dev_priv)
111{
enum transcoder trans_shift;
u32 mask, val;
i915_reg_t imr_reg;

/*
* gen12+ has registers relative to transcoder and one per transcoder
* using the same bit definition: handle it as TRANSCODER_EDP to force
* 0 shift in bit definition
*/
if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
trans_shift = 0;
imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60814) + (
(&(dev_priv)->__info)->display_mmio_offset))) });
} else {
trans_shift = dev_priv->psr.transcoder;
imr_reg = EDP_PSR_IMR((const i915_reg_t){ .reg = (0x64834) });
}

mask = EDP_PSR_ERROR(trans_shift)(0x4 << ((trans_shift) == TRANSCODER_EDP ? 0 : ((trans_shift
) - TRANSCODER_A + 1) * 8));
if (dev_priv->psr.debug & I915_PSR_DEBUG_IRQ0x10)
mask |= EDP_PSR_POST_EXIT(trans_shift)(0x2 << ((trans_shift) == TRANSCODER_EDP ? 0 : ((trans_shift
) - TRANSCODER_A + 1) * 8)) |
	EDP_PSR_PRE_ENTRY(trans_shift)(0x1 << ((trans_shift) == TRANSCODER_EDP ? 0 : ((trans_shift
) - TRANSCODER_A + 1) * 8));

/* Warning: it is masking/setting reserved bits too */
val = intel_de_read(dev_priv, imr_reg);
val &= ~EDP_PSR_TRANS_MASK(trans_shift)(0x7 << ((trans_shift) == TRANSCODER_EDP ? 0 : ((trans_shift
) - TRANSCODER_A + 1) * 8));
val |= ~mask;
intel_de_write(dev_priv, imr_reg, val);
139}

141static void psr_event_print(struct drm_i915_privateinteldrm_softc *i915,
	    u32 val, bool_Bool psr2_enabled)
143{
drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "PSR exit events: 0x%x\n"
, val);
if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE(1 << 17))
drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tPSR2 watchdog timer expired\n"
);
if ((val & PSR_EVENT_PSR2_DISABLED(1 << 16)) && psr2_enabled)
drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tPSR2 disabled\n"
);
if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN(1 << 15))
drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tSU dirty FIFO underrun\n"
);
if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN(1 << 14))
drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tSU CRC FIFO underrun\n"
);
if (val & PSR_EVENT_GRAPHICS_RESET(1 << 12))
drm_dbg_kms(&i915->drm, "\tGraphics reset\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tGraphics reset\n"
);
if (val & PSR_EVENT_PCH_INTERRUPT(1 << 11))
drm_dbg_kms(&i915->drm, "\tPCH interrupt\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tPCH interrupt\n"
);
if (val & PSR_EVENT_MEMORY_UP(1 << 10))
drm_dbg_kms(&i915->drm, "\tMemory up\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tMemory up\n"
);
if (val & PSR_EVENT_FRONT_BUFFER_MODIFY(1 << 9))
drm_dbg_kms(&i915->drm, "\tFront buffer modification\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tFront buffer modification\n"
);
if (val & PSR_EVENT_WD_TIMER_EXPIRE(1 << 8))
drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tPSR watchdog timer expired\n"
);
if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE(1 << 6))
drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tPIPE registers updated\n"
);
if (val & PSR_EVENT_REGISTER_UPDATE(1 << 5))
drm_dbg_kms(&i915->drm, "\tRegister updated\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tRegister updated\n"
);
if (val & PSR_EVENT_HDCP_ENABLE(1 << 4))
drm_dbg_kms(&i915->drm, "\tHDCP enabled\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tHDCP enabled\n"
);
if (val & PSR_EVENT_KVMR_SESSION_ENABLE(1 << 3))
drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tKVMR session enabled\n"
);
if (val & PSR_EVENT_VBI_ENABLE(1 << 2))
drm_dbg_kms(&i915->drm, "\tVBI enabled\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tVBI enabled\n"
);
if (val & PSR_EVENT_LPSP_MODE_EXIT(1 << 1))
drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tLPSP mode exited\n"
);
if ((val & PSR_EVENT_PSR_DISABLE(1 << 0)) && !psr2_enabled)
drm_dbg_kms(&i915->drm, "\tPSR disabled\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tPSR disabled\n"
);
177}

179void intel_psr_irq_handler(struct drm_i915_privateinteldrm_softc *dev_priv, u32 psr_iir)
180{
enum transcoder cpu_transcoder = dev_priv->psr.transcoder;
enum transcoder trans_shift;
i915_reg_t imr_reg;
ktime_t time_ns =  ktime_get();

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
trans_shift = 0;
imr_reg = TRANS_PSR_IMR(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60814) + (
(&(dev_priv)->__info)->display_mmio_offset))) });
} else {
trans_shift = dev_priv->psr.transcoder;
imr_reg = EDP_PSR_IMR((const i915_reg_t){ .reg = (0x64834) });
}

if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)(0x1 << ((trans_shift) == TRANSCODER_EDP ? 0 : ((trans_shift
) - TRANSCODER_A + 1) * 8))) {
dev_priv->psr.last_entry_attempt = time_ns;
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[transcoder %s] PSR entry attempt in 2 vblanks\n"
, transcoder_name(cpu_transcoder))
	    "[transcoder %s] PSR entry attempt in 2 vblanks\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[transcoder %s] PSR entry attempt in 2 vblanks\n"
, transcoder_name(cpu_transcoder))
	    transcoder_name(cpu_transcoder))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[transcoder %s] PSR entry attempt in 2 vblanks\n"
, transcoder_name(cpu_transcoder));
}

if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)(0x2 << ((trans_shift) == TRANSCODER_EDP ? 0 : ((trans_shift
) - TRANSCODER_A + 1) * 8))) {
dev_priv->psr.last_exit = time_ns;
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[transcoder %s] PSR exit completed\n"
, transcoder_name(cpu_transcoder))
	    "[transcoder %s] PSR exit completed\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[transcoder %s] PSR exit completed\n"
, transcoder_name(cpu_transcoder))
	    transcoder_name(cpu_transcoder))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[transcoder %s] PSR exit completed\n"
, transcoder_name(cpu_transcoder));

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) {
	u32 val = intel_de_read(dev_priv,
				PSR_EVENT(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info
)->trans_offsets[TRANSCODER_A] + (0x60848) + ((&(dev_priv
)->__info)->display_mmio_offset))) }));
	bool_Bool psr2_enabled = dev_priv->psr.psr2_enabled;

	intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info
)->trans_offsets[TRANSCODER_A] + (0x60848) + ((&(dev_priv
)->__info)->display_mmio_offset))) }),
		       val);
	psr_event_print(dev_priv, val, psr2_enabled);
}
}

if (psr_iir & EDP_PSR_ERROR(trans_shift)(0x4 << ((trans_shift) == TRANSCODER_EDP ? 0 : ((trans_shift
) - TRANSCODER_A + 1) * 8))) {
u32 val;

drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",printf("drm:pid%d:%s *WARNING* " "[drm] " "[transcoder %s] PSR aux error\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , transcoder_name
(cpu_transcoder))
	 transcoder_name(cpu_transcoder))printf("drm:pid%d:%s *WARNING* " "[drm] " "[transcoder %s] PSR aux error\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , transcoder_name
(cpu_transcoder));

dev_priv->psr.irq_aux_error = true1;

/*
 * If this interruption is not masked it will keep
 * interrupting so fast that it prevents the scheduled
 * work to run.
 * Also after a PSR error, we don't want to arm PSR
 * again so we don't care about unmask the interruption
 * or unset irq_aux_error.
 */
val = intel_de_read(dev_priv, imr_reg);
val |= EDP_PSR_ERROR(trans_shift)(0x4 << ((trans_shift) == TRANSCODER_EDP ? 0 : ((trans_shift
) - TRANSCODER_A + 1) * 8));
intel_de_write(dev_priv, imr_reg, val);

schedule_work(&dev_priv->psr.work);
}
240}

242static bool_Bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
243{
u8 alpm_caps = 0;

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP0x02e,
	      &alpm_caps) != 1)
return false0;
return alpm_caps & DP_ALPM_CAP(1 << 0);
250}

252static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
253{
struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp);
u8 val = 8; /* assume the worst if we can't read the value */

if (drm_dp_dpcd_readb(&intel_dp->aux,
	      DP_SYNCHRONIZATION_LATENCY_IN_SINK0x2009, &val) == 1)
val &= DP_MAX_RESYNC_FRAME_COUNT_MASK(0xf << 0);
else
drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unable to get sink synchronization latency, assuming 8 frames\n"
)
	    "Unable to get sink synchronization latency, assuming 8 frames\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unable to get sink synchronization latency, assuming 8 frames\n"
);
return val;
264}

266static u16 intel_dp_get_su_x_granulartiy(struct intel_dp *intel_dp)
267{
struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp);
u16 val;
ssize_t r;

/*
* Returning the default X granularity if granularity not required or
* if DPCD read fails
*/
if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED(1 << 5)))
return 4;

r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY0x072, &val, 2);
if (r != 2)
drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unable to read DP_PSR2_SU_X_GRANULARITY\n"
)
	    "Unable to read DP_PSR2_SU_X_GRANULARITY\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unable to read DP_PSR2_SU_X_GRANULARITY\n"
);

/*
* Spec says that if the value read is 0 the default granularity should
* be used instead.
*/
if (r != 2 || val == 0)
val = 4;

return val;
292}

294void intel_psr_init_dpcd(struct intel_dp *intel_dp)
295{
struct drm_i915_privateinteldrm_softc *dev_priv =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);

if (dev_priv->psr.dp) {
drm_warn(&dev_priv->drm,printf("drm:pid%d:%s *WARNING* " "[drm] " "More than one eDP panel found, PSR support should be extended\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
	 "More than one eDP panel found, PSR support should be extended\n")printf("drm:pid%d:%s *WARNING* " "[drm] " "More than one eDP panel found, PSR support should be extended\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return;
}

drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT0x070, intel_dp->psr_dpcd,
	 sizeof(intel_dp->psr_dpcd));

if (!intel_dp->psr_dpcd[0])
return;
drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "eDP panel supports PSR version %x\n"
, intel_dp->psr_dpcd[0])
    intel_dp->psr_dpcd[0])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "eDP panel supports PSR version %x\n"
, intel_dp->psr_dpcd[0]);

if (drm_dp_has_quirk(&intel_dp->desc, 0, DP_DPCD_QUIRK_NO_PSR)) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR support not currently available for this panel\n"
)
	    "PSR support not currently available for this panel\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR support not currently available for this panel\n"
);
return;
}

if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP(1 << 7))) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Panel lacks power state control, PSR cannot be enabled\n"
)
	    "Panel lacks power state control, PSR cannot be enabled\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Panel lacks power state control, PSR cannot be enabled\n"
);
return;
}

dev_priv->psr.sink_support = true1;
dev_priv->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);

dev_priv->psr.dp = intel_dp;

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 &&
   (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED3)) {
bool_Bool y_req = intel_dp->psr_dpcd[1] &
	     DP_PSR2_SU_Y_COORDINATE_REQUIRED(1 << 4);
bool_Bool alpm = intel_dp_get_alpm_status(intel_dp);

/*
 * All panels that supports PSR version 03h (PSR2 +
 * Y-coordinate) can handle Y-coordinates in VSC but we are
 * only sure that it is going to be used when required by the
 * panel. This way panel is capable to do selective update
 * without a aux frame sync.
 *
 * To support PSR version 02h and PSR version 03h without
 * Y-coordinate requirement panels we would need to enable
 * GTC first.
 */
dev_priv->psr.sink_psr2_support = y_req && alpm;
drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 %ssupported\n"
, dev_priv->psr.sink_psr2_support ? "" : "not ")
	    dev_priv->psr.sink_psr2_support ? "" : "not ")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 %ssupported\n"
, dev_priv->psr.sink_psr2_support ? "" : "not ");

if (dev_priv->psr.sink_psr2_support) {
	dev_priv->psr.colorimetry_support =
		intel_dp_get_colorimetry_status(intel_dp);
	dev_priv->psr.su_x_granularity =
		intel_dp_get_su_x_granulartiy(intel_dp);
}
}
359}

361static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
362{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
u32 aux_clock_divider, aux_ctl;
int i;
static const u8 aux_msg[] = {
[0] = DP_AUX_NATIVE_WRITE0x8 << 4,
[1] = DP_SET_POWER0x600 >> 8,
[2] = DP_SET_POWER0x600 & 0xff,
[3] = 1 - 1,
[4] = DP_SET_POWER_D00x1,
};
u32 psr_aux_mask = EDP_PSR_AUX_CTL_TIME_OUT_MASK(3 << 26) |
	   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK(0x1f << 20) |
	   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK(0xf << 16) |
	   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK(0x7ff);

BUILD_BUG_ON(sizeof(aux_msg) > 20)extern char _ctassert[(!(sizeof(aux_msg) > 20)) ? 1 : -1 ]
 __attribute__((__unused__));
for (i = 0; i < sizeof(aux_msg); i += 4)
intel_de_write(dev_priv,
	       EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60814) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust) + (i >> 2) + 4) }),
	       intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));

aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

/* Start with bits set for DDI_AUX_CTL register */
aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
			     aux_clock_divider);

/* Select only valid bits for SRD_AUX_CTL */
aux_ctl &= psr_aux_mask;
intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60810) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) }),
       aux_ctl);
394}

396static void intel_psr_enable_sink(struct intel_dp *intel_dp)
397{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE(1 << 0);

/* Enable ALPM at sink for psr2 */
if (dev_priv->psr.psr2_enabled) {
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG0x116,
		   DP_ALPM_ENABLE(1 << 0) |
		   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE(1 << 1));

dpcd_val |= DP_PSR_ENABLE_PSR2(1 << 6) | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS(1 << 5);
} else {
if (dev_priv->psr.link_standby)
	dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE(1 << 1);

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 8)
	dpcd_val |= DP_PSR_CRC_VERIFICATION(1 << 2);
}

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG0x170, dpcd_val);

drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER0x600, DP_SET_POWER_D00x1);
419}

421static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
422{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11)
val |= EDP_PSR_TP4_TIME_0US(3 << 6);

if (dev_priv->params.psr_safest_params) {
val |= EDP_PSR_TP1_TIME_2500us(2 << 4);
val |= EDP_PSR_TP2_TP3_TIME_2500us(2 << 8);
goto check_tp3_sel;
}

if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
val |= EDP_PSR_TP1_TIME_0us(3 << 4);
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
val |= EDP_PSR_TP1_TIME_100us(1 << 4);
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
val |= EDP_PSR_TP1_TIME_500us(0 << 4);
else
val |= EDP_PSR_TP1_TIME_2500us(2 << 4);

if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
val |= EDP_PSR_TP2_TP3_TIME_0us(3 << 8);
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR_TP2_TP3_TIME_100us(1 << 8);
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR_TP2_TP3_TIME_500us(0 << 8);
else
val |= EDP_PSR_TP2_TP3_TIME_2500us(2 << 8);

453check_tp3_sel:
if (intel_dp_source_supports_hbr2(intel_dp) &&
   drm_dp_tps3_supported(intel_dp->dpcd))
val |= EDP_PSR_TP1_TP3_SEL(1 << 11);
else
val |= EDP_PSR_TP1_TP2_SEL(0 << 11);

return val;
461}

463static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
464{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
int idle_frames;

/* Let's use 6 as the minimum to cover all known cases including the
* off-by-one issue that HW has in some cases.
*/
idle_frames = max(6, dev_priv->vbt.psr.idle_frames)(((6)>(dev_priv->vbt.psr.idle_frames))?(6):(dev_priv->
vbt.psr.idle_frames));
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1)(((idle_frames)>(dev_priv->psr.sink_sync_latency + 1))?
(idle_frames):(dev_priv->psr.sink_sync_latency + 1));

if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)({ int __ret = !!((idle_frames > 0xf)); if (__ret) printf(
"%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "idle_frames > 0xf" ")"); __builtin_expect
(!!(__ret), 0); }))
idle_frames = 0xf;

return idle_frames;
478}

480static void hsw_activate_psr1(struct intel_dp *intel_dp)
481{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
u32 max_sleep_time = 0x1f;
u32 val = EDP_PSR_ENABLE(1 << 31);

val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT0;

val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT20;
if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL))
val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES(0 << 25);

if (dev_priv->psr.link_standby)
val |= EDP_PSR_LINK_STANDBY(1 << 27);

val |= intel_psr1_get_tp_time(intel_dp);

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 8)
val |= EDP_PSR_CRC_ENABLE(1 << 10);

val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) })) &
EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK(1 << 29));
intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) }), val);
503}

505static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
506{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;

if (dev_priv->params.psr_safest_params)
return EDP_PSR2_TP2_TIME_2500us(2 << 8);

if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
   dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
val |= EDP_PSR2_TP2_TIME_50us(3 << 8);
else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR2_TP2_TIME_100us(1 << 8);
else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR2_TP2_TIME_500us(0 << 8);
else
val |= EDP_PSR2_TP2_TIME_2500us(2 << 8);

return val;
524}

526static void hsw_activate_psr2(struct intel_dp *intel_dp)
527{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
u32 val;

val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT0;

val |= EDP_PSR2_ENABLE(1 << 31) | EDP_SU_TRACK_ENABLE(1 << 30);
if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE))
val |= EDP_Y_COORDINATE_ENABLE(1 << 25);

val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1)((dev_priv->psr.sink_sync_latency + 1) << 4);
val |= intel_psr2_get_tp_time(intel_dp);

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
/*
 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
 * values from BSpec. In order to setting an optimal power
 * consumption, lower than 4k resoluition mode needs to decrese
 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
 */
val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2(0 << 28);
val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7)(((7) - 5) << 13);
val |= TGL_EDP_PSR2_FAST_WAKE(7)(((7) - 5) << 10);
} else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) {
val |= EDP_PSR2_IO_BUFFER_WAKE(7)((8 - (7)) << 13);
val |= EDP_PSR2_FAST_WAKE(7)((8 - (7)) << 11);
}

if (dev_priv->psr.psr2_sel_fetch_enabled) {
/* WA 1408330847 */
if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)(IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) && tgl_revids_get
(dev_priv)->disp_stepping >= (TGL_REVID_A0) && tgl_revids_get
(dev_priv)->disp_stepping <= (TGL_REVID_A0)) ||
    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)(IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) && (((dev_priv
)->drm.pdev->revision) >= (0x0) && ((dev_priv
)->drm.pdev->revision) <= (0x0))))
	intel_de_rmw(dev_priv, CHICKEN_PAR1_1((const i915_reg_t){ .reg = (0x42080) }),
		     DIS_RAM_BYPASS_PSR2_MAN_TRACK(1 << 16),
		     DIS_RAM_BYPASS_PSR2_MAN_TRACK(1 << 16));

intel_de_write(dev_priv,
	       PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60910) + (
(&(dev_priv)->__info)->display_mmio_offset))) }),
	       PSR2_MAN_TRK_CTL_ENABLE((u32)((1UL << (31)) + 0)));
} else if (HAS_PSR2_SEL_FETCH(dev_priv)(((&(dev_priv)->__info)->gen) >= 12)) {
intel_de_write(dev_priv,
	       PSR2_MAN_TRK_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60910) + (
(&(dev_priv)->__info)->display_mmio_offset))) }), 0);
}

/*
* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
* recommending keep this bit unset while PSR2 is enabled.
*/
intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) }), 0);

intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60900) + (
(&(dev_priv)->__info)->display_mmio_offset))) }), val);
579}

581static bool_Bool
582transcoder_has_psr2(struct drm_i915_privateinteldrm_softc *dev_priv, enum transcoder trans)
583{
if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9)
return false0;
else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12)
return trans == TRANSCODER_A;
else
return trans == TRANSCODER_EDP;
590}

592static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
593{
if (!cstate || !cstate->hw.active)
return 0;

return DIV_ROUND_UP(1000 * 1000,(((1000 * 1000) + ((drm_mode_vrefresh(&cstate->hw.adjusted_mode
)) - 1)) / (drm_mode_vrefresh(&cstate->hw.adjusted_mode
)))
	    drm_mode_vrefresh(&cstate->hw.adjusted_mode))(((1000 * 1000) + ((drm_mode_vrefresh(&cstate->hw.adjusted_mode
)) - 1)) / (drm_mode_vrefresh(&cstate->hw.adjusted_mode
)));
599}

601static void psr2_program_idle_frames(struct drm_i915_privateinteldrm_softc *dev_priv,
		     u32 idle_frames)
603{
u32 val;

idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT0;
val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60900) + (
(&(dev_priv)->__info)->display_mmio_offset))) }));
val &= ~EDP_PSR2_IDLE_FRAME_MASK0xf;
val |= idle_frames;
intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60900) + (
(&(dev_priv)->__info)->display_mmio_offset))) }), val);
611}

613static void tgl_psr2_enable_dc3co(struct drm_i915_privateinteldrm_softc *dev_priv)
614{
psr2_program_idle_frames(dev_priv, 0);
intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO((u32)((1UL << (30)) + 0)));
617}

619static void tgl_psr2_disable_dc3co(struct drm_i915_privateinteldrm_softc *dev_priv)
620{
struct intel_dp *intel_dp = dev_priv->psr.dp;

intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6(2 << 0));
psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp));
625}

627static void tgl_dc3co_disable_work(struct work_struct *work)
628{
struct drm_i915_privateinteldrm_softc *dev_priv =
container_of(work, typeof(*dev_priv), psr.dc3co_work.work)({ const __typeof( ((typeof(*dev_priv) *)0)->psr.dc3co_work
.work ) *__mptr = (work); (typeof(*dev_priv) *)( (char *)__mptr
 - __builtin_offsetof(typeof(*dev_priv), psr.dc3co_work.work)
 );});

mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);
/* If delayed work is pending, it is not idle */
if (delayed_work_pending(&dev_priv->psr.dc3co_work))
goto unlock;

tgl_psr2_disable_dc3co(dev_priv);
638unlock:
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
640}

642static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_privateinteldrm_softc *dev_priv)
643{
if (!dev_priv->psr.dc3co_enabled)
return;

cancel_delayed_work(&dev_priv->psr.dc3co_work);
/* Before PSR2 exit disallow dc3co*/
tgl_psr2_disable_dc3co(dev_priv);
650}

652static void
653tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
		  struct intel_crtc_state *crtc_state)
655{
const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
u32 exit_scanlines;

if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO((u32)((1UL << (30)) + 0))))
return;

/* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
if (to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
 = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})->pipe != PIPE_A ||
   dig_port->base.port != PORT_A)
return;

/*
* DC3CO Exit time 200us B.Spec 49196
* PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
*/
exit_scanlines =
intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;

if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)({ int __ret = !!((exit_scanlines > crtc_vdisplay)); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "exit_scanlines > crtc_vdisplay"
 ")"); __builtin_expect(!!(__ret), 0); }))
return;

crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
680}

682static bool_Bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
			      struct intel_crtc_state *crtc_state)
684{
struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base )
 *__mptr = (crtc_state->uapi.state); (struct intel_atomic_state
 *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state
, base) );});
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
struct intel_plane_state *plane_state;
struct intel_plane *plane;
int i;

if (!dev_priv->params.enable_psr2_sel_fetch) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 sel fetch not enabled, disabled by parameter\n"
)
	    "PSR2 sel fetch not enabled, disabled by parameter\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 sel fetch not enabled, disabled by parameter\n"
);
return false0;
}

if (crtc_state->uapi.async_flip) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 sel fetch not enabled, async flip enabled\n"
)
	    "PSR2 sel fetch not enabled, async flip enabled\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 sel fetch not enabled, async flip enabled\n"
);
return false0;
}

for_each_new_intel_plane_in_state(state, plane, plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane
 && ((plane) = ({ const __typeof( ((struct intel_plane
 *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); (
struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct
 intel_plane, base) );}), (plane_state) = ({ const __typeof( (
(struct intel_plane_state *)0)->uapi ) *__mptr = ((state)->
base.planes[i].new_state); (struct intel_plane_state *)( (char
 *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi
) );}), 1); (i)++) if (!(plane)) {} else {
if (plane_state->uapi.rotation != DRM_MODE_ROTATE_0(1<<0)) {
	drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 sel fetch not enabled, plane rotated\n"
)
		    "PSR2 sel fetch not enabled, plane rotated\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 sel fetch not enabled, plane rotated\n"
);
	return false0;
}
}

return crtc_state->enable_psr2_sel_fetch = true1;
712}

714static bool_Bool intel_psr2_config_valid(struct intel_dp *intel_dp,
		    struct intel_crtc_state *crtc_state)
716{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;

if (!dev_priv->psr.sink_psr2_support)
return false0;

if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not supported in transcoder %s\n"
, transcoder_name(crtc_state->cpu_transcoder))
	    "PSR2 not supported in transcoder %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not supported in transcoder %s\n"
, transcoder_name(crtc_state->cpu_transcoder))
	    transcoder_name(crtc_state->cpu_transcoder))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not supported in transcoder %s\n"
, transcoder_name(crtc_state->cpu_transcoder));
return false0;
}

/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
* over PSR2.
*/
if (crtc_state->dsc.compression_enable) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 cannot be enabled since DSC is enabled\n"
)
	    "PSR2 cannot be enabled since DSC is enabled\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 cannot be enabled since DSC is enabled\n"
);
return false0;
}

if (crtc_state->crc_enabled) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled because it would inhibit pipe CRC calculation\n"
)
	    "PSR2 not enabled because it would inhibit pipe CRC calculation\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled because it would inhibit pipe CRC calculation\n"
);
return false0;
}

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
psr_max_h = 5120;
psr_max_v = 3200;
max_bpp = 30;
} else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
psr_max_h = 4096;
psr_max_v = 2304;
max_bpp = 24;
} else if (IS_GEN(dev_priv, 9)(0 + (&(dev_priv)->__info)->gen == (9))) {
psr_max_h = 3640;
psr_max_v = 2304;
max_bpp = 24;
}

if (crtc_state->pipe_bpp > max_bpp) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, pipe bpp %d > max supported %d\n"
, crtc_state->pipe_bpp, max_bpp)
	    "PSR2 not enabled, pipe bpp %d > max supported %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, pipe bpp %d > max supported %d\n"
, crtc_state->pipe_bpp, max_bpp)
	    crtc_state->pipe_bpp, max_bpp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, pipe bpp %d > max supported %d\n"
, crtc_state->pipe_bpp, max_bpp);
return false0;
}

/*
* HW sends SU blocks of size four scan lines, which means the starting
* X coordinate and Y granularity requirements will always be met. We
* only need to validate the SU block width is a multiple of
* x granularity.
*/
if (crtc_hdisplay % dev_priv->psr.su_x_granularity) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, hdisplay(%d) not multiple of %d\n"
, crtc_hdisplay, dev_priv->psr.su_x_granularity)
	    "PSR2 not enabled, hdisplay(%d) not multiple of %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, hdisplay(%d) not multiple of %d\n"
, crtc_hdisplay, dev_priv->psr.su_x_granularity)
	    crtc_hdisplay, dev_priv->psr.su_x_granularity)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, hdisplay(%d) not multiple of %d\n"
, crtc_hdisplay, dev_priv->psr.su_x_granularity);
return false0;
}

if (HAS_PSR2_SEL_FETCH(dev_priv)(((&(dev_priv)->__info)->gen) >= 12)) {
if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
    !HAS_PSR_HW_TRACKING(dev_priv)((&(dev_priv)->__info)->display.has_psr_hw_tracking
)) {
	drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"
)
		    "PSR2 not enabled, selective fetch not valid and no HW tracking available\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"
);
	return false0;
}
}

if (!crtc_state->enable_psr2_sel_fetch &&
   (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n"
, crtc_hdisplay, crtc_vdisplay, psr_max_h, psr_max_v)
	    "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n"
, crtc_hdisplay, crtc_vdisplay, psr_max_h, psr_max_v)
	    crtc_hdisplay, crtc_vdisplay,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n"
, crtc_hdisplay, crtc_vdisplay, psr_max_h, psr_max_v)
	    psr_max_h, psr_max_v)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n"
, crtc_hdisplay, crtc_vdisplay, psr_max_h, psr_max_v);
return false0;
}

tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
return true1;
803}

805void intel_psr_compute_config(struct intel_dp *intel_dp,
	      struct intel_crtc_state *crtc_state)
807{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int psr_setup_time;

if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support))
return;

if (intel_dp != dev_priv->psr.dp)
return;

if (!psr_global_enabled(dev_priv))
return;
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
* for now it only supports one instance of PSR, so lets keep it
* hardcoded to PORT_A
*/
if (dig_port->base.port != PORT_A) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: Port not supported\n"
)
	    "PSR condition failed: Port not supported\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: Port not supported\n"
);
return;
}

if (dev_priv->psr.sink_not_reliable) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR sink implementation is not reliable\n"
)
	    "PSR sink implementation is not reliable\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR sink implementation is not reliable\n"
);
return;
}

if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: Interlaced mode enabled\n"
)
	    "PSR condition failed: Interlaced mode enabled\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: Interlaced mode enabled\n"
);
return;
}

psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
if (psr_setup_time < 0) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: Invalid PSR setup time (0x%02x)\n"
, intel_dp->psr_dpcd[1])
	    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: Invalid PSR setup time (0x%02x)\n"
, intel_dp->psr_dpcd[1])
	    intel_dp->psr_dpcd[1])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: Invalid PSR setup time (0x%02x)\n"
, intel_dp->psr_dpcd[1]);
return;
}

if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
   adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: PSR setup time (%d us) too long\n"
, psr_setup_time)
	    "PSR condition failed: PSR setup time (%d us) too long\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: PSR setup time (%d us) too long\n"
, psr_setup_time)
	    psr_setup_time)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR condition failed: PSR setup time (%d us) too long\n"
, psr_setup_time);
return;
}

crtc_state->has_psr = true1;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC0x07);
865}

867static void intel_psr_activate(struct intel_dp *intel_dp)
868{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);

if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder))
drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = (((&(dev_priv)->__info)->trans_offsets[(dev_priv
->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60900) + ((&(dev_priv)->__info)->
display_mmio_offset))) })) & (1 << 31))); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (0x60900) + ((&(dev_priv)->__info)->display_mmio_offset))) })) & (1 << 31)"
 ")"); __builtin_expect(!!(__ret), 0); })
	    intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = (((&(dev_priv)->__info)->trans_offsets[(dev_priv
->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets
[TRANSCODER_A] + (0x60900) + ((&(dev_priv)->__info)->
display_mmio_offset))) })) & (1 << 31))); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (0x60900) + ((&(dev_priv)->__info)->display_mmio_offset))) })) & (1 << 31)"
 ")"); __builtin_expect(!!(__ret), 0); });

drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = ((((&(dev_priv)->__info)->trans_offsets[(
dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->
trans_offsets[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->
__info)->display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust
)) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
 "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->__info)->display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })) & (1 << 31)"
 ")"); __builtin_expect(!!(__ret), 0); })
    intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = ((((&(dev_priv)->__info)->trans_offsets[(
dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->
trans_offsets[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->
__info)->display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust
)) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
 "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + ((&(dev_priv)->__info)->display_mmio_offset)) - dev_priv->hsw_psr_mmio_adjust)) })) & (1 << 31)"
 ")"); __builtin_expect(!!(__ret), 0); });
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active)({ int __ret = !!((dev_priv->psr.active)); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "dev_priv->psr.active" ")"); __builtin_expect
(!!(__ret), 0); });
lockdep_assert_held(&dev_priv->psr.lock)do { (void)(&dev_priv->psr.lock); } while(0);

/* psr1 and psr2 are mutually exclusive.*/
if (dev_priv->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);

dev_priv->psr.active = true1;
887}

889static void intel_psr_enable_source(struct intel_dp *intel_dp,
		    const struct intel_crtc_state *crtc_state)
891{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 mask;

/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
* use hardcoded values PSR AUX transactions
*/
if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL))
hsw_psr_setup_aux(intel_dp);

if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9)(0 + (&(dev_priv)->__info)->gen == (9)) &&
			   !IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE))) {
i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder)((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP
] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4
, [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(cpu_transcoder
)])) });
u32 chicken = intel_de_read(dev_priv, reg);

chicken |= PSR2_VSC_ENABLE_PROG_HEADER(1 << 12) |
	   PSR2_ADD_VERTICAL_LINE_COUNT(1 << 15);
intel_de_write(dev_priv, reg, chicken);
}

/*
* Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
* mask LPSP to avoid dependency on other drivers that might block
* runtime_pm besides preventing  other hw tracking issues now we
* can rely on frontbuffer tracking.
*/
mask = EDP_PSR_DEBUG_MASK_MEMUP(1 << 26) |
      EDP_PSR_DEBUG_MASK_HPD(1 << 25) |
      EDP_PSR_DEBUG_MASK_LPSP(1 << 27) |
      EDP_PSR_DEBUG_MASK_MAX_SLEEP(1 << 28);

if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 11)
mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE(1 << 16);

intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60860) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) }),
       mask);

psr_irq_control(dev_priv);

if (crtc_state->dc3co_exitline) {
u32 val;

/*
 * TODO: if future platforms supports DC3CO in more than one
 * transcoder, EXITLINE will need to be unset when disabling PSR
 */
val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info
)->trans_offsets[TRANSCODER_A] + (0x60018) + ((&(dev_priv
)->__info)->display_mmio_offset))) }));
val &= ~EXITLINE_MASK((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) <<
 (0))) + 0));
val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT0;
val |= EXITLINE_ENABLE((u32)((1UL << (31)) + 0));
intel_de_write(dev_priv, EXITLINE(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info
)->trans_offsets[TRANSCODER_A] + (0x60018) + ((&(dev_priv
)->__info)->display_mmio_offset))) }), val);
}

if (HAS_PSR_HW_TRACKING(dev_priv)((&(dev_priv)->__info)->display.has_psr_hw_tracking
))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1((const i915_reg_t){ .reg = (0x42080) }), IGNORE_PSR2_HW_TRACKING(1 << 1),
	     dev_priv->psr.psr2_sel_fetch_enabled ?
	     IGNORE_PSR2_HW_TRACKING(1 << 1) : 0);
949}

951static void intel_psr_enable_locked(struct drm_i915_privateinteldrm_softc *dev_priv,
		    const struct intel_crtc_state *crtc_state,
		    const struct drm_connector_state *conn_state)
954{
struct intel_dp *intel_dp = dev_priv->psr.dp;
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct intel_encoder *encoder = &dig_port->base;
u32 val;

drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled)({ int __ret = !!((dev_priv->psr.enabled)); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "dev_priv->psr.enabled" ")"); __builtin_expect
(!!(__ret), 0); });

dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
 = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})->pipe;
dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
/* DC5/DC6 requires at least 6 idle frames */
val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6)(((uint64_t)(intel_get_frame_time_us(crtc_state) * 6)) * hz /
 1000000);
dev_priv->psr.dc3co_exit_delay = val;
dev_priv->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;

/*
* If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
* will still keep the error set even after the reset done in the
* irq_preinstall and irq_uninstall hooks.
* And enabling in this situation cause the screen to freeze in the
* first time that PSR HW tries to activate so lets keep PSR disabled
* to avoid any rendering problems.
*/
if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) {
val = intel_de_read(dev_priv,
		    TRANS_PSR_IIR(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60818) + (
(&(dev_priv)->__info)->display_mmio_offset))) }));
val &= EDP_PSR_ERROR(0)(0x4 << ((0) == TRANSCODER_EDP ? 0 : ((0) - TRANSCODER_A
 + 1) * 8));
} else {
val = intel_de_read(dev_priv, EDP_PSR_IIR((const i915_reg_t){ .reg = (0x64838) }));
val &= EDP_PSR_ERROR(dev_priv->psr.transcoder)(0x4 << ((dev_priv->psr.transcoder) == TRANSCODER_EDP
 ? 0 : ((dev_priv->psr.transcoder) - TRANSCODER_A + 1) * 8
));
}
if (val) {
dev_priv->psr.sink_not_reliable = true1;
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR interruption error set, not enabling PSR\n"
)
	    "PSR interruption error set, not enabling PSR\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR interruption error set, not enabling PSR\n"
);
return;
}

drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Enabling PSR%s\n"
, dev_priv->psr.psr2_enabled ? "2" : "1")
    dev_priv->psr.psr2_enabled ? "2" : "1")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Enabling PSR%s\n"
, dev_priv->psr.psr2_enabled ? "2" : "1");
intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
		     &dev_priv->psr.vsc);
intel_write_dp_vsc_sdp(encoder, crtc_state, &dev_priv->psr.vsc);
intel_psr_enable_sink(intel_dp);
intel_psr_enable_source(intel_dp, crtc_state);
dev_priv->psr.enabled = true1;

intel_psr_activate(intel_dp);
1005}

1007/**
* intel_psr_enable - Enable PSR
* @intel_dp: Intel DP
* @crtc_state: new CRTC state
* @conn_state: new CONNECTOR state
*
* This function can only be called after the pipe is fully trained and enabled.
*/
1015void intel_psr_enable(struct intel_dp *intel_dp,
      const struct intel_crtc_state *crtc_state,
      const struct drm_connector_state *conn_state)
1018{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);

if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support) || dev_priv->psr.dp != intel_dp)
return;

dev_priv->psr.force_mode_changed = false0;

if (!crtc_state->has_psr)
return;

drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp)({ int __ret = !!((dev_priv->drrs.dp)); if (__ret) printf(
"%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "dev_priv->drrs.dp" ")"); __builtin_expect
(!!(__ret), 0); });

mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);

if (!psr_global_enabled(dev_priv)) {
drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR disabled by flag\n"
);
goto unlock;
}

intel_psr_enable_locked(dev_priv, crtc_state, conn_state);

1040unlock:
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
1042}

1044static void intel_psr_exit(struct drm_i915_privateinteldrm_softc *dev_priv)
1045{
u32 val;

if (!dev_priv->psr.active) {
if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) {
	val = intel_de_read(dev_priv,
			    EDP_PSR2_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60900) + (
(&(dev_priv)->__info)->display_mmio_offset))) }));
	drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE)({ int __ret = !!((val & (1 << 31))); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "val & (1 << 31)" ")"); __builtin_expect
(!!(__ret), 0); });
}

val = intel_de_read(dev_priv,
		    EDP_PSR_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) }));
drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE)({ int __ret = !!((val & (1 << 31))); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "val & (1 << 31)" ")"); __builtin_expect
(!!(__ret), 0); });

return;
}

if (dev_priv->psr.psr2_enabled) {
tgl_disallow_dc3co_on_psr2_exit(dev_priv);
val = intel_de_read(dev_priv,
		    EDP_PSR2_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60900) + (
(&(dev_priv)->__info)->display_mmio_offset))) }));
drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE))({ int __ret = !!((!(val & (1 << 31)))); if (__ret)
 printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "!(val & (1 << 31))"
 ")"); __builtin_expect(!!(__ret), 0); });
val &= ~EDP_PSR2_ENABLE(1 << 31);
intel_de_write(dev_priv,
	       EDP_PSR2_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60900) + (
(&(dev_priv)->__info)->display_mmio_offset))) }), val);
} else {
val = intel_de_read(dev_priv,
		    EDP_PSR_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) }));
drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE))({ int __ret = !!((!(val & (1 << 31)))); if (__ret)
 printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "!(val & (1 << 31))"
 ")"); __builtin_expect(!!(__ret), 0); });
val &= ~EDP_PSR_ENABLE(1 << 31);
intel_de_write(dev_priv,
	       EDP_PSR_CTL(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60800) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) }), val);
}
dev_priv->psr.active = false0;
1079}

1081static void intel_psr_disable_locked(struct intel_dp *intel_dp)
1082{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
i915_reg_t psr_status;
u32 psr_status_mask;

lockdep_assert_held(&dev_priv->psr.lock)do { (void)(&dev_priv->psr.lock); } while(0);

if (!dev_priv->psr.enabled)
return;

drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling PSR%s\n"
, dev_priv->psr.psr2_enabled ? "2" : "1")
    dev_priv->psr.psr2_enabled ? "2" : "1")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling PSR%s\n"
, dev_priv->psr.psr2_enabled ? "2" : "1");

intel_psr_exit(dev_priv);

if (dev_priv->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60940) + (
(&(dev_priv)->__info)->display_mmio_offset))) });
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK(0xf << 28);
} else {
psr_status = EDP_PSR_STATUS(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60840) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) });
psr_status_mask = EDP_PSR_STATUS_STATE_MASK(7 << 29);
}

/* Wait till PSR is idle */
if (intel_de_wait_for_clear(dev_priv, psr_status,
		    psr_status_mask, 2000))
drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting PSR idle state\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

/* WA 1408330847 */
if (dev_priv->psr.psr2_sel_fetch_enabled &&
   (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0)(IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) && tgl_revids_get
(dev_priv)->disp_stepping >= (TGL_REVID_A0) && tgl_revids_get
(dev_priv)->disp_stepping <= (TGL_REVID_A0)) ||
    IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)(IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) && (((dev_priv
)->drm.pdev->revision) >= (0x0) && ((dev_priv
)->drm.pdev->revision) <= (0x0)))))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1((const i915_reg_t){ .reg = (0x42080) }),
	     DIS_RAM_BYPASS_PSR2_MAN_TRACK(1 << 16), 0);

/* Disable PSR on Sink */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG0x170, 0);

if (dev_priv->psr.psr2_enabled)
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG0x116, 0);

dev_priv->psr.enabled = false0;
1124}

1126/**
* intel_psr_disable - Disable PSR
* @intel_dp: Intel DP
* @old_crtc_state: old CRTC state
*
* This function needs to be called before disabling pipe.
*/
1133void intel_psr_disable(struct intel_dp *intel_dp,
       const struct intel_crtc_state *old_crtc_state)
1135{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);

if (!old_crtc_state->has_psr)
return;

if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv))({ int __ret = !!((!(((&(dev_priv)->__info)->display
.has_psr) && dev_priv->psr.sink_support))); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "!(((&(dev_priv)->__info)->display.has_psr) && dev_priv->psr.sink_support)"
 ")"); __builtin_expect(!!(__ret), 0); }))
return;

mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);

intel_psr_disable_locked(intel_dp);

mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
cancel_work_sync(&dev_priv->psr.work);
cancel_delayed_work_sync(&dev_priv->psr.dc3co_work);
1151}

1153static void psr_force_hw_tracking_exit(struct drm_i915_privateinteldrm_softc *dev_priv)
1154{
if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9)
/*
 * Display WA #0884: skl+
 * This documented WA for bxt can be safely applied
 * broadly so we can force HW tracking to exit PSR
 * instead of disabling and re-enabling.
 * Workaround tells us to write 0 to CUR_SURFLIVE_A,
 * but it makes more sense write to the current active
 * pipe.
 */
intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
cursor_offsets[(dev_priv->psr.pipe)] - (&(dev_priv)->
__info)->cursor_offsets[PIPE_A] + (0x700ac) + ((&(dev_priv
)->__info)->display_mmio_offset)) }), 0);
else
/*
 * A write to CURSURFLIVE do not cause HW tracking to exit PSR
 * on older gens so doing the manual exit instead.
 */
intel_psr_exit(dev_priv);
1172}

1174void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1175{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
 = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
struct i915_psr *psr = &dev_priv->psr;

if (!HAS_PSR2_SEL_FETCH(dev_priv)(((&(dev_priv)->__info)->gen) >= 12) ||
   !crtc_state->enable_psr2_sel_fetch)
return;

intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(psr->transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(psr->transcoder)] - (&(dev_priv)->__info
)->trans_offsets[TRANSCODER_A] + (0x60910) + ((&(dev_priv
)->__info)->display_mmio_offset))) }),
       crtc_state->psr2_man_track_ctl);
1186}

1188void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
		 struct intel_crtc *crtc)
1190{
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);

if (!crtc_state->enable_psr2_sel_fetch)
return;

crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE((u32)((1UL << (31)) + 0)) |
			 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME((u32)((1UL << (3)) + 0));
1198}

1200/**
* intel_psr_update - Update PSR state
* @intel_dp: Intel DP
* @crtc_state: new CRTC state
* @conn_state: new CONNECTOR state
*
* This functions will update PSR states, disabling, enabling or switching PSR
* version when executing fastsets. For full modeset, intel_psr_disable() and
* intel_psr_enable() should be called instead.
*/
1210void intel_psr_update(struct intel_dp *intel_dp,
      const struct intel_crtc_state *crtc_state,
      const struct drm_connector_state *conn_state)
1213{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
struct i915_psr *psr = &dev_priv->psr;
bool_Bool enable, psr2_enable;

if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support) || READ_ONCE(psr->dp)({ typeof(psr->dp) __tmp = *(volatile typeof(psr->dp) *
)&(psr->dp); membar_datadep_consumer(); __tmp; }) != intel_dp)
return;

dev_priv->psr.force_mode_changed = false0;

mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);

enable = crtc_state->has_psr && psr_global_enabled(dev_priv);
psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);

if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
if (crtc_state->crc_enabled && psr->enabled)
	psr_force_hw_tracking_exit(dev_priv);
else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9 && psr->enabled) {
	/*
	 * Activate PSR again after a force exit when enabling
	 * CRC in older gens
	 */
	if (!dev_priv->psr.active &&
	    !dev_priv->psr.busy_frontbuffer_bits)
		schedule_work(&dev_priv->psr.work);
}

goto unlock;
}

if (psr->enabled)
intel_psr_disable_locked(intel_dp);

if (enable)
intel_psr_enable_locked(dev_priv, crtc_state, conn_state);

1251unlock:
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
1253}

1255/**
* intel_psr_wait_for_idle - wait for PSR1 to idle
* @new_crtc_state: new CRTC state
* @out_value: PSR status in case of failure
*
* This function is expected to be called from pipe_update_start() where it is
* not expected to race with PSR enable or disable.
*
* Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
*/
1265int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
	    u32 *out_value)
1267{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
 = (new_crtc_state->uapi.crtc); (struct intel_crtc *)( (char
 *)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);

if (!dev_priv->psr.enabled || !new_crtc_state->has_psr)
return 0;

/* FIXME: Update this for PSR2 if we need to wait for idle */
if (READ_ONCE(dev_priv->psr.psr2_enabled)({ typeof(dev_priv->psr.psr2_enabled) __tmp = *(volatile typeof
(dev_priv->psr.psr2_enabled) *)&(dev_priv->psr.psr2_enabled
); membar_datadep_consumer(); __tmp; }))
return 0;

/*
* From bspec: Panel Self Refresh (BDW+)
* Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
* defensive enough to cover everything.
*/

return __intel_wait_for_register(&dev_priv->uncore,
			 EDP_PSR_STATUS(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60840) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) }),
			 EDP_PSR_STATUS_STATE_MASK(7 << 29),
			 EDP_PSR_STATUS_STATE_IDLE(0 << 29), 2, 50,
			 out_value);
1290}

1292static bool_Bool __psr_wait_for_idle_locked(struct drm_i915_privateinteldrm_softc *dev_priv)
1293{
i915_reg_t reg;
u32 mask;
int err;

if (!dev_priv->psr.enabled)
return false0;

if (dev_priv->psr.psr2_enabled) {
reg = EDP_PSR2_STATUS(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60940) + (
(&(dev_priv)->__info)->display_mmio_offset))) });
mask = EDP_PSR2_STATUS_STATE_MASK(0xf << 28);
} else {
reg = EDP_PSR_STATUS(dev_priv->psr.transcoder)((const i915_reg_t){ .reg = ((((&(dev_priv)->__info)->
trans_offsets[(dev_priv->psr.transcoder)] - (&(dev_priv
)->__info)->trans_offsets[TRANSCODER_A] + (0x60840) + (
(&(dev_priv)->__info)->display_mmio_offset)) - dev_priv
->hsw_psr_mmio_adjust)) });
mask = EDP_PSR_STATUS_STATE_MASK(7 << 29);
}

mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);

err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
if (err)
drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting for PSR Idle for re-enable\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
	"Timed out waiting for PSR Idle for re-enable\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting for PSR Idle for re-enable\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

/* After the unlocked wait, verify that PSR is still wanted! */
mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);
return err == 0 && dev_priv->psr.enabled;
1319}

1321static int intel_psr_fastset_force(struct drm_i915_privateinteldrm_softc *dev_priv)
1322{
struct drm_device *dev = &dev_priv->drm;
struct drm_modeset_acquire_ctx ctx;
struct drm_atomic_state *state;
struct intel_crtc *crtc;
int err;

state = drm_atomic_state_alloc(dev);
if (!state)
return -ENOMEM12;

drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE(1UL << (0)));
state->acquire_ctx = &ctx;

1336retry:
for_each_intel_crtc(dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base
.head ) *__mptr = ((&(dev)->mode_config.crtc_list)->
next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*crtc), base.head) );}); &crtc->base.head !=
 (&(dev)->mode_config.crtc_list); crtc = ({ const __typeof
( ((__typeof(*crtc) *)0)->base.head ) *__mptr = (crtc->
base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*crtc), base.head) );})) {
struct intel_crtc_state *crtc_state =
	intel_atomic_get_crtc_state(state, crtc);

if (IS_ERR(crtc_state)) {
	err = PTR_ERR(crtc_state);
	goto error;
}

if (crtc_state->hw.active && crtc_state->has_psr) {
	/* Mark mode as changed to trigger a pipe->update() */
	crtc_state->uapi.mode_changed = true1;
	break;
}
}

err = drm_atomic_commit(state);

1355error:
if (err == -EDEADLK11) {
drm_atomic_state_clear(state);
err = drm_modeset_backoff(&ctx);
if (!err)
	goto retry;
}

drm_modeset_drop_locks(&ctx);
drm_modeset_acquire_fini(&ctx);
drm_atomic_state_put(state);

return err;
1368}

1370int intel_psr_debug_set(struct drm_i915_privateinteldrm_softc *dev_priv, u64 val)
1371{
const u32 mode = val & I915_PSR_DEBUG_MODE_MASK0x0f;
u32 old_mode;
int ret;

if (val & ~(I915_PSR_DEBUG_IRQ0x10 | I915_PSR_DEBUG_MODE_MASK0x0f) ||
   mode > I915_PSR_DEBUG_FORCE_PSR10x03) {
drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Invalid debug mask %llx\n"
, val);
return -EINVAL22;
}

ret = mutex_lock_interruptible(&dev_priv->psr.lock);
if (ret)
return ret;

old_mode = dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK0x0f;
dev_priv->psr.debug = val;

/*
* Do it right away if it's already enabled, otherwise it will be done
* when enabling the source.
*/
if (dev_priv->psr.enabled)
psr_irq_control(dev_priv);

mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);

if (old_mode != mode)
ret = intel_psr_fastset_force(dev_priv);

return ret;
1402}

1404static void intel_psr_handle_irq(struct drm_i915_privateinteldrm_softc *dev_priv)
1405{
struct i915_psr *psr = &dev_priv->psr;

intel_psr_disable_locked(psr->dp);
psr->sink_not_reliable = true1;
/* let's make sure that sink is awaken */
drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER0x600, DP_SET_POWER_D00x1);
1412}

1414static void intel_psr_work(struct work_struct *work)
1415{
struct drm_i915_privateinteldrm_softc *dev_priv =
container_of(work, typeof(*dev_priv), psr.work)({ const __typeof( ((typeof(*dev_priv) *)0)->psr.work ) *__mptr
 = (work); (typeof(*dev_priv) *)( (char *)__mptr - __builtin_offsetof
(typeof(*dev_priv), psr.work) );});

mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);

if (!dev_priv->psr.enabled)
goto unlock;

if (READ_ONCE(dev_priv->psr.irq_aux_error)({ typeof(dev_priv->psr.irq_aux_error) __tmp = *(volatile typeof
(dev_priv->psr.irq_aux_error) *)&(dev_priv->psr.irq_aux_error
); membar_datadep_consumer(); __tmp; }))
intel_psr_handle_irq(dev_priv);

/*
* We have to make sure PSR is ready for re-enable
* otherwise it keeps disabled until next full enable/disable cycle.
* PSR might take some time to get fully disabled
* and be ready for re-enable.
*/
if (!__psr_wait_for_idle_locked(dev_priv))
goto unlock;

/*
* The delayed work can race with an invalidate hence we need to
* recheck. Since psr_flush first clears this and then reschedules we
* won't ever miss a flush when bailing out here.
*/
if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)
goto unlock;

intel_psr_activate(dev_priv->psr.dp);
1445unlock:
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
1447}

1449/**
* intel_psr_invalidate - Invalidade PSR
* @dev_priv: i915 device
* @frontbuffer_bits: frontbuffer plane tracking bits
* @origin: which operation caused the invalidate
*
* Since the hardware frontbuffer tracking has gaps we need to integrate
* with the software frontbuffer tracking. This function gets called every
* time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
* disabled if the frontbuffer mask contains a buffer relevant to PSR.
*
* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
*/
1462void intel_psr_invalidate(struct drm_i915_privateinteldrm_softc *dev_priv,
	  unsigned frontbuffer_bits, enum fb_op_origin origin)
1464{
if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support))
return;

if (origin == ORIGIN_FLIP)
return;

mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);
if (!dev_priv->psr.enabled) {
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
return;
}

frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)(((~0UL) >> (64 - (8 * ((dev_priv->psr.pipe) + 1) - 1
) - 1)) & ((~0UL) << (8 * (dev_priv->psr.pipe)))
);
dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;

if (frontbuffer_bits)
intel_psr_exit(dev_priv);

mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
1484}

1486/*
* When we will be completely rely on PSR2 S/W tracking in future,
* intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
* event also therefore tgl_dc3co_flush() require to be changed
* accordingly in future.
*/
1492static void
1493tgl_dc3co_flush(struct drm_i915_privateinteldrm_softc *dev_priv,
unsigned int frontbuffer_bits, enum fb_op_origin origin)
1495{
mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);

if (!dev_priv->psr.dc3co_enabled)
goto unlock;

if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
goto unlock;

/*
* At every frontbuffer flush flip event modified delay of delayed work,
* when delayed work schedules that means display has been idle.
*/
if (!(frontbuffer_bits &
   INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)(((~0UL) >> (64 - (8 * ((dev_priv->psr.pipe) + 1) - 1
) - 1)) & ((~0UL) << (8 * (dev_priv->psr.pipe)))
)))
goto unlock;

tgl_psr2_enable_dc3co(dev_priv);
mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work,
	 dev_priv->psr.dc3co_exit_delay);

1516unlock:
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
1518}

1520/**
* intel_psr_flush - Flush PSR
* @dev_priv: i915 device
* @frontbuffer_bits: frontbuffer plane tracking bits
* @origin: which operation caused the flush
*
* Since the hardware frontbuffer tracking has gaps we need to integrate
* with the software frontbuffer tracking. This function gets called every
* time frontbuffer rendering has completed and flushed out to memory. PSR
* can be enabled again if no other frontbuffer relevant to PSR is dirty.
*
* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
*/
1533void intel_psr_flush(struct drm_i915_privateinteldrm_softc *dev_priv,
     unsigned frontbuffer_bits, enum fb_op_origin origin)
1535{
if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support))
return;

if (origin == ORIGIN_FLIP) {
tgl_dc3co_flush(dev_priv, frontbuffer_bits, origin);
return;
}

mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);
if (!dev_priv->psr.enabled) {
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
return;
}

frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe)(((~0UL) >> (64 - (8 * ((dev_priv->psr.pipe) + 1) - 1
) - 1)) & ((~0UL) << (8 * (dev_priv->psr.pipe)))
);
dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;

/* By definition flush = invalidate + flush */
if (frontbuffer_bits)
psr_force_hw_tracking_exit(dev_priv);

if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
schedule_work(&dev_priv->psr.work);
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);
1560}

1562/**
* intel_psr_init - Init basic PSR work and mutex.
* @dev_priv: i915 device private
*
* This function is  called only once at driver load to initialize basic
* PSR stuff.
*/
1569void intel_psr_init(struct drm_i915_privateinteldrm_softc *dev_priv)
1570{
if (!HAS_PSR(dev_priv)((&(dev_priv)->__info)->display.has_psr))
return;

if (!dev_priv->psr.sink_support)
return;

if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL))
/*
 * HSW don't have PSR registers on the same space as transcoder
 * so set this to a value that when subtract to the register
 * in transcoder space results in the right offset for HSW
 */
dev_priv->hsw_psr_mmio_adjust = _SRD_CTL_EDP0x6f800 - _HSW_EDP_PSR_BASE0x64800;

if (dev_priv->params.enable_psr == -1)
if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9 || !dev_priv->vbt.psr.enable)
	dev_priv->params.enable_psr = 0;

/* Set link_standby x link_off defaults */
if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL))
/* HSW and BDW require workarounds that we don't implement. */
dev_priv->psr.link_standby = false0;
else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 12)
/* For new platforms up to TGL let's respect VBT back again */
dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;

INIT_WORK(&dev_priv->psr.work, intel_psr_work);
INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work);
rw_init(&dev_priv->psr.lock, "psrlk")_rw_init_flags(&dev_priv->psr.lock, "psrlk", 0, ((void
 *)0));
1600}

1602static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
			   u8 *status, u8 *error_status)
1604{
struct drm_dp_aux *aux = &intel_dp->aux;
int ret;

ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS0x2008, status);
if (ret != 1)
10
←
Assuming 'ret' is not equal to 1, which participates in a condition later→
11
←
Taking true branch→
return ret;
12
←
Returning without writing to '*error_status'→
13
←
Returning value (loaded from 'ret'), which participates in a condition later→

ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS0x2006, error_status);
if (ret != 1)
return ret;

*status = *status & DP_PSR_SINK_STATE_MASK0x07;

return 0;
1619}

1621static void psr_alpm_check(struct intel_dp *intel_dp)
1622{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
struct drm_dp_aux *aux = &intel_dp->aux;
struct i915_psr *psr = &dev_priv->psr;
u8 val;
int r;

if (!psr->psr2_enabled)
return;

r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS0x200b, &val);
if (r != 1) {
drm_err(&dev_priv->drm, "Error reading ALPM status\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Error reading ALPM status\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return;
}

if (val & DP_ALPM_LOCK_TIMEOUT_ERROR(1 << 0)) {
intel_psr_disable_locked(intel_dp);
psr->sink_not_reliable = true1;
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "ALPM lock timeout error, disabling PSR\n"
)
	    "ALPM lock timeout error, disabling PSR\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "ALPM lock timeout error, disabling PSR\n"
);

/* Clearing error */
drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS0x200b, val);
}
1647}

1649static void psr_capability_changed_check(struct intel_dp *intel_dp)
1650{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
struct i915_psr *psr = &dev_priv->psr;
u8 val;
int r;

r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI0x2007, &val);
if (r != 1) {
drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Error reading DP_PSR_ESI\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return;
}

if (val & DP_PSR_CAPS_CHANGE(1 << 0)) {
intel_psr_disable_locked(intel_dp);
psr->sink_not_reliable = true1;
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Sink PSR capability changed, disabling PSR\n"
)
	    "Sink PSR capability changed, disabling PSR\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Sink PSR capability changed, disabling PSR\n"
);

/* Clearing it */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI0x2007, val);
}
1671}

1673void intel_psr_short_pulse(struct intel_dp *intel_dp)
1674{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
struct i915_psr *psr = &dev_priv->psr;
u8 status, error_status;
1
'error_status' declared without an initial value→
const u8 errors = DP_PSR_RFB_STORAGE_ERROR(1 << 1) |
	  DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR(1 << 2) |
	  DP_PSR_LINK_CRC_ERROR(1 << 0);

if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support) || !intel_dp_is_edp(intel_dp))
2
←
Assuming field 'has_psr' is not equal to 0→
3
←
Assuming the condition is false→
4
←
Assuming the condition is false→
5
←
Taking false branch→
return;

mutex_lock(&psr->lock)rw_enter_write(&psr->lock);

if (!psr->enabled || psr->dp != intel_dp)
6
←
Assuming field 'enabled' is true→
7
←
Assuming 'intel_dp' is equal to field 'dp'→
8
←
Taking false branch→
goto exit;

if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
9
←
Calling 'psr_get_status_and_error_status'→
14
←
Returning from 'psr_get_status_and_error_status'→
15
←
Assuming the condition is false→
16
←
Taking false branch→
drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Error reading PSR status or error status\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
	"Error reading PSR status or error status\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Error reading PSR status or error status\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
goto exit;
}

if (status == DP_PSR_SINK_INTERNAL_ERROR7 || (error_status & errors)) {
17
←
Assuming 'status' is not equal to DP_PSR_SINK_INTERNAL_ERROR→
18
←
The left operand of '&' is a garbage value
intel_psr_disable_locked(intel_dp);
psr->sink_not_reliable = true1;
}

if (status == DP_PSR_SINK_INTERNAL_ERROR7 && !error_status)
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR sink internal error, disabling PSR\n"
)
	    "PSR sink internal error, disabling PSR\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR sink internal error, disabling PSR\n"
);
if (error_status & DP_PSR_RFB_STORAGE_ERROR(1 << 1))
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR RFB storage error, disabling PSR\n"
)
	    "PSR RFB storage error, disabling PSR\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR RFB storage error, disabling PSR\n"
);
if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR(1 << 2))
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR VSC SDP uncorrectable error, disabling PSR\n"
)
	    "PSR VSC SDP uncorrectable error, disabling PSR\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR VSC SDP uncorrectable error, disabling PSR\n"
);
if (error_status & DP_PSR_LINK_CRC_ERROR(1 << 0))
drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR Link CRC error, disabling PSR\n"
)
	    "PSR Link CRC error, disabling PSR\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PSR Link CRC error, disabling PSR\n"
);

if (error_status & ~errors)
drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PSR_ERROR_STATUS unhandled errors %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , error_status
 & ~errors)
	"PSR_ERROR_STATUS unhandled errors %x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PSR_ERROR_STATUS unhandled errors %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , error_status
 & ~errors)
	error_status & ~errors)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PSR_ERROR_STATUS unhandled errors %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , error_status
 & ~errors);
/* clear status register */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS0x2006, error_status);

psr_alpm_check(intel_dp);
psr_capability_changed_check(intel_dp);

1724exit:
mutex_unlock(&psr->lock)rw_exit_write(&psr->lock);
1726}

1728bool_Bool intel_psr_enabled(struct intel_dp *intel_dp)
1729{
struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp);
bool_Bool ret;

if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support) || !intel_dp_is_edp(intel_dp))
return false0;

mutex_lock(&dev_priv->psr.lock)rw_enter_write(&dev_priv->psr.lock);
ret = (dev_priv->psr.dp == intel_dp && dev_priv->psr.enabled);
mutex_unlock(&dev_priv->psr.lock)rw_exit_write(&dev_priv->psr.lock);

return ret;
1741}

1743void intel_psr_atomic_check(struct drm_connector *connector,
	    struct drm_connector_state *old_state,
	    struct drm_connector_state *new_state)
1746{
struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->dev);
struct intel_connector *intel_connector;
struct intel_digital_port *dig_port;
struct drm_crtc_state *crtc_state;

if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support) || !new_state->crtc ||
   !dev_priv->psr.force_mode_changed)
return;

intel_connector = to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) *
__mptr = (connector); (struct intel_connector *)( (char *)__mptr
 - __builtin_offsetof(struct intel_connector, base) );});
dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr
 = (new_state->best_encoder); (struct intel_encoder *)( (char
 *)__mptr - __builtin_offsetof(struct intel_encoder, base) );
}));
if (dev_priv->psr.dp != &dig_port->dp)
return;

crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
				   new_state->crtc);
crtc_state->mode_changed = true1;
1764}

1766void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp)
1767{
struct drm_i915_privateinteldrm_softc *dev_priv;

if (!intel_dp)
return;

dev_priv = dp_to_i915(intel_dp);
if (!CAN_PSR(dev_priv)(((&(dev_priv)->__info)->display.has_psr) &&
 dev_priv->psr.sink_support) || intel_dp != dev_priv->psr.dp)
return;

dev_priv->psr.force_mode_changed = true1;
1778}