Bug Summary

File:dev/pci/if_em_hw.c
Warning:line 5928, column 2
Value stored to 'ret_val' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name if_em_hw.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/if_em_hw.c
1/*******************************************************************************
2
3 Copyright (c) 2001-2005, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33
34/* $OpenBSD: if_em_hw.c,v 1.113 2022/01/09 05:42:50 jsg Exp $ */
35/*
36 * if_em_hw.c Shared functions for accessing and configuring the MAC
37 */
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/sockio.h>
42#include <sys/mbuf.h>
43#include <sys/malloc.h>
44#include <sys/kernel.h>
45#include <sys/device.h>
46#include <sys/socket.h>
47#include <sys/kstat.h>
48
49#include <net/if.h>
50#include <net/if_media.h>
51
52#include <netinet/in.h>
53#include <netinet/if_ether.h>
54
55#include <uvm/uvm_extern.h>
56
57#include <dev/pci/pcireg.h>
58#include <dev/pci/pcivar.h>
59
60#include <dev/pci/if_em.h>
61#include <dev/pci/if_em_hw.h>
62#include <dev/pci/if_em_soc.h>
63
64#include <dev/mii/rgephyreg.h>
65
66#define STATIC
67
68static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t);
69static void em_swfw_sync_release(struct em_hw *, uint16_t);
70static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *);
71static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t);
72static int32_t em_get_software_semaphore(struct em_hw *);
73static void em_release_software_semaphore(struct em_hw *);
74
75static int32_t em_check_downshift(struct em_hw *);
76static void em_clear_vfta(struct em_hw *);
77void em_clear_vfta_i350(struct em_hw *);
78static int32_t em_commit_shadow_ram(struct em_hw *);
79static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t);
80static int32_t em_config_fc_after_link_up(struct em_hw *);
81static int32_t em_match_gig_phy(struct em_hw *);
82static int32_t em_detect_gig_phy(struct em_hw *);
83static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t);
84static int32_t em_get_auto_rd_done(struct em_hw *);
85static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *);
86static int32_t em_get_hw_eeprom_semaphore(struct em_hw *);
87static int32_t em_get_phy_cfg_done(struct em_hw *);
88static int32_t em_get_software_flag(struct em_hw *);
89static int32_t em_ich8_cycle_init(struct em_hw *);
90static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t);
91static int32_t em_id_led_init(struct em_hw *);
92static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t,
93 uint32_t);
94static int32_t em_init_lcd_from_nvm(struct em_hw *);
95static int32_t em_phy_no_cable_workaround(struct em_hw *);
96static void em_init_rx_addrs(struct em_hw *);
97static void em_initialize_hardware_bits(struct em_softc *);
98static void em_toggle_lanphypc_pch_lpt(struct em_hw *);
99static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool_Bool force);
100static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *);
101static int32_t em_kumeran_lock_loss_workaround(struct em_hw *);
102static int32_t em_mng_enable_host_if(struct em_hw *);
103static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t,
104 uint16_t *);
105static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t,
106 uint16_t *data);
107static int32_t em_poll_eerd_eewr_done(struct em_hw *, int);
108static void em_put_hw_eeprom_semaphore(struct em_hw *);
109static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *);
110static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
111static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
112static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *);
113static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *);
114static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t,
115 uint16_t *);
116static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t,
117 uint16_t);
118static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
119 uint16_t *);
120static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
121 uint16_t *);
122static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t,
123 uint16_t *);
124static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *);
125static void em_release_software_flag(struct em_hw *);
126static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t);
127static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t);
128static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t);
129static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t);
130static void em_set_pci_express_master_disable(struct em_hw *);
131static int32_t em_wait_autoneg(struct em_hw *);
132static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t);
133static int32_t em_set_phy_type(struct em_hw *);
134static void em_phy_init_script(struct em_hw *);
135static int32_t em_setup_copper_link(struct em_hw *);
136static int32_t em_setup_fiber_serdes_link(struct em_hw *);
137static int32_t em_adjust_serdes_amplitude(struct em_hw *);
138static int32_t em_phy_force_speed_duplex(struct em_hw *);
139static int32_t em_config_mac_to_phy(struct em_hw *);
140static void em_raise_mdi_clk(struct em_hw *, uint32_t *);
141static void em_lower_mdi_clk(struct em_hw *, uint32_t *);
142static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t);
143static uint16_t em_shift_in_mdi_bits(struct em_hw *);
144static int32_t em_phy_reset_dsp(struct em_hw *);
145static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t,
146 uint16_t *);
147static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t,
148 uint16_t *);
149static int32_t em_spi_eeprom_ready(struct em_hw *);
150static void em_raise_ee_clk(struct em_hw *, uint32_t *);
151static void em_lower_ee_clk(struct em_hw *, uint32_t *);
152static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t);
153static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t);
154static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *);
155static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t);
156static int32_t em_acquire_eeprom(struct em_hw *);
157static void em_release_eeprom(struct em_hw *);
158static void em_standby_eeprom(struct em_hw *);
159static int32_t em_set_vco_speed(struct em_hw *);
160static int32_t em_polarity_reversal_workaround(struct em_hw *);
161static int32_t em_set_phy_mode(struct em_hw *);
162static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *);
163static uint8_t em_calculate_mng_checksum(char *, uint32_t);
164static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t);
165static int32_t em_configure_kmrn_for_1000(struct em_hw *);
166static int32_t em_set_pciex_completion_timeout(struct em_hw *hw);
167static int32_t em_set_mdio_slow_mode_hv(struct em_hw *);
168int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *);
169int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *);
170int32_t em_link_stall_workaround_hv(struct em_hw *);
171int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t);
172int32_t em_k1_workaround_lv(struct em_hw *);
173int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t);
174int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t);
175void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t);
176int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t,
177 uint16_t *, boolean_t);
178int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t,
179 uint16_t *, boolean_t);
180int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *,
181 boolean_t);
182int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t);
183void em_power_up_serdes_link_82575(struct em_hw *);
184int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *,
185 uint16_t *);
186int32_t em_set_eee_i350(struct em_hw *);
187int32_t em_set_eee_pchlan(struct em_hw *);
188int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *);
189int32_t em_initialize_M88E1512_phy(struct em_hw *);
190
191/* IGP cable length table */
192static const uint16_t
193em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE128] =
194 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
195 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
196 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
197 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
198 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
199 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
200 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
201 110,
202 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120,
203 120};
204
205static const uint16_t
206em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE113] =
207 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
208 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
209 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
210 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
211 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
212 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
213 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118,
214 121, 124};
215
216/******************************************************************************
217 * Set the phy type member in the hw struct.
218 *
219 * hw - Struct containing variables accessed by shared code
220 *****************************************************************************/
221STATIC int32_t
222em_set_phy_type(struct em_hw *hw)
223{
224 DEBUGFUNC("em_set_phy_type");;
225
226 if (hw->mac_type == em_undefined)
227 return -E1000_ERR_PHY_TYPE6;
228
229 switch (hw->phy_id) {
230 case M88E1000_E_PHY_ID0x01410C50:
231 case M88E1000_I_PHY_ID0x01410C30:
232 case M88E1011_I_PHY_ID0x01410C20:
233 case M88E1111_I_PHY_ID0x01410CC0:
234 case M88E1112_E_PHY_ID0x01410C90:
235 case M88E1543_E_PHY_ID0x01410EA0:
236 case M88E1512_E_PHY_ID0x01410DD0:
237 case I210_I_PHY_ID0x01410C00:
238 case I347AT4_E_PHY_ID0x01410DC0:
239 hw->phy_type = em_phy_m88;
240 break;
241 case IGP01E1000_I_PHY_ID0x02A80380:
242 if (hw->mac_type == em_82541 ||
243 hw->mac_type == em_82541_rev_2 ||
244 hw->mac_type == em_82547 ||
245 hw->mac_type == em_82547_rev_2) {
246 hw->phy_type = em_phy_igp;
247 break;
248 }
249 case IGP03E1000_E_PHY_ID0x02A80390:
250 case IGP04E1000_E_PHY_ID0x02A80391:
251 hw->phy_type = em_phy_igp_3;
252 break;
253 case IFE_E_PHY_ID0x02A80330:
254 case IFE_PLUS_E_PHY_ID0x02A80320:
255 case IFE_C_E_PHY_ID0x02A80310:
256 hw->phy_type = em_phy_ife;
257 break;
258 case M88E1141_E_PHY_ID0x01410CD0:
259 hw->phy_type = em_phy_oem;
260 break;
261 case I82577_E_PHY_ID0x01540050:
262 hw->phy_type = em_phy_82577;
263 break;
264 case I82578_E_PHY_ID0x004DD040:
265 hw->phy_type = em_phy_82578;
266 break;
267 case I82579_E_PHY_ID0x01540090:
268 hw->phy_type = em_phy_82579;
269 break;
270 case I217_E_PHY_ID0x015400A0:
271 hw->phy_type = em_phy_i217;
272 break;
273 case I82580_I_PHY_ID0x015403A0:
274 case I350_I_PHY_ID0x015403B0:
275 hw->phy_type = em_phy_82580;
276 break;
277 case RTL8211_E_PHY_ID0x001CC912:
278 hw->phy_type = em_phy_rtl8211;
279 break;
280 case BME1000_E_PHY_ID0x01410CB0:
281 if (hw->phy_revision == 1) {
282 hw->phy_type = em_phy_bm;
283 break;
284 }
285 /* FALLTHROUGH */
286 case GG82563_E_PHY_ID0x01410CA0:
287 if (hw->mac_type == em_80003es2lan) {
288 hw->phy_type = em_phy_gg82563;
289 break;
290 }
291 /* FALLTHROUGH */
292 default:
293 /* Should never have loaded on this device */
294 hw->phy_type = em_phy_undefined;
295 return -E1000_ERR_PHY_TYPE6;
296 }
297
298 return E1000_SUCCESS0;
299}
300
301/******************************************************************************
302 * IGP phy init script - initializes the GbE PHY
303 *
304 * hw - Struct containing variables accessed by shared code
305 *****************************************************************************/
306static void
307em_phy_init_script(struct em_hw *hw)
308{
309 uint16_t phy_saved_data;
310 DEBUGFUNC("em_phy_init_script");;
311
312 if (hw->phy_init_script) {
313 msec_delay(20)(*delay_func)(1000*(20));
314 /*
315 * Save off the current value of register 0x2F5B to be
316 * restored at the end of this routine.
317 */
318 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
319
320 /* Disabled the PHY transmitter */
321 em_write_phy_reg(hw, 0x2F5B, 0x0003);
322 msec_delay(20)(*delay_func)(1000*(20));
323 em_write_phy_reg(hw, 0x0000, 0x0140);
324 msec_delay(5)(*delay_func)(1000*(5));
325
326 switch (hw->mac_type) {
327 case em_82541:
328 case em_82547:
329 em_write_phy_reg(hw, 0x1F95, 0x0001);
330 em_write_phy_reg(hw, 0x1F71, 0xBD21);
331 em_write_phy_reg(hw, 0x1F79, 0x0018);
332 em_write_phy_reg(hw, 0x1F30, 0x1600);
333 em_write_phy_reg(hw, 0x1F31, 0x0014);
334 em_write_phy_reg(hw, 0x1F32, 0x161C);
335 em_write_phy_reg(hw, 0x1F94, 0x0003);
336 em_write_phy_reg(hw, 0x1F96, 0x003F);
337 em_write_phy_reg(hw, 0x2010, 0x0008);
338 break;
339 case em_82541_rev_2:
340 case em_82547_rev_2:
341 em_write_phy_reg(hw, 0x1F73, 0x0099);
342 break;
343 default:
344 break;
345 }
346
347 em_write_phy_reg(hw, 0x0000, 0x3300);
348 msec_delay(20)(*delay_func)(1000*(20));
349
350 /* Now enable the transmitter */
351 em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
352
353 if (hw->mac_type == em_82547) {
354 uint16_t fused, fine, coarse;
355 /* Move to analog registers page */
356 em_read_phy_reg(hw,
357 IGP01E1000_ANALOG_SPARE_FUSE_STATUS0x20D1, &fused);
358
359 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED0x0100)) {
360 em_read_phy_reg(hw,
361 IGP01E1000_ANALOG_FUSE_STATUS0x20D0, &fused);
362
363 fine = fused &
364 IGP01E1000_ANALOG_FUSE_FINE_MASK0x0F80;
365 coarse = fused &
366 IGP01E1000_ANALOG_FUSE_COARSE_MASK0x0070;
367
368 if (coarse >
369 IGP01E1000_ANALOG_FUSE_COARSE_THRESH0x0040) {
370 coarse -=
371 IGP01E1000_ANALOG_FUSE_COARSE_100x0010;
372 fine -=
373 IGP01E1000_ANALOG_FUSE_FINE_10x0080;
374 } else if (coarse ==
375 IGP01E1000_ANALOG_FUSE_COARSE_THRESH0x0040)
376 fine -= IGP01E1000_ANALOG_FUSE_FINE_100x0500;
377
378 fused = (fused &
379 IGP01E1000_ANALOG_FUSE_POLY_MASK0xF000) |
380 (fine &
381 IGP01E1000_ANALOG_FUSE_FINE_MASK0x0F80) |
382 (coarse &
383 IGP01E1000_ANALOG_FUSE_COARSE_MASK0x0070);
384
385 em_write_phy_reg(hw,
386 IGP01E1000_ANALOG_FUSE_CONTROL0x20DC,
387 fused);
388
389 em_write_phy_reg(hw,
390 IGP01E1000_ANALOG_FUSE_BYPASS0x20DE,
391 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL0x0002);
392 }
393 }
394 }
395}
396
397/******************************************************************************
398 * Set the mac type member in the hw struct.
399 *
400 * hw - Struct containing variables accessed by shared code
401 *****************************************************************************/
402int32_t
403em_set_mac_type(struct em_hw *hw)
404{
405 DEBUGFUNC("em_set_mac_type");;
406
407 switch (hw->device_id) {
408 case E1000_DEV_ID_825420x1000:
409 switch (hw->revision_id) {
410 case E1000_82542_2_0_REV_ID2:
411 hw->mac_type = em_82542_rev2_0;
412 break;
413 case E1000_82542_2_1_REV_ID3:
414 hw->mac_type = em_82542_rev2_1;
415 break;
416 default:
417 /* Invalid 82542 revision ID */
418 return -E1000_ERR_MAC_TYPE5;
419 }
420 break;
421 case E1000_DEV_ID_82543GC_FIBER0x1001:
422 case E1000_DEV_ID_82543GC_COPPER0x1004:
423 hw->mac_type = em_82543;
424 break;
425 case E1000_DEV_ID_82544EI_COPPER0x1008:
426 case E1000_DEV_ID_82544EI_FIBER0x1009:
427 case E1000_DEV_ID_82544GC_COPPER0x100C:
428 case E1000_DEV_ID_82544GC_LOM0x100D:
429 hw->mac_type = em_82544;
430 break;
431 case E1000_DEV_ID_82540EM0x100E:
432 case E1000_DEV_ID_82540EM_LOM0x1015:
433 case E1000_DEV_ID_82540EP0x1017:
434 case E1000_DEV_ID_82540EP_LOM0x1016:
435 case E1000_DEV_ID_82540EP_LP0x101E:
436 hw->mac_type = em_82540;
437 break;
438 case E1000_DEV_ID_82545EM_COPPER0x100F:
439 case E1000_DEV_ID_82545EM_FIBER0x1011:
440 hw->mac_type = em_82545;
441 break;
442 case E1000_DEV_ID_82545GM_COPPER0x1026:
443 case E1000_DEV_ID_82545GM_FIBER0x1027:
444 case E1000_DEV_ID_82545GM_SERDES0x1028:
445 hw->mac_type = em_82545_rev_3;
446 break;
447 case E1000_DEV_ID_82546EB_COPPER0x1010:
448 case E1000_DEV_ID_82546EB_FIBER0x1012:
449 case E1000_DEV_ID_82546EB_QUAD_COPPER0x101D:
450 hw->mac_type = em_82546;
451 break;
452 case E1000_DEV_ID_82546GB_COPPER0x1079:
453 case E1000_DEV_ID_82546GB_FIBER0x107A:
454 case E1000_DEV_ID_82546GB_SERDES0x107B:
455 case E1000_DEV_ID_82546GB_PCIE0x108A:
456 case E1000_DEV_ID_82546GB_QUAD_COPPER0x1099:
457 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP30x10B5:
458 case E1000_DEV_ID_82546GB_20x109B:
459 hw->mac_type = em_82546_rev_3;
460 break;
461 case E1000_DEV_ID_82541EI0x1013:
462 case E1000_DEV_ID_82541EI_MOBILE0x1018:
463 case E1000_DEV_ID_82541ER_LOM0x1014:
464 hw->mac_type = em_82541;
465 break;
466 case E1000_DEV_ID_82541ER0x1078:
467 case E1000_DEV_ID_82541GI0x1076:
468 case E1000_DEV_ID_82541GI_LF0x107C:
469 case E1000_DEV_ID_82541GI_MOBILE0x1077:
470 hw->mac_type = em_82541_rev_2;
471 break;
472 case E1000_DEV_ID_82547EI0x1019:
473 case E1000_DEV_ID_82547EI_MOBILE0x101A:
474 hw->mac_type = em_82547;
475 break;
476 case E1000_DEV_ID_82547GI0x1075:
477 hw->mac_type = em_82547_rev_2;
478 break;
479 case E1000_DEV_ID_82571EB_AF0x10A1:
480 case E1000_DEV_ID_82571EB_AT0x10A0:
481 case E1000_DEV_ID_82571EB_COPPER0x105E:
482 case E1000_DEV_ID_82571EB_FIBER0x105F:
483 case E1000_DEV_ID_82571EB_SERDES0x1060:
484 case E1000_DEV_ID_82571EB_QUAD_COPPER0x10A4:
485 case E1000_DEV_ID_82571EB_QUAD_FIBER0x10A5:
486 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP0x10BC:
487 case E1000_DEV_ID_82571EB_SERDES_DUAL0x10D9:
488 case E1000_DEV_ID_82571EB_SERDES_QUAD0x10DA:
489 case E1000_DEV_ID_82571PT_QUAD_COPPER0x10D5:
490 hw->mac_type = em_82571;
491 break;
492 case E1000_DEV_ID_82572EI_COPPER0x107D:
493 case E1000_DEV_ID_82572EI_FIBER0x107E:
494 case E1000_DEV_ID_82572EI_SERDES0x107F:
495 case E1000_DEV_ID_82572EI0x10B9:
496 hw->mac_type = em_82572;
497 break;
498 case E1000_DEV_ID_82573E0x108B:
499 case E1000_DEV_ID_82573E_IAMT0x108C:
500 case E1000_DEV_ID_82573E_PM0x10B3:
501 case E1000_DEV_ID_82573L0x109A:
502 case E1000_DEV_ID_82573L_PL_10x10B0:
503 case E1000_DEV_ID_82573L_PL_20x10B4:
504 case E1000_DEV_ID_82573V_PM0x10B2:
505 hw->mac_type = em_82573;
506 break;
507 case E1000_DEV_ID_82574L0x10D3:
508 case E1000_DEV_ID_82574LA0x10F6:
509 case E1000_DEV_ID_82583V0x150C:
510 hw->mac_type = em_82574;
511 break;
512 case E1000_DEV_ID_82575EB_PT0x10A7:
513 case E1000_DEV_ID_82575EB_PF0x10A9:
514 case E1000_DEV_ID_82575GB_QP0x10D6:
515 case E1000_DEV_ID_82575GB_QP_PM0x10E2:
516 hw->mac_type = em_82575;
517 hw->initialize_hw_bits_disable = 1;
518 break;
519 case E1000_DEV_ID_825760x10C9:
520 case E1000_DEV_ID_82576_FIBER0x10E6:
521 case E1000_DEV_ID_82576_SERDES0x10E7:
522 case E1000_DEV_ID_82576_QUAD_COPPER0x10E8:
523 case E1000_DEV_ID_82576_QUAD_CU_ET20x1526:
524 case E1000_DEV_ID_82576_NS0x150A:
525 case E1000_DEV_ID_82576_NS_SERDES0x1518:
526 case E1000_DEV_ID_82576_SERDES_QUAD0x150D:
527 hw->mac_type = em_82576;
528 hw->initialize_hw_bits_disable = 1;
529 break;
530 case E1000_DEV_ID_82580_COPPER0x150E:
531 case E1000_DEV_ID_82580_FIBER0x150F:
532 case E1000_DEV_ID_82580_QUAD_FIBER0x1527:
533 case E1000_DEV_ID_82580_SERDES0x1510:
534 case E1000_DEV_ID_82580_SGMII0x1511:
535 case E1000_DEV_ID_82580_COPPER_DUAL0x1516:
536 case E1000_DEV_ID_DH89XXCC_SGMII0x0438:
537 case E1000_DEV_ID_DH89XXCC_SERDES0x043A:
538 case E1000_DEV_ID_DH89XXCC_BACKPLANE0x043C:
539 case E1000_DEV_ID_DH89XXCC_SFP0x0440:
540 hw->mac_type = em_82580;
541 hw->initialize_hw_bits_disable = 1;
542 break;
543 case E1000_DEV_ID_I210_COPPER0x1533:
544 case E1000_DEV_ID_I210_COPPER_OEM10x1534:
545 case E1000_DEV_ID_I210_COPPER_IT0x1535:
546 case E1000_DEV_ID_I210_FIBER0x1536:
547 case E1000_DEV_ID_I210_SERDES0x1537:
548 case E1000_DEV_ID_I210_SGMII0x1538:
549 case E1000_DEV_ID_I210_COPPER_FLASHLESS0x157B:
550 case E1000_DEV_ID_I210_SERDES_FLASHLESS0x157C:
551 case E1000_DEV_ID_I211_COPPER0x1539:
552 hw->mac_type = em_i210;
553 hw->initialize_hw_bits_disable = 1;
554 hw->eee_enable = 1;
555 break;
556 case E1000_DEV_ID_I350_COPPER0x1521:
557 case E1000_DEV_ID_I350_FIBER0x1522:
558 case E1000_DEV_ID_I350_SERDES0x1523:
559 case E1000_DEV_ID_I350_SGMII0x1524:
560 case E1000_DEV_ID_I350_DA40x1546:
561 case E1000_DEV_ID_I354_BACKPLANE_1GBPS0x1F40:
562 case E1000_DEV_ID_I354_SGMII0x1F41:
563 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS0x1F45:
564 hw->mac_type = em_i350;
565 hw->initialize_hw_bits_disable = 1;
566 hw->eee_enable = 1;
567 break;
568 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT0x10BA:
569 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT0x10BB:
570 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT0x1096:
571 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT0x1098:
572 hw->mac_type = em_80003es2lan;
573 break;
574 case E1000_DEV_ID_ICH8_IFE0x104C:
575 case E1000_DEV_ID_ICH8_IFE_G0x10C5:
576 case E1000_DEV_ID_ICH8_IFE_GT0x10C4:
577 case E1000_DEV_ID_ICH8_IGP_AMT0x104A:
578 case E1000_DEV_ID_ICH8_IGP_C0x104B:
579 case E1000_DEV_ID_ICH8_IGP_M0x104D:
580 case E1000_DEV_ID_ICH8_IGP_M_AMT0x1049:
581 case E1000_DEV_ID_ICH8_82567V_30x1501:
582 hw->mac_type = em_ich8lan;
583 break;
584 case E1000_DEV_ID_ICH9_BM0x10E5:
585 case E1000_DEV_ID_ICH9_IFE0x10C0:
586 case E1000_DEV_ID_ICH9_IFE_G0x10C2:
587 case E1000_DEV_ID_ICH9_IFE_GT0x10C3:
588 case E1000_DEV_ID_ICH9_IGP_AMT0x10BD:
589 case E1000_DEV_ID_ICH9_IGP_C0x294C:
590 case E1000_DEV_ID_ICH9_IGP_M0x10BF:
591 case E1000_DEV_ID_ICH9_IGP_M_AMT0x10F5:
592 case E1000_DEV_ID_ICH9_IGP_M_V0x10CB:
593 case E1000_DEV_ID_ICH10_R_BM_LF0x10CD:
594 case E1000_DEV_ID_ICH10_R_BM_LM0x10CC:
595 case E1000_DEV_ID_ICH10_R_BM_V0x10CE:
596 hw->mac_type = em_ich9lan;
597 break;
598 case E1000_DEV_ID_ICH10_D_BM_LF0x10DF:
599 case E1000_DEV_ID_ICH10_D_BM_LM0x10DE:
600 case E1000_DEV_ID_ICH10_D_BM_V0x1525:
601 hw->mac_type = em_ich10lan;
602 break;
603 case E1000_DEV_ID_PCH_M_HV_LC0x10EB:
604 case E1000_DEV_ID_PCH_M_HV_LM0x10EA:
605 case E1000_DEV_ID_PCH_D_HV_DC0x10F0:
606 case E1000_DEV_ID_PCH_D_HV_DM0x10EF:
607 hw->mac_type = em_pchlan;
608 hw->eee_enable = 1;
609 break;
610 case E1000_DEV_ID_PCH2_LV_LM0x1502:
611 case E1000_DEV_ID_PCH2_LV_V0x1503:
612 hw->mac_type = em_pch2lan;
613 break;
614 case E1000_DEV_ID_PCH_LPT_I217_LM0x153A:
615 case E1000_DEV_ID_PCH_LPT_I217_V0x153B:
616 case E1000_DEV_ID_PCH_LPTLP_I218_LM0x155A:
617 case E1000_DEV_ID_PCH_LPTLP_I218_V0x1559:
618 case E1000_DEV_ID_PCH_I218_LM20x15A0:
619 case E1000_DEV_ID_PCH_I218_V20x15A1:
620 case E1000_DEV_ID_PCH_I218_LM30x15A2:
621 case E1000_DEV_ID_PCH_I218_V30x15A3:
622 hw->mac_type = em_pch_lpt;
623 break;
624 case E1000_DEV_ID_PCH_SPT_I219_LM0x156F:
625 case E1000_DEV_ID_PCH_SPT_I219_V0x1570:
626 case E1000_DEV_ID_PCH_SPT_I219_LM20x15B7:
627 case E1000_DEV_ID_PCH_SPT_I219_V20x15B8:
628 case E1000_DEV_ID_PCH_LBG_I219_LM30x15B9:
629 case E1000_DEV_ID_PCH_SPT_I219_LM40x15D7:
630 case E1000_DEV_ID_PCH_SPT_I219_V40x15D8:
631 case E1000_DEV_ID_PCH_SPT_I219_LM50x15E3:
632 case E1000_DEV_ID_PCH_SPT_I219_V50x15D6:
633 case E1000_DEV_ID_PCH_CMP_I219_LM120x0D53:
634 case E1000_DEV_ID_PCH_CMP_I219_V120x0D55:
635 hw->mac_type = em_pch_spt;
636 break;
637 case E1000_DEV_ID_PCH_CNP_I219_LM60x15BD:
638 case E1000_DEV_ID_PCH_CNP_I219_V60x15BE:
639 case E1000_DEV_ID_PCH_CNP_I219_LM70x15BB:
640 case E1000_DEV_ID_PCH_CNP_I219_V70x15BC:
641 case E1000_DEV_ID_PCH_ICP_I219_LM80x15DF:
642 case E1000_DEV_ID_PCH_ICP_I219_V80x15E0:
643 case E1000_DEV_ID_PCH_ICP_I219_LM90x15E1:
644 case E1000_DEV_ID_PCH_ICP_I219_V90x15E2:
645 case E1000_DEV_ID_PCH_CMP_I219_LM100x0D4E:
646 case E1000_DEV_ID_PCH_CMP_I219_V100x0D4F:
647 case E1000_DEV_ID_PCH_CMP_I219_LM110x0D4C:
648 case E1000_DEV_ID_PCH_CMP_I219_V110x0D4D:
649 case E1000_DEV_ID_PCH_TGP_I219_LM130x15FB:
650 case E1000_DEV_ID_PCH_TGP_I219_V130x15FC:
651 case E1000_DEV_ID_PCH_TGP_I219_LM140x15F9:
652 case E1000_DEV_ID_PCH_TGP_I219_V140x15FA:
653 case E1000_DEV_ID_PCH_TGP_I219_LM150x15F4:
654 case E1000_DEV_ID_PCH_TGP_I219_V150x15F5:
655 case E1000_DEV_ID_PCH_ADP_I219_LM160x1A1E:
656 case E1000_DEV_ID_PCH_ADP_I219_V160x1A1F:
657 case E1000_DEV_ID_PCH_ADP_I219_LM170x1A1C:
658 case E1000_DEV_ID_PCH_ADP_I219_V170x1A1D:
659 case E1000_DEV_ID_PCH_MTP_I219_LM180x550A:
660 case E1000_DEV_ID_PCH_MTP_I219_V180x550B:
661 case E1000_DEV_ID_PCH_MTP_I219_LM190x550C:
662 case E1000_DEV_ID_PCH_MTP_I219_V190x550D:
663 hw->mac_type = em_pch_cnp;
664 break;
665 case E1000_DEV_ID_EP80579_LAN_10x5040:
666 hw->mac_type = em_icp_xxxx;
667 hw->icp_xxxx_port_num = 0;
668 break;
669 case E1000_DEV_ID_EP80579_LAN_20x5044:
670 case E1000_DEV_ID_EP80579_LAN_40x5041:
671 hw->mac_type = em_icp_xxxx;
672 hw->icp_xxxx_port_num = 1;
673 break;
674 case E1000_DEV_ID_EP80579_LAN_30x5048:
675 case E1000_DEV_ID_EP80579_LAN_50x5045:
676 hw->mac_type = em_icp_xxxx;
677 hw->icp_xxxx_port_num = 2;
678 break;
679 case E1000_DEV_ID_EP80579_LAN_60x5049:
680 hw->mac_type = em_icp_xxxx;
681 hw->icp_xxxx_port_num = 3;
682 break;
683 default:
684 /* Should never have loaded on this device */
685 return -E1000_ERR_MAC_TYPE5;
686 }
687
688 switch (hw->mac_type) {
689 case em_ich8lan:
690 case em_ich9lan:
691 case em_ich10lan:
692 case em_pchlan:
693 case em_pch2lan:
694 case em_pch_lpt:
695 case em_pch_spt:
696 case em_pch_cnp:
697 hw->swfwhw_semaphore_present = TRUE1;
698 hw->asf_firmware_present = TRUE1;
699 break;
700 case em_80003es2lan:
701 case em_82575:
702 case em_82576:
703 case em_82580:
704 case em_i210:
705 case em_i350:
706 hw->swfw_sync_present = TRUE1;
707 /* FALLTHROUGH */
708 case em_82571:
709 case em_82572:
710 case em_82573:
711 case em_82574:
712 hw->eeprom_semaphore_present = TRUE1;
713 /* FALLTHROUGH */
714 case em_82541:
715 case em_82547:
716 case em_82541_rev_2:
717 case em_82547_rev_2:
718 hw->asf_firmware_present = TRUE1;
719 break;
720 default:
721 break;
722 }
723
724 return E1000_SUCCESS0;
725}
726
727/**
728 * em_set_sfp_media_type_82575 - derives SFP module media type.
729 * @hw: pointer to the HW structure
730 *
731 * The media type is chosen based on SFP module.
732 * compatibility flags retrieved from SFP ID EEPROM.
733 **/
734STATIC int32_t em_set_sfp_media_type_82575(struct em_hw *hw)
735{
736 struct sfp_e1000_flags eth_flags;
737 int32_t ret_val = E1000_ERR_CONFIG3;
738 uint32_t ctrl_ext = 0;
739 uint8_t transceiver_type = 0;
740 int32_t timeout = 3;
741
742 /* Turn I2C interface ON and power on sfp cage */
743 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
744 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA0x00000080;
745 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext | 0x02000000)))
;
746
747 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
748
749 /* Read SFP module data */
750 while (timeout) {
751 ret_val = em_read_sfp_data_byte(hw,
752 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET)(0x0000 + (0x00)),
753 &transceiver_type);
754 if (ret_val == E1000_SUCCESS0)
755 break;
756 msec_delay(100)(*delay_func)(1000*(100));
757 timeout--;
758 }
759 if (ret_val != E1000_SUCCESS0)
760 goto out;
761
762 ret_val = em_read_sfp_data_byte(hw,
763 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET)(0x0000 + (0x06)),
764 (uint8_t *)&eth_flags);
765 if (ret_val != E1000_SUCCESS0)
766 goto out;
767
768 /* Check if there is some SFP module plugged and powered */
769 if ((transceiver_type == E1000_SFF_IDENTIFIER_SFP0x03) ||
770 (transceiver_type == E1000_SFF_IDENTIFIER_SFF0x02)) {
771 if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) {
772 hw->media_type = em_media_type_internal_serdes;
773 } else if (eth_flags.e100_base_fx || eth_flags.e100_base_lx) {
774 hw->media_type = em_media_type_internal_serdes;
775 hw->sgmii_active = TRUE1;
776 } else if (eth_flags.e1000_base_t) {
777 hw->media_type = em_media_type_copper;
778 hw->sgmii_active = TRUE1;
779 } else {
780 DEBUGOUT("PHY module has not been recognized\n");
781 ret_val = E1000_ERR_CONFIG3;
782 goto out;
783 }
784 } else {
785 ret_val = E1000_ERR_CONFIG3;
786 goto out;
787 }
788 ret_val = E1000_SUCCESS0;
789out:
790 /* Restore I2C interface setting */
791 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)))
;
792 return ret_val;
793}
794
795
796/*****************************************************************************
797 * Set media type and TBI compatibility.
798 *
799 * hw - Struct containing variables accessed by shared code
800 * **************************************************************************/
801void
802em_set_media_type(struct em_hw *hw)
803{
804 uint32_t status, ctrl_ext, mdic;
805 DEBUGFUNC("em_set_media_type");;
806
807 if (hw->mac_type != em_82543) {
808 /* tbi_compatibility is only valid on 82543 */
809 hw->tbi_compatibility_en = FALSE0;
810 }
811
812 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
813 hw->mac_type == em_82576 ||
814 hw->mac_type == em_i210 || hw->mac_type == em_i350) {
815 hw->media_type = em_media_type_copper;
816 hw->sgmii_active = FALSE0;
817
818 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
819 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) {
820 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX0x00400000:
821 hw->media_type = em_media_type_internal_serdes;
822 ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000;
823 break;
824 case E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000:
825 mdic = EM_READ_REG(hw, E1000_MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00E04)))
;
826 ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000;
827 if (mdic & E1000_MDICNFG_EXT_MDIO0x80000000) {
828 hw->media_type = em_media_type_copper;
829 hw->sgmii_active = TRUE1;
830 break;
831 }
832 /* FALLTHROUGH */
833 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000:
834 ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000;
835 if (em_set_sfp_media_type_82575(hw) != 0) {
836 hw->media_type = em_media_type_internal_serdes;
837 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) ==
838 E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000) {
839 hw->media_type = em_media_type_copper;
840 hw->sgmii_active = TRUE1;
841 }
842 }
843
844 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000;
845 if (hw->sgmii_active)
846 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000;
847 else
848 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000;
849 break;
850 default:
851 ctrl_ext &= ~E1000_CTRL_I2C_ENA0x02000000;
852 break;
853 }
854 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)))
;
855 return;
856 }
857
858 switch (hw->device_id) {
859 case E1000_DEV_ID_82545GM_SERDES0x1028:
860 case E1000_DEV_ID_82546GB_SERDES0x107B:
861 case E1000_DEV_ID_82571EB_SERDES0x1060:
862 case E1000_DEV_ID_82571EB_SERDES_DUAL0x10D9:
863 case E1000_DEV_ID_82571EB_SERDES_QUAD0x10DA:
864 case E1000_DEV_ID_82572EI_SERDES0x107F:
865 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT0x1098:
866 hw->media_type = em_media_type_internal_serdes;
867 break;
868 case E1000_DEV_ID_EP80579_LAN_10x5040:
869 case E1000_DEV_ID_EP80579_LAN_20x5044:
870 case E1000_DEV_ID_EP80579_LAN_30x5048:
871 case E1000_DEV_ID_EP80579_LAN_40x5041:
872 case E1000_DEV_ID_EP80579_LAN_50x5045:
873 case E1000_DEV_ID_EP80579_LAN_60x5049:
874 hw->media_type = em_media_type_copper;
875 break;
876 default:
877 switch (hw->mac_type) {
878 case em_82542_rev2_0:
879 case em_82542_rev2_1:
880 hw->media_type = em_media_type_fiber;
881 break;
882 case em_ich8lan:
883 case em_ich9lan:
884 case em_ich10lan:
885 case em_pchlan:
886 case em_pch2lan:
887 case em_pch_lpt:
888 case em_pch_spt:
889 case em_pch_cnp:
890 case em_82573:
891 case em_82574:
892 /*
893 * The STATUS_TBIMODE bit is reserved or reused for
894 * the this device.
895 */
896 hw->media_type = em_media_type_copper;
897 break;
898 default:
899 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
900 if (status & E1000_STATUS_TBIMODE0x00000020) {
901 hw->media_type = em_media_type_fiber;
902 /* tbi_compatibility not valid on fiber */
903 hw->tbi_compatibility_en = FALSE0;
904 } else {
905 hw->media_type = em_media_type_copper;
906 }
907 break;
908 }
909 }
910}
911/******************************************************************************
912 * Reset the transmit and receive units; mask and clear all interrupts.
913 *
914 * hw - Struct containing variables accessed by shared code
915 *****************************************************************************/
916int32_t
917em_reset_hw(struct em_hw *hw)
918{
919 uint32_t ctrl;
920 uint32_t ctrl_ext;
921 uint32_t icr;
922 uint32_t manc;
923 uint32_t led_ctrl;
924 uint32_t timeout;
925 uint32_t extcnf_ctrl;
926 int32_t ret_val;
927 DEBUGFUNC("em_reset_hw");;
928
929 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
930 if (hw->mac_type == em_82542_rev2_0) {
931 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
932 em_pci_clear_mwi(hw);
933 }
934 if (hw->bus_type == em_bus_type_pci_express) {
935 /*
936 * Prevent the PCI-E bus from sticking if there is no TLP
937 * connection on the last TLP read/write transaction when MAC
938 * is reset.
939 */
940 if (em_disable_pciex_master(hw) != E1000_SUCCESS0) {
941 DEBUGOUT("PCI-E Master disable polling has failed.\n");
942 }
943 }
944
945 /* Set the completion timeout for 82575 chips */
946 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
947 hw->mac_type == em_82576 ||
948 hw->mac_type == em_i210 || hw->mac_type == em_i350) {
949 ret_val = em_set_pciex_completion_timeout(hw);
950 if (ret_val) {
951 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
952 }
953 }
954
955 /* Clear interrupt mask to stop board from generating interrupts */
956 DEBUGOUT("Masking off all interrupts\n");
957 E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register
(0x000D8))), (0xffffffff)))
;
958 /*
959 * Disable the Transmit and Receive units. Then delay to allow any
960 * pending transactions to complete before we hit the MAC with the
961 * global reset.
962 */
963 E1000_WRITE_REG(hw, RCTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (0)))
;
964 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400))), (0x00000008)))
;
965 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
966 /*
967 * The tbi_compatibility_on Flag must be cleared when Rctl is
968 * cleared.
969 */
970 hw->tbi_compatibility_on = FALSE0;
971 /*
972 * Delay to allow any outstanding PCI transactions to complete before
973 * resetting the device
974 */
975 msec_delay(10)(*delay_func)(1000*(10));
976
977 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
978
979 /* Must reset the PHY before resetting the MAC */
980 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
981 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((ctrl | 0x80000000))))
;
982 msec_delay(5)(*delay_func)(1000*(5));
983 }
984 /*
985 * Must acquire the MDIO ownership before MAC reset. Ownership
986 * defaults to firmware after a reset.
987 */
988 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
989 timeout = 10;
990
991 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))))
;
992 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020;
993
994 do {
995 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00))), (extcnf_ctrl)))
;
996 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))))
;
997
998 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020)
999 break;
1000 else
1001 extcnf_ctrl |=
1002 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020;
1003
1004 msec_delay(2)(*delay_func)(1000*(2));
1005 timeout--;
1006 } while (timeout);
1007 }
1008 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1009 if (hw->mac_type == em_ich8lan) {
1010 /* Set Tx and Rx buffer allocation to 8k apiece. */
1011 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01000 : em_translate_82542_register
(0x01000))), (0x0008)))
;
1012 /* Set Packet Buffer Size to 16k. */
1013 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01008 : em_translate_82542_register
(0x01008))), (0x0010)))
;
1014 }
1015 /*
1016 * Issue a global reset to the MAC. This will reset the chip's
1017 * transmit, receive, DMA, and link units. It will not effect the
1018 * current PCI configuration. The global reset bit is self-
1019 * clearing, and should clear within a microsecond.
1020 */
1021 DEBUGOUT("Issuing a global reset to MAC\n");
1022
1023 switch (hw->mac_type) {
1024 case em_82544:
1025 case em_82540:
1026 case em_82545:
1027 case em_82546:
1028 case em_82541:
1029 case em_82541_rev_2:
1030 /*
1031 * These controllers can't ack the 64-bit write when issuing
1032 * the reset, so use IO-mapping as a workaround to issue the
1033 * reset
1034 */
1035 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST))em_write_reg_io((hw), 0x00000, (ctrl | 0x04000000));
1036 break;
1037 case em_82545_rev_3:
1038 case em_82546_rev_3:
1039 /* Reset is performed on a shadow of the control register */
1040 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00004 : em_translate_82542_register
(0x00004))), ((ctrl | 0x04000000))))
;
1041 break;
1042 case em_ich8lan:
1043 case em_ich9lan:
1044 case em_ich10lan:
1045 case em_pchlan:
1046 case em_pch2lan:
1047 case em_pch_lpt:
1048 case em_pch_spt:
1049 case em_pch_cnp:
1050 if (!hw->phy_reset_disable &&
1051 em_check_phy_reset_block(hw) == E1000_SUCCESS0) {
1052 /*
1053 * PHY HW reset requires MAC CORE reset at the same
1054 * time to make sure the interface between MAC and
1055 * the external PHY is reset.
1056 */
1057 ctrl |= E1000_CTRL_PHY_RST0x80000000;
1058 /*
1059 * Gate automatic PHY configuration by hardware on
1060 * non-managed 82579
1061 */
1062 if ((hw->mac_type == em_pch2lan) &&
1063 !(E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54)))))
& E1000_FWSM_FW_VALID0x00008000)) {
1064 em_gate_hw_phy_config_ich8lan(hw, TRUE1);
1065 }
1066 }
1067 em_get_software_flag(hw);
1068 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((ctrl | 0x04000000))))
;
1069 /* HW reset releases software_flag */
1070 hw->sw_flag = 0;
1071 msec_delay(20)(*delay_func)(1000*(20));
1072
1073 /* Ungate automatic PHY configuration on non-managed 82579 */
1074 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable &&
1075 !(E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54)))))
& E1000_FWSM_FW_VALID0x00008000)) {
1076 msec_delay(10)(*delay_func)(1000*(10));
1077 em_gate_hw_phy_config_ich8lan(hw, FALSE0);
1078 }
1079 break;
1080 default:
1081 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((ctrl | 0x04000000))))
;
1082 break;
1083 }
1084
1085 if (em_check_phy_reset_block(hw) == E1000_SUCCESS0) {
1086 if (hw->mac_type == em_pchlan) {
1087 ret_val = em_hv_phy_workarounds_ich8lan(hw);
1088 if (ret_val)
1089 return ret_val;
1090 }
1091 else if (hw->mac_type == em_pch2lan) {
1092 ret_val = em_lv_phy_workarounds_ich8lan(hw);
1093 if (ret_val)
1094 return ret_val;
1095 }
1096 }
1097
1098 /*
1099 * After MAC reset, force reload of EEPROM to restore power-on
1100 * settings to device. Later controllers reload the EEPROM
1101 * automatically, so just wait for reload to complete.
1102 */
1103 switch (hw->mac_type) {
1104 case em_82542_rev2_0:
1105 case em_82542_rev2_1:
1106 case em_82543:
1107 case em_82544:
1108 /* Wait for reset to complete */
1109 usec_delay(10)(*delay_func)(10);
1110 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
1111 ctrl_ext |= E1000_CTRL_EXT_EE_RST0x00002000;
1112 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)))
;
1113 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
1114 /* Wait for EEPROM reload */
1115 msec_delay(2)(*delay_func)(1000*(2));
1116 break;
1117 case em_82541:
1118 case em_82541_rev_2:
1119 case em_82547:
1120 case em_82547_rev_2:
1121 /* Wait for EEPROM reload */
1122 msec_delay(20)(*delay_func)(1000*(20));
1123 break;
1124 case em_82573:
1125 case em_82574:
1126 if (em_is_onboard_nvm_eeprom(hw) == FALSE0) {
1127 usec_delay(10)(*delay_func)(10);
1128 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
1129 ctrl_ext |= E1000_CTRL_EXT_EE_RST0x00002000;
1130 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)))
;
1131 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
1132 }
1133 /* FALLTHROUGH */
1134
1135 /* Auto read done will delay 5ms or poll based on mac type */
1136 ret_val = em_get_auto_rd_done(hw);
1137 if (ret_val)
1138 return ret_val;
1139 break;
1140 default:
1141 /* Wait for EEPROM reload (it happens automatically) */
1142 msec_delay(5)(*delay_func)(1000*(5));
1143 break;
1144 }
1145
1146 /* Disable HW ARPs on ASF enabled adapters */
1147 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 &&
1148 hw->mac_type != em_icp_xxxx) {
1149 manc = E1000_READ_REG(hw, MANC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05820 : em_translate_82542_register
(0x05820)))))
;
1150 manc &= ~(E1000_MANC_ARP_EN0x00002000);
1151 E1000_WRITE_REG(hw, MANC, manc)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05820 : em_translate_82542_register
(0x05820))), (manc)))
;
1152 }
1153 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
1154 em_phy_init_script(hw);
1155
1156 /* Configure activity LED after PHY reset */
1157 led_ctrl = E1000_READ_REG(hw, LEDCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00)))))
;
1158 led_ctrl &= IGP_ACTIVITY_LED_MASK0xFFFFF0FF;
1159 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE0x0300 | IGP_LED3_MODE0x07000000);
1160 E1000_WRITE_REG(hw, LEDCTL, led_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00))), (led_ctrl)))
;
1161 }
1162
1163 /*
1164 * For PCH, this write will make sure that any noise
1165 * will be detected as a CRC error and be dropped rather than show up
1166 * as a bad packet to the DMA engine.
1167 */
1168 if (hw->mac_type == em_pchlan)
1169 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F50 : em_translate_82542_register
(0x05F50))), (0x65656565)))
;
1170
1171 /* Clear interrupt mask to stop board from generating interrupts */
1172 DEBUGOUT("Masking off all interrupts\n");
1173 E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register
(0x000D8))), (0xffffffff)))
;
1174
1175 /* Clear any pending interrupt events. */
1176 icr = E1000_READ_REG(hw, ICR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000C0 : em_translate_82542_register
(0x000C0)))))
;
1177
1178 /* If MWI was previously enabled, reenable it. */
1179 if (hw->mac_type == em_82542_rev2_0) {
1180 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE0x0010)
1181 em_pci_set_mwi(hw);
1182 }
1183 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
)
) {
1184 uint32_t kab = E1000_READ_REG(hw, KABGTXD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03004 : em_translate_82542_register
(0x03004)))))
;
1185 kab |= E1000_KABGTXD_BGSQLBIAS0x00050000;
1186 E1000_WRITE_REG(hw, KABGTXD, kab)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03004 : em_translate_82542_register
(0x03004))), (kab)))
;
1187 }
1188
1189 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) {
1190 uint32_t mdicnfg;
1191 uint16_t nvm_data;
1192
1193 /* clear global device reset status bit */
1194 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00008), (0x00100000)))
;
1195
1196 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A0x0024 +
1197 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func)(hw->bus_func ? (0x40 + (0x40 * hw->bus_func)) : 0), 1,
1198 &nvm_data);
1199
1200 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00E04)))
;
1201 if (nvm_data & NVM_WORD24_EXT_MDIO0x0004)
1202 mdicnfg |= E1000_MDICNFG_EXT_MDIO0x80000000;
1203 if (nvm_data & NVM_WORD24_COM_MDIO0x0008)
1204 mdicnfg |= E1000_MDICNFG_COM_MDIO0x40000000;
1205 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00E04), (mdicnfg)))
;
1206 }
1207
1208 if (hw->mac_type == em_i210 || hw->mac_type == em_i350)
1209 em_set_eee_i350(hw);
1210
1211 return E1000_SUCCESS0;
1212}
1213
1214/******************************************************************************
1215 *
1216 * Initialize a number of hardware-dependent bits
1217 *
1218 * hw: Struct containing variables accessed by shared code
1219 *
1220 *****************************************************************************/
1221STATIC void
1222em_initialize_hardware_bits(struct em_softc *sc)
1223{
1224 struct em_hw *hw = &sc->hw;
1225 struct em_queue *que;
1226
1227 DEBUGFUNC("em_initialize_hardware_bits");;
1228
1229 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) {
1230 /* Settings common to all silicon */
1231 uint32_t reg_ctrl, reg_ctrl_ext;
1232 uint32_t reg_tarc0, reg_tarc1;
1233 uint32_t reg_tctl;
1234 uint32_t reg_txdctl;
1235 reg_tarc0 = E1000_READ_REG(hw, TARC0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03840 : em_translate_82542_register
(0x03840)))))
;
1236 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and
1237 * 27 */
1238 FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++)
{
1239 reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ?
(0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me
) * 0x40))) : em_translate_82542_register(((que->me) < 4
? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->
me) * 0x40))))))))
;
1240 reg_txdctl |= E1000_TXDCTL_COUNT_DESC0x00400000; /* Set bit 22 */
1241 E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ?
(0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me
) * 0x40))) : em_translate_82542_register(((que->me) < 4
? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->
me) * 0x40)))))), (reg_txdctl)))
;
1242 }
1243
1244 /*
1245 * Old code always initialized queue 1,
1246 * even when unused, keep behaviour
1247 */
1248 if (sc->num_queues == 1) {
1249 reg_txdctl = E1000_READ_REG(hw, TXDCTL(1))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828
+ ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register
(((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40
))))))))
;
1250 reg_txdctl |= E1000_TXDCTL_COUNT_DESC0x00400000;
1251 E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828
+ ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register
(((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40
)))))), (reg_txdctl)))
;
1252 }
1253
1254 switch (hw->mac_type) {
1255 case em_82571:
1256 case em_82572:
1257 reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940)))))
;
1258 reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))))
;
1259
1260 /* Set the phy Tx compatible mode bits */
1261 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */
1262
1263 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */
1264 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */
1265
1266 if (reg_tctl & E1000_TCTL_MULR0x10000000)
1267 /* Clear bit 28 if MULR is 1b */
1268 reg_tarc1 &= ~0x10000000;
1269 else
1270 /* Set bit 28 if MULR is 0b */
1271 reg_tarc1 |= 0x10000000;
1272
1273 E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940))), (reg_tarc1)))
;
1274 break;
1275 case em_82573:
1276 case em_82574:
1277 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
1278 reg_ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
1279
1280 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */
1281 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
1282 reg_ctrl &= ~0x20000000; /* Clear bit 29 */
1283
1284 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (reg_ctrl_ext)))
;
1285 E1000_WRITE_REG(hw, CTRL, reg_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (reg_ctrl)))
;
1286 break;
1287 case em_80003es2lan:
1288 if ((hw->media_type == em_media_type_fiber) ||
1289 (hw->media_type == em_media_type_internal_serdes)) {
1290 /* Clear bit 20 */
1291 reg_tarc0 &= ~0x00100000;
1292 }
1293 reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))))
;
1294 reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940)))))
;
1295 if (reg_tctl & E1000_TCTL_MULR0x10000000)
1296 /* Clear bit 28 if MULR is 1b */
1297 reg_tarc1 &= ~0x10000000;
1298 else
1299 /* Set bit 28 if MULR is 0b */
1300 reg_tarc1 |= 0x10000000;
1301
1302 E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940))), (reg_tarc1)))
;
1303 break;
1304 case em_ich8lan:
1305 case em_ich9lan:
1306 case em_ich10lan:
1307 case em_pchlan:
1308 case em_pch2lan:
1309 case em_pch_lpt:
1310 case em_pch_spt:
1311 case em_pch_cnp:
1312 if (hw->mac_type == em_ich8lan)
1313 /* Set TARC0 bits 29 and 28 */
1314 reg_tarc0 |= 0x30000000;
1315
1316 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
1317 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
1318 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
1319 if (hw->mac_type >= em_pchlan)
1320 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN0x00100000;
1321 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (reg_ctrl_ext)))
;
1322
1323 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23,
1324 * 24, 26, 27 */
1325
1326 reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940)))))
;
1327 reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))))
;
1328
1329 if (reg_tctl & E1000_TCTL_MULR0x10000000)
1330 /* Clear bit 28 if MULR is 1b */
1331 reg_tarc1 &= ~0x10000000;
1332 else
1333 /* Set bit 28 if MULR is 0b */
1334 reg_tarc1 |= 0x10000000;
1335
1336 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and
1337 * 30 */
1338
1339 E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940))), (reg_tarc1)))
;
1340 break;
1341 default:
1342 break;
1343 }
1344
1345 E1000_WRITE_REG(hw, TARC0, reg_tarc0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03840 : em_translate_82542_register
(0x03840))), (reg_tarc0)))
;
1346 }
1347}
1348
1349/**
1350 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
1351 * @hw: pointer to the HW structure
1352 *
1353 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
1354 * used to reset the PHY to a quiescent state when necessary.
1355 **/
1356static void
1357em_toggle_lanphypc_pch_lpt(struct em_hw *hw)
1358{
1359 uint32_t mac_reg;
1360
1361 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");;
1362
1363 /* Set Phy Config Counter to 50msec */
1364 mac_reg = E1000_READ_REG(hw, FEXTNVM3)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0003C : em_translate_82542_register
(0x0003C)))))
;
1365 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK0x0C000000;
1366 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC0x08000000;
1367 E1000_WRITE_REG(hw, FEXTNVM3, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0003C : em_translate_82542_register
(0x0003C))), (mac_reg)))
;
1368
1369 /* Toggle LANPHYPC Value bit */
1370 mac_reg = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
1371 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE0x00010000;
1372 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE0x00020000;
1373 E1000_WRITE_REG(hw, CTRL, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (mac_reg)))
;
1374 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
1375 msec_delay(1)(*delay_func)(1000*(1));
1376 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE0x00010000;
1377 E1000_WRITE_REG(hw, CTRL, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (mac_reg)))
;
1378 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
1379
1380 if (hw->mac_type < em_pch_lpt) {
1381 msec_delay(50)(*delay_func)(1000*(50));
1382 } else {
1383 uint16_t count = 20;
1384
1385 do {
1386 msec_delay(5)(*delay_func)(1000*(5));
1387 } while (!(E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
&
1388 E1000_CTRL_EXT_LPCD0x00000004) && count--);
1389
1390 msec_delay(30)(*delay_func)(1000*(30));
1391 }
1392}
1393
1394/**
1395 * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1396 * @hw: pointer to the HW structure
1397 * @force: boolean indicating whether or not to force disabling ULP
1398 *
1399 * Un-configure ULP mode when link is up, the system is transitioned from
1400 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1401 * system, poll for an indication from ME that ULP has been un-configured.
1402 * If not on an ME enabled system, un-configure the ULP mode by software.
1403 *
1404 * During nominal operation, this function is called when link is acquired
1405 * to disable ULP mode (force=FALSE); otherwise, for example when unloading
1406 * the driver or during Sx->S0 transitions, this is called with force=TRUE
1407 * to forcibly disable ULP.
1408 */
1409static int
1410em_disable_ulp_lpt_lp(struct em_hw *hw, bool_Bool force)
1411{
1412 int ret_val = E1000_SUCCESS0;
1413 uint32_t mac_reg;
1414 uint16_t phy_reg;
1415 int i = 0;
1416
1417 if ((hw->mac_type < em_pch_lpt) ||
1418 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM0x153A) ||
1419 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V0x153B) ||
1420 (hw->device_id == E1000_DEV_ID_PCH_I218_LM20x15A0) ||
1421 (hw->device_id == E1000_DEV_ID_PCH_I218_V20x15A1))
1422 return 0;
1423
1424 if (E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54)))))
& E1000_FWSM_FW_VALID0x00008000) {
1425 if (force) {
1426 /* Request ME un-configure ULP mode in the PHY */
1427 mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))))
;
1428 mac_reg &= ~E1000_H2ME_ULP0x00000800;
1429 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS0x00001000;
1430 E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (mac_reg)))
;
1431 }
1432
1433 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1434 while (E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54)))))
& E1000_FWSM_ULP_CFG_DONE0x00000400) {
1435 if (i++ == 30) {
1436 ret_val = -E1000_ERR_PHY2;
1437 goto out;
1438 }
1439
1440 msec_delay(10)(*delay_func)(1000*(10));
1441 }
1442 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1443
1444 if (force) {
1445 mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))))
;
1446 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS0x00001000;
1447 E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (mac_reg)))
;
1448 } else {
1449 /* Clear H2ME.ULP after ME ULP configuration */
1450 mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))))
;
1451 mac_reg &= ~E1000_H2ME_ULP0x00000800;
1452 E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (mac_reg)))
;
1453 }
1454
1455 goto out;
1456 }
1457
1458 ret_val = em_get_software_flag(hw);
1459 if (ret_val)
1460 goto out;
1461
1462 if (force)
1463 /* Toggle LANPHYPC Value bit */
1464 em_toggle_lanphypc_pch_lpt(hw);
1465
1466 /* Unforce SMBus mode in PHY */
1467 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), &phy_reg);
1468 if (ret_val) {
1469 /* The MAC might be in PCIe mode, so temporarily force to
1470 * SMBus mode in order to access the PHY.
1471 */
1472 mac_reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
1473 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS0x00000800;
1474 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (mac_reg)))
;
1475
1476 msec_delay(50)(*delay_func)(1000*(50));
1477
1478 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), &phy_reg);
1479 if (ret_val)
1480 goto release;
1481 }
1482 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS0x0001;
1483 em_write_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), phy_reg);
1484
1485 /* Unforce SMBus mode in MAC */
1486 mac_reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
1487 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS0x00000800;
1488 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (mac_reg)))
;
1489
1490 /* When ULP mode was previously entered, K1 was disabled by the
1491 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1492 */
1493 ret_val = em_read_phy_reg(hw, HV_PM_CTRL(((770) << 5) | ((17) & 0x1F)), &phy_reg);
1494 if (ret_val)
1495 goto release;
1496 phy_reg |= HV_PM_CTRL_K1_ENABLE0x4000;
1497 em_write_phy_reg(hw, HV_PM_CTRL(((770) << 5) | ((17) & 0x1F)), phy_reg);
1498
1499 /* Clear ULP enabled configuration */
1500 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), &phy_reg);
1501 if (ret_val)
1502 goto release;
1503 phy_reg &= ~(I218_ULP_CONFIG1_IND0x0004 |
1504 I218_ULP_CONFIG1_STICKY_ULP0x0010 |
1505 I218_ULP_CONFIG1_RESET_TO_SMBUS0x0100 |
1506 I218_ULP_CONFIG1_WOL_HOST0x0040 |
1507 I218_ULP_CONFIG1_INBAND_EXIT0x0020 |
1508 I218_ULP_CONFIG1_EN_ULP_LANPHYPC0x0400 |
1509 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST0x0800 |
1510 I218_ULP_CONFIG1_DISABLE_SMB_PERST0x1000);
1511 em_write_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), phy_reg);
1512
1513 /* Commit ULP changes by starting auto ULP configuration */
1514 phy_reg |= I218_ULP_CONFIG1_START0x0001;
1515 em_write_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), phy_reg);
1516
1517 /* Clear Disable SMBus Release on PERST# in MAC */
1518 mac_reg = E1000_READ_REG(hw, FEXTNVM7)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0xe4UL : em_translate_82542_register
(0xe4UL)))))
;
1519 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST0x00000020;
1520 E1000_WRITE_REG(hw, FEXTNVM7, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0xe4UL : em_translate_82542_register
(0xe4UL))), (mac_reg)))
;
1521
1522release:
1523 em_release_software_flag(hw);
1524 if (force) {
1525 em_phy_reset(hw);
1526 msec_delay(50)(*delay_func)(1000*(50));
1527 }
1528out:
1529 if (ret_val)
1530 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1531
1532 return ret_val;
1533}
1534
1535/******************************************************************************
1536 * Performs basic configuration of the adapter.
1537 *
1538 * hw - Struct containing variables accessed by shared code
1539 *
1540 * Assumes that the controller has previously been reset and is in a
1541 * post-reset uninitialized state. Initializes the receive address registers,
1542 * multicast table, and VLAN filter table. Calls routines to setup link
1543 * configuration and flow control settings. Clears all on-chip counters. Leaves
1544 * the transmit and receive units disabled and uninitialized.
1545 *****************************************************************************/
1546int32_t
1547em_init_hw(struct em_softc *sc)
1548{
1549 struct em_hw *hw = &sc->hw;
1550 struct em_queue *que;
1551 uint32_t ctrl;
1552 uint32_t i;
1553 int32_t ret_val;
1554 uint16_t pcix_cmd_word;
1555 uint16_t pcix_stat_hi_word;
1556 uint16_t cmd_mmrbc;
1557 uint16_t stat_mmrbc;
1558 uint32_t mta_size;
1559 uint32_t reg_data;
1560 uint32_t ctrl_ext;
1561 uint32_t snoop;
1562 uint32_t fwsm;
1563 DEBUGFUNC("em_init_hw");;
1564
1565 /* force full DMA clock frequency for ICH8 */
1566 if (hw->mac_type == em_ich8lan) {
1567 reg_data = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
1568 reg_data &= ~0x80000000;
1569 E1000_WRITE_REG(hw, STATUS, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008))), (reg_data)))
;
1570 }
1571
1572 if (hw->mac_type == em_pchlan ||
1573 hw->mac_type == em_pch2lan ||
1574 hw->mac_type == em_pch_lpt ||
1575 hw->mac_type == em_pch_spt ||
1576 hw->mac_type == em_pch_cnp) {
1577 /*
1578 * The MAC-PHY interconnect may still be in SMBus mode
1579 * after Sx->S0. Toggle the LANPHYPC Value bit to force
1580 * the interconnect to PCIe mode, but only if there is no
1581 * firmware present otherwise firmware will have done it.
1582 */
1583 fwsm = E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54)))))
;
1584 if ((fwsm & E1000_FWSM_FW_VALID0x00008000) == 0) {
1585 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
1586 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE0x00010000;
1587 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE0x00020000;
1588 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
1589 usec_delay(10)(*delay_func)(10);
1590 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE0x00010000;
1591 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
1592 msec_delay(50)(*delay_func)(1000*(50));
1593 }
1594
1595 /* Gate automatic PHY configuration on non-managed 82579 */
1596 if (hw->mac_type == em_pch2lan)
1597 em_gate_hw_phy_config_ich8lan(hw, TRUE1);
1598
1599 em_disable_ulp_lpt_lp(hw, TRUE1);
1600 /*
1601 * Reset the PHY before any access to it. Doing so,
1602 * ensures that the PHY is in a known good state before
1603 * we read/write PHY registers. The generic reset is
1604 * sufficient here, because we haven't determined
1605 * the PHY type yet.
1606 */
1607 em_phy_reset(hw);
1608
1609 /* Ungate automatic PHY configuration on non-managed 82579 */
1610 if (hw->mac_type == em_pch2lan &&
1611 (fwsm & E1000_FWSM_FW_VALID0x00008000) == 0)
1612 em_gate_hw_phy_config_ich8lan(hw, FALSE0);
1613
1614 /* Set MDIO slow mode before any other MDIO access */
1615 ret_val = em_set_mdio_slow_mode_hv(hw);
1616 if (ret_val)
1617 return ret_val;
1618 }
1619
1620 /* Initialize Identification LED */
1621 ret_val = em_id_led_init(hw);
1622 if (ret_val) {
1623 DEBUGOUT("Error Initializing Identification LED\n");
1624 return ret_val;
1625 }
1626 /* Set the media type and TBI compatibility */
1627 em_set_media_type(hw);
1628
1629 /* Magic delay that improves problems with i219LM on HP Elitebook */
1630 msec_delay(1)(*delay_func)(1000*(1));
1631 /* Must be called after em_set_media_type because media_type is used */
1632 em_initialize_hardware_bits(sc);
1633
1634 /* Disabling VLAN filtering. */
1635 DEBUGOUT("Initializing the IEEE VLAN\n");
1636 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */
1637 if (!IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
)
) {
1638 if (hw->mac_type < em_82545_rev_3)
1639 E1000_WRITE_REG(hw, VET, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00038 : em_translate_82542_register
(0x00038))), (0)))
;
1640 if (hw->mac_type == em_i350)
1641 em_clear_vfta_i350(hw);
1642 else
1643 em_clear_vfta(hw);
1644 }
1645 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1646 if (hw->mac_type == em_82542_rev2_0) {
1647 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1648 em_pci_clear_mwi(hw);
1649 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (0x00000001)))
;
1650 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
1651 msec_delay(5)(*delay_func)(1000*(5));
1652 }
1653 /*
1654 * Setup the receive address. This involves initializing all of the
1655 * Receive Address Registers (RARs 0 - 15).
1656 */
1657 em_init_rx_addrs(hw);
1658
1659 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/
1660 if (hw->mac_type == em_82542_rev2_0) {
1661 E1000_WRITE_REG(hw, RCTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (0)))
;
1662 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
1663 msec_delay(1)(*delay_func)(1000*(1));
1664 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE0x0010)
1665 em_pci_set_mwi(hw);
1666 }
1667 /* Zero out the Multicast HASH table */
1668 DEBUGOUT("Zeroing the MTA\n");
1669 mta_size = E1000_MC_TBL_SIZE128;
1670 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
)
)
1671 mta_size = E1000_MC_TBL_SIZE_ICH8LAN32;
1672 for (i = 0; i < mta_size; i++) {
1673 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register
(0x05200)) + ((i) << 2)), (0)))
;
1674 /*
1675 * use write flush to prevent Memory Write Block (MWB) from
1676 * occurring when accessing our register space
1677 */
1678 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
1679 }
1680 /*
1681 * Set the PCI priority bit correctly in the CTRL register. This
1682 * determines if the adapter gives priority to receives, or if it
1683 * gives equal priority to transmits and receives. Valid only on
1684 * 82542 and 82543 silicon.
1685 */
1686 if (hw->dma_fairness && hw->mac_type <= em_82543) {
1687 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
1688 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl | 0x00000004)))
;
1689 }
1690 switch (hw->mac_type) {
1691 case em_82545_rev_3:
1692 case em_82546_rev_3:
1693 break;
1694 default:
1695 /*
1696 * Workaround for PCI-X problem when BIOS sets MMRBC
1697 * incorrectly.
1698 */
1699 if (hw->bus_type == em_bus_type_pcix) {
1700 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER0xE6,
1701 &pcix_cmd_word);
1702 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI0xEA,
1703 &pcix_stat_hi_word);
1704 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK0x000C)
1705 >> PCIX_COMMAND_MMRBC_SHIFT0x2;
1706 stat_mmrbc = (pcix_stat_hi_word &
1707 PCIX_STATUS_HI_MMRBC_MASK0x0060) >>
1708 PCIX_STATUS_HI_MMRBC_SHIFT0x5;
1709
1710 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K0x3)
1711 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K0x2;
1712 if (cmd_mmrbc > stat_mmrbc) {
1713 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK0x000C;
1714 pcix_cmd_word |= stat_mmrbc <<
1715 PCIX_COMMAND_MMRBC_SHIFT0x2;
1716 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER0xE6,
1717 &pcix_cmd_word);
1718 }
1719 }
1720 break;
1721 }
1722
1723 /* More time needed for PHY to initialize */
1724 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
)
)
1725 msec_delay(15)(*delay_func)(1000*(15));
1726
1727 /*
1728 * The 82578 Rx buffer will stall if wakeup is enabled in host and
1729 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
1730 * Reset the phy after disabling host wakeup to reset the Rx buffer.
1731 */
1732 if (hw->phy_type == em_phy_82578) {
1733 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1)(((800) << 5) | ((1) & 0x1F)),
1734 (uint16_t *)&reg_data);
1735 ret_val = em_phy_reset(hw);
1736 if (ret_val)
1737 return ret_val;
1738 }
1739
1740 /* Call a subroutine to configure the link and setup flow control. */
1741 ret_val = em_setup_link(hw);
1742
1743 /* Set the transmit descriptor write-back policy */
1744 if (hw->mac_type > em_82544) {
1745 FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++)
{
1746 ctrl = E1000_READ_REG(hw, TXDCTL(que->me))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ?
(0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me
) * 0x40))) : em_translate_82542_register(((que->me) < 4
? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->
me) * 0x40))))))))
;
1747 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH0x00FF0000) |
1748 E1000_TXDCTL_FULL_TX_DESC_WB0x01010000;
1749 E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ?
(0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me
) * 0x40))) : em_translate_82542_register(((que->me) < 4
? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->
me) * 0x40)))))), (ctrl)))
;
1750 }
1751 }
1752 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1753 em_enable_tx_pkt_filtering(hw);
1754 }
1755 switch (hw->mac_type) {
1756 default:
1757 break;
1758 case em_80003es2lan:
1759 /* Enable retransmit on late collisions */
1760 reg_data = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))))
;
1761 reg_data |= E1000_TCTL_RTLC0x01000000;
1762 E1000_WRITE_REG(hw, TCTL, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400))), (reg_data)))
;
1763
1764 /* Configure Gigabit Carry Extend Padding */
1765 reg_data = E1000_READ_REG(hw, TCTL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00404 : em_translate_82542_register
(0x00404)))))
;
1766 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK0x000FFC00;
1767 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX0x00010000;
1768 E1000_WRITE_REG(hw, TCTL_EXT, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00404 : em_translate_82542_register
(0x00404))), (reg_data)))
;
1769
1770 /* Configure Transmit Inter-Packet Gap */
1771 reg_data = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410)))))
;
1772 reg_data &= ~E1000_TIPG_IPGT_MASK0x000003FF;
1773 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_10000x00000008;
1774 E1000_WRITE_REG(hw, TIPG, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410))), (reg_data)))
;
1775
1776 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F00 : em_translate_82542_register
(0x05F00)) + ((0x0001) << 2))))
;
1777 reg_data &= ~0x00100000;
1778 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F00 : em_translate_82542_register
(0x05F00)) + ((0x0001) << 2)), (reg_data)))
;
1779 /* FALLTHROUGH */
1780 case em_82571:
1781 case em_82572:
1782 case em_82575:
1783 case em_82576:
1784 case em_82580:
1785 case em_i210:
1786 case em_i350:
1787 case em_ich8lan:
1788 case em_ich9lan:
1789 case em_ich10lan:
1790 case em_pchlan:
1791 case em_pch2lan:
1792 case em_pch_lpt:
1793 case em_pch_spt:
1794 case em_pch_cnp:
1795 /*
1796 * Old code always initialized queue 1,
1797 * even when unused, keep behaviour
1798 */
1799 if (sc->num_queues == 1) {
1800 ctrl = E1000_READ_REG(hw, TXDCTL(1))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828
+ ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register
(((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40
))))))))
;
1801 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH0x00FF0000) |
1802 E1000_TXDCTL_FULL_TX_DESC_WB0x01010000;
1803 E1000_WRITE_REG(hw, TXDCTL(1), ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828
+ ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register
(((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40
)))))), (ctrl)))
;
1804 }
1805 break;
1806 }
1807
1808 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1809 uint32_t gcr = E1000_READ_REG(hw, GCR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register
(0x05B00)))))
;
1810 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX0x08000000;
1811 E1000_WRITE_REG(hw, GCR, gcr)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register
(0x05B00))), (gcr)))
;
1812 }
1813 /*
1814 * Clear all of the statistics registers (clear on read). It is
1815 * important that we do this after we have tried to establish link
1816 * because the symbol error count will increment wildly if there is
1817 * no link.
1818 */
1819 em_clear_hw_cntrs(hw);
1820 /*
1821 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default
1822 * after reset.
1823 */
1824 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
)
) {
1825 if (hw->mac_type == em_ich8lan)
1826 snoop = PCI_EX_82566_SNOOP_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010
| 0x00000020)
;
1827 else
1828 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010
| 0x00000020)
);
1829
1830 em_set_pci_ex_no_snoop(hw, snoop);
1831 }
1832
1833 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER0x1099 ||
1834 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP30x10B5) {
1835 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
1836 /*
1837 * Relaxed ordering must be disabled to avoid a parity error
1838 * crash in a PCI slot.
1839 */
1840 ctrl_ext |= E1000_CTRL_EXT_RO_DIS0x00020000;
1841 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)))
;
1842 }
1843 return ret_val;
1844}
1845
1846/******************************************************************************
1847 * Adjust SERDES output amplitude based on EEPROM setting.
1848 *
1849 * hw - Struct containing variables accessed by shared code.
1850 *****************************************************************************/
1851static int32_t
1852em_adjust_serdes_amplitude(struct em_hw *hw)
1853{
1854 uint16_t eeprom_data;
1855 int32_t ret_val;
1856 DEBUGFUNC("em_adjust_serdes_amplitude");;
1857
1858 if (hw->media_type != em_media_type_internal_serdes ||
1859 hw->mac_type >= em_82575)
1860 return E1000_SUCCESS0;
1861
1862 switch (hw->mac_type) {
1863 case em_82545_rev_3:
1864 case em_82546_rev_3:
1865 break;
1866 default:
1867 return E1000_SUCCESS0;
1868 }
1869
1870 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE0x0006, 1, &eeprom_data);
1871 if (ret_val) {
1872 return ret_val;
1873 }
1874 if (eeprom_data != EEPROM_RESERVED_WORD0xFFFF) {
1875 /* Adjust SERDES output amplitude only. */
1876 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK0x000F;
1877 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL0x1A,
1878 eeprom_data);
1879 if (ret_val)
1880 return ret_val;
1881 }
1882 return E1000_SUCCESS0;
1883}
1884
1885/******************************************************************************
1886 * Configures flow control and link settings.
1887 *
1888 * hw - Struct containing variables accessed by shared code
1889 *
1890 * Determines which flow control settings to use. Calls the appropriate media-
1891 * specific link configuration function. Configures the flow control settings.
1892 * Assuming the adapter has a valid link partner, a valid link should be
1893 * established. Assumes the hardware has previously been reset and the
1894 * transmitter and receiver are not enabled.
1895 *****************************************************************************/
1896int32_t
1897em_setup_link(struct em_hw *hw)
1898{
1899 uint32_t ctrl_ext;
1900 int32_t ret_val;
1901 uint16_t eeprom_data;
1902 uint16_t eeprom_control2_reg_offset;
1903 DEBUGFUNC("em_setup_link");;
1904
1905 eeprom_control2_reg_offset =
1906 (hw->mac_type != em_icp_xxxx)
1907 ? EEPROM_INIT_CONTROL2_REG0x000F
1908 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num)((((hw->icp_xxxx_port_num) + 1) << 4) + 1);
1909 /*
1910 * In the case of the phy reset being blocked, we already have a
1911 * link. We do not have to set it up again.
1912 */
1913 if (em_check_phy_reset_block(hw))
1914 return E1000_SUCCESS0;
1915 /*
1916 * Read and store word 0x0F of the EEPROM. This word contains bits
1917 * that determine the hardware's default PAUSE (flow control) mode, a
1918 * bit that determines whether the HW defaults to enabling or
1919 * disabling auto-negotiation, and the direction of the SW defined
1920 * pins. If there is no SW over-ride of the flow control setting,
1921 * then the variable hw->fc will be initialized based on a value in
1922 * the EEPROM.
1923 */
1924 if (hw->fc == E1000_FC_DEFAULT0xFF) {
1925 switch (hw->mac_type) {
1926 case em_ich8lan:
1927 case em_ich9lan:
1928 case em_ich10lan:
1929 case em_pchlan:
1930 case em_pch2lan:
1931 case em_pch_lpt:
1932 case em_pch_spt:
1933 case em_pch_cnp:
1934 case em_82573:
1935 case em_82574:
1936 hw->fc = E1000_FC_FULL3;
1937 break;
1938 default:
1939 ret_val = em_read_eeprom(hw,
1940 eeprom_control2_reg_offset, 1, &eeprom_data);
1941 if (ret_val) {
1942 DEBUGOUT("EEPROM Read Error\n");
1943 return -E1000_ERR_EEPROM1;
1944 }
1945 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK0x3000) == 0)
1946 hw->fc = E1000_FC_NONE0;
1947 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK0x3000) ==
1948 EEPROM_WORD0F_ASM_DIR0x2000)
1949 hw->fc = E1000_FC_TX_PAUSE2;
1950 else
1951 hw->fc = E1000_FC_FULL3;
1952 break;
1953 }
1954 }
1955 /*
1956 * We want to save off the original Flow Control configuration just
1957 * in case we get disconnected and then reconnected into a different
1958 * hub or switch with different Flow Control capabilities.
1959 */
1960 if (hw->mac_type == em_82542_rev2_0)
1961 hw->fc &= (~E1000_FC_TX_PAUSE2);
1962
1963 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
1964 hw->fc &= (~E1000_FC_RX_PAUSE1);
1965
1966 hw->original_fc = hw->fc;
1967
1968 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1969 /*
1970 * Take the 4 bits from EEPROM word 0x0F that determine the initial
1971 * polarity value for the SW controlled pins, and setup the Extended
1972 * Device Control reg with that info. This is needed because one of
1973 * the SW controlled pins is used for signal detection. So this
1974 * should be done before em_setup_pcs_link() or em_phy_setup() is
1975 * called.
1976 */
1977 if (hw->mac_type == em_82543) {
1978 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG0x000F,
1979 1, &eeprom_data);
1980 if (ret_val) {
1981 DEBUGOUT("EEPROM Read Error\n");
1982 return -E1000_ERR_EEPROM1;
1983 }
1984 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT0x00F0) <<
1985 SWDPIO__EXT_SHIFT4);
1986 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)))
;
1987 }
1988 /* Make sure we have a valid PHY */
1989 ret_val = em_detect_gig_phy(hw);
1990 if (ret_val) {
1991 DEBUGOUT("Error, did not detect valid phy.\n");
1992 if (hw->mac_type == em_icp_xxxx)
1993 return E1000_DEFER_INIT15;
1994 else
1995 return ret_val;
1996 }
1997 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1998
1999 /* Call the necessary subroutine to configure the link. */
2000 switch (hw->media_type) {
2001 case em_media_type_copper:
2002 case em_media_type_oem:
2003 ret_val = em_setup_copper_link(hw);
2004 break;
2005 default:
2006 ret_val = em_setup_fiber_serdes_link(hw);
2007 break;
2008 }
2009 /*
2010 * Initialize the flow control address, type, and PAUSE timer
2011 * registers to their default values. This is done even if flow
2012 * control is disabled, because it does not hurt anything to
2013 * initialize these registers.
2014 */
2015 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"
2016 );
2017
2018 /*
2019 * FCAL/H and FCT are hardcoded to standard values in
2020 * em_ich8lan / em_ich9lan / em_ich10lan.
2021 */
2022 if (!IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
)
) {
2023 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00030 : em_translate_82542_register
(0x00030))), (0x8808)))
;
2024 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0002C : em_translate_82542_register
(0x0002C))), (0x00000100)))
;
2025 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00028 : em_translate_82542_register
(0x00028))), (0x00C28001)))
;
2026 }
2027 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00170 : em_translate_82542_register
(0x00170))), (hw->fc_pause_time)))
;
2028
2029 if (hw->phy_type == em_phy_82577 ||
2030 hw->phy_type == em_phy_82578 ||
2031 hw->phy_type == em_phy_82579 ||
2032 hw->phy_type == em_phy_i217) {
2033 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F40 : em_translate_82542_register
(0x05F40))), (0x1000)))
;
2034 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27)(((769) << 5) | ((27) & 0x1F)),
2035 hw->fc_pause_time);
2036 }
2037
2038 /*
2039 * Set the flow control receive threshold registers. Normally, these
2040 * registers will be set to a default threshold that may be adjusted
2041 * later by the driver's runtime code. However, if the ability to
2042 * transmit pause frames in not enabled, then these registers will be
2043 * set to 0.
2044 */
2045 if (!(hw->fc & E1000_FC_TX_PAUSE2)) {
2046 E1000_WRITE_REG(hw, FCRTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register
(0x02160))), (0)))
;
2047 E1000_WRITE_REG(hw, FCRTH, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register
(0x02168))), (0)))
;
2048 } else {
2049 /*
2050 * We need to set up the Receive Threshold high and low water
2051 * marks as well as (optionally) enabling the transmission of
2052 * XON frames.
2053 */
2054 if (hw->fc_send_xon) {
2055 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register
(0x02160))), ((hw->fc_low_water | 0x80000000))))
2056 | E1000_FCRTL_XONE))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register
(0x02160))), ((hw->fc_low_water | 0x80000000))))
;
2057 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register
(0x02168))), (hw->fc_high_water)))
;
2058 } else {
2059 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register
(0x02160))), (hw->fc_low_water)))
;
2060 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register
(0x02168))), (hw->fc_high_water)))
;
2061 }
2062 }
2063 return ret_val;
2064}
2065
2066void
2067em_power_up_serdes_link_82575(struct em_hw *hw)
2068{
2069 uint32_t reg;
2070
2071 if (hw->media_type != em_media_type_internal_serdes &&
2072 hw->sgmii_active == FALSE0)
2073 return;
2074
2075 /* Enable PCS to turn on link */
2076 reg = E1000_READ_REG(hw, PCS_CFG0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04200 : em_translate_82542_register
(0x04200)))))
;
2077 reg |= E1000_PCS_CFG_PCS_EN8;
2078 E1000_WRITE_REG(hw, PCS_CFG0, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04200 : em_translate_82542_register
(0x04200))), (reg)))
;
2079
2080 /* Power up the laser */
2081 reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
2082 reg &= ~E1000_CTRL_EXT_SDP3_DATA0x00000080;
2083 E1000_WRITE_REG(hw, CTRL_EXT, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (reg)))
;
2084
2085 /* flush the write to verify completion */
2086 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
2087 delay(5)(*delay_func)(5);
2088}
2089
2090/******************************************************************************
2091 * Sets up link for a fiber based or serdes based adapter
2092 *
2093 * hw - Struct containing variables accessed by shared code
2094 *
2095 * Manipulates Physical Coding Sublayer functions in order to configure
2096 * link. Assumes the hardware has been previously reset and the transmitter
2097 * and receiver are not enabled.
2098 *****************************************************************************/
2099static int32_t
2100em_setup_fiber_serdes_link(struct em_hw *hw)
2101{
2102 uint32_t ctrl, ctrl_ext, reg;
2103 uint32_t status;
2104 uint32_t txcw = 0;
2105 uint32_t i;
2106 uint32_t signal = 0;
2107 int32_t ret_val;
2108 DEBUGFUNC("em_setup_fiber_serdes_link");;
2109
2110 if (hw->media_type != em_media_type_internal_serdes &&
2111 hw->sgmii_active == FALSE0)
2112 return -E1000_ERR_CONFIG3;
2113
2114 /*
2115 * On 82571 and 82572 Fiber connections, SerDes loopback mode
2116 * persists until explicitly turned off or a power cycle is
2117 * performed. A read to the register does not indicate its status.
2118 * Therefore, we ensure loopback mode is disabled during
2119 * initialization.
2120 */
2121 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 ||
2122 hw->mac_type >= em_82575)
2123 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00024 : em_translate_82542_register
(0x00024))), (0x0400)))
;
2124
2125 if (hw->mac_type >= em_82575)
2126 em_power_up_serdes_link_82575(hw);
2127
2128 /*
2129 * On adapters with a MAC newer than 82544, SWDP 1 will be set when
2130 * the optics detect a signal. On older adapters, it will be cleared
2131 * when there is a signal. This applies to fiber media only. If
2132 * we're on serdes media, adjust the output amplitude to value set in
2133 * the EEPROM.
2134 */
2135 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
2136 if (hw->media_type == em_media_type_fiber)
2137 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN10x00080000 : 0;
2138
2139 ret_val = em_adjust_serdes_amplitude(hw);
2140 if (ret_val)
2141 return ret_val;
2142
2143 /* Take the link out of reset */
2144 ctrl &= ~(E1000_CTRL_LRST0x00000008);
2145
2146 if (hw->mac_type >= em_82575) {
2147 /* set both sw defined pins on 82575/82576*/
2148 ctrl |= E1000_CTRL_SWDPIN00x00040000 | E1000_CTRL_SWDPIN10x00080000;
2149
2150 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
2151 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) {
2152 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX0x00400000:
2153 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000:
2154 /* the backplane is always connected */
2155 reg = E1000_READ_REG(hw, PCS_LCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04208 : em_translate_82542_register
(0x04208)))))
;
2156 reg |= E1000_PCS_LCTL_FORCE_FCTRL0x80;
2157 reg |= E1000_PCS_LCTL_FSV_10004 | E1000_PCS_LCTL_FDV_FULL8;
2158 reg |= E1000_PCS_LCTL_FSD0x10; /* Force Speed */
2159 DEBUGOUT("Configuring Forced Link\n");
2160 E1000_WRITE_REG(hw, PCS_LCTL, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04208 : em_translate_82542_register
(0x04208))), (reg)))
;
2161 em_force_mac_fc(hw);
2162 hw->autoneg_failed = 0;
2163 return E1000_SUCCESS0;
2164 break;
2165 default:
2166 /* Set switch control to serdes energy detect */
2167 reg = E1000_READ_REG(hw, CONNSW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034)))))
;
2168 reg |= E1000_CONNSW_ENRGSRC0x4;
2169 E1000_WRITE_REG(hw, CONNSW, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034))), (reg)))
;
2170 break;
2171 }
2172 }
2173
2174 /* Adjust VCO speed to improve BER performance */
2175 ret_val = em_set_vco_speed(hw);
2176 if (ret_val)
2177 return ret_val;
2178
2179 em_config_collision_dist(hw);
2180 /*
2181 * Check for a software override of the flow control settings, and
2182 * setup the device accordingly. If auto-negotiation is enabled,
2183 * then software will have to set the "PAUSE" bits to the correct
2184 * value in the Tranmsit Config Word Register (TXCW) and re-start
2185 * auto-negotiation. However, if auto-negotiation is disabled, then
2186 * software will have to manually configure the two flow control
2187 * enable bits in the CTRL register.
2188 *
2189 * The possible values of the "fc" parameter are: 0: Flow control is
2190 * completely disabled 1: Rx flow control is enabled (we can receive
2191 * pause frames, but not send pause frames). 2: Tx flow control is
2192 * enabled (we can send pause frames but we do not support receiving
2193 * pause frames). 3: Both Rx and TX flow control (symmetric) are
2194 * enabled.
2195 */
2196 switch (hw->fc) {
2197 case E1000_FC_NONE0:
2198 /*
2199 * Flow control is completely disabled by a software
2200 * over-ride.
2201 */
2202 txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020);
2203 break;
2204 case E1000_FC_RX_PAUSE1:
2205 /*
2206 * RX Flow control is enabled and TX Flow control is disabled
2207 * by a software over-ride. Since there really isn't a way to
2208 * advertise that we are capable of RX Pause ONLY, we will
2209 * advertise that we support both symmetric and asymmetric RX
2210 * PAUSE. Later, we will disable the adapter's ability to
2211 * send PAUSE frames.
2212 */
2213 txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 |
2214 E1000_TXCW_PAUSE_MASK0x00000180);
2215 break;
2216 case E1000_FC_TX_PAUSE2:
2217 /*
2218 * TX Flow control is enabled, and RX Flow control is
2219 * disabled, by a software over-ride.
2220 */
2221 txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 | E1000_TXCW_ASM_DIR0x00000100);
2222 break;
2223 case E1000_FC_FULL3:
2224 /*
2225 * Flow control (both RX and TX) is enabled by a software
2226 * over-ride.
2227 */
2228 txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 |
2229 E1000_TXCW_PAUSE_MASK0x00000180);
2230 break;
2231 default:
2232 DEBUGOUT("Flow control param set incorrectly\n");
2233 return -E1000_ERR_CONFIG3;
2234 break;
2235 }
2236 /*
2237 * Since auto-negotiation is enabled, take the link out of reset (the
2238 * link will be in reset, because we previously reset the chip). This
2239 * will restart auto-negotiation. If auto-negotiation is successful
2240 * then the link-up status bit will be set and the flow control
2241 * enable bits (RFCE and TFCE) will be set according to their
2242 * negotiated value.
2243 */
2244 DEBUGOUT("Auto-negotiation enabled\n");
2245
2246 E1000_WRITE_REG(hw, TXCW, txcw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178))), (txcw)))
;
2247 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
2248 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
2249
2250 hw->txcw = txcw;
2251 msec_delay(1)(*delay_func)(1000*(1));
2252 /*
2253 * If we have a signal (the cable is plugged in) then poll for a
2254 * "Link-Up" indication in the Device Status Register. Time-out if a
2255 * link isn't seen in 500 milliseconds seconds (Auto-negotiation
2256 * should complete in less than 500 milliseconds even if the other
2257 * end is doing it in SW). For internal serdes, we just assume a
2258 * signal is present, then poll.
2259 */
2260 if (hw->media_type == em_media_type_internal_serdes ||
2261 (E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
& E1000_CTRL_SWDPIN10x00080000) == signal) {
2262 DEBUGOUT("Looking for Link\n");
2263 for (i = 0; i < (LINK_UP_TIMEOUT500 / 10); i++) {
2264 msec_delay(10)(*delay_func)(1000*(10));
2265 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
2266 if (status & E1000_STATUS_LU0x00000002)
2267 break;
2268 }
2269 if (i == (LINK_UP_TIMEOUT500 / 10)) {
2270 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2271 hw->autoneg_failed = 1;
2272 /*
2273 * AutoNeg failed to achieve a link, so we'll call
2274 * em_check_for_link. This routine will force the
2275 * link up if we detect a signal. This will allow us
2276 * to communicate with non-autonegotiating link
2277 * partners.
2278 */
2279 ret_val = em_check_for_link(hw);
2280 if (ret_val) {
2281 DEBUGOUT("Error while checking for link\n");
2282 return ret_val;
2283 }
2284 hw->autoneg_failed = 0;
2285 } else {
2286 hw->autoneg_failed = 0;
2287 DEBUGOUT("Valid Link Found\n");
2288 }
2289 } else {
2290 DEBUGOUT("No Signal Detected\n");
2291 }
2292 return E1000_SUCCESS0;
2293}
2294
2295/******************************************************************************
2296 * Make sure we have a valid PHY and change PHY mode before link setup.
2297 *
2298 * hw - Struct containing variables accessed by shared code
2299 *****************************************************************************/
2300static int32_t
2301em_copper_link_preconfig(struct em_hw *hw)
2302{
2303 uint32_t ctrl;
2304 int32_t ret_val;
2305 uint16_t phy_data;
2306 DEBUGFUNC("em_copper_link_preconfig");;
2307
2308 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
2309 /*
2310 * With 82543, we need to force speed and duplex on the MAC equal to
2311 * what the PHY speed and duplex configuration is. In addition, we
2312 * need to perform a hardware reset on the PHY to take it out of
2313 * reset.
2314 */
2315 if (hw->mac_type > em_82543) {
2316 ctrl |= E1000_CTRL_SLU0x00000040;
2317 ctrl &= ~(E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000);
2318 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
2319 } else {
2320 ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000 |
2321 E1000_CTRL_SLU0x00000040);
2322 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
2323 ret_val = em_phy_hw_reset(hw);
2324 if (ret_val)
2325 return ret_val;
2326 }
2327
2328 /* Set PHY to class A mode (if necessary) */
2329 ret_val = em_set_phy_mode(hw);
2330 if (ret_val)
2331 return ret_val;
2332
2333 if ((hw->mac_type == em_82545_rev_3) ||
2334 (hw->mac_type == em_82546_rev_3)) {
2335 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
2336 &phy_data);
2337 phy_data |= 0x00000008;
2338 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
2339 phy_data);
2340 }
2341 if (hw->mac_type <= em_82543 ||
2342 hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
2343 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
2344 hw->phy_reset_disable = FALSE0;
2345 if ((hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
2346 hw->mac_type == em_82576 ||
2347 hw->mac_type == em_i210 || hw->mac_type == em_i350) &&
2348 hw->sgmii_active) {
2349 /* allow time for SFP cage time to power up phy */
2350 msec_delay(300)(*delay_func)(1000*(300));
2351
2352 /*
2353 * SFP documentation requires the following to configure the SFP module
2354 * to work on SGMII. No further documentation is given.
2355 */
2356 em_write_phy_reg(hw, 0x1B, 0x8084);
2357 em_phy_hw_reset(hw);
2358 }
2359
2360 return E1000_SUCCESS0;
2361}
2362
2363/******************************************************************************
2364 * Copper link setup for em_phy_igp series.
2365 *
2366 * hw - Struct containing variables accessed by shared code
2367 *****************************************************************************/
2368static int32_t
2369em_copper_link_igp_setup(struct em_hw *hw)
2370{
2371 uint32_t led_ctrl;
2372 int32_t ret_val;
2373 uint16_t phy_data;
2374 DEBUGFUNC("em_copper_link_igp_setup");;
2375
2376 if (hw->phy_reset_disable)
2377 return E1000_SUCCESS0;
2378
2379 ret_val = em_phy_reset(hw);
2380 if (ret_val) {
2381 DEBUGOUT("Error Resetting the PHY\n");
2382 return ret_val;
2383 }
2384 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2385 msec_delay(15)(*delay_func)(1000*(15));
2386 if (hw->mac_type != em_ich8lan &&
2387 hw->mac_type != em_ich9lan &&
2388 hw->mac_type != em_ich10lan) {
2389 /* Configure activity LED after PHY reset */
2390 led_ctrl = E1000_READ_REG(hw, LEDCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00)))))
;
2391 led_ctrl &= IGP_ACTIVITY_LED_MASK0xFFFFF0FF;
2392 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE0x0300 | IGP_LED3_MODE0x07000000);
2393 E1000_WRITE_REG(hw, LEDCTL, led_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00))), (led_ctrl)))
;
2394 }
2395 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2396 if (hw->phy_type == em_phy_igp) {
2397 /* disable lplu d3 during driver init */
2398 ret_val = em_set_d3_lplu_state(hw, FALSE0);
2399 if (ret_val) {
2400 DEBUGOUT("Error Disabling LPLU D3\n");
2401 return ret_val;
2402 }
2403 }
2404 /* disable lplu d0 during driver init */
2405 if (hw->mac_type == em_pchlan ||
2406 hw->mac_type == em_pch2lan ||
2407 hw->mac_type == em_pch_lpt ||
2408 hw->mac_type == em_pch_spt ||
2409 hw->mac_type == em_pch_cnp)
2410 ret_val = em_set_lplu_state_pchlan(hw, FALSE0);
2411 else
2412 ret_val = em_set_d0_lplu_state(hw, FALSE0);
2413 if (ret_val) {
2414 DEBUGOUT("Error Disabling LPLU D0\n");
2415 return ret_val;
2416 }
2417 /* Configure mdi-mdix settings */
2418 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12, &phy_data);
2419 if (ret_val)
2420 return ret_val;
2421
2422 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2423 hw->dsp_config_state = em_dsp_config_disabled;
2424 /* Force MDI for earlier revs of the IGP PHY */
2425 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX0x1000 |
2426 IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000);
2427 hw->mdix = 1;
2428
2429 } else {
2430 hw->dsp_config_state = em_dsp_config_enabled;
2431 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX0x1000;
2432
2433 switch (hw->mdix) {
2434 case 1:
2435 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000;
2436 break;
2437 case 2:
2438 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000;
2439 break;
2440 case 0:
2441 default:
2442 phy_data |= IGP01E1000_PSCR_AUTO_MDIX0x1000;
2443 break;
2444 }
2445 }
2446 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12, phy_data);
2447 if (ret_val)
2448 return ret_val;
2449
2450 /* set auto-master slave resolution settings */
2451 if (hw->autoneg) {
2452 em_ms_type phy_ms_setting = hw->master_slave;
2453 if (hw->ffe_config_state == em_ffe_config_active)
2454 hw->ffe_config_state = em_ffe_config_enabled;
2455
2456 if (hw->dsp_config_state == em_dsp_config_activated)
2457 hw->dsp_config_state = em_dsp_config_enabled;
2458 /*
2459 * when autonegotiation advertisement is only 1000Mbps then
2460 * we should disable SmartSpeed and enable Auto MasterSlave
2461 * resolution as hardware default.
2462 */
2463 if (hw->autoneg_advertised == ADVERTISE_1000_FULL0x0020) {
2464 /* Disable SmartSpeed */
2465 ret_val = em_read_phy_reg(hw,
2466 IGP01E1000_PHY_PORT_CONFIG0x10, &phy_data);
2467 if (ret_val)
2468 return ret_val;
2469
2470 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED0x0080;
2471 ret_val = em_write_phy_reg(hw,
2472 IGP01E1000_PHY_PORT_CONFIG0x10, phy_data);
2473 if (ret_val)
2474 return ret_val;
2475 /* Set auto Master/Slave resolution process */
2476 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09,
2477 &phy_data);
2478 if (ret_val)
2479 return ret_val;
2480
2481 phy_data &= ~CR_1000T_MS_ENABLE0x1000;
2482 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09,
2483 phy_data);
2484 if (ret_val)
2485 return ret_val;
2486 }
2487 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09, &phy_data);
2488 if (ret_val)
2489 return ret_val;
2490
2491 /* load defaults for future use */
2492 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE0x1000) ?
2493 ((phy_data & CR_1000T_MS_VALUE0x0800) ? em_ms_force_master :
2494 em_ms_force_slave) : em_ms_auto;
2495
2496 switch (phy_ms_setting) {
2497 case em_ms_force_master:
2498 phy_data |= (CR_1000T_MS_ENABLE0x1000 | CR_1000T_MS_VALUE0x0800);
2499 break;
2500 case em_ms_force_slave:
2501 phy_data |= CR_1000T_MS_ENABLE0x1000;
2502 phy_data &= ~(CR_1000T_MS_VALUE0x0800);
2503 break;
2504 case em_ms_auto:
2505 phy_data &= ~CR_1000T_MS_ENABLE0x1000;
2506 break;
2507 default:
2508 break;
2509 }
2510 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09, phy_data);
2511 if (ret_val)
2512 return ret_val;
2513 }
2514 return E1000_SUCCESS0;
2515}
2516
2517/******************************************************************************
2518 * Copper link setup for em_phy_gg82563 series.
2519 *
2520 * hw - Struct containing variables accessed by shared code
2521 *****************************************************************************/
2522static int32_t
2523em_copper_link_ggp_setup(struct em_hw *hw)
2524{
2525 int32_t ret_val;
2526 uint16_t phy_data;
2527 uint32_t reg_data;
2528 DEBUGFUNC("em_copper_link_ggp_setup");;
2529
2530 if (!hw->phy_reset_disable) {
2531
2532 /* Enable CRS on TX for half-duplex operation. */
2533 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)),
2534 &phy_data);
2535 if (ret_val)
2536 return ret_val;
2537
2538 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX0x0010;
2539 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2540 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ0x0007;
2541
2542 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)),
2543 phy_data);
2544 if (ret_val)
2545 return ret_val;
2546 /*
2547 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1
2548 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only
2549 * (MDI-X for 10/100Base-T modes)
2550 */
2551 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL(((0) << 5) | ((16) & 0x1F)),
2552 &phy_data);
2553
2554 if (ret_val)
2555 return ret_val;
2556
2557 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK0x0060;
2558
2559 switch (hw->mdix) {
2560 case 1:
2561 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI0x0000;
2562 break;
2563 case 2:
2564 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX0x0020;
2565 break;
2566 case 0:
2567 default:
2568 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO0x0060;
2569 break;
2570 }
2571 /*
2572 * Options: disable_polarity_correction = 0 (default)
2573 * Automatic Correction for Reversed Cable Polarity 0 -
2574 * Disabled 1 - Enabled
2575 */
2576 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE0x0002;
2577 if (hw->disable_polarity_correction == 1)
2578 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE0x0002;
2579 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL(((0) << 5) | ((16) & 0x1F)),
2580 phy_data);
2581
2582 if (ret_val)
2583 return ret_val;
2584
2585 /* SW Reset the PHY so all changes take effect */
2586 ret_val = em_phy_reset(hw);
2587 if (ret_val) {
2588 DEBUGOUT("Error Resetting the PHY\n");
2589 return ret_val;
2590 }
2591 } /* phy_reset_disable */
2592 if (hw->mac_type == em_80003es2lan) {
2593 /* Bypass RX and TX FIFO's */
2594 ret_val = em_write_kmrn_reg(hw,
2595 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL0x00000000,
2596 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS0x00000008 |
2597 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS0x00000800);
2598 if (ret_val)
2599 return ret_val;
2600
2601 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2(((0) << 5) | ((26) & 0x1F)),
2602 &phy_data);
2603 if (ret_val)
2604 return ret_val;
2605
2606 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG0x2000;
2607 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2(((0) << 5) | ((26) & 0x1F)),
2608 phy_data);
2609
2610 if (ret_val)
2611 return ret_val;
2612
2613 reg_data = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))))
;
2614 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000);
2615 E1000_WRITE_REG(hw, CTRL_EXT, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (reg_data)))
;
2616
2617 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL(((193) << 5) | ((20) & 0x1F)),
2618 &phy_data);
2619 if (ret_val)
2620 return ret_val;
2621 /*
2622 * Do not init these registers when the HW is in IAMT mode,
2623 * since the firmware will have already initialized them. We
2624 * only initialize them if the HW is not in IAMT mode.
2625 */
2626 if (em_check_mng_mode(hw) == FALSE0) {
2627 /* Enable Electrical Idle on the PHY */
2628 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE0x0001;
2629 ret_val = em_write_phy_reg(hw,
2630 GG82563_PHY_PWR_MGMT_CTRL(((193) << 5) | ((20) & 0x1F)), phy_data);
2631 if (ret_val)
2632 return ret_val;
2633
2634 ret_val = em_read_phy_reg(hw,
2635 GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), &phy_data);
2636 if (ret_val)
2637 return ret_val;
2638
2639 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800;
2640 ret_val = em_write_phy_reg(hw,
2641 GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), phy_data);
2642
2643 if (ret_val)
2644 return ret_val;
2645 }
2646 /*
2647 * Workaround: Disable padding in Kumeran interface in the
2648 * MAC and in the PHY to avoid CRC errors.
2649 */
2650 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL(((194) << 5) | ((18) & 0x1F)),
2651 &phy_data);
2652 if (ret_val)
2653 return ret_val;
2654 phy_data |= GG82563_ICR_DIS_PADDING0x0010;
2655 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL(((194) << 5) | ((18) & 0x1F)),
2656 phy_data);
2657 if (ret_val)
2658 return ret_val;
2659 }
2660 return E1000_SUCCESS0;
2661}
2662
2663/******************************************************************************
2664 * Copper link setup for em_phy_m88 series.
2665 *
2666 * hw - Struct containing variables accessed by shared code
2667 *****************************************************************************/
2668static int32_t
2669em_copper_link_mgp_setup(struct em_hw *hw)
2670{
2671 int32_t ret_val;
2672 uint16_t phy_data;
2673 DEBUGFUNC("em_copper_link_mgp_setup");;
2674
2675 if (hw->phy_reset_disable)
2676 return E1000_SUCCESS0;
2677
2678 /* disable lplu d0 during driver init */
2679 if (hw->mac_type == em_pchlan ||
2680 hw->mac_type == em_pch2lan ||
2681 hw->mac_type == em_pch_lpt ||
2682 hw->mac_type == em_pch_spt ||
2683 hw->mac_type == em_pch_cnp)
2684 ret_val = em_set_lplu_state_pchlan(hw, FALSE0);
2685
2686 /* Enable CRS on TX. This must be set for half-duplex operation. */
2687 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, &phy_data);
2688 if (ret_val)
2689 return ret_val;
2690
2691 if (hw->phy_id == M88E1141_E_PHY_ID0x01410CD0) {
2692 phy_data |= 0x00000008;
2693 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
2694 phy_data);
2695 if (ret_val)
2696 return ret_val;
2697
2698 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
2699 &phy_data);
2700 if (ret_val)
2701 return ret_val;
2702
2703 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800;
2704
2705 }
2706 /* For BM PHY this bit is downshift enable */
2707 else if (hw->phy_type != em_phy_bm)
2708 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800;
2709 /*
2710 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI
2711 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for
2712 * 10/100Base-T modes)
2713 */
2714 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE0x0060;
2715
2716 switch (hw->mdix) {
2717 case 1:
2718 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE0x0000;
2719 break;
2720 case 2:
2721 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE0x0020;
2722 break;
2723 case 3:
2724 phy_data |= M88E1000_PSCR_AUTO_X_1000T0x0040;
2725 break;
2726 case 0:
2727 default:
2728 phy_data |= M88E1000_PSCR_AUTO_X_MODE0x0060;
2729 break;
2730 }
2731 /*
2732 * Options: disable_polarity_correction = 0 (default) Automatic
2733 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled
2734 */
2735 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL0x0002;
2736 if (hw->disable_polarity_correction == 1)
2737 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL0x0002;
2738
2739 /* Enable downshift on BM (disabled by default) */
2740 if (hw->phy_type == em_phy_bm)
2741 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT0x0800;
2742
2743 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, phy_data);
2744 if (ret_val)
2745 return ret_val;
2746
2747 if (((hw->phy_type == em_phy_m88) &&
2748 (hw->phy_revision < M88E1011_I_REV_40x04) &&
2749 (hw->phy_id != BME1000_E_PHY_ID0x01410CB0)) ||
2750 (hw->phy_type == em_phy_oem)) {
2751 /*
2752 * Force TX_CLK in the Extended PHY Specific Control Register
2753 * to 25MHz clock.
2754 */
2755 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
2756 &phy_data);
2757 if (ret_val)
2758 return ret_val;
2759
2760 if (hw->phy_type == em_phy_oem) {
2761 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL0x0002;
2762 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL0x0080;
2763 }
2764 phy_data |= M88E1000_EPSCR_TX_CLK_250x0070;
2765
2766 if ((hw->phy_revision == E1000_REVISION_22) &&
2767 (hw->phy_id == M88E1111_I_PHY_ID0x01410CC0)) {
2768 /* Vidalia Phy, set the downshift counter to 5x */
2769 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK0x0E00);
2770 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X0x0800;
2771 ret_val = em_write_phy_reg(hw,
2772 M88E1000_EXT_PHY_SPEC_CTRL0x14, phy_data);
2773 if (ret_val)
2774 return ret_val;
2775 } else {
2776 /* Configure Master and Slave downshift values */
2777 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK0x0C00 |
2778 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK0x0300);
2779 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X0x0000 |
2780 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X0x0100);
2781 ret_val = em_write_phy_reg(hw,
2782 M88E1000_EXT_PHY_SPEC_CTRL0x14, phy_data);
2783 if (ret_val)
2784 return ret_val;
2785 }
2786 }
2787 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
2788 /*
2789 * Set PHY page 0, register 29 to 0x0003
2790 * The next two writes are supposed to lower BER for gig
2791 * connection
2792 */
2793 ret_val = em_write_phy_reg(hw, BM_REG_BIAS129, 0x0003);
2794 if (ret_val)
2795 return ret_val;
2796
2797 /* Set PHY page 0, register 30 to 0x0000 */
2798 ret_val = em_write_phy_reg(hw, BM_REG_BIAS230, 0x0000);
2799 if (ret_val)
2800 return ret_val;
2801 }
2802 if (hw->phy_type == em_phy_82578) {
2803 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
2804 &phy_data);
2805 if (ret_val)
2806 return ret_val;
2807
2808 /* 82578 PHY - set the downshift count to 1x. */
2809 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE0x0020;
2810 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK0x001C;
2811 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
2812 phy_data);
2813 if (ret_val)
2814 return ret_val;
2815 }
2816 /* SW Reset the PHY so all changes take effect */
2817 ret_val = em_phy_reset(hw);
2818 if (ret_val) {
2819 DEBUGOUT("Error Resetting the PHY\n");
2820 return ret_val;
2821 }
2822 return E1000_SUCCESS0;
2823}
2824
2825/******************************************************************************
2826 * Copper link setup for em_phy_82577 series.
2827 *
2828 * hw - Struct containing variables accessed by shared code
2829 *****************************************************************************/
2830static int32_t
2831em_copper_link_82577_setup(struct em_hw *hw)
2832{
2833 int32_t ret_val;
2834 uint16_t phy_data;
2835 uint32_t led_ctl;
2836 DEBUGFUNC("em_copper_link_82577_setup");;
2837
2838 if (hw->phy_reset_disable)
2839 return E1000_SUCCESS0;
2840
2841 /* Enable CRS on TX for half-duplex operation. */
2842 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG22, &phy_data);
2843 if (ret_val)
2844 return ret_val;
2845
2846 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX(1 << 15) |
2847 I82577_PHY_CFG_ENABLE_DOWNSHIFT((1 << 10) + (1 << 11));
2848
2849 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG22, phy_data);
2850 if (ret_val)
2851 return ret_val;
2852
2853 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2854 msec_delay(15)(*delay_func)(1000*(15));
2855 led_ctl = hw->ledctl_mode1;
2856
2857 /* disable lplu d0 during driver init */
2858 ret_val = em_set_lplu_state_pchlan(hw, FALSE0);
2859 if (ret_val) {
2860 DEBUGOUT("Error Disabling LPLU D0\n");
2861 return ret_val;
2862 }
2863
2864 E1000_WRITE_REG(hw, LEDCTL, led_ctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00))), (led_ctl)))
;
2865
2866 return E1000_SUCCESS0;
2867}
2868
2869static int32_t
2870em_copper_link_82580_setup(struct em_hw *hw)
2871{
2872 int32_t ret_val;
2873 uint16_t phy_data;
2874
2875 if (hw->phy_reset_disable)
2876 return E1000_SUCCESS0;
2877
2878 ret_val = em_phy_reset(hw);
2879 if (ret_val)
2880 goto out;
2881
2882 /* Enable CRS on TX. This must be set for half-duplex operation. */
2883 ret_val = em_read_phy_reg(hw, I82580_CFG_REG22, &phy_data);
2884 if (ret_val)
2885 goto out;
2886
2887 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX(1 << 15) |
2888 I82580_CFG_ENABLE_DOWNSHIFT(3 << 10);
2889
2890 ret_val = em_write_phy_reg(hw, I82580_CFG_REG22, phy_data);
2891
2892out:
2893 return ret_val;
2894}
2895
2896static int32_t
2897em_copper_link_rtl8211_setup(struct em_hw *hw)
2898{
2899 int32_t ret_val;
2900 uint16_t phy_data;
2901
2902 DEBUGFUNC("em_copper_link_rtl8211_setup: begin");;
2903
2904 if (!hw) {
2905 return -1;
2906 }
2907 /* SW Reset the PHY so all changes take effect */
2908 em_phy_hw_reset(hw);
2909
2910 /* Enable CRS on TX. This must be set for half-duplex operation. */
2911 phy_data = 0;
2912
2913 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data);
2914 if (ret_val) {
2915 printf("Unable to read RGEPHY_CR register\n");
2916 return ret_val;
2917 }
2918 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id,
2919 hw->phy_addr, phy_data);
2920 phy_data |= RGEPHY_CR_ASSERT_CRS0x0800;
2921
2922 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data);
2923 if (ret_val) {
2924 printf("Unable to write RGEPHY_CR register\n");
2925 return ret_val;
2926 }
2927
2928 phy_data = 0; /* LED Control Register 0x18 */
2929 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC0x18, &phy_data);
2930 if (ret_val) {
2931 printf("Unable to read RGEPHY_LC register\n");
2932 return ret_val;
2933 }
2934
2935 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */
2936 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC0x18, phy_data);
2937 if (ret_val) {
2938 printf("Unable to write RGEPHY_LC register\n");
2939 return ret_val;
2940 }
2941 /* LED Control and Definition Register 0x11, PHY spec status reg */
2942 phy_data = 0;
2943 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR0x11, &phy_data);
2944 if (ret_val) {
2945 printf("Unable to read RGEPHY_SR register\n");
2946 return ret_val;
2947 }
2948
2949 phy_data |= 0x0010; /* LED active Low */
2950 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR0x11, phy_data);
2951 if (ret_val) {
2952 printf("Unable to write RGEPHY_SR register\n");
2953 return ret_val;
2954 }
2955
2956 phy_data = 0;
2957 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR0x11, &phy_data);
2958 if (ret_val) {
2959 printf("Unable to read RGEPHY_SR register\n");
2960 return ret_val;
2961 }
2962
2963 /* Switch to Page2 */
2964 phy_data = RGEPHY_PS_PAGE_20x0002;
2965 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS0x1F, phy_data);
2966 if (ret_val) {
2967 printf("Unable to write PHY RGEPHY_PS register\n");
2968 return ret_val;
2969 }
2970
2971 phy_data = 0x0000;
2972 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P20x1A, phy_data);
2973 if (ret_val) {
2974 printf("Unable to write RGEPHY_LC_P2 register\n");
2975 return ret_val;
2976 }
2977 usec_delay(5)(*delay_func)(5);
2978
2979
2980 /* LED Configuration Control Reg for setting for 0x1A Register */
2981 phy_data = 0;
2982 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P20x1A, &phy_data);
2983 if (ret_val) {
2984 printf("Unable to read RGEPHY_LC_P2 register\n");
2985 return ret_val;
2986 }
2987
2988 phy_data &= 0xF000;
2989 phy_data |= 0x0F24;
2990 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P20x1A, phy_data);
2991 if (ret_val) {
2992 printf("Unable to write RGEPHY_LC_P2 register\n");
2993 return ret_val;
2994 }
2995 phy_data = 0;
2996 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P20x1A, &phy_data);
2997 if (ret_val) {
2998 printf("Unable to read RGEPHY_LC_P2 register\n");
2999 return ret_val;
3000 }
3001 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data);
3002
3003
3004 /* After setting Page2, go back to Page 0 */
3005 phy_data = 0;
3006 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS0x1F, phy_data);
3007 if (ret_val) {
3008 printf("Unable to write PHY RGEPHY_PS register\n");
3009 return ret_val;
3010 }
3011
3012 /* pulse streching= 42-84ms, blink rate=84mm */
3013 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS0x2000 | RGEPHY_LC_LINK0x0008 |
3014 RGEPHY_LC_DUPLEX0x0004 | RGEPHY_LC_RX0x0002;
3015
3016 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC0x18, phy_data);
3017 if (ret_val) {
3018 printf("Unable to write RGEPHY_LC register\n");
3019 return ret_val;
3020 }
3021 return E1000_SUCCESS0;
3022}
3023
3024/******************************************************************************
3025 * Setup auto-negotiation and flow control advertisements,
3026 * and then perform auto-negotiation.
3027 *
3028 * hw - Struct containing variables accessed by shared code
3029 *****************************************************************************/
3030int32_t
3031em_copper_link_autoneg(struct em_hw *hw)
3032{
3033 int32_t ret_val;
3034 uint16_t phy_data;
3035 DEBUGFUNC("em_copper_link_autoneg");;
3036 /*
3037 * Perform some bounds checking on the hw->autoneg_advertised
3038 * parameter. If this variable is zero, then set it to the default.
3039 */
3040 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT0x002F;
3041 /*
3042 * If autoneg_advertised is zero, we assume it was not defaulted by
3043 * the calling code so we set to advertise full capability.
3044 */
3045 if (hw->autoneg_advertised == 0)
3046 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT0x002F;
3047
3048 /* IFE phy only supports 10/100 */
3049 if (hw->phy_type == em_phy_ife)
3050 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL0x000F;
3051
3052 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3053 ret_val = em_phy_setup_autoneg(hw);
3054 if (ret_val) {
3055 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3056 return ret_val;
3057 }
3058 DEBUGOUT("Restarting Auto-Neg\n");
3059 /*
3060 * Restart auto-negotiation by setting the Auto Neg Enable bit and
3061 * the Auto Neg Restart bit in the PHY control register.
3062 */
3063 ret_val = em_read_phy_reg(hw, PHY_CTRL0x00, &phy_data);
3064 if (ret_val)
3065 return ret_val;
3066
3067 phy_data |= (MII_CR_AUTO_NEG_EN0x1000 | MII_CR_RESTART_AUTO_NEG0x0200);
3068 ret_val = em_write_phy_reg(hw, PHY_CTRL0x00, phy_data);
3069 if (ret_val)
3070 return ret_val;
3071 /*
3072 * Does the user want to wait for Auto-Neg to complete here, or check
3073 * at a later time (for example, callback routine).
3074 */
3075 if (hw->wait_autoneg_complete) {
3076 ret_val = em_wait_autoneg(hw);
3077 if (ret_val) {
3078 DEBUGOUT("Error while waiting for autoneg to complete\n"
3079 );
3080 return ret_val;
3081 }
3082 }
3083 hw->get_link_status = TRUE1;
3084
3085 return E1000_SUCCESS0;
3086}
3087
3088/******************************************************************************
3089 * Config the MAC and the PHY after link is up.
3090 * 1) Set up the MAC to the current PHY speed/duplex
3091 * if we are on 82543. If we
3092 * are on newer silicon, we only need to configure
3093 * collision distance in the Transmit Control Register.
3094 * 2) Set up flow control on the MAC to that established with
3095 * the link partner.
3096 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3097 *
3098 * hw - Struct containing variables accessed by shared code
3099 *****************************************************************************/
3100int32_t
3101em_copper_link_postconfig(struct em_hw *hw)
3102{
3103 int32_t ret_val;
3104 DEBUGFUNC("em_copper_link_postconfig");;
3105
3106 if (hw->mac_type >= em_82544 &&
3107 hw->mac_type != em_icp_xxxx) {
3108 em_config_collision_dist(hw);
3109 } else {
3110 ret_val = em_config_mac_to_phy(hw);
3111 if (ret_val) {
3112 DEBUGOUT("Error configuring MAC to PHY settings\n");
3113 return ret_val;
3114 }
3115 }
3116 ret_val = em_config_fc_after_link_up(hw);
3117 if (ret_val) {
3118 DEBUGOUT("Error Configuring Flow Control\n");
3119 return ret_val;
3120 }
3121 /* Config DSP to improve Giga link quality */
3122 if (hw->phy_type == em_phy_igp) {
3123 ret_val = em_config_dsp_after_link_change(hw, TRUE1);
3124 if (ret_val) {
3125 DEBUGOUT("Error Configuring DSP after link up\n");
3126 return ret_val;
3127 }
3128 }
3129 return E1000_SUCCESS0;
3130}
3131
3132/******************************************************************************
3133 * Detects which PHY is present and setup the speed and duplex
3134 *
3135 * hw - Struct containing variables accessed by shared code
3136 *****************************************************************************/
3137static int32_t
3138em_setup_copper_link(struct em_hw *hw)
3139{
3140 int32_t ret_val;
3141 uint16_t i;
3142 uint16_t phy_data;
3143 uint16_t reg_data;
3144 DEBUGFUNC("em_setup_copper_link");;
3145
3146 switch (hw->mac_type) {
3147 case em_80003es2lan:
3148 case em_ich8lan:
3149 case em_ich9lan:
3150 case em_ich10lan:
3151 case em_pchlan:
3152 case em_pch2lan:
3153 case em_pch_lpt:
3154 case em_pch_spt:
3155 case em_pch_cnp:
3156 /*
3157 * Set the mac to wait the maximum time between each
3158 * iteration and increase the max iterations when polling the
3159 * phy; this fixes erroneous timeouts at 10Mbps.
3160 */
3161 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4)(((0x34) << 5) | ((4) & 0x1F)), 0xFFFF);
3162 if (ret_val)
3163 return ret_val;
3164 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9)(((0x34) << 5) | ((9) & 0x1F)),
3165 &reg_data);
3166 if (ret_val)
3167 return ret_val;
3168 reg_data |= 0x3F;
3169 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9)(((0x34) << 5) | ((9) & 0x1F)),
3170 reg_data);
3171 if (ret_val)
3172 return ret_val;
3173 default:
3174 break;
3175 }
3176
3177 /* Check if it is a valid PHY and set PHY mode if necessary. */
3178 ret_val = em_copper_link_preconfig(hw);
3179 if (ret_val)
3180 return ret_val;
3181
3182 switch (hw->mac_type) {
3183 case em_80003es2lan:
3184 /* Kumeran registers are written-only */
3185 reg_data =
3186 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT0x00000500;
3187 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING0x00000010;
3188 ret_val = em_write_kmrn_reg(hw,
3189 E1000_KUMCTRLSTA_OFFSET_INB_CTRL0x00000002, reg_data);
3190 if (ret_val)
3191 return ret_val;
3192 break;
3193 default:
3194 break;
3195 }
3196
3197 if (hw->phy_type == em_phy_igp ||
3198 hw->phy_type == em_phy_igp_3 ||
3199 hw->phy_type == em_phy_igp_2) {
3200 ret_val = em_copper_link_igp_setup(hw);
3201 if (ret_val)
3202 return ret_val;
3203 } else if (hw->phy_type == em_phy_m88 ||
3204 hw->phy_type == em_phy_bm ||
3205 hw->phy_type == em_phy_oem ||
3206 hw->phy_type == em_phy_82578) {
3207 ret_val = em_copper_link_mgp_setup(hw);
3208 if (ret_val)
3209 return ret_val;
3210 } else if (hw->phy_type == em_phy_gg82563) {
3211 ret_val = em_copper_link_ggp_setup(hw);
3212 if (ret_val)
3213 return ret_val;
3214 } else if (hw->phy_type == em_phy_82577 ||
3215 hw->phy_type == em_phy_82579 ||
3216 hw->phy_type == em_phy_i217) {
3217 ret_val = em_copper_link_82577_setup(hw);
3218 if (ret_val)
3219 return ret_val;
3220 } else if (hw->phy_type == em_phy_82580) {
3221 ret_val = em_copper_link_82580_setup(hw);
3222 if (ret_val)
3223 return ret_val;
3224 } else if (hw->phy_type == em_phy_rtl8211) {
3225 ret_val = em_copper_link_rtl8211_setup(hw);
3226 if (ret_val)
3227 return ret_val;
3228 }
3229 if (hw->autoneg) {
3230 /*
3231 * Setup autoneg and flow control advertisement and perform
3232 * autonegotiation
3233 */
3234 ret_val = em_copper_link_autoneg(hw);
3235 if (ret_val)
3236 return ret_val;
3237 } else {
3238 /*
3239 * PHY will be set to 10H, 10F, 100H,or 100F depending on
3240 * value from forced_speed_duplex.
3241 */
3242 DEBUGOUT("Forcing speed and duplex\n");
3243 ret_val = em_phy_force_speed_duplex(hw);
3244 if (ret_val) {
3245 DEBUGOUT("Error Forcing Speed and Duplex\n");
3246 return ret_val;
3247 }
3248 }
3249 /*
3250 * Check link status. Wait up to 100 microseconds for link to become
3251 * valid.
3252 */
3253 for (i = 0; i < 10; i++) {
3254 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
3255 if (ret_val)
3256 return ret_val;
3257 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
3258 if (ret_val)
3259 return ret_val;
3260
3261 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS0x0004) != 0;
3262
3263 if (phy_data & MII_SR_LINK_STATUS0x0004) {
3264 /* Config the MAC and PHY after link is up */
3265 ret_val = em_copper_link_postconfig(hw);
3266 if (ret_val)
3267 return ret_val;
3268
3269 DEBUGOUT("Valid link established!!!\n");
3270 return E1000_SUCCESS0;
3271 }
3272 usec_delay(10)(*delay_func)(10);
3273 }
3274
3275 DEBUGOUT("Unable to establish link!!!\n");
3276 return E1000_SUCCESS0;
3277}
3278
3279/******************************************************************************
3280 * Configure the MAC-to-PHY interface for 10/100Mbps
3281 *
3282 * hw - Struct containing variables accessed by shared code
3283 *****************************************************************************/
3284static int32_t
3285em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex)
3286{
3287 int32_t ret_val = E1000_SUCCESS0;
3288 uint32_t tipg;
3289 uint16_t reg_data;
3290 DEBUGFUNC("em_configure_kmrn_for_10_100");;
3291
3292 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT0x00000004;
3293 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL0x00000010,
3294 reg_data);
3295 if (ret_val)
3296 return ret_val;
3297
3298 /* Configure Transmit Inter-Packet Gap */
3299 tipg = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410)))))
;
3300 tipg &= ~E1000_TIPG_IPGT_MASK0x000003FF;
3301 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_1000x00000009;
3302 E1000_WRITE_REG(hw, TIPG, tipg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410))), (tipg)))
;
3303
3304 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), &reg_data);
3305
3306 if (ret_val)
3307 return ret_val;
3308
3309 if (duplex == HALF_DUPLEX1)
3310 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER0x0800;
3311 else
3312 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800;
3313
3314 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), reg_data);
3315
3316 return ret_val;
3317}
3318
3319static int32_t
3320em_configure_kmrn_for_1000(struct em_hw *hw)
3321{
3322 int32_t ret_val = E1000_SUCCESS0;
3323 uint16_t reg_data;
3324 uint32_t tipg;
3325 DEBUGFUNC("em_configure_kmrn_for_1000");;
3326
3327 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT0x00000000;
3328 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL0x00000010,
3329 reg_data);
3330 if (ret_val)
3331 return ret_val;
3332
3333 /* Configure Transmit Inter-Packet Gap */
3334 tipg = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410)))))
;
3335 tipg &= ~E1000_TIPG_IPGT_MASK0x000003FF;
3336 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10000x00000008;
3337 E1000_WRITE_REG(hw, TIPG, tipg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410))), (tipg)))
;
3338
3339 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), &reg_data);
3340
3341 if (ret_val)
3342 return ret_val;
3343
3344 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800;
3345 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), reg_data);
3346
3347 return ret_val;
3348}
3349
3350/******************************************************************************
3351 * Configures PHY autoneg and flow control advertisement settings
3352 *
3353 * hw - Struct containing variables accessed by shared code
3354 *****************************************************************************/
3355int32_t
3356em_phy_setup_autoneg(struct em_hw *hw)
3357{
3358 int32_t ret_val;
3359 uint16_t mii_autoneg_adv_reg;
3360 uint16_t mii_1000t_ctrl_reg;
3361 DEBUGFUNC("em_phy_setup_autoneg");;
3362
3363 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3364 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV0x04, &mii_autoneg_adv_reg);
3365 if (ret_val)
3366 return ret_val;
3367
3368 if (hw->phy_type != em_phy_ife) {
3369 /* Read the MII 1000Base-T Control Register (Address 9). */
3370 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09,
3371 &mii_1000t_ctrl_reg);
3372 if (ret_val)
3373 return ret_val;
3374 } else
3375 mii_1000t_ctrl_reg = 0;
3376 /*
3377 * Need to parse both autoneg_advertised and fc and set up the
3378 * appropriate PHY registers. First we will parse for
3379 * autoneg_advertised software override. Since we can advertise a
3380 * plethora of combinations, we need to check each bit individually.
3381 */
3382 /*
3383 * First we clear all the 10/100 mb speed bits in the Auto-Neg
3384 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3385 * the 1000Base-T Control Register (Address 9).
3386 */
3387 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK0x01E0;
3388 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK0x0300;
3389
3390 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
3391
3392 /* Do we want to advertise 10 Mb Half Duplex? */
3393 if (hw->autoneg_advertised & ADVERTISE_10_HALF0x0001) {
3394 DEBUGOUT("Advertise 10mb Half duplex\n");
3395 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS0x0020;
3396 }
3397 /* Do we want to advertise 10 Mb Full Duplex? */
3398 if (hw->autoneg_advertised & ADVERTISE_10_FULL0x0002) {
3399 DEBUGOUT("Advertise 10mb Full duplex\n");
3400 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS0x0040;
3401 }
3402 /* Do we want to advertise 100 Mb Half Duplex? */
3403 if (hw->autoneg_advertised & ADVERTISE_100_HALF0x0004) {
3404 DEBUGOUT("Advertise 100mb Half duplex\n");
3405 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS0x0080;
3406 }
3407 /* Do we want to advertise 100 Mb Full Duplex? */
3408 if (hw->autoneg_advertised & ADVERTISE_100_FULL0x0008) {
3409 DEBUGOUT("Advertise 100mb Full duplex\n");
3410 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS0x0100;
3411 }
3412 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3413 if (hw->autoneg_advertised & ADVERTISE_1000_HALF0x0010) {
3414 DEBUGOUT("Advertise 1000mb Half duplex requested, request"
3415 " denied!\n");
3416 }
3417 /* Do we want to advertise 1000 Mb Full Duplex? */
3418 if (hw->autoneg_advertised & ADVERTISE_1000_FULL0x0020) {
3419 DEBUGOUT("Advertise 1000mb Full duplex\n");
3420 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS0x0200;
3421 if (hw->phy_type == em_phy_ife) {
3422 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is"
3423 " not supported.\n");
3424 }
3425 }
3426 /*
3427 * Check for a software override of the flow control settings, and
3428 * setup the PHY advertisement registers accordingly. If
3429 * auto-negotiation is enabled, then software will have to set the
3430 * "PAUSE" bits to the correct value in the Auto-Negotiation
3431 * Advertisement Register (PHY_AUTONEG_ADV) and re-start
3432 * auto-negotiation.
3433 *
3434 * The possible values of the "fc" parameter are: 0: Flow control is
3435 * completely disabled 1: Rx flow control is enabled (we can receive
3436 * pause frames but not send pause frames). 2: Tx flow control is
3437 * enabled (we can send pause frames but we do not support receiving
3438 * pause frames). 3: Both Rx and TX flow control (symmetric) are
3439 * enabled. other: No software override. The flow control
3440 * configuration in the EEPROM is used.
3441 */
3442 switch (hw->fc) {
3443 case E1000_FC_NONE0: /* 0 */
3444 /*
3445 * Flow control (RX & TX) is completely disabled by a
3446 * software over-ride.
3447 */
3448 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
3449 break;
3450 case E1000_FC_RX_PAUSE1:/* 1 */
3451 /*
3452 * RX Flow control is enabled, and TX Flow control is
3453 * disabled, by a software over-ride.
3454 */
3455 /*
3456 * Since there really isn't a way to advertise that we are
3457 * capable of RX Pause ONLY, we will advertise that we
3458 * support both symmetric and asymmetric RX PAUSE. Later (in
3459 * em_config_fc_after_link_up) we will disable the hw's
3460 * ability to send PAUSE frames.
3461 */
3462 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
3463 break;
3464 case E1000_FC_TX_PAUSE2:/* 2 */
3465 /*
3466 * TX Flow control is enabled, and RX Flow control is
3467 * disabled, by a software over-ride.
3468 */
3469 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR0x0800;
3470 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE0x0400;
3471 break;
3472 case E1000_FC_FULL3: /* 3 */
3473 /*
3474 * Flow control (both RX and TX) is enabled by a software
3475 * over-ride.
3476 */
3477 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
3478 break;
3479 default:
3480 DEBUGOUT("Flow control param set incorrectly\n");
3481 return -E1000_ERR_CONFIG3;
3482 }
3483
3484 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV0x04, mii_autoneg_adv_reg);
3485 if (ret_val)
3486 return ret_val;
3487
3488 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3489
3490 if (hw->phy_type != em_phy_ife) {
3491 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09,
3492 mii_1000t_ctrl_reg);
3493 if (ret_val)
3494 return ret_val;
3495 }
3496 return E1000_SUCCESS0;
3497}
3498/******************************************************************************
3499 * Force PHY speed and duplex settings to hw->forced_speed_duplex
3500 *
3501 * hw - Struct containing variables accessed by shared code
3502 *****************************************************************************/
3503static int32_t
3504em_phy_force_speed_duplex(struct em_hw *hw)
3505{
3506 uint32_t ctrl;
3507 int32_t ret_val;
3508 uint16_t mii_ctrl_reg;
3509 uint16_t mii_status_reg;
3510 uint16_t phy_data;
3511 uint16_t i;
3512 DEBUGFUNC("em_phy_force_speed_duplex");;
3513
3514 /* Turn off Flow control if we are forcing speed and duplex. */
3515 hw->fc = E1000_FC_NONE0;
3516
3517 DEBUGOUT1("hw->fc = %d\n", hw->fc);
3518
3519 /* Read the Device Control Register. */
3520 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
3521
3522 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
3523 ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000);
3524 ctrl &= ~(DEVICE_SPEED_MASK0x00000300);
3525
3526 /* Clear the Auto Speed Detect Enable bit. */
3527 ctrl &= ~E1000_CTRL_ASDE0x00000020;
3528
3529 /* Read the MII Control Register. */
3530 ret_val = em_read_phy_reg(hw, PHY_CTRL0x00, &mii_ctrl_reg);
3531 if (ret_val)
3532 return ret_val;
3533
3534 /* We need to disable autoneg in order to force link and duplex. */
3535
3536 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN0x1000;
3537
3538 /* Are we forcing Full or Half Duplex? */
3539 if (hw->forced_speed_duplex == em_100_full ||
3540 hw->forced_speed_duplex == em_10_full) {
3541 /*
3542 * We want to force full duplex so we SET the full duplex
3543 * bits in the Device and MII Control Registers.
3544 */
3545 ctrl |= E1000_CTRL_FD0x00000001;
3546 mii_ctrl_reg |= MII_CR_FULL_DUPLEX0x0100;
3547 DEBUGOUT("Full Duplex\n");
3548 } else {
3549 /*
3550 * We want to force half duplex so we CLEAR the full duplex
3551 * bits in the Device and MII Control Registers.
3552 */
3553 ctrl &= ~E1000_CTRL_FD0x00000001;
3554 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX0x0100;
3555 DEBUGOUT("Half Duplex\n");
3556 }
3557
3558 /* Are we forcing 100Mbps??? */
3559 if (hw->forced_speed_duplex == em_100_full ||
3560 hw->forced_speed_duplex == em_100_half) {
3561 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
3562 ctrl |= E1000_CTRL_SPD_1000x00000100;
3563 mii_ctrl_reg |= MII_CR_SPEED_1000x2000;
3564 mii_ctrl_reg &= ~(MII_CR_SPEED_10000x0040 | MII_CR_SPEED_100x0000);
3565 DEBUGOUT("Forcing 100mb ");
3566 } else {
3567 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
3568 ctrl &= ~(E1000_CTRL_SPD_10000x00000200 | E1000_CTRL_SPD_1000x00000100);
3569 mii_ctrl_reg |= MII_CR_SPEED_100x0000;
3570 mii_ctrl_reg &= ~(MII_CR_SPEED_10000x0040 | MII_CR_SPEED_1000x2000);
3571 DEBUGOUT("Forcing 10mb ");
3572 }
3573
3574 em_config_collision_dist(hw);
3575
3576 /* Write the configured values back to the Device Control Reg. */
3577 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
3578
3579 if ((hw->phy_type == em_phy_m88) ||
3580 (hw->phy_type == em_phy_gg82563) ||
3581 (hw->phy_type == em_phy_bm) ||
3582 (hw->phy_type == em_phy_oem ||
3583 (hw->phy_type == em_phy_82578))) {
3584 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
3585 &phy_data);
3586 if (ret_val)
3587 return ret_val;
3588 /*
3589 * Clear Auto-Crossover to force MDI manually. M88E1000
3590 * requires MDI forced whenever speed are duplex are forced.
3591 */
3592 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE0x0060;
3593 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
3594 phy_data);
3595 if (ret_val)
3596 return ret_val;
3597
3598 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
3599
3600 /* Need to reset the PHY or these changes will be ignored */
3601 mii_ctrl_reg |= MII_CR_RESET0x8000;
3602
3603 }
3604 else if (hw->phy_type == em_phy_rtl8211) {
3605 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data);
3606 if(ret_val) {
3607 printf("Unable to read RGEPHY_CR register\n"
3608 );
3609 return ret_val;
3610 }
3611
3612 /*
3613 * Clear Auto-Crossover to force MDI manually. RTL8211 requires
3614 * MDI forced whenever speed are duplex are forced.
3615 */
3616
3617 phy_data |= RGEPHY_CR_MDI_MASK0x0060; // enable MDIX
3618 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data);
3619 if(ret_val) {
3620 printf("Unable to write RGEPHY_CR register\n");
3621 return ret_val;
3622 }
3623 mii_ctrl_reg |= MII_CR_RESET0x8000;
3624
3625 }
3626 /* Disable MDI-X support for 10/100 */
3627 else if (hw->phy_type == em_phy_ife) {
3628 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL0x1C, &phy_data);
3629 if (ret_val)
3630 return ret_val;
3631
3632 phy_data &= ~IFE_PMC_AUTO_MDIX0x0080;
3633 phy_data &= ~IFE_PMC_FORCE_MDIX0x0040;
3634
3635 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL0x1C, phy_data);
3636 if (ret_val)
3637 return ret_val;
3638 } else {
3639 /*
3640 * Clear Auto-Crossover to force MDI manually. IGP requires
3641 * MDI forced whenever speed or duplex are forced.
3642 */
3643 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12,
3644 &phy_data);
3645 if (ret_val)
3646 return ret_val;
3647
3648 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX0x1000;
3649 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000;
3650
3651 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12,
3652 phy_data);
3653 if (ret_val)
3654 return ret_val;
3655 }
3656
3657 /* Write back the modified PHY MII control register. */
3658 ret_val = em_write_phy_reg(hw, PHY_CTRL0x00, mii_ctrl_reg);
3659 if (ret_val)
3660 return ret_val;
3661
3662 usec_delay(1)(*delay_func)(1);
3663 /*
3664 * The wait_autoneg_complete flag may be a little misleading here.
3665 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
3666 * But we do want to delay for a period while forcing only so we
3667 * don't generate false No Link messages. So we will wait here only
3668 * if the user has set wait_autoneg_complete to 1, which is the
3669 * default.
3670 */
3671 if (hw->wait_autoneg_complete) {
3672 /* We will wait for autoneg to complete. */
3673 DEBUGOUT("Waiting for forced speed/duplex link.\n");
3674 mii_status_reg = 0;
3675 /*
3676 * We will wait for autoneg to complete or 4.5 seconds to
3677 * expire.
3678 */
3679 for (i = PHY_FORCE_TIME20; i > 0; i--) {
3680 /*
3681 * Read the MII Status Register and wait for Auto-Neg
3682 * Complete bit to be set.
3683 */
3684 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01,
3685 &mii_status_reg);
3686 if (ret_val)
3687 return ret_val;
3688
3689 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01,
3690 &mii_status_reg);
3691 if (ret_val)
3692 return ret_val;
3693
3694 if (mii_status_reg & MII_SR_LINK_STATUS0x0004)
3695 break;
3696 msec_delay(100)(*delay_func)(1000*(100));
3697 }
3698 if ((i == 0) &&
3699 ((hw->phy_type == em_phy_m88) ||
3700 (hw->phy_type == em_phy_gg82563) ||
3701 (hw->phy_type == em_phy_bm))) {
3702 /*
3703 * We didn't get link. Reset the DSP and wait again
3704 * for link.
3705 */
3706 ret_val = em_phy_reset_dsp(hw);
3707 if (ret_val) {
3708 DEBUGOUT("Error Resetting PHY DSP\n");
3709 return ret_val;
3710 }
3711 }
3712 /*
3713 * This loop will early-out if the link condition has been
3714 * met.
3715 */
3716 for (i = PHY_FORCE_TIME20; i > 0; i--) {
3717 if (mii_status_reg & MII_SR_LINK_STATUS0x0004)
3718 break;
3719 msec_delay(100)(*delay_func)(1000*(100));
3720 /*
3721 * Read the MII Status Register and wait for Auto-Neg
3722 * Complete bit to be set.
3723 */
3724 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01,
3725 &mii_status_reg);
3726 if (ret_val)
3727 return ret_val;
3728
3729 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01,
3730 &mii_status_reg);
3731 if (ret_val)
3732 return ret_val;
3733 }
3734 }
3735 if (hw->phy_type == em_phy_m88 ||
3736 hw->phy_type == em_phy_bm ||
3737 hw->phy_type == em_phy_oem) {
3738 /*
3739 * Because we reset the PHY above, we need to re-force TX_CLK
3740 * in the Extended PHY Specific Control Register to 25MHz
3741 * clock. This value defaults back to a 2.5MHz clock when
3742 * the PHY is reset.
3743 */
3744 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
3745 &phy_data);
3746 if (ret_val)
3747 return ret_val;
3748
3749 phy_data |= M88E1000_EPSCR_TX_CLK_250x0070;
3750 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
3751 phy_data);
3752 if (ret_val)
3753 return ret_val;
3754 /*
3755 * In addition, because of the s/w reset above, we need to
3756 * enable CRS on TX. This must be set for both full and half
3757 * duplex operation.
3758 */
3759 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
3760 &phy_data);
3761 if (ret_val)
3762 return ret_val;
3763
3764 if (hw->phy_id == M88E1141_E_PHY_ID0x01410CD0)
3765 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800;
3766 else
3767 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800;
3768
3769 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
3770 phy_data);
3771 if (ret_val)
3772 return ret_val;
3773
3774 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
3775 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full ||
3776 hw->forced_speed_duplex == em_10_half)) {
3777 ret_val = em_polarity_reversal_workaround(hw);
3778 if (ret_val)
3779 return ret_val;
3780 }
3781 } else if (hw->phy_type == em_phy_rtl8211) {
3782 /*
3783 * In addition, because of the s/w reset above, we need to enable
3784 * CRX on TX. This must be set for both full and half duplex
3785 * operation.
3786 */
3787
3788 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data);
3789 if(ret_val) {
3790 printf("Unable to read RGEPHY_CR register\n");
3791 return ret_val;
3792 }
3793
3794 phy_data &= ~RGEPHY_CR_ASSERT_CRS0x0800;
3795 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data);
3796 if(ret_val) {
3797 printf("Unable to write RGEPHY_CR register\n");
3798 return ret_val;
3799 }
3800 } else if (hw->phy_type == em_phy_gg82563) {
3801 /*
3802 * The TX_CLK of the Extended PHY Specific Control Register
3803 * defaults to 2.5MHz on a reset. We need to re-force it
3804 * back to 25MHz, if we're not in a forced 10/duplex
3805 * configuration.
3806 */
3807 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)),
3808 &phy_data);
3809 if (ret_val)
3810 return ret_val;
3811
3812 phy_data &= ~GG82563_MSCR_TX_CLK_MASK0x0007;
3813 if ((hw->forced_speed_duplex == em_10_full) ||
3814 (hw->forced_speed_duplex == em_10_half))
3815 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ0x0004;
3816 else
3817 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ0x0005;
3818
3819 /* Also due to the reset, we need to enable CRS on Tx. */
3820 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX0x0010;
3821
3822 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)),
3823 phy_data);
3824 if (ret_val)
3825 return ret_val;
3826 }
3827 return E1000_SUCCESS0;
3828}
3829
3830/******************************************************************************
3831 * Sets the collision distance in the Transmit Control register
3832 *
3833 * hw - Struct containing variables accessed by shared code
3834 *
3835 * Link should have been established previously. Reads the speed and duplex
3836 * information from the Device Status register.
3837 *****************************************************************************/
3838void
3839em_config_collision_dist(struct em_hw *hw)
3840{
3841 uint32_t tctl, coll_dist;
3842 DEBUGFUNC("em_config_collision_dist");;
3843
3844 if (hw->mac_type < em_82543)
3845 coll_dist = E1000_COLLISION_DISTANCE_8254264;
3846 else
3847 coll_dist = E1000_COLLISION_DISTANCE63;
3848
3849 tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))))
;
3850
3851 tctl &= ~E1000_TCTL_COLD0x003ff000;
3852 tctl |= coll_dist << E1000_COLD_SHIFT12;
3853
3854 E1000_WRITE_REG(hw, TCTL, tctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400))), (tctl)))
;
3855 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
3856}
3857
3858/******************************************************************************
3859 * Sets MAC speed and duplex settings to reflect the those in the PHY
3860 *
3861 * hw - Struct containing variables accessed by shared code
3862 * mii_reg - data to write to the MII control register
3863 *
3864 * The contents of the PHY register containing the needed information need to
3865 * be passed in.
3866 *****************************************************************************/
3867static int32_t
3868em_config_mac_to_phy(struct em_hw *hw)
3869{
3870 uint32_t ctrl;
3871 int32_t ret_val;
3872 uint16_t phy_data;
3873 DEBUGFUNC("em_config_mac_to_phy");;
3874 /*
3875 * 82544 or newer MAC, Auto Speed Detection takes care of MAC
3876 * speed/duplex configuration.
3877 */
3878 if (hw->mac_type >= em_82544
3879 && hw->mac_type != em_icp_xxxx)
3880 return E1000_SUCCESS0;
3881 /*
3882 * Read the Device Control Register and set the bits to Force Speed
3883 * and Duplex.
3884 */
3885 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
3886 ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000);
3887 ctrl &= ~(E1000_CTRL_SPD_SEL0x00000300 | E1000_CTRL_ILOS0x00000080);
3888 /*
3889 * Set up duplex in the Device Control and Transmit Control registers
3890 * depending on negotiated values.
3891 */
3892 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS0x11, &phy_data);
3893 if (ret_val)
3894 return ret_val;
3895
3896 if (phy_data & M88E1000_PSSR_DPLX0x2000)
3897 ctrl |= E1000_CTRL_FD0x00000001;
3898 else
3899 ctrl &= ~E1000_CTRL_FD0x00000001;
3900
3901 em_config_collision_dist(hw);
3902 /*
3903 * Set up speed in the Device Control register depending on
3904 * negotiated values.
3905 */
3906 if ((phy_data & M88E1000_PSSR_SPEED0xC000) == M88E1000_PSSR_1000MBS0x8000)
3907 ctrl |= E1000_CTRL_SPD_10000x00000200;
3908 else if ((phy_data & M88E1000_PSSR_SPEED0xC000) == M88E1000_PSSR_100MBS0x4000)
3909 ctrl |= E1000_CTRL_SPD_1000x00000100;
3910
3911 /* Write the configured values back to the Device Control Reg. */
3912 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
3913 return E1000_SUCCESS0;
3914}
3915
3916/******************************************************************************
3917 * Forces the MAC's flow control settings.
3918 *
3919 * hw - Struct containing variables accessed by shared code
3920 *
3921 * Sets the TFCE and RFCE bits in the device control register to reflect
3922 * the adapter settings. TFCE and RFCE need to be explicitly set by
3923 * software when a Copper PHY is used because autonegotiation is managed
3924 * by the PHY rather than the MAC. Software must also configure these
3925 * bits when link is forced on a fiber connection.
3926 *****************************************************************************/
3927int32_t
3928em_force_mac_fc(struct em_hw *hw)
3929{
3930 uint32_t ctrl;
3931 DEBUGFUNC("em_force_mac_fc");;
3932
3933 /* Get the current configuration of the Device Control Register */
3934 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
3935 /*
3936 * Because we didn't get link via the internal auto-negotiation
3937 * mechanism (we either forced link or we got link via PHY auto-neg),
3938 * we have to manually enable/disable transmit an receive flow
3939 * control.
3940 *
3941 * The "Case" statement below enables/disable flow control according to
3942 * the "hw->fc" parameter.
3943 *
3944 * The possible values of the "fc" parameter are: 0: Flow control is
3945 * completely disabled 1: Rx flow control is enabled (we can receive
3946 * pause frames but not send pause frames). 2: Tx flow control is
3947 * enabled (we can send pause frames frames but we do not receive
3948 * pause frames). 3: Both Rx and TX flow control (symmetric) is
3949 * enabled. other: No other values should be possible at this point.
3950 */
3951
3952 switch (hw->fc) {
3953 case E1000_FC_NONE0:
3954 ctrl &= (~(E1000_CTRL_TFCE0x10000000 | E1000_CTRL_RFCE0x08000000));
3955 break;
3956 case E1000_FC_RX_PAUSE1:
3957 ctrl &= (~E1000_CTRL_TFCE0x10000000);
3958 ctrl |= E1000_CTRL_RFCE0x08000000;
3959 break;
3960 case E1000_FC_TX_PAUSE2:
3961 ctrl &= (~E1000_CTRL_RFCE0x08000000);
3962 ctrl |= E1000_CTRL_TFCE0x10000000;
3963 break;
3964 case E1000_FC_FULL3:
3965 ctrl |= (E1000_CTRL_TFCE0x10000000 | E1000_CTRL_RFCE0x08000000);
3966 break;
3967 default:
3968 DEBUGOUT("Flow control param set incorrectly\n");
3969 return -E1000_ERR_CONFIG3;
3970 }
3971
3972 /* Disable TX Flow Control for 82542 (rev 2.0) */
3973 if (hw->mac_type == em_82542_rev2_0)
3974 ctrl &= (~E1000_CTRL_TFCE0x10000000);
3975
3976 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
3977 return E1000_SUCCESS0;
3978}
3979/******************************************************************************
3980 * Configures flow control settings after link is established
3981 *
3982 * hw - Struct containing variables accessed by shared code
3983 *
3984 * Should be called immediately after a valid link has been established.
3985 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3986 * and autonegotiation is enabled, the MAC flow control settings will be set
3987 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3988 * and RFCE bits will be automatically set to the negotiated flow control mode.
3989 *****************************************************************************/
3990STATIC int32_t
3991em_config_fc_after_link_up(struct em_hw *hw)
3992{
3993 int32_t ret_val;
3994 uint16_t mii_status_reg;
3995 uint16_t mii_nway_adv_reg;
3996 uint16_t mii_nway_lp_ability_reg;
3997 uint16_t speed;
3998 uint16_t duplex;
3999 DEBUGFUNC("em_config_fc_after_link_up");;
4000 /*
4001 * Check for the case where we have fiber media and auto-neg failed
4002 * so we had to force link. In this case, we need to force the
4003 * configuration of the MAC to match the "fc" parameter.
4004 */
4005 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed))
4006 || ((hw->media_type == em_media_type_internal_serdes) &&
4007 (hw->autoneg_failed)) ||
4008 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) ||
4009 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) {
4010 ret_val = em_force_mac_fc(hw);
4011 if (ret_val) {
4012 DEBUGOUT("Error forcing flow control settings\n");
4013 return ret_val;
4014 }
4015 }
4016 /*
4017 * Check for the case where we have copper media and auto-neg is
4018 * enabled. In this case, we need to check and see if Auto-Neg has
4019 * completed, and if so, how the PHY and link partner has flow
4020 * control configured.
4021 */
4022 if ((hw->media_type == em_media_type_copper ||
4023 (hw->media_type == em_media_type_oem)) &&
4024 hw->autoneg) {
4025 /*
4026 * Read the MII Status Register and check to see if AutoNeg
4027 * has completed. We read this twice because this reg has
4028 * some "sticky" (latched) bits.
4029 */
4030 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg);
4031 if (ret_val)
4032 return ret_val;
4033 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg);
4034 if (ret_val)
4035 return ret_val;
4036
4037 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE0x0020) {
4038 /*
4039 * The AutoNeg process has completed, so we now need
4040 * to read both the Auto Negotiation Advertisement
4041 * Register (Address 4) and the Auto_Negotiation Base
4042 * Page Ability Register (Address 5) to determine how
4043 * flow control was negotiated.
4044 */
4045 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV0x04,
4046 &mii_nway_adv_reg);
4047 if (ret_val)
4048 return ret_val;
4049 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY0x05,
4050 &mii_nway_lp_ability_reg);
4051 if (ret_val)
4052 return ret_val;
4053 /*
4054 * Two bits in the Auto Negotiation Advertisement
4055 * Register (Address 4) and two bits in the Auto
4056 * Negotiation Base Page Ability Register (Address 5)
4057 * determine flow control for both the PHY and the
4058 * link partner. The following table, taken out of
4059 * the IEEE 802.3ab/D6.0 dated March 25, 1999,
4060 * describes these PAUSE resolution bits and how flow
4061 * control is determined based upon these settings.
4062 * NOTE: DC = Don't Care
4063 *
4064 * LOCAL DEVICE | LINK PARTNER |
4065 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
4066 * -------|---------|-------|---------|---------------
4067 * 0 | 0 | DC | DC | em_fc_none
4068 * 0 | 1 | 0 | DC | em_fc_none
4069 * 0 | 1 | 1 | 0 | em_fc_none
4070 * 0 | 1 | 1 | 1 | em_fc_tx_pause
4071 * 1 | 0 | 0 | DC | em_fc_none
4072 * 1 | DC | 1 | DC | em_fc_full
4073 * 1 | 1 | 0 | 0 | em_fc_none
4074 * 1 | 1 | 0 | 1 | em_fc_rx_pause
4075 *
4076 */
4077 /*
4078 * Are both PAUSE bits set to 1? If so, this implies
4079 * Symmetric Flow Control is enabled at both ends.
4080 * The ASM_DIR bits are irrelevant per the spec.
4081 *
4082 * For Symmetric Flow Control:
4083 *
4084 * LOCAL DEVICE | LINK PARTNER
4085 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
4086 * -------|---------|-------|---------|---------------
4087 * 1 | DC | 1 | DC | em_fc_full
4088 *
4089 */
4090 if ((mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) &&
4091 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400)) {
4092 /*
4093 * Now we need to check if the user selected
4094 * RX ONLY of pause frames. In this case, we
4095 * had to advertise FULL flow control because
4096 * we could not advertise RX ONLY. Hence, we
4097 * must now check to see if we need to turn
4098 * OFF the TRANSMISSION of PAUSE frames.
4099 */
4100 if (hw->original_fc == E1000_FC_FULL3) {
4101 hw->fc = E1000_FC_FULL3;
4102 DEBUGOUT("Flow Control = FULL.\n");
4103 } else {
4104 hw->fc = E1000_FC_RX_PAUSE1;
4105 DEBUGOUT("Flow Control = RX PAUSE"
4106 " frames only.\n");
4107 }
4108 }
4109 /*
4110 * For receiving PAUSE frames ONLY.
4111 *
4112 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR |
4113 * PAUSE | ASM_DIR | Result
4114 * -------|---------|-------|---------|---------------
4115 * ----- 0 | 1 | 1 | 1 |
4116 * em_fc_tx_pause
4117 *
4118 */
4119 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) &&
4120 (mii_nway_adv_reg & NWAY_AR_ASM_DIR0x0800) &&
4121 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400) &&
4122 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR0x0800)) {
4123 hw->fc = E1000_FC_TX_PAUSE2;
4124 DEBUGOUT("Flow Control = TX PAUSE frames only."
4125 "\n");
4126 }
4127 /*
4128 * For transmitting PAUSE frames ONLY.
4129 *
4130 * LOCAL DEVICE | LINK PARTNER
4131 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
4132 * -------|---------|-------|---------|---------------
4133 * 1 | 1 | 0 | 1 | em_fc_rx_pause
4134 *
4135 */
4136 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) &&
4137 (mii_nway_adv_reg & NWAY_AR_ASM_DIR0x0800) &&
4138 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400) &&
4139 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR0x0800)) {
4140 hw->fc = E1000_FC_RX_PAUSE1;
4141 DEBUGOUT("Flow Control = RX PAUSE frames only."
4142 "\n");
4143 }
4144 /*
4145 * Per the IEEE spec, at this point flow control
4146 * should be disabled. However, we want to consider
4147 * that we could be connected to a legacy switch that
4148 * doesn't advertise desired flow control, but can be
4149 * forced on the link partner. So if we advertised
4150 * no flow control, that is what we will resolve to.
4151 * If we advertised some kind of receive capability
4152 * (Rx Pause Only or Full Flow Control) and the link
4153 * partner advertised none, we will configure
4154 * ourselves to enable Rx Flow Control only. We can
4155 * do this safely for two reasons: If the link
4156 * partner really didn't want flow control enabled,
4157 * and we enable Rx, no harm done since we won't be
4158 * receiving any PAUSE frames anyway. If the intent
4159 * on the link partner was to have flow control
4160 * enabled, then by us enabling RX only, we can at
4161 * least receive pause frames and process them. This
4162 * is a good idea because in most cases, since we are
4163 * predominantly a server NIC, more times than not we
4164 * will be asked to delay transmission of packets
4165 * than asking our link partner to pause transmission
4166 * of frames.
4167 */
4168 else if ((hw->original_fc == E1000_FC_NONE0 ||
4169 hw->original_fc == E1000_FC_TX_PAUSE2) ||
4170 hw->fc_strict_ieee) {
4171 hw->fc = E1000_FC_NONE0;
4172 DEBUGOUT("Flow Control = NONE.\n");
4173 } else {
4174 hw->fc = E1000_FC_RX_PAUSE1;
4175 DEBUGOUT("Flow Control = RX PAUSE frames only."
4176 "\n");
4177 }
4178 /*
4179 * Now we need to do one last check... If we auto-
4180 * negotiated to HALF DUPLEX, flow control should not
4181 * be enabled per IEEE 802.3 spec.
4182 */
4183 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4184 if (ret_val) {
4185 DEBUGOUT("Error getting link speed and duplex"
4186 "\n");
4187 return ret_val;
4188 }
4189 if (duplex == HALF_DUPLEX1)
4190 hw->fc = E1000_FC_NONE0;
4191 /*
4192 * Now we call a subroutine to actually force the MAC
4193 * controller to use the correct flow control
4194 * settings.
4195 */
4196 ret_val = em_force_mac_fc(hw);
4197 if (ret_val) {
4198 DEBUGOUT("Error forcing flow control settings"
4199 "\n");
4200 return ret_val;
4201 }
4202 } else {
4203 DEBUGOUT("Copper PHY and Auto Neg has not completed."
4204 "\n");
4205 }
4206 }
4207 return E1000_SUCCESS0;
4208}
4209/******************************************************************************
4210 * Checks to see if the link status of the hardware has changed.
4211 *
4212 * hw - Struct containing variables accessed by shared code
4213 *
4214 * Called by any function that needs to check the link status of the adapter.
4215 *****************************************************************************/
4216int32_t
4217em_check_for_link(struct em_hw *hw)
4218{
4219 uint32_t rxcw = 0;
4220 uint32_t ctrl;
4221 uint32_t status;
4222 uint32_t rctl;
4223 uint32_t icr;
4224 uint32_t signal = 0;
4225 int32_t ret_val;
4226 uint16_t phy_data;
4227 DEBUGFUNC("em_check_for_link");;
4228 uint16_t speed, duplex;
4229
4230 if (hw->mac_type >= em_82575 &&
4231 hw->media_type != em_media_type_copper) {
4232 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed,
4233 &duplex);
4234 hw->get_link_status = hw->serdes_link_down;
4235
4236 return (ret_val);
4237 }
4238
4239 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
4240 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
4241 /*
4242 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will
4243 * be set when the optics detect a signal. On older adapters, it will
4244 * be cleared when there is a signal. This applies to fiber media
4245 * only.
4246 */
4247 if ((hw->media_type == em_media_type_fiber) ||
4248 (hw->media_type == em_media_type_internal_serdes)) {
4249 rxcw = E1000_READ_REG(hw, RXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00180 : em_translate_82542_register
(0x00180)))))
;
4250
4251 if (hw->media_type == em_media_type_fiber) {
4252 signal = (hw->mac_type > em_82544) ?
4253 E1000_CTRL_SWDPIN10x00080000 : 0;
4254 if (status & E1000_STATUS_LU0x00000002)
4255 hw->get_link_status = FALSE0;
4256 }
4257 }
4258 /*
4259 * If we have a copper PHY then we only want to go out to the PHY
4260 * registers to see if Auto-Neg has completed and/or if our link
4261 * status has changed. The get_link_status flag will be set if we
4262 * receive a Link Status Change interrupt or we have Rx Sequence
4263 * Errors.
4264 */
4265 if ((hw->media_type == em_media_type_copper ||
4266 (hw->media_type == em_media_type_oem)) &&
4267 hw->get_link_status) {
4268 /*
4269 * First we want to see if the MII Status Register reports
4270 * link. If so, then we want to get the current speed/duplex
4271 * of the PHY. Read the register twice since the link bit is
4272 * sticky.
4273 */
4274 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
4275 if (ret_val)
4276 return ret_val;
4277 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
4278 if (ret_val)
4279 return ret_val;
4280
4281 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS0x0004) != 0;
4282
4283 if (hw->mac_type == em_pchlan) {
4284 ret_val = em_k1_gig_workaround_hv(hw,
4285 hw->icp_xxxx_is_link_up);
4286 if (ret_val)
4287 return ret_val;
4288 }
4289
4290 if (phy_data & MII_SR_LINK_STATUS0x0004) {
4291 hw->get_link_status = FALSE0;
4292
4293 if (hw->phy_type == em_phy_82578) {
4294 ret_val = em_link_stall_workaround_hv(hw);
4295 if (ret_val)
4296 return ret_val;
4297 }
4298
4299 if (hw->mac_type == em_pch2lan) {
4300 ret_val = em_k1_workaround_lv(hw);
4301 if (ret_val)
4302 return ret_val;
4303 }
4304 /* Work-around I218 hang issue */
4305 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM0x155A) ||
4306 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V0x1559) ||
4307 (hw->device_id == E1000_DEV_ID_PCH_I218_LM30x15A2) ||
4308 (hw->device_id == E1000_DEV_ID_PCH_I218_V30x15A3)) {
4309 ret_val = em_k1_workaround_lpt_lp(hw,
4310 hw->icp_xxxx_is_link_up);
4311 if (ret_val)
4312 return ret_val;
4313 }
4314
4315 /*
4316 * Check if there was DownShift, must be checked
4317 * immediately after link-up
4318 */
4319 em_check_downshift(hw);
4320
4321 /* Enable/Disable EEE after link up */
4322 if (hw->mac_type == em_pch2lan ||
4323 hw->mac_type == em_pch_lpt ||
4324 hw->mac_type == em_pch_spt ||
4325 hw->mac_type == em_pch_cnp) {
4326 ret_val = em_set_eee_pchlan(hw);
4327 if (ret_val)
4328 return ret_val;
4329 }
4330
4331 /*
4332 * If we are on 82544 or 82543 silicon and
4333 * speed/duplex are forced to 10H or 10F, then we
4334 * will implement the polarity reversal workaround.
4335 * We disable interrupts first, and upon returning,
4336 * place the devices interrupt state to its previous
4337 * value except for the link status change interrupt
4338 * which will happen due to the execution of this
4339 * workaround.
4340 */
4341 if ((hw->mac_type == em_82544 ||
4342 hw->mac_type == em_82543) && (!hw->autoneg) &&
4343 (hw->forced_speed_duplex == em_10_full ||
4344 hw->forced_speed_duplex == em_10_half)) {
4345 E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register
(0x000D8))), (0xffffffff)))
;
4346 ret_val = em_polarity_reversal_workaround(hw);
4347 icr = E1000_READ_REG(hw, ICR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000C0 : em_translate_82542_register
(0x000C0)))))
;
4348 E1000_WRITE_REG(hw, ICS,((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000C8 : em_translate_82542_register
(0x000C8))), ((icr & ~0x00000004))))
4349 (icr & ~E1000_ICS_LSC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000C8 : em_translate_82542_register
(0x000C8))), ((icr & ~0x00000004))))
;
4350 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000D0 : em_translate_82542_register
(0x000D0))), (( 0x00000080 | 0x00000001 | 0x00000010 | 0x00000008
| 0x00000040 | 0x00000004))))
;
4351 }
4352 } else {
4353 /* No link detected */
4354 em_config_dsp_after_link_change(hw, FALSE0);
4355 return 0;
4356 }
4357 /*
4358 * If we are forcing speed/duplex, then we simply return
4359 * since we have already determined whether we have link or
4360 * not.
4361 */
4362 if (!hw->autoneg)
4363 return -E1000_ERR_CONFIG3;
4364
4365 /* optimize the dsp settings for the igp phy */
4366 em_config_dsp_after_link_change(hw, TRUE1);
4367 /*
4368 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
4369 * have Si on board that is 82544 or newer, Auto Speed
4370 * Detection takes care of MAC speed/duplex configuration.
4371 * So we only need to configure Collision Distance in the
4372 * MAC. Otherwise, we need to force speed/duplex on the MAC
4373 * to the current PHY speed/duplex settings.
4374 */
4375 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) {
4376 em_config_collision_dist(hw);
4377 } else {
4378 ret_val = em_config_mac_to_phy(hw);
4379 if (ret_val) {
4380 DEBUGOUT("Error configuring MAC to PHY"
4381 " settings\n");
4382 return ret_val;
4383 }
4384 }
4385 /*
4386 * Configure Flow Control now that Auto-Neg has completed.
4387 * First, we need to restore the desired flow control
4388 * settings because we may have had to re-autoneg with a
4389 * different link partner.
4390 */
4391 ret_val = em_config_fc_after_link_up(hw);
4392 if (ret_val) {
4393 DEBUGOUT("Error configuring flow control\n");
4394 return ret_val;
4395 }
4396 /*
4397 * At this point we know that we are on copper and we have
4398 * auto-negotiated link. These are conditions for checking
4399 * the link partner capability register. We use the link
4400 * speed to determine if TBI compatibility needs to be turned
4401 * on or off. If the link is not at gigabit speed, then TBI
4402 * compatibility is not needed. If we are at gigabit speed,
4403 * we turn on TBI compatibility.
4404 */
4405 if (hw->tbi_compatibility_en) {
4406 uint16_t speed, duplex;
4407 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4408 if (ret_val) {
4409 DEBUGOUT("Error getting link speed and duplex"
4410 "\n");
4411 return ret_val;
4412 }
4413 if (speed != SPEED_10001000) {
4414 /*
4415 * If link speed is not set to gigabit speed,
4416 * we do not need to enable TBI
4417 * compatibility.
4418 */
4419 if (hw->tbi_compatibility_on) {
4420 /*
4421 * If we previously were in the mode,
4422 * turn it off.
4423 */
4424 rctl = E1000_READ_REG(hw, RCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100)))))
;
4425 rctl &= ~E1000_RCTL_SBP0x00000004;
4426 E1000_WRITE_REG(hw, RCTL, rctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (rctl)))
;
4427 hw->tbi_compatibility_on = FALSE0;
4428 }
4429 } else {
4430 /*
4431 * If TBI compatibility is was previously
4432 * off, turn it on. For compatibility with a
4433 * TBI link partner, we will store bad
4434 * packets. Some frames have an additional
4435 * byte on the end and will look like CRC
4436 * errors to to the hardware.
4437 */
4438 if (!hw->tbi_compatibility_on) {
4439 hw->tbi_compatibility_on = TRUE1;
4440 rctl = E1000_READ_REG(hw, RCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100)))))
;
4441 rctl |= E1000_RCTL_SBP0x00000004;
4442 E1000_WRITE_REG(hw, RCTL, rctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (rctl)))
;
4443 }
4444 }
4445 }
4446 }
4447 /*
4448 * If we don't have link (auto-negotiation failed or link partner
4449 * cannot auto-negotiate), the cable is plugged in (we have signal),
4450 * and our link partner is not trying to auto-negotiate with us (we
4451 * are receiving idles or data), we need to force link up. We also
4452 * need to give auto-negotiation time to complete, in case the cable
4453 * was just plugged in. The autoneg_failed flag does this.
4454 */
4455 else if ((((hw->media_type == em_media_type_fiber) &&
4456 ((ctrl & E1000_CTRL_SWDPIN10x00080000) == signal)) ||
4457 (hw->media_type == em_media_type_internal_serdes)) &&
4458 (!(status & E1000_STATUS_LU0x00000002)) && (!(rxcw & E1000_RXCW_C0x20000000))) {
4459 if (hw->autoneg_failed == 0) {
4460 hw->autoneg_failed = 1;
4461 return 0;
4462 }
4463 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
4464
4465 /* Disable auto-negotiation in the TXCW register */
4466 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178))), ((hw->txcw & ~0x80000000))))
;
4467
4468 /* Force link-up and also force full-duplex. */
4469 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
4470 ctrl |= (E1000_CTRL_SLU0x00000040 | E1000_CTRL_FD0x00000001);
4471 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
4472
4473 /* Configure Flow Control after forcing link up. */
4474 ret_val = em_config_fc_after_link_up(hw);
4475 if (ret_val) {
4476 DEBUGOUT("Error configuring flow control\n");
4477 return ret_val;
4478 }
4479 }
4480 /*
4481 * If we are forcing link and we are receiving /C/ ordered sets,
4482 * re-enable auto-negotiation in the TXCW register and disable forced
4483 * link in the Device Control register in an attempt to
4484 * auto-negotiate with our link partner.
4485 */
4486 else if (((hw->media_type == em_media_type_fiber) ||
4487 (hw->media_type == em_media_type_internal_serdes)) &&
4488 (ctrl & E1000_CTRL_SLU0x00000040) && (rxcw & E1000_RXCW_C0x20000000)) {
4489 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
4490 E1000_WRITE_REG(hw, TXCW, hw->txcw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178))), (hw->txcw)))
;
4491 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((ctrl & ~0x00000040))))
;
4492
4493 hw->serdes_link_down = FALSE0;
4494 }
4495 /*
4496 * If we force link for non-auto-negotiation switch, check link
4497 * status based on MAC synchronization for internal serdes media
4498 * type.
4499 */
4500 else if ((hw->media_type == em_media_type_internal_serdes) &&
4501 !(E1000_TXCW_ANE0x80000000 & E1000_READ_REG(hw, TXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178)))))
)) {
4502 /* SYNCH bit and IV bit are sticky. */
4503 usec_delay(10)(*delay_func)(10);
4504 if (E1000_RXCW_SYNCH0x40000000 & E1000_READ_REG(hw, RXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00180 : em_translate_82542_register
(0x00180)))))
) {
4505 if (!(rxcw & E1000_RXCW_IV0x08000000)) {
4506 hw->serdes_link_down = FALSE0;
4507 DEBUGOUT("SERDES: Link is up.\n");
4508 }
4509 } else {
4510 hw->serdes_link_down = TRUE1;
4511 DEBUGOUT("SERDES: Link is down.\n");
4512 }
4513 }
4514 if ((hw->media_type == em_media_type_internal_serdes) &&
4515 (E1000_TXCW_ANE0x80000000 & E1000_READ_REG(hw, TXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178)))))
)) {
4516 hw->serdes_link_down = !(E1000_STATUS_LU0x00000002 &
4517 E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
);
4518 }
4519 return E1000_SUCCESS0;
4520}
4521
4522int32_t
4523em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed,
4524 uint16_t *duplex)
4525{
4526 uint32_t pcs;
4527
4528 hw->serdes_link_down = TRUE1;
4529 *speed = 0;
4530 *duplex = 0;
4531
4532 /*
4533 * Read the PCS Status register for link state. For non-copper mode,
4534 * the status register is not accurate. The PCS status register is
4535 * used instead.
4536 */
4537 pcs = E1000_READ_REG(hw, PCS_LSTAT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0420C : em_translate_82542_register
(0x0420C)))))
;
4538
4539 /*
4540 * The link up bit determines when link is up on autoneg. The sync ok
4541 * gets set once both sides sync up and agree upon link. Stable link
4542 * can be determined by checking for both link up and link sync ok
4543 */
4544 if ((pcs & E1000_PCS_LSTS_LINK_OK0x01) && (pcs & E1000_PCS_LSTS_SYNK_OK0x10)) {
4545 hw->serdes_link_down = FALSE0;
4546
4547 /* Detect and store PCS speed */
4548 if (pcs & E1000_PCS_LSTS_SPEED_10000x04) {
4549 *speed = SPEED_10001000;
4550 } else if (pcs & E1000_PCS_LSTS_SPEED_1000x02) {
4551 *speed = SPEED_100100;
4552 } else {
4553 *speed = SPEED_1010;
4554 }
4555
4556 /* Detect and store PCS duplex */
4557 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL0x08) {
4558 *duplex = FULL_DUPLEX2;
4559 } else {
4560 *duplex = HALF_DUPLEX1;
4561 }
4562 }
4563
4564 return (0);
4565}
4566
4567
4568/******************************************************************************
4569 * Detects the current speed and duplex settings of the hardware.
4570 *
4571 * hw - Struct containing variables accessed by shared code
4572 * speed - Speed of the connection
4573 * duplex - Duplex setting of the connection
4574 *****************************************************************************/
4575int32_t
4576em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex)
4577{
4578 uint32_t status;
4579 int32_t ret_val;
4580 uint16_t phy_data;
4581 DEBUGFUNC("em_get_speed_and_duplex");;
4582
4583 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper)
4584 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex);
4585
4586 if (hw->mac_type >= em_82543) {
4587 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
4588 if (status & E1000_STATUS_SPEED_10000x00000080) {
4589 *speed = SPEED_10001000;
4590 DEBUGOUT("1000 Mbs, ");
4591 } else if (status & E1000_STATUS_SPEED_1000x00000040) {
4592 *speed = SPEED_100100;
4593 DEBUGOUT("100 Mbs, ");
4594 } else {
4595 *speed = SPEED_1010;
4596 DEBUGOUT("10 Mbs, ");
4597 }
4598
4599 if (status & E1000_STATUS_FD0x00000001) {
4600 *duplex = FULL_DUPLEX2;
4601 DEBUGOUT("Full Duplex\n");
4602 } else {
4603 *duplex = HALF_DUPLEX1;
4604 DEBUGOUT(" Half Duplex\n");
4605 }
4606 } else {
4607 DEBUGOUT("1000 Mbs, Full Duplex\n");
4608 *speed = SPEED_10001000;
4609 *duplex = FULL_DUPLEX2;
4610 }
4611 /*
4612 * IGP01 PHY may advertise full duplex operation after speed
4613 * downgrade even if it is operating at half duplex. Here we set the
4614 * duplex settings to match the duplex in the link partner's
4615 * capabilities.
4616 */
4617 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) {
4618 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP0x06, &phy_data);
4619 if (ret_val)
4620 return ret_val;
4621
4622 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS0x0001))
4623 *duplex = HALF_DUPLEX1;
4624 else {
4625 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY0x05,
4626 &phy_data);
4627 if (ret_val)
4628 return ret_val;
4629 if ((*speed == SPEED_100100 &&
4630 !(phy_data & NWAY_LPAR_100TX_FD_CAPS0x0100)) ||
4631 (*speed == SPEED_1010 &&
4632 !(phy_data & NWAY_LPAR_10T_FD_CAPS0x0040)))
4633 *duplex = HALF_DUPLEX1;
4634 }
4635 }
4636 if ((hw->mac_type == em_80003es2lan) &&
4637 (hw->media_type == em_media_type_copper)) {
4638 if (*speed == SPEED_10001000)
4639 ret_val = em_configure_kmrn_for_1000(hw);
4640 else
4641 ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
4642 if (ret_val)
4643 return ret_val;
4644 }
4645 if ((hw->mac_type == em_ich8lan) &&
4646 (hw->phy_type == em_phy_igp_3) &&
4647 (*speed == SPEED_10001000)) {
4648 ret_val = em_kumeran_lock_loss_workaround(hw);
4649 if (ret_val)
4650 return ret_val;
4651 }
4652 return E1000_SUCCESS0;
4653}
4654
4655/******************************************************************************
4656 * Blocks until autoneg completes or times out (~4.5 seconds)
4657 *
4658 * hw - Struct containing variables accessed by shared code
4659 *****************************************************************************/
4660STATIC int32_t
4661em_wait_autoneg(struct em_hw *hw)
4662{
4663 int32_t ret_val;
4664 uint16_t i;
4665 uint16_t phy_data;
4666 DEBUGFUNC("em_wait_autoneg");;
4667 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4668
4669 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4670 for (i = PHY_AUTO_NEG_TIME45; i > 0; i--) {
4671 /*
4672 * Read the MII Status Register and wait for Auto-Neg
4673 * Complete bit to be set.
4674 */
4675 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
4676 if (ret_val)
4677 return ret_val;
4678 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
4679 if (ret_val)
4680 return ret_val;
4681 if (phy_data & MII_SR_AUTONEG_COMPLETE0x0020) {
4682 return E1000_SUCCESS0;
4683 }
4684 msec_delay(100)(*delay_func)(1000*(100));
4685 }
4686 return E1000_SUCCESS0;
4687}
4688
4689/******************************************************************************
4690 * Raises the Management Data Clock
4691 *
4692 * hw - Struct containing variables accessed by shared code
4693 * ctrl - Device control register's current value
4694 *****************************************************************************/
4695static void
4696em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4697{
4698 /*
4699 * Raise the clock input to the Management Data Clock (by setting the
4700 * MDC bit), and then delay 10 microseconds.
4701 */
4702 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((*ctrl | 0x00200000))))
;
4703 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
4704 usec_delay(10)(*delay_func)(10);
4705}
4706
4707/******************************************************************************
4708 * Lowers the Management Data Clock
4709 *
4710 * hw - Struct containing variables accessed by shared code
4711 * ctrl - Device control register's current value
4712 *****************************************************************************/
4713static void
4714em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4715{
4716 /*
4717 * Lower the clock input to the Management Data Clock (by clearing
4718 * the MDC bit), and then delay 10 microseconds.
4719 */
4720 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((*ctrl & ~0x00200000))))
;
4721 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
4722 usec_delay(10)(*delay_func)(10);
4723}
4724
4725/******************************************************************************
4726 * Shifts data bits out to the PHY
4727 *
4728 * hw - Struct containing variables accessed by shared code
4729 * data - Data to send out to the PHY
4730 * count - Number of bits to shift out
4731 *
4732 * Bits are shifted out in MSB to LSB order.
4733 *****************************************************************************/
4734static void
4735em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count)
4736{
4737 uint32_t ctrl;
4738 uint32_t mask;
4739 /*
4740 * We need to shift "count" number of bits out to the PHY. So, the
4741 * value in the "data" parameter will be shifted out to the PHY one
4742 * bit at a time. In order to do this, "data" must be broken down
4743 * into bits.
4744 */
4745 mask = 0x01;
4746 mask <<= (count - 1);
4747
4748 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
4749
4750 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output
4751 * pins.
4752 */
4753 ctrl |= (E1000_CTRL_MDIO_DIR0x01000000 | E1000_CTRL_MDC_DIR0x02000000);
4754
4755 while (mask) {
4756 /*
4757 * A "1" is shifted out to the PHY by setting the MDIO bit to
4758 * "1" and then raising and lowering the Management Data
4759 * Clock. A "0" is shifted out to the PHY by setting the MDIO
4760 * bit to "0" and then raising and lowering the clock.
4761 */
4762 if (data & mask)
4763 ctrl |= E1000_CTRL_MDIO0x00100000;
4764 else
4765 ctrl &= ~E1000_CTRL_MDIO0x00100000;
4766
4767 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
4768 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
4769
4770 usec_delay(10)(*delay_func)(10);
4771
4772 em_raise_mdi_clk(hw, &ctrl);
4773 em_lower_mdi_clk(hw, &ctrl);
4774
4775 mask = mask >> 1;
4776 }
4777}
4778
4779/******************************************************************************
4780 * Shifts data bits in from the PHY
4781 *
4782 * hw - Struct containing variables accessed by shared code
4783 *
4784 * Bits are shifted in in MSB to LSB order.
4785 *****************************************************************************/
4786static uint16_t
4787em_shift_in_mdi_bits(struct em_hw *hw)
4788{
4789 uint32_t ctrl;
4790 uint16_t data = 0;
4791 uint8_t i;
4792 /*
4793 * In order to read a register from the PHY, we need to shift in a
4794 * total of 18 bits from the PHY. The first two bit (turnaround)
4795 * times are used to avoid contention on the MDIO pin when a read
4796 * operation is performed. These two bits are ignored by us and
4797 * thrown away. Bits are "shifted in" by raising the input to the
4798 * Management Data Clock (setting the MDC bit), and then reading the
4799 * value of the MDIO bit.
4800 */
4801 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
4802 /*
4803 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
4804 * input.
4805 */
4806 ctrl &= ~E1000_CTRL_MDIO_DIR0x01000000;
4807 ctrl &= ~E1000_CTRL_MDIO0x00100000;
4808
4809 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)))
;
4810 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
;
4811 /*
4812 * Raise and Lower the clock before reading in the data. This
4813 * accounts for the turnaround bits. The first clock occurred when we
4814 * clocked out the last bit of the Register Address.
4815 */
4816 em_raise_mdi_clk(hw, &ctrl);
4817 em_lower_mdi_clk(hw, &ctrl);
4818
4819 for (data = 0, i = 0; i < 16; i++) {
4820 data = data << 1;
4821 em_raise_mdi_clk(hw, &ctrl);
4822 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))))
;
4823 /* Check to see if we shifted in a "1". */
4824 if (ctrl & E1000_CTRL_MDIO0x00100000)
4825 data |= 1;
4826 em_lower_mdi_clk(hw, &ctrl);
4827 }
4828
4829 em_raise_mdi_clk(hw, &ctrl);
4830 em_lower_mdi_clk(hw, &ctrl);
4831
4832 return data;
4833}
4834
4835STATIC int32_t
4836em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)
4837{
4838 uint32_t swfw_sync = 0;
4839 uint32_t swmask = mask;
4840 uint32_t fwmask = mask << 16;
4841 int32_t timeout = 200;
4842 DEBUGFUNC("em_swfw_sync_acquire");;
4843
4844 if (hw->swfwhw_semaphore_present)
4845 return em_get_software_flag(hw);
4846
4847 if (!hw->swfw_sync_present)
4848 return em_get_hw_eeprom_semaphore(hw);
4849
4850 while (timeout) {
4851 if (em_get_hw_eeprom_semaphore(hw))
4852 return -E1000_ERR_SWFW_SYNC13;
4853
4854 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register
(0x05B5C)))))
;
4855 if (!(swfw_sync & (fwmask | swmask))) {
4856 break;
4857 }
4858 /*
4859 * firmware currently using resource (fwmask)
4860 * or other software thread currently using resource (swmask)
4861 */
4862 em_put_hw_eeprom_semaphore(hw);
4863 msec_delay_irq(5)(*delay_func)(1000*(5));
4864 timeout--;
4865 }
4866
4867 if (!timeout) {
4868 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout."
4869 "\n");
4870 return -E1000_ERR_SWFW_SYNC13;
4871 }
4872 swfw_sync |= swmask;
4873 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register
(0x05B5C))), (swfw_sync)))
;
4874
4875 em_put_hw_eeprom_semaphore(hw);
4876 return E1000_SUCCESS0;
4877}
4878
4879STATIC void
4880em_swfw_sync_release(struct em_hw *hw, uint16_t mask)
4881{
4882 uint32_t swfw_sync;
4883 uint32_t swmask = mask;
4884 DEBUGFUNC("em_swfw_sync_release");;
4885
4886 if (hw->swfwhw_semaphore_present) {
4887 em_release_software_flag(hw);
4888 return;
4889 }
4890 if (!hw->swfw_sync_present) {
4891 em_put_hw_eeprom_semaphore(hw);
4892 return;
4893 }
4894 /*
4895 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC;
4896 */
4897 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS0);
4898 /* empty */
4899
4900 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register
(0x05B5C)))))
;
4901 swfw_sync &= ~swmask;
4902 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register
(0x05B5C))), (swfw_sync)))
;
4903
4904 em_put_hw_eeprom_semaphore(hw);
4905}
4906
4907/****************************************************************************
4908 * Read BM PHY wakeup register. It works as such:
4909 * 1) Set page 769, register 17, bit 2 = 1
4910 * 2) Set page to 800 for host (801 if we were manageability)
4911 * 3) Write the address using the address opcode (0x11)
4912 * 4) Read or write the data using the data opcode (0x12)
4913 * 5) Restore 769_17.2 to its original value
4914 ****************************************************************************/
4915int32_t
4916em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr,
4917 uint16_t *phy_data, boolean_t read)
4918{
4919 int32_t ret_val;
4920 uint16_t reg = BM_PHY_REG_NUM(reg_addr)((uint16_t)(((reg_addr) & 0x1F) | (((reg_addr) >> (
21 - 5)) & ~0x1F)))
;
4921 uint16_t phy_reg = 0;
4922
4923 /* All operations in this function are phy address 1 */
4924 hw->phy_addr = 1;
4925
4926 /* Set page 769 */
4927 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
4928 (BM_WUC_ENABLE_PAGE769 << PHY_PAGE_SHIFT5));
4929
4930 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, &phy_reg);
4931 if (ret_val)
4932 goto out;
4933
4934 /* First clear bit 4 to avoid a power state change */
4935 phy_reg &= ~(BM_WUC_HOST_WU_BIT(1 << 4));
4936 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, phy_reg);
4937 if (ret_val)
4938 goto out;
4939
4940 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
4941 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17,
4942 phy_reg | BM_WUC_ENABLE_BIT(1 << 2));
4943 if (ret_val)
4944 goto out;
4945
4946 /* Select page 800 */
4947 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
4948 (BM_WUC_PAGE800 << PHY_PAGE_SHIFT5));
4949
4950 /* Write the page 800 offset value using opcode 0x11 */
4951 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE0x11, reg);
4952 if (ret_val)
4953 goto out;
4954
4955 if (read)
4956 /* Read the page 800 value using opcode 0x12 */
4957 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE0x12,
4958 phy_data);
4959 else
4960 /* Write the page 800 value using opcode 0x12 */
4961 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE0x12,
4962 *phy_data);
4963
4964 if (ret_val)
4965 goto out;
4966
4967 /*
4968 * Restore 769_17.2 to its original value
4969 * Set page 769
4970 */
4971 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
4972 (BM_WUC_ENABLE_PAGE769 << PHY_PAGE_SHIFT5));
4973
4974 /* Clear 769_17.2 */
4975 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, phy_reg);
4976 if (ret_val)
4977 goto out;
4978
4979out:
4980 return ret_val;
4981}
4982
4983/***************************************************************************
4984 * Read HV PHY vendor specific high registers
4985 ***************************************************************************/
4986int32_t
4987em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr,
4988 uint16_t *phy_data, boolean_t read)
4989{
4990 int32_t ret_val;
4991 uint32_t addr_reg = 0;
4992 uint32_t data_reg = 0;
4993
4994 /* This takes care of the difference with desktop vs mobile phy */
4995 addr_reg = (hw->phy_type == em_phy_82578) ?
4996 I82578_PHY_ADDR_REG29 : I82577_PHY_ADDR_REG16;
4997 data_reg = addr_reg + 1;
4998
4999 /* All operations in this function are phy address 2 */
5000 hw->phy_addr = 2;
5001
5002 /* masking with 0x3F to remove the page from offset */
5003 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F);
5004 if (ret_val) {
5005 printf("Could not write PHY the HV address register\n");
5006 goto out;
5007 }
5008
5009 /* Read or write the data value next */
5010 if (read)
5011 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data);
5012 else
5013 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data);
5014
5015 if (ret_val) {
5016 printf("Could not read data value from HV data register\n");
5017 goto out;
5018 }
5019
5020out:
5021 return ret_val;
5022}
5023
5024/******************************************************************************
5025 * Reads or writes the value from a PHY register, if the value is on a specific
5026 * non zero page, sets the page first.
5027 * hw - Struct containing variables accessed by shared code
5028 * reg_addr - address of the PHY register to read
5029 *****************************************************************************/
5030int32_t
5031em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data,
5032 boolean_t read)
5033{
5034 uint32_t ret_val;
5035 uint16_t swfw;
5036 uint16_t page = BM_PHY_REG_PAGE(reg_addr)((uint16_t)(((reg_addr) >> 5) & 0xFFFF));
5037 uint16_t reg = BM_PHY_REG_NUM(reg_addr)((uint16_t)(((reg_addr) & 0x1F) | (((reg_addr) >> (
21 - 5)) & ~0x1F)))
;
5038
5039 DEBUGFUNC("em_access_phy_reg_hv");;
5040
5041 swfw = E1000_SWFW_PHY0_SM0x0002;
5042
5043 if (em_swfw_sync_acquire(hw, swfw))
5044 return -E1000_ERR_SWFW_SYNC13;
5045
5046 if (page == BM_WUC_PAGE800) {
5047 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr,
5048 phy_data, read);
5049 goto release;
5050 }
5051
5052 if (page >= HV_INTC_FC_PAGE_START768)
5053 hw->phy_addr = 1;
5054 else
5055 hw->phy_addr = 2;
5056
5057 if (page == HV_INTC_FC_PAGE_START768)
5058 page = 0;
5059
5060 /*
5061 * Workaround MDIO accesses being disabled after entering IEEE Power
5062 * Down (whenever bit 11 of the PHY Control register is set)
5063 */
5064 if (!read &&
5065 (hw->phy_type == em_phy_82578) &&
5066 (hw->phy_revision >= 1) &&
5067 (hw->phy_addr == 2) &&
5068 ((MAX_PHY_REG_ADDRESS0x1F & reg) == 0) &&
5069 (*phy_data & (1 << 11))) {
5070 uint16_t data2 = 0x7EFF;
5071
5072 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
5073 &data2, FALSE0);
5074 if (ret_val)
5075 return ret_val;
5076 }
5077
5078 if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) {
5079 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
5080 (page << PHY_PAGE_SHIFT5));
5081 if (ret_val)
5082 return ret_val;
5083 }
5084 if (read)
5085 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg,
5086 phy_data);
5087 else
5088 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg,
5089 *phy_data);
5090release:
5091 em_swfw_sync_release(hw, swfw);
5092 return ret_val;
5093}
5094
5095/******************************************************************************
5096 * Reads the value from a PHY register, if the value is on a specific non zero
5097 * page, sets the page first.
5098 * hw - Struct containing variables accessed by shared code
5099 * reg_addr - address of the PHY register to read
5100 *****************************************************************************/
5101int32_t
5102em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5103{
5104 uint32_t ret_val;
5105 uint16_t swfw;
5106 DEBUGFUNC("em_read_phy_reg");;
5107
5108 if (hw->mac_type == em_pchlan ||
5109 hw->mac_type == em_pch2lan ||
5110 hw->mac_type == em_pch_lpt ||
5111 hw->mac_type == em_pch_spt ||
5112 hw->mac_type == em_pch_cnp)
5113 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE1));
5114
5115 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575) ||
5116 (hw->mac_type == em_82576)) &&
5117 (E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))))
& E1000_STATUS_FUNC_10x00000004)) {
5118 swfw = E1000_SWFW_PHY1_SM0x0004;
5119 } else {
5120 swfw = E1000_SWFW_PHY0_SM0x0002;
5121 }
5122 if (em_swfw_sync_acquire(hw, swfw))
5123 return -E1000_ERR_SWFW_SYNC13;
5124
5125 if ((hw->phy_type == em_phy_igp ||
5126 hw->phy_type == em_phy_igp_3 ||
5127 hw->phy_type == em_phy_igp_2) &&
5128 (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF)) {
5129 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
5130 (uint16_t) reg_addr);
5131 if (ret_val) {
5132 em_swfw_sync_release(hw, swfw);
5133 return ret_val;
5134 }
5135 } else if (hw->phy_type == em_phy_gg82563) {
5136 if (((reg_addr & MAX_PHY_REG_ADDRESS0x1F) > MAX_PHY_MULTI_PAGE_REG0xF) ||
5137 (hw->mac_type == em_80003es2lan)) {
5138 /* Select Configuration Page */
5139 if ((reg_addr & MAX_PHY_REG_ADDRESS0x1F) <
5140 GG82563_MIN_ALT_REG30) {
5141 ret_val = em_write_phy_reg_ex(hw,
5142 GG82563_PHY_PAGE_SELECT(((0) << 5) | ((22) & 0x1F)),
5143 (uint16_t) ((uint16_t) reg_addr >>
5144 GG82563_PAGE_SHIFT5));
5145 } else {
5146 /*
5147 * Use Alternative Page Select register to
5148 * access registers 30 and 31
5149 */
5150 ret_val = em_write_phy_reg_ex(hw,
5151 GG82563_PHY_PAGE_SELECT_ALT(((0) << 5) | ((29) & 0x1F)),
5152 (uint16_t) ((uint16_t) reg_addr >>
5153 GG82563_PAGE_SHIFT5));
5154 }
5155
5156 if (ret_val) {
5157 em_swfw_sync_release(hw, swfw);
5158 return ret_val;
5159 }
5160 }
5161 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
5162 if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) {
5163 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT22,
5164 (uint16_t) ((uint16_t) reg_addr >>
5165 PHY_PAGE_SHIFT5));
5166 if (ret_val)
5167 return ret_val;
5168 }
5169 }
5170 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg_addr,
5171 phy_data);
5172
5173 em_swfw_sync_release(hw, swfw);
5174 return ret_val;
5175}
5176
5177STATIC int32_t
5178em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5179{
5180 uint32_t i;
5181 uint32_t mdic = 0;
5182 DEBUGFUNC("em_read_phy_reg_ex");;
5183
5184 /* SGMII active is only set on some specific chips */
5185 if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) {
5186 if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR255) {
5187 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5188 return -E1000_ERR_PARAM4;
5189 }
5190 return em_read_phy_reg_i2c(hw, reg_addr, phy_data);
5191 }
5192 if (reg_addr > MAX_PHY_REG_ADDRESS0x1F) {
5193 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5194 return -E1000_ERR_PARAM4;
5195 }
5196 if (hw->mac_type == em_icp_xxxx) {
5197 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num,
5198 reg_addr);
5199 return E1000_SUCCESS0;
5200 }
5201 if (hw->mac_type > em_82543) {
5202 /*
5203 * Set up Op-code, Phy Address, and register address in the
5204 * MDI Control register. The MAC will take care of
5205 * interfacing with the PHY to retrieve the desired data.
5206 */
5207 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT16) |
5208 (hw->phy_addr << E1000_MDIC_PHY_SHIFT21) |
5209 (E1000_MDIC_OP_READ0x08000000));
5210
5211 E1000_WRITE_REG(hw, MDIC, mdic)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020))), (mdic)))
;
5212
5213 /*
5214 * Poll the ready bit to see if the MDI read completed
5215 * Increasing the time out as testing showed failures with
5216 * the lower time out (from FreeBSD driver)
5217 */
5218 for (i = 0; i < 1960; i++) {
5219 usec_delay(50)(*delay_func)(50);
5220 mdic = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020)))))
;
5221 if (mdic & E1000_MDIC_READY0x10000000)
5222 break;
5223 }
5224 if (!(mdic & E1000_MDIC_READY0x10000000)) {
5225 DEBUGOUT("MDI Read did not complete\n");
5226 return -E1000_ERR_PHY2;
5227 }
5228 if (mdic & E1000_MDIC_ERROR0x40000000) {
5229 DEBUGOUT("MDI Error\n");
5230 return -E1000_ERR_PHY2;
5231 }
5232 *phy_data = (uint16_t) mdic;
5233
5234 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
5235 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp)
5236 usec_delay(100)(*delay_func)(100);
5237 } else {
5238 /*
5239 * We must first send a preamble through the MDIO pin to
5240 * signal the beginning of an MII instruction. This is done
5241 * by sending 32 consecutive "1" bits.
5242 */
5243 em_shift_out_mdi_bits(hw, PHY_PREAMBLE0xFFFFFFFF, PHY_PREAMBLE_SIZE32);
5244 /*
5245 * Now combine the next few fields that are required for a
5246 * read operation. We use this method instead of calling the
5247 * em_shift_out_mdi_bits routine five different times. The
5248 * format of a MII read instruction consists of a shift out
5249 * of 14 bits and is defined as follows: <Preamble><SOF><Op
5250 * Code><Phy Addr><Reg Addr> followed by a shift in of 18
5251 * bits. This first two bits shifted in are TurnAround bits
5252 * used to avoid contention on the MDIO pin when a READ
5253 * operation is performed. These two bits are thrown away
5254 * followed by a shift in of 16 bits which contains the
5255 * desired data.
5256 */
5257 mdic = ((reg_addr) | (hw->phy_addr << 5) |
5258 (PHY_OP_READ0x02 << 10) | (PHY_SOF0x01 << 12));
5259
5260 em_shift_out_mdi_bits(hw, mdic, 14);
5261 /*
5262 * Now that we've shifted out the read command to the MII, we
5263 * need to "shift in" the 16-bit value (18 total bits) of the
5264 * requested PHY register address.
5265 */
5266 *phy_data = em_shift_in_mdi_bits(hw);
5267 }
5268 return E1000_SUCCESS0;
5269}
5270
5271/******************************************************************************
5272 * Writes a value to a PHY register
5273 *
5274 * hw - Struct containing variables accessed by shared code
5275 * reg_addr - address of the PHY register to write
5276 * data - data to write to the PHY
5277 *****************************************************************************/
5278int32_t
5279em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5280{
5281 uint32_t ret_val;
5282 DEBUGFUNC("em_write_phy_reg");;
5283
5284 if (hw->mac_type == em_pchlan ||
5285 hw->mac_type == em_pch2lan ||
5286 hw->mac_type == em_pch_lpt ||
5287 hw->mac_type == em_pch_spt ||
5288 hw->mac_type == em_pch_cnp)
5289 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE0));
5290
5291 if (em_swfw_sync_acquire(hw, hw->swfw))
5292 return -E1000_ERR_SWFW_SYNC13;
5293
5294 if ((hw->phy_type == em_phy_igp ||
5295 hw->phy_type == em_phy_igp_3 ||
5296 hw->phy_type == em_phy_igp_2) &&
5297 (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF)) {
5298 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
5299 (uint16_t) reg_addr);
5300 if (ret_val) {
5301 em_swfw_sync_release(hw, hw->swfw);
5302 return ret_val;
5303 }
5304 } else if (hw->phy_type == em_phy_gg82563) {
5305 if (((reg_addr & MAX_PHY_REG_ADDRESS0x1F) > MAX_PHY_MULTI_PAGE_REG0xF) ||
5306 (hw->mac_type == em_80003es2lan)) {
5307 /* Select Configuration Page */
5308 if ((reg_addr & MAX_PHY_REG_ADDRESS0x1F) <
5309 GG82563_MIN_ALT_REG30) {
5310 ret_val = em_write_phy_reg_ex(hw,
5311 GG82563_PHY_PAGE_SELECT(((0) << 5) | ((22) & 0x1F)),
5312 (uint16_t) ((uint16_t) reg_addr >>
5313 GG82563_PAGE_SHIFT5));
5314 } else {
5315 /*
5316 * Use Alternative Page Select register to
5317 * access registers 30 and 31
5318 */
5319 ret_val = em_write_phy_reg_ex(hw,
5320 GG82563_PHY_PAGE_SELECT_ALT(((0) << 5) | ((29) & 0x1F)),
5321 (uint16_t) ((uint16_t) reg_addr >>
5322 GG82563_PAGE_SHIFT5));
5323 }
5324
5325 if (ret_val) {
5326 em_swfw_sync_release(hw, hw->swfw);
5327 return ret_val;
5328 }
5329 }
5330 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
5331 if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) {
5332 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT22,
5333 (uint16_t) ((uint16_t) reg_addr >>
5334 PHY_PAGE_SHIFT5));
5335 if (ret_val)
5336 return ret_val;
5337 }
5338 }
5339 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg_addr,
5340 phy_data);
5341
5342 em_swfw_sync_release(hw, hw->swfw);
5343 return ret_val;
5344}
5345
5346STATIC int32_t
5347em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5348{
5349 uint32_t i;
5350 uint32_t mdic = 0;
5351 DEBUGFUNC("em_write_phy_reg_ex");;
5352
5353 /* SGMII active is only set on some specific chips */
5354 if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) {
5355 if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR255) {
5356 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5357 return -E1000_ERR_PARAM4;
5358 }
5359 return em_write_phy_reg_i2c(hw, reg_addr, phy_data);
5360 }
5361 if (reg_addr > MAX_PHY_REG_ADDRESS0x1F) {
5362 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5363 return -E1000_ERR_PARAM4;
5364 }
5365 if (hw->mac_type == em_icp_xxxx) {
5366 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num,
5367 reg_addr, phy_data);
5368 return E1000_SUCCESS0;
5369 }
5370 if (hw->mac_type > em_82543) {
5371 /*
5372 * Set up Op-code, Phy Address, register address, and data
5373 * intended for the PHY register in the MDI Control register.
5374 * The MAC will take care of interfacing with the PHY to send
5375 * the desired data.
5376 */
5377 mdic = (((uint32_t) phy_data) |
5378 (reg_addr << E1000_MDIC_REG_SHIFT16) |
5379 (hw->phy_addr << E1000_MDIC_PHY_SHIFT21) |
5380 (E1000_MDIC_OP_WRITE0x04000000));
5381
5382 E1000_WRITE_REG(hw, MDIC, mdic)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020))), (mdic)))
;
5383
5384 /* Poll the ready bit to see if the MDI read completed */
5385 for (i = 0; i < 641; i++) {
5386 usec_delay(5)(*delay_func)(5);
5387 mdic = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020)))))
;
5388 if (mdic & E1000_MDIC_READY0x10000000)
5389 break;
5390 }
5391 if (!(mdic & E1000_MDIC_READY0x10000000)) {
5392 DEBUGOUT("MDI Write did not complete\n");
5393 return -E1000_ERR_PHY2;
5394 }
5395
5396 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
5397 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp)
5398 usec_delay(100)(*delay_func)(100);
5399 } else {
5400 /*
5401 * We'll need to use the SW defined pins to shift the write
5402 * command out to the PHY. We first send a preamble to the
5403 * PHY to signal the beginning of the MII instruction. This
5404 * is done by sending 32 consecutive "1" bits.
5405 */
5406 em_shift_out_mdi_bits(hw, PHY_PREAMBLE0xFFFFFFFF, PHY_PREAMBLE_SIZE32);
5407 /*
5408 * Now combine the remaining required fields that will
5409 * indicate a write operation. We use this method instead of
5410 * calling the em_shift_out_mdi_bits routine for each field
5411 * in the command. The format of a MII write instruction is
5412 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg
5413 * Addr><Turnaround><Data>.
5414 */
5415 mdic = ((PHY_TURNAROUND0x02) | (reg_addr << 2) |
5416 (hw->phy_addr << 7) | (PHY_OP_WRITE0x01 << 12) |
5417 (PHY_SOF0x01 << 14));
5418 mdic <<= 16;
5419 mdic |= (uint32_t) phy_data;
5420
5421 em_shift_out_mdi_bits(hw, mdic, 32);
5422 }
5423
5424 return E1000_SUCCESS0;
5425}
5426
5427STATIC int32_t
5428em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data)
5429{
5430 uint32_t reg_val;
5431 DEBUGFUNC("em_read_kmrn_reg");;
5432
5433 if (em_swfw_sync_acquire(hw, hw->swfw))
5434 return -E1000_ERR_SWFW_SYNC13;
5435
5436 /* Write register address */
5437 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT16) &
5438 E1000_KUMCTRLSTA_OFFSET0x001F0000) |
5439 E1000_KUMCTRLSTA_REN0x00200000;
5440
5441 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034))), (reg_val)))
;
5442 usec_delay(2)(*delay_func)(2);
5443
5444 /* Read the data returned */
5445 reg_val = E1000_READ_REG(hw, KUMCTRLSTA)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034)))))
;
5446 *data = (uint16_t) reg_val;
5447
5448 em_swfw_sync_release(hw, hw->swfw);
5449 return E1000_SUCCESS0;
5450}
5451
5452STATIC int32_t
5453em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data)
5454{
5455 uint32_t reg_val;
5456 DEBUGFUNC("em_write_kmrn_reg");;
5457
5458 if (em_swfw_sync_acquire(hw, hw->swfw))
5459 return -E1000_ERR_SWFW_SYNC13;
5460
5461 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT16) &
5462 E1000_KUMCTRLSTA_OFFSET0x001F0000) | data;
5463
5464 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034))), (reg_val)))
;
5465 usec_delay(2)(*delay_func)(2);
5466
5467 em_swfw_sync_release(hw, hw->swfw);
5468 return E1000_SUCCESS0;
5469}
5470
5471/**
5472 * em_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
5473 * @hw: pointer to the HW structure
5474 *
5475 * Called to determine if the I2C pins are being used for I2C or as an
5476 * external MDIO interface since the two options are mutually exclusive.
5477 **/
5478int em_sgmii_uses_mdio_82575(struct em_hw *hw)
5479{
5480 uint32_t reg = 0;
5481 int ext_mdio = 0;
5482
5483 DEBUGFUNC("em_sgmii_uses_mdio_82575");;
5484
5485 switch (hw->mac_type) {
5486 case em_82575:
5487 case em_82576:
5488 reg = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020)))))
;
5489 ext_mdio = !!(reg & E1000_MDIC_DEST0x80000000);
5490 break;
5491 case em_82580:
5492 case em_i350:
5493 case em_i210:
5494 reg = E1000_READ_REG(hw, MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E04 : em_translate_82542_register
(0x00E04)))))
;
5495 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO0x80000000);
5496 break;
5497 default:
5498 break;
5499 }
5500 return ext_mdio;
5501}
5502
5503/**
5504 * em_read_phy_reg_i2c - Read PHY register using i2c
5505 * @hw: pointer to the HW structure
5506 * @offset: register offset to be read
5507 * @data: pointer to the read data
5508 *
5509 * Reads the PHY register at offset using the i2c interface and stores the
5510 * retrieved information in data.
5511 **/
5512int32_t em_read_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t *data)
5513{
5514 uint32_t i, i2ccmd = 0;
5515
5516 DEBUGFUNC("em_read_phy_reg_i2c");;
5517
5518 /* Set up Op-code, Phy Address, and register address in the I2CCMD
5519 * register. The MAC will take care of interfacing with the
5520 * PHY to retrieve the desired data.
5521 */
5522 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT16) |
5523 (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT24) |
5524 (E1000_I2CCMD_OPCODE_READ0x08000000));
5525
5526 E1000_WRITE_REG(hw, I2CCMD, i2ccmd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028))), (i2ccmd)))
;
5527
5528 /* Poll the ready bit to see if the I2C read completed */
5529 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT200; i++) {
5530 usec_delay(50)(*delay_func)(50);
5531 i2ccmd = E1000_READ_REG(hw, I2CCMD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028)))))
;
5532 if (i2ccmd & E1000_I2CCMD_READY0x20000000)
5533 break;
5534 }
5535 if (!(i2ccmd & E1000_I2CCMD_READY0x20000000)) {
5536 DEBUGOUT("I2CCMD Read did not complete\n");
5537 return -E1000_ERR_PHY2;
5538 }
5539 if (i2ccmd & E1000_I2CCMD_ERROR0x80000000) {
5540 DEBUGOUT("I2CCMD Error bit set\n");
5541 return -E1000_ERR_PHY2;
5542 }
5543
5544 /* Need to byte-swap the 16-bit value. */
5545 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
5546
5547 return E1000_SUCCESS0;
5548}
5549
5550/**
5551 * em_write_phy_reg_i2c - Write PHY register using i2c
5552 * @hw: pointer to the HW structure
5553 * @offset: register offset to write to
5554 * @data: data to write at register offset
5555 *
5556 * Writes the data to PHY register at the offset using the i2c interface.
5557 **/
5558int32_t em_write_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t data)
5559{
5560 uint32_t i, i2ccmd = 0;
5561 uint16_t phy_data_swapped;
5562
5563 DEBUGFUNC("em_write_phy_reg_i2c");;
5564
5565 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
5566 if ((hw->phy_addr == 0) || (hw->phy_addr > 7)) {
5567 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
5568 hw->phy_addr);
5569 return -E1000_ERR_CONFIG3;
5570 }
5571
5572 /* Swap the data bytes for the I2C interface */
5573 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
5574
5575 /* Set up Op-code, Phy Address, and register address in the I2CCMD
5576 * register. The MAC will take care of interfacing with the
5577 * PHY to retrieve the desired data.
5578 */
5579 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT16) |
5580 (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT24) |
5581 E1000_I2CCMD_OPCODE_WRITE0x00000000 |
5582 phy_data_swapped);
5583
5584 E1000_WRITE_REG(hw, I2CCMD, i2ccmd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028))), (i2ccmd)))
;
5585
5586 /* Poll the ready bit to see if the I2C read completed */
5587 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT200; i++) {
5588 usec_delay(50)(*delay_func)(50);
5589 i2ccmd = E1000_READ_REG(hw, I2CCMD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028)))))
;
5590 if (i2ccmd & E1000_I2CCMD_READY0x20000000)
5591 break;
5592 }
5593 if (!(i2ccmd & E1000_I2CCMD_READY0x20000000)) {
5594 DEBUGOUT("I2CCMD Write did not complete\n");
5595 return -E1000_ERR_PHY2;
5596 }
5597 if (i2ccmd & E1000_I2CCMD_ERROR0x80000000) {
5598 DEBUGOUT("I2CCMD Error bit set\n");
5599 return -E1000_ERR_PHY2;
5600 }
5601
5602 return E1000_SUCCESS0;
5603}
5604
5605/**
5606 * em_read_sfp_data_byte - Reads SFP module data.
5607 * @hw: pointer to the HW structure
5608 * @offset: byte location offset to be read
5609 * @data: read data buffer pointer
5610 *
5611 * Reads one byte from SFP module data stored
5612 * in SFP resided EEPROM memory or SFP diagnostic area.
5613 * Function should be called with
5614 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
5615 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
5616 * access
5617 **/
5618int32_t em_read_sfp_data_byte(struct em_hw *hw, uint16_t offset, uint8_t *data)
5619{
5620 uint32_t i = 0;
5621 uint32_t i2ccmd = 0;
5622 uint32_t data_local = 0;
5623
5624 DEBUGFUNC("em_read_sfp_data_byte");;
5625
5626 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)(0x0100 + (255))) {
5627 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
5628 return -E1000_ERR_PHY2;
5629 }
5630
5631 /* Set up Op-code, EEPROM Address,in the I2CCMD
5632 * register. The MAC will take care of interfacing with the
5633 * EEPROM to retrieve the desired data.
5634 */
5635 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT16) |
5636 E1000_I2CCMD_OPCODE_READ0x08000000);
5637
5638 E1000_WRITE_REG(hw, I2CCMD, i2ccmd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028))), (i2ccmd)))
;
5639
5640 /* Poll the ready bit to see if the I2C read completed */
5641 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT200; i++) {
5642 usec_delay(50)(*delay_func)(50);
5643 data_local = E1000_READ_REG(hw, I2CCMD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028)))))
;
5644 if (data_local & E1000_I2CCMD_READY0x20000000)
5645 break;
5646 }
5647 if (!(data_local & E1000_I2CCMD_READY0x20000000)) {
5648 DEBUGOUT("I2CCMD Read did not complete\n");
5649 return -E1000_ERR_PHY2;
5650 }
5651 if (data_local & E1000_I2CCMD_ERROR0x80000000) {
5652 DEBUGOUT("I2CCMD Error bit set\n");
5653 return -E1000_ERR_PHY2;
5654 }
5655 *data = (uint8_t) data_local & 0xFF;
5656
5657 return E1000_SUCCESS0;
5658}
5659
5660/******************************************************************************
5661 * Returns the PHY to the power-on reset state
5662 *
5663 * hw - Struct containing variables accessed by shared code
5664 *****************************************************************************/
5665int32_t
5666em_phy_hw_reset(struct em_hw *hw)
5667{
5668 uint32_t ctrl, ctrl_ext;
5669 uint32_t led_ctrl;
5670 int32_t ret_val;
5671 DEBUGFUNC("em_phy_hw_reset");;
5672 /*
5673 * In the case of the phy reset being blocked, it's not an error, we
5674 * simply return success without performing the reset.
5675 */
5676 ret_val = em_check_phy_reset_block(hw);
5677 if (ret_val)
5678 return E1000_SUCCESS0;
5679
5680 DEBUGOUT("Resetting Phy...\n");
5681
5682 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) {
5683 if (em_swfw_sync_acquire(hw, hw->swfw)) {
5684 DEBUGOUT("Unable to acquire swfw sync\n");
5685 return -E1000_ERR_SWFW_SYNC13;
5686 }
5687 /*
5688 * Read the device control register and assert the
5689 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For
5690 * pre-em_82571 hardware, we delay for 10ms between the
5691 * assert and deassert. For em_82571 hardware and later, we
5692 * instead delay for 50us between and 10ms after the
5693 * deassertion.
5694 */