Bug Summary

File:dev/pci/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
Warning:line 1312, column 3
Value stored to 'value0' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name dcn10_link_encoder.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/delay.h>
27#include <linux/slab.h>
28
29#include "reg_helper.h"
30
31#include "core_types.h"
32#include "link_encoder.h"
33#include "dcn10_link_encoder.h"
34#include "stream_encoder.h"
35#include "i2caux_interface.h"
36#include "dc_bios_types.h"
37
38#include "gpio_service_interface.h"
39
40#define CTXenc10->base.ctx \
41 enc10->base.ctx
42#define DC_LOGGERenc10->base.ctx->logger \
43 enc10->base.ctx->logger
44
45#define REG(reg)(enc10->link_regs->reg)\
46 (enc10->link_regs->reg)
47
48#undef FN
49#define FN(reg_name, field_name)enc10->link_shift->field_name, enc10->link_mask->
field_name \
50 enc10->link_shift->field_name, enc10->link_mask->field_name
51
52
53/*
54 * @brief
55 * Trigger Source Select
56 * ASIC-dependent, actual values for register programming
57 */
58#define DCN10_DIG_FE_SOURCE_SELECT_INVALID0x0 0x0
59#define DCN10_DIG_FE_SOURCE_SELECT_DIGA0x1 0x1
60#define DCN10_DIG_FE_SOURCE_SELECT_DIGB0x2 0x2
61#define DCN10_DIG_FE_SOURCE_SELECT_DIGC0x4 0x4
62#define DCN10_DIG_FE_SOURCE_SELECT_DIGD0x08 0x08
63#define DCN10_DIG_FE_SOURCE_SELECT_DIGE0x10 0x10
64#define DCN10_DIG_FE_SOURCE_SELECT_DIGF0x20 0x20
65#define DCN10_DIG_FE_SOURCE_SELECT_DIGG0x40 0x40
66
67enum {
68 DP_MST_UPDATE_MAX_RETRY = 50
69};
70
71static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
72 .validate_output_with_stream =
73 dcn10_link_encoder_validate_output_with_stream,
74 .hw_init = dcn10_link_encoder_hw_init,
75 .setup = dcn10_link_encoder_setup,
76 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
77 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
78 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
79 .disable_output = dcn10_link_encoder_disable_output,
80 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
81 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
82 .update_mst_stream_allocation_table =
83 dcn10_link_encoder_update_mst_stream_allocation_table,
84 .psr_program_dp_dphy_fast_training =
85 dcn10_psr_program_dp_dphy_fast_training,
86 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
87 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
88 .enable_hpd = dcn10_link_encoder_enable_hpd,
89 .disable_hpd = dcn10_link_encoder_disable_hpd,
90 .is_dig_enabled = dcn10_is_dig_enabled,
91 .get_dig_frontend = dcn10_get_dig_frontend,
92 .get_dig_mode = dcn10_get_dig_mode,
93 .destroy = dcn10_link_encoder_destroy,
94 .get_max_link_cap = dcn10_link_encoder_get_max_link_cap,
95};
96
97static enum bp_result link_transmitter_control(
98 struct dcn10_link_encoder *enc10,
99 struct bp_transmitter_control *cntl)
100{
101 enum bp_result result;
102 struct dc_bios *bp = enc10->base.ctx->dc_bios;
103
104 result = bp->funcs->transmitter_control(bp, cntl);
105
106 return result;
107}
108
109static void enable_phy_bypass_mode(
110 struct dcn10_link_encoder *enc10,
111 bool_Bool enable)
112{
113 /* This register resides in DP back end block;
114 * transmitter is used for the offset
115 */
116 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_CNTL), 1, enc10->link_shift->DPHY_BYPASS, enc10
->link_mask->DPHY_BYPASS, enable);
117
118}
119
120static void disable_prbs_symbols(
121 struct dcn10_link_encoder *enc10,
122 bool_Bool disable)
123{
124 /* This register resides in DP back end block;
125 * transmitter is used for the offset
126 */
127 REG_UPDATE_4(DP_DPHY_CNTL,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_CNTL), 4, enc10->link_shift->DPHY_ATEST_SEL_LANE0
, enc10->link_mask->DPHY_ATEST_SEL_LANE0, disable, enc10
->link_shift->DPHY_ATEST_SEL_LANE1, enc10->link_mask
->DPHY_ATEST_SEL_LANE1, disable, enc10->link_shift->
DPHY_ATEST_SEL_LANE2, enc10->link_mask->DPHY_ATEST_SEL_LANE2
, disable, enc10->link_shift->DPHY_ATEST_SEL_LANE3, enc10
->link_mask->DPHY_ATEST_SEL_LANE3, disable)
128 DPHY_ATEST_SEL_LANE0, disable,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_CNTL), 4, enc10->link_shift->DPHY_ATEST_SEL_LANE0
, enc10->link_mask->DPHY_ATEST_SEL_LANE0, disable, enc10
->link_shift->DPHY_ATEST_SEL_LANE1, enc10->link_mask
->DPHY_ATEST_SEL_LANE1, disable, enc10->link_shift->
DPHY_ATEST_SEL_LANE2, enc10->link_mask->DPHY_ATEST_SEL_LANE2
, disable, enc10->link_shift->DPHY_ATEST_SEL_LANE3, enc10
->link_mask->DPHY_ATEST_SEL_LANE3, disable)
129 DPHY_ATEST_SEL_LANE1, disable,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_CNTL), 4, enc10->link_shift->DPHY_ATEST_SEL_LANE0
, enc10->link_mask->DPHY_ATEST_SEL_LANE0, disable, enc10
->link_shift->DPHY_ATEST_SEL_LANE1, enc10->link_mask
->DPHY_ATEST_SEL_LANE1, disable, enc10->link_shift->
DPHY_ATEST_SEL_LANE2, enc10->link_mask->DPHY_ATEST_SEL_LANE2
, disable, enc10->link_shift->DPHY_ATEST_SEL_LANE3, enc10
->link_mask->DPHY_ATEST_SEL_LANE3, disable)
130 DPHY_ATEST_SEL_LANE2, disable,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_CNTL), 4, enc10->link_shift->DPHY_ATEST_SEL_LANE0
, enc10->link_mask->DPHY_ATEST_SEL_LANE0, disable, enc10
->link_shift->DPHY_ATEST_SEL_LANE1, enc10->link_mask
->DPHY_ATEST_SEL_LANE1, disable, enc10->link_shift->
DPHY_ATEST_SEL_LANE2, enc10->link_mask->DPHY_ATEST_SEL_LANE2
, disable, enc10->link_shift->DPHY_ATEST_SEL_LANE3, enc10
->link_mask->DPHY_ATEST_SEL_LANE3, disable)
131 DPHY_ATEST_SEL_LANE3, disable)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_CNTL), 4, enc10->link_shift->DPHY_ATEST_SEL_LANE0
, enc10->link_mask->DPHY_ATEST_SEL_LANE0, disable, enc10
->link_shift->DPHY_ATEST_SEL_LANE1, enc10->link_mask
->DPHY_ATEST_SEL_LANE1, disable, enc10->link_shift->
DPHY_ATEST_SEL_LANE2, enc10->link_mask->DPHY_ATEST_SEL_LANE2
, disable, enc10->link_shift->DPHY_ATEST_SEL_LANE3, enc10
->link_mask->DPHY_ATEST_SEL_LANE3, disable);
132}
133
134static void disable_prbs_mode(
135 struct dcn10_link_encoder *enc10)
136{
137 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_PRBS_CNTL), 1, enc10->link_shift->DPHY_PRBS_EN
, enc10->link_mask->DPHY_PRBS_EN, 0);
138}
139
140static void program_pattern_symbols(
141 struct dcn10_link_encoder *enc10,
142 uint16_t pattern_symbols[8])
143{
144 /* This register resides in DP back end block;
145 * transmitter is used for the offset
146 */
147 REG_SET_3(DP_DPHY_SYM0, 0,generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM0), 0, 3, enc10->link_shift->DPHY_SYM1, enc10
->link_mask->DPHY_SYM1, pattern_symbols[0], enc10->link_shift
->DPHY_SYM2, enc10->link_mask->DPHY_SYM2, pattern_symbols
[1], enc10->link_shift->DPHY_SYM3, enc10->link_mask->
DPHY_SYM3, pattern_symbols[2])
148 DPHY_SYM1, pattern_symbols[0],generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM0), 0, 3, enc10->link_shift->DPHY_SYM1, enc10
->link_mask->DPHY_SYM1, pattern_symbols[0], enc10->link_shift
->DPHY_SYM2, enc10->link_mask->DPHY_SYM2, pattern_symbols
[1], enc10->link_shift->DPHY_SYM3, enc10->link_mask->
DPHY_SYM3, pattern_symbols[2])
149 DPHY_SYM2, pattern_symbols[1],generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM0), 0, 3, enc10->link_shift->DPHY_SYM1, enc10
->link_mask->DPHY_SYM1, pattern_symbols[0], enc10->link_shift
->DPHY_SYM2, enc10->link_mask->DPHY_SYM2, pattern_symbols
[1], enc10->link_shift->DPHY_SYM3, enc10->link_mask->
DPHY_SYM3, pattern_symbols[2])
150 DPHY_SYM3, pattern_symbols[2])generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM0), 0, 3, enc10->link_shift->DPHY_SYM1, enc10
->link_mask->DPHY_SYM1, pattern_symbols[0], enc10->link_shift
->DPHY_SYM2, enc10->link_mask->DPHY_SYM2, pattern_symbols
[1], enc10->link_shift->DPHY_SYM3, enc10->link_mask->
DPHY_SYM3, pattern_symbols[2]);
151
152 /* This register resides in DP back end block;
153 * transmitter is used for the offset
154 */
155 REG_SET_3(DP_DPHY_SYM1, 0,generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM1), 0, 3, enc10->link_shift->DPHY_SYM4, enc10
->link_mask->DPHY_SYM4, pattern_symbols[3], enc10->link_shift
->DPHY_SYM5, enc10->link_mask->DPHY_SYM5, pattern_symbols
[4], enc10->link_shift->DPHY_SYM6, enc10->link_mask->
DPHY_SYM6, pattern_symbols[5])
156 DPHY_SYM4, pattern_symbols[3],generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM1), 0, 3, enc10->link_shift->DPHY_SYM4, enc10
->link_mask->DPHY_SYM4, pattern_symbols[3], enc10->link_shift
->DPHY_SYM5, enc10->link_mask->DPHY_SYM5, pattern_symbols
[4], enc10->link_shift->DPHY_SYM6, enc10->link_mask->
DPHY_SYM6, pattern_symbols[5])
157 DPHY_SYM5, pattern_symbols[4],generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM1), 0, 3, enc10->link_shift->DPHY_SYM4, enc10
->link_mask->DPHY_SYM4, pattern_symbols[3], enc10->link_shift
->DPHY_SYM5, enc10->link_mask->DPHY_SYM5, pattern_symbols
[4], enc10->link_shift->DPHY_SYM6, enc10->link_mask->
DPHY_SYM6, pattern_symbols[5])
158 DPHY_SYM6, pattern_symbols[5])generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM1), 0, 3, enc10->link_shift->DPHY_SYM4, enc10
->link_mask->DPHY_SYM4, pattern_symbols[3], enc10->link_shift
->DPHY_SYM5, enc10->link_mask->DPHY_SYM5, pattern_symbols
[4], enc10->link_shift->DPHY_SYM6, enc10->link_mask->
DPHY_SYM6, pattern_symbols[5]);
159
160 /* This register resides in DP back end block;
161 * transmitter is used for the offset
162 */
163 REG_SET_2(DP_DPHY_SYM2, 0,generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM2), 0, 2, enc10->link_shift->DPHY_SYM7, enc10
->link_mask->DPHY_SYM7, pattern_symbols[6], enc10->link_shift
->DPHY_SYM8, enc10->link_mask->DPHY_SYM8, pattern_symbols
[7])
164 DPHY_SYM7, pattern_symbols[6],generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM2), 0, 2, enc10->link_shift->DPHY_SYM7, enc10
->link_mask->DPHY_SYM7, pattern_symbols[6], enc10->link_shift
->DPHY_SYM8, enc10->link_mask->DPHY_SYM8, pattern_symbols
[7])
165 DPHY_SYM8, pattern_symbols[7])generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_SYM2), 0, 2, enc10->link_shift->DPHY_SYM7, enc10
->link_mask->DPHY_SYM7, pattern_symbols[6], enc10->link_shift
->DPHY_SYM8, enc10->link_mask->DPHY_SYM8, pattern_symbols
[7]);
166}
167
168static void set_dp_phy_pattern_d102(
169 struct dcn10_link_encoder *enc10)
170{
171 /* Disable PHY Bypass mode to setup the test pattern */
172 enable_phy_bypass_mode(enc10, false0);
173
174 /* For 10-bit PRBS or debug symbols
175 * please use the following sequence:
176 *
177 * Enable debug symbols on the lanes
178 */
179 disable_prbs_symbols(enc10, true1);
180
181 /* Disable PRBS mode */
182 disable_prbs_mode(enc10);
183
184 /* Program debug symbols to be output */
185 {
186 uint16_t pattern_symbols[8] = {
187 0x2AA, 0x2AA, 0x2AA, 0x2AA,
188 0x2AA, 0x2AA, 0x2AA, 0x2AA
189 };
190
191 program_pattern_symbols(enc10, pattern_symbols);
192 }
193
194 /* Enable phy bypass mode to enable the test pattern */
195
196 enable_phy_bypass_mode(enc10, true1);
197}
198
199static void set_link_training_complete(
200 struct dcn10_link_encoder *enc10,
201 bool_Bool complete)
202{
203 /* This register resides in DP back end block;
204 * transmitter is used for the offset
205 */
206 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_CNTL), 1, enc10->link_shift->DP_LINK_TRAINING_COMPLETE
, enc10->link_mask->DP_LINK_TRAINING_COMPLETE, complete
);
207
208}
209
210void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
211 struct link_encoder *enc,
212 uint32_t index)
213{
214 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
215 /* Write Training Pattern */
216
217 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index)dm_write_reg_func(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_TRAINING_PATTERN_SEL), index, __func__);
218
219 /* Set HW Register Training Complete to false */
220
221 set_link_training_complete(enc10, false0);
222
223 /* Disable PHY Bypass mode to output Training Pattern */
224
225 enable_phy_bypass_mode(enc10, false0);
226
227 /* Disable PRBS mode */
228 disable_prbs_mode(enc10);
229}
230
231static void setup_panel_mode(
232 struct dcn10_link_encoder *enc10,
233 enum dp_panel_mode panel_mode)
234{
235 uint32_t value;
236
237 if (!REG(DP_DPHY_INTERNAL_CTRL)(enc10->link_regs->DP_DPHY_INTERNAL_CTRL))
238 return;
239
240 value = REG_READ(DP_DPHY_INTERNAL_CTRL)dm_read_reg_func(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_INTERNAL_CTRL), __func__);
241
242 switch (panel_mode) {
243 case DP_PANEL_MODE_EDP:
244 value = 0x1;
245 break;
246 case DP_PANEL_MODE_SPECIAL:
247 value = 0x11;
248 break;
249 default:
250 value = 0x0;
251 break;
252 }
253
254 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value)dm_write_reg_func(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_INTERNAL_CTRL), value, __func__);
255}
256
257static void set_dp_phy_pattern_symbol_error(
258 struct dcn10_link_encoder *enc10)
259{
260 /* Disable PHY Bypass mode to setup the test pattern */
261 enable_phy_bypass_mode(enc10, false0);
262
263 /* program correct panel mode*/
264 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
265
266 /* A PRBS23 pattern is used for most DP electrical measurements. */
267
268 /* Enable PRBS symbols on the lanes */
269 disable_prbs_symbols(enc10, false0);
270
271 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
272 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_PRBS_CNTL), 2, enc10->link_shift->DPHY_PRBS_SEL
, enc10->link_mask->DPHY_PRBS_SEL, 1, enc10->link_shift
->DPHY_PRBS_EN, enc10->link_mask->DPHY_PRBS_EN, 1)
273 DPHY_PRBS_SEL, 1,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_PRBS_CNTL), 2, enc10->link_shift->DPHY_PRBS_SEL
, enc10->link_mask->DPHY_PRBS_SEL, 1, enc10->link_shift
->DPHY_PRBS_EN, enc10->link_mask->DPHY_PRBS_EN, 1)
274 DPHY_PRBS_EN, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_PRBS_CNTL), 2, enc10->link_shift->DPHY_PRBS_SEL
, enc10->link_mask->DPHY_PRBS_SEL, 1, enc10->link_shift
->DPHY_PRBS_EN, enc10->link_mask->DPHY_PRBS_EN, 1);
275
276 /* Enable phy bypass mode to enable the test pattern */
277 enable_phy_bypass_mode(enc10, true1);
278}
279
280static void set_dp_phy_pattern_prbs7(
281 struct dcn10_link_encoder *enc10)
282{
283 /* Disable PHY Bypass mode to setup the test pattern */
284 enable_phy_bypass_mode(enc10, false0);
285
286 /* A PRBS7 pattern is used for most DP electrical measurements. */
287
288 /* Enable PRBS symbols on the lanes */
289 disable_prbs_symbols(enc10, false0);
290
291 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
292 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_PRBS_CNTL), 2, enc10->link_shift->DPHY_PRBS_SEL
, enc10->link_mask->DPHY_PRBS_SEL, 0, enc10->link_shift
->DPHY_PRBS_EN, enc10->link_mask->DPHY_PRBS_EN, 1)
293 DPHY_PRBS_SEL, 0,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_PRBS_CNTL), 2, enc10->link_shift->DPHY_PRBS_SEL
, enc10->link_mask->DPHY_PRBS_SEL, 0, enc10->link_shift
->DPHY_PRBS_EN, enc10->link_mask->DPHY_PRBS_EN, 1)
294 DPHY_PRBS_EN, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_PRBS_CNTL), 2, enc10->link_shift->DPHY_PRBS_SEL
, enc10->link_mask->DPHY_PRBS_SEL, 0, enc10->link_shift
->DPHY_PRBS_EN, enc10->link_mask->DPHY_PRBS_EN, 1);
295
296 /* Enable phy bypass mode to enable the test pattern */
297 enable_phy_bypass_mode(enc10, true1);
298}
299
300static void set_dp_phy_pattern_80bit_custom(
301 struct dcn10_link_encoder *enc10,
302 const uint8_t *pattern)
303{
304 /* Disable PHY Bypass mode to setup the test pattern */
305 enable_phy_bypass_mode(enc10, false0);
306
307 /* Enable debug symbols on the lanes */
308
309 disable_prbs_symbols(enc10, true1);
310
311 /* Enable PHY bypass mode to enable the test pattern */
312 /* TODO is it really needed ? */
313
314 enable_phy_bypass_mode(enc10, true1);
315
316 /* Program 80 bit custom pattern */
317 {
318 uint16_t pattern_symbols[8];
319
320 pattern_symbols[0] =
321 ((pattern[1] & 0x03) << 8) | pattern[0];
322 pattern_symbols[1] =
323 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
324 pattern_symbols[2] =
325 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
326 pattern_symbols[3] =
327 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
328 pattern_symbols[4] =
329 ((pattern[6] & 0x03) << 8) | pattern[5];
330 pattern_symbols[5] =
331 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
332 pattern_symbols[6] =
333 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
334 pattern_symbols[7] =
335 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
336
337 program_pattern_symbols(enc10, pattern_symbols);
338 }
339
340 /* Enable phy bypass mode to enable the test pattern */
341
342 enable_phy_bypass_mode(enc10, true1);
343}
344
345static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
346 struct dcn10_link_encoder *enc10,
347 unsigned int cp2520_pattern)
348{
349
350 /* previously there is a register DP_HBR2_EYE_PATTERN
351 * that is enabled to get the pattern.
352 * But it does not work with the latest spec change,
353 * so we are programming the following registers manually.
354 *
355 * The following settings have been confirmed
356 * by Nick Chorney and Sandra Liu
357 */
358
359 /* Disable PHY Bypass mode to setup the test pattern */
360
361 enable_phy_bypass_mode(enc10, false0);
362
363 /* Setup DIG encoder in DP SST mode */
364 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
365
366 /* ensure normal panel mode. */
367 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
368
369 /* no vbid after BS (SR)
370 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
371 * 11000260 / 11000104 / 110000FC
372 */
373 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_FRAMING_CNTL), 3, enc10->link_shift->DP_IDLE_BS_INTERVAL
, enc10->link_mask->DP_IDLE_BS_INTERVAL, 0xFC, enc10->
link_shift->DP_VBID_DISABLE, enc10->link_mask->DP_VBID_DISABLE
, 1, enc10->link_shift->DP_VID_ENHANCED_FRAME_MODE, enc10
->link_mask->DP_VID_ENHANCED_FRAME_MODE, 1)
374 DP_IDLE_BS_INTERVAL, 0xFC,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_FRAMING_CNTL), 3, enc10->link_shift->DP_IDLE_BS_INTERVAL
, enc10->link_mask->DP_IDLE_BS_INTERVAL, 0xFC, enc10->
link_shift->DP_VBID_DISABLE, enc10->link_mask->DP_VBID_DISABLE
, 1, enc10->link_shift->DP_VID_ENHANCED_FRAME_MODE, enc10
->link_mask->DP_VID_ENHANCED_FRAME_MODE, 1)
375 DP_VBID_DISABLE, 1,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_FRAMING_CNTL), 3, enc10->link_shift->DP_IDLE_BS_INTERVAL
, enc10->link_mask->DP_IDLE_BS_INTERVAL, 0xFC, enc10->
link_shift->DP_VBID_DISABLE, enc10->link_mask->DP_VBID_DISABLE
, 1, enc10->link_shift->DP_VID_ENHANCED_FRAME_MODE, enc10
->link_mask->DP_VID_ENHANCED_FRAME_MODE, 1)
376 DP_VID_ENHANCED_FRAME_MODE, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_FRAMING_CNTL), 3, enc10->link_shift->DP_IDLE_BS_INTERVAL
, enc10->link_mask->DP_IDLE_BS_INTERVAL, 0xFC, enc10->
link_shift->DP_VBID_DISABLE, enc10->link_mask->DP_VBID_DISABLE
, 1, enc10->link_shift->DP_VID_ENHANCED_FRAME_MODE, enc10
->link_mask->DP_VID_ENHANCED_FRAME_MODE, 1);
377
378 /* swap every BS with SR */
379 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_SCRAM_CNTL), 1, enc10->link_shift->DPHY_SCRAMBLER_BS_COUNT
, enc10->link_mask->DPHY_SCRAMBLER_BS_COUNT, 0);
380
381 /* select cp2520 patterns */
382 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)(enc10->link_regs->DP_DPHY_HBR2_PATTERN_CONTROL))
383 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_HBR2_PATTERN_CONTROL), 1, enc10->link_shift->
DP_DPHY_HBR2_PATTERN_CONTROL, enc10->link_mask->DP_DPHY_HBR2_PATTERN_CONTROL
, cp2520_pattern)
384 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_HBR2_PATTERN_CONTROL), 1, enc10->link_shift->
DP_DPHY_HBR2_PATTERN_CONTROL, enc10->link_mask->DP_DPHY_HBR2_PATTERN_CONTROL
, cp2520_pattern);
385 else
386 /* pre-DCE11 can only generate CP2520 pattern 2 */
387 ASSERT(cp2520_pattern == 2)do { if (({ static int __warned; int __ret = !!(!(cp2520_pattern
== 2)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(cp2520_pattern == 2)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_link_encoder.c"
, 387); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
388
389 /* set link training complete */
390 set_link_training_complete(enc10, true1);
391
392 /* disable video stream */
393 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_VID_STREAM_CNTL), 1, enc10->link_shift->DP_VID_STREAM_ENABLE
, enc10->link_mask->DP_VID_STREAM_ENABLE, 0);
394
395 /* Disable PHY Bypass mode to setup the test pattern */
396 enable_phy_bypass_mode(enc10, false0);
397}
398
399static void set_dp_phy_pattern_passthrough_mode(
400 struct dcn10_link_encoder *enc10,
401 enum dp_panel_mode panel_mode)
402{
403 /* program correct panel mode */
404 setup_panel_mode(enc10, panel_mode);
405
406 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
407 * in case we were doing HBR2 compliance pattern before
408 */
409 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_FRAMING_CNTL), 3, enc10->link_shift->DP_IDLE_BS_INTERVAL
, enc10->link_mask->DP_IDLE_BS_INTERVAL, 0x2000, enc10->
link_shift->DP_VBID_DISABLE, enc10->link_mask->DP_VBID_DISABLE
, 0, enc10->link_shift->DP_VID_ENHANCED_FRAME_MODE, enc10
->link_mask->DP_VID_ENHANCED_FRAME_MODE, 1)
410 DP_IDLE_BS_INTERVAL, 0x2000,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_FRAMING_CNTL), 3, enc10->link_shift->DP_IDLE_BS_INTERVAL
, enc10->link_mask->DP_IDLE_BS_INTERVAL, 0x2000, enc10->
link_shift->DP_VBID_DISABLE, enc10->link_mask->DP_VBID_DISABLE
, 0, enc10->link_shift->DP_VID_ENHANCED_FRAME_MODE, enc10
->link_mask->DP_VID_ENHANCED_FRAME_MODE, 1)
411 DP_VBID_DISABLE, 0,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_FRAMING_CNTL), 3, enc10->link_shift->DP_IDLE_BS_INTERVAL
, enc10->link_mask->DP_IDLE_BS_INTERVAL, 0x2000, enc10->
link_shift->DP_VBID_DISABLE, enc10->link_mask->DP_VBID_DISABLE
, 0, enc10->link_shift->DP_VID_ENHANCED_FRAME_MODE, enc10
->link_mask->DP_VID_ENHANCED_FRAME_MODE, 1)
412 DP_VID_ENHANCED_FRAME_MODE, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_FRAMING_CNTL), 3, enc10->link_shift->DP_IDLE_BS_INTERVAL
, enc10->link_mask->DP_IDLE_BS_INTERVAL, 0x2000, enc10->
link_shift->DP_VBID_DISABLE, enc10->link_mask->DP_VBID_DISABLE
, 0, enc10->link_shift->DP_VID_ENHANCED_FRAME_MODE, enc10
->link_mask->DP_VID_ENHANCED_FRAME_MODE, 1);
413
414 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_SCRAM_CNTL), 1, enc10->link_shift->DPHY_SCRAMBLER_BS_COUNT
, enc10->link_mask->DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
415
416 /* set link training complete */
417 set_link_training_complete(enc10, true1);
418
419 /* Disable PHY Bypass mode to setup the test pattern */
420 enable_phy_bypass_mode(enc10, false0);
421
422 /* Disable PRBS mode */
423 disable_prbs_mode(enc10);
424}
425
426/* return value is bit-vector */
427static uint8_t get_frontend_source(
428 enum engine_id engine)
429{
430 switch (engine) {
431 case ENGINE_ID_DIGA:
432 return DCN10_DIG_FE_SOURCE_SELECT_DIGA0x1;
433 case ENGINE_ID_DIGB:
434 return DCN10_DIG_FE_SOURCE_SELECT_DIGB0x2;
435 case ENGINE_ID_DIGC:
436 return DCN10_DIG_FE_SOURCE_SELECT_DIGC0x4;
437 case ENGINE_ID_DIGD:
438 return DCN10_DIG_FE_SOURCE_SELECT_DIGD0x08;
439 case ENGINE_ID_DIGE:
440 return DCN10_DIG_FE_SOURCE_SELECT_DIGE0x10;
441 case ENGINE_ID_DIGF:
442 return DCN10_DIG_FE_SOURCE_SELECT_DIGF0x20;
443 case ENGINE_ID_DIGG:
444 return DCN10_DIG_FE_SOURCE_SELECT_DIGG0x40;
445 default:
446 ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_link_encoder.c"
, 446); __builtin_expect(!!(__ret), 0); })) do {} while (0); }
while (0);
447 return DCN10_DIG_FE_SOURCE_SELECT_INVALID0x0;
448 }
449}
450
451unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
452{
453 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
454 int32_t value;
455 enum engine_id result;
456
457 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value)generic_reg_get(enc10->base.ctx, (enc10->link_regs->
DIG_BE_CNTL), enc10->link_shift->DIG_FE_SOURCE_SELECT, enc10
->link_mask->DIG_FE_SOURCE_SELECT, &value);
458
459 switch (value) {
460 case DCN10_DIG_FE_SOURCE_SELECT_DIGA0x1:
461 result = ENGINE_ID_DIGA;
462 break;
463 case DCN10_DIG_FE_SOURCE_SELECT_DIGB0x2:
464 result = ENGINE_ID_DIGB;
465 break;
466 case DCN10_DIG_FE_SOURCE_SELECT_DIGC0x4:
467 result = ENGINE_ID_DIGC;
468 break;
469 case DCN10_DIG_FE_SOURCE_SELECT_DIGD0x08:
470 result = ENGINE_ID_DIGD;
471 break;
472 case DCN10_DIG_FE_SOURCE_SELECT_DIGE0x10:
473 result = ENGINE_ID_DIGE;
474 break;
475 case DCN10_DIG_FE_SOURCE_SELECT_DIGF0x20:
476 result = ENGINE_ID_DIGF;
477 break;
478 case DCN10_DIG_FE_SOURCE_SELECT_DIGG0x40:
479 result = ENGINE_ID_DIGG;
480 break;
481 default:
482 // invalid source select DIG
483 result = ENGINE_ID_UNKNOWN;
484 }
485
486 return result;
487
488}
489
490void enc1_configure_encoder(
491 struct dcn10_link_encoder *enc10,
492 const struct dc_link_settings *link_settings)
493{
494 /* set number of lanes */
495 REG_SET(DP_CONFIG, 0,generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_CONFIG), 0, 1, enc10->link_shift->DP_UDI_LANES, enc10
->link_mask->DP_UDI_LANES, link_settings->lane_count
- LANE_COUNT_ONE)
496 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE)generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_CONFIG), 0, 1, enc10->link_shift->DP_UDI_LANES, enc10
->link_mask->DP_UDI_LANES, link_settings->lane_count
- LANE_COUNT_ONE);
497
498 /* setup scrambler */
499 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_SCRAM_CNTL), 1, enc10->link_shift->DPHY_SCRAMBLER_ADVANCE
, enc10->link_mask->DPHY_SCRAMBLER_ADVANCE, 1);
500}
501
502void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
503 bool_Bool exit_link_training_required)
504{
505 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
506
507 if (exit_link_training_required)
508 REG_UPDATE(DP_DPHY_FAST_TRAINING,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_FAST_TRAINING), 1, enc10->link_shift->DPHY_RX_FAST_TRAINING_CAPABLE
, enc10->link_mask->DPHY_RX_FAST_TRAINING_CAPABLE, 1)
509 DPHY_RX_FAST_TRAINING_CAPABLE, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_FAST_TRAINING), 1, enc10->link_shift->DPHY_RX_FAST_TRAINING_CAPABLE
, enc10->link_mask->DPHY_RX_FAST_TRAINING_CAPABLE, 1);
510 else {
511 REG_UPDATE(DP_DPHY_FAST_TRAINING,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_FAST_TRAINING), 1, enc10->link_shift->DPHY_RX_FAST_TRAINING_CAPABLE
, enc10->link_mask->DPHY_RX_FAST_TRAINING_CAPABLE, 0)
512 DPHY_RX_FAST_TRAINING_CAPABLE, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_FAST_TRAINING), 1, enc10->link_shift->DPHY_RX_FAST_TRAINING_CAPABLE
, enc10->link_mask->DPHY_RX_FAST_TRAINING_CAPABLE, 0);
513 /*In DCE 11, we are able to pre-program a Force SR register
514 * to be able to trigger SR symbol after 5 idle patterns
515 * transmitted. Upon PSR Exit, DMCU can trigger
516 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
517 * DPHY_LOAD_BS_COUNT_START and the internal counter
518 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
519 * replaced by SR symbol once.
520 */
521
522 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_DPHY_BS_SR_SWAP_CNTL), 1, enc10->link_shift->DPHY_LOAD_BS_COUNT
, enc10->link_mask->DPHY_LOAD_BS_COUNT, 0x5);
523 }
524}
525
526void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
527 unsigned int sdp_transmit_line_num_deadline)
528{
529 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
530
531 REG_UPDATE_2(DP_SEC_CNTL1,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_SEC_CNTL1), 2, enc10->link_shift->DP_SEC_GSP0_LINE_NUM
, enc10->link_mask->DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline
, enc10->link_shift->DP_SEC_GSP0_PRIORITY, enc10->link_mask
->DP_SEC_GSP0_PRIORITY, 1)
532 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_SEC_CNTL1), 2, enc10->link_shift->DP_SEC_GSP0_LINE_NUM
, enc10->link_mask->DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline
, enc10->link_shift->DP_SEC_GSP0_PRIORITY, enc10->link_mask
->DP_SEC_GSP0_PRIORITY, 1)
533 DP_SEC_GSP0_PRIORITY, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_SEC_CNTL1), 2, enc10->link_shift->DP_SEC_GSP0_LINE_NUM
, enc10->link_mask->DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline
, enc10->link_shift->DP_SEC_GSP0_PRIORITY, enc10->link_mask
->DP_SEC_GSP0_PRIORITY, 1);
534}
535
536bool_Bool dcn10_is_dig_enabled(struct link_encoder *enc)
537{
538 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
539 uint32_t value;
540
541 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value)generic_reg_get(enc10->base.ctx, (enc10->link_regs->
DIG_BE_EN_CNTL), enc10->link_shift->DIG_ENABLE, enc10->
link_mask->DIG_ENABLE, &value);
542 return value;
543}
544
545static void link_encoder_disable(struct dcn10_link_encoder *enc10)
546{
547 /* reset training pattern */
548 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_TRAINING_PATTERN_SEL), 0, 1, enc10->link_shift->
DPHY_TRAINING_PATTERN_SEL, enc10->link_mask->DPHY_TRAINING_PATTERN_SEL
, 0)
549 DPHY_TRAINING_PATTERN_SEL, 0)generic_reg_set_ex(enc10->base.ctx, (enc10->link_regs->
DP_DPHY_TRAINING_PATTERN_SEL), 0, 1, enc10->link_shift->
DPHY_TRAINING_PATTERN_SEL, enc10->link_mask->DPHY_TRAINING_PATTERN_SEL
, 0);
550
551 /* reset training complete */
552 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_LINK_CNTL), 1, enc10->link_shift->DP_LINK_TRAINING_COMPLETE
, enc10->link_mask->DP_LINK_TRAINING_COMPLETE, 0);
553
554 /* reset panel mode */
555 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT);
556}
557
558static void hpd_initialize(
559 struct dcn10_link_encoder *enc10)
560{
561 /* Associate HPD with DIG_BE */
562 enum hpd_source_id hpd_source = enc10->base.hpd_source;
563
564 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DIG_BE_CNTL), 1, enc10->link_shift->DIG_HPD_SELECT
, enc10->link_mask->DIG_HPD_SELECT, hpd_source);
565}
566
567bool_Bool dcn10_link_encoder_validate_dvi_output(
568 const struct dcn10_link_encoder *enc10,
569 enum amd_signal_type connector_signal,
570 enum amd_signal_type signal,
571 const struct dc_crtc_timing *crtc_timing)
572{
573 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK165000;
574
575 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
576 max_pixel_clock *= 2;
577
578 /* This handles the case of HDMI downgrade to DVI we don't want to
579 * we don't want to cap the pixel clock if the DDI is not DVI.
580 */
581 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
582 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
583 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
584
585 /* DVI only support RGB pixel encoding */
586 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
587 return false0;
588
589 /*connect DVI via adpater's HDMI connector*/
590 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
591 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
592 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
593 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK165000 * 10))
594 return false0;
595 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK25000 * 10))
596 return false0;
597
598 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
599 return false0;
600
601 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
602 switch (crtc_timing->display_color_depth) {
603 case COLOR_DEPTH_666:
604 case COLOR_DEPTH_888:
605 break;
606 case COLOR_DEPTH_101010:
607 case COLOR_DEPTH_161616:
608 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
609 return false0;
610 break;
611 default:
612 return false0;
613 }
614
615 return true1;
616}
617
618static bool_Bool dcn10_link_encoder_validate_hdmi_output(
619 const struct dcn10_link_encoder *enc10,
620 const struct dc_crtc_timing *crtc_timing,
621 const struct dc_edid_caps *edid_caps,
622 int adjusted_pix_clk_100hz)
623{
624 enum dc_color_depth max_deep_color =
625 enc10->base.features.max_hdmi_deep_color;
626
627 // check pixel clock against edid specified max TMDS clk
628 if (edid_caps->max_tmds_clk_mhz != 0 &&
629 adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
630 return false0;
631
632 if (max_deep_color < crtc_timing->display_color_depth)
633 return false0;
634
635 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
636 return false0;
637 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK25000 * 10))
638 return false0;
639
640 if ((adjusted_pix_clk_100hz == 0) ||
641 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
642 return false0;
643
644 /* DCE11 HW does not support 420 */
645 if (!enc10->base.features.hdmi_ycbcr420_supported &&
646 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
647 return false0;
648
649 if (!enc10->base.features.flags.bits.HDMI_6GB_EN &&
650 adjusted_pix_clk_100hz >= 3000000)
651 return false0;
652 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
653 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
654 return false0;
655 return true1;
656}
657
658bool_Bool dcn10_link_encoder_validate_dp_output(
659 const struct dcn10_link_encoder *enc10,
660 const struct dc_crtc_timing *crtc_timing)
661{
662 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
663 if (!enc10->base.features.dp_ycbcr420_supported)
664 return false0;
665 }
666
667 return true1;
668}
669
670void dcn10_link_encoder_construct(
671 struct dcn10_link_encoder *enc10,
672 const struct encoder_init_data *init_data,
673 const struct encoder_feature_support *enc_features,
674 const struct dcn10_link_enc_registers *link_regs,
675 const struct dcn10_link_enc_aux_registers *aux_regs,
676 const struct dcn10_link_enc_hpd_registers *hpd_regs,
677 const struct dcn10_link_enc_shift *link_shift,
678 const struct dcn10_link_enc_mask *link_mask)
679{
680 struct bp_encoder_cap_info bp_cap_info = {0};
681 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
682 enum bp_result result = BP_RESULT_OK;
683
684 enc10->base.funcs = &dcn10_lnk_enc_funcs;
685 enc10->base.ctx = init_data->ctx;
686 enc10->base.id = init_data->encoder;
687
688 enc10->base.hpd_source = init_data->hpd_source;
689 enc10->base.connector = init_data->connector;
690
691 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
692
693 enc10->base.features = *enc_features;
694
695 enc10->base.transmitter = init_data->transmitter;
696
697 /* set the flag to indicate whether driver poll the I2C data pin
698 * while doing the DP sink detect
699 */
700
701/* if (dal_adapter_service_is_feature_supported(as,
702 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
703 enc10->base.features.flags.bits.
704 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
705
706 enc10->base.output_signals =
707 SIGNAL_TYPE_DVI_SINGLE_LINK |
708 SIGNAL_TYPE_DVI_DUAL_LINK |
709 SIGNAL_TYPE_LVDS |
710 SIGNAL_TYPE_DISPLAY_PORT |
711 SIGNAL_TYPE_DISPLAY_PORT_MST |
712 SIGNAL_TYPE_EDP |
713 SIGNAL_TYPE_HDMI_TYPE_A;
714
715 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
716 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
717 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
718 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
719 * Prefer DIG assignment is decided by board design.
720 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
721 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
722 * By this, adding DIGG should not hurt DCE 8.0.
723 * This will let DCE 8.1 share DCE 8.0 as much as possible
724 */
725
726 enc10->link_regs = link_regs;
727 enc10->aux_regs = aux_regs;
728 enc10->hpd_regs = hpd_regs;
729 enc10->link_shift = link_shift;
730 enc10->link_mask = link_mask;
731
732 switch (enc10->base.transmitter) {
733 case TRANSMITTER_UNIPHY_A:
734 enc10->base.preferred_engine = ENGINE_ID_DIGA;
735 break;
736 case TRANSMITTER_UNIPHY_B:
737 enc10->base.preferred_engine = ENGINE_ID_DIGB;
738 break;
739 case TRANSMITTER_UNIPHY_C:
740 enc10->base.preferred_engine = ENGINE_ID_DIGC;
741 break;
742 case TRANSMITTER_UNIPHY_D:
743 enc10->base.preferred_engine = ENGINE_ID_DIGD;
744 break;
745 case TRANSMITTER_UNIPHY_E:
746 enc10->base.preferred_engine = ENGINE_ID_DIGE;
747 break;
748 case TRANSMITTER_UNIPHY_F:
749 enc10->base.preferred_engine = ENGINE_ID_DIGF;
750 break;
751 case TRANSMITTER_UNIPHY_G:
752 enc10->base.preferred_engine = ENGINE_ID_DIGG;
753 break;
754 default:
755 ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_link_encoder.c"
, 755); __builtin_expect(!!(__ret), 0); })) do {} while (0); }
while (0);
756 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
757 }
758
759 /* default to one to mirror Windows behavior */
760 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
761
762 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
763 enc10->base.id, &bp_cap_info);
764
765 /* Override features with DCE-specific values */
766 if (result == BP_RESULT_OK) {
767 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
768 bp_cap_info.DP_HBR2_EN;
769 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
770 bp_cap_info.DP_HBR3_EN;
771 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
772 enc10->base.features.flags.bits.DP_IS_USB_C =
773 bp_cap_info.DP_IS_USB_C;
774 } else {
775 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",printk("\0014" "[" "drm" "] " "%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n"
, __func__, result)
776 __func__,printk("\0014" "[" "drm" "] " "%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n"
, __func__, result)
777 result)printk("\0014" "[" "drm" "] " "%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n"
, __func__, result);
778 }
779 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
780 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
781 }
782}
783
784bool_Bool dcn10_link_encoder_validate_output_with_stream(
785 struct link_encoder *enc,
786 const struct dc_stream_state *stream)
787{
788 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
789 bool_Bool is_valid;
790
791 //if SCDC (340-600MHz) is disabled, set to HDMI 1.4 timing limit
792 if (stream->sink->edid_caps.panel_patch.skip_scdc_overwrite &&
793 enc10->base.features.max_hdmi_pixel_clock > 300000)
794 enc10->base.features.max_hdmi_pixel_clock = 300000;
795
796 switch (stream->signal) {
797 case SIGNAL_TYPE_DVI_SINGLE_LINK:
798 case SIGNAL_TYPE_DVI_DUAL_LINK:
799 is_valid = dcn10_link_encoder_validate_dvi_output(
800 enc10,
801 stream->link->connector_signal,
802 stream->signal,
803 &stream->timing);
804 break;
805 case SIGNAL_TYPE_HDMI_TYPE_A:
806 is_valid = dcn10_link_encoder_validate_hdmi_output(
807 enc10,
808 &stream->timing,
809 &stream->sink->edid_caps,
810 stream->phy_pix_clk * 10);
811 break;
812 case SIGNAL_TYPE_DISPLAY_PORT:
813 case SIGNAL_TYPE_DISPLAY_PORT_MST:
814 is_valid = dcn10_link_encoder_validate_dp_output(
815 enc10, &stream->timing);
816 break;
817 case SIGNAL_TYPE_EDP:
818 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true1 : false0;
819 break;
820 case SIGNAL_TYPE_VIRTUAL:
821 is_valid = true1;
822 break;
823 default:
824 is_valid = false0;
825 break;
826 }
827
828 return is_valid;
829}
830
831void dcn10_link_encoder_hw_init(
832 struct link_encoder *enc)
833{
834 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
835 struct bp_transmitter_control cntl = { 0 };
836 enum bp_result result;
837
838 cntl.action = TRANSMITTER_CONTROL_INIT;
839 cntl.engine_id = ENGINE_ID_UNKNOWN;
840 cntl.transmitter = enc10->base.transmitter;
841 cntl.connector_obj_id = enc10->base.connector;
842 cntl.lanes_number = LANE_COUNT_FOUR;
843 cntl.coherent = false0;
844 cntl.hpd_sel = enc10->base.hpd_source;
845
846 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
847 cntl.signal = SIGNAL_TYPE_EDP;
848
849 result = link_transmitter_control(enc10, &cntl);
850
851 if (result != BP_RESULT_OK) {
852 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
)
853 __func__)__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
);
854 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 854); do
{} while (0); } while (0);
855 return;
856 }
857
858 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
859 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
860
861 result = link_transmitter_control(enc10, &cntl);
862
863 ASSERT(result == BP_RESULT_OK)do { if (({ static int __warned; int __ret = !!(!(result == BP_RESULT_OK
)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(result == BP_RESULT_OK)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_link_encoder.c"
, 863); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
864
865 }
866 dcn10_aux_initialize(enc10);
867
868 /* reinitialize HPD.
869 * hpd_initialize() will pass DIG_FE id to HW context.
870 * All other routine within HW context will use fe_engine_offset
871 * as DIG_FE id even caller pass DIG_FE id.
872 * So this routine must be called first.
873 */
874 hpd_initialize(enc10);
875}
876
877void dcn10_link_encoder_destroy(struct link_encoder **enc)
878{
879 kfree(TO_DCN10_LINK_ENC(*enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (*enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );}));
880 *enc = NULL((void *)0);
881}
882
883void dcn10_link_encoder_setup(
884 struct link_encoder *enc,
885 enum amd_signal_type signal)
886{
887 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
888
889 switch (signal) {
890 case SIGNAL_TYPE_EDP:
891 case SIGNAL_TYPE_DISPLAY_PORT:
892 /* DP SST */
893 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DIG_BE_CNTL), 1, enc10->link_shift->DIG_MODE, enc10
->link_mask->DIG_MODE, 0);
894 break;
895 case SIGNAL_TYPE_LVDS:
896 /* LVDS */
897 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DIG_BE_CNTL), 1, enc10->link_shift->DIG_MODE, enc10
->link_mask->DIG_MODE, 1);
898 break;
899 case SIGNAL_TYPE_DVI_SINGLE_LINK:
900 case SIGNAL_TYPE_DVI_DUAL_LINK:
901 /* TMDS-DVI */
902 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DIG_BE_CNTL), 1, enc10->link_shift->DIG_MODE, enc10
->link_mask->DIG_MODE, 2);
903 break;
904 case SIGNAL_TYPE_HDMI_TYPE_A:
905 /* TMDS-HDMI */
906 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DIG_BE_CNTL), 1, enc10->link_shift->DIG_MODE, enc10
->link_mask->DIG_MODE, 3);
907 break;
908 case SIGNAL_TYPE_DISPLAY_PORT_MST:
909 /* DP MST */
910 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DIG_BE_CNTL), 1, enc10->link_shift->DIG_MODE, enc10
->link_mask->DIG_MODE, 5);
911 break;
912 default:
913 ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_link_encoder.c"
, 913); __builtin_expect(!!(__ret), 0); })) do {} while (0); }
while (0);
914 /* invalid mode ! */
915 break;
916 }
917
918}
919
920/* TODO: still need depth or just pass in adjusted pixel clock? */
921void dcn10_link_encoder_enable_tmds_output(
922 struct link_encoder *enc,
923 enum clock_source_id clock_source,
924 enum dc_color_depth color_depth,
925 enum amd_signal_type signal,
926 uint32_t pixel_clock)
927{
928 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
929 struct bp_transmitter_control cntl = { 0 };
930 enum bp_result result;
931
932 /* Enable the PHY */
933
934 cntl.action = TRANSMITTER_CONTROL_ENABLE;
935 cntl.engine_id = enc->preferred_engine;
936 cntl.transmitter = enc10->base.transmitter;
937 cntl.pll_id = clock_source;
938 cntl.signal = signal;
939 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
940 cntl.lanes_number = 8;
941 else
942 cntl.lanes_number = 4;
943
944 cntl.hpd_sel = enc10->base.hpd_source;
945
946 cntl.pixel_clock = pixel_clock;
947 cntl.color_depth = color_depth;
948
949 result = link_transmitter_control(enc10, &cntl);
950
951 if (result != BP_RESULT_OK) {
952 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
)
953 __func__)__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
);
954 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 954); do
{} while (0); } while (0);
955 }
956}
957
958/* enables DP PHY output */
959void dcn10_link_encoder_enable_dp_output(
960 struct link_encoder *enc,
961 const struct dc_link_settings *link_settings,
962 enum clock_source_id clock_source)
963{
964 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
965 struct bp_transmitter_control cntl = { 0 };
966 enum bp_result result;
967
968 /* Enable the PHY */
969
970 /* number_of_lanes is used for pixel clock adjust,
971 * but it's not passed to asic_control.
972 * We need to set number of lanes manually.
973 */
974 enc1_configure_encoder(enc10, link_settings);
975
976 cntl.action = TRANSMITTER_CONTROL_ENABLE;
977 cntl.engine_id = enc->preferred_engine;
978 cntl.transmitter = enc10->base.transmitter;
979 cntl.pll_id = clock_source;
980 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
981 cntl.lanes_number = link_settings->lane_count;
982 cntl.hpd_sel = enc10->base.hpd_source;
983 cntl.pixel_clock = link_settings->link_rate
984 * LINK_RATE_REF_FREQ_IN_KHZ;
985 /* TODO: check if undefined works */
986 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
987
988 result = link_transmitter_control(enc10, &cntl);
989
990 if (result != BP_RESULT_OK) {
991 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
)
992 __func__)__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
);
993 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 993); do
{} while (0); } while (0);
994 }
995}
996
997/* enables DP PHY output in MST mode */
998void dcn10_link_encoder_enable_dp_mst_output(
999 struct link_encoder *enc,
1000 const struct dc_link_settings *link_settings,
1001 enum clock_source_id clock_source)
1002{
1003 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1004 struct bp_transmitter_control cntl = { 0 };
1005 enum bp_result result;
1006
1007 /* Enable the PHY */
1008
1009 /* number_of_lanes is used for pixel clock adjust,
1010 * but it's not passed to asic_control.
1011 * We need to set number of lanes manually.
1012 */
1013 enc1_configure_encoder(enc10, link_settings);
1014
1015 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1016 cntl.engine_id = ENGINE_ID_UNKNOWN;
1017 cntl.transmitter = enc10->base.transmitter;
1018 cntl.pll_id = clock_source;
1019 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1020 cntl.lanes_number = link_settings->lane_count;
1021 cntl.hpd_sel = enc10->base.hpd_source;
1022 cntl.pixel_clock = link_settings->link_rate
1023 * LINK_RATE_REF_FREQ_IN_KHZ;
1024 /* TODO: check if undefined works */
1025 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1026
1027 result = link_transmitter_control(enc10, &cntl);
1028
1029 if (result != BP_RESULT_OK) {
1030 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
)
1031 __func__)__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
);
1032 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1032); do
{} while (0); } while (0);
1033 }
1034}
1035/*
1036 * @brief
1037 * Disable transmitter and its encoder
1038 */
1039void dcn10_link_encoder_disable_output(
1040 struct link_encoder *enc,
1041 enum amd_signal_type signal)
1042{
1043 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1044 struct bp_transmitter_control cntl = { 0 };
1045 enum bp_result result;
1046
1047 if (!dcn10_is_dig_enabled(enc)) {
1048 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1049 /*in DP_Alt_No_Connect case, we turn off the dig already,
1050 after excuation the PHY w/a sequence, not allow touch PHY any more*/
1051 return;
1052 }
1053 /* Power-down RX and disable GPU PHY should be paired.
1054 * Disabling PHY without powering down RX may cause
1055 * symbol lock loss, on which we will get DP Sink interrupt.
1056 */
1057
1058 /* There is a case for the DP active dongles
1059 * where we want to disable the PHY but keep RX powered,
1060 * for those we need to ignore DP Sink interrupt
1061 * by checking lane count that has been set
1062 * on the last do_enable_output().
1063 */
1064
1065 /* disable transmitter */
1066 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1067 cntl.transmitter = enc10->base.transmitter;
1068 cntl.hpd_sel = enc10->base.hpd_source;
1069 cntl.signal = signal;
1070 cntl.connector_obj_id = enc10->base.connector;
1071
1072 result = link_transmitter_control(enc10, &cntl);
1073
1074 if (result != BP_RESULT_OK) {
1075 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
)
1076 __func__)__drm_err("%s: Failed to execute VBIOS command table!\n", __func__
);
1077 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1077); do
{} while (0); } while (0);
1078 return;
1079 }
1080
1081 /* disable encoder */
1082 if (dc_is_dp_signal(signal))
1083 link_encoder_disable(enc10);
1084}
1085
1086void dcn10_link_encoder_dp_set_lane_settings(
1087 struct link_encoder *enc,
1088 const struct link_training_settings *link_settings)
1089{
1090 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1091 union dpcd_training_lane_set training_lane_set = { { 0 } };
1092 int32_t lane = 0;
1093 struct bp_transmitter_control cntl = { 0 };
1094
1095 if (!link_settings) {
1096 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1096); do
{} while (0); } while (0);
1097 return;
1098 }
1099
1100 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1101 cntl.transmitter = enc10->base.transmitter;
1102 cntl.connector_obj_id = enc10->base.connector;
1103 cntl.lanes_number = link_settings->link_settings.lane_count;
1104 cntl.hpd_sel = enc10->base.hpd_source;
1105 cntl.pixel_clock = link_settings->link_settings.link_rate *
1106 LINK_RATE_REF_FREQ_IN_KHZ;
1107
1108 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1109 /* translate lane settings */
1110
1111 training_lane_set.bits.VOLTAGE_SWING_SET =
1112 link_settings->lane_settings[lane].VOLTAGE_SWING;
1113 training_lane_set.bits.PRE_EMPHASIS_SET =
1114 link_settings->lane_settings[lane].PRE_EMPHASIS;
1115
1116 /* post cursor 2 setting only applies to HBR2 link rate */
1117 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
1118 /* this is passed to VBIOS
1119 * to program post cursor 2 level
1120 */
1121 training_lane_set.bits.POST_CURSOR2_SET =
1122 link_settings->lane_settings[lane].POST_CURSOR2;
1123 }
1124
1125 cntl.lane_select = lane;
1126 cntl.lane_settings = training_lane_set.raw;
1127
1128 /* call VBIOS table to set voltage swing and pre-emphasis */
1129 link_transmitter_control(enc10, &cntl);
1130 }
1131}
1132
1133/* set DP PHY test and training patterns */
1134void dcn10_link_encoder_dp_set_phy_pattern(
1135 struct link_encoder *enc,
1136 const struct encoder_set_dp_phy_pattern_param *param)
1137{
1138 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1139
1140 switch (param->dp_phy_pattern) {
1141 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1142 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0);
1143 break;
1144 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1145 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1);
1146 break;
1147 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1148 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2);
1149 break;
1150 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1151 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3);
1152 break;
1153 case DP_TEST_PATTERN_D102:
1154 set_dp_phy_pattern_d102(enc10);
1155 break;
1156 case DP_TEST_PATTERN_SYMBOL_ERROR:
1157 set_dp_phy_pattern_symbol_error(enc10);
1158 break;
1159 case DP_TEST_PATTERN_PRBS7:
1160 set_dp_phy_pattern_prbs7(enc10);
1161 break;
1162 case DP_TEST_PATTERN_80BIT_CUSTOM:
1163 set_dp_phy_pattern_80bit_custom(
1164 enc10, param->custom_pattern);
1165 break;
1166 case DP_TEST_PATTERN_CP2520_1:
1167 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1);
1168 break;
1169 case DP_TEST_PATTERN_CP2520_2:
1170 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2);
1171 break;
1172 case DP_TEST_PATTERN_CP2520_3:
1173 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3);
1174 break;
1175 case DP_TEST_PATTERN_VIDEO_MODE: {
1176 set_dp_phy_pattern_passthrough_mode(
1177 enc10, param->dp_panel_mode);
1178 break;
1179 }
1180
1181 default:
1182 /* invalid phy pattern */
1183 ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_link_encoder.c"
, 1183); __builtin_expect(!!(__ret), 0); })) do {} while (0);
} while (0);
1184 break;
1185 }
1186}
1187
1188static void fill_stream_allocation_row_info(
1189 const struct link_mst_stream_allocation *stream_allocation,
1190 uint32_t *src,
1191 uint32_t *slots)
1192{
1193 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1194
1195 if (stream_enc) {
1196 *src = stream_enc->id;
1197 *slots = stream_allocation->slot_count;
1198 } else {
1199 *src = 0;
1200 *slots = 0;
1201 }
1202}
1203
1204/* programs DP MST VC payload allocation */
1205void dcn10_link_encoder_update_mst_stream_allocation_table(
1206 struct link_encoder *enc,
1207 const struct link_mst_stream_allocation_table *table)
1208{
1209 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1210 uint32_t value0 = 0;
1211 uint32_t value1 = 0;
1212 uint32_t value2 = 0;
1213 uint32_t slots = 0;
1214 uint32_t src = 0;
1215 uint32_t retries = 0;
1216
1217 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1218
1219 /* --- Set MSE Stream Attribute -
1220 * Setup VC Payload Table on Tx Side,
1221 * Issue allocation change trigger
1222 * to commit payload on both tx and rx side
1223 */
1224
1225 /* we should clean-up table each time */
1226
1227 if (table->stream_count >= 1) {
1228 fill_stream_allocation_row_info(
1229 &table->stream_allocations[0],
1230 &src,
1231 &slots);
1232 } else {
1233 src = 0;
1234 slots = 0;
1235 }
1236
1237 REG_UPDATE_2(DP_MSE_SAT0,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT0), 2, enc10->link_shift->DP_MSE_SAT_SRC0
, enc10->link_mask->DP_MSE_SAT_SRC0, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT0, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT0
, slots)
1238 DP_MSE_SAT_SRC0, src,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT0), 2, enc10->link_shift->DP_MSE_SAT_SRC0
, enc10->link_mask->DP_MSE_SAT_SRC0, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT0, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT0
, slots)
1239 DP_MSE_SAT_SLOT_COUNT0, slots)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT0), 2, enc10->link_shift->DP_MSE_SAT_SRC0
, enc10->link_mask->DP_MSE_SAT_SRC0, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT0, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT0
, slots);
1240
1241 if (table->stream_count >= 2) {
1242 fill_stream_allocation_row_info(
1243 &table->stream_allocations[1],
1244 &src,
1245 &slots);
1246 } else {
1247 src = 0;
1248 slots = 0;
1249 }
1250
1251 REG_UPDATE_2(DP_MSE_SAT0,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT0), 2, enc10->link_shift->DP_MSE_SAT_SRC1
, enc10->link_mask->DP_MSE_SAT_SRC1, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT1, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT1
, slots)
1252 DP_MSE_SAT_SRC1, src,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT0), 2, enc10->link_shift->DP_MSE_SAT_SRC1
, enc10->link_mask->DP_MSE_SAT_SRC1, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT1, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT1
, slots)
1253 DP_MSE_SAT_SLOT_COUNT1, slots)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT0), 2, enc10->link_shift->DP_MSE_SAT_SRC1
, enc10->link_mask->DP_MSE_SAT_SRC1, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT1, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT1
, slots);
1254
1255 if (table->stream_count >= 3) {
1256 fill_stream_allocation_row_info(
1257 &table->stream_allocations[2],
1258 &src,
1259 &slots);
1260 } else {
1261 src = 0;
1262 slots = 0;
1263 }
1264
1265 REG_UPDATE_2(DP_MSE_SAT1,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT1), 2, enc10->link_shift->DP_MSE_SAT_SRC2
, enc10->link_mask->DP_MSE_SAT_SRC2, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT2, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT2
, slots)
1266 DP_MSE_SAT_SRC2, src,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT1), 2, enc10->link_shift->DP_MSE_SAT_SRC2
, enc10->link_mask->DP_MSE_SAT_SRC2, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT2, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT2
, slots)
1267 DP_MSE_SAT_SLOT_COUNT2, slots)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT1), 2, enc10->link_shift->DP_MSE_SAT_SRC2
, enc10->link_mask->DP_MSE_SAT_SRC2, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT2, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT2
, slots);
1268
1269 if (table->stream_count >= 4) {
1270 fill_stream_allocation_row_info(
1271 &table->stream_allocations[3],
1272 &src,
1273 &slots);
1274 } else {
1275 src = 0;
1276 slots = 0;
1277 }
1278
1279 REG_UPDATE_2(DP_MSE_SAT1,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT1), 2, enc10->link_shift->DP_MSE_SAT_SRC3
, enc10->link_mask->DP_MSE_SAT_SRC3, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT3, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT3
, slots)
1280 DP_MSE_SAT_SRC3, src,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT1), 2, enc10->link_shift->DP_MSE_SAT_SRC3
, enc10->link_mask->DP_MSE_SAT_SRC3, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT3, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT3
, slots)
1281 DP_MSE_SAT_SLOT_COUNT3, slots)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT1), 2, enc10->link_shift->DP_MSE_SAT_SRC3
, enc10->link_mask->DP_MSE_SAT_SRC3, src, enc10->link_shift
->DP_MSE_SAT_SLOT_COUNT3, enc10->link_mask->DP_MSE_SAT_SLOT_COUNT3
, slots);
1282
1283 /* --- wait for transaction finish */
1284
1285 /* send allocation change trigger (ACT) ?
1286 * this step first sends the ACT,
1287 * then double buffers the SAT into the hardware
1288 * making the new allocation active on the DP MST mode link
1289 */
1290
1291 /* DP_MSE_SAT_UPDATE:
1292 * 0 - No Action
1293 * 1 - Update SAT with trigger
1294 * 2 - Update SAT without trigger
1295 */
1296 REG_UPDATE(DP_MSE_SAT_UPDATE,generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT_UPDATE), 1, enc10->link_shift->DP_MSE_SAT_UPDATE
, enc10->link_mask->DP_MSE_SAT_UPDATE, 1)
1297 DP_MSE_SAT_UPDATE, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DP_MSE_SAT_UPDATE), 1, enc10->link_shift->DP_MSE_SAT_UPDATE
, enc10->link_mask->DP_MSE_SAT_UPDATE, 1);
1298
1299 /* wait for update to complete
1300 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1301 * then wait for the transmission
1302 * of at least 16 MTP headers on immediate local link.
1303 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1304 * a value of 1 indicates that DP MST mode
1305 * is in the 16 MTP keepout region after a VC has been added.
1306 * MST stream bandwidth (VC rate) can be configured
1307 * after this bit is cleared
1308 */
1309 do {
1310 udelay(10);
1311
1312 value0 = REG_READ(DP_MSE_SAT_UPDATE)dm_read_reg_func(enc10->base.ctx, (enc10->link_regs->
DP_MSE_SAT_UPDATE), __func__);
Value stored to 'value0' is never read
1313
1314 REG_GET(DP_MSE_SAT_UPDATE,generic_reg_get(enc10->base.ctx, (enc10->link_regs->
DP_MSE_SAT_UPDATE), enc10->link_shift->DP_MSE_SAT_UPDATE
, enc10->link_mask->DP_MSE_SAT_UPDATE, &value1)
1315 DP_MSE_SAT_UPDATE, &value1)generic_reg_get(enc10->base.ctx, (enc10->link_regs->
DP_MSE_SAT_UPDATE), enc10->link_shift->DP_MSE_SAT_UPDATE
, enc10->link_mask->DP_MSE_SAT_UPDATE, &value1);
1316
1317 REG_GET(DP_MSE_SAT_UPDATE,generic_reg_get(enc10->base.ctx, (enc10->link_regs->
DP_MSE_SAT_UPDATE), enc10->link_shift->DP_MSE_16_MTP_KEEPOUT
, enc10->link_mask->DP_MSE_16_MTP_KEEPOUT, &value2)
1318 DP_MSE_16_MTP_KEEPOUT, &value2)generic_reg_get(enc10->base.ctx, (enc10->link_regs->
DP_MSE_SAT_UPDATE), enc10->link_shift->DP_MSE_16_MTP_KEEPOUT
, enc10->link_mask->DP_MSE_16_MTP_KEEPOUT, &value2);
1319
1320 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1321 if (!value1 && !value2)
1322 break;
1323 ++retries;
1324 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1325}
1326
1327void dcn10_link_encoder_connect_dig_be_to_fe(
1328 struct link_encoder *enc,
1329 enum engine_id engine,
1330 bool_Bool connect)
1331{
1332 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1333 uint32_t field;
1334
1335 if (engine != ENGINE_ID_UNKNOWN) {
1336
1337 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field)generic_reg_get(enc10->base.ctx, (enc10->link_regs->
DIG_BE_CNTL), enc10->link_shift->DIG_FE_SOURCE_SELECT, enc10
->link_mask->DIG_FE_SOURCE_SELECT, &field);
1338
1339 if (connect)
1340 field |= get_frontend_source(engine);
1341 else
1342 field &= ~get_frontend_source(engine);
1343
1344 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field)generic_reg_update_ex(enc10->base.ctx, (enc10->link_regs
->DIG_BE_CNTL), 1, enc10->link_shift->DIG_FE_SOURCE_SELECT
, enc10->link_mask->DIG_FE_SOURCE_SELECT, field);
1345 }
1346}
1347
1348
1349#define HPD_REG(reg)(enc10->hpd_regs->reg)\
1350 (enc10->hpd_regs->reg)
1351
1352#define HPD_REG_READ(reg_name)dm_read_reg_func(enc10->base.ctx, (enc10->hpd_regs->
reg_name), __func__) \
1353 dm_read_reg(CTX, HPD_REG(reg_name))dm_read_reg_func(enc10->base.ctx, (enc10->hpd_regs->
reg_name), __func__)
1354
1355#define HPD_REG_UPDATE_N(reg_name, n, ...)generic_reg_update_ex(enc10->base.ctx, (enc10->hpd_regs
->reg_name), n, ...) \
1356 generic_reg_update_ex(CTXenc10->base.ctx, \
1357 HPD_REG(reg_name)(enc10->hpd_regs->reg_name), \
1358 n, __VA_ARGS__)
1359
1360#define HPD_REG_UPDATE(reg_name, field, val)generic_reg_update_ex(enc10->base.ctx, (enc10->hpd_regs
->reg_name), 1, enc10->link_shift->field, enc10->
link_mask->field, val) \
1361 HPD_REG_UPDATE_N(reg_name, 1, \generic_reg_update_ex(enc10->base.ctx, (enc10->hpd_regs
->reg_name), 1, enc10->link_shift->field, enc10->
link_mask->field, val)
1362 FN(reg_name, field), val)generic_reg_update_ex(enc10->base.ctx, (enc10->hpd_regs
->reg_name), 1, enc10->link_shift->field, enc10->
link_mask->field, val)
1363
1364void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1365{
1366 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1367
1368 HPD_REG_UPDATE(DC_HPD_CONTROL,generic_reg_update_ex(enc10->base.ctx, (enc10->hpd_regs
->DC_HPD_CONTROL), 1, enc10->link_shift->DC_HPD_EN, enc10
->link_mask->DC_HPD_EN, 1)
1369 DC_HPD_EN, 1)generic_reg_update_ex(enc10->base.ctx, (enc10->hpd_regs
->DC_HPD_CONTROL), 1, enc10->link_shift->DC_HPD_EN, enc10
->link_mask->DC_HPD_EN, 1);
1370}
1371
1372void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1373{
1374 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1375
1376 HPD_REG_UPDATE(DC_HPD_CONTROL,generic_reg_update_ex(enc10->base.ctx, (enc10->hpd_regs
->DC_HPD_CONTROL), 1, enc10->link_shift->DC_HPD_EN, enc10
->link_mask->DC_HPD_EN, 0)
1377 DC_HPD_EN, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->hpd_regs
->DC_HPD_CONTROL), 1, enc10->link_shift->DC_HPD_EN, enc10
->link_mask->DC_HPD_EN, 0);
1378}
1379
1380#define AUX_REG(reg)(enc10->aux_regs->reg)\
1381 (enc10->aux_regs->reg)
1382
1383#define AUX_REG_READ(reg_name)dm_read_reg_func(enc10->base.ctx, (enc10->aux_regs->
reg_name), __func__) \
1384 dm_read_reg(CTX, AUX_REG(reg_name))dm_read_reg_func(enc10->base.ctx, (enc10->aux_regs->
reg_name), __func__)
1385
1386#define AUX_REG_UPDATE_N(reg_name, n, ...)generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->reg_name), n, ...) \
1387 generic_reg_update_ex(CTXenc10->base.ctx, \
1388 AUX_REG(reg_name)(enc10->aux_regs->reg_name), \
1389 n, __VA_ARGS__)
1390
1391#define AUX_REG_UPDATE(reg_name, field, val)generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->reg_name), 1, enc10->link_shift->field, enc10->
link_mask->field, val) \
1392 AUX_REG_UPDATE_N(reg_name, 1, \generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->reg_name), 1, enc10->link_shift->field, enc10->
link_mask->field, val)
1393 FN(reg_name, field), val)generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->reg_name), 1, enc10->link_shift->field, enc10->
link_mask->field, val)
1394
1395#define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2)generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->reg), 2, enc10->link_shift->f1, enc10->link_mask
->f1, v1, enc10->link_shift->f2, enc10->link_mask
->f2, v2) \
1396 AUX_REG_UPDATE_N(reg, 2,\generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->reg), 2, enc10->link_shift->f1, enc10->link_mask
->f1, v1, enc10->link_shift->f2, enc10->link_mask
->f2, v2)
1397 FN(reg, f1), v1,\generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->reg), 2, enc10->link_shift->f1, enc10->link_mask
->f1, v1, enc10->link_shift->f2, enc10->link_mask
->f2, v2)
1398 FN(reg, f2), v2)generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->reg), 2, enc10->link_shift->f1, enc10->link_mask
->f1, v1, enc10->link_shift->f2, enc10->link_mask
->f2, v2)
1399
1400void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
1401{
1402 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1403
1404 AUX_REG_UPDATE_2(AUX_CONTROL,generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->AUX_CONTROL), 2, enc10->link_shift->AUX_HPD_SEL, enc10
->link_mask->AUX_HPD_SEL, hpd_source, enc10->link_shift
->AUX_LS_READ_EN, enc10->link_mask->AUX_LS_READ_EN, 0
)
1405 AUX_HPD_SEL, hpd_source,generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->AUX_CONTROL), 2, enc10->link_shift->AUX_HPD_SEL, enc10
->link_mask->AUX_HPD_SEL, hpd_source, enc10->link_shift
->AUX_LS_READ_EN, enc10->link_mask->AUX_LS_READ_EN, 0
)
1406 AUX_LS_READ_EN, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->AUX_CONTROL), 2, enc10->link_shift->AUX_HPD_SEL, enc10
->link_mask->AUX_HPD_SEL, hpd_source, enc10->link_shift
->AUX_LS_READ_EN, enc10->link_mask->AUX_LS_READ_EN, 0
);
1407
1408 /* 1/4 window (the maximum allowed) */
1409 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->AUX_DPHY_RX_CONTROL0), 1, enc10->link_shift->AUX_RX_RECEIVE_WINDOW
, enc10->link_mask->AUX_RX_RECEIVE_WINDOW, 0)
1410 AUX_RX_RECEIVE_WINDOW, 0)generic_reg_update_ex(enc10->base.ctx, (enc10->aux_regs
->AUX_DPHY_RX_CONTROL0), 1, enc10->link_shift->AUX_RX_RECEIVE_WINDOW
, enc10->link_mask->AUX_RX_RECEIVE_WINDOW, 0);
1411}
1412
1413enum amd_signal_type dcn10_get_dig_mode(
1414 struct link_encoder *enc)
1415{
1416 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc)({ const __typeof( ((struct dcn10_link_encoder *)0)->base )
*__mptr = (enc); (struct dcn10_link_encoder *)( (char *)__mptr
- __builtin_offsetof(struct dcn10_link_encoder, base) );});
1417 uint32_t value;
1418 REG_GET(DIG_BE_CNTL, DIG_MODE, &value)generic_reg_get(enc10->base.ctx, (enc10->link_regs->
DIG_BE_CNTL), enc10->link_shift->DIG_MODE, enc10->link_mask
->DIG_MODE, &value);
1419 switch (value) {
1420 case 1:
1421 return SIGNAL_TYPE_DISPLAY_PORT;
1422 case 2:
1423 return SIGNAL_TYPE_DVI_SINGLE_LINK;
1424 case 3:
1425 return SIGNAL_TYPE_HDMI_TYPE_A;
1426 case 5:
1427 return SIGNAL_TYPE_DISPLAY_PORT_MST;
1428 default:
1429 return SIGNAL_TYPE_NONE;
1430 }
1431 return SIGNAL_TYPE_NONE;
1432}
1433
1434void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
1435 struct dc_link_settings *link_settings)
1436{
1437 /* Set Default link settings */
1438 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1439 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false0, 0};
1440
1441 /* Higher link settings based on feature supported */
1442 if (enc->features.flags.bits.IS_HBR2_CAPABLE)
1443 max_link_cap.link_rate = LINK_RATE_HIGH2;
1444
1445 if (enc->features.flags.bits.IS_HBR3_CAPABLE)
1446 max_link_cap.link_rate = LINK_RATE_HIGH3;
1447
1448 *link_settings = max_link_cap;
1449}