Bug Summary

File:dev/pci/ixgbe_82598.c
Warning:line 144, column 2
Value stored to 'ret_val' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ixgbe_82598.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/ixgbe_82598.c
1/* $OpenBSD: ixgbe_82598.c,v 1.19 2022/01/09 05:42:56 jsg Exp $ */
2
3/******************************************************************************
4 SPDX-License-Identifier: BSD-3-Clause
5
6 Copyright (c) 2001-2017, Intel Corporation
7 All rights reserved.
8
9 Redistribution and use in source and binary forms, with or without
10 modification, are permitted provided that the following conditions are met:
11
12 1. Redistributions of source code must retain the above copyright notice,
13 this list of conditions and the following disclaimer.
14
15 2. Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18
19 3. Neither the name of the Intel Corporation nor the names of its
20 contributors may be used to endorse or promote products derived from
21 this software without specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 POSSIBILITY OF SUCH DAMAGE.
34
35******************************************************************************/
36/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 331224 2018-03-19 20:55:05Z erj $*/
37
38
39#include <dev/pci/ixgbe.h>
40#include <dev/pci/ixgbe_type.h>
41
42#define IXGBE_82598_MAX_TX_QUEUES32 32
43#define IXGBE_82598_MAX_RX_QUEUES64 64
44#define IXGBE_82598_RAR_ENTRIES16 16
45#define IXGBE_82598_MC_TBL_SIZE128 128
46#define IXGBE_82598_VFT_TBL_SIZE128 128
47#define IXGBE_82598_RX_PB_SIZE512 512
48
49uint32_t ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
50int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool_Bool *autoneg);
53enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
54int32_t ixgbe_fc_enable_82598(struct ixgbe_hw *hw);
55int32_t ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
56 bool_Bool autoneg_wait_to_complete);
57int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw);
58int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
59 ixgbe_link_speed *speed, bool_Bool *link_up,
60 bool_Bool link_up_wait_to_complete);
61int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool_Bool autoneg_wait_to_complete);
64int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
65 ixgbe_link_speed speed,
66 bool_Bool autoneg_wait_to_complete);
67int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
68
69int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw);
70int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);
71int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq);
72int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan,
73 uint32_t vind, bool_Bool vlan_on, bool_Bool vlvf_bypass);
74int32_t ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
75int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val);
76int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val);
77int32_t ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, uint8_t dev_addr,
78 uint8_t byte_offset, uint8_t *eeprom_data);
79int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset,
80 uint8_t *eeprom_data);
81uint64_t ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
82int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
83void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
84void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
85int32_t ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, uint32_t regval);
86
87/**
88 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
89 * @hw: pointer to the HW structure
90 *
91 * The defaults for 82598 should be in the range of 50us to 50ms,
92 * however the hardware default for these parts is 500us to 1ms which is less
93 * than the 10ms recommended by the pci-e spec. To address this we need to
94 * increase the value to either 10ms to 250ms for capability version 1 config,
95 * or 16ms to 55ms for version 2.
96 **/
97void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
98{
99 uint32_t gcr = IXGBE_READ_REG(hw, IXGBE_GCR)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x11000
)));
100 uint16_t pcie_devctl2;
101
102 /* only take action if timeout value is defaulted to 0 */
103 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK0x0000F000)
104 goto out;
105
106 /*
107 * if capabilities version is type 1 we can write the
108 * timeout of 10ms to 250ms through the GCR register
109 */
110 if (!(gcr & IXGBE_GCR_CAP_VER20x00040000)) {
111 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms0x00001000;
112 goto out;
113 }
114
115 /*
116 * for version 2 capabilities we need to write the config space
117 * directly in order to set the completion timeout value for
118 * 16ms to 55ms
119 */
120 pcie_devctl2 = IXGBE_READ_PCIE_WORDixgbe_read_pci_cfg(hw, IXGBE_PCI_DEVICE_CONTROL20xC8);
121 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms0x0005;
122 IXGBE_WRITE_PCIE_WORDixgbe_write_pci_cfg(hw, IXGBE_PCI_DEVICE_CONTROL20xC8, pcie_devctl2);
123out:
124 /* disable completion timeout resend */
125 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND0x00010000;
126 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x11000
), (gcr)));
127}
128
129/**
130 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
131 * @hw: pointer to hardware structure
132 *
133 * Initialize the function pointers and assign the MAC type for 82598.
134 * Does not touch the hardware.
135 **/
136int32_t ixgbe_init_ops_82598(struct ixgbe_hw *hw)
137{
138 struct ixgbe_mac_info *mac = &hw->mac;
139 struct ixgbe_phy_info *phy = &hw->phy;
140 int32_t ret_val;
141
142 DEBUGFUNC("ixgbe_init_ops_82598");;
143
144 ret_val = ixgbe_init_phy_ops_generic(hw);
Value stored to 'ret_val' is never read
145 ret_val = ixgbe_init_ops_generic(hw);
146
147 /* PHY */
148 phy->ops.init = ixgbe_init_phy_ops_82598;
149
150 /* MAC */
151 mac->ops.start_hw = ixgbe_start_hw_82598;
152 mac->ops.reset_hw = ixgbe_reset_hw_82598;
153 mac->ops.get_media_type = ixgbe_get_media_type_82598;
154 mac->ops.get_supported_physical_layer =
155 ixgbe_get_supported_physical_layer_82598;
156 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598;
157 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598;
158 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598;
159 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598;
160
161 /* RAR, Multicast, VLAN */
162 mac->ops.set_vmdq = ixgbe_set_vmdq_82598;
163 mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598;
164 mac->ops.set_vfta = ixgbe_set_vfta_82598;
165 mac->ops.set_vlvf = NULL((void *)0);
166 mac->ops.clear_vfta = ixgbe_clear_vfta_82598;
167
168 /* Flow Control */
169 mac->ops.fc_enable = ixgbe_fc_enable_82598;
170
171 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE128;
172 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE128;
173 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES16;
174 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE512;
175 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES64;
176 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES32;
177 mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/;
178
179 /* SFP+ Module */
180 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;
181
182 /* Link */
183 mac->ops.check_link = ixgbe_check_mac_link_82598;
184 mac->ops.setup_link = ixgbe_setup_mac_link_82598;
185 mac->ops.flap_tx_laser = NULL((void *)0);
186 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598;
187
188 return ret_val;
189}
190
191/**
192 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
193 * @hw: pointer to hardware structure
194 *
195 * Initialize any function pointers that were not able to be
196 * set during init_shared_code because the PHY/SFP type was
197 * not known. Perform the SFP init if necessary.
198 *
199 **/
200int32_t ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
201{
202 struct ixgbe_mac_info *mac = &hw->mac;
203 struct ixgbe_phy_info *phy = &hw->phy;
204 int32_t ret_val = IXGBE_SUCCESS0;
205 uint16_t list_offset, data_offset;
206
207 DEBUGFUNC("ixgbe_init_phy_ops_82598");;
208
209 /* Identify the PHY */
210 phy->ops.identify(hw);
211
212 /* Overwrite the link function pointers if copper PHY */
213 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
214 mac->ops.setup_link = ixgbe_setup_copper_link_82598;
215 mac->ops.get_link_capabilities =
216 ixgbe_get_copper_link_capabilities_generic;
217 }
218
219 switch (hw->phy.type) {
220 case ixgbe_phy_tn:
221 phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
222 phy->ops.check_link = ixgbe_check_phy_link_tnx;
223 phy->ops.get_firmware_version =
224 ixgbe_get_phy_firmware_version_tnx;
225 break;
226 case ixgbe_phy_nl:
227 phy->ops.reset = ixgbe_reset_phy_nl;
228
229 /* Call SFP+ identify routine to get the SFP+ module type */
230 ret_val = phy->ops.identify_sfp(hw);
231 if (ret_val != IXGBE_SUCCESS0)
232 goto out;
233 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
234 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED-19;
235 goto out;
236 }
237
238 /* Check to see if SFP+ module is supported */
239 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
240 &list_offset,
241 &data_offset);
242 if (ret_val != IXGBE_SUCCESS0) {
243 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED-19;
244 goto out;
245 }
246 break;
247 default:
248 break;
249 }
250
251out:
252 return ret_val;
253}
254
255/**
256 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
257 * @hw: pointer to hardware structure
258 *
259 * Starts the hardware using the generic start_hw function.
260 * Disables relaxed ordering Then set pcie completion timeout
261 *
262 **/
263int32_t ixgbe_start_hw_82598(struct ixgbe_hw *hw)
264{
265 uint32_t regval;
266 uint32_t i;
267 int32_t ret_val = IXGBE_SUCCESS0;
268
269 DEBUGFUNC("ixgbe_start_hw_82598");;
270
271 ret_val = ixgbe_start_hw_generic(hw);
272 if (ret_val)
273 return ret_val;
274
275 /* Disable relaxed ordering */
276 for (i = 0; ((i < hw->mac.max_tx_queues) &&
277 (i < IXGBE_DCA_MAX_QUEUES_8259816)); i++) {
278 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x07200
+ ((i) * 4)))));
279 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN(1 << 11);
280 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x07200
+ ((i) * 4))), (regval)));
281 }
282
283 for (i = 0; ((i < hw->mac.max_rx_queues) &&
284 (i < IXGBE_DCA_MAX_QUEUES_8259816)); i++) {
285 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((i) <=
15) ? (0x02200 + ((i) * 4)) : (((i) < 64) ? (0x0100C + ((
i) * 0x40)) : (0x0D00C + (((i) - 64) * 0x40)))))));
286 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN(1 << 13) |
287 IXGBE_DCA_RXCTRL_HEAD_WRO_EN(1 << 15));
288 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((i) <=
15) ? (0x02200 + ((i) * 4)) : (((i) < 64) ? (0x0100C + ((
i) * 0x40)) : (0x0D00C + (((i) - 64) * 0x40))))), (regval)));
289 }
290
291 /* set the completion timeout for interface */
292 ixgbe_set_pcie_completion_timeout(hw);
293
294 return ret_val;
295}
296
297/**
298 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
299 * @hw: pointer to hardware structure
300 * @speed: pointer to link speed
301 * @autoneg: boolean auto-negotiation value
302 *
303 * Determines the link capabilities by reading the AUTOC register.
304 **/
305int32_t ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
306 ixgbe_link_speed *speed,
307 bool_Bool *autoneg)
308{
309 int32_t status = IXGBE_SUCCESS0;
310 uint32_t autoc = 0;
311
312 DEBUGFUNC("ixgbe_get_link_capabilities_82598");;
313
314 /*
315 * Determine link capabilities based on the stored value of AUTOC,
316 * which represents EEPROM defaults. If AUTOC value has not been
317 * stored, use the current register value.
318 */
319 if (hw->mac.orig_link_settings_stored)
320 autoc = hw->mac.orig_autoc;
321 else
322 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A0
)));
323
324 switch (autoc & IXGBE_AUTOC_LMS_MASK(0x7 << 13)) {
325 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN(0x0 << 13):
326 *speed = IXGBE_LINK_SPEED_1GB_FULL0x0020;
327 *autoneg = FALSE0;
328 break;
329
330 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN(0x1 << 13):
331 *speed = IXGBE_LINK_SPEED_10GB_FULL0x0080;
332 *autoneg = FALSE0;
333 break;
334
335 case IXGBE_AUTOC_LMS_1G_AN(0x2 << 13):
336 *speed = IXGBE_LINK_SPEED_1GB_FULL0x0020;
337 *autoneg = TRUE1;
338 break;
339
340 case IXGBE_AUTOC_LMS_KX4_AN(0x4 << 13):
341 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN(0x6 << 13):
342 *speed = IXGBE_LINK_SPEED_UNKNOWN0;
343 if (autoc & IXGBE_AUTOC_KX4_SUPP0x80000000)
344 *speed |= IXGBE_LINK_SPEED_10GB_FULL0x0080;
345 if (autoc & IXGBE_AUTOC_KX_SUPP0x40000000)
346 *speed |= IXGBE_LINK_SPEED_1GB_FULL0x0020;
347 *autoneg = TRUE1;
348 break;
349
350 default:
351 status = IXGBE_ERR_LINK_SETUP-8;
352 break;
353 }
354
355 return status;
356}
357
358/**
359 * ixgbe_get_media_type_82598 - Determines media type
360 * @hw: pointer to hardware structure
361 *
362 * Returns the media type (fiber, copper, backplane)
363 **/
364enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
365{
366 enum ixgbe_media_type media_type;
367
368 DEBUGFUNC("ixgbe_get_media_type_82598");;
369
370 /* Detect if there is a copper PHY attached. */
371 switch (hw->phy.type) {
372 case ixgbe_phy_cu_unknown:
373 case ixgbe_phy_tn:
374 media_type = ixgbe_media_type_copper;
375 goto out;
376 default:
377 break;
378 }
379
380 /* Media type for I82598 is based on device ID */
381 switch (hw->device_id) {
382 case IXGBE_DEV_ID_825980x10B6:
383 case IXGBE_DEV_ID_82598_BX0x1508:
384 /* Default device ID is mezzanine card KX/KX4 */
385 media_type = ixgbe_media_type_backplane;
386 break;
387 case IXGBE_DEV_ID_82598AF_DUAL_PORT0x10C6:
388 case IXGBE_DEV_ID_82598AF_SINGLE_PORT0x10C7:
389 case IXGBE_DEV_ID_82598_DA_DUAL_PORT0x10F1:
390 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM0x10E1:
391 case IXGBE_DEV_ID_82598EB_XF_LR0x10F4:
392 case IXGBE_DEV_ID_82598EB_SFP_LOM0x10DB:
393 media_type = ixgbe_media_type_fiber;
394 break;
395 case IXGBE_DEV_ID_82598EB_CX40x10DD:
396 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT0x10EC:
397 media_type = ixgbe_media_type_cx4;
398 break;
399 case IXGBE_DEV_ID_82598AT0x10C8:
400 case IXGBE_DEV_ID_82598AT20x150B:
401 media_type = ixgbe_media_type_copper;
402 break;
403 default:
404 media_type = ixgbe_media_type_unknown;
405 break;
406 }
407out:
408 return media_type;
409}
410
411/**
412 * ixgbe_fc_enable_82598 - Enable flow control
413 * @hw: pointer to hardware structure
414 *
415 * Enable flow control according to the current settings.
416 **/
417int32_t ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
418{
419 int32_t ret_val = IXGBE_SUCCESS0;
420 uint32_t fctrl_reg;
421 uint32_t rmcs_reg;
422 uint32_t reg;
423 uint32_t fcrtl, fcrth;
424 uint32_t link_speed = 0;
425 int i;
426 bool_Bool link_up;
427
428 DEBUGFUNC("ixgbe_fc_enable_82598");;
429
430 /* Validate the water mark configuration */
431 if (!hw->fc.pause_time) {
432 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS-13;
433 goto out;
434 }
435
436 /* Low water mark of zero causes XOFF floods */
437 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS8; i++) {
438 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
439 hw->fc.high_water[i]) {
440 if (!hw->fc.low_water[i] ||
441 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
442 DEBUGOUT("Invalid water mark configuration\n");
443 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS-13;
444 goto out;
445 }
446 }
447 }
448
449 /*
450 * On 82598 having Rx FC on causes resets while doing 1G
451 * so if it's on turn it off once we know link_speed. For
452 * more details see 82598 Specification update.
453 */
454 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE0);
455 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL0x0020) {
456 switch (hw->fc.requested_mode) {
457 case ixgbe_fc_full:
458 hw->fc.requested_mode = ixgbe_fc_tx_pause;
459 break;
460 case ixgbe_fc_rx_pause:
461 hw->fc.requested_mode = ixgbe_fc_none;
462 break;
463 default:
464 /* no change */
465 break;
466 }
467 }
468
469 /* Negotiate the fc mode to use */
470 ixgbe_fc_autoneg(hw);
471
472 /* Disable any previous flow control settings */
473 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x05080
)));
474 fctrl_reg &= ~(IXGBE_FCTRL_RFCE0x00008000 | IXGBE_FCTRL_RPFCE0x00004000);
475
476 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x03D00
)));
477 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY0x00000010 | IXGBE_RMCS_TFCE_802_3X0x00000008);
478
479 /*
480 * The possible values of fc.current_mode are:
481 * 0: Flow control is completely disabled
482 * 1: Rx flow control is enabled (we can receive pause frames,
483 * but not send pause frames).
484 * 2: Tx flow control is enabled (we can send pause frames but
485 * we do not support receiving pause frames).
486 * 3: Both Rx and Tx flow control (symmetric) are enabled.
487 * other: Invalid.
488 */
489 switch (hw->fc.current_mode) {
490 case ixgbe_fc_none:
491 /*
492 * Flow control is disabled by software override or autoneg.
493 * The code below will actually disable it in the HW.
494 */
495 break;
496 case ixgbe_fc_rx_pause:
497 /*
498 * Rx Flow control is enabled and Tx Flow control is
499 * disabled by software override. Since there really
500 * isn't a way to advertise that we are capable of RX
501 * Pause ONLY, we will advertise that we support both
502 * symmetric and asymmetric Rx PAUSE. Later, we will
503 * disable the adapter's ability to send PAUSE frames.
504 */
505 fctrl_reg |= IXGBE_FCTRL_RFCE0x00008000;
506 break;
507 case ixgbe_fc_tx_pause:
508 /*
509 * Tx Flow control is enabled, and Rx Flow control is
510 * disabled by software override.
511 */
512 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X0x00000008;
513 break;
514 case ixgbe_fc_full:
515 /* Flow control (both Rx and Tx) is enabled by SW override. */
516 fctrl_reg |= IXGBE_FCTRL_RFCE0x00008000;
517 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X0x00000008;
518 break;
519 default:
520 DEBUGOUT("Flow control param set incorrectly\n");
521 ret_val = IXGBE_ERR_CONFIG-4;
522 goto out;
523 break;
524 }
525
526 /* Set 802.3x based flow control settings. */
527 fctrl_reg |= IXGBE_FCTRL_DPF0x00002000;
528 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x05080
), (fctrl_reg)));
529 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x03D00
), (rmcs_reg)));
530
531 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
532 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS8; i++) {
533 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
534 hw->fc.high_water[i]) {
535 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE0x80000000;
536 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN0x80000000;
537 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x03220
+ ((i) * 8))), (fcrtl)));
538 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x03260
+ ((i) * 8))), (fcrth)));
539 } else {
540 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x03220
+ ((i) * 8))), (0)));
541 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x03260
+ ((i) * 8))), (0)));
542 }
543
544 }
545
546 /* Configure pause time (2 TCs per register) */
547 reg = hw->fc.pause_time * 0x00010001;
548 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS8 / 2); i++)
549 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x03200
+ ((i) * 4))), (reg)));
550
551 /* Configure flow control refresh threshold value */
552 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x032A0
), (hw->fc.pause_time / 2)));
553
554out:
555 return ret_val;
556}
557
558/**
559 * ixgbe_start_mac_link_82598 - Configures MAC link settings
560 * @hw: pointer to hardware structure
561 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
562 *
563 * Configures link settings based on values in the ixgbe_hw struct.
564 * Restarts the link. Performs autonegotiation if needed.
565 **/
566int32_t ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
567 bool_Bool autoneg_wait_to_complete)
568{
569 uint32_t autoc_reg;
570 uint32_t links_reg;
571 uint32_t i;
572 int32_t status = IXGBE_SUCCESS0;
573
574 DEBUGFUNC("ixgbe_start_mac_link_82598");;
575
576 /* Restart link */
577 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A0
)));
578 autoc_reg |= IXGBE_AUTOC_AN_RESTART0x00001000;
579 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A0
), (autoc_reg)));
580
581 /* Only poll for autoneg to complete if specified to do so */
582 if (autoneg_wait_to_complete) {
583 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK(0x7 << 13)) ==
584 IXGBE_AUTOC_LMS_KX4_AN(0x4 << 13) ||
585 (autoc_reg & IXGBE_AUTOC_LMS_MASK(0x7 << 13)) ==
586 IXGBE_AUTOC_LMS_KX4_AN_1G_AN(0x6 << 13)) {
587 links_reg = 0; /* Just in case Autoneg time = 0 */
588 for (i = 0; i < IXGBE_AUTO_NEG_TIME45; i++) {
589 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A4
)));
590 if (links_reg & IXGBE_LINKS_KX_AN_COMP0x80000000)
591 break;
592 msec_delay(100)(*delay_func)(1000 * (100));
593 }
594 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP0x80000000)) {
595 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE-14;
596 DEBUGOUT("Autonegotiation did not complete.\n");
597 }
598 }
599 }
600
601 /* Add delay to filter out noises during initial link setup */
602 msec_delay(50)(*delay_func)(1000 * (50));
603
604 return status;
605}
606
607/**
608 * ixgbe_validate_link_ready - Function looks for phy link
609 * @hw: pointer to hardware structure
610 *
611 * Function indicates success when phy link is available. If phy is not ready
612 * within 5 seconds of MAC indicating link, the function returns error.
613 **/
614int32_t ixgbe_validate_link_ready(struct ixgbe_hw *hw)
615{
616 uint32_t timeout;
617 uint16_t an_reg;
618
619 if (hw->device_id != IXGBE_DEV_ID_82598AT20x150B)
620 return IXGBE_SUCCESS0;
621
622 for (timeout = 0;
623 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT50; timeout++) {
624 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS0x1,
625 IXGBE_MDIO_AUTO_NEG_DEV_TYPE0x7, &an_reg);
626
627 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE0x20) &&
628 (an_reg & IXGBE_MII_AUTONEG_LINK_UP0x04))
629 break;
630
631 msec_delay(100)(*delay_func)(1000 * (100));
632 }
633
634 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT50) {
635 DEBUGOUT("Link was indicated but link is down\n");
636 return IXGBE_ERR_LINK_SETUP-8;
637 }
638
639 return IXGBE_SUCCESS0;
640}
641
642/**
643 * ixgbe_check_mac_link_82598 - Get link/speed status
644 * @hw: pointer to hardware structure
645 * @speed: pointer to link speed
646 * @link_up: TRUE is link is up, FALSE otherwise
647 * @link_up_wait_to_complete: bool used to wait for link up or not
648 *
649 * Reads the links register to determine if link is up and the current speed
650 **/
651int32_t ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
652 ixgbe_link_speed *speed, bool_Bool *link_up,
653 bool_Bool link_up_wait_to_complete)
654{
655 uint32_t links_reg;
656 uint32_t i;
657 uint16_t link_reg, adapt_comp_reg;
658
659 DEBUGFUNC("ixgbe_check_mac_link_82598");;
660
661 /*
662 * SERDES PHY requires us to read link status from undocumented
663 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
664 * indicates link down. OxC00C is read to check that the XAUI lanes
665 * are active. Bit 0 clear indicates active; set indicates inactive.
666 */
667 if (hw->phy.type == ixgbe_phy_nl) {
668 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV1, &link_reg);
669 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV1, &link_reg);
670 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV1,
671 &adapt_comp_reg);
672 if (link_up_wait_to_complete) {
673 for (i = 0; i < hw->mac.max_link_up_time; i++) {
674 if ((link_reg & 1) &&
675 ((adapt_comp_reg & 1) == 0)) {
676 *link_up = TRUE1;
677 break;
678 } else {
679 *link_up = FALSE0;
680 }
681 msec_delay(100)(*delay_func)(1000 * (100));
682 hw->phy.ops.read_reg(hw, 0xC79F,
683 IXGBE_TWINAX_DEV1,
684 &link_reg);
685 hw->phy.ops.read_reg(hw, 0xC00C,
686 IXGBE_TWINAX_DEV1,
687 &adapt_comp_reg);
688 }
689 } else {
690 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
691 *link_up = TRUE1;
692 else
693 *link_up = FALSE0;
694 }
695
696 if (*link_up == FALSE0)
697 goto out;
698 }
699
700 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A4
)));
701 if (link_up_wait_to_complete) {
702 for (i = 0; i < hw->mac.max_link_up_time; i++) {
703 if (links_reg & IXGBE_LINKS_UP0x40000000) {
704 *link_up = TRUE1;
705 break;
706 } else {
707 *link_up = FALSE0;
708 }
709 msec_delay(100)(*delay_func)(1000 * (100));
710 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A4
)));
711 }
712 } else {
713 if (links_reg & IXGBE_LINKS_UP0x40000000)
714 *link_up = TRUE1;
715 else
716 *link_up = FALSE0;
717 }
718
719 if (links_reg & IXGBE_LINKS_SPEED0x20000000)
720 *speed = IXGBE_LINK_SPEED_10GB_FULL0x0080;
721 else
722 *speed = IXGBE_LINK_SPEED_1GB_FULL0x0020;
723
724 if ((hw->device_id == IXGBE_DEV_ID_82598AT20x150B) && (*link_up == TRUE1) &&
725 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS0))
726 *link_up = FALSE0;
727
728out:
729 return IXGBE_SUCCESS0;
730}
731
732/**
733 * ixgbe_setup_mac_link_82598 - Set MAC link speed
734 * @hw: pointer to hardware structure
735 * @speed: new link speed
736 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
737 *
738 * Set the link speed in the AUTOC register and restarts link.
739 **/
740int32_t ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
741 ixgbe_link_speed speed,
742 bool_Bool autoneg_wait_to_complete)
743{
744 bool_Bool autoneg = FALSE0;
745 int32_t status = IXGBE_SUCCESS0;
746 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN0;
747 uint32_t curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A0
)));
748 uint32_t autoc = curr_autoc;
749 uint32_t link_mode = autoc & IXGBE_AUTOC_LMS_MASK(0x7 << 13);
750
751 DEBUGFUNC("ixgbe_setup_mac_link_82598");;
752
753 /* Check to see if speed passed in is supported. */
754 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
755 speed &= link_capabilities;
756
757 if (speed == IXGBE_LINK_SPEED_UNKNOWN0)
758 status = IXGBE_ERR_LINK_SETUP-8;
759
760 /* Set KX4/KX support according to speed requested */
761 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN(0x4 << 13) ||
762 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN(0x6 << 13)) {
763 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK0xC0000000;
764 if (speed & IXGBE_LINK_SPEED_10GB_FULL0x0080)
765 autoc |= IXGBE_AUTOC_KX4_SUPP0x80000000;
766 if (speed & IXGBE_LINK_SPEED_1GB_FULL0x0020)
767 autoc |= IXGBE_AUTOC_KX_SUPP0x40000000;
768 if (autoc != curr_autoc)
769 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A0
), (autoc)));
770 }
771
772 if (status == IXGBE_SUCCESS0) {
773 /*
774 * Setup and restart the link based on the new values in
775 * ixgbe_hw This will write the AUTOC register based on the new
776 * stored values
777 */
778 status = ixgbe_start_mac_link_82598(hw,
779 autoneg_wait_to_complete);
780 }
781
782 return status;
783}
784
785
786/**
787 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
788 * @hw: pointer to hardware structure
789 * @speed: new link speed
790 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
791 *
792 * Sets the link speed in the AUTOC register in the MAC and restarts link.
793 **/
794int32_t ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
795 ixgbe_link_speed speed,
796 bool_Bool autoneg_wait_to_complete)
797{
798 int32_t status;
799
800 DEBUGFUNC("ixgbe_setup_copper_link_82598");;
801
802 /* Setup the PHY according to input speed */
803 status = hw->phy.ops.setup_link_speed(hw, speed,
804 autoneg_wait_to_complete);
805 /* Set up MAC */
806 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
807
808 return status;
809}
810
811/**
812 * ixgbe_reset_hw_82598 - Performs hardware reset
813 * @hw: pointer to hardware structure
814 *
815 * Resets the hardware by resetting the transmit and receive units, masks and
816 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
817 * reset.
818 **/
819int32_t ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
820{
821 int32_t status = IXGBE_SUCCESS0;
822 int32_t phy_status = IXGBE_SUCCESS0;
823 uint32_t ctrl;
824 uint32_t gheccr;
825 uint32_t i;
826 uint32_t autoc;
827 uint8_t analog_val;
828
829 DEBUGFUNC("ixgbe_reset_hw_82598");;
830
831 /* Call adapter stop to disable tx/rx and clear interrupts */
832 status = hw->mac.ops.stop_adapter(hw);
833 if (status != IXGBE_SUCCESS0)
834 goto reset_hw_out;
835
836 /*
837 * Power up the Atlas Tx lanes if they are currently powered down.
838 * Atlas Tx lanes are powered down for MAC loopback tests, but
839 * they are not automatically restored on reset.
840 */
841 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK0x24, &analog_val);
842 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN0x10) {
843 /* Enable Tx Atlas so packets can be transmitted again */
844 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK0x24,
845 &analog_val);
846 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN0x10;
847 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK0x24,
848 analog_val);
849
850 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G0xB,
851 &analog_val);
852 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL0xF0;
853 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G0xB,
854 analog_val);
855
856 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G0xC,
857 &analog_val);
858 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL0xF0;
859 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G0xC,
860 analog_val);
861
862 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN0xD,
863 &analog_val);
864 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL0xF0;
865 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN0xD,
866 analog_val);
867 }
868
869 /* Reset PHY */
870 if (hw->phy.reset_disable == FALSE0) {
871 /* PHY ops must be identified and initialized prior to reset */
872
873 /* Init PHY and function pointers, perform SFP setup */
874 phy_status = hw->phy.ops.init(hw);
875 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED-19)
876 goto reset_hw_out;
877 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT-20)
878 goto mac_reset_top;
879
880 hw->phy.ops.reset(hw);
881 }
882
883mac_reset_top:
884 /*
885 * Issue global reset to the MAC. This needs to be a SW reset.
886 * If link reset is used, it might reset the MAC when mng is using it
887 */
888 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00000
))) | IXGBE_CTRL_RST0x04000000;
889 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00000
), (ctrl)));
890 IXGBE_WRITE_FLUSH(hw)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00008
)));
891
892 /* Poll for reset bit to self-clear indicating reset is complete */
893 for (i = 0; i < 10; i++) {
894 usec_delay(1)(*delay_func)(1);
895 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00000
)));
896 if (!(ctrl & IXGBE_CTRL_RST0x04000000))
897 break;
898 }
899 if (ctrl & IXGBE_CTRL_RST0x04000000) {
900 status = IXGBE_ERR_RESET_FAILED-15;
901 DEBUGOUT("Reset polling failed to complete.\n");
902 }
903
904 msec_delay(50)(*delay_func)(1000 * (50));
905
906 /*
907 * Double resets are required for recovery from certain error
908 * conditions. Between resets, it is necessary to stall to allow time
909 * for any pending HW events to complete.
910 */
911 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED0x01) {
912 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED0x01;
913 goto mac_reset_top;
914 }
915
916 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x110B0
)));
917 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
918 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x110B0
), (gheccr)));
919
920 /*
921 * Store the original AUTOC value if it has not been
922 * stored off yet. Otherwise restore the stored original
923 * AUTOC value since the reset operation sets back to defaults.
924 */
925 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A0
)));
926 if (hw->mac.orig_link_settings_stored == FALSE0) {
927 hw->mac.orig_autoc = autoc;
928 hw->mac.orig_link_settings_stored = TRUE1;
929 } else if (autoc != hw->mac.orig_autoc) {
930 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A0
), (hw->mac.orig_autoc)));
931 }
932
933 /* Store the permanent mac address */
934 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
935
936 /*
937 * Store MAC address from RAR0, clear receive address registers, and
938 * clear the multicast table
939 */
940 hw->mac.ops.init_rx_addrs(hw);
941
942reset_hw_out:
943 if (phy_status != IXGBE_SUCCESS0)
944 status = phy_status;
945
946 return status;
947}
948
949/**
950 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
951 * @hw: pointer to hardware struct
952 * @rar: receive address register index to associate with a VMDq index
953 * @vmdq: VMDq set index
954 **/
955int32_t ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)
956{
957 uint32_t rar_high;
958 uint32_t rar_entries = hw->mac.num_rar_entries;
959
960 DEBUGFUNC("ixgbe_set_vmdq_82598");;
961
962 /* Make sure we are using a valid rar index range */
963 if (rar >= rar_entries) {
964 DEBUGOUT1("RAR index %d is out of range.\n", rar);
965 return IXGBE_ERR_INVALID_ARGUMENT-32;
966 }
967
968 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((rar
) <= 15) ? (0x05404 + ((rar) * 8)) : (0x0A204 + ((rar) * 8
))))));
969 rar_high &= ~IXGBE_RAH_VIND_MASK0x003C0000;
970 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT18) & IXGBE_RAH_VIND_MASK0x003C0000);
971 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((rar
) <= 15) ? (0x05404 + ((rar) * 8)) : (0x0A204 + ((rar) * 8
)))), (rar_high)));
972 return IXGBE_SUCCESS0;
973}
974
975/**
976 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
977 * @hw: pointer to hardware struct
978 * @rar: receive address register index to associate with a VMDq index
979 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
980 **/
981int32_t ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, uint32_t rar, uint32_t vmdq)
982{
983 uint32_t rar_high;
984 uint32_t rar_entries = hw->mac.num_rar_entries;
985
986 /* Make sure we are using a valid rar index range */
987 if (rar >= rar_entries) {
988 DEBUGOUT1("RAR index %d is out of range.\n", rar);
989 return IXGBE_ERR_INVALID_ARGUMENT-32;
990 }
991
992 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((rar
) <= 15) ? (0x05404 + ((rar) * 8)) : (0x0A204 + ((rar) * 8
))))));
993 if (rar_high & IXGBE_RAH_VIND_MASK0x003C0000) {
994 rar_high &= ~IXGBE_RAH_VIND_MASK0x003C0000;
995 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((((rar
) <= 15) ? (0x05404 + ((rar) * 8)) : (0x0A204 + ((rar) * 8
)))), (rar_high)));
996 }
997
998 return IXGBE_SUCCESS0;
999}
1000
1001/**
1002 * ixgbe_set_vfta_82598 - Set VLAN filter table
1003 * @hw: pointer to hardware structure
1004 * @vlan: VLAN id to write to VLAN filter
1005 * @vind: VMDq output index that maps queue to VLAN id in VFTA
1006 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
1007 * @vlvf_bypass: boolean flag - unused
1008 *
1009 * Turn on/off specified VLAN in the VLAN filter table.
1010 **/
1011int32_t ixgbe_set_vfta_82598(struct ixgbe_hw *hw, uint32_t vlan, uint32_t vind,
1012 bool_Bool vlan_on, bool_Bool vlvf_bypass)
1013{
1014 uint32_t regindex;
1015 uint32_t bitindex;
1016 uint32_t bits;
1017 uint32_t vftabyte;
1018
1019 DEBUGFUNC("ixgbe_set_vfta_82598");;
1020
1021 if (vlan > 4095)
1022 return IXGBE_ERR_PARAM-5;
1023
1024 /* Determine 32-bit word position in array */
1025 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1026
1027 /* Determine the location of the (VMD) queue index */
1028 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1029 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
1030
1031 /* Set the nibble for VMD queue index */
1032 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x0A200
+ ((vftabyte) * 0x200) + ((regindex) * 4)))));
1033 bits &= (~(0x0F << bitindex));
1034 bits |= (vind << bitindex);
1035 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x0A200
+ ((vftabyte) * 0x200) + ((regindex) * 4))), (bits)));
1036
1037 /* Determine the location of the bit for this VLAN id */
1038 bitindex = vlan & 0x1F; /* lower five bits */
1039
1040 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x0A000
+ ((regindex) * 4)))));
1041 if (vlan_on)
1042 /* Turn on this VLAN id */
1043 bits |= (1 << bitindex);
1044 else
1045 /* Turn off this VLAN id */
1046 bits &= ~(1 << bitindex);
1047 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x0A000
+ ((regindex) * 4))), (bits)));
1048
1049 return IXGBE_SUCCESS0;
1050}
1051
1052/**
1053 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1054 * @hw: pointer to hardware structure
1055 *
1056 * Clears the VLAN filer table, and the VMDq index associated with the filter
1057 **/
1058int32_t ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1059{
1060 uint32_t offset;
1061 uint32_t vlanbyte;
1062
1063 DEBUGFUNC("ixgbe_clear_vfta_82598");;
1064
1065 for (offset = 0; offset < hw->mac.vft_size; offset++)
1066 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x0A000
+ ((offset) * 4))), (0)));
1067
1068 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1069 for (offset = 0; offset < hw->mac.vft_size; offset++)
1070 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x0A200
+ ((vlanbyte) * 0x200) + ((offset) * 4))), (0)))
1071 0)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), ((0x0A200
+ ((vlanbyte) * 0x200) + ((offset) * 4))), (0)));
1072
1073 return IXGBE_SUCCESS0;
1074}
1075
1076/**
1077 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1078 * @hw: pointer to hardware structure
1079 * @reg: analog register to read
1080 * @val: read value
1081 *
1082 * Performs read operation to Atlas analog register specified.
1083 **/
1084int32_t ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t *val)
1085{
1086 uint32_t atlas_ctl;
1087
1088 DEBUGFUNC("ixgbe_read_analog_reg8_82598");;
1089
1090 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x04800
), (0x00010000 | (reg << 8))))
1091 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8))((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x04800
), (0x00010000 | (reg << 8))));
1092 IXGBE_WRITE_FLUSH(hw)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00008
)));
1093 usec_delay(10)(*delay_func)(10);
1094 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x04800
)));
1095 *val = (uint8_t)atlas_ctl;
1096
1097 return IXGBE_SUCCESS0;
1098}
1099
1100/**
1101 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1102 * @hw: pointer to hardware structure
1103 * @reg: atlas register to write
1104 * @val: value to write
1105 *
1106 * Performs write operation to Atlas analog register specified.
1107 **/
1108int32_t ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, uint32_t reg, uint8_t val)
1109{
1110 uint32_t atlas_ctl;
1111
1112 DEBUGFUNC("ixgbe_write_analog_reg8_82598");;
1113
1114 atlas_ctl = (reg << 8) | val;
1115 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x04800
), (atlas_ctl)));
1116 IXGBE_WRITE_FLUSH(hw)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00008
)));
1117 usec_delay(10)(*delay_func)(10);
1118
1119 return IXGBE_SUCCESS0;
1120}
1121
1122/**
1123 * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
1124 * @hw: pointer to hardware structure
1125 * @dev_addr: address to read from
1126 * @byte_offset: byte offset to read from dev_addr
1127 * @eeprom_data: value read
1128 *
1129 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1130 **/
1131int32_t ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, uint8_t dev_addr,
1132 uint8_t byte_offset, uint8_t *eeprom_data)
1133{
1134 int32_t status = IXGBE_SUCCESS0;
1135 uint16_t sfp_addr = 0;
1136 uint16_t sfp_data = 0;
1137 uint16_t sfp_stat = 0;
1138 uint16_t gssr;
1139 uint32_t i;
1140
1141 DEBUGFUNC("ixgbe_read_i2c_phy_82598");;
1142
1143 if (IXGBE_READ_REG(hw, IXGBE_STATUS)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x00008
))) & IXGBE_STATUS_LAN_ID_10x00000004)
1144 gssr = IXGBE_GSSR_PHY1_SM0x0004;
1145 else
1146 gssr = IXGBE_GSSR_PHY0_SM0x0002;
1147
1148 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS0)
1149 return IXGBE_ERR_SWFW_SYNC-16;
1150
1151 if (hw->phy.type == ixgbe_phy_nl) {
1152 /*
1153 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1154 * 0xC30D. These registers are used to talk to the SFP+
1155 * module's EEPROM through the SDA/SCL (I2C) interface.
1156 */
1157 sfp_addr = (dev_addr << 8) + byte_offset;
1158 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK0x100);
1159 hw->phy.ops.write_reg_mdi(hw,
1160 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR0xC30A,
1161 IXGBE_MDIO_PMA_PMD_DEV_TYPE0x1,
1162 sfp_addr);
1163
1164 /* Poll status */
1165 for (i = 0; i < 100; i++) {
1166 hw->phy.ops.read_reg_mdi(hw,
1167 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT0xC30C,
1168 IXGBE_MDIO_PMA_PMD_DEV_TYPE0x1,
1169 &sfp_stat);
1170 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK0x3;
1171 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS0x3)
1172 break;
1173 msec_delay(10)(*delay_func)(1000 * (10));
1174 }
1175
1176 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS0x1) {
1177 DEBUGOUT("EEPROM read did not pass.\n");
1178 status = IXGBE_ERR_SFP_NOT_PRESENT-20;
1179 goto out;
1180 }
1181
1182 /* Read data */
1183 hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA0xC30B,
1184 IXGBE_MDIO_PMA_PMD_DEV_TYPE0x1, &sfp_data);
1185
1186 *eeprom_data = (uint8_t)(sfp_data >> 8);
1187 } else {
1188 status = IXGBE_ERR_PHY-3;
1189 }
1190
1191out:
1192 hw->mac.ops.release_swfw_sync(hw, gssr);
1193 return status;
1194}
1195
1196/**
1197 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1198 * @hw: pointer to hardware structure
1199 * @byte_offset: EEPROM byte offset to read
1200 * @eeprom_data: value read
1201 *
1202 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1203 **/
1204int32_t ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, uint8_t byte_offset,
1205 uint8_t *eeprom_data)
1206{
1207 return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR0xA0,
1208 byte_offset, eeprom_data);
1209}
1210
1211/**
1212 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1213 * @hw: pointer to hardware structure
1214 *
1215 * Determines physical layer capabilities of the current configuration.
1216 **/
1217uint64_t ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1218{
1219 uint64_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN0;
1220 uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->read_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x042A0
)));
1221 uint32_t pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK0x00000180;
1222 uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK0x00000200;
1223 uint16_t ext_ability = 0;
1224
1225 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");;
1226
1227 hw->phy.ops.identify(hw);
1228
1229 /* Copper PHY must be checked before AUTOC LMS to determine correct
1230 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1231 switch (hw->phy.type) {
1232 case ixgbe_phy_tn:
1233 case ixgbe_phy_cu_unknown:
1234 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY0xB,
1235 IXGBE_MDIO_PMA_PMD_DEV_TYPE0x1, &ext_ability);
1236 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY0x0004)
1237 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T0x00001;
1238 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY0x0020)
1239 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T0x00002;
1240 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY0x0080)
1241 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX0x00004;
1242 goto out;
1243 default:
1244 break;
1245 }
1246
1247 switch (autoc & IXGBE_AUTOC_LMS_MASK(0x7 << 13)) {
1248 case IXGBE_AUTOC_LMS_1G_AN(0x2 << 13):
1249 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN(0x0 << 13):
1250 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX(0x1 << 9))
1251 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX0x00200;
1252 else
1253 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX0x00400;
1254 break;
1255 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN(0x1 << 13):
1256 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4(0x2 << 7))
1257 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX40x00100;
1258 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4(0x1 << 7))
1259 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX40x00080;
1260 else /* XAUI */
1261 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN0;
1262 break;
1263 case IXGBE_AUTOC_LMS_KX4_AN(0x4 << 13):
1264 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN(0x6 << 13):
1265 if (autoc & IXGBE_AUTOC_KX_SUPP0x40000000)
1266 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX0x00200;
1267 if (autoc & IXGBE_AUTOC_KX4_SUPP0x80000000)
1268 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX40x00080;
1269 break;
1270 default:
1271 break;
1272 }
1273
1274 if (hw->phy.type == ixgbe_phy_nl) {
1275 hw->phy.ops.identify_sfp(hw);
1276
1277 switch (hw->phy.sfp_type) {
1278 case ixgbe_sfp_type_da_cu:
1279 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU0x00008;
1280 break;
1281 case ixgbe_sfp_type_sr:
1282 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR0x00040;
1283 break;
1284 case ixgbe_sfp_type_lr:
1285 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR0x00010;
1286 break;
1287 default:
1288 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN0;
1289 break;
1290 }
1291 }
1292
1293 switch (hw->device_id) {
1294 case IXGBE_DEV_ID_82598_DA_DUAL_PORT0x10F1:
1295 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU0x00008;
1296 break;
1297 case IXGBE_DEV_ID_82598AF_DUAL_PORT0x10C6:
1298 case IXGBE_DEV_ID_82598AF_SINGLE_PORT0x10C7:
1299 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM0x10E1:
1300 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR0x00040;
1301 break;
1302 case IXGBE_DEV_ID_82598EB_XF_LR0x10F4:
1303 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR0x00010;
1304 break;
1305 default:
1306 break;
1307 }
1308
1309out:
1310 return physical_layer;
1311}
1312
1313/**
1314 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1315 * port devices.
1316 * @hw: pointer to the HW structure
1317 *
1318 * Calls common function and corrects issue with some single port devices
1319 * that enable LAN1 but not LAN0.
1320 **/
1321void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1322{
1323 struct ixgbe_bus_info *bus = &hw->bus;
1324 uint16_t pci_gen = 0;
1325 uint16_t pci_ctrl2 = 0;
1326
1327 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");;
1328
1329 ixgbe_set_lan_id_multi_port_pcie(hw);
1330
1331 /* check if LAN0 is disabled */
1332 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR0x06, &pci_gen);
1333 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1334
1335 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL20x5, &pci_ctrl2);
1336
1337 /* if LAN0 is completely disabled force function to 0 */
1338 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE0x2) &&
1339 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT0x1) &&
1340 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE0x8)) {
1341
1342 bus->func = 0;
1343 }
1344 }
1345}
1346
1347/**
1348 * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit
1349 * @hw: pointer to hardware structure
1350 * @regval: register value to write to RXCTRL
1351 *
1352 * Enables the Rx DMA unit
1353 **/
1354int32_t ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, uint32_t regval)
1355{
1356 DEBUGFUNC("ixgbe_enable_rx_dma_82598");;
1357
1358 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval)((((struct ixgbe_osdep *)(hw)->back)->os_memt)->write_4
((((struct ixgbe_osdep *)(hw)->back)->os_memh), (0x03000
), (regval)));
1359
1360 return IXGBE_SUCCESS0;
1361}