/usr/src/sys/dev/ic/re.c

Bug Summary

File:	dev/ic/re.c
Warning:	line 1753, column 16 Access to field 'rl_cmdstat' results in a dereference of an undefined pointer value (loaded from variable 'd')
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name re.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/ic/re.c
1/*	$OpenBSD: re.c,v 1.211 2021/05/17 11:59:53 visa Exp $	*/
2/*	$FreeBSD: if_re.c,v 1.31 2004/09/04 07:54:05 ru Exp $	*/
3/*
* Copyright (c) 1997, 1998-2003
*	Bill Paul <wpaul@windriver.com>.  All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
*    must display the following acknowledgement:
*	This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
*    may be used to endorse or promote products derived from this software
*    without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/

35/*
* Realtek 8139C+/8169/8169S/8110S PCI NIC driver
*
* Written by Bill Paul <wpaul@windriver.com>
* Senior Networking Software Engineer
* Wind River Systems
*/

43/*
* This driver is designed to support Realtek's next generation of
* 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
* seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
* RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
*
* The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
* with the older 8139 family, however it also supports a special
* C+ mode of operation that provides several new performance enhancing
* features. These include:
*
*	o Descriptor based DMA mechanism. Each descriptor represents
*	  a single packet fragment. Data buffers may be aligned on
*	  any byte boundary.
*
*	o 64-bit DMA
*
*	o TCP/IP checksum offload for both RX and TX
*
*	o High and normal priority transmit DMA rings
*
*	o VLAN tag insertion and extraction
*
*	o TCP large send (segmentation offload)
*
* Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
* programming API is fairly straightforward. The RX filtering, EEPROM
* access and PHY access is the same as it is on the older 8139 series
* chips.
*
* The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
* same programming API and feature set as the 8139C+ with the following
* differences and additions:
*
*	o 1000Mbps mode
*
*	o Jumbo frames
*
* 	o GMII and TBI ports/registers for interfacing with copper
*	  or fiber PHYs
*
*      o RX and TX DMA rings can have up to 1024 descriptors
*        (the 8139C+ allows a maximum of 64)
*
*	o Slight differences in register layout from the 8139C+
*
* The TX start and timer interrupt registers are at different locations
* on the 8169 than they are on the 8139C+. Also, the status word in the
* RX descriptor has a slightly different bit layout. The 8169 does not
* have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
* copper gigE PHY.
*
* The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
* (the 'S' stands for 'single-chip'). These devices have the same
* programming API as the older 8169, but also have some vendor-specific
* registers for the on-board PHY. The 8110S is a LAN-on-motherboard
* part designed to be pin-compatible with the Realtek 8100 10/100 chip.
* 
* This driver takes advantage of the RX and TX checksum offload and
* VLAN tag insertion/extraction features. It also implements TX
* interrupt moderation using the timer interrupt registers, which
* significantly reduces TX interrupt load. There is also support
* for jumbo frames, however the 8169/8169S/8110S can not transmit
* jumbo frames larger than 7440, so the max MTU possible with this
* driver is 7422 bytes.
*/

110#include "bpfilter.h"
111#include "vlan.h"

113#include <sys/param.h>
114#include <sys/endian.h>
115#include <sys/systm.h>
116#include <sys/sockio.h>
117#include <sys/mbuf.h>
118#include <sys/malloc.h>
119#include <sys/kernel.h>
120#include <sys/device.h>
121#include <sys/timeout.h>
122#include <sys/socket.h>
123#include <sys/atomic.h>

125#include <machine/bus.h>

127#include <net/if.h>
128#include <net/if_media.h>

130#include <netinet/in.h>
131#include <netinet/ip.h>
132#include <netinet/if_ether.h>

134#if NBPFILTER1 > 0
135#include <net/bpf.h>
136#endif

138#include <dev/mii/mii.h>
139#include <dev/mii/miivar.h>

141#include <dev/pci/pcidevs.h>

143#include <dev/ic/rtl81x9reg.h>
144#include <dev/ic/revar.h>

146#ifdef RE_DEBUG
147int redebug = 0;
148#define DPRINTF(x)	do { if (redebug) printf x; } while (0)
149#else
150#define DPRINTF(x)
151#endif

153static inline void re_set_bufaddr(struct rl_desc *, bus_addr_t);

155int	re_encap(struct rl_softc *, unsigned int, struct mbuf *);

157int	re_newbuf(struct rl_softc *);
158int	re_rx_list_init(struct rl_softc *);
159void	re_rx_list_fill(struct rl_softc *);
160int	re_tx_list_init(struct rl_softc *);
161int	re_rxeof(struct rl_softc *);
162int	re_txeof(struct rl_softc *);
163void	re_tick(void *);
164void	re_start(struct ifqueue *);
165void	re_txstart(void *);
166int	re_ioctl(struct ifnet *, u_long, caddr_t);
167void	re_watchdog(struct ifnet *);
168int	re_ifmedia_upd(struct ifnet *);
169void	re_ifmedia_sts(struct ifnet *, struct ifmediareq *);

171void	re_set_jumbo(struct rl_softc *);

173void	re_eeprom_putbyte(struct rl_softc *, int);
174void	re_eeprom_getword(struct rl_softc *, int, u_int16_t *);
175void	re_read_eeprom(struct rl_softc *, caddr_t, int, int);

177int	re_gmii_readreg(struct device *, int, int);
178void	re_gmii_writereg(struct device *, int, int, int);

180int	re_miibus_readreg(struct device *, int, int);
181void	re_miibus_writereg(struct device *, int, int, int);
182void	re_miibus_statchg(struct device *);

184void	re_iff(struct rl_softc *);

186void	re_setup_hw_im(struct rl_softc *);
187void	re_setup_sim_im(struct rl_softc *);
188void	re_disable_hw_im(struct rl_softc *);
189void	re_disable_sim_im(struct rl_softc *);
190void	re_config_imtype(struct rl_softc *, int);
191void	re_setup_intr(struct rl_softc *, int, int);
192#ifndef SMALL_KERNEL
193int	re_wol(struct ifnet*, int);
194#endif

196void	in_delayed_cksum(struct mbuf *);

198struct cfdriver re_cd = {
0, "re", DV_IFNET
200};

202#define EE_SET(x)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) |
 x)))					\
CSR_WRITE_1(sc, RL_EECMD,			\((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) |
 x)))
CSR_READ_1(sc, RL_EECMD) | x)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) |
 x)))

206#define EE_CLR(x)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) &
 ~x)))					\
CSR_WRITE_1(sc, RL_EECMD,			\((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) &
 ~x)))
CSR_READ_1(sc, RL_EECMD) & ~x)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) &
 ~x)))

210#define RL_FRAMELEN(mtu)(mtu + ((6 * 2) + 2) + 4 + 4)				\
(mtu + ETHER_HDR_LEN((6 * 2) + 2) + ETHER_CRC_LEN4 +		\
ETHER_VLAN_ENCAP_LEN4)

214static const struct re_revision {
u_int32_t		re_chipid;
const char		*re_name;
217} re_revisions[] = {
{ RL_HWREV_81000x78800000,	"RTL8100" },
{ RL_HWREV_8100E0x30800000,	"RTL8100E" },
{ RL_HWREV_8100E_SPIN20x38800000, "RTL8100E 2" },
{ RL_HWREV_81010x74c00000,	"RTL8101" },
{ RL_HWREV_8101E0x34000000,	"RTL8101E" },
{ RL_HWREV_8102E0x34800000,	"RTL8102E" },
{ RL_HWREV_8106E0x44800000,	"RTL8106E" },
{ RL_HWREV_8401E0x24000000,	"RTL8401E" },
{ RL_HWREV_84020x44000000,	"RTL8402" },
{ RL_HWREV_84110x48800000,	"RTL8411" },
{ RL_HWREV_8411B0x5c800000,	"RTL8411B" },
{ RL_HWREV_8102EL0x24800000,	"RTL8102EL" },
{ RL_HWREV_8102EL_SPIN10x24C00000, "RTL8102EL 1" },
{ RL_HWREV_8103E0x34C00000,       "RTL8103E" },
{ RL_HWREV_8110S0x04000000,	"RTL8110S" },
{ RL_HWREV_8139CPLUS0x74800000,	"RTL8139C+" },
{ RL_HWREV_8168B_SPIN10x30000000,	"RTL8168 1" },
{ RL_HWREV_8168B_SPIN20x38000000,	"RTL8168 2" },
{ RL_HWREV_8168B_SPIN30x38400000,	"RTL8168 3" },
{ RL_HWREV_8168C0x3c000000,	"RTL8168C/8111C" },
{ RL_HWREV_8168C_SPIN20x3c400000,	"RTL8168C/8111C" },
{ RL_HWREV_8168CP0x3c800000,	"RTL8168CP/8111CP" },
{ RL_HWREV_8168F0x48000000,	"RTL8168F/8111F" },
{ RL_HWREV_8168G0x4c000000,	"RTL8168G/8111G" },
{ RL_HWREV_8168GU0x50800000,	"RTL8168GU/8111GU" },
{ RL_HWREV_8168H0x54000000,	"RTL8168H/8111H" },
{ RL_HWREV_8105E0x40800000,	"RTL8105E" },
{ RL_HWREV_8105E_SPIN10x40C00000,	"RTL8105E" },
{ RL_HWREV_8168D0x28000000,	"RTL8168D/8111D" },
{ RL_HWREV_8168DP0x28800000,      "RTL8168DP/8111DP" },
{ RL_HWREV_8168E0x2C000000,       "RTL8168E/8111E" },
{ RL_HWREV_8168E_VL0x2C800000,	"RTL8168E/8111E-VL" },
{ RL_HWREV_8168EP0x50000000,	"RTL8168EP/8111EP" },
{ RL_HWREV_8168FP0x54800000,	"RTL8168FP/8111FP" },
{ RL_HWREV_81690x00000000,	"RTL8169" },
{ RL_HWREV_8169_8110SB0x10000000,	"RTL8169/8110SB" },
{ RL_HWREV_8169_8110SBL0x7cc00000, "RTL8169SBL" },
{ RL_HWREV_8169_8110SCd0x18000000, "RTL8169/8110SCd" },
{ RL_HWREV_8169_8110SCe0x98000000, "RTL8169/8110SCe" },
{ RL_HWREV_8169S0x00800000,	"RTL8169S" },

{ 0, NULL((void *)0) }
260};


263static inline void
264re_set_bufaddr(struct rl_desc *d, bus_addr_t addr)
265{
d->rl_bufaddr_lo = htole32((uint32_t)addr)((__uint32_t)((uint32_t)addr));
if (sizeof(bus_addr_t) == sizeof(uint64_t))
d->rl_bufaddr_hi = htole32((uint64_t)addr >> 32)((__uint32_t)((uint64_t)addr >> 32));
else
d->rl_bufaddr_hi = 0;
271}

273/*
* Send a read command and address to the EEPROM, check for ACK.
*/
276void
277re_eeprom_putbyte(struct rl_softc *sc, int addr)
278{
int	d, i;

d = addr | (RL_9346_READ0x6 << sc->rl_eewidth);

/*
* Feed in each bit and strobe the clock.
*/

for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
if (d & i)
	EE_SET(RL_EE_DATAIN)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) |
 0x02)));
else
	EE_CLR(RL_EE_DATAIN)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) &
 ~0x02)));
DELAY(100)(*delay_func)(100);
EE_SET(RL_EE_CLK)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) |
 0x04)));
DELAY(150)(*delay_func)(150);
EE_CLR(RL_EE_CLK)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) &
 ~0x04)));
DELAY(100)(*delay_func)(100);
}
298}

300/*
* Read a word of data stored in the EEPROM at address 'addr.'
*/
303void
304re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
305{
int		i;
u_int16_t	word = 0;

/*
* Send address of word we want to read.
*/
re_eeprom_putbyte(sc, addr);

/*
* Start reading bits from EEPROM.
*/
for (i = 0x8000; i; i >>= 1) {
EE_SET(RL_EE_CLK)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) |
 0x04)));
DELAY(100)(*delay_func)(100);
if (CSR_READ_1(sc, RL_EECMD)((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) & RL_EE_DATAOUT0x01)
	word |= i;
EE_CLR(RL_EE_CLK)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) &
 ~0x04)));
DELAY(100)(*delay_func)(100);
}

*dest = word;
327}

329/*
* Read a sequence of words from the EEPROM.
*/
332void
333re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
334{
int		i;
u_int16_t	word = 0, *ptr;

CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) |
 (0x80))));

DELAY(100)(*delay_func)(100);

for (i = 0; i < cnt; i++) {
CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) |
 (0x08))));
re_eeprom_getword(sc, off + i, &word);
CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) &
 ~(0x08))));
ptr = (u_int16_t *)(dest + (i * 2));
*ptr = word;
}

CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0050))) &
 ~(0x80))));
351}

353int
354re_gmii_readreg(struct device *self, int phy, int reg)
355{
struct rl_softc	*sc = (struct rl_softc *)self;
u_int32_t	rval;
int		i;

if (phy != 7)
return (0);

/* Let the rgephy driver read the GMEDIASTAT register */

if (reg == RL_GMEDIASTAT0x006C) {
rval = CSR_READ_1(sc, RL_GMEDIASTAT)((sc->rl_btag)->read_1((sc->rl_bhandle), (0x006C)));
return (rval);
}

CSR_WRITE_4(sc, RL_PHYAR, reg << 16)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0060), (
reg << 16)));

for (i = 0; i < RL_PHY_TIMEOUT20; i++) {
rval = CSR_READ_4(sc, RL_PHYAR)((sc->rl_btag)->read_4((sc->rl_bhandle), (0x0060)));
if (rval & RL_PHYAR_BUSY0x80000000)
	break;
DELAY(25)(*delay_func)(25);
}

if (i == RL_PHY_TIMEOUT20) {
printf ("%s: PHY read failed\n", sc->sc_dev.dv_xname);
return (0);
}

DELAY(20)(*delay_func)(20);

return (rval & RL_PHYAR_PHYDATA0x0000FFFF);
387}

389void
390re_gmii_writereg(struct device *dev, int phy, int reg, int data)
391{
struct rl_softc	*sc = (struct rl_softc *)dev;
u_int32_t	rval;
int		i;

CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0060), (
(reg << 16) | (data & 0x0000FFFF) | 0x80000000)))
   (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0060), (
(reg << 16) | (data & 0x0000FFFF) | 0x80000000)));

for (i = 0; i < RL_PHY_TIMEOUT20; i++) {
rval = CSR_READ_4(sc, RL_PHYAR)((sc->rl_btag)->read_4((sc->rl_bhandle), (0x0060)));
if (!(rval & RL_PHYAR_BUSY0x80000000))
	break;
DELAY(25)(*delay_func)(25);
}

if (i == RL_PHY_TIMEOUT20)
printf ("%s: PHY write failed\n", sc->sc_dev.dv_xname);

DELAY(20)(*delay_func)(20);
410}

412int
413re_miibus_readreg(struct device *dev, int phy, int reg)
414{
struct rl_softc	*sc = (struct rl_softc *)dev;
u_int16_t	rval = 0;
u_int16_t	re8139_reg = 0;
int		s;

s = splnet()splraise(0x7);

if (sc->sc_hwrev != RL_HWREV_8139CPLUS0x74800000) {
rval = re_gmii_readreg(dev, phy, reg);
splx(s)spllower(s);
return (rval);
}

/* Pretend the internal PHY is only at address 0 */
if (phy) {
splx(s)spllower(s);
return (0);
}
switch(reg) {
case MII_BMCR0x00:
re8139_reg = RL_BMCR0x0062;
break;
case MII_BMSR0x01:
re8139_reg = RL_BMSR0x0064;
break;
case MII_ANAR0x04:
re8139_reg = RL_ANAR0x0066;
break;
case MII_ANER0x06:
re8139_reg = RL_ANER0x006A;
break;
case MII_ANLPAR0x05:
re8139_reg = RL_LPAR0x0068;
break;
case MII_PHYIDR10x02:
case MII_PHYIDR20x03:
splx(s)spllower(s);
return (0);
/*
* Allow the rlphy driver to read the media status
* register. If we have a link partner which does not
* support NWAY, this is the register which will tell
* us the results of parallel detection.
*/
case RL_MEDIASTAT0x0058:
rval = CSR_READ_1(sc, RL_MEDIASTAT)((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0058)));
splx(s)spllower(s);
return (rval);
default:
printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg);
splx(s)spllower(s);
return (0);
}
rval = CSR_READ_2(sc, re8139_reg)((sc->rl_btag)->read_2((sc->rl_bhandle), (re8139_reg
)));
if (re8139_reg == RL_BMCR0x0062) {
/* 8139C+ has different bit layout. */
rval &= ~(BMCR_LOOP0x4000 | BMCR_ISO0x0400);
}
splx(s)spllower(s);
return (rval);
475}

477void
478re_miibus_writereg(struct device *dev, int phy, int reg, int data)
479{
struct rl_softc	*sc = (struct rl_softc *)dev;
u_int16_t	re8139_reg = 0;
int		s;

s = splnet()splraise(0x7);

if (sc->sc_hwrev != RL_HWREV_8139CPLUS0x74800000) {
re_gmii_writereg(dev, phy, reg, data);
splx(s)spllower(s);
return;
}

/* Pretend the internal PHY is only at address 0 */
if (phy) {
splx(s)spllower(s);
return;
}
switch(reg) {
case MII_BMCR0x00:
re8139_reg = RL_BMCR0x0062;
/* 8139C+ has different bit layout. */
data &= ~(BMCR_LOOP0x4000 | BMCR_ISO0x0400);
break;
case MII_BMSR0x01:
re8139_reg = RL_BMSR0x0064;
break;
case MII_ANAR0x04:
re8139_reg = RL_ANAR0x0066;
break;
case MII_ANER0x06:
re8139_reg = RL_ANER0x006A;
break;
case MII_ANLPAR0x05:
re8139_reg = RL_LPAR0x0068;
break;
case MII_PHYIDR10x02:
case MII_PHYIDR20x03:
splx(s)spllower(s);
return;
break;
default:
printf("%s: bad phy register %x\n", sc->sc_dev.dv_xname, reg);
splx(s)spllower(s);
return;
}
CSR_WRITE_2(sc, re8139_reg, data)((sc->rl_btag)->write_2((sc->rl_bhandle), (re8139_reg
), (data)));
splx(s)spllower(s);
527}

529void
530re_miibus_statchg(struct device *dev)
531{
struct rl_softc		*sc = (struct rl_softc *)dev;
struct ifnet		*ifp = &sc->sc_arpcom.ac_if;
struct mii_data		*mii = &sc->sc_mii;

if ((ifp->if_flags & IFF_RUNNING0x40) == 0)
return;

sc->rl_flags &= ~RL_FLAG_LINK0x00002000;
if ((mii->mii_media_status & (IFM_ACTIVE0x0000000000000002ULL | IFM_AVALID0x0000000000000001ULL)) ==
   (IFM_ACTIVE0x0000000000000002ULL | IFM_AVALID0x0000000000000001ULL)) {
switch (IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL)) {
case IFM_10_T3:
case IFM_100_TX6:
	sc->rl_flags |= RL_FLAG_LINK0x00002000;
	break;
case IFM_1000_T16:
	if ((sc->rl_flags & RL_FLAG_FASTETHER0x00040000) != 0)
		break;
	sc->rl_flags |= RL_FLAG_LINK0x00002000;
	break;
default:
	break;
}
}

/*
* Realtek controllers do not provide an interface to
* Tx/Rx MACs for resolved speed, duplex and flow-control
* parameters.
*/
562}

564void
565re_iff(struct rl_softc *sc)
566{
struct ifnet		*ifp = &sc->sc_arpcom.ac_if;
int			h = 0;
u_int32_t		hashes[2];
u_int32_t		rxfilt;
struct arpcom		*ac = &sc->sc_arpcom;
struct ether_multi	*enm;
struct ether_multistep	step;

rxfilt = CSR_READ_4(sc, RL_RXCFG)((sc->rl_btag)->read_4((sc->rl_bhandle), (0x0044)));
rxfilt &= ~(RL_RXCFG_RX_ALLPHYS0x00000001 | RL_RXCFG_RX_BROAD0x00000008 |
   RL_RXCFG_RX_INDIV0x00000002 | RL_RXCFG_RX_MULTI0x00000004);
ifp->if_flags &= ~IFF_ALLMULTI0x200;

/*
* Always accept frames destined to our station address.
* Always accept broadcast frames.
*/
rxfilt |= RL_RXCFG_RX_INDIV0x00000002 | RL_RXCFG_RX_BROAD0x00000008;

if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI0x200;
rxfilt |= RL_RXCFG_RX_MULTI0x00000004;
if (ifp->if_flags & IFF_PROMISC0x100)
	rxfilt |= RL_RXCFG_RX_ALLPHYS0x00000001;
hashes[0] = hashes[1] = 0xFFFFFFFF;
} else {
rxfilt |= RL_RXCFG_RX_MULTI0x00000004;
/* Program new filter. */
bzero(hashes, sizeof(hashes))__builtin_bzero((hashes), (sizeof(hashes)));

ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	h = ether_crc32_be(enm->enm_addrlo,
	    ETHER_ADDR_LEN6) >> 26;

	if (h < 32)
		hashes[0] |= (1 << h);
	else
		hashes[1] |= (1 << (h - 32));

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}
}

/*
* For some unfathomable reason, Realtek decided to reverse
* the order of the multicast hash registers in the PCI Express
* parts. This means we have to write the hash pattern in reverse
* order for those devices.
*/
if (sc->rl_flags & RL_FLAG_PCIE0x00000004) {
CSR_WRITE_4(sc, RL_MAR0, swap32(hashes[1]))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0008), (
(__uint32_t)(__builtin_constant_p(hashes[1]) ? (__uint32_t)((
(__uint32_t)(hashes[1]) & 0xff) << 24 | ((__uint32_t
)(hashes[1]) & 0xff00) << 8 | ((__uint32_t)(hashes[
1]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[1]) &
 0xff000000) >> 24) : __swap32md(hashes[1])))));
CSR_WRITE_4(sc, RL_MAR4, swap32(hashes[0]))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x000C), (
(__uint32_t)(__builtin_constant_p(hashes[0]) ? (__uint32_t)((
(__uint32_t)(hashes[0]) & 0xff) << 24 | ((__uint32_t
)(hashes[0]) & 0xff00) << 8 | ((__uint32_t)(hashes[
0]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[0]) &
 0xff000000) >> 24) : __swap32md(hashes[0])))));
} else {
CSR_WRITE_4(sc, RL_MAR0, hashes[0])((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0008), (
hashes[0])));
CSR_WRITE_4(sc, RL_MAR4, hashes[1])((sc->rl_btag)->write_4((sc->rl_bhandle), (0x000C), (
hashes[1])));
}

CSR_WRITE_4(sc, RL_RXCFG, rxfilt)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0044), (
rxfilt)));
626}

628void
629re_reset(struct rl_softc *sc)
630{
int	i;

CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0037), (
0x0010)));

for (i = 0; i < RL_TIMEOUT1000; i++) {
DELAY(10)(*delay_func)(10);
if (!(CSR_READ_1(sc, RL_COMMAND)((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0037))) & RL_CMD_RESET0x0010))
	break;
}
if (i == RL_TIMEOUT1000)
printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);

if (sc->rl_flags & RL_FLAG_MACRESET0x00000200)
CSR_WRITE_1(sc, RL_LDPS, 1)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0082), (
1)));
645}

647/*
* Attach the interface. Allocate softc structures, do ifmedia
* setup and ethernet/BPF attach.
*/
651int
652re_attach(struct rl_softc *sc, const char *intrstr)
653{
u_char		eaddr[ETHER_ADDR_LEN6];
u_int16_t	as[ETHER_ADDR_LEN6 / 2];
struct ifnet	*ifp;
u_int16_t	re_did = 0;
int		error = 0, i;
const struct re_revision *rr;
const char	*re_name = NULL((void *)0);

sc->sc_hwrev = CSR_READ_4(sc, RL_TXCFG)((sc->rl_btag)->read_4((sc->rl_bhandle), (0x0040))) & RL_TXCFG_HWREV0x7C800000;

switch (sc->sc_hwrev) {
case RL_HWREV_8139CPLUS0x74800000:
sc->rl_flags |= RL_FLAG_FASTETHER0x00040000 | RL_FLAG_AUTOPAD0x00001000;
sc->rl_max_mtu = RL_MTU(1518 - ((6 * 2) + 2) - 4);
break;
case RL_HWREV_8100E0x30800000:
case RL_HWREV_8100E_SPIN20x38800000:
case RL_HWREV_8101E0x34000000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_FASTETHER0x00040000;
sc->rl_max_mtu = RL_MTU(1518 - ((6 * 2) + 2) - 4);
break;
case RL_HWREV_8103E0x34C00000:
sc->rl_flags |= RL_FLAG_MACSLEEP0x00000800;
/* FALLTHROUGH */
case RL_HWREV_8102E0x34800000:
case RL_HWREV_8102EL0x24800000:
case RL_HWREV_8102EL_SPIN10x24C00000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PAR0x00000010 |
    RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 | RL_FLAG_FASTETHER0x00040000 |
    RL_FLAG_CMDSTOP0x00000400 | RL_FLAG_AUTOPAD0x00001000;
sc->rl_max_mtu = RL_MTU(1518 - ((6 * 2) + 2) - 4);
break;
case RL_HWREV_8401E0x24000000:
case RL_HWREV_8105E0x40800000:
case RL_HWREV_8105E_SPIN10x40C00000:
case RL_HWREV_8106E0x44800000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PHYWAKE_PM0x00004000 |
    RL_FLAG_PAR0x00000010 | RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 |
    RL_FLAG_FASTETHER0x00040000 | RL_FLAG_CMDSTOP0x00000400 | RL_FLAG_AUTOPAD0x00001000;
sc->rl_max_mtu = RL_MTU(1518 - ((6 * 2) + 2) - 4);
break;
case RL_HWREV_84020x44000000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PHYWAKE_PM0x00004000 |
    RL_FLAG_PAR0x00000010 | RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 |
    RL_FLAG_FASTETHER0x00040000 | RL_FLAG_CMDSTOP0x00000400 | RL_FLAG_AUTOPAD0x00001000 |
    RL_FLAG_CMDSTOP_WAIT_TXQ0x00080000;
sc->rl_max_mtu = RL_MTU(1518 - ((6 * 2) + 2) - 4);
break;
case RL_HWREV_8168B_SPIN10x30000000:
case RL_HWREV_8168B_SPIN20x38000000:
sc->rl_flags |= RL_FLAG_WOLRXENB0x00800000;
/* FALLTHROUGH */
case RL_HWREV_8168B_SPIN30x38400000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_MACSTAT0x00000040;
sc->rl_max_mtu = RL_MTU(1518 - ((6 * 2) + 2) - 4);
break;
case RL_HWREV_8168C_SPIN20x3c400000:
sc->rl_flags |= RL_FLAG_MACSLEEP0x00000800;
/* FALLTHROUGH */
case RL_HWREV_8168C0x3c000000:
case RL_HWREV_8168CP0x3c800000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PAR0x00000010 |
    RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 | RL_FLAG_CMDSTOP0x00000400 |
    RL_FLAG_AUTOPAD0x00001000 | RL_FLAG_JUMBOV20x00100000 | RL_FLAG_WOL_MANLINK0x00200000;
sc->rl_max_mtu = RL_JUMBO_MTU_6K((6 * 1024) - ((6 * 2) + 2) - 4 - 4);
break;
case RL_HWREV_8168D0x28000000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PHYWAKE_PM0x00004000 |
    RL_FLAG_PAR0x00000010 | RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 |
    RL_FLAG_CMDSTOP0x00000400 | RL_FLAG_AUTOPAD0x00001000 | RL_FLAG_JUMBOV20x00100000 |
    RL_FLAG_WOL_MANLINK0x00200000;
sc->rl_max_mtu = RL_JUMBO_MTU_9K((9 * 1024) - ((6 * 2) + 2) - 4 - 4);
break;
case RL_HWREV_8168DP0x28800000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PAR0x00000010 |
    RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 | RL_FLAG_AUTOPAD0x00001000 |
    RL_FLAG_JUMBOV20x00100000 | RL_FLAG_WAIT_TXPOLL0x00400000 | RL_FLAG_WOL_MANLINK0x00200000;
sc->rl_max_mtu = RL_JUMBO_MTU_9K((9 * 1024) - ((6 * 2) + 2) - 4 - 4);
break;
case RL_HWREV_8168E0x2C000000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PHYWAKE_PM0x00004000 |
    RL_FLAG_PAR0x00000010 | RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 |
    RL_FLAG_CMDSTOP0x00000400 | RL_FLAG_AUTOPAD0x00001000 | RL_FLAG_JUMBOV20x00100000 |
    RL_FLAG_WOL_MANLINK0x00200000;
sc->rl_max_mtu = RL_JUMBO_MTU_9K((9 * 1024) - ((6 * 2) + 2) - 4 - 4);
break;
case RL_HWREV_8168E_VL0x2C800000:
sc->rl_flags |= RL_FLAG_EARLYOFF0x00008000 | RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PAR0x00000010 |
    RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 | RL_FLAG_CMDSTOP0x00000400 |
    RL_FLAG_AUTOPAD0x00001000 | RL_FLAG_JUMBOV20x00100000 | RL_FLAG_CMDSTOP_WAIT_TXQ0x00080000 |
    RL_FLAG_WOL_MANLINK0x00200000;
sc->rl_max_mtu = RL_JUMBO_MTU_6K((6 * 1024) - ((6 * 2) + 2) - 4 - 4);
break;
case RL_HWREV_8168F0x48000000:
sc->rl_flags |= RL_FLAG_EARLYOFF0x00008000;
/* FALLTHROUGH */
case RL_HWREV_84110x48800000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PAR0x00000010 |
    RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 | RL_FLAG_CMDSTOP0x00000400 |
    RL_FLAG_AUTOPAD0x00001000 | RL_FLAG_JUMBOV20x00100000 | RL_FLAG_CMDSTOP_WAIT_TXQ0x00080000 |
    RL_FLAG_WOL_MANLINK0x00200000;
sc->rl_max_mtu = RL_JUMBO_MTU_9K((9 * 1024) - ((6 * 2) + 2) - 4 - 4);
break;
case RL_HWREV_8168EP0x50000000:
case RL_HWREV_8168FP0x54800000:
case RL_HWREV_8168G0x4c000000:
case RL_HWREV_8168GU0x50800000:
case RL_HWREV_8168H0x54000000:
case RL_HWREV_8411B0x5c800000:
if (sc->sc_product == PCI_PRODUCT_REALTEK_RT8101E0x8136) {
	/* RTL8106EUS */
	sc->rl_flags |= RL_FLAG_FASTETHER0x00040000;
	sc->rl_max_mtu = RL_MTU(1518 - ((6 * 2) + 2) - 4);
} else {
	sc->rl_flags |= RL_FLAG_JUMBOV20x00100000 | RL_FLAG_WOL_MANLINK0x00200000;
	sc->rl_max_mtu = RL_JUMBO_MTU_9K((9 * 1024) - ((6 * 2) + 2) - 4 - 4);
}

sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008 | RL_FLAG_PAR0x00000010 |
    RL_FLAG_DESCV20x00000020 | RL_FLAG_MACSTAT0x00000040 | RL_FLAG_CMDSTOP0x00000400 |
    RL_FLAG_AUTOPAD0x00001000 | RL_FLAG_CMDSTOP_WAIT_TXQ0x00080000 |
    RL_FLAG_EARLYOFFV20x00010000 | RL_FLAG_RXDV_GATED0x00020000;
break;
case RL_HWREV_8169_8110SB0x10000000:
case RL_HWREV_8169_8110SBL0x7cc00000:
case RL_HWREV_8169_8110SCd0x18000000:
case RL_HWREV_8169_8110SCe0x98000000:
sc->rl_flags |= RL_FLAG_PHYWAKE0x00000008;
/* FALLTHROUGH */
case RL_HWREV_81690x00000000:
case RL_HWREV_8169S0x00800000:
case RL_HWREV_8110S0x04000000:
sc->rl_flags |= RL_FLAG_MACRESET0x00000200;
sc->rl_max_mtu = RL_JUMBO_MTU_7K((7 * 1024) - ((6 * 2) + 2) - 4 - 4);
break;
default:
break;
}

if (sc->sc_hwrev == RL_HWREV_8139CPLUS0x74800000) {
sc->rl_cfg0 = RL_8139_CFG00x0051;
sc->rl_cfg1 = RL_8139_CFG10x0052;
sc->rl_cfg2 = 0;
sc->rl_cfg3 = RL_8139_CFG30x0059;
sc->rl_cfg4 = RL_8139_CFG40x005A;
sc->rl_cfg5 = RL_8139_CFG50x00D8;
} else {
sc->rl_cfg0 = RL_CFG00x0051;
sc->rl_cfg1 = RL_CFG10x0052;
sc->rl_cfg2 = RL_CFG20x0053;
sc->rl_cfg3 = RL_CFG30x0054;
sc->rl_cfg4 = RL_CFG40x0055;
sc->rl_cfg5 = RL_CFG50x0056;
}

/* Reset the adapter. */
re_reset(sc);

sc->rl_tx_time = 5;		/* 125us */
sc->rl_rx_time = 2;		/* 50us */
if (sc->rl_flags & RL_FLAG_PCIE0x00000004)
sc->rl_sim_time = 75;	/* 75us */
else
sc->rl_sim_time = 125;	/* 125us */
sc->rl_imtype = RL_IMTYPE_SIM1;	/* simulated interrupt moderation */

if (sc->sc_hwrev == RL_HWREV_8139CPLUS0x74800000)
sc->rl_bus_speed = 33; /* XXX */
else if (sc->rl_flags & RL_FLAG_PCIE0x00000004)
sc->rl_bus_speed = 125;
else {
u_int8_t cfg2;

cfg2 = CSR_READ_1(sc, sc->rl_cfg2)((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->rl_cfg2
)));
switch (cfg2 & RL_CFG2_PCI_MASK0x07) {
case RL_CFG2_PCI_33MHZ0x00:
		sc->rl_bus_speed = 33;
	break;
case RL_CFG2_PCI_66MHZ0x01:
	sc->rl_bus_speed = 66;
	break;
default:
	printf("%s: unknown bus speed, assume 33MHz\n",
	    sc->sc_dev.dv_xname);
	sc->rl_bus_speed = 33;
	break;
}

if (cfg2 & RL_CFG2_PCI_64BIT0x08)
	sc->rl_flags |= RL_FLAG_PCI640x00000002;
}

re_config_imtype(sc, sc->rl_imtype);

if (sc->rl_flags & RL_FLAG_PAR0x00000010) {
/*
 * XXX Should have a better way to extract station
 * address from EEPROM.
 */
for (i = 0; i < ETHER_ADDR_LEN6; i++)
	eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i)((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0000 + i
)));
} else {
sc->rl_eewidth = RL_9356_ADDR_LEN8;
re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
if (re_did != 0x8129)
	sc->rl_eewidth = RL_9346_ADDR_LEN6;

/*
 * Get station address from the EEPROM.
 */
re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR0x07, 3);
for (i = 0; i < ETHER_ADDR_LEN6 / 2; i++)
	as[i] = letoh16(as[i])((__uint16_t)(as[i]));
bcopy(as, eaddr, ETHER_ADDR_LEN6);
}

/*
* Set RX length mask, TX poll request register
* and descriptor count.
*/
if (sc->sc_hwrev == RL_HWREV_8139CPLUS0x74800000) {
sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN0x00001FFF;
sc->rl_txstart = RL_TXSTART0x00D9;
sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT64;
sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT64;
sc->rl_ldata.rl_tx_ndescs = RL_8139_NTXSEGS8;
} else {
sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN0x00003FFF;
sc->rl_txstart = RL_GTXSTART0x0038;
sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT1024;
sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT1024;
sc->rl_ldata.rl_tx_ndescs = RL_8169_NTXSEGS32;
}

bcopy(eaddr, (char *)&sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN6);

for (rr = re_revisions; rr->re_name != NULL((void *)0); rr++) {
if (rr->re_chipid == sc->sc_hwrev)
	re_name = rr->re_name;
}

if (re_name == NULL((void *)0))
printf(": unknown ASIC (0x%04x)", sc->sc_hwrev >> 16);
else
printf(": %s (0x%04x)", re_name, sc->sc_hwrev >> 16);

printf(", %s, address %s\n", intrstr,
   ether_sprintf(sc->sc_arpcom.ac_enaddr));

/* Allocate DMA'able memory for the TX ring */
if ((error = bus_dmamem_alloc(sc->sc_dmat, RL_TX_LIST_SZ(sc),(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (256
), (0), (&sc->rl_ldata.rl_tx_listseg), (1), (&sc->
rl_ldata.rl_tx_listnseg), (0x0001 | 0x1000))
    RL_RING_ALIGN, 0, &sc->rl_ldata.rl_tx_listseg, 1,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (256
), (0), (&sc->rl_ldata.rl_tx_listseg), (1), (&sc->
rl_ldata.rl_tx_listnseg), (0x0001 | 0x1000))
    &sc->rl_ldata.rl_tx_listnseg, BUS_DMA_NOWAIT |(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (256
), (0), (&sc->rl_ldata.rl_tx_listseg), (1), (&sc->
rl_ldata.rl_tx_listnseg), (0x0001 | 0x1000))
    BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (256
), (0), (&sc->rl_ldata.rl_tx_listseg), (1), (&sc->
rl_ldata.rl_tx_listnseg), (0x0001 | 0x1000))) != 0) {
printf("%s: can't allocate tx listseg, error = %d\n",
    sc->sc_dev.dv_xname, error);
goto fail_0;
}

/* Load the map for the TX ring. */
if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_tx_listseg,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->rl_ldata.rl_tx_listseg), (sc->rl_ldata.rl_tx_listnseg
), (((sc)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc
))), ((caddr_t *)&sc->rl_ldata.rl_tx_list), (0x0004 | 0x0001
))
    sc->rl_ldata.rl_tx_listnseg, RL_TX_LIST_SZ(sc),(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->rl_ldata.rl_tx_listseg), (sc->rl_ldata.rl_tx_listnseg
), (((sc)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc
))), ((caddr_t *)&sc->rl_ldata.rl_tx_list), (0x0004 | 0x0001
))
    (caddr_t *)&sc->rl_ldata.rl_tx_list,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->rl_ldata.rl_tx_listseg), (sc->rl_ldata.rl_tx_listnseg
), (((sc)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc
))), ((caddr_t *)&sc->rl_ldata.rl_tx_list), (0x0004 | 0x0001
))
    BUS_DMA_COHERENT | BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->rl_ldata.rl_tx_listseg), (sc->rl_ldata.rl_tx_listnseg
), (((sc)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc
))), ((caddr_t *)&sc->rl_ldata.rl_tx_list), (0x0004 | 0x0001
))) != 0) {
printf("%s: can't map tx list, error = %d\n",
    sc->sc_dev.dv_xname, error);
goto fail_1;
}

if ((error = bus_dmamap_create(sc->sc_dmat, RL_TX_LIST_SZ(sc), 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (1)
, (((sc)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)
)), (0), (0), (&sc->rl_ldata.rl_tx_list_map))
    RL_TX_LIST_SZ(sc), 0, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (1)
, (((sc)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)
)), (0), (0), (&sc->rl_ldata.rl_tx_list_map))
    &sc->rl_ldata.rl_tx_list_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (1)
, (((sc)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)
)), (0), (0), (&sc->rl_ldata.rl_tx_list_map))) != 0) {
printf("%s: can't create tx list map, error = %d\n",
    sc->sc_dev.dv_xname, error);
goto fail_2;
}

if ((error = bus_dmamap_load(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
rl_ldata.rl_tx_list_map), (sc->rl_ldata.rl_tx_list), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (((
void *)0)), (0x0001))
    sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
rl_ldata.rl_tx_list_map), (sc->rl_ldata.rl_tx_list), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (((
void *)0)), (0x0001))
    RL_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
rl_ldata.rl_tx_list_map), (sc->rl_ldata.rl_tx_list), (((sc
)->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))), (((
void *)0)), (0x0001))) != 0) {
printf("%s: can't load tx list, error = %d\n",
    sc->sc_dev.dv_xname, error);
goto fail_3;
}

/* Create DMA maps for TX buffers */
for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
error = bus_dmamap_create(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((9 *
 1024)), (sc->rl_ldata.rl_tx_ndescs), ((9 * 1024)), (0), (
0), (&sc->rl_ldata.rl_txq[i].txq_dmamap))
    RL_JUMBO_FRAMELEN, sc->rl_ldata.rl_tx_ndescs,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((9 *
 1024)), (sc->rl_ldata.rl_tx_ndescs), ((9 * 1024)), (0), (
0), (&sc->rl_ldata.rl_txq[i].txq_dmamap))
    RL_JUMBO_FRAMELEN, 0, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((9 *
 1024)), (sc->rl_ldata.rl_tx_ndescs), ((9 * 1024)), (0), (
0), (&sc->rl_ldata.rl_txq[i].txq_dmamap))
    &sc->rl_ldata.rl_txq[i].txq_dmamap)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((9 *
 1024)), (sc->rl_ldata.rl_tx_ndescs), ((9 * 1024)), (0), (
0), (&sc->rl_ldata.rl_txq[i].txq_dmamap));
if (error) {
	printf("%s: can't create DMA map for TX\n",
	    sc->sc_dev.dv_xname);
	goto fail_4;
}
}

      /* Allocate DMA'able memory for the RX ring */
if ((error = bus_dmamem_alloc(sc->sc_dmat, RL_RX_DMAMEM_SZ(sc),(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((((sc
)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (((
* 2) + 2) + 28))), (256), (0), (&sc->rl_ldata.rl_rx_listseg
), (1), (&sc->rl_ldata.rl_rx_listnseg), (0x0001 | 0x1000
))
    RL_RING_ALIGN, 0, &sc->rl_ldata.rl_rx_listseg, 1,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((((sc
)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (((
* 2) + 2) + 28))), (256), (0), (&sc->rl_ldata.rl_rx_listseg
), (1), (&sc->rl_ldata.rl_rx_listnseg), (0x0001 | 0x1000
))
    &sc->rl_ldata.rl_rx_listnseg, BUS_DMA_NOWAIT |(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((((sc
)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (((
* 2) + 2) + 28))), (256), (0), (&sc->rl_ldata.rl_rx_listseg
), (1), (&sc->rl_ldata.rl_rx_listnseg), (0x0001 | 0x1000
))
    BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((((sc
)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (((
* 2) + 2) + 28))), (256), (0), (&sc->rl_ldata.rl_rx_listseg
), (1), (&sc->rl_ldata.rl_rx_listnseg), (0x0001 | 0x1000
))) != 0) {
printf("%s: can't allocate rx listnseg, error = %d\n",
    sc->sc_dev.dv_xname, error);
goto fail_4;
}

      /* Load the map for the RX ring. */
if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_rx_listseg,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->rl_ldata.rl_rx_listseg), (sc->rl_ldata.rl_rx_listnseg
), ((((sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc
)) + (((6 * 2) + 2) + 28))), ((caddr_t *)&sc->rl_ldata
.rl_rx_list), (0x0004 | 0x0001))
    sc->rl_ldata.rl_rx_listnseg, RL_RX_DMAMEM_SZ(sc),(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->rl_ldata.rl_rx_listseg), (sc->rl_ldata.rl_rx_listnseg
), ((((sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc
)) + (((6 * 2) + 2) + 28))), ((caddr_t *)&sc->rl_ldata
.rl_rx_list), (0x0004 | 0x0001))
    (caddr_t *)&sc->rl_ldata.rl_rx_list,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->rl_ldata.rl_rx_listseg), (sc->rl_ldata.rl_rx_listnseg
), ((((sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc
)) + (((6 * 2) + 2) + 28))), ((caddr_t *)&sc->rl_ldata
.rl_rx_list), (0x0004 | 0x0001))
    BUS_DMA_COHERENT | BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&sc
->rl_ldata.rl_rx_listseg), (sc->rl_ldata.rl_rx_listnseg
), ((((sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc
)) + (((6 * 2) + 2) + 28))), ((caddr_t *)&sc->rl_ldata
.rl_rx_list), (0x0004 | 0x0001))) != 0) {
printf("%s: can't map rx list, error = %d\n",
    sc->sc_dev.dv_xname, error);
goto fail_5;

}

if ((error = bus_dmamap_create(sc->sc_dmat, RL_RX_DMAMEM_SZ(sc), 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((((
sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (
((6 * 2) + 2) + 28))), (1), ((((sc)->rl_ldata.rl_rx_desc_cnt
 * sizeof(struct rl_desc)) + (((6 * 2) + 2) + 28))), (0), (0)
, (&sc->rl_ldata.rl_rx_list_map))
    RL_RX_DMAMEM_SZ(sc), 0, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((((
sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (
((6 * 2) + 2) + 28))), (1), ((((sc)->rl_ldata.rl_rx_desc_cnt
 * sizeof(struct rl_desc)) + (((6 * 2) + 2) + 28))), (0), (0)
, (&sc->rl_ldata.rl_rx_list_map))
    &sc->rl_ldata.rl_rx_list_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((((
sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (
((6 * 2) + 2) + 28))), (1), ((((sc)->rl_ldata.rl_rx_desc_cnt
 * sizeof(struct rl_desc)) + (((6 * 2) + 2) + 28))), (0), (0)
, (&sc->rl_ldata.rl_rx_list_map))) != 0) {
printf("%s: can't create rx list map, error = %d\n",
    sc->sc_dev.dv_xname, error);
goto fail_6;
}

if ((error = bus_dmamap_load(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
rl_ldata.rl_rx_list_map), (sc->rl_ldata.rl_rx_list), ((((sc
)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (((
* 2) + 2) + 28))), (((void *)0)), (0x0001))
    sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
rl_ldata.rl_rx_list_map), (sc->rl_ldata.rl_rx_list), ((((sc
)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (((
* 2) + 2) + 28))), (((void *)0)), (0x0001))
    RL_RX_DMAMEM_SZ(sc), NULL, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (sc->
rl_ldata.rl_rx_list_map), (sc->rl_ldata.rl_rx_list), ((((sc
)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)) + (((
* 2) + 2) + 28))), (((void *)0)), (0x0001))) != 0) {
printf("%s: can't load rx list, error = %d\n",
    sc->sc_dev.dv_xname, error);
goto fail_7;
}

/* Create DMA maps for RX buffers */
for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
error = bus_dmamap_create(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((sc
->rl_max_mtu + ((6 * 2) + 2) + 4 + 4)), (1), ((sc->rl_max_mtu
 + ((6 * 2) + 2) + 4 + 4)), (0), (0), (&sc->rl_ldata.rl_rxsoft
[i].rxs_dmamap))
    RL_FRAMELEN(sc->rl_max_mtu), 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((sc
->rl_max_mtu + ((6 * 2) + 2) + 4 + 4)), (1), ((sc->rl_max_mtu
 + ((6 * 2) + 2) + 4 + 4)), (0), (0), (&sc->rl_ldata.rl_rxsoft
[i].rxs_dmamap))
    RL_FRAMELEN(sc->rl_max_mtu), 0, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((sc
->rl_max_mtu + ((6 * 2) + 2) + 4 + 4)), (1), ((sc->rl_max_mtu
 + ((6 * 2) + 2) + 4 + 4)), (0), (0), (&sc->rl_ldata.rl_rxsoft
[i].rxs_dmamap))
    &sc->rl_ldata.rl_rxsoft[i].rxs_dmamap)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((sc
->rl_max_mtu + ((6 * 2) + 2) + 4 + 4)), (1), ((sc->rl_max_mtu
 + ((6 * 2) + 2) + 4 + 4)), (0), (0), (&sc->rl_ldata.rl_rxsoft
[i].rxs_dmamap));
if (error) {
	printf("%s: can't create DMA map for RX\n",
	    sc->sc_dev.dv_xname);
	goto fail_8;
}
}

ifp = &sc->sc_arpcom.ac_if;
ifp->if_softc = sc;
strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ16);
ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
ifp->if_xflags = IFXF_MPSAFE0x1;
ifp->if_ioctl = re_ioctl;
ifp->if_qstart = re_start;
ifp->if_watchdog = re_watchdog;
ifp->if_hardmtu = sc->rl_max_mtu;
ifq_set_maxlen(&ifp->if_snd, sc->rl_ldata.rl_tx_desc_cnt)((&ifp->if_snd)->ifq_maxlen = (sc->rl_ldata.rl_tx_desc_cnt
));

ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010 | IFCAP_CSUM_TCPv40x00000002 |
   IFCAP_CSUM_UDPv40x00000004;

/*
* RTL8168/8111C generates wrong IP checksummed frame if the
* packet has IP options so disable TX IP checksum offloading.
*/
switch (sc->sc_hwrev) {
case RL_HWREV_8168C0x3c000000:
case RL_HWREV_8168C_SPIN20x3c400000:
case RL_HWREV_8168CP0x3c800000:
break;
default:
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_CSUM_IPv40x00000001;
}

1029#if NVLAN1 > 0
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020;
1031#endif

1033#ifndef SMALL_KERNEL
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_WOL0x00008000;
ifp->if_wol = re_wol;
re_wol(ifp, 0);
1037#endif
timeout_set(&sc->timer_handle, re_tick, sc);
task_set(&sc->rl_start, re_txstart, sc);

/* Take PHY out of power down mode. */
if (sc->rl_flags & RL_FLAG_PHYWAKE_PM0x00004000) {
CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x006F), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x006F))) |
 0x80)));
if (sc->sc_hwrev == RL_HWREV_8401E0x24000000)
	CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08)((sc->rl_btag)->write_1((sc->rl_bhandle), (0xD1), ((
(sc->rl_btag)->read_1((sc->rl_bhandle), (0xD1))) &
 ~0x08)));
}
if (sc->rl_flags & RL_FLAG_PHYWAKE0x00000008) {
re_gmii_writereg((struct device *)sc, 1, 0x1f, 0);
re_gmii_writereg((struct device *)sc, 1, 0x0e, 0);
}

/* Do MII setup */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = re_miibus_readreg;
sc->sc_mii.mii_writereg = re_miibus_writereg;
sc->sc_mii.mii_statchg = re_miibus_statchg;
ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK0xff00000000000000ULL, re_ifmedia_upd,
   re_ifmedia_sts);
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY-1,
   MII_OFFSET_ANY-1, MIIF_DOPAUSE0x0100);
if (LIST_FIRST(&sc->sc_mii.mii_phys)((&sc->sc_mii.mii_phys)->lh_first) == NULL((void *)0)) {
printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
ifmedia_add(&sc->sc_mii.mii_media,
    IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL, 0, NULL((void *)0));
ifmedia_set(&sc->sc_mii.mii_media,
    IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL);
} else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER0x0000000000000100ULL|IFM_AUTO0ULL);

/*
* Call MI attach routine.
*/
if_attach(ifp);
ether_ifattach(ifp);

return (0);

1078fail_8:
/* Destroy DMA maps for RX buffers. */
for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
if (sc->rl_ldata.rl_rxsoft[i].rxs_dmamap != NULL((void *)0))
	bus_dmamap_destroy(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->rl_ldata.rl_rxsoft[i].rxs_dmamap))
	    sc->rl_ldata.rl_rxsoft[i].rxs_dmamap)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->rl_ldata.rl_rxsoft[i].rxs_dmamap));
}

/* Free DMA'able memory for the RX ring. */
bus_dmamap_unload(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (sc->
rl_ldata.rl_rx_list_map));
1088fail_7:
bus_dmamap_destroy(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->rl_ldata.rl_rx_list_map));
1090fail_6:
bus_dmamem_unmap(sc->sc_dmat,(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t
)sc->rl_ldata.rl_rx_list), ((((sc)->rl_ldata.rl_rx_desc_cnt
 * sizeof(struct rl_desc)) + (((6 * 2) + 2) + 28))))
   (caddr_t)sc->rl_ldata.rl_rx_list, RL_RX_DMAMEM_SZ(sc))(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t
)sc->rl_ldata.rl_rx_list), ((((sc)->rl_ldata.rl_rx_desc_cnt
 * sizeof(struct rl_desc)) + (((6 * 2) + 2) + 28))));
1093fail_5:
bus_dmamem_free(sc->sc_dmat,(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
sc->rl_ldata.rl_rx_listseg), (sc->rl_ldata.rl_rx_listnseg
))
   &sc->rl_ldata.rl_rx_listseg, sc->rl_ldata.rl_rx_listnseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
sc->rl_ldata.rl_rx_listseg), (sc->rl_ldata.rl_rx_listnseg
));

1097fail_4:
/* Destroy DMA maps for TX buffers. */
for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
if (sc->rl_ldata.rl_txq[i].txq_dmamap != NULL((void *)0))
	bus_dmamap_destroy(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->rl_ldata.rl_txq[i].txq_dmamap))
	    sc->rl_ldata.rl_txq[i].txq_dmamap)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->rl_ldata.rl_txq[i].txq_dmamap));
}

/* Free DMA'able memory for the TX ring. */
bus_dmamap_unload(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (sc->
rl_ldata.rl_tx_list_map));
1107fail_3:
bus_dmamap_destroy(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (sc
->rl_ldata.rl_tx_list_map));
1109fail_2:
bus_dmamem_unmap(sc->sc_dmat,(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t
)sc->rl_ldata.rl_tx_list), (((sc)->rl_ldata.rl_tx_desc_cnt
 * sizeof(struct rl_desc))))
   (caddr_t)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ(sc))(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), ((caddr_t
)sc->rl_ldata.rl_tx_list), (((sc)->rl_ldata.rl_tx_desc_cnt
 * sizeof(struct rl_desc))));
1112fail_1:
bus_dmamem_free(sc->sc_dmat,(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
sc->rl_ldata.rl_tx_listseg), (sc->rl_ldata.rl_tx_listnseg
))
   &sc->rl_ldata.rl_tx_listseg, sc->rl_ldata.rl_tx_listnseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
sc->rl_ldata.rl_tx_listseg), (sc->rl_ldata.rl_tx_listnseg
));
1115fail_0:
return (1);
1117}


1120int
1121re_newbuf(struct rl_softc *sc)
1122{
struct mbuf	*m;
bus_dmamap_t	map;
struct rl_desc	*d;
struct rl_rxsoft *rxs;
u_int32_t	cmdstat;
int		error, idx;

m = MCLGETL(NULL, M_DONTWAIT, RL_FRAMELEN(sc->rl_max_mtu))m_clget((((void *)0)), (0x0002), ((sc->rl_max_mtu + ((6 * 2
) + 2) + 4 + 4)));
if (!m)
return (ENOBUFS55);

/*
* Initialize mbuf length fields and fixup
* alignment so that the frame payload is
* longword aligned on strict alignment archs.
*/
m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = RL_FRAMELEN(sc->rl_max_mtu)(sc->rl_max_mtu + ((6 * 2) + 2) + 4 + 4);
m->m_datam_hdr.mh_data += RE_ETHER_ALIGN0;

idx = sc->rl_ldata.rl_rx_prodidx;
rxs = &sc->rl_ldata.rl_rxsoft[idx];
map = rxs->rxs_dmamap;
error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0200|0x0001))
   BUS_DMA_READ|BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0200|0x0001));
if (error) {
m_freem(m);
return (ENOBUFS55);
}

bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x01))
   BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x01));

d = &sc->rl_ldata.rl_rx_list[idx];
RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_rx_list_map), (sizeof(struct rl_desc) * (
idx)), (sizeof(struct rl_desc)), ((0x02|0x08)));
cmdstat = letoh32(d->rl_cmdstat)((__uint32_t)(d->rl_cmdstat));
RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_rx_list_map), (sizeof(struct rl_desc) * (
idx)), (sizeof(struct rl_desc)), ((0x01)));
if (cmdstat & RL_RDESC_STAT_OWN0x80000000) {
printf("%s: tried to map busy RX descriptor\n",
    sc->sc_dev.dv_xname);
m_freem(m);
return (ENOBUFS55);
}

rxs->rxs_mbuf = m;

d->rl_vlanctl = 0;
cmdstat = map->dm_segs[0].ds_len;
if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
cmdstat |= RL_RDESC_CMD_EOR0x40000000;
re_set_bufaddr(d, map->dm_segs[0].ds_addr);
d->rl_cmdstat = htole32(cmdstat)((__uint32_t)(cmdstat));
RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_rx_list_map), (sizeof(struct rl_desc) * (
idx)), (sizeof(struct rl_desc)), ((0x01|0x04)));
cmdstat |= RL_RDESC_CMD_OWN0x80000000;
d->rl_cmdstat = htole32(cmdstat)((__uint32_t)(cmdstat));
RL_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_rx_list_map), (sizeof(struct rl_desc) * (
idx)), (sizeof(struct rl_desc)), ((0x01|0x04)));

sc->rl_ldata.rl_rx_prodidx = RL_NEXT_RX_DESC(sc, idx)(((idx) + 1) % (sc)->rl_ldata.rl_rx_desc_cnt);

return (0);
1182}


1185int
1186re_tx_list_init(struct rl_softc *sc)
1187{
int i;

memset(sc->rl_ldata.rl_tx_list, 0, RL_TX_LIST_SZ(sc))__builtin_memset((sc->rl_ldata.rl_tx_list), (0), (((sc)->
rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc))));
for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
sc->rl_ldata.rl_txq[i].txq_mbuf = NULL((void *)0);
}

bus_dmamap_sync(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rl_ldata.rl_tx_list_map), (0), (sc->rl_ldata.rl_tx_list_map
->dm_mapsize), (0x01|0x04))
   sc->rl_ldata.rl_tx_list_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rl_ldata.rl_tx_list_map), (0), (sc->rl_ldata.rl_tx_list_map
->dm_mapsize), (0x01|0x04))
   sc->rl_ldata.rl_tx_list_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rl_ldata.rl_tx_list_map), (0), (sc->rl_ldata.rl_tx_list_map
->dm_mapsize), (0x01|0x04))
   BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (sc->
rl_ldata.rl_tx_list_map), (0), (sc->rl_ldata.rl_tx_list_map
->dm_mapsize), (0x01|0x04));
sc->rl_ldata.rl_txq_prodidx = 0;
sc->rl_ldata.rl_txq_considx = 0;
sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
sc->rl_ldata.rl_tx_nextfree = 0;

return (0);
1205}

1207int
1208re_rx_list_init(struct rl_softc *sc)
1209{
bzero(sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ(sc))__builtin_bzero((sc->rl_ldata.rl_rx_list), (((sc)->rl_ldata
.rl_rx_desc_cnt * sizeof(struct rl_desc))));

sc->rl_ldata.rl_rx_prodidx = 0;
sc->rl_ldata.rl_rx_considx = 0;
sc->rl_head = sc->rl_tail = NULL((void *)0);

if_rxr_init(&sc->rl_ldata.rl_rx_ring, 2,
   sc->rl_ldata.rl_rx_desc_cnt - 1);
re_rx_list_fill(sc);

return (0);
1221}

1223void
1224re_rx_list_fill(struct rl_softc *sc)
1225{
u_int slots;

for (slots = if_rxr_get(&sc->rl_ldata.rl_rx_ring,
   sc->rl_ldata.rl_rx_desc_cnt);
   slots > 0; slots--) {
if (re_newbuf(sc) == ENOBUFS55)
	break;
}
if_rxr_put(&sc->rl_ldata.rl_rx_ring, slots)do { (&sc->rl_ldata.rl_rx_ring)->rxr_alive -= (slots
); } while (0);
1235}

1237/*
* RX handler for C+ and 8169. For the gigE chips, we support
* the reception of jumbo frames that have been fragmented
* across multiple 2K mbuf cluster buffers.
*/
1242int
1243re_rxeof(struct rl_softc *sc)
1244{
struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
struct mbuf	*m;
struct ifnet	*ifp;
int		i, total_len, rx = 0;
struct rl_desc	*cur_rx;
struct rl_rxsoft *rxs;
u_int32_t	rxstat, rxvlan;

ifp = &sc->sc_arpcom.ac_if;

for (i = sc->rl_ldata.rl_rx_considx;
   if_rxr_inuse(&sc->rl_ldata.rl_rx_ring)((&sc->rl_ldata.rl_rx_ring)->rxr_alive) > 0;
    i = RL_NEXT_RX_DESC(sc, i)(((i) + 1) % (sc)->rl_ldata.rl_rx_desc_cnt)) {
cur_rx = &sc->rl_ldata.rl_rx_list[i];
RL_RXDESCSYNC(sc, i,(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_rx_list_map), (sizeof(struct rl_desc) * (
i)), (sizeof(struct rl_desc)), ((0x02|0x08)))
    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_rx_list_map), (sizeof(struct rl_desc) * (
i)), (sizeof(struct rl_desc)), ((0x02|0x08)));
rxstat = letoh32(cur_rx->rl_cmdstat)((__uint32_t)(cur_rx->rl_cmdstat));
rxvlan = letoh32(cur_rx->rl_vlanctl)((__uint32_t)(cur_rx->rl_vlanctl));
RL_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_rx_list_map), (sizeof(struct rl_desc) * (
i)), (sizeof(struct rl_desc)), ((0x01)));
if ((rxstat & RL_RDESC_STAT_OWN0x80000000) != 0)
	break;
total_len = rxstat & sc->rl_rxlenmask;
rxs = &sc->rl_ldata.rl_rxsoft[i];
m = rxs->rxs_mbuf;
rxs->rxs_mbuf = NULL((void *)0);
if_rxr_put(&sc->rl_ldata.rl_rx_ring, 1)do { (&sc->rl_ldata.rl_rx_ring)->rxr_alive -= (1); }
 while (0);
rx = 1;

/* Invalidate the RX mbuf and unload its map */

bus_dmamap_sync(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (rxs->
rxs_dmamap), (0), (rxs->rxs_dmamap->dm_mapsize), (0x02)
)
    rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (rxs->
rxs_dmamap), (0), (rxs->rxs_dmamap->dm_mapsize), (0x02)
)
    BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (rxs->
rxs_dmamap), (0), (rxs->rxs_dmamap->dm_mapsize), (0x02)
);
bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (rxs
->rxs_dmamap));

if ((sc->rl_flags & RL_FLAG_JUMBOV20x00100000) != 0 &&
    (rxstat & (RL_RDESC_STAT_SOF0x20000000 | RL_RDESC_STAT_EOF0x10000000)) !=
    (RL_RDESC_STAT_SOF0x20000000 | RL_RDESC_STAT_EOF0x10000000)) {
	ifp->if_ierrorsif_data.ifi_ierrors++;
	m_freem(m);
	continue;
} else if (!(rxstat & RL_RDESC_STAT_EOF0x10000000)) {
	m->m_lenm_hdr.mh_len = RL_FRAMELEN(sc->rl_max_mtu)(sc->rl_max_mtu + ((6 * 2) + 2) + 4 + 4);
	if (sc->rl_head == NULL((void *)0))
		sc->rl_head = sc->rl_tail = m;
	else {
		m->m_flagsm_hdr.mh_flags &= ~M_PKTHDR0x0002;
		sc->rl_tail->m_nextm_hdr.mh_next = m;
		sc->rl_tail = m;
	}
	continue;
}

/*
 * NOTE: for the 8139C+, the frame length field
 * is always 12 bits in size, but for the gigE chips,
 * it is 13 bits (since the max RX frame length is 16K).
 * Unfortunately, all 32 bits in the status word
 * were already used, so to make room for the extra
 * length bit, Realtek took out the 'frame alignment
 * error' bit and shifted the other status bits
 * over one slot. The OWN, EOR, FS and LS bits are
 * still in the same places. We have already extracted
 * the frame length and checked the OWN bit, so rather
 * than using an alternate bit mapping, we shift the
 * status bits one space to the right so we can evaluate
 * them using the 8169 status as though it was in the
 * same format as that of the 8139C+.
 */
if (sc->sc_hwrev != RL_HWREV_8139CPLUS0x74800000)
	rxstat >>= 1;

/*
 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
 * set, but if CRC is clear, it will still be a valid frame.
 */
if ((rxstat & RL_RDESC_STAT_RXERRSUM0x00100000) != 0 &&
	    !(rxstat & RL_RDESC_STAT_RXERRSUM0x00100000 && !(total_len > 8191 &&
    (rxstat & RL_RDESC_STAT_ERRS(0x00200000|0x00080000| 0x00040000)) == RL_RDESC_STAT_GIANT0x00200000))) {
	ifp->if_ierrorsif_data.ifi_ierrors++;
	/*
	 * If this is part of a multi-fragment packet,
	 * discard all the pieces.
	 */
	if (sc->rl_head != NULL((void *)0)) {
		m_freem(sc->rl_head);
		sc->rl_head = sc->rl_tail = NULL((void *)0);
	}
	m_freem(m);
	continue;
}

if (sc->rl_head != NULL((void *)0)) {
	m->m_lenm_hdr.mh_len = total_len % RL_FRAMELEN(sc->rl_max_mtu)(sc->rl_max_mtu + ((6 * 2) + 2) + 4 + 4);
	if (m->m_lenm_hdr.mh_len == 0)
		m->m_lenm_hdr.mh_len = RL_FRAMELEN(sc->rl_max_mtu)(sc->rl_max_mtu + ((6 * 2) + 2) + 4 + 4);
	/* 
	 * Special case: if there's 4 bytes or less
	 * in this buffer, the mbuf can be discarded:
	 * the last 4 bytes is the CRC, which we don't
	 * care about anyway.
	 */
	if (m->m_lenm_hdr.mh_len <= ETHER_CRC_LEN4) {
		sc->rl_tail->m_lenm_hdr.mh_len -=
		    (ETHER_CRC_LEN4 - m->m_lenm_hdr.mh_len);
		m_freem(m);
	} else {
		m->m_lenm_hdr.mh_len -= ETHER_CRC_LEN4;
		m->m_flagsm_hdr.mh_flags &= ~M_PKTHDR0x0002;
		sc->rl_tail->m_nextm_hdr.mh_next = m;
	}
	m = sc->rl_head;
	sc->rl_head = sc->rl_tail = NULL((void *)0);
	m->m_pkthdrM_dat.MH.MH_pkthdr.len = total_len - ETHER_CRC_LEN4;
} else
	m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len =
	    (total_len - ETHER_CRC_LEN4);

/* Do RX checksumming */

if (sc->rl_flags & RL_FLAG_DESCV20x00000020) {
	/* Check IP header checksum */
	if ((rxvlan & RL_RDESC_IPV40x40000000) &&
	    !(rxstat & RL_RDESC_STAT_IPSUMBAD0x00008000))
		m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008;

	/* Check TCP/UDP checksum */
	if ((rxvlan & (RL_RDESC_IPV40x40000000|RL_RDESC_IPV60x80000000)) &&
	    (((rxstat & RL_RDESC_STAT_TCP0x00010000) &&
	    !(rxstat & RL_RDESC_STAT_TCPSUMBAD0x00002000)) ||
	    ((rxstat & RL_RDESC_STAT_UDP0x00020000) &&
	    !(rxstat & RL_RDESC_STAT_UDPSUMBAD0x00004000))))
		m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK0x0020 |
		    M_UDP_CSUM_IN_OK0x0080;
} else {
	/* Check IP header checksum */
	if ((rxstat & RL_RDESC_STAT_PROTOID0x00030000) &&
	    !(rxstat & RL_RDESC_STAT_IPSUMBAD0x00008000))
		m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008;

	/* Check TCP/UDP checksum */
	if ((RL_TCPPKT(rxstat)(((rxstat) & 0x00030000) == 0x00010000) &&
	    !(rxstat & RL_RDESC_STAT_TCPSUMBAD0x00002000)) ||
	    (RL_UDPPKT(rxstat)(((rxstat) & 0x00030000) == 0x00020000) &&
	    !(rxstat & RL_RDESC_STAT_UDPSUMBAD0x00004000)))
		m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK0x0020 |
		    M_UDP_CSUM_IN_OK0x0080;
}
1393#if NVLAN1 > 0
if (rxvlan & RL_RDESC_VLANCTL_TAG0x00010000) {
	m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag =
	    ntohs((rxvlan & RL_RDESC_VLANCTL_DATA))(__uint16_t)(__builtin_constant_p((rxvlan & 0x0000FFFF)) ?
 (__uint16_t)(((__uint16_t)((rxvlan & 0x0000FFFF)) & 0xffU
) << 8 | ((__uint16_t)((rxvlan & 0x0000FFFF)) &
 0xff00U) >> 8) : __swap16md((rxvlan & 0x0000FFFF))
);
	m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020;
}
1399#endif

ml_enqueue(&ml, m);
}

if (ifiq_input(&ifp->if_rcv, &ml))
if_rxr_livelocked(&sc->rl_ldata.rl_rx_ring);

sc->rl_ldata.rl_rx_considx = i;
re_rx_list_fill(sc);


return (rx);
1412}

1414int
1415re_txeof(struct rl_softc *sc)
1416{
struct ifnet	*ifp = &sc->sc_arpcom.ac_if;
struct rl_txq	*txq;
uint32_t	txstat;
unsigned int	prod, cons;
unsigned int	idx;
int		free = 0;

prod = sc->rl_ldata.rl_txq_prodidx;
cons = sc->rl_ldata.rl_txq_considx;

while (prod != cons) {
txq = &sc->rl_ldata.rl_txq[cons];

idx = txq->txq_descidx;
RL_TXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_tx_list_map), (sizeof(struct rl_desc) * (
idx)), (sizeof(struct rl_desc)), ((0x02)));
txstat = letoh32(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat)((__uint32_t)(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat));
RL_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_tx_list_map), (sizeof(struct rl_desc) * (
idx)), (sizeof(struct rl_desc)), ((0x01)));
if (ISSET(txstat, RL_TDESC_CMD_OWN)((txstat) & (0x80000000))) {
	free = 2;
	break;
}

bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (txq->
txq_dmamap), (0), (txq->txq_dmamap->dm_mapsize), (0x08)
)
    0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (txq->
txq_dmamap), (0), (txq->txq_dmamap->dm_mapsize), (0x08)
);
bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (txq
->txq_dmamap));
m_freem(txq->txq_mbuf);
txq->txq_mbuf = NULL((void *)0);

if (txstat & (RL_TDESC_STAT_EXCESSCOL0x00100000 | RL_TDESC_STAT_COLCNT0x000F0000))
	ifp->if_collisionsif_data.ifi_collisions++;
if (txstat & RL_TDESC_STAT_TXERRSUM0x00800000)
	ifp->if_oerrorsif_data.ifi_oerrors++;

cons = RL_NEXT_TX_DESC(sc, idx)(((idx) + 1) % (sc)->rl_ldata.rl_tx_desc_cnt);
free = 1;
}

if (free == 0)
return (0);

sc->rl_ldata.rl_txq_considx = cons;

/*
* Some chips will ignore a second TX request issued while an
* existing transmission is in progress. If the transmitter goes
* idle but there are still packets waiting to be sent, we need
* to restart the channel here to flush them out. This only
* seems to be required with the PCIe devices.
*/
if (ifq_is_oactive(&ifp->if_snd))
ifq_restart(&ifp->if_snd);
else if (free == 2)
ifq_serialize(&ifp->if_snd, &sc->rl_start);
else
ifp->if_timer = 0;

return (1);
1474}

1476void
1477re_tick(void *xsc)
1478{
struct rl_softc	*sc = xsc;
struct mii_data	*mii;
int s;

mii = &sc->sc_mii;

s = splnet()splraise(0x7);

mii_tick(mii);

if ((sc->rl_flags & RL_FLAG_LINK0x00002000) == 0)
re_miibus_statchg(&sc->sc_dev);

splx(s)spllower(s);

timeout_add_sec(&sc->timer_handle, 1);
1495}

1497int
1498re_intr(void *arg)
1499{
struct rl_softc	*sc = arg;
struct ifnet	*ifp;
u_int16_t	status;
int		claimed = 0, rx, tx;

ifp = &sc->sc_arpcom.ac_if;

if (!(ifp->if_flags & IFF_RUNNING0x40))
return (0);

/* Disable interrupts. */
CSR_WRITE_2(sc, RL_IMR, 0)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x003C), (
0)));

rx = tx = 0;
status = CSR_READ_2(sc, RL_ISR)((sc->rl_btag)->read_2((sc->rl_bhandle), (0x003E)));
/* If the card has gone away the read returns 0xffff. */
if (status == 0xffff)
return (0);
if (status)
CSR_WRITE_2(sc, RL_ISR, status)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x003E), (
status)));

if (status & RL_ISR_TIMEOUT_EXPIRED0x4000)
claimed = 1;

if (status & RL_INTRS_CPLUS(0x0001|0x0002|0x0008| 0x0010|0x0040| 0x8000|0x0004)) {
if (status &
    (sc->rl_rx_ack | RL_ISR_RX_ERR0x0002 | RL_ISR_FIFO_OFLOW0x0040)) {
	rx |= re_rxeof(sc);
	claimed = 1;
}

if (status & (sc->rl_tx_ack | RL_ISR_TX_ERR0x0008)) {
	tx |= re_txeof(sc);
	claimed = 1;
}

if (status & RL_ISR_SYSTEM_ERR0x8000) {
	KERNEL_LOCK()_kernel_lock();
	re_init(ifp);
	KERNEL_UNLOCK()_kernel_unlock();
	claimed = 1;
}
}

if (sc->rl_imtype == RL_IMTYPE_SIM1) {
if (sc->rl_timerintr) {
	if ((tx | rx) == 0) {
		/*
		 * Nothing needs to be processed, fallback
		 * to use TX/RX interrupts.
		 */
		re_setup_intr(sc, 1, RL_IMTYPE_NONE0);

		/*
		 * Recollect, mainly to avoid the possible
		 * race introduced by changing interrupt
		 * masks.
		 */
		re_rxeof(sc);
		re_txeof(sc);
	} else
		CSR_WRITE_4(sc, RL_TIMERCNT, 1)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0048), (
1))); /* reload */
} else if (tx | rx) {
	/*
	 * Assume that using simulated interrupt moderation
	 * (hardware timer based) could reduce the interrupt
	 * rate.
	 */
	re_setup_intr(sc, 1, RL_IMTYPE_SIM1);
}
}

CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x003C), (
sc->rl_intrs)));

return (claimed);
1575}

1577int
1578re_encap(struct rl_softc *sc, unsigned int idx, struct mbuf *m)
1579{
struct rl_txq	*txq;
bus_dmamap_t	map;
int		error, seg, nsegs, curidx, lastidx, pad;
int		off;
struct ip	*ip;
struct rl_desc	*d;
11
←
'd' declared without an initial value→
u_int32_t	cmdstat, vlanctl = 0, csum_flags = 0;

/*
* Set up checksum offload. Note: checksum offload bits must
* appear in all descriptors of a multi-descriptor transmit
* attempt. This is according to testing done with an 8169
* chip. This is a requirement.
*/

/*
* Set RL_TDESC_CMD_IPCSUM if any checksum offloading
* is requested.  Otherwise, RL_TDESC_CMD_TCPCSUM/
* RL_TDESC_CMD_UDPCSUM does not take affect.
*/

if ((sc->rl_flags & RL_FLAG_JUMBOV20x00100000) &&
12
←
Assuming the condition is false→
   m->m_pkthdrM_dat.MH.MH_pkthdr.len > RL_MTU(1518 - ((6 * 2) + 2) - 4) &&
   (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags &
   (M_IPV4_CSUM_OUT0x0001|M_TCP_CSUM_OUT0x0002|M_UDP_CSUM_OUT0x0004)) != 0) {
struct mbuf mh, *mp;

mp = m_getptr(m, ETHER_HDR_LEN((6 * 2) + 2), &off);
mh.m_flagsm_hdr.mh_flags = 0;
mh.m_datam_hdr.mh_data = mtod(mp, caddr_t)((caddr_t)((mp)->m_hdr.mh_data)) + off;
mh.m_nextm_hdr.mh_next = mp->m_nextm_hdr.mh_next;
mh.m_pkthdrM_dat.MH.MH_pkthdr.len = mp->m_pkthdrM_dat.MH.MH_pkthdr.len - ETHER_HDR_LEN((6 * 2) + 2);
mh.m_lenm_hdr.mh_len = mp->m_lenm_hdr.mh_len - off;
ip = (struct ip *)mh.m_datam_hdr.mh_data;

if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_IPV4_CSUM_OUT0x0001)
	ip->ip_sum = in_cksum(&mh, sizeof(struct ip)); 
if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & (M_TCP_CSUM_OUT0x0002|M_UDP_CSUM_OUT0x0004))
	in_delayed_cksum(&mh);

m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags &=
    ~(M_IPV4_CSUM_OUT0x0001|M_TCP_CSUM_OUT0x0002|M_UDP_CSUM_OUT0x0004);
}

if ((m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags &
13
←
Assuming the condition is false→
14
←
Taking false branch→
   (M_IPV4_CSUM_OUT0x0001|M_TCP_CSUM_OUT0x0002|M_UDP_CSUM_OUT0x0004)) != 0) {
if (sc->rl_flags & RL_FLAG_DESCV20x00000020) {
	vlanctl |= RL_TDESC_CMD_IPCSUMV20x20000000;
	if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_TCP_CSUM_OUT0x0002)
		vlanctl |= RL_TDESC_CMD_TCPCSUMV20x40000000;
	if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_UDP_CSUM_OUT0x0004)
		vlanctl |= RL_TDESC_CMD_UDPCSUMV20x80000000;
} else {
	csum_flags |= RL_TDESC_CMD_IPCSUM0x00040000;
	if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_TCP_CSUM_OUT0x0002)
		csum_flags |= RL_TDESC_CMD_TCPCSUM0x00010000;
	if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_UDP_CSUM_OUT0x0004)
		csum_flags |= RL_TDESC_CMD_UDPCSUM0x00020000;
}
}

txq = &sc->rl_ldata.rl_txq[idx];
map = txq->txq_dmamap;

error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0400|0x0001))
   BUS_DMA_WRITE|BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0400|0x0001));
switch (error) {
15
←
Control jumps to 'case 0:'  at line 1647→
case 0:
break;
16
←
 Execution continues on line 1661→

case EFBIG27:
if (m_defrag(m, M_DONTWAIT0x0002) == 0 &&
    bus_dmamap_load_mbuf(sc->sc_dmat, map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0400|0x0001))
    BUS_DMA_WRITE|BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0400|0x0001)) == 0)
	break;

/* FALLTHROUGH */
default:
return (0);
}

bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x04))
   BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x04));

nsegs = map->dm_nsegs;
pad = 0;

/*
* With some of the Realtek chips, using the checksum offload
* support in conjunction with the autopadding feature results
* in the transmission of corrupt frames. For example, if we
* need to send a really small IP fragment that's less than 60
* bytes in size, and IP header checksumming is enabled, the
* resulting ethernet frame that appears on the wire will
* have garbled payload. To work around this, if TX IP checksum
* offload is enabled, we always manually pad short frames out
* to the minimum ethernet frame size.
*/
if ((sc->rl_flags & RL_FLAG_AUTOPAD0x00001000) == 0 &&
17
←
Assuming the condition is false→
   m->m_pkthdrM_dat.MH.MH_pkthdr.len < RL_IP4CSUMTX_PADLEN(((6 * 2) + 2) + 28) &&
   (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_IPV4_CSUM_OUT0x0001) != 0) {
pad = 1;
nsegs++;
}

/*
* Set up hardware VLAN tagging. Note: vlan tag info must
* appear in all descriptors of a multi-descriptor
* transmission attempt.
*/
1690#if NVLAN1 > 0
if (m->m_flagsm_hdr.mh_flags & M_VLANTAG0x0020)
18
←
Assuming the condition is false→
19
←
Taking false branch→
vlanctl |= swap16(m->m_pkthdr.ether_vtag)(__uint16_t)(__builtin_constant_p(m->M_dat.MH.MH_pkthdr.ether_vtag
) ? (__uint16_t)(((__uint16_t)(m->M_dat.MH.MH_pkthdr.ether_vtag
) & 0xffU) << 8 | ((__uint16_t)(m->M_dat.MH.MH_pkthdr
.ether_vtag) & 0xff00U) >> 8) : __swap16md(m->M_dat
.MH.MH_pkthdr.ether_vtag)) |
    RL_TDESC_VLANCTL_TAG0x00020000;
1694#endif

/*
* Map the segment array into descriptors. Note that we set the
* start-of-frame and end-of-frame markers for either TX or RX, but
* they really only have meaning in the TX case. (In the RX case,
* it's the chip that tells us where packets begin and end.)
* We also keep track of the end of the ring and set the
* end-of-ring bits as needed, and we set the ownership bits
* in all except the very first descriptor. (The caller will
* set this descriptor later when it start transmission or
* reception.)
*/
curidx = idx;
cmdstat = RL_TDESC_CMD_SOF0x20000000;

for (seg = 0; seg < map->dm_nsegs; seg++) {
20
←
Assuming 'seg' is >= field 'dm_nsegs'→
21
←
Loop condition is false. Execution continues on line 1731→
d = &sc->rl_ldata.rl_tx_list[curidx];

RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_POSTWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_tx_list_map), (sizeof(struct rl_desc) * (
curidx)), (sizeof(struct rl_desc)), ((0x08)));

d->rl_vlanctl = htole32(vlanctl)((__uint32_t)(vlanctl));
re_set_bufaddr(d, map->dm_segs[seg].ds_addr);
cmdstat |= csum_flags | map->dm_segs[seg].ds_len;

if (curidx == sc->rl_ldata.rl_tx_desc_cnt - 1)
	cmdstat |= RL_TDESC_CMD_EOR0x40000000;

d->rl_cmdstat = htole32(cmdstat)((__uint32_t)(cmdstat));

RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_PREWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_tx_list_map), (sizeof(struct rl_desc) * (
curidx)), (sizeof(struct rl_desc)), ((0x04)));

lastidx = curidx;
cmdstat = RL_TDESC_CMD_OWN0x80000000;
curidx = RL_NEXT_TX_DESC(sc, curidx)(((curidx) + 1) % (sc)->rl_ldata.rl_tx_desc_cnt);
}

if (pad21.1
'pad' is 0
) {
22
←
Taking false branch→
d = &sc->rl_ldata.rl_tx_list[curidx];

RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_POSTWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_tx_list_map), (sizeof(struct rl_desc) * (
curidx)), (sizeof(struct rl_desc)), ((0x08)));

d->rl_vlanctl = htole32(vlanctl)((__uint32_t)(vlanctl));
re_set_bufaddr(d, RL_TXPADDADDR(sc)((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + ((
sc)->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc))));
cmdstat = csum_flags |
    RL_TDESC_CMD_OWN0x80000000 | RL_TDESC_CMD_EOF0x10000000 |
    (RL_IP4CSUMTX_PADLEN(((6 * 2) + 2) + 28) + 1 - m->m_pkthdrM_dat.MH.MH_pkthdr.len);

if (curidx == sc->rl_ldata.rl_tx_desc_cnt - 1)
	cmdstat |= RL_TDESC_CMD_EOR0x40000000;

d->rl_cmdstat = htole32(cmdstat)((__uint32_t)(cmdstat));

RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_PREWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_tx_list_map), (sizeof(struct rl_desc) * (
curidx)), (sizeof(struct rl_desc)), ((0x04)));

lastidx = curidx;
}

/* d is already pointing at the last descriptor */
d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF)((__uint32_t)(0x10000000));
23
←
Access to field 'rl_cmdstat' results in a dereference of an undefined pointer value (loaded from variable 'd')

/* Transfer ownership of packet to the chip. */
d = &sc->rl_ldata.rl_tx_list[idx];

RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_POSTWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_tx_list_map), (sizeof(struct rl_desc) * (
curidx)), (sizeof(struct rl_desc)), ((0x08)));
d->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN)((__uint32_t)(0x80000000));
RL_TXDESCSYNC(sc, curidx, BUS_DMASYNC_PREWRITE)(*((sc)->sc_dmat)->_dmamap_sync)(((sc)->sc_dmat), ((
sc)->rl_ldata.rl_tx_list_map), (sizeof(struct rl_desc) * (
curidx)), (sizeof(struct rl_desc)), ((0x04)));

/* update info of TX queue and descriptors */
txq->txq_mbuf = m;
txq->txq_descidx = lastidx;

return (nsegs);
1767}

1769void
1770re_txstart(void *xsc)
1771{
struct rl_softc *sc = xsc;

CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START)((sc->rl_btag)->write_1((sc->rl_bhandle), (sc->rl_txstart
), (0x40)));
1775}

1777/*
* Main transmit routine for C+ and gigE NICs.
*/

1781void
1782re_start(struct ifqueue *ifq)
1783{
struct ifnet	*ifp = ifq->ifq_if;
struct rl_softc	*sc = ifp->if_softc;
struct mbuf	*m;
unsigned int	idx;
unsigned int	free, used;
int		post = 0;

if (!ISSET(sc->rl_flags, RL_FLAG_LINK)((sc->rl_flags) & (0x00002000))) {
1
Assuming the condition is false→
2
←
Taking false branch→
ifq_purge(ifq);
return;
}

free = sc->rl_ldata.rl_txq_considx;
idx = sc->rl_ldata.rl_txq_prodidx;
if (free <= idx)
3
←
Assuming 'free' is > 'idx'→
4
←
Taking false branch→
free += sc->rl_ldata.rl_tx_desc_cnt;
free -= idx;

for (;;) {
5
←
Loop condition is true.  Entering loop body→
if (sc->rl_ldata.rl_tx_ndescs >= free + 2) {
6
←
Assuming the condition is false→
7
←
Taking false branch→
	ifq_set_oactive(ifq);
	break;
}

m = ifq_dequeue(ifq);
if (m == NULL((void *)0))
8
←
Assuming 'm' is not equal to NULL→
9
←
Taking false branch→
	break;

used = re_encap(sc, idx, m);
10
←
Calling 're_encap'→
if (used == 0) {
	m_freem(m);
	continue;
}

1818#if NBPFILTER1 > 0
if (ifp->if_bpf)
	bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
1821#endif

KASSERT(used <= free)((used <= free) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/ic/re.c"
, 1823, "used <= free"));
free -= used;

idx += used;
if (idx >= sc->rl_ldata.rl_tx_desc_cnt)
	idx -= sc->rl_ldata.rl_tx_desc_cnt;

post = 1;
}

if (post == 0)
return;

ifp->if_timer = 5;
sc->rl_ldata.rl_txq_prodidx = idx;
ifq_serialize(ifq, &sc->rl_start);
1839}

1841int
1842re_init(struct ifnet *ifp)
1843{
struct rl_softc *sc = ifp->if_softc;
u_int16_t	cfg;
uint32_t	rxcfg;
int		s;
union {
u_int32_t align_dummy;
u_char eaddr[ETHER_ADDR_LEN6];
} eaddr;

s = splnet()splraise(0x7);

/*
* Cancel pending I/O and free all RX/TX buffers.
*/
re_stop(ifp);

/* Put controller into known state. */
re_reset(sc);

/*
* Enable C+ RX and TX mode, as well as VLAN stripping and
* RX checksum offload. We must configure the C+ register
* before all others.
*/
cfg = RL_CPLUSCMD_TXENB0x0001 | RL_CPLUSCMD_PCI_MRW0x0008 |
   RL_CPLUSCMD_RXCSUM_ENB0x0020;

if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020)
cfg |= RL_CPLUSCMD_VLANSTRIP0x0040;

if (sc->rl_flags & RL_FLAG_MACSTAT0x00000040)
cfg |= RL_CPLUSCMD_MACSTAT_DIS0x0080;
else
cfg |= RL_CPLUSCMD_RXENB0x0002;

CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x00E0), (
cfg)));

/*
* Init our MAC address.  Even though the chipset
* documentation doesn't mention it, we need to enter "Config
* register write enable" mode to modify the ID registers.
*/
bcopy(sc->sc_arpcom.ac_enaddr, eaddr.eaddr, ETHER_ADDR_LEN6);
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
(0x80|0x40))));
CSR_WRITE_4(sc, RL_IDR4,((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0004), (
((__uint32_t)(*(u_int32_t *)(&eaddr.eaddr[4]))))))
   htole32(*(u_int32_t *)(&eaddr.eaddr[4])))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0004), (
((__uint32_t)(*(u_int32_t *)(&eaddr.eaddr[4]))))));
CSR_WRITE_4(sc, RL_IDR0,((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0000), (
((__uint32_t)(*(u_int32_t *)(&eaddr.eaddr[0]))))))
   htole32(*(u_int32_t *)(&eaddr.eaddr[0])))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0000), (
((__uint32_t)(*(u_int32_t *)(&eaddr.eaddr[0]))))));
/*
* Default on PC Engines APU1 is to have all LEDs off unless
* there is network activity. Override to provide a link status
* LED.
*/
if (sc->sc_hwrev == RL_HWREV_8168E0x2C000000 &&
   hw_vendor != NULL((void *)0) && hw_prod != NULL((void *)0) &&
   strcmp(hw_vendor, "PC Engines") == 0 &&
   strcmp(hw_prod, "APU") == 0) {
CSR_SETBIT_1(sc, RL_CFG4, RL_CFG4_CUSTOM_LED)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0055), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0055))) |
 (0x40))));
CSR_WRITE_1(sc, RL_LEDSEL, RL_LED_LINK | RL_LED_ACT << 4)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0018), (
0x7 | 0x8 << 4)));
}
/*
* Protect config register again
*/
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
0x00)));

if ((sc->rl_flags & RL_FLAG_JUMBOV20x00100000) != 0)
re_set_jumbo(sc);

/*
* For C+ mode, initialize the RX descriptors and mbufs.
*/
re_rx_list_init(sc);
re_tx_list_init(sc);

/*
* Load the addresses of the RX and TX lists into the chip.
*/
CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,((sc->rl_btag)->write_4((sc->rl_bhandle), (0x00E8), (
((u_int64_t) (sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr
) >> 32))))
   RL_ADDR_HI(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x00E8), (
((u_int64_t) (sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr
) >> 32))));
CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,((sc->rl_btag)->write_4((sc->rl_bhandle), (0x00E4), (
((u_int64_t) (sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr
) & 0xFFFFFFFF))))
   RL_ADDR_LO(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x00E4), (
((u_int64_t) (sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr
) & 0xFFFFFFFF))));

CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0024), (
((u_int64_t) (sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr
) >> 32))))
   RL_ADDR_HI(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0024), (
((u_int64_t) (sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr
) >> 32))));
CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0020), (
((u_int64_t) (sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr
) & 0xFFFFFFFF))))
   RL_ADDR_LO(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0020), (
((u_int64_t) (sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr
) & 0xFFFFFFFF))));

if (sc->rl_flags & RL_FLAG_RXDV_GATED0x00020000)
CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &((sc->rl_btag)->write_4((sc->rl_bhandle), (0x00F0), (
((sc->rl_btag)->read_4((sc->rl_bhandle), (0x00F0))) &
 ~0x00080000)))
    ~0x00080000)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x00F0), (
((sc->rl_btag)->read_4((sc->rl_bhandle), (0x00F0))) &
 ~0x00080000)));

/*
* Set the initial TX and RX configuration.
*/
CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0040), (
(0x03000000|0x00000700))));

CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x00EC), (
16)));

rxcfg = RL_RXCFG_CONFIG(0x0000E000|0x00000700|0x00001800);
if (sc->rl_flags & RL_FLAG_EARLYOFF0x00008000)
rxcfg |= RL_RXCFG_EARLYOFF0x00003800;
else if (sc->rl_flags & RL_FLAG_EARLYOFFV20x00010000)
rxcfg |= RL_RXCFG_EARLYOFFV20x00000800;
CSR_WRITE_4(sc, RL_RXCFG, rxcfg)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0044), (
rxcfg)));

/*
* Enable transmit and receive.
*/
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0037), (
0x0004 | 0x0008)));

/* Program promiscuous mode and multicast filters. */
re_iff(sc);

/*
* Enable interrupts.
*/
re_setup_intr(sc, 1, sc->rl_imtype);
CSR_WRITE_2(sc, RL_ISR, sc->rl_intrs)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x003E), (
sc->rl_intrs)));

/* Start RX/TX process. */
CSR_WRITE_4(sc, RL_MISSEDPKT, 0)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x004C), (
0)));

/*
* For 8169 gigE NICs, set the max allowed RX packet
* size so we can receive jumbo frames.
*/
if (sc->sc_hwrev != RL_HWREV_8139CPLUS0x74800000) {
if (sc->rl_flags & RL_FLAG_PCIE0x00000004 &&
    (sc->rl_flags & RL_FLAG_JUMBOV20x00100000) == 0)
	CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x00DA), (
(1 << 11))));
else
	CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x00DA), (
16383)));
}

CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |((sc->rl_btag)->write_1((sc->rl_bhandle), (sc->rl_cfg1
), (((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->
rl_cfg1))) | 0x20)))
   RL_CFG1_DRVLOAD)((sc->rl_btag)->write_1((sc->rl_bhandle), (sc->rl_cfg1
), (((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->
rl_cfg1))) | 0x20)));

ifp->if_flags |= IFF_RUNNING0x40;
ifq_clr_oactive(&ifp->if_snd);

splx(s)spllower(s);

sc->rl_flags &= ~RL_FLAG_LINK0x00002000;
mii_mediachg(&sc->sc_mii);

timeout_add_sec(&sc->timer_handle, 1);

return (0);
1992}

1994/*
* Set media options.
*/
1997int
1998re_ifmedia_upd(struct ifnet *ifp)
1999{
struct rl_softc	*sc;

sc = ifp->if_softc;

return (mii_mediachg(&sc->sc_mii));
2005}

2007/*
* Report current media status.
*/
2010void
2011re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2012{
struct rl_softc	*sc;

sc = ifp->if_softc;

mii_pollstat(&sc->sc_mii);
ifmr->ifm_active = sc->sc_mii.mii_media_active;
ifmr->ifm_status = sc->sc_mii.mii_media_status;
2020}

2022int
2023re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2024{
struct rl_softc	*sc = ifp->if_softc;
struct ifreq	*ifr = (struct ifreq *) data;
int		s, error = 0;

s = splnet()splraise(0x7);

switch(command) {
case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
ifp->if_flags |= IFF_UP0x1;
if (!(ifp->if_flags & IFF_RUNNING0x40))
	re_init(ifp);
break;
case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
if (ifp->if_flags & IFF_UP0x1) {
	if (ifp->if_flags & IFF_RUNNING0x40)
		error = ENETRESET52;
	else
		re_init(ifp);
} else {
	if (ifp->if_flags & IFF_RUNNING0x40)
		re_stop(ifp);
}
break;
case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((56))):
case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((55))):
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
break;
case SIOCGIFRXR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((170))):
error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_dataifr_ifru.ifru_data,
    NULL((void *)0), RL_FRAMELEN(sc->rl_max_mtu)(sc->rl_max_mtu + ((6 * 2) + 2) + 4 + 4), &sc->rl_ldata.rl_rx_ring);
	break;
default:
error = ether_ioctl(ifp, &sc->sc_arpcom, command, data);
}

if (error == ENETRESET52) {
if (ifp->if_flags & IFF_RUNNING0x40)
	re_iff(sc);
error = 0;
}

splx(s)spllower(s);
return (error);
2068}

2070void
2071re_watchdog(struct ifnet *ifp)
2072{
struct rl_softc	*sc;
int	s;

sc = ifp->if_softc;
s = splnet()splraise(0x7);
printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);

re_init(ifp);

splx(s)spllower(s);
2083}

2085/*
* Stop the adapter and free any mbufs allocated to the
* RX and TX lists.
*/
2089void
2090re_stop(struct ifnet *ifp)
2091{
struct rl_softc *sc;
int	i;

sc = ifp->if_softc;

ifp->if_timer = 0;
sc->rl_flags &= ~RL_FLAG_LINK0x00002000;
sc->rl_timerintr = 0;

timeout_del(&sc->timer_handle);
ifp->if_flags &= ~IFF_RUNNING0x40;

/*
* Disable accepting frames to put RX MAC into idle state.
* Otherwise it's possible to get frames while stop command
* execution is in progress and controller can DMA the frame
* to already freed RX buffer during that period.
*/
CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0044), (
((sc->rl_btag)->read_4((sc->rl_bhandle), (0x0044))) &
 ~(0x00000001 | 0x00000008 | 0x00000002 | 0x00000004))))
   ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | RL_RXCFG_RX_INDIV |((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0044), (
((sc->rl_btag)->read_4((sc->rl_bhandle), (0x0044))) &
 ~(0x00000001 | 0x00000008 | 0x00000002 | 0x00000004))))
   RL_RXCFG_RX_MULTI))((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0044), (
((sc->rl_btag)->read_4((sc->rl_bhandle), (0x0044))) &
 ~(0x00000001 | 0x00000008 | 0x00000002 | 0x00000004))));

if (sc->rl_flags & RL_FLAG_WAIT_TXPOLL0x00400000) {
for (i = RL_TIMEOUT1000; i > 0; i--) {
	if ((CSR_READ_1(sc, sc->rl_txstart)((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->rl_txstart
))) &
	    RL_TXSTART_START0x40) == 0)
		break;
	DELAY(20)(*delay_func)(20);
}
if (i == 0)
	printf("%s: stopping TX poll timed out!\n",
	    sc->sc_dev.dv_xname);
CSR_WRITE_1(sc, RL_COMMAND, 0x00)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0037), (
0x00)));
} else if (sc->rl_flags & RL_FLAG_CMDSTOP0x00000400) {
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0037), (
0x0080 | 0x0004 | 0x0008)))
    RL_CMD_RX_ENB)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0037), (
0x0080 | 0x0004 | 0x0008)));
if (sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ0x00080000) {
	for (i = RL_TIMEOUT1000; i > 0; i--) {
		if ((CSR_READ_4(sc, RL_TXCFG)((sc->rl_btag)->read_4((sc->rl_bhandle), (0x0040))) &
		    RL_TXCFG_QUEUE_EMPTY0x00000800) != 0)
			break;
		DELAY(100)(*delay_func)(100);
	}
	if (i == 0)
		printf("%s: stopping TXQ timed out!\n",
		    sc->sc_dev.dv_xname);
}
} else
CSR_WRITE_1(sc, RL_COMMAND, 0x00)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0037), (
0x00)));
DELAY(1000)(*delay_func)(1000);
CSR_WRITE_2(sc, RL_IMR, 0x0000)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x003C), (
0x0000)));
CSR_WRITE_2(sc, RL_ISR, 0xFFFF)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x003E), (
0xFFFF)));

intr_barrier(sc->sc_ih);
ifq_barrier(&ifp->if_snd);

ifq_clr_oactive(&ifp->if_snd);
mii_down(&sc->sc_mii);

if (sc->rl_head != NULL((void *)0)) {
m_freem(sc->rl_head);
sc->rl_head = sc->rl_tail = NULL((void *)0);
}

/* Free the TX list buffers. */
for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
if (sc->rl_ldata.rl_txq[i].txq_mbuf != NULL((void *)0)) {
	bus_dmamap_unload(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (sc->
rl_ldata.rl_txq[i].txq_dmamap))
	    sc->rl_ldata.rl_txq[i].txq_dmamap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (sc->
rl_ldata.rl_txq[i].txq_dmamap));
	m_freem(sc->rl_ldata.rl_txq[i].txq_mbuf);
	sc->rl_ldata.rl_txq[i].txq_mbuf = NULL((void *)0);
}
}

/* Free the RX list buffers. */
for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
if (sc->rl_ldata.rl_rxsoft[i].rxs_mbuf != NULL((void *)0)) {
	bus_dmamap_unload(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (sc->
rl_ldata.rl_rxsoft[i].rxs_dmamap))
	    sc->rl_ldata.rl_rxsoft[i].rxs_dmamap)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (sc->
rl_ldata.rl_rxsoft[i].rxs_dmamap));
	m_freem(sc->rl_ldata.rl_rxsoft[i].rxs_mbuf);
	sc->rl_ldata.rl_rxsoft[i].rxs_mbuf = NULL((void *)0);
}
}
2175}

2177void
2178re_setup_hw_im(struct rl_softc *sc)
2179{
KASSERT(sc->rl_flags & RL_FLAG_HWIM)((sc->rl_flags & 0x00000080) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/ic/re.c", 2180, "sc->rl_flags & RL_FLAG_HWIM"
));

/*
* Interrupt moderation
*
* 0xABCD
* A - unknown (maybe TX related)
* B - TX timer (unit: 25us)
* C - unknown (maybe RX related)
* D - RX timer (unit: 25us)
*
*
* re(4)'s interrupt moderation is actually controlled by
* two variables, like most other NICs (bge, bnx etc.)
* o  timer
* o  number of packets [P]
*
* The logic relationship between these two variables is
* similar to other NICs too:
* if (timer expire || packets > [P])
*     Interrupt is delivered
*
* Currently we only know how to set 'timer', but not
* 'number of packets', which should be ~30, as far as I
* tested (sink ~900Kpps, interrupt rate is 30KHz)
*/
CSR_WRITE_2(sc, RL_IM,((sc->rl_btag)->write_2((sc->rl_bhandle), (0x00E2), (
((sc->rl_rx_time) & 0xf) | (((sc->rl_tx_time) &
 0xf) << 8) | 0x5050)))
    RL_IM_RXTIME(sc->rl_rx_time) |((sc->rl_btag)->write_2((sc->rl_bhandle), (0x00E2), (
((sc->rl_rx_time) & 0xf) | (((sc->rl_tx_time) &
 0xf) << 8) | 0x5050)))
    RL_IM_TXTIME(sc->rl_tx_time) |((sc->rl_btag)->write_2((sc->rl_bhandle), (0x00E2), (
((sc->rl_rx_time) & 0xf) | (((sc->rl_tx_time) &
 0xf) << 8) | 0x5050)))
    RL_IM_MAGIC)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x00E2), (
((sc->rl_rx_time) & 0xf) | (((sc->rl_tx_time) &
 0xf) << 8) | 0x5050)));
2210}

2212void
2213re_disable_hw_im(struct rl_softc *sc)
2214{
if (sc->rl_flags & RL_FLAG_HWIM0x00000080)
CSR_WRITE_2(sc, RL_IM, 0)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x00E2), (
0)));
2217}

2219void
2220re_setup_sim_im(struct rl_softc *sc)
2221{
if (sc->sc_hwrev == RL_HWREV_8139CPLUS0x74800000)
CSR_WRITE_4(sc, RL_TIMERINT, 0x400)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0054), (
0x400))); /* XXX */
else {
u_int32_t nticks;

/*
 * Datasheet says tick decreases at bus speed,
 * but it seems the clock runs a little bit
 * faster, so we do some compensation here.
 */
nticks = (sc->rl_sim_time * sc->rl_bus_speed * 8) / 5;
CSR_WRITE_4(sc, RL_TIMERINT_8169, nticks)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0058), (
nticks)));
}
CSR_WRITE_4(sc, RL_TIMERCNT, 1)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0048), (
1))); /* reload */
sc->rl_timerintr = 1;
2237}

2239void
2240re_disable_sim_im(struct rl_softc *sc)
2241{
if (sc->sc_hwrev == RL_HWREV_8139CPLUS0x74800000)
CSR_WRITE_4(sc, RL_TIMERINT, 0)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0054), (
0)));
else 
CSR_WRITE_4(sc, RL_TIMERINT_8169, 0)((sc->rl_btag)->write_4((sc->rl_bhandle), (0x0058), (
0)));
sc->rl_timerintr = 0;
2247}

2249void
2250re_config_imtype(struct rl_softc *sc, int imtype)
2251{
switch (imtype) {
case RL_IMTYPE_HW2:
KASSERT(sc->rl_flags & RL_FLAG_HWIM)((sc->rl_flags & 0x00000080) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/ic/re.c", 2254, "sc->rl_flags & RL_FLAG_HWIM"
));
/* FALLTHROUGH */
case RL_IMTYPE_NONE0:
sc->rl_intrs = RL_INTRS_CPLUS(0x0001|0x0002|0x0008| 0x0010|0x0040| 0x8000|0x0004);
sc->rl_rx_ack = RL_ISR_RX_OK0x0001 | RL_ISR_FIFO_OFLOW0x0040 |
		RL_ISR_RX_OVERRUN0x0010;
sc->rl_tx_ack = RL_ISR_TX_OK0x0004;
break;

case RL_IMTYPE_SIM1:
sc->rl_intrs = RL_INTRS_TIMER(0x0002|0x0008|0x8000| 0x4000);
sc->rl_rx_ack = RL_ISR_TIMEOUT_EXPIRED0x4000;
sc->rl_tx_ack = RL_ISR_TIMEOUT_EXPIRED0x4000;
break;

default:
panic("%s: unknown imtype %d",
      sc->sc_dev.dv_xname, imtype);
}
2273}

2275void
2276re_set_jumbo(struct rl_softc *sc)
2277{
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
(0x80|0x40))));
CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) |((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0054), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0054))) |
 0x04)))
   RL_CFG3_JUMBO_EN0)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0054), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0054))) |
 0x04)));

switch (sc->sc_hwrev) {
case RL_HWREV_8168DP0x28800000:
break;
case RL_HWREV_8168E0x2C000000:
CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0055), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0055))) |
 0x01)))
    RL_CFG4_8168E_JUMBO_EN1)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0055), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0055))) |
 0x01)));
break;
default:
CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0055), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0055))) |
 0x02)))
    RL_CFG4_JUMBO_EN1)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0055), (
((sc->rl_btag)->read_1((sc->rl_bhandle), (0x0055))) |
 0x02)));
break;
}

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
0x00)));
2296}

2298void
2299re_setup_intr(struct rl_softc *sc, int enable_intrs, int imtype)
2300{
re_config_imtype(sc, imtype);

if (enable_intrs)
CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x003C), (
sc->rl_intrs)));
else
CSR_WRITE_2(sc, RL_IMR, 0)((sc->rl_btag)->write_2((sc->rl_bhandle), (0x003C), (
0))); 

switch (imtype) {
case RL_IMTYPE_NONE0:
re_disable_sim_im(sc);
re_disable_hw_im(sc);
break;

case RL_IMTYPE_HW2:
KASSERT(sc->rl_flags & RL_FLAG_HWIM)((sc->rl_flags & 0x00000080) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/ic/re.c", 2315, "sc->rl_flags & RL_FLAG_HWIM"
));
re_disable_sim_im(sc);
re_setup_hw_im(sc);
break;

case RL_IMTYPE_SIM1:
re_disable_hw_im(sc);
re_setup_sim_im(sc);
break;

default:
panic("%s: unknown imtype %d",
      sc->sc_dev.dv_xname, imtype);
}
2329}

2331#ifndef SMALL_KERNEL
2332int
2333re_wol(struct ifnet *ifp, int enable)
2334{
struct rl_softc *sc = ifp->if_softc;
u_int8_t val;

if (enable) {
if ((CSR_READ_1(sc, sc->rl_cfg1)((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->rl_cfg1
))) & RL_CFG1_PME0x01) == 0) {
	printf("%s: power management is disabled, "
	    "cannot do WOL\n", sc->sc_dev.dv_xname);
	return (ENOTSUP91);
}
if ((CSR_READ_1(sc, sc->rl_cfg2)((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->rl_cfg2
))) & RL_CFG2_AUXPWR0x10) == 0)
	printf("%s: no auxiliary power, cannot do WOL from D3 "
	    "(power-off) state\n", sc->sc_dev.dv_xname);
}

re_iff(sc);

/* Temporarily enable write to configuration registers. */
CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
(0x80|0x40))));

/* Always disable all wake events except magic packet. */
if (enable) {
val = CSR_READ_1(sc, sc->rl_cfg5)((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->rl_cfg5
)));
val &= ~(RL_CFG5_WOL_UCAST0x10 | RL_CFG5_WOL_MCAST0x20 |
    RL_CFG5_WOL_BCAST0x40);
CSR_WRITE_1(sc, sc->rl_cfg5, val)((sc->rl_btag)->write_1((sc->rl_bhandle), (sc->rl_cfg5
), (val)));

val = CSR_READ_1(sc, sc->rl_cfg3)((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->rl_cfg3
)));
val |= RL_CFG3_WOL_MAGIC0x20;
val &= ~RL_CFG3_WOL_LINK0x10;
CSR_WRITE_1(sc, sc->rl_cfg3, val)((sc->rl_btag)->write_1((sc->rl_bhandle), (sc->rl_cfg3
), (val)));
} else {
val = CSR_READ_1(sc, sc->rl_cfg5)((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->rl_cfg5
)));
val &= ~(RL_CFG5_WOL_UCAST0x10 | RL_CFG5_WOL_MCAST0x20 |
    RL_CFG5_WOL_BCAST0x40);
CSR_WRITE_1(sc, sc->rl_cfg5, val)((sc->rl_btag)->write_1((sc->rl_bhandle), (sc->rl_cfg5
), (val)));

val = CSR_READ_1(sc, sc->rl_cfg3)((sc->rl_btag)->read_1((sc->rl_bhandle), (sc->rl_cfg3
)));
val &= ~(RL_CFG3_WOL_MAGIC0x20 | RL_CFG3_WOL_LINK0x10);
CSR_WRITE_1(sc, sc->rl_cfg3, val)((sc->rl_btag)->write_1((sc->rl_bhandle), (sc->rl_cfg3
), (val)));
}

CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF)((sc->rl_btag)->write_1((sc->rl_bhandle), (0x0050), (
0x00)));

return (0);
2379}
2380#endif