/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu

Bug Summary

File:	dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
Warning:	line 6388, column 27 Access to field 'hdisplay' results in a dereference of a null pointer (loaded from variable 'native_mode')
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name amdgpu_dm.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/

26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS

29#include "dm_services_types.h"
30#include "dc.h"
31#include "dc/inc/core_types.h"
32#include "dal_asic_id.h"
33#include "dmub/dmub_srv.h"
34#include "dc/inc/hw/dmcu.h"
35#include "dc/inc/hw/abm.h"
36#include "dc/dc_dmub_srv.h"

38#include "vid.h"
39#include "amdgpu.h"
40#include "amdgpu_display.h"
41#include "amdgpu_ucode.h"
42#include "atom.h"
43#include "amdgpu_dm.h"
44#ifdef CONFIG_DRM_AMD_DC_HDCP
45#include "amdgpu_dm_hdcp.h"
46#include <drm/drm_hdcp.h>
47#endif
48#include "amdgpu_pm.h"

50#include "amd_shared.h"
51#include "amdgpu_dm_irq.h"
52#include "dm_helpers.h"
53#include "amdgpu_dm_mst_types.h"
54#if defined(CONFIG_DEBUG_FS)
55#include "amdgpu_dm_debugfs.h"
56#endif

58#include "ivsrcid/ivsrcid_vislands30.h"

60#include <linux/module.h>
61#include <linux/moduleparam.h>
62#include <linux/version.h>
63#include <linux/types.h>
64#include <linux/pm_runtime.h>
65#include <linux/pci.h>
66#include <linux/firmware.h>
67#include <linux/component.h>

69#include <drm/drm_atomic.h>
70#include <drm/drm_atomic_uapi.h>
71#include <drm/drm_atomic_helper.h>
72#include <drm/drm_dp_mst_helper.h>
73#include <drm/drm_fb_helper.h>
74#include <drm/drm_fourcc.h>
75#include <drm/drm_edid.h>
76#include <drm/drm_vblank.h>
77#include <drm/drm_audio_component.h>
78#include <drm/drm_hdcp.h>

80#if defined(CONFIG_DRM_AMD_DC_DCN1)
81#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"

83#include "dcn/dcn_1_0_offset.h"
84#include "dcn/dcn_1_0_sh_mask.h"
85#include "soc15_hw_ip.h"
86#include "vega10_ip_offset.h"

88#include "soc15_common.h"
89#endif

91#include "modules/inc/mod_freesync.h"
92#include "modules/power/power_helpers.h"
93#include "modules/inc/mod_info_packet.h"

95#define FIRMWARE_RENOIR_DMUB"amdgpu/renoir_dmcub.bin" "amdgpu/renoir_dmcub.bin"
96MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
97#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
98#define FIRMWARE_SIENNA_CICHLID_DMUB"amdgpu/sienna_cichlid_dmcub.bin" "amdgpu/sienna_cichlid_dmcub.bin"
99MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
100#define FIRMWARE_NAVY_FLOUNDER_DMUB"amdgpu/navy_flounder_dmcub.bin" "amdgpu/navy_flounder_dmcub.bin"
101MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
102#endif
103#define FIRMWARE_GREEN_SARDINE_DMUB"amdgpu/green_sardine_dmcub.bin" "amdgpu/green_sardine_dmcub.bin"
104MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);

106#define FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin"		"amdgpu/raven_dmcu.bin"
107MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);

109#define FIRMWARE_NAVI12_DMCU"amdgpu/navi12_dmcu.bin"            "amdgpu/navi12_dmcu.bin"
110MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);

112/* Number of bytes in PSP header for firmware. */
113#define PSP_HEADER_BYTES0x100 0x100

115/* Number of bytes in PSP footer for firmware. */
116#define PSP_FOOTER_BYTES0x100 0x100

118/**
* DOC: overview
*
* The AMDgpu display manager, **amdgpu_dm** (or even simpler,
* **dm**) sits between DRM and DC. It acts as a liason, converting DRM
* requests into DC requests, and DC responses into DRM responses.
*
* The root control structure is &struct amdgpu_display_manager.
*/

128/* basic init/fini API */
129static int amdgpu_dm_init(struct amdgpu_device *adev);
130static void amdgpu_dm_fini(struct amdgpu_device *adev);

132static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
133{
switch (link->dpcd_caps.dongle_type) {
case DISPLAY_DONGLE_NONE:
return DRM_MODE_SUBCONNECTOR_Native;
case DISPLAY_DONGLE_DP_VGA_CONVERTER:
return DRM_MODE_SUBCONNECTOR_VGA;
case DISPLAY_DONGLE_DP_DVI_CONVERTER:
case DISPLAY_DONGLE_DP_DVI_DONGLE:
return DRM_MODE_SUBCONNECTOR_DVID;
case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
case DISPLAY_DONGLE_DP_HDMI_DONGLE:
return DRM_MODE_SUBCONNECTOR_HDMIA;
case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
default:
return DRM_MODE_SUBCONNECTOR_Unknown;
}
149}

151static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
152{
struct dc_link *link = aconnector->dc_link;
struct drm_connector *connector = &aconnector->base;
enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;

if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort10)
return;

if (aconnector->dc_sink)
subconnector = get_subconnector_type(link);

drm_object_property_set_value(&connector->base,
	connector->dev->mode_config.dp_subconnector_property,
	subconnector);
166}

168/*
* initializes drm_device display related structures, based on the information
* provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
* drm_encoder, drm_mode_config
*
* Returns 0 on success
*/
175static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
176/* removes and deallocates the drm structures, created by the above function */
177static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);

179static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
		struct drm_plane *plane,
		unsigned long possible_crtcs,
		const struct dc_plane_cap *plane_cap);
183static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
	       struct drm_plane *plane,
	       uint32_t link_index);
186static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
		    struct amdgpu_dm_connector *amdgpu_dm_connector,
		    uint32_t link_index,
		    struct amdgpu_encoder *amdgpu_encoder);
190static int amdgpu_dm_encoder_init(struct drm_device *dev,
		  struct amdgpu_encoder *aencoder,
		  uint32_t link_index);

194static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);

196static int amdgpu_dm_atomic_commit(struct drm_device *dev,
		   struct drm_atomic_state *state,
		   bool_Bool nonblock);

200static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);

202static int amdgpu_dm_atomic_check(struct drm_device *dev,
		  struct drm_atomic_state *state);

205static void handle_cursor_update(struct drm_plane *plane,
		 struct drm_plane_state *old_plane_state);

208static void amdgpu_dm_set_psr_caps(struct dc_link *link);
209static bool_Bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
210static bool_Bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
211static bool_Bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
212static bool_Bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);

214/*
* dm_vblank_get_counter
*
* @brief
* Get counter for number of vertical blanks
*
* @param
* struct amdgpu_device *adev - [in] desired amdgpu device
* int disp_idx - [in] which CRTC to get the counter from
*
* @return
* Counter for vertical blanks
*/
227static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
228{
if (crtc >= adev->mode_info.num_crtc)
return 0;
else {
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];

if (acrtc->dm_irq_params.stream == NULL((void *)0)) {
	DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc)
		  crtc)__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc);
	return 0;
}

return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
}
242}

244static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
		  u32 *vbl, u32 *position)
246{
uint32_t v_blank_start, v_blank_end, h_position, v_position;

if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
return -EINVAL22;
else {
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];

if (acrtc->dm_irq_params.stream ==  NULL((void *)0)) {
	DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc)
		  crtc)__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc);
	return 0;
}

/*
 * TODO rework base driver to use values directly.
 * for now parse it back into reg-format
 */
dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
			 &v_blank_start,
			 &v_blank_end,
			 &h_position,
			 &v_position);

*position = v_position | (h_position << 16);
*vbl = v_blank_start | (v_blank_end << 16);
}

return 0;
275}

277static bool_Bool dm_is_idle(void *handle)
278{
/* XXX todo */
return true1;
281}

283static int dm_wait_for_idle(void *handle)
284{
/* XXX todo */
return 0;
287}

289static bool_Bool dm_check_soft_reset(void *handle)
290{
return false0;
292}

294static int dm_soft_reset(void *handle)
295{
/* XXX todo */
return 0;
298}

300static struct amdgpu_crtc *
301get_crtc_by_otg_inst(struct amdgpu_device *adev,
     int otg_inst)
303{
struct drm_device *dev = adev_to_drm(adev);
struct drm_crtc *crtc;
struct amdgpu_crtc *amdgpu_crtc;

if (otg_inst == -1) {
WARN_ON(1)({ int __ret = !!(1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "1", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 309); __builtin_expect(!!(__ret), 0); });
return adev->mode_info.crtcs[0];
}

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
 ) *__mptr = ((&dev->mode_config.crtc_list)->next);
 (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&dev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
 );})) {
amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

if (amdgpu_crtc->otg_inst == otg_inst)
	return amdgpu_crtc;
}

return NULL((void *)0);
321}

323static inline bool_Bool amdgpu_dm_vrr_active_irq(struct amdgpu_crtc *acrtc)
324{
return acrtc->dm_irq_params.freesync_config.state ==
       VRR_STATE_ACTIVE_VARIABLE ||
      acrtc->dm_irq_params.freesync_config.state ==
       VRR_STATE_ACTIVE_FIXED;
329}

331static inline bool_Bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
332{
return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
      dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
335}

337/**
* dm_pflip_high_irq() - Handle pageflip interrupt
* @interrupt_params: ignored
*
* Handles the pageflip interrupt by notifying all interested parties
* that the pageflip has been completed.
*/
344static void dm_pflip_high_irq(void *interrupt_params)
345{
struct amdgpu_crtc *amdgpu_crtc;
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
unsigned long flags;
struct drm_pending_vblank_event *e;
uint32_t vpos, hpos, v_blank_start, v_blank_end;
bool_Bool vrr_active;

amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);

/* IRQ could occur when in initial stage */
/* TODO work and BO cleanup */
if (amdgpu_crtc == NULL((void *)0)) {
DRM_DEBUG_DRIVER("CRTC is null, returning.\n")__drm_dbg(DRM_UT_DRIVER, "CRTC is null, returning.\n");
return;
}

spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);

if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n"
, amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, amdgpu_crtc
->crtc_id, amdgpu_crtc)
				 amdgpu_crtc->pflip_status,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n"
, amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, amdgpu_crtc
->crtc_id, amdgpu_crtc)
				 AMDGPU_FLIP_SUBMITTED,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n"
, amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, amdgpu_crtc
->crtc_id, amdgpu_crtc)
				 amdgpu_crtc->crtc_id,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n"
, amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, amdgpu_crtc
->crtc_id, amdgpu_crtc)
				 amdgpu_crtc)__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n"
, amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED, amdgpu_crtc
->crtc_id, amdgpu_crtc);
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
return;
}

/* page flip completed. */
e = amdgpu_crtc->event;
amdgpu_crtc->event = NULL((void *)0);

if (!e)
WARN_ON(1)({ int __ret = !!(1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "1", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 380); __builtin_expect(!!(__ret), 0); });

vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);

/* Fixed refresh rate, or VRR scanout position outside front-porch? */
if (!vrr_active ||
   !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
		      &v_blank_end, &hpos, &vpos) ||
   (vpos < v_blank_start)) {
/* Update to correct count and vblank timestamp if racing with
 * vblank irq. This also updates to the correct vblank timestamp
 * even in VRR mode, as scanout is past the front-porch atm.
 */
drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);

/* Wake up userspace by sending the pageflip event with proper
 * count and timestamp of vblank of flip completion.
 */
if (e) {
	drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);

	/* Event sent, so done with vblank for this flip */
	drm_crtc_vblank_put(&amdgpu_crtc->base);
}
} else if (e) {
/* VRR active and inside front-porch: vblank count and
 * timestamp for pageflip event will only be up to date after
 * drm_crtc_handle_vblank() has been executed from late vblank
 * irq handler after start of back-porch (vline 0). We queue the
 * pageflip event for send-out by drm_crtc_handle_vblank() with
 * updated timestamp and count, once it runs after us.
 *
 * We need to open-code this instead of using the helper
 * drm_crtc_arm_vblank_event(), as that helper would
 * call drm_crtc_accurate_vblank_count(), which we must
 * not call in VRR mode while we are in front-porch!
 */

/* sequence will be replaced by real count during send-out. */
e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
e->pipe = amdgpu_crtc->crtc_id;

list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
e = NULL((void *)0);
}

/* Keep track of vblank of this flip for flip throttling. We use the
* cooked hw counter, as that one incremented at start of this vblank
* of pageflip completion, so last_flip_vblank is the forbidden count
* for queueing new pageflips if vsync + VRR is enabled.
*/
amdgpu_crtc->dm_irq_params.last_flip_vblank =
amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);

amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);

DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",__drm_dbg(DRM_UT_DRIVER, "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n"
, amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int) !e)
	 amdgpu_crtc->crtc_id, amdgpu_crtc,__drm_dbg(DRM_UT_DRIVER, "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n"
, amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int) !e)
	 vrr_active, (int) !e)__drm_dbg(DRM_UT_DRIVER, "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n"
, amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int) !e);
440}

442static void dm_vupdate_high_irq(void *interrupt_params)
443{
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
struct amdgpu_crtc *acrtc;
unsigned long flags;
int vrr_active;

acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);

if (acrtc) {
vrr_active = amdgpu_dm_vrr_active_irq(acrtc);

DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d\n",__drm_dbg(DRM_UT_VBL, "crtc:%d, vupdate-vrr:%d\n", acrtc->
crtc_id, vrr_active)
	      acrtc->crtc_id,__drm_dbg(DRM_UT_VBL, "crtc:%d, vupdate-vrr:%d\n", acrtc->
crtc_id, vrr_active)
	      vrr_active)__drm_dbg(DRM_UT_VBL, "crtc:%d, vupdate-vrr:%d\n", acrtc->
crtc_id, vrr_active);

/* Core vblank handling is done here after end of front-porch in
 * vrr mode, as vblank timestamping will give valid results
 * while now done after front-porch. This will also deliver
 * page-flip completion events that have been queued to us
 * if a pageflip happened inside front-porch.
 */
if (vrr_active) {
	drm_crtc_handle_vblank(&acrtc->base);

	/* BTR processing for pre-DCE12 ASICs */
	if (acrtc->dm_irq_params.stream &&
	    adev->family < AMDGPU_FAMILY_AI141) {
		spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
		mod_freesync_handle_v_update(
		    adev->dm.freesync_module,
		    acrtc->dm_irq_params.stream,
		    &acrtc->dm_irq_params.vrr_params);

		dc_stream_adjust_vmin_vmax(
		    adev->dm.dc,
		    acrtc->dm_irq_params.stream,
		    &acrtc->dm_irq_params.vrr_params.adjust);
		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
	}
}
}
485}

487/**
* dm_crtc_high_irq() - Handles CRTC interrupt
* @interrupt_params: used for determining the CRTC instance
*
* Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
* event handler.
*/
494static void dm_crtc_high_irq(void *interrupt_params)
495{
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
struct amdgpu_crtc *acrtc;
unsigned long flags;
int vrr_active;

acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
if (!acrtc)
return;

vrr_active = amdgpu_dm_vrr_active_irq(acrtc);

DRM_DEBUG_VBL("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,__drm_dbg(DRM_UT_VBL, "crtc:%d, vupdate-vrr:%d, planes:%d\n",
 acrtc->crtc_id, vrr_active, acrtc->dm_irq_params.active_planes
)
      vrr_active, acrtc->dm_irq_params.active_planes)__drm_dbg(DRM_UT_VBL, "crtc:%d, vupdate-vrr:%d, planes:%d\n",
 acrtc->crtc_id, vrr_active, acrtc->dm_irq_params.active_planes
);

/**
* Core vblank handling at start of front-porch is only possible
* in non-vrr mode, as only there vblank timestamping will give
* valid results while done in front-porch. Otherwise defer it
* to dm_vupdate_high_irq after end of front-porch.
*/
if (!vrr_active)
drm_crtc_handle_vblank(&acrtc->base);

/**
* Following stuff must happen at start of vblank, for crc
* computation and below-the-range btr support in vrr mode.
*/
amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);

/* BTR updates need to happen before VUPDATE on Vega and above. */
if (adev->family < AMDGPU_FAMILY_AI141)
return;

spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);

if (acrtc->dm_irq_params.stream &&
   acrtc->dm_irq_params.vrr_params.supported &&
   acrtc->dm_irq_params.freesync_config.state ==
    VRR_STATE_ACTIVE_VARIABLE) {
mod_freesync_handle_v_update(adev->dm.freesync_module,
			     acrtc->dm_irq_params.stream,
			     &acrtc->dm_irq_params.vrr_params);

dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
			   &acrtc->dm_irq_params.vrr_params.adjust);
}

/*
* If there aren't any active_planes then DCH HUBP may be clock-gated.
* In that case, pageflip completion interrupts won't fire and pageflip
* completion events won't get delivered. Prevent this by sending
* pending pageflip events from here if a flip is still pending.
*
* If any planes are enabled, use dm_pflip_high_irq() instead, to
* avoid race conditions between flip programming and completion,
* which could cause too early flip completion events.
*/
if (adev->family >= AMDGPU_FAMILY_RV142 &&
   acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
   acrtc->dm_irq_params.active_planes == 0) {
if (acrtc->event) {
	drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
	acrtc->event = NULL((void *)0);
	drm_crtc_vblank_put(&acrtc->base);
}
acrtc->pflip_status = AMDGPU_FLIP_NONE;
}

spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
566}

568static int dm_set_clockgating_state(void *handle,
  enum amd_clockgating_state state)
570{
return 0;
572}

574static int dm_set_powergating_state(void *handle,
  enum amd_powergating_state state)
576{
return 0;
578}

580/* Prototypes of private functions */
581static int dm_early_init(void* handle);

583/* Allocate memory for FBC compressed data  */
584static void amdgpu_dm_fbc_init(struct drm_connector *connector)
585{
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_compressor_info *compressor = &adev->dm.compressor;
struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct drm_display_mode *mode;
unsigned long max_size = 0;

if (adev->dm.dc->fbc_compressor == NULL((void *)0))
return;

if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
return;

if (compressor->bo_ptr)
return;


list_for_each_entry(mode, &connector->modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head
 ) *__mptr = ((&connector->modes)->next); (__typeof
(*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode
), head) );}); &mode->head != (&connector->modes
); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head )
 *__mptr = (mode->head.next); (__typeof(*mode) *)( (char *
)__mptr - __builtin_offsetof(__typeof(*mode), head) );})) {
if (max_size < mode->htotal * mode->vtotal)
	max_size = mode->htotal * mode->vtotal;
}

if (max_size) {
int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE(1 << 12),
	    AMDGPU_GEM_DOMAIN_GTT0x2, &compressor->bo_ptr,
	    &compressor->gpu_addr, &compressor->cpu_addr);

if (r)
	DRM_ERROR("DM: Failed to initialize FBC\n")__drm_err("DM: Failed to initialize FBC\n");
else {
	adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
	DRM_INFO("DM: FBC alloc %lu\n", max_size*4)printk("\0016" "[" "drm" "] " "DM: FBC alloc %lu\n", max_size
*4);
}

}

622}

624static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
			  int pipe, bool_Bool *enabled,
			  unsigned char *buf, int max_bytes)
627{
struct drm_device *dev = dev_get_drvdata(kdev)((void *)0);
struct amdgpu_device *adev = drm_to_adev(dev);
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
struct amdgpu_dm_connector *aconnector;
int ret = 0;

*enabled = false0;

mutex_lock(&adev->dm.audio_lock)rw_enter_write(&adev->dm.audio_lock);

drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter
))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (aconnector->audio_inst != port)
	continue;

*enabled = true1;
ret = drm_eld_size(connector->eld);
memcpy(buf, connector->eld, min(max_bytes, ret))__builtin_memcpy((buf), (connector->eld), ((((max_bytes)<
(ret))?(max_bytes):(ret))));

break;
}
drm_connector_list_iter_end(&conn_iter);

mutex_unlock(&adev->dm.audio_lock)rw_exit_write(&adev->dm.audio_lock);

DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled)__drm_dbg(DRM_UT_KMS, "Get ELD : idx=%d ret=%d en=%d\n", port
, ret, *enabled);

return ret;
658}

660static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
.get_eld = amdgpu_dm_audio_component_get_eld,
662};

664static int amdgpu_dm_audio_component_bind(struct device *kdev,
		       struct device *hda_kdev, void *data)
666{
struct drm_device *dev = dev_get_drvdata(kdev)((void *)0);
struct amdgpu_device *adev = drm_to_adev(dev);
struct drm_audio_component *acomp = data;

acomp->ops = &amdgpu_dm_audio_component_ops;
acomp->dev = kdev;
adev->dm.audio_component = acomp;

return 0;
676}

678static void amdgpu_dm_audio_component_unbind(struct device *kdev,
			  struct device *hda_kdev, void *data)
680{
struct drm_device *dev = dev_get_drvdata(kdev)((void *)0);
struct amdgpu_device *adev = drm_to_adev(dev);
struct drm_audio_component *acomp = data;

acomp->ops = NULL((void *)0);
acomp->dev = NULL((void *)0);
adev->dm.audio_component = NULL((void *)0);
688}

690#ifdef notyet
691static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
.bind	= amdgpu_dm_audio_component_bind,
.unbind	= amdgpu_dm_audio_component_unbind,
694};
695#endif

697static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
698{
int i, ret;

if (!amdgpu_audio)
return 0;

adev->mode_info.audio.enabled = true1;

adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;

for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
adev->mode_info.audio.pin[i].channels = -1;
adev->mode_info.audio.pin[i].rate = -1;
adev->mode_info.audio.pin[i].bits_per_sample = -1;
adev->mode_info.audio.pin[i].status_bits = 0;
adev->mode_info.audio.pin[i].category_code = 0;
adev->mode_info.audio.pin[i].connected = false0;
adev->mode_info.audio.pin[i].id =
	adev->dm.dc->res_pool->audios[i]->inst;
adev->mode_info.audio.pin[i].offset = 0;
}

ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops)0;
if (ret < 0)
return ret;

adev->dm.audio_registered = true1;

return 0;
727}

729static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
730{
if (!amdgpu_audio)
return;

if (!adev->mode_info.audio.enabled)
return;

if (adev->dm.audio_registered) {
component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
adev->dm.audio_registered = false0;
}

/* TODO: Disable audio? */

adev->mode_info.audio.enabled = false0;
745}

747static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
748{
struct drm_audio_component *acomp = adev->dm.audio_component;

if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
DRM_DEBUG_KMS("Notify ELD: %d\n", pin)__drm_dbg(DRM_UT_KMS, "Notify ELD: %d\n", pin);

acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
				 pin, -1);
}
757}

759static int dm_dmub_hw_init(struct amdgpu_device *adev)
760{
const struct dmcub_firmware_header_v1_0 *hdr;
struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
const struct firmware *dmub_fw = adev->dm.dmub_fw;
struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
struct abm *abm = adev->dm.dc->res_pool->abm;
struct dmub_srv_hw_params hw_params;
enum dmub_status status;
const unsigned char *fw_inst_const, *fw_bss_data;
uint32_t i, fw_inst_const_size, fw_bss_data_size;
bool_Bool has_hw_support;

if (!dmub_srv)
/* DMUB isn't supported on the ASIC. */
return 0;

if (!fb_info) {
DRM_ERROR("No framebuffer info for DMUB service.\n")__drm_err("No framebuffer info for DMUB service.\n");
return -EINVAL22;
}

if (!dmub_fw) {
/* Firmware required for DMUB support. */
DRM_ERROR("No firmware provided for DMUB.\n")__drm_err("No firmware provided for DMUB.\n");
return -EINVAL22;
}

status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error checking HW support for DMUB: %d\n", status)__drm_err("Error checking HW support for DMUB: %d\n", status);
return -EINVAL22;
}

if (!has_hw_support) {
DRM_INFO("DMUB unsupported on ASIC\n")printk("\0016" "[" "drm" "] " "DMUB unsupported on ASIC\n");
return 0;
}

hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;

fw_inst_const = dmub_fw->data +
	le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) +
	PSP_HEADER_BYTES0x100;

fw_bss_data = dmub_fw->data +
      le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) +
      le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes));

/* Copy firmware and bios info into FB memory. */
fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) -
	     PSP_HEADER_BYTES0x100 - PSP_FOOTER_BYTES0x100;

fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes)((__uint32_t)(hdr->bss_data_bytes));

/* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
* amdgpu_ucode_init_single_fw will load dmub firmware
* fw_inst_const part to cw0; otherwise, the firmware back door load
* will be done by dm_dmub_hw_init
*/
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr
), (fw_inst_const), (fw_inst_const_size))
		fw_inst_const_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr
), (fw_inst_const), (fw_inst_const_size));
}

if (fw_bss_data_size)
memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr
), (fw_bss_data), (fw_bss_data_size))
       fw_bss_data, fw_bss_data_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr
), (fw_bss_data), (fw_bss_data_size));

/* Copy firmware bios info into FB memory. */
memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr
), (adev->bios), (adev->bios_size))
      adev->bios_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr
), (adev->bios), (adev->bios_size));

/* Reset regions that need to be reset. */
memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_4_MAILBOX].size))
fb_info->fb[DMUB_WINDOW_4_MAILBOX].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_4_MAILBOX].size));

memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size))
      fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size));

memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_6_FW_STATE].size))
      fb_info->fb[DMUB_WINDOW_6_FW_STATE].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_6_FW_STATE].size));

/* Initialize hardware. */
memset(&hw_params, 0, sizeof(hw_params))__builtin_memset((&hw_params), (0), (sizeof(hw_params)));
hw_params.fb_base = adev->gmc.fb_start;
hw_params.fb_offset = adev->gmc.aper_base;

/* backdoor load firmware and trigger dmub running */
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
hw_params.load_inst_const = true1;

if (dmcu)
hw_params.psp_version = dmcu->psp_version;

for (i = 0; i < fb_info->num_fb; ++i)
hw_params.fb[i] = &fb_info->fb[i];

status = dmub_srv_hw_init(dmub_srv, &hw_params);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error initializing DMUB HW: %d\n", status)__drm_err("Error initializing DMUB HW: %d\n", status);
return -EINVAL22;
}

/* Wait for firmware load to finish. */
status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
if (status != DMUB_STATUS_OK)
DRM_WARN("Wait for DMUB auto-load failed: %d\n", status)printk("\0014" "[" "drm" "] " "Wait for DMUB auto-load failed: %d\n"
, status);

/* Init DMCU and ABM if available. */
if (dmcu && abm) {
dmcu->funcs->dmcu_init(dmcu);
abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
}

if (!adev->dm.dc->ctx->dmub_srv)
adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
if (!adev->dm.dc->ctx->dmub_srv) {
DRM_ERROR("Couldn't allocate DC DMUB server!\n")__drm_err("Couldn't allocate DC DMUB server!\n");
return -ENOMEM12;
}

DRM_INFO("DMUB hardware initialized: version=0x%08X\n",printk("\0016" "[" "drm" "] " "DMUB hardware initialized: version=0x%08X\n"
, adev->dm.dmcub_fw_version)
 adev->dm.dmcub_fw_version)printk("\0016" "[" "drm" "] " "DMUB hardware initialized: version=0x%08X\n"
, adev->dm.dmcub_fw_version);

return 0;
886}

888static void amdgpu_check_debugfs_connector_property_change(struct amdgpu_device *adev,
					   struct drm_atomic_state *state)
890{
struct drm_connector *connector;
struct drm_crtc *crtc;
struct amdgpu_dm_connector *amdgpu_dm_connector;
struct drm_connector_state *conn_state;
struct dm_crtc_state *acrtc_state;
struct drm_crtc_state *crtc_state;
struct dc_stream_state *stream;
struct drm_device *dev = adev_to_drm(adev);

list_for_each_entry(connector, &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
 (&dev->mode_config.connector_list); connector = ({ const
 __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*connector), head) );})) {

amdgpu_dm_connector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
conn_state = connector->state;

if (!(conn_state && conn_state->crtc))
	continue;

crtc = conn_state->crtc;
acrtc_state = to_dm_crtc_state(crtc->state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (crtc->state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (!(acrtc_state && acrtc_state->stream))
	continue;

stream = acrtc_state->stream;

if (amdgpu_dm_connector->dsc_settings.dsc_force_enable ||
    amdgpu_dm_connector->dsc_settings.dsc_num_slices_v ||
    amdgpu_dm_connector->dsc_settings.dsc_num_slices_h ||
    amdgpu_dm_connector->dsc_settings.dsc_bits_per_pixel) {
	conn_state = drm_atomic_get_connector_state(state, connector);
	crtc_state = drm_atomic_get_crtc_state(state, crtc);
	crtc_state->mode_changed = true1;
}
}
925}

927static int amdgpu_dm_init(struct amdgpu_device *adev)
928{
struct dc_init_data init_data;
930#ifdef CONFIG_DRM_AMD_DC_HDCP
struct dc_callback_init init_params;
932#endif
int r;

adev->dm.ddev = adev_to_drm(adev);
adev->dm.adev = adev;

/* Zero all the fields */
memset(&init_data, 0, sizeof(init_data))__builtin_memset((&init_data), (0), (sizeof(init_data)));
940#ifdef CONFIG_DRM_AMD_DC_HDCP
memset(&init_params, 0, sizeof(init_params))__builtin_memset((&init_params), (0), (sizeof(init_params
)));
942#endif

rw_init(&adev->dm.dc_lock, "dmdc")_rw_init_flags(&adev->dm.dc_lock, "dmdc", 0, ((void *)
0));
rw_init(&adev->dm.audio_lock, "dmaud")_rw_init_flags(&adev->dm.audio_lock, "dmaud", 0, ((void
 *)0));

if(amdgpu_dm_irq_init(adev)) {
DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n")__drm_err("amdgpu: failed to initialize DM IRQ support.\n");
goto error;
}

init_data.asic_id.chip_family = adev->family;

init_data.asic_id.pci_revision_id = adev->pdev->revision;
init_data.asic_id.hw_internal_rev = adev->external_rev_id;
init_data.asic_id.chip_id = adev->pdev->device;

init_data.asic_id.vram_width = adev->gmc.vram_width;
/* TODO: initialize init_data.asic_id.vram_type here!!!! */
init_data.asic_id.atombios_base_address =
adev->mode_info.atom_context->bios;

init_data.driver = adev;

adev->dm.cgs_device = amdgpu_cgs_create_device(adev);

if (!adev->dm.cgs_device) {
DRM_ERROR("amdgpu: failed to create cgs device.\n")__drm_err("amdgpu: failed to create cgs device.\n");
goto error;
}

init_data.cgs_device = adev->dm.cgs_device;

init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;

switch (adev->asic_type) {
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_RAVEN:
case CHIP_RENOIR:
init_data.flags.gpu_vm_support = true1;
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)((adev->external_rev_id >= 0xA1) && (adev->external_rev_id
 < 0xFF)))
	init_data.flags.disable_dmcu = true1;
break;
default:
break;
}

if (amdgpu_dc_feature_mask & DC_FBC_MASK)
init_data.flags.fbc_support = true1;

if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
init_data.flags.multi_mon_pp_mclk_switch = true1;

if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
init_data.flags.disable_fractional_pwm = true1;

init_data.flags.power_down_display_on_boot = true1;

init_data.soc_bounding_box = adev->dm.soc_bounding_box;

/* Display Core create. */
adev->dm.dc = dc_create(&init_data);

if (adev->dm.dc) {
DRM_INFO("Display Core initialized with v%s!\n", DC_VER)printk("\0016" "[" "drm" "] " "Display Core initialized with v%s!\n"
, "3.2.104");
} else {
DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER)printk("\0016" "[" "drm" "] " "Display Core failed to initialize with v%s!\n"
, "3.2.104");
goto error;
}

if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
adev->dm.dc->debug.force_single_disp_pipe_split = false0;
adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
}

if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false0 : true1;

if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
adev->dm.dc->debug.disable_stutter = true1;

if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
adev->dm.dc->debug.disable_dsc = true1;

if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
adev->dm.dc->debug.disable_clock_gate = true1;

r = dm_dmub_hw_init(adev);
if (r) {
DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r)__drm_err("DMUB interface failed to initialize: status=%d\n",
 r);
goto error;
}

dc_hardware_init(adev->dm.dc);

adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
if (!adev->dm.freesync_module) {
DRM_ERROR(__drm_err("amdgpu: failed to initialize freesync_module.\n")
"amdgpu: failed to initialize freesync_module.\n")__drm_err("amdgpu: failed to initialize freesync_module.\n");
} else
DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",__drm_dbg(DRM_UT_DRIVER, "amdgpu: freesync_module init done %p.\n"
, adev->dm.freesync_module)
		adev->dm.freesync_module)__drm_dbg(DRM_UT_DRIVER, "amdgpu: freesync_module init done %p.\n"
, adev->dm.freesync_module);

amdgpu_dm_init_color_mod();

1047#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);

if (!adev->dm.hdcp_workqueue)
	DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n")__drm_err("amdgpu: failed to initialize hdcp_workqueue.\n");
else
	DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue)__drm_dbg(DRM_UT_DRIVER, "amdgpu: hdcp_workqueue init done %p.\n"
, adev->dm.hdcp_workqueue);

dc_init_callbacks(adev->dm.dc, &init_params);
}
1058#endif
if (amdgpu_dm_initialize_drm_device(adev)) {
DRM_ERROR(__drm_err("amdgpu: failed to initialize sw for display support.\n"
)
"amdgpu: failed to initialize sw for display support.\n")__drm_err("amdgpu: failed to initialize sw for display support.\n"
);
goto error;
}

/* create fake encoders for MST */
dm_dp_create_fake_mst_encoders(adev);

/* TODO: Add_display_info? */

/* TODO use dynamic cursor width */
adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;

if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
DRM_ERROR(__drm_err("amdgpu: failed to initialize sw for display support.\n"
)
"amdgpu: failed to initialize sw for display support.\n")__drm_err("amdgpu: failed to initialize sw for display support.\n"
);
goto error;
}

DRM_DEBUG_DRIVER("KMS initialized.\n")__drm_dbg(DRM_UT_DRIVER, "KMS initialized.\n");

return 0;
1083error:
amdgpu_dm_fini(adev);

return -EINVAL22;
1087}

1089static void amdgpu_dm_fini(struct amdgpu_device *adev)
1090{
int i;

for (i = 0; i < adev->dm.display_indexes_num; i++) {
drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
}

amdgpu_dm_audio_fini(adev);

amdgpu_dm_destroy_drm_device(&adev->dm);

1101#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.hdcp_workqueue) {
hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
adev->dm.hdcp_workqueue = NULL((void *)0);
}

if (adev->dm.dc)
dc_deinit_callbacks(adev->dm.dc);
1109#endif
if (adev->dm.dc->ctx->dmub_srv) {
dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
adev->dm.dc->ctx->dmub_srv = NULL((void *)0);
}

if (adev->dm.dmub_bo)
amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
		      &adev->dm.dmub_bo_gpu_addr,
		      &adev->dm.dmub_bo_cpu_addr);

/* DC Destroy TODO: Replace destroy DAL */
if (adev->dm.dc)
dc_destroy(&adev->dm.dc);
/*
* TODO: pageflip, vlank interrupt
*
* amdgpu_dm_irq_fini(adev);
*/

if (adev->dm.cgs_device) {
amdgpu_cgs_destroy_device(adev->dm.cgs_device);
adev->dm.cgs_device = NULL((void *)0);
}
if (adev->dm.freesync_module) {
mod_freesync_destroy(adev->dm.freesync_module);
adev->dm.freesync_module = NULL((void *)0);
}

mutex_destroy(&adev->dm.audio_lock);
mutex_destroy(&adev->dm.dc_lock);

return;
1142}

1144static int load_dmcu_fw(struct amdgpu_device *adev)
1145{
const char *fw_name_dmcu = NULL((void *)0);
int r;
const struct dmcu_firmware_header_v1_0 *hdr;

switch(adev->asic_type) {
1151#if defined(CONFIG_DRM_AMD_DC_SI)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
1156#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_TONGA:
case CHIP_FIJI:
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
case CHIP_VEGAM:
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_RENOIR:
1176#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
1179#endif
return 0;
case CHIP_NAVI12:
fw_name_dmcu = FIRMWARE_NAVI12_DMCU"amdgpu/navi12_dmcu.bin";
break;
case CHIP_RAVEN:
if (ASICREV_IS_PICASSO(adev->external_rev_id)((adev->external_rev_id >= 0x41) && (adev->external_rev_id
 < 0x81)))
	fw_name_dmcu = FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin";
else if (ASICREV_IS_RAVEN2(adev->external_rev_id)((adev->external_rev_id >= 0x81) && (adev->external_rev_id
 < 0x91)))
	fw_name_dmcu = FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin";
else
	return 0;
break;
default:
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type)__drm_err("Unsupported ASIC type: 0x%X\n", adev->asic_type
);
return -EINVAL22;
}

if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n")__drm_dbg(DRM_UT_KMS, "dm: DMCU firmware not supported on direct or SMU loading\n"
);
return 0;
}

r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
if (r == -ENOENT2) {
/* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
DRM_DEBUG_KMS("dm: DMCU firmware not found\n")__drm_dbg(DRM_UT_KMS, "dm: DMCU firmware not found\n");
adev->dm.fw_dmcu = NULL((void *)0);
return 0;
}
if (r) {
dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu
)
	fw_name_dmcu)printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu
);
return r;
}

r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
if (r) {
dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't validate firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu
)
	fw_name_dmcu)printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't validate firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu
);
release_firmware(adev->dm.fw_dmcu);
adev->dm.fw_dmcu = NULL((void *)0);
return r;
}

hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
adev->firmware.fw_size +=
roundup2(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->header.ucode_size_bytes)) - ((__uint32_t
)(hdr->intv_size_bytes))) + (((1 << 12)) - 1)) &
 (~((__typeof(((__uint32_t)(hdr->header.ucode_size_bytes))
 - ((__uint32_t)(hdr->intv_size_bytes))))((1 << 12))
 - 1)));

adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
adev->firmware.fw_size +=
roundup2(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->intv_size_bytes))) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(hdr->intv_size_bytes
))))((1 << 12)) - 1)));

adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version));

DRM_DEBUG_KMS("PSP loading DMCU firmware\n")__drm_dbg(DRM_UT_KMS, "PSP loading DMCU firmware\n");

return 0;
1240}

1242static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1243{
struct amdgpu_device *adev = ctx;

return dm_read_reg(adev->dm.dc->ctx, address)dm_read_reg_func(adev->dm.dc->ctx, address, __func__);
1247}

1249static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
		     uint32_t value)
1251{
struct amdgpu_device *adev = ctx;

return dm_write_reg(adev->dm.dc->ctx, address, value)dm_write_reg_func(adev->dm.dc->ctx, address, value, __func__
);
1255}

1257static int dm_dmub_sw_init(struct amdgpu_device *adev)
1258{
struct dmub_srv_create_params create_params;
struct dmub_srv_region_params region_params;
struct dmub_srv_region_info region_info;
struct dmub_srv_fb_params fb_params;
struct dmub_srv_fb_info *fb_info;
struct dmub_srv *dmub_srv;
const struct dmcub_firmware_header_v1_0 *hdr;
const char *fw_name_dmub;
enum dmub_asic dmub_asic;
enum dmub_status status;
int r;

switch (adev->asic_type) {
case CHIP_RENOIR:
dmub_asic = DMUB_ASIC_DCN21;
fw_name_dmub = FIRMWARE_RENOIR_DMUB"amdgpu/renoir_dmcub.bin";
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)((adev->external_rev_id >= 0xA1) && (adev->external_rev_id
 < 0xFF)))
	fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB"amdgpu/green_sardine_dmcub.bin";
break;
1278#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
case CHIP_SIENNA_CICHLID:
dmub_asic = DMUB_ASIC_DCN30;
fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB"amdgpu/sienna_cichlid_dmcub.bin";
break;
case CHIP_NAVY_FLOUNDER:
dmub_asic = DMUB_ASIC_DCN30;
fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB"amdgpu/navy_flounder_dmcub.bin";
break;
1287#endif

default:
/* ASIC doesn't support DMUB. */
return 0;
}

r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
if (r) {
DRM_ERROR("DMUB firmware loading failed: %d\n", r)__drm_err("DMUB firmware loading failed: %d\n", r);
return 0;
}

r = amdgpu_ucode_validate(adev->dm.dmub_fw);
if (r) {
DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r)__drm_err("Couldn't validate DMUB firmware: %d\n", r);
return 0;
}

hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version));

if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
	AMDGPU_UCODE_ID_DMCUB;
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
	adev->dm.dmub_fw;
adev->firmware.fw_size +=
	roundup2(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->inst_const_bytes))) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(hdr->inst_const_bytes
))))((1 << 12)) - 1)));

DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",printk("\0016" "[" "drm" "] " "Loading DMUB firmware via PSP: version=0x%08X\n"
, adev->dm.dmcub_fw_version)
	 adev->dm.dmcub_fw_version)printk("\0016" "[" "drm" "] " "Loading DMUB firmware via PSP: version=0x%08X\n"
, adev->dm.dmcub_fw_version);
}


adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL(0x0001 | 0x0004));
dmub_srv = adev->dm.dmub_srv;

if (!dmub_srv) {
DRM_ERROR("Failed to allocate DMUB service!\n")__drm_err("Failed to allocate DMUB service!\n");
return -ENOMEM12;
}

memset(&create_params, 0, sizeof(create_params))__builtin_memset((&create_params), (0), (sizeof(create_params
)));
create_params.user_ctx = adev;
create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
create_params.asic = dmub_asic;

/* Create the DMUB service. */
status = dmub_srv_create(dmub_srv, &create_params);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error creating DMUB service: %d\n", status)__drm_err("Error creating DMUB service: %d\n", status);
return -EINVAL22;
}

/* Calculate the size of all the regions for the DMUB service. */
memset(&region_params, 0, sizeof(region_params))__builtin_memset((&region_params), (0), (sizeof(region_params
)));

region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) -
			PSP_HEADER_BYTES0x100 - PSP_FOOTER_BYTES0x100;
region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes)((__uint32_t)(hdr->bss_data_bytes));
region_params.vbios_size = adev->bios_size;
region_params.fw_bss_data = region_params.bss_data_size ?
adev->dm.dmub_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) +
le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) : NULL((void *)0);
region_params.fw_inst_const =
adev->dm.dmub_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) +
PSP_HEADER_BYTES0x100;

status = dmub_srv_calc_region_info(dmub_srv, &region_params,
			   &region_info);

if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error calculating DMUB region info: %d\n", status)__drm_err("Error calculating DMUB region info: %d\n", status);
return -EINVAL22;
}

/*
* Allocate a framebuffer based on the total size of all the regions.
* TODO: Move this into GART.
*/
r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE(1 << 12),
		    AMDGPU_GEM_DOMAIN_VRAM0x4, &adev->dm.dmub_bo,
		    &adev->dm.dmub_bo_gpu_addr,
		    &adev->dm.dmub_bo_cpu_addr);
if (r)
return r;

/* Rebase the regions on the framebuffer address. */
memset(&fb_params, 0, sizeof(fb_params))__builtin_memset((&fb_params), (0), (sizeof(fb_params)));
fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
fb_params.region_info = &region_info;

adev->dm.dmub_fb_info =
kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL(0x0001 | 0x0004));
fb_info = adev->dm.dmub_fb_info;

if (!fb_info) {
DRM_ERROR(__drm_err("Failed to allocate framebuffer info for DMUB service!\n"
)
	"Failed to allocate framebuffer info for DMUB service!\n")__drm_err("Failed to allocate framebuffer info for DMUB service!\n"
);
return -ENOMEM12;
}

status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error calculating DMUB FB info: %d\n", status)__drm_err("Error calculating DMUB FB info: %d\n", status);
return -EINVAL22;
}

return 0;
1401}

1403static int dm_sw_init(void *handle)
1404{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;

r = dm_dmub_sw_init(adev);
if (r)
return r;

return load_dmcu_fw(adev);
1413}

1415static int dm_sw_fini(void *handle)
1416{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

kfree(adev->dm.dmub_fb_info);
adev->dm.dmub_fb_info = NULL((void *)0);

if (adev->dm.dmub_srv) {
dmub_srv_destroy(adev->dm.dmub_srv);
adev->dm.dmub_srv = NULL((void *)0);
}

release_firmware(adev->dm.dmub_fw);
adev->dm.dmub_fw = NULL((void *)0);

release_firmware(adev->dm.fw_dmcu);
adev->dm.fw_dmcu = NULL((void *)0);

return 0;
1434}

1436static int detect_mst_link_for_all_connectors(struct drm_device *dev)
1437{
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
int ret = 0;

drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (aconnector->dc_link->type == dc_connection_mst_branch &&
    aconnector->mst_mgr.aux) {
	DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",__drm_dbg(DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n"
, aconnector, aconnector->base.base.id)
			 aconnector,__drm_dbg(DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n"
, aconnector, aconnector->base.base.id)
			 aconnector->base.base.id)__drm_dbg(DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n"
, aconnector, aconnector->base.base.id);

	ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true1);
	if (ret < 0) {
		DRM_ERROR("DM_MST: Failed to start MST\n")__drm_err("DM_MST: Failed to start MST\n");
		aconnector->dc_link->type =
			dc_connection_single;
		break;
	}
}
}
drm_connector_list_iter_end(&iter);

return ret;
1464}

1466static int dm_late_init(void *handle)
1467{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

struct dmcu_iram_parameters params;
unsigned int linear_lut[16];
int i;
struct dmcu *dmcu = NULL((void *)0);
bool_Bool ret = true1;

dmcu = adev->dm.dc->res_pool->dmcu;

for (i = 0; i < 16; i++)
linear_lut[i] = 0xFFFF * i / 15;

params.set = 0;
params.backlight_ramping_start = 0xCCCC;
params.backlight_ramping_reduction = 0xCCCCCCCC;
params.backlight_lut_array_size = 16;
params.backlight_lut_array = linear_lut;

/* Min backlight level after ABM reduction,  Don't allow below 1%
* 0xFFFF x 0.01 = 0x28F
*/
params.min_abm_backlight = 0x28F;

/* In the case where abm is implemented on dmcub,
* dmcu object will be null.
* ABM 2.4 and up are implemented on dmcub.
*/
if (dmcu)
ret = dmcu_load_iram(dmcu, params);
else if (adev->dm.dc->ctx->dmub_srv)
ret = dmub_init_abm_config(adev->dm.dc->res_pool, params);

if (!ret)
return -EINVAL22;

return detect_mst_link_for_all_connectors(adev_to_drm(adev));
1505}

1507static void s3_handle_mst(struct drm_device *dev, bool_Bool suspend)
1508{
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
struct drm_dp_mst_topology_mgr *mgr;
int ret;
bool_Bool need_hotplug = false0;

drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (aconnector->dc_link->type != dc_connection_mst_branch ||
    aconnector->mst_port)
	continue;

mgr = &aconnector->mst_mgr;

if (suspend) {
	drm_dp_mst_topology_mgr_suspend(mgr);
} else {
	ret = drm_dp_mst_topology_mgr_resume(mgr, true1);
	if (ret < 0) {
		drm_dp_mst_topology_mgr_set_mst(mgr, false0);
		need_hotplug = true1;
	}
}
}
drm_connector_list_iter_end(&iter);

if (need_hotplug)
drm_kms_helper_hotplug_event(dev);
1539}

1541static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
1542{
struct smu_context *smu = &adev->smu;
int ret = 0;

if (!is_support_sw_smu(adev))
return 0;

/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
* on window driver dc implementation.
* For Navi1x, clock settings of dcn watermarks are fixed. the settings
* should be passed to smu during boot up and resume from s3.
* boot up: dc calculate dcn watermark clock settings within dc_create,
* dcn20_resource_construct
* then call pplib functions below to pass the settings to smu:
* smu_set_watermarks_for_clock_ranges
* smu_set_watermarks_table
* navi10_set_watermarks_table
* smu_write_watermarks_table
*
* For Renoir, clock settings of dcn watermark are also fixed values.
* dc has implemented different flow for window driver:
* dc_hardware_init / dc_set_power_state
* dcn10_init_hw
* notify_wm_ranges
* set_wm_ranges
* -- Linux
* smu_set_watermarks_for_clock_ranges
* renoir_set_watermarks_table
* smu_write_watermarks_table
*
* For Linux,
* dc_hardware_init -> amdgpu_dm_init
* dc_set_power_state --> dm_resume
*
* therefore, this function apply to navi10/12/14 but not Renoir
* *
*/
switch(adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
break;
default:
return 0;
}

ret = smu_write_watermarks_table(smu);
if (ret) {
DRM_ERROR("Failed to update WMTABLE!\n")__drm_err("Failed to update WMTABLE!\n");
return ret;
}

return 0;
1595}

1597/**
* dm_hw_init() - Initialize DC device
* @handle: The base driver device containing the amdgpu_dm device.
*
* Initialize the &struct amdgpu_display_manager device. This involves calling
* the initializers of each DM component, then populating the struct with them.
*
* Although the function implies hardware initialization, both hardware and
* software are initialized here. Splitting them out to their relevant init
* hooks is a future TODO item.
*
* Some notable things that are initialized here:
*
* - Display Core, both software and hardware
* - DC modules that we need (freesync and color management)
* - DRM software states
* - Interrupt sources and handlers
* - Vblank support
* - Debug FS entries, if enabled
*/
1617static int dm_hw_init(void *handle)
1618{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* Create DAL display manager */
amdgpu_dm_init(adev);
amdgpu_dm_hpd_init(adev);

return 0;
1625}

1627/**
* dm_hw_fini() - Teardown DC device
* @handle: The base driver device containing the amdgpu_dm device.
*
* Teardown components within &struct amdgpu_display_manager that require
* cleanup. This involves cleaning up the DRM device, DC, and any modules that
* were loaded. Also flush IRQ workqueues and disable them.
*/
1635static int dm_hw_fini(void *handle)
1636{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

amdgpu_dm_hpd_fini(adev);

amdgpu_dm_irq_fini(adev);
amdgpu_dm_fini(adev);
return 0;
1644}


1647static int dm_enable_vblank(struct drm_crtc *crtc);
1648static void dm_disable_vblank(struct drm_crtc *crtc);

1650static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
		 struct dc_state *state, bool_Bool enable)
1652{
enum dc_irq_source irq_source;
struct amdgpu_crtc *acrtc;
int rc = -EBUSY16;
int i = 0;

for (i = 0; i < state->stream_count; i++) {
acrtc = get_crtc_by_otg_inst(
		adev, state->stream_status[i].primary_otg_inst);

if (acrtc && state->stream_status[i].plane_count != 0) {
	irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY16;
	DRM_DEBUG("crtc %d - vupdate irq %sabling: r=%d\n",__drm_dbg(DRM_UT_CORE, "crtc %d - vupdate irq %sabling: r=%d\n"
, acrtc->crtc_id, enable ? "en" : "dis", rc)
		  acrtc->crtc_id, enable ? "en" : "dis", rc)__drm_dbg(DRM_UT_CORE, "crtc %d - vupdate irq %sabling: r=%d\n"
, acrtc->crtc_id, enable ? "en" : "dis", rc);
	if (rc)
		DRM_WARN("Failed to %s pflip interrupts\n",printk("\0014" "[" "drm" "] " "Failed to %s pflip interrupts\n"
, enable ? "enable" : "disable")
			 enable ? "enable" : "disable")printk("\0014" "[" "drm" "] " "Failed to %s pflip interrupts\n"
, enable ? "enable" : "disable");

	if (enable) {
		rc = dm_enable_vblank(&acrtc->base);
		if (rc)
			DRM_WARN("Failed to enable vblank interrupts\n")printk("\0014" "[" "drm" "] " "Failed to enable vblank interrupts\n"
);
	} else {
		dm_disable_vblank(&acrtc->base);
	}

}
}

1682}

1684static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
1685{
struct dc_state *context = NULL((void *)0);
enum dc_status res = DC_ERROR_UNEXPECTED;
int i;
struct dc_stream_state *del_streams[MAX_PIPES6];
int del_streams_count = 0;

memset(del_streams, 0, sizeof(del_streams))__builtin_memset((del_streams), (0), (sizeof(del_streams)));

context = dc_create_state(dc);
if (context == NULL((void *)0))
goto context_alloc_fail;

dc_resource_state_copy_construct_current(dc, context);

/* First remove from context all streams */
for (i = 0; i < context->stream_count; i++) {
struct dc_stream_state *stream = context->streams[i];

del_streams[del_streams_count++] = stream;
}

/* Remove all planes for removed streams and then remove the streams */
for (i = 0; i < del_streams_count; i++) {
if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
	res = DC_FAIL_DETACH_SURFACES;
	goto fail;
}

res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
if (res != DC_OK)
	goto fail;
}


res = dc_validate_global_state(dc, context, false0);

if (res != DC_OK) {
DRM_ERROR("%s:resource validation failed, dc_status:%d\n", __func__, res)__drm_err("%s:resource validation failed, dc_status:%d\n", __func__
, res);
goto fail;
}

res = dc_commit_state(dc, context);

1729fail:
dc_release_state(context);

1732context_alloc_fail:
return res;
1734}

1736static int dm_suspend(void *handle)
1737{
struct amdgpu_device *adev = handle;
struct amdgpu_display_manager *dm = &adev->dm;
int ret = 0;

if (amdgpu_in_reset(adev)) {
mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
dm->cached_dc_state = dc_copy_state(dm->dc->current_state);

dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false0);

amdgpu_dm_commit_zero_streams(dm->dc);

amdgpu_dm_irq_suspend(adev);

return ret;
}

WARN_ON(adev->dm.cached_state)({ int __ret = !!(adev->dm.cached_state); if (__ret) printf
("WARNING %s failed at %s:%d\n", "adev->dm.cached_state", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 1755); __builtin_expect(!!(__ret), 0); });
adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));

s3_handle_mst(adev_to_drm(adev), true1);

amdgpu_dm_irq_suspend(adev);

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);

return 0;
1765}

1767static struct amdgpu_dm_connector *
1768amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
			     struct drm_crtc *crtc)
1770{
uint32_t i;
struct drm_connector_state *new_con_state;
struct drm_connector *connector;
struct drm_crtc *crtc_from_state;

for_each_new_connector_in_state(state, connector, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (new_con_state) =
 (state)->connectors[i].new_state, (void)(new_con_state) ,
 1))) {} else {
crtc_from_state = new_con_state->crtc;

if (crtc_from_state == crtc)
	return to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
}

return NULL((void *)0);
1784}

1786static void emulated_link_detect(struct dc_link *link)
1787{
struct dc_sink_init_data sink_init_data = { 0 };
struct display_sink_capability sink_caps = { 0 };
enum dc_edid_status edid_status;
struct dc_context *dc_ctx = link->ctx;
struct dc_sink *sink = NULL((void *)0);
struct dc_sink *prev_sink = NULL((void *)0);

link->type = dc_connection_none;
prev_sink = link->local_sink;

if (prev_sink)
dc_sink_release(prev_sink);

switch (link->connector_signal) {
case SIGNAL_TYPE_HDMI_TYPE_A: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
break;
}

case SIGNAL_TYPE_DVI_SINGLE_LINK: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
}

case SIGNAL_TYPE_DVI_DUAL_LINK: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
break;
}

case SIGNAL_TYPE_LVDS: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_LVDS;
break;
}

case SIGNAL_TYPE_EDP: {
sink_caps.transaction_type =
	DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
sink_caps.signal = SIGNAL_TYPE_EDP;
break;
}

case SIGNAL_TYPE_DISPLAY_PORT: {
sink_caps.transaction_type =
	DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
break;
}

default:
DC_ERROR("Invalid connector type! signal:%d\n",do { (void)(dc_ctx); __drm_err("Invalid connector type! signal:%d\n"
, link->connector_signal); } while (0)
	link->connector_signal)do { (void)(dc_ctx); __drm_err("Invalid connector type! signal:%d\n"
, link->connector_signal); } while (0);
return;
}

sink_init_data.link = link;
sink_init_data.sink_signal = sink_caps.signal;

sink = dc_sink_create(&sink_init_data);
if (!sink) {
DC_ERROR("Failed to create sink!\n")do { (void)(dc_ctx); __drm_err("Failed to create sink!\n"); }
 while (0);
return;
}

/* dc_sink_create returns a new reference */
link->local_sink = sink;

edid_status = dm_helpers_read_local_edid(
	link->ctx,
	link,
	sink);

if (edid_status != EDID_OK)
DC_ERROR("Failed to read EDID")do { (void)(dc_ctx); __drm_err("Failed to read EDID"); } while
 (0);

1866}

1868static void dm_gpureset_commit_state(struct dc_state *dc_state,
		     struct amdgpu_display_manager *dm)
1870{
struct {
struct dc_surface_update surface_updates[MAX_SURFACES3];
struct dc_plane_info plane_infos[MAX_SURFACES3];
struct dc_scaling_info scaling_infos[MAX_SURFACES3];
struct dc_flip_addrs flip_addrs[MAX_SURFACES3];
struct dc_stream_update stream_update;
} * bundle;
int k, m;

bundle = kzalloc(sizeof(*bundle), GFP_KERNEL(0x0001 | 0x0004));

if (!bundle) {
dm_error("Failed to allocate update bundle\n")__drm_err("Failed to allocate update bundle\n");
goto cleanup;
}

for (k = 0; k < dc_state->stream_count; k++) {
bundle->stream_update.stream = dc_state->streams[k];

for (m = 0; m < dc_state->stream_status->plane_count; m++) {
	bundle->surface_updates[m].surface =
		dc_state->stream_status->plane_states[m];
	bundle->surface_updates[m].surface->force_full_update =
		true1;
}
dc_commit_updates_for_stream(
	dm->dc, bundle->surface_updates,
	dc_state->stream_status->plane_count,
	dc_state->streams[k], &bundle->stream_update, dc_state);
}

1902cleanup:
kfree(bundle);

return;
1906}

1908static void dm_set_dpms_off(struct dc_link *link)
1909{
struct dc_stream_state *stream_state;
struct amdgpu_dm_connector *aconnector = link->priv;
struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
struct dc_stream_update stream_update;
bool_Bool dpms_off = true1;

memset(&stream_update, 0, sizeof(stream_update))__builtin_memset((&stream_update), (0), (sizeof(stream_update
)));
stream_update.dpms_off = &dpms_off;

mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock);
stream_state = dc_stream_find_from_link(link);

if (stream_state == NULL((void *)0)) {
DRM_DEBUG_DRIVER("Error finding stream state associated with link!\n")__drm_dbg(DRM_UT_DRIVER, "Error finding stream state associated with link!\n"
);
mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);
return;
}

stream_update.stream = stream_state;
dc_commit_updates_for_stream(stream_state->ctx->dc, NULL((void *)0), 0,
		     stream_state, &stream_update,
		     stream_state->ctx->dc->current_state);
mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);
1933}

1935static int dm_resume(void *handle)
1936{
struct amdgpu_device *adev = handle;
struct drm_device *ddev = adev_to_drm(adev);
struct amdgpu_display_manager *dm = &adev->dm;
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
struct drm_crtc *crtc;
struct drm_crtc_state *new_crtc_state;
struct dm_crtc_state *dm_new_crtc_state;
struct drm_plane *plane;
struct drm_plane_state *new_plane_state;
struct dm_plane_state *dm_new_plane_state;
struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (dm->atomic_obj.state); (struct dm_atomic_state *
)( (char *)__mptr - __builtin_offsetof(struct dm_atomic_state
, base) );});
enum dc_connection_type new_connection_type = dc_connection_none;
struct dc_state *dc_state;
int i, r, j;

if (amdgpu_in_reset(adev)) {
dc_state = dm->cached_dc_state;

r = dm_dmub_hw_init(adev);
if (r)
	DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r)__drm_err("DMUB interface failed to initialize: status=%d\n",
 r);

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
dc_resume(dm->dc);

amdgpu_dm_irq_resume_early(adev);

for (i = 0; i < dc_state->stream_count; i++) {
	dc_state->streams[i]->mode_changed = true1;
	for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
		dc_state->stream_status[i].plane_states[j]->update_flags.raw
			= 0xffffffff;
	}
}

WARN_ON(!dc_commit_state(dm->dc, dc_state))({ int __ret = !!(!dc_commit_state(dm->dc, dc_state)); if (
__ret) printf("WARNING %s failed at %s:%d\n", "!dc_commit_state(dm->dc, dc_state)"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 1974); __builtin_expect(!!(__ret), 0); });

dm_gpureset_commit_state(dm->cached_dc_state, dm);

dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true1);

dc_release_state(dm->cached_dc_state);
dm->cached_dc_state = NULL((void *)0);

amdgpu_dm_irq_resume_late(adev);

mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);

return 0;
}
/* Recreate dc_state - DC invalidates it when setting power state to S3. */
dc_release_state(dm_state->context);
dm_state->context = dc_create_state(dm->dc);
/* TODO: Remove dc_state->dccg, use dc->dccg directly. */
dc_resource_state_construct(dm->dc, dm_state->context);

/* Before powering on DC we need to re-initialize DMUB. */
r = dm_dmub_hw_init(adev);
if (r)
DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r)__drm_err("DMUB interface failed to initialize: status=%d\n",
 r);

/* power on hardware */
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

/* program HPD filter */
dc_resume(dm->dc);

/*
* early enable HPD Rx IRQ, should be done before set mode as short
* pulse interrupts are used for MST
*/
amdgpu_dm_irq_resume_early(adev);

/* On resume we need to rewrite the MSTM control bits to enable MST*/
s3_handle_mst(ddev, false0);

/* Do detection*/
drm_connector_list_iter_begin(ddev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

/*
 * this is the case when traversing through already created
 * MST connectors, should be skipped
 */
if (aconnector->mst_port)
	continue;

mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock);
if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
	DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");

if (aconnector->base.force && new_connection_type == dc_connection_none)
	emulated_link_detect(aconnector->dc_link);
else
	dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);

if (aconnector->fake_enable && aconnector->dc_link->local_sink)
	aconnector->fake_enable = false0;

if (aconnector->dc_sink)
	dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL((void *)0);
amdgpu_dm_update_connector_after_detect(aconnector);
mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock);
}
drm_connector_list_iter_end(&iter);

/* Force mode set in atomic commit */
for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config
.num_crtc; (i)++) if (!((dm->cached_state)->crtcs[i].ptr
 && ((crtc) = (dm->cached_state)->crtcs[i].ptr,
 (void)(crtc) , (new_crtc_state) = (dm->cached_state)->
crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else
new_crtc_state->active_changed = true1;

/*
* atomic_check is expected to create the dc states. We need to release
* them here, since they were duplicated as part of the suspend
* procedure.
*/
for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config
.num_crtc; (i)++) if (!((dm->cached_state)->crtcs[i].ptr
 && ((crtc) = (dm->cached_state)->crtcs[i].ptr,
 (void)(crtc) , (new_crtc_state) = (dm->cached_state)->
crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
if (dm_new_crtc_state->stream) {
	WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1)({ int __ret = !!(kref_read(&dm_new_crtc_state->stream
->refcount) > 1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "kref_read(&dm_new_crtc_state->stream->refcount) > 1"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 2059); __builtin_expect(!!(__ret), 0); });
	dc_stream_release(dm_new_crtc_state->stream);
	dm_new_crtc_state->stream = NULL((void *)0);
}
}

for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config
.num_total_plane; (i)++) if (!((dm->cached_state)->planes
[i].ptr && ((plane) = (dm->cached_state)->planes
[i].ptr, (void)(plane) , (new_plane_state) = (dm->cached_state
)->planes[i].new_state, (void)(new_plane_state) , 1))) {} else {
dm_new_plane_state = to_dm_plane_state(new_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});
if (dm_new_plane_state->dc_state) {
	WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1)({ int __ret = !!(kref_read(&dm_new_plane_state->dc_state
->refcount) > 1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "kref_read(&dm_new_plane_state->dc_state->refcount) > 1"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 2068); __builtin_expect(!!(__ret), 0); });
	dc_plane_state_release(dm_new_plane_state->dc_state);
	dm_new_plane_state->dc_state = NULL((void *)0);
}
}

drm_atomic_helper_resume(ddev, dm->cached_state);

dm->cached_state = NULL((void *)0);

amdgpu_dm_irq_resume_late(adev);

amdgpu_dm_smu_write_watermarks_table(adev);

return 0;
2083}

2085/**
* DOC: DM Lifecycle
*
* DM (and consequently DC) is registered in the amdgpu base driver as a IP
* block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
* the base driver's device list to be initialized and torn down accordingly.
*
* The functions to do so are provided as hooks in &struct amd_ip_funcs.
*/

2095static const struct amd_ip_funcs amdgpu_dm_funcs = {
.name = "dm",
.early_init = dm_early_init,
.late_init = dm_late_init,
.sw_init = dm_sw_init,
.sw_fini = dm_sw_fini,
.hw_init = dm_hw_init,
.hw_fini = dm_hw_fini,
.suspend = dm_suspend,
.resume = dm_resume,
.is_idle = dm_is_idle,
.wait_for_idle = dm_wait_for_idle,
.check_soft_reset = dm_check_soft_reset,
.soft_reset = dm_soft_reset,
.set_clockgating_state = dm_set_clockgating_state,
.set_powergating_state = dm_set_powergating_state,
2111};

2113const struct amdgpu_ip_block_version dm_ip_block =
2114{
.type = AMD_IP_BLOCK_TYPE_DCE,
.major = 1,
.minor = 0,
.rev = 0,
.funcs = &amdgpu_dm_funcs,
2120};


2123/**
* DOC: atomic
*
* *WIP*
*/

2129static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_display_user_framebuffer_create,
.output_poll_changed = drm_fb_helper_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
.atomic_commit = amdgpu_dm_atomic_commit,
2134};

2136static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
.atomic_commit_tail = amdgpu_dm_atomic_commit_tail
2138};

2140static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2141{
u32 max_cll, min_cll, max, min, q, r;
struct amdgpu_dm_backlight_caps *caps;
struct amdgpu_display_manager *dm;
struct drm_connector *conn_base;
struct amdgpu_device *adev;
struct dc_link *link = NULL((void *)0);
static const u8 pre_computed_values[] = {
50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98};

if (!aconnector || !aconnector->dc_link)
return;

link = aconnector->dc_link;
if (link->connector_signal != SIGNAL_TYPE_EDP)
return;

conn_base = &aconnector->base;
adev = drm_to_adev(conn_base->dev);
dm = &adev->dm;
caps = &dm->backlight_caps;
caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
caps->aux_support = false0;
max_cll = conn_base->hdr_sink_metadata.hdmi_type1.max_cll;
min_cll = conn_base->hdr_sink_metadata.hdmi_type1.min_cll;

if (caps->ext_caps->bits.oled == 1 /*||
   caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
   caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
caps->aux_support = true1;

if (amdgpu_backlight == 0)
caps->aux_support = false0;
else if (amdgpu_backlight == 1)
caps->aux_support = true1;

/* From the specification (CTA-861-G), for calculating the maximum
* luminance we need to use:
*	Luminance = 50*2**(CV/32)
* Where CV is a one-byte value.
* For calculating this expression we may need float point precision;
* to avoid this complexity level, we take advantage that CV is divided
* by a constant. From the Euclids division algorithm, we know that CV
* can be written as: CV = 32*q + r. Next, we replace CV in the
* Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
* need to pre-compute the value of r/32. For pre-computing the values
* We just used the following Ruby line:
*	(0...32).each {|cv| puts (50*2**(cv/32.0)).round}
* The results of the above expressions can be verified at
* pre_computed_values.
*/
q = max_cll >> 5;
r = max_cll % 32;
max = (1 << q) * pre_computed_values[r];

// min luminance: maxLum * (CV/255)^2 / 100
q = DIV_ROUND_CLOSEST(min_cll, 255)(((min_cll) + ((255) / 2)) / (255));
min = max * DIV_ROUND_CLOSEST((q * q), 100)((((q * q)) + ((100) / 2)) / (100));

caps->aux_max_input_signal = max;
caps->aux_min_input_signal = min;
2203}

2205void amdgpu_dm_update_connector_after_detect(
struct amdgpu_dm_connector *aconnector)
2207{
struct drm_connector *connector = &aconnector->base;
struct drm_device *dev = connector->dev;
struct dc_sink *sink;

/* MST handled by drm_mst framework */
if (aconnector->mst_mgr.mst_state == true1)
return;

sink = aconnector->dc_link->local_sink;
if (sink)
dc_sink_retain(sink);

/*
* Edid mgmt connector gets first update only in mode_valid hook and then
* the connector sink is set to either fake or physical sink depends on link status.
* Skip if already done during boot.
*/
if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
	&& aconnector->dc_em_sink) {

/*
 * For S3 resume with headless use eml_sink to fake stream
 * because on resume connector->sink is set to NULL
 */
mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex);

if (sink) {
	if (aconnector->dc_sink) {
		amdgpu_dm_update_freesync_caps(connector, NULL((void *)0));
		/*
		 * retain and release below are used to
		 * bump up refcount for sink because the link doesn't point
		 * to it anymore after disconnect, so on next crtc to connector
		 * reshuffle by UMD we will get into unwanted dc_sink release
		 */
		dc_sink_release(aconnector->dc_sink);
	}
	aconnector->dc_sink = sink;
	dc_sink_retain(aconnector->dc_sink);
	amdgpu_dm_update_freesync_caps(connector,
			aconnector->edid);
} else {
	amdgpu_dm_update_freesync_caps(connector, NULL((void *)0));
	if (!aconnector->dc_sink) {
		aconnector->dc_sink = aconnector->dc_em_sink;
		dc_sink_retain(aconnector->dc_sink);
	}
}

mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex);

if (sink)
	dc_sink_release(sink);
return;
}

/*
* TODO: temporary guard to look for proper fix
* if this sink is MST sink, we should not do anything
*/
if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
dc_sink_release(sink);
return;
}

if (aconnector->dc_sink == sink) {
/*
 * We got a DP short pulse (Link Loss, DP CTS, etc...).
 * Do nothing!!
 */
DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",__drm_dbg(DRM_UT_DRIVER, "DCHPD: connector_id=%d: dc_sink didn't change.\n"
, aconnector->connector_id)
		aconnector->connector_id)__drm_dbg(DRM_UT_DRIVER, "DCHPD: connector_id=%d: dc_sink didn't change.\n"
, aconnector->connector_id);
if (sink)
	dc_sink_release(sink);
return;
}

DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",__drm_dbg(DRM_UT_DRIVER, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n"
, aconnector->connector_id, aconnector->dc_sink, sink)
aconnector->connector_id, aconnector->dc_sink, sink)__drm_dbg(DRM_UT_DRIVER, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n"
, aconnector->connector_id, aconnector->dc_sink, sink);

mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex);

/*
* 1. Update status of the drm connector
* 2. Send an event and let userspace tell us what to do
*/
if (sink) {
/*
 * TODO: check if we still need the S3 mode update workaround.
 * If yes, put it here.
 */
if (aconnector->dc_sink) {
	amdgpu_dm_update_freesync_caps(connector, NULL((void *)0));
	dc_sink_release(aconnector->dc_sink);
}

aconnector->dc_sink = sink;
dc_sink_retain(aconnector->dc_sink);
if (sink->dc_edid.length == 0) {
	aconnector->edid = NULL((void *)0);
	if (aconnector->dc_link->aux_mode) {
		drm_dp_cec_unset_edid(
			&aconnector->dm_dp_aux.aux);
	}
} else {
	aconnector->edid =
		(struct edid *)sink->dc_edid.raw_edid;

	drm_connector_update_edid_property(connector,
					   aconnector->edid);
	if (aconnector->dc_link->aux_mode)
		drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
				    aconnector->edid);
}

amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
update_connector_ext_caps(aconnector);
} else {
drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
amdgpu_dm_update_freesync_caps(connector, NULL((void *)0));
drm_connector_update_edid_property(connector, NULL((void *)0));
aconnector->num_modes = 0;
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL((void *)0);
aconnector->edid = NULL((void *)0);
2333#ifdef CONFIG_DRM_AMD_DC_HDCP
/* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2)
	connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;
2337#endif
}

mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex);

update_subconnector_property(aconnector);

if (sink)
dc_sink_release(sink);
2346}

2348static void handle_hpd_irq(void *param)
2349{
struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
struct drm_connector *connector = &aconnector->base;
struct drm_device *dev = connector->dev;
enum dc_connection_type new_connection_type = dc_connection_none;
2354#ifdef CONFIG_DRM_AMD_DC_HDCP
struct amdgpu_device *adev = drm_to_adev(dev);
2356#endif

/*
* In case of failure or MST no need to update connector status or notify the OS
* since (for MST case) MST does this in its own context.
*/
mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock);

2364#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.hdcp_workqueue)
hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
2367#endif
if (aconnector->fake_enable)
aconnector->fake_enable = false0;

if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");

if (aconnector->base.force && new_connection_type == dc_connection_none) {
emulated_link_detect(aconnector->dc_link);


drm_modeset_lock_all(dev);
dm_restore_drm_connector_state(dev, connector);
drm_modeset_unlock_all(dev);

if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
	drm_kms_helper_hotplug_event(dev);

} else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
if (new_connection_type == dc_connection_none &&
    aconnector->dc_link->type == dc_connection_none)
	dm_set_dpms_off(aconnector->dc_link);

amdgpu_dm_update_connector_after_detect(aconnector);

drm_modeset_lock_all(dev);
dm_restore_drm_connector_state(dev, connector);
drm_modeset_unlock_all(dev);

if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
	drm_kms_helper_hotplug_event(dev);
}
mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock);

2401}

2403static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
2404{
uint8_t esi[DP_PSR_ERROR_STATUS0x2006 - DP_SINK_COUNT_ESI0x2002] = { 0 };
uint8_t dret;
bool_Bool new_irq_handled = false0;
int dpcd_addr;
int dpcd_bytes_to_read;

const int max_process_count = 30;
int process_count = 0;

const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);

if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
dpcd_bytes_to_read = DP_LANE0_1_STATUS0x202 - DP_SINK_COUNT0x200;
/* DPCD 0x200 - 0x201 for downstream IRQ */
dpcd_addr = DP_SINK_COUNT0x200;
} else {
dpcd_bytes_to_read = DP_PSR_ERROR_STATUS0x2006 - DP_SINK_COUNT_ESI0x2002;
/* DPCD 0x2002 - 0x2005 for downstream IRQ */
dpcd_addr = DP_SINK_COUNT_ESI0x2002;
}

dret = drm_dp_dpcd_read(
&aconnector->dm_dp_aux.aux,
dpcd_addr,
esi,
dpcd_bytes_to_read);

while (dret == dpcd_bytes_to_read &&
process_count < max_process_count) {
uint8_t retry;
dret = 0;

process_count++;

DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2])__drm_dbg(DRM_UT_DRIVER, "ESI %02x %02x %02x\n", esi[0], esi[
1], esi[2]);
/* handle HPD short pulse irq */
if (aconnector->mst_mgr.mst_state)
	drm_dp_mst_hpd_irq(
		&aconnector->mst_mgr,
		esi,
		&new_irq_handled);

if (new_irq_handled) {
	/* ACK at DPCD to notify down stream */
	const int ack_dpcd_bytes_to_write =
		dpcd_bytes_to_read - 1;

	for (retry = 0; retry < 3; retry++) {
		uint8_t wret;

		wret = drm_dp_dpcd_write(
			&aconnector->dm_dp_aux.aux,
			dpcd_addr + 1,
			&esi[1],
			ack_dpcd_bytes_to_write);
		if (wret == ack_dpcd_bytes_to_write)
			break;
	}

	/* check if there is new irq to be handled */
	dret = drm_dp_dpcd_read(
		&aconnector->dm_dp_aux.aux,
		dpcd_addr,
		esi,
		dpcd_bytes_to_read);

	new_irq_handled = false0;
} else {
	break;
}
}

if (process_count == max_process_count)
DRM_DEBUG_DRIVER("Loop exceeded max iterations\n")__drm_dbg(DRM_UT_DRIVER, "Loop exceeded max iterations\n");
2479}

2481static void handle_hpd_rx_irq(void *param)
2482{
struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
struct drm_connector *connector = &aconnector->base;
struct drm_device *dev = connector->dev;
struct dc_link *dc_link = aconnector->dc_link;
bool_Bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
enum dc_connection_type new_connection_type = dc_connection_none;
2489#ifdef CONFIG_DRM_AMD_DC_HDCP
union hpd_irq_data hpd_irq_data;
struct amdgpu_device *adev = drm_to_adev(dev);

memset(&hpd_irq_data, 0, sizeof(hpd_irq_data))__builtin_memset((&hpd_irq_data), (0), (sizeof(hpd_irq_data
)));
2494#endif

/*
* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
* conflict, after implement i2c helper, this mutex should be
* retired.
*/
if (dc_link->type != dc_connection_mst_branch)
mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock);


2505#ifdef CONFIG_DRM_AMD_DC_HDCP
if (dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data, NULL((void *)0)) &&
2507#else
if (dc_link_handle_hpd_rx_irq(dc_link, NULL((void *)0), NULL((void *)0)) &&
2509#endif
	!is_mst_root_connector) {
/* Downstream Port status changed. */
if (!dc_link_detect_sink(dc_link, &new_connection_type))
	DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");

if (aconnector->base.force && new_connection_type == dc_connection_none) {
	emulated_link_detect(dc_link);

	if (aconnector->fake_enable)
		aconnector->fake_enable = false0;

	amdgpu_dm_update_connector_after_detect(aconnector);


	drm_modeset_lock_all(dev);
	dm_restore_drm_connector_state(dev, connector);
	drm_modeset_unlock_all(dev);

	drm_kms_helper_hotplug_event(dev);
} else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {

	if (aconnector->fake_enable)
		aconnector->fake_enable = false0;

	amdgpu_dm_update_connector_after_detect(aconnector);


	drm_modeset_lock_all(dev);
	dm_restore_drm_connector_state(dev, connector);
	drm_modeset_unlock_all(dev);

	drm_kms_helper_hotplug_event(dev);
}
}
2544#ifdef CONFIG_DRM_AMD_DC_HDCP
if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
if (adev->dm.hdcp_workqueue)
	hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
}
2549#endif
if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
   (dc_link->type == dc_connection_mst_branch))
dm_handle_hpd_rx_irq(aconnector);

if (dc_link->type != dc_connection_mst_branch) {
drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock);
}
2558}

2560static void register_hpd_handlers(struct amdgpu_device *adev)
2561{
struct drm_device *dev = adev_to_drm(adev);
struct drm_connector *connector;
struct amdgpu_dm_connector *aconnector;
const struct dc_link *dc_link;
struct dc_interrupt_params int_params = {0};

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

list_for_each_entry(connector,for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
 (&dev->mode_config.connector_list); connector = ({ const
 __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*connector), head) );}))
	&dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
 (&dev->mode_config.connector_list); connector = ({ const
 __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*connector), head) );}))	{

aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
dc_link = aconnector->dc_link;

if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
	int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
	int_params.irq_source = dc_link->irq_source_hpd;

	amdgpu_dm_irq_register_interrupt(adev, &int_params,
			handle_hpd_irq,
			(void *) aconnector);
}

if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {

	/* Also register for DP short pulse (hpd_rx). */
	int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
	int_params.irq_source =	dc_link->irq_source_hpd_rx;

	amdgpu_dm_irq_register_interrupt(adev, &int_params,
			handle_hpd_rx_irq,
			(void *) aconnector);
}
}
2597}

2599#if defined(CONFIG_DRM_AMD_DC_SI)
2600/* Register IRQ sources and initialize IRQ callbacks */
2601static int dce60_register_irq_handlers(struct amdgpu_device *adev)
2602{
struct dc *dc = adev->dm.dc;
struct common_irq_params *c_irq_params;
struct dc_interrupt_params int_params = {0};
int r;
int i;
unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY0;

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

/*
* Actions of amdgpu_irq_add_id():
* 1. Register a set() function with base driver.
*    Base driver will call set() function to enable/disable an
*    interrupt in DC hardware.
* 2. Register amdgpu_dm_irq_handler().
*    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
*    coming from DC hardware.
*    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
*    for acknowledging and handling. */

/* Use VBLANK interrupt */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
if (r) {
	DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i+1 , 0);

c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_crtc_high_irq, c_irq_params);
}

/* Use GRPH_PFLIP interrupt */
for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8;
	i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP18; i += 2) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
if (r) {
	DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_pflip_high_irq, c_irq_params);

}

/* HPD */
r = amdgpu_irq_add_id(adev, client_id,
	VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq);
if (r) {
DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n");
return r;
}

register_hpd_handlers(adev);

return 0;
2679}
2680#endif

2682/* Register IRQ sources and initialize IRQ callbacks */
2683static int dce110_register_irq_handlers(struct amdgpu_device *adev)
2684{
struct dc *dc = adev->dm.dc;
struct common_irq_params *c_irq_params;
struct dc_interrupt_params int_params = {0};
int r;
int i;
unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY0;

if (adev->asic_type >= CHIP_VEGA10)
client_id = SOC15_IH_CLIENTID_DCE;

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

/*
* Actions of amdgpu_irq_add_id():
* 1. Register a set() function with base driver.
*    Base driver will call set() function to enable/disable an
*    interrupt in DC hardware.
* 2. Register amdgpu_dm_irq_handler().
*    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
*    coming from DC hardware.
*    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
*    for acknowledging and handling. */

/* Use VBLANK interrupt */
for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT019; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT024; i++) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
if (r) {
	DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_crtc_high_irq, c_irq_params);
}

/* Use VUPDATE interrupt */
for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT7; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT17; i += 2) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
if (r) {
	DRM_ERROR("Failed to add vupdate irq id!\n")__drm_err("Failed to add vupdate irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_vupdate_high_irq, c_irq_params);
}

/* Use GRPH_PFLIP interrupt */
for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8;
	i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP18; i += 2) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
if (r) {
	DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_pflip_high_irq, c_irq_params);

}

/* HPD */
r = amdgpu_irq_add_id(adev, client_id,
	VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq);
if (r) {
DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n");
return r;
}

register_hpd_handlers(adev);

return 0;
2785}

2787#if defined(CONFIG_DRM_AMD_DC_DCN1)
2788/* Register IRQ sources and initialize IRQ callbacks */
2789static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
2790{
struct dc *dc = adev->dm.dc;
struct common_irq_params *c_irq_params;
struct dc_interrupt_params int_params = {0};
int r;
int i;

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

/*
* Actions of amdgpu_irq_add_id():
* 1. Register a set() function with base driver.
*    Base driver will call set() function to enable/disable an
*    interrupt in DC hardware.
* 2. Register amdgpu_dm_irq_handler().
*    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
*    coming from DC hardware.
*    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
*    for acknowledging and handling.
*/

/* Use VSTARTUP interrupt */
for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP0x3C;
	i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP0x3C + adev->mode_info.num_crtc - 1;
	i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);

if (r) {
	DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(
	adev, &int_params, dm_crtc_high_irq, c_irq_params);
}

/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
* the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
* to trigger at end of each vblank, regardless of state of the lock,
* matching DCE behaviour.
*/
for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT0x57;
    i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT0x57 + adev->mode_info.num_crtc - 1;
    i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);

if (r) {
	DRM_ERROR("Failed to add vupdate irq id!\n")__drm_err("Failed to add vupdate irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_vupdate_high_irq, c_irq_params);
}

/* Use GRPH_PFLIP interrupt */
for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT0x4F;
	i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT0x4F + adev->mode_info.num_crtc - 1;
	i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
if (r) {
	DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_pflip_high_irq, c_irq_params);

}

/* HPD */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT9,
	&adev->hpd_irq);
if (r) {
DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n");
return r;
}

register_hpd_handlers(adev);

return 0;
2899}
2900#endif

2902/*
* Acquires the lock for the atomic state object and returns
* the new atomic state.
*
* This should only be called during atomic check.
*/
2908static int dm_atomic_get_state(struct drm_atomic_state *state,
	       struct dm_atomic_state **dm_state)
2910{
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_display_manager *dm = &adev->dm;
struct drm_private_state *priv_state;

if (*dm_state)
return 0;

priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
if (IS_ERR(priv_state))
return PTR_ERR(priv_state);

*dm_state = to_dm_atomic_state(priv_state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (priv_state); (struct dm_atomic_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_atomic_state, base) );});

return 0;
2926}

2928static struct dm_atomic_state *
2929dm_atomic_get_new_state(struct drm_atomic_state *state)
2930{
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_display_manager *dm = &adev->dm;
struct drm_private_obj *obj;
struct drm_private_state *new_obj_state;
int i;

for_each_new_private_obj_in_state(state, obj, new_obj_state, i)for ((i) = 0; (i) < (state)->num_private_objs &&
 ((obj) = (state)->private_objs[i].ptr, (new_obj_state) = (
state)->private_objs[i].new_state, 1); (i)++) {
if (obj->funcs == dm->atomic_obj.funcs)
	return to_dm_atomic_state(new_obj_state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (new_obj_state); (struct dm_atomic_state *)( (char *
)__mptr - __builtin_offsetof(struct dm_atomic_state, base) );
});
}

return NULL((void *)0);
2944}

2946static struct drm_private_state *
2947dm_atomic_duplicate_state(struct drm_private_obj *obj)
2948{
struct dm_atomic_state *old_state, *new_state;

new_state = kzalloc(sizeof(*new_state), GFP_KERNEL(0x0001 | 0x0004));
if (!new_state)
return NULL((void *)0);

__drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);

old_state = to_dm_atomic_state(obj->state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (obj->state); (struct dm_atomic_state *)( (char *
)__mptr - __builtin_offsetof(struct dm_atomic_state, base) );
});

if (old_state && old_state->context)
new_state->context = dc_copy_state(old_state->context);

if (!new_state->context) {
kfree(new_state);
return NULL((void *)0);
}

return &new_state->base;
2968}

2970static void dm_atomic_destroy_state(struct drm_private_obj *obj,
		    struct drm_private_state *state)
2972{
struct dm_atomic_state *dm_state = to_dm_atomic_state(state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (state); (struct dm_atomic_state *)( (char *)__mptr -
 __builtin_offsetof(struct dm_atomic_state, base) );});

if (dm_state && dm_state->context)
dc_release_state(dm_state->context);

kfree(dm_state);
2979}

2981static struct drm_private_state_funcs dm_atomic_state_funcs = {
.atomic_duplicate_state = dm_atomic_duplicate_state,
.atomic_destroy_state = dm_atomic_destroy_state,
2984};

2986static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
2987{
struct dm_atomic_state *state;
int r;

adev->mode_info.mode_config_initialized = true1;

adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;

adev_to_drm(adev)->mode_config.max_width = 16384;
adev_to_drm(adev)->mode_config.max_height = 16384;

adev_to_drm(adev)->mode_config.preferred_depth = 24;
adev_to_drm(adev)->mode_config.prefer_shadow = 1;
/* indicates support for immediate flip */
adev_to_drm(adev)->mode_config.async_page_flip = true1;

adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;

state = kzalloc(sizeof(*state), GFP_KERNEL(0x0001 | 0x0004));
if (!state)
return -ENOMEM12;

state->context = dc_create_state(adev->dm.dc);
if (!state->context) {
kfree(state);
return -ENOMEM12;
}

dc_resource_state_copy_construct_current(adev->dm.dc, state->context);

drm_atomic_private_obj_init(adev_to_drm(adev),
		    &adev->dm.atomic_obj,
		    &state->base,
		    &dm_atomic_state_funcs);

r = amdgpu_display_modeset_create_props(adev);
if (r) {
dc_release_state(state->context);
kfree(state);
return r;
}

r = amdgpu_dm_audio_init(adev);
if (r) {
dc_release_state(state->context);
kfree(state);
return r;
}

return 0;
3038}

3040#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12 12
3041#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255 255
3042#define AUX_BL_DEFAULT_TRANSITION_TIME_MS50 50

3044#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE1) ||\
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

3047static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
3048{
3049#if defined(CONFIG_ACPI1)
struct amdgpu_dm_backlight_caps caps;

memset(&caps, 0, sizeof(caps))__builtin_memset((&caps), (0), (sizeof(caps)));

if (dm->backlight_caps.caps_valid)
return;

amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
if (caps.caps_valid) {
dm->backlight_caps.caps_valid = true1;
if (caps.aux_support)
	return;
dm->backlight_caps.min_input_signal = caps.min_input_signal;
dm->backlight_caps.max_input_signal = caps.max_input_signal;
} else {
dm->backlight_caps.min_input_signal =
		AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12;
dm->backlight_caps.max_input_signal =
		AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255;
}
3070#else
if (dm->backlight_caps.aux_support)
return;

dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12;
dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255;
3076#endif
3077}

3079static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
		unsigned *min, unsigned *max)
3081{
if (!caps)
return 0;

if (caps->aux_support) {
// Firmware limits are in nits, DC API wants millinits.
*max = 1000 * caps->aux_max_input_signal;
*min = 1000 * caps->aux_min_input_signal;
} else {
// Firmware limits are 8-bit, PWM control is 16-bit.
*max = 0x101 * caps->max_input_signal;
*min = 0x101 * caps->min_input_signal;
}
return 1;
3095}

3097static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
			uint32_t brightness)
3099{
unsigned min, max;

if (!get_brightness_range(caps, &min, &max))
return brightness;

// Rescale 0..255 to min..max
return min + DIV_ROUND_CLOSEST((max - min) * brightness,((((max - min) * brightness) + ((0xFF) / 2)) / (0xFF))
		       AMDGPU_MAX_BL_LEVEL)((((max - min) * brightness) + ((0xFF) / 2)) / (0xFF));
3108}

3110static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
		      uint32_t brightness)
3112{
unsigned min, max;

if (!get_brightness_range(caps, &min, &max))
return brightness;

if (brightness < min)
return 0;
// Rescale min..max to 0..255
return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),(((0xFF * (brightness - min)) + ((max - min) / 2)) / (max - min
))
		 max - min)(((0xFF * (brightness - min)) + ((max - min) / 2)) / (max - min
));
3123}

3125static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
3126{
struct amdgpu_display_manager *dm = bl_get_data(bd)(bd)->data;
struct amdgpu_dm_backlight_caps caps;
struct dc_link *link = NULL((void *)0);
u32 brightness;
bool_Bool rc;

amdgpu_dm_update_backlight_caps(dm);
caps = dm->backlight_caps;

link = (struct dc_link *)dm->backlight_link;

brightness = convert_brightness_from_user(&caps, bd->props.brightness);
// Change brightness based on AUX property
if (caps.aux_support)
rc = dc_link_set_backlight_level_nits(link, true1, brightness,
				      AUX_BL_DEFAULT_TRANSITION_TIME_MS50);
else
rc = dc_link_set_backlight_level(dm->backlight_link, brightness, 0);

return rc ? 0 : 1;
3147}

3149static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
3150{
struct amdgpu_display_manager *dm = bl_get_data(bd)(bd)->data;
struct amdgpu_dm_backlight_caps caps;

amdgpu_dm_update_backlight_caps(dm);
caps = dm->backlight_caps;

if (caps.aux_support) {
struct dc_link *link = (struct dc_link *)dm->backlight_link;
u32 avg, peak;
bool_Bool rc;

rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
if (!rc)
	return bd->props.brightness;
return convert_brightness_to_user(&caps, avg);
} else {
int ret = dc_link_get_backlight_level(dm->backlight_link);

if (ret == DC_ERROR_UNEXPECTED)
	return bd->props.brightness;
return convert_brightness_to_user(&caps, ret);
}
3173}

3175static const struct backlight_ops amdgpu_dm_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME1,
.get_brightness = amdgpu_dm_backlight_get_brightness,
.update_status	= amdgpu_dm_backlight_update_status,
3179};

3181static void
3182amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
3183{
char bl_name[16];
struct backlight_properties props = { 0 };

amdgpu_dm_update_backlight_caps(dm);

props.max_brightness = AMDGPU_MAX_BL_LEVEL0xFF;
props.brightness = AMDGPU_MAX_BL_LEVEL0xFF;
props.type = BACKLIGHT_RAW0;

snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
 adev_to_drm(dm->adev)->primary->index);

dm->backlight_dev = backlight_device_register(bl_name,
				      adev_to_drm(dm->adev)->dev,
				      dm,
				      &amdgpu_dm_backlight_ops,
				      &props);

if (IS_ERR(dm->backlight_dev))
DRM_ERROR("DM: Backlight registration failed!\n")__drm_err("DM: Backlight registration failed!\n");
else
DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name)__drm_dbg(DRM_UT_DRIVER, "DM: Registered Backlight device: %s\n"
, bl_name);
3206}

3208#endif

3210static int initialize_plane(struct amdgpu_display_manager *dm,
	    struct amdgpu_mode_info *mode_info, int plane_id,
	    enum drm_plane_type plane_type,
	    const struct dc_plane_cap *plane_cap)
3214{
struct drm_plane *plane;
unsigned long possible_crtcs;
int ret = 0;

plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL(0x0001 | 0x0004));
if (!plane) {
DRM_ERROR("KMS: Failed to allocate plane\n")__drm_err("KMS: Failed to allocate plane\n");
return -ENOMEM12;
}
plane->type = plane_type;

/*
* HACK: IGT tests expect that the primary plane for a CRTC
* can only have one possible CRTC. Only expose support for
* any CRTC if they're not going to be used as a primary plane
* for a CRTC - like overlay or underlay planes.
*/
possible_crtcs = 1 << plane_id;
if (plane_id >= dm->dc->caps.max_streams)
possible_crtcs = 0xff;

ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);

if (ret) {
DRM_ERROR("KMS: Failed to initialize plane\n")__drm_err("KMS: Failed to initialize plane\n");
kfree(plane);
return ret;
}

if (mode_info)
mode_info->planes[plane_id] = plane;

return ret;
3248}


3251static void register_backlight_device(struct amdgpu_display_manager *dm,
		      struct dc_link *link)
3253{
3254#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE1) ||\
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
   link->type != dc_connection_none) {
/*
 * Event if registration failed, we should continue with
 * DM initialization because not having a backlight control
 * is better then a black screen.
 */
amdgpu_dm_register_backlight_device(dm);

if (dm->backlight_dev)
	dm->backlight_link = link;
}
3269#endif
3270}


3273/*
* In this architecture, the association
* connector -> encoder -> crtc
* id not really requried. The crtc and connector will hold the
* display_index as an abstraction to use with DAL component
*
* Returns 0 on success
*/
3281static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
3282{
struct amdgpu_display_manager *dm = &adev->dm;
int32_t i;
struct amdgpu_dm_connector *aconnector = NULL((void *)0);
struct amdgpu_encoder *aencoder = NULL((void *)0);
struct amdgpu_mode_info *mode_info = &adev->mode_info;
uint32_t link_cnt;
int32_t primary_planes;
enum dc_connection_type new_connection_type = dc_connection_none;
const struct dc_plane_cap *plane;

dm->display_indexes_num = dm->dc->caps.max_streams;
/* Update the actual used number of crtc */
adev->mode_info.num_crtc = adev->dm.display_indexes_num;

link_cnt = dm->dc->caps.max_links;
if (amdgpu_dm_mode_config_init(dm->adev)) {
DRM_ERROR("DM: Failed to initialize mode config\n")__drm_err("DM: Failed to initialize mode config\n");
return -EINVAL22;
}

/* There is one primary plane per CRTC */
primary_planes = dm->dc->caps.max_streams;
ASSERT(primary_planes <= AMDGPU_MAX_PLANES)do { if (({ static int __warned; int __ret = !!(!(primary_planes
 <= 6)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(primary_planes <= 6)", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 3305); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);

/*
* Initialize primary planes, implicit planes for legacy IOCTLS.
* Order is reversed to match iteration order in atomic check.
*/
for (i = (primary_planes - 1); i >= 0; i--) {
plane = &dm->dc->caps.planes[i];

if (initialize_plane(dm, mode_info, i,
		     DRM_PLANE_TYPE_PRIMARY, plane)) {
	DRM_ERROR("KMS: Failed to initialize primary plane\n")__drm_err("KMS: Failed to initialize primary plane\n");
	goto fail;
}
}

/*
* Initialize overlay planes, index starting after primary planes.
* These planes have a higher DRM index than the primary planes since
* they should be considered as having a higher z-order.
* Order is reversed to match iteration order in atomic check.
*
* Only support DCN for now, and only expose one so we don't encourage
* userspace to use up all the pipes.
*/
for (i = 0; i < dm->dc->caps.max_planes; ++i) {
struct dc_plane_cap *plane = &dm->dc->caps.planes[i];

if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
	continue;

if (!plane->blends_with_above || !plane->blends_with_below)
	continue;

if (!plane->pixel_format_support.argb8888)
	continue;

if (initialize_plane(dm, NULL((void *)0), primary_planes + i,
		     DRM_PLANE_TYPE_OVERLAY, plane)) {
	DRM_ERROR("KMS: Failed to initialize overlay plane\n")__drm_err("KMS: Failed to initialize overlay plane\n");
	goto fail;
}

/* Only create one overlay plane. */
break;
}

for (i = 0; i < dm->dc->caps.max_streams; i++)
if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
	DRM_ERROR("KMS: Failed to initialize crtc\n")__drm_err("KMS: Failed to initialize crtc\n");
	goto fail;
}

/* loops over all connectors on the board */
for (i = 0; i < link_cnt; i++) {
struct dc_link *link = NULL((void *)0);

if (i > AMDGPU_DM_MAX_DISPLAY_INDEX31) {
	DRM_ERROR(__drm_err("KMS: Cannot support more than %d display indexes\n"
, 31)
		"KMS: Cannot support more than %d display indexes\n",__drm_err("KMS: Cannot support more than %d display indexes\n"
, 31)
			AMDGPU_DM_MAX_DISPLAY_INDEX)__drm_err("KMS: Cannot support more than %d display indexes\n"
, 31);
	continue;
}

aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL(0x0001 | 0x0004));
if (!aconnector)
	goto fail;

aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL(0x0001 | 0x0004));
if (!aencoder)
	goto fail;

if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
	DRM_ERROR("KMS: Failed to initialize encoder\n")__drm_err("KMS: Failed to initialize encoder\n");
	goto fail;
}

if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
	DRM_ERROR("KMS: Failed to initialize connector\n")__drm_err("KMS: Failed to initialize connector\n");
	goto fail;
}

link = dc_get_link_at_index(dm->dc, i);

if (!dc_link_detect_sink(link, &new_connection_type))
	DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");

if (aconnector->base.force && new_connection_type == dc_connection_none) {
	emulated_link_detect(link);
	amdgpu_dm_update_connector_after_detect(aconnector);

} else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
	amdgpu_dm_update_connector_after_detect(aconnector);
	register_backlight_device(dm, link);
	if (amdgpu_dc_feature_mask & DC_PSR_MASK)
		amdgpu_dm_set_psr_caps(link);
}


}

/* Software is initialized. Now we can register interrupt handlers. */
switch (adev->asic_type) {
3408#if defined(CONFIG_DRM_AMD_DC_SI)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
if (dce60_register_irq_handlers(dm->adev)) {
	DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n");
	goto fail;
}
break;
3418#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_TONGA:
case CHIP_FIJI:
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
case CHIP_VEGAM:
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
if (dce110_register_irq_handlers(dm->adev)) {
	DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n");
	goto fail;
}
break;
3440#if defined(CONFIG_DRM_AMD_DC_DCN1)
case CHIP_RAVEN:
case CHIP_NAVI12:
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_RENOIR:
3446#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
3449#endif
if (dcn10_register_irq_handlers(dm->adev)) {
	DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n");
	goto fail;
}
break;
3455#endif
default:
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type)__drm_err("Unsupported ASIC type: 0x%X\n", adev->asic_type
);
goto fail;
}

return 0;
3462fail:
kfree(aencoder);
kfree(aconnector);

return -EINVAL22;
3467}

3469static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
3470{
drm_mode_config_cleanup(dm->ddev);
drm_atomic_private_obj_fini(&dm->atomic_obj);
return;
3474}

3476/******************************************************************************
* amdgpu_display_funcs functions
*****************************************************************************/

3480/*
* dm_bandwidth_update - program display watermarks
*
* @adev: amdgpu_device pointer
*
* Calculate and program the display watermarks and line buffer allocation.
*/
3487static void dm_bandwidth_update(struct amdgpu_device *adev)
3488{
/* TODO: implement later */
3490}

3492static const struct amdgpu_display_funcs dm_display_funcs = {
.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
.backlight_set_level = NULL((void *)0), /* never called for DC */
.backlight_get_level = NULL((void *)0), /* never called for DC */
.hpd_sense = NULL((void *)0),/* called unconditionally */
.hpd_set_polarity = NULL((void *)0), /* called unconditionally */
.hpd_get_gpio_reg = NULL((void *)0), /* VBIOS parsing. DAL does it. */
.page_flip_get_scanoutpos =
dm_crtc_get_scanoutpos,/* called unconditionally */
.add_encoder = NULL((void *)0), /* VBIOS parsing. DAL does it. */
.add_connector = NULL((void *)0), /* VBIOS parsing. DAL does it. */
3504};

3506#if defined(CONFIG_DEBUG_KERNEL_DC)

3508static ssize_t s3_debug_store(struct device *device,
	      struct device_attribute *attr,
	      const char *buf,
	      size_t count)
3512{
int ret;
int s3_state;
struct drm_device *drm_dev = dev_get_drvdata(device)((void *)0);
struct amdgpu_device *adev = drm_to_adev(drm_dev);

ret = kstrtoint(buf, 0, &s3_state);

if (ret == 0) {
if (s3_state) {
	dm_resume(adev);
	drm_kms_helper_hotplug_event(adev_to_drm(adev));
} else
	dm_suspend(adev);
}

return ret == 0 ? count : 0;
3529}

3531DEVICE_ATTR_WO(s3_debug);

3533#endif

3535static int dm_early_init(void *handle)
3536{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

switch (adev->asic_type) {
3540#if defined(CONFIG_DRM_AMD_DC_SI)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_OLAND:
adev->mode_info.num_crtc = 2;
adev->mode_info.num_hpd = 2;
adev->mode_info.num_dig = 2;
break;
3553#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_KAVERI:
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 7;
break;
case CHIP_KABINI:
case CHIP_MULLINS:
adev->mode_info.num_crtc = 2;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_FIJI:
case CHIP_TONGA:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 7;
break;
case CHIP_CARRIZO:
adev->mode_info.num_crtc = 3;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 9;
break;
case CHIP_STONEY:
adev->mode_info.num_crtc = 2;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 9;
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
adev->mode_info.num_dig = 5;
break;
case CHIP_POLARIS10:
case CHIP_VEGAM:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
3606#if defined(CONFIG_DRM_AMD_DC_DCN1)
case CHIP_RAVEN:
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
break;
3612#endif
case CHIP_NAVI10:
case CHIP_NAVI12:
3615#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
3618#endif
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_NAVI14:
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
adev->mode_info.num_dig = 5;
break;
case CHIP_RENOIR:
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
break;
default:
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type)__drm_err("Unsupported ASIC type: 0x%X\n", adev->asic_type
);
return -EINVAL22;
}

amdgpu_dm_set_irq_funcs(adev);

if (adev->mode_info.funcs == NULL((void *)0))
adev->mode_info.funcs = &dm_display_funcs;

/*
* Note: Do NOT change adev->audio_endpt_rreg and
* adev->audio_endpt_wreg because they are initialised in
* amdgpu_device_init()
*/
3648#if defined(CONFIG_DEBUG_KERNEL_DC)
device_create_file(0
adev_to_drm(adev)->dev,0
&dev_attr_s3_debug)0;
3652#endif

return 0;
3655}

3657static bool_Bool modeset_required(struct drm_crtc_state *crtc_state,
	     struct dc_stream_state *new_stream,
	     struct dc_stream_state *old_stream)
3660{
return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
3662}

3664static bool_Bool modereset_required(struct drm_crtc_state *crtc_state)
3665{
return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
3667}

3669static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
3670{
drm_encoder_cleanup(encoder);
kfree(encoder);
3673}

3675static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
.destroy = amdgpu_dm_encoder_destroy,
3677};


3680static int fill_dc_scaling_info(const struct drm_plane_state *state,
		struct dc_scaling_info *scaling_info)
3682{
int scale_w, scale_h;

memset(scaling_info, 0, sizeof(*scaling_info))__builtin_memset((scaling_info), (0), (sizeof(*scaling_info))
);

/* Source is fixed 16.16 but we ignore mantissa for now... */
scaling_info->src_rect.x = state->src_x >> 16;
scaling_info->src_rect.y = state->src_y >> 16;

/*
* For reasons we don't (yet) fully understand a non-zero
* src_y coordinate into an NV12 buffer can cause a
* system hang. To avoid hangs (and maybe be overly cautious)
* let's reject both non-zero src_x and src_y.
*
* We currently know of only one use-case to reproduce a
* scenario with non-zero src_x and src_y for NV12, which
* is to gesture the YouTube Android app into full screen
* on ChromeOS.
*/
if (state->fb &&
   state->fb->format->format == DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
 16) | ((__u32)('2') << 24)) &&
   (scaling_info->src_rect.x != 0 ||
    scaling_info->src_rect.y != 0))
return -EINVAL22;

/*
* For reasons we don't (yet) fully understand a non-zero
* src_y coordinate into an NV12 buffer can cause a
* system hang. To avoid hangs (and maybe be overly cautious)
* let's reject both non-zero src_x and src_y.
*
* We currently know of only one use-case to reproduce a
* scenario with non-zero src_x and src_y for NV12, which
* is to gesture the YouTube Android app into full screen
* on ChromeOS.
*/
if (state->fb &&
   state->fb->format->format == DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
 16) | ((__u32)('2') << 24)) &&
   (scaling_info->src_rect.x != 0 ||
    scaling_info->src_rect.y != 0))
return -EINVAL22;

scaling_info->src_rect.width = state->src_w >> 16;
if (scaling_info->src_rect.width == 0)
return -EINVAL22;

scaling_info->src_rect.height = state->src_h >> 16;
if (scaling_info->src_rect.height == 0)
return -EINVAL22;

scaling_info->dst_rect.x = state->crtc_x;
scaling_info->dst_rect.y = state->crtc_y;

if (state->crtc_w == 0)
return -EINVAL22;

scaling_info->dst_rect.width = state->crtc_w;

if (state->crtc_h == 0)
return -EINVAL22;

scaling_info->dst_rect.height = state->crtc_h;

/* DRM doesn't specify clipping on destination output. */
scaling_info->clip_rect = scaling_info->dst_rect;

/* TODO: Validate scaling per-format with DC plane caps */
scale_w = scaling_info->dst_rect.width * 1000 /
  scaling_info->src_rect.width;

if (scale_w < 250 || scale_w > 16000)
return -EINVAL22;

scale_h = scaling_info->dst_rect.height * 1000 /
  scaling_info->src_rect.height;

if (scale_h < 250 || scale_h > 16000)
return -EINVAL22;

/*
* The "scaling_quality" can be ignored for now, quality = 0 has DC
* assume reasonable defaults based on the format.
*/

return 0;
3768}

3770static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
       uint64_t *tiling_flags, bool_Bool *tmz_surface)
3772{
struct amdgpu_bo *rbo;
int r;

if (!amdgpu_fb) {
*tiling_flags = 0;
*tmz_surface = false0;
return 0;
}

rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
 = ((amdgpu_fb->base.obj[0])); (struct amdgpu_bo *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_bo, tbo.base) );
});
r = amdgpu_bo_reserve(rbo, false0);

if (unlikely(r)__builtin_expect(!!(r), 0)) {
/* Don't show error message when returning -ERESTARTSYS */
if (r != -ERESTARTSYS4)
	DRM_ERROR("Unable to reserve buffer: %d\n", r)__drm_err("Unable to reserve buffer: %d\n", r);
return r;
}

if (tiling_flags)
amdgpu_bo_get_tiling_flags(rbo, tiling_flags);

if (tmz_surface)
*tmz_surface = amdgpu_bo_encrypted(rbo);

amdgpu_bo_unreserve(rbo);

return r;
3801}

3803static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
3804{
uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B)(((__u64)(tiling_flags) >> 5) & 0xFFFFFF);

return offset ? (address + offset * 256) : 0;
3808}

3810static int
3811fill_plane_dcc_attributes(struct amdgpu_device *adev,
	  const struct amdgpu_framebuffer *afb,
	  const enum surface_pixel_format format,
	  const enum dc_rotation_angle rotation,
	  const struct plane_size *plane_size,
	  const union dc_tiling_info *tiling_info,
	  const uint64_t info,
	  struct dc_plane_dcc_param *dcc,
	  struct dc_plane_address *address,
	  bool_Bool force_disable_dcc)
3821{
struct dc *dc = adev->dm.dc;
struct dc_dcc_surface_param input;
struct dc_surface_dcc_cap output;
uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B)(((__u64)(info) >> 5) & 0xFFFFFF);
uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B)(((__u64)(info) >> 43) & 0x1) != 0;
uint64_t dcc_address;

memset(&input, 0, sizeof(input))__builtin_memset((&input), (0), (sizeof(input)));
memset(&output, 0, sizeof(output))__builtin_memset((&output), (0), (sizeof(output)));

if (force_disable_dcc)
return 0;

if (!offset)
return 0;

if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return 0;

if (!dc->cap_funcs.get_dcc_compression_cap)
return -EINVAL22;

input.format = format;
input.surface_size.width = plane_size->surface_size.width;
input.surface_size.height = plane_size->surface_size.height;
input.swizzle_mode = tiling_info->gfx9.swizzle;

if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
input.scan = SCAN_DIRECTION_HORIZONTAL;
else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
input.scan = SCAN_DIRECTION_VERTICAL;

if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
return -EINVAL22;

if (!output.capable)
return -EINVAL22;

if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
return -EINVAL22;

dcc->enable = 1;
dcc->meta_pitch =
AMDGPU_TILING_GET(info, DCC_PITCH_MAX)(((__u64)(info) >> 29) & 0x3FFF) + 1;
dcc->independent_64b_blks = i64b;

dcc_address = get_dcc_address(afb->address, info);
address->grph.meta_addr.low_part = lower_32_bits(dcc_address)((u32)(dcc_address));
address->grph.meta_addr.high_part = upper_32_bits(dcc_address)((u32)(((dcc_address) >> 16) >> 16));

return 0;
3873}

3875static int
3876fill_plane_buffer_attributes(struct amdgpu_device *adev,
	     const struct amdgpu_framebuffer *afb,
	     const enum surface_pixel_format format,
	     const enum dc_rotation_angle rotation,
	     const uint64_t tiling_flags,
	     union dc_tiling_info *tiling_info,
	     struct plane_size *plane_size,
	     struct dc_plane_dcc_param *dcc,
	     struct dc_plane_address *address,
	     bool_Bool tmz_surface,
	     bool_Bool force_disable_dcc)
3887{
const struct drm_framebuffer *fb = &afb->base;
int ret;

memset(tiling_info, 0, sizeof(*tiling_info))__builtin_memset((tiling_info), (0), (sizeof(*tiling_info)));
memset(plane_size, 0, sizeof(*plane_size))__builtin_memset((plane_size), (0), (sizeof(*plane_size)));
memset(dcc, 0, sizeof(*dcc))__builtin_memset((dcc), (0), (sizeof(*dcc)));
memset(address, 0, sizeof(*address))__builtin_memset((address), (0), (sizeof(*address)));

address->tmz_surface = tmz_surface;

if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
plane_size->surface_size.x = 0;
plane_size->surface_size.y = 0;
plane_size->surface_size.width = fb->width;
plane_size->surface_size.height = fb->height;
plane_size->surface_pitch =
	fb->pitches[0] / fb->format->cpp[0];

address->type = PLN_ADDR_TYPE_GRAPHICS;
address->grph.addr.low_part = lower_32_bits(afb->address)((u32)(afb->address));
address->grph.addr.high_part = upper_32_bits(afb->address)((u32)(((afb->address) >> 16) >> 16));
} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
uint64_t chroma_addr = afb->address + fb->offsets[1];

plane_size->surface_size.x = 0;
plane_size->surface_size.y = 0;
plane_size->surface_size.width = fb->width;
plane_size->surface_size.height = fb->height;
plane_size->surface_pitch =
	fb->pitches[0] / fb->format->cpp[0];

plane_size->chroma_size.x = 0;
plane_size->chroma_size.y = 0;
/* TODO: set these based on surface format */
plane_size->chroma_size.width = fb->width / 2;
plane_size->chroma_size.height = fb->height / 2;

plane_size->chroma_pitch =
	fb->pitches[1] / fb->format->cpp[1];

address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
address->video_progressive.luma_addr.low_part =
	lower_32_bits(afb->address)((u32)(afb->address));
address->video_progressive.luma_addr.high_part =
	upper_32_bits(afb->address)((u32)(((afb->address) >> 16) >> 16));
address->video_progressive.chroma_addr.low_part =
	lower_32_bits(chroma_addr)((u32)(chroma_addr));
address->video_progressive.chroma_addr.high_part =
	upper_32_bits(chroma_addr)((u32)(((chroma_addr) >> 16) >> 16));
}

/* Fill GFX8 params */
if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)(((__u64)(tiling_flags) >> 0) & 0xf) == DC_ARRAY_2D_TILED_THIN1) {
unsigned int bankw, bankh, mtaspect, tile_split, num_banks;

bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH)(((__u64)(tiling_flags) >> 15) & 0x3);
bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT)(((__u64)(tiling_flags) >> 17) & 0x3);
mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT)(((__u64)(tiling_flags) >> 19) & 0x3);
tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)(((__u64)(tiling_flags) >> 9) & 0x7);
num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS)(((__u64)(tiling_flags) >> 21) & 0x3);

/* XXX fix me for VI */
tiling_info->gfx8.num_banks = num_banks;
tiling_info->gfx8.array_mode =
		DC_ARRAY_2D_TILED_THIN1;
tiling_info->gfx8.tile_split = tile_split;
tiling_info->gfx8.bank_width = bankw;
tiling_info->gfx8.bank_height = bankh;
tiling_info->gfx8.tile_aspect = mtaspect;
tiling_info->gfx8.tile_mode =
		DC_ADDR_SURF_MICRO_TILING_DISPLAY;
} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)(((__u64)(tiling_flags) >> 0) & 0xf)
	== DC_ARRAY_1D_TILED_THIN1) {
tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
}

tiling_info->gfx8.pipe_config =
	AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG)(((__u64)(tiling_flags) >> 4) & 0x1f);

if (adev->asic_type == CHIP_VEGA10 ||
   adev->asic_type == CHIP_VEGA12 ||
   adev->asic_type == CHIP_VEGA20 ||
   adev->asic_type == CHIP_NAVI10 ||
   adev->asic_type == CHIP_NAVI14 ||
   adev->asic_type == CHIP_NAVI12 ||
3973#if defined(CONFIG_DRM_AMD_DC_DCN3_01)
adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_NAVY_FLOUNDER ||
3976#endif
   adev->asic_type == CHIP_RENOIR ||
   adev->asic_type == CHIP_RAVEN) {
/* Fill GFX9 params */
tiling_info->gfx9.num_pipes =
	adev->gfx.config.gb_addr_config_fields.num_pipes;
tiling_info->gfx9.num_banks =
	adev->gfx.config.gb_addr_config_fields.num_banks;
tiling_info->gfx9.pipe_interleave =
	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
tiling_info->gfx9.num_shader_engines =
	adev->gfx.config.gb_addr_config_fields.num_se;
tiling_info->gfx9.max_compressed_frags =
	adev->gfx.config.gb_addr_config_fields.max_compress_frags;
tiling_info->gfx9.num_rb_per_se =
	adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
tiling_info->gfx9.swizzle =
	AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE)(((__u64)(tiling_flags) >> 0) & 0x1f);
tiling_info->gfx9.shaderEnable = 1;

3996#ifdef CONFIG_DRM_AMD_DC_DCN3_01
if (adev->asic_type == CHIP_SIENNA_CICHLID ||
    adev->asic_type == CHIP_NAVY_FLOUNDER)
	tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
4000#endif
ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
				plane_size, tiling_info,
				tiling_flags, dcc, address,
				force_disable_dcc);
if (ret)
	return ret;
}

return 0;
4010}

4012static void
4013fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
	       bool_Bool *per_pixel_alpha, bool_Bool *global_alpha,
	       int *global_alpha_value)
4016{
*per_pixel_alpha = false0;
*global_alpha = false0;
*global_alpha_value = 0xff;

if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
return;

if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI0) {
static const uint32_t alpha_formats[] = {
	DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
	DRM_FORMAT_RGBA8888((__u32)('R') | ((__u32)('A') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
	DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
};
uint32_t format = plane_state->fb->format->format;
unsigned int i;

for (i = 0; i < ARRAY_SIZE(alpha_formats)(sizeof((alpha_formats)) / sizeof((alpha_formats)[0])); ++i) {
	if (format == alpha_formats[i]) {
		*per_pixel_alpha = true1;
		break;
	}
}
}

if (plane_state->alpha < 0xffff) {
*global_alpha = true1;
*global_alpha_value = plane_state->alpha >> 8;
}
4045}

4047static int
4048fill_plane_color_attributes(const struct drm_plane_state *plane_state,
	    const enum surface_pixel_format format,
	    enum dc_color_space *color_space)
4051{
bool_Bool full_range;

*color_space = COLOR_SPACE_SRGB;

/* DRM color properties only affect non-RGB formats. */
if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return 0;

full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);

switch (plane_state->color_encoding) {
case DRM_COLOR_YCBCR_BT601:
if (full_range)
	*color_space = COLOR_SPACE_YCBCR601;
else
	*color_space = COLOR_SPACE_YCBCR601_LIMITED;
break;

case DRM_COLOR_YCBCR_BT709:
if (full_range)
	*color_space = COLOR_SPACE_YCBCR709;
else
	*color_space = COLOR_SPACE_YCBCR709_LIMITED;
break;

case DRM_COLOR_YCBCR_BT2020:
if (full_range)
	*color_space = COLOR_SPACE_2020_YCBCR;
else
	return -EINVAL22;
break;

default:
return -EINVAL22;
}

return 0;
4089}

4091static int
4092fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
	    const struct drm_plane_state *plane_state,
	    const uint64_t tiling_flags,
	    struct dc_plane_info *plane_info,
	    struct dc_plane_address *address,
	    bool_Bool tmz_surface,
	    bool_Bool force_disable_dcc)
4099{
const struct drm_framebuffer *fb = plane_state->fb;
const struct amdgpu_framebuffer *afb =
to_amdgpu_framebuffer(plane_state->fb)({ const __typeof( ((struct amdgpu_framebuffer *)0)->base )
 *__mptr = (plane_state->fb); (struct amdgpu_framebuffer *
)( (char *)__mptr - __builtin_offsetof(struct amdgpu_framebuffer
, base) );});
struct drm_format_name_buf format_name;
int ret;

memset(plane_info, 0, sizeof(*plane_info))__builtin_memset((plane_info), (0), (sizeof(*plane_info)));

switch (fb->format->format) {
case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
 16) | ((__u32)(' ') << 24)):
plane_info->format =
	SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
break;
case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
 16) | ((__u32)('6') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
break;
case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)):
case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
break;
case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)):
case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
break;
case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)):
case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
break;
case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)):
case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
break;
case DRM_FORMAT_NV21((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('2') <<
 16) | ((__u32)('1') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
break;
case DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
 16) | ((__u32)('2') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
break;
case DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
 16) | ((__u32)('0') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
break;
case DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24)):
case DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
break;
case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24)):
case DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
break;
default:
DRM_ERROR(__drm_err("Unsupported screen format %s\n", drm_get_format_name
(fb->format->format, &format_name))
	"Unsupported screen format %s\n",__drm_err("Unsupported screen format %s\n", drm_get_format_name
(fb->format->format, &format_name))
	drm_get_format_name(fb->format->format, &format_name))__drm_err("Unsupported screen format %s\n", drm_get_format_name
(fb->format->format, &format_name));
return -EINVAL22;
}

switch (plane_state->rotation & DRM_MODE_ROTATE_MASK( (1<<0) | (1<<1) | (1<<2) | (1<<3))) {
case DRM_MODE_ROTATE_0(1<<0):
plane_info->rotation = ROTATION_ANGLE_0;
break;
case DRM_MODE_ROTATE_90(1<<1):
plane_info->rotation = ROTATION_ANGLE_90;
break;
case DRM_MODE_ROTATE_180(1<<2):
plane_info->rotation = ROTATION_ANGLE_180;
break;
case DRM_MODE_ROTATE_270(1<<3):
plane_info->rotation = ROTATION_ANGLE_270;
break;
default:
plane_info->rotation = ROTATION_ANGLE_0;
break;
}

plane_info->visible = true1;
plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;

plane_info->layer_index = 0;

ret = fill_plane_color_attributes(plane_state, plane_info->format,
			  &plane_info->color_space);
if (ret)
return ret;

ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
			   plane_info->rotation, tiling_flags,
			   &plane_info->tiling_info,
			   &plane_info->plane_size,
			   &plane_info->dcc, address, tmz_surface,
			   force_disable_dcc);
if (ret)
return ret;

fill_blending_from_plane_state(
plane_state, &plane_info->per_pixel_alpha,
&plane_info->global_alpha, &plane_info->global_alpha_value);

return 0;
4198}

4200static int fill_dc_plane_attributes(struct amdgpu_device *adev,
		    struct dc_plane_state *dc_plane_state,
		    struct drm_plane_state *plane_state,
		    struct drm_crtc_state *crtc_state)
4204{
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (crtc_state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_crtc_state, base) );});
struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (plane_state); (struct dm_plane_state *)( (char *)__mptr -
 __builtin_offsetof(struct dm_plane_state, base) );});
struct dc_scaling_info scaling_info;
struct dc_plane_info plane_info;
int ret;
bool_Bool force_disable_dcc = false0;

ret = fill_dc_scaling_info(plane_state, &scaling_info);
if (ret)
return ret;

dc_plane_state->src_rect = scaling_info.src_rect;
dc_plane_state->dst_rect = scaling_info.dst_rect;
dc_plane_state->clip_rect = scaling_info.clip_rect;
dc_plane_state->scaling_quality = scaling_info.scaling_quality;

force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
ret = fill_dc_plane_info_and_addr(adev, plane_state,
			  dm_plane_state->tiling_flags,
			  &plane_info,
			  &dc_plane_state->address,
			  dm_plane_state->tmz_surface,
			  force_disable_dcc);
if (ret)
return ret;

dc_plane_state->format = plane_info.format;
dc_plane_state->color_space = plane_info.color_space;
dc_plane_state->format = plane_info.format;
dc_plane_state->plane_size = plane_info.plane_size;
dc_plane_state->rotation = plane_info.rotation;
dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
dc_plane_state->stereo_format = plane_info.stereo_format;
dc_plane_state->tiling_info = plane_info.tiling_info;
dc_plane_state->visible = plane_info.visible;
dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
dc_plane_state->global_alpha = plane_info.global_alpha;
dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
dc_plane_state->dcc = plane_info.dcc;
dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0

/*
* Always set input transfer function, since plane state is refreshed
* every time.
*/
ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
if (ret)
return ret;

return 0;
4255}

4257static void update_stream_scaling_settings(const struct drm_display_mode *mode,
			   const struct dm_connector_state *dm_state,
			   struct dc_stream_state *stream)
4260{
enum amdgpu_rmx_type rmx_type;

struct rect src = { 0 }; /* viewport in composition space*/
struct rect dst = { 0 }; /* stream addressable area */

/* no mode. nothing to be done */
if (!mode)
return;

/* Full screen scaling by default */
src.width = mode->hdisplay;
src.height = mode->vdisplay;
dst.width = stream->timing.h_addressable;
dst.height = stream->timing.v_addressable;

if (dm_state) {
rmx_type = dm_state->scaling;
if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
	if (src.width * dst.height <
			src.height * dst.width) {
		/* height needs less upscaling/more downscaling */
		dst.width = src.width *
				dst.height / src.height;
	} else {
		/* width needs less upscaling/more downscaling */
		dst.height = src.height *
				dst.width / src.width;
	}
} else if (rmx_type == RMX_CENTER) {
	dst = src;
}

dst.x = (stream->timing.h_addressable - dst.width) / 2;
dst.y = (stream->timing.v_addressable - dst.height) / 2;

if (dm_state->underscan_enable) {
	dst.x += dm_state->underscan_hborder / 2;
	dst.y += dm_state->underscan_vborder / 2;
	dst.width -= dm_state->underscan_hborder;
	dst.height -= dm_state->underscan_vborder;
}
}

stream->src = src;
stream->dst = dst;

DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",__drm_dbg(DRM_UT_DRIVER, "Destination Rectangle x:%d  y:%d  width:%d  height:%d\n"
, dst.x, dst.y, dst.width, dst.height)
	dst.x, dst.y, dst.width, dst.height)__drm_dbg(DRM_UT_DRIVER, "Destination Rectangle x:%d  y:%d  width:%d  height:%d\n"
, dst.x, dst.y, dst.width, dst.height);

4310}

4312static enum dc_color_depth
4313convert_color_depth_from_display_info(const struct drm_connector *connector,
		      bool_Bool is_y420, int requested_bpc)
4315{
uint8_t bpc;

if (is_y420) {
bpc = 8;

/* Cap display bpc based on HDMI 2.0 HF-VSDB */
if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48(1 << 2))
	bpc = 16;
else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36(1 << 1))
	bpc = 12;
else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30(1 << 0))
	bpc = 10;
} else {
bpc = (uint8_t)connector->display_info.bpc;
/* Assume 8 bpc by default if no bpc is specified. */
bpc = bpc ? bpc : 8;
}

if (requested_bpc > 0) {
/*
 * Cap display bpc based on the user requested value.
 *
 * The value for state->max_bpc may not correctly updated
 * depending on when the connector gets added to the state
 * or if this was called outside of atomic check, so it
 * can't be used directly.
 */
bpc = min_t(u8, bpc, requested_bpc)({ u8 __min_a = (bpc); u8 __min_b = (requested_bpc); __min_a <
 __min_b ? __min_a : __min_b; });

/* Round down to the nearest even number. */
bpc = bpc - (bpc & 1);
}

switch (bpc) {
case 0:
/*
 * Temporary Work around, DRM doesn't parse color depth for
 * EDID revision before 1.4
 * TODO: Fix edid parsing
 */
return COLOR_DEPTH_888;
case 6:
return COLOR_DEPTH_666;
case 8:
return COLOR_DEPTH_888;
case 10:
return COLOR_DEPTH_101010;
case 12:
return COLOR_DEPTH_121212;
case 14:
return COLOR_DEPTH_141414;
case 16:
return COLOR_DEPTH_161616;
default:
return COLOR_DEPTH_UNDEFINED;
}
4372}

4374static enum dc_aspect_ratio
4375get_aspect_ratio(const struct drm_display_mode *mode_in)
4376{
/* 1-1 mapping, since both enums follow the HDMI spec. */
return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
4379}

4381static enum dc_color_space
4382get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
4383{
enum dc_color_space color_space = COLOR_SPACE_SRGB;

switch (dc_crtc_timing->pixel_encoding)	{
case PIXEL_ENCODING_YCBCR422:
case PIXEL_ENCODING_YCBCR444:
case PIXEL_ENCODING_YCBCR420:
{
/*
 * 27030khz is the separation point between HDTV and SDTV
 * according to HDMI spec, we use YCbCr709 and YCbCr601
 * respectively
 */
if (dc_crtc_timing->pix_clk_100hz > 270300) {
	if (dc_crtc_timing->flags.Y_ONLY)
		color_space =
			COLOR_SPACE_YCBCR709_LIMITED;
	else
		color_space = COLOR_SPACE_YCBCR709;
} else {
	if (dc_crtc_timing->flags.Y_ONLY)
		color_space =
			COLOR_SPACE_YCBCR601_LIMITED;
	else
		color_space = COLOR_SPACE_YCBCR601;
}

}
break;
case PIXEL_ENCODING_RGB:
color_space = COLOR_SPACE_SRGB;
break;

default:
WARN_ON(1)({ int __ret = !!(1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "1", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 4417); __builtin_expect(!!(__ret), 0); });
break;
}

return color_space;
4422}

4424static bool_Bool adjust_colour_depth_from_display_info(
struct dc_crtc_timing *timing_out,
const struct drm_display_info *info)
4427{
enum dc_color_depth depth = timing_out->display_color_depth;
int normalized_clk;
do {
normalized_clk = timing_out->pix_clk_100hz / 10;
/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
	normalized_clk /= 2;
/* Adjusting pix clock following on HDMI spec based on colour depth */
switch (depth) {
case COLOR_DEPTH_888:
	break;
case COLOR_DEPTH_101010:
	normalized_clk = (normalized_clk * 30) / 24;
	break;
case COLOR_DEPTH_121212:
	normalized_clk = (normalized_clk * 36) / 24;
	break;
case COLOR_DEPTH_161616:
	normalized_clk = (normalized_clk * 48) / 24;
	break;
default:
	/* The above depths are the only ones valid for HDMI. */
	return false0;
}
if (normalized_clk <= info->max_tmds_clock) {
	timing_out->display_color_depth = depth;
	return true1;
}
} while (--depth > COLOR_DEPTH_666);
return false0;
4458}

4460static void fill_stream_properties_from_drm_display_mode(
struct dc_stream_state *stream,
const struct drm_display_mode *mode_in,
const struct drm_connector *connector,
const struct drm_connector_state *connector_state,
const struct dc_stream_state *old_stream,
int requested_bpc)
4467{
struct dc_crtc_timing *timing_out = &stream->timing;
const struct drm_display_info *info = &connector->display_info;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct hdmi_vendor_infoframe hv_frame;
struct hdmi_avi_infoframe avi_frame;

memset(&hv_frame, 0, sizeof(hv_frame))__builtin_memset((&hv_frame), (0), (sizeof(hv_frame)));
memset(&avi_frame, 0, sizeof(avi_frame))__builtin_memset((&avi_frame), (0), (sizeof(avi_frame)));

timing_out->h_border_left = 0;
timing_out->h_border_right = 0;
timing_out->v_border_top = 0;
timing_out->v_border_bottom = 0;
/* TODO: un-hardcode */
if (drm_mode_is_420_only(info, mode_in)
	&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
else if (drm_mode_is_420_also(info, mode_in)
	&& aconnector->force_yuv420_output)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444(1<<1))
	&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
else
timing_out->pixel_encoding = PIXEL_ENCODING_RGB;

timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
timing_out->display_color_depth = convert_color_depth_from_display_info(
connector,
(timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
requested_bpc);
timing_out->scan_type = SCANNING_TYPE_NODATA;
timing_out->hdmi_vic = 0;

if(old_stream) {
timing_out->vic = old_stream->timing.vic;
timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
} else {
timing_out->vic = drm_match_cea_mode(mode_in);
if (mode_in->flags & DRM_MODE_FLAG_PHSYNC(1<<0))
	timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
if (mode_in->flags & DRM_MODE_FLAG_PVSYNC(1<<2))
	timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
}

if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
timing_out->vic = avi_frame.video_code;
drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
timing_out->hdmi_vic = hv_frame.vic;
}

timing_out->h_addressable = mode_in->crtc_hdisplay;
timing_out->h_total = mode_in->crtc_htotal;
timing_out->h_sync_width =
mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
timing_out->h_front_porch =
mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
timing_out->v_total = mode_in->crtc_vtotal;
timing_out->v_addressable = mode_in->crtc_vdisplay;
timing_out->v_front_porch =
mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
timing_out->v_sync_width =
mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
timing_out->aspect_ratio = get_aspect_ratio(mode_in);

stream->output_color_space = get_output_color_space(timing_out);

stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
if (!adjust_colour_depth_from_display_info(timing_out, info) &&
    drm_mode_is_420_also(info, mode_in) &&
    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
	timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
	adjust_colour_depth_from_display_info(timing_out, info);
}
}
4548}

4550static void fill_audio_info(struct audio_info *audio_info,
	    const struct drm_connector *drm_connector,
	    const struct dc_sink *dc_sink)
4553{
int i = 0;
int cea_revision = 0;
const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;

audio_info->manufacture_id = edid_caps->manufacturer_id;
audio_info->product_id = edid_caps->product_id;

cea_revision = drm_connector->display_info.cea_rev;

4563#ifdef __linux__
strscpy(audio_info->display_name,
edid_caps->display_name,
AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS20);
4567#else
strncpy(audio_info->display_name,
edid_caps->display_name,
AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS20 - 1);
4571#endif

if (cea_revision >= 3) {
audio_info->mode_count = edid_caps->audio_mode_count;

for (i = 0; i < audio_info->mode_count; ++i) {
	audio_info->modes[i].format_code =
			(enum audio_format_code)
			(edid_caps->audio_modes[i].format_code);
	audio_info->modes[i].channel_count =
			edid_caps->audio_modes[i].channel_count;
	audio_info->modes[i].sample_rates.all =
			edid_caps->audio_modes[i].sample_rate;
	audio_info->modes[i].sample_size =
			edid_caps->audio_modes[i].sample_size;
}
}

audio_info->flags.all = edid_caps->speaker_flags;

/* TODO: We only check for the progressive mode, check for interlace mode too */
if (drm_connector->latency_present[0]) {
audio_info->video_latency = drm_connector->video_latency[0];
audio_info->audio_latency = drm_connector->audio_latency[0];
}

/* TODO: For DP, video and audio latency should be calculated from DPCD caps */

4599}

4601static void
4602copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
		      struct drm_display_mode *dst_mode)
4604{
dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
dst_mode->crtc_clock = src_mode->crtc_clock;
dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
dst_mode->crtc_htotal = src_mode->crtc_htotal;
dst_mode->crtc_hskew = src_mode->crtc_hskew;
dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
4619}

4621static void
4622decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
			const struct drm_display_mode *native_mode,
			bool_Bool scale_enabled)
4625{
if (scale_enabled) {
copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
} else if (native_mode->clock == drm_mode->clock &&
	native_mode->htotal == drm_mode->htotal &&
	native_mode->vtotal == drm_mode->vtotal) {
copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
} else {
/* no scaling nor amdgpu inserted, no need to patch */
}
4635}

4637static struct dc_sink *
4638create_fake_sink(struct amdgpu_dm_connector *aconnector)
4639{
struct dc_sink_init_data sink_init_data = { 0 };
struct dc_sink *sink = NULL((void *)0);
sink_init_data.link = aconnector->dc_link;
sink_init_data.sink_signal = aconnector->dc_link->connector_signal;

sink = dc_sink_create(&sink_init_data);
if (!sink) {
DRM_ERROR("Failed to create sink!\n")__drm_err("Failed to create sink!\n");
return NULL((void *)0);
}
sink->sink_signal = SIGNAL_TYPE_VIRTUAL;

return sink;
4653}

4655static void set_multisync_trigger_params(
struct dc_stream_state *stream)
4657{
if (stream->triggered_crtc_reset.enabled) {
stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
}
4662}

4664static void set_master_stream(struct dc_stream_state *stream_set[],
	      int stream_count)
4666{
int j, highest_rfr = 0, master_stream = 0;

for (j = 0;  j < stream_count; j++) {
if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
	int refresh_rate = 0;

	refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
		(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
	if (refresh_rate > highest_rfr) {
		highest_rfr = refresh_rate;
		master_stream = j;
	}
}
}
for (j = 0;  j < stream_count; j++) {
if (stream_set[j])
	stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
}
4685}

4687static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
4688{
int i = 0;

if (context->stream_count < 2)
return;
for (i = 0; i < context->stream_count ; i++) {
if (!context->streams[i])
	continue;
/*
 * TODO: add a function to read AMD VSDB bits and set
 * crtc_sync_master.multi_sync_enabled flag
 * For now it's set to false
 */
set_multisync_trigger_params(context->streams[i]);
}
set_master_stream(context->streams, context->stream_count);
4704}

4706static struct dc_stream_state *
4707create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
       const struct drm_display_mode *drm_mode,
       const struct dm_connector_state *dm_state,
       const struct dc_stream_state *old_stream,
       int requested_bpc)
4712{
struct drm_display_mode *preferred_mode = NULL((void *)0);
struct drm_connector *drm_connector;
const struct drm_connector_state *con_state =
dm_state ? &dm_state->base : NULL((void *)0);
struct dc_stream_state *stream = NULL((void *)0);
struct drm_display_mode mode = *drm_mode;
bool_Bool native_mode_found = false0;
bool_Bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false0;
int mode_refresh;
int preferred_refresh = 0;
4723#if defined(CONFIG_DRM_AMD_DC_DCN1)
struct dsc_dec_dpcd_caps dsc_caps;
4725#endif
uint32_t link_bandwidth_kbps;

struct dc_sink *sink = NULL((void *)0);
if (aconnector == NULL((void *)0)) {
DRM_ERROR("aconnector is NULL!\n")__drm_err("aconnector is NULL!\n");
return stream;
}

drm_connector = &aconnector->base;

if (!aconnector->dc_sink) {
sink = create_fake_sink(aconnector);
if (!sink)
	return stream;
} else {
sink = aconnector->dc_sink;
dc_sink_retain(sink);
}

stream = dc_create_stream_for_sink(sink);

if (stream == NULL((void *)0)) {
DRM_ERROR("Failed to create stream for sink!\n")__drm_err("Failed to create stream for sink!\n");
goto finish;
}

stream->dm_stream_context = aconnector;

stream->timing.flags.LTE_340MCSC_SCRAMBLE =
drm_connector->display_info.hdmi.scdc.scrambling.low_rates;

list_for_each_entry(preferred_mode, &aconnector->base.modes, head)for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode
) *)0)->head ) *__mptr = ((&aconnector->base.modes)
->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*preferred_mode), head) );}); &preferred_mode->
head != (&aconnector->base.modes); preferred_mode = ({
 const __typeof( ((__typeof(*preferred_mode) *)0)->head ) *
__mptr = (preferred_mode->head.next); (__typeof(*preferred_mode
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode
), head) );})) {
/* Search for preferred mode */
if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED(1<<3)) {
	native_mode_found = true1;
	break;
}
}
if (!native_mode_found)
preferred_mode = list_first_entry_or_null((list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}))
		&aconnector->base.modes,(list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}))
		struct drm_display_mode,(list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}))
		head)(list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}));

mode_refresh = drm_mode_vrefresh(&mode);

if (preferred_mode == NULL((void *)0)) {
/*
 * This may not be an error, the use case is when we have no
 * usermode calls to reset and set mode upon hotplug. In this
 * case, we call set mode ourselves to restore the previous mode
 * and the modelist may not be filled in in time.
 */
DRM_DEBUG_DRIVER("No preferred mode found\n")__drm_dbg(DRM_UT_DRIVER, "No preferred mode found\n");
} else {
decide_crtc_timing_for_drm_display_mode(
		&mode, preferred_mode,
		dm_state ? (dm_state->scaling != RMX_OFF) : false0);
preferred_refresh = drm_mode_vrefresh(preferred_mode);
}

if (!dm_state)
drm_mode_set_crtcinfo(&mode, 0);

/*
* If scaling is enabled and refresh rate didn't change
* we copy the vic and polarities of the old timings
*/
if (!scale || mode_refresh != preferred_refresh)
fill_stream_properties_from_drm_display_mode(stream,
	&mode, &aconnector->base, con_state, NULL((void *)0), requested_bpc);
else
fill_stream_properties_from_drm_display_mode(stream,
	&mode, &aconnector->base, con_state, old_stream, requested_bpc);

stream->timing.flags.DSC = 0;

if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4804#if defined(CONFIG_DRM_AMD_DC_DCN1)
dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
		      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
		      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
		      &dsc_caps);
4809#endif
link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
					     dc_link_get_link_cap(aconnector->dc_link));

4813#if defined(CONFIG_DRM_AMD_DC_DCN1)
if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) {
	/* Set DSC policy according to dsc_clock_en */
	dc_dsc_policy_set_enable_dsc_when_not_needed(
		aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);

	if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
				  &dsc_caps,
				  aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
				  link_bandwidth_kbps,
				  &stream->timing,
				  &stream->timing.dsc_cfg))
		stream->timing.flags.DSC = 1;
	/* Overwrite the stream flag if DSC is enabled through debugfs */
	if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
		stream->timing.flags.DSC = 1;

	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
		stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;

	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
		stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;

	if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
		stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
}
4839#endif
}

update_stream_scaling_settings(&mode, dm_state, stream);

fill_audio_info(
&stream->audio_info,
drm_connector,
sink);

update_stream_signal(stream, sink);

if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);

if (stream->link->psr_settings.psr_feature_enabled) {
//
// should decide stream support vsc sdp colorimetry capability
// before building vsc info packet
//
stream->use_vsc_sdp_for_colorimetry = false0;
if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
	stream->use_vsc_sdp_for_colorimetry =
		aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
} else {
	if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
		stream->use_vsc_sdp_for_colorimetry = true1;
}
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket);
}
4869finish:
dc_sink_release(sink);

return stream;
4873}

4875static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
4876{
drm_crtc_cleanup(crtc);
kfree(crtc);
4879}

4881static void dm_crtc_destroy_state(struct drm_crtc *crtc,
		  struct drm_crtc_state *state)
4883{
struct dm_crtc_state *cur = to_dm_crtc_state(state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_crtc_state, base) );});

/* TODO Destroy dc_stream objects are stream object is flattened */
if (cur->stream)
dc_stream_release(cur->stream);


__drm_atomic_helper_crtc_destroy_state(state);


kfree(state);
4895}

4897static void dm_crtc_reset_state(struct drm_crtc *crtc)
4898{
struct dm_crtc_state *state;

if (crtc->state)
dm_crtc_destroy_state(crtc, crtc->state);

state = kzalloc(sizeof(*state), GFP_KERNEL(0x0001 | 0x0004));
if (WARN_ON(!state)({ int __ret = !!(!state); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!state", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 4905); __builtin_expect(!!(__ret), 0); }))
return;

__drm_atomic_helper_crtc_reset(crtc, &state->base);
4909}

4911static struct drm_crtc_state *
4912dm_crtc_duplicate_state(struct drm_crtc *crtc)
4913{
struct dm_crtc_state *state, *cur;

cur = to_dm_crtc_state(crtc->state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (crtc->state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (WARN_ON(!crtc->state)({ int __ret = !!(!crtc->state); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!crtc->state", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 4918); __builtin_expect(!!(__ret), 0); }))
return NULL((void *)0);

state = kzalloc(sizeof(*state), GFP_KERNEL(0x0001 | 0x0004));
if (!state)
return NULL((void *)0);

__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);

if (cur->stream) {
state->stream = cur->stream;
dc_stream_retain(state->stream);
}

state->active_planes = cur->active_planes;
state->vrr_infopacket = cur->vrr_infopacket;
state->abm_level = cur->abm_level;
state->vrr_supported = cur->vrr_supported;
state->freesync_config = cur->freesync_config;
state->crc_src = cur->crc_src;
state->cm_has_degamma = cur->cm_has_degamma;
state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;

/* TODO Duplicate dc_stream after objects are stream object is flattened */

return &state->base;
4944}

4946static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool_Bool enable)
4947{
enum dc_irq_source irq_source;
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
int rc;

irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;

rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY16;

DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",__drm_dbg(DRM_UT_DRIVER, "crtc %d - vupdate irq %sabling: r=%d\n"
, acrtc->crtc_id, enable ? "en" : "dis", rc)
	 acrtc->crtc_id, enable ? "en" : "dis", rc)__drm_dbg(DRM_UT_DRIVER, "crtc %d - vupdate irq %sabling: r=%d\n"
, acrtc->crtc_id, enable ? "en" : "dis", rc);
return rc;
4960}

4962static inline int dm_set_vblank(struct drm_crtc *crtc, bool_Bool enable)
4963{
enum dc_irq_source irq_source;
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (crtc->state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
int rc = 0;

if (enable) {
/* vblank irq on -> Only need vupdate irq in vrr mode */
if (amdgpu_dm_vrr_active(acrtc_state))
	rc = dm_set_vupdate_irq(crtc, true1);
} else {
/* vblank irq off -> vupdate irq off */
rc = dm_set_vupdate_irq(crtc, false0);
}

if (rc)
return rc;

irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY16;
4984}

4986static int dm_enable_vblank(struct drm_crtc *crtc)
4987{
return dm_set_vblank(crtc, true1);
4989}

4991static void dm_disable_vblank(struct drm_crtc *crtc)
4992{
dm_set_vblank(crtc, false0);
4994}

4996/* Implemented only the options currently availible for the driver */
4997static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
.reset = dm_crtc_reset_state,
.destroy = amdgpu_dm_crtc_destroy,
.gamma_set = drm_atomic_helper_legacy_gamma_set,
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
.atomic_duplicate_state = dm_crtc_duplicate_state,
.atomic_destroy_state = dm_crtc_destroy_state,
.set_crc_source = amdgpu_dm_crtc_set_crc_source((void *)0),
.verify_crc_source = amdgpu_dm_crtc_verify_crc_source((void *)0),
.get_crc_sources = amdgpu_dm_crtc_get_crc_sources((void *)0),
.get_vblank_counter = amdgpu_get_vblank_counter_kms,
.enable_vblank = dm_enable_vblank,
.disable_vblank = dm_disable_vblank,
.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
5012};

5014static enum drm_connector_status
5015amdgpu_dm_connector_detect(struct drm_connector *connector, bool_Bool force)
5016{
bool_Bool connected;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

/*
* Notes:
* 1. This interface is NOT called in context of HPD irq.
* 2. This interface *is called* in context of user-mode ioctl. Which
* makes it a bad place for *any* MST-related activity.
*/

if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
   !aconnector->fake_enable)
connected = (aconnector->dc_sink != NULL((void *)0));
else
connected = (aconnector->base.force == DRM_FORCE_ON);

update_subconnector_property(aconnector);

return (connected ? connector_status_connected :
	connector_status_disconnected);
5037}

5039int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
			    struct drm_connector_state *connector_state,
			    struct drm_property *property,
			    uint64_t val)
5043{
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_connector_state *dm_old_state =
to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});
struct dm_connector_state *dm_new_state =
to_dm_connector_state(connector_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector_state)); (struct dm_connector_state *)
( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

int ret = -EINVAL22;

if (property == dev->mode_config.scaling_mode_property) {
enum amdgpu_rmx_type rmx_type;

switch (val) {
case DRM_MODE_SCALE_CENTER2:
	rmx_type = RMX_CENTER;
	break;
case DRM_MODE_SCALE_ASPECT3:
	rmx_type = RMX_ASPECT;
	break;
case DRM_MODE_SCALE_FULLSCREEN1:
	rmx_type = RMX_FULL;
	break;
case DRM_MODE_SCALE_NONE0:
default:
	rmx_type = RMX_OFF;
	break;
}

if (dm_old_state->scaling == rmx_type)
	return 0;

dm_new_state->scaling = rmx_type;
ret = 0;
} else if (property == adev->mode_info.underscan_hborder_property) {
dm_new_state->underscan_hborder = val;
ret = 0;
} else if (property == adev->mode_info.underscan_vborder_property) {
dm_new_state->underscan_vborder = val;
ret = 0;
} else if (property == adev->mode_info.underscan_property) {
dm_new_state->underscan_enable = val;
ret = 0;
} else if (property == adev->mode_info.abm_level_property) {
dm_new_state->abm_level = val;
ret = 0;
}

return ret;
5092}

5094int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
			    const struct drm_connector_state *state,
			    struct drm_property *property,
			    uint64_t *val)
5098{
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_connector_state *dm_state =
to_dm_connector_state(state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((state)); (struct dm_connector_state *)( (char *)
__mptr - __builtin_offsetof(struct dm_connector_state, base) )
;});
int ret = -EINVAL22;

if (property == dev->mode_config.scaling_mode_property) {
switch (dm_state->scaling) {
case RMX_CENTER:
	*val = DRM_MODE_SCALE_CENTER2;
	break;
case RMX_ASPECT:
	*val = DRM_MODE_SCALE_ASPECT3;
	break;
case RMX_FULL:
	*val = DRM_MODE_SCALE_FULLSCREEN1;
	break;
case RMX_OFF:
default:
	*val = DRM_MODE_SCALE_NONE0;
	break;
}
ret = 0;
} else if (property == adev->mode_info.underscan_hborder_property) {
*val = dm_state->underscan_hborder;
ret = 0;
} else if (property == adev->mode_info.underscan_vborder_property) {
*val = dm_state->underscan_vborder;
ret = 0;
} else if (property == adev->mode_info.underscan_property) {
*val = dm_state->underscan_enable;
ret = 0;
} else if (property == adev->mode_info.abm_level_property) {
*val = dm_state->abm_level;
ret = 0;
}

return ret;
5137}

5139static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
5140{
struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
5144}

5146static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
5147{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
const struct dc_link *link = aconnector->dc_link;
struct amdgpu_device *adev = drm_to_adev(connector->dev);
struct amdgpu_display_manager *dm = &adev->dm;

/*
* Call only if mst_mgr was iniitalized before since it's not done
* for all connector types.
*/
if (aconnector->mst_mgr.dev)
drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);

5160#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE1) ||\
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)

if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
   link->type != dc_connection_none &&
   dm->backlight_dev) {
backlight_device_unregister(dm->backlight_dev);
dm->backlight_dev = NULL((void *)0);
}
5169#endif

if (aconnector->dc_em_sink)
dc_sink_release(aconnector->dc_em_sink);
aconnector->dc_em_sink = NULL((void *)0);
if (aconnector->dc_sink)
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL((void *)0);

drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
drm_connector_unregister(connector);
drm_connector_cleanup(connector);
if (aconnector->i2c) {
i2c_del_adapter(&aconnector->i2c->base);
kfree(aconnector->i2c);
}
kfree(aconnector->dm_dp_aux.aux.name);

kfree(connector);
5188}

5190void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
5191{
struct dm_connector_state *state =
to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

if (connector->state)
__drm_atomic_helper_connector_destroy_state(connector->state);

kfree(state);

state = kzalloc(sizeof(*state), GFP_KERNEL(0x0001 | 0x0004));

if (state) {
state->scaling = RMX_OFF;
state->underscan_enable = false0;
state->underscan_hborder = 0;
state->underscan_vborder = 0;
state->base.max_requested_bpc = 8;
state->vcpi_slots = 0;
state->pbn = 0;
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14)
	state->abm_level = amdgpu_dm_abm_level;

__drm_atomic_helper_connector_reset(connector, &state->base);
}
5215}

5217struct drm_connector_state *
5218amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
5219{
struct dm_connector_state *state =
to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

struct dm_connector_state *new_state =
	kmemdup(state, sizeof(*state), GFP_KERNEL(0x0001 | 0x0004));

if (!new_state)
return NULL((void *)0);

__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);

new_state->freesync_capable = state->freesync_capable;
new_state->abm_level = state->abm_level;
new_state->scaling = state->scaling;
new_state->underscan_enable = state->underscan_enable;
new_state->underscan_hborder = state->underscan_hborder;
new_state->underscan_vborder = state->underscan_vborder;
new_state->vcpi_slots = state->vcpi_slots;
new_state->pbn = state->pbn;
return &new_state->base;
5240}

5242static int
5243amdgpu_dm_connector_late_register(struct drm_connector *connector)
5244{
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
int r;

if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort10) ||
   (connector->connector_type == DRM_MODE_CONNECTOR_eDP14)) {
amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
if (r)
	return r;
}

5257#if defined(CONFIG_DEBUG_FS)
connector_debugfs_init(amdgpu_dm_connector);
5259#endif

return 0;
5262}

5264static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
.reset = amdgpu_dm_connector_funcs_reset,
.detect = amdgpu_dm_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = amdgpu_dm_connector_destroy,
.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
.atomic_get_property = amdgpu_dm_connector_atomic_get_property,
.late_register = amdgpu_dm_connector_late_register,
.early_unregister = amdgpu_dm_connector_unregister
5275};

5277static int get_modes(struct drm_connector *connector)
5278{
return amdgpu_dm_connector_get_modes(connector);
1
Calling 'amdgpu_dm_connector_get_modes'→
5280}

5282static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
5283{
struct dc_sink_init_data init_params = {
	.link = aconnector->dc_link,
	.sink_signal = SIGNAL_TYPE_VIRTUAL
};
struct edid *edid;

if (!aconnector->base.edid_blob_ptr) {
DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",__drm_err("No EDID firmware found on connector: %s ,forcing to OFF!\n"
, aconnector->base.name)
		aconnector->base.name)__drm_err("No EDID firmware found on connector: %s ,forcing to OFF!\n"
, aconnector->base.name);

aconnector->base.force = DRM_FORCE_OFF;
aconnector->base.override_edid = false0;
return;
}

edid = (struct edid *) aconnector->base.edid_blob_ptr->data;

aconnector->edid = edid;

aconnector->dc_em_sink = dc_link_add_remote_sink(
aconnector->dc_link,
(uint8_t *)edid,
(edid->extensions + 1) * EDID_LENGTH128,
&init_params);

if (aconnector->base.force == DRM_FORCE_ON) {
aconnector->dc_sink = aconnector->dc_link->local_sink ?
aconnector->dc_link->local_sink :
aconnector->dc_em_sink;
dc_sink_retain(aconnector->dc_sink);
}
5315}

5317static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
5318{
struct dc_link *link = (struct dc_link *)aconnector->dc_link;

/*
* In case of headless boot with force on for DP managed connector
* Those settings have to be != 0 to get initial modeset
*/
if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
}


aconnector->base.override_edid = true1;
create_eml_sink(aconnector);
5333}

5335static struct dc_stream_state *
5336create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
		const struct drm_display_mode *drm_mode,
		const struct dm_connector_state *dm_state,
		const struct dc_stream_state *old_stream)
5340{
struct drm_connector *connector = &aconnector->base;
struct amdgpu_device *adev = drm_to_adev(connector->dev);
struct dc_stream_state *stream;
const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL((void *)0);
int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
enum dc_status dc_result = DC_OK;

do {
stream = create_stream_for_sink(aconnector, drm_mode,
				dm_state, old_stream,
				requested_bpc);
if (stream == NULL((void *)0)) {
	DRM_ERROR("Failed to create stream for sink!\n")__drm_err("Failed to create stream for sink!\n");
	break;
}

dc_result = dc_validate_stream(adev->dm.dc, stream);

if (dc_result != DC_OK) {
	DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",__drm_dbg(DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      drm_mode->hdisplay,__drm_dbg(DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      drm_mode->vdisplay,__drm_dbg(DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      drm_mode->clock,__drm_dbg(DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      dc_result,__drm_dbg(DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      dc_status_to_str(dc_result))__drm_dbg(DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result));

	dc_stream_release(stream);
	stream = NULL((void *)0);
	requested_bpc -= 2; /* lower bpc to retry validation */
}

} while (stream == NULL((void *)0) && requested_bpc >= 6);

if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n")__drm_dbg(DRM_UT_KMS, "Retry forcing YCbCr420 encoding\n");

aconnector->force_yuv420_output = true1;
stream = create_validate_stream_for_sink(aconnector, drm_mode,
				dm_state, old_stream);
aconnector->force_yuv420_output = false0;
}

return stream;
5384}

5386enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
		   struct drm_display_mode *mode)
5388{
int result = MODE_ERROR;
struct dc_sink *dc_sink;
/* TODO: Unhardcode stream count */
struct dc_stream_state *stream;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if ((mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) ||
	(mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5)))
return result;

/*
* Only run this the first time mode_valid is called to initilialize
* EDID mgmt
*/
if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
!aconnector->dc_em_sink)
handle_edid_mgmt(aconnector);

dc_sink = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );})->dc_sink;

if (dc_sink == NULL((void *)0)) {
DRM_ERROR("dc_sink is NULL!\n")__drm_err("dc_sink is NULL!\n");
goto fail;
}

stream = create_validate_stream_for_sink(aconnector, mode, NULL((void *)0), NULL((void *)0));
if (stream) {
dc_stream_release(stream);
result = MODE_OK;
}

5420fail:
/* TODO: error handling*/
return result;
5423}

5425static int fill_hdr_info_packet(const struct drm_connector_state *state,
		struct dc_info_packet *out)
5427{
struct hdmi_drm_infoframe frame;
unsigned char buf[30]; /* 26 + 4 */
ssize_t len;
int ret, i;

memset(out, 0, sizeof(*out))__builtin_memset((out), (0), (sizeof(*out)));

if (!state->hdr_output_metadata)
return 0;

ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
if (ret)
return ret;

len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
if (len < 0)
return (int)len;

/* Static metadata is a fixed 26 bytes + 4 byte header. */
if (len != 30)
return -EINVAL22;

/* Prepare the infopacket for DC. */
switch (state->connector->connector_type) {
case DRM_MODE_CONNECTOR_HDMIA11:
out->hb0 = 0x87; /* type */
out->hb1 = 0x01; /* version */
out->hb2 = 0x1A; /* length */
out->sb[0] = buf[3]; /* checksum */
i = 1;
break;

case DRM_MODE_CONNECTOR_DisplayPort10:
case DRM_MODE_CONNECTOR_eDP14:
out->hb0 = 0x00; /* sdp id, zero */
out->hb1 = 0x87; /* type */
out->hb2 = 0x1D; /* payload len - 1 */
out->hb3 = (0x13 << 2); /* sdp version */
out->sb[0] = 0x01; /* version */
out->sb[1] = 0x1A; /* length */
i = 2;
break;

default:
return -EINVAL22;
}

memcpy(&out->sb[i], &buf[4], 26)__builtin_memcpy((&out->sb[i]), (&buf[4]), (26));
out->valid = true1;

print_hex_dump(KERN_DEBUG"\0017", "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
       sizeof(out->sb), false0);

return 0;
5482}

5484static bool_Bool
5485is_hdr_metadata_different(const struct drm_connector_state *old_state,
	  const struct drm_connector_state *new_state)
5487{
struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
struct drm_property_blob *new_blob = new_state->hdr_output_metadata;

if (old_blob != new_blob) {
if (old_blob && new_blob &&
    old_blob->length == new_blob->length)
	return memcmp(old_blob->data, new_blob->data,__builtin_memcmp((old_blob->data), (new_blob->data), (old_blob
->length))
		      old_blob->length)__builtin_memcmp((old_blob->data), (new_blob->data), (old_blob
->length));

return true1;
}

return false0;
5501}

5503static int
5504amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
		 struct drm_atomic_state *state)
5506{
struct drm_connector_state *new_con_state =
drm_atomic_get_new_connector_state(state, conn);
struct drm_connector_state *old_con_state =
drm_atomic_get_old_connector_state(state, conn);
struct drm_crtc *crtc = new_con_state->crtc;
struct drm_crtc_state *new_crtc_state;
int ret;

if (!crtc)
return 0;

if (is_hdr_metadata_different(old_con_state, new_con_state)) {
struct dc_info_packet hdr_infopacket;

ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
if (ret)
	return ret;

new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
if (IS_ERR(new_crtc_state))
	return PTR_ERR(new_crtc_state);

/*
 * DC considers the stream backends changed if the
 * static metadata changes. Forcing the modeset also
 * gives a simple way for userspace to switch from
 * 8bpc to 10bpc when setting the metadata to enter
 * or exit HDR.
 *
 * Changing the static metadata after it's been
 * set is permissible, however. So only force a
 * modeset if we're entering or exiting HDR.
 */
new_crtc_state->mode_changed =
	!old_con_state->hdr_output_metadata ||
	!new_con_state->hdr_output_metadata;
}

return 0;
5546}

5548static const struct drm_connector_helper_funcs
5549amdgpu_dm_connector_helper_funcs = {
/*
* If hotplugging a second bigger display in FB Con mode, bigger resolution
* modes will be filtered by drm_mode_validate_size(), and those modes
* are missing after user start lightdm. So we need to renew modes list.
* in get_modes call back, not just return the modes count
*/
.get_modes = get_modes,
.mode_valid = amdgpu_dm_connector_mode_valid,
.atomic_check = amdgpu_dm_connector_atomic_check,
5559};

5561static void dm_crtc_helper_disable(struct drm_crtc *crtc)
5562{
5563}

5565static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
5566{
struct drm_atomic_state *state = new_crtc_state->state;
struct drm_plane *plane;
int num_active = 0;

drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask)for ((plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)->
head ) *__mptr = ((&(state->dev)->mode_config.plane_list
)->next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*(plane)), head) );}); &(plane)->head != (&
(state->dev)->mode_config.plane_list); (plane) = ({ const
 __typeof( ((__typeof(*(plane)) *)0)->head ) *__mptr = ((plane
)->head.next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*(plane)), head) );})) if (!((new_crtc_state->plane_mask
) & drm_plane_mask(plane))) {} else {
struct drm_plane_state *new_plane_state;

/* Cursor planes are "fake". */
if (plane->type == DRM_PLANE_TYPE_CURSOR)
	continue;

new_plane_state = drm_atomic_get_new_plane_state(state, plane);

if (!new_plane_state) {
	/*
	 * The plane is enable on the CRTC and hasn't changed
	 * state. This means that it previously passed
	 * validation and is therefore enabled.
	 */
	num_active += 1;
	continue;
}

/* We need a framebuffer to be considered enabled. */
num_active += (new_plane_state->fb != NULL((void *)0));
}

return num_active;
5595}

5597static void dm_update_crtc_active_planes(struct drm_crtc *crtc,
			 struct drm_crtc_state *new_crtc_state)
5599{
struct dm_crtc_state *dm_new_crtc_state =
to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

dm_new_crtc_state->active_planes = 0;

if (!dm_new_crtc_state->stream)
return;

dm_new_crtc_state->active_planes =
count_crtc_active_planes(new_crtc_state);
5610}

5612static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
		       struct drm_crtc_state *state)
5614{
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
struct dc *dc = adev->dm.dc;
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_crtc_state, base) );});
int ret = -EINVAL22;

dm_update_crtc_active_planes(crtc, state);

if (unlikely(!dm_crtc_state->stream &&__builtin_expect(!!(!dm_crtc_state->stream && modeset_required
(state, ((void *)0), dm_crtc_state->stream)), 0)
     modeset_required(state, NULL, dm_crtc_state->stream))__builtin_expect(!!(!dm_crtc_state->stream && modeset_required
(state, ((void *)0), dm_crtc_state->stream)), 0)) {
WARN_ON(1)({ int __ret = !!(1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "1", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 5624); __builtin_expect(!!(__ret), 0); });
return ret;
}

/*
* We require the primary plane to be enabled whenever the CRTC is, otherwise
* drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
* planes are disabled, which is not supported by the hardware. And there is legacy
* userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
*/
if (state->enable &&
   !(state->plane_mask & drm_plane_mask(crtc->primary)))
return -EINVAL22;

/* In some use cases, like reset, no stream is attached */
if (!dm_crtc_state->stream)
return 0;

if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
return 0;

return ret;
5646}

5648static bool_Bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
		      const struct drm_display_mode *mode,
		      struct drm_display_mode *adjusted_mode)
5651{
return true1;
5653}

5655static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
.disable = dm_crtc_helper_disable,
.atomic_check = dm_crtc_helper_atomic_check,
.mode_fixup = dm_crtc_helper_mode_fixup,
.get_scanout_position = amdgpu_crtc_get_scanout_position,
5660};

5662static void dm_encoder_helper_disable(struct drm_encoder *encoder)
5663{

5665}

5667static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth)
5668{
switch (display_color_depth) {
case COLOR_DEPTH_666:
	return 6;
case COLOR_DEPTH_888:
	return 8;
case COLOR_DEPTH_101010:
	return 10;
case COLOR_DEPTH_121212:
	return 12;
case COLOR_DEPTH_141414:
	return 14;
case COLOR_DEPTH_161616:
	return 16;
default:
	break;
}
return 0;
5686}

5688static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
			  struct drm_crtc_state *crtc_state,
			  struct drm_connector_state *conn_state)
5691{
struct drm_atomic_state *state = crtc_state->state;
struct drm_connector *connector = conn_state->connector;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((conn_state)); (struct dm_connector_state *)( (char
 *)__mptr - __builtin_offsetof(struct dm_connector_state, base
) );});
const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
struct drm_dp_mst_topology_mgr *mst_mgr;
struct drm_dp_mst_port *mst_port;
enum dc_color_depth color_depth;
int clock, bpp = 0;
bool_Bool is_y420 = false0;

if (!aconnector->port || !aconnector->dc_sink)
return 0;

mst_port = aconnector->port;
mst_mgr = &aconnector->mst_port->mst_mgr;

if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
return 0;

if (!state->duplicated) {
int max_bpc = conn_state->max_requested_bpc;
is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
		aconnector->force_yuv420_output;
color_depth = convert_color_depth_from_display_info(connector,
						    is_y420,
						    max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false0);
}
dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state,
							   mst_mgr,
							   mst_port,
							   dm_new_connector_state->pbn,
							   dm_mst_get_pbn_divider(aconnector->dc_link));
if (dm_new_connector_state->vcpi_slots < 0) {
DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots)__drm_dbg(DRM_UT_ATOMIC, "failed finding vcpi slots: %d\n", (
int)dm_new_connector_state->vcpi_slots);
return dm_new_connector_state->vcpi_slots;
}
return 0;
5733}

5735const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
.disable = dm_encoder_helper_disable,
.atomic_check = dm_encoder_helper_atomic_check
5738};

5740#if defined(CONFIG_DRM_AMD_DC_DCN1)
5741static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
			    struct dc_state *dc_state)
5743{
struct dc_stream_state *stream = NULL((void *)0);
struct drm_connector *connector;
struct drm_connector_state *new_con_state, *old_con_state;
struct amdgpu_dm_connector *aconnector;
struct dm_connector_state *dm_conn_state;
int i, j, clock, bpp;
int vcpi, pbn_div, pbn = 0;

for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {

aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (!aconnector->port)
	continue;

if (!new_con_state || !new_con_state->crtc)
	continue;

dm_conn_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});

for (j = 0; j < dc_state->stream_count; j++) {
	stream = dc_state->streams[j];
	if (!stream)
		continue;

	if ((struct amdgpu_dm_connector*)stream->dm_stream_context == aconnector)
		break;

	stream = NULL((void *)0);
}

if (!stream)
	continue;

if (stream->timing.flags.DSC != 1) {
	drm_dp_mst_atomic_enable_dsc(state,
				     aconnector->port,
				     dm_conn_state->pbn,
				     0,
				     false0);
	continue;
}

pbn_div = dm_mst_get_pbn_divider(stream->link);
bpp = stream->timing.dsc_cfg.bits_per_pixel;
clock = stream->timing.pix_clk_100hz / 10;
pbn = drm_dp_calc_pbn_mode(clock, bpp, true1);
vcpi = drm_dp_mst_atomic_enable_dsc(state,
				    aconnector->port,
				    pbn, pbn_div,
				    true1);
if (vcpi < 0)
	return vcpi;

dm_conn_state->pbn = pbn;
dm_conn_state->vcpi_slots = vcpi;
}
return 0;
5802}
5803#endif

5805static void dm_drm_plane_reset(struct drm_plane *plane)
5806{
struct dm_plane_state *amdgpu_state = NULL((void *)0);

if (plane->state)
plane->funcs->atomic_destroy_state(plane, plane->state);

amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL(0x0001 | 0x0004));
WARN_ON(amdgpu_state == NULL)({ int __ret = !!(amdgpu_state == ((void *)0)); if (__ret) printf
("WARNING %s failed at %s:%d\n", "amdgpu_state == ((void *)0)"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 5813); __builtin_expect(!!(__ret), 0); });

if (amdgpu_state)
__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
5817}

5819static struct drm_plane_state *
5820dm_drm_plane_duplicate_state(struct drm_plane *plane)
5821{
struct dm_plane_state *dm_plane_state, *old_dm_plane_state;

old_dm_plane_state = to_dm_plane_state(plane->state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (plane->state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});
dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL(0x0001 | 0x0004));
if (!dm_plane_state)
return NULL((void *)0);

__drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);

if (old_dm_plane_state->dc_state) {
dm_plane_state->dc_state = old_dm_plane_state->dc_state;
dc_plane_state_retain(dm_plane_state->dc_state);
}

/* Framebuffer hasn't been updated yet, so retain old flags. */
dm_plane_state->tiling_flags = old_dm_plane_state->tiling_flags;
dm_plane_state->tmz_surface = old_dm_plane_state->tmz_surface;

return &dm_plane_state->base;
5841}

5843static void dm_drm_plane_destroy_state(struct drm_plane *plane,
		struct drm_plane_state *state)
5845{
struct dm_plane_state *dm_plane_state = to_dm_plane_state(state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (state); (struct dm_plane_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_plane_state, base) );});

if (dm_plane_state->dc_state)
dc_plane_state_release(dm_plane_state->dc_state);

drm_atomic_helper_plane_destroy_state(plane, state);
5852}

5854static const struct drm_plane_funcs dm_plane_funcs = {
.update_plane	= drm_atomic_helper_update_plane,
.disable_plane	= drm_atomic_helper_disable_plane,
.destroy	= drm_primary_helper_destroy,
.reset = dm_drm_plane_reset,
.atomic_duplicate_state = dm_drm_plane_duplicate_state,
.atomic_destroy_state = dm_drm_plane_destroy_state,
5861};

5863static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
		      struct drm_plane_state *new_state)
5865{
struct amdgpu_framebuffer *afb;
struct drm_gem_object *obj;
struct amdgpu_device *adev;
struct amdgpu_bo *rbo;
struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
struct list_head list;
struct ttm_validate_buffer tv;
struct ww_acquire_ctx ticket;
uint32_t domain;
int r;

if (!new_state->fb) {
DRM_DEBUG_DRIVER("No FB bound\n")__drm_dbg(DRM_UT_DRIVER, "No FB bound\n");
return 0;
}

afb = to_amdgpu_framebuffer(new_state->fb)({ const __typeof( ((struct amdgpu_framebuffer *)0)->base )
 *__mptr = (new_state->fb); (struct amdgpu_framebuffer *)(
 (char *)__mptr - __builtin_offsetof(struct amdgpu_framebuffer
, base) );});
obj = new_state->fb->obj[0];
rbo = gem_to_amdgpu_bo(obj)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
 = ((obj)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );});
adev = amdgpu_ttm_adev(rbo->tbo.bdev);
INIT_LIST_HEAD(&list);

tv.bo = &rbo->tbo;
tv.num_shared = 1;
list_add(&tv.head, &list);

r = ttm_eu_reserve_buffers(&ticket, &list, false0, NULL((void *)0));
if (r) {
dev_err(adev->dev, "fail to reserve bo (%d)\n", r)printf("drm:pid%d:%s *ERROR* " "fail to reserve bo (%d)\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

if (plane->type != DRM_PLANE_TYPE_CURSOR)
domain = amdgpu_display_supported_domains(adev, rbo->flags);
else
domain = AMDGPU_GEM_DOMAIN_VRAM0x4;

r = amdgpu_bo_pin(rbo, domain);
if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) {
if (r != -ERESTARTSYS4)
	DRM_ERROR("Failed to pin framebuffer with error %d\n", r)__drm_err("Failed to pin framebuffer with error %d\n", r);
ttm_eu_backoff_reservation(&ticket, &list);
return r;
}

r = amdgpu_ttm_alloc_gart(&rbo->tbo);
if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) {
amdgpu_bo_unpin(rbo);
ttm_eu_backoff_reservation(&ticket, &list);
DRM_ERROR("%p bind failed\n", rbo)__drm_err("%p bind failed\n", rbo);
return r;
}

ttm_eu_backoff_reservation(&ticket, &list);

afb->address = amdgpu_bo_gpu_offset(rbo);

amdgpu_bo_ref(rbo);

/**
* We don't do surface updates on planes that have been newly created,
* but we also don't have the afb->address during atomic check.
*
* Fill in buffer attributes depending on the address here, but only on
* newly created planes since they're not being used by DC yet and this
* won't modify global state.
*/
dm_plane_state_old = to_dm_plane_state(plane->state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (plane->state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});
dm_plane_state_new = to_dm_plane_state(new_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_state); (struct dm_plane_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_plane_state, base) );});

if (dm_plane_state_new->dc_state &&
   dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
struct dc_plane_state *plane_state =
	dm_plane_state_new->dc_state;
bool_Bool force_disable_dcc = !plane_state->dcc.enable;

fill_plane_buffer_attributes(
	adev, afb, plane_state->format, plane_state->rotation,
	dm_plane_state_new->tiling_flags,
	&plane_state->tiling_info, &plane_state->plane_size,
	&plane_state->dcc, &plane_state->address,
	dm_plane_state_new->tmz_surface, force_disable_dcc);
}

return 0;
5951}

5953static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
		       struct drm_plane_state *old_state)
5955{
struct amdgpu_bo *rbo;
int r;

if (!old_state->fb)
return;

rbo = gem_to_amdgpu_bo(old_state->fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
 = ((old_state->fb->obj[0])); (struct amdgpu_bo *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_bo, tbo.base) );
});
r = amdgpu_bo_reserve(rbo, false0);
if (unlikely(r)__builtin_expect(!!(r), 0)) {
DRM_ERROR("failed to reserve rbo before unpin\n")__drm_err("failed to reserve rbo before unpin\n");
return;
}

amdgpu_bo_unpin(rbo);
amdgpu_bo_unreserve(rbo);
amdgpu_bo_unref(&rbo);
5972}

5974static int dm_plane_helper_check_state(struct drm_plane_state *state,
		       struct drm_crtc_state *new_crtc_state)
5976{
int max_downscale = 0;
int max_upscale = INT_MAX0x7fffffff;

/* TODO: These should be checked against DC plane caps */
return drm_atomic_helper_check_plane_state(
state, new_crtc_state, max_downscale, max_upscale, true1, true1);
5983}

5985static int dm_plane_atomic_check(struct drm_plane *plane,
		 struct drm_plane_state *state)
5987{
struct amdgpu_device *adev = drm_to_adev(plane->dev);
struct dc *dc = adev->dm.dc;
struct dm_plane_state *dm_plane_state;
struct dc_scaling_info scaling_info;
struct drm_crtc_state *new_crtc_state;
int ret;

dm_plane_state = to_dm_plane_state(state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (state); (struct dm_plane_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_plane_state, base) );});

if (!dm_plane_state->dc_state)
return 0;

new_crtc_state =
drm_atomic_get_new_crtc_state(state->state, state->crtc);
if (!new_crtc_state)
return -EINVAL22;

ret = dm_plane_helper_check_state(state, new_crtc_state);
if (ret)
return ret;

ret = fill_dc_scaling_info(state, &scaling_info);
if (ret)
return ret;

if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
return 0;

return -EINVAL22;
6017}

6019static int dm_plane_atomic_async_check(struct drm_plane *plane,
		       struct drm_plane_state *new_plane_state)
6021{
/* Only support async updates on cursor planes. */
if (plane->type != DRM_PLANE_TYPE_CURSOR)
return -EINVAL22;

return 0;
6027}

6029static void dm_plane_atomic_async_update(struct drm_plane *plane,
			 struct drm_plane_state *new_state)
6031{
struct drm_plane_state *old_state =
drm_atomic_get_old_plane_state(new_state->state, plane);

swap(plane->state->fb, new_state->fb)do { __typeof(plane->state->fb) __tmp = (plane->state
->fb); (plane->state->fb) = (new_state->fb); (new_state
->fb) = __tmp; } while(0);

plane->state->src_x = new_state->src_x;
plane->state->src_y = new_state->src_y;
plane->state->src_w = new_state->src_w;
plane->state->src_h = new_state->src_h;
plane->state->crtc_x = new_state->crtc_x;
plane->state->crtc_y = new_state->crtc_y;
plane->state->crtc_w = new_state->crtc_w;
plane->state->crtc_h = new_state->crtc_h;

handle_cursor_update(plane, old_state);
6047}

6049static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
.prepare_fb = dm_plane_helper_prepare_fb,
.cleanup_fb = dm_plane_helper_cleanup_fb,
.atomic_check = dm_plane_atomic_check,
.atomic_async_check = dm_plane_atomic_async_check,
.atomic_async_update = dm_plane_atomic_async_update
6055};

6057/*
* TODO: these are currently initialized to rgb formats only.
* For future use cases we should either initialize them dynamically based on
* plane capabilities, or initialize this array to all formats, so internal drm
* check will succeed, and let DC implement proper check
*/
6063static const uint32_t rgb_formats[] = {
DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_RGBA8888((__u32)('R') | ((__u32)('A') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)),
DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)),
DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)),
DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)),
DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
 16) | ((__u32)('6') << 24)),
6074};

6076static const uint32_t overlay_formats[] = {
DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_RGBA8888((__u32)('R') | ((__u32)('A') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)),
DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
 16) | ((__u32)('6') << 24))
6083};

6085static const u32 cursor_formats[] = {
DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24))
6087};

6089static int get_plane_formats(const struct drm_plane *plane,
	     const struct dc_plane_cap *plane_cap,
	     uint32_t *formats, int max_formats)
6092{
int i, num_formats = 0;

/*
* TODO: Query support for each group of formats directly from
* DC plane caps. This will require adding more formats to the
* caps list.
*/

switch (plane->type) {
case DRM_PLANE_TYPE_PRIMARY:
for (i = 0; i < ARRAY_SIZE(rgb_formats)(sizeof((rgb_formats)) / sizeof((rgb_formats)[0])); ++i) {
	if (num_formats >= max_formats)
		break;

	formats[num_formats++] = rgb_formats[i];
}

if (plane_cap && plane_cap->pixel_format_support.nv12)
	formats[num_formats++] = DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
 16) | ((__u32)('2') << 24));
if (plane_cap && plane_cap->pixel_format_support.p010)
	formats[num_formats++] = DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
 16) | ((__u32)('0') << 24));
if (plane_cap && plane_cap->pixel_format_support.fp16) {
	formats[num_formats++] = DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24));
	formats[num_formats++] = DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24));
	formats[num_formats++] = DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24));
	formats[num_formats++] = DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24));
}
break;

case DRM_PLANE_TYPE_OVERLAY:
for (i = 0; i < ARRAY_SIZE(overlay_formats)(sizeof((overlay_formats)) / sizeof((overlay_formats)[0])); ++i) {
	if (num_formats >= max_formats)
		break;

	formats[num_formats++] = overlay_formats[i];
}
break;

case DRM_PLANE_TYPE_CURSOR:
for (i = 0; i < ARRAY_SIZE(cursor_formats)(sizeof((cursor_formats)) / sizeof((cursor_formats)[0])); ++i) {
	if (num_formats >= max_formats)
		break;

	formats[num_formats++] = cursor_formats[i];
}
break;
}

return num_formats;
6142}

6144static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
		struct drm_plane *plane,
		unsigned long possible_crtcs,
		const struct dc_plane_cap *plane_cap)
6148{
uint32_t formats[32];
int num_formats;
int res = -EPERM1;
unsigned int supported_rotations;

num_formats = get_plane_formats(plane, plane_cap, formats,
			ARRAY_SIZE(formats)(sizeof((formats)) / sizeof((formats)[0])));

res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs,
		       &dm_plane_funcs, formats, num_formats,
		       NULL((void *)0), plane->type, NULL((void *)0));
if (res)
return res;

if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
   plane_cap && plane_cap->per_pixel_alpha) {
unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE)(1UL << (2)) |
			  BIT(DRM_MODE_BLEND_PREMULTI)(1UL << (0));

drm_plane_create_alpha_property(plane);
drm_plane_create_blend_mode_property(plane, blend_caps);
}

if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
   plane_cap &&
   (plane_cap->pixel_format_support.nv12 ||
    plane_cap->pixel_format_support.p010)) {
/* This only affects YUV formats. */
drm_plane_create_color_properties(
	plane,
	BIT(DRM_COLOR_YCBCR_BT601)(1UL << (DRM_COLOR_YCBCR_BT601)) |
	BIT(DRM_COLOR_YCBCR_BT709)(1UL << (DRM_COLOR_YCBCR_BT709)) |
	BIT(DRM_COLOR_YCBCR_BT2020)(1UL << (DRM_COLOR_YCBCR_BT2020)),
	BIT(DRM_COLOR_YCBCR_LIMITED_RANGE)(1UL << (DRM_COLOR_YCBCR_LIMITED_RANGE)) |
	BIT(DRM_COLOR_YCBCR_FULL_RANGE)(1UL << (DRM_COLOR_YCBCR_FULL_RANGE)),
	DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
}

supported_rotations =
DRM_MODE_ROTATE_0(1<<0) | DRM_MODE_ROTATE_90(1<<1) |
DRM_MODE_ROTATE_180(1<<2) | DRM_MODE_ROTATE_270(1<<3);

if (dm->adev->asic_type >= CHIP_BONAIRE)
drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0(1<<0),
				   supported_rotations);

drm_plane_helper_add(plane, &dm_plane_helper_funcs);

/* Create (reset) the plane state */
if (plane->funcs->reset)
plane->funcs->reset(plane);

return 0;
6202}

6204static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
	       struct drm_plane *plane,
	       uint32_t crtc_index)
6207{
struct amdgpu_crtc *acrtc = NULL((void *)0);
struct drm_plane *cursor_plane;

int res = -ENOMEM12;

cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL(0x0001 | 0x0004));
if (!cursor_plane)
goto fail;

cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL((void *)0));

acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL(0x0001 | 0x0004));
if (!acrtc)
goto fail;

res = drm_crtc_init_with_planes(
	dm->ddev,
	&acrtc->base,
	plane,
	cursor_plane,
	&amdgpu_dm_crtc_funcs, NULL((void *)0));

if (res)
goto fail;

drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);

/* Create (reset) the plane state */
if (acrtc->base.funcs->reset)
acrtc->base.funcs->reset(&acrtc->base);

acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;

acrtc->crtc_id = crtc_index;
acrtc->base.enabled = false0;
acrtc->otg_inst = -1;

dm->adev->mode_info.crtcs[crtc_index] = acrtc;
drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES4096,
		   true1, MAX_COLOR_LUT_ENTRIES4096);
drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES256);

return 0;

6254fail:
kfree(acrtc);
kfree(cursor_plane);
return res;
6258}


6261static int to_drm_connector_type(enum amd_signal_type st)
6262{
switch (st) {
case SIGNAL_TYPE_HDMI_TYPE_A:
return DRM_MODE_CONNECTOR_HDMIA11;
case SIGNAL_TYPE_EDP:
return DRM_MODE_CONNECTOR_eDP14;
case SIGNAL_TYPE_LVDS:
return DRM_MODE_CONNECTOR_LVDS7;
case SIGNAL_TYPE_RGB:
return DRM_MODE_CONNECTOR_VGA1;
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
return DRM_MODE_CONNECTOR_DisplayPort10;
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_DVI_SINGLE_LINK:
return DRM_MODE_CONNECTOR_DVID3;
case SIGNAL_TYPE_VIRTUAL:
return DRM_MODE_CONNECTOR_VIRTUAL15;

default:
return DRM_MODE_CONNECTOR_Unknown0;
}
6284}

6286static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6287{
struct drm_encoder *encoder;

/* There is only one encoder per connector */
drm_connector_for_each_possible_encoder(connector, encoder)for ((encoder) = ({ const __typeof( ((__typeof(*(encoder)) *)
0)->head ) *__mptr = ((&((connector)->dev)->mode_config
.encoder_list)->next); (__typeof(*(encoder)) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*(encoder)), head) );}); &
(encoder)->head != (&((connector)->dev)->mode_config
.encoder_list); (encoder) = ({ const __typeof( ((__typeof(*(encoder
)) *)0)->head ) *__mptr = ((encoder)->head.next); (__typeof
(*(encoder)) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*(encoder)), head) );})) if (!(((connector)->possible_encoders
) & drm_encoder_mask(encoder))) {} else
return encoder;

return NULL((void *)0);
6295}

6297static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6298{
struct drm_encoder *encoder;
struct amdgpu_encoder *amdgpu_encoder;

encoder = amdgpu_dm_connector_to_encoder(connector);

if (encoder == NULL((void *)0))
return;

amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
 = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});

amdgpu_encoder->native_mode.clock = 0;

if (!list_empty(&connector->probed_modes)) {
struct drm_display_mode *preferred_mode = NULL((void *)0);

list_for_each_entry(preferred_mode,for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode
) *)0)->head ) *__mptr = ((&connector->probed_modes
)->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*preferred_mode), head) );}); &preferred_mode->
head != (&connector->probed_modes); preferred_mode = (
{ const __typeof( ((__typeof(*preferred_mode) *)0)->head )
 *__mptr = (preferred_mode->head.next); (__typeof(*preferred_mode
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode
), head) );}))
		    &connector->probed_modes,for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode
) *)0)->head ) *__mptr = ((&connector->probed_modes
)->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*preferred_mode), head) );}); &preferred_mode->
head != (&connector->probed_modes); preferred_mode = (
{ const __typeof( ((__typeof(*preferred_mode) *)0)->head )
 *__mptr = (preferred_mode->head.next); (__typeof(*preferred_mode
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode
), head) );}))
		    head)for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode
) *)0)->head ) *__mptr = ((&connector->probed_modes
)->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*preferred_mode), head) );}); &preferred_mode->
head != (&connector->probed_modes); preferred_mode = (
{ const __typeof( ((__typeof(*preferred_mode) *)0)->head )
 *__mptr = (preferred_mode->head.next); (__typeof(*preferred_mode
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode
), head) );})) {
	if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED(1<<3))
		amdgpu_encoder->native_mode = *preferred_mode;

	break;
}

}
6324}

6326static struct drm_display_mode *
6327amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
	     char *name,
	     int hdisplay, int vdisplay)
6330{
struct drm_device *dev = encoder->dev;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
 = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
struct drm_display_mode *mode = NULL((void *)0);
struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;

mode = drm_mode_duplicate(dev, native_mode);

if (mode == NULL((void *)0))
return NULL((void *)0);

mode->hdisplay = hdisplay;
mode->vdisplay = vdisplay;
mode->type &= ~DRM_MODE_TYPE_PREFERRED(1<<3);
6344#ifdef __linux__
strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN32);
6346#else
strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN32);
6348#endif

return mode;

6352}

6354static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
				 struct drm_connector *connector)
6356{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
 = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
6
←
'amdgpu_encoder' initialized to a null pointer value→
struct drm_display_mode *mode = NULL((void *)0);
struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7
←
'native_mode' initialized to a null pointer value→
struct amdgpu_dm_connector *amdgpu_dm_connector =
		to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
int i;
int n;
struct mode_size {
char name[DRM_DISPLAY_MODE_LEN32];
int w;
int h;
} common_modes[] = {
{  "640x480",  640,  480},
{  "800x600",  800,  600},
{ "1024x768", 1024,  768},
{ "1280x720", 1280,  720},
{ "1280x800", 1280,  800},
{"1280x1024", 1280, 1024},
{ "1440x900", 1440,  900},
{"1680x1050", 1680, 1050},
{"1600x1200", 1600, 1200},
{"1920x1080", 1920, 1080},
{"1920x1200", 1920, 1200}
};

n = ARRAY_SIZE(common_modes)(sizeof((common_modes)) / sizeof((common_modes)[0]));

for (i = 0; i < n; i++) {
8
←
Loop condition is true.  Entering loop body→
struct drm_display_mode *curmode = NULL((void *)0);
bool_Bool mode_existed = false0;

if (common_modes[i].w > native_mode->hdisplay ||
9
←
Access to field 'hdisplay' results in a dereference of a null pointer (loaded from variable 'native_mode')
    common_modes[i].h > native_mode->vdisplay ||
   (common_modes[i].w == native_mode->hdisplay &&
    common_modes[i].h == native_mode->vdisplay))
	continue;

list_for_each_entry(curmode, &connector->probed_modes, head)for (curmode = ({ const __typeof( ((__typeof(*curmode) *)0)->
head ) *__mptr = ((&connector->probed_modes)->next)
; (__typeof(*curmode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*curmode), head) );}); &curmode->head != (&
connector->probed_modes); curmode = ({ const __typeof( ((__typeof
(*curmode) *)0)->head ) *__mptr = (curmode->head.next);
 (__typeof(*curmode) *)( (char *)__mptr - __builtin_offsetof(
__typeof(*curmode), head) );})) {
	if (common_modes[i].w == curmode->hdisplay &&
	    common_modes[i].h == curmode->vdisplay) {
		mode_existed = true1;
		break;
	}
}

if (mode_existed)
	continue;

mode = amdgpu_dm_create_common_mode(encoder,
		common_modes[i].name, common_modes[i].w,
		common_modes[i].h);
drm_mode_probed_add(connector, mode);
amdgpu_dm_connector->num_modes++;
}
6411}

6413static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
			      struct edid *edid)
6415{
struct amdgpu_dm_connector *amdgpu_dm_connector =
	to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (edid) {
/* empty probed_modes */
INIT_LIST_HEAD(&connector->probed_modes);
amdgpu_dm_connector->num_modes =
		drm_add_edid_modes(connector, edid);

/* sorting the probed modes before calling function
 * amdgpu_dm_get_native_mode() since EDID can have
 * more than one preferred mode. The modes that are
 * later in the probed mode list could be of higher
 * and preferred resolution. For example, 3840x2160
 * resolution in base EDID preferred timing and 4096x2160
 * preferred resolution in DID extension block later.
 */
drm_mode_sort(&connector->probed_modes);
amdgpu_dm_get_native_mode(connector);
} else {
amdgpu_dm_connector->num_modes = 0;
}
6438}

6440static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
6441{
struct amdgpu_dm_connector *amdgpu_dm_connector =
	to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct drm_encoder *encoder;
struct edid *edid = amdgpu_dm_connector->edid;

encoder = amdgpu_dm_connector_to_encoder(connector);

if (!edid || !drm_edid_is_valid(edid)) {
2
←
Assuming 'edid' is non-null→
3
←
Assuming the condition is false→
4
←
Taking false branch→
amdgpu_dm_connector->num_modes =
		drm_add_modes_noedid(connector, 640, 480);
} else {
amdgpu_dm_connector_ddc_get_modes(connector, edid);
amdgpu_dm_connector_add_common_modes(encoder, connector);
5
←
Calling 'amdgpu_dm_connector_add_common_modes'→
}
amdgpu_dm_fbc_init(connector);

return amdgpu_dm_connector->num_modes;
6459}

6461void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
		     struct amdgpu_dm_connector *aconnector,
		     int connector_type,
		     struct dc_link *link,
		     int link_index)
6466{
struct amdgpu_device *adev = drm_to_adev(dm->ddev);

/*
* Some of the properties below require access to state, like bpc.
* Allocate some default initial connector state with our reset helper.
*/
if (aconnector->base.funcs->reset)
aconnector->base.funcs->reset(&aconnector->base);

aconnector->connector_id = link_index;
aconnector->dc_link = link;
aconnector->base.interlace_allowed = false0;
aconnector->base.doublescan_allowed = false0;
aconnector->base.stereo_allowed = false0;
aconnector->base.dpms = DRM_MODE_DPMS_OFF3;
aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
aconnector->audio_inst = -1;
rw_init(&aconnector->hpd_lock, "dmhpd")_rw_init_flags(&aconnector->hpd_lock, "dmhpd", 0, ((void
 *)0));

/*
* configure support HPD hot plug connector_>polled default value is 0
* which means HPD hot plug not supported
*/
switch (connector_type) {
case DRM_MODE_CONNECTOR_HDMIA11:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD(1 << 0);
aconnector->base.ycbcr_420_allowed =
	link->link_enc->features.hdmi_ycbcr420_supported ? true1 : false0;
break;
case DRM_MODE_CONNECTOR_DisplayPort10:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD(1 << 0);
aconnector->base.ycbcr_420_allowed =
	link->link_enc->features.dp_ycbcr420_supported ? true1 : false0;
break;
case DRM_MODE_CONNECTOR_DVID3:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD(1 << 0);
break;
default:
break;
}

drm_object_attach_property(&aconnector->base.base,
		dm->ddev->mode_config.scaling_mode_property,
		DRM_MODE_SCALE_NONE0);

drm_object_attach_property(&aconnector->base.base,
		adev->mode_info.underscan_property,
		UNDERSCAN_OFF);
drm_object_attach_property(&aconnector->base.base,
		adev->mode_info.underscan_hborder_property,
		0);
drm_object_attach_property(&aconnector->base.base,
		adev->mode_info.underscan_vborder_property,
		0);

if (!aconnector->mst_port)
drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);

/* This defaults to the max in the range, but we want 8bpc for non-edp. */
aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP14) ? 16 : 8;
aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;

if (connector_type == DRM_MODE_CONNECTOR_eDP14 &&
   (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
drm_object_attach_property(&aconnector->base.base,
		adev->mode_info.abm_level_property, 0);
}

if (connector_type == DRM_MODE_CONNECTOR_HDMIA11 ||
   connector_type == DRM_MODE_CONNECTOR_DisplayPort10 ||
   connector_type == DRM_MODE_CONNECTOR_eDP14) {
drm_object_attach_property(
	&aconnector->base.base,
	dm->ddev->mode_config.hdr_output_metadata_property, 0);

if (!aconnector->mst_port)
	drm_connector_attach_vrr_capable_property(&aconnector->base);

6545#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.hdcp_workqueue)
	drm_connector_attach_content_protection_property(&aconnector->base, true1);
6548#endif
}
6550}

6552static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
	      struct i2c_msg *msgs, int num)
6554{
struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
struct ddc_service *ddc_service = i2c->ddc_service;
struct i2c_command cmd;
int i;
int result = -EIO5;

cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL(0x0001 | 0x0004));

if (!cmd.payloads)
return result;

cmd.number_of_payloads = num;
cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
cmd.speed = 100;

for (i = 0; i < num; i++) {
cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD0x0001);
cmd.payloads[i].address = msgs[i].addr;
cmd.payloads[i].length = msgs[i].len;
cmd.payloads[i].data = msgs[i].buf;
}

if (dc_submit_i2c(
	ddc_service->ctx->dc,
	ddc_service->ddc_pin->hw_info.ddc_channel,
	&cmd))
result = num;

kfree(cmd.payloads);
return result;
6585}

6587static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
6588{
return I2C_FUNC_I2C0 | I2C_FUNC_SMBUS_EMUL0;
6590}

6592static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
.master_xfer = amdgpu_dm_i2c_xfer,
.functionality = amdgpu_dm_i2c_func,
6595};

6597static struct amdgpu_i2c_adapter *
6598create_i2c(struct ddc_service *ddc_service,
  int link_index,
  int *res)
6601{
struct amdgpu_device *adev = ddc_service->ctx->driver_context;
struct amdgpu_i2c_adapter *i2c;

i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL(0x0001 | 0x0004));
if (!i2c)
return NULL((void *)0);
6608#ifdef notyet
i2c->base.owner = THIS_MODULE((void *)0);
i2c->base.class = I2C_CLASS_DDC;
i2c->base.dev.parent = &adev->pdev->dev;
6612#endif
i2c->base.algo = &amdgpu_dm_i2c_algo;
snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
i2c_set_adapdata(&i2c->base, i2c);
i2c->ddc_service = ddc_service;
i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;

return i2c;
6620}


6623/*
* Note: this function assumes that dc_link_detect() was called for the
* dc_link which will be represented by this aconnector.
*/
6627static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
		    struct amdgpu_dm_connector *aconnector,
		    uint32_t link_index,
		    struct amdgpu_encoder *aencoder)
6631{
int res = 0;
int connector_type;
struct dc *dc = dm->dc;
struct dc_link *link = dc_get_link_at_index(dc, link_index);
struct amdgpu_i2c_adapter *i2c;

link->priv = aconnector;

DRM_DEBUG_DRIVER("%s()\n", __func__)__drm_dbg(DRM_UT_DRIVER, "%s()\n", __func__);

i2c = create_i2c(link->ddc, link->link_index, &res);
if (!i2c) {
DRM_ERROR("Failed to create i2c adapter data\n")__drm_err("Failed to create i2c adapter data\n");
return -ENOMEM12;
}

aconnector->i2c = i2c;
res = i2c_add_adapter(&i2c->base)0;

if (res) {
DRM_ERROR("Failed to register hw i2c %d\n", link->link_index)__drm_err("Failed to register hw i2c %d\n", link->link_index
);
goto out_free;
}

connector_type = to_drm_connector_type(link->connector_signal);

res = drm_connector_init_with_ddc(
	dm->ddev,
	&aconnector->base,
	&amdgpu_dm_connector_funcs,
	connector_type,
	&i2c->base);

if (res) {
DRM_ERROR("connector_init failed\n")__drm_err("connector_init failed\n");
aconnector->connector_id = -1;
goto out_free;
}

drm_connector_helper_add(
	&aconnector->base,
	&amdgpu_dm_connector_helper_funcs);

amdgpu_dm_connector_init_helper(
dm,
aconnector,
connector_type,
link,
link_index);

drm_connector_attach_encoder(
&aconnector->base, &aencoder->base);

if (connector_type == DRM_MODE_CONNECTOR_DisplayPort10
|| connector_type == DRM_MODE_CONNECTOR_eDP14)
amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);

6689out_free:
if (res) {
kfree(i2c);
aconnector->i2c = NULL((void *)0);
}
return res;
6695}

6697int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
6698{
switch (adev->mode_info.num_crtc) {
case 1:
return 0x1;
case 2:
return 0x3;
case 3:
return 0x7;
case 4:
return 0xf;
case 5:
return 0x1f;
case 6:
default:
return 0x3f;
}
6714}

6716static int amdgpu_dm_encoder_init(struct drm_device *dev,
		  struct amdgpu_encoder *aencoder,
		  uint32_t link_index)
6719{
struct amdgpu_device *adev = drm_to_adev(dev);

int res = drm_encoder_init(dev,
		   &aencoder->base,
		   &amdgpu_dm_encoder_funcs,
		   DRM_MODE_ENCODER_TMDS2,
		   NULL((void *)0));

aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);

if (!res)
aencoder->encoder_id = link_index;
else
aencoder->encoder_id = -1;

drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);

return res;
6738}

6740static void manage_dm_interrupts(struct amdgpu_device *adev,
		 struct amdgpu_crtc *acrtc,
		 bool_Bool enable)
6743{
/*
* We have no guarantee that the frontend index maps to the same
* backend index - some even map to more than one.
*
* TODO: Use a different interrupt or check DC itself for the mapping.
*/
int irq_type =
amdgpu_display_crtc_idx_to_irq_type(
	adev,
	acrtc->crtc_id);

if (enable) {
drm_crtc_vblank_on(&acrtc->base);
amdgpu_irq_get(
	adev,
	&adev->pageflip_irq,
	irq_type);
} else {

amdgpu_irq_put(
	adev,
	&adev->pageflip_irq,
	irq_type);
drm_crtc_vblank_off(&acrtc->base);
}
6769}

6771static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
		      struct amdgpu_crtc *acrtc)
6773{
int irq_type =
amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);

/**
* This reads the current state for the IRQ and force reapplies
* the setting to hardware.
*/
amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
6782}

6784static bool_Bool
6785is_scaling_state_different(const struct dm_connector_state *dm_state,
	   const struct dm_connector_state *old_dm_state)
6787{
if (dm_state->scaling != old_dm_state->scaling)
return true1;
if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
	return true1;
} else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
	return true1;
} else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
   dm_state->underscan_vborder != old_dm_state->underscan_vborder)
return true1;
return false0;
6800}

6802#ifdef CONFIG_DRM_AMD_DC_HDCP
6803static bool_Bool is_content_protection_different(struct drm_connector_state *state,
			    const struct drm_connector_state *old_state,
			    const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
6806{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (old_state->hdcp_content_type != state->hdcp_content_type &&
   state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED0) {
state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;
return true1;
}

/* CP is being re enabled, ignore this */
if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2 &&
   state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED1) {
state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED2;
return false0;
}

/* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED */
if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED0 &&
   state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2)
state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;

/* Check if something is connected/enabled, otherwise we start hdcp but nothing is connected/enabled
* hot-plug, headless s3, dpms
*/
if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED1 && connector->dpms == DRM_MODE_DPMS_ON0 &&
   aconnector->dc_sink != NULL((void *)0))
return true1;

if (old_state->content_protection == state->content_protection)
return false0;

if (state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED0)
return true1;

return false0;
6841}

6843#endif
6844static void remove_stream(struct amdgpu_device *adev,
	  struct amdgpu_crtc *acrtc,
	  struct dc_stream_state *stream)
6847{
/* this is the update mode case */

acrtc->otg_inst = -1;
acrtc->enabled = false0;
6852}

6854static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
	       struct dc_cursor_position *position)
6856{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
int x, y;
int xorigin = 0, yorigin = 0;

if (!crtc || !plane->state->fb)
return 0;

if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
   (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
DRM_ERROR("%s: bad cursor width or height %d x %d\n",__drm_err("%s: bad cursor width or height %d x %d\n", __func__
, plane->state->crtc_w, plane->state->crtc_h)
	  __func__,__drm_err("%s: bad cursor width or height %d x %d\n", __func__
, plane->state->crtc_w, plane->state->crtc_h)
	  plane->state->crtc_w,__drm_err("%s: bad cursor width or height %d x %d\n", __func__
, plane->state->crtc_w, plane->state->crtc_h)
	  plane->state->crtc_h)__drm_err("%s: bad cursor width or height %d x %d\n", __func__
, plane->state->crtc_w, plane->state->crtc_h);
return -EINVAL22;
}

x = plane->state->crtc_x;
y = plane->state->crtc_y;

if (x <= -amdgpu_crtc->max_cursor_width ||
   y <= -amdgpu_crtc->max_cursor_height)
return 0;

if (x < 0) {
xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1)(((-x)<(amdgpu_crtc->max_cursor_width - 1))?(-x):(amdgpu_crtc
->max_cursor_width - 1));
x = 0;
}
if (y < 0) {
yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1)(((-y)<(amdgpu_crtc->max_cursor_height - 1))?(-y):(amdgpu_crtc
->max_cursor_height - 1));
y = 0;
}
position->enable = true1;
position->translate_by_source = true1;
position->x = x;
position->y = y;
position->x_hotspot = xorigin;
position->y_hotspot = yorigin;

return 0;
6896}

6898static void handle_cursor_update(struct drm_plane *plane,
		 struct drm_plane_state *old_plane_state)
6900{
struct amdgpu_device *adev = drm_to_adev(plane->dev);
struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb)({ const __typeof( ((struct amdgpu_framebuffer *)0)->base )
 *__mptr = (plane->state->fb); (struct amdgpu_framebuffer
 *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_framebuffer
, base) );});
struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (crtc->state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );}) : NULL((void *)0);
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
uint64_t address = afb ? afb->address : 0;
struct dc_cursor_position position = {0};
struct dc_cursor_attributes attributes;
int ret;

if (!plane->state->fb && !old_plane_state->fb)
return;

DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",__drm_dbg(DRM_UT_DRIVER, "%s: crtc_id=%d with size %d to %d\n"
, __func__, amdgpu_crtc->crtc_id, plane->state->crtc_w
, plane->state->crtc_h)
	 __func__,__drm_dbg(DRM_UT_DRIVER, "%s: crtc_id=%d with size %d to %d\n"
, __func__, amdgpu_crtc->crtc_id, plane->state->crtc_w
, plane->state->crtc_h)
	 amdgpu_crtc->crtc_id,__drm_dbg(DRM_UT_DRIVER, "%s: crtc_id=%d with size %d to %d\n"
, __func__, amdgpu_crtc->crtc_id, plane->state->crtc_w
, plane->state->crtc_h)
	 plane->state->crtc_w,__drm_dbg(DRM_UT_DRIVER, "%s: crtc_id=%d with size %d to %d\n"
, __func__, amdgpu_crtc->crtc_id, plane->state->crtc_w
, plane->state->crtc_h)
	 plane->state->crtc_h)__drm_dbg(DRM_UT_DRIVER, "%s: crtc_id=%d with size %d to %d\n"
, __func__, amdgpu_crtc->crtc_id, plane->state->crtc_w
, plane->state->crtc_h);

ret = get_cursor_position(plane, crtc, &position);
if (ret)
return;

if (!position.enable) {
/* turn off cursor */
if (crtc_state && crtc_state->stream) {
	mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock);
	dc_stream_set_cursor_position(crtc_state->stream,
				      &position);
	mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);
}
return;
}

amdgpu_crtc->cursor_width = plane->state->crtc_w;
amdgpu_crtc->cursor_height = plane->state->crtc_h;

memset(&attributes, 0, sizeof(attributes))__builtin_memset((&attributes), (0), (sizeof(attributes))
);
attributes.address.high_part = upper_32_bits(address)((u32)(((address) >> 16) >> 16));
attributes.address.low_part  = lower_32_bits(address)((u32)(address));
attributes.width             = plane->state->crtc_w;
attributes.height            = plane->state->crtc_h;
attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
attributes.rotation_angle    = 0;
attributes.attribute_flags.value = 0;

attributes.pitch = attributes.width;

if (crtc_state->stream) {
mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock);
if (!dc_stream_set_cursor_attributes(crtc_state->stream,
					 &attributes))
	DRM_ERROR("DC failed to set cursor attributes\n")__drm_err("DC failed to set cursor attributes\n");

if (!dc_stream_set_cursor_position(crtc_state->stream,
				   &position))
	DRM_ERROR("DC failed to set cursor position\n")__drm_err("DC failed to set cursor position\n");
mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);
}
6960}

6962static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
6963{

assert_spin_locked(&acrtc->base.dev->event_lock)do { if (((&acrtc->base.dev->event_lock)->mtx_owner
 != ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" :
 "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})) && !(panicstr || db_active)) panic("mutex %p not held in %s"
, (&acrtc->base.dev->event_lock), __func__); } while
 (0);
WARN_ON(acrtc->event)({ int __ret = !!(acrtc->event); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "acrtc->event", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 6966); __builtin_expect(!!(__ret), 0); });

acrtc->event = acrtc->base.state->event;

/* Set the flip status */
acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;

/* Mark this event as consumed */
acrtc->base.state->event = NULL((void *)0);

DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",__drm_dbg(DRM_UT_DRIVER, "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n"
, acrtc->crtc_id)
				 acrtc->crtc_id)__drm_dbg(DRM_UT_DRIVER, "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n"
, acrtc->crtc_id);
6978}

6980static void update_freesync_state_on_stream(
struct amdgpu_display_manager *dm,
struct dm_crtc_state *new_crtc_state,
struct dc_stream_state *new_stream,
struct dc_plane_state *surface,
u32 flip_timestamp_in_us)
6986{
struct mod_vrr_params vrr_params;
struct dc_info_packet vrr_infopacket = {0};
struct amdgpu_device *adev = dm->adev;
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (new_crtc_state->base.crtc); (struct amdgpu_crtc *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) );});
unsigned long flags;

if (!new_stream)
return;

/*
* TODO: Determine why min/max totals and vrefresh can be 0 here.
* For now it's sufficient to just guard against these conditions.
*/

if (!new_stream->timing.h_total || !new_stream->timing.v_total)
return;

spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
      vrr_params = acrtc->dm_irq_params.vrr_params;

if (surface) {
mod_freesync_handle_preflip(
	dm->freesync_module,
	surface,
	new_stream,
	flip_timestamp_in_us,
	&vrr_params);

if (adev->family < AMDGPU_FAMILY_AI141 &&
    amdgpu_dm_vrr_active(new_crtc_state)) {
	mod_freesync_handle_v_update(dm->freesync_module,
				     new_stream, &vrr_params);

	/* Need to call this before the frame ends. */
	dc_stream_adjust_vmin_vmax(dm->dc,
				   new_crtc_state->stream,
				   &vrr_params.adjust);
}
}

mod_freesync_build_vrr_infopacket(
dm->freesync_module,
new_stream,
&vrr_params,
PACKET_TYPE_VRR,
TRANSFER_FUNC_UNKNOWN,
&vrr_infopacket);

new_crtc_state->freesync_timing_changed |=
(memcmp(&acrtc->dm_irq_params.vrr_params.adjust,__builtin_memcmp((&acrtc->dm_irq_params.vrr_params.adjust
), (&vrr_params.adjust), (sizeof(vrr_params.adjust)))
	&vrr_params.adjust,__builtin_memcmp((&acrtc->dm_irq_params.vrr_params.adjust
), (&vrr_params.adjust), (sizeof(vrr_params.adjust)))
	sizeof(vrr_params.adjust))__builtin_memcmp((&acrtc->dm_irq_params.vrr_params.adjust
), (&vrr_params.adjust), (sizeof(vrr_params.adjust))) != 0);

new_crtc_state->freesync_vrr_info_changed |=
(memcmp(&new_crtc_state->vrr_infopacket,__builtin_memcmp((&new_crtc_state->vrr_infopacket), (&
vrr_infopacket), (sizeof(vrr_infopacket)))
	&vrr_infopacket,__builtin_memcmp((&new_crtc_state->vrr_infopacket), (&
vrr_infopacket), (sizeof(vrr_infopacket)))
	sizeof(vrr_infopacket))__builtin_memcmp((&new_crtc_state->vrr_infopacket), (&
vrr_infopacket), (sizeof(vrr_infopacket))) != 0);

acrtc->dm_irq_params.vrr_params = vrr_params;
new_crtc_state->vrr_infopacket = vrr_infopacket;

new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust;
new_stream->vrr_infopacket = vrr_infopacket;

if (new_crtc_state->freesync_vrr_info_changed)
DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",__drm_dbg(DRM_UT_KMS, "VRR packet update: crtc=%u enabled=%d state=%d"
, new_crtc_state->base.crtc->base.id, (int)new_crtc_state
->base.vrr_enabled, (int)vrr_params.state)
	      new_crtc_state->base.crtc->base.id,__drm_dbg(DRM_UT_KMS, "VRR packet update: crtc=%u enabled=%d state=%d"
, new_crtc_state->base.crtc->base.id, (int)new_crtc_state
->base.vrr_enabled, (int)vrr_params.state)
	      (int)new_crtc_state->base.vrr_enabled,__drm_dbg(DRM_UT_KMS, "VRR packet update: crtc=%u enabled=%d state=%d"
, new_crtc_state->base.crtc->base.id, (int)new_crtc_state
->base.vrr_enabled, (int)vrr_params.state)
	      (int)vrr_params.state)__drm_dbg(DRM_UT_KMS, "VRR packet update: crtc=%u enabled=%d state=%d"
, new_crtc_state->base.crtc->base.id, (int)new_crtc_state
->base.vrr_enabled, (int)vrr_params.state);

spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
7058}

7060static void update_stream_irq_parameters(
struct amdgpu_display_manager *dm,
struct dm_crtc_state *new_crtc_state)
7063{
struct dc_stream_state *new_stream = new_crtc_state->stream;
struct mod_vrr_params vrr_params;
struct mod_freesync_config config = new_crtc_state->freesync_config;
struct amdgpu_device *adev = dm->adev;
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (new_crtc_state->base.crtc); (struct amdgpu_crtc *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) );});
unsigned long flags;

if (!new_stream)
return;

/*
* TODO: Determine why min/max totals and vrefresh can be 0 here.
* For now it's sufficient to just guard against these conditions.
*/
if (!new_stream->timing.h_total || !new_stream->timing.v_total)
return;

spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
vrr_params = acrtc->dm_irq_params.vrr_params;

if (new_crtc_state->vrr_supported &&
   config.min_refresh_in_uhz &&
   config.max_refresh_in_uhz) {
config.state = new_crtc_state->base.vrr_enabled ?
	VRR_STATE_ACTIVE_VARIABLE :
	VRR_STATE_INACTIVE;
} else {
config.state = VRR_STATE_UNSUPPORTED;
}

mod_freesync_build_vrr_params(dm->freesync_module,
		      new_stream,
		      &config, &vrr_params);

new_crtc_state->freesync_timing_changed |=
(memcmp(&acrtc->dm_irq_params.vrr_params.adjust,__builtin_memcmp((&acrtc->dm_irq_params.vrr_params.adjust
), (&vrr_params.adjust), (sizeof(vrr_params.adjust)))
	&vrr_params.adjust, sizeof(vrr_params.adjust))__builtin_memcmp((&acrtc->dm_irq_params.vrr_params.adjust
), (&vrr_params.adjust), (sizeof(vrr_params.adjust))) != 0);

new_crtc_state->freesync_config = config;
/* Copy state for access from DM IRQ handler */
acrtc->dm_irq_params.freesync_config = config;
acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
acrtc->dm_irq_params.vrr_params = vrr_params;
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
7108}

7110static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
			    struct dm_crtc_state *new_state)
7112{
bool_Bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
bool_Bool new_vrr_active = amdgpu_dm_vrr_active(new_state);

if (!old_vrr_active && new_vrr_active) {
/* Transition VRR inactive -> active:
 * While VRR is active, we must not disable vblank irq, as a
 * reenable after disable would compute bogus vblank/pflip
 * timestamps if it likely happened inside display front-porch.
 *
 * We also need vupdate irq for the actual core vblank handling
 * at end of vblank.
 */
dm_set_vupdate_irq(new_state->base.crtc, true1);
drm_crtc_vblank_get(new_state->base.crtc);
DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",__drm_dbg(DRM_UT_DRIVER, "%s: crtc=%u VRR off->on: Get vblank ref\n"
, __func__, new_state->base.crtc->base.id)
		 __func__, new_state->base.crtc->base.id)__drm_dbg(DRM_UT_DRIVER, "%s: crtc=%u VRR off->on: Get vblank ref\n"
, __func__, new_state->base.crtc->base.id);
} else if (old_vrr_active && !new_vrr_active) {
/* Transition VRR active -> inactive:
 * Allow vblank irq disable again for fixed refresh rate.
 */
dm_set_vupdate_irq(new_state->base.crtc, false0);
drm_crtc_vblank_put(new_state->base.crtc);
DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",__drm_dbg(DRM_UT_DRIVER, "%s: crtc=%u VRR on->off: Drop vblank ref\n"
, __func__, new_state->base.crtc->base.id)
		 __func__, new_state->base.crtc->base.id)__drm_dbg(DRM_UT_DRIVER, "%s: crtc=%u VRR on->off: Drop vblank ref\n"
, __func__, new_state->base.crtc->base.id);
}
7138}

7140static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7141{
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
int i;

/*
* TODO: Make this per-stream so we don't issue redundant updates for
* commits with multiple streams.
*/
for_each_oldnew_plane_in_state(state, plane, old_plane_state,for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (void)(plane) , (old_plane_state)
 = (state)->planes[i].old_state, (new_plane_state) = (state
)->planes[i].new_state, 1))) {} else
		       new_plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (void)(plane) , (old_plane_state)
 = (state)->planes[i].old_state, (new_plane_state) = (state
)->planes[i].new_state, 1))) {} else
if (plane->type == DRM_PLANE_TYPE_CURSOR)
	handle_cursor_update(plane, old_plane_state);
7154}

7156static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
		    struct dc_state *dc_state,
		    struct drm_device *dev,
		    struct amdgpu_display_manager *dm,
		    struct drm_crtc *pcrtc,
		    bool_Bool wait_for_vblank)
7162{
uint32_t i;
uint64_t timestamp_ns;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (pcrtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
struct drm_crtc_state *new_pcrtc_state =
	drm_atomic_get_new_crtc_state(state, pcrtc);
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_pcrtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
struct dm_crtc_state *dm_old_crtc_state =
	to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc))({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (drm_atomic_get_old_crtc_state(state, pcrtc)); (struct dm_crtc_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_crtc_state
, base) );});
int planes_count = 0, vpos, hpos;
long r;
unsigned long flags;
struct amdgpu_bo *abo;
uint32_t target_vblank, last_flip_vblank;
bool_Bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
bool_Bool pflip_present = false0;
struct {
struct dc_surface_update surface_updates[MAX_SURFACES3];
struct dc_plane_info plane_infos[MAX_SURFACES3];
struct dc_scaling_info scaling_infos[MAX_SURFACES3];
struct dc_flip_addrs flip_addrs[MAX_SURFACES3];
struct dc_stream_update stream_update;
} *bundle;

bundle = kzalloc(sizeof(*bundle), GFP_KERNEL(0x0001 | 0x0004));

if (!bundle) {
dm_error("Failed to allocate update bundle\n")__drm_err("Failed to allocate update bundle\n");
goto cleanup;
}

/*
* Disable the cursor first if we're disabling all the planes.
* It'll remain on the screen after the planes are re-enabled
* if we don't.
*/
if (acrtc_state->active_planes == 0)
amdgpu_dm_commit_cursors(state);

/* update planes when needed */
for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (void)(plane) , (old_plane_state)
 = (state)->planes[i].old_state, (new_plane_state) = (state
)->planes[i].new_state, 1))) {} else {
struct drm_crtc *crtc = new_plane_state->crtc;
struct drm_crtc_state *new_crtc_state;
struct drm_framebuffer *fb = new_plane_state->fb;
bool_Bool plane_needs_flip;
struct dc_plane_state *dc_plane;
struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});

/* Cursor plane is handled after stream updates */
if (plane->type == DRM_PLANE_TYPE_CURSOR)
	continue;

if (!fb || !crtc || pcrtc != crtc)
	continue;

new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
if (!new_crtc_state->active)
	continue;

dc_plane = dm_new_plane_state->dc_state;

bundle->surface_updates[planes_count].surface = dc_plane;
if (new_pcrtc_state->color_mgmt_changed) {
	bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
	bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
	bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
}

fill_dc_scaling_info(new_plane_state,
		     &bundle->scaling_infos[planes_count]);

bundle->surface_updates[planes_count].scaling_info =
	&bundle->scaling_infos[planes_count];

plane_needs_flip = old_plane_state->fb && new_plane_state->fb;

pflip_present = pflip_present || plane_needs_flip;

if (!plane_needs_flip) {
	planes_count += 1;
	continue;
}

abo = gem_to_amdgpu_bo(fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
 = ((fb->obj[0])); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );});

/*
 * Wait for all fences on this FB. Do limited wait to avoid
 * deadlock during GPU reset when this fence will not signal
 * but we hold reservation lock for the BO.
 */
r = dma_resv_wait_timeout_rcu(abo->tbo.base.resv, true1,
					false0,
					msecs_to_jiffies(5000)(((uint64_t)(5000)) * hz / 1000));
if (unlikely(r <= 0)__builtin_expect(!!(r <= 0), 0))
	DRM_ERROR("Waiting for fences timed out!")__drm_err("Waiting for fences timed out!");

fill_dc_plane_info_and_addr(
	dm->adev, new_plane_state,
	dm_new_plane_state->tiling_flags,
	&bundle->plane_infos[planes_count],
	&bundle->flip_addrs[planes_count].address,
	dm_new_plane_state->tmz_surface, false0);

DRM_DEBUG_DRIVER("plane: id=%d dcc_en=%d\n",__drm_dbg(DRM_UT_DRIVER, "plane: id=%d dcc_en=%d\n", new_plane_state
->plane->index, bundle->plane_infos[planes_count].dcc
.enable)
		 new_plane_state->plane->index,__drm_dbg(DRM_UT_DRIVER, "plane: id=%d dcc_en=%d\n", new_plane_state
->plane->index, bundle->plane_infos[planes_count].dcc
.enable)
		 bundle->plane_infos[planes_count].dcc.enable)__drm_dbg(DRM_UT_DRIVER, "plane: id=%d dcc_en=%d\n", new_plane_state
->plane->index, bundle->plane_infos[planes_count].dcc
.enable);

bundle->surface_updates[planes_count].plane_info =
	&bundle->plane_infos[planes_count];

/*
 * Only allow immediate flips for fast updates that don't
 * change FB pitch, DCC state, rotation or mirroing.
 */
bundle->flip_addrs[planes_count].flip_immediate =
	crtc->state->async_flip &&
	acrtc_state->update_type == UPDATE_TYPE_FAST;

timestamp_ns = ktime_get_ns();
bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
bundle->surface_updates[planes_count].surface = dc_plane;

if (!bundle->surface_updates[planes_count].surface) {
	DRM_ERROR("No surface for CRTC: id=%d\n",__drm_err("No surface for CRTC: id=%d\n", acrtc_attach->crtc_id
)
			acrtc_attach->crtc_id)__drm_err("No surface for CRTC: id=%d\n", acrtc_attach->crtc_id
);
	continue;
}

if (plane == pcrtc->primary)
	update_freesync_state_on_stream(
		dm,
		acrtc_state,
		acrtc_state->stream,
		dc_plane,
		bundle->flip_addrs[planes_count].flip_timestamp_in_us);

DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",__drm_dbg(DRM_UT_DRIVER, "%s Flipping to hi: 0x%x, low: 0x%x\n"
, __func__, bundle->flip_addrs[planes_count].address.grph.
addr.high_part, bundle->flip_addrs[planes_count].address.grph
.addr.low_part)
		 __func__,__drm_dbg(DRM_UT_DRIVER, "%s Flipping to hi: 0x%x, low: 0x%x\n"
, __func__, bundle->flip_addrs[planes_count].address.grph.
addr.high_part, bundle->flip_addrs[planes_count].address.grph
.addr.low_part)
		 bundle->flip_addrs[planes_count].address.grph.addr.high_part,__drm_dbg(DRM_UT_DRIVER, "%s Flipping to hi: 0x%x, low: 0x%x\n"
, __func__, bundle->flip_addrs[planes_count].address.grph.
addr.high_part, bundle->flip_addrs[planes_count].address.grph
.addr.low_part)
		 bundle->flip_addrs[planes_count].address.grph.addr.low_part)__drm_dbg(DRM_UT_DRIVER, "%s Flipping to hi: 0x%x, low: 0x%x\n"
, __func__, bundle->flip_addrs[planes_count].address.grph.
addr.high_part, bundle->flip_addrs[planes_count].address.grph
.addr.low_part);

planes_count += 1;

}

if (pflip_present) {
if (!vrr_active) {
	/* Use old throttling in non-vrr fixed refresh rate mode
	 * to keep flip scheduling based on target vblank counts
	 * working in a backwards compatible way, e.g., for
	 * clients using the GLX_OML_sync_control extension or
	 * DRI3/Present extension with defined target_msc.
	 */
	last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
}
else {
	/* For variable refresh rate mode only:
	 * Get vblank of last completed flip to avoid > 1 vrr
	 * flips per video frame by use of throttling, but allow
	 * flip programming anywhere in the possibly large
	 * variable vrr vblank interval for fine-grained flip
	 * timing control and more opportunity to avoid stutter
	 * on late submission of flips.
	 */
	spin_lock_irqsave(&pcrtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&pcrtc->dev->event_lock);
 } while (0);
	last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&pcrtc->dev->event_lock
); } while (0);
}

target_vblank = last_flip_vblank + wait_for_vblank;

/*
 * Wait until we're out of the vertical blank period before the one
 * targeted by the flip
 */
while ((acrtc_attach->enabled &&
	(amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
					    0, &vpos, &hpos, NULL((void *)0),
					    NULL((void *)0), &pcrtc->hwmode)
	 & (DRM_SCANOUTPOS_VALID(1 << 0) | DRM_SCANOUTPOS_IN_VBLANK(1 << 1))) ==
	(DRM_SCANOUTPOS_VALID(1 << 0) | DRM_SCANOUTPOS_IN_VBLANK(1 << 1)) &&
	(int)(target_vblank -
	  amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
	usleep_range(1000, 1100);
}

/**
 * Prepare the flip event for the pageflip interrupt to handle.
 *
 * This only works in the case where we've already turned on the
 * appropriate hardware blocks (eg. HUBP) so in the transition case
 * from 0 -> n planes we have to skip a hardware generated event
 * and rely on sending it from software.
 */
if (acrtc_attach->base.state->event &&
    acrtc_state->active_planes > 0) {
	drm_crtc_vblank_get(pcrtc);

	spin_lock_irqsave(&pcrtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&pcrtc->dev->event_lock);
 } while (0);

	WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE)({ int __ret = !!(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE
); if (__ret) printf("WARNING %s failed at %s:%d\n", "acrtc_attach->pflip_status != AMDGPU_FLIP_NONE"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7365); __builtin_expect(!!(__ret), 0); });
	prepare_flip_isr(acrtc_attach);

	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&pcrtc->dev->event_lock
); } while (0);
}

if (acrtc_state->stream) {
	if (acrtc_state->freesync_vrr_info_changed)
		bundle->stream_update.vrr_infopacket =
			&acrtc_state->stream->vrr_infopacket;
}
}

/* Update the planes if changed or disable if we don't have any. */
if ((planes_count || acrtc_state->active_planes == 0) &&
acrtc_state->stream) {
bundle->stream_update.stream = acrtc_state->stream;
if (new_pcrtc_state->mode_changed) {
	bundle->stream_update.src = acrtc_state->stream->src;
	bundle->stream_update.dst = acrtc_state->stream->dst;
}

if (new_pcrtc_state->color_mgmt_changed) {
	/*
	 * TODO: This isn't fully correct since we've actually
	 * already modified the stream in place.
	 */
	bundle->stream_update.gamut_remap =
		&acrtc_state->stream->gamut_remap_matrix;
	bundle->stream_update.output_csc_transform =
		&acrtc_state->stream->csc_color_matrix;
	bundle->stream_update.out_transfer_func =
		acrtc_state->stream->out_transfer_func;
}

acrtc_state->stream->abm_level = acrtc_state->abm_level;
if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
	bundle->stream_update.abm_level = &acrtc_state->abm_level;

/*
 * If FreeSync state on the stream has changed then we need to
 * re-adjust the min/max bounds now that DC doesn't handle this
 * as part of commit.
 */
if (amdgpu_dm_vrr_active(dm_old_crtc_state) !=
    amdgpu_dm_vrr_active(acrtc_state)) {
	spin_lock_irqsave(&pcrtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&pcrtc->dev->event_lock);
 } while (0);
	dc_stream_adjust_vmin_vmax(
		dm->dc, acrtc_state->stream,
		&acrtc_attach->dm_irq_params.vrr_params.adjust);
	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&pcrtc->dev->event_lock
); } while (0);
}
mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
		acrtc_state->stream->link->psr_settings.psr_allow_active)
	amdgpu_dm_psr_disable(acrtc_state->stream);

dc_commit_updates_for_stream(dm->dc,
				     bundle->surface_updates,
				     planes_count,
				     acrtc_state->stream,
				     &bundle->stream_update,
				     dc_state);

/**
 * Enable or disable the interrupts on the backend.
 *
 * Most pipes are put into power gating when unused.
 *
 * When power gating is enabled on a pipe we lose the
 * interrupt enablement state when power gating is disabled.
 *
 * So we need to update the IRQ control state in hardware
 * whenever the pipe turns on (since it could be previously
 * power gated) or off (since some pipes can't be power gated
 * on some ASICs).
 */
if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
	dm_update_pflip_irq_state(drm_to_adev(dev),
				  acrtc_attach);

if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
		acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
		!acrtc_state->stream->link->psr_settings.psr_feature_enabled)
	amdgpu_dm_link_setup_psr(acrtc_state->stream);
else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
		acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
		!acrtc_state->stream->link->psr_settings.psr_allow_active) {
	amdgpu_dm_psr_enable(acrtc_state->stream);
}

mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);
}

/*
* Update cursor state *after* programming all the planes.
* This avoids redundant programming in the case where we're going
* to be disabling a single plane - those pipes are being disabled.
*/
if (acrtc_state->active_planes)
amdgpu_dm_commit_cursors(state);

7467cleanup:
kfree(bundle);
7469}

7471static void amdgpu_dm_commit_audio(struct drm_device *dev,
		   struct drm_atomic_state *state)
7473{
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_state *old_con_state, *new_con_state;
struct drm_crtc_state *new_crtc_state;
struct dm_crtc_state *new_dm_crtc_state;
const struct dc_stream_status *status;
int i, inst;

/* Notify device removals. */
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
if (old_con_state->crtc != new_con_state->crtc) {
	/* CRTC changes require notification. */
	goto notify;
}

if (!new_con_state->crtc)
	continue;

new_crtc_state = drm_atomic_get_new_crtc_state(
	state, new_con_state->crtc);

if (!new_crtc_state)
	continue;

if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
	continue;

notify:
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

mutex_lock(&adev->dm.audio_lock)rw_enter_write(&adev->dm.audio_lock);
inst = aconnector->audio_inst;
aconnector->audio_inst = -1;
mutex_unlock(&adev->dm.audio_lock)rw_exit_write(&adev->dm.audio_lock);

amdgpu_dm_audio_eld_notify(adev, inst);
}

/* Notify audio device additions. */
for_each_new_connector_in_state(state, connector, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (new_con_state) =
 (state)->connectors[i].new_state, (void)(new_con_state) ,
 1))) {} else {
if (!new_con_state->crtc)
	continue;

new_crtc_state = drm_atomic_get_new_crtc_state(
	state, new_con_state->crtc);

if (!new_crtc_state)
	continue;

if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
	continue;

new_dm_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
if (!new_dm_crtc_state->stream)
	continue;

status = dc_stream_get_status(new_dm_crtc_state->stream);
if (!status)
	continue;

aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

mutex_lock(&adev->dm.audio_lock)rw_enter_write(&adev->dm.audio_lock);
inst = status->audio_inst;
aconnector->audio_inst = inst;
mutex_unlock(&adev->dm.audio_lock)rw_exit_write(&adev->dm.audio_lock);

amdgpu_dm_audio_eld_notify(adev, inst);
}
7544}

7546/*
* amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
* @crtc_state: the DRM CRTC state
* @stream_state: the DC stream state.
*
* Copy the mirrored transient state flags from DRM, to DC. It is used to bring
* a dc_stream_state's flags in sync with a drm_crtc_state's flags.
*/
7554static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
				struct dc_stream_state *stream_state)
7556{
stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
7558}

7560static int amdgpu_dm_atomic_commit(struct drm_device *dev,
		   struct drm_atomic_state *state,
		   bool_Bool nonblock)
7563{
/*
* Add check here for SoC's that support hardware cursor plane, to
* unset legacy_cursor_update
*/

return drm_atomic_helper_commit(dev, state, nonblock);

/*TODO Handle EINTR, reenable IRQ*/
7572}

7574/**
* amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
* @state: The atomic state to commit
*
* This will tell DC to commit the constructed DC state from atomic_check,
* programming the hardware. Any failures here implies a hardware failure, since
* atomic check should have filtered anything non-kosher.
*/
7582static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
7583{
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_display_manager *dm = &adev->dm;
struct dm_atomic_state *dm_state;
struct dc_state *dc_state = NULL((void *)0), *dc_state_temp = NULL((void *)0);
uint32_t i, j;
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
unsigned long flags;
bool_Bool wait_for_vblank = true1;
struct drm_connector *connector;
struct drm_connector_state *old_con_state, *new_con_state;
struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
int crtc_disable_count = 0;
bool_Bool mode_set_reset_required = false0;

drm_atomic_helper_update_legacy_modeset_state(dev, state);

dm_state = dm_atomic_get_new_state(state);
if (dm_state && dm_state->context) {
dc_state = dm_state->context;
} else {
/* No state changes, retain current state. */
dc_state_temp = dc_create_state(dm->dc);
ASSERT(dc_state_temp)do { if (({ static int __warned; int __ret = !!(!(dc_state_temp
)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(dc_state_temp)", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7608); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);
dc_state = dc_state_temp;
dc_resource_state_copy_construct_current(dm->dc, dc_state);
}

for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else
		       new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (old_crtc_state->active &&
    (!new_crtc_state->active ||
     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
	manage_dm_interrupts(adev, acrtc, false0);
	dc_stream_release(dm_old_crtc_state->stream);
}
}

drm_atomic_helper_calc_timestamping_constants(state);

/* update changed items */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

DRM_DEBUG_DRIVER(__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	"planes_changed:%d, mode_changed:%d,active_changed:%d,"__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	"connectors_changed:%d\n",__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	acrtc->crtc_id,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->enable,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->active,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->planes_changed,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->mode_changed,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->active_changed,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->connectors_changed)__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed);

/* Copy all transient state flags into dc state */
if (dm_new_crtc_state->stream) {
	amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
					    dm_new_crtc_state->stream);
}

/* handles headless hotplug case, updating new_state and
 * aconnector as needed
 */

if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {

	DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc)__drm_dbg(DRM_UT_DRIVER, "Atomic commit: SET crtc id %d: [%p]\n"
, acrtc->crtc_id, acrtc);

	if (!dm_new_crtc_state->stream) {
		/*
		 * this could happen because of issues with
		 * userspace notifications delivery.
		 * In this case userspace tries to set mode on
		 * display which is disconnected in fact.
		 * dc_sink is NULL in this case on aconnector.
		 * We expect reset mode will come soon.
		 *
		 * This can also happen when unplug is done
		 * during resume sequence ended
		 *
		 * In this case, we want to pretend we still
		 * have a sink to keep the pipe running so that
		 * hw state is consistent with the sw state
		 */
		DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",__drm_dbg(DRM_UT_DRIVER, "%s: Failed to create new stream for crtc %d\n"
, __func__, acrtc->base.base.id)
				__func__, acrtc->base.base.id)__drm_dbg(DRM_UT_DRIVER, "%s: Failed to create new stream for crtc %d\n"
, __func__, acrtc->base.base.id);
		continue;
	}

	if (dm_old_crtc_state->stream)
		remove_stream(adev, acrtc, dm_old_crtc_state->stream);

	pm_runtime_get_noresume(dev->dev);

	acrtc->enabled = true1;
	acrtc->hw_mode = new_crtc_state->mode;
	crtc->hwmode = new_crtc_state->mode;
	mode_set_reset_required = true1;
} else if (modereset_required(new_crtc_state)) {
	DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc)__drm_dbg(DRM_UT_DRIVER, "Atomic commit: RESET. crtc id %d:[%p]\n"
, acrtc->crtc_id, acrtc);
	/* i.e. reset mode */
	if (dm_old_crtc_state->stream)
		remove_stream(adev, acrtc, dm_old_crtc_state->stream);
	mode_set_reset_required = true1;
}
} /* for_each_crtc_in_state() */

if (dc_state) {
/* if there mode set or reset, disable eDP PSR */
if (mode_set_reset_required)
	amdgpu_dm_psr_disable_all(dm);

dm_enable_per_frame_crtc_master_sync(dc_state);
mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
WARN_ON(!dc_commit_state(dm->dc, dc_state))({ int __ret = !!(!dc_commit_state(dm->dc, dc_state)); if (
__ret) printf("WARNING %s failed at %s:%d\n", "!dc_commit_state(dm->dc, dc_state)"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7708); __builtin_expect(!!(__ret), 0); });
mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);
}

for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (dm_new_crtc_state->stream != NULL((void *)0)) {
	const struct dc_stream_status *status =
			dc_stream_get_status(dm_new_crtc_state->stream);

	if (!status)
		status = dc_stream_get_status_from_state(dc_state,
							 dm_new_crtc_state->stream);
	if (!status)
		DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc)do { __drm_err("got no status for stream %p on acrtc%p\n", dm_new_crtc_state
->stream, acrtc); do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n"
, __func__, 7725); do {} while (0); } while (0); } while (0);
	else
		acrtc->otg_inst = status->primary_otg_inst;
}
}
7730#ifdef CONFIG_DRM_AMD_DC_HDCP
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (dm_new_con_state->base.crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

new_crtc_state = NULL((void *)0);

if (acrtc)
	new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL((void *)0) &&
    connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2) {
	hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
	new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;
	continue;
}

if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
	hdcp_update_display(
		adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
		new_con_state->hdcp_content_type,
		new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED1 ? true1
											 : false0);
}
7757#endif

/* Handle connector state changes */
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((old_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (dm_new_con_state->base.crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
struct dc_surface_update dummy_updates[MAX_SURFACES3];
struct dc_stream_update stream_update;
struct dc_info_packet hdr_packet;
struct dc_stream_status *status = NULL((void *)0);
bool_Bool abm_changed, hdr_changed, scaling_changed;

memset(&dummy_updates, 0, sizeof(dummy_updates))__builtin_memset((&dummy_updates), (0), (sizeof(dummy_updates
)));
memset(&stream_update, 0, sizeof(stream_update))__builtin_memset((&stream_update), (0), (sizeof(stream_update
)));

if (acrtc) {
	new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
	old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
}

/* Skip any modesets/resets */
if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
	continue;

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

scaling_changed = is_scaling_state_different(dm_new_con_state,
					     dm_old_con_state);

abm_changed = dm_new_crtc_state->abm_level !=
	      dm_old_crtc_state->abm_level;

hdr_changed =
	is_hdr_metadata_different(old_con_state, new_con_state);

if (!scaling_changed && !abm_changed && !hdr_changed)
	continue;

stream_update.stream = dm_new_crtc_state->stream;
if (scaling_changed) {
	update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
			dm_new_con_state, dm_new_crtc_state->stream);

	stream_update.src = dm_new_crtc_state->stream->src;
	stream_update.dst = dm_new_crtc_state->stream->dst;
}

if (abm_changed) {
	dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;

	stream_update.abm_level = &dm_new_crtc_state->abm_level;
}

if (hdr_changed) {
	fill_hdr_info_packet(new_con_state, &hdr_packet);
	stream_update.hdr_static_metadata = &hdr_packet;
}

status = dc_stream_get_status(dm_new_crtc_state->stream);
WARN_ON(!status)({ int __ret = !!(!status); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!status", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7818); __builtin_expect(!!(__ret), 0); });
WARN_ON(!status->plane_count)({ int __ret = !!(!status->plane_count); if (__ret) printf
("WARNING %s failed at %s:%d\n", "!status->plane_count", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7819); __builtin_expect(!!(__ret), 0); });

/*
 * TODO: DC refuses to perform stream updates without a dc_surface_update.
 * Here we create an empty update on each plane.
 * To fix this, DC should permit updating only stream properties.
 */
for (j = 0; j < status->plane_count; j++)
	dummy_updates[j].surface = status->plane_states[0];


mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
dc_commit_updates_for_stream(dm->dc,
				     dummy_updates,
				     status->plane_count,
				     dm_new_crtc_state->stream,
				     &stream_update,
				     dc_state);
mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);
}

/* Count number of newly disabled CRTCs for dropping PM refs later. */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else
		      new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else {
if (old_crtc_state->active && !new_crtc_state->active)
	crtc_disable_count++;

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

/* For freesync config update on crtc state and params for irq */
update_stream_irq_parameters(dm, dm_new_crtc_state);

/* Handle vrr on->off / off->on transitions */
amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
				dm_new_crtc_state);
}

/**
* Enable interrupts for CRTCs that are newly enabled or went through
* a modeset. It was intentionally deferred until after the front end
* state was modified to wait until the OTG was on and so the IRQ
* handlers didn't access stale or invalid state.
*/
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (new_crtc_state->active &&
    (!old_crtc_state->active ||
     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
	dc_stream_retain(dm_new_crtc_state->stream);
	acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
	manage_dm_interrupts(adev, acrtc, true1);

7875#ifdef CONFIG_DEBUG_FS
	/**
	 * Frontend may have changed so reapply the CRC capture
	 * settings for the stream.
	 */
	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

	if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
		amdgpu_dm_crtc_configure_crc_source(
			crtc, dm_new_crtc_state,
			dm_new_crtc_state->crc_src);
	}
7887#endif
}
}

for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)for ((j) = 0; (j) < (state)->dev->mode_config.num_crtc
; (j)++) if (!((state)->crtcs[j].ptr && ((crtc) = (
state)->crtcs[j].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[j].new_state, (void)(new_crtc_state) , 1))) {} else
if (new_crtc_state->async_flip)
	wait_for_vblank = false0;

/* update planes when needed per crtc*/
for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)for ((j) = 0; (j) < (state)->dev->mode_config.num_crtc
; (j)++) if (!((state)->crtcs[j].ptr && ((crtc) = (
state)->crtcs[j].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[j].new_state, (void)(new_crtc_state) , 1))) {} else {
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (dm_new_crtc_state->stream)
	amdgpu_dm_commit_planes(state, dc_state, dev,
				dm, crtc, wait_for_vblank);
}

/* Update audio instances for each connector. */
amdgpu_dm_commit_audio(dev, state);

/*
* send vblank event on all events not handled in flip and
* mark consumed event for drm_atomic_helper_commit_hw_done
*/
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {

if (new_crtc_state->event)
	drm_send_event_locked(dev, &new_crtc_state->event->base);

new_crtc_state->event = NULL((void *)0);
}
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);

/* Signal HW programming completion */
drm_atomic_helper_commit_hw_done(state);

if (wait_for_vblank)
drm_atomic_helper_wait_for_flip_done(dev, state);

drm_atomic_helper_cleanup_planes(dev, state);

/*
* Finally, drop a runtime PM reference for each newly disabled CRTC,
* so we can put the GPU into runtime suspend if we're not driving any
* displays anymore
*/
for (i = 0; i < crtc_disable_count; i++)
pm_runtime_put_autosuspend(dev->dev);
pm_runtime_mark_last_busy(dev->dev);

if (dc_state_temp)
dc_release_state(dc_state_temp);
7940}


7943static int dm_force_atomic_commit(struct drm_connector *connector)
7944{
int ret = 0;
struct drm_device *ddev = connector->dev;
struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (connector->encoder->crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
struct drm_plane *plane = disconnected_acrtc->base.primary;
struct drm_connector_state *conn_state;
struct drm_crtc_state *crtc_state;
struct drm_plane_state *plane_state;

if (!state)
return -ENOMEM12;

state->acquire_ctx = ddev->mode_config.acquire_ctx;

/* Construct an atomic state to restore previous display setting */

/*
* Attach connectors to drm_atomic_state
*/
conn_state = drm_atomic_get_connector_state(state, connector);

ret = PTR_ERR_OR_ZERO(conn_state);
if (ret)
goto out;

/* Attach crtc to drm_atomic_state*/
crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);

ret = PTR_ERR_OR_ZERO(crtc_state);
if (ret)
goto out;

/* force a restore */
crtc_state->mode_changed = true1;

/* Attach plane to drm_atomic_state */
plane_state = drm_atomic_get_plane_state(state, plane);

ret = PTR_ERR_OR_ZERO(plane_state);
if (ret)
goto out;

/* Call commit internally with the state we just constructed */
ret = drm_atomic_commit(state);

7990out:
drm_atomic_state_put(state);
if (ret)
DRM_ERROR("Restoring old state failed with %i\n", ret)__drm_err("Restoring old state failed with %i\n", ret);

return ret;
7996}

7998/*
* This function handles all cases when set mode does not come upon hotplug.
* This includes when a display is unplugged then plugged back into the
* same port and when running without usermode desktop manager supprot
*/
8003void dm_restore_drm_connector_state(struct drm_device *dev,
		    struct drm_connector *connector)
8005{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct amdgpu_crtc *disconnected_acrtc;
struct dm_crtc_state *acrtc_state;

if (!aconnector->dc_sink || !connector->state || !connector->encoder)
return;

disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (connector->encoder->crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
if (!disconnected_acrtc)
return;

acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (disconnected_acrtc->base.state); (struct dm_crtc_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_crtc_state
, base) );});
if (!acrtc_state->stream)
return;

/*
* If the previous sink is not released and different from the current,
* we deduce we are in a state where we can not rely on usermode call
* to turn on the display, so we do it here
*/
if (acrtc_state->stream->sink != aconnector->dc_sink)
dm_force_atomic_commit(&aconnector->base);
8028}

8030/*
* Grabs all modesetting locks to serialize against any blocking commits,
* Waits for completion of all non blocking commits.
*/
8034static int do_aquire_global_lock(struct drm_device *dev,
		 struct drm_atomic_state *state)
8036{
struct drm_crtc *crtc;
struct drm_crtc_commit *commit;
long ret;

/*
* Adding all modeset locks to aquire_ctx will
* ensure that when the framework release it the
* extra locks we are locking here will get released to
*/
ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
if (ret)
return ret;

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
 ) *__mptr = ((&dev->mode_config.crtc_list)->next);
 (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&dev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
 );})) {
spin_lock(&crtc->commit_lock)mtx_enter(&crtc->commit_lock);
commit = list_first_entry_or_null(&crtc->commit_list,(list_empty(&crtc->commit_list) ? ((void *)0) : ({ const
 __typeof( ((struct drm_crtc_commit *)0)->commit_entry ) *
__mptr = ((&crtc->commit_list)->next); (struct drm_crtc_commit
 *)( (char *)__mptr - __builtin_offsetof(struct drm_crtc_commit
, commit_entry) );}))
		struct drm_crtc_commit, commit_entry)(list_empty(&crtc->commit_list) ? ((void *)0) : ({ const
 __typeof( ((struct drm_crtc_commit *)0)->commit_entry ) *
__mptr = ((&crtc->commit_list)->next); (struct drm_crtc_commit
 *)( (char *)__mptr - __builtin_offsetof(struct drm_crtc_commit
, commit_entry) );}));
if (commit)
	drm_crtc_commit_get(commit);
spin_unlock(&crtc->commit_lock)mtx_leave(&crtc->commit_lock);

if (!commit)
	continue;

/*
 * Make sure all pending HW programming completed and
 * page flips done
 */
ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZhz);

if (ret > 0)
	ret = wait_for_completion_interruptible_timeout(
			&commit->flip_done, 10*HZhz);

if (ret == 0)
	DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "__drm_err("[CRTC:%d:%s] hw_done or flip_done " "timed out\n",
 crtc->base.id, crtc->name)
		  "timed out\n", crtc->base.id, crtc->name)__drm_err("[CRTC:%d:%s] hw_done or flip_done " "timed out\n",
 crtc->base.id, crtc->name);

drm_crtc_commit_put(commit);
}

return ret < 0 ? ret : 0;
8079}

8081static void get_freesync_config_for_crtc(
struct dm_crtc_state *new_crtc_state,
struct dm_connector_state *new_con_state)
8084{
struct mod_freesync_config config = {0};
struct amdgpu_dm_connector *aconnector =
	to_amdgpu_dm_connector(new_con_state->base.connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (new_con_state->base.connector); (struct amdgpu_dm_connector
 *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector
, base) );});
struct drm_display_mode *mode = &new_crtc_state->base.mode;
int vrefresh = drm_mode_vrefresh(mode);

new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
			vrefresh >= aconnector->min_vfreq &&
			vrefresh <= aconnector->max_vfreq;

if (new_crtc_state->vrr_supported) {
new_crtc_state->stream->ignore_msa_timing_param = true1;
config.state = new_crtc_state->base.vrr_enabled ?
		VRR_STATE_ACTIVE_VARIABLE :
		VRR_STATE_INACTIVE;
config.min_refresh_in_uhz =
		aconnector->min_vfreq * 1000000;
config.max_refresh_in_uhz =
		aconnector->max_vfreq * 1000000;
config.vsif_supported = true1;
config.btr = true1;
}

new_crtc_state->freesync_config = config;
8109}

8111static void reset_freesync_config_for_crtc(
struct dm_crtc_state *new_crtc_state)
8113{
new_crtc_state->vrr_supported = false0;

memset(&new_crtc_state->vrr_infopacket, 0,__builtin_memset((&new_crtc_state->vrr_infopacket), (0
), (sizeof(new_crtc_state->vrr_infopacket)))
      sizeof(new_crtc_state->vrr_infopacket))__builtin_memset((&new_crtc_state->vrr_infopacket), (0
), (sizeof(new_crtc_state->vrr_infopacket)));
8118}

8120static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
		struct drm_atomic_state *state,
		struct drm_crtc *crtc,
		struct drm_crtc_state *old_crtc_state,
		struct drm_crtc_state *new_crtc_state,
		bool_Bool enable,
		bool_Bool *lock_and_validation_needed)
8127{
struct dm_atomic_state *dm_state = NULL((void *)0);
struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
struct dc_stream_state *new_stream;
int ret = 0;

/*
* TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
* update changed items
*/
struct amdgpu_crtc *acrtc = NULL((void *)0);
struct amdgpu_dm_connector *aconnector = NULL((void *)0);
struct drm_connector_state *drm_new_conn_state = NULL((void *)0), *drm_old_conn_state = NULL((void *)0);
struct dm_connector_state *dm_new_conn_state = NULL((void *)0), *dm_old_conn_state = NULL((void *)0);

new_stream = NULL((void *)0);

dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);

/* TODO This hack should go away */
if (aconnector && enable) {
/* Make sure fake sink is created in plug-in scenario */
drm_new_conn_state = drm_atomic_get_new_connector_state(state,
					    &aconnector->base);
drm_old_conn_state = drm_atomic_get_old_connector_state(state,
					    &aconnector->base);

if (IS_ERR(drm_new_conn_state)) {
	ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
	goto fail;
}

dm_new_conn_state = to_dm_connector_state(drm_new_conn_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((drm_new_conn_state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});
dm_old_conn_state = to_dm_connector_state(drm_old_conn_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((drm_old_conn_state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
	goto skip_modeset;

new_stream = create_validate_stream_for_sink(aconnector,
					     &new_crtc_state->mode,
					     dm_new_conn_state,
					     dm_old_crtc_state->stream);

/*
 * we can have no stream on ACTION_SET if a display
 * was disconnected during S3, in this case it is not an
 * error, the OS will be updated after detection, and
 * will do the right thing on next atomic commit
 */

if (!new_stream) {
	DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",__drm_dbg(DRM_UT_DRIVER, "%s: Failed to create new stream for crtc %d\n"
, __func__, acrtc->base.base.id)
			__func__, acrtc->base.base.id)__drm_dbg(DRM_UT_DRIVER, "%s: Failed to create new stream for crtc %d\n"
, __func__, acrtc->base.base.id);
	ret = -ENOMEM12;
	goto fail;
}

/*
 * TODO: Check VSDB bits to decide whether this should
 * be enabled or not.
 */
new_stream->triggered_crtc_reset.enabled =
	dm->force_timing_sync;

dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;

ret = fill_hdr_info_packet(drm_new_conn_state,
			   &new_stream->hdr_static_metadata);
if (ret)
	goto fail;

/*
 * If we already removed the old stream from the context
 * (and set the new stream to NULL) then we can't reuse
 * the old stream even if the stream and scaling are unchanged.
 * We'll hit the BUG_ON and black screen.
 *
 * TODO: Refactor this function to allow this check to work
 * in all conditions.
 */
if (dm_new_crtc_state->stream &&
    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
	new_crtc_state->mode_changed = false0;
	DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",__drm_dbg(DRM_UT_DRIVER, "Mode change not required, setting mode_changed to %d"
, new_crtc_state->mode_changed)
			 new_crtc_state->mode_changed)__drm_dbg(DRM_UT_DRIVER, "Mode change not required, setting mode_changed to %d"
, new_crtc_state->mode_changed);
}
}

/* mode_changed flag may get updated above, need to check again */
if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
goto skip_modeset;

DRM_DEBUG_DRIVER(__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
"planes_changed:%d, mode_changed:%d,active_changed:%d,"__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
"connectors_changed:%d\n",__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
acrtc->crtc_id,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->enable,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->active,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->planes_changed,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->mode_changed,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->active_changed,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->connectors_changed)__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
 "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed);

/* Remove stream for any changed/disabled CRTC */
if (!enable) {

if (!dm_old_crtc_state->stream)
	goto skip_modeset;

ret = dm_atomic_get_state(state, &dm_state);
if (ret)
	goto fail;

DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",__drm_dbg(DRM_UT_DRIVER, "Disabling DRM crtc: %d\n", crtc->
base.id)
		crtc->base.id)__drm_dbg(DRM_UT_DRIVER, "Disabling DRM crtc: %d\n", crtc->
base.id);

/* i.e. reset mode */
if (dc_remove_stream_from_ctx(
		dm->dc,
		dm_state->context,
		dm_old_crtc_state->stream) != DC_OK) {
	ret = -EINVAL22;
	goto fail;
}

dc_stream_release(dm_old_crtc_state->stream);
dm_new_crtc_state->stream = NULL((void *)0);

reset_freesync_config_for_crtc(dm_new_crtc_state);

*lock_and_validation_needed = true1;

} else {/* Add stream for any updated/enabled CRTC */
/*
 * Quick fix to prevent NULL pointer on new_stream when
 * added MST connectors not found in existing crtc_state in the chained mode
 * TODO: need to dig out the root cause of that
 */
if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
	goto skip_modeset;

if (modereset_required(new_crtc_state))
	goto skip_modeset;

if (modeset_required(new_crtc_state, new_stream,
		     dm_old_crtc_state->stream)) {

	WARN_ON(dm_new_crtc_state->stream)({ int __ret = !!(dm_new_crtc_state->stream); if (__ret) printf
("WARNING %s failed at %s:%d\n", "dm_new_crtc_state->stream"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 8279); __builtin_expect(!!(__ret), 0); });

	ret = dm_atomic_get_state(state, &dm_state);
	if (ret)
		goto fail;

	dm_new_crtc_state->stream = new_stream;

	dc_stream_retain(new_stream);

	DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",__drm_dbg(DRM_UT_DRIVER, "Enabling DRM crtc: %d\n", crtc->
base.id)
				crtc->base.id)__drm_dbg(DRM_UT_DRIVER, "Enabling DRM crtc: %d\n", crtc->
base.id);

	if (dc_add_stream_to_ctx(
			dm->dc,
			dm_state->context,
			dm_new_crtc_state->stream) != DC_OK) {
		ret = -EINVAL22;
		goto fail;
	}

	*lock_and_validation_needed = true1;
}
}

8304skip_modeset:
/* Release extra reference */
if (new_stream)
 dc_stream_release(new_stream);

/*
* We want to do dc stream updates that do not require a
* full modeset below.
*/
if (!(enable && aconnector && new_crtc_state->active))
return 0;
/*
* Given above conditions, the dc state cannot be NULL because:
* 1. We're in the process of enabling CRTCs (just been added
*    to the dc context, or already is on the context)
* 2. Has a valid connector attached, and
* 3. Is currently active and enabled.
* => The dc stream state currently exists.
*/
BUG_ON(dm_new_crtc_state->stream == NULL)((!(dm_new_crtc_state->stream == ((void *)0))) ? (void)0 :
 __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 8323, "!(dm_new_crtc_state->stream == ((void *)0))"));

/* Scaling or underscan settings */
if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
		drm_atomic_crtc_needs_modeset(new_crtc_state))
update_stream_scaling_settings(
	&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);

/* ABM settings */
dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;

/*
* Color management settings. We also update color properties
* when a modeset is needed, to ensure it gets reprogrammed.
*/
if (dm_new_crtc_state->base.color_mgmt_changed ||
   drm_atomic_crtc_needs_modeset(new_crtc_state)) {
ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
if (ret)
	goto fail;
}

/* Update Freesync settings. */
get_freesync_config_for_crtc(dm_new_crtc_state,
		     dm_new_conn_state);

return ret;

8351fail:
if (new_stream)
dc_stream_release(new_stream);
return ret;
8355}

8357static bool_Bool should_reset_plane(struct drm_atomic_state *state,
	       struct drm_plane *plane,
	       struct drm_plane_state *old_plane_state,
	       struct drm_plane_state *new_plane_state)
8361{
struct drm_plane *other;
struct drm_plane_state *old_other_state, *new_other_state;
struct drm_crtc_state *new_crtc_state;
int i;

/*
* TODO: Remove this hack once the checks below are sufficient
* enough to determine when we need to reset all the planes on
* the stream.
*/
if (state->allow_modeset)
return true1;

/* Exit early if we know that we're adding or removing the plane. */
if (old_plane_state->crtc != new_plane_state->crtc)
return true1;

/* old crtc == new_crtc == NULL, plane not in context. */
if (!new_plane_state->crtc)
return false0;

new_crtc_state =
drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);

if (!new_crtc_state)
return true1;

/* CRTC Degamma changes currently require us to recreate planes. */
if (new_crtc_state->color_mgmt_changed)
return true1;

if (drm_atomic_crtc_needs_modeset(new_crtc_state))
return true1;

/*
* If there are any new primary or overlay planes being added or
* removed then the z-order can potentially change. To ensure
* correct z-order and pipe acquisition the current DC architecture
* requires us to remove and recreate all existing planes.
*
* TODO: Come up with a more elegant solution for this.
*/
for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((other) =
 (state)->planes[i].ptr, (void)(other) , (old_other_state)
 = (state)->planes[i].old_state, (new_other_state) = (state
)->planes[i].new_state, 1))) {} else {
struct dm_plane_state *old_dm_plane_state, *new_dm_plane_state;

if (other->type == DRM_PLANE_TYPE_CURSOR)
	continue;

if (old_other_state->crtc != new_plane_state->crtc &&
    new_other_state->crtc != new_plane_state->crtc)
	continue;

if (old_other_state->crtc != new_other_state->crtc)
	return true1;

/* Src/dst size and scaling updates. */
if (old_other_state->src_w != new_other_state->src_w ||
    old_other_state->src_h != new_other_state->src_h ||
    old_other_state->crtc_w != new_other_state->crtc_w ||
    old_other_state->crtc_h != new_other_state->crtc_h)
	return true1;

/* Rotation / mirroring updates. */
if (old_other_state->rotation != new_other_state->rotation)
	return true1;

/* Blending updates. */
if (old_other_state->pixel_blend_mode !=
    new_other_state->pixel_blend_mode)
	return true1;

/* Alpha updates. */
if (old_other_state->alpha != new_other_state->alpha)
	return true1;

/* Colorspace changes. */
if (old_other_state->color_range != new_other_state->color_range ||
    old_other_state->color_encoding != new_other_state->color_encoding)
	return true1;

/* Framebuffer checks fall at the end. */
if (!old_other_state->fb || !new_other_state->fb)
	continue;

/* Pixel format changes can require bandwidth updates. */
if (old_other_state->fb->format != new_other_state->fb->format)
	return true1;

old_dm_plane_state = to_dm_plane_state(old_other_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (old_other_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});
new_dm_plane_state = to_dm_plane_state(new_other_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_other_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});

/* Tiling and DCC changes also require bandwidth updates. */
if (old_dm_plane_state->tiling_flags !=
    new_dm_plane_state->tiling_flags)
	return true1;
}

return false0;
8460}

8462static int dm_update_plane_state(struct dc *dc,
		 struct drm_atomic_state *state,
		 struct drm_plane *plane,
		 struct drm_plane_state *old_plane_state,
		 struct drm_plane_state *new_plane_state,
		 bool_Bool enable,
		 bool_Bool *lock_and_validation_needed)
8469{

struct dm_atomic_state *dm_state = NULL((void *)0);
struct drm_crtc *new_plane_crtc, *old_plane_crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
struct amdgpu_crtc *new_acrtc;
bool_Bool needs_reset;
int ret = 0;


new_plane_crtc = new_plane_state->crtc;
old_plane_crtc = old_plane_state->crtc;
dm_new_plane_state = to_dm_plane_state(new_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});
dm_old_plane_state = to_dm_plane_state(old_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (old_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});

/*TODO Implement better atomic check for cursor plane */
if (plane->type == DRM_PLANE_TYPE_CURSOR) {
if (!enable || !new_plane_crtc ||
	drm_atomic_plane_disabling(plane->state, new_plane_state))
	return 0;

new_acrtc = to_amdgpu_crtc(new_plane_crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (new_plane_crtc); (struct amdgpu_crtc *)( (char *)__mptr -
 __builtin_offsetof(struct amdgpu_crtc, base) );});

if ((new_plane_state->crtc_w > new_acrtc->max_cursor_width) ||
	(new_plane_state->crtc_h > new_acrtc->max_cursor_height)) {
	DRM_DEBUG_ATOMIC("Bad cursor size %d x %d\n",__drm_dbg(DRM_UT_ATOMIC, "Bad cursor size %d x %d\n", new_plane_state
->crtc_w, new_plane_state->crtc_h)
					 new_plane_state->crtc_w, new_plane_state->crtc_h)__drm_dbg(DRM_UT_ATOMIC, "Bad cursor size %d x %d\n", new_plane_state
->crtc_w, new_plane_state->crtc_h);
	return -EINVAL22;
}

return 0;
}

needs_reset = should_reset_plane(state, plane, old_plane_state,
			 new_plane_state);

/* Remove any changed/removed planes */
if (!enable) {
if (!needs_reset)
	return 0;

if (!old_plane_crtc)
	return 0;

old_crtc_state = drm_atomic_get_old_crtc_state(
		state, old_plane_crtc);
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (!dm_old_crtc_state->stream)
	return 0;

DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",__drm_dbg(DRM_UT_ATOMIC, "Disabling DRM plane: %d on DRM crtc %d\n"
, plane->base.id, old_plane_crtc->base.id)
		plane->base.id, old_plane_crtc->base.id)__drm_dbg(DRM_UT_ATOMIC, "Disabling DRM plane: %d on DRM crtc %d\n"
, plane->base.id, old_plane_crtc->base.id);

ret = dm_atomic_get_state(state, &dm_state);
if (ret)
	return ret;

if (!dc_remove_plane_from_context(
		dc,
		dm_old_crtc_state->stream,
		dm_old_plane_state->dc_state,
		dm_state->context)) {

	return -EINVAL22;
}


dc_plane_state_release(dm_old_plane_state->dc_state);
dm_new_plane_state->dc_state = NULL((void *)0);

*lock_and_validation_needed = true1;

} else { /* Add new planes */
struct dc_plane_state *dc_new_plane_state;

if (drm_atomic_plane_disabling(plane->state, new_plane_state))
	return 0;

if (!new_plane_crtc)
	return 0;

new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (!dm_new_crtc_state->stream)
	return 0;

if (!needs_reset)
	return 0;

ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
if (ret)
	return ret;

WARN_ON(dm_new_plane_state->dc_state)({ int __ret = !!(dm_new_plane_state->dc_state); if (__ret
) printf("WARNING %s failed at %s:%d\n", "dm_new_plane_state->dc_state"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 8566); __builtin_expect(!!(__ret), 0); });

dc_new_plane_state = dc_create_plane_state(dc);
if (!dc_new_plane_state)
	return -ENOMEM12;

DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",__drm_dbg(DRM_UT_DRIVER, "Enabling DRM plane: %d on DRM crtc %d\n"
, plane->base.id, new_plane_crtc->base.id)
		plane->base.id, new_plane_crtc->base.id)__drm_dbg(DRM_UT_DRIVER, "Enabling DRM plane: %d on DRM crtc %d\n"
, plane->base.id, new_plane_crtc->base.id);

ret = fill_dc_plane_attributes(
	drm_to_adev(new_plane_crtc->dev),
	dc_new_plane_state,
	new_plane_state,
	new_crtc_state);
if (ret) {
	dc_plane_state_release(dc_new_plane_state);
	return ret;
}

ret = dm_atomic_get_state(state, &dm_state);
if (ret) {
	dc_plane_state_release(dc_new_plane_state);
	return ret;
}

/*
 * Any atomic check errors that occur after this will
 * not need a release. The plane state will be attached
 * to the stream, and therefore part of the atomic
 * state. It'll be released when the atomic state is
 * cleaned.
 */
if (!dc_add_plane_to_context(
		dc,
		dm_new_crtc_state->stream,
		dc_new_plane_state,
		dm_state->context)) {

	dc_plane_state_release(dc_new_plane_state);
	return -EINVAL22;
}

dm_new_plane_state->dc_state = dc_new_plane_state;

/* Tell DC to do a full surface update every time there
 * is a plane change. Inefficient, but works for now.
 */
dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;

*lock_and_validation_needed = true1;
}


return ret;
8620}

8622#if defined(CONFIG_DRM_AMD_DC_DCN1)
8623static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
8624{
struct drm_connector *connector;
struct drm_connector_state *conn_state;
struct amdgpu_dm_connector *aconnector = NULL((void *)0);
int i;
for_each_new_connector_in_state(state, connector, conn_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (conn_state) = (
state)->connectors[i].new_state, (void)(conn_state) , 1)))
 {} else {
if (conn_state->crtc != crtc)
	continue;

aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (!aconnector->port || !aconnector->mst_port)
	aconnector = NULL((void *)0);
else
	break;
}

if (!aconnector)
return 0;

return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
8644}
8645#endif

8647static int validate_overlay(struct drm_atomic_state *state)
8648{
int i;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
struct drm_plane_state *primary_state, *overlay_state = NULL((void *)0);

/* Check if primary plane is contained inside overlay */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i)for ((i) = ((state)->dev->mode_config.num_total_plane -
 1); (i) >= 0; (i)--) if (!((state)->planes[i].ptr &&
 ((plane) = (state)->planes[i].ptr, (old_plane_state) = (state
)->planes[i].old_state, (new_plane_state) = (state)->planes
[i].new_state, 1))) {} else {
if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
	if (drm_atomic_plane_disabling(plane->state, new_plane_state))
		return 0;

	overlay_state = new_plane_state;
	continue;
}
}

/* check if we're making changes to the overlay plane */
if (!overlay_state)
return 0;

/* check if overlay plane is enabled */
if (!overlay_state->crtc)
return 0;

/* find the primary plane for the CRTC that the overlay is enabled on */
primary_state = drm_atomic_get_plane_state(state, overlay_state->crtc->primary);
if (IS_ERR(primary_state))
return PTR_ERR(primary_state);

/* check if primary plane is enabled */
if (!primary_state->crtc)
return 0;

/* Perform the bounds check to ensure the overlay plane covers the primary */
if (primary_state->crtc_x < overlay_state->crtc_x ||
   primary_state->crtc_y < overlay_state->crtc_y ||
   primary_state->crtc_x + primary_state->crtc_w > overlay_state->crtc_x + overlay_state->crtc_w ||
   primary_state->crtc_y + primary_state->crtc_h > overlay_state->crtc_y + overlay_state->crtc_h) {
DRM_DEBUG_ATOMIC("Overlay plane is enabled with hardware cursor but does not fully cover primary plane\n")__drm_dbg(DRM_UT_ATOMIC, "Overlay plane is enabled with hardware cursor but does not fully cover primary plane\n"
);
return -EINVAL22;
}

return 0;
8692}

8694/**
* amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
* @dev: The DRM device
* @state: The atomic state to commit
*
* Validate that the given atomic state is programmable by DC into hardware.
* This involves constructing a &struct dc_state reflecting the new hardware
* state we wish to commit, then querying DC to see if it is programmable. It's
* important not to modify the existing DC state. Otherwise, atomic_check
* may unexpectedly commit hardware changes.
*
* When validating the DC state, it's important that the right locks are
* acquired. For full updates case which removes/adds/updates streams on one
* CRTC while flipping on another CRTC, acquiring global lock will guarantee
* that any such full update commit will wait for completion of any outstanding
* flip using DRMs synchronization events.
*
* Note that DM adds the affected connectors for all CRTCs in state, when that
* might not seem necessary. This is because DC stream creation requires the
* DC sink, which is tied to the DRM connector state. Cleaning this up should
* be possible but non-trivial - a possible TODO item.
*
* Return: -Error code if validation failed.
*/
8718static int amdgpu_dm_atomic_check(struct drm_device *dev,
		  struct drm_atomic_state *state)
8720{
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_atomic_state *dm_state = NULL((void *)0);
struct dc *dc = adev->dm.dc;
struct drm_connector *connector;
struct drm_connector_state *old_con_state, *new_con_state;
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
enum dc_status status;
int ret, i;
bool_Bool lock_and_validation_needed = false0;

amdgpu_check_debugfs_connector_property_change(adev, state);

ret = drm_atomic_helper_check_modeset(dev, state);
if (ret)
goto fail;

/* Check connector changes */
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((old_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});

/* Skip connectors that are disabled or part of modeset already. */
if (!old_con_state->crtc && !new_con_state->crtc)
	continue;

if (!new_con_state->crtc)
	continue;

new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
if (IS_ERR(new_crtc_state)) {
	ret = PTR_ERR(new_crtc_state);
	goto fail;
}

if (dm_old_con_state->abm_level !=
    dm_new_con_state->abm_level)
	new_crtc_state->connectors_changed = true1;
}

8763#if defined(CONFIG_DRM_AMD_DC_DCN1)
if (dc_resource_is_dsc_encoding_supported(dc)) {
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else {
	if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
		ret = add_affected_mst_dsc_crtcs(state, crtc);
		if (ret)
			goto fail;
	}
}
}
8773#endif
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else {
if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
    !new_crtc_state->color_mgmt_changed &&
    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
	continue;

ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
if (ret)
	goto fail;

if (!new_crtc_state->enable)
	continue;

ret = drm_atomic_add_affected_connectors(state, crtc);
if (ret)
	return ret;

ret = drm_atomic_add_affected_planes(state, crtc);
if (ret)
	goto fail;
}

/*
* Add all primary and overlay planes on the CRTC to the state
* whenever a plane is enabled to maintain correct z-ordering
* and to enable fast surface updates.
*/
drm_for_each_crtc(crtc, dev)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
 ) *__mptr = ((&(dev)->mode_config.crtc_list)->next
); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&(dev)->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
 );})) {
bool_Bool modified = false0;

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (void)(plane) , (old_plane_state)
 = (state)->planes[i].old_state, (new_plane_state) = (state
)->planes[i].new_state, 1))) {} else {
	if (plane->type == DRM_PLANE_TYPE_CURSOR)
		continue;

	if (new_plane_state->crtc == crtc ||
	    old_plane_state->crtc == crtc) {
		modified = true1;
		break;
	}
}

if (!modified)
	continue;

drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask)for ((plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)->
head ) *__mptr = ((&(state->dev)->mode_config.plane_list
)->next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*(plane)), head) );}); &(plane)->head != (&
(state->dev)->mode_config.plane_list); (plane) = ({ const
 __typeof( ((__typeof(*(plane)) *)0)->head ) *__mptr = ((plane
)->head.next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*(plane)), head) );})) if (!((crtc->state->plane_mask
) & drm_plane_mask(plane))) {} else {
	if (plane->type == DRM_PLANE_TYPE_CURSOR)
		continue;

	new_plane_state =
		drm_atomic_get_plane_state(state, plane);

	if (IS_ERR(new_plane_state)) {
		ret = PTR_ERR(new_plane_state);
		goto fail;
	}
}
}

/* Prepass for updating tiling flags on new planes. */
for_each_new_plane_in_state(state, plane, new_plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (void)(plane) , (new_plane_state)
 = (state)->planes[i].new_state, (void)(new_plane_state) ,
 1))) {} else {
struct dm_plane_state *new_dm_plane_state = to_dm_plane_state(new_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});
struct amdgpu_framebuffer *new_afb = to_amdgpu_framebuffer(new_plane_state->fb)({ const __typeof( ((struct amdgpu_framebuffer *)0)->base )
 *__mptr = (new_plane_state->fb); (struct amdgpu_framebuffer
 *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_framebuffer
, base) );});

ret = get_fb_info(new_afb, &new_dm_plane_state->tiling_flags,
		  &new_dm_plane_state->tmz_surface);
if (ret)
	goto fail;
}

/* Remove exiting planes if they are modified */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i)for ((i) = ((state)->dev->mode_config.num_total_plane -
 1); (i) >= 0; (i)--) if (!((state)->planes[i].ptr &&
 ((plane) = (state)->planes[i].ptr, (old_plane_state) = (state
)->planes[i].old_state, (new_plane_state) = (state)->planes
[i].new_state, 1))) {} else {
ret = dm_update_plane_state(dc, state, plane,
			    old_plane_state,
			    new_plane_state,
			    false0,
			    &lock_and_validation_needed);
if (ret)
	goto fail;
}

/* Disable all crtcs which require disable */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else {
ret = dm_update_crtc_state(&adev->dm, state, crtc,
			   old_crtc_state,
			   new_crtc_state,
			   false0,
			   &lock_and_validation_needed);
if (ret)
	goto fail;
}

/* Enable all crtcs which require enable */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, 1))) {} else {
ret = dm_update_crtc_state(&adev->dm, state, crtc,
			   old_crtc_state,
			   new_crtc_state,
			   true1,
			   &lock_and_validation_needed);
if (ret)
	goto fail;
}

ret = validate_overlay(state);
if (ret)
goto fail;

/* Add new/modified planes */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i)for ((i) = ((state)->dev->mode_config.num_total_plane -
 1); (i) >= 0; (i)--) if (!((state)->planes[i].ptr &&
 ((plane) = (state)->planes[i].ptr, (old_plane_state) = (state
)->planes[i].old_state, (new_plane_state) = (state)->planes
[i].new_state, 1))) {} else {
ret = dm_update_plane_state(dc, state, plane,
			    old_plane_state,
			    new_plane_state,
			    true1,
			    &lock_and_validation_needed);
if (ret)
	goto fail;
}

/* Run this here since we want to validate the streams we created */
ret = drm_atomic_helper_check_planes(dev, state);
if (ret)
goto fail;

if (state->legacy_cursor_update) {
/*
 * This is a fast cursor update coming from the plane update
 * helper, check if it can be done asynchronously for better
 * performance.
 */
state->async_update =
	!drm_atomic_helper_async_check(dev, state);

/*
 * Skip the remaining global validation if this is an async
 * update. Cursor updates can be done without affecting
 * state or bandwidth calcs and this avoids the performance
 * penalty of locking the private state object and
 * allocating a new dc_state.
 */
if (state->async_update)
	return 0;
}

/* Check scaling and underscan changes*/
/* TODO Removed scaling changes validation due to inability to commit
* new stream into context w\o causing full reset. Need to
* decide how to handle.
*/
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((old_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (dm_new_con_state->base.crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});

/* Skip any modesets/resets */
if (!acrtc || drm_atomic_crtc_needs_modeset(
		drm_atomic_get_new_crtc_state(state, &acrtc->base)))
	continue;

/* Skip any thing not scale or underscan changes */
if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
	continue;

lock_and_validation_needed = true1;
}

/**
* Streams and planes are reset when there are changes that affect
* bandwidth. Anything that affects bandwidth needs to go through
* DC global validation to ensure that the configuration can be applied
* to hardware.
*
* We have to currently stall out here in atomic_check for outstanding
* commits to finish in this case because our IRQ handlers reference
* DRM state directly - we can end up disabling interrupts too early
* if we don't.
*
* TODO: Remove this stall and drop DM state private objects.
*/
if (lock_and_validation_needed) {
ret = dm_atomic_get_state(state, &dm_state);
if (ret)
	goto fail;

ret = do_aquire_global_lock(dev, state);
if (ret)
	goto fail;

8960#if defined(CONFIG_DRM_AMD_DC_DCN1)
if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
	goto fail;

ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
if (ret)
	goto fail;
8967#endif

/*
 * Perform validation of MST topology in the state:
 * We need to perform MST atomic check before calling
 * dc_validate_global_state(), or there is a chance
 * to get stuck in an infinite loop and hang eventually.
 */
ret = drm_dp_mst_atomic_check(state);
if (ret)
	goto fail;
status = dc_validate_global_state(dc, dm_state->context, false0);
if (status != DC_OK) {
	drm_dbg_atomic(dev,drm_dev_dbg((dev)->dev, DRM_UT_ATOMIC, "DC global validation failure: %s (%d)"
, dc_status_to_str(status), status)
		       "DC global validation failure: %s (%d)",drm_dev_dbg((dev)->dev, DRM_UT_ATOMIC, "DC global validation failure: %s (%d)"
, dc_status_to_str(status), status)
		       dc_status_to_str(status), status)drm_dev_dbg((dev)->dev, DRM_UT_ATOMIC, "DC global validation failure: %s (%d)"
, dc_status_to_str(status), status);
	ret = -EINVAL22;
	goto fail;
}
} else {
/*
 * The commit is a fast update. Fast updates shouldn't change
 * the DC context, affect global validation, and can have their
 * commit work done in parallel with other commits not touching
 * the same resource. If we have a new DC context as part of
 * the DM atomic state from validation we need to free it and
 * retain the existing one instead.
 *
 * Furthermore, since the DM atomic state only contains the DC
 * context and can safely be annulled, we can free the state
 * and clear the associated private object now to free
 * some memory and avoid a possible use-after-free later.
 */

for (i = 0; i < state->num_private_objs; i++) {
	struct drm_private_obj *obj = state->private_objs[i].ptr;

	if (obj->funcs == adev->dm.atomic_obj.funcs) {
		int j = state->num_private_objs-1;

		dm_atomic_destroy_state(obj,
				state->private_objs[i].state);

		/* If i is not at the end of the array then the
		 * last element needs to be moved to where i was
		 * before the array can safely be truncated.
		 */
		if (i != j)
			state->private_objs[i] =
				state->private_objs[j];

		state->private_objs[j].ptr = NULL((void *)0);
		state->private_objs[j].state = NULL((void *)0);
		state->private_objs[j].old_state = NULL((void *)0);
		state->private_objs[j].new_state = NULL((void *)0);

		state->num_private_objs = j;
		break;
	}
}
}

/* Store the overall update type for use later in atomic check. */
for_each_new_crtc_in_state (state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {
struct dm_crtc_state *dm_new_crtc_state =
	to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

dm_new_crtc_state->update_type = lock_and_validation_needed ?
					 UPDATE_TYPE_FULL :
					 UPDATE_TYPE_FAST;
}

/* Must be success */
WARN_ON(ret)({ int __ret = !!(ret); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "ret", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 9040); __builtin_expect(!!(__ret), 0); });
return ret;

9043fail:
if (ret == -EDEADLK11)
DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n")__drm_dbg(DRM_UT_DRIVER, "Atomic check stopped to avoid deadlock.\n"
);
else if (ret == -EINTR4 || ret == -EAGAIN35 || ret == -ERESTARTSYS4)
DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n")__drm_dbg(DRM_UT_DRIVER, "Atomic check stopped due to signal.\n"
);
else
DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret)__drm_dbg(DRM_UT_DRIVER, "Atomic check failed with err: %d \n"
, ret);

return ret;
9052}

9054static bool_Bool is_dp_capable_without_timing_msa(struct dc *dc,
			     struct amdgpu_dm_connector *amdgpu_dm_connector)
9056{
uint8_t dpcd_data;
bool_Bool capable = false0;

if (amdgpu_dm_connector->dc_link &&
dm_helpers_dp_read_dpcd(
		NULL((void *)0),
		amdgpu_dm_connector->dc_link,
		DP_DOWN_STREAM_PORT_COUNT0x007,
		&dpcd_data,
		sizeof(dpcd_data))) {
capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED(1 << 6)) ? true1:false0;
}

return capable;
9071}
9072void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
			struct edid *edid)
9074{
int i;
bool_Bool edid_check_required;
struct detailed_timing *timing;
struct detailed_non_pixel *data;
struct detailed_data_monitor_range *range;
struct amdgpu_dm_connector *amdgpu_dm_connector =
	to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct dm_connector_state *dm_con_state = NULL((void *)0);

struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
bool_Bool freesync_capable = false0;

if (!connector->state) {
DRM_ERROR("%s - Connector has no state", __func__)__drm_err("%s - Connector has no state", __func__);
goto update;
}

if (!edid) {
dm_con_state = to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

amdgpu_dm_connector->min_vfreq = 0;
amdgpu_dm_connector->max_vfreq = 0;
amdgpu_dm_connector->pixel_clock_mhz = 0;

goto update;
}

dm_con_state = to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

edid_check_required = false0;
if (!amdgpu_dm_connector->dc_sink) {
DRM_ERROR("dc_sink NULL, could not add free_sync module.\n")__drm_err("dc_sink NULL, could not add free_sync module.\n");
goto update;
}
if (!adev->dm.freesync_module)
goto update;
/*
* if edid non zero restrict freesync only for dp and edp
*/
if (edid) {
if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
	|| amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
	edid_check_required = is_dp_capable_without_timing_msa(
				adev->dm.dc,
				amdgpu_dm_connector);
}
}
if (edid_check_required == true1 && (edid->version > 1 ||
  (edid->version == 1 && edid->revision > 1))) {
for (i = 0; i < 4; i++) {

	timing	= &edid->detailed_timings[i];
	data	= &timing->data.other_data;
	range	= &data->data.range;
	/*
	 * Check if monitor has continuous frequency mode
	 */
	if (data->type != EDID_DETAIL_MONITOR_RANGE0xfd)
		continue;
	/*
	 * Check for flag range limits only. If flag == 1 then
	 * no additional timing information provided.
	 * Default GTF, GTF Secondary curve and CVT are not
	 * supported
	 */
	if (range->flags != 1)
		continue;

	amdgpu_dm_connector->min_vfreq = range->min_vfreq;
	amdgpu_dm_connector->max_vfreq = range->max_vfreq;
	amdgpu_dm_connector->pixel_clock_mhz =
		range->pixel_clock_mhz * 10;
	break;
}

if (amdgpu_dm_connector->max_vfreq -
    amdgpu_dm_connector->min_vfreq > 10) {

	freesync_capable = true1;
}
}

9158update:
if (dm_con_state)
dm_con_state->freesync_capable = freesync_capable;

if (connector->vrr_capable_property)
drm_connector_set_vrr_capable_property(connector,
				       freesync_capable);
9165}

9167static void amdgpu_dm_set_psr_caps(struct dc_link *link)
9168{
uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE2];

if (!(link->connector_signal & SIGNAL_TYPE_EDP))
return;
if (link->type == dc_connection_none)
return;
if (dm_helpers_dp_read_dpcd(NULL((void *)0), link, DP_PSR_SUPPORT0x070,
			dpcd_data, sizeof(dpcd_data))) {
link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];

if (dpcd_data[0] == 0) {
	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
	link->psr_settings.psr_feature_enabled = false0;
} else {
	link->psr_settings.psr_version = DC_PSR_VERSION_1;
	link->psr_settings.psr_feature_enabled = true1;
}

DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled)printk("\0016" "[" "drm" "] " "PSR support:%d\n", link->psr_settings
.psr_feature_enabled);
}
9189}

9191/*
* amdgpu_dm_link_setup_psr() - configure psr link
* @stream: stream state
*
* Return: true if success
*/
9197static bool_Bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
9198{
struct dc_link *link = NULL((void *)0);
struct psr_config psr_config = {0};
struct psr_context psr_context = {0};
bool_Bool ret = false0;

if (stream == NULL((void *)0))
return false0;

link = stream->link;

psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;

if (psr_config.psr_version > 0) {
psr_config.psr_exit_link_training_required = 0x1;
psr_config.psr_frame_capture_indication_req = 0;
psr_config.psr_rfb_setup_time = 0x37;
psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
psr_config.allow_smu_optimizations = 0x0;

ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);

}
DRM_DEBUG_DRIVER("PSR link: %d\n",	link->psr_settings.psr_feature_enabled)__drm_dbg(DRM_UT_DRIVER, "PSR link: %d\n", link->psr_settings
.psr_feature_enabled);

return ret;
9224}

9226/*
* amdgpu_dm_psr_enable() - enable psr f/w
* @stream: stream state
*
* Return: true if success
*/
9232bool_Bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
9233{
struct dc_link *link = stream->link;
unsigned int vsync_rate_hz = 0;
struct dc_static_screen_params params = {0};
/* Calculate number of static frames before generating interrupt to
* enter PSR.
*/
// Init fail safe of 2 frames static
unsigned int num_frames_static = 2;

DRM_DEBUG_DRIVER("Enabling psr...\n")__drm_dbg(DRM_UT_DRIVER, "Enabling psr...\n");

vsync_rate_hz = div64_u64(div64_u64((
	stream->timing.pix_clk_100hz * 100),
	stream->timing.v_total),
	stream->timing.h_total);

/* Round up
* Calculate number of frames such that at least 30 ms of time has
* passed.
*/
if (vsync_rate_hz != 0) {
unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
num_frames_static = (30000 / frame_time_microsec) + 1;
}

params.triggers.cursor_update = true1;
params.triggers.overlay_update = true1;
params.triggers.surface_update = true1;
params.num_frames = num_frames_static;

dc_stream_set_static_screen_params(link->ctx->dc,
			   &stream, 1,
			   &params);

return dc_link_set_psr_allow_active(link, true1, false0);
9269}

9271/*
* amdgpu_dm_psr_disable() - disable psr f/w
* @stream:  stream state
*
* Return: true if success
*/
9277static bool_Bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
9278{

DRM_DEBUG_DRIVER("Disabling psr...\n")__drm_dbg(DRM_UT_DRIVER, "Disabling psr...\n");

return dc_link_set_psr_allow_active(stream->link, false0, true1);
9283}

9285/*
* amdgpu_dm_psr_disable() - disable psr f/w
* if psr is enabled on any stream
*
* Return: true if success
*/
9291static bool_Bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
9292{
DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n")__drm_dbg(DRM_UT_DRIVER, "Disabling psr if psr is enabled on any stream\n"
);
return dc_set_psr_allow_active(dm->dc, false0);
9295}

9297void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
9298{
struct amdgpu_device *adev = drm_to_adev(dev);
struct dc *dc = adev->dm.dc;
int i;

mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock);
if (dc->current_state) {
for (i = 0; i < dc->current_state->stream_count; ++i)
	dc->current_state->streams[i]
		->triggered_crtc_reset.enabled =
		adev->dm.force_timing_sync;

dm_enable_per_frame_crtc_master_sync(dc->current_state);
dc_trigger_sync(dc, dc->current_state);
}
mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);
9314}