/usr/src/sys/dev/pci/if

Bug Summary

File:	dev/pci/if_em.c
Warning:	line 1288, column 15 Assigned value is garbage or undefined
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name if_em.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/if_em.c
1/**************************************************************************

3Copyright (c) 2001-2003, Intel Corporation
4All rights reserved.

6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice,
  this list of conditions and the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright
  notice, this list of conditions and the following disclaimer in the
  documentation and/or other materials provided with the distribution.

3. Neither the name of the Intel Corporation nor the names of its
  contributors may be used to endorse or promote products derived from
  this software without specific prior written permission.

20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.

32***************************************************************************/

34/* $OpenBSD: if_em.c,v 1.360 2022/01/09 05:42:50 jsg Exp $ */
35/* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */

37#include <dev/pci/if_em.h>
38#include <dev/pci/if_em_soc.h>

40/*********************************************************************
*  Driver version
*********************************************************************/

44#define EM_DRIVER_VERSION"6.2.9"	"6.2.9"

46/*********************************************************************
*  PCI Device ID Table
*********************************************************************/
49const struct pci_matchid em_devices[] = {
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT0x1096 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT0x1098 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT0x10ba },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT0x10bb },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82540EM0x100e },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82540EM_LOM0x1015 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82540EP0x1017 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82540EP_LOM0x1016 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82540EP_LP0x101e },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82541EI0x1013 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82541EI_MOBILE0x1018 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82541ER0x1078 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82541ER_LOM0x1014 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82541GI0x1076 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82541GI_LF0x107c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82541GI_MOBILE0x1077 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_825420x1000 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82543GC_COPPER0x1004 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82543GC_FIBER0x1001 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82544EI_COPPER0x1008 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82544EI_FIBER0x1009 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82544GC_COPPER0x100c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82544GC_LOM0x100d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82545EM_COPPER0x100f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82545EM_FIBER0x1011 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82545GM_COPPER0x1026 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82545GM_FIBER0x1027 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82545GM_SERDES0x1028 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546EB_COPPER0x1010 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546EB_FIBER0x1012 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546EB_QUAD_CPR0x101d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546GB_COPPER0x1079 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546GB_FIBER0x107a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546GB_PCIE0x108a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR0x1099 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K0x10b5 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546GB_SERDES0x107b },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82546GB_20x109b },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82547EI0x1019 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82547EI_MOBILE0x101a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82547GI0x1075 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_AF0x10a1 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_AT0x10a0 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_COPPER0x105e },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_FIBER0x105f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR0x10a4 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP0x10bc },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR0x10a5 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_SERDES0x1060 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL0x10d9 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD0x10da },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR0x10d5 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82572EI_COPPER0x107d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82572EI_FIBER0x107e },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82572EI_SERDES0x107f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82572EI0x10b9 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82573E0x108b },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82573E_IAMT0x108c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82573E_PM0x10b3 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82573L0x109a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82573L_PL_10x10b0 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82573L_PL_20x10b4 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82573V_PM0x10b2 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82574L0x10d3 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82574LA0x10f6 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82575EB_COPPER0x10a7 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82575EB_SERDES0x10a9 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR0x10d6 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82575GB_QP_PM0x10e2 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_825760x10c9 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82576_FIBER0x10e6 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82576_SERDES0x10e7 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82576_QUAD_COPPER0x10e8 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82576_QUAD_CU_ET20x1526 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82576_NS0x150a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82576_NS_SERDES0x1518 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82576_SERDES_QUAD0x150d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82577LC0x10eb },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82577LM0x10ea },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82578DC0x10f0 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82578DM0x10ef },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82579LM0x1502 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82579V0x1503 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I210_COPPER0x1533 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I210_COPPER_OEM10x1534 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I210_COPPER_IT0x1535 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I210_FIBER0x1536 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I210_SERDES0x1537 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I210_SGMII0x1538 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I210_COPPER_NF0x157b },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I210_SERDES_NF0x157c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I211_COPPER0x1539 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I217_LM0x153a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I217_V0x153b },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I218_LM0x155a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I218_LM_20x15a0 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I218_LM_30x15a2 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I218_V0x1559 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I218_V_20x15a1 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I218_V_30x15a3 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM0x156f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM20x15b7 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM30x15b9 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM40x15d7 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM50x15e3 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM60x15bd },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM70x15bb },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM80x15df },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM90x15e1 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM100x0d4e },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM110x0d4c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM120x0d53 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM130x15fb },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM140x15f9 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM150x15f4 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM160x1a1e },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM170x1a1c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM180x550a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_LM190x550c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V0x1570 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V20x15b8 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V40x15d8 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V50x15d6 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V60x15be },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V70x15bc },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V80x15e0 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V90x15e2 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V100x0d4f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V110x0d4d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V120x0d55 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V130x15fc },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V140x15fa },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V150x15f5 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V160x1a1f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V170x1a1d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V180x550b },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I219_V190x550d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82580_COPPER0x150e },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82580_FIBER0x150f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82580_SERDES0x1510 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82580_SGMII0x1511 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82580_COPPER_DUAL0x1516 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82580_QUAD_FIBER0x1527 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_DH89XXCC_SGMII0x0438 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_DH89XXCC_SERDES0x043a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE0x043c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_DH89XXCC_SFP0x0440 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_82583V0x150c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I350_COPPER0x1521 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I350_FIBER0x1522 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I350_SERDES0x1523 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I350_SGMII0x1524 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I354_BP_1GBPS0x1f40 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I354_BP_2_5GBPS0x1f45 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I354_SGMII0x1f41 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH8_82567V_30x1501 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH8_IFE0x104c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH8_IFE_G0x10c5 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH8_IFE_GT0x10c4 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH8_IGP_AMT0x104a },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH8_IGP_C0x104b },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH8_IGP_M0x104d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT0x1049 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_BM0x10e5 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_IFE0x10c0 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_IFE_G0x10c2 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_IFE_GT0x10c3 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_IGP_AMT0x10bd },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_IGP_C0x294c },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_IGP_M0x10bf },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT0x10f5 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH9_IGP_M_V0x10cb },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH10_D_BM_LF0x10df },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH10_D_BM_LM0x10de },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH10_D_BM_V0x1525 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH10_R_BM_LF0x10cd },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH10_R_BM_LM0x10cc },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_ICH10_R_BM_V0x10ce },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_EP80579_LAN_10x5040 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_EP80579_LAN_20x5044 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_EP80579_LAN_30x5048 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_EP80579_LAN_40x5041 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_EP80579_LAN_50x5045 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_EP80579_LAN_60x5049 }
234};

236/*********************************************************************
*  Function prototypes
*********************************************************************/
239int  em_probe(struct device *, void *, void *);
240void em_attach(struct device *, struct device *, void *);
241void em_defer_attach(struct device*);
242int  em_detach(struct device *, int);
243int  em_activate(struct device *, int);
244int  em_intr(void *);
245int  em_allocate_legacy(struct em_softc *);
246void em_start(struct ifqueue *);
247int  em_ioctl(struct ifnet *, u_long, caddr_t);
248void em_watchdog(struct ifnet *);
249void em_init(void *);
250void em_stop(void *, int);
251void em_media_status(struct ifnet *, struct ifmediareq *);
252int  em_media_change(struct ifnet *);
253uint64_t  em_flowstatus(struct em_softc *);
254void em_identify_hardware(struct em_softc *);
255int  em_allocate_pci_resources(struct em_softc *);
256void em_free_pci_resources(struct em_softc *);
257void em_local_timer(void *);
258int  em_hardware_init(struct em_softc *);
259void em_setup_interface(struct em_softc *);
260int  em_setup_transmit_structures(struct em_softc *);
261void em_initialize_transmit_unit(struct em_softc *);
262int  em_setup_receive_structures(struct em_softc *);
263void em_initialize_receive_unit(struct em_softc *);
264void em_enable_intr(struct em_softc *);
265void em_disable_intr(struct em_softc *);
266void em_free_transmit_structures(struct em_softc *);
267void em_free_receive_structures(struct em_softc *);
268void em_update_stats_counters(struct em_softc *);
269void em_disable_aspm(struct em_softc *);
270void em_txeof(struct em_queue *);
271int  em_allocate_receive_structures(struct em_softc *);
272int  em_allocate_transmit_structures(struct em_softc *);
273int  em_allocate_desc_rings(struct em_softc *);
274int  em_rxfill(struct em_queue *);
275void em_rxrefill(void *);
276int  em_rxeof(struct em_queue *);
277void em_receive_checksum(struct em_softc *, struct em_rx_desc *,
	 struct mbuf *);
279u_int	em_transmit_checksum_setup(struct em_queue *, struct mbuf *, u_int,
   u_int32_t *, u_int32_t *);
281void em_iff(struct em_softc *);
282void em_update_link_status(struct em_softc *);
283int  em_get_buf(struct em_queue *, int);
284void em_enable_hw_vlans(struct em_softc *);
285u_int em_encap(struct em_queue *, struct mbuf *);
286void em_smartspeed(struct em_softc *);
287int  em_82547_fifo_workaround(struct em_softc *, int);
288void em_82547_update_fifo_head(struct em_softc *, int);
289int  em_82547_tx_fifo_reset(struct em_softc *);
290void em_82547_move_tail(void *arg);
291void em_82547_move_tail_locked(struct em_softc *);
292int  em_dma_malloc(struct em_softc *, bus_size_t, struct em_dma_alloc *);
293void em_dma_free(struct em_softc *, struct em_dma_alloc *);
294u_int32_t em_fill_descriptors(u_int64_t address, u_int32_t length,
	      PDESC_ARRAY desc_array);
296void em_flush_tx_ring(struct em_queue *);
297void em_flush_rx_ring(struct em_queue *);
298void em_flush_desc_rings(struct em_softc *);
299int em_get_sffpage(struct em_softc *, struct if_sffpage *);

301#ifndef SMALL_KERNEL
302/* MSIX/Multiqueue functions */
303int  em_allocate_msix(struct em_softc *);
304int  em_setup_queues_msix(struct em_softc *);
305int  em_queue_intr_msix(void *);
306int  em_link_intr_msix(void *);
307void em_enable_queue_intr_msix(struct em_queue *);
308#else
309#define em_allocate_msix(_sc) 	(-1)
310#endif

312#if NKSTAT0 > 0
313void	em_kstat_attach(struct em_softc *);
314int	em_kstat_read(struct kstat *);
315void	em_tbi_adjust_stats(struct em_softc *, uint32_t, uint8_t *);
316#endif

318/*********************************************************************
*  OpenBSD Device Interface Entry Points
*********************************************************************/

322struct cfattach em_ca = {
sizeof(struct em_softc), em_probe, em_attach, em_detach,
em_activate
325};

327struct cfdriver em_cd = {
NULL((void *)0), "em", DV_IFNET
329};

331static int em_smart_pwr_down = FALSE0;
332int em_enable_msix = 0;

334/*********************************************************************
*  Device identification routine
*
*  em_probe determines if the driver should be loaded on
*  adapter based on PCI vendor/device id of the adapter.
*
*  return 0 on no match, positive on match
*********************************************************************/

343int
344em_probe(struct device *parent, void *match, void *aux)
345{
INIT_DEBUGOUT("em_probe: begin")if (0) printf("em_probe: begin" "\n");

return (pci_matchbyid((struct pci_attach_args *)aux, em_devices,
   nitems(em_devices)(sizeof((em_devices)) / sizeof((em_devices)[0]))));
350}

352void
353em_defer_attach(struct device *self)
354{
struct em_softc *sc = (struct em_softc *)self;
struct pci_attach_args *pa = &sc->osdep.em_pa;
pci_chipset_tag_t	pc = pa->pa_pc;
void *gcu;

INIT_DEBUGOUT("em_defer_attach: begin")if (0) printf("em_defer_attach: begin" "\n");

if ((gcu = em_lookup_gcu(self)) == 0) {
printf("%s: No GCU found, deferred attachment failed\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));

if (sc->sc_intrhand)
	pci_intr_disestablish(pc, sc->sc_intrhand);
sc->sc_intrhand = 0;

em_stop(sc, 1);

em_free_pci_resources(sc);

return;
}

sc->hw.gcu = gcu;

em_attach_miibus(self);			

em_setup_interface(sc);			

em_setup_link(&sc->hw);			

em_update_link_status(sc);
386}

388/*********************************************************************
*  Device initialization routine
*
*  The attach entry point is called when the driver is being loaded.
*  This routine identifies the type of hardware, allocates all resources
*  and initializes the hardware.
*
*********************************************************************/

397void 
398em_attach(struct device *parent, struct device *self, void *aux)
399{
struct pci_attach_args *pa = aux;
struct em_softc *sc;
int defer = 0;
  
INIT_DEBUGOUT("em_attach: begin")if (0) printf("em_attach: begin" "\n");

sc = (struct em_softc *)self;
sc->sc_dmat = pa->pa_dmat;
sc->osdep.em_pa = *pa;

timeout_set(&sc->timer_handle, em_local_timer, sc);
timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc);

rw_init(&sc->sfflock, "emsff")_rw_init_flags(&sc->sfflock, "emsff", 0, ((void *)0));

/* Determine hardware revision */
em_identify_hardware(sc);

/*
* Only use MSI on the newer PCIe parts, with the exception
* of 82571/82572 due to "Byte Enables 2 and 3 Are Not Set" errata
*/
if (sc->hw.mac_type <= em_82572)
sc->osdep.em_pa.pa_flags &= ~PCI_FLAGS_MSI_ENABLED0x20;

/* Parameters (to be read from user) */
if (sc->hw.mac_type >= em_82544) {
sc->sc_tx_slots = EM_MAX_TXD512;
sc->sc_rx_slots = EM_MAX_RXD256;
} else {
sc->sc_tx_slots = EM_MAX_TXD_82543256;
sc->sc_rx_slots = EM_MAX_RXD_82543256;
}
sc->tx_int_delay = EM_TIDV64;
sc->tx_abs_int_delay = EM_TADV64;
sc->rx_int_delay = EM_RDTR0;
sc->rx_abs_int_delay = EM_RADV64;
sc->hw.autoneg = DO_AUTO_NEG1;
sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT0;
sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT(0x0001 | 0x0002 | 0x0004 | 0x0008 | 0x0020);
sc->hw.tbi_compatibility_en = TRUE1;
sc->sc_rx_buffer_len = EM_RXBUFFER_20482048;

sc->hw.phy_init_script = 1;
sc->hw.phy_reset_disable = FALSE0;

446#ifndef EM_MASTER_SLAVE
sc->hw.master_slave = em_ms_hw_default;
448#else
sc->hw.master_slave = EM_MASTER_SLAVE;
450#endif

/*
* This controls when hardware reports transmit completion
* status.   
*/
sc->hw.report_tx_early = 1;

if (em_allocate_pci_resources(sc))
goto err_pci;

/* Initialize eeprom parameters */
em_init_eeprom_params(&sc->hw);

/*
* Set the max frame size assuming standard Ethernet
* sized frames.
*/
switch (sc->hw.mac_type) {
case em_82573:
{
	uint16_t	eeprom_data = 0;

	/*
	 * 82573 only supports Jumbo frames
	 * if ASPM is disabled.
	 */
	em_read_eeprom(&sc->hw, EEPROM_INIT_3GIO_30x001A,
	    1, &eeprom_data);
	if (eeprom_data & EEPROM_WORD1A_ASPM_MASK0x000C) {
		sc->hw.max_frame_size = ETHER_MAX_LEN1518;
		break;
	}
	/* Allow Jumbo frames */
	/* FALLTHROUGH */
}
case em_82571:
case em_82572:
case em_82574:
case em_82575:
case em_82576:
case em_82580:
case em_i210:
case em_i350:
case em_ich9lan:
case em_ich10lan:
case em_pch2lan:
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
case em_80003es2lan:
	/* 9K Jumbo Frame size */
	sc->hw.max_frame_size = 9234;
	break;
case em_pchlan:
	sc->hw.max_frame_size = 4096;
	break;
case em_82542_rev2_0:
case em_82542_rev2_1:
case em_ich8lan:
	/* Adapters that do not support Jumbo frames */
	sc->hw.max_frame_size = ETHER_MAX_LEN1518;
	break;
default:
	sc->hw.max_frame_size =
	    MAX_JUMBO_FRAME_SIZE0x3F00;
}

sc->hw.min_frame_size = 
   ETHER_MIN_LEN64 + ETHER_CRC_LEN4;

if (em_allocate_desc_rings(sc) != 0) {
printf("%s: Unable to allocate descriptor ring memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto err_pci;
}

/* Initialize the hardware */
if ((defer = em_hardware_init(sc))) {
if (defer == EAGAIN35)
	config_defer(self, em_defer_attach);
else {
	printf("%s: Unable to initialize the hardware\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto err_pci;
}
}

if (sc->hw.mac_type == em_80003es2lan || sc->hw.mac_type == em_82575 ||
   sc->hw.mac_type == em_82576 ||
   sc->hw.mac_type == em_82580 || sc->hw.mac_type == em_i210 ||
   sc->hw.mac_type == em_i350) {
uint32_t reg = EM_READ_REG(&sc->hw, E1000_STATUS)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (0x00008)));
sc->hw.bus_func = (reg & E1000_STATUS_FUNC_MASK0x0000000C) >>
    E1000_STATUS_FUNC_SHIFT2;

switch (sc->hw.bus_func) {
case 0:
	sc->hw.swfw = E1000_SWFW_PHY0_SM0x0002;
	break;
case 1:
	sc->hw.swfw = E1000_SWFW_PHY1_SM0x0004;
	break;
case 2:
	sc->hw.swfw = E1000_SWFW_PHY2_SM0x0020;
	break;
case 3:
	sc->hw.swfw = E1000_SWFW_PHY3_SM0x0040;
	break;
}
} else {
sc->hw.bus_func = 0;
}

/* Copy the permanent MAC address out of the EEPROM */
if (em_read_mac_addr(&sc->hw) < 0) {
printf("%s: EEPROM read error while reading mac address\n",
       DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto err_pci;
}

bcopy(sc->hw.mac_addr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN6);

/* Setup OS specific network interface */
if (!defer)
em_setup_interface(sc);

/* Initialize statistics */
em_clear_hw_cntrs(&sc->hw);
579#if NKSTAT0 > 0
em_kstat_attach(sc);
581#endif
sc->hw.get_link_status = 1;
if (!defer)
em_update_link_status(sc);

586#ifdef EM_DEBUG
printf(", mac %#x phy %#x", sc->hw.mac_type, sc->hw.phy_type);
588#endif
printf(", address %s\n", ether_sprintf(sc->sc_ac.ac_enaddr));

/* Indicate SOL/IDER usage */
if (em_check_phy_reset_block(&sc->hw))
printf("%s: PHY reset is blocked due to SOL/IDER session.\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));

/* Identify 82544 on PCI-X */
em_get_bus_info(&sc->hw);
if (sc->hw.bus_type == em_bus_type_pcix &&
   sc->hw.mac_type == em_82544)
sc->pcix_82544 = TRUE1;
      else
sc->pcix_82544 = FALSE0;

sc->hw.icp_xxxx_is_link_up = FALSE0;

INIT_DEBUGOUT("em_attach: end")if (0) printf("em_attach: end" "\n");
return;

609err_pci:
em_free_pci_resources(sc);
611}

613/*********************************************************************
*  Transmit entry point
*
*  em_start is called by the stack to initiate a transmit.
*  The driver will remain in this routine as long as there are
*  packets to transmit and transmit resources are available.
*  In case resources are not available stack is notified and
*  the packet is requeued.
**********************************************************************/

623void
624em_start(struct ifqueue *ifq)
625{
struct ifnet *ifp = ifq->ifq_if;
struct em_softc *sc = ifp->if_softc;
u_int head, free, used;
struct mbuf *m;
int post = 0;
struct em_queue *que = sc->queues; /* Use only first queue. */

if (!sc->link_active) {
1
Assuming field 'link_active' is not equal to 0→
2
←
Taking false branch→
ifq_purge(ifq);
return;
}

/* calculate free space */
head = que->tx.sc_tx_desc_head;
free = que->tx.sc_tx_desc_tail;
if (free <= head)
3
←
Assuming 'free' is > 'head'→
4
←
Taking false branch→
free += sc->sc_tx_slots;
free -= head;

if (sc->hw.mac_type != em_82547) {
5
←
Assuming field 'mac_type' is equal to em_82547→
6
←
Taking false branch→
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08))
    0, que->tx.sc_tx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08));
}

for (;;) {
7
←
Loop condition is true.  Entering loop body→
/* use 2 because cksum setup can use an extra slot */
if (EM_MAX_SCATTER64 + 2 > free) {
8
←
Assuming the condition is false→
9
←
Taking false branch→
	ifq_set_oactive(ifq);
	break;
}

m = ifq_dequeue(ifq);
if (m == NULL((void *)0))
10
←
Assuming 'm' is not equal to NULL→
11
←
Taking false branch→
	break;

used = em_encap(que, m);
12
←
Calling 'em_encap'→
if (used == 0) {
	m_freem(m);
	continue;
}

KASSERT(used <= free)((used <= free) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_em.c"
, 668, "used <= free"));

free -= used;

672#if NBPFILTER1 > 0
/* Send a copy of the frame to the BPF listener */
if (ifp->if_bpf)
	bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
676#endif

/* Set timeout in case hardware has problems transmitting */
ifp->if_timer = EM_TX_TIMEOUT5;

if (sc->hw.mac_type == em_82547) {
	int len = m->m_pkthdrM_dat.MH.MH_pkthdr.len;

	if (sc->link_duplex == HALF_DUPLEX1)
		em_82547_move_tail_locked(sc);
	else {
		E1000_WRITE_REG(&sc->hw, TDT(que->me),((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03818 + ((que->me) *
 0x100)) : (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40)))))), (que->tx.sc_tx_desc_head
)))
		    que->tx.sc_tx_desc_head)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03818 + ((que->me) *
 0x100)) : (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40)))))), (que->tx.sc_tx_desc_head
)));
		em_82547_update_fifo_head(sc, len);
	}
}

post = 1;
}

if (sc->hw.mac_type != em_82547) {
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04))
    0, que->tx.sc_tx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04))
    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04));
/* 
 * Advance the Transmit Descriptor Tail (Tdt),
 * this tells the E1000 that this frame is
 * available to transmit.
 */
if (post)
	E1000_WRITE_REG(&sc->hw, TDT(que->me),((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03818 + ((que->me) *
 0x100)) : (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40)))))), (que->tx.sc_tx_desc_head
)))
	    que->tx.sc_tx_desc_head)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03818 + ((que->me) *
 0x100)) : (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40)))))), (que->tx.sc_tx_desc_head
)));
}
709}

711/*********************************************************************
*  Ioctl entry point
*
*  em_ioctl is called when the user wants to configure the
*  interface.
*
*  return 0 on success, positive on failure
**********************************************************************/

720int
721em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
722{
int		error = 0;
struct ifreq   *ifr = (struct ifreq *) data;
struct em_softc *sc = ifp->if_softc;
int s;

s = splnet()splraise(0x7);

switch (command) {
case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface "if (0) printf("ioctl rcv'd: SIOCSIFADDR (Set Interface " "Addr)"
 "\n")
	       "Addr)")if (0) printf("ioctl rcv'd: SIOCSIFADDR (Set Interface " "Addr)"
 "\n");
if (!(ifp->if_flags & IFF_UP0x1)) {
	ifp->if_flags |= IFF_UP0x1;
	em_init(sc);
}
break;

case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)")if (0) printf("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)"
 "\n");
if (ifp->if_flags & IFF_UP0x1) {
	if (ifp->if_flags & IFF_RUNNING0x40)
		error = ENETRESET52;
	else
		em_init(sc);
} else {
	if (ifp->if_flags & IFF_RUNNING0x40)
		em_stop(sc, 0);
}
break;

case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((55))):
/* Check SOL/IDER usage */
if (em_check_phy_reset_block(&sc->hw)) {
	printf("%s: Media change is blocked due to SOL/IDER session.\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	break;
}
case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((56))):
IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)")if (0) printf("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)"
 "\n");
error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
break;

case SIOCGIFRXR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((170))):
error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_dataifr_ifru.ifru_data,
    NULL((void *)0), EM_MCLBYTES(2048 + 2), &sc->queues->rx.sc_rx_ring);
break;

case SIOCGIFSFFPAGE(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct if_sffpage) & 0x1fff) << 16) | ((('i')) <<
 8) | ((57))):
error = rw_enter(&sc->sfflock, RW_WRITE0x0001UL|RW_INTR0x0010UL);
if (error != 0)
	break;

error = em_get_sffpage(sc, (struct if_sffpage *)data);
rw_exit(&sc->sfflock);
break;

default:
error = ether_ioctl(ifp, &sc->sc_ac, command, data);
}

if (error == ENETRESET52) {
if (ifp->if_flags & IFF_RUNNING0x40) {
	em_disable_intr(sc);
	em_iff(sc);
	if (sc->hw.mac_type == em_82542_rev2_0)
		em_initialize_receive_unit(sc);
	em_enable_intr(sc);
}
error = 0;
}

splx(s)spllower(s);
return (error);
796}

798/*********************************************************************
*  Watchdog entry point
*
*  This routine is called whenever hardware quits transmitting.
*
**********************************************************************/

805void
806em_watchdog(struct ifnet *ifp)
807{
struct em_softc *sc = ifp->if_softc;
struct em_queue *que = sc->queues; /* Use only first queue. */


/* If we are in this routine because of pause frames, then
* don't reset the hardware.
*/
if (E1000_READ_REG(&sc->hw, STATUS)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00008 : em_translate_82542_register(0x00008))))) & E1000_STATUS_TXOFF0x00000010) {
ifp->if_timer = EM_TX_TIMEOUT5;
return;
}
printf("%s: watchdog: head %u tail %u TDH %u TDT %u\n",
   DEVNAME(sc)((sc)->sc_dev.dv_xname),
   que->tx.sc_tx_desc_head, que->tx.sc_tx_desc_tail,
   E1000_READ_REG(&sc->hw, TDH(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? ((que->me) < 4 ? (0x03810 + ((que->me) * 0x100)) :
 (0x0E010 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03810 + ((que->me) * 0x100)) : (
0x0E010 + ((que->me) * 0x40)))))))),
   E1000_READ_REG(&sc->hw, TDT(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? ((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) :
 (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40)))))))));

em_init(sc);

sc->watchdog_events++;
828}

830/*********************************************************************
*  Init entry point
*
*  This routine is used in two ways. It is used by the stack as
*  init entry point in network interface structure. It is also used
*  by the driver as a hw/sw initialization routine to get to a
*  consistent state.
*
**********************************************************************/

840void
841em_init(void *arg)
842{
struct em_softc *sc = arg;
struct ifnet   *ifp = &sc->sc_ac.ac_if;
uint32_t	pba;
int s;

s = splnet()splraise(0x7);

INIT_DEBUGOUT("em_init: begin")if (0) printf("em_init: begin" "\n");

em_stop(sc, 0);

/*
* Packet Buffer Allocation (PBA)
* Writing PBA sets the receive portion of the buffer
* the remainder is used for the transmit buffer.
*
* Devices before the 82547 had a Packet Buffer of 64K.
*   Default allocation: PBA=48K for Rx, leaving 16K for Tx.
* After the 82547 the buffer was reduced to 40K.
*   Default allocation: PBA=30K for Rx, leaving 10K for Tx.
*   Note: default does not leave enough room for Jumbo Frame >10k.
*/
switch (sc->hw.mac_type) {
case em_82547:
case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
if (sc->hw.max_frame_size > EM_RXBUFFER_81928192)
	pba = E1000_PBA_22K0x0016; /* 22K for Rx, 18K for Tx */
else
	pba = E1000_PBA_30K0x001E; /* 30K for Rx, 10K for Tx */
sc->tx_fifo_head = 0;
sc->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT7;
sc->tx_fifo_size = (E1000_PBA_40K0x0028 - pba) << EM_PBA_BYTES_SHIFT0xA;
break;
case em_82571:
case em_82572: /* Total Packet Buffer on these is 48k */
case em_82575:
case em_82576:
case em_82580:
case em_80003es2lan:
case em_i350:
pba = E1000_PBA_32K0x0020; /* 32K for Rx, 16K for Tx */
break;
case em_i210:
pba = E1000_PBA_34K0x0022;
break;
case em_82573: /* 82573: Total Packet Buffer is 32K */
/* Jumbo frames not supported */
pba = E1000_PBA_12K0x000C; /* 12K for Rx, 20K for Tx */
break;
case em_82574: /* Total Packet Buffer is 40k */
pba = E1000_PBA_20K0x0014; /* 20K for Rx, 20K for Tx */
break;
case em_ich8lan:
pba = E1000_PBA_8K0x0008;
break;
case em_ich9lan:
case em_ich10lan:
/* Boost Receive side for jumbo frames */
if (sc->hw.max_frame_size > EM_RXBUFFER_40964096)
	pba = E1000_PBA_14K0x000E;
else
	pba = E1000_PBA_10K0x000A;
break;
case em_pchlan:
case em_pch2lan:
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
pba = E1000_PBA_26K0x001A;
break;
default:
/* Devices before 82547 had a Packet Buffer of 64K.   */
if (sc->hw.max_frame_size > EM_RXBUFFER_81928192)
	pba = E1000_PBA_40K0x0028; /* 40K for Rx, 24K for Tx */
else
	pba = E1000_PBA_48K0x0030; /* 48K for Rx, 16K for Tx */
}
INIT_DEBUGOUT1("em_init: pba=%dK",pba)if (0) printf("em_init: pba=%dK" "\n", pba);
E1000_WRITE_REG(&sc->hw, PBA, pba)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01000 : em_translate_82542_register(0x01000))),
 (pba)));

/* Get the latest mac address, User can use a LAA */
bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac_addr, ETHER_ADDR_LEN6);

/* Initialize the hardware */
if (em_hardware_init(sc)) {
printf("%s: Unable to initialize the hardware\n", 
       DEVNAME(sc)((sc)->sc_dev.dv_xname));
splx(s)spllower(s);
return;
}
em_update_link_status(sc);

E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_VLAN)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00038 : em_translate_82542_register(0x00038))),
 (0x8100)));
if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020)
em_enable_hw_vlans(sc);

/* Prepare transmit descriptors and buffers */
if (em_setup_transmit_structures(sc)) {
printf("%s: Could not setup transmit structures\n", 
       DEVNAME(sc)((sc)->sc_dev.dv_xname));
em_stop(sc, 0);
splx(s)spllower(s);
return;
}
em_initialize_transmit_unit(sc);

/* Prepare receive descriptors and buffers */
if (em_setup_receive_structures(sc)) {
printf("%s: Could not setup receive structures\n", 
       DEVNAME(sc)((sc)->sc_dev.dv_xname));
em_stop(sc, 0);
splx(s)spllower(s);
return;
}
em_initialize_receive_unit(sc);

959#ifndef SMALL_KERNEL
if (sc->msix) {
if (em_setup_queues_msix(sc)) {
	printf("%s: Can't setup msix queues\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
	splx(s)spllower(s);
	return;
}
}
967#endif

/* Program promiscuous mode and multicast filters. */
em_iff(sc);

ifp->if_flags |= IFF_RUNNING0x40;
ifq_clr_oactive(&ifp->if_snd);

timeout_add_sec(&sc->timer_handle, 1);
em_clear_hw_cntrs(&sc->hw);
em_enable_intr(sc);

/* Don't reset the phy next time init gets called */
sc->hw.phy_reset_disable = TRUE1;

splx(s)spllower(s);
983}

985/*********************************************************************
*
*  Interrupt Service routine
*
**********************************************************************/
990int 
991em_intr(void *arg)
992{
struct em_softc	*sc = arg;
struct em_queue *que = sc->queues; /* single queue */
struct ifnet	*ifp = &sc->sc_ac.ac_if;
u_int32_t	reg_icr, test_icr;

test_icr = reg_icr = E1000_READ_REG(&sc->hw, ICR)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x000C0 : em_translate_82542_register(0x000C0)))));
if (sc->hw.mac_type >= em_82571)
test_icr = (reg_icr & E1000_ICR_INT_ASSERTED0x80000000);
if (!test_icr)
return (0);

if (ifp->if_flags & IFF_RUNNING0x40) {
em_txeof(que);
if (em_rxeof(que))
	em_rxrefill(que);
}

/* Link status change */
if (reg_icr & (E1000_ICR_RXSEQ0x00000008 | E1000_ICR_LSC0x00000004)) {
KERNEL_LOCK()_kernel_lock();
sc->hw.get_link_status = 1;
em_check_for_link(&sc->hw);
em_update_link_status(sc);
KERNEL_UNLOCK()_kernel_unlock();
}

return (1);
1020}

1022/*********************************************************************
*
*  Media Ioctl callback
*
*  This routine is called whenever the user queries the status of
*  the interface using ifconfig.
*
**********************************************************************/
1030void
1031em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1032{
struct em_softc *sc = ifp->if_softc;
uint64_t fiber_type = IFM_1000_SX11;
u_int16_t gsr;

INIT_DEBUGOUT("em_media_status: begin")if (0) printf("em_media_status: begin" "\n");

em_check_for_link(&sc->hw);
em_update_link_status(sc);

ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL;
ifmr->ifm_active = IFM_ETHER0x0000000000000100ULL;

if (!sc->link_active) {
ifmr->ifm_active |= IFM_NONE2ULL;
return;
}

ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL;

if (sc->hw.media_type == em_media_type_fiber ||
   sc->hw.media_type == em_media_type_internal_serdes) {
if (sc->hw.mac_type == em_82545)
	fiber_type = IFM_1000_LX14;
ifmr->ifm_active |= fiber_type | IFM_FDX0x0000010000000000ULL;
} else {
switch (sc->link_speed) {
case 10:
	ifmr->ifm_active |= IFM_10_T3;
	break;
case 100:
	ifmr->ifm_active |= IFM_100_TX6;
	break;
case 1000:
	ifmr->ifm_active |= IFM_1000_T16;
	break;
}

if (sc->link_duplex == FULL_DUPLEX2)
	ifmr->ifm_active |= em_flowstatus(sc) | IFM_FDX0x0000010000000000ULL;
else
	ifmr->ifm_active |= IFM_HDX0x0000020000000000ULL;

if (IFM_SUBTYPE(ifmr->ifm_active)((ifmr->ifm_active) & 0x00000000000000ffULL) == IFM_1000_T16) {
	em_read_phy_reg(&sc->hw, PHY_1000T_STATUS0x0A, &gsr);
	if (gsr & SR_1000T_MS_CONFIG_RES0x4000)
		ifmr->ifm_active |= IFM_ETH_MASTER0x0000000000010000ULL;
}
}
1081}

1083/*********************************************************************
*
*  Media Ioctl callback
*
*  This routine is called when the user changes speed/duplex using
*  media/mediopt option with ifconfig.
*
**********************************************************************/
1091int
1092em_media_change(struct ifnet *ifp)
1093{
struct em_softc *sc = ifp->if_softc;
struct ifmedia	*ifm = &sc->media;

INIT_DEBUGOUT("em_media_change: begin")if (0) printf("em_media_change: begin" "\n");

if (IFM_TYPE(ifm->ifm_media)((ifm->ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL)
return (EINVAL22);

switch (IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL)) {
case IFM_AUTO0ULL:
sc->hw.autoneg = DO_AUTO_NEG1;
sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT(0x0001 | 0x0002 | 0x0004 | 0x0008 | 0x0020);
break;
case IFM_1000_LX14:
case IFM_1000_SX11:
case IFM_1000_T16:
sc->hw.autoneg = DO_AUTO_NEG1;
sc->hw.autoneg_advertised = ADVERTISE_1000_FULL0x0020;
break;
case IFM_100_TX6:
sc->hw.autoneg = FALSE0;
sc->hw.autoneg_advertised = 0;
if ((ifm->ifm_media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL)
	sc->hw.forced_speed_duplex = em_100_full;
else
	sc->hw.forced_speed_duplex = em_100_half;
break;
case IFM_10_T3:
sc->hw.autoneg = FALSE0;
sc->hw.autoneg_advertised = 0;
if ((ifm->ifm_media & IFM_GMASK0x00ffff0000000000ULL) == IFM_FDX0x0000010000000000ULL)
	sc->hw.forced_speed_duplex = em_10_full;
else
	sc->hw.forced_speed_duplex = em_10_half;
break;
default:
printf("%s: Unsupported media type\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
}

/*
* As the speed/duplex settings may have changed we need to
* reset the PHY.
*/
sc->hw.phy_reset_disable = FALSE0;

em_init(sc);

return (0);
1142}

1144uint64_t
1145em_flowstatus(struct em_softc *sc)
1146{
u_int16_t ar, lpar;

if (sc->hw.media_type == em_media_type_fiber ||
   sc->hw.media_type == em_media_type_internal_serdes)
return (0);

em_read_phy_reg(&sc->hw, PHY_AUTONEG_ADV0x04, &ar);
em_read_phy_reg(&sc->hw, PHY_LP_ABILITY0x05, &lpar);

if ((ar & NWAY_AR_PAUSE0x0400) && (lpar & NWAY_LPAR_PAUSE0x0400))
return (IFM_FLOW0x0000040000000000ULL|IFM_ETH_TXPAUSE0x0000000000040000ULL|IFM_ETH_RXPAUSE0x0000000000020000ULL);
else if (!(ar & NWAY_AR_PAUSE0x0400) && (ar & NWAY_AR_ASM_DIR0x0800) &&
(lpar & NWAY_LPAR_PAUSE0x0400) && (lpar & NWAY_LPAR_ASM_DIR0x0800))
return (IFM_FLOW0x0000040000000000ULL|IFM_ETH_TXPAUSE0x0000000000040000ULL);
else if ((ar & NWAY_AR_PAUSE0x0400) && (ar & NWAY_AR_ASM_DIR0x0800) &&
!(lpar & NWAY_LPAR_PAUSE0x0400) && (lpar & NWAY_LPAR_ASM_DIR0x0800))
return (IFM_FLOW0x0000040000000000ULL|IFM_ETH_RXPAUSE0x0000000000020000ULL);

return (0);
1166}

1168/*********************************************************************
*
*  This routine maps the mbufs to tx descriptors.
*
*  return 0 on success, positive on failure
**********************************************************************/
1174u_int
1175em_encap(struct em_queue *que, struct mbuf *m)
1176{
struct em_softc *sc = que->sc;
struct em_packet *pkt;
struct em_tx_desc *desc;
bus_dmamap_t map;
u_int32_t txd_upper, txd_lower;
u_int head, last, used = 0;
13
←
'last' declared without an initial value→
int i, j;

/* For 82544 Workaround */
DESC_ARRAY		desc_array;
u_int32_t		array_elements;

/* get a dmamap for this packet from the next free slot */
head = que->tx.sc_tx_desc_head;
pkt = &que->tx.sc_tx_pkts_ring[head];
map = pkt->pkt_map;

switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0001))) {
14
←
Control jumps to 'case 27:'  at line 1197→
case 0:
break;
case EFBIG27:
if (m_defrag(m, M_DONTWAIT0x0002) == 0 &&
15
←
Assuming the condition is true→
17
←
Taking true branch→
    bus_dmamap_load_mbuf(sc->sc_dmat, map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0001))
16
←
Assuming the condition is true→
     BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
map), (m), (0x0001)) == 0)
	break;
18
←
 Execution continues on line 1209→

/* FALLTHROUGH */
default:
sc->no_tx_dma_setup++;
return (0);
}

bus_dmamap_sync(sc->sc_dmat, map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x04))
   0, map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x04))
   BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (map),
 (0), (map->dm_mapsize), (0x04));

if (sc->hw.mac_type == em_82547) {
19
←
Assuming field 'mac_type' is not equal to em_82547→
20
←
Taking false branch→
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08))
    0, que->tx.sc_tx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08));
}

if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 &&
21
←
Assuming field 'mac_type' is < em_82543→
   sc->hw.mac_type != em_82576 &&
   sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 &&
   sc->hw.mac_type != em_i350) {
used += em_transmit_checksum_setup(que, m, head,
    &txd_upper, &txd_lower);
} else {
txd_upper = txd_lower = 0;
}

head += used;
if (head >= sc->sc_tx_slots)
22
←
Assuming 'head' is < field 'sc_tx_slots'→
23
←
Taking false branch→
head -= sc->sc_tx_slots;

for (i = 0; i < map->dm_nsegs; i++) {
24
←
Assuming 'i' is >= field 'dm_nsegs'→
25
←
Loop condition is false. Execution continues on line 1277→
/* If sc is 82544 and on PCI-X bus */
if (sc->pcix_82544) {
	/*
	 * Check the Address and Length combination and
	 * split the data accordingly
	 */
	array_elements = em_fill_descriptors(
	    map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len,
	    &desc_array);
	for (j = 0; j < array_elements; j++) {
		desc = &que->tx.sc_tx_desc_ring[head];

		desc->buffer_addr = htole64(((__uint64_t)(desc_array.descriptor[j].address))
			desc_array.descriptor[j].address)((__uint64_t)(desc_array.descriptor[j].address));
		desc->lower.data = htole32(((__uint32_t)((que->tx.sc_txd_cmd | txd_lower | (u_int16_t
)desc_array.descriptor[j].length)))
			(que->tx.sc_txd_cmd | txd_lower |((__uint32_t)((que->tx.sc_txd_cmd | txd_lower | (u_int16_t
)desc_array.descriptor[j].length)))
			 (u_int16_t)desc_array.descriptor[j].length))((__uint32_t)((que->tx.sc_txd_cmd | txd_lower | (u_int16_t
)desc_array.descriptor[j].length)));
		desc->upper.data = htole32(txd_upper)((__uint32_t)(txd_upper));

		last = head;
		if (++head == sc->sc_tx_slots)
			head = 0;

		used++;
	}
} else {
	desc = &que->tx.sc_tx_desc_ring[head];

	desc->buffer_addr = htole64(map->dm_segs[i].ds_addr)((__uint64_t)(map->dm_segs[i].ds_addr));
	desc->lower.data = htole32(que->tx.sc_txd_cmd |((__uint32_t)(que->tx.sc_txd_cmd | txd_lower | map->dm_segs
[i].ds_len))
	    txd_lower | map->dm_segs[i].ds_len)((__uint32_t)(que->tx.sc_txd_cmd | txd_lower | map->dm_segs
[i].ds_len));
	desc->upper.data = htole32(txd_upper)((__uint32_t)(txd_upper));

	last = head;
	if (++head == sc->sc_tx_slots)
       		head = 0;

	used++;
}
}

1275#if NVLAN1 > 0
/* Find out if we are in VLAN mode */
if (m->m_flagsm_hdr.mh_flags & M_VLANTAG0x0020) {
26
←
Assuming the condition is false→
27
←
Taking false branch→
/* Set the VLAN id */
desc->upper.fields.special = htole16(m->m_pkthdr.ether_vtag)((__uint16_t)(m->M_dat.MH.MH_pkthdr.ether_vtag));

/* Tell hardware to add tag */
desc->lower.data |= htole32(E1000_TXD_CMD_VLE)((__uint32_t)(0x40000000));
}
1284#endif

/* mark the packet with the mbuf and last desc slot */
pkt->pkt_m = m;
pkt->pkt_eop = last;
28
←
Assigned value is garbage or undefined

que->tx.sc_tx_desc_head = head;

/* 
* Last Descriptor of Packet
* needs End Of Packet (EOP)
* and Report Status (RS)
*/
desc->lower.data |= htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)((__uint32_t)(0x01000000 | 0x08000000));

if (sc->hw.mac_type == em_82547) {
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04))
    0, que->tx.sc_tx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04))
    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04));
}

return (used);
1306}

1308/*********************************************************************
*
* 82547 workaround to avoid controller hang in half-duplex environment.
* The workaround is to avoid queuing a large packet that would span
* the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
* in this case. We do that only when FIFO is quiescent.
*
**********************************************************************/
1316void
1317em_82547_move_tail_locked(struct em_softc *sc)
1318{
uint16_t hw_tdt;
uint16_t sw_tdt;
struct em_tx_desc *tx_desc;
uint16_t length = 0;
boolean_t eop = 0;
struct em_queue *que = sc->queues; /* single queue chip */

hw_tdt = E1000_READ_REG(&sc->hw, TDT(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? ((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) :
 (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40))))))));
sw_tdt = que->tx.sc_tx_desc_head;

while (hw_tdt != sw_tdt) {
tx_desc = &que->tx.sc_tx_desc_ring[hw_tdt];
length += tx_desc->lower.flags.length;
eop = tx_desc->lower.data & E1000_TXD_CMD_EOP0x01000000;
if (++hw_tdt == sc->sc_tx_slots)
	hw_tdt = 0;

if (eop) {
	if (em_82547_fifo_workaround(sc, length)) {
		sc->tx_fifo_wrk_cnt++;
		timeout_add(&sc->tx_fifo_timer_handle, 1);
		break;
	}
	E1000_WRITE_REG(&sc->hw, TDT(que->me), hw_tdt)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03818 + ((que->me) *
 0x100)) : (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40)))))), (hw_tdt)));
	em_82547_update_fifo_head(sc, length);
	length = 0;
}
}
1347}

1349void
1350em_82547_move_tail(void *arg)
1351{
struct em_softc *sc = arg;
int s;

s = splnet()splraise(0x7);
em_82547_move_tail_locked(sc);
splx(s)spllower(s);
1358}

1360int
1361em_82547_fifo_workaround(struct em_softc *sc, int len)
1362{
int fifo_space, fifo_pkt_len;

fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR)(((len + 0x10) + (0x10) - 1) & ~((0x10) - 1));

if (sc->link_duplex == HALF_DUPLEX1) {
fifo_space = sc->tx_fifo_size - sc->tx_fifo_head;

if (fifo_pkt_len >= (EM_82547_PKT_THRESH0x3e0 + fifo_space)) {
	if (em_82547_tx_fifo_reset(sc))
		return (0);
	else
		return (1);
}
}

return (0);
1379}

1381void
1382em_82547_update_fifo_head(struct em_softc *sc, int len)
1383{
int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR)(((len + 0x10) + (0x10) - 1) & ~((0x10) - 1));

/* tx_fifo_head is always 16 byte aligned */
sc->tx_fifo_head += fifo_pkt_len;
if (sc->tx_fifo_head >= sc->tx_fifo_size)
sc->tx_fifo_head -= sc->tx_fifo_size;
1390}

1392int
1393em_82547_tx_fifo_reset(struct em_softc *sc)
1394{
uint32_t tctl;
struct em_queue *que = sc->queues; /* single queue chip */

if ((E1000_READ_REG(&sc->hw, TDT(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? ((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) :
 (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40)))))))) ==
    E1000_READ_REG(&sc->hw, TDH(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? ((que->me) < 4 ? (0x03810 + ((que->me) * 0x100)) :
 (0x0E010 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03810 + ((que->me) * 0x100)) : (
0x0E010 + ((que->me) * 0x40))))))))) &&
   (E1000_READ_REG(&sc->hw, TDFT)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x03418 : em_translate_82542_register(0x03418))))) ==
    E1000_READ_REG(&sc->hw, TDFH)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x03410 : em_translate_82542_register(0x03410)))))) &&
   (E1000_READ_REG(&sc->hw, TDFTS)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x03428 : em_translate_82542_register(0x03428))))) ==
    E1000_READ_REG(&sc->hw, TDFHS)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x03420 : em_translate_82542_register(0x03420)))))) &&
   (E1000_READ_REG(&sc->hw, TDFPC)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x03430 : em_translate_82542_register(0x03430))))) == 0)) {

/* Disable TX unit */
tctl = E1000_READ_REG(&sc->hw, TCTL)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00400 : em_translate_82542_register(0x00400)))));
E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00400 : em_translate_82542_register(0x00400))),
 (tctl & ~0x00000002)));

/* Reset FIFO pointers */
E1000_WRITE_REG(&sc->hw, TDFT, sc->tx_head_addr)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x03418 : em_translate_82542_register(0x03418))),
 (sc->tx_head_addr)));
E1000_WRITE_REG(&sc->hw, TDFH, sc->tx_head_addr)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x03410 : em_translate_82542_register(0x03410))),
 (sc->tx_head_addr)));
E1000_WRITE_REG(&sc->hw, TDFTS, sc->tx_head_addr)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x03428 : em_translate_82542_register(0x03428))),
 (sc->tx_head_addr)));
E1000_WRITE_REG(&sc->hw, TDFHS, sc->tx_head_addr)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x03420 : em_translate_82542_register(0x03420))),
 (sc->tx_head_addr)));

/* Re-enable TX unit */
E1000_WRITE_REG(&sc->hw, TCTL, tctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00400 : em_translate_82542_register(0x00400))),
 (tctl)));
E1000_WRITE_FLUSH(&sc->hw)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00008 : em_translate_82542_register(0x00008)))));

sc->tx_fifo_head = 0;
sc->tx_fifo_reset_cnt++;

return (TRUE1);
} else
return (FALSE0);
1426}

1428void
1429em_iff(struct em_softc *sc)
1430{
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct arpcom *ac = &sc->sc_ac;
u_int32_t reg_rctl = 0;
u_int8_t  mta[MAX_NUM_MULTICAST_ADDRESSES128 * ETH_LENGTH_OF_ADDRESS6];
struct ether_multi *enm;
struct ether_multistep step;
int i = 0;

IOCTL_DEBUGOUT("em_iff: begin")if (0) printf("em_iff: begin" "\n");

if (sc->hw.mac_type == em_82542_rev2_0) {
reg_rctl = E1000_READ_REG(&sc->hw, RCTL)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00100 : em_translate_82542_register(0x00100)))));
if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE0x0010)
	em_pci_clear_mwi(&sc->hw);
reg_rctl |= E1000_RCTL_RST0x00000001;
E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00100 : em_translate_82542_register(0x00100))),
 (reg_rctl)));
msec_delay(5)(*delay_func)(1000*(5));
}

reg_rctl = E1000_READ_REG(&sc->hw, RCTL)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00100 : em_translate_82542_register(0x00100)))));
reg_rctl &= ~(E1000_RCTL_MPE0x00000010 | E1000_RCTL_UPE0x00000008);
ifp->if_flags &= ~IFF_ALLMULTI0x200;

if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0 ||
   ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES128) {
ifp->if_flags |= IFF_ALLMULTI0x200;
reg_rctl |= E1000_RCTL_MPE0x00000010;
if (ifp->if_flags & IFF_PROMISC0x100)
	reg_rctl |= E1000_RCTL_UPE0x00000008;
} else {
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	bcopy(enm->enm_addrlo, mta + i, ETH_LENGTH_OF_ADDRESS6);
	i += ETH_LENGTH_OF_ADDRESS6;

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}

em_mc_addr_list_update(&sc->hw, mta, ac->ac_multicnt, 0, 1);
}

E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00100 : em_translate_82542_register(0x00100))),
 (reg_rctl)));

if (sc->hw.mac_type == em_82542_rev2_0) {
reg_rctl = E1000_READ_REG(&sc->hw, RCTL)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00100 : em_translate_82542_register(0x00100)))));
reg_rctl &= ~E1000_RCTL_RST0x00000001;
E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00100 : em_translate_82542_register(0x00100))),
 (reg_rctl)));
msec_delay(5)(*delay_func)(1000*(5));
if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE0x0010)
	em_pci_set_mwi(&sc->hw);
}
1482}

1484/*********************************************************************
*  Timer routine
*
*  This routine checks for link status and updates statistics.
*
**********************************************************************/

1491void
1492em_local_timer(void *arg)
1493{
struct em_softc *sc = arg;
int s;

timeout_add_sec(&sc->timer_handle, 1);

s = splnet()splraise(0x7);
em_smartspeed(sc);
splx(s)spllower(s);

1503#if NKSTAT0 > 0
if (sc->kstat != NULL((void *)0) && mtx_enter_try(&sc->kstat_mtx)) {
em_kstat_read(sc->kstat);
mtx_leave(&sc->kstat_mtx);
}
1508#endif
1509}

1511void
1512em_update_link_status(struct em_softc *sc)
1513{
struct ifnet *ifp = &sc->sc_ac.ac_if;
u_char link_state;

if (E1000_READ_REG(&sc->hw, STATUS)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00008 : em_translate_82542_register(0x00008))))) & E1000_STATUS_LU0x00000002) {
if (sc->link_active == 0) {
	em_get_speed_and_duplex(&sc->hw,
				&sc->link_speed,
				&sc->link_duplex);
	/* Check if we may set SPEED_MODE bit on PCI-E */
	if ((sc->link_speed == SPEED_10001000) &&
	    ((sc->hw.mac_type == em_82571) ||
	    (sc->hw.mac_type == em_82572) ||
	    (sc->hw.mac_type == em_82575) ||
	    (sc->hw.mac_type == em_82576) ||
	    (sc->hw.mac_type == em_82580))) {
		int tarc0;

		tarc0 = E1000_READ_REG(&sc->hw, TARC0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x03840 : em_translate_82542_register(0x03840)))));
		tarc0 |= SPEED_MODE_BIT(1<<21);
		E1000_WRITE_REG(&sc->hw, TARC0, tarc0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x03840 : em_translate_82542_register(0x03840))),
 (tarc0)));
	}
	sc->link_active = 1;
	sc->smartspeed = 0;
	ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(sc->link_speed)((((sc->link_speed) * 1000ULL) * 1000ULL));
}
link_state = (sc->link_duplex == FULL_DUPLEX2) ?
    LINK_STATE_FULL_DUPLEX6 : LINK_STATE_HALF_DUPLEX5;
} else {
if (sc->link_active == 1) {
	ifp->if_baudrateif_data.ifi_baudrate = sc->link_speed = 0;
	sc->link_duplex = 0;
	sc->link_active = 0;
}
link_state = LINK_STATE_DOWN2;
}
if (ifp->if_link_stateif_data.ifi_link_state != link_state) {
ifp->if_link_stateif_data.ifi_link_state = link_state;
if_link_state_change(ifp);
}
1553}

1555/*********************************************************************
*
*  This routine disables all traffic on the adapter by issuing a
*  global reset on the MAC and deallocates TX/RX buffers. 
*
**********************************************************************/

1562void
1563em_stop(void *arg, int softonly)
1564{
struct em_softc *sc = arg;
struct em_queue *que = sc->queues; /* Use only first queue. */
struct ifnet   *ifp = &sc->sc_ac.ac_if;

/* Tell the stack that the interface is no longer active */
ifp->if_flags &= ~IFF_RUNNING0x40;

INIT_DEBUGOUT("em_stop: begin")if (0) printf("em_stop: begin" "\n");

timeout_del(&que->rx_refill);
timeout_del(&sc->timer_handle);
timeout_del(&sc->tx_fifo_timer_handle);

if (!softonly)
em_disable_intr(sc);
if (sc->hw.mac_type >= em_pch_spt)
em_flush_desc_rings(sc);
if (!softonly)
em_reset_hw(&sc->hw);

intr_barrier(sc->sc_intrhand);
ifq_barrier(&ifp->if_snd);

KASSERT((ifp->if_flags & IFF_RUNNING) == 0)(((ifp->if_flags & 0x40) == 0) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/if_em.c", 1588, "(ifp->if_flags & IFF_RUNNING) == 0"
));

ifq_clr_oactive(&ifp->if_snd);
ifp->if_timer = 0;

em_free_transmit_structures(sc);
em_free_receive_structures(sc);
1595}

1597/*********************************************************************
*
*  Determine hardware revision.
*
**********************************************************************/
1602void
1603em_identify_hardware(struct em_softc *sc)
1604{
u_int32_t reg;
struct pci_attach_args *pa = &sc->osdep.em_pa;

/* Make sure our PCI config space has the necessary stuff set */
sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag,
			    PCI_COMMAND_STATUS_REG0x04);

/* Save off the information about this board */
sc->hw.vendor_id = PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff);
sc->hw.device_id = PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff);

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG0x08);
sc->hw.revision_id = PCI_REVISION(reg)(((reg) >> 0) & 0xff);

reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG0x2c);
sc->hw.subsystem_vendor_id = PCI_VENDOR(reg)(((reg) >> 0) & 0xffff);
sc->hw.subsystem_id = PCI_PRODUCT(reg)(((reg) >> 16) & 0xffff);

/* Identify the MAC */
if (em_set_mac_type(&sc->hw))
printf("%s: Unknown MAC Type\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));

if (sc->hw.mac_type == em_pchlan)
sc->hw.revision_id = PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) & 0x0f;

if (sc->hw.mac_type == em_82541 ||
   sc->hw.mac_type == em_82541_rev_2 ||
   sc->hw.mac_type == em_82547 ||
   sc->hw.mac_type == em_82547_rev_2)
sc->hw.phy_init_script = TRUE1;
1635}

1637void
1638em_legacy_irq_quirk_spt(struct em_softc *sc)
1639{
uint32_t	reg;

/* Legacy interrupt: SPT needs a quirk. */
if (sc->hw.mac_type != em_pch_spt && sc->hw.mac_type != em_pch_cnp)
return;
if (sc->legacy_irq == 0)
return;

reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM7)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (0xe4UL)));
reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE0x04UL;
EM_WRITE_REG(&sc->hw, E1000_FEXTNVM7, reg)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (0xe4UL), (reg)));

reg = EM_READ_REG(&sc->hw, E1000_FEXTNVM9)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (0x5bb4UL)));
reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS0x0800UL |
   E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS0x1000UL;
EM_WRITE_REG(&sc->hw, E1000_FEXTNVM9, reg)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (0x5bb4UL), (reg)));
1656}

1658int
1659em_allocate_pci_resources(struct em_softc *sc)
1660{
int		val, rid;
struct pci_attach_args *pa = &sc->osdep.em_pa;
struct em_queue	       *que = NULL((void *)0);

val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA0x0010);
if (PCI_MAPREG_TYPE(val)((val) & 0x00000001) != PCI_MAPREG_TYPE_MEM0x00000000) {
printf(": mmba is not mem space\n");
return (ENXIO6);
}
if (pci_mapreg_map(pa, EM_MMBA0x0010, PCI_MAPREG_MEM_TYPE(val)((val) & 0x00000006), 0,
   &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle,
   &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) {
printf(": cannot find mem space\n");
return (ENXIO6);
}

switch (sc->hw.mac_type) {
case em_82544:
case em_82540:
case em_82545:
case em_82546:
case em_82541:
case em_82541_rev_2:
/* Figure out where our I/O BAR is ? */
for (rid = PCI_MAPREG_START0x10; rid < PCI_MAPREG_END0x28;) {
	val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid);
	if (PCI_MAPREG_TYPE(val)((val) & 0x00000001) == PCI_MAPREG_TYPE_IO0x00000001) {
		sc->io_rid = rid;
		break;
	}
	rid += 4;
	if (PCI_MAPREG_MEM_TYPE(val)((val) & 0x00000006) ==
	    PCI_MAPREG_MEM_TYPE_64BIT0x00000004)
		rid += 4;	/* skip high bits, too */
}

if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO0x00000001, 0,
    &sc->osdep.io_bus_space_tag, &sc->osdep.io_bus_space_handle,
    &sc->osdep.em_iobase, &sc->osdep.em_iosize, 0)) {
	printf(": cannot find i/o space\n");
	return (ENXIO6);
}

sc->hw.io_base = 0;
break;
default:
break;
}

sc->osdep.em_flashoffset = 0;
/* for ICH8 and family we need to find the flash memory */
if (sc->hw.mac_type >= em_pch_spt) {
sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag;
sc->osdep.flash_bus_space_handle = sc->osdep.mem_bus_space_handle;
sc->osdep.em_flashbase = 0;
sc->osdep.em_flashsize = 0;
sc->osdep.em_flashoffset = 0xe000;
} else if (IS_ICH8(sc->hw.mac_type)(sc->hw.mac_type == em_ich8lan || sc->hw.mac_type == em_ich9lan
 || sc->hw.mac_type == em_ich10lan || sc->hw.mac_type ==
 em_pchlan || sc->hw.mac_type == em_pch2lan || sc->hw.mac_type
 == em_pch_lpt || sc->hw.mac_type == em_pch_spt || sc->
hw.mac_type == em_pch_cnp)) {
val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH0x0014);
if (PCI_MAPREG_TYPE(val)((val) & 0x00000001) != PCI_MAPREG_TYPE_MEM0x00000000) {
	printf(": flash is not mem space\n");
	return (ENXIO6);
}

if (pci_mapreg_map(pa, EM_FLASH0x0014, PCI_MAPREG_MEM_TYPE(val)((val) & 0x00000006), 0,
    &sc->osdep.flash_bus_space_tag, &sc->osdep.flash_bus_space_handle,
    &sc->osdep.em_flashbase, &sc->osdep.em_flashsize, 0)) {
	printf(": cannot find mem space\n");
	return (ENXIO6);
}
      }

sc->osdep.dev = (struct device *)sc;
sc->hw.back = &sc->osdep;

/* Only one queue for the moment. */
que = malloc(sizeof(struct em_queue), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (que == NULL((void *)0)) {
printf(": unable to allocate queue memory\n");
return (ENOMEM12);
}
que->me = 0;
que->sc = sc;
timeout_set(&que->rx_refill, em_rxrefill, que);

sc->queues = que;
sc->num_queues = 1;
sc->msix = 0;
sc->legacy_irq = 0;
if (em_allocate_msix(sc) && em_allocate_legacy(sc))
return (ENXIO6);

/*
* the ICP_xxxx device has multiple, duplicate register sets for
* use when it is being used as a network processor. Disable those
* registers here, as they are not necessary in this context and
* can confuse the system
*/
if(sc->hw.mac_type == em_icp_xxxx) {
int offset;
pcireg_t val;

if (!pci_get_capability(sc->osdep.em_pa.pa_pc, 
    sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST0x09, &offset, &val)) {
	return (0);
}
offset += PCI_ST_SMIA_OFFSET0x04;
pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag,
    offset, 0x06);
E1000_WRITE_REG(&sc->hw, IMC1, ~0x0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x008D8 : em_translate_82542_register(0x008D8))),
 (~0x0)));
E1000_WRITE_REG(&sc->hw, IMC2, ~0x0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x008F8 : em_translate_82542_register(0x008F8))),
 (~0x0)));
}
return (0);
1774}

1776void
1777em_free_pci_resources(struct em_softc *sc)
1778{
struct pci_attach_args *pa = &sc->osdep.em_pa;
pci_chipset_tag_t	pc = pa->pa_pc;
struct em_queue	       *que = NULL((void *)0);
if (sc->sc_intrhand)
pci_intr_disestablish(pc, sc->sc_intrhand);
sc->sc_intrhand = 0;

if (sc->osdep.em_flashbase)
bus_space_unmap(sc->osdep.flash_bus_space_tag, sc->osdep.flash_bus_space_handle,
		sc->osdep.em_flashsize);
sc->osdep.em_flashbase = 0;

if (sc->osdep.em_iobase)
bus_space_unmap(sc->osdep.io_bus_space_tag, sc->osdep.io_bus_space_handle,
		sc->osdep.em_iosize);
sc->osdep.em_iobase = 0;

if (sc->osdep.em_membase)
bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle,
		sc->osdep.em_memsize);
sc->osdep.em_membase = 0;

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
if (que->rx.sc_rx_desc_ring != NULL((void *)0)) {
	que->rx.sc_rx_desc_ring = NULL((void *)0);
	em_dma_free(sc, &que->rx.sc_rx_dma);
}
if (que->tx.sc_tx_desc_ring != NULL((void *)0)) {
	que->tx.sc_tx_desc_ring = NULL((void *)0);
	em_dma_free(sc, &que->tx.sc_tx_dma);
}
if (que->tag)
	pci_intr_disestablish(pc, que->tag);
que->tag = NULL((void *)0);
que->eims = 0;
que->me = 0;
que->sc = NULL((void *)0);
}
sc->legacy_irq = 0;
sc->msix_linkvec = 0;
sc->msix_queuesmask = 0;
if (sc->queues)
free(sc->queues, M_DEVBUF2,
    sc->num_queues * sizeof(struct em_queue));
sc->num_queues = 0;
sc->queues = NULL((void *)0);
1825}

1827/*********************************************************************
*
*  Initialize the hardware to a configuration as specified by the
*  em_softc structure. The controller is reset, the EEPROM is
*  verified, the MAC address is set, then the shared initialization
*  routines are called.
*
**********************************************************************/
1835int
1836em_hardware_init(struct em_softc *sc)
1837{
uint32_t ret_val;
u_int16_t rx_buffer_size;

INIT_DEBUGOUT("em_hardware_init: begin")if (0) printf("em_hardware_init: begin" "\n");
if (sc->hw.mac_type >= em_pch_spt)
em_flush_desc_rings(sc);
/* Issue a global reset */
em_reset_hw(&sc->hw);

/* When hardware is reset, fifo_head is also reset */
sc->tx_fifo_head = 0;

/* Make sure we have a good EEPROM before we read from it */
if (em_get_flash_presence_i210(&sc->hw) &&
   em_validate_eeprom_checksum(&sc->hw) < 0) {
/*
 * Some PCIe parts fail the first check due to
 * the link being in sleep state, call it again,
 * if it fails a second time its a real issue.
 */
if (em_validate_eeprom_checksum(&sc->hw) < 0) {
	printf("%s: The EEPROM Checksum Is Not Valid\n",
	       DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return (EIO5);
}
}

if (em_get_flash_presence_i210(&sc->hw) &&
   em_read_part_num(&sc->hw, &(sc->part_num)) < 0) {
printf("%s: EEPROM read error while reading part number\n",
       DEVNAME(sc)((sc)->sc_dev.dv_xname));
return (EIO5);
}

/* Set up smart power down as default off on newer adapters */
if (!em_smart_pwr_down &&
    (sc->hw.mac_type == em_82571 ||
     sc->hw.mac_type == em_82572 ||
     sc->hw.mac_type == em_82575 ||
     sc->hw.mac_type == em_82576 ||
     sc->hw.mac_type == em_82580 ||
     sc->hw.mac_type == em_i210 ||
     sc->hw.mac_type == em_i350 )) {
uint16_t phy_tmp = 0;

/* Speed up time to link by disabling smart power down */
em_read_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT0x19, &phy_tmp);
phy_tmp &= ~IGP02E1000_PM_SPD0x0001;
em_write_phy_reg(&sc->hw, IGP02E1000_PHY_POWER_MGMT0x19, phy_tmp);
}

em_legacy_irq_quirk_spt(sc);

/*
* These parameters control the automatic generation (Tx) and 
* response (Rx) to Ethernet PAUSE frames.
* - High water mark should allow for at least two frames to be
*   received after sending an XOFF.
* - Low water mark works best when it is very near the high water mark.
*   This allows the receiver to restart by sending XON when it has
*   drained a bit.  Here we use an arbitrary value of 1500 which will
*   restart after one full frame is pulled from the buffer.  There
*   could be several smaller frames in the buffer and if so they will
*   not trigger the XON until their total number reduces the buffer
*   by 1500.
* - The pause time is fairly large at 1000 x 512ns = 512 usec.
*/
rx_buffer_size = ((E1000_READ_REG(&sc->hw, PBA)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x01000 : em_translate_82542_register(0x01000))))) & 0xffff) << 10 );

sc->hw.fc_high_water = rx_buffer_size -
   EM_ROUNDUP(sc->hw.max_frame_size, 1024)(((sc->hw.max_frame_size) + (1024) - 1) & ~((1024) - 1
));
sc->hw.fc_low_water = sc->hw.fc_high_water - 1500;
if (sc->hw.mac_type == em_80003es2lan)
sc->hw.fc_pause_time = 0xFFFF;
else
sc->hw.fc_pause_time = 1000;
sc->hw.fc_send_xon = TRUE1;
sc->hw.fc = E1000_FC_FULL3;

em_disable_aspm(sc);

if ((ret_val = em_init_hw(sc)) != 0) {
if (ret_val == E1000_DEFER_INIT15) {
	INIT_DEBUGOUT("\nHardware Initialization Deferred ")if (0) printf("\nHardware Initialization Deferred " "\n");
	return (EAGAIN35);
}
printf("\n%s: Hardware Initialization Failed: %d\n",
       DEVNAME(sc)((sc)->sc_dev.dv_xname), ret_val);
return (EIO5);
}

em_check_for_link(&sc->hw);

return (0);
1932}

1934/*********************************************************************
*
*  Setup networking device structure and register an interface.
*
**********************************************************************/
1939void
1940em_setup_interface(struct em_softc *sc)
1941{
struct ifnet   *ifp;
uint64_t fiber_type = IFM_1000_SX11;

INIT_DEBUGOUT("em_setup_interface: begin")if (0) printf("em_setup_interface: begin" "\n");

ifp = &sc->sc_ac.ac_if;
strlcpy(ifp->if_xname, DEVNAME(sc)((sc)->sc_dev.dv_xname), IFNAMSIZ16);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
ifp->if_xflags = IFXF_MPSAFE0x1;
ifp->if_ioctl = em_ioctl;
ifp->if_qstart = em_start;
ifp->if_watchdog = em_watchdog;
ifp->if_hardmtu =
sc->hw.max_frame_size - ETHER_HDR_LEN((6 * 2) + 2) - ETHER_CRC_LEN4;
ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_slots - 1)((&ifp->if_snd)->ifq_maxlen = (sc->sc_tx_slots -
 1));

ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010;

1961#if NVLAN1 > 0
if (sc->hw.mac_type != em_82575 && sc->hw.mac_type != em_82580 &&
   sc->hw.mac_type != em_82576 &&
   sc->hw.mac_type != em_i210 && sc->hw.mac_type != em_i350)
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020;
1966#endif

if (sc->hw.mac_type >= em_82543 && sc->hw.mac_type != em_82575 &&
   sc->hw.mac_type != em_82576 &&
   sc->hw.mac_type != em_82580 && sc->hw.mac_type != em_i210 &&
   sc->hw.mac_type != em_i350)
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_CSUM_TCPv40x00000002 | IFCAP_CSUM_UDPv40x00000004;

/* 
* Specify the media types supported by this adapter and register
* callbacks to update media and link information
*/
ifmedia_init(&sc->media, IFM_IMASK0xff00000000000000ULL, em_media_change,
     em_media_status);
if (sc->hw.media_type == em_media_type_fiber ||
   sc->hw.media_type == em_media_type_internal_serdes) {
if (sc->hw.mac_type == em_82545)
	fiber_type = IFM_1000_LX14;
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | fiber_type | IFM_FDX0x0000010000000000ULL, 
	    0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | fiber_type, 
	    0, NULL((void *)0));
} else {
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_10_T3, 0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_10_T3 | IFM_FDX0x0000010000000000ULL, 
	    0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6, 
	    0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6 | IFM_FDX0x0000010000000000ULL, 
	    0, NULL((void *)0));
if (sc->hw.phy_type != em_phy_ife) {
	ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16 | IFM_FDX0x0000010000000000ULL, 
		    0, NULL((void *)0));
	ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16, 0, NULL((void *)0));
}
}
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL, 0, NULL((void *)0));
ifmedia_set(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL);

if_attach(ifp);
ether_ifattach(ifp);
em_enable_intr(sc);
2008}

2010int
2011em_detach(struct device *self, int flags)
2012{
struct em_softc *sc = (struct em_softc *)self;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct pci_attach_args *pa = &sc->osdep.em_pa;
pci_chipset_tag_t	pc = pa->pa_pc;

if (sc->sc_intrhand)
pci_intr_disestablish(pc, sc->sc_intrhand);
sc->sc_intrhand = 0;

em_stop(sc, 1);

em_free_pci_resources(sc);

ether_ifdetach(ifp);
if_detach(ifp);

return (0);
2030}

2032int
2033em_activate(struct device *self, int act)
2034{
struct em_softc *sc = (struct em_softc *)self;
struct ifnet *ifp = &sc->sc_ac.ac_if;
int rv = 0;

switch (act) {
case DVACT_SUSPEND3:
if (ifp->if_flags & IFF_RUNNING0x40)
	em_stop(sc, 0);
/* We have no children atm, but we will soon */
rv = config_activate_children(self, act);
break;
case DVACT_RESUME4:
if (ifp->if_flags & IFF_UP0x1)
	em_init(sc);
break;
default:
rv = config_activate_children(self, act);
break;
}
return (rv);
2055}

2057/*********************************************************************
*
*  Workaround for SmartSpeed on 82541 and 82547 controllers
*
**********************************************************************/	
2062void
2063em_smartspeed(struct em_softc *sc)
2064{
uint16_t phy_tmp;

if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || 
   !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL0x0020))
return;

if (sc->smartspeed == 0) {
/* If Master/Slave config fault is asserted twice,
 * we assume back-to-back */
em_read_phy_reg(&sc->hw, PHY_1000T_STATUS0x0A, &phy_tmp);
if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT0x8000))
	return;
em_read_phy_reg(&sc->hw, PHY_1000T_STATUS0x0A, &phy_tmp);
if (phy_tmp & SR_1000T_MS_CONFIG_FAULT0x8000) {
	em_read_phy_reg(&sc->hw, PHY_1000T_CTRL0x09,
			&phy_tmp);
	if (phy_tmp & CR_1000T_MS_ENABLE0x1000) {
		phy_tmp &= ~CR_1000T_MS_ENABLE0x1000;
		em_write_phy_reg(&sc->hw,
				    PHY_1000T_CTRL0x09, phy_tmp);
		sc->smartspeed++;
		if (sc->hw.autoneg &&
		    !em_phy_setup_autoneg(&sc->hw) &&
		    !em_read_phy_reg(&sc->hw, PHY_CTRL0x00,
				       &phy_tmp)) {
			phy_tmp |= (MII_CR_AUTO_NEG_EN0x1000 |  
				    MII_CR_RESTART_AUTO_NEG0x0200);
			em_write_phy_reg(&sc->hw,
					 PHY_CTRL0x00, phy_tmp);
		}
	}
}
return;
} else if (sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT3) {
/* If still no link, perhaps using 2/3 pair cable */
em_read_phy_reg(&sc->hw, PHY_1000T_CTRL0x09, &phy_tmp);
phy_tmp |= CR_1000T_MS_ENABLE0x1000;
em_write_phy_reg(&sc->hw, PHY_1000T_CTRL0x09, phy_tmp);
if (sc->hw.autoneg &&
    !em_phy_setup_autoneg(&sc->hw) &&
    !em_read_phy_reg(&sc->hw, PHY_CTRL0x00, &phy_tmp)) {
	phy_tmp |= (MII_CR_AUTO_NEG_EN0x1000 |
		    MII_CR_RESTART_AUTO_NEG0x0200);
	em_write_phy_reg(&sc->hw, PHY_CTRL0x00, phy_tmp);
}
}
/* Restart process after EM_SMARTSPEED_MAX iterations */
if (sc->smartspeed++ == EM_SMARTSPEED_MAX15)
sc->smartspeed = 0;
2114}

2116/*
* Manage DMA'able memory.
*/
2119int
2120em_dma_malloc(struct em_softc *sc, bus_size_t size, struct em_dma_alloc *dma)
2121{
int r;

r = bus_dmamap_create(sc->sc_dmat, size, 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (size
), (1), (size), (0), (0x0000 | 0x0002), (&dma->dma_map
))
   size, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &dma->dma_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (size
), (1), (size), (0), (0x0000 | 0x0002), (&dma->dma_map
));
if (r != 0)
return (r);

r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &dma->dma_seg,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (size
), ((1 << 12)), (0), (&dma->dma_seg), (1), (&
dma->dma_nseg), (0x0000 | 0x1000))
   1, &dma->dma_nseg, BUS_DMA_WAITOK | BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (size
), ((1 << 12)), (0), (&dma->dma_seg), (1), (&
dma->dma_nseg), (0x0000 | 0x1000));
if (r != 0)
goto destroy;

r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, size,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&dma
->dma_seg), (dma->dma_nseg), (size), (&dma->dma_vaddr
), (0x0000 | 0x0004))
   &dma->dma_vaddr, BUS_DMA_WAITOK | BUS_DMA_COHERENT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&dma
->dma_seg), (dma->dma_nseg), (size), (&dma->dma_vaddr
), (0x0000 | 0x0004));
if (r != 0)
goto free;

r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, size,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (dma->
dma_map), (dma->dma_vaddr), (size), (((void *)0)), (0x0000
))
   NULL, BUS_DMA_WAITOK)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (dma->
dma_map), (dma->dma_vaddr), (size), (((void *)0)), (0x0000
));
if (r != 0)
goto unmap;

dma->dma_size = size;
return (0);

2147unmap:
bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (dma->
dma_vaddr), (size));
2149free:
bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
dma->dma_seg), (dma->dma_nseg));
2151destroy:
bus_dmamap_destroy(sc->sc_dmat, dma->dma_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (dma
->dma_map));

return (r);
2155}

2157void
2158em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma)
2159{
bus_dmamap_unload(sc->sc_dmat, dma->dma_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (dma
->dma_map));
bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (dma->
dma_vaddr), (dma->dma_size));
bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
dma->dma_seg), (dma->dma_nseg));
bus_dmamap_destroy(sc->sc_dmat, dma->dma_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (dma
->dma_map));
2164}

2166/*********************************************************************
*
*  Allocate memory for tx_buffer structures. The tx_buffer stores all
*  the information needed to transmit a packet on the wire.
*
**********************************************************************/
2172int
2173em_allocate_transmit_structures(struct em_softc *sc)
2174{
struct em_queue *que;

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04))
    0, que->tx.sc_tx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04))
    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01 | 0x04));

que->tx.sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots,
    sizeof(*que->tx.sc_tx_pkts_ring), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (que->tx.sc_tx_pkts_ring == NULL((void *)0)) {
	printf("%s: Unable to allocate tx_buffer memory\n", 
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return (ENOMEM12);
}
}

return (0);
2192}

2194/*********************************************************************
*
*  Allocate and initialize transmit structures. 
*
**********************************************************************/
2199int
2200em_setup_transmit_structures(struct em_softc *sc)
2201{
struct em_queue *que;
struct em_packet *pkt;
int error, i;

if ((error = em_allocate_transmit_structures(sc)) != 0)
goto fail;

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
bzero((void *) que->tx.sc_tx_desc_ring,__builtin_bzero(((void *) que->tx.sc_tx_desc_ring), ((sizeof
(struct em_tx_desc)) * sc->sc_tx_slots))
    (sizeof(struct em_tx_desc)) * sc->sc_tx_slots)__builtin_bzero(((void *) que->tx.sc_tx_desc_ring), ((sizeof
(struct em_tx_desc)) * sc->sc_tx_slots));

for (i = 0; i < sc->sc_tx_slots; i++) {
	pkt = &que->tx.sc_tx_pkts_ring[i];
	error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (0x3F00
), (64 / (sc->pcix_82544 ? 2 : 1)), (0x3F00), (0), (0x0001
), (&pkt->pkt_map))
	    EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1),(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (0x3F00
), (64 / (sc->pcix_82544 ? 2 : 1)), (0x3F00), (0), (0x0001
), (&pkt->pkt_map))
	    MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (0x3F00
), (64 / (sc->pcix_82544 ? 2 : 1)), (0x3F00), (0), (0x0001
), (&pkt->pkt_map));
	if (error != 0) {
		printf("%s: Unable to create TX DMA map\n",
		    DEVNAME(sc)((sc)->sc_dev.dv_xname));
		goto fail;
	}
}

que->tx.sc_tx_desc_head = 0;
que->tx.sc_tx_desc_tail = 0;

/* Set checksum context */
que->tx.active_checksum_context = OFFLOAD_NONE;
}

return (0);

2234fail:
em_free_transmit_structures(sc);
return (error);
2237}

2239/*********************************************************************
*
*  Enable transmit unit.
*
**********************************************************************/
2244void
2245em_initialize_transmit_unit(struct em_softc *sc)
2246{
u_int32_t	reg_tctl, reg_tipg = 0;
u_int64_t	bus_addr;
struct em_queue *que;

INIT_DEBUGOUT("em_initialize_transmit_unit: begin")if (0) printf("em_initialize_transmit_unit: begin" "\n");

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
/* Setup the Base and Length of the Tx Descriptor Ring */
bus_addr = que->tx.sc_tx_dma.dma_map->dm_segs[0].ds_addr;
E1000_WRITE_REG(&sc->hw, TDLEN(que->me),((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03808 + ((que->me) *
 0x100)) : (0x0E008 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03808 + ((que->me) * 0x100)) : (
0x0E008 + ((que->me) * 0x40)))))), (sc->sc_tx_slots * sizeof
(struct em_tx_desc))))
    sc->sc_tx_slots *((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03808 + ((que->me) *
 0x100)) : (0x0E008 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03808 + ((que->me) * 0x100)) : (
0x0E008 + ((que->me) * 0x40)))))), (sc->sc_tx_slots * sizeof
(struct em_tx_desc))))
    sizeof(struct em_tx_desc))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03808 + ((que->me) *
 0x100)) : (0x0E008 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03808 + ((que->me) * 0x100)) : (
0x0E008 + ((que->me) * 0x40)))))), (sc->sc_tx_slots * sizeof
(struct em_tx_desc))));
E1000_WRITE_REG(&sc->hw, TDBAH(que->me), (u_int32_t)(bus_addr >> 32))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03804 + ((que->me) *
 0x100)) : (0x0E004 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03804 + ((que->me) * 0x100)) : (
0x0E004 + ((que->me) * 0x40)))))), ((u_int32_t)(bus_addr >>
 32))));
E1000_WRITE_REG(&sc->hw, TDBAL(que->me), (u_int32_t)bus_addr)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03800 + ((que->me) *
 0x100)) : (0x0E000 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03800 + ((que->me) * 0x100)) : (
0x0E000 + ((que->me) * 0x40)))))), ((u_int32_t)bus_addr)));

/* Setup the HW Tx Head and Tail descriptor pointers */
E1000_WRITE_REG(&sc->hw, TDT(que->me), 0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03818 + ((que->me) *
 0x100)) : (0x0E018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03818 + ((que->me) * 0x100)) : (
0x0E018 + ((que->me) * 0x40)))))), (0)));
E1000_WRITE_REG(&sc->hw, TDH(que->me), 0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03810 + ((que->me) *
 0x100)) : (0x0E010 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03810 + ((que->me) * 0x100)) : (
0x0E010 + ((que->me) * 0x40)))))), (0)));

HW_DEBUGOUT2("Base = %x, Length = %x\n",if (0) printf("Base = %x, Length = %x\n" "\n", ((((struct em_osdep
 *)(&sc->hw)->back)->mem_bus_space_tag)->read_4
((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_handle
), (((&sc->hw)->mac_type >= em_82543 ? ((que->
me) < 4 ? (0x03800 + ((que->me) * 0x100)) : (0x0E000 + (
(que->me) * 0x40))) : em_translate_82542_register(((que->
me) < 4 ? (0x03800 + ((que->me) * 0x100)) : (0x0E000 + (
(que->me) * 0x40)))))))), ((((struct em_osdep *)(&sc->
hw)->back)->mem_bus_space_tag)->read_4((((struct em_osdep
 *)(&sc->hw)->back)->mem_bus_space_handle), (((&
sc->hw)->mac_type >= em_82543 ? ((que->me) < 4
 ? (0x03808 + ((que->me) * 0x100)) : (0x0E008 + ((que->
me) * 0x40))) : em_translate_82542_register(((que->me) <
? (0x03808 + ((que->me) * 0x100)) : (0x0E008 + ((que->
me) * 0x40)))))))))
    E1000_READ_REG(&sc->hw, TDBAL(que->me)),if (0) printf("Base = %x, Length = %x\n" "\n", ((((struct em_osdep
 *)(&sc->hw)->back)->mem_bus_space_tag)->read_4
((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_handle
), (((&sc->hw)->mac_type >= em_82543 ? ((que->
me) < 4 ? (0x03800 + ((que->me) * 0x100)) : (0x0E000 + (
(que->me) * 0x40))) : em_translate_82542_register(((que->
me) < 4 ? (0x03800 + ((que->me) * 0x100)) : (0x0E000 + (
(que->me) * 0x40)))))))), ((((struct em_osdep *)(&sc->
hw)->back)->mem_bus_space_tag)->read_4((((struct em_osdep
 *)(&sc->hw)->back)->mem_bus_space_handle), (((&
sc->hw)->mac_type >= em_82543 ? ((que->me) < 4
 ? (0x03808 + ((que->me) * 0x100)) : (0x0E008 + ((que->
me) * 0x40))) : em_translate_82542_register(((que->me) <
? (0x03808 + ((que->me) * 0x100)) : (0x0E008 + ((que->
me) * 0x40)))))))))
    E1000_READ_REG(&sc->hw, TDLEN(que->me)))if (0) printf("Base = %x, Length = %x\n" "\n", ((((struct em_osdep
 *)(&sc->hw)->back)->mem_bus_space_tag)->read_4
((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_handle
), (((&sc->hw)->mac_type >= em_82543 ? ((que->
me) < 4 ? (0x03800 + ((que->me) * 0x100)) : (0x0E000 + (
(que->me) * 0x40))) : em_translate_82542_register(((que->
me) < 4 ? (0x03800 + ((que->me) * 0x100)) : (0x0E000 + (
(que->me) * 0x40)))))))), ((((struct em_osdep *)(&sc->
hw)->back)->mem_bus_space_tag)->read_4((((struct em_osdep
 *)(&sc->hw)->back)->mem_bus_space_handle), (((&
sc->hw)->mac_type >= em_82543 ? ((que->me) < 4
 ? (0x03808 + ((que->me) * 0x100)) : (0x0E008 + ((que->
me) * 0x40))) : em_translate_82542_register(((que->me) <
? (0x03808 + ((que->me) * 0x100)) : (0x0E008 + ((que->
me) * 0x40)))))))));

/* Set the default values for the Tx Inter Packet Gap timer */
switch (sc->hw.mac_type) {
case em_82542_rev2_0:
case em_82542_rev2_1:
	reg_tipg = DEFAULT_82542_TIPG_IPGT10;
	reg_tipg |= DEFAULT_82542_TIPG_IPGR12 << E1000_TIPG_IPGR1_SHIFT10;
	reg_tipg |= DEFAULT_82542_TIPG_IPGR210 << E1000_TIPG_IPGR2_SHIFT20;
	break;
case em_80003es2lan:
	reg_tipg = DEFAULT_82543_TIPG_IPGR18;
	reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR27 << E1000_TIPG_IPGR2_SHIFT20;
	break;
default:
	if (sc->hw.media_type == em_media_type_fiber ||
	    sc->hw.media_type == em_media_type_internal_serdes)
		reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER9;
	else
		reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER8;
	reg_tipg |= DEFAULT_82543_TIPG_IPGR18 << E1000_TIPG_IPGR1_SHIFT10;
	reg_tipg |= DEFAULT_82543_TIPG_IPGR26 << E1000_TIPG_IPGR2_SHIFT20;
}


E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00410 : em_translate_82542_register(0x00410))),
 (reg_tipg)));
E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x03820 : em_translate_82542_register(0x03820))),
 (sc->tx_int_delay)));
if (sc->hw.mac_type >= em_82540)
	E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x0382C : em_translate_82542_register(0x0382C))),
 (sc->tx_abs_int_delay)));

/* Setup Transmit Descriptor Base Settings */
que->tx.sc_txd_cmd = E1000_TXD_CMD_IFCS0x02000000;

if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 ||
    sc->hw.mac_type == em_82576 ||
    sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) {
	/* 82575/6 need to enable the TX queue and lack the IDE bit */
	reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? ((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) :
 (0x0E028 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (
0x0E028 + ((que->me) * 0x40))))))));
	reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE0x02000000;
	E1000_WRITE_REG(&sc->hw, TXDCTL(que->me), reg_tctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x03828 + ((que->me) *
 0x100)) : (0x0E028 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x03828 + ((que->me) * 0x100)) : (
0x0E028 + ((que->me) * 0x40)))))), (reg_tctl)));
} else if (sc->tx_int_delay > 0)
	que->tx.sc_txd_cmd |= E1000_TXD_CMD_IDE0x80000000;
}

/* Program the Transmit Control Register */
reg_tctl = E1000_TCTL_PSP0x00000008 | E1000_TCTL_EN0x00000002 |
   (E1000_COLLISION_THRESHOLD15 << E1000_CT_SHIFT4);
if (sc->hw.mac_type >= em_82571)
reg_tctl |= E1000_TCTL_MULR0x10000000;
if (sc->link_duplex == FULL_DUPLEX2)
reg_tctl |= E1000_FDX_COLLISION_DISTANCE63 << E1000_COLD_SHIFT12;
else
reg_tctl |= E1000_HDX_COLLISION_DISTANCE63 << E1000_COLD_SHIFT12;
/* This write will effectively turn on the transmit unit */
E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00400 : em_translate_82542_register(0x00400))),
 (reg_tctl)));

/* SPT Si errata workaround to avoid data corruption */

if (sc->hw.mac_type == em_pch_spt) {
uint32_t	reg_val;

reg_val = EM_READ_REG(&sc->hw, E1000_IOSFPC)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (0x00F28)));
reg_val |= E1000_RCTL_RDMTS_HEX0x00010000;
EM_WRITE_REG(&sc->hw, E1000_IOSFPC, reg_val)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (0x00F28), (reg_val)));

reg_val = E1000_READ_REG(&sc->hw, TARC0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x03840 : em_translate_82542_register(0x03840)))));
/* i218-i219 Specification Update 1.5.4.5 */
reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ(1 << 28 | 1 << 29);
reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ(1 << 29);
E1000_WRITE_REG(&sc->hw, TARC0, reg_val)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x03840 : em_translate_82542_register(0x03840))),
 (reg_val)));
}
2339}

2341/*********************************************************************
*
*  Free all transmit related data structures.
*
**********************************************************************/
2346void
2347em_free_transmit_structures(struct em_softc *sc)
2348{
struct em_queue *que;
struct em_packet *pkt;
int i;

INIT_DEBUGOUT("free_transmit_structures: begin")if (0) printf("free_transmit_structures: begin" "\n");

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
if (que->tx.sc_tx_pkts_ring != NULL((void *)0)) {
	for (i = 0; i < sc->sc_tx_slots; i++) {
		pkt = &que->tx.sc_tx_pkts_ring[i];

		if (pkt->pkt_m != NULL((void *)0)) {
			bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x08))
			    0, pkt->pkt_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x08))
			    BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x08));
			bus_dmamap_unload(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (pkt
->pkt_map))
			    pkt->pkt_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (pkt
->pkt_map));

			m_freem(pkt->pkt_m);
			pkt->pkt_m = NULL((void *)0);
		}

		if (pkt->pkt_map != NULL((void *)0)) {
			bus_dmamap_destroy(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (pkt
->pkt_map))
			    pkt->pkt_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (pkt
->pkt_map));
			pkt->pkt_map = NULL((void *)0);
		}
	}

	free(que->tx.sc_tx_pkts_ring, M_DEVBUF2,
	    sc->sc_tx_slots * sizeof(*que->tx.sc_tx_pkts_ring));
	que->tx.sc_tx_pkts_ring = NULL((void *)0);
}

bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08))
    0, que->tx.sc_tx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02 | 0x08));
}
2387}

2389/*********************************************************************
*
*  The offload context needs to be set when we transfer the first
*  packet of a particular protocol (TCP/UDP). We change the
*  context only if the protocol type changes.
*
**********************************************************************/
2396u_int
2397em_transmit_checksum_setup(struct em_queue *que, struct mbuf *mp, u_int head,
  u_int32_t *txd_upper, u_int32_t *txd_lower)
2399{
struct em_context_desc *TXD;

if (mp->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_TCP_CSUM_OUT0x0002) {
*txd_upper = E1000_TXD_POPTS_TXSM0x02 << 8;
*txd_lower = E1000_TXD_CMD_DEXT0x20000000 | E1000_TXD_DTYP_D0x00100000;
if (que->tx.active_checksum_context == OFFLOAD_TCP_IP)
	return (0);
else
	que->tx.active_checksum_context = OFFLOAD_TCP_IP;
} else if (mp->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_UDP_CSUM_OUT0x0004) {
*txd_upper = E1000_TXD_POPTS_TXSM0x02 << 8;
*txd_lower = E1000_TXD_CMD_DEXT0x20000000 | E1000_TXD_DTYP_D0x00100000;
if (que->tx.active_checksum_context == OFFLOAD_UDP_IP)
	return (0);
else
	que->tx.active_checksum_context = OFFLOAD_UDP_IP;
} else {
*txd_upper = 0;
*txd_lower = 0;
return (0);
}

/* If we reach this point, the checksum offload context
* needs to be reset.
*/
TXD = (struct em_context_desc *)&que->tx.sc_tx_desc_ring[head];

TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN((6 * 2) + 2);
TXD->lower_setup.ip_fields.ipcso = 
   ETHER_HDR_LEN((6 * 2) + 2) + offsetof(struct ip, ip_sum)__builtin_offsetof(struct ip, ip_sum);
TXD->lower_setup.ip_fields.ipcse = 
   htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1)((__uint16_t)(((6 * 2) + 2) + sizeof(struct ip) - 1));

TXD->upper_setup.tcp_fields.tucss = 
   ETHER_HDR_LEN((6 * 2) + 2) + sizeof(struct ip);
TXD->upper_setup.tcp_fields.tucse = htole16(0)((__uint16_t)(0));

if (que->tx.active_checksum_context == OFFLOAD_TCP_IP) {
TXD->upper_setup.tcp_fields.tucso = 
    ETHER_HDR_LEN((6 * 2) + 2) + sizeof(struct ip) + 
    offsetof(struct tcphdr, th_sum)__builtin_offsetof(struct tcphdr, th_sum);
} else if (que->tx.active_checksum_context == OFFLOAD_UDP_IP) {
TXD->upper_setup.tcp_fields.tucso = 
    ETHER_HDR_LEN((6 * 2) + 2) + sizeof(struct ip) + 
    offsetof(struct udphdr, uh_sum)__builtin_offsetof(struct udphdr, uh_sum);
}

TXD->tcp_seg_setup.data = htole32(0)((__uint32_t)(0));
TXD->cmd_and_length = htole32(que->tx.sc_txd_cmd | E1000_TXD_CMD_DEXT)((__uint32_t)(que->tx.sc_txd_cmd | 0x20000000));

return (1);
2451}

2453/**********************************************************************
*
*  Examine each tx_buffer in the used queue. If the hardware is done
*  processing the packet then free associated resources. The
*  tx_buffer is put back on the free queue. 
*
**********************************************************************/
2460void
2461em_txeof(struct em_queue *que)
2462{
struct em_softc *sc = que->sc;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct em_packet *pkt;
struct em_tx_desc *desc;
u_int head, tail;
u_int free = 0;

head = que->tx.sc_tx_desc_head;
tail = que->tx.sc_tx_desc_tail;

if (head == tail)
return;

bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02))
   0, que->tx.sc_tx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02))
   BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x02));

do {
pkt = &que->tx.sc_tx_pkts_ring[tail];
desc = &que->tx.sc_tx_desc_ring[pkt->pkt_eop];

if (!ISSET(desc->upper.fields.status, E1000_TXD_STAT_DD)((desc->upper.fields.status) & (0x00000001)))
	break;

bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x08))
    0, pkt->pkt_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x08))
    BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x08));
bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (pkt
->pkt_map));

KASSERT(pkt->pkt_m != NULL)((pkt->pkt_m != ((void *)0)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/if_em.c", 2492, "pkt->pkt_m != NULL"
));

m_freem(pkt->pkt_m);
pkt->pkt_m = NULL((void *)0);

tail = pkt->pkt_eop;

if (++tail == sc->sc_tx_slots)
	tail = 0;

free++;
} while (tail != head);

bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01))
   0, que->tx.sc_tx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01))
   BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
tx.sc_tx_dma.dma_map), (0), (que->tx.sc_tx_dma.dma_map->
dm_mapsize), (0x01));

if (free == 0)
return;

que->tx.sc_tx_desc_tail = tail;

if (ifq_is_oactive(&ifp->if_snd))
ifq_restart(&ifp->if_snd);
else if (tail == head)
ifp->if_timer = 0;
2518}

2520/*********************************************************************
*
*  Get a buffer from system mbuf buffer pool.
*
**********************************************************************/
2525int
2526em_get_buf(struct em_queue *que, int i)
2527{
struct em_softc *sc = que->sc;
struct mbuf    *m;
struct em_packet *pkt;
struct em_rx_desc *desc;
int error;

pkt = &que->rx.sc_rx_pkts_ring[i];
desc = &que->rx.sc_rx_desc_ring[i];

KASSERT(pkt->pkt_m == NULL)((pkt->pkt_m == ((void *)0)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/if_em.c", 2537, "pkt->pkt_m == NULL"
));

m = MCLGETL(NULL, M_DONTWAIT, EM_MCLBYTES)m_clget((((void *)0)), (0x0002), ((2048 + 2)));
if (m == NULL((void *)0)) {
sc->mbuf_cluster_failed++;
return (ENOBUFS55);
}
m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = EM_MCLBYTES(2048 + 2);
m_adj(m, ETHER_ALIGN2);

error = bus_dmamap_load_mbuf(sc->sc_dmat, pkt->pkt_map,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
pkt->pkt_map), (m), (0x0001))
   m, BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
pkt->pkt_map), (m), (0x0001));
if (error) {
m_freem(m);
return (error);
}

bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x01))
   0, pkt->pkt_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x01))
   BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x01));
pkt->pkt_m = m;

memset(desc, 0, sizeof(*desc))__builtin_memset((desc), (0), (sizeof(*desc)));
htolem64(&desc->buffer_addr, pkt->pkt_map->dm_segs[0].ds_addr)(*(__uint64_t *)(&desc->buffer_addr) = ((__uint64_t)(pkt
->pkt_map->dm_segs[0].ds_addr)));

return (0);
2563}

2565/*********************************************************************
*
*  Allocate memory for rx_buffer structures. Since we use one 
*  rx_buffer per received packet, the maximum number of rx_buffer's 
*  that we'll need is equal to the number of receive descriptors 
*  that we've allocated.
*
**********************************************************************/
2573int
2574em_allocate_receive_structures(struct em_softc *sc)
2575{
struct em_queue *que;
struct em_packet *pkt;
int i;
int error;

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
que->rx.sc_rx_pkts_ring = mallocarray(sc->sc_rx_slots,
    sizeof(*que->rx.sc_rx_pkts_ring),
    M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (que->rx.sc_rx_pkts_ring == NULL((void *)0)) {
	printf("%s: Unable to allocate rx_buffer memory\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return (ENOMEM12);
}

bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x01 | 0x04))
    0, que->rx.sc_rx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x01 | 0x04))
    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x01 | 0x04));

for (i = 0; i < sc->sc_rx_slots; i++) {
	pkt = &que->rx.sc_rx_pkts_ring[i];

	error = bus_dmamap_create(sc->sc_dmat, EM_MCLBYTES, 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((2048
 + 2)), (1), ((2048 + 2)), (0), (0x0001), (&pkt->pkt_map
))
	    EM_MCLBYTES, 0, BUS_DMA_NOWAIT, &pkt->pkt_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((2048
 + 2)), (1), ((2048 + 2)), (0), (0x0001), (&pkt->pkt_map
));
	if (error != 0) {
		printf("%s: em_allocate_receive_structures: "
		    "bus_dmamap_create failed; error %u\n",
		    DEVNAME(sc)((sc)->sc_dev.dv_xname), error);
		goto fail;
	}

	pkt->pkt_m = NULL((void *)0);
}
}

      return (0);

2613fail:
em_free_receive_structures(sc);
return (error);
2616}

2618/*********************************************************************
*
*  Allocate and initialize receive structures.
*  
**********************************************************************/
2623int
2624em_setup_receive_structures(struct em_softc *sc)
2625{
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct em_queue *que;
u_int lwm;

if (em_allocate_receive_structures(sc))
return (ENOMEM12);

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
memset(que->rx.sc_rx_desc_ring, 0,__builtin_memset((que->rx.sc_rx_desc_ring), (0), (sc->sc_rx_slots
 * sizeof(*que->rx.sc_rx_desc_ring)))
    sc->sc_rx_slots * sizeof(*que->rx.sc_rx_desc_ring))__builtin_memset((que->rx.sc_rx_desc_ring), (0), (sc->sc_rx_slots
 * sizeof(*que->rx.sc_rx_desc_ring)));

/* Setup our descriptor pointers */
que->rx.sc_rx_desc_tail = 0;
que->rx.sc_rx_desc_head = sc->sc_rx_slots - 1;

lwm = max(4, 2 * ((ifp->if_hardmtu / MCLBYTES(1 << 11)) + 1));
if_rxr_init(&que->rx.sc_rx_ring, lwm, sc->sc_rx_slots);

if (em_rxfill(que) == 0) {
	printf("%s: unable to fill any rx descriptors\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return (ENOMEM12);
}
}

return (0);
2652}

2654/*********************************************************************
*
*  Enable receive unit.
*  
**********************************************************************/
2659void
2660em_initialize_receive_unit(struct em_softc *sc)
2661{
struct em_queue *que;
u_int32_t	reg_rctl;
u_int32_t	reg_rxcsum;
u_int32_t	reg_srrctl;
u_int64_t	bus_addr;

INIT_DEBUGOUT("em_initialize_receive_unit: begin")if (0) printf("em_initialize_receive_unit: begin" "\n");

/* Make sure receives are disabled while setting up the descriptor ring */
E1000_WRITE_REG(&sc->hw, RCTL, 0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00100 : em_translate_82542_register(0x00100))),
 (0)));

/* Set the Receive Delay Timer Register */
E1000_WRITE_REG(&sc->hw, RDTR,((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x02820 : em_translate_82542_register(0x02820))),
 (sc->rx_int_delay | 0x80000000))) 
	sc->rx_int_delay | E1000_RDT_FPDB)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x02820 : em_translate_82542_register(0x02820))),
 (sc->rx_int_delay | 0x80000000)));

if (sc->hw.mac_type >= em_82540) {
if (sc->rx_int_delay)
	E1000_WRITE_REG(&sc->hw, RADV, sc->rx_abs_int_delay)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x0282C : em_translate_82542_register(0x0282C))),
 (sc->rx_abs_int_delay)));

/* Set the interrupt throttling rate.  Value is calculated
 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x000C4 : em_translate_82542_register(0x000C4))),
 (1000000000/(8000 * 256))));
}

/* Setup the Receive Control Register */
reg_rctl = E1000_RCTL_EN0x00000002 | E1000_RCTL_BAM0x00008000 | E1000_RCTL_LBM_NO0x00000000 |
   E1000_RCTL_RDMTS_HALF0x00000000 |
   (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT12);

if (sc->hw.tbi_compatibility_on == TRUE1)
reg_rctl |= E1000_RCTL_SBP0x00000004;

/*
* The i350 has a bug where it always strips the CRC whether
* asked to or not.  So ask for stripped CRC here and
* cope in rxeof
*/
if (sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350)
reg_rctl |= E1000_RCTL_SECRC0x04000000;

switch (sc->sc_rx_buffer_len) {
default:
case EM_RXBUFFER_20482048:
reg_rctl |= E1000_RCTL_SZ_20480x00000000;
break;
case EM_RXBUFFER_40964096:
reg_rctl |= E1000_RCTL_SZ_40960x00030000|E1000_RCTL_BSEX0x02000000|E1000_RCTL_LPE0x00000020;
break;		  
case EM_RXBUFFER_81928192:
reg_rctl |= E1000_RCTL_SZ_81920x00020000|E1000_RCTL_BSEX0x02000000|E1000_RCTL_LPE0x00000020;
break;
case EM_RXBUFFER_1638416384:
reg_rctl |= E1000_RCTL_SZ_163840x00010000|E1000_RCTL_BSEX0x02000000|E1000_RCTL_LPE0x00000020;
break;
}

if (sc->hw.max_frame_size != ETHER_MAX_LEN1518)
reg_rctl |= E1000_RCTL_LPE0x00000020;

/* Enable 82543 Receive Checksum Offload for TCP and UDP */
if (sc->hw.mac_type >= em_82543) {
reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x05000 : em_translate_82542_register(0x05000)))));
reg_rxcsum |= (E1000_RXCSUM_IPOFL0x00000100 | E1000_RXCSUM_TUOFL0x00000200);
E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x05000 : em_translate_82542_register(0x05000))),
 (reg_rxcsum)));
}

/*
* XXX TEMPORARY WORKAROUND: on some systems with 82573
* long latencies are observed, like Lenovo X60.
*/
if (sc->hw.mac_type == em_82573)
E1000_WRITE_REG(&sc->hw, RDTR, 0x20)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x02820 : em_translate_82542_register(0x02820))),
 (0x20)));

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
if (sc->num_queues > 1) {
	/*
	 * Disable Drop Enable for every queue, default has
	 * it enabled for queues > 0
	 */
	reg_srrctl = E1000_READ_REG(&sc->hw, SRRCTL(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? ((que->me) < 4 ? (0x0280C + ((que->me) * 0x100)) :
 (0x0C00C + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x0280C + ((que->me) * 0x100)) : (
0x0C00C + ((que->me) * 0x40))))))));
	reg_srrctl &= ~E1000_SRRCTL_DROP_EN0x80000000;
	E1000_WRITE_REG(&sc->hw, SRRCTL(que->me), reg_srrctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x0280C + ((que->me) *
 0x100)) : (0x0C00C + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x0280C + ((que->me) * 0x100)) : (
0x0C00C + ((que->me) * 0x40)))))), (reg_srrctl)));
}

/* Setup the Base and Length of the Rx Descriptor Ring */
bus_addr = que->rx.sc_rx_dma.dma_map->dm_segs[0].ds_addr;
E1000_WRITE_REG(&sc->hw, RDLEN(que->me),((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x02808 + ((que->me) *
 0x100)) : (0x0C008 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02808 + ((que->me) * 0x100)) : (
0x0C008 + ((que->me) * 0x40)))))), (sc->sc_rx_slots * sizeof
(*que->rx.sc_rx_desc_ring))))
    sc->sc_rx_slots * sizeof(*que->rx.sc_rx_desc_ring))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x02808 + ((que->me) *
 0x100)) : (0x0C008 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02808 + ((que->me) * 0x100)) : (
0x0C008 + ((que->me) * 0x40)))))), (sc->sc_rx_slots * sizeof
(*que->rx.sc_rx_desc_ring))));
E1000_WRITE_REG(&sc->hw, RDBAH(que->me), (u_int32_t)(bus_addr >> 32))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x02804 + ((que->me) *
 0x100)) : (0x0C004 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02804 + ((que->me) * 0x100)) : (
0x0C004 + ((que->me) * 0x40)))))), ((u_int32_t)(bus_addr >>
 32))));
E1000_WRITE_REG(&sc->hw, RDBAL(que->me), (u_int32_t)bus_addr)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x02800 + ((que->me) *
 0x100)) : (0x0C000 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02800 + ((que->me) * 0x100)) : (
0x0C000 + ((que->me) * 0x40)))))), ((u_int32_t)bus_addr)));

if (sc->hw.mac_type == em_82575 || sc->hw.mac_type == em_82580 ||
    sc->hw.mac_type == em_82576 ||
    sc->hw.mac_type == em_i210 || sc->hw.mac_type == em_i350) {
	/* 82575/6 need to enable the RX queue */
	uint32_t reg;
	reg = E1000_READ_REG(&sc->hw, RXDCTL(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? ((que->me) < 4 ? (0x02828 + ((que->me) * 0x100)) :
 (0x0C028 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02828 + ((que->me) * 0x100)) : (
0x0C028 + ((que->me) * 0x40))))))));
	reg |= E1000_RXDCTL_QUEUE_ENABLE0x2000000;
	E1000_WRITE_REG(&sc->hw, RXDCTL(que->me), reg)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x02828 + ((que->me) *
 0x100)) : (0x0C028 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02828 + ((que->me) * 0x100)) : (
0x0C028 + ((que->me) * 0x40)))))), (reg)));
}
}

/* Enable Receives */
E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00100 : em_translate_82542_register(0x00100))),
 (reg_rctl)));

/* Setup the HW Rx Head and Tail Descriptor Pointers */
FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
E1000_WRITE_REG(&sc->hw, RDH(que->me), 0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x02810 + ((que->me) *
 0x100)) : (0x0C010 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02810 + ((que->me) * 0x100)) : (
0x0C010 + ((que->me) * 0x40)))))), (0)));
E1000_WRITE_REG(&sc->hw, RDT(que->me), que->rx.sc_rx_desc_head)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x02818 + ((que->me) *
 0x100)) : (0x0C018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02818 + ((que->me) * 0x100)) : (
0x0C018 + ((que->me) * 0x40)))))), (que->rx.sc_rx_desc_head
)));
}
2772}

2774/*********************************************************************
*
*  Free receive related data structures.
*
**********************************************************************/
2779void
2780em_free_receive_structures(struct em_softc *sc)
2781{
struct em_queue *que;
struct em_packet *pkt;
int i;

INIT_DEBUGOUT("free_receive_structures: begin")if (0) printf("free_receive_structures: begin" "\n");

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
if_rxr_init(&que->rx.sc_rx_ring, 0, 0);

bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x02 | 0x08))
    0, que->rx.sc_rx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x02 | 0x08))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x02 | 0x08));

if (que->rx.sc_rx_pkts_ring != NULL((void *)0)) {
	for (i = 0; i < sc->sc_rx_slots; i++) {
		pkt = &que->rx.sc_rx_pkts_ring[i];
		if (pkt->pkt_m != NULL((void *)0)) {
			bus_dmamap_sync(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x02))
			    pkt->pkt_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x02))
			    0, pkt->pkt_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x02))
			    BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x02));
			bus_dmamap_unload(sc->sc_dmat,(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (pkt
->pkt_map))
			    pkt->pkt_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (pkt
->pkt_map));
			m_freem(pkt->pkt_m);
			pkt->pkt_m = NULL((void *)0);
		}
		bus_dmamap_destroy(sc->sc_dmat, pkt->pkt_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (pkt
->pkt_map));
	}

	free(que->rx.sc_rx_pkts_ring, M_DEVBUF2,
	    sc->sc_rx_slots * sizeof(*que->rx.sc_rx_pkts_ring));
	que->rx.sc_rx_pkts_ring = NULL((void *)0);
}

if (que->rx.fmp != NULL((void *)0)) {
	m_freem(que->rx.fmp);
	que->rx.fmp = NULL((void *)0);
	que->rx.lmp = NULL((void *)0);
}
}
2822}

2824int
2825em_rxfill(struct em_queue *que)
2826{
struct em_softc *sc = que->sc;
u_int slots;
int post = 0;
int i;

i = que->rx.sc_rx_desc_head;

bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x08))
   0, que->rx.sc_rx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x08))
   BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x08));

for (slots = if_rxr_get(&que->rx.sc_rx_ring, sc->sc_rx_slots);
   slots > 0; slots--) {
if (++i == sc->sc_rx_slots)
	i = 0;

if (em_get_buf(que, i) != 0)
	break;

que->rx.sc_rx_desc_head = i;
post = 1;
}

if_rxr_put(&que->rx.sc_rx_ring, slots)do { (&que->rx.sc_rx_ring)->rxr_alive -= (slots); }
 while (0);

bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x04))
   0, que->rx.sc_rx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x04))
   BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x04));

return (post);
2857}

2859void
2860em_rxrefill(void *arg)
2861{
struct em_queue *que = arg;
struct em_softc *sc = que->sc;

if (em_rxfill(que))
E1000_WRITE_REG(&sc->hw, RDT(que->me), que->rx.sc_rx_desc_head)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? ((que->me) < 4 ? (0x02818 + ((que->me) *
 0x100)) : (0x0C018 + ((que->me) * 0x40))) : em_translate_82542_register
(((que->me) < 4 ? (0x02818 + ((que->me) * 0x100)) : (
0x0C018 + ((que->me) * 0x40)))))), (que->rx.sc_rx_desc_head
)));
else if (if_rxr_needrefill(&que->rx.sc_rx_ring)((&que->rx.sc_rx_ring)->rxr_alive < (&que->
rx.sc_rx_ring)->rxr_lwm))
timeout_add(&que->rx_refill, 1);
2869}

2871/*********************************************************************
*
*  This routine executes in interrupt context. It replenishes
*  the mbufs in the descriptor and sends data which has been
*  dma'ed into host memory to upper layer.
*
*********************************************************************/
2878int
2879em_rxeof(struct em_queue *que)
2880{
struct em_softc	    *sc = que->sc;
struct ifnet	    *ifp = &sc->sc_ac.ac_if;
struct mbuf_list    ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
struct mbuf	    *m;
u_int8_t	    accept_frame = 0;
u_int8_t	    eop = 0;
u_int16_t	    len, desc_len, prev_len_adj;
int		    i, rv = 0;

/* Pointer to the receive descriptor being examined. */
struct em_rx_desc   *desc;
struct em_packet    *pkt;
u_int8_t	    status;

if (if_rxr_inuse(&que->rx.sc_rx_ring)((&que->rx.sc_rx_ring)->rxr_alive) == 0)
return (0);

i = que->rx.sc_rx_desc_tail;

bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x02))
   0, que->rx.sc_rx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x02))
   BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x02));

do {
m = NULL((void *)0);

pkt = &que->rx.sc_rx_pkts_ring[i];
desc = &que->rx.sc_rx_desc_ring[i];

status = desc->status;
if (!ISSET(status, E1000_RXD_STAT_DD)((status) & (0x01)))
	break;

/* pull the mbuf off the ring */
bus_dmamap_sync(sc->sc_dmat, pkt->pkt_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x02))
    0, pkt->pkt_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x02))
    BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (pkt->
pkt_map), (0), (pkt->pkt_map->dm_mapsize), (0x02));
bus_dmamap_unload(sc->sc_dmat, pkt->pkt_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (pkt
->pkt_map));
m = pkt->pkt_m;
pkt->pkt_m = NULL((void *)0);

KASSERT(m != NULL)((m != ((void *)0)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_em.c"
, 2922, "m != NULL"));

if_rxr_put(&que->rx.sc_rx_ring, 1)do { (&que->rx.sc_rx_ring)->rxr_alive -= (1); } while
 (0);
rv = 1;

accept_frame = 1;
prev_len_adj = 0;
desc_len = letoh16(desc->length)((__uint16_t)(desc->length));

if (status & E1000_RXD_STAT_EOP0x02) {
	eop = 1;
	if (desc_len < ETHER_CRC_LEN4) {
		len = 0;
		prev_len_adj = ETHER_CRC_LEN4 - desc_len;
	} else if (sc->hw.mac_type == em_i210 ||
	    sc->hw.mac_type == em_i350)
		len = desc_len;
	else
		len = desc_len - ETHER_CRC_LEN4;
} else {
	eop = 0;
	len = desc_len;
}

if (desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK( 0x01 | 0x02 | 0x04 | 0x10 | 0x80)) {
	u_int8_t last_byte;
	u_int32_t pkt_len = desc_len;

	if (que->rx.fmp != NULL((void *)0))
		pkt_len += que->rx.fmp->m_pkthdrM_dat.MH.MH_pkthdr.len;

	last_byte = *(mtod(m, caddr_t)((caddr_t)((m)->m_hdr.mh_data)) + desc_len - 1);
	if (TBI_ACCEPT(&sc->hw, status, desc->errors,((&sc->hw)->tbi_compatibility_on && (((desc
->errors) & ( 0x01 | 0x02 | 0x04 | 0x10 | 0x80)) == 0x01
) && ((last_byte) == 0x0F) && (((status) &
 0x08) ? (((pkt_len) > ((&sc->hw)->min_frame_size
 - 4)) && ((pkt_len) <= ((&sc->hw)->max_frame_size
 + 1))) : (((pkt_len) > (&sc->hw)->min_frame_size
) && ((pkt_len) <= ((&sc->hw)->max_frame_size
 + 4 + 1)))))
	    pkt_len, last_byte)((&sc->hw)->tbi_compatibility_on && (((desc
->errors) & ( 0x01 | 0x02 | 0x04 | 0x10 | 0x80)) == 0x01
) && ((last_byte) == 0x0F) && (((status) &
 0x08) ? (((pkt_len) > ((&sc->hw)->min_frame_size
 - 4)) && ((pkt_len) <= ((&sc->hw)->max_frame_size
 + 1))) : (((pkt_len) > (&sc->hw)->min_frame_size
) && ((pkt_len) <= ((&sc->hw)->max_frame_size
 + 4 + 1)))))) {
2956#if NKSTAT0 > 0
		em_tbi_adjust_stats(sc,
		    pkt_len, sc->hw.mac_addr);
2959#endif
		if (len > 0)
			len--;
	} else
		accept_frame = 0;
}

if (accept_frame) {
	/* Assign correct length to the current fragment */
	m->m_lenm_hdr.mh_len = len;

	if (que->rx.fmp == NULL((void *)0)) {
		m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len;
		que->rx.fmp = m;	 /* Store the first mbuf */
		que->rx.lmp = m;
	} else {
		/* Chain mbuf's together */
		m->m_flagsm_hdr.mh_flags &= ~M_PKTHDR0x0002;
		/*
		 * Adjust length of previous mbuf in chain if
		 * we received less than 4 bytes in the last
		 * descriptor.
		 */
		if (prev_len_adj > 0) {
			que->rx.lmp->m_lenm_hdr.mh_len -= prev_len_adj;
			que->rx.fmp->m_pkthdrM_dat.MH.MH_pkthdr.len -= prev_len_adj;
		}
		que->rx.lmp->m_nextm_hdr.mh_next = m;
		que->rx.lmp = m;
		que->rx.fmp->m_pkthdrM_dat.MH.MH_pkthdr.len += m->m_lenm_hdr.mh_len;
	}

	if (eop) {
		m = que->rx.fmp;

		em_receive_checksum(sc, desc, m);
2995#if NVLAN1 > 0
		if (desc->status & E1000_RXD_STAT_VP0x08) {
			m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag =
			    letoh16(desc->special)((__uint16_t)(desc->special));
			m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020;
		}
3001#endif
		ml_enqueue(&ml, m);

		que->rx.fmp = NULL((void *)0);
		que->rx.lmp = NULL((void *)0);
	}
} else {
	que->rx.dropped_pkts++;

	if (que->rx.fmp != NULL((void *)0)) {
		m_freem(que->rx.fmp);
		que->rx.fmp = NULL((void *)0);
		que->rx.lmp = NULL((void *)0);
	}

	m_freem(m);
}

/* Advance our pointers to the next descriptor. */
if (++i == sc->sc_rx_slots)
	i = 0;
} while (if_rxr_inuse(&que->rx.sc_rx_ring)((&que->rx.sc_rx_ring)->rxr_alive) > 0);

bus_dmamap_sync(sc->sc_dmat, que->rx.sc_rx_dma.dma_map,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x01))
   0, que->rx.sc_rx_dma.dma_map->dm_mapsize,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x01))
   BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (que->
rx.sc_rx_dma.dma_map), (0), (que->rx.sc_rx_dma.dma_map->
dm_mapsize), (0x01));

que->rx.sc_rx_desc_tail = i;

if (ifiq_input(&ifp->if_rcv, &ml))
if_rxr_livelocked(&que->rx.sc_rx_ring);

return (rv);
3034}

3036/*********************************************************************
*
*  Verify that the hardware indicated that the checksum is valid. 
*  Inform the stack about the status of checksum so that stack
*  doesn't spend time verifying the checksum.
*
*********************************************************************/
3043void
3044em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc,
  struct mbuf *mp)
3046{
/* 82543 or newer only */
if ((sc->hw.mac_type < em_82543) ||
   /* Ignore Checksum bit is set */
   (rx_desc->status & E1000_RXD_STAT_IXSM0x04)) {
mp->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags = 0;
return;
}

if (rx_desc->status & E1000_RXD_STAT_IPCS0x40) {
/* Did it pass? */
if (!(rx_desc->errors & E1000_RXD_ERR_IPE0x40)) {
	/* IP Checksum Good */
	mp->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK0x0008;

} else
	mp->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags = 0;
}

if (rx_desc->status & E1000_RXD_STAT_TCPCS0x20) {
/* Did it pass? */        
if (!(rx_desc->errors & E1000_RXD_ERR_TCPE0x20))
	mp->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |=
		M_TCP_CSUM_IN_OK0x0020 | M_UDP_CSUM_IN_OK0x0080;
}
3071}

3073/*
* This turns on the hardware offload of the VLAN
* tag insertion and strip
*/
3077void 
3078em_enable_hw_vlans(struct em_softc *sc)
3079{
uint32_t ctrl;

ctrl = E1000_READ_REG(&sc->hw, CTRL)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00000 : em_translate_82542_register(0x00000)))));
ctrl |= E1000_CTRL_VME0x40000000;
E1000_WRITE_REG(&sc->hw, CTRL, ctrl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x00000 : em_translate_82542_register(0x00000))),
 (ctrl)));
3085}

3087void
3088em_enable_intr(struct em_softc *sc)
3089{
uint32_t mask;

if (sc->msix) {
mask = sc->msix_queuesmask | sc->msix_linkmask;
E1000_WRITE_REG(&sc->hw, EIAC, mask)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x0152C : em_translate_82542_register(0x0152C))),
 (mask)));
E1000_WRITE_REG(&sc->hw, EIAM, mask)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01530 : em_translate_82542_register(0x01530))),
 (mask)));
E1000_WRITE_REG(&sc->hw, EIMS, mask)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01524 : em_translate_82542_register(0x01524))),
 (mask)));
E1000_WRITE_REG(&sc->hw, IMS, E1000_IMS_LSC)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x000D0 : em_translate_82542_register(0x000D0))),
 (0x00000004)));
} else
E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x000D0 : em_translate_82542_register(0x000D0))),
 ((( 0x00000080 | 0x00000001 | 0x00000010 | 0x00000008 | 0x00000040
 | 0x00000004)))));
3100}

3102void
3103em_disable_intr(struct em_softc *sc)
3104{
/*
* The first version of 82542 had an errata where when link
* was forced it would stay up even if the cable was disconnected
* Sequence errors were used to detect the disconnect and then
* the driver would unforce the link.  This code is in the ISR.
* For this to work correctly the Sequence error interrupt had
* to be enabled all the time.
*/
if (sc->msix) {
E1000_WRITE_REG(&sc->hw, EIMC, ~0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01528 : em_translate_82542_register(0x01528))),
 (~0)));
E1000_WRITE_REG(&sc->hw, EIAC, 0)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x0152C : em_translate_82542_register(0x0152C))),
 (0)));
} else if (sc->hw.mac_type == em_82542_rev2_0)
E1000_WRITE_REG(&sc->hw, IMC, (0xffffffff & ~E1000_IMC_RXSEQ))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x000D8 : em_translate_82542_register(0x000D8))),
 ((0xffffffff & ~0x00000008))));
else
E1000_WRITE_REG(&sc->hw, IMC, 0xffffffff)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x000D8 : em_translate_82542_register(0x000D8))),
 (0xffffffff)));
3120}

3122void
3123em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3124{
struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
pcireg_t val;

val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
if (reg & 0x2) {
val &= 0x0000ffff;
val |= (*value << 16);
} else {
val &= 0xffff0000;
val |= *value;
}
pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, val);
3137}

3139void
3140em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3141{
struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
pcireg_t val;

val = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3);
if (reg & 0x2)
*value = (val >> 16) & 0xffff;
else
*value = val & 0xffff;
3150}

3152void
3153em_pci_set_mwi(struct em_hw *hw)
3154{
struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG0x04,
(hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE0x0010));
3159}

3161void
3162em_pci_clear_mwi(struct em_hw *hw)
3163{
struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;

pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG0x04,
(hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE0x0010));
3168}

3170/*
* We may eventually really do this, but its unnecessary
* for now so we just return unsupported.
*/
3174int32_t
3175em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3176{
return -E1000_NOT_IMPLEMENTED14;
3178}

3180/*********************************************************************
3181* 82544 Coexistence issue workaround.
3182*    There are 2 issues.
3183*       1. Transmit Hang issue.
3184*    To detect this issue, following equation can be used...
3185*          SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3186*          If SUM[3:0] is in between 1 to 4, we will have this issue.
3187*
3188*       2. DAC issue.
3189*    To detect this issue, following equation can be used...
3190*          SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3191*          If SUM[3:0] is in between 9 to c, we will have this issue.
3192*
3193*
3194*    WORKAROUND:
3195*          Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC)
3196*
3197*** *********************************************************************/
3198u_int32_t
3199em_fill_descriptors(u_int64_t address, u_int32_t length,
  PDESC_ARRAY desc_array)
3201{
      /* Since issue is sensitive to length and address.*/
      /* Let us first check the address...*/
      u_int32_t safe_terminator;
      if (length <= 4) {
              desc_array->descriptor[0].address = address;
              desc_array->descriptor[0].length = length;
              desc_array->elements = 1;
              return desc_array->elements;
      }
      safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF);
      /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
      if (safe_terminator == 0   ||
      (safe_terminator > 4   &&
      safe_terminator < 9)   ||
      (safe_terminator > 0xC &&
      safe_terminator <= 0xF)) {
              desc_array->descriptor[0].address = address;
              desc_array->descriptor[0].length = length;
              desc_array->elements = 1;
              return desc_array->elements;
      }

      desc_array->descriptor[0].address = address;
      desc_array->descriptor[0].length = length - 4;
      desc_array->descriptor[1].address = address + (length - 4);
      desc_array->descriptor[1].length = 4;
      desc_array->elements = 2;
      return desc_array->elements;
3230}

3232/*
* Disable the L0S and L1 LINK states.
*/
3235void
3236em_disable_aspm(struct em_softc *sc)
3237{
int offset;
pcireg_t val;

switch (sc->hw.mac_type) {
case em_82571:
case em_82572:
case em_82573:
case em_82574:
	break;
default:
	return;
}

if (!pci_get_capability(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag,
   PCI_CAP_PCIEXPRESS0x10, &offset, NULL((void *)0)))
return;

/* Disable PCIe Active State Power Management (ASPM). */
val = pci_conf_read(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag,
   offset + PCI_PCIE_LCSR0x10);

switch (sc->hw.mac_type) {
case em_82571:
case em_82572:
	val &= ~PCI_PCIE_LCSR_ASPM_L10x00000002;
	break;
case em_82573:
case em_82574:
	val &= ~(PCI_PCIE_LCSR_ASPM_L0S0x00000001 |
	    PCI_PCIE_LCSR_ASPM_L10x00000002);
	break;
default:
	break;
}

pci_conf_write(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag,
   offset + PCI_PCIE_LCSR0x10, val);
3275}

3277/*
* em_flush_tx_ring - remove all descriptors from the tx_ring
*
* We want to clear all pending descriptors from the TX ring.
* zeroing happens when the HW reads the regs. We assign the ring itself as
* the data of the next descriptor. We don't care about the data we are about
* to reset the HW.
*/
3285void
3286em_flush_tx_ring(struct em_queue *que)
3287{
struct em_softc		*sc = que->sc;
uint32_t		 tctl, txd_lower = E1000_TXD_CMD_IFCS0x02000000;
uint16_t		 size = 512;
struct em_tx_desc	*txd;

KASSERT(que->tx.sc_tx_desc_ring != NULL)((que->tx.sc_tx_desc_ring != ((void *)0)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/if_em.c", 3293, "que->tx.sc_tx_desc_ring != NULL"
));

tctl = EM_READ_REG(&sc->hw, E1000_TCTL)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (0x00400)));
EM_WRITE_REG(&sc->hw, E1000_TCTL, tctl | E1000_TCTL_EN)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (0x00400), (tctl | 0x00000002)));

KASSERT(EM_READ_REG(&sc->hw, E1000_TDT(que->me)) == que->tx.sc_tx_desc_head)((((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((que->me) < 4 ? (0x03818 + ((que
->me) * 0x100)) : (0x0E018 + ((que->me) * 0x40)))))) ==
 que->tx.sc_tx_desc_head) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/if_em.c", 3298, "EM_READ_REG(&sc->hw, E1000_TDT(que->me)) == que->tx.sc_tx_desc_head"
));

txd = &que->tx.sc_tx_desc_ring[que->tx.sc_tx_desc_head];
txd->buffer_addr = que->tx.sc_tx_dma.dma_map->dm_segs[0].ds_addr;
txd->lower.data = htole32(txd_lower | size)((__uint32_t)(txd_lower | size));
txd->upper.data = 0;

/* flush descriptors to memory before notifying the HW */
bus_space_barrier(sc->osdep.mem_bus_space_tag,
   sc->osdep.mem_bus_space_handle, 0, 0, BUS_SPACE_BARRIER_WRITE0x02);

if (++que->tx.sc_tx_desc_head == sc->sc_tx_slots)
que->tx.sc_tx_desc_head = 0;

EM_WRITE_REG(&sc->hw, E1000_TDT(que->me), que->tx.sc_tx_desc_head)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((que->me) < 4 ? (0x03818 +
 ((que->me) * 0x100)) : (0x0E018 + ((que->me) * 0x40)))
), (que->tx.sc_tx_desc_head)));
bus_space_barrier(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle,
   0, 0, BUS_SPACE_BARRIER_READ0x01|BUS_SPACE_BARRIER_WRITE0x02);
usec_delay(250)(*delay_func)(250);
3316}

3318/*
* em_flush_rx_ring - remove all descriptors from the rx_ring
*
* Mark all descriptors in the RX ring as consumed and disable the rx ring
*/
3323void
3324em_flush_rx_ring(struct em_queue *que)
3325{
uint32_t	rctl, rxdctl;
struct em_softc	*sc = que->sc;

rctl = EM_READ_REG(&sc->hw, E1000_RCTL)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (0x00100)));
EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (0x00100), (rctl & ~0x00000002
)));
E1000_WRITE_FLUSH(&sc->hw)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00008 : em_translate_82542_register(0x00008)))));
usec_delay(150)(*delay_func)(150);

rxdctl = EM_READ_REG(&sc->hw, E1000_RXDCTL(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((que->me) < 4 ? (0x02828 + ((que
->me) * 0x100)) : (0x0C028 + ((que->me) * 0x40))))));
/* zero the lower 14 bits (prefetch and host thresholds) */
rxdctl &= 0xffffc000;
/*
* update thresholds: prefetch threshold to 31, host threshold to 1
* and make sure the granularity is "descriptors" and not "cache lines"
*/
rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC0x1000000);
EM_WRITE_REG(&sc->hw, E1000_RXDCTL(que->me), rxdctl)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((que->me) < 4 ? (0x02828 +
 ((que->me) * 0x100)) : (0x0C028 + ((que->me) * 0x40)))
), (rxdctl)));

/* momentarily enable the RX ring for the changes to take effect */
EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl | E1000_RCTL_EN)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (0x00100), (rctl | 0x00000002)));
E1000_WRITE_FLUSH(&sc->hw)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x00008 : em_translate_82542_register(0x00008)))));
usec_delay(150)(*delay_func)(150);
EM_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (0x00100), (rctl & ~0x00000002
)));
3349}

3351/*
* em_flush_desc_rings - remove all descriptors from the descriptor rings
*
* In i219, the descriptor rings must be emptied before resetting the HW
* or before changing the device state to D3 during runtime (runtime PM).
*
* Failure to do this will cause the HW to enter a unit hang state which can
* only be released by PCI reset on the device
*
*/
3361void
3362em_flush_desc_rings(struct em_softc *sc)
3363{
struct em_queue		*que = sc->queues; /* Use only first queue. */
struct pci_attach_args	*pa = &sc->osdep.em_pa;
uint32_t		 fextnvm11, tdlen;
uint16_t		 hang_state;

/* First, disable MULR fix in FEXTNVM11 */
fextnvm11 = EM_READ_REG(&sc->hw, E1000_FEXTNVM11)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (0x05bbc)));
fextnvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX0x00002000;
EM_WRITE_REG(&sc->hw, E1000_FEXTNVM11, fextnvm11)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (0x05bbc), (fextnvm11)));

/* do nothing if we're not in faulty state, or if the queue is empty */
tdlen = EM_READ_REG(&sc->hw, E1000_TDLEN(que->me))((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((que->me) < 4 ? (0x03808 + ((que
->me) * 0x100)) : (0x0E008 + ((que->me) * 0x40))))));
hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS0xe4);
if (!(hang_state & FLUSH_DESC_REQUIRED0x100) || !tdlen)
return;
em_flush_tx_ring(que);

/* recheck, maybe the fault is caused by the rx ring */
hang_state = pci_conf_read(pa->pa_pc, pa->pa_tag, PCICFG_DESC_RING_STATUS0xe4);
if (hang_state & FLUSH_DESC_REQUIRED0x100)
em_flush_rx_ring(que);
3385}

3387int
3388em_allocate_legacy(struct em_softc *sc)
3389{
pci_intr_handle_t	 ih;
const char		*intrstr = NULL((void *)0);
struct pci_attach_args	*pa = &sc->osdep.em_pa;
pci_chipset_tag_t	 pc = pa->pa_pc;

if (pci_intr_map_msi(pa, &ih)) {
if (pci_intr_map(pa, &ih)) {
	printf(": couldn't map interrupt\n");
	return (ENXIO6);
}
sc->legacy_irq = 1;
}

intrstr = pci_intr_string(pc, ih);
sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET0x7 | IPL_MPSAFE0x100,
   em_intr, sc, DEVNAME(sc)((sc)->sc_dev.dv_xname));
if (sc->sc_intrhand == NULL((void *)0)) {
printf(": couldn't establish interrupt");
if (intrstr != NULL((void *)0))
	printf(" at %s", intrstr);
printf("\n");
return (ENXIO6);
}
printf(": %s", intrstr);

return (0);
3416}

3418#if NKSTAT0 > 0
3419/* this is used to look up the array of kstats quickly */
3420enum em_stat {
em_stat_crcerrs,
em_stat_algnerrc,
em_stat_symerrs,
em_stat_rxerrc,
em_stat_mpc,
em_stat_scc,
em_stat_ecol,
em_stat_mcc,
em_stat_latecol,
em_stat_colc,
em_stat_dc,
em_stat_tncrs,
em_stat_sec,
em_stat_cexterr,
em_stat_rlec,
em_stat_xonrxc,
em_stat_xontxc,
em_stat_xoffrxc,
em_stat_xofftxc,
em_stat_fcruc,
em_stat_prc64,
em_stat_prc127,
em_stat_prc255,
em_stat_prc511,
em_stat_prc1023,
em_stat_prc1522,
em_stat_gprc,
em_stat_bprc,
em_stat_mprc,
em_stat_gptc,
em_stat_gorc,
em_stat_gotc,
em_stat_rnbc,
em_stat_ruc,
em_stat_rfc,
em_stat_roc,
em_stat_rjc,
em_stat_mgtprc,
em_stat_mgtpdc,
em_stat_mgtptc,
em_stat_tor,
em_stat_tot,
em_stat_tpr,
em_stat_tpt,
em_stat_ptc64,
em_stat_ptc127,
em_stat_ptc255,
em_stat_ptc511,
em_stat_ptc1023,
em_stat_ptc1522,
em_stat_mptc,
em_stat_bptc,
3473#if 0
em_stat_tsctc,
em_stat_tsctf,
3476#endif

em_stat_count,
3479};

3481struct em_counter {
const char		*name;
enum kstat_kv_unit	 unit;
uint32_t		 reg;
3485};

3487static const struct em_counter em_counters[em_stat_count] = {
[em_stat_crcerrs] =
   { "rx crc errs",	KSTAT_KV_U_PACKETS,	E1000_CRCERRS0x04000 },
[em_stat_algnerrc] = /* >= em_82543 */
   { "rx align errs",	KSTAT_KV_U_PACKETS,	0 },
[em_stat_symerrs] = /* >= em_82543 */
   { "rx align errs",	KSTAT_KV_U_PACKETS,	0 },
[em_stat_rxerrc] =
   { "rx errs",	KSTAT_KV_U_PACKETS,	E1000_RXERRC0x0400C },
[em_stat_mpc] =
   { "rx missed",	KSTAT_KV_U_PACKETS,	E1000_MPC0x04010 },
[em_stat_scc] =
   { "tx single coll",	KSTAT_KV_U_PACKETS,	E1000_SCC0x04014 },
[em_stat_ecol] =
   { "tx excess coll",	KSTAT_KV_U_PACKETS,	E1000_ECOL0x04018 },
[em_stat_mcc] =
   { "tx multi coll",	KSTAT_KV_U_PACKETS,	E1000_MCC0x0401C },
[em_stat_latecol] =
   { "tx late coll",	KSTAT_KV_U_PACKETS,	E1000_LATECOL0x04020 },
[em_stat_colc] =
   { "tx coll",	KSTAT_KV_U_NONE,	E1000_COLC0x04028 },
[em_stat_dc] =
   { "tx defers",	KSTAT_KV_U_NONE,	E1000_DC0x04030 },
[em_stat_tncrs] = /* >= em_82543 */
   { "tx no CRS",	KSTAT_KV_U_PACKETS,	0 },
[em_stat_sec] =
   { "seq errs",	KSTAT_KV_U_NONE,	E1000_SEC0x04038 },
[em_stat_cexterr] = /* >= em_82543 */
   { "carr ext errs",	KSTAT_KV_U_PACKETS,	0 },
[em_stat_rlec] =
   { "rx len errs",	KSTAT_KV_U_PACKETS,	E1000_RLEC0x04040 },
[em_stat_xonrxc] =
   { "rx xon",		KSTAT_KV_U_PACKETS,	E1000_XONRXC0x04048 },
[em_stat_xontxc] =
   { "tx xon",		KSTAT_KV_U_PACKETS,	E1000_XONTXC0x0404C },
[em_stat_xoffrxc] =
   { "rx xoff",	KSTAT_KV_U_PACKETS,	E1000_XOFFRXC0x04050 },
[em_stat_xofftxc] =
   { "tx xoff",	KSTAT_KV_U_PACKETS,	E1000_XOFFTXC0x04054 },
[em_stat_fcruc] =
   { "FC unsupported",	KSTAT_KV_U_PACKETS,	E1000_FCRUC0x04058 },
[em_stat_prc64] =
   { "rx 64B",		KSTAT_KV_U_PACKETS,	E1000_PRC640x0405C },
[em_stat_prc127] =
   { "rx 65-127B",	KSTAT_KV_U_PACKETS,	E1000_PRC1270x04060 },
[em_stat_prc255] =
   { "rx 128-255B",	KSTAT_KV_U_PACKETS,	E1000_PRC2550x04064 },
[em_stat_prc511] =
   { "rx 256-511B",	KSTAT_KV_U_PACKETS,	E1000_PRC5110x04068 },
[em_stat_prc1023] =
   { "rx 512-1023B",	KSTAT_KV_U_PACKETS,	E1000_PRC10230x0406C },
[em_stat_prc1522] =
   { "rx 1024-maxB",	KSTAT_KV_U_PACKETS,	E1000_PRC15220x04070 },
[em_stat_gprc] =
   { "rx good",	KSTAT_KV_U_PACKETS,	E1000_GPRC0x04074 },
[em_stat_bprc] =
   { "rx bcast",	KSTAT_KV_U_PACKETS,	E1000_BPRC0x04078 },
[em_stat_mprc] =
   { "rx mcast",	KSTAT_KV_U_PACKETS,	E1000_MPRC0x0407C },
[em_stat_gptc] =
   { "tx good",	KSTAT_KV_U_PACKETS,	E1000_GPTC0x04080 },
[em_stat_gorc] = /* 64bit */
   { "rx good",	KSTAT_KV_U_BYTES,	0 },
[em_stat_gotc] = /* 64bit */
   { "tx good",	KSTAT_KV_U_BYTES,	0 },
[em_stat_rnbc] =
   { "rx no buffers",	KSTAT_KV_U_PACKETS,	E1000_RNBC0x040A0 },
[em_stat_ruc] =
   { "rx undersize",	KSTAT_KV_U_PACKETS,	E1000_RUC0x040A4 },
[em_stat_rfc] =
   { "rx fragments",	KSTAT_KV_U_PACKETS,	E1000_RFC0x040A8 },
[em_stat_roc] =
   { "rx oversize",	KSTAT_KV_U_PACKETS,	E1000_ROC0x040AC },
[em_stat_rjc] =
   { "rx jabbers",	KSTAT_KV_U_PACKETS,	E1000_RJC0x040B0 },
[em_stat_mgtprc] =
   { "rx mgmt",	KSTAT_KV_U_PACKETS,	E1000_MGTPRC0x040B4 },
[em_stat_mgtpdc] =
   { "rx mgmt drops",	KSTAT_KV_U_PACKETS,	E1000_MGTPDC0x040B8 },
[em_stat_mgtptc] =
   { "tx mgmt",	KSTAT_KV_U_PACKETS,	E1000_MGTPTC0x040BC },
[em_stat_tor] = /* 64bit */
   { "rx total",	KSTAT_KV_U_BYTES,	0 },
[em_stat_tot] = /* 64bit */
   { "tx total",	KSTAT_KV_U_BYTES,	0 },
[em_stat_tpr] =
   { "rx total",	KSTAT_KV_U_PACKETS,	E1000_TPR0x040D0 },
[em_stat_tpt] =
   { "tx total",	KSTAT_KV_U_PACKETS,	E1000_TPT0x040D4 },
[em_stat_ptc64] =
   { "tx 64B",		KSTAT_KV_U_PACKETS,	E1000_PTC640x040D8 },
[em_stat_ptc127] =
   { "tx 65-127B",	KSTAT_KV_U_PACKETS,	E1000_PTC1270x040DC },
[em_stat_ptc255] =
   { "tx 128-255B",	KSTAT_KV_U_PACKETS,	E1000_PTC2550x040E0 },
[em_stat_ptc511] =
   { "tx 256-511B",	KSTAT_KV_U_PACKETS,	E1000_PTC5110x040E4 },
[em_stat_ptc1023] =
   { "tx 512-1023B",	KSTAT_KV_U_PACKETS,	E1000_PTC10230x040E8 },
[em_stat_ptc1522] =
   { "tx 1024-maxB",	KSTAT_KV_U_PACKETS,	E1000_PTC15220x040EC },
[em_stat_mptc] =
   { "tx mcast",	KSTAT_KV_U_PACKETS,	E1000_MPTC0x040F0 },
[em_stat_bptc] =
   { "tx bcast",	KSTAT_KV_U_PACKETS,	E1000_BPTC0x040F4 },
3592};

3594/**********************************************************************
*
*  Update the board statistics counters. 
*
**********************************************************************/
3599int
3600em_kstat_read(struct kstat *ks)
3601{
struct em_softc *sc = ks->ks_softc;
struct em_hw *hw = &sc->hw;
struct kstat_kv *kvs = ks->ks_data;
uint32_t lo, hi;
unsigned int i;

for (i = 0; i < nitems(em_counters)(sizeof((em_counters)) / sizeof((em_counters)[0])); i++) {
const struct em_counter *c = &em_counters[i];
if (c->reg == 0)
	continue;

kstat_kv_u64(&kvs[i])(&kvs[i])->kv_v.v_u64 += EM_READ_REG(hw,((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? c->reg : em_translate_82542_register
(c->reg)))))
    E1000_REG_TR(hw, c->reg))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? c->reg : em_translate_82542_register
(c->reg))))); /* wtf */
}

/* Handle the exceptions. */

if (sc->hw.mac_type >= em_82543) {
kstat_kv_u64(&kvs[em_stat_algnerrc])(&kvs[em_stat_algnerrc])->kv_v.v_u64 +=
    E1000_READ_REG(hw, ALGNERRC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04004 : em_translate_82542_register
(0x04004)))));
kstat_kv_u64(&kvs[em_stat_rxerrc])(&kvs[em_stat_rxerrc])->kv_v.v_u64 +=
    E1000_READ_REG(hw, RXERRC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0400C : em_translate_82542_register
(0x0400C)))));
kstat_kv_u64(&kvs[em_stat_cexterr])(&kvs[em_stat_cexterr])->kv_v.v_u64 +=
    E1000_READ_REG(hw, CEXTERR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0403C : em_translate_82542_register
(0x0403C)))));
kstat_kv_u64(&kvs[em_stat_tncrs])(&kvs[em_stat_tncrs])->kv_v.v_u64 +=
    E1000_READ_REG(hw, TNCRS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04034 : em_translate_82542_register
(0x04034)))));
3628#if 0
sc->stats.tsctc += 
E1000_READ_REG(hw, TSCTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040F8 : em_translate_82542_register
(0x040F8)))));
sc->stats.tsctfc += 
E1000_READ_REG(hw, TSCTFC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040FC : em_translate_82542_register
(0x040FC)))));
3633#endif
}

/* For the 64-bit byte counters the low dword must be read first. */
/* Both registers clear on the read of the high dword */

lo = E1000_READ_REG(hw, GORCL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04088 : em_translate_82542_register
(0x04088)))));
hi = E1000_READ_REG(hw, GORCH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0408C : em_translate_82542_register
(0x0408C)))));
kstat_kv_u64(&kvs[em_stat_gorc])(&kvs[em_stat_gorc])->kv_v.v_u64 +=
   ((uint64_t)hi << 32) | (uint64_t)lo;

lo = E1000_READ_REG(hw, GOTCL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04090 : em_translate_82542_register
(0x04090)))));
hi = E1000_READ_REG(hw, GOTCH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04094 : em_translate_82542_register
(0x04094)))));
kstat_kv_u64(&kvs[em_stat_gotc])(&kvs[em_stat_gotc])->kv_v.v_u64 +=
   ((uint64_t)hi << 32) | (uint64_t)lo;

lo = E1000_READ_REG(hw, TORL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040C0 : em_translate_82542_register
(0x040C0)))));
hi = E1000_READ_REG(hw, TORH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040C4 : em_translate_82542_register
(0x040C4)))));
kstat_kv_u64(&kvs[em_stat_tor])(&kvs[em_stat_tor])->kv_v.v_u64 +=
   ((uint64_t)hi << 32) | (uint64_t)lo;

lo = E1000_READ_REG(hw, TOTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040C8 : em_translate_82542_register
(0x040C8)))));
hi = E1000_READ_REG(hw, TOTH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040CC : em_translate_82542_register
(0x040CC)))));
kstat_kv_u64(&kvs[em_stat_tot])(&kvs[em_stat_tot])->kv_v.v_u64 +=
   ((uint64_t)hi << 32) | (uint64_t)lo;

getnanouptime(&ks->ks_updated);

return (0);
3662}

3664void
3665em_kstat_attach(struct em_softc *sc)
3666{
struct kstat *ks;
struct kstat_kv *kvs;
unsigned int i;

mtx_init(&sc->kstat_mtx, IPL_SOFTCLOCK)do { (void)(((void *)0)); (void)(0); __mtx_init((&sc->
kstat_mtx), ((((0x4)) > 0x0 && ((0x4)) < 0x9) ?
 0x9 : ((0x4)))); } while (0);

ks = kstat_create(DEVNAME(sc)((sc)->sc_dev.dv_xname), 0, "em-stats", 0,
   KSTAT_T_KV1, 0);
if (ks == NULL((void *)0))
return;

kvs = mallocarray(nitems(em_counters)(sizeof((em_counters)) / sizeof((em_counters)[0])), sizeof(*kvs),
   M_DEVBUF2, M_WAITOK0x0001|M_ZERO0x0008);
for (i = 0; i < nitems(em_counters)(sizeof((em_counters)) / sizeof((em_counters)[0])); i++) {
const struct em_counter *c = &em_counters[i];
kstat_kv_unit_init(&kvs[i], c->name,
    KSTAT_KV_T_COUNTER64, c->unit);
}

ks->ks_softc = sc;
ks->ks_data = kvs;
ks->ks_datalen = nitems(em_counters)(sizeof((em_counters)) / sizeof((em_counters)[0])) * sizeof(*kvs);
ks->ks_read = em_kstat_read;
kstat_set_mutex(ks, &sc->kstat_mtx);

kstat_install(ks);
3693}

3695/******************************************************************************
* Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
*****************************************************************************/
3698void
3699em_tbi_adjust_stats(struct em_softc *sc, uint32_t frame_len, uint8_t *mac_addr)
3700{
struct em_hw *hw = &sc->hw;
struct kstat *ks = sc->kstat;
struct kstat_kv *kvs;

if (ks == NULL((void *)0))
return;

/* First adjust the frame length. */
frame_len--;

mtx_enter(&sc->kstat_mtx);
kvs = ks->ks_data;

/*
* We need to adjust the statistics counters, since the hardware
* counters overcount this packet as a CRC error and undercount the
* packet as a good packet
*/

/* This packet should not be counted as a CRC error.	*/
kstat_kv_u64(&kvs[em_stat_crcerrs])(&kvs[em_stat_crcerrs])->kv_v.v_u64--;
/* This packet does count as a Good Packet Received.	*/
kstat_kv_u64(&kvs[em_stat_gprc])(&kvs[em_stat_gprc])->kv_v.v_u64++;

/* Adjust the Good Octets received counters		*/
kstat_kv_u64(&kvs[em_stat_gorc])(&kvs[em_stat_gorc])->kv_v.v_u64 += frame_len;

/*
* Is this a broadcast or multicast?  Check broadcast first, since
* the test for a multicast frame will test positive on a broadcast
* frame.
*/
if (ETHER_IS_BROADCAST(mac_addr)(((mac_addr)[0] & (mac_addr)[1] & (mac_addr)[2] &
 (mac_addr)[3] & (mac_addr)[4] & (mac_addr)[5]) == 0xff
)) {
/* Broadcast packet */
kstat_kv_u64(&kvs[em_stat_bprc])(&kvs[em_stat_bprc])->kv_v.v_u64++;
} else if (ETHER_IS_MULTICAST(mac_addr)(*(mac_addr) & 0x01)) { 
/* Multicast packet */
kstat_kv_u64(&kvs[em_stat_mprc])(&kvs[em_stat_mprc])->kv_v.v_u64++;
}

if (frame_len == hw->max_frame_size) {
/*
 * In this case, the hardware has overcounted the number of
 * oversize frames.
 */
kstat_kv_u64(&kvs[em_stat_roc])(&kvs[em_stat_roc])->kv_v.v_u64--;
}

/*
* Adjust the bin counters when the extra byte put the frame in the
* wrong bin. Remember that the frame_len was adjusted above.
*/
if (frame_len == 64) {
kstat_kv_u64(&kvs[em_stat_prc64])(&kvs[em_stat_prc64])->kv_v.v_u64++;
kstat_kv_u64(&kvs[em_stat_prc127])(&kvs[em_stat_prc127])->kv_v.v_u64--;
} else if (frame_len == 127) {
kstat_kv_u64(&kvs[em_stat_prc127])(&kvs[em_stat_prc127])->kv_v.v_u64++;
kstat_kv_u64(&kvs[em_stat_prc255])(&kvs[em_stat_prc255])->kv_v.v_u64--;
} else if (frame_len == 255) {
kstat_kv_u64(&kvs[em_stat_prc255])(&kvs[em_stat_prc255])->kv_v.v_u64++;
kstat_kv_u64(&kvs[em_stat_prc511])(&kvs[em_stat_prc511])->kv_v.v_u64--;
} else if (frame_len == 511) {
kstat_kv_u64(&kvs[em_stat_prc511])(&kvs[em_stat_prc511])->kv_v.v_u64++;
kstat_kv_u64(&kvs[em_stat_prc1023])(&kvs[em_stat_prc1023])->kv_v.v_u64--;
} else if (frame_len == 1023) {
kstat_kv_u64(&kvs[em_stat_prc1023])(&kvs[em_stat_prc1023])->kv_v.v_u64++;
kstat_kv_u64(&kvs[em_stat_prc1522])(&kvs[em_stat_prc1522])->kv_v.v_u64--;
} else if (frame_len == 1522) {
kstat_kv_u64(&kvs[em_stat_prc1522])(&kvs[em_stat_prc1522])->kv_v.v_u64++;
}

mtx_leave(&sc->kstat_mtx);
3773}
3774#endif /* NKSTAT > 0 */

3776#ifndef SMALL_KERNEL
3777int
3778em_allocate_msix(struct em_softc *sc)
3779{
pci_intr_handle_t	 ih;
const char		*intrstr = NULL((void *)0);
struct pci_attach_args	*pa = &sc->osdep.em_pa;
pci_chipset_tag_t	 pc = pa->pa_pc;
struct em_queue		*que = sc->queues; /* Use only first queue. */
int			 vec;

if (!em_enable_msix)
return (ENODEV19);

switch (sc->hw.mac_type) {
case em_82576:
case em_82580:
case em_i350:
case em_i210:
break;
default:
return (ENODEV19);
}

vec = 0;
if (pci_intr_map_msix(pa, vec, &ih))
return (ENODEV19);
sc->msix = 1;

que->me = vec;
que->eims = 1 << vec;
snprintf(que->name, sizeof(que->name), "%s:%d", DEVNAME(sc)((sc)->sc_dev.dv_xname), vec);

intrstr = pci_intr_string(pc, ih);
que->tag = pci_intr_establish(pc, ih, IPL_NET0x7 | IPL_MPSAFE0x100,
   em_queue_intr_msix, que, que->name);
if (que->tag == NULL((void *)0)) {
printf(": couldn't establish interrupt");
if (intrstr != NULL((void *)0))
	printf(" at %s", intrstr);
printf("\n");
return (ENXIO6);
}

/* Setup linkvector, use last queue vector + 1 */
vec++;
sc->msix_linkvec = vec;
if (pci_intr_map_msix(pa, sc->msix_linkvec, &ih)) {
printf(": couldn't map link vector\n");
return (ENXIO6);
}

intrstr = pci_intr_string(pc, ih);
sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET0x7 | IPL_MPSAFE0x100,
   em_link_intr_msix, sc, DEVNAME(sc)((sc)->sc_dev.dv_xname));
if (sc->sc_intrhand == NULL((void *)0)) {
printf(": couldn't establish interrupt");
if (intrstr != NULL((void *)0))
	printf(" at %s", intrstr);
printf("\n");
return (ENXIO6);
}
printf(", %s, %d queue%s", intrstr, vec, (vec > 1) ? "s" : "");

return (0);
3841}

3843/*
* Interrupt for a specific queue, (not link interrupts). The EICR bit which
* maps to the EIMS bit expresses both RX and TX, therefore we can't
* distinguish if this is a RX completion of TX completion and must do both.
* The bits in EICR are autocleared and we _cannot_ read EICR.
*/
3849int
3850em_queue_intr_msix(void *vque)
3851{
struct em_queue *que = vque;
struct em_softc *sc = que->sc;
struct ifnet   *ifp = &sc->sc_ac.ac_if;

if (ifp->if_flags & IFF_RUNNING0x40) {
em_txeof(que);
if (em_rxeof(que))
	em_rxrefill(que);
}

em_enable_queue_intr_msix(que);

return (1);
3865}

3867int
3868em_link_intr_msix(void *arg)
3869{
struct em_softc *sc = arg;
uint32_t icr;

icr = E1000_READ_REG(&sc->hw, ICR)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x000C0 : em_translate_82542_register(0x000C0)))));

/* Link status change */
if (icr & E1000_ICR_LSC0x00000004) {
KERNEL_LOCK()_kernel_lock();
sc->hw.get_link_status = 1;
em_check_for_link(&sc->hw);
em_update_link_status(sc);
KERNEL_UNLOCK()_kernel_unlock();
}

/* Re-arm unconditionally */
E1000_WRITE_REG(&sc->hw, IMS, E1000_ICR_LSC)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x000D0 : em_translate_82542_register(0x000D0))),
 (0x00000004)));
E1000_WRITE_REG(&sc->hw, EIMS, sc->msix_linkmask)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01524 : em_translate_82542_register(0x01524))),
 (sc->msix_linkmask)));

return (1);
3889}

3891/*
* Maps queues into msix interrupt vectors.
*/
3894int
3895em_setup_queues_msix(struct em_softc *sc)
3896{
uint32_t ivar, newitr, index;
struct em_queue *que;

KASSERT(sc->msix)((sc->msix) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_em.c"
, 3900, "sc->msix"));

/* First turn on RSS capability */
if (sc->hw.mac_type != em_82575)
E1000_WRITE_REG(&sc->hw, GPIE,((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01514 : em_translate_82542_register(0x01514))),
 (0x00000010 | 0x40000000 | 0x80000000 | 0x00000001)))
    E1000_GPIE_MSIX_MODE | E1000_GPIE_EIAME |((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01514 : em_translate_82542_register(0x01514))),
 (0x00000010 | 0x40000000 | 0x80000000 | 0x00000001)))
    E1000_GPIE_PBA | E1000_GPIE_NSICR)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01514 : em_translate_82542_register(0x01514))),
 (0x00000010 | 0x40000000 | 0x80000000 | 0x00000001)));

/* Turn on MSIX */
switch (sc->hw.mac_type) {
case em_82580:
case em_i350:
case em_i210:
/* RX entries */
/*
 * Note, this maps Queues into MSIX vectors, it works fine.
 * The funky calculation of offsets and checking if que->me is
 * odd is due to the weird register distribution, the datasheet
 * explains it well.
 */
FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
	index = que->me >> 1;
	ivar = E1000_READ_REG_ARRAY(&sc->hw, IVAR0, index)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x01700 : em_translate_82542_register(0x01700)) + ((index)
 << 2))));
	if (que->me & 1) {
		ivar &= 0xFF00FFFF;
		ivar |= (que->me | E1000_IVAR_VALID0x80) << 16;
	} else {
		ivar &= 0xFFFFFF00;
		ivar |= que->me | E1000_IVAR_VALID0x80;
	}
	E1000_WRITE_REG_ARRAY(&sc->hw, IVAR0, index, ivar)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01700 : em_translate_82542_register(0x01700)) +
 ((index) << 2)), (ivar)));
}

/* TX entries */
FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
	index = que->me >> 1;
	ivar = E1000_READ_REG_ARRAY(&sc->hw, IVAR0, index)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x01700 : em_translate_82542_register(0x01700)) + ((index)
 << 2))));
	if (que->me & 1) {
		ivar &= 0x00FFFFFF;
		ivar |= (que->me | E1000_IVAR_VALID0x80) << 24;
	} else {
		ivar &= 0xFFFF00FF;
		ivar |= (que->me | E1000_IVAR_VALID0x80) << 8;
	}
	E1000_WRITE_REG_ARRAY(&sc->hw, IVAR0, index, ivar)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01700 : em_translate_82542_register(0x01700)) +
 ((index) << 2)), (ivar)));
	sc->msix_queuesmask |= que->eims;
}

/* And for the link interrupt */
ivar = (sc->msix_linkvec | E1000_IVAR_VALID0x80) << 8;
sc->msix_linkmask = 1 << sc->msix_linkvec;
E1000_WRITE_REG(&sc->hw, IVAR_MISC, ivar)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01740 : em_translate_82542_register(0x01740))),
 (ivar)));
break;
case em_82576:
/* RX entries */
FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
	index = que->me & 0x7; /* Each IVAR has two entries */
	ivar = E1000_READ_REG_ARRAY(&sc->hw, IVAR0, index)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x01700 : em_translate_82542_register(0x01700)) + ((index)
 << 2))));
	if (que->me < 8) {
		ivar &= 0xFFFFFF00;
		ivar |= que->me | E1000_IVAR_VALID0x80;
	} else {
		ivar &= 0xFF00FFFF;
		ivar |= (que->me | E1000_IVAR_VALID0x80) << 16;
	}
	E1000_WRITE_REG_ARRAY(&sc->hw, IVAR0, index, ivar)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01700 : em_translate_82542_register(0x01700)) +
 ((index) << 2)), (ivar)));
	sc->msix_queuesmask |= que->eims;
}
/* TX entries */
FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
	index = que->me & 0x7; /* Each IVAR has two entries */
	ivar = E1000_READ_REG_ARRAY(&sc->hw, IVAR0, index)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->read_4((((struct em_osdep *)(&sc->hw)->back)->
mem_bus_space_handle), (((&sc->hw)->mac_type >= em_82543
 ? 0x01700 : em_translate_82542_register(0x01700)) + ((index)
 << 2))));
	if (que->me < 8) {
		ivar &= 0xFFFF00FF;
		ivar |= (que->me | E1000_IVAR_VALID0x80) << 8;
	} else {
		ivar &= 0x00FFFFFF;
		ivar |= (que->me | E1000_IVAR_VALID0x80) << 24;
	}
	E1000_WRITE_REG_ARRAY(&sc->hw, IVAR0, index, ivar)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01700 : em_translate_82542_register(0x01700)) +
 ((index) << 2)), (ivar)));
	sc->msix_queuesmask |= que->eims;
}

/* And for the link interrupt */
ivar = (sc->msix_linkvec | E1000_IVAR_VALID0x80) << 8;
sc->msix_linkmask = 1 << sc->msix_linkvec;
E1000_WRITE_REG(&sc->hw, IVAR_MISC, ivar)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? 0x01740 : em_translate_82542_register(0x01740))),
 (ivar)));
break;
default:
panic("unsupported mac");
break;
}

/* Set the starting interrupt rate */
newitr = (4000000 / MAX_INTS_PER_SEC8000) & 0x7FFC;

if (sc->hw.mac_type == em_82575)
newitr |= newitr << 16;
else
newitr |= E1000_EITR_CNT_IGNR0x80000000;

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++)
E1000_WRITE_REG(&sc->hw, EITR(que->me), newitr)((((struct em_osdep *)(&sc->hw)->back)->mem_bus_space_tag
)->write_4((((struct em_osdep *)(&sc->hw)->back)
->mem_bus_space_handle), (((&sc->hw)->mac_type >=
 em_82543 ? (0x01680 + (0x4 * (que->me))) : em_translate_82542_register
((0x01680 + (0x4 * (que->me)))))), (newitr)));

return (0);
4005}

4007void
4008em_enable_queue_intr_msix(struct em_queue *que)
4009{
E1000_WRITE_REG(&que->sc->hw, EIMS, que->eims)((((struct em_osdep *)(&que->sc->hw)->back)->
mem_bus_space_tag)->write_4((((struct em_osdep *)(&que
->sc->hw)->back)->mem_bus_space_handle), (((&
que->sc->hw)->mac_type >= em_82543 ? 0x01524 : em_translate_82542_register
(0x01524))), (que->eims)));
4011}
4012#endif /* !SMALL_KERNEL */

4014int
4015em_allocate_desc_rings(struct em_softc *sc)
4016{
struct em_queue *que;

FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
/* Allocate Transmit Descriptor ring */
if (em_dma_malloc(sc, sc->sc_tx_slots * sizeof(struct em_tx_desc),
    &que->tx.sc_tx_dma) != 0) {
	printf("%s: Unable to allocate tx_desc memory\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return (ENOMEM12);
}
que->tx.sc_tx_desc_ring =
    (struct em_tx_desc *)que->tx.sc_tx_dma.dma_vaddr;

/* Allocate Receive Descriptor ring */
if (em_dma_malloc(sc, sc->sc_rx_slots * sizeof(struct em_rx_desc),
    &que->rx.sc_rx_dma) != 0) {
	printf("%s: Unable to allocate rx_desc memory\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	return (ENOMEM12);
}
que->rx.sc_rx_desc_ring =
    (struct em_rx_desc *)que->rx.sc_rx_dma.dma_vaddr;
}

return (0);
4042}

4044int
4045em_get_sffpage(struct em_softc *sc, struct if_sffpage *sff)
4046{
struct em_hw *hw = &sc->hw;
size_t i;
int off;

if (hw->mac_type != em_82575 && hw->mac_type != em_82580 &&
   hw->mac_type != em_82576 &&
   hw->mac_type != em_i210 && hw->mac_type != em_i350)
return (ENODEV19);

if (sff->sff_addr == IFSFF_ADDR_EEPROM0xa0)
off = E1000_I2CCMD_SFP_DATA_ADDR(0)(0x0000 + (0));
else if (sff->sff_addr == IFSFF_ADDR_DDM0xa2)
off = E1000_I2CCMD_SFP_DIAG_ADDR(0)(0x0100 + (0));
else
return (EIO5);

for (i = 0; i < sizeof(sff->sff_data); i++) {
if (em_read_sfp_data_byte(hw, off + i,
    &sff->sff_data[i]) != E1000_SUCCESS0)
	return (EIO5);
}

return (0);
4070}