File: | dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c |
Warning: | line 3277, column 22 Access to field 'stream' results in a dereference of a null pointer (loaded from variable 'head_pipe') |
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1 | /* | |||
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |||
3 | * Copyright 2019 Raptor Engineering, LLC | |||
4 | * | |||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
6 | * copy of this software and associated documentation files (the "Software"), | |||
7 | * to deal in the Software without restriction, including without limitation | |||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
9 | * and/or sell copies of the Software, and to permit persons to whom the | |||
10 | * Software is furnished to do so, subject to the following conditions: | |||
11 | * | |||
12 | * The above copyright notice and this permission notice shall be included in | |||
13 | * all copies or substantial portions of the Software. | |||
14 | * | |||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
21 | * OTHER DEALINGS IN THE SOFTWARE. | |||
22 | * | |||
23 | * Authors: AMD | |||
24 | * | |||
25 | */ | |||
26 | ||||
27 | #include <linux/slab.h> | |||
28 | ||||
29 | #include "dm_services.h" | |||
30 | #include "dc.h" | |||
31 | ||||
32 | #include "dcn20_init.h" | |||
33 | ||||
34 | #include "resource.h" | |||
35 | #include "include/irq_service_interface.h" | |||
36 | #include "dcn20/dcn20_resource.h" | |||
37 | ||||
38 | #include "dcn10/dcn10_hubp.h" | |||
39 | #include "dcn10/dcn10_ipp.h" | |||
40 | #include "dcn20_hubbub.h" | |||
41 | #include "dcn20_mpc.h" | |||
42 | #include "dcn20_hubp.h" | |||
43 | #include "irq/dcn20/irq_service_dcn20.h" | |||
44 | #include "dcn20_dpp.h" | |||
45 | #include "dcn20_optc.h" | |||
46 | #include "dcn20_hwseq.h" | |||
47 | #include "dce110/dce110_hw_sequencer.h" | |||
48 | #include "dcn10/dcn10_resource.h" | |||
49 | #include "dcn20_opp.h" | |||
50 | ||||
51 | #include "dcn20_dsc.h" | |||
52 | ||||
53 | #include "dcn20_link_encoder.h" | |||
54 | #include "dcn20_stream_encoder.h" | |||
55 | #include "dce/dce_clock_source.h" | |||
56 | #include "dce/dce_audio.h" | |||
57 | #include "dce/dce_hwseq.h" | |||
58 | #include "virtual/virtual_stream_encoder.h" | |||
59 | #include "dce110/dce110_resource.h" | |||
60 | #include "dml/display_mode_vba.h" | |||
61 | #include "dcn20_dccg.h" | |||
62 | #include "dcn20_vmid.h" | |||
63 | #include "dc_link_ddc.h" | |||
64 | #include "dce/dce_panel_cntl.h" | |||
65 | ||||
66 | #include "navi10_ip_offset.h" | |||
67 | ||||
68 | #include "dcn/dcn_2_0_0_offset.h" | |||
69 | #include "dcn/dcn_2_0_0_sh_mask.h" | |||
70 | #include "dpcs/dpcs_2_0_0_offset.h" | |||
71 | #include "dpcs/dpcs_2_0_0_sh_mask.h" | |||
72 | ||||
73 | #include "nbio/nbio_2_3_offset.h" | |||
74 | ||||
75 | #include "dcn20/dcn20_dwb.h" | |||
76 | #include "dcn20/dcn20_mmhubbub.h" | |||
77 | ||||
78 | #include "mmhub/mmhub_2_0_0_offset.h" | |||
79 | #include "mmhub/mmhub_2_0_0_sh_mask.h" | |||
80 | ||||
81 | #include "reg_helper.h" | |||
82 | #include "dce/dce_abm.h" | |||
83 | #include "dce/dce_dmcu.h" | |||
84 | #include "dce/dce_aux.h" | |||
85 | #include "dce/dce_i2c.h" | |||
86 | #include "vm_helper.h" | |||
87 | ||||
88 | #include "amdgpu_socbb.h" | |||
89 | ||||
90 | #define DC_LOGGER_INIT(logger) | |||
91 | ||||
92 | struct _vcs_dpi_ip_params_st dcn2_0_ip = { | |||
93 | .odm_capable = 1, | |||
94 | .gpuvm_enable = 0, | |||
95 | .hostvm_enable = 0, | |||
96 | .gpuvm_max_page_table_levels = 4, | |||
97 | .hostvm_max_page_table_levels = 4, | |||
98 | .hostvm_cached_page_table_levels = 0, | |||
99 | .pte_group_size_bytes = 2048, | |||
100 | .num_dsc = 6, | |||
101 | .rob_buffer_size_kbytes = 168, | |||
102 | .det_buffer_size_kbytes = 164, | |||
103 | .dpte_buffer_size_in_pte_reqs_luma = 84, | |||
104 | .pde_proc_buffer_size_64k_reqs = 48, | |||
105 | .dpp_output_buffer_pixels = 2560, | |||
106 | .opp_output_buffer_lines = 1, | |||
107 | .pixel_chunk_size_kbytes = 8, | |||
108 | .pte_chunk_size_kbytes = 2, | |||
109 | .meta_chunk_size_kbytes = 2, | |||
110 | .writeback_chunk_size_kbytes = 2, | |||
111 | .line_buffer_size_bits = 789504, | |||
112 | .is_line_buffer_bpp_fixed = 0, | |||
113 | .line_buffer_fixed_bpp = 0, | |||
114 | .dcc_supported = true1, | |||
115 | .max_line_buffer_lines = 12, | |||
116 | .writeback_luma_buffer_size_kbytes = 12, | |||
117 | .writeback_chroma_buffer_size_kbytes = 8, | |||
118 | .writeback_chroma_line_buffer_width_pixels = 4, | |||
119 | .writeback_max_hscl_ratio = 1, | |||
120 | .writeback_max_vscl_ratio = 1, | |||
121 | .writeback_min_hscl_ratio = 1, | |||
122 | .writeback_min_vscl_ratio = 1, | |||
123 | .writeback_max_hscl_taps = 12, | |||
124 | .writeback_max_vscl_taps = 12, | |||
125 | .writeback_line_buffer_luma_buffer_size = 0, | |||
126 | .writeback_line_buffer_chroma_buffer_size = 14643, | |||
127 | .cursor_buffer_size = 8, | |||
128 | .cursor_chunk_size = 2, | |||
129 | .max_num_otg = 6, | |||
130 | .max_num_dpp = 6, | |||
131 | .max_num_wb = 1, | |||
132 | .max_dchub_pscl_bw_pix_per_clk = 4, | |||
133 | .max_pscl_lb_bw_pix_per_clk = 2, | |||
134 | .max_lb_vscl_bw_pix_per_clk = 4, | |||
135 | .max_vscl_hscl_bw_pix_per_clk = 4, | |||
136 | .max_hscl_ratio = 8, | |||
137 | .max_vscl_ratio = 8, | |||
138 | .hscl_mults = 4, | |||
139 | .vscl_mults = 4, | |||
140 | .max_hscl_taps = 8, | |||
141 | .max_vscl_taps = 8, | |||
142 | .dispclk_ramp_margin_percent = 1, | |||
143 | .underscan_factor = 1.10, | |||
144 | .min_vblank_lines = 32, // | |||
145 | .dppclk_delay_subtotal = 77, // | |||
146 | .dppclk_delay_scl_lb_only = 16, | |||
147 | .dppclk_delay_scl = 50, | |||
148 | .dppclk_delay_cnvc_formatter = 8, | |||
149 | .dppclk_delay_cnvc_cursor = 6, | |||
150 | .dispclk_delay_subtotal = 87, // | |||
151 | .dcfclk_cstate_latency = 10, // SRExitTime | |||
152 | .max_inter_dcn_tile_repeaters = 8, | |||
153 | .xfc_supported = true1, | |||
154 | .xfc_fill_bw_overhead_percent = 10.0, | |||
155 | .xfc_fill_constant_bytes = 0, | |||
156 | .number_of_cursors = 1, | |||
157 | }; | |||
158 | ||||
159 | static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = { | |||
160 | .odm_capable = 1, | |||
161 | .gpuvm_enable = 0, | |||
162 | .hostvm_enable = 0, | |||
163 | .gpuvm_max_page_table_levels = 4, | |||
164 | .hostvm_max_page_table_levels = 4, | |||
165 | .hostvm_cached_page_table_levels = 0, | |||
166 | .num_dsc = 5, | |||
167 | .rob_buffer_size_kbytes = 168, | |||
168 | .det_buffer_size_kbytes = 164, | |||
169 | .dpte_buffer_size_in_pte_reqs_luma = 84, | |||
170 | .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo | |||
171 | .dpp_output_buffer_pixels = 2560, | |||
172 | .opp_output_buffer_lines = 1, | |||
173 | .pixel_chunk_size_kbytes = 8, | |||
174 | .pte_enable = 1, | |||
175 | .max_page_table_levels = 4, | |||
176 | .pte_chunk_size_kbytes = 2, | |||
177 | .meta_chunk_size_kbytes = 2, | |||
178 | .writeback_chunk_size_kbytes = 2, | |||
179 | .line_buffer_size_bits = 789504, | |||
180 | .is_line_buffer_bpp_fixed = 0, | |||
181 | .line_buffer_fixed_bpp = 0, | |||
182 | .dcc_supported = true1, | |||
183 | .max_line_buffer_lines = 12, | |||
184 | .writeback_luma_buffer_size_kbytes = 12, | |||
185 | .writeback_chroma_buffer_size_kbytes = 8, | |||
186 | .writeback_chroma_line_buffer_width_pixels = 4, | |||
187 | .writeback_max_hscl_ratio = 1, | |||
188 | .writeback_max_vscl_ratio = 1, | |||
189 | .writeback_min_hscl_ratio = 1, | |||
190 | .writeback_min_vscl_ratio = 1, | |||
191 | .writeback_max_hscl_taps = 12, | |||
192 | .writeback_max_vscl_taps = 12, | |||
193 | .writeback_line_buffer_luma_buffer_size = 0, | |||
194 | .writeback_line_buffer_chroma_buffer_size = 14643, | |||
195 | .cursor_buffer_size = 8, | |||
196 | .cursor_chunk_size = 2, | |||
197 | .max_num_otg = 5, | |||
198 | .max_num_dpp = 5, | |||
199 | .max_num_wb = 1, | |||
200 | .max_dchub_pscl_bw_pix_per_clk = 4, | |||
201 | .max_pscl_lb_bw_pix_per_clk = 2, | |||
202 | .max_lb_vscl_bw_pix_per_clk = 4, | |||
203 | .max_vscl_hscl_bw_pix_per_clk = 4, | |||
204 | .max_hscl_ratio = 8, | |||
205 | .max_vscl_ratio = 8, | |||
206 | .hscl_mults = 4, | |||
207 | .vscl_mults = 4, | |||
208 | .max_hscl_taps = 8, | |||
209 | .max_vscl_taps = 8, | |||
210 | .dispclk_ramp_margin_percent = 1, | |||
211 | .underscan_factor = 1.10, | |||
212 | .min_vblank_lines = 32, // | |||
213 | .dppclk_delay_subtotal = 77, // | |||
214 | .dppclk_delay_scl_lb_only = 16, | |||
215 | .dppclk_delay_scl = 50, | |||
216 | .dppclk_delay_cnvc_formatter = 8, | |||
217 | .dppclk_delay_cnvc_cursor = 6, | |||
218 | .dispclk_delay_subtotal = 87, // | |||
219 | .dcfclk_cstate_latency = 10, // SRExitTime | |||
220 | .max_inter_dcn_tile_repeaters = 8, | |||
221 | .xfc_supported = true1, | |||
222 | .xfc_fill_bw_overhead_percent = 10.0, | |||
223 | .xfc_fill_constant_bytes = 0, | |||
224 | .ptoi_supported = 0, | |||
225 | .number_of_cursors = 1, | |||
226 | }; | |||
227 | ||||
228 | static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { | |||
229 | /* Defaults that get patched on driver load from firmware. */ | |||
230 | .clock_limits = { | |||
231 | { | |||
232 | .state = 0, | |||
233 | .dcfclk_mhz = 560.0, | |||
234 | .fabricclk_mhz = 560.0, | |||
235 | .dispclk_mhz = 513.0, | |||
236 | .dppclk_mhz = 513.0, | |||
237 | .phyclk_mhz = 540.0, | |||
238 | .socclk_mhz = 560.0, | |||
239 | .dscclk_mhz = 171.0, | |||
240 | .dram_speed_mts = 8960.0, | |||
241 | }, | |||
242 | { | |||
243 | .state = 1, | |||
244 | .dcfclk_mhz = 694.0, | |||
245 | .fabricclk_mhz = 694.0, | |||
246 | .dispclk_mhz = 642.0, | |||
247 | .dppclk_mhz = 642.0, | |||
248 | .phyclk_mhz = 600.0, | |||
249 | .socclk_mhz = 694.0, | |||
250 | .dscclk_mhz = 214.0, | |||
251 | .dram_speed_mts = 11104.0, | |||
252 | }, | |||
253 | { | |||
254 | .state = 2, | |||
255 | .dcfclk_mhz = 875.0, | |||
256 | .fabricclk_mhz = 875.0, | |||
257 | .dispclk_mhz = 734.0, | |||
258 | .dppclk_mhz = 734.0, | |||
259 | .phyclk_mhz = 810.0, | |||
260 | .socclk_mhz = 875.0, | |||
261 | .dscclk_mhz = 245.0, | |||
262 | .dram_speed_mts = 14000.0, | |||
263 | }, | |||
264 | { | |||
265 | .state = 3, | |||
266 | .dcfclk_mhz = 1000.0, | |||
267 | .fabricclk_mhz = 1000.0, | |||
268 | .dispclk_mhz = 1100.0, | |||
269 | .dppclk_mhz = 1100.0, | |||
270 | .phyclk_mhz = 810.0, | |||
271 | .socclk_mhz = 1000.0, | |||
272 | .dscclk_mhz = 367.0, | |||
273 | .dram_speed_mts = 16000.0, | |||
274 | }, | |||
275 | { | |||
276 | .state = 4, | |||
277 | .dcfclk_mhz = 1200.0, | |||
278 | .fabricclk_mhz = 1200.0, | |||
279 | .dispclk_mhz = 1284.0, | |||
280 | .dppclk_mhz = 1284.0, | |||
281 | .phyclk_mhz = 810.0, | |||
282 | .socclk_mhz = 1200.0, | |||
283 | .dscclk_mhz = 428.0, | |||
284 | .dram_speed_mts = 16000.0, | |||
285 | }, | |||
286 | /*Extra state, no dispclk ramping*/ | |||
287 | { | |||
288 | .state = 5, | |||
289 | .dcfclk_mhz = 1200.0, | |||
290 | .fabricclk_mhz = 1200.0, | |||
291 | .dispclk_mhz = 1284.0, | |||
292 | .dppclk_mhz = 1284.0, | |||
293 | .phyclk_mhz = 810.0, | |||
294 | .socclk_mhz = 1200.0, | |||
295 | .dscclk_mhz = 428.0, | |||
296 | .dram_speed_mts = 16000.0, | |||
297 | }, | |||
298 | }, | |||
299 | .num_states = 5, | |||
300 | .sr_exit_time_us = 8.6, | |||
301 | .sr_enter_plus_exit_time_us = 10.9, | |||
302 | .urgent_latency_us = 4.0, | |||
303 | .urgent_latency_pixel_data_only_us = 4.0, | |||
304 | .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, | |||
305 | .urgent_latency_vm_data_only_us = 4.0, | |||
306 | .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, | |||
307 | .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, | |||
308 | .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, | |||
309 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, | |||
310 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, | |||
311 | .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, | |||
312 | .max_avg_sdp_bw_use_normal_percent = 40.0, | |||
313 | .max_avg_dram_bw_use_normal_percent = 40.0, | |||
314 | .writeback_latency_us = 12.0, | |||
315 | .ideal_dram_bw_after_urgent_percent = 40.0, | |||
316 | .max_request_size_bytes = 256, | |||
317 | .dram_channel_width_bytes = 2, | |||
318 | .fabric_datapath_to_dcn_data_return_bytes = 64, | |||
319 | .dcn_downspread_percent = 0.5, | |||
320 | .downspread_percent = 0.38, | |||
321 | .dram_page_open_time_ns = 50.0, | |||
322 | .dram_rw_turnaround_time_ns = 17.5, | |||
323 | .dram_return_buffer_per_channel_bytes = 8192, | |||
324 | .round_trip_ping_latency_dcfclk_cycles = 131, | |||
325 | .urgent_out_of_order_return_per_channel_bytes = 256, | |||
326 | .channel_interleave_bytes = 256, | |||
327 | .num_banks = 8, | |||
328 | .num_chans = 16, | |||
329 | .vmm_page_size_bytes = 4096, | |||
330 | .dram_clock_change_latency_us = 404.0, | |||
331 | .dummy_pstate_latency_us = 5.0, | |||
332 | .writeback_dram_clock_change_latency_us = 23.0, | |||
333 | .return_bus_width_bytes = 64, | |||
334 | .dispclk_dppclk_vco_speed_mhz = 3850, | |||
335 | .xfc_bus_transport_time_us = 20, | |||
336 | .xfc_xbuf_latency_tolerance_us = 4, | |||
337 | .use_urgent_burst_bw = 0 | |||
338 | }; | |||
339 | ||||
340 | static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = { | |||
341 | .clock_limits = { | |||
342 | { | |||
343 | .state = 0, | |||
344 | .dcfclk_mhz = 560.0, | |||
345 | .fabricclk_mhz = 560.0, | |||
346 | .dispclk_mhz = 513.0, | |||
347 | .dppclk_mhz = 513.0, | |||
348 | .phyclk_mhz = 540.0, | |||
349 | .socclk_mhz = 560.0, | |||
350 | .dscclk_mhz = 171.0, | |||
351 | .dram_speed_mts = 8960.0, | |||
352 | }, | |||
353 | { | |||
354 | .state = 1, | |||
355 | .dcfclk_mhz = 694.0, | |||
356 | .fabricclk_mhz = 694.0, | |||
357 | .dispclk_mhz = 642.0, | |||
358 | .dppclk_mhz = 642.0, | |||
359 | .phyclk_mhz = 600.0, | |||
360 | .socclk_mhz = 694.0, | |||
361 | .dscclk_mhz = 214.0, | |||
362 | .dram_speed_mts = 11104.0, | |||
363 | }, | |||
364 | { | |||
365 | .state = 2, | |||
366 | .dcfclk_mhz = 875.0, | |||
367 | .fabricclk_mhz = 875.0, | |||
368 | .dispclk_mhz = 734.0, | |||
369 | .dppclk_mhz = 734.0, | |||
370 | .phyclk_mhz = 810.0, | |||
371 | .socclk_mhz = 875.0, | |||
372 | .dscclk_mhz = 245.0, | |||
373 | .dram_speed_mts = 14000.0, | |||
374 | }, | |||
375 | { | |||
376 | .state = 3, | |||
377 | .dcfclk_mhz = 1000.0, | |||
378 | .fabricclk_mhz = 1000.0, | |||
379 | .dispclk_mhz = 1100.0, | |||
380 | .dppclk_mhz = 1100.0, | |||
381 | .phyclk_mhz = 810.0, | |||
382 | .socclk_mhz = 1000.0, | |||
383 | .dscclk_mhz = 367.0, | |||
384 | .dram_speed_mts = 16000.0, | |||
385 | }, | |||
386 | { | |||
387 | .state = 4, | |||
388 | .dcfclk_mhz = 1200.0, | |||
389 | .fabricclk_mhz = 1200.0, | |||
390 | .dispclk_mhz = 1284.0, | |||
391 | .dppclk_mhz = 1284.0, | |||
392 | .phyclk_mhz = 810.0, | |||
393 | .socclk_mhz = 1200.0, | |||
394 | .dscclk_mhz = 428.0, | |||
395 | .dram_speed_mts = 16000.0, | |||
396 | }, | |||
397 | /*Extra state, no dispclk ramping*/ | |||
398 | { | |||
399 | .state = 5, | |||
400 | .dcfclk_mhz = 1200.0, | |||
401 | .fabricclk_mhz = 1200.0, | |||
402 | .dispclk_mhz = 1284.0, | |||
403 | .dppclk_mhz = 1284.0, | |||
404 | .phyclk_mhz = 810.0, | |||
405 | .socclk_mhz = 1200.0, | |||
406 | .dscclk_mhz = 428.0, | |||
407 | .dram_speed_mts = 16000.0, | |||
408 | }, | |||
409 | }, | |||
410 | .num_states = 5, | |||
411 | .sr_exit_time_us = 8.6, | |||
412 | .sr_enter_plus_exit_time_us = 10.9, | |||
413 | .urgent_latency_us = 4.0, | |||
414 | .urgent_latency_pixel_data_only_us = 4.0, | |||
415 | .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, | |||
416 | .urgent_latency_vm_data_only_us = 4.0, | |||
417 | .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, | |||
418 | .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, | |||
419 | .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, | |||
420 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0, | |||
421 | .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0, | |||
422 | .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, | |||
423 | .max_avg_sdp_bw_use_normal_percent = 40.0, | |||
424 | .max_avg_dram_bw_use_normal_percent = 40.0, | |||
425 | .writeback_latency_us = 12.0, | |||
426 | .ideal_dram_bw_after_urgent_percent = 40.0, | |||
427 | .max_request_size_bytes = 256, | |||
428 | .dram_channel_width_bytes = 2, | |||
429 | .fabric_datapath_to_dcn_data_return_bytes = 64, | |||
430 | .dcn_downspread_percent = 0.5, | |||
431 | .downspread_percent = 0.38, | |||
432 | .dram_page_open_time_ns = 50.0, | |||
433 | .dram_rw_turnaround_time_ns = 17.5, | |||
434 | .dram_return_buffer_per_channel_bytes = 8192, | |||
435 | .round_trip_ping_latency_dcfclk_cycles = 131, | |||
436 | .urgent_out_of_order_return_per_channel_bytes = 256, | |||
437 | .channel_interleave_bytes = 256, | |||
438 | .num_banks = 8, | |||
439 | .num_chans = 8, | |||
440 | .vmm_page_size_bytes = 4096, | |||
441 | .dram_clock_change_latency_us = 404.0, | |||
442 | .dummy_pstate_latency_us = 5.0, | |||
443 | .writeback_dram_clock_change_latency_us = 23.0, | |||
444 | .return_bus_width_bytes = 64, | |||
445 | .dispclk_dppclk_vco_speed_mhz = 3850, | |||
446 | .xfc_bus_transport_time_us = 20, | |||
447 | .xfc_xbuf_latency_tolerance_us = 4, | |||
448 | .use_urgent_burst_bw = 0 | |||
449 | }; | |||
450 | ||||
451 | static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 }; | |||
452 | ||||
453 | #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL0x210f | |||
454 | #define mmDP0_DP_DPHY_INTERNAL_CTRL0x210f 0x210f | |||
455 | #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX2 2 | |||
456 | #define mmDP1_DP_DPHY_INTERNAL_CTRL0x220f 0x220f | |||
457 | #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX2 2 | |||
458 | #define mmDP2_DP_DPHY_INTERNAL_CTRL0x230f 0x230f | |||
459 | #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX2 2 | |||
460 | #define mmDP3_DP_DPHY_INTERNAL_CTRL0x240f 0x240f | |||
461 | #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX2 2 | |||
462 | #define mmDP4_DP_DPHY_INTERNAL_CTRL0x250f 0x250f | |||
463 | #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX2 2 | |||
464 | #define mmDP5_DP_DPHY_INTERNAL_CTRL0x260f 0x260f | |||
465 | #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX2 2 | |||
466 | #define mmDP6_DP_DPHY_INTERNAL_CTRL0x270f 0x270f | |||
467 | #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX2 2 | |||
468 | #endif | |||
469 | ||||
470 | ||||
471 | enum dcn20_clk_src_array_id { | |||
472 | DCN20_CLK_SRC_PLL0, | |||
473 | DCN20_CLK_SRC_PLL1, | |||
474 | DCN20_CLK_SRC_PLL2, | |||
475 | DCN20_CLK_SRC_PLL3, | |||
476 | DCN20_CLK_SRC_PLL4, | |||
477 | DCN20_CLK_SRC_PLL5, | |||
478 | DCN20_CLK_SRC_TOTAL | |||
479 | }; | |||
480 | ||||
481 | /* begin ********************* | |||
482 | * macros to expend register list macro defined in HW object header file */ | |||
483 | ||||
484 | /* DCN */ | |||
485 | /* TODO awful hack. fixup dcn20_dwb.h */ | |||
486 | #undef BASE_INNER | |||
487 | #define BASE_INNER(seg)DCN_BASE__INST0_SEGseg DCN_BASE__INST0_SEG ## seg | |||
488 | ||||
489 | #define BASE(seg)DCN_BASE__INST0_SEGseg BASE_INNER(seg)DCN_BASE__INST0_SEGseg | |||
490 | ||||
491 | #define SR(reg_name).reg_name = DCN_BASE__INST0_SEGmmreg_name_BASE_IDX + mmreg_name\ | |||
492 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## reg_name ## _BASE_IDX + \ | |||
493 | mm ## reg_name | |||
494 | ||||
495 | #define SRI(reg_name, block, id).reg_name = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX + mmblockid_reg_name\ | |||
496 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | |||
497 | mm ## block ## id ## _ ## reg_name | |||
498 | ||||
499 | #define SRIR(var_name, reg_name, block, id).var_name = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX + mmblockid_reg_name\ | |||
500 | .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | |||
501 | mm ## block ## id ## _ ## reg_name | |||
502 | ||||
503 | #define SRII(reg_name, block, id).reg_name[id] = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX + mmblockid_reg_name\ | |||
504 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | |||
505 | mm ## block ## id ## _ ## reg_name | |||
506 | ||||
507 | #define DCCG_SRII(reg_name, block, id).block_reg_name[id] = DCN_BASE__INST0_SEGmmblockid_reg_name_BASE_IDX + mmblockid_reg_name\ | |||
508 | .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## block ## id ## _ ## reg_name ## _BASE_IDX + \ | |||
509 | mm ## block ## id ## _ ## reg_name | |||
510 | ||||
511 | #define VUPDATE_SRII(reg_name, block, id).reg_name[id] = DCN_BASE__INST0_SEGmmreg_name_blockid_BASE_IDX + mmreg_name_blockid\ | |||
512 | .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX)DCN_BASE__INST0_SEGmm ## reg_name ## _ ## block ## id ## _BASE_IDX + \ | |||
513 | mm ## reg_name ## _ ## block ## id | |||
514 | ||||
515 | /* NBIO */ | |||
516 | #define NBIO_BASE_INNER(seg)NBIO_BASE__INST0_SEGseg \ | |||
517 | NBIO_BASE__INST0_SEG ## seg | |||
518 | ||||
519 | #define NBIO_BASE(seg)NBIO_BASE__INST0_SEGseg \ | |||
520 | NBIO_BASE_INNER(seg)NBIO_BASE__INST0_SEGseg | |||
521 | ||||
522 | #define NBIO_SR(reg_name).reg_name = NBIO_BASE__INST0_SEGmmreg_name_BASE_IDX + mmreg_name\ | |||
523 | .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX)NBIO_BASE__INST0_SEGmm ## reg_name ## _BASE_IDX + \ | |||
524 | mm ## reg_name | |||
525 | ||||
526 | /* MMHUB */ | |||
527 | #define MMHUB_BASE_INNER(seg)MMHUB_BASE__INST0_SEGseg \ | |||
528 | MMHUB_BASE__INST0_SEG ## seg | |||
529 | ||||
530 | #define MMHUB_BASE(seg)MMHUB_BASE__INST0_SEGseg \ | |||
531 | MMHUB_BASE_INNER(seg)MMHUB_BASE__INST0_SEGseg | |||
532 | ||||
533 | #define MMHUB_SR(reg_name).reg_name = MMHUB_BASE__INST0_SEGmmMMreg_name_BASE_IDX + mmMMreg_name\ | |||
534 | .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX)MMHUB_BASE__INST0_SEGmmMM ## reg_name ## _BASE_IDX + \ | |||
535 | mmMM ## reg_name | |||
536 | ||||
537 | static const struct bios_registers bios_regs = { | |||
538 | NBIO_SR(BIOS_SCRATCH_3).BIOS_SCRATCH_3 = 0x00000014 + 0x003b, | |||
539 | NBIO_SR(BIOS_SCRATCH_6).BIOS_SCRATCH_6 = 0x00000014 + 0x003e | |||
540 | }; | |||
541 | ||||
542 | #define clk_src_regs(index, pllid)[index] = { .PIXCLK_RESYNC_CNTL = DCN_BASE__INST0_SEGmmPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX + mmPHYPLLpllid_PIXCLK_RESYNC_CNTL, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL [0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,}\ | |||
543 | [index] = {\ | |||
544 | CS_COMMON_REG_LIST_DCN2_0(index, pllid).PIXCLK_RESYNC_CNTL = DCN_BASE__INST0_SEGmmPHYPLLpllid_PIXCLK_RESYNC_CNTL_BASE_IDX + mmPHYPLLpllid_PIXCLK_RESYNC_CNTL, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE[2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, .PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095, .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL [0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL [3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL[4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,\ | |||
545 | } | |||
546 | ||||
547 | static const struct dce110_clk_src_regs clk_src_regs[] = { | |||
548 | clk_src_regs(0, A)[0] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0040, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095 , .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL [4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,}, | |||
549 | clk_src_regs(1, B)[1] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0041, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095 , .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL [4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,}, | |||
550 | clk_src_regs(2, C)[2] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0042, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095 , .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL [4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,}, | |||
551 | clk_src_regs(3, D)[3] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x0043, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095 , .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL [4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,}, | |||
552 | clk_src_regs(4, E)[4] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x004c, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095 , .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL [4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,}, | |||
553 | clk_src_regs(5, F)[5] = { .PIXCLK_RESYNC_CNTL = 0x000000C0 + 0x007e, .PHASE[0] = 0x000000C0 + 0x0081, .PHASE[1] = 0x000000C0 + 0x0085, .PHASE [2] = 0x000000C0 + 0x0089, .PHASE[3] = 0x000000C0 + 0x008d, . PHASE[4] = 0x000000C0 + 0x0091, .PHASE[5] = 0x000000C0 + 0x0095 , .MODULO[0] = 0x000000C0 + 0x0082, .MODULO[1] = 0x000000C0 + 0x0086, .MODULO[2] = 0x000000C0 + 0x008a, .MODULO[3] = 0x000000C0 + 0x008e, .MODULO[4] = 0x000000C0 + 0x0092, .MODULO[5] = 0x000000C0 + 0x0096, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PIXEL_RATE_CNTL [4] = 0x000000C0 + 0x0090, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094,} | |||
554 | }; | |||
555 | ||||
556 | static const struct dce110_clk_src_shift cs_shift = { | |||
557 | CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT).DP_DTO0_PHASE = 0x0, .DP_DTO0_MODULO = 0x0, .PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x4, .DP_DTO0_ENABLE = 0x4 | |||
558 | }; | |||
559 | ||||
560 | static const struct dce110_clk_src_mask cs_mask = { | |||
561 | CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK).DP_DTO0_PHASE = 0xFFFFFFFFL, .DP_DTO0_MODULO = 0xFFFFFFFFL, . PHYPLLA_DCCG_DEEP_COLOR_CNTL = 0x00000030L, .DP_DTO0_ENABLE = 0x00000010L | |||
562 | }; | |||
563 | ||||
564 | static const struct dce_dmcu_registers dmcu_regs = { | |||
565 | DMCU_DCN10_REG_LIST().DMCU_CTRL = 0x000034C0 + 0x00da, .DMCU_STATUS = 0x000034C0 + 0x00db, .DMCU_RAM_ACCESS_CTRL = 0x000034C0 + 0x00e2, .DMCU_IRAM_WR_CTRL = 0x000034C0 + 0x00e7, .DMCU_IRAM_WR_DATA = 0x000034C0 + 0x00e8 , .MASTER_COMM_DATA_REG1 = 0x000034C0 + 0x00f9, .MASTER_COMM_DATA_REG2 = 0x000034C0 + 0x00fa, .MASTER_COMM_DATA_REG3 = 0x000034C0 + 0x00fb, .MASTER_COMM_CMD_REG = 0x000034C0 + 0x00fc, .MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .DMCU_IRAM_RD_CTRL = 0x000034C0 + 0x00e9 , .DMCU_IRAM_RD_DATA = 0x000034C0 + 0x00ea, .DMCU_INTERRUPT_TO_UC_EN_MASK = 0x000034C0 + 0x00f1, .SMU_INTERRUPT_CONTROL = 0x000034C0 + 0x00ce, .DC_DMCU_SCRATCH = 0x000034C0 + 0x00f5, .DMU_MEM_PWR_CNTL = 0x000034C0 + 0x00cc | |||
566 | }; | |||
567 | ||||
568 | static const struct dce_dmcu_shift dmcu_shift = { | |||
569 | DMCU_MASK_SH_LIST_DCN10(__SHIFT).DMCU_ENABLE = 0x4, .UC_IN_STOP_MODE = 0x2, .UC_IN_RESET = 0x0 , .IRAM_HOST_ACCESS_EN = 0x5, .IRAM_WR_ADDR_AUTO_INC = 0x2, . IRAM_RD_ADDR_AUTO_INC = 0x3, .MASTER_COMM_CMD_REG_BYTE0 = 0x0 , .MASTER_COMM_INTERRUPT = 0x0, .STATIC_SCREEN1_INT_TO_UC_EN = 0x6, .STATIC_SCREEN2_INT_TO_UC_EN = 0x7, .STATIC_SCREEN3_INT_TO_UC_EN = 0x9, .STATIC_SCREEN4_INT_TO_UC_EN = 0xa, .DC_SMU_INT_ENABLE = 0x0, .DMCU_IRAM_MEM_PWR_STATE = 0xa | |||
570 | }; | |||
571 | ||||
572 | static const struct dce_dmcu_mask dmcu_mask = { | |||
573 | DMCU_MASK_SH_LIST_DCN10(_MASK).DMCU_ENABLE = 0x00000010L, .UC_IN_STOP_MODE = 0x00000004L, . UC_IN_RESET = 0x00000001L, .IRAM_HOST_ACCESS_EN = 0x00000020L , .IRAM_WR_ADDR_AUTO_INC = 0x00000004L, .IRAM_RD_ADDR_AUTO_INC = 0x00000008L, .MASTER_COMM_CMD_REG_BYTE0 = 0x000000FFL, .MASTER_COMM_INTERRUPT = 0x00000001L, .STATIC_SCREEN1_INT_TO_UC_EN = 0x00000040L, . STATIC_SCREEN2_INT_TO_UC_EN = 0x00000080L, .STATIC_SCREEN3_INT_TO_UC_EN = 0x00000200L, .STATIC_SCREEN4_INT_TO_UC_EN = 0x00000400L, . DC_SMU_INT_ENABLE = 0x00000001L, .DMCU_IRAM_MEM_PWR_STATE = 0x00000400L | |||
574 | }; | |||
575 | ||||
576 | static const struct dce_abm_registers abm_regs = { | |||
577 | ABM_DCN20_REG_LIST().MASTER_COMM_CNTL_REG = 0x000034C0 + 0x00fd, .MASTER_COMM_CMD_REG = 0x000034C0 + 0x00fc, .MASTER_COMM_DATA_REG1 = 0x000034C0 + 0x00f9, .DC_ABM1_HG_SAMPLE_RATE = 0x000034C0 + 0x17cd, .DC_ABM1_LS_SAMPLE_RATE = 0x000034C0 + 0x17ce, .BL1_PWM_BL_UPDATE_SAMPLE_RATE = 0x000034C0 + 0x17b7, .DC_ABM1_HG_MISC_CTRL = 0x000034C0 + 0x17c5, .DC_ABM1_IPCSC_COEFF_SEL = 0x000034C0 + 0x17ba, .BL1_PWM_CURRENT_ABM_LEVEL = 0x000034C0 + 0x17b3, .BL1_PWM_TARGET_ABM_LEVEL = 0x000034C0 + 0x17b2, . BL1_PWM_USER_LEVEL = 0x000034C0 + 0x17b1, .DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES = 0x000034C0 + 0x17ca, .DC_ABM1_HGLS_REG_READ_PROGRESS = 0x000034C0 + 0x17c4, .DC_ABM1_ACE_OFFSET_SLOPE_0 = 0x000034C0 + 0x17bb, .DC_ABM1_ACE_THRES_12 = 0x000034C0 + 0x17c0, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a | |||
578 | }; | |||
579 | ||||
580 | static const struct dce_abm_shift abm_shift = { | |||
581 | ABM_MASK_SH_LIST_DCN20(__SHIFT).MASTER_COMM_INTERRUPT = 0x0, .MASTER_COMM_CMD_REG_BYTE0 = 0x0 , .MASTER_COMM_CMD_REG_BYTE1 = 0x8, .MASTER_COMM_CMD_REG_BYTE2 = 0x10, .ABM1_HG_NUM_OF_BINS_SEL = 0x0, .ABM1_HG_VMAX_SEL = 0x8 , .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x10, .ABM1_IPCSC_COEFF_SEL_R = 0x10, .ABM1_IPCSC_COEFF_SEL_G = 0x8, .ABM1_IPCSC_COEFF_SEL_B = 0x0, .BL1_PWM_CURRENT_ABM_LEVEL = 0x0, .BL1_PWM_TARGET_ABM_LEVEL = 0x0, .BL1_PWM_USER_LEVEL = 0x0, .ABM1_LS_MIN_PIXEL_VALUE_THRES = 0x0, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x10, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR = 0x10, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x18, .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR = 0x1f | |||
582 | }; | |||
583 | ||||
584 | static const struct dce_abm_mask abm_mask = { | |||
585 | ABM_MASK_SH_LIST_DCN20(_MASK).MASTER_COMM_INTERRUPT = 0x00000001L, .MASTER_COMM_CMD_REG_BYTE0 = 0x000000FFL, .MASTER_COMM_CMD_REG_BYTE1 = 0x0000FF00L, .MASTER_COMM_CMD_REG_BYTE2 = 0x00FF0000L, .ABM1_HG_NUM_OF_BINS_SEL = 0x00000003L, .ABM1_HG_VMAX_SEL = 0x00000100L, .ABM1_HG_BIN_BITWIDTH_SIZE_SEL = 0x00030000L, .ABM1_IPCSC_COEFF_SEL_R = 0x000F0000L, .ABM1_IPCSC_COEFF_SEL_G = 0x00000F00L, .ABM1_IPCSC_COEFF_SEL_B = 0x0000000FL, .BL1_PWM_CURRENT_ABM_LEVEL = 0x0001FFFFL, .BL1_PWM_TARGET_ABM_LEVEL = 0x0001FFFFL, .BL1_PWM_USER_LEVEL = 0x0001FFFFL, .ABM1_LS_MIN_PIXEL_VALUE_THRES = 0x000003FFL, .ABM1_LS_MAX_PIXEL_VALUE_THRES = 0x03FF0000L, .ABM1_HG_REG_READ_MISSED_FRAME_CLEAR = 0x00010000L, .ABM1_LS_REG_READ_MISSED_FRAME_CLEAR = 0x01000000L , .ABM1_BL_REG_READ_MISSED_FRAME_CLEAR = 0x80000000L | |||
586 | }; | |||
587 | ||||
588 | #define audio_regs(id)[id] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = DCN_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX + mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, .AZALIA_F0_CODEC_ENDPOINT_DATA = DCN_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX + mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}\ | |||
589 | [id] = {\ | |||
590 | AUD_COMMON_REG_LIST(id).AZALIA_F0_CODEC_ENDPOINT_INDEX = DCN_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX + mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_INDEX, .AZALIA_F0_CODEC_ENDPOINT_DATA = DCN_BASE__INST0_SEGmmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX + mmAZF0ENDPOINTid_AZALIA_F0_CODEC_ENDPOINT_DATA, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae\ | |||
591 | } | |||
592 | ||||
593 | static const struct dce_audio_registers audio_regs[] = { | |||
594 | audio_regs(0)[0] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0386 , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0387, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | |||
595 | audio_regs(1)[1] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x038c , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x038d, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | |||
596 | audio_regs(2)[2] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0392 , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0393, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | |||
597 | audio_regs(3)[3] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x0398 , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x0399, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | |||
598 | audio_regs(4)[4] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x039e , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x039f, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | |||
599 | audio_regs(5)[5] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x03a4 , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x03a5, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | |||
600 | audio_regs(6)[6] = { .AZALIA_F0_CODEC_ENDPOINT_INDEX = 0x000034C0 + 0x03aa , .AZALIA_F0_CODEC_ENDPOINT_DATA = 0x000034C0 + 0x03ab, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS = 0x000034C0 + 0x040c, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES = 0x000034C0 + 0x040b, .AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES = 0x000034C0 + 0x040d, .DCCG_AUDIO_DTO_SOURCE = 0x000000C0 + 0x00ab, .DCCG_AUDIO_DTO0_MODULE = 0x000000C0 + 0x00ad, .DCCG_AUDIO_DTO0_PHASE = 0x000000C0 + 0x00ac, .DCCG_AUDIO_DTO1_MODULE = 0x000000C0 + 0x00af, .DCCG_AUDIO_DTO1_PHASE = 0x000000C0 + 0x00ae}, | |||
601 | }; | |||
602 | ||||
603 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh , .AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh , .DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh , .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh , .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh , .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh , .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh , .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh , .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh , .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh , .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh\ | |||
604 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh).AZALIA_ENDPOINT_REG_INDEX = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEXmask_sh,\ | |||
605 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh).AZALIA_ENDPOINT_REG_DATA = AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATAmask_sh,\ | |||
606 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh).DCCG_AUDIO_DTO0_SOURCE_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SELmask_sh , .DCCG_AUDIO_DTO_SEL = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SELmask_sh , .DCCG_AUDIO_DTO2_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO1_USE_512FBR_DTO = DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTOmask_sh , .DCCG_AUDIO_DTO0_MODULE = DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULEmask_sh , .DCCG_AUDIO_DTO0_PHASE = DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASEmask_sh , .DCCG_AUDIO_DTO1_MODULE = DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULEmask_sh , .DCCG_AUDIO_DTO1_PHASE = DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASEmask_sh , .AUDIO_RATE_CAPABILITIES = AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIESmask_sh , .CLKSTOP = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOPmask_sh , .EPSS = AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSSmask_sh | |||
607 | ||||
608 | static const struct dce_audio_shift audio_shift = { | |||
609 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT).AZALIA_ENDPOINT_REG_INDEX = 0x0, .AZALIA_ENDPOINT_REG_DATA = 0x0, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x0, .DCCG_AUDIO_DTO_SEL = 0x4, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x14, .DCCG_AUDIO_DTO0_USE_512FBR_DTO = 0x18, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x1c, .DCCG_AUDIO_DTO0_MODULE = 0x0, .DCCG_AUDIO_DTO0_PHASE = 0x0, .DCCG_AUDIO_DTO1_MODULE = 0x0, .DCCG_AUDIO_DTO1_PHASE = 0x0, .AUDIO_RATE_CAPABILITIES = 0x0, .CLKSTOP = 0x1e, .EPSS = 0x1f | |||
610 | }; | |||
611 | ||||
612 | static const struct dce_audio_mask audio_mask = { | |||
613 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK).AZALIA_ENDPOINT_REG_INDEX = 0x00003FFFL, .AZALIA_ENDPOINT_REG_DATA = 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_SOURCE_SEL = 0x00000007L, .DCCG_AUDIO_DTO_SEL = 0x00000030L, .DCCG_AUDIO_DTO2_USE_512FBR_DTO = 0x00100000L , .DCCG_AUDIO_DTO0_USE_512FBR_DTO = 0x01000000L, .DCCG_AUDIO_DTO1_USE_512FBR_DTO = 0x10000000L, .DCCG_AUDIO_DTO0_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO0_PHASE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_MODULE = 0xFFFFFFFFL, .DCCG_AUDIO_DTO1_PHASE = 0xFFFFFFFFL, .AUDIO_RATE_CAPABILITIES = 0x00000FFFL, .CLKSTOP = 0x40000000L, .EPSS = 0x80000000L | |||
614 | }; | |||
615 | ||||
616 | #define stream_enc_regs(id)[id] = { .AFMT_CNTL = DCN_BASE__INST0_SEGmmDIGid_AFMT_CNTL_BASE_IDX + mmDIGid_AFMT_CNTL, .AFMT_GENERIC_0 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_0_BASE_IDX + mmDIGid_AFMT_GENERIC_0, .AFMT_GENERIC_1 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_1_BASE_IDX + mmDIGid_AFMT_GENERIC_1, .AFMT_GENERIC_2 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_2_BASE_IDX + mmDIGid_AFMT_GENERIC_2, .AFMT_GENERIC_3 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_3_BASE_IDX + mmDIGid_AFMT_GENERIC_3, .AFMT_GENERIC_4 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_4_BASE_IDX + mmDIGid_AFMT_GENERIC_4, .AFMT_GENERIC_5 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_5_BASE_IDX + mmDIGid_AFMT_GENERIC_5, .AFMT_GENERIC_6 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_6_BASE_IDX + mmDIGid_AFMT_GENERIC_6, .AFMT_GENERIC_7 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_7_BASE_IDX + mmDIGid_AFMT_GENERIC_7, .AFMT_GENERIC_HDR = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_HDR_BASE_IDX + mmDIGid_AFMT_GENERIC_HDR, .AFMT_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGmmDIGid_AFMT_INFOFRAME_CONTROL0_BASE_IDX + mmDIGid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_AFMT_VBI_PACKET_CONTROL_BASE_IDX + mmDIGid_AFMT_VBI_PACKET_CONTROL, .AFMT_VBI_PACKET_CONTROL1 = DCN_BASE__INST0_SEGmmDIGid_AFMT_VBI_PACKET_CONTROL1_BASE_IDX + mmDIGid_AFMT_VBI_PACKET_CONTROL1, .AFMT_AUDIO_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX + mmDIGid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2 = DCN_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX + mmDIGid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL = DCN_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX + mmDIGid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = DCN_BASE__INST0_SEGmmDIGid_AFMT_60958_0_BASE_IDX + mmDIGid_AFMT_60958_0, .AFMT_60958_1 = DCN_BASE__INST0_SEGmmDIGid_AFMT_60958_1_BASE_IDX + mmDIGid_AFMT_60958_1, .AFMT_60958_2 = DCN_BASE__INST0_SEGmmDIGid_AFMT_60958_2_BASE_IDX + mmDIGid_AFMT_60958_2, .DIG_FE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_FE_CNTL_BASE_IDX + mmDIGid_DIG_FE_CNTL, .HDMI_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_CONTROL_BASE_IDX + mmDIGid_HDMI_CONTROL, .HDMI_DB_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_DB_CONTROL_BASE_IDX + mmDIGid_HDMI_DB_CONTROL, .HDMI_GC = DCN_BASE__INST0_SEGmmDIGid_HDMI_GC_BASE_IDX + mmDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_GENERIC_PACKET_CONTROL2 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL2, .HDMI_GENERIC_PACKET_CONTROL3 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL3, .HDMI_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX + mmDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX + mmDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX + mmDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX + mmDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX + mmDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_0_BASE_IDX + mmDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_1_BASE_IDX + mmDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_0_BASE_IDX + mmDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_1_BASE_IDX + mmDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_0_BASE_IDX + mmDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_1_BASE_IDX + mmDIGid_HDMI_ACR_48_1, .DP_DB_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DB_CNTL_BASE_IDX + mmDPid_DP_DB_CNTL, .DP_MSA_MISC = DCN_BASE__INST0_SEGmmDPid_DP_MSA_MISC_BASE_IDX + mmDPid_DP_MSA_MISC, .DP_MSA_COLORIMETRY = DCN_BASE__INST0_SEGmmDPid_DP_MSA_COLORIMETRY_BASE_IDX + mmDPid_DP_MSA_COLORIMETRY, .DP_MSA_TIMING_PARAM1 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM1_BASE_IDX + mmDPid_DP_MSA_TIMING_PARAM1, .DP_MSA_TIMING_PARAM2 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM2_BASE_IDX + mmDPid_DP_MSA_TIMING_PARAM2, .DP_MSA_TIMING_PARAM3 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM3_BASE_IDX + mmDPid_DP_MSA_TIMING_PARAM3, .DP_MSA_TIMING_PARAM4 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM4_BASE_IDX + mmDPid_DP_MSA_TIMING_PARAM4, .DP_MSE_RATE_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_MSE_RATE_CNTL_BASE_IDX + mmDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE = DCN_BASE__INST0_SEGmmDPid_DP_MSE_RATE_UPDATE_BASE_IDX + mmDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmDPid_DP_PIXEL_FORMAT_BASE_IDX + mmDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX + mmDPid_DP_SEC_CNTL, .DP_SEC_CNTL2 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL2_BASE_IDX + mmDPid_DP_SEC_CNTL2, .DP_SEC_CNTL6 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL6_BASE_IDX + mmDPid_DP_SEC_CNTL6, .DP_STEER_FIFO = DCN_BASE__INST0_SEGmmDPid_DP_STEER_FIFO_BASE_IDX + mmDPid_DP_STEER_FIFO, .DP_VID_M = DCN_BASE__INST0_SEGmmDPid_DP_VID_M_BASE_IDX + mmDPid_DP_VID_M, .DP_VID_N = DCN_BASE__INST0_SEGmmDPid_DP_VID_N_BASE_IDX + mmDPid_DP_VID_N, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX + mmDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING = DCN_BASE__INST0_SEGmmDPid_DP_VID_TIMING_BASE_IDX + mmDPid_DP_VID_TIMING, .DP_SEC_AUD_N = DCN_BASE__INST0_SEGmmDPid_DP_SEC_AUD_N_BASE_IDX + mmDPid_DP_SEC_AUD_N, .DP_SEC_TIMESTAMP = DCN_BASE__INST0_SEGmmDPid_DP_SEC_TIMESTAMP_BASE_IDX + mmDPid_DP_SEC_TIMESTAMP, .DIG_CLOCK_PATTERN = DCN_BASE__INST0_SEGmmDIGid_DIG_CLOCK_PATTERN_BASE_IDX + mmDIGid_DIG_CLOCK_PATTERN, .HDMI_GENERIC_PACKET_CONTROL4 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL4, .HDMI_GENERIC_PACKET_CONTROL5 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL5, .DP_DSC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DSC_CNTL_BASE_IDX + mmDPid_DP_DSC_CNTL, .DP_DSC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGmmDPid_DP_DSC_BYTES_PER_PIXEL_BASE_IDX + mmDPid_DP_DSC_BYTES_PER_PIXEL, .DME_CONTROL = DCN_BASE__INST0_SEGmmDIGid_DME_CONTROL_BASE_IDX + mmDIGid_DME_CONTROL, .DP_SEC_METADATA_TRANSMISSION = DCN_BASE__INST0_SEGmmDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX + mmDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX + mmDIGid_HDMI_METADATA_PACKET_CONTROL, .DP_SEC_FRAMING4 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_FRAMING4_BASE_IDX + mmDPid_DP_SEC_FRAMING4}\ | |||
617 | [id] = {\ | |||
618 | SE_DCN2_REG_LIST(id).AFMT_CNTL = DCN_BASE__INST0_SEGmmDIGid_AFMT_CNTL_BASE_IDX + mmDIGid_AFMT_CNTL , .AFMT_GENERIC_0 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_0_BASE_IDX + mmDIGid_AFMT_GENERIC_0, .AFMT_GENERIC_1 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_1_BASE_IDX + mmDIGid_AFMT_GENERIC_1, .AFMT_GENERIC_2 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_2_BASE_IDX + mmDIGid_AFMT_GENERIC_2, .AFMT_GENERIC_3 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_3_BASE_IDX + mmDIGid_AFMT_GENERIC_3, .AFMT_GENERIC_4 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_4_BASE_IDX + mmDIGid_AFMT_GENERIC_4, .AFMT_GENERIC_5 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_5_BASE_IDX + mmDIGid_AFMT_GENERIC_5, .AFMT_GENERIC_6 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_6_BASE_IDX + mmDIGid_AFMT_GENERIC_6, .AFMT_GENERIC_7 = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_7_BASE_IDX + mmDIGid_AFMT_GENERIC_7, .AFMT_GENERIC_HDR = DCN_BASE__INST0_SEGmmDIGid_AFMT_GENERIC_HDR_BASE_IDX + mmDIGid_AFMT_GENERIC_HDR, .AFMT_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGmmDIGid_AFMT_INFOFRAME_CONTROL0_BASE_IDX + mmDIGid_AFMT_INFOFRAME_CONTROL0, .AFMT_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_AFMT_VBI_PACKET_CONTROL_BASE_IDX + mmDIGid_AFMT_VBI_PACKET_CONTROL, .AFMT_VBI_PACKET_CONTROL1 = DCN_BASE__INST0_SEGmmDIGid_AFMT_VBI_PACKET_CONTROL1_BASE_IDX + mmDIGid_AFMT_VBI_PACKET_CONTROL1, .AFMT_AUDIO_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX + mmDIGid_AFMT_AUDIO_PACKET_CONTROL, .AFMT_AUDIO_PACKET_CONTROL2 = DCN_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX + mmDIGid_AFMT_AUDIO_PACKET_CONTROL2, .AFMT_AUDIO_SRC_CONTROL = DCN_BASE__INST0_SEGmmDIGid_AFMT_AUDIO_SRC_CONTROL_BASE_IDX + mmDIGid_AFMT_AUDIO_SRC_CONTROL, .AFMT_60958_0 = DCN_BASE__INST0_SEGmmDIGid_AFMT_60958_0_BASE_IDX + mmDIGid_AFMT_60958_0, .AFMT_60958_1 = DCN_BASE__INST0_SEGmmDIGid_AFMT_60958_1_BASE_IDX + mmDIGid_AFMT_60958_1, .AFMT_60958_2 = DCN_BASE__INST0_SEGmmDIGid_AFMT_60958_2_BASE_IDX + mmDIGid_AFMT_60958_2, .DIG_FE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_FE_CNTL_BASE_IDX + mmDIGid_DIG_FE_CNTL, .HDMI_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_CONTROL_BASE_IDX + mmDIGid_HDMI_CONTROL, .HDMI_DB_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_DB_CONTROL_BASE_IDX + mmDIGid_HDMI_DB_CONTROL, .HDMI_GC = DCN_BASE__INST0_SEGmmDIGid_HDMI_GC_BASE_IDX + mmDIGid_HDMI_GC, .HDMI_GENERIC_PACKET_CONTROL0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL0, .HDMI_GENERIC_PACKET_CONTROL1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL1, .HDMI_GENERIC_PACKET_CONTROL2 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL2, .HDMI_GENERIC_PACKET_CONTROL3 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL3, .HDMI_INFOFRAME_CONTROL0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL0_BASE_IDX + mmDIGid_HDMI_INFOFRAME_CONTROL0, .HDMI_INFOFRAME_CONTROL1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_INFOFRAME_CONTROL1_BASE_IDX + mmDIGid_HDMI_INFOFRAME_CONTROL1, .HDMI_VBI_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_VBI_PACKET_CONTROL_BASE_IDX + mmDIGid_HDMI_VBI_PACKET_CONTROL, .HDMI_AUDIO_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX + mmDIGid_HDMI_AUDIO_PACKET_CONTROL, .HDMI_ACR_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_PACKET_CONTROL_BASE_IDX + mmDIGid_HDMI_ACR_PACKET_CONTROL, .HDMI_ACR_32_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_0_BASE_IDX + mmDIGid_HDMI_ACR_32_0, .HDMI_ACR_32_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_32_1_BASE_IDX + mmDIGid_HDMI_ACR_32_1, .HDMI_ACR_44_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_0_BASE_IDX + mmDIGid_HDMI_ACR_44_0, .HDMI_ACR_44_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_44_1_BASE_IDX + mmDIGid_HDMI_ACR_44_1, .HDMI_ACR_48_0 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_0_BASE_IDX + mmDIGid_HDMI_ACR_48_0, .HDMI_ACR_48_1 = DCN_BASE__INST0_SEGmmDIGid_HDMI_ACR_48_1_BASE_IDX + mmDIGid_HDMI_ACR_48_1, .DP_DB_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DB_CNTL_BASE_IDX + mmDPid_DP_DB_CNTL, .DP_MSA_MISC = DCN_BASE__INST0_SEGmmDPid_DP_MSA_MISC_BASE_IDX + mmDPid_DP_MSA_MISC, .DP_MSA_COLORIMETRY = DCN_BASE__INST0_SEGmmDPid_DP_MSA_COLORIMETRY_BASE_IDX + mmDPid_DP_MSA_COLORIMETRY, .DP_MSA_TIMING_PARAM1 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM1_BASE_IDX + mmDPid_DP_MSA_TIMING_PARAM1, .DP_MSA_TIMING_PARAM2 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM2_BASE_IDX + mmDPid_DP_MSA_TIMING_PARAM2, .DP_MSA_TIMING_PARAM3 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM3_BASE_IDX + mmDPid_DP_MSA_TIMING_PARAM3, .DP_MSA_TIMING_PARAM4 = DCN_BASE__INST0_SEGmmDPid_DP_MSA_TIMING_PARAM4_BASE_IDX + mmDPid_DP_MSA_TIMING_PARAM4, .DP_MSE_RATE_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_MSE_RATE_CNTL_BASE_IDX + mmDPid_DP_MSE_RATE_CNTL, .DP_MSE_RATE_UPDATE = DCN_BASE__INST0_SEGmmDPid_DP_MSE_RATE_UPDATE_BASE_IDX + mmDPid_DP_MSE_RATE_UPDATE, .DP_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmDPid_DP_PIXEL_FORMAT_BASE_IDX + mmDPid_DP_PIXEL_FORMAT, .DP_SEC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX + mmDPid_DP_SEC_CNTL, .DP_SEC_CNTL2 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL2_BASE_IDX + mmDPid_DP_SEC_CNTL2, .DP_SEC_CNTL6 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL6_BASE_IDX + mmDPid_DP_SEC_CNTL6, .DP_STEER_FIFO = DCN_BASE__INST0_SEGmmDPid_DP_STEER_FIFO_BASE_IDX + mmDPid_DP_STEER_FIFO, .DP_VID_M = DCN_BASE__INST0_SEGmmDPid_DP_VID_M_BASE_IDX + mmDPid_DP_VID_M, .DP_VID_N = DCN_BASE__INST0_SEGmmDPid_DP_VID_N_BASE_IDX + mmDPid_DP_VID_N, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX + mmDPid_DP_VID_STREAM_CNTL, .DP_VID_TIMING = DCN_BASE__INST0_SEGmmDPid_DP_VID_TIMING_BASE_IDX + mmDPid_DP_VID_TIMING, .DP_SEC_AUD_N = DCN_BASE__INST0_SEGmmDPid_DP_SEC_AUD_N_BASE_IDX + mmDPid_DP_SEC_AUD_N, .DP_SEC_TIMESTAMP = DCN_BASE__INST0_SEGmmDPid_DP_SEC_TIMESTAMP_BASE_IDX + mmDPid_DP_SEC_TIMESTAMP, .DIG_CLOCK_PATTERN = DCN_BASE__INST0_SEGmmDIGid_DIG_CLOCK_PATTERN_BASE_IDX + mmDIGid_DIG_CLOCK_PATTERN, .HDMI_GENERIC_PACKET_CONTROL4 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL4, .HDMI_GENERIC_PACKET_CONTROL5 = DCN_BASE__INST0_SEGmmDIGid_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX + mmDIGid_HDMI_GENERIC_PACKET_CONTROL5, .DP_DSC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DSC_CNTL_BASE_IDX + mmDPid_DP_DSC_CNTL, .DP_DSC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGmmDPid_DP_DSC_BYTES_PER_PIXEL_BASE_IDX + mmDPid_DP_DSC_BYTES_PER_PIXEL, .DME_CONTROL = DCN_BASE__INST0_SEGmmDIGid_DME_CONTROL_BASE_IDX + mmDIGid_DME_CONTROL, .DP_SEC_METADATA_TRANSMISSION = DCN_BASE__INST0_SEGmmDPid_DP_SEC_METADATA_TRANSMISSION_BASE_IDX + mmDPid_DP_SEC_METADATA_TRANSMISSION, .HDMI_METADATA_PACKET_CONTROL = DCN_BASE__INST0_SEGmmDIGid_HDMI_METADATA_PACKET_CONTROL_BASE_IDX + mmDIGid_HDMI_METADATA_PACKET_CONTROL, .DP_SEC_FRAMING4 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_FRAMING4_BASE_IDX + mmDPid_DP_SEC_FRAMING4\ | |||
619 | } | |||
620 | ||||
621 | static const struct dcn10_stream_enc_registers stream_enc_regs[] = { | |||
622 | stream_enc_regs(0)[0] = { .AFMT_CNTL = 0x000034C0 + 0x20e6, .AFMT_GENERIC_0 = 0x000034C0 + 0x208d, .AFMT_GENERIC_1 = 0x000034C0 + 0x208e, .AFMT_GENERIC_2 = 0x000034C0 + 0x208f, .AFMT_GENERIC_3 = 0x000034C0 + 0x2090 , .AFMT_GENERIC_4 = 0x000034C0 + 0x2091, .AFMT_GENERIC_5 = 0x000034C0 + 0x2092, .AFMT_GENERIC_6 = 0x000034C0 + 0x2093, .AFMT_GENERIC_7 = 0x000034C0 + 0x2094, .AFMT_GENERIC_HDR = 0x000034C0 + 0x208c , .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x20ac, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x20ab, .AFMT_VBI_PACKET_CONTROL1 = 0x000034C0 + 0x20e7, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x20aa, . AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x207c, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x20ad, .AFMT_60958_0 = 0x000034C0 + 0x20a0, . AFMT_60958_1 = 0x000034C0 + 0x20a1, .AFMT_60958_2 = 0x000034C0 + 0x20a7, .DIG_FE_CNTL = 0x000034C0 + 0x2068, .HDMI_CONTROL = 0x000034C0 + 0x2071, .HDMI_DB_CONTROL = 0x000034C0 + 0x2088, .HDMI_GC = 0x000034C0 + 0x207b, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x2078, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x2095, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x2086 , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x2087, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2076, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2077, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2075, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2073, .HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2074, .HDMI_ACR_32_0 = 0x000034C0 + 0x2096, .HDMI_ACR_32_1 = 0x000034C0 + 0x2097, .HDMI_ACR_44_0 = 0x000034C0 + 0x2098, .HDMI_ACR_44_1 = 0x000034C0 + 0x2099, .HDMI_ACR_48_0 = 0x000034C0 + 0x209a, .HDMI_ACR_48_1 = 0x000034C0 + 0x209b, .DP_DB_CNTL = 0x000034C0 + 0x2159, .DP_MSA_MISC = 0x000034C0 + 0x210e, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x210a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x214c , .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x214d, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x214e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x214f , .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2137, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2139, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2109 , .DP_SEC_CNTL = 0x000034C0 + 0x212b, .DP_SEC_CNTL2 = 0x000034C0 + 0x2153, .DP_SEC_CNTL6 = 0x000034C0 + 0x2157, .DP_STEER_FIFO = 0x000034C0 + 0x210d, .DP_VID_M = 0x000034C0 + 0x2112, .DP_VID_N = 0x000034C0 + 0x2111, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x210c , .DP_VID_TIMING = 0x000034C0 + 0x2110, .DP_SEC_AUD_N = 0x000034C0 + 0x2131, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2135, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x206b, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x2070, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x20f6 , .DP_DSC_CNTL = 0x000034C0 + 0x2152, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x215c, .DME_CONTROL = 0x000034C0 + 0x2089, . DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x215b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x206f, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2130 }, | |||
623 | stream_enc_regs(1)[1] = { .AFMT_CNTL = 0x000034C0 + 0x21e6, .AFMT_GENERIC_0 = 0x000034C0 + 0x218d, .AFMT_GENERIC_1 = 0x000034C0 + 0x218e, .AFMT_GENERIC_2 = 0x000034C0 + 0x218f, .AFMT_GENERIC_3 = 0x000034C0 + 0x2190 , .AFMT_GENERIC_4 = 0x000034C0 + 0x2191, .AFMT_GENERIC_5 = 0x000034C0 + 0x2192, .AFMT_GENERIC_6 = 0x000034C0 + 0x2193, .AFMT_GENERIC_7 = 0x000034C0 + 0x2194, .AFMT_GENERIC_HDR = 0x000034C0 + 0x218c , .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x21ac, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x21ab, .AFMT_VBI_PACKET_CONTROL1 = 0x000034C0 + 0x21e7, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x21aa, . AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x217c, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x21ad, .AFMT_60958_0 = 0x000034C0 + 0x21a0, . AFMT_60958_1 = 0x000034C0 + 0x21a1, .AFMT_60958_2 = 0x000034C0 + 0x21a7, .DIG_FE_CNTL = 0x000034C0 + 0x2168, .HDMI_CONTROL = 0x000034C0 + 0x2171, .HDMI_DB_CONTROL = 0x000034C0 + 0x2188, .HDMI_GC = 0x000034C0 + 0x217b, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x2178, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x2195, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x2186 , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x2187, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2176, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2177, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2175, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2173, .HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2174, .HDMI_ACR_32_0 = 0x000034C0 + 0x2196, .HDMI_ACR_32_1 = 0x000034C0 + 0x2197, .HDMI_ACR_44_0 = 0x000034C0 + 0x2198, .HDMI_ACR_44_1 = 0x000034C0 + 0x2199, .HDMI_ACR_48_0 = 0x000034C0 + 0x219a, .HDMI_ACR_48_1 = 0x000034C0 + 0x219b, .DP_DB_CNTL = 0x000034C0 + 0x2259, .DP_MSA_MISC = 0x000034C0 + 0x220e, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x220a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x224c , .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x224d, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x224e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x224f , .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2237, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2239, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2209 , .DP_SEC_CNTL = 0x000034C0 + 0x222b, .DP_SEC_CNTL2 = 0x000034C0 + 0x2253, .DP_SEC_CNTL6 = 0x000034C0 + 0x2257, .DP_STEER_FIFO = 0x000034C0 + 0x220d, .DP_VID_M = 0x000034C0 + 0x2212, .DP_VID_N = 0x000034C0 + 0x2211, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x220c , .DP_VID_TIMING = 0x000034C0 + 0x2210, .DP_SEC_AUD_N = 0x000034C0 + 0x2231, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2235, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x216b, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x2170, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x21f6 , .DP_DSC_CNTL = 0x000034C0 + 0x2252, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x225c, .DME_CONTROL = 0x000034C0 + 0x2189, . DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x225b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x216f, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2230 }, | |||
624 | stream_enc_regs(2)[2] = { .AFMT_CNTL = 0x000034C0 + 0x22e6, .AFMT_GENERIC_0 = 0x000034C0 + 0x228d, .AFMT_GENERIC_1 = 0x000034C0 + 0x228e, .AFMT_GENERIC_2 = 0x000034C0 + 0x228f, .AFMT_GENERIC_3 = 0x000034C0 + 0x2290 , .AFMT_GENERIC_4 = 0x000034C0 + 0x2291, .AFMT_GENERIC_5 = 0x000034C0 + 0x2292, .AFMT_GENERIC_6 = 0x000034C0 + 0x2293, .AFMT_GENERIC_7 = 0x000034C0 + 0x2294, .AFMT_GENERIC_HDR = 0x000034C0 + 0x228c , .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x22ac, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x22ab, .AFMT_VBI_PACKET_CONTROL1 = 0x000034C0 + 0x22e7, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x22aa, . AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x227c, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x22ad, .AFMT_60958_0 = 0x000034C0 + 0x22a0, . AFMT_60958_1 = 0x000034C0 + 0x22a1, .AFMT_60958_2 = 0x000034C0 + 0x22a7, .DIG_FE_CNTL = 0x000034C0 + 0x2268, .HDMI_CONTROL = 0x000034C0 + 0x2271, .HDMI_DB_CONTROL = 0x000034C0 + 0x2288, .HDMI_GC = 0x000034C0 + 0x227b, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x2278, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x2295, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x2286 , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x2287, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2276, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2277, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2275, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2273, .HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2274, .HDMI_ACR_32_0 = 0x000034C0 + 0x2296, .HDMI_ACR_32_1 = 0x000034C0 + 0x2297, .HDMI_ACR_44_0 = 0x000034C0 + 0x2298, .HDMI_ACR_44_1 = 0x000034C0 + 0x2299, .HDMI_ACR_48_0 = 0x000034C0 + 0x229a, .HDMI_ACR_48_1 = 0x000034C0 + 0x229b, .DP_DB_CNTL = 0x000034C0 + 0x2359, .DP_MSA_MISC = 0x000034C0 + 0x230e, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x230a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x234c , .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x234d, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x234e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x234f , .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2337, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2339, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2309 , .DP_SEC_CNTL = 0x000034C0 + 0x232b, .DP_SEC_CNTL2 = 0x000034C0 + 0x2353, .DP_SEC_CNTL6 = 0x000034C0 + 0x2357, .DP_STEER_FIFO = 0x000034C0 + 0x230d, .DP_VID_M = 0x000034C0 + 0x2312, .DP_VID_N = 0x000034C0 + 0x2311, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x230c , .DP_VID_TIMING = 0x000034C0 + 0x2310, .DP_SEC_AUD_N = 0x000034C0 + 0x2331, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2335, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x226b, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x2270, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x22f6 , .DP_DSC_CNTL = 0x000034C0 + 0x2352, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x235c, .DME_CONTROL = 0x000034C0 + 0x2289, . DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x235b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x226f, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2330 }, | |||
625 | stream_enc_regs(3)[3] = { .AFMT_CNTL = 0x000034C0 + 0x23e6, .AFMT_GENERIC_0 = 0x000034C0 + 0x238d, .AFMT_GENERIC_1 = 0x000034C0 + 0x238e, .AFMT_GENERIC_2 = 0x000034C0 + 0x238f, .AFMT_GENERIC_3 = 0x000034C0 + 0x2390 , .AFMT_GENERIC_4 = 0x000034C0 + 0x2391, .AFMT_GENERIC_5 = 0x000034C0 + 0x2392, .AFMT_GENERIC_6 = 0x000034C0 + 0x2393, .AFMT_GENERIC_7 = 0x000034C0 + 0x2394, .AFMT_GENERIC_HDR = 0x000034C0 + 0x238c , .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x23ac, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x23ab, .AFMT_VBI_PACKET_CONTROL1 = 0x000034C0 + 0x23e7, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x23aa, . AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x237c, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x23ad, .AFMT_60958_0 = 0x000034C0 + 0x23a0, . AFMT_60958_1 = 0x000034C0 + 0x23a1, .AFMT_60958_2 = 0x000034C0 + 0x23a7, .DIG_FE_CNTL = 0x000034C0 + 0x2368, .HDMI_CONTROL = 0x000034C0 + 0x2371, .HDMI_DB_CONTROL = 0x000034C0 + 0x2388, .HDMI_GC = 0x000034C0 + 0x237b, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x2378, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x2395, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x2386 , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x2387, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2376, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2377, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2375, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2373, .HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2374, .HDMI_ACR_32_0 = 0x000034C0 + 0x2396, .HDMI_ACR_32_1 = 0x000034C0 + 0x2397, .HDMI_ACR_44_0 = 0x000034C0 + 0x2398, .HDMI_ACR_44_1 = 0x000034C0 + 0x2399, .HDMI_ACR_48_0 = 0x000034C0 + 0x239a, .HDMI_ACR_48_1 = 0x000034C0 + 0x239b, .DP_DB_CNTL = 0x000034C0 + 0x2459, .DP_MSA_MISC = 0x000034C0 + 0x240e, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x240a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x244c , .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x244d, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x244e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x244f , .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2437, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2439, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2409 , .DP_SEC_CNTL = 0x000034C0 + 0x242b, .DP_SEC_CNTL2 = 0x000034C0 + 0x2453, .DP_SEC_CNTL6 = 0x000034C0 + 0x2457, .DP_STEER_FIFO = 0x000034C0 + 0x240d, .DP_VID_M = 0x000034C0 + 0x2412, .DP_VID_N = 0x000034C0 + 0x2411, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x240c , .DP_VID_TIMING = 0x000034C0 + 0x2410, .DP_SEC_AUD_N = 0x000034C0 + 0x2431, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2435, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x236b, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x2370, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x23f6 , .DP_DSC_CNTL = 0x000034C0 + 0x2452, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x245c, .DME_CONTROL = 0x000034C0 + 0x2389, . DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x245b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x236f, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2430 }, | |||
626 | stream_enc_regs(4)[4] = { .AFMT_CNTL = 0x000034C0 + 0x24e6, .AFMT_GENERIC_0 = 0x000034C0 + 0x248d, .AFMT_GENERIC_1 = 0x000034C0 + 0x248e, .AFMT_GENERIC_2 = 0x000034C0 + 0x248f, .AFMT_GENERIC_3 = 0x000034C0 + 0x2490 , .AFMT_GENERIC_4 = 0x000034C0 + 0x2491, .AFMT_GENERIC_5 = 0x000034C0 + 0x2492, .AFMT_GENERIC_6 = 0x000034C0 + 0x2493, .AFMT_GENERIC_7 = 0x000034C0 + 0x2494, .AFMT_GENERIC_HDR = 0x000034C0 + 0x248c , .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x24ac, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x24ab, .AFMT_VBI_PACKET_CONTROL1 = 0x000034C0 + 0x24e7, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x24aa, . AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x247c, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x24ad, .AFMT_60958_0 = 0x000034C0 + 0x24a0, . AFMT_60958_1 = 0x000034C0 + 0x24a1, .AFMT_60958_2 = 0x000034C0 + 0x24a7, .DIG_FE_CNTL = 0x000034C0 + 0x2468, .HDMI_CONTROL = 0x000034C0 + 0x2471, .HDMI_DB_CONTROL = 0x000034C0 + 0x2488, .HDMI_GC = 0x000034C0 + 0x247b, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x2478, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x2495, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x2486 , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x2487, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2476, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2477, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2475, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2473, .HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2474, .HDMI_ACR_32_0 = 0x000034C0 + 0x2496, .HDMI_ACR_32_1 = 0x000034C0 + 0x2497, .HDMI_ACR_44_0 = 0x000034C0 + 0x2498, .HDMI_ACR_44_1 = 0x000034C0 + 0x2499, .HDMI_ACR_48_0 = 0x000034C0 + 0x249a, .HDMI_ACR_48_1 = 0x000034C0 + 0x249b, .DP_DB_CNTL = 0x000034C0 + 0x2559, .DP_MSA_MISC = 0x000034C0 + 0x250e, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x250a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x254c , .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x254d, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x254e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x254f , .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2537, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2539, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2509 , .DP_SEC_CNTL = 0x000034C0 + 0x252b, .DP_SEC_CNTL2 = 0x000034C0 + 0x2553, .DP_SEC_CNTL6 = 0x000034C0 + 0x2557, .DP_STEER_FIFO = 0x000034C0 + 0x250d, .DP_VID_M = 0x000034C0 + 0x2512, .DP_VID_N = 0x000034C0 + 0x2511, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x250c , .DP_VID_TIMING = 0x000034C0 + 0x2510, .DP_SEC_AUD_N = 0x000034C0 + 0x2531, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2535, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x246b, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x2470, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x24f6 , .DP_DSC_CNTL = 0x000034C0 + 0x2552, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x255c, .DME_CONTROL = 0x000034C0 + 0x2489, . DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x255b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x246f, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2530 }, | |||
627 | stream_enc_regs(5)[5] = { .AFMT_CNTL = 0x000034C0 + 0x25e6, .AFMT_GENERIC_0 = 0x000034C0 + 0x258d, .AFMT_GENERIC_1 = 0x000034C0 + 0x258e, .AFMT_GENERIC_2 = 0x000034C0 + 0x258f, .AFMT_GENERIC_3 = 0x000034C0 + 0x2590 , .AFMT_GENERIC_4 = 0x000034C0 + 0x2591, .AFMT_GENERIC_5 = 0x000034C0 + 0x2592, .AFMT_GENERIC_6 = 0x000034C0 + 0x2593, .AFMT_GENERIC_7 = 0x000034C0 + 0x2594, .AFMT_GENERIC_HDR = 0x000034C0 + 0x258c , .AFMT_INFOFRAME_CONTROL0 = 0x000034C0 + 0x25ac, .AFMT_VBI_PACKET_CONTROL = 0x000034C0 + 0x25ab, .AFMT_VBI_PACKET_CONTROL1 = 0x000034C0 + 0x25e7, .AFMT_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x25aa, . AFMT_AUDIO_PACKET_CONTROL2 = 0x000034C0 + 0x257c, .AFMT_AUDIO_SRC_CONTROL = 0x000034C0 + 0x25ad, .AFMT_60958_0 = 0x000034C0 + 0x25a0, . AFMT_60958_1 = 0x000034C0 + 0x25a1, .AFMT_60958_2 = 0x000034C0 + 0x25a7, .DIG_FE_CNTL = 0x000034C0 + 0x2568, .HDMI_CONTROL = 0x000034C0 + 0x2571, .HDMI_DB_CONTROL = 0x000034C0 + 0x2588, .HDMI_GC = 0x000034C0 + 0x257b, .HDMI_GENERIC_PACKET_CONTROL0 = 0x000034C0 + 0x2578, .HDMI_GENERIC_PACKET_CONTROL1 = 0x000034C0 + 0x2595, .HDMI_GENERIC_PACKET_CONTROL2 = 0x000034C0 + 0x2586 , .HDMI_GENERIC_PACKET_CONTROL3 = 0x000034C0 + 0x2587, .HDMI_INFOFRAME_CONTROL0 = 0x000034C0 + 0x2576, .HDMI_INFOFRAME_CONTROL1 = 0x000034C0 + 0x2577, .HDMI_VBI_PACKET_CONTROL = 0x000034C0 + 0x2575, .HDMI_AUDIO_PACKET_CONTROL = 0x000034C0 + 0x2573, .HDMI_ACR_PACKET_CONTROL = 0x000034C0 + 0x2574, .HDMI_ACR_32_0 = 0x000034C0 + 0x2596, .HDMI_ACR_32_1 = 0x000034C0 + 0x2597, .HDMI_ACR_44_0 = 0x000034C0 + 0x2598, .HDMI_ACR_44_1 = 0x000034C0 + 0x2599, .HDMI_ACR_48_0 = 0x000034C0 + 0x259a, .HDMI_ACR_48_1 = 0x000034C0 + 0x259b, .DP_DB_CNTL = 0x000034C0 + 0x2659, .DP_MSA_MISC = 0x000034C0 + 0x260e, .DP_MSA_COLORIMETRY = 0x000034C0 + 0x260a, .DP_MSA_TIMING_PARAM1 = 0x000034C0 + 0x264c , .DP_MSA_TIMING_PARAM2 = 0x000034C0 + 0x264d, .DP_MSA_TIMING_PARAM3 = 0x000034C0 + 0x264e, .DP_MSA_TIMING_PARAM4 = 0x000034C0 + 0x264f , .DP_MSE_RATE_CNTL = 0x000034C0 + 0x2637, .DP_MSE_RATE_UPDATE = 0x000034C0 + 0x2639, .DP_PIXEL_FORMAT = 0x000034C0 + 0x2609 , .DP_SEC_CNTL = 0x000034C0 + 0x262b, .DP_SEC_CNTL2 = 0x000034C0 + 0x2653, .DP_SEC_CNTL6 = 0x000034C0 + 0x2657, .DP_STEER_FIFO = 0x000034C0 + 0x260d, .DP_VID_M = 0x000034C0 + 0x2612, .DP_VID_N = 0x000034C0 + 0x2611, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x260c , .DP_VID_TIMING = 0x000034C0 + 0x2610, .DP_SEC_AUD_N = 0x000034C0 + 0x2631, .DP_SEC_TIMESTAMP = 0x000034C0 + 0x2635, .DIG_CLOCK_PATTERN = 0x000034C0 + 0x256b, .HDMI_GENERIC_PACKET_CONTROL4 = 0x000034C0 + 0x2570, .HDMI_GENERIC_PACKET_CONTROL5 = 0x000034C0 + 0x25f6 , .DP_DSC_CNTL = 0x000034C0 + 0x2652, .DP_DSC_BYTES_PER_PIXEL = 0x000034C0 + 0x265c, .DME_CONTROL = 0x000034C0 + 0x2589, . DP_SEC_METADATA_TRANSMISSION = 0x000034C0 + 0x265b, .HDMI_METADATA_PACKET_CONTROL = 0x000034C0 + 0x256f, .DP_SEC_FRAMING4 = 0x000034C0 + 0x2630 }, | |||
628 | }; | |||
629 | ||||
630 | static const struct dcn10_stream_encoder_shift se_shift = { | |||
631 | SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT).AFMT_GENERIC_INDEX = 0x1c, .AFMT_GENERIC_HB0 = 0x0, .AFMT_GENERIC_HB1 = 0x8, .AFMT_GENERIC_HB2 = 0x10, .AFMT_GENERIC_HB3 = 0x18, . DP_PIXEL_ENCODING = 0x0, .DP_COMPONENT_DEPTH = 0x18, .HDMI_PACKET_GEN_VERSION = 0x4, .HDMI_KEEPOUT_MODE = 0x0, .HDMI_DEEP_COLOR_ENABLE = 0x18 , .HDMI_DEEP_COLOR_DEPTH = 0x1c, .HDMI_DATA_SCRAMBLE_EN = 0x1 , .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x3, .HDMI_GC_CONT = 0x5 , .HDMI_GC_SEND = 0x4, .HDMI_NULL_SEND = 0x0, .HDMI_AUDIO_INFO_SEND = 0x4, .AFMT_AUDIO_INFO_UPDATE = 0x7, .HDMI_AUDIO_INFO_LINE = 0x8, .HDMI_GC_AVMUTE = 0x0, .DP_MSE_RATE_X = 0x1a, .DP_MSE_RATE_Y = 0x0, .DP_MSE_RATE_UPDATE_PENDING = 0x0, .DP_SEC_GSP0_ENABLE = 0x14, .DP_SEC_STREAM_ENABLE = 0x0, .DP_SEC_GSP1_ENABLE = 0x15 , .DP_SEC_GSP2_ENABLE = 0x16, .DP_SEC_GSP3_ENABLE = 0x17, .DP_SEC_MPG_ENABLE = 0x1c, .DP_SEC_GSP4_SEND = 0xc, .DP_SEC_GSP4_SEND_PENDING = 0xd, .DP_SEC_GSP4_LINE_NUM = 0x10, .DP_SEC_GSP4_SEND_ANY_LINE = 0xf, .DP_VID_STREAM_DIS_DEFER = 0x8, .DP_VID_STREAM_ENABLE = 0x0, .DP_VID_STREAM_STATUS = 0x10, .DP_STEER_FIFO_RESET = 0x0 , .DP_VID_M_N_GEN_EN = 0x8, .DP_VID_N = 0x0, .DP_VID_M = 0x0, .DIG_START = 0xa, .AFMT_AUDIO_SRC_SELECT = 0x0, .AFMT_AUDIO_CHANNEL_ENABLE = 0x8, .HDMI_AUDIO_PACKETS_PER_LINE = 0x10, .HDMI_AUDIO_DELAY_EN = 0x4, .AFMT_60958_CS_UPDATE = 0x1a, .AFMT_AUDIO_LAYOUT_OVRD = 0x0, .AFMT_60958_OSF_OVRD = 0x1c, .HDMI_ACR_AUTO_SEND = 0xc , .HDMI_ACR_SOURCE = 0x8, .HDMI_ACR_AUDIO_PRIORITY = 0x1f, .HDMI_ACR_CTS_32 = 0xc, .HDMI_ACR_N_32 = 0x0, .HDMI_ACR_CTS_44 = 0xc, .HDMI_ACR_N_44 = 0x0, .HDMI_ACR_CTS_48 = 0xc, .HDMI_ACR_N_48 = 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0x14, .AFMT_60958_CS_CLOCK_ACCURACY = 0x1c, .AFMT_60958_CS_CHANNEL_NUMBER_R = 0x14, .AFMT_60958_CS_CHANNEL_NUMBER_2 = 0x0, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x4, .AFMT_60958_CS_CHANNEL_NUMBER_4 = 0x8, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0xc, .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x10, .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x14, .DP_SEC_AUD_N = 0x0, .DP_SEC_TIMESTAMP_MODE = 0x0, . DP_SEC_ASP_ENABLE = 0x4, .DP_SEC_ATP_ENABLE = 0x8, .DP_SEC_AIP_ENABLE = 0xc, .DP_SEC_ACM_ENABLE = 0x10, .AFMT_AUDIO_SAMPLE_SEND = 0x0 , .AFMT_AUDIO_CLOCK_EN = 0x0, .HDMI_CLOCK_CHANNEL_RATE = 0x2, .TMDS_PIXEL_ENCODING = 0x1c, .TMDS_COLOR_FORMAT = 0x1e, .DIG_STEREOSYNC_SELECT = 0x4, .DIG_STEREOSYNC_GATE_EN = 0x8, .AFMT_GENERIC_LOCK_STATUS = 0x8, .AFMT_GENERIC_CONFLICT = 0x10, .AFMT_GENERIC_CONFLICT_CLR = 0x11, .AFMT_GENERIC0_FRAME_UPDATE_PENDING = 0x1, .AFMT_GENERIC1_FRAME_UPDATE_PENDING = 0x5, .AFMT_GENERIC2_FRAME_UPDATE_PENDING = 0x9, .AFMT_GENERIC3_FRAME_UPDATE_PENDING = 0xd, .AFMT_GENERIC4_FRAME_UPDATE_PENDING = 0x11, .AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING = 0x13, .AFMT_GENERIC5_FRAME_UPDATE_PENDING = 0x15, .AFMT_GENERIC6_FRAME_UPDATE_PENDING = 0x19, .AFMT_GENERIC7_FRAME_UPDATE_PENDING = 0x1d, .AFMT_GENERIC0_FRAME_UPDATE = 0x0, .AFMT_GENERIC1_FRAME_UPDATE = 0x4, .AFMT_GENERIC2_FRAME_UPDATE = 0x8, .AFMT_GENERIC3_FRAME_UPDATE = 0xc, .AFMT_GENERIC4_FRAME_UPDATE = 0x10, .AFMT_GENERIC0_IMMEDIATE_UPDATE = 0x2, .AFMT_GENERIC1_IMMEDIATE_UPDATE = 0x6, .AFMT_GENERIC2_IMMEDIATE_UPDATE = 0xa, .AFMT_GENERIC3_IMMEDIATE_UPDATE = 0xe, .AFMT_GENERIC4_IMMEDIATE_UPDATE = 0x12, .AFMT_GENERIC5_IMMEDIATE_UPDATE = 0x16, .AFMT_GENERIC6_IMMEDIATE_UPDATE = 0x1a, .AFMT_GENERIC7_IMMEDIATE_UPDATE = 0x1e, .AFMT_GENERIC5_FRAME_UPDATE = 0x14, .AFMT_GENERIC6_FRAME_UPDATE = 0x18, .AFMT_GENERIC7_FRAME_UPDATE = 0x1c, .DP_SEC_GSP4_ENABLE = 0x18, .DP_SEC_GSP5_ENABLE = 0x19, .DP_SEC_GSP6_ENABLE = 0x1a , .DP_SEC_GSP7_ENABLE = 0x1b, .DP_SEC_GSP7_PPS = 0x1c, .DP_SEC_GSP7_SEND = 0x18, .DP_SEC_GSP7_LINE_NUM = 0x0, .DP_DB_DISABLE = 0xc, . DP_MSA_MISC0 = 0x18, .DP_MSA_HTOTAL = 0x10, .DP_MSA_VTOTAL = 0x0 , .DP_MSA_HSTART = 0x10, .DP_MSA_VSTART = 0x0, .DP_MSA_HSYNCWIDTH = 0x10, .DP_MSA_HSYNCPOLARITY = 0x1f, .DP_MSA_VSYNCWIDTH = 0x0 , .DP_MSA_VSYNCPOLARITY = 0xf, .DP_MSA_HWIDTH = 0x10, .DP_MSA_VHEIGHT = 0x0, .HDMI_DB_DISABLE = 0xc, .DP_VID_N_MUL = 0xa, .DIG_SOURCE_SELECT = 0x0, .DIG_CLOCK_PATTERN = 0x0, .HDMI_GENERIC0_CONT = 0x1, . HDMI_GENERIC0_SEND = 0x0, .HDMI_GENERIC1_CONT = 0x5, .HDMI_GENERIC1_SEND = 0x4, .HDMI_GENERIC2_CONT = 0x9, .HDMI_GENERIC2_SEND = 0x8, .HDMI_GENERIC3_CONT = 0xd, .HDMI_GENERIC3_SEND = 0xc, .HDMI_GENERIC4_CONT = 0x11, .HDMI_GENERIC4_SEND = 0x10, .HDMI_GENERIC5_CONT = 0x15 , .HDMI_GENERIC5_SEND = 0x14, .HDMI_GENERIC6_CONT = 0x19, .HDMI_GENERIC6_SEND = 0x18, .HDMI_GENERIC7_CONT = 0x1d, .HDMI_GENERIC7_SEND = 0x1c , .HDMI_GENERIC0_LINE = 0x0, .HDMI_GENERIC1_LINE = 0x10, .HDMI_GENERIC2_LINE = 0x0, .HDMI_GENERIC3_LINE = 0x10, .HDMI_GENERIC4_LINE = 0x0 , .HDMI_GENERIC5_LINE = 0x10, .HDMI_GENERIC6_LINE = 0x0, .HDMI_GENERIC7_LINE = 0x10, .DP_DSC_MODE = 0x0, .DP_DSC_SLICE_WIDTH = 0x10, .DP_DSC_BYTES_PER_PIXEL = 0x0, .DP_VBID6_LINE_REFERENCE = 0xf, .DP_VBID6_LINE_NUM = 0x10 , .METADATA_ENGINE_EN = 0x4, .METADATA_HUBP_REQUESTOR_ID = 0x0 , .METADATA_STREAM_TYPE = 0x8, .DP_SEC_METADATA_PACKET_ENABLE = 0x0, .DP_SEC_METADATA_PACKET_LINE_REFERENCE = 0x1, .DP_SEC_METADATA_PACKET_LINE = 0x10, .HDMI_METADATA_PACKET_ENABLE = 0x0, .HDMI_METADATA_PACKET_LINE_REFERENCE = 0x4, .HDMI_METADATA_PACKET_LINE = 0x10, .DOLBY_VISION_EN = 0x12, .DP_PIXEL_COMBINE = 0x1c, .DP_SST_SDP_SPLITTING = 0x0 | |||
632 | }; | |||
633 | ||||
634 | static const struct dcn10_stream_encoder_mask se_mask = { | |||
635 | SE_COMMON_MASK_SH_LIST_DCN20(_MASK).AFMT_GENERIC_INDEX = 0xF0000000L, .AFMT_GENERIC_HB0 = 0x000000FFL , .AFMT_GENERIC_HB1 = 0x0000FF00L, .AFMT_GENERIC_HB2 = 0x00FF0000L , .AFMT_GENERIC_HB3 = 0xFF000000L, .DP_PIXEL_ENCODING = 0x00000007L , .DP_COMPONENT_DEPTH = 0x07000000L, .HDMI_PACKET_GEN_VERSION = 0x00000010L, .HDMI_KEEPOUT_MODE = 0x00000001L, .HDMI_DEEP_COLOR_ENABLE = 0x01000000L, .HDMI_DEEP_COLOR_DEPTH = 0x30000000L, .HDMI_DATA_SCRAMBLE_EN = 0x00000002L, .HDMI_NO_EXTRA_NULL_PACKET_FILLED = 0x00000008L , .HDMI_GC_CONT = 0x00000020L, .HDMI_GC_SEND = 0x00000010L, . HDMI_NULL_SEND = 0x00000001L, .HDMI_AUDIO_INFO_SEND = 0x00000010L , .AFMT_AUDIO_INFO_UPDATE = 0x00000080L, .HDMI_AUDIO_INFO_LINE = 0x00003F00L, .HDMI_GC_AVMUTE = 0x00000001L, .DP_MSE_RATE_X = 0xFC000000L, .DP_MSE_RATE_Y = 0x03FFFFFFL, .DP_MSE_RATE_UPDATE_PENDING = 0x00000001L, .DP_SEC_GSP0_ENABLE = 0x00100000L, .DP_SEC_STREAM_ENABLE = 0x00000001L, .DP_SEC_GSP1_ENABLE = 0x00200000L, .DP_SEC_GSP2_ENABLE = 0x00400000L, .DP_SEC_GSP3_ENABLE = 0x00800000L, .DP_SEC_MPG_ENABLE = 0x10000000L, .DP_SEC_GSP4_SEND = 0x00001000L, .DP_SEC_GSP4_SEND_PENDING = 0x00002000L, .DP_SEC_GSP4_LINE_NUM = 0xFFFF0000L, .DP_SEC_GSP4_SEND_ANY_LINE = 0x00008000L, .DP_VID_STREAM_DIS_DEFER = 0x00000300L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_VID_STREAM_STATUS = 0x00010000L, .DP_STEER_FIFO_RESET = 0x00000001L, .DP_VID_M_N_GEN_EN = 0x00000100L, .DP_VID_N = 0x00FFFFFFL, .DP_VID_M = 0x00FFFFFFL, .DIG_START = 0x00000400L , .AFMT_AUDIO_SRC_SELECT = 0x00000007L, .AFMT_AUDIO_CHANNEL_ENABLE = 0x0000FF00L, .HDMI_AUDIO_PACKETS_PER_LINE = 0x001F0000L, . HDMI_AUDIO_DELAY_EN = 0x00000030L, .AFMT_60958_CS_UPDATE = 0x04000000L , .AFMT_AUDIO_LAYOUT_OVRD = 0x00000001L, .AFMT_60958_OSF_OVRD = 0x10000000L, .HDMI_ACR_AUTO_SEND = 0x00001000L, .HDMI_ACR_SOURCE = 0x00000100L, .HDMI_ACR_AUDIO_PRIORITY = 0x80000000L, .HDMI_ACR_CTS_32 = 0xFFFFF000L, .HDMI_ACR_N_32 = 0x000FFFFFL, .HDMI_ACR_CTS_44 = 0xFFFFF000L, .HDMI_ACR_N_44 = 0x000FFFFFL, .HDMI_ACR_CTS_48 = 0xFFFFF000L, .HDMI_ACR_N_48 = 0x000FFFFFL, .AFMT_60958_CS_CHANNEL_NUMBER_L = 0x00F00000L, .AFMT_60958_CS_CLOCK_ACCURACY = 0x30000000L, . AFMT_60958_CS_CHANNEL_NUMBER_R = 0x00F00000L, .AFMT_60958_CS_CHANNEL_NUMBER_2 = 0x0000000FL, .AFMT_60958_CS_CHANNEL_NUMBER_3 = 0x000000F0L , .AFMT_60958_CS_CHANNEL_NUMBER_4 = 0x00000F00L, .AFMT_60958_CS_CHANNEL_NUMBER_5 = 0x0000F000L, .AFMT_60958_CS_CHANNEL_NUMBER_6 = 0x000F0000L , .AFMT_60958_CS_CHANNEL_NUMBER_7 = 0x00F00000L, .DP_SEC_AUD_N = 0x00FFFFFFL, .DP_SEC_TIMESTAMP_MODE = 0x00000001L, .DP_SEC_ASP_ENABLE = 0x00000010L, .DP_SEC_ATP_ENABLE = 0x00000100L, .DP_SEC_AIP_ENABLE = 0x00001000L, .DP_SEC_ACM_ENABLE = 0x00010000L, .AFMT_AUDIO_SAMPLE_SEND = 0x00000001L, .AFMT_AUDIO_CLOCK_EN = 0x00000001L, .HDMI_CLOCK_CHANNEL_RATE = 0x00000004L, .TMDS_PIXEL_ENCODING = 0x10000000L, .TMDS_COLOR_FORMAT = 0xC0000000L, .DIG_STEREOSYNC_SELECT = 0x00000070L, .DIG_STEREOSYNC_GATE_EN = 0x00000100L, .AFMT_GENERIC_LOCK_STATUS = 0x00000100L, .AFMT_GENERIC_CONFLICT = 0x00010000L, .AFMT_GENERIC_CONFLICT_CLR = 0x00020000L, .AFMT_GENERIC0_FRAME_UPDATE_PENDING = 0x00000002L, .AFMT_GENERIC1_FRAME_UPDATE_PENDING = 0x00000020L , .AFMT_GENERIC2_FRAME_UPDATE_PENDING = 0x00000200L, .AFMT_GENERIC3_FRAME_UPDATE_PENDING = 0x00002000L, .AFMT_GENERIC4_FRAME_UPDATE_PENDING = 0x00020000L , .AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING = 0x00080000L, .AFMT_GENERIC5_FRAME_UPDATE_PENDING = 0x00200000L, .AFMT_GENERIC6_FRAME_UPDATE_PENDING = 0x02000000L , .AFMT_GENERIC7_FRAME_UPDATE_PENDING = 0x20000000L, .AFMT_GENERIC0_FRAME_UPDATE = 0x00000001L, .AFMT_GENERIC1_FRAME_UPDATE = 0x00000010L, .AFMT_GENERIC2_FRAME_UPDATE = 0x00000100L, .AFMT_GENERIC3_FRAME_UPDATE = 0x00001000L, .AFMT_GENERIC4_FRAME_UPDATE = 0x00010000L, .AFMT_GENERIC0_IMMEDIATE_UPDATE = 0x00000004L , .AFMT_GENERIC1_IMMEDIATE_UPDATE = 0x00000040L, .AFMT_GENERIC2_IMMEDIATE_UPDATE = 0x00000400L, .AFMT_GENERIC3_IMMEDIATE_UPDATE = 0x00004000L , .AFMT_GENERIC4_IMMEDIATE_UPDATE = 0x00040000L, .AFMT_GENERIC5_IMMEDIATE_UPDATE = 0x00400000L, .AFMT_GENERIC6_IMMEDIATE_UPDATE = 0x04000000L , .AFMT_GENERIC7_IMMEDIATE_UPDATE = 0x40000000L, .AFMT_GENERIC5_FRAME_UPDATE = 0x00100000L, .AFMT_GENERIC6_FRAME_UPDATE = 0x01000000L, .AFMT_GENERIC7_FRAME_UPDATE = 0x10000000L, .DP_SEC_GSP4_ENABLE = 0x01000000L, .DP_SEC_GSP5_ENABLE = 0x02000000L, .DP_SEC_GSP6_ENABLE = 0x04000000L, .DP_SEC_GSP7_ENABLE = 0x08000000L, .DP_SEC_GSP7_PPS = 0x10000000L, .DP_SEC_GSP7_SEND = 0x01000000L, .DP_SEC_GSP7_LINE_NUM = 0x0000FFFFL, .DP_DB_DISABLE = 0x00001000L, .DP_MSA_MISC0 = 0xFF000000L, .DP_MSA_HTOTAL = 0xFFFF0000L, .DP_MSA_VTOTAL = 0x0000FFFFL, .DP_MSA_HSTART = 0xFFFF0000L , .DP_MSA_VSTART = 0x0000FFFFL, .DP_MSA_HSYNCWIDTH = 0x7FFF0000L , .DP_MSA_HSYNCPOLARITY = 0x80000000L, .DP_MSA_VSYNCWIDTH = 0x00007FFFL , .DP_MSA_VSYNCPOLARITY = 0x00008000L, .DP_MSA_HWIDTH = 0xFFFF0000L , .DP_MSA_VHEIGHT = 0x0000FFFFL, .HDMI_DB_DISABLE = 0x00001000L , .DP_VID_N_MUL = 0x00000C00L, .DIG_SOURCE_SELECT = 0x00000007L , .DIG_CLOCK_PATTERN = 0x000003FFL, .HDMI_GENERIC0_CONT = 0x00000002L , .HDMI_GENERIC0_SEND = 0x00000001L, .HDMI_GENERIC1_CONT = 0x00000020L , .HDMI_GENERIC1_SEND = 0x00000010L, .HDMI_GENERIC2_CONT = 0x00000200L , .HDMI_GENERIC2_SEND = 0x00000100L, .HDMI_GENERIC3_CONT = 0x00002000L , .HDMI_GENERIC3_SEND = 0x00001000L, .HDMI_GENERIC4_CONT = 0x00020000L , .HDMI_GENERIC4_SEND = 0x00010000L, .HDMI_GENERIC5_CONT = 0x00200000L , .HDMI_GENERIC5_SEND = 0x00100000L, .HDMI_GENERIC6_CONT = 0x02000000L , .HDMI_GENERIC6_SEND = 0x01000000L, .HDMI_GENERIC7_CONT = 0x20000000L , .HDMI_GENERIC7_SEND = 0x10000000L, .HDMI_GENERIC0_LINE = 0x0000FFFFL , .HDMI_GENERIC1_LINE = 0xFFFF0000L, .HDMI_GENERIC2_LINE = 0x0000FFFFL , .HDMI_GENERIC3_LINE = 0xFFFF0000L, .HDMI_GENERIC4_LINE = 0x0000FFFFL , .HDMI_GENERIC5_LINE = 0xFFFF0000L, .HDMI_GENERIC6_LINE = 0x0000FFFFL , .HDMI_GENERIC7_LINE = 0xFFFF0000L, .DP_DSC_MODE = 0x00000003L , .DP_DSC_SLICE_WIDTH = 0x1FFF0000L, .DP_DSC_BYTES_PER_PIXEL = 0x7FFFFFFFL, .DP_VBID6_LINE_REFERENCE = 0x00008000L, .DP_VBID6_LINE_NUM = 0xFFFF0000L, .METADATA_ENGINE_EN = 0x00000010L, .METADATA_HUBP_REQUESTOR_ID = 0x00000007L, .METADATA_STREAM_TYPE = 0x00000100L, .DP_SEC_METADATA_PACKET_ENABLE = 0x00000001L, .DP_SEC_METADATA_PACKET_LINE_REFERENCE = 0x00000002L , .DP_SEC_METADATA_PACKET_LINE = 0xFFFF0000L, .HDMI_METADATA_PACKET_ENABLE = 0x00000001L, .HDMI_METADATA_PACKET_LINE_REFERENCE = 0x00000010L , .HDMI_METADATA_PACKET_LINE = 0xFFFF0000L, .DOLBY_VISION_EN = 0x00040000L, .DP_PIXEL_COMBINE = 0x30000000L, .DP_SST_SDP_SPLITTING = 0x00000001L | |||
636 | }; | |||
637 | ||||
638 | ||||
639 | #define aux_regs(id)[id] = { .AUX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX + mmDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX + mmDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX + mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_DPHY_TX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX + mmDP_AUXid_AUX_DPHY_TX_CONTROL}\ | |||
640 | [id] = {\ | |||
641 | DCN2_AUX_REG_LIST(id).AUX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX + mmDP_AUXid_AUX_CONTROL, .AUX_DPHY_RX_CONTROL0 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL0_BASE_IDX + mmDP_AUXid_AUX_DPHY_RX_CONTROL0, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX + mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_DPHY_TX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_TX_CONTROL_BASE_IDX + mmDP_AUXid_AUX_DPHY_TX_CONTROL\ | |||
642 | } | |||
643 | ||||
644 | static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { | |||
645 | aux_regs(0)[0] = { .AUX_CONTROL = 0x000034C0 + 0x1f50, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1f5a, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f5b , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f59}, | |||
646 | aux_regs(1)[1] = { .AUX_CONTROL = 0x000034C0 + 0x1f6c, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1f76, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f77 , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f75}, | |||
647 | aux_regs(2)[2] = { .AUX_CONTROL = 0x000034C0 + 0x1f88, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1f92, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f93 , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1f91}, | |||
648 | aux_regs(3)[3] = { .AUX_CONTROL = 0x000034C0 + 0x1fa4, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1fae, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1faf , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1fad}, | |||
649 | aux_regs(4)[4] = { .AUX_CONTROL = 0x000034C0 + 0x1fc0, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1fca, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fcb , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1fc9}, | |||
650 | aux_regs(5)[5] = { .AUX_CONTROL = 0x000034C0 + 0x1fdc, .AUX_DPHY_RX_CONTROL0 = 0x000034C0 + 0x1fe6, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fe7 , .AUX_DPHY_TX_CONTROL = 0x000034C0 + 0x1fe5} | |||
651 | }; | |||
652 | ||||
653 | #define hpd_regs(id)[id] = { .DC_HPD_CONTROL = DCN_BASE__INST0_SEGmmHPDid_DC_HPD_CONTROL_BASE_IDX + mmHPDid_DC_HPD_CONTROL}\ | |||
654 | [id] = {\ | |||
655 | HPD_REG_LIST(id).DC_HPD_CONTROL = DCN_BASE__INST0_SEGmmHPDid_DC_HPD_CONTROL_BASE_IDX + mmHPDid_DC_HPD_CONTROL\ | |||
656 | } | |||
657 | ||||
658 | static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { | |||
659 | hpd_regs(0)[0] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f16}, | |||
660 | hpd_regs(1)[1] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f1e}, | |||
661 | hpd_regs(2)[2] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f26}, | |||
662 | hpd_regs(3)[3] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f2e}, | |||
663 | hpd_regs(4)[4] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f36}, | |||
664 | hpd_regs(5)[5] = { .DC_HPD_CONTROL = 0x000034C0 + 0x1f3e} | |||
665 | }; | |||
666 | ||||
667 | #define link_regs(id, phyid)[id] = { .DP_DPHY_INTERNAL_CTRL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX + mmDPid_DP_DPHY_INTERNAL_CTRL, .DIG_BE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_BE_CNTL_BASE_IDX + mmDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_BE_EN_CNTL_BASE_IDX + mmDIGid_DIG_BE_EN_CNTL, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX + mmDIGid_TMDS_CTL_BITS, .DP_CONFIG = DCN_BASE__INST0_SEGmmDPid_DP_CONFIG_BASE_IDX + mmDPid_DP_CONFIG, .DP_DPHY_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_CNTL_BASE_IDX + mmDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_PRBS_CNTL_BASE_IDX + mmDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX + mmDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM0_BASE_IDX + mmDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM1_BASE_IDX + mmDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM2_BASE_IDX + mmDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX + mmDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_LINK_CNTL_BASE_IDX + mmDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_LINK_FRAMING_CNTL_BASE_IDX + mmDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT0_BASE_IDX + mmDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT1_BASE_IDX + mmDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT2_BASE_IDX + mmDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT_UPDATE_BASE_IDX + mmDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX + mmDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX + mmDPid_DP_VID_STREAM_CNTL, .DP_DPHY_FAST_TRAINING = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_FAST_TRAINING_BASE_IDX + mmDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL1_BASE_IDX + mmDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX + mmDPid_DP_DPHY_BS_SR_SWAP_CNTL, .DP_DPHY_HBR2_PATTERN_CONTROL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX + mmDPid_DP_DPHY_HBR2_PATTERN_CONTROL, .CLOCK_ENABLE = DCN_BASE__INST0_SEGmmSYMCLKphyid_CLOCK_ENABLE_BASE_IDX + mmSYMCLKphyid_CLOCK_ENABLE, .CHANNEL_XBAR_CNTL = DCN_BASE__INST0_SEGmmUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX + mmUNIPHYphyid_CHANNEL_XBAR_CNTL, .DIG_LANE_ENABLE = DCN_BASE__INST0_SEGmmDIGid_DIG_LANE_ENABLE_BASE_IDX + mmDIGid_DIG_LANE_ENABLE, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX + mmDIGid_TMDS_CTL_BITS, .RDPCSTX_PHY_CNTL3 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL3_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL3, .RDPCSTX_PHY_CNTL4 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL4_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL4, .RDPCSTX_PHY_CNTL5 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL5_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL5, .RDPCSTX_PHY_CNTL6 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL6_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL6, .RDPCSTX_PHY_CNTL7 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL7_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL7, .RDPCSTX_PHY_CNTL8 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL8_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL8, .RDPCSTX_PHY_CNTL9 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL9_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL9, .RDPCSTX_PHY_CNTL10 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL10_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL10, .RDPCSTX_PHY_CNTL11 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL11_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL11, .RDPCSTX_PHY_CNTL12 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL12_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL12, .RDPCSTX_PHY_CNTL13 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL13_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL13, .RDPCSTX_PHY_CNTL14 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL14_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL14, .RDPCSTX_CNTL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_CNTL_BASE_IDX + mmRDPCSTXid_RDPCSTX_CNTL, .RDPCSTX_CLOCK_CNTL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_CLOCK_CNTL_BASE_IDX + mmRDPCSTXid_RDPCSTX_CLOCK_CNTL, .RDPCSTX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX + mmRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL, .RDPCSTX_PHY_CNTL0 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL0_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL0 , .RDPCSTX_PHY_CNTL2 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL2_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL2, .RDPCSTX_PLL_UPDATE_DATA = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX + mmRDPCSTXid_RDPCSTX_PLL_UPDATE_DATA, .RDPCS_TX_CR_ADDR = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCS_TX_CR_ADDR_BASE_IDX + mmRDPCSTXid_RDPCS_TX_CR_ADDR, .RDPCS_TX_CR_DATA = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCS_TX_CR_DATA_BASE_IDX + mmRDPCSTXid_RDPCS_TX_CR_DATA, .RDPCSTX_PHY_FUSE0 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE0_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_FUSE0, .RDPCSTX_PHY_FUSE1 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE1_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_FUSE1, .RDPCSTX_PHY_FUSE2 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE2_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_FUSE2, .RDPCSTX_PHY_FUSE3 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE3_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_FUSE3, .DPCSTX_TX_CLOCK_CNTL = DCN_BASE__INST0_SEGmmDPCSTXid_DPCSTX_TX_CLOCK_CNTL_BASE_IDX + mmDPCSTXid_DPCSTX_TX_CLOCK_CNTL, .DPCSTX_TX_CNTL = DCN_BASE__INST0_SEGmmDPCSTXid_DPCSTX_TX_CNTL_BASE_IDX + mmDPCSTXid_DPCSTX_TX_CNTL, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2939, .RDPCSTX_PHY_RX_LD_VAL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX + mmRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, .DP_DPHY_INTERNAL_CTRL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX + mmDPid_DP_DPHY_INTERNAL_CTRL }\ | |||
668 | [id] = {\ | |||
669 | LE_DCN10_REG_LIST(id).DP_DPHY_INTERNAL_CTRL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX + mmDPid_DP_DPHY_INTERNAL_CTRL, .DIG_BE_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_BE_CNTL_BASE_IDX + mmDIGid_DIG_BE_CNTL, .DIG_BE_EN_CNTL = DCN_BASE__INST0_SEGmmDIGid_DIG_BE_EN_CNTL_BASE_IDX + mmDIGid_DIG_BE_EN_CNTL, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX + mmDIGid_TMDS_CTL_BITS, .DP_CONFIG = DCN_BASE__INST0_SEGmmDPid_DP_CONFIG_BASE_IDX + mmDPid_DP_CONFIG, .DP_DPHY_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_CNTL_BASE_IDX + mmDPid_DP_DPHY_CNTL, .DP_DPHY_PRBS_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_PRBS_CNTL_BASE_IDX + mmDPid_DP_DPHY_PRBS_CNTL, .DP_DPHY_SCRAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SCRAM_CNTL_BASE_IDX + mmDPid_DP_DPHY_SCRAM_CNTL, .DP_DPHY_SYM0 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM0_BASE_IDX + mmDPid_DP_DPHY_SYM0, .DP_DPHY_SYM1 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM1_BASE_IDX + mmDPid_DP_DPHY_SYM1, .DP_DPHY_SYM2 = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_SYM2_BASE_IDX + mmDPid_DP_DPHY_SYM2, .DP_DPHY_TRAINING_PATTERN_SEL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX + mmDPid_DP_DPHY_TRAINING_PATTERN_SEL, .DP_LINK_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_LINK_CNTL_BASE_IDX + mmDPid_DP_LINK_CNTL, .DP_LINK_FRAMING_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_LINK_FRAMING_CNTL_BASE_IDX + mmDPid_DP_LINK_FRAMING_CNTL, .DP_MSE_SAT0 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT0_BASE_IDX + mmDPid_DP_MSE_SAT0, .DP_MSE_SAT1 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT1_BASE_IDX + mmDPid_DP_MSE_SAT1, .DP_MSE_SAT2 = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT2_BASE_IDX + mmDPid_DP_MSE_SAT2, .DP_MSE_SAT_UPDATE = DCN_BASE__INST0_SEGmmDPid_DP_MSE_SAT_UPDATE_BASE_IDX + mmDPid_DP_MSE_SAT_UPDATE, .DP_SEC_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL_BASE_IDX + mmDPid_DP_SEC_CNTL, .DP_VID_STREAM_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_VID_STREAM_CNTL_BASE_IDX + mmDPid_DP_VID_STREAM_CNTL, .DP_DPHY_FAST_TRAINING = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_FAST_TRAINING_BASE_IDX + mmDPid_DP_DPHY_FAST_TRAINING, .DP_SEC_CNTL1 = DCN_BASE__INST0_SEGmmDPid_DP_SEC_CNTL1_BASE_IDX + mmDPid_DP_SEC_CNTL1, .DP_DPHY_BS_SR_SWAP_CNTL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX + mmDPid_DP_DPHY_BS_SR_SWAP_CNTL, .DP_DPHY_HBR2_PATTERN_CONTROL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX + mmDPid_DP_DPHY_HBR2_PATTERN_CONTROL, \ | |||
670 | UNIPHY_DCN2_REG_LIST(phyid).CLOCK_ENABLE = DCN_BASE__INST0_SEGmmSYMCLKphyid_CLOCK_ENABLE_BASE_IDX + mmSYMCLKphyid_CLOCK_ENABLE, .CHANNEL_XBAR_CNTL = DCN_BASE__INST0_SEGmmUNIPHYphyid_CHANNEL_XBAR_CNTL_BASE_IDX + mmUNIPHYphyid_CHANNEL_XBAR_CNTL, \ | |||
671 | DPCS_DCN2_REG_LIST(id).DIG_LANE_ENABLE = DCN_BASE__INST0_SEGmmDIGid_DIG_LANE_ENABLE_BASE_IDX + mmDIGid_DIG_LANE_ENABLE, .TMDS_CTL_BITS = DCN_BASE__INST0_SEGmmDIGid_TMDS_CTL_BITS_BASE_IDX + mmDIGid_TMDS_CTL_BITS, .RDPCSTX_PHY_CNTL3 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL3_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL3, .RDPCSTX_PHY_CNTL4 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL4_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL4, .RDPCSTX_PHY_CNTL5 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL5_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL5, .RDPCSTX_PHY_CNTL6 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL6_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL6, .RDPCSTX_PHY_CNTL7 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL7_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL7, .RDPCSTX_PHY_CNTL8 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL8_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL8, .RDPCSTX_PHY_CNTL9 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL9_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL9, .RDPCSTX_PHY_CNTL10 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL10_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL10, .RDPCSTX_PHY_CNTL11 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL11_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL11, .RDPCSTX_PHY_CNTL12 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL12_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL12, .RDPCSTX_PHY_CNTL13 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL13_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL13, .RDPCSTX_PHY_CNTL14 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL14_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL14, .RDPCSTX_CNTL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_CNTL_BASE_IDX + mmRDPCSTXid_RDPCSTX_CNTL, .RDPCSTX_CLOCK_CNTL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_CLOCK_CNTL_BASE_IDX + mmRDPCSTXid_RDPCSTX_CLOCK_CNTL, .RDPCSTX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX + mmRDPCSTXid_RDPCSTX_INTERRUPT_CONTROL, .RDPCSTX_PHY_CNTL0 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL0_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL0 , .RDPCSTX_PHY_CNTL2 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_CNTL2_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_CNTL2, .RDPCSTX_PLL_UPDATE_DATA = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX + mmRDPCSTXid_RDPCSTX_PLL_UPDATE_DATA, .RDPCS_TX_CR_ADDR = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCS_TX_CR_ADDR_BASE_IDX + mmRDPCSTXid_RDPCS_TX_CR_ADDR, .RDPCS_TX_CR_DATA = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCS_TX_CR_DATA_BASE_IDX + mmRDPCSTXid_RDPCS_TX_CR_DATA, .RDPCSTX_PHY_FUSE0 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE0_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_FUSE0, .RDPCSTX_PHY_FUSE1 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE1_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_FUSE1, .RDPCSTX_PHY_FUSE2 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE2_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_FUSE2, .RDPCSTX_PHY_FUSE3 = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_FUSE3_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_FUSE3, .DPCSTX_TX_CLOCK_CNTL = DCN_BASE__INST0_SEGmmDPCSTXid_DPCSTX_TX_CLOCK_CNTL_BASE_IDX + mmDPCSTXid_DPCSTX_TX_CLOCK_CNTL, .DPCSTX_TX_CNTL = DCN_BASE__INST0_SEGmmDPCSTXid_DPCSTX_TX_CNTL_BASE_IDX + mmDPCSTXid_DPCSTX_TX_CNTL, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2939, .RDPCSTX_PHY_RX_LD_VAL = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX + mmRDPCSTXid_RDPCSTX_PHY_RX_LD_VAL, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = DCN_BASE__INST0_SEGmmRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX + mmRDPCSTXid_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, \ | |||
672 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id).DP_DPHY_INTERNAL_CTRL = DCN_BASE__INST0_SEGmmDPid_DP_DPHY_INTERNAL_CTRL_BASE_IDX + mmDPid_DP_DPHY_INTERNAL_CTRL \ | |||
673 | } | |||
674 | ||||
675 | static const struct dcn10_link_enc_registers link_enc_regs[] = { | |||
676 | link_regs(0, A)[0] = { .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x210f, .DIG_BE_CNTL = 0x000034C0 + 0x20af, .DIG_BE_EN_CNTL = 0x000034C0 + 0x20b0 , .TMDS_CTL_BITS = 0x000034C0 + 0x20da, .DP_CONFIG = 0x000034C0 + 0x210b, .DP_DPHY_CNTL = 0x000034C0 + 0x2117, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x211d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x211e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2119, .DP_DPHY_SYM1 = 0x000034C0 + 0x211a, .DP_DPHY_SYM2 = 0x000034C0 + 0x211b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2118, .DP_LINK_CNTL = 0x000034C0 + 0x2108, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2113, .DP_MSE_SAT0 = 0x000034C0 + 0x213a, .DP_MSE_SAT1 = 0x000034C0 + 0x213b, .DP_MSE_SAT2 = 0x000034C0 + 0x213c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x213d , .DP_SEC_CNTL = 0x000034C0 + 0x212b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x210c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2124, .DP_SEC_CNTL1 = 0x000034C0 + 0x212c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2144, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2145 , .CLOCK_ENABLE = 0x000000C0 + 0x00a0, .CHANNEL_XBAR_CNTL = 0x000034C0 + 0x286e, .DIG_LANE_ENABLE = 0x000034C0 + 0x20e1, .TMDS_CTL_BITS = 0x000034C0 + 0x20da, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2943 , .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2944, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2945, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2946 , .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2947, .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2948, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2949 , .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x294a, .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x294b, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x294c , .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x294d, .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x294e, .RDPCSTX_CNTL = 0x000034C0 + 0x2930, . RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2931, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2932, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2940 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2942, .RDPCSTX_PLL_UPDATE_DATA = 0x000034C0 + 0x2933, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2934 , .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2935, .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x294f, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2950 , .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2951, .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2952, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2928 , .DPCSTX_TX_CNTL = 0x000034C0 + 0x2929, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2939, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2953, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x293c , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x210f }, | |||
677 | link_regs(1, B)[1] = { .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x220f, .DIG_BE_CNTL = 0x000034C0 + 0x21af, .DIG_BE_EN_CNTL = 0x000034C0 + 0x21b0 , .TMDS_CTL_BITS = 0x000034C0 + 0x21da, .DP_CONFIG = 0x000034C0 + 0x220b, .DP_DPHY_CNTL = 0x000034C0 + 0x2217, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x221d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x221e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2219, .DP_DPHY_SYM1 = 0x000034C0 + 0x221a, .DP_DPHY_SYM2 = 0x000034C0 + 0x221b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2218, .DP_LINK_CNTL = 0x000034C0 + 0x2208, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2213, .DP_MSE_SAT0 = 0x000034C0 + 0x223a, .DP_MSE_SAT1 = 0x000034C0 + 0x223b, .DP_MSE_SAT2 = 0x000034C0 + 0x223c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x223d , .DP_SEC_CNTL = 0x000034C0 + 0x222b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x220c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2224, .DP_SEC_CNTL1 = 0x000034C0 + 0x222c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2244, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2245 , .CLOCK_ENABLE = 0x000000C0 + 0x00a1, .CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2870, .DIG_LANE_ENABLE = 0x000034C0 + 0x21e1, .TMDS_CTL_BITS = 0x000034C0 + 0x21da, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2a1b , .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2a1c, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2a1d, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2a1e , .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2a1f, .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2a20, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2a21 , .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2a22, .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2a23, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2a24 , .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2a25, .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2a26, .RDPCSTX_CNTL = 0x000034C0 + 0x2a08, . RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2a09, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2a0a, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2a18 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2a1a, .RDPCSTX_PLL_UPDATE_DATA = 0x000034C0 + 0x2a0b, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2a0c , .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2a0d, .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2a27, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2a28 , .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2a29, .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2a2a, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2a00 , .DPCSTX_TX_CNTL = 0x000034C0 + 0x2a01, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2939, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2a2b, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2a14 , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x220f }, | |||
678 | link_regs(2, C)[2] = { .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x230f, .DIG_BE_CNTL = 0x000034C0 + 0x22af, .DIG_BE_EN_CNTL = 0x000034C0 + 0x22b0 , .TMDS_CTL_BITS = 0x000034C0 + 0x22da, .DP_CONFIG = 0x000034C0 + 0x230b, .DP_DPHY_CNTL = 0x000034C0 + 0x2317, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x231d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x231e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2319, .DP_DPHY_SYM1 = 0x000034C0 + 0x231a, .DP_DPHY_SYM2 = 0x000034C0 + 0x231b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2318, .DP_LINK_CNTL = 0x000034C0 + 0x2308, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2313, .DP_MSE_SAT0 = 0x000034C0 + 0x233a, .DP_MSE_SAT1 = 0x000034C0 + 0x233b, .DP_MSE_SAT2 = 0x000034C0 + 0x233c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x233d , .DP_SEC_CNTL = 0x000034C0 + 0x232b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x230c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2324, .DP_SEC_CNTL1 = 0x000034C0 + 0x232c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2344, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2345 , .CLOCK_ENABLE = 0x000000C0 + 0x00a2, .CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2872, .DIG_LANE_ENABLE = 0x000034C0 + 0x22e1, .TMDS_CTL_BITS = 0x000034C0 + 0x22da, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2af3 , .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2af4, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2af5, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2af6 , .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2af7, .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2af8, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2af9 , .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2afa, .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2afb, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2afc , .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2afd, .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2afe, .RDPCSTX_CNTL = 0x000034C0 + 0x2ae0, . RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2ae1, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2ae2, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2af0 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2af2, .RDPCSTX_PLL_UPDATE_DATA = 0x000034C0 + 0x2ae3, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2ae4 , .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2ae5, .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2aff, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2b00 , .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2b01, .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2b02, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2ad8 , .DPCSTX_TX_CNTL = 0x000034C0 + 0x2ad9, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2939, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2b03, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2aec , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x230f }, | |||
679 | link_regs(3, D)[3] = { .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x240f, .DIG_BE_CNTL = 0x000034C0 + 0x23af, .DIG_BE_EN_CNTL = 0x000034C0 + 0x23b0 , .TMDS_CTL_BITS = 0x000034C0 + 0x23da, .DP_CONFIG = 0x000034C0 + 0x240b, .DP_DPHY_CNTL = 0x000034C0 + 0x2417, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x241d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x241e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2419, .DP_DPHY_SYM1 = 0x000034C0 + 0x241a, .DP_DPHY_SYM2 = 0x000034C0 + 0x241b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2418, .DP_LINK_CNTL = 0x000034C0 + 0x2408, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2413, .DP_MSE_SAT0 = 0x000034C0 + 0x243a, .DP_MSE_SAT1 = 0x000034C0 + 0x243b, .DP_MSE_SAT2 = 0x000034C0 + 0x243c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x243d , .DP_SEC_CNTL = 0x000034C0 + 0x242b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x240c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2424, .DP_SEC_CNTL1 = 0x000034C0 + 0x242c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2444, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2445 , .CLOCK_ENABLE = 0x000000C0 + 0x00a3, .CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2874, .DIG_LANE_ENABLE = 0x000034C0 + 0x23e1, .TMDS_CTL_BITS = 0x000034C0 + 0x23da, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2bcb , .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2bcc, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2bcd, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2bce , .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2bcf, .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2bd0, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2bd1 , .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2bd2, .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2bd3, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2bd4 , .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2bd5, .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2bd6, .RDPCSTX_CNTL = 0x000034C0 + 0x2bb8, . RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2bb9, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2bba, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2bc8 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2bca, .RDPCSTX_PLL_UPDATE_DATA = 0x000034C0 + 0x2bbb, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2bbc , .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2bbd, .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2bd7, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2bd8 , .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2bd9, .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2bda, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2bb0 , .DPCSTX_TX_CNTL = 0x000034C0 + 0x2bb1, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2939, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2bdb, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2bc4 , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x240f }, | |||
680 | link_regs(4, E)[4] = { .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x250f, .DIG_BE_CNTL = 0x000034C0 + 0x24af, .DIG_BE_EN_CNTL = 0x000034C0 + 0x24b0 , .TMDS_CTL_BITS = 0x000034C0 + 0x24da, .DP_CONFIG = 0x000034C0 + 0x250b, .DP_DPHY_CNTL = 0x000034C0 + 0x2517, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x251d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x251e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2519, .DP_DPHY_SYM1 = 0x000034C0 + 0x251a, .DP_DPHY_SYM2 = 0x000034C0 + 0x251b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2518, .DP_LINK_CNTL = 0x000034C0 + 0x2508, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2513, .DP_MSE_SAT0 = 0x000034C0 + 0x253a, .DP_MSE_SAT1 = 0x000034C0 + 0x253b, .DP_MSE_SAT2 = 0x000034C0 + 0x253c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x253d , .DP_SEC_CNTL = 0x000034C0 + 0x252b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x250c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2524, .DP_SEC_CNTL1 = 0x000034C0 + 0x252c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2544, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2545 , .CLOCK_ENABLE = 0x000000C0 + 0x00a4, .CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2876, .DIG_LANE_ENABLE = 0x000034C0 + 0x24e1, .TMDS_CTL_BITS = 0x000034C0 + 0x24da, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2ca3 , .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2ca4, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2ca5, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2ca6 , .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2ca7, .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2ca8, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2ca9 , .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2caa, .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2cab, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2cac , .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2cad, .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2cae, .RDPCSTX_CNTL = 0x000034C0 + 0x2c90, . RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2c91, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2c92, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2ca0 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2ca2, .RDPCSTX_PLL_UPDATE_DATA = 0x000034C0 + 0x2c93, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2c94 , .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2c95, .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2caf, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2cb0 , .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2cb1, .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2cb2, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2c88 , .DPCSTX_TX_CNTL = 0x000034C0 + 0x2c89, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2939, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2cb3, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2c9c , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x250f }, | |||
681 | link_regs(5, F)[5] = { .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x260f, .DIG_BE_CNTL = 0x000034C0 + 0x25af, .DIG_BE_EN_CNTL = 0x000034C0 + 0x25b0 , .TMDS_CTL_BITS = 0x000034C0 + 0x25da, .DP_CONFIG = 0x000034C0 + 0x260b, .DP_DPHY_CNTL = 0x000034C0 + 0x2617, .DP_DPHY_PRBS_CNTL = 0x000034C0 + 0x261d, .DP_DPHY_SCRAM_CNTL = 0x000034C0 + 0x261e , .DP_DPHY_SYM0 = 0x000034C0 + 0x2619, .DP_DPHY_SYM1 = 0x000034C0 + 0x261a, .DP_DPHY_SYM2 = 0x000034C0 + 0x261b, .DP_DPHY_TRAINING_PATTERN_SEL = 0x000034C0 + 0x2618, .DP_LINK_CNTL = 0x000034C0 + 0x2608, . DP_LINK_FRAMING_CNTL = 0x000034C0 + 0x2613, .DP_MSE_SAT0 = 0x000034C0 + 0x263a, .DP_MSE_SAT1 = 0x000034C0 + 0x263b, .DP_MSE_SAT2 = 0x000034C0 + 0x263c, .DP_MSE_SAT_UPDATE = 0x000034C0 + 0x263d , .DP_SEC_CNTL = 0x000034C0 + 0x262b, .DP_VID_STREAM_CNTL = 0x000034C0 + 0x260c, .DP_DPHY_FAST_TRAINING = 0x000034C0 + 0x2624, .DP_SEC_CNTL1 = 0x000034C0 + 0x262c, .DP_DPHY_BS_SR_SWAP_CNTL = 0x000034C0 + 0x2644, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x000034C0 + 0x2645 , .CLOCK_ENABLE = 0x000000C0 + 0x00a5, .CHANNEL_XBAR_CNTL = 0x000034C0 + 0x2878, .DIG_LANE_ENABLE = 0x000034C0 + 0x25e1, .TMDS_CTL_BITS = 0x000034C0 + 0x25da, .RDPCSTX_PHY_CNTL3 = 0x000034C0 + 0x2d7b , .RDPCSTX_PHY_CNTL4 = 0x000034C0 + 0x2d7c, .RDPCSTX_PHY_CNTL5 = 0x000034C0 + 0x2d7d, .RDPCSTX_PHY_CNTL6 = 0x000034C0 + 0x2d7e , .RDPCSTX_PHY_CNTL7 = 0x000034C0 + 0x2d7f, .RDPCSTX_PHY_CNTL8 = 0x000034C0 + 0x2d80, .RDPCSTX_PHY_CNTL9 = 0x000034C0 + 0x2d81 , .RDPCSTX_PHY_CNTL10 = 0x000034C0 + 0x2d82, .RDPCSTX_PHY_CNTL11 = 0x000034C0 + 0x2d83, .RDPCSTX_PHY_CNTL12 = 0x000034C0 + 0x2d84 , .RDPCSTX_PHY_CNTL13 = 0x000034C0 + 0x2d85, .RDPCSTX_PHY_CNTL14 = 0x000034C0 + 0x2d86, .RDPCSTX_CNTL = 0x000034C0 + 0x2d68, . RDPCSTX_CLOCK_CNTL = 0x000034C0 + 0x2d69, .RDPCSTX_INTERRUPT_CONTROL = 0x000034C0 + 0x2d6a, .RDPCSTX_PHY_CNTL0 = 0x000034C0 + 0x2d78 , .RDPCSTX_PHY_CNTL2 = 0x000034C0 + 0x2d7a, .RDPCSTX_PLL_UPDATE_DATA = 0x000034C0 + 0x2d6b, .RDPCS_TX_CR_ADDR = 0x000034C0 + 0x2d6c , .RDPCS_TX_CR_DATA = 0x000034C0 + 0x2d6d, .RDPCSTX_PHY_FUSE0 = 0x000034C0 + 0x2d87, .RDPCSTX_PHY_FUSE1 = 0x000034C0 + 0x2d88 , .RDPCSTX_PHY_FUSE2 = 0x000034C0 + 0x2d89, .RDPCSTX_PHY_FUSE3 = 0x000034C0 + 0x2d8a, .DPCSTX_TX_CLOCK_CNTL = 0x000034C0 + 0x2d60 , .DPCSTX_TX_CNTL = 0x000034C0 + 0x2d61, .RDPCSTX0_RDPCSTX_SCRATCH = 0x000034C0 + 0x2939, .RDPCSTX_PHY_RX_LD_VAL = 0x000034C0 + 0x2d8b, .RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG = 0x000034C0 + 0x2d74 , .DP_DPHY_INTERNAL_CTRL = 0x000034C0 + 0x260f } | |||
682 | }; | |||
683 | ||||
684 | static const struct dcn10_link_enc_shift le_shift = { | |||
685 | LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT).DIG_ENABLE = 0x0, .DIG_HPD_SELECT = 0x1c, .DIG_MODE = 0x10, . DIG_FE_SOURCE_SELECT = 0x8, .TMDS_CTL0 = 0x0, .DPHY_BYPASS = 0x10 , .DPHY_ATEST_SEL_LANE0 = 0x0, .DPHY_ATEST_SEL_LANE1 = 0x1, . DPHY_ATEST_SEL_LANE2 = 0x2, .DPHY_ATEST_SEL_LANE3 = 0x3, .DPHY_PRBS_EN = 0x0, .DPHY_PRBS_SEL = 0x4, .DPHY_SYM1 = 0x0, .DPHY_SYM2 = 0xa , .DPHY_SYM3 = 0x14, .DPHY_SYM4 = 0x0, .DPHY_SYM5 = 0xa, .DPHY_SYM6 = 0x14, .DPHY_SYM7 = 0x0, .DPHY_SYM8 = 0xa, .DPHY_SCRAMBLER_BS_COUNT = 0x8, .DPHY_SCRAMBLER_ADVANCE = 0x4, .DPHY_RX_FAST_TRAINING_CAPABLE = 0x0, .DPHY_LOAD_BS_COUNT = 0x0, .DPHY_TRAINING_PATTERN_SEL = 0x0, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x0, .DP_LINK_TRAINING_COMPLETE = 0x4, .DP_IDLE_BS_INTERVAL = 0x0, .DP_VBID_DISABLE = 0x18, . DP_VID_ENHANCED_FRAME_MODE = 0x1c, .DP_VID_STREAM_ENABLE = 0x0 , .DP_UDI_LANES = 0x0, .DP_SEC_GSP0_LINE_NUM = 0x10, .DP_SEC_GSP0_PRIORITY = 0x4, .DP_MSE_SAT_SRC0 = 0x0, .DP_MSE_SAT_SRC1 = 0x10, .DP_MSE_SAT_SLOT_COUNT0 = 0x8, .DP_MSE_SAT_SLOT_COUNT1 = 0x18, .DP_MSE_SAT_SRC2 = 0x0 , .DP_MSE_SAT_SRC3 = 0x10, .DP_MSE_SAT_SLOT_COUNT2 = 0x8, .DP_MSE_SAT_SLOT_COUNT3 = 0x18, .DP_MSE_SAT_UPDATE = 0x0, .DP_MSE_16_MTP_KEEPOUT = 0x8 , .AUX_HPD_SEL = 0x14, .AUX_LS_READ_EN = 0x8, .AUX_RX_RECEIVE_WINDOW = 0x8, .DC_HPD_EN = 0x1c, .DPHY_FEC_EN = 0x4, .DPHY_FEC_READY_SHADOW = 0x5, .DPHY_FEC_ACTIVE_STATUS = 0x6, .DIG_LANE0EN = 0x0, .DIG_LANE1EN = 0x1, .DIG_LANE2EN = 0x2, .DIG_LANE3EN = 0x3, .DIG_CLK_EN = 0x8, .TMDS_CTL0 = 0x0, .SYMCLKA_CLOCK_ENABLE = 0x0, .UNIPHY_LINK_ENABLE = 0x1c, .UNIPHY_CHANNEL0_XBAR_SOURCE = 0x0, .UNIPHY_CHANNEL1_XBAR_SOURCE = 0x8, .UNIPHY_CHANNEL2_XBAR_SOURCE = 0x10, .UNIPHY_CHANNEL3_XBAR_SOURCE = 0x18, .AUX_RX_START_WINDOW = 0x4, .AUX_RX_HALF_SYM_DETECT_LEN = 0xc, .AUX_RX_TRANSITION_FILTER_EN = 0x10, .AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x11, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = 0x12, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = 0x13, .AUX_RX_PHASE_DETECT_LEN = 0x14, .AUX_RX_DETECTION_THRESHOLD = 0x1c, .AUX_TX_PRECHARGE_LEN = 0x0, .AUX_TX_PRECHARGE_SYMBOLS = 0x8, .AUX_MODE_DET_CHECK_DELAY = 0x10, .AUX_RX_PRECHARGE_SKIP = 0x0, .AUX_RX_TIMEOUT_LEN = 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf,\ | |||
686 | DPCS_DCN2_MASK_SH_LIST(__SHIFT).RDPCS_PHY_DP_TX0_CLK_RDY = 0x2, .RDPCS_PHY_DP_TX0_DATA_EN = 0x3 , .RDPCS_PHY_DP_TX1_CLK_RDY = 0xa, .RDPCS_PHY_DP_TX1_DATA_EN = 0xb, .RDPCS_PHY_DP_TX2_CLK_RDY = 0x12, .RDPCS_PHY_DP_TX2_DATA_EN = 0x13, .RDPCS_PHY_DP_TX3_CLK_RDY = 0x1a, .RDPCS_PHY_DP_TX3_DATA_EN = 0x1b, .RDPCS_PHY_DP_TX0_TERM_CTRL = 0x0, .RDPCS_PHY_DP_TX1_TERM_CTRL = 0x8, .RDPCS_PHY_DP_TX2_TERM_CTRL = 0x10, .RDPCS_PHY_DP_TX3_TERM_CTRL = 0x18, .RDPCS_PHY_DP_MPLLB_MULTIPLIER = 0x4, .RDPCS_PHY_DP_TX0_WIDTH = 0x4, .RDPCS_PHY_DP_TX0_RATE = 0x1, .RDPCS_PHY_DP_TX1_WIDTH = 0xc, .RDPCS_PHY_DP_TX1_RATE = 0x9, .RDPCS_PHY_DP_TX2_PSTATE = 0x8, .RDPCS_PHY_DP_TX3_PSTATE = 0xc, .RDPCS_PHY_DP_TX2_MPLL_EN = 0xa, .RDPCS_PHY_DP_TX3_MPLL_EN = 0xe, .RDPCS_PHY_DP_MPLLB_FRACN_QUOT = 0x10, .RDPCS_PHY_DP_MPLLB_FRACN_DEN = 0x0, .RDPCS_PHY_DP_MPLLB_SSC_PEAK = 0x0, .RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD = 0x18, .RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE = 0x0, .RDPCS_PHY_DP_MPLLB_FRACN_REM = 0x0, .RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = 0x14, .RDPCS_PHY_HDMI_MPLLB_HDMI_DIV = 0x10, .RDPCS_PHY_DP_MPLLB_SSC_EN = 0x8, .RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN = 0x0, .RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x4, .RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN = 0x2, .RDPCS_PHY_DP_MPLLB_STATE = 0x7, .RDPCS_PHY_DP_MPLLB_DIV_CLK_EN = 0x1c, .RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER = 0x14, .RDPCS_PHY_DP_MPLLB_FRACN_EN = 0x18, .RDPCS_PHY_DP_MPLLB_PMIX_EN = 0x1c, .RDPCS_TX_FIFO_LANE0_EN = 0xc, .RDPCS_TX_FIFO_LANE1_EN = 0xd, .RDPCS_TX_FIFO_LANE2_EN = 0xe, .RDPCS_TX_FIFO_LANE3_EN = 0xf, .RDPCS_TX_FIFO_EN = 0x10, .RDPCS_TX_FIFO_RD_START_DELAY = 0x14, .RDPCS_EXT_REFCLK_EN = 0x0, .RDPCS_SRAMCLK_BYPASS = 0x10 , .RDPCS_SRAMCLK_EN = 0xd, .RDPCS_SRAMCLK_CLOCK_ON = 0xe, .RDPCS_SYMCLK_DIV2_CLOCK_ON = 0xa, .RDPCS_SYMCLK_DIV2_GATE_DIS = 0x8, .RDPCS_SYMCLK_DIV2_EN = 0x9, .RDPCS_PHY_DP_TX0_DISABLE = 0x1, .RDPCS_PHY_DP_TX1_DISABLE = 0x9, .RDPCS_PHY_DP_TX2_DISABLE = 0x11, .RDPCS_PHY_DP_TX3_DISABLE = 0x19, .RDPCS_PHY_DP_TX0_REQ = 0x4, .RDPCS_PHY_DP_TX1_REQ = 0xc, .RDPCS_PHY_DP_TX2_REQ = 0x14, .RDPCS_PHY_DP_TX3_REQ = 0x1c , .RDPCS_PHY_DP_TX0_ACK = 0x5, .RDPCS_PHY_DP_TX1_ACK = 0xd, . RDPCS_PHY_DP_TX2_ACK = 0x15, .RDPCS_PHY_DP_TX3_ACK = 0x1d, .RDPCS_PHY_DP_TX0_RESET = 0x0, .RDPCS_PHY_DP_TX1_RESET = 0x8, .RDPCS_PHY_DP_TX2_RESET = 0x10, .RDPCS_PHY_DP_TX3_RESET = 0x18, .RDPCS_PHY_RESET = 0x0 , .RDPCS_PHY_CR_MUX_SEL = 0x15, .RDPCS_PHY_REF_RANGE = 0x9, . RDPCS_SRAM_BYPASS = 0x1f, .RDPCS_SRAM_EXT_LD_DONE = 0x1d, .RDPCS_PHY_HDMIMODE_ENABLE = 0x8, .RDPCS_SRAM_INIT_DONE = 0x1c, .RDPCS_PHY_DP4_POR = 0x3 , .RDPCS_PLL_UPDATE_DATA = 0x0, .RDPCS_REG_FIFO_ERROR_MASK = 0x10 , .RDPCS_TX_FIFO_ERROR_MASK = 0x14, .RDPCS_DPALT_DISABLE_TOGGLE_MASK = 0x11, .RDPCS_DPALT_4LANE_TOGGLE_MASK = 0x12, .RDPCS_TX_CR_ADDR = 0x0, .RDPCS_TX_CR_DATA = 0x0, .RDPCS_PHY_DP_MPLLB_V2I = 0x12 , .RDPCS_PHY_DP_TX0_EQ_MAIN = 0x0, .RDPCS_PHY_DP_TX0_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX0_EQ_POST = 0xc, .RDPCS_PHY_DP_MPLLB_FREQ_VCO = 0x14, .RDPCS_PHY_DP_MPLLB_CP_INT = 0x12, .RDPCS_PHY_DP_MPLLB_CP_PROP = 0x19, .RDPCS_PHY_DP_TX1_EQ_MAIN = 0x0, .RDPCS_PHY_DP_TX1_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX1_EQ_POST = 0xc, .RDPCS_PHY_DP_TX2_EQ_MAIN = 0x0, .RDPCS_PHY_DP_TX2_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX2_EQ_POST = 0xc, .RDPCS_PHY_DP_TX3_EQ_MAIN = 0x0, .RDPCS_PHY_DCO_FINETUNE = 0x12, .RDPCS_PHY_DCO_RANGE = 0x18, .RDPCS_PHY_DP_TX3_EQ_PRE = 0x6, .RDPCS_PHY_DP_TX3_EQ_POST = 0xc, .DPCS_SYMCLK_CLOCK_ON = 0x2, .DPCS_SYMCLK_GATE_DIS = 0x0, .DPCS_SYMCLK_EN = 0x1, . DPCS_TX_DATA_SWAP = 0xe, .DPCS_TX_DATA_ORDER_INVERT = 0xf, .DPCS_TX_FIFO_EN = 0x10, .DPCS_TX_FIFO_RD_START_DELAY = 0x14, .RDPCS_PHY_RX_REF_LD_VAL = 0x0, .RDPCS_PHY_RX_VCO_LD_VAL = 0x8, .RDPCS_PHY_DPALT_DISABLE_ACK = 0x12, .RDPCS_PHY_DP_TX0_PSTATE = 0x0, .RDPCS_PHY_DP_TX1_PSTATE = 0x4, .RDPCS_PHY_DP_TX0_MPLL_EN = 0x2, .RDPCS_PHY_DP_TX1_MPLL_EN = 0x6, .RDPCS_PHY_DP_REF_CLK_EN = 0x13, .RDPCS_PHY_DP_TX2_WIDTH = 0x14, .RDPCS_PHY_DP_TX2_RATE = 0x11, .RDPCS_PHY_DP_TX3_WIDTH = 0x1c, .RDPCS_PHY_DP_TX3_RATE = 0x19, .UNIPHYA_SOFT_RESET = 0x0, .UNIPHYB_SOFT_RESET = 0x2, .UNIPHYC_SOFT_RESET = 0x4, . UNIPHYD_SOFT_RESET = 0x6, .UNIPHYE_SOFT_RESET = 0x8, .RDPCS_PHY_DPALT_DP4 = 0x10, .RDPCS_PHY_DPALT_DISABLE = 0x11 | |||
687 | }; | |||
688 | ||||
689 | static const struct dcn10_link_enc_mask le_mask = { | |||
690 | LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK).DIG_ENABLE = 0x00000001L, .DIG_HPD_SELECT = 0x70000000L, .DIG_MODE = 0x00070000L, .DIG_FE_SOURCE_SELECT = 0x00007F00L, .TMDS_CTL0 = 0x00000001L, .DPHY_BYPASS = 0x00010000L, .DPHY_ATEST_SEL_LANE0 = 0x00000001L, .DPHY_ATEST_SEL_LANE1 = 0x00000002L, .DPHY_ATEST_SEL_LANE2 = 0x00000004L, .DPHY_ATEST_SEL_LANE3 = 0x00000008L, .DPHY_PRBS_EN = 0x00000001L, .DPHY_PRBS_SEL = 0x00000030L, .DPHY_SYM1 = 0x000003FFL , .DPHY_SYM2 = 0x000FFC00L, .DPHY_SYM3 = 0x3FF00000L, .DPHY_SYM4 = 0x000003FFL, .DPHY_SYM5 = 0x000FFC00L, .DPHY_SYM6 = 0x3FF00000L , .DPHY_SYM7 = 0x000003FFL, .DPHY_SYM8 = 0x000FFC00L, .DPHY_SCRAMBLER_BS_COUNT = 0x0003FF00L, .DPHY_SCRAMBLER_ADVANCE = 0x00000010L, .DPHY_RX_FAST_TRAINING_CAPABLE = 0x00000001L, .DPHY_LOAD_BS_COUNT = 0x000003FFL, .DPHY_TRAINING_PATTERN_SEL = 0x00000003L, .DP_DPHY_HBR2_PATTERN_CONTROL = 0x00000007L, . DP_LINK_TRAINING_COMPLETE = 0x00000010L, .DP_IDLE_BS_INTERVAL = 0x0003FFFFL, .DP_VBID_DISABLE = 0x01000000L, .DP_VID_ENHANCED_FRAME_MODE = 0x10000000L, .DP_VID_STREAM_ENABLE = 0x00000001L, .DP_UDI_LANES = 0x00000003L, .DP_SEC_GSP0_LINE_NUM = 0xFFFF0000L, .DP_SEC_GSP0_PRIORITY = 0x00000010L, .DP_MSE_SAT_SRC0 = 0x00000007L, .DP_MSE_SAT_SRC1 = 0x00070000L, .DP_MSE_SAT_SLOT_COUNT0 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT1 = 0x3F000000L, .DP_MSE_SAT_SRC2 = 0x00000007L, .DP_MSE_SAT_SRC3 = 0x00070000L, .DP_MSE_SAT_SLOT_COUNT2 = 0x00003F00L, .DP_MSE_SAT_SLOT_COUNT3 = 0x3F000000L, .DP_MSE_SAT_UPDATE = 0x00000003L, .DP_MSE_16_MTP_KEEPOUT = 0x00000100L, .AUX_HPD_SEL = 0x00700000L, .AUX_LS_READ_EN = 0x00000100L, .AUX_RX_RECEIVE_WINDOW = 0x00000700L, .DC_HPD_EN = 0x10000000L, .DPHY_FEC_EN = 0x00000010L, .DPHY_FEC_READY_SHADOW = 0x00000020L, .DPHY_FEC_ACTIVE_STATUS = 0x00000040L, .DIG_LANE0EN = 0x00000001L, .DIG_LANE1EN = 0x00000002L, .DIG_LANE2EN = 0x00000004L , .DIG_LANE3EN = 0x00000008L, .DIG_CLK_EN = 0x00000100L, .TMDS_CTL0 = 0x00000001L, .SYMCLKA_CLOCK_ENABLE = 0x00000001L, .UNIPHY_LINK_ENABLE = 0x10000000L, .UNIPHY_CHANNEL0_XBAR_SOURCE = 0x00000003L, . UNIPHY_CHANNEL1_XBAR_SOURCE = 0x00000300L, .UNIPHY_CHANNEL2_XBAR_SOURCE = 0x00030000L, .UNIPHY_CHANNEL3_XBAR_SOURCE = 0x03000000L, . AUX_RX_START_WINDOW = 0x00000070L, .AUX_RX_HALF_SYM_DETECT_LEN = 0x00003000L, .AUX_RX_TRANSITION_FILTER_EN = 0x00010000L, . AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00020000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_START = 0x00040000L, .AUX_RX_ALLOW_BELOW_THRESHOLD_STOP = 0x00080000L , .AUX_RX_PHASE_DETECT_LEN = 0x00300000L, .AUX_RX_DETECTION_THRESHOLD = 0x70000000L, .AUX_TX_PRECHARGE_LEN = 0x0000000FL, .AUX_TX_PRECHARGE_SYMBOLS = 0x00003F00L, .AUX_MODE_DET_CHECK_DELAY = 0x00070000L, .AUX_RX_PRECHARGE_SKIP = 0x000000FFL, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL = 0x00018000L,\ | |||
691 | DPCS_DCN2_MASK_SH_LIST(_MASK).RDPCS_PHY_DP_TX0_CLK_RDY = 0x00000004L, .RDPCS_PHY_DP_TX0_DATA_EN = 0x00000008L, .RDPCS_PHY_DP_TX1_CLK_RDY = 0x00000400L, .RDPCS_PHY_DP_TX1_DATA_EN = 0x00000800L, .RDPCS_PHY_DP_TX2_CLK_RDY = 0x00040000L, .RDPCS_PHY_DP_TX2_DATA_EN = 0x00080000L, .RDPCS_PHY_DP_TX3_CLK_RDY = 0x04000000L, .RDPCS_PHY_DP_TX3_DATA_EN = 0x08000000L, .RDPCS_PHY_DP_TX0_TERM_CTRL = 0x00000007L, .RDPCS_PHY_DP_TX1_TERM_CTRL = 0x00000700L, .RDPCS_PHY_DP_TX2_TERM_CTRL = 0x00070000L, .RDPCS_PHY_DP_TX3_TERM_CTRL = 0x07000000L, .RDPCS_PHY_DP_MPLLB_MULTIPLIER = 0x0000FFF0L, .RDPCS_PHY_DP_TX0_WIDTH = 0x00000030L, .RDPCS_PHY_DP_TX0_RATE = 0x0000000EL, .RDPCS_PHY_DP_TX1_WIDTH = 0x00003000L, .RDPCS_PHY_DP_TX1_RATE = 0x00000E00L, .RDPCS_PHY_DP_TX2_PSTATE = 0x00000300L, .RDPCS_PHY_DP_TX3_PSTATE = 0x00003000L, .RDPCS_PHY_DP_TX2_MPLL_EN = 0x00000400L, .RDPCS_PHY_DP_TX3_MPLL_EN = 0x00004000L, .RDPCS_PHY_DP_MPLLB_FRACN_QUOT = 0xFFFF0000L, .RDPCS_PHY_DP_MPLLB_FRACN_DEN = 0x0000FFFFL, .RDPCS_PHY_DP_MPLLB_SSC_PEAK = 0x000FFFFFL, .RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD = 0x01000000L , .RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE = 0x001FFFFFL, .RDPCS_PHY_DP_MPLLB_FRACN_REM = 0x0000FFFFL, .RDPCS_PHY_DP_REF_CLK_MPLLB_DIV = 0x00700000L , .RDPCS_PHY_HDMI_MPLLB_HDMI_DIV = 0x00070000L, .RDPCS_PHY_DP_MPLLB_SSC_EN = 0x00000100L, .RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN = 0x00000001L , .RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000070L, .RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN = 0x00000004L, .RDPCS_PHY_DP_MPLLB_STATE = 0x00000080L, .RDPCS_PHY_DP_MPLLB_DIV_CLK_EN = 0x10000000L, .RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER = 0x0FF00000L , .RDPCS_PHY_DP_MPLLB_FRACN_EN = 0x01000000L, .RDPCS_PHY_DP_MPLLB_PMIX_EN = 0x10000000L, .RDPCS_TX_FIFO_LANE0_EN = 0x00001000L, .RDPCS_TX_FIFO_LANE1_EN = 0x00002000L, .RDPCS_TX_FIFO_LANE2_EN = 0x00004000L, .RDPCS_TX_FIFO_LANE3_EN = 0x00008000L, .RDPCS_TX_FIFO_EN = 0x00010000L, .RDPCS_TX_FIFO_RD_START_DELAY = 0x00F00000L, .RDPCS_EXT_REFCLK_EN = 0x00000001L, .RDPCS_SRAMCLK_BYPASS = 0x00010000L, .RDPCS_SRAMCLK_EN = 0x00002000L, .RDPCS_SRAMCLK_CLOCK_ON = 0x00004000L, .RDPCS_SYMCLK_DIV2_CLOCK_ON = 0x00000400L, .RDPCS_SYMCLK_DIV2_GATE_DIS = 0x00000100L, .RDPCS_SYMCLK_DIV2_EN = 0x00000200L, .RDPCS_PHY_DP_TX0_DISABLE = 0x00000002L, .RDPCS_PHY_DP_TX1_DISABLE = 0x00000200L, .RDPCS_PHY_DP_TX2_DISABLE = 0x00020000L, .RDPCS_PHY_DP_TX3_DISABLE = 0x02000000L, .RDPCS_PHY_DP_TX0_REQ = 0x00000010L, .RDPCS_PHY_DP_TX1_REQ = 0x00001000L, .RDPCS_PHY_DP_TX2_REQ = 0x00100000L, .RDPCS_PHY_DP_TX3_REQ = 0x10000000L, .RDPCS_PHY_DP_TX0_ACK = 0x00000020L, .RDPCS_PHY_DP_TX1_ACK = 0x00002000L, .RDPCS_PHY_DP_TX2_ACK = 0x00200000L, .RDPCS_PHY_DP_TX3_ACK = 0x20000000L, .RDPCS_PHY_DP_TX0_RESET = 0x00000001L, .RDPCS_PHY_DP_TX1_RESET = 0x00000100L, .RDPCS_PHY_DP_TX2_RESET = 0x00010000L, .RDPCS_PHY_DP_TX3_RESET = 0x01000000L, .RDPCS_PHY_RESET = 0x00000001L, .RDPCS_PHY_CR_MUX_SEL = 0x00200000L, .RDPCS_PHY_REF_RANGE = 0x00003E00L, .RDPCS_SRAM_BYPASS = 0x80000000L, .RDPCS_SRAM_EXT_LD_DONE = 0x20000000L, .RDPCS_PHY_HDMIMODE_ENABLE = 0x00000100L, .RDPCS_SRAM_INIT_DONE = 0x10000000L, .RDPCS_PHY_DP4_POR = 0x00000008L, .RDPCS_PLL_UPDATE_DATA = 0x00000001L, .RDPCS_REG_FIFO_ERROR_MASK = 0x00010000L, .RDPCS_TX_FIFO_ERROR_MASK = 0x00100000L, .RDPCS_DPALT_DISABLE_TOGGLE_MASK = 0x00020000L , .RDPCS_DPALT_4LANE_TOGGLE_MASK = 0x00040000L, .RDPCS_TX_CR_ADDR = 0x0000FFFFL, .RDPCS_TX_CR_DATA = 0x0000FFFFL, .RDPCS_PHY_DP_MPLLB_V2I = 0x000C0000L, .RDPCS_PHY_DP_TX0_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DP_TX0_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX0_EQ_POST = 0x0003F000L, .RDPCS_PHY_DP_MPLLB_FREQ_VCO = 0x00300000L, .RDPCS_PHY_DP_MPLLB_CP_INT = 0x01FC0000L, .RDPCS_PHY_DP_MPLLB_CP_PROP = 0xFE000000L, .RDPCS_PHY_DP_TX1_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DP_TX1_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX1_EQ_POST = 0x0003F000L, .RDPCS_PHY_DP_TX2_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DP_TX2_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX2_EQ_POST = 0x0003F000L, .RDPCS_PHY_DP_TX3_EQ_MAIN = 0x0000003FL, .RDPCS_PHY_DCO_FINETUNE = 0x00FC0000L, .RDPCS_PHY_DCO_RANGE = 0x03000000L, .RDPCS_PHY_DP_TX3_EQ_PRE = 0x00000FC0L, .RDPCS_PHY_DP_TX3_EQ_POST = 0x0003F000L, .DPCS_SYMCLK_CLOCK_ON = 0x00000004L, .DPCS_SYMCLK_GATE_DIS = 0x00000001L, .DPCS_SYMCLK_EN = 0x00000002L, .DPCS_TX_DATA_SWAP = 0x00004000L, .DPCS_TX_DATA_ORDER_INVERT = 0x00008000L, .DPCS_TX_FIFO_EN = 0x00010000L, .DPCS_TX_FIFO_RD_START_DELAY = 0x00F00000L, .RDPCS_PHY_RX_REF_LD_VAL = 0x0000007FL, .RDPCS_PHY_RX_VCO_LD_VAL = 0x001FFF00L, .RDPCS_PHY_DPALT_DISABLE_ACK = 0x00040000L, . RDPCS_PHY_DP_TX0_PSTATE = 0x00000003L, .RDPCS_PHY_DP_TX1_PSTATE = 0x00000030L, .RDPCS_PHY_DP_TX0_MPLL_EN = 0x00000004L, .RDPCS_PHY_DP_TX1_MPLL_EN = 0x00000040L, .RDPCS_PHY_DP_REF_CLK_EN = 0x00080000L, .RDPCS_PHY_DP_TX2_WIDTH = 0x00300000L, .RDPCS_PHY_DP_TX2_RATE = 0x000E0000L, .RDPCS_PHY_DP_TX3_WIDTH = 0x30000000L, .RDPCS_PHY_DP_TX3_RATE = 0x0E000000L, .UNIPHYA_SOFT_RESET = 0x00000001L, .UNIPHYB_SOFT_RESET = 0x00000004L, .UNIPHYC_SOFT_RESET = 0x00000010L, .UNIPHYD_SOFT_RESET = 0x00000040L, .UNIPHYE_SOFT_RESET = 0x00000100L, .RDPCS_PHY_DPALT_DP4 = 0x00010000L, .RDPCS_PHY_DPALT_DISABLE = 0x00020000L | |||
692 | }; | |||
693 | ||||
694 | static const struct dce_panel_cntl_registers panel_cntl_regs[] = { | |||
695 | { DCN_PANEL_CNTL_REG_LIST().PWRSEQ_CNTL = 0x000034C0 + 0x2883, .PWRSEQ_STATE = 0x000034C0 + 0x2884, .PWRSEQ_REF_DIV = 0x000034C0 + 0x2885, .BL_PWM_CNTL = 0x000034C0 + 0x2888, .BL_PWM_CNTL2 = 0x000034C0 + 0x2889, . BL_PWM_PERIOD_CNTL = 0x000034C0 + 0x288a, .BL_PWM_GRP1_REG_LOCK = 0x000034C0 + 0x288b, .BIOS_SCRATCH_2 = 0x00000014 + 0x003a } | |||
696 | }; | |||
697 | ||||
698 | static const struct dce_panel_cntl_shift panel_cntl_shift = { | |||
699 | DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT).LVTMA_BLON = 0x18, .LVTMA_BLON_OVRD = 0x19, .LVTMA_DIGON = 0x10 , .LVTMA_DIGON_OVRD = 0x11, .LVTMA_PWRSEQ_TARGET_STATE = 0x4, .LVTMA_PWRSEQ_TARGET_STATE_R = 0x0, .BL_PWM_REF_DIV = 0x10, . BL_PWM_PERIOD = 0x0, .BL_PWM_PERIOD_BITCNT = 0x10, .BL_ACTIVE_INT_FRAC_CNT = 0x0, .BL_PWM_FRACTIONAL_EN = 0x1e, .BL_PWM_EN = 0x1f, .BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = 0x1f, .BL_PWM_GRP1_REG_LOCK = 0x0, .BL_PWM_GRP1_REG_UPDATE_PENDING = 0x8 | |||
700 | }; | |||
701 | ||||
702 | static const struct dce_panel_cntl_mask panel_cntl_mask = { | |||
703 | DCE_PANEL_CNTL_MASK_SH_LIST(_MASK).LVTMA_BLON = 0x01000000L, .LVTMA_BLON_OVRD = 0x02000000L, .LVTMA_DIGON = 0x00010000L, .LVTMA_DIGON_OVRD = 0x00020000L, .LVTMA_PWRSEQ_TARGET_STATE = 0x00000010L, .LVTMA_PWRSEQ_TARGET_STATE_R = 0x00000001L, . BL_PWM_REF_DIV = 0xFFFF0000L, .BL_PWM_PERIOD = 0x0000FFFFL, . BL_PWM_PERIOD_BITCNT = 0x000F0000L, .BL_ACTIVE_INT_FRAC_CNT = 0x0000FFFFL, .BL_PWM_FRACTIONAL_EN = 0x40000000L, .BL_PWM_EN = 0x80000000L, .BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN = 0x80000000L , .BL_PWM_GRP1_REG_LOCK = 0x00000001L, .BL_PWM_GRP1_REG_UPDATE_PENDING = 0x00000100L | |||
704 | }; | |||
705 | ||||
706 | #define ipp_regs(id)[id] = { .FORMAT_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX + mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX + mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL , .CURSOR0_COLOR0 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX + mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX + mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR_SETTINGS = DCN_BASE__INST0_SEGmmHUBPREQid_CURSOR_SETTINGS_BASE_IDX + mmHUBPREQid_CURSOR_SETTINGS, .CURSOR_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX + mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX + mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX + mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX + mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX + mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX + mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX + mmCURSOR0_id_CURSOR_DST_OFFSET,}\ | |||
707 | [id] = {\ | |||
708 | IPP_REG_LIST_DCN20(id).FORMAT_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX + mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX + mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL , .CURSOR0_COLOR0 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX + mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX + mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR_SETTINGS = DCN_BASE__INST0_SEGmmHUBPREQid_CURSOR_SETTINGS_BASE_IDX + mmHUBPREQid_CURSOR_SETTINGS, .CURSOR_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX + mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX + mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX + mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX + mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX + mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX + mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX + mmCURSOR0_id_CURSOR_DST_OFFSET,\ | |||
709 | } | |||
710 | ||||
711 | static const struct dcn10_ipp_registers ipp_regs[] = { | |||
712 | ipp_regs(0)[0] = { .FORMAT_CONTROL = 0x000034C0 + 0x0cd0, .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0ccf, .CURSOR0_CONTROL = 0x000034C0 + 0x0ce0 , .CURSOR0_COLOR0 = 0x000034C0 + 0x0ce1, .CURSOR0_COLOR1 = 0x000034C0 + 0x0ce2, .CURSOR_SETTINGS = 0x000034C0 + 0x065e, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x067a, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0679, .CURSOR_SIZE = 0x000034C0 + 0x067b, .CURSOR_CONTROL = 0x000034C0 + 0x0678, .CURSOR_POSITION = 0x000034C0 + 0x067c, .CURSOR_HOT_SPOT = 0x000034C0 + 0x067d, .CURSOR_DST_OFFSET = 0x000034C0 + 0x067f,}, | |||
713 | ipp_regs(1)[1] = { .FORMAT_CONTROL = 0x000034C0 + 0x0e3b, .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0e3a, .CURSOR0_CONTROL = 0x000034C0 + 0x0e4b , .CURSOR0_COLOR0 = 0x000034C0 + 0x0e4c, .CURSOR0_COLOR1 = 0x000034C0 + 0x0e4d, .CURSOR_SETTINGS = 0x000034C0 + 0x073a, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0756, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0755, .CURSOR_SIZE = 0x000034C0 + 0x0757, .CURSOR_CONTROL = 0x000034C0 + 0x0754, .CURSOR_POSITION = 0x000034C0 + 0x0758, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0759, .CURSOR_DST_OFFSET = 0x000034C0 + 0x075b,}, | |||
714 | ipp_regs(2)[2] = { .FORMAT_CONTROL = 0x000034C0 + 0x0fa6, .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0fa5, .CURSOR0_CONTROL = 0x000034C0 + 0x0fb6 , .CURSOR0_COLOR0 = 0x000034C0 + 0x0fb7, .CURSOR0_COLOR1 = 0x000034C0 + 0x0fb8, .CURSOR_SETTINGS = 0x000034C0 + 0x0816, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0832, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0831, .CURSOR_SIZE = 0x000034C0 + 0x0833, .CURSOR_CONTROL = 0x000034C0 + 0x0830, .CURSOR_POSITION = 0x000034C0 + 0x0834, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0835, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0837,}, | |||
715 | ipp_regs(3)[3] = { .FORMAT_CONTROL = 0x000034C0 + 0x1111, .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x1110, .CURSOR0_CONTROL = 0x000034C0 + 0x1121 , .CURSOR0_COLOR0 = 0x000034C0 + 0x1122, .CURSOR0_COLOR1 = 0x000034C0 + 0x1123, .CURSOR_SETTINGS = 0x000034C0 + 0x08f2, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x090e, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x090d, .CURSOR_SIZE = 0x000034C0 + 0x090f, .CURSOR_CONTROL = 0x000034C0 + 0x090c, .CURSOR_POSITION = 0x000034C0 + 0x0910, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0911, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0913,}, | |||
716 | ipp_regs(4)[4] = { .FORMAT_CONTROL = 0x000034C0 + 0x35db, .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x35da, .CURSOR0_CONTROL = 0x000034C0 + 0x35eb , .CURSOR0_COLOR0 = 0x000034C0 + 0x35ec, .CURSOR0_COLOR1 = 0x000034C0 + 0x35ed, .CURSOR_SETTINGS = 0x000034C0 + 0x09ce, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x09ea, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x09e9, .CURSOR_SIZE = 0x000034C0 + 0x09eb, .CURSOR_CONTROL = 0x000034C0 + 0x09e8, .CURSOR_POSITION = 0x000034C0 + 0x09ec, .CURSOR_HOT_SPOT = 0x000034C0 + 0x09ed, .CURSOR_DST_OFFSET = 0x000034C0 + 0x09ef,}, | |||
717 | ipp_regs(5)[5] = { .FORMAT_CONTROL = 0x000034C0 + 0x3746, .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x3745, .CURSOR0_CONTROL = 0x000034C0 + 0x3756 , .CURSOR0_COLOR0 = 0x000034C0 + 0x3757, .CURSOR0_COLOR1 = 0x000034C0 + 0x3758, .CURSOR_SETTINGS = 0x000034C0 + 0x0aaa, .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0ac6, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0ac5, .CURSOR_SIZE = 0x000034C0 + 0x0ac7, .CURSOR_CONTROL = 0x000034C0 + 0x0ac4, .CURSOR_POSITION = 0x000034C0 + 0x0ac8, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0ac9, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0acb,}, | |||
718 | }; | |||
719 | ||||
720 | static const struct dcn10_ipp_shift ipp_shift = { | |||
721 | IPP_MASK_SH_LIST_DCN20(__SHIFT).CNVC_SURFACE_PIXEL_FORMAT = 0x0, .CNVC_BYPASS = 0xc, .ALPHA_EN = 0x8, .FORMAT_EXPANSION_MODE = 0x0, .CUR0_MODE = 0x4, .CUR0_COLOR0 = 0x0, .CUR0_COLOR1 = 0x0, .CUR0_EXPANSION_MODE = 0x1, .CUR0_ENABLE = 0x0, .CURSOR0_DST_Y_OFFSET = 0x0, .CURSOR0_CHUNK_HDL_ADJUST = 0x8, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0, .CURSOR_SURFACE_ADDRESS = 0x0, .CURSOR_WIDTH = 0x10, .CURSOR_HEIGHT = 0x0, .CURSOR_MODE = 0x8, .CURSOR_2X_MAGNIFY = 0x4, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK = 0x18, .CURSOR_ENABLE = 0x0, .CURSOR_X_POSITION = 0x10, .CURSOR_Y_POSITION = 0x0, .CURSOR_HOT_SPOT_X = 0x10, .CURSOR_HOT_SPOT_Y = 0x0, . CURSOR_DST_X_OFFSET = 0x0 | |||
722 | }; | |||
723 | ||||
724 | static const struct dcn10_ipp_mask ipp_mask = { | |||
725 | IPP_MASK_SH_LIST_DCN20(_MASK).CNVC_SURFACE_PIXEL_FORMAT = 0x0000007FL, .CNVC_BYPASS = 0x00001000L , .ALPHA_EN = 0x00000100L, .FORMAT_EXPANSION_MODE = 0x00000001L , .CUR0_MODE = 0x00000070L, .CUR0_COLOR0 = 0x00FFFFFFL, .CUR0_COLOR1 = 0x00FFFFFFL, .CUR0_EXPANSION_MODE = 0x00000002L, .CUR0_ENABLE = 0x00000001L, .CURSOR0_DST_Y_OFFSET = 0x000000FFL, .CURSOR0_CHUNK_HDL_ADJUST = 0x00000300L, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, . CURSOR_SURFACE_ADDRESS = 0xFFFFFFFFL, .CURSOR_WIDTH = 0x01FF0000L , .CURSOR_HEIGHT = 0x000001FFL, .CURSOR_MODE = 0x00000700L, . CURSOR_2X_MAGNIFY = 0x00000010L, .CURSOR_PITCH = 0x00030000L, .CURSOR_LINES_PER_CHUNK = 0x1F000000L, .CURSOR_ENABLE = 0x00000001L , .CURSOR_X_POSITION = 0x3FFF0000L, .CURSOR_Y_POSITION = 0x00003FFFL , .CURSOR_HOT_SPOT_X = 0x00FF0000L, .CURSOR_HOT_SPOT_Y = 0x000000FFL , .CURSOR_DST_X_OFFSET = 0x00001FFFL, | |||
726 | }; | |||
727 | ||||
728 | #define opp_regs(id)[id] = { .FMT_BIT_DEPTH_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX + mmFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_CONTROL_BASE_IDX + mmFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX + mmFMTid_FMT_DITHER_RAND_R_SEED, .FMT_DITHER_RAND_G_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX + mmFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX + mmFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = DCN_BASE__INST0_SEGmmFMTid_FMT_CLAMP_CNTL_BASE_IDX + mmFMTid_FMT_CLAMP_CNTL, .FMT_DYNAMIC_EXP_CNTL = DCN_BASE__INST0_SEGmmFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX + mmFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_MAP420_MEMORY_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX + mmFMTid_FMT_MAP420_MEMORY_CONTROL, .OPPBUF_CONTROL = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_CONTROL_BASE_IDX + mmOPPBUFid_OPPBUF_CONTROL, .OPPBUF_3D_PARAMETERS_0 = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX + mmOPPBUFid_OPPBUF_3D_PARAMETERS_0, .OPPBUF_3D_PARAMETERS_1 = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX + mmOPPBUFid_OPPBUF_3D_PARAMETERS_1, .OPP_PIPE_CONTROL = DCN_BASE__INST0_SEGmmOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX + mmOPP_PIPEid_OPP_PIPE_CONTROL, .DPG_CONTROL = DCN_BASE__INST0_SEGmmDPGid_DPG_CONTROL_BASE_IDX + mmDPGid_DPG_CONTROL, .DPG_DIMENSIONS = DCN_BASE__INST0_SEGmmDPGid_DPG_DIMENSIONS_BASE_IDX + mmDPGid_DPG_DIMENSIONS, .DPG_OFFSET_SEGMENT = DCN_BASE__INST0_SEGmmDPGid_DPG_OFFSET_SEGMENT_BASE_IDX + mmDPGid_DPG_OFFSET_SEGMENT, .DPG_COLOUR_B_CB = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_B_CB_BASE_IDX + mmDPGid_DPG_COLOUR_B_CB, .DPG_COLOUR_G_Y = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_G_Y_BASE_IDX + mmDPGid_DPG_COLOUR_G_Y, .DPG_COLOUR_R_CR = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_R_CR_BASE_IDX + mmDPGid_DPG_COLOUR_R_CR, .DPG_RAMP_CONTROL = DCN_BASE__INST0_SEGmmDPGid_DPG_RAMP_CONTROL_BASE_IDX + mmDPGid_DPG_RAMP_CONTROL, .DPG_STATUS = DCN_BASE__INST0_SEGmmDPGid_DPG_STATUS_BASE_IDX + mmDPGid_DPG_STATUS, .FMT_422_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_422_CONTROL_BASE_IDX + mmFMTid_FMT_422_CONTROL, .OPPBUF_CONTROL1 = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_CONTROL1_BASE_IDX + mmOPPBUFid_OPPBUF_CONTROL1,}\ | |||
729 | [id] = {\ | |||
730 | OPP_REG_LIST_DCN20(id).FMT_BIT_DEPTH_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_BIT_DEPTH_CONTROL_BASE_IDX + mmFMTid_FMT_BIT_DEPTH_CONTROL, .FMT_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_CONTROL_BASE_IDX + mmFMTid_FMT_CONTROL, .FMT_DITHER_RAND_R_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_R_SEED_BASE_IDX + mmFMTid_FMT_DITHER_RAND_R_SEED, .FMT_DITHER_RAND_G_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_G_SEED_BASE_IDX + mmFMTid_FMT_DITHER_RAND_G_SEED, .FMT_DITHER_RAND_B_SEED = DCN_BASE__INST0_SEGmmFMTid_FMT_DITHER_RAND_B_SEED_BASE_IDX + mmFMTid_FMT_DITHER_RAND_B_SEED, .FMT_CLAMP_CNTL = DCN_BASE__INST0_SEGmmFMTid_FMT_CLAMP_CNTL_BASE_IDX + mmFMTid_FMT_CLAMP_CNTL, .FMT_DYNAMIC_EXP_CNTL = DCN_BASE__INST0_SEGmmFMTid_FMT_DYNAMIC_EXP_CNTL_BASE_IDX + mmFMTid_FMT_DYNAMIC_EXP_CNTL, .FMT_MAP420_MEMORY_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_MAP420_MEMORY_CONTROL_BASE_IDX + mmFMTid_FMT_MAP420_MEMORY_CONTROL, .OPPBUF_CONTROL = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_CONTROL_BASE_IDX + mmOPPBUFid_OPPBUF_CONTROL, .OPPBUF_3D_PARAMETERS_0 = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_0_BASE_IDX + mmOPPBUFid_OPPBUF_3D_PARAMETERS_0, .OPPBUF_3D_PARAMETERS_1 = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_3D_PARAMETERS_1_BASE_IDX + mmOPPBUFid_OPPBUF_3D_PARAMETERS_1, .OPP_PIPE_CONTROL = DCN_BASE__INST0_SEGmmOPP_PIPEid_OPP_PIPE_CONTROL_BASE_IDX + mmOPP_PIPEid_OPP_PIPE_CONTROL, .DPG_CONTROL = DCN_BASE__INST0_SEGmmDPGid_DPG_CONTROL_BASE_IDX + mmDPGid_DPG_CONTROL, .DPG_DIMENSIONS = DCN_BASE__INST0_SEGmmDPGid_DPG_DIMENSIONS_BASE_IDX + mmDPGid_DPG_DIMENSIONS, .DPG_OFFSET_SEGMENT = DCN_BASE__INST0_SEGmmDPGid_DPG_OFFSET_SEGMENT_BASE_IDX + mmDPGid_DPG_OFFSET_SEGMENT, .DPG_COLOUR_B_CB = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_B_CB_BASE_IDX + mmDPGid_DPG_COLOUR_B_CB, .DPG_COLOUR_G_Y = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_G_Y_BASE_IDX + mmDPGid_DPG_COLOUR_G_Y, .DPG_COLOUR_R_CR = DCN_BASE__INST0_SEGmmDPGid_DPG_COLOUR_R_CR_BASE_IDX + mmDPGid_DPG_COLOUR_R_CR, .DPG_RAMP_CONTROL = DCN_BASE__INST0_SEGmmDPGid_DPG_RAMP_CONTROL_BASE_IDX + mmDPGid_DPG_RAMP_CONTROL, .DPG_STATUS = DCN_BASE__INST0_SEGmmDPGid_DPG_STATUS_BASE_IDX + mmDPGid_DPG_STATUS, .FMT_422_CONTROL = DCN_BASE__INST0_SEGmmFMTid_FMT_422_CONTROL_BASE_IDX + mmFMTid_FMT_422_CONTROL, .OPPBUF_CONTROL1 = DCN_BASE__INST0_SEGmmOPPBUFid_OPPBUF_CONTROL1_BASE_IDX + mmOPPBUFid_OPPBUF_CONTROL1,\ | |||
731 | } | |||
732 | ||||
733 | static const struct dcn20_opp_registers opp_regs[] = { | |||
734 | opp_regs(0)[0] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x1841, .FMT_CONTROL = 0x000034C0 + 0x1840, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x1842, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1843, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x1844, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1845 , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x183f, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x1847, .OPPBUF_CONTROL = 0x000034C0 + 0x1884 , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1885, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x1886, .OPP_PIPE_CONTROL = 0x000034C0 + 0x188c , .DPG_CONTROL = 0x000034C0 + 0x1854, .DPG_DIMENSIONS = 0x000034C0 + 0x1856, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x185a, .DPG_COLOUR_B_CB = 0x000034C0 + 0x1859, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1858 , .DPG_COLOUR_R_CR = 0x000034C0 + 0x1857, .DPG_RAMP_CONTROL = 0x000034C0 + 0x1855, .DPG_STATUS = 0x000034C0 + 0x185b, .FMT_422_CONTROL = 0x000034C0 + 0x1849, .OPPBUF_CONTROL1 = 0x000034C0 + 0x1889 ,}, | |||
735 | opp_regs(1)[1] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x189b, .FMT_CONTROL = 0x000034C0 + 0x189a, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x189c, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x189d, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x189e, .FMT_CLAMP_CNTL = 0x000034C0 + 0x189f , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x1899, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x18a1, .OPPBUF_CONTROL = 0x000034C0 + 0x18de , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x18df, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x18e0, .OPP_PIPE_CONTROL = 0x000034C0 + 0x18e6 , .DPG_CONTROL = 0x000034C0 + 0x18ae, .DPG_DIMENSIONS = 0x000034C0 + 0x18b0, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x18b4, .DPG_COLOUR_B_CB = 0x000034C0 + 0x18b3, .DPG_COLOUR_G_Y = 0x000034C0 + 0x18b2 , .DPG_COLOUR_R_CR = 0x000034C0 + 0x18b1, .DPG_RAMP_CONTROL = 0x000034C0 + 0x18af, .DPG_STATUS = 0x000034C0 + 0x18b5, .FMT_422_CONTROL = 0x000034C0 + 0x18a3, .OPPBUF_CONTROL1 = 0x000034C0 + 0x18e3 ,}, | |||
736 | opp_regs(2)[2] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x18f5, .FMT_CONTROL = 0x000034C0 + 0x18f4, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x18f6, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x18f7, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x18f8, .FMT_CLAMP_CNTL = 0x000034C0 + 0x18f9 , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x18f3, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x18fb, .OPPBUF_CONTROL = 0x000034C0 + 0x1938 , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1939, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x193a, .OPP_PIPE_CONTROL = 0x000034C0 + 0x1940 , .DPG_CONTROL = 0x000034C0 + 0x1908, .DPG_DIMENSIONS = 0x000034C0 + 0x190a, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x190e, .DPG_COLOUR_B_CB = 0x000034C0 + 0x190d, .DPG_COLOUR_G_Y = 0x000034C0 + 0x190c , .DPG_COLOUR_R_CR = 0x000034C0 + 0x190b, .DPG_RAMP_CONTROL = 0x000034C0 + 0x1909, .DPG_STATUS = 0x000034C0 + 0x190f, .FMT_422_CONTROL = 0x000034C0 + 0x18fd, .OPPBUF_CONTROL1 = 0x000034C0 + 0x193d ,}, | |||
737 | opp_regs(3)[3] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x194f, .FMT_CONTROL = 0x000034C0 + 0x194e, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x1950, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1951, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x1952, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1953 , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x194d, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x1955, .OPPBUF_CONTROL = 0x000034C0 + 0x1992 , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1993, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x1994, .OPP_PIPE_CONTROL = 0x000034C0 + 0x199a , .DPG_CONTROL = 0x000034C0 + 0x1962, .DPG_DIMENSIONS = 0x000034C0 + 0x1964, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x1968, .DPG_COLOUR_B_CB = 0x000034C0 + 0x1967, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1966 , .DPG_COLOUR_R_CR = 0x000034C0 + 0x1965, .DPG_RAMP_CONTROL = 0x000034C0 + 0x1963, .DPG_STATUS = 0x000034C0 + 0x1969, .FMT_422_CONTROL = 0x000034C0 + 0x1957, .OPPBUF_CONTROL1 = 0x000034C0 + 0x1997 ,}, | |||
738 | opp_regs(4)[4] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x19a9, .FMT_CONTROL = 0x000034C0 + 0x19a8, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x19aa, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x19ab, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x19ac, .FMT_CLAMP_CNTL = 0x000034C0 + 0x19ad , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x19a7, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x19af, .OPPBUF_CONTROL = 0x000034C0 + 0x19ec , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x19ed, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x19ee, .OPP_PIPE_CONTROL = 0x000034C0 + 0x19f4 , .DPG_CONTROL = 0x000034C0 + 0x19bc, .DPG_DIMENSIONS = 0x000034C0 + 0x19be, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x19c2, .DPG_COLOUR_B_CB = 0x000034C0 + 0x19c1, .DPG_COLOUR_G_Y = 0x000034C0 + 0x19c0 , .DPG_COLOUR_R_CR = 0x000034C0 + 0x19bf, .DPG_RAMP_CONTROL = 0x000034C0 + 0x19bd, .DPG_STATUS = 0x000034C0 + 0x19c3, .FMT_422_CONTROL = 0x000034C0 + 0x19b1, .OPPBUF_CONTROL1 = 0x000034C0 + 0x19f1 ,}, | |||
739 | opp_regs(5)[5] = { .FMT_BIT_DEPTH_CONTROL = 0x000034C0 + 0x1a03, .FMT_CONTROL = 0x000034C0 + 0x1a02, .FMT_DITHER_RAND_R_SEED = 0x000034C0 + 0x1a04, .FMT_DITHER_RAND_G_SEED = 0x000034C0 + 0x1a05, .FMT_DITHER_RAND_B_SEED = 0x000034C0 + 0x1a06, .FMT_CLAMP_CNTL = 0x000034C0 + 0x1a07 , .FMT_DYNAMIC_EXP_CNTL = 0x000034C0 + 0x1a01, .FMT_MAP420_MEMORY_CONTROL = 0x000034C0 + 0x1a09, .OPPBUF_CONTROL = 0x000034C0 + 0x1a46 , .OPPBUF_3D_PARAMETERS_0 = 0x000034C0 + 0x1a47, .OPPBUF_3D_PARAMETERS_1 = 0x000034C0 + 0x1a48, .OPP_PIPE_CONTROL = 0x000034C0 + 0x1a4e , .DPG_CONTROL = 0x000034C0 + 0x1a16, .DPG_DIMENSIONS = 0x000034C0 + 0x1a18, .DPG_OFFSET_SEGMENT = 0x000034C0 + 0x1a1c, .DPG_COLOUR_B_CB = 0x000034C0 + 0x1a1b, .DPG_COLOUR_G_Y = 0x000034C0 + 0x1a1a , .DPG_COLOUR_R_CR = 0x000034C0 + 0x1a19, .DPG_RAMP_CONTROL = 0x000034C0 + 0x1a17, .DPG_STATUS = 0x000034C0 + 0x1a1d, .FMT_422_CONTROL = 0x000034C0 + 0x1a0b, .OPPBUF_CONTROL1 = 0x000034C0 + 0x1a4b ,}, | |||
740 | }; | |||
741 | ||||
742 | static const struct dcn20_opp_shift opp_shift = { | |||
743 | OPP_MASK_SH_LIST_DCN20(__SHIFT).FMT_TRUNCATE_EN = 0x0, .FMT_TRUNCATE_DEPTH = 0x4, .FMT_TRUNCATE_MODE = 0x1, .FMT_SPATIAL_DITHER_EN = 0x8, .FMT_SPATIAL_DITHER_MODE = 0x9, .FMT_SPATIAL_DITHER_DEPTH = 0xb, .FMT_TEMPORAL_DITHER_EN = 0x10, .FMT_HIGHPASS_RANDOM_ENABLE = 0xf, .FMT_FRAME_RANDOM_ENABLE = 0xd, .FMT_RGB_RANDOM_ENABLE = 0xe, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0x8, .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0xc, .FMT_PIXEL_ENCODING = 0x10, .FMT_STEREOSYNC_OVERRIDE = 0x0, .FMT_RAND_R_SEED = 0x0 , .FMT_RAND_G_SEED = 0x0, .FMT_RAND_B_SEED = 0x0, .FMT_CLAMP_DATA_EN = 0x0, .FMT_CLAMP_COLOR_FORMAT = 0x10, .FMT_DYNAMIC_EXP_EN = 0x0, .FMT_DYNAMIC_EXP_MODE = 0x4, .FMT_MAP420MEM_PWR_FORCE = 0x0, .OPPBUF_ACTIVE_WIDTH = 0x0, .OPPBUF_PIXEL_REPETITION = 0x18 , .OPPBUF_3D_VACT_SPACE1_SIZE = 0x0, .OPPBUF_3D_VACT_SPACE2_SIZE = 0xa, .OPP_PIPE_CLOCK_EN = 0x0, .DPG_EN = 0x0, .DPG_MODE = 0x4 , .DPG_DYNAMIC_RANGE = 0x8, .DPG_BIT_DEPTH = 0xc, .DPG_VRES = 0x10, .DPG_HRES = 0x14, .DPG_ACTIVE_WIDTH = 0x10, .DPG_ACTIVE_HEIGHT = 0x0, .DPG_X_OFFSET = 0x0, .DPG_SEGMENT_WIDTH = 0x10, .DPG_COLOUR0_R_CR = 0x0, .DPG_COLOUR1_R_CR = 0x10, .DPG_COLOUR0_B_CB = 0x0, .DPG_COLOUR1_B_CB = 0x10, .DPG_COLOUR0_G_Y = 0x0, .DPG_COLOUR1_G_Y = 0x10, .DPG_RAMP0_OFFSET = 0x0, .DPG_INC0 = 0x18, .DPG_INC1 = 0x1c, .DPG_DOUBLE_BUFFER_PENDING = 0x0, .OPPBUF_DISPLAY_SEGMENTATION = 0x10, .OPPBUF_OVERLAP_PIXEL_NUM = 0x14, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x0 | |||
744 | }; | |||
745 | ||||
746 | static const struct dcn20_opp_mask opp_mask = { | |||
747 | OPP_MASK_SH_LIST_DCN20(_MASK).FMT_TRUNCATE_EN = 0x00000001L, .FMT_TRUNCATE_DEPTH = 0x00000030L , .FMT_TRUNCATE_MODE = 0x00000002L, .FMT_SPATIAL_DITHER_EN = 0x00000100L , .FMT_SPATIAL_DITHER_MODE = 0x00000600L, .FMT_SPATIAL_DITHER_DEPTH = 0x00001800L, .FMT_TEMPORAL_DITHER_EN = 0x00010000L, .FMT_HIGHPASS_RANDOM_ENABLE = 0x00008000L, .FMT_FRAME_RANDOM_ENABLE = 0x00002000L, .FMT_RGB_RANDOM_ENABLE = 0x00004000L, .FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX = 0x00000F00L , .FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP = 0x00003000L, . FMT_PIXEL_ENCODING = 0x00030000L, .FMT_STEREOSYNC_OVERRIDE = 0x00000001L , .FMT_RAND_R_SEED = 0x000000FFL, .FMT_RAND_G_SEED = 0x000000FFL , .FMT_RAND_B_SEED = 0x000000FFL, .FMT_CLAMP_DATA_EN = 0x00000001L , .FMT_CLAMP_COLOR_FORMAT = 0x00070000L, .FMT_DYNAMIC_EXP_EN = 0x00000001L, .FMT_DYNAMIC_EXP_MODE = 0x00000010L, .FMT_MAP420MEM_PWR_FORCE = 0x00000003L, .OPPBUF_ACTIVE_WIDTH = 0x00003FFFL, .OPPBUF_PIXEL_REPETITION = 0x0F000000L, .OPPBUF_3D_VACT_SPACE1_SIZE = 0x000003FFL, .OPPBUF_3D_VACT_SPACE2_SIZE = 0x000FFC00L, .OPP_PIPE_CLOCK_EN = 0x00000001L, .DPG_EN = 0x00000001L , .DPG_MODE = 0x00000070L, .DPG_DYNAMIC_RANGE = 0x00000100L, . DPG_BIT_DEPTH = 0x00003000L, .DPG_VRES = 0x000F0000L, .DPG_HRES = 0x00F00000L, .DPG_ACTIVE_WIDTH = 0x3FFF0000L, .DPG_ACTIVE_HEIGHT = 0x00003FFFL, .DPG_X_OFFSET = 0x00003FFFL, .DPG_SEGMENT_WIDTH = 0x3FFF0000L, .DPG_COLOUR0_R_CR = 0x0000FFFFL, .DPG_COLOUR1_R_CR = 0xFFFF0000L, .DPG_COLOUR0_B_CB = 0x0000FFFFL, .DPG_COLOUR1_B_CB = 0xFFFF0000L, .DPG_COLOUR0_G_Y = 0x0000FFFFL, .DPG_COLOUR1_G_Y = 0xFFFF0000L, .DPG_RAMP0_OFFSET = 0x0000FFFFL, .DPG_INC0 = 0x0F000000L , .DPG_INC1 = 0xF0000000L, .DPG_DOUBLE_BUFFER_PENDING = 0x00000001L , .OPPBUF_DISPLAY_SEGMENTATION = 0x00070000L, .OPPBUF_OVERLAP_PIXEL_NUM = 0x00F00000L, .FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT = 0x00000001L | |||
748 | }; | |||
749 | ||||
750 | #define aux_engine_regs(id)[id] = { .AUX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX + mmDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_ARB_CONTROL_BASE_IDX + mmDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_DATA_BASE_IDX + mmDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_CONTROL_BASE_IDX + mmDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX + mmDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX + mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_SW_STATUS = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_STATUS_BASE_IDX + mmDP_AUXid_AUX_SW_STATUS, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, .AUX_RESET_MASK = 0x00000010L, }\ | |||
751 | [id] = {\ | |||
752 | AUX_COMMON_REG_LIST0(id).AUX_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_CONTROL_BASE_IDX + mmDP_AUXid_AUX_CONTROL, .AUX_ARB_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_ARB_CONTROL_BASE_IDX + mmDP_AUXid_AUX_ARB_CONTROL, .AUX_SW_DATA = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_DATA_BASE_IDX + mmDP_AUXid_AUX_SW_DATA, .AUX_SW_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_CONTROL_BASE_IDX + mmDP_AUXid_AUX_SW_CONTROL, .AUX_INTERRUPT_CONTROL = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_INTERRUPT_CONTROL_BASE_IDX + mmDP_AUXid_AUX_INTERRUPT_CONTROL, .AUX_DPHY_RX_CONTROL1 = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_DPHY_RX_CONTROL1_BASE_IDX + mmDP_AUXid_AUX_DPHY_RX_CONTROL1, .AUX_SW_STATUS = DCN_BASE__INST0_SEGmmDP_AUXid_AUX_SW_STATUS_BASE_IDX + mmDP_AUXid_AUX_SW_STATUS, \ | |||
753 | .AUXN_IMPCAL = 0, \ | |||
754 | .AUXP_IMPCAL = 0, \ | |||
755 | .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK0x00000010L, \ | |||
756 | } | |||
757 | ||||
758 | static const struct dce110_aux_registers aux_engine_regs[] = { | |||
759 | aux_engine_regs(0)[0] = { .AUX_CONTROL = 0x000034C0 + 0x1f50, .AUX_ARB_CONTROL = 0x000034C0 + 0x1f52, .AUX_SW_DATA = 0x000034C0 + 0x1f56, .AUX_SW_CONTROL = 0x000034C0 + 0x1f51, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1f53, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f5b, .AUX_SW_STATUS = 0x000034C0 + 0x1f54, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | |||
760 | aux_engine_regs(1)[1] = { .AUX_CONTROL = 0x000034C0 + 0x1f6c, .AUX_ARB_CONTROL = 0x000034C0 + 0x1f6e, .AUX_SW_DATA = 0x000034C0 + 0x1f72, .AUX_SW_CONTROL = 0x000034C0 + 0x1f6d, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1f6f, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f77, .AUX_SW_STATUS = 0x000034C0 + 0x1f70, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | |||
761 | aux_engine_regs(2)[2] = { .AUX_CONTROL = 0x000034C0 + 0x1f88, .AUX_ARB_CONTROL = 0x000034C0 + 0x1f8a, .AUX_SW_DATA = 0x000034C0 + 0x1f8e, .AUX_SW_CONTROL = 0x000034C0 + 0x1f89, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1f8b, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1f93, .AUX_SW_STATUS = 0x000034C0 + 0x1f8c, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | |||
762 | aux_engine_regs(3)[3] = { .AUX_CONTROL = 0x000034C0 + 0x1fa4, .AUX_ARB_CONTROL = 0x000034C0 + 0x1fa6, .AUX_SW_DATA = 0x000034C0 + 0x1faa, .AUX_SW_CONTROL = 0x000034C0 + 0x1fa5, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1fa7, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1faf, .AUX_SW_STATUS = 0x000034C0 + 0x1fa8, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | |||
763 | aux_engine_regs(4)[4] = { .AUX_CONTROL = 0x000034C0 + 0x1fc0, .AUX_ARB_CONTROL = 0x000034C0 + 0x1fc2, .AUX_SW_DATA = 0x000034C0 + 0x1fc6, .AUX_SW_CONTROL = 0x000034C0 + 0x1fc1, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1fc3, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fcb, .AUX_SW_STATUS = 0x000034C0 + 0x1fc4, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, }, | |||
764 | aux_engine_regs(5)[5] = { .AUX_CONTROL = 0x000034C0 + 0x1fdc, .AUX_ARB_CONTROL = 0x000034C0 + 0x1fde, .AUX_SW_DATA = 0x000034C0 + 0x1fe2, .AUX_SW_CONTROL = 0x000034C0 + 0x1fdd, .AUX_INTERRUPT_CONTROL = 0x000034C0 + 0x1fdf, .AUX_DPHY_RX_CONTROL1 = 0x000034C0 + 0x1fe7, .AUX_SW_STATUS = 0x000034C0 + 0x1fe0, .AUXN_IMPCAL = 0, .AUXP_IMPCAL = 0, . AUX_RESET_MASK = 0x00000010L, } | |||
765 | }; | |||
766 | ||||
767 | #define tf_regs(id)[id] = { .CM_GAMUT_REMAP_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX + mmCMid_CM_GAMUT_REMAP_CONTROL, .CM_GAMUT_REMAP_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C11_C12, .CM_GAMUT_REMAP_C13_C14 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C13_C14, .CM_GAMUT_REMAP_C21_C22 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C21_C22, .CM_GAMUT_REMAP_C23_C24 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C23_C24, .CM_GAMUT_REMAP_C31_C32 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C31_C32, .CM_GAMUT_REMAP_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C33_C34, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = DCN_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX + mmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = DCN_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX + mmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, .OTG_H_BLANK = DCN_BASE__INST0_SEGmmDSCLid_OTG_H_BLANK_BASE_IDX + mmDSCLid_OTG_H_BLANK, .OTG_V_BLANK = DCN_BASE__INST0_SEGmmDSCLid_OTG_V_BLANK_BASE_IDX + mmDSCLid_OTG_V_BLANK, .SCL_MODE = DCN_BASE__INST0_SEGmmDSCLid_SCL_MODE_BASE_IDX + mmDSCLid_SCL_MODE, .LB_DATA_FORMAT = DCN_BASE__INST0_SEGmmDSCLid_LB_DATA_FORMAT_BASE_IDX + mmDSCLid_LB_DATA_FORMAT, .LB_MEMORY_CTRL = DCN_BASE__INST0_SEGmmDSCLid_LB_MEMORY_CTRL_BASE_IDX + mmDSCLid_LB_MEMORY_CTRL, .DSCL_AUTOCAL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_AUTOCAL_BASE_IDX + mmDSCLid_DSCL_AUTOCAL, .SCL_BLACK_OFFSET = DCN_BASE__INST0_SEGmmDSCLid_SCL_BLACK_OFFSET_BASE_IDX + mmDSCLid_SCL_BLACK_OFFSET, .SCL_TAP_CONTROL = DCN_BASE__INST0_SEGmmDSCLid_SCL_TAP_CONTROL_BASE_IDX + mmDSCLid_SCL_TAP_CONTROL, .SCL_COEF_RAM_TAP_SELECT = DCN_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX + mmDSCLid_SCL_COEF_RAM_TAP_SELECT, .SCL_COEF_RAM_TAP_DATA = DCN_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX + mmDSCLid_SCL_COEF_RAM_TAP_DATA, .DSCL_2TAP_CONTROL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_2TAP_CONTROL_BASE_IDX + mmDSCLid_DSCL_2TAP_CONTROL, .MPC_SIZE = DCN_BASE__INST0_SEGmmDSCLid_MPC_SIZE_BASE_IDX + mmDSCLid_MPC_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX + mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_SCALE_RATIO_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX + mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C, .SCL_VERT_FILTER_SCALE_RATIO_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C, .SCL_HORZ_FILTER_INIT = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX + mmDSCLid_SCL_HORZ_FILTER_INIT, .SCL_HORZ_FILTER_INIT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX + mmDSCLid_SCL_HORZ_FILTER_INIT_C, .SCL_VERT_FILTER_INIT = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_INIT, .SCL_VERT_FILTER_INIT_BOT = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BOT_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_INIT_BOT, .SCL_VERT_FILTER_INIT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_INIT_C, .SCL_VERT_FILTER_INIT_BOT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_INIT_BOT_C, .RECOUT_START = DCN_BASE__INST0_SEGmmDSCLid_RECOUT_START_BASE_IDX + mmDSCLid_RECOUT_START, .RECOUT_SIZE = DCN_BASE__INST0_SEGmmDSCLid_RECOUT_SIZE_BASE_IDX + mmDSCLid_RECOUT_SIZE, .CM_ICSC_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_CONTROL_BASE_IDX + mmCMid_CM_ICSC_CONTROL, .CM_ICSC_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_C11_C12_BASE_IDX + mmCMid_CM_ICSC_C11_C12, .CM_ICSC_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_C33_C34_BASE_IDX + mmCMid_CM_ICSC_C33_C34, .CM_DGAM_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX + mmCMid_CM_DGAM_RAMB_START_CNTL_B, .CM_DGAM_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX + mmCMid_CM_DGAM_RAMB_START_CNTL_G, .CM_DGAM_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX + mmCMid_CM_DGAM_RAMB_START_CNTL_R, .CM_DGAM_RAMB_SLOPE_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX + mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_B, .CM_DGAM_RAMB_SLOPE_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX + mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_G, .CM_DGAM_RAMB_SLOPE_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX + mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_R, .CM_DGAM_RAMB_END_CNTL1_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL1_B, .CM_DGAM_RAMB_END_CNTL2_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL2_B, .CM_DGAM_RAMB_END_CNTL1_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL1_G, .CM_DGAM_RAMB_END_CNTL2_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL2_G, .CM_DGAM_RAMB_END_CNTL1_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL1_R, .CM_DGAM_RAMB_END_CNTL2_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL2_R, .CM_DGAM_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_REGION_0_1_BASE_IDX + mmCMid_CM_DGAM_RAMB_REGION_0_1, .CM_DGAM_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_REGION_14_15_BASE_IDX + mmCMid_CM_DGAM_RAMB_REGION_14_15, .CM_DGAM_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX + mmCMid_CM_DGAM_RAMA_START_CNTL_B, .CM_DGAM_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX + mmCMid_CM_DGAM_RAMA_START_CNTL_G, .CM_DGAM_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX + mmCMid_CM_DGAM_RAMA_START_CNTL_R, .CM_DGAM_RAMA_SLOPE_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX + mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_B, .CM_DGAM_RAMA_SLOPE_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX + mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_G, .CM_DGAM_RAMA_SLOPE_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX + mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_R, .CM_DGAM_RAMA_END_CNTL1_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL1_B, .CM_DGAM_RAMA_END_CNTL2_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL2_B, .CM_DGAM_RAMA_END_CNTL1_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL1_G, .CM_DGAM_RAMA_END_CNTL2_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL2_G, .CM_DGAM_RAMA_END_CNTL1_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL1_R, .CM_DGAM_RAMA_END_CNTL2_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL2_R, .CM_DGAM_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_REGION_0_1_BASE_IDX + mmCMid_CM_DGAM_RAMA_REGION_0_1, .CM_DGAM_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_REGION_14_15_BASE_IDX + mmCMid_CM_DGAM_RAMA_REGION_14_15, .CM_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmCMid_CM_MEM_PWR_CTRL_BASE_IDX + mmCMid_CM_MEM_PWR_CTRL, .CM_DGAM_LUT_WRITE_EN_MASK = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX + mmCMid_CM_DGAM_LUT_WRITE_EN_MASK, .CM_DGAM_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_INDEX_BASE_IDX + mmCMid_CM_DGAM_LUT_INDEX, .CM_DGAM_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_DATA_BASE_IDX + mmCMid_CM_DGAM_LUT_DATA, .CM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_CONTROL_BASE_IDX + mmCMid_CM_CONTROL, .CM_DGAM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_CONTROL_BASE_IDX + mmCMid_CM_DGAM_CONTROL, .CM_TEST_DEBUG_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_TEST_DEBUG_INDEX_BASE_IDX + mmCMid_CM_TEST_DEBUG_INDEX, .CM_TEST_DEBUG_DATA = DCN_BASE__INST0_SEGmmCMid_CM_TEST_DEBUG_DATA_BASE_IDX + mmCMid_CM_TEST_DEBUG_DATA, .FORMAT_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX + mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX + mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL , .CURSOR0_COLOR0 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX + mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX + mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR0_FP_SCALE_BIAS = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX + mmCNVC_CURid_CURSOR0_FP_SCALE_BIAS, .DPP_CONTROL = DCN_BASE__INST0_SEGmmDPP_TOPid_DPP_CONTROL_BASE_IDX + mmDPP_TOPid_DPP_CONTROL, .CM_HDR_MULT_COEF = DCN_BASE__INST0_SEGmmCMid_CM_HDR_MULT_COEF_BASE_IDX + mmCMid_CM_HDR_MULT_COEF, .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_CONTROL_BASE_IDX + mmCMid_CM_BLNDGAM_CONTROL, .CM_BLNDGAM_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_START_CNTL_B, .CM_BLNDGAM_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_START_CNTL_G, .CM_BLNDGAM_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_START_CNTL_R, .CM_BLNDGAM_RAMB_END_CNTL1_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B, .CM_BLNDGAM_RAMB_END_CNTL2_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B, .CM_BLNDGAM_RAMB_END_CNTL1_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G, .CM_BLNDGAM_RAMB_END_CNTL2_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G, .CM_BLNDGAM_RAMB_END_CNTL1_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R, .CM_BLNDGAM_RAMB_END_CNTL2_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R, .CM_BLNDGAM_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_0_1, .CM_BLNDGAM_RAMB_REGION_2_3 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_2_3, .CM_BLNDGAM_RAMB_REGION_4_5 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_4_5, .CM_BLNDGAM_RAMB_REGION_6_7 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_6_7, .CM_BLNDGAM_RAMB_REGION_8_9 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_8_9, .CM_BLNDGAM_RAMB_REGION_10_11 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_10_11, .CM_BLNDGAM_RAMB_REGION_12_13 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_12_13, .CM_BLNDGAM_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_14_15, .CM_BLNDGAM_RAMB_REGION_16_17 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_16_17, .CM_BLNDGAM_RAMB_REGION_18_19 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_18_19, .CM_BLNDGAM_RAMB_REGION_20_21 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_20_21, .CM_BLNDGAM_RAMB_REGION_22_23 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_22_23, .CM_BLNDGAM_RAMB_REGION_24_25 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_24_25, .CM_BLNDGAM_RAMB_REGION_26_27 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_26_27, .CM_BLNDGAM_RAMB_REGION_28_29 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_28_29, .CM_BLNDGAM_RAMB_REGION_30_31 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_30_31, .CM_BLNDGAM_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_32_33, .CM_BLNDGAM_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_START_CNTL_B, .CM_BLNDGAM_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_START_CNTL_G, .CM_BLNDGAM_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_START_CNTL_R, .CM_BLNDGAM_RAMA_END_CNTL1_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B, .CM_BLNDGAM_RAMA_END_CNTL2_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B, .CM_BLNDGAM_RAMA_END_CNTL1_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G, .CM_BLNDGAM_RAMA_END_CNTL2_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G, .CM_BLNDGAM_RAMA_END_CNTL1_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R, .CM_BLNDGAM_RAMA_END_CNTL2_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R, .CM_BLNDGAM_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_0_1, .CM_BLNDGAM_RAMA_REGION_2_3 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_2_3, .CM_BLNDGAM_RAMA_REGION_4_5 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_4_5, .CM_BLNDGAM_RAMA_REGION_6_7 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_6_7, .CM_BLNDGAM_RAMA_REGION_8_9 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_8_9, .CM_BLNDGAM_RAMA_REGION_10_11 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_10_11, .CM_BLNDGAM_RAMA_REGION_12_13 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_12_13, .CM_BLNDGAM_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_14_15, .CM_BLNDGAM_RAMA_REGION_16_17 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_16_17, .CM_BLNDGAM_RAMA_REGION_18_19 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_18_19, .CM_BLNDGAM_RAMA_REGION_20_21 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_20_21, .CM_BLNDGAM_RAMA_REGION_22_23 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_22_23, .CM_BLNDGAM_RAMA_REGION_24_25 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_24_25, .CM_BLNDGAM_RAMA_REGION_26_27 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_26_27, .CM_BLNDGAM_RAMA_REGION_28_29 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_28_29, .CM_BLNDGAM_RAMA_REGION_30_31 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_30_31, .CM_BLNDGAM_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_32_33, .CM_BLNDGAM_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_INDEX_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_INDEX , .CM_BLNDGAM_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_DATA_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_DATA, .CM_3DLUT_MODE = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_MODE_BASE_IDX + mmCMid_CM_3DLUT_MODE, .CM_3DLUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_INDEX_BASE_IDX + mmCMid_CM_3DLUT_INDEX, .CM_3DLUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_BASE_IDX + mmCMid_CM_3DLUT_DATA, .CM_3DLUT_DATA_30BIT = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_30BIT_BASE_IDX + mmCMid_CM_3DLUT_DATA_30BIT, .CM_3DLUT_READ_WRITE_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX + mmCMid_CM_3DLUT_READ_WRITE_CONTROL, .CM_SHAPER_LUT_WRITE_EN_MASK = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX + mmCMid_CM_SHAPER_LUT_WRITE_EN_MASK, .CM_SHAPER_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_CONTROL_BASE_IDX + mmCMid_CM_SHAPER_CONTROL, .CM_SHAPER_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX + mmCMid_CM_SHAPER_RAMB_START_CNTL_B, .CM_SHAPER_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX + mmCMid_CM_SHAPER_RAMB_START_CNTL_G, .CM_SHAPER_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX + mmCMid_CM_SHAPER_RAMB_START_CNTL_R, .CM_SHAPER_RAMB_END_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX + mmCMid_CM_SHAPER_RAMB_END_CNTL_B, .CM_SHAPER_RAMB_END_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX + mmCMid_CM_SHAPER_RAMB_END_CNTL_G, .CM_SHAPER_RAMB_END_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX + mmCMid_CM_SHAPER_RAMB_END_CNTL_R, .CM_SHAPER_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_0_1, .CM_SHAPER_RAMB_REGION_2_3 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_2_3, .CM_SHAPER_RAMB_REGION_4_5 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_4_5, .CM_SHAPER_RAMB_REGION_6_7 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_6_7, .CM_SHAPER_RAMB_REGION_8_9 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_8_9, .CM_SHAPER_RAMB_REGION_10_11 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_10_11, .CM_SHAPER_RAMB_REGION_12_13 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_12_13, .CM_SHAPER_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_14_15, .CM_SHAPER_RAMB_REGION_16_17 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_16_17, .CM_SHAPER_RAMB_REGION_18_19 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_18_19, .CM_SHAPER_RAMB_REGION_20_21 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_20_21, .CM_SHAPER_RAMB_REGION_22_23 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_22_23, .CM_SHAPER_RAMB_REGION_24_25 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_24_25, .CM_SHAPER_RAMB_REGION_26_27 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_26_27, .CM_SHAPER_RAMB_REGION_28_29 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_28_29, .CM_SHAPER_RAMB_REGION_30_31 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_30_31, .CM_SHAPER_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_32_33, .CM_SHAPER_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX + mmCMid_CM_SHAPER_RAMA_START_CNTL_B, .CM_SHAPER_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX + mmCMid_CM_SHAPER_RAMA_START_CNTL_G, .CM_SHAPER_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX + mmCMid_CM_SHAPER_RAMA_START_CNTL_R, .CM_SHAPER_RAMA_END_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX + mmCMid_CM_SHAPER_RAMA_END_CNTL_B, .CM_SHAPER_RAMA_END_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX + mmCMid_CM_SHAPER_RAMA_END_CNTL_G, .CM_SHAPER_RAMA_END_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX + mmCMid_CM_SHAPER_RAMA_END_CNTL_R, .CM_SHAPER_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_0_1, .CM_SHAPER_RAMA_REGION_2_3 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_2_3, .CM_SHAPER_RAMA_REGION_4_5 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_4_5, .CM_SHAPER_RAMA_REGION_6_7 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_6_7, .CM_SHAPER_RAMA_REGION_8_9 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_8_9, .CM_SHAPER_RAMA_REGION_10_11 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_10_11, .CM_SHAPER_RAMA_REGION_12_13 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_12_13, .CM_SHAPER_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_14_15, .CM_SHAPER_RAMA_REGION_16_17 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_16_17, .CM_SHAPER_RAMA_REGION_18_19 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_18_19, .CM_SHAPER_RAMA_REGION_20_21 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_20_21, .CM_SHAPER_RAMA_REGION_22_23 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_22_23, .CM_SHAPER_RAMA_REGION_24_25 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_24_25, .CM_SHAPER_RAMA_REGION_26_27 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_26_27, .CM_SHAPER_RAMA_REGION_28_29 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_28_29, .CM_SHAPER_RAMA_REGION_30_31 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_30_31, .CM_SHAPER_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_32_33, .CM_SHAPER_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_INDEX_BASE_IDX + mmCMid_CM_SHAPER_LUT_INDEX , .CM_BLNDGAM_LUT_WRITE_EN_MASK = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_WRITE_EN_MASK, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX + mmCURSOR0_id_CURSOR_CONTROL, .ALPHA_2BIT_LUT = DCN_BASE__INST0_SEGmmCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX + mmCNVC_CFGid_ALPHA_2BIT_LUT, .FCNV_FP_BIAS_R = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX + mmCNVC_CFGid_FCNV_FP_BIAS_R, .FCNV_FP_BIAS_G = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX + mmCNVC_CFGid_FCNV_FP_BIAS_G, .FCNV_FP_BIAS_B = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX + mmCNVC_CFGid_FCNV_FP_BIAS_B, .FCNV_FP_SCALE_R = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX + mmCNVC_CFGid_FCNV_FP_SCALE_R, .FCNV_FP_SCALE_G = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX + mmCNVC_CFGid_FCNV_FP_SCALE_G, .FCNV_FP_SCALE_B = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX + mmCNVC_CFGid_FCNV_FP_SCALE_B, .COLOR_KEYER_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_CONTROL, .COLOR_KEYER_ALPHA = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_ALPHA, .COLOR_KEYER_RED = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_RED, .COLOR_KEYER_GREEN = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_GREEN, .COLOR_KEYER_BLUE = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_BLUE, .CM_SHAPER_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_DATA_BASE_IDX + mmCMid_CM_SHAPER_LUT_DATA, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX + mmCURSOR0_id_CURSOR_CONTROL, .OBUF_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX + mmDSCLid_OBUF_MEM_PWR_CTRL, .DSCL_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX + mmDSCLid_DSCL_MEM_PWR_CTRL, .CM_GAMUT_REMAP_B_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C11_C12, .CM_GAMUT_REMAP_B_C13_C14 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C13_C14, .CM_GAMUT_REMAP_B_C21_C22 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C21_C22, .CM_GAMUT_REMAP_B_C23_C24 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C23_C24, .CM_GAMUT_REMAP_B_C31_C32 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C31_C32, .CM_GAMUT_REMAP_B_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C33_C34, .CM_ICSC_B_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_B_C11_C12_BASE_IDX + mmCMid_CM_ICSC_B_C11_C12, .CM_ICSC_B_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_B_C33_C34_BASE_IDX + mmCMid_CM_ICSC_B_C33_C34,}\ | |||
768 | [id] = {\ | |||
769 | TF_REG_LIST_DCN20(id).CM_GAMUT_REMAP_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_CONTROL_BASE_IDX + mmCMid_CM_GAMUT_REMAP_CONTROL, .CM_GAMUT_REMAP_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C11_C12_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C11_C12, .CM_GAMUT_REMAP_C13_C14 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C13_C14_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C13_C14, .CM_GAMUT_REMAP_C21_C22 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C21_C22_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C21_C22, .CM_GAMUT_REMAP_C23_C24 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C23_C24_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C23_C24, .CM_GAMUT_REMAP_C31_C32 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C31_C32_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C31_C32, .CM_GAMUT_REMAP_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_C33_C34_BASE_IDX + mmCMid_CM_GAMUT_REMAP_C33_C34, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = DCN_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX + mmDSCLid_DSCL_EXT_OVERSCAN_LEFT_RIGHT, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = DCN_BASE__INST0_SEGmmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX + mmDSCLid_DSCL_EXT_OVERSCAN_TOP_BOTTOM, .OTG_H_BLANK = DCN_BASE__INST0_SEGmmDSCLid_OTG_H_BLANK_BASE_IDX + mmDSCLid_OTG_H_BLANK, .OTG_V_BLANK = DCN_BASE__INST0_SEGmmDSCLid_OTG_V_BLANK_BASE_IDX + mmDSCLid_OTG_V_BLANK, .SCL_MODE = DCN_BASE__INST0_SEGmmDSCLid_SCL_MODE_BASE_IDX + mmDSCLid_SCL_MODE, .LB_DATA_FORMAT = DCN_BASE__INST0_SEGmmDSCLid_LB_DATA_FORMAT_BASE_IDX + mmDSCLid_LB_DATA_FORMAT, .LB_MEMORY_CTRL = DCN_BASE__INST0_SEGmmDSCLid_LB_MEMORY_CTRL_BASE_IDX + mmDSCLid_LB_MEMORY_CTRL, .DSCL_AUTOCAL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_AUTOCAL_BASE_IDX + mmDSCLid_DSCL_AUTOCAL, .SCL_BLACK_OFFSET = DCN_BASE__INST0_SEGmmDSCLid_SCL_BLACK_OFFSET_BASE_IDX + mmDSCLid_SCL_BLACK_OFFSET, .SCL_TAP_CONTROL = DCN_BASE__INST0_SEGmmDSCLid_SCL_TAP_CONTROL_BASE_IDX + mmDSCLid_SCL_TAP_CONTROL, .SCL_COEF_RAM_TAP_SELECT = DCN_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_SELECT_BASE_IDX + mmDSCLid_SCL_COEF_RAM_TAP_SELECT, .SCL_COEF_RAM_TAP_DATA = DCN_BASE__INST0_SEGmmDSCLid_SCL_COEF_RAM_TAP_DATA_BASE_IDX + mmDSCLid_SCL_COEF_RAM_TAP_DATA, .DSCL_2TAP_CONTROL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_2TAP_CONTROL_BASE_IDX + mmDSCLid_DSCL_2TAP_CONTROL, .MPC_SIZE = DCN_BASE__INST0_SEGmmDSCLid_MPC_SIZE_BASE_IDX + mmDSCLid_MPC_SIZE, .SCL_HORZ_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX + mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO, .SCL_VERT_FILTER_SCALE_RATIO = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO, .SCL_HORZ_FILTER_SCALE_RATIO_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX + mmDSCLid_SCL_HORZ_FILTER_SCALE_RATIO_C, .SCL_VERT_FILTER_SCALE_RATIO_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_SCALE_RATIO_C, .SCL_HORZ_FILTER_INIT = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_BASE_IDX + mmDSCLid_SCL_HORZ_FILTER_INIT, .SCL_HORZ_FILTER_INIT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_HORZ_FILTER_INIT_C_BASE_IDX + mmDSCLid_SCL_HORZ_FILTER_INIT_C, .SCL_VERT_FILTER_INIT = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_INIT, .SCL_VERT_FILTER_INIT_BOT = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BOT_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_INIT_BOT, .SCL_VERT_FILTER_INIT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_C_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_INIT_C, .SCL_VERT_FILTER_INIT_BOT_C = DCN_BASE__INST0_SEGmmDSCLid_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX + mmDSCLid_SCL_VERT_FILTER_INIT_BOT_C, .RECOUT_START = DCN_BASE__INST0_SEGmmDSCLid_RECOUT_START_BASE_IDX + mmDSCLid_RECOUT_START, .RECOUT_SIZE = DCN_BASE__INST0_SEGmmDSCLid_RECOUT_SIZE_BASE_IDX + mmDSCLid_RECOUT_SIZE, .CM_ICSC_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_CONTROL_BASE_IDX + mmCMid_CM_ICSC_CONTROL, .CM_ICSC_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_C11_C12_BASE_IDX + mmCMid_CM_ICSC_C11_C12, .CM_ICSC_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_C33_C34_BASE_IDX + mmCMid_CM_ICSC_C33_C34, .CM_DGAM_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX + mmCMid_CM_DGAM_RAMB_START_CNTL_B, .CM_DGAM_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX + mmCMid_CM_DGAM_RAMB_START_CNTL_G, .CM_DGAM_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX + mmCMid_CM_DGAM_RAMB_START_CNTL_R, .CM_DGAM_RAMB_SLOPE_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX + mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_B, .CM_DGAM_RAMB_SLOPE_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX + mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_G, .CM_DGAM_RAMB_SLOPE_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX + mmCMid_CM_DGAM_RAMB_SLOPE_CNTL_R, .CM_DGAM_RAMB_END_CNTL1_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL1_B, .CM_DGAM_RAMB_END_CNTL2_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL2_B, .CM_DGAM_RAMB_END_CNTL1_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL1_G, .CM_DGAM_RAMB_END_CNTL2_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL2_G, .CM_DGAM_RAMB_END_CNTL1_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL1_R, .CM_DGAM_RAMB_END_CNTL2_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX + mmCMid_CM_DGAM_RAMB_END_CNTL2_R, .CM_DGAM_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_REGION_0_1_BASE_IDX + mmCMid_CM_DGAM_RAMB_REGION_0_1, .CM_DGAM_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMB_REGION_14_15_BASE_IDX + mmCMid_CM_DGAM_RAMB_REGION_14_15, .CM_DGAM_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX + mmCMid_CM_DGAM_RAMA_START_CNTL_B, .CM_DGAM_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX + mmCMid_CM_DGAM_RAMA_START_CNTL_G, .CM_DGAM_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX + mmCMid_CM_DGAM_RAMA_START_CNTL_R, .CM_DGAM_RAMA_SLOPE_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX + mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_B, .CM_DGAM_RAMA_SLOPE_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX + mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_G, .CM_DGAM_RAMA_SLOPE_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX + mmCMid_CM_DGAM_RAMA_SLOPE_CNTL_R, .CM_DGAM_RAMA_END_CNTL1_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL1_B, .CM_DGAM_RAMA_END_CNTL2_B = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL2_B, .CM_DGAM_RAMA_END_CNTL1_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL1_G, .CM_DGAM_RAMA_END_CNTL2_G = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL2_G, .CM_DGAM_RAMA_END_CNTL1_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL1_R, .CM_DGAM_RAMA_END_CNTL2_R = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX + mmCMid_CM_DGAM_RAMA_END_CNTL2_R, .CM_DGAM_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_REGION_0_1_BASE_IDX + mmCMid_CM_DGAM_RAMA_REGION_0_1, .CM_DGAM_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_RAMA_REGION_14_15_BASE_IDX + mmCMid_CM_DGAM_RAMA_REGION_14_15, .CM_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmCMid_CM_MEM_PWR_CTRL_BASE_IDX + mmCMid_CM_MEM_PWR_CTRL, .CM_DGAM_LUT_WRITE_EN_MASK = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX + mmCMid_CM_DGAM_LUT_WRITE_EN_MASK, .CM_DGAM_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_INDEX_BASE_IDX + mmCMid_CM_DGAM_LUT_INDEX, .CM_DGAM_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_LUT_DATA_BASE_IDX + mmCMid_CM_DGAM_LUT_DATA, .CM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_CONTROL_BASE_IDX + mmCMid_CM_CONTROL, .CM_DGAM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_DGAM_CONTROL_BASE_IDX + mmCMid_CM_DGAM_CONTROL, .CM_TEST_DEBUG_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_TEST_DEBUG_INDEX_BASE_IDX + mmCMid_CM_TEST_DEBUG_INDEX, .CM_TEST_DEBUG_DATA = DCN_BASE__INST0_SEGmmCMid_CM_TEST_DEBUG_DATA_BASE_IDX + mmCMid_CM_TEST_DEBUG_DATA, .FORMAT_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_FORMAT_CONTROL_BASE_IDX + mmCNVC_CFGid_FORMAT_CONTROL, .CNVC_SURFACE_PIXEL_FORMAT = DCN_BASE__INST0_SEGmmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX + mmCNVC_CFGid_CNVC_SURFACE_PIXEL_FORMAT, .CURSOR0_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_CONTROL_BASE_IDX + mmCNVC_CURid_CURSOR0_CONTROL , .CURSOR0_COLOR0 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR0_BASE_IDX + mmCNVC_CURid_CURSOR0_COLOR0, .CURSOR0_COLOR1 = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_COLOR1_BASE_IDX + mmCNVC_CURid_CURSOR0_COLOR1, .CURSOR0_FP_SCALE_BIAS = DCN_BASE__INST0_SEGmmCNVC_CURid_CURSOR0_FP_SCALE_BIAS_BASE_IDX + mmCNVC_CURid_CURSOR0_FP_SCALE_BIAS, .DPP_CONTROL = DCN_BASE__INST0_SEGmmDPP_TOPid_DPP_CONTROL_BASE_IDX + mmDPP_TOPid_DPP_CONTROL, .CM_HDR_MULT_COEF = DCN_BASE__INST0_SEGmmCMid_CM_HDR_MULT_COEF_BASE_IDX + mmCMid_CM_HDR_MULT_COEF, .CM_BLNDGAM_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_CONTROL_BASE_IDX + mmCMid_CM_BLNDGAM_CONTROL, .CM_BLNDGAM_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_START_CNTL_B, .CM_BLNDGAM_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_START_CNTL_G, .CM_BLNDGAM_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_START_CNTL_R, .CM_BLNDGAM_RAMB_END_CNTL1_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_B, .CM_BLNDGAM_RAMB_END_CNTL2_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_B, .CM_BLNDGAM_RAMB_END_CNTL1_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_G, .CM_BLNDGAM_RAMB_END_CNTL2_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_G, .CM_BLNDGAM_RAMB_END_CNTL1_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL1_R, .CM_BLNDGAM_RAMB_END_CNTL2_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_END_CNTL2_R, .CM_BLNDGAM_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_0_1, .CM_BLNDGAM_RAMB_REGION_2_3 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_2_3, .CM_BLNDGAM_RAMB_REGION_4_5 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_4_5, .CM_BLNDGAM_RAMB_REGION_6_7 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_6_7, .CM_BLNDGAM_RAMB_REGION_8_9 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_8_9, .CM_BLNDGAM_RAMB_REGION_10_11 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_10_11, .CM_BLNDGAM_RAMB_REGION_12_13 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_12_13, .CM_BLNDGAM_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_14_15, .CM_BLNDGAM_RAMB_REGION_16_17 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_16_17, .CM_BLNDGAM_RAMB_REGION_18_19 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_18_19, .CM_BLNDGAM_RAMB_REGION_20_21 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_20_21, .CM_BLNDGAM_RAMB_REGION_22_23 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_22_23, .CM_BLNDGAM_RAMB_REGION_24_25 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_24_25, .CM_BLNDGAM_RAMB_REGION_26_27 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_26_27, .CM_BLNDGAM_RAMB_REGION_28_29 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_28_29, .CM_BLNDGAM_RAMB_REGION_30_31 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_30_31, .CM_BLNDGAM_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_REGION_32_33, .CM_BLNDGAM_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_START_CNTL_B, .CM_BLNDGAM_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_START_CNTL_G, .CM_BLNDGAM_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_START_CNTL_R, .CM_BLNDGAM_RAMA_END_CNTL1_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_B, .CM_BLNDGAM_RAMA_END_CNTL2_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_B, .CM_BLNDGAM_RAMA_END_CNTL1_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_G, .CM_BLNDGAM_RAMA_END_CNTL2_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_G, .CM_BLNDGAM_RAMA_END_CNTL1_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL1_R, .CM_BLNDGAM_RAMA_END_CNTL2_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_END_CNTL2_R, .CM_BLNDGAM_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_0_1, .CM_BLNDGAM_RAMA_REGION_2_3 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_2_3, .CM_BLNDGAM_RAMA_REGION_4_5 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_4_5, .CM_BLNDGAM_RAMA_REGION_6_7 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_6_7, .CM_BLNDGAM_RAMA_REGION_8_9 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_8_9, .CM_BLNDGAM_RAMA_REGION_10_11 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_10_11, .CM_BLNDGAM_RAMA_REGION_12_13 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_12_13, .CM_BLNDGAM_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_14_15, .CM_BLNDGAM_RAMA_REGION_16_17 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_16_17, .CM_BLNDGAM_RAMA_REGION_18_19 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_18_19, .CM_BLNDGAM_RAMA_REGION_20_21 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_20_21, .CM_BLNDGAM_RAMA_REGION_22_23 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_22_23, .CM_BLNDGAM_RAMA_REGION_24_25 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_24_25, .CM_BLNDGAM_RAMA_REGION_26_27 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_26_27, .CM_BLNDGAM_RAMA_REGION_28_29 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_28_29, .CM_BLNDGAM_RAMA_REGION_30_31 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_30_31, .CM_BLNDGAM_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_REGION_32_33, .CM_BLNDGAM_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_INDEX_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_INDEX , .CM_BLNDGAM_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_DATA_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_DATA, .CM_3DLUT_MODE = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_MODE_BASE_IDX + mmCMid_CM_3DLUT_MODE, .CM_3DLUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_INDEX_BASE_IDX + mmCMid_CM_3DLUT_INDEX, .CM_3DLUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_BASE_IDX + mmCMid_CM_3DLUT_DATA, .CM_3DLUT_DATA_30BIT = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_DATA_30BIT_BASE_IDX + mmCMid_CM_3DLUT_DATA_30BIT, .CM_3DLUT_READ_WRITE_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX + mmCMid_CM_3DLUT_READ_WRITE_CONTROL, .CM_SHAPER_LUT_WRITE_EN_MASK = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX + mmCMid_CM_SHAPER_LUT_WRITE_EN_MASK, .CM_SHAPER_CONTROL = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_CONTROL_BASE_IDX + mmCMid_CM_SHAPER_CONTROL, .CM_SHAPER_RAMB_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX + mmCMid_CM_SHAPER_RAMB_START_CNTL_B, .CM_SHAPER_RAMB_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX + mmCMid_CM_SHAPER_RAMB_START_CNTL_G, .CM_SHAPER_RAMB_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX + mmCMid_CM_SHAPER_RAMB_START_CNTL_R, .CM_SHAPER_RAMB_END_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX + mmCMid_CM_SHAPER_RAMB_END_CNTL_B, .CM_SHAPER_RAMB_END_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX + mmCMid_CM_SHAPER_RAMB_END_CNTL_G, .CM_SHAPER_RAMB_END_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX + mmCMid_CM_SHAPER_RAMB_END_CNTL_R, .CM_SHAPER_RAMB_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_0_1, .CM_SHAPER_RAMB_REGION_2_3 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_2_3, .CM_SHAPER_RAMB_REGION_4_5 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_4_5, .CM_SHAPER_RAMB_REGION_6_7 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_6_7, .CM_SHAPER_RAMB_REGION_8_9 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_8_9, .CM_SHAPER_RAMB_REGION_10_11 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_10_11, .CM_SHAPER_RAMB_REGION_12_13 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_12_13, .CM_SHAPER_RAMB_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_14_15, .CM_SHAPER_RAMB_REGION_16_17 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_16_17, .CM_SHAPER_RAMB_REGION_18_19 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_18_19, .CM_SHAPER_RAMB_REGION_20_21 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_20_21, .CM_SHAPER_RAMB_REGION_22_23 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_22_23, .CM_SHAPER_RAMB_REGION_24_25 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_24_25, .CM_SHAPER_RAMB_REGION_26_27 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_26_27, .CM_SHAPER_RAMB_REGION_28_29 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_28_29, .CM_SHAPER_RAMB_REGION_30_31 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_30_31, .CM_SHAPER_RAMB_REGION_32_33 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX + mmCMid_CM_SHAPER_RAMB_REGION_32_33, .CM_SHAPER_RAMA_START_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX + mmCMid_CM_SHAPER_RAMA_START_CNTL_B, .CM_SHAPER_RAMA_START_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX + mmCMid_CM_SHAPER_RAMA_START_CNTL_G, .CM_SHAPER_RAMA_START_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX + mmCMid_CM_SHAPER_RAMA_START_CNTL_R, .CM_SHAPER_RAMA_END_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX + mmCMid_CM_SHAPER_RAMA_END_CNTL_B, .CM_SHAPER_RAMA_END_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX + mmCMid_CM_SHAPER_RAMA_END_CNTL_G, .CM_SHAPER_RAMA_END_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX + mmCMid_CM_SHAPER_RAMA_END_CNTL_R, .CM_SHAPER_RAMA_REGION_0_1 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_0_1, .CM_SHAPER_RAMA_REGION_2_3 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_2_3, .CM_SHAPER_RAMA_REGION_4_5 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_4_5, .CM_SHAPER_RAMA_REGION_6_7 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_6_7, .CM_SHAPER_RAMA_REGION_8_9 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_8_9, .CM_SHAPER_RAMA_REGION_10_11 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_10_11, .CM_SHAPER_RAMA_REGION_12_13 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_12_13, .CM_SHAPER_RAMA_REGION_14_15 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_14_15, .CM_SHAPER_RAMA_REGION_16_17 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_16_17, .CM_SHAPER_RAMA_REGION_18_19 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_18_19, .CM_SHAPER_RAMA_REGION_20_21 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_20_21, .CM_SHAPER_RAMA_REGION_22_23 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_22_23, .CM_SHAPER_RAMA_REGION_24_25 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_24_25, .CM_SHAPER_RAMA_REGION_26_27 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_26_27, .CM_SHAPER_RAMA_REGION_28_29 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_28_29, .CM_SHAPER_RAMA_REGION_30_31 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_30_31, .CM_SHAPER_RAMA_REGION_32_33 = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX + mmCMid_CM_SHAPER_RAMA_REGION_32_33, .CM_SHAPER_LUT_INDEX = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_INDEX_BASE_IDX + mmCMid_CM_SHAPER_LUT_INDEX , .CM_BLNDGAM_LUT_WRITE_EN_MASK = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX + mmCMid_CM_BLNDGAM_LUT_WRITE_EN_MASK, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_B, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_G, .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMB_SLOPE_CNTL_R, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_B, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_G, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = DCN_BASE__INST0_SEGmmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX + mmCMid_CM_BLNDGAM_RAMA_SLOPE_CNTL_R, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX + mmCURSOR0_id_CURSOR_CONTROL, .ALPHA_2BIT_LUT = DCN_BASE__INST0_SEGmmCNVC_CFGid_ALPHA_2BIT_LUT_BASE_IDX + mmCNVC_CFGid_ALPHA_2BIT_LUT, .FCNV_FP_BIAS_R = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_R_BASE_IDX + mmCNVC_CFGid_FCNV_FP_BIAS_R, .FCNV_FP_BIAS_G = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_G_BASE_IDX + mmCNVC_CFGid_FCNV_FP_BIAS_G, .FCNV_FP_BIAS_B = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_BIAS_B_BASE_IDX + mmCNVC_CFGid_FCNV_FP_BIAS_B, .FCNV_FP_SCALE_R = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_R_BASE_IDX + mmCNVC_CFGid_FCNV_FP_SCALE_R, .FCNV_FP_SCALE_G = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_G_BASE_IDX + mmCNVC_CFGid_FCNV_FP_SCALE_G, .FCNV_FP_SCALE_B = DCN_BASE__INST0_SEGmmCNVC_CFGid_FCNV_FP_SCALE_B_BASE_IDX + mmCNVC_CFGid_FCNV_FP_SCALE_B, .COLOR_KEYER_CONTROL = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_CONTROL_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_CONTROL, .COLOR_KEYER_ALPHA = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_ALPHA_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_ALPHA, .COLOR_KEYER_RED = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_RED_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_RED, .COLOR_KEYER_GREEN = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_GREEN_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_GREEN, .COLOR_KEYER_BLUE = DCN_BASE__INST0_SEGmmCNVC_CFGid_COLOR_KEYER_BLUE_BASE_IDX + mmCNVC_CFGid_COLOR_KEYER_BLUE, .CM_SHAPER_LUT_DATA = DCN_BASE__INST0_SEGmmCMid_CM_SHAPER_LUT_DATA_BASE_IDX + mmCMid_CM_SHAPER_LUT_DATA, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX + mmCURSOR0_id_CURSOR_CONTROL, .OBUF_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmDSCLid_OBUF_MEM_PWR_CTRL_BASE_IDX + mmDSCLid_OBUF_MEM_PWR_CTRL, .DSCL_MEM_PWR_CTRL = DCN_BASE__INST0_SEGmmDSCLid_DSCL_MEM_PWR_CTRL_BASE_IDX + mmDSCLid_DSCL_MEM_PWR_CTRL,\ | |||
770 | TF_REG_LIST_DCN20_COMMON_APPEND(id).CM_GAMUT_REMAP_B_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C11_C12, .CM_GAMUT_REMAP_B_C13_C14 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C13_C14, .CM_GAMUT_REMAP_B_C21_C22 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C21_C22, .CM_GAMUT_REMAP_B_C23_C24 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C23_C24, .CM_GAMUT_REMAP_B_C31_C32 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C31_C32, .CM_GAMUT_REMAP_B_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX + mmCMid_CM_GAMUT_REMAP_B_C33_C34, .CM_ICSC_B_C11_C12 = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_B_C11_C12_BASE_IDX + mmCMid_CM_ICSC_B_C11_C12, .CM_ICSC_B_C33_C34 = DCN_BASE__INST0_SEGmmCMid_CM_ICSC_B_C33_C34_BASE_IDX + mmCMid_CM_ICSC_B_C33_C34,\ | |||
771 | } | |||
772 | ||||
773 | static const struct dcn2_dpp_registers tf_regs[] = { | |||
774 | tf_regs(0)[0] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x0d28, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x0d29, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x0d2a, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x0d2b, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x0d2c, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x0d2d, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x0d2e, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x0cfe, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0cff, .OTG_H_BLANK = 0x000034C0 + 0x0d00, .OTG_V_BLANK = 0x000034C0 + 0x0d01, .SCL_MODE = 0x000034C0 + 0x0cec, .LB_DATA_FORMAT = 0x000034C0 + 0x0d05, .LB_MEMORY_CTRL = 0x000034C0 + 0x0d06 , .DSCL_AUTOCAL = 0x000034C0 + 0x0cfd, .SCL_BLACK_OFFSET = 0x000034C0 + 0x0cfb, .SCL_TAP_CONTROL = 0x000034C0 + 0x0ced, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0cea, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x0ceb, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0cef, .MPC_SIZE = 0x000034C0 + 0x0d04, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x0cf1, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0cf5 , .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0cf3, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0cf8, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x0cf2 , .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x0cf4, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0cf6, .SCL_VERT_FILTER_INIT_BOT = 0x000034C0 + 0x0cf7, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x0cf9, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x0cfa, .RECOUT_START = 0x000034C0 + 0x0d02, . RECOUT_SIZE = 0x000034C0 + 0x0d03, .CM_ICSC_CONTROL = 0x000034C0 + 0x0d1b, .CM_ICSC_C11_C12 = 0x000034C0 + 0x0d1c, .CM_ICSC_C33_C34 = 0x000034C0 + 0x0d21, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0d4f, .CM_DGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x0d50, . CM_DGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x0d51, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x0d52, .CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x0d53, .CM_DGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x0d54, . CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0d55, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0d56, .CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x0d57, .CM_DGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x0d58, . CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0d59, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0d5a, .CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x0d5b, .CM_DGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x0d62, . CM_DGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x0d3b, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0d3c, .CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0d3d, .CM_DGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x0d3e, . CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x0d3f, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x0d40, .CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x0d41, .CM_DGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x0d42, . CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0d43, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0d44, .CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x0d45, .CM_DGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x0d46, . CM_DGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0d47, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0d4e, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x0da2 , .CM_DGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0d3a, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x0d38, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x0d39 , .CM_CONTROL = 0x000034C0 + 0x0d1a, .CM_DGAM_CONTROL = 0x000034C0 + 0x0d37, .CM_TEST_DEBUG_INDEX = 0x000034C0 + 0x0de9, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x0dea, .FORMAT_CONTROL = 0x000034C0 + 0x0cd0 , .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0ccf, .CURSOR0_CONTROL = 0x000034C0 + 0x0ce0, .CURSOR0_COLOR0 = 0x000034C0 + 0x0ce1 , .CURSOR0_COLOR1 = 0x000034C0 + 0x0ce2, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0ce3, .DPP_CONTROL = 0x000034C0 + 0x0cc5, . CM_HDR_MULT_COEF = 0x000034C0 + 0x0da1, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0d63, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0d84, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x0d85 , .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x0d86, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0d8a, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0d8b, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x0d8c , .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x0d8d, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0d8e, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0d8f, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x0d90, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x0d91, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x0d92, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x0d93, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x0d94, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x0d95, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x0d96, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x0d97, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x0d98 , .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x0d99, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x0d9a, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x0d9b, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x0d9c , .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x0d9d, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x0d9e, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x0d9f, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x0da0 , .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x0d67, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0d68, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0d69, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x0d6d , .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x0d6e, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0d6f, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0d70, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x0d71 , .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x0d72, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0d73, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x0d74, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x0d75, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x0d76, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x0d77, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x0d78, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x0d79 , .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0d7a, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x0d7b, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x0d7c, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x0d7d , .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x0d7e, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x0d7f, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x0d80, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x0d81 , .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x0d82, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x0d83, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x0d64 , .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x0d65, .CM_3DLUT_MODE = 0x000034C0 + 0x0de0, .CM_3DLUT_INDEX = 0x000034C0 + 0x0de1, . CM_3DLUT_DATA = 0x000034C0 + 0x0de2, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x0de3, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x0de4 , .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0daf, .CM_SHAPER_CONTROL = 0x000034C0 + 0x0da7, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x0dc7, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x0dc8 , .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x0dc9, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x0dca, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x0dcb, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x0dcc, . CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x0dcd, .CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x0dce, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x0dcf, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x0dd0, . CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x0dd1, .CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x0dd2, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x0dd3, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x0dd4 , .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x0dd5, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x0dd6, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x0dd7, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x0dd8 , .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x0dd9, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x0dda, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x0ddb, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x0ddc , .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x0ddd, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x0db0, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x0db1, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x0db2 , .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x0db3, .CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x0db4, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x0db5, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x0db6, . CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x0db7, .CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x0db8, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x0db9, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x0dba, . CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x0dbb, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x0dbc, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x0dbd, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x0dbe , .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x0dbf, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x0dc0, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x0dc1, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x0dc2 , .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x0dc3, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x0dc4, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x0dc5, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x0dc6 , .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x0dad, .CM_BLNDGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0d66, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x0d87, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x0d88 , .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x0d89, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x0d6a, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x0d6b, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x0d6c , .CURSOR_CONTROL = 0x000034C0 + 0x0678, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0cdd, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0cd1, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0cd2, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0cd3 , .FCNV_FP_SCALE_R = 0x000034C0 + 0x0cd4, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0cd5, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0cd6, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0cd7, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0cd8 , .COLOR_KEYER_RED = 0x000034C0 + 0x0cd9, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0cda, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0cdb , .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x0dae, .CURSOR_CONTROL = 0x000034C0 + 0x0678, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0d0b , .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0d08, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x0d2f, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x0d30, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x0d31, . CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x0d32, .CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x0d33, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x0d34, .CM_ICSC_B_C11_C12 = 0x000034C0 + 0x0d22, .CM_ICSC_B_C33_C34 = 0x000034C0 + 0x0d27,}, | |||
775 | tf_regs(1)[1] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x0e93, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x0e94, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x0e95, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x0e96, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x0e97, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x0e98, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x0e99, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x0e69, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0e6a, .OTG_H_BLANK = 0x000034C0 + 0x0e6b, .OTG_V_BLANK = 0x000034C0 + 0x0e6c, .SCL_MODE = 0x000034C0 + 0x0e57, .LB_DATA_FORMAT = 0x000034C0 + 0x0e70, .LB_MEMORY_CTRL = 0x000034C0 + 0x0e71 , .DSCL_AUTOCAL = 0x000034C0 + 0x0e68, .SCL_BLACK_OFFSET = 0x000034C0 + 0x0e66, .SCL_TAP_CONTROL = 0x000034C0 + 0x0e58, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0e55, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x0e56, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0e5a, .MPC_SIZE = 0x000034C0 + 0x0e6f, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x0e5c, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0e60 , .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0e5e, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0e63, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x0e5d , .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x0e5f, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0e61, .SCL_VERT_FILTER_INIT_BOT = 0x000034C0 + 0x0e62, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x0e64, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x0e65, .RECOUT_START = 0x000034C0 + 0x0e6d, . RECOUT_SIZE = 0x000034C0 + 0x0e6e, .CM_ICSC_CONTROL = 0x000034C0 + 0x0e86, .CM_ICSC_C11_C12 = 0x000034C0 + 0x0e87, .CM_ICSC_C33_C34 = 0x000034C0 + 0x0e8c, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0eba, .CM_DGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x0ebb, . CM_DGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x0ebc, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x0ebd, .CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x0ebe, .CM_DGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x0ebf, . CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0ec0, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0ec1, .CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x0ec2, .CM_DGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x0ec3, . CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0ec4, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0ec5, .CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x0ec6, .CM_DGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x0ecd, . CM_DGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x0ea6, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0ea7, .CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0ea8, .CM_DGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x0ea9, . CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x0eaa, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x0eab, .CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x0eac, .CM_DGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x0ead, . CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0eae, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0eaf, .CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x0eb0, .CM_DGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x0eb1, . CM_DGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0eb2, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0eb9, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x0f0d , .CM_DGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0ea5, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x0ea3, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x0ea4 , .CM_CONTROL = 0x000034C0 + 0x0e85, .CM_DGAM_CONTROL = 0x000034C0 + 0x0ea2, .CM_TEST_DEBUG_INDEX = 0x000034C0 + 0x0f54, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x0f55, .FORMAT_CONTROL = 0x000034C0 + 0x0e3b , .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0e3a, .CURSOR0_CONTROL = 0x000034C0 + 0x0e4b, .CURSOR0_COLOR0 = 0x000034C0 + 0x0e4c , .CURSOR0_COLOR1 = 0x000034C0 + 0x0e4d, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0e4e, .DPP_CONTROL = 0x000034C0 + 0x0e30, . CM_HDR_MULT_COEF = 0x000034C0 + 0x0f0c, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x0ece, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x0eef, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x0ef0 , .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x0ef1, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x0ef5, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x0ef6, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x0ef7 , .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x0ef8, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x0ef9, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x0efa, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x0efb, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x0efc, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x0efd, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x0efe, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x0eff, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x0f00, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x0f01, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x0f02, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x0f03 , .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x0f04, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x0f05, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x0f06, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x0f07 , .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x0f08, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x0f09, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x0f0a, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x0f0b , .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x0ed2, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x0ed3, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x0ed4, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x0ed8 , .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x0ed9, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x0eda, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x0edb, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x0edc , .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x0edd, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x0ede, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x0edf, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x0ee0, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x0ee1, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x0ee2, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x0ee3, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x0ee4 , .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x0ee5, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x0ee6, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x0ee7, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x0ee8 , .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x0ee9, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x0eea, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x0eeb, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x0eec , .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x0eed, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x0eee, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x0ecf , .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x0ed0, .CM_3DLUT_MODE = 0x000034C0 + 0x0f4b, .CM_3DLUT_INDEX = 0x000034C0 + 0x0f4c, . CM_3DLUT_DATA = 0x000034C0 + 0x0f4d, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x0f4e, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x0f4f , .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0f1a, .CM_SHAPER_CONTROL = 0x000034C0 + 0x0f12, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x0f32, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x0f33 , .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x0f34, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x0f35, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x0f36, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x0f37, . CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x0f38, .CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x0f39, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x0f3a, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x0f3b, . CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x0f3c, .CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x0f3d, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x0f3e, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x0f3f , .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x0f40, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x0f41, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x0f42, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x0f43 , .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x0f44, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x0f45, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x0f46, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x0f47 , .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x0f48, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x0f1b, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x0f1c, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x0f1d , .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x0f1e, .CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x0f1f, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x0f20, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x0f21, . CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x0f22, .CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x0f23, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x0f24, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x0f25, . CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x0f26, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x0f27, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x0f28, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x0f29 , .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x0f2a, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x0f2b, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x0f2c, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x0f2d , .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x0f2e, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x0f2f, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x0f30, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x0f31 , .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x0f18, .CM_BLNDGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x0ed1, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x0ef2, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x0ef3 , .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x0ef4, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x0ed5, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x0ed6, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x0ed7 , .CURSOR_CONTROL = 0x000034C0 + 0x0754, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0e48, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0e3c, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0e3d, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0e3e , .FCNV_FP_SCALE_R = 0x000034C0 + 0x0e3f, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0e40, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0e41, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0e42, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0e43 , .COLOR_KEYER_RED = 0x000034C0 + 0x0e44, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0e45, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0e46 , .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x0f19, .CURSOR_CONTROL = 0x000034C0 + 0x0754, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0e76 , .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0e73, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x0e9a, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x0e9b, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x0e9c, . CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x0e9d, .CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x0e9e, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x0e9f, .CM_ICSC_B_C11_C12 = 0x000034C0 + 0x0e8d, .CM_ICSC_B_C33_C34 = 0x000034C0 + 0x0e92,}, | |||
776 | tf_regs(2)[2] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x0ffe, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x0fff, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x1000, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x1001, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x1002, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x1003, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x1004, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x0fd4, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x0fd5, .OTG_H_BLANK = 0x000034C0 + 0x0fd6, .OTG_V_BLANK = 0x000034C0 + 0x0fd7, .SCL_MODE = 0x000034C0 + 0x0fc2, .LB_DATA_FORMAT = 0x000034C0 + 0x0fdb, .LB_MEMORY_CTRL = 0x000034C0 + 0x0fdc , .DSCL_AUTOCAL = 0x000034C0 + 0x0fd3, .SCL_BLACK_OFFSET = 0x000034C0 + 0x0fd1, .SCL_TAP_CONTROL = 0x000034C0 + 0x0fc3, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x0fc0, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x0fc1, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x0fc5, .MPC_SIZE = 0x000034C0 + 0x0fda, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x0fc7, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0fcb , .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0fc9, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x0fce, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x0fc8 , .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x0fca, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x0fcc, .SCL_VERT_FILTER_INIT_BOT = 0x000034C0 + 0x0fcd, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x0fcf, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x0fd0, .RECOUT_START = 0x000034C0 + 0x0fd8, . RECOUT_SIZE = 0x000034C0 + 0x0fd9, .CM_ICSC_CONTROL = 0x000034C0 + 0x0ff1, .CM_ICSC_C11_C12 = 0x000034C0 + 0x0ff2, .CM_ICSC_C33_C34 = 0x000034C0 + 0x0ff7, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x1025, .CM_DGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x1026, . CM_DGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x1027, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x1028, .CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x1029, .CM_DGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x102a, . CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x102b, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x102c, .CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x102d, .CM_DGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x102e, . CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x102f, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x1030, .CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x1031, .CM_DGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x1038, . CM_DGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x1011, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x1012, .CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x1013, .CM_DGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x1014, . CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x1015, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x1016, .CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x1017, .CM_DGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x1018, . CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x1019, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x101a, .CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x101b, .CM_DGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x101c, . CM_DGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x101d, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x1024, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x1078 , .CM_DGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x1010, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x100e, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x100f , .CM_CONTROL = 0x000034C0 + 0x0ff0, .CM_DGAM_CONTROL = 0x000034C0 + 0x100d, .CM_TEST_DEBUG_INDEX = 0x000034C0 + 0x10bf, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x10c0, .FORMAT_CONTROL = 0x000034C0 + 0x0fa6 , .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x0fa5, .CURSOR0_CONTROL = 0x000034C0 + 0x0fb6, .CURSOR0_COLOR0 = 0x000034C0 + 0x0fb7 , .CURSOR0_COLOR1 = 0x000034C0 + 0x0fb8, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x0fb9, .DPP_CONTROL = 0x000034C0 + 0x0f9b, . CM_HDR_MULT_COEF = 0x000034C0 + 0x1077, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x1039, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x105a, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x105b , .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x105c, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x1060, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x1061, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x1062 , .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x1063, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x1064, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x1065, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x1066, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x1067, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x1068, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x1069, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x106a, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x106b, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x106c, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x106d, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x106e , .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x106f, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x1070, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x1071, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x1072 , .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x1073, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x1074, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x1075, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x1076 , .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x103d, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x103e, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x103f, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x1043 , .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x1044, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x1045, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x1046, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x1047 , .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x1048, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x1049, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x104a, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x104b, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x104c, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x104d, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x104e, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x104f , .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x1050, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x1051, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x1052, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x1053 , .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x1054, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x1055, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x1056, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x1057 , .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x1058, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x1059, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x103a , .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x103b, .CM_3DLUT_MODE = 0x000034C0 + 0x10b6, .CM_3DLUT_INDEX = 0x000034C0 + 0x10b7, . CM_3DLUT_DATA = 0x000034C0 + 0x10b8, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x10b9, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x10ba , .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x1085, .CM_SHAPER_CONTROL = 0x000034C0 + 0x107d, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x109d, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x109e , .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x109f, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x10a0, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x10a1, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x10a2, . CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x10a3, .CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x10a4, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x10a5, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x10a6, . CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x10a7, .CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x10a8, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x10a9, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x10aa , .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x10ab, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x10ac, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x10ad, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x10ae , .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x10af, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x10b0, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x10b1, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x10b2 , .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x10b3, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x1086, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x1087, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x1088 , .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x1089, .CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x108a, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x108b, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x108c, . CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x108d, .CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x108e, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x108f, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x1090, . CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x1091, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x1092, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x1093, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x1094 , .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x1095, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x1096, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x1097, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x1098 , .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x1099, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x109a, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x109b, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x109c , .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x1083, .CM_BLNDGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x103c, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x105d, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x105e , .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x105f, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x1040, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x1041, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x1042 , .CURSOR_CONTROL = 0x000034C0 + 0x0830, .ALPHA_2BIT_LUT = 0x000034C0 + 0x0fb3, .FCNV_FP_BIAS_R = 0x000034C0 + 0x0fa7, .FCNV_FP_BIAS_G = 0x000034C0 + 0x0fa8, .FCNV_FP_BIAS_B = 0x000034C0 + 0x0fa9 , .FCNV_FP_SCALE_R = 0x000034C0 + 0x0faa, .FCNV_FP_SCALE_G = 0x000034C0 + 0x0fab, .FCNV_FP_SCALE_B = 0x000034C0 + 0x0fac, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x0fad, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x0fae , .COLOR_KEYER_RED = 0x000034C0 + 0x0faf, .COLOR_KEYER_GREEN = 0x000034C0 + 0x0fb0, .COLOR_KEYER_BLUE = 0x000034C0 + 0x0fb1 , .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x1084, .CURSOR_CONTROL = 0x000034C0 + 0x0830, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x0fe1 , .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x0fde, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x1005, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x1006, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x1007, . CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x1008, .CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x1009, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x100a, .CM_ICSC_B_C11_C12 = 0x000034C0 + 0x0ff8, .CM_ICSC_B_C33_C34 = 0x000034C0 + 0x0ffd,}, | |||
777 | tf_regs(3)[3] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x1169, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x116a, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x116b, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x116c, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x116d, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x116e, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x116f, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x113f, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x1140, .OTG_H_BLANK = 0x000034C0 + 0x1141, .OTG_V_BLANK = 0x000034C0 + 0x1142, .SCL_MODE = 0x000034C0 + 0x112d, .LB_DATA_FORMAT = 0x000034C0 + 0x1146, .LB_MEMORY_CTRL = 0x000034C0 + 0x1147 , .DSCL_AUTOCAL = 0x000034C0 + 0x113e, .SCL_BLACK_OFFSET = 0x000034C0 + 0x113c, .SCL_TAP_CONTROL = 0x000034C0 + 0x112e, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x112b, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x112c, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x1130, .MPC_SIZE = 0x000034C0 + 0x1145, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x1132, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x1136 , .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1134, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x1139, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x1133 , .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x1135, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x1137, .SCL_VERT_FILTER_INIT_BOT = 0x000034C0 + 0x1138, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x113a, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x113b, .RECOUT_START = 0x000034C0 + 0x1143, . RECOUT_SIZE = 0x000034C0 + 0x1144, .CM_ICSC_CONTROL = 0x000034C0 + 0x115c, .CM_ICSC_C11_C12 = 0x000034C0 + 0x115d, .CM_ICSC_C33_C34 = 0x000034C0 + 0x1162, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x1190, .CM_DGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x1191, . CM_DGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x1192, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x1193, .CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x1194, .CM_DGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x1195, . CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x1196, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x1197, .CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x1198, .CM_DGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x1199, . CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x119a, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x119b, .CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x119c, .CM_DGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x11a3, . CM_DGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x117c, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x117d, .CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x117e, .CM_DGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x117f, . CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x1180, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x1181, .CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x1182, .CM_DGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x1183, . CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x1184, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x1185, .CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x1186, .CM_DGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x1187, . CM_DGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x1188, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x118f, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x11e3 , .CM_DGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x117b, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x1179, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x117a , .CM_CONTROL = 0x000034C0 + 0x115b, .CM_DGAM_CONTROL = 0x000034C0 + 0x1178, .CM_TEST_DEBUG_INDEX = 0x000034C0 + 0x122a, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x122b, .FORMAT_CONTROL = 0x000034C0 + 0x1111 , .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x1110, .CURSOR0_CONTROL = 0x000034C0 + 0x1121, .CURSOR0_COLOR0 = 0x000034C0 + 0x1122 , .CURSOR0_COLOR1 = 0x000034C0 + 0x1123, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x1124, .DPP_CONTROL = 0x000034C0 + 0x1106, . CM_HDR_MULT_COEF = 0x000034C0 + 0x11e2, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x11a4, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x11c5, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x11c6 , .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x11c7, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x11cb, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x11cc, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x11cd , .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x11ce, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x11cf, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x11d0, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x11d1, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x11d2, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x11d3, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x11d4, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x11d5, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x11d6, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x11d7, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x11d8, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x11d9 , .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x11da, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x11db, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x11dc, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x11dd , .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x11de, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x11df, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x11e0, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x11e1 , .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x11a8, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x11a9, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x11aa, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x11ae , .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x11af, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x11b0, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x11b1, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x11b2 , .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x11b3, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x11b4, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x11b5, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x11b6, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x11b7, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x11b8, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x11b9, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x11ba , .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x11bb, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x11bc, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x11bd, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x11be , .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x11bf, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x11c0, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x11c1, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x11c2 , .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x11c3, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x11c4, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x11a5 , .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x11a6, .CM_3DLUT_MODE = 0x000034C0 + 0x1221, .CM_3DLUT_INDEX = 0x000034C0 + 0x1222, . CM_3DLUT_DATA = 0x000034C0 + 0x1223, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x1224, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x1225 , .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x11f0, .CM_SHAPER_CONTROL = 0x000034C0 + 0x11e8, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x1208, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x1209 , .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x120a, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x120b, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x120c, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x120d, . CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x120e, .CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x120f, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x1210, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x1211, . CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x1212, .CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x1213, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x1214, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x1215 , .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x1216, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x1217, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x1218, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x1219 , .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x121a, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x121b, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x121c, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x121d , .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x121e, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x11f1, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x11f2, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x11f3 , .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x11f4, .CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x11f5, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x11f6, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x11f7, . CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x11f8, .CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x11f9, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x11fa, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x11fb, . CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x11fc, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x11fd, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x11fe, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x11ff , .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x1200, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x1201, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x1202, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x1203 , .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x1204, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x1205, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x1206, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x1207 , .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x11ee, .CM_BLNDGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x11a7, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x11c8, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x11c9 , .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x11ca, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x11ab, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x11ac, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x11ad , .CURSOR_CONTROL = 0x000034C0 + 0x090c, .ALPHA_2BIT_LUT = 0x000034C0 + 0x111e, .FCNV_FP_BIAS_R = 0x000034C0 + 0x1112, .FCNV_FP_BIAS_G = 0x000034C0 + 0x1113, .FCNV_FP_BIAS_B = 0x000034C0 + 0x1114 , .FCNV_FP_SCALE_R = 0x000034C0 + 0x1115, .FCNV_FP_SCALE_G = 0x000034C0 + 0x1116, .FCNV_FP_SCALE_B = 0x000034C0 + 0x1117, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x1118, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x1119 , .COLOR_KEYER_RED = 0x000034C0 + 0x111a, .COLOR_KEYER_GREEN = 0x000034C0 + 0x111b, .COLOR_KEYER_BLUE = 0x000034C0 + 0x111c , .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x11ef, .CURSOR_CONTROL = 0x000034C0 + 0x090c, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x114c , .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x1149, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x1170, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x1171, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x1172, . CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x1173, .CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x1174, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x1175, .CM_ICSC_B_C11_C12 = 0x000034C0 + 0x1163, .CM_ICSC_B_C33_C34 = 0x000034C0 + 0x1168,}, | |||
778 | tf_regs(4)[4] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x3633, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x3634, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x3635, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x3636, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x3637, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x3638, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x3639, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x3609, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x360a, .OTG_H_BLANK = 0x000034C0 + 0x360b, .OTG_V_BLANK = 0x000034C0 + 0x360c, .SCL_MODE = 0x000034C0 + 0x35f7, .LB_DATA_FORMAT = 0x000034C0 + 0x3610, .LB_MEMORY_CTRL = 0x000034C0 + 0x3611 , .DSCL_AUTOCAL = 0x000034C0 + 0x3608, .SCL_BLACK_OFFSET = 0x000034C0 + 0x3606, .SCL_TAP_CONTROL = 0x000034C0 + 0x35f8, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x35f5, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x35f6, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x35fa, .MPC_SIZE = 0x000034C0 + 0x360f, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x35fc, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x3600 , .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x35fe, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x3603, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x35fd , .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x35ff, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x3601, .SCL_VERT_FILTER_INIT_BOT = 0x000034C0 + 0x3602, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x3604, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x3605, .RECOUT_START = 0x000034C0 + 0x360d, . RECOUT_SIZE = 0x000034C0 + 0x360e, .CM_ICSC_CONTROL = 0x000034C0 + 0x3626, .CM_ICSC_C11_C12 = 0x000034C0 + 0x3627, .CM_ICSC_C33_C34 = 0x000034C0 + 0x362c, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x365a, .CM_DGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x365b, . CM_DGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x365c, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x365d, .CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x365e, .CM_DGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x365f, . CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x3660, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x3661, .CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x3662, .CM_DGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x3663, . CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x3664, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x3665, .CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x3666, .CM_DGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x366d, . CM_DGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x3646, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x3647, .CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x3648, .CM_DGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x3649, . CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x364a, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x364b, .CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x364c, .CM_DGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x364d, . CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x364e, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x364f, .CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x3650, .CM_DGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x3651, . CM_DGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x3652, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x3659, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x36ad , .CM_DGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x3645, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x3643, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x3644 , .CM_CONTROL = 0x000034C0 + 0x3625, .CM_DGAM_CONTROL = 0x000034C0 + 0x3642, .CM_TEST_DEBUG_INDEX = 0x000034C0 + 0x36f4, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x36f5, .FORMAT_CONTROL = 0x000034C0 + 0x35db , .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x35da, .CURSOR0_CONTROL = 0x000034C0 + 0x35eb, .CURSOR0_COLOR0 = 0x000034C0 + 0x35ec , .CURSOR0_COLOR1 = 0x000034C0 + 0x35ed, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x35ee, .DPP_CONTROL = 0x000034C0 + 0x35d0, . CM_HDR_MULT_COEF = 0x000034C0 + 0x36ac, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x366e, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x368f, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x3690 , .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x3691, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x3695, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x3696, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x3697 , .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x3698, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x3699, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x369a, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x369b, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x369c, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x369d, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x369e, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x369f, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x36a0, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x36a1, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x36a2, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x36a3 , .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x36a4, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x36a5, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x36a6, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x36a7 , .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x36a8, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x36a9, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x36aa, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x36ab , .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x3672, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x3673, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x3674, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x3678 , .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x3679, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x367a, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x367b, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x367c , .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x367d, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x367e, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x367f, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x3680, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x3681, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x3682, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x3683, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x3684 , .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x3685, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x3686, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x3687, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x3688 , .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x3689, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x368a, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x368b, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x368c , .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x368d, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x368e, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x366f , .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x3670, .CM_3DLUT_MODE = 0x000034C0 + 0x36eb, .CM_3DLUT_INDEX = 0x000034C0 + 0x36ec, . CM_3DLUT_DATA = 0x000034C0 + 0x36ed, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x36ee, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x36ef , .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x36ba, .CM_SHAPER_CONTROL = 0x000034C0 + 0x36b2, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x36d2, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x36d3 , .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x36d4, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x36d5, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x36d6, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x36d7, . CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x36d8, .CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x36d9, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x36da, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x36db, . CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x36dc, .CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x36dd, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x36de, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x36df , .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x36e0, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x36e1, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x36e2, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x36e3 , .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x36e4, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x36e5, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x36e6, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x36e7 , .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x36e8, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x36bb, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x36bc, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x36bd , .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x36be, .CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x36bf, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x36c0, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x36c1, . CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x36c2, .CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x36c3, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x36c4, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x36c5, . CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x36c6, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x36c7, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x36c8, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x36c9 , .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x36ca, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x36cb, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x36cc, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x36cd , .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x36ce, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x36cf, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x36d0, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x36d1 , .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x36b8, .CM_BLNDGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x3671, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x3692, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x3693 , .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x3694, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x3675, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x3676, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x3677 , .CURSOR_CONTROL = 0x000034C0 + 0x09e8, .ALPHA_2BIT_LUT = 0x000034C0 + 0x35e8, .FCNV_FP_BIAS_R = 0x000034C0 + 0x35dc, .FCNV_FP_BIAS_G = 0x000034C0 + 0x35dd, .FCNV_FP_BIAS_B = 0x000034C0 + 0x35de , .FCNV_FP_SCALE_R = 0x000034C0 + 0x35df, .FCNV_FP_SCALE_G = 0x000034C0 + 0x35e0, .FCNV_FP_SCALE_B = 0x000034C0 + 0x35e1, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x35e2, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x35e3 , .COLOR_KEYER_RED = 0x000034C0 + 0x35e4, .COLOR_KEYER_GREEN = 0x000034C0 + 0x35e5, .COLOR_KEYER_BLUE = 0x000034C0 + 0x35e6 , .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x36b9, .CURSOR_CONTROL = 0x000034C0 + 0x09e8, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x3616 , .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x3613, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x363a, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x363b, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x363c, . CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x363d, .CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x363e, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x363f, .CM_ICSC_B_C11_C12 = 0x000034C0 + 0x362d, .CM_ICSC_B_C33_C34 = 0x000034C0 + 0x3632,}, | |||
779 | tf_regs(5)[5] = { .CM_GAMUT_REMAP_CONTROL = 0x000034C0 + 0x379e, .CM_GAMUT_REMAP_C11_C12 = 0x000034C0 + 0x379f, .CM_GAMUT_REMAP_C13_C14 = 0x000034C0 + 0x37a0, .CM_GAMUT_REMAP_C21_C22 = 0x000034C0 + 0x37a1, .CM_GAMUT_REMAP_C23_C24 = 0x000034C0 + 0x37a2, .CM_GAMUT_REMAP_C31_C32 = 0x000034C0 + 0x37a3, .CM_GAMUT_REMAP_C33_C34 = 0x000034C0 + 0x37a4, .DSCL_EXT_OVERSCAN_LEFT_RIGHT = 0x000034C0 + 0x3774, .DSCL_EXT_OVERSCAN_TOP_BOTTOM = 0x000034C0 + 0x3775, .OTG_H_BLANK = 0x000034C0 + 0x3776, .OTG_V_BLANK = 0x000034C0 + 0x3777, .SCL_MODE = 0x000034C0 + 0x3762, .LB_DATA_FORMAT = 0x000034C0 + 0x377b, .LB_MEMORY_CTRL = 0x000034C0 + 0x377c , .DSCL_AUTOCAL = 0x000034C0 + 0x3773, .SCL_BLACK_OFFSET = 0x000034C0 + 0x3771, .SCL_TAP_CONTROL = 0x000034C0 + 0x3763, .SCL_COEF_RAM_TAP_SELECT = 0x000034C0 + 0x3760, .SCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x3761, .DSCL_2TAP_CONTROL = 0x000034C0 + 0x3765, .MPC_SIZE = 0x000034C0 + 0x377a, .SCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x3767, .SCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x376b , .SCL_HORZ_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x3769, .SCL_VERT_FILTER_SCALE_RATIO_C = 0x000034C0 + 0x376e, .SCL_HORZ_FILTER_INIT = 0x000034C0 + 0x3768 , .SCL_HORZ_FILTER_INIT_C = 0x000034C0 + 0x376a, .SCL_VERT_FILTER_INIT = 0x000034C0 + 0x376c, .SCL_VERT_FILTER_INIT_BOT = 0x000034C0 + 0x376d, .SCL_VERT_FILTER_INIT_C = 0x000034C0 + 0x376f, .SCL_VERT_FILTER_INIT_BOT_C = 0x000034C0 + 0x3770, .RECOUT_START = 0x000034C0 + 0x3778, . RECOUT_SIZE = 0x000034C0 + 0x3779, .CM_ICSC_CONTROL = 0x000034C0 + 0x3791, .CM_ICSC_C11_C12 = 0x000034C0 + 0x3792, .CM_ICSC_C33_C34 = 0x000034C0 + 0x3797, .CM_DGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x37c5, .CM_DGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x37c6, . CM_DGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x37c7, .CM_DGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x37c8, .CM_DGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x37c9, .CM_DGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x37ca, . CM_DGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x37cb, .CM_DGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x37cc, .CM_DGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x37cd, .CM_DGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x37ce, . CM_DGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x37cf, .CM_DGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x37d0, .CM_DGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x37d1, .CM_DGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x37d8, . CM_DGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x37b1, .CM_DGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x37b2, .CM_DGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x37b3, .CM_DGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x37b4, . CM_DGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x37b5, .CM_DGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x37b6, .CM_DGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x37b7, .CM_DGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x37b8, . CM_DGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x37b9, .CM_DGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x37ba, .CM_DGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x37bb, .CM_DGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x37bc, . CM_DGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x37bd, .CM_DGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x37c4, .CM_MEM_PWR_CTRL = 0x000034C0 + 0x3818 , .CM_DGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x37b0, .CM_DGAM_LUT_INDEX = 0x000034C0 + 0x37ae, .CM_DGAM_LUT_DATA = 0x000034C0 + 0x37af , .CM_CONTROL = 0x000034C0 + 0x3790, .CM_DGAM_CONTROL = 0x000034C0 + 0x37ad, .CM_TEST_DEBUG_INDEX = 0x000034C0 + 0x385f, .CM_TEST_DEBUG_DATA = 0x000034C0 + 0x3860, .FORMAT_CONTROL = 0x000034C0 + 0x3746 , .CNVC_SURFACE_PIXEL_FORMAT = 0x000034C0 + 0x3745, .CURSOR0_CONTROL = 0x000034C0 + 0x3756, .CURSOR0_COLOR0 = 0x000034C0 + 0x3757 , .CURSOR0_COLOR1 = 0x000034C0 + 0x3758, .CURSOR0_FP_SCALE_BIAS = 0x000034C0 + 0x3759, .DPP_CONTROL = 0x000034C0 + 0x373b, . CM_HDR_MULT_COEF = 0x000034C0 + 0x3817, .CM_BLNDGAM_CONTROL = 0x000034C0 + 0x37d9, .CM_BLNDGAM_RAMB_START_CNTL_B = 0x000034C0 + 0x37fa, .CM_BLNDGAM_RAMB_START_CNTL_G = 0x000034C0 + 0x37fb , .CM_BLNDGAM_RAMB_START_CNTL_R = 0x000034C0 + 0x37fc, .CM_BLNDGAM_RAMB_END_CNTL1_B = 0x000034C0 + 0x3800, .CM_BLNDGAM_RAMB_END_CNTL2_B = 0x000034C0 + 0x3801, .CM_BLNDGAM_RAMB_END_CNTL1_G = 0x000034C0 + 0x3802 , .CM_BLNDGAM_RAMB_END_CNTL2_G = 0x000034C0 + 0x3803, .CM_BLNDGAM_RAMB_END_CNTL1_R = 0x000034C0 + 0x3804, .CM_BLNDGAM_RAMB_END_CNTL2_R = 0x000034C0 + 0x3805, .CM_BLNDGAM_RAMB_REGION_0_1 = 0x000034C0 + 0x3806, .CM_BLNDGAM_RAMB_REGION_2_3 = 0x000034C0 + 0x3807, .CM_BLNDGAM_RAMB_REGION_4_5 = 0x000034C0 + 0x3808, .CM_BLNDGAM_RAMB_REGION_6_7 = 0x000034C0 + 0x3809, .CM_BLNDGAM_RAMB_REGION_8_9 = 0x000034C0 + 0x380a, .CM_BLNDGAM_RAMB_REGION_10_11 = 0x000034C0 + 0x380b, .CM_BLNDGAM_RAMB_REGION_12_13 = 0x000034C0 + 0x380c, .CM_BLNDGAM_RAMB_REGION_14_15 = 0x000034C0 + 0x380d, .CM_BLNDGAM_RAMB_REGION_16_17 = 0x000034C0 + 0x380e , .CM_BLNDGAM_RAMB_REGION_18_19 = 0x000034C0 + 0x380f, .CM_BLNDGAM_RAMB_REGION_20_21 = 0x000034C0 + 0x3810, .CM_BLNDGAM_RAMB_REGION_22_23 = 0x000034C0 + 0x3811, .CM_BLNDGAM_RAMB_REGION_24_25 = 0x000034C0 + 0x3812 , .CM_BLNDGAM_RAMB_REGION_26_27 = 0x000034C0 + 0x3813, .CM_BLNDGAM_RAMB_REGION_28_29 = 0x000034C0 + 0x3814, .CM_BLNDGAM_RAMB_REGION_30_31 = 0x000034C0 + 0x3815, .CM_BLNDGAM_RAMB_REGION_32_33 = 0x000034C0 + 0x3816 , .CM_BLNDGAM_RAMA_START_CNTL_B = 0x000034C0 + 0x37dd, .CM_BLNDGAM_RAMA_START_CNTL_G = 0x000034C0 + 0x37de, .CM_BLNDGAM_RAMA_START_CNTL_R = 0x000034C0 + 0x37df, .CM_BLNDGAM_RAMA_END_CNTL1_B = 0x000034C0 + 0x37e3 , .CM_BLNDGAM_RAMA_END_CNTL2_B = 0x000034C0 + 0x37e4, .CM_BLNDGAM_RAMA_END_CNTL1_G = 0x000034C0 + 0x37e5, .CM_BLNDGAM_RAMA_END_CNTL2_G = 0x000034C0 + 0x37e6, .CM_BLNDGAM_RAMA_END_CNTL1_R = 0x000034C0 + 0x37e7 , .CM_BLNDGAM_RAMA_END_CNTL2_R = 0x000034C0 + 0x37e8, .CM_BLNDGAM_RAMA_REGION_0_1 = 0x000034C0 + 0x37e9, .CM_BLNDGAM_RAMA_REGION_2_3 = 0x000034C0 + 0x37ea, .CM_BLNDGAM_RAMA_REGION_4_5 = 0x000034C0 + 0x37eb, .CM_BLNDGAM_RAMA_REGION_6_7 = 0x000034C0 + 0x37ec, .CM_BLNDGAM_RAMA_REGION_8_9 = 0x000034C0 + 0x37ed, .CM_BLNDGAM_RAMA_REGION_10_11 = 0x000034C0 + 0x37ee, .CM_BLNDGAM_RAMA_REGION_12_13 = 0x000034C0 + 0x37ef , .CM_BLNDGAM_RAMA_REGION_14_15 = 0x000034C0 + 0x37f0, .CM_BLNDGAM_RAMA_REGION_16_17 = 0x000034C0 + 0x37f1, .CM_BLNDGAM_RAMA_REGION_18_19 = 0x000034C0 + 0x37f2, .CM_BLNDGAM_RAMA_REGION_20_21 = 0x000034C0 + 0x37f3 , .CM_BLNDGAM_RAMA_REGION_22_23 = 0x000034C0 + 0x37f4, .CM_BLNDGAM_RAMA_REGION_24_25 = 0x000034C0 + 0x37f5, .CM_BLNDGAM_RAMA_REGION_26_27 = 0x000034C0 + 0x37f6, .CM_BLNDGAM_RAMA_REGION_28_29 = 0x000034C0 + 0x37f7 , .CM_BLNDGAM_RAMA_REGION_30_31 = 0x000034C0 + 0x37f8, .CM_BLNDGAM_RAMA_REGION_32_33 = 0x000034C0 + 0x37f9, .CM_BLNDGAM_LUT_INDEX = 0x000034C0 + 0x37da , .CM_BLNDGAM_LUT_DATA = 0x000034C0 + 0x37db, .CM_3DLUT_MODE = 0x000034C0 + 0x3856, .CM_3DLUT_INDEX = 0x000034C0 + 0x3857, . CM_3DLUT_DATA = 0x000034C0 + 0x3858, .CM_3DLUT_DATA_30BIT = 0x000034C0 + 0x3859, .CM_3DLUT_READ_WRITE_CONTROL = 0x000034C0 + 0x385a , .CM_SHAPER_LUT_WRITE_EN_MASK = 0x000034C0 + 0x3825, .CM_SHAPER_CONTROL = 0x000034C0 + 0x381d, .CM_SHAPER_RAMB_START_CNTL_B = 0x000034C0 + 0x383d, .CM_SHAPER_RAMB_START_CNTL_G = 0x000034C0 + 0x383e , .CM_SHAPER_RAMB_START_CNTL_R = 0x000034C0 + 0x383f, .CM_SHAPER_RAMB_END_CNTL_B = 0x000034C0 + 0x3840, .CM_SHAPER_RAMB_END_CNTL_G = 0x000034C0 + 0x3841, .CM_SHAPER_RAMB_END_CNTL_R = 0x000034C0 + 0x3842, . CM_SHAPER_RAMB_REGION_0_1 = 0x000034C0 + 0x3843, .CM_SHAPER_RAMB_REGION_2_3 = 0x000034C0 + 0x3844, .CM_SHAPER_RAMB_REGION_4_5 = 0x000034C0 + 0x3845, .CM_SHAPER_RAMB_REGION_6_7 = 0x000034C0 + 0x3846, . CM_SHAPER_RAMB_REGION_8_9 = 0x000034C0 + 0x3847, .CM_SHAPER_RAMB_REGION_10_11 = 0x000034C0 + 0x3848, .CM_SHAPER_RAMB_REGION_12_13 = 0x000034C0 + 0x3849, .CM_SHAPER_RAMB_REGION_14_15 = 0x000034C0 + 0x384a , .CM_SHAPER_RAMB_REGION_16_17 = 0x000034C0 + 0x384b, .CM_SHAPER_RAMB_REGION_18_19 = 0x000034C0 + 0x384c, .CM_SHAPER_RAMB_REGION_20_21 = 0x000034C0 + 0x384d, .CM_SHAPER_RAMB_REGION_22_23 = 0x000034C0 + 0x384e , .CM_SHAPER_RAMB_REGION_24_25 = 0x000034C0 + 0x384f, .CM_SHAPER_RAMB_REGION_26_27 = 0x000034C0 + 0x3850, .CM_SHAPER_RAMB_REGION_28_29 = 0x000034C0 + 0x3851, .CM_SHAPER_RAMB_REGION_30_31 = 0x000034C0 + 0x3852 , .CM_SHAPER_RAMB_REGION_32_33 = 0x000034C0 + 0x3853, .CM_SHAPER_RAMA_START_CNTL_B = 0x000034C0 + 0x3826, .CM_SHAPER_RAMA_START_CNTL_G = 0x000034C0 + 0x3827, .CM_SHAPER_RAMA_START_CNTL_R = 0x000034C0 + 0x3828 , .CM_SHAPER_RAMA_END_CNTL_B = 0x000034C0 + 0x3829, .CM_SHAPER_RAMA_END_CNTL_G = 0x000034C0 + 0x382a, .CM_SHAPER_RAMA_END_CNTL_R = 0x000034C0 + 0x382b, .CM_SHAPER_RAMA_REGION_0_1 = 0x000034C0 + 0x382c, . CM_SHAPER_RAMA_REGION_2_3 = 0x000034C0 + 0x382d, .CM_SHAPER_RAMA_REGION_4_5 = 0x000034C0 + 0x382e, .CM_SHAPER_RAMA_REGION_6_7 = 0x000034C0 + 0x382f, .CM_SHAPER_RAMA_REGION_8_9 = 0x000034C0 + 0x3830, . CM_SHAPER_RAMA_REGION_10_11 = 0x000034C0 + 0x3831, .CM_SHAPER_RAMA_REGION_12_13 = 0x000034C0 + 0x3832, .CM_SHAPER_RAMA_REGION_14_15 = 0x000034C0 + 0x3833, .CM_SHAPER_RAMA_REGION_16_17 = 0x000034C0 + 0x3834 , .CM_SHAPER_RAMA_REGION_18_19 = 0x000034C0 + 0x3835, .CM_SHAPER_RAMA_REGION_20_21 = 0x000034C0 + 0x3836, .CM_SHAPER_RAMA_REGION_22_23 = 0x000034C0 + 0x3837, .CM_SHAPER_RAMA_REGION_24_25 = 0x000034C0 + 0x3838 , .CM_SHAPER_RAMA_REGION_26_27 = 0x000034C0 + 0x3839, .CM_SHAPER_RAMA_REGION_28_29 = 0x000034C0 + 0x383a, .CM_SHAPER_RAMA_REGION_30_31 = 0x000034C0 + 0x383b, .CM_SHAPER_RAMA_REGION_32_33 = 0x000034C0 + 0x383c , .CM_SHAPER_LUT_INDEX = 0x000034C0 + 0x3823, .CM_BLNDGAM_LUT_WRITE_EN_MASK = 0x000034C0 + 0x37dc, .CM_BLNDGAM_RAMB_SLOPE_CNTL_B = 0x000034C0 + 0x37fd, .CM_BLNDGAM_RAMB_SLOPE_CNTL_G = 0x000034C0 + 0x37fe , .CM_BLNDGAM_RAMB_SLOPE_CNTL_R = 0x000034C0 + 0x37ff, .CM_BLNDGAM_RAMA_SLOPE_CNTL_B = 0x000034C0 + 0x37e0, .CM_BLNDGAM_RAMA_SLOPE_CNTL_G = 0x000034C0 + 0x37e1, .CM_BLNDGAM_RAMA_SLOPE_CNTL_R = 0x000034C0 + 0x37e2 , .CURSOR_CONTROL = 0x000034C0 + 0x0ac4, .ALPHA_2BIT_LUT = 0x000034C0 + 0x3753, .FCNV_FP_BIAS_R = 0x000034C0 + 0x3747, .FCNV_FP_BIAS_G = 0x000034C0 + 0x3748, .FCNV_FP_BIAS_B = 0x000034C0 + 0x3749 , .FCNV_FP_SCALE_R = 0x000034C0 + 0x374a, .FCNV_FP_SCALE_G = 0x000034C0 + 0x374b, .FCNV_FP_SCALE_B = 0x000034C0 + 0x374c, .COLOR_KEYER_CONTROL = 0x000034C0 + 0x374d, .COLOR_KEYER_ALPHA = 0x000034C0 + 0x374e , .COLOR_KEYER_RED = 0x000034C0 + 0x374f, .COLOR_KEYER_GREEN = 0x000034C0 + 0x3750, .COLOR_KEYER_BLUE = 0x000034C0 + 0x3751 , .CM_SHAPER_LUT_DATA = 0x000034C0 + 0x3824, .CURSOR_CONTROL = 0x000034C0 + 0x0ac4, .OBUF_MEM_PWR_CTRL = 0x000034C0 + 0x3781 , .DSCL_MEM_PWR_CTRL = 0x000034C0 + 0x377e, .CM_GAMUT_REMAP_B_C11_C12 = 0x000034C0 + 0x37a5, .CM_GAMUT_REMAP_B_C13_C14 = 0x000034C0 + 0x37a6, .CM_GAMUT_REMAP_B_C21_C22 = 0x000034C0 + 0x37a7, . CM_GAMUT_REMAP_B_C23_C24 = 0x000034C0 + 0x37a8, .CM_GAMUT_REMAP_B_C31_C32 = 0x000034C0 + 0x37a9, .CM_GAMUT_REMAP_B_C33_C34 = 0x000034C0 + 0x37aa, .CM_ICSC_B_C11_C12 = 0x000034C0 + 0x3798, .CM_ICSC_B_C33_C34 = 0x000034C0 + 0x379d,}, | |||
780 | }; | |||
781 | ||||
782 | static const struct dcn2_dpp_shift tf_shift = { | |||
783 | TF_REG_LIST_SH_MASK_DCN20(__SHIFT).CM_GAMUT_REMAP_MODE = 0x0, .CM_GAMUT_REMAP_C11 = 0x0, .CM_GAMUT_REMAP_C12 = 0x10, .CM_GAMUT_REMAP_C13 = 0x0, .CM_GAMUT_REMAP_C14 = 0x10 , .CM_GAMUT_REMAP_C21 = 0x0, .CM_GAMUT_REMAP_C22 = 0x10, .CM_GAMUT_REMAP_C23 = 0x0, .CM_GAMUT_REMAP_C24 = 0x10, .CM_GAMUT_REMAP_C31 = 0x0 , .CM_GAMUT_REMAP_C32 = 0x10, .CM_GAMUT_REMAP_C33 = 0x0, .CM_GAMUT_REMAP_C34 = 0x10, .EXT_OVERSCAN_LEFT = 0x10, .EXT_OVERSCAN_RIGHT = 0x0 , .EXT_OVERSCAN_BOTTOM = 0x0, .EXT_OVERSCAN_TOP = 0x10, .OTG_H_BLANK_START = 0x0, .OTG_H_BLANK_END = 0x10, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END = 0x10, .INTERLEAVE_EN = 0x0, .LB_DATA_FORMAT__ALPHA_EN = 0x4 , .MEMORY_CONFIG = 0x0, .LB_MAX_PARTITIONS = 0x8, .AUTOCAL_MODE = 0x0, .AUTOCAL_NUM_PIPE = 0x8, .AUTOCAL_PIPE_ID = 0xc, .SCL_BLACK_OFFSET_RGB_Y = 0x0, .SCL_BLACK_OFFSET_CBCR = 0x10, .SCL_V_NUM_TAPS = 0x0, .SCL_H_NUM_TAPS = 0x4, .SCL_V_NUM_TAPS_C = 0x8, .SCL_H_NUM_TAPS_C = 0xc, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x0, .SCL_COEF_RAM_PHASE = 0x8, .SCL_COEF_RAM_FILTER_TYPE = 0x10, .SCL_COEF_RAM_EVEN_TAP_COEF = 0x0, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0xf, .SCL_COEF_RAM_ODD_TAP_COEF = 0x10, .SCL_COEF_RAM_ODD_TAP_COEF_EN = 0x1f, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x0, .SCL_H_2TAP_SHARP_EN = 0x4, .SCL_H_2TAP_SHARP_FACTOR = 0x8, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x10, .SCL_V_2TAP_SHARP_EN = 0x14, .SCL_V_2TAP_SHARP_FACTOR = 0x18, .SCL_COEF_RAM_SELECT = 0x8, .DSCL_MODE = 0x0, .RECOUT_START_X = 0x0, .RECOUT_START_Y = 0x10, .RECOUT_WIDTH = 0x0, .RECOUT_HEIGHT = 0x10, .MPC_WIDTH = 0x0, .MPC_HEIGHT = 0x10, .SCL_H_SCALE_RATIO = 0x0, .SCL_V_SCALE_RATIO = 0x0, .SCL_H_SCALE_RATIO_C = 0x0, .SCL_V_SCALE_RATIO_C = 0x0 , .SCL_H_INIT_FRAC = 0x0, .SCL_H_INIT_INT = 0x18, .SCL_H_INIT_FRAC_C = 0x0, .SCL_H_INIT_INT_C = 0x18, .SCL_V_INIT_FRAC = 0x0, .SCL_V_INIT_INT = 0x18, .SCL_V_INIT_FRAC_BOT = 0x0, .SCL_V_INIT_INT_BOT = 0x18 , .SCL_V_INIT_FRAC_C = 0x0, .SCL_V_INIT_INT_C = 0x18, .SCL_V_INIT_FRAC_BOT_C = 0x0, .SCL_V_INIT_INT_BOT_C = 0x18, .SCL_CHROMA_COEF_MODE = 0x10, .SCL_COEF_RAM_SELECT_CURRENT = 0xc, .CM_ICSC_MODE = 0x0 , .CM_ICSC_C11 = 0x0, .CM_ICSC_C12 = 0x10, .CM_ICSC_C33 = 0x0 , .CM_ICSC_C34 = 0x10, .CM_DGAM_RAMB_EXP_REGION_START_B = 0x0 , .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .CM_DGAM_RAMB_EXP_REGION_START_G = 0x0, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .CM_DGAM_RAMB_EXP_REGION_START_R = 0x0, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G = 0x0, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_B = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_BASE_B = 0x10, .CM_DGAM_RAMB_EXP_REGION_END_G = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_BASE_G = 0x10, .CM_DGAM_RAMB_EXP_REGION_END_R = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x0, .CM_DGAM_RAMB_EXP_REGION_END_BASE_R = 0x10, .CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_DGAM_RAMA_EXP_REGION_START_B = 0x0, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_DGAM_RAMA_EXP_REGION_START_G = 0x0, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .CM_DGAM_RAMA_EXP_REGION_START_R = 0x0, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G = 0x0, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_B = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_BASE_B = 0x10, .CM_DGAM_RAMA_EXP_REGION_END_G = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_BASE_G = 0x10, .CM_DGAM_RAMA_EXP_REGION_END_R = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x0, .CM_DGAM_RAMA_EXP_REGION_END_BASE_R = 0x10, .CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .SHARED_MEM_PWR_DIS = 0x2, .CM_DGAM_LUT_WRITE_EN_MASK = 0x0, .CM_DGAM_LUT_WRITE_SEL = 0x4, .CM_DGAM_LUT_INDEX = 0x0, .CM_DGAM_LUT_DATA = 0x0, .CM_DGAM_LUT_MODE = 0x0, .CM_TEST_DEBUG_INDEX = 0x0, .CNVC_BYPASS = 0xc, .FORMAT_CONTROL__ALPHA_EN = 0x8, .FORMAT_EXPANSION_MODE = 0x0, .CNVC_SURFACE_PIXEL_FORMAT = 0x0, .CUR0_MODE = 0x4, .CUR0_EXPANSION_MODE = 0x1, .CUR0_ENABLE = 0x0, .CUR0_COLOR0 = 0x0, .CUR0_COLOR1 = 0x0, .CUR0_FP_BIAS = 0x10, .CUR0_FP_SCALE = 0x0, .DPP_CLOCK_ENABLE = 0x4, .CM_HDR_MULT_COEF = 0x0, .CM_3DLUT_MODE = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, . CM_BLNDGAM_RAMB_EXP_REGION_START_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .CM_BLNDGAM_RAMB_EXP_REGION_START_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, . CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION_START_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_START_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_START_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, . CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_BLNDGAM_LUT_INDEX = 0x0, .CM_BLNDGAM_LUT_DATA = 0x0 , .BLNDGAM_MEM_PWR_FORCE = 0x4, .CM_3DLUT_MODE = 0x0, .CM_3DLUT_SIZE = 0x4, .CM_3DLUT_INDEX = 0x0, .CM_3DLUT_DATA0 = 0x0, .CM_3DLUT_DATA1 = 0x10, .CM_3DLUT_DATA_30BIT = 0x2, .CM_3DLUT_WRITE_EN_MASK = 0x0, .CM_3DLUT_RAM_SEL = 0x4, .CM_3DLUT_30BIT_EN = 0x8, .CM_3DLUT_READ_SEL = 0x10, .CM_SHAPER_LUT_MODE = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_B = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .CM_SHAPER_RAMB_EXP_REGION_START_G = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G = 0x14, .CM_SHAPER_RAMB_EXP_REGION_START_R = 0x0, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R = 0x14, .CM_SHAPER_RAMB_EXP_REGION_END_B = 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_B = 0x10, .CM_SHAPER_RAMB_EXP_REGION_END_G = 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_G = 0x10, .CM_SHAPER_RAMB_EXP_REGION_END_R = 0x0, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_R = 0x10, .CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET = 0x0, .CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET = 0x10, .CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION_START_B = 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .CM_SHAPER_RAMA_EXP_REGION_START_G = 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G = 0x14, .CM_SHAPER_RAMA_EXP_REGION_START_R = 0x0, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R = 0x14, .CM_SHAPER_RAMA_EXP_REGION_END_B = 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x10, .CM_SHAPER_RAMA_EXP_REGION_END_G = 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_G = 0x10, .CM_SHAPER_RAMA_EXP_REGION_END_R = 0x0, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_R = 0x10, .CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x1c, .CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET = 0x0, .CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS = 0xc, .CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET = 0x10, .CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x1c, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x0, .CM_SHAPER_LUT_WRITE_SEL = 0x4, .CM_SHAPER_LUT_INDEX = 0x0, .CM_SHAPER_LUT_DATA = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_B = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_G = 0x0, .CM_BLNDGAM_RAMB_EXP_REGION_END_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_B = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_G = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_R = 0x0, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G = 0x10, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R = 0x10, .CM_BLNDGAM_LUT_MODE = 0x0, .CM_BLNDGAM_LUT_WRITE_EN_MASK = 0x0, .CM_BLNDGAM_LUT_WRITE_SEL = 0x4, .CM_BLNDGAM_CONFIG_STATUS = 0x8, .CM_SHAPER_LUT_MODE = 0x0, .CM_DGAM_CONFIG_STATUS = 0x8 , .CM_BYPASS = 0x0, .CURSOR_MODE = 0x8, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK = 0x18, .CURSOR_ENABLE = 0x0, .FORMAT_CNV16 = 0x4, .CNVC_BYPASS_MSB_ALIGN = 0xd, .CLAMP_POSITIVE = 0x10, .CLAMP_POSITIVE_C = 0x11, .ALPHA_2BIT_LUT0 = 0x0, .ALPHA_2BIT_LUT1 = 0x8, .ALPHA_2BIT_LUT2 = 0x10, .ALPHA_2BIT_LUT3 = 0x18, .FCNV_FP_BIAS_R = 0x0, .FCNV_FP_BIAS_G = 0x0, .FCNV_FP_BIAS_B = 0x0, .FCNV_FP_SCALE_R = 0x0, .FCNV_FP_SCALE_G = 0x0, .FCNV_FP_SCALE_B = 0x0, .COLOR_KEYER_EN = 0x0, .COLOR_KEYER_MODE = 0x4, .COLOR_KEYER_ALPHA_LOW = 0x0 , .COLOR_KEYER_ALPHA_HIGH = 0x10, .COLOR_KEYER_RED_LOW = 0x0, .COLOR_KEYER_RED_HIGH = 0x10, .COLOR_KEYER_GREEN_LOW = 0x0, . COLOR_KEYER_GREEN_HIGH = 0x10, .COLOR_KEYER_BLUE_LOW = 0x0, . COLOR_KEYER_BLUE_HIGH = 0x10, .CUR0_PIX_INV_MODE = 0x2, .CUR0_PIXEL_ALPHA_MOD_EN = 0x7, .CUR0_ROM_EN = 0x3, .OBUF_MEM_PWR_FORCE = 0x0, .LUT_MEM_PWR_FORCE = 0x0, | |||
784 | TF_DEBUG_REG_LIST_SH_DCN20.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16, .CM_TEST_DEBUG_DATA_ICSC_MODE = 3, .CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE = 9 | |||
785 | }; | |||
786 | ||||
787 | static const struct dcn2_dpp_mask tf_mask = { | |||
788 | TF_REG_LIST_SH_MASK_DCN20(_MASK).CM_GAMUT_REMAP_MODE = 0x00000003L, .CM_GAMUT_REMAP_C11 = 0x0000FFFFL , .CM_GAMUT_REMAP_C12 = 0xFFFF0000L, .CM_GAMUT_REMAP_C13 = 0x0000FFFFL , .CM_GAMUT_REMAP_C14 = 0xFFFF0000L, .CM_GAMUT_REMAP_C21 = 0x0000FFFFL , .CM_GAMUT_REMAP_C22 = 0xFFFF0000L, .CM_GAMUT_REMAP_C23 = 0x0000FFFFL , .CM_GAMUT_REMAP_C24 = 0xFFFF0000L, .CM_GAMUT_REMAP_C31 = 0x0000FFFFL , .CM_GAMUT_REMAP_C32 = 0xFFFF0000L, .CM_GAMUT_REMAP_C33 = 0x0000FFFFL , .CM_GAMUT_REMAP_C34 = 0xFFFF0000L, .EXT_OVERSCAN_LEFT = 0x1FFF0000L , .EXT_OVERSCAN_RIGHT = 0x00001FFFL, .EXT_OVERSCAN_BOTTOM = 0x00001FFFL , .EXT_OVERSCAN_TOP = 0x1FFF0000L, .OTG_H_BLANK_START = 0x00003FFFL , .OTG_H_BLANK_END = 0x3FFF0000L, .OTG_V_BLANK_START = 0x00003FFFL , .OTG_V_BLANK_END = 0x3FFF0000L, .INTERLEAVE_EN = 0x00000001L , .LB_DATA_FORMAT__ALPHA_EN = 0x00000010L, .MEMORY_CONFIG = 0x00000003L , .LB_MAX_PARTITIONS = 0x00003F00L, .AUTOCAL_MODE = 0x00000003L , .AUTOCAL_NUM_PIPE = 0x00000300L, .AUTOCAL_PIPE_ID = 0x00003000L , .SCL_BLACK_OFFSET_RGB_Y = 0x0000FFFFL, .SCL_BLACK_OFFSET_CBCR = 0xFFFF0000L, .SCL_V_NUM_TAPS = 0x00000007L, .SCL_H_NUM_TAPS = 0x00000070L, .SCL_V_NUM_TAPS_C = 0x00000700L, .SCL_H_NUM_TAPS_C = 0x00007000L, .SCL_COEF_RAM_TAP_PAIR_IDX = 0x00000003L, .SCL_COEF_RAM_PHASE = 0x00003F00L, .SCL_COEF_RAM_FILTER_TYPE = 0x00070000L, .SCL_COEF_RAM_EVEN_TAP_COEF = 0x00003FFFL, .SCL_COEF_RAM_EVEN_TAP_COEF_EN = 0x00008000L, .SCL_COEF_RAM_ODD_TAP_COEF = 0x3FFF0000L, .SCL_COEF_RAM_ODD_TAP_COEF_EN = 0x80000000L, .SCL_H_2TAP_HARDCODE_COEF_EN = 0x00000001L, . SCL_H_2TAP_SHARP_EN = 0x00000010L, .SCL_H_2TAP_SHARP_FACTOR = 0x00000700L, .SCL_V_2TAP_HARDCODE_COEF_EN = 0x00010000L, .SCL_V_2TAP_SHARP_EN = 0x00100000L, .SCL_V_2TAP_SHARP_FACTOR = 0x07000000L, .SCL_COEF_RAM_SELECT = 0x00000100L, .DSCL_MODE = 0x00000007L, .RECOUT_START_X = 0x00001FFFL , .RECOUT_START_Y = 0x1FFF0000L, .RECOUT_WIDTH = 0x00003FFFL, .RECOUT_HEIGHT = 0x3FFF0000L, .MPC_WIDTH = 0x00003FFFL, .MPC_HEIGHT = 0x3FFF0000L, .SCL_H_SCALE_RATIO = 0x03FFFFFFL, .SCL_V_SCALE_RATIO = 0x03FFFFFFL, .SCL_H_SCALE_RATIO_C = 0x03FFFFFFL, .SCL_V_SCALE_RATIO_C = 0x03FFFFFFL, .SCL_H_INIT_FRAC = 0x00FFFFFFL, .SCL_H_INIT_INT = 0x0F000000L, .SCL_H_INIT_FRAC_C = 0x00FFFFFFL, .SCL_H_INIT_INT_C = 0x0F000000L, .SCL_V_INIT_FRAC = 0x00FFFFFFL, .SCL_V_INIT_INT = 0x0F000000L, .SCL_V_INIT_FRAC_BOT = 0x00FFFFFFL, .SCL_V_INIT_INT_BOT = 0x0F000000L, .SCL_V_INIT_FRAC_C = 0x00FFFFFFL, .SCL_V_INIT_INT_C = 0x0F000000L, .SCL_V_INIT_FRAC_BOT_C = 0x00FFFFFFL, .SCL_V_INIT_INT_BOT_C = 0x0F000000L, .SCL_CHROMA_COEF_MODE = 0x00010000L, .SCL_COEF_RAM_SELECT_CURRENT = 0x00001000L, .CM_ICSC_MODE = 0x00000003L, .CM_ICSC_C11 = 0x0000FFFFL , .CM_ICSC_C12 = 0xFFFF0000L, .CM_ICSC_C33 = 0x0000FFFFL, .CM_ICSC_C34 = 0xFFFF0000L, .CM_DGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL , .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .CM_DGAM_RAMB_EXP_REGION_START_G = 0x0003FFFFL, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L , .CM_DGAM_RAMB_EXP_REGION_START_R = 0x0003FFFFL, .CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL , .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G = 0x0003FFFFL, .CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R = 0x0003FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_BASE_B = 0xFFFF0000L, .CM_DGAM_RAMB_EXP_REGION_END_G = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_BASE_G = 0xFFFF0000L, .CM_DGAM_RAMB_EXP_REGION_END_R = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x0000FFFFL, .CM_DGAM_RAMB_EXP_REGION_END_BASE_R = 0xFFFF0000L, .CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL , .CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L , .CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL, .CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L , .CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_DGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L , .CM_DGAM_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .CM_DGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL , .CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL, .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G = 0x0003FFFFL , .CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R = 0x0003FFFFL, .CM_DGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0000FFFFL , .CM_DGAM_RAMA_EXP_REGION_END_BASE_B = 0xFFFF0000L, .CM_DGAM_RAMA_EXP_REGION_END_G = 0x0000FFFFL, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G = 0x0000FFFFL , .CM_DGAM_RAMA_EXP_REGION_END_BASE_G = 0xFFFF0000L, .CM_DGAM_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x0000FFFFL , .CM_DGAM_RAMA_EXP_REGION_END_BASE_R = 0xFFFF0000L, .CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L , .CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, .CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L , .SHARED_MEM_PWR_DIS = 0x00000004L, .CM_DGAM_LUT_WRITE_EN_MASK = 0x00000007L, .CM_DGAM_LUT_WRITE_SEL = 0x00000010L, .CM_DGAM_LUT_INDEX = 0x000001FFL, .CM_DGAM_LUT_DATA = 0x0007FFFFL, .CM_DGAM_LUT_MODE = 0x00000007L, .CM_TEST_DEBUG_INDEX = 0x000000FFL, .CNVC_BYPASS = 0x00001000L, .FORMAT_CONTROL__ALPHA_EN = 0x00000100L, .FORMAT_EXPANSION_MODE = 0x00000001L, .CNVC_SURFACE_PIXEL_FORMAT = 0x0000007FL, .CUR0_MODE = 0x00000070L, .CUR0_EXPANSION_MODE = 0x00000002L, .CUR0_ENABLE = 0x00000001L, .CUR0_COLOR0 = 0x00FFFFFFL, .CUR0_COLOR1 = 0x00FFFFFFL , .CUR0_FP_BIAS = 0xFFFF0000L, .CUR0_FP_SCALE = 0x0000FFFFL, . DPP_CLOCK_ENABLE = 0x00000010L, .CM_HDR_MULT_COEF = 0x0007FFFFL , .CM_3DLUT_MODE = 0x00000003L, .CM_BLNDGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .CM_BLNDGAM_RAMB_EXP_REGION_START_G = 0x0003FFFFL , .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L, . CM_BLNDGAM_RAMB_EXP_REGION_START_R = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0000FFFFL , .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G = 0x0000FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R = 0x0000FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L , .CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L , .CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L , .CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L , .CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L , .CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L , .CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . CM_BLNDGAM_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .CM_BLNDGAM_RAMA_EXP_REGION_START_R = 0x0003FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, . CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G = 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R = 0x0000FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L , .CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L , .CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L , .CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L , .CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L , .CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL , .CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L, . CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x70000000L, .CM_BLNDGAM_LUT_INDEX = 0x000001FFL, .CM_BLNDGAM_LUT_DATA = 0x0007FFFFL, .BLNDGAM_MEM_PWR_FORCE = 0x00000030L, .CM_3DLUT_MODE = 0x00000003L, .CM_3DLUT_SIZE = 0x00000010L, .CM_3DLUT_INDEX = 0x000007FFL, .CM_3DLUT_DATA0 = 0x0000FFFFL, .CM_3DLUT_DATA1 = 0xFFFF0000L, .CM_3DLUT_DATA_30BIT = 0xFFFFFFFCL, .CM_3DLUT_WRITE_EN_MASK = 0x0000000FL, .CM_3DLUT_RAM_SEL = 0x00000010L, .CM_3DLUT_30BIT_EN = 0x00000100L, .CM_3DLUT_READ_SEL = 0x00030000L, .CM_SHAPER_LUT_MODE = 0x00000003L, .CM_SHAPER_RAMB_EXP_REGION_START_B = 0x0003FFFFL , .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . CM_SHAPER_RAMB_EXP_REGION_START_G = 0x0003FFFFL, .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .CM_SHAPER_RAMB_EXP_REGION_START_R = 0x0003FFFFL , .CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R = 0x07F00000L, . CM_SHAPER_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_B = 0x3FFF0000L, .CM_SHAPER_RAMB_EXP_REGION_END_G = 0x0000FFFFL , .CM_SHAPER_RAMB_EXP_REGION_END_BASE_G = 0x3FFF0000L, .CM_SHAPER_RAMB_EXP_REGION_END_R = 0x0000FFFFL, .CM_SHAPER_RAMB_EXP_REGION_END_BASE_R = 0x3FFF0000L , .CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION_START_B = 0x0003FFFFL , .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, . CM_SHAPER_RAMA_EXP_REGION_START_G = 0x0003FFFFL, .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G = 0x07F00000L, .CM_SHAPER_RAMA_EXP_REGION_START_R = 0x0003FFFFL , .CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R = 0x07F00000L, . CM_SHAPER_RAMA_EXP_REGION_END_B = 0x0000FFFFL, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_B = 0x3FFF0000L, .CM_SHAPER_RAMA_EXP_REGION_END_G = 0x0000FFFFL , .CM_SHAPER_RAMA_EXP_REGION_END_BASE_G = 0x3FFF0000L, .CM_SHAPER_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .CM_SHAPER_RAMA_EXP_REGION_END_BASE_R = 0x3FFF0000L , .CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET = 0x000001FFL , .CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS = 0x70000000L , .CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS = 0x00007000L, .CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET = 0x01FF0000L , .CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET = 0x000001FFL, .CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS = 0x00007000L , .CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET = 0x01FF0000L, .CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS = 0x70000000L, .CM_SHAPER_LUT_WRITE_EN_MASK = 0x00000007L, . CM_SHAPER_LUT_WRITE_SEL = 0x00000010L, .CM_SHAPER_LUT_INDEX = 0x000000FFL, .CM_SHAPER_LUT_DATA = 0x00FFFFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G = 0x0003FFFFL , .CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R = 0x0003FFFFL, . CM_BLNDGAM_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_G = 0x0000FFFFL, .CM_BLNDGAM_RAMB_EXP_REGION_END_R = 0x0000FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL, . CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R = 0x0003FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL , .CM_BLNDGAM_RAMA_EXP_REGION_END_G = 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_R = 0x0000FFFFL, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B = 0xFFFF0000L , .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G = 0xFFFF0000L, .CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R = 0xFFFF0000L, .CM_BLNDGAM_LUT_MODE = 0x00000003L, .CM_BLNDGAM_LUT_WRITE_EN_MASK = 0x00000007L, .CM_BLNDGAM_LUT_WRITE_SEL = 0x00000010L, .CM_BLNDGAM_CONFIG_STATUS = 0x00000300L, .CM_SHAPER_LUT_MODE = 0x00000003L, .CM_DGAM_CONFIG_STATUS = 0x00000700L, .CM_BYPASS = 0x00000001L, .CURSOR_MODE = 0x00000700L , .CURSOR_PITCH = 0x00030000L, .CURSOR_LINES_PER_CHUNK = 0x1F000000L , .CURSOR_ENABLE = 0x00000001L, .FORMAT_CNV16 = 0x00000010L, . CNVC_BYPASS_MSB_ALIGN = 0x00002000L, .CLAMP_POSITIVE = 0x00010000L , .CLAMP_POSITIVE_C = 0x00020000L, .ALPHA_2BIT_LUT0 = 0x000000FFL , .ALPHA_2BIT_LUT1 = 0x0000FF00L, .ALPHA_2BIT_LUT2 = 0x00FF0000L , .ALPHA_2BIT_LUT3 = 0xFF000000L, .FCNV_FP_BIAS_R = 0x0007FFFFL , .FCNV_FP_BIAS_G = 0x0007FFFFL, .FCNV_FP_BIAS_B = 0x0007FFFFL , .FCNV_FP_SCALE_R = 0x0007FFFFL, .FCNV_FP_SCALE_G = 0x0007FFFFL , .FCNV_FP_SCALE_B = 0x0007FFFFL, .COLOR_KEYER_EN = 0x00000001L , .COLOR_KEYER_MODE = 0x00000030L, .COLOR_KEYER_ALPHA_LOW = 0x0000FFFFL , .COLOR_KEYER_ALPHA_HIGH = 0xFFFF0000L, .COLOR_KEYER_RED_LOW = 0x0000FFFFL, .COLOR_KEYER_RED_HIGH = 0xFFFF0000L, .COLOR_KEYER_GREEN_LOW = 0x0000FFFFL, .COLOR_KEYER_GREEN_HIGH = 0xFFFF0000L, .COLOR_KEYER_BLUE_LOW = 0x0000FFFFL, .COLOR_KEYER_BLUE_HIGH = 0xFFFF0000L, .CUR0_PIX_INV_MODE = 0x00000004L, .CUR0_PIXEL_ALPHA_MOD_EN = 0x00000080L, .CUR0_ROM_EN = 0x00000008L, .OBUF_MEM_PWR_FORCE = 0x00000003L, .LUT_MEM_PWR_FORCE = 0x00000003L, | |||
789 | TF_DEBUG_REG_LIST_MASK_DCN20.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000, .CM_TEST_DEBUG_DATA_ICSC_MODE = 0x18, .CM_TEST_DEBUG_DATA_GAMUT_REMAP_MODE = 0x600 | |||
790 | }; | |||
791 | ||||
792 | #define dwbc_regs_dcn2(id)[id] = { .WB_ENABLE = 0x000034C0 + 0x01da, .WB_EC_CONFIG = 0x000034C0 + 0x01db, .CNV_MODE = 0x000034C0 + 0x01dc, .CNV_WINDOW_START = 0x000034C0 + 0x01dd, .CNV_WINDOW_SIZE = 0x000034C0 + 0x01de , .CNV_UPDATE = 0x000034C0 + 0x01df, .CNV_SOURCE_SIZE = 0x000034C0 + 0x01e0, .CNV_TEST_CNTL = 0x000034C0 + 0x01ee, .CNV_TEST_CRC_RED = 0x000034C0 + 0x01ef, .CNV_TEST_CRC_GREEN = 0x000034C0 + 0x01f0 , .CNV_TEST_CRC_BLUE = 0x000034C0 + 0x01f1, .WBSCL_COEF_RAM_SELECT = 0x000034C0 + 0x020a, .WBSCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x020b, .WBSCL_MODE = 0x000034C0 + 0x020c, .WBSCL_TAP_CONTROL = 0x000034C0 + 0x020d, .WBSCL_DEST_SIZE = 0x000034C0 + 0x020e , .WBSCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x020f, .WBSCL_HORZ_FILTER_INIT_Y_RGB = 0x000034C0 + 0x0210, .WBSCL_HORZ_FILTER_INIT_CBCR = 0x000034C0 + 0x0211, .WBSCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0212 , .WBSCL_VERT_FILTER_INIT_Y_RGB = 0x000034C0 + 0x0213, .WBSCL_VERT_FILTER_INIT_CBCR = 0x000034C0 + 0x0214, .WBSCL_ROUND_OFFSET = 0x000034C0 + 0x0215 , .WBSCL_OVERFLOW_STATUS = 0x000034C0 + 0x0216, .WBSCL_COEF_RAM_CONFLICT_STATUS = 0x000034C0 + 0x0217, .WBSCL_TEST_CNTL = 0x000034C0 + 0x0218 , .WBSCL_TEST_CRC_RED = 0x000034C0 + 0x0219, .WBSCL_TEST_CRC_GREEN = 0x000034C0 + 0x021a, .WBSCL_TEST_CRC_BLUE = 0x000034C0 + 0x021b , .WBSCL_BACKPRESSURE_CNT_EN = 0x000034C0 + 0x021c, .WB_MCIF_BACKPRESSURE_CNT = 0x000034C0 + 0x021d, .WBSCL_CLAMP_Y_RGB = 0x000034C0 + 0x021e , .WBSCL_CLAMP_CBCR = 0x000034C0 + 0x021f, .WBSCL_OUTSIDE_PIX_STRATEGY = 0x000034C0 + 0x0220, .WBSCL_OUTSIDE_PIX_STRATEGY_CBCR = 0x000034C0 + 0x0221, .WBSCL_DEBUG = 0x000034C0 + 0x0222, .WBSCL_TEST_DEBUG_INDEX = 0x000034C0 + 0x0223, .WBSCL_TEST_DEBUG_DATA = 0x000034C0 + 0x0224, .WB_DEBUG_CTRL = 0x000034C0 + 0x01f2, .WB_DBG_MODE = 0x000034C0 + 0x01f3, .WB_HW_DEBUG = 0x000034C0 + 0x01f4, .CNV_TEST_DEBUG_INDEX = 0x000034C0 + 0x01f8, .CNV_TEST_DEBUG_DATA = 0x000034C0 + 0x01f9 , .WB_SOFT_RESET = 0x000034C0 + 0x01f5, .WB_WARM_UP_MODE_CTL1 = 0x000034C0 + 0x01f6, .WB_WARM_UP_MODE_CTL2 = 0x000034C0 + 0x01f7 , }\ | |||
793 | [id] = {\ | |||
794 | DWBC_COMMON_REG_LIST_DCN2_0(id).WB_ENABLE = 0x000034C0 + 0x01da, .WB_EC_CONFIG = 0x000034C0 + 0x01db, .CNV_MODE = 0x000034C0 + 0x01dc, .CNV_WINDOW_START = 0x000034C0 + 0x01dd, .CNV_WINDOW_SIZE = 0x000034C0 + 0x01de, .CNV_UPDATE = 0x000034C0 + 0x01df, .CNV_SOURCE_SIZE = 0x000034C0 + 0x01e0, .CNV_TEST_CNTL = 0x000034C0 + 0x01ee, .CNV_TEST_CRC_RED = 0x000034C0 + 0x01ef, .CNV_TEST_CRC_GREEN = 0x000034C0 + 0x01f0 , .CNV_TEST_CRC_BLUE = 0x000034C0 + 0x01f1, .WBSCL_COEF_RAM_SELECT = 0x000034C0 + 0x020a, .WBSCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x020b, .WBSCL_MODE = 0x000034C0 + 0x020c, .WBSCL_TAP_CONTROL = 0x000034C0 + 0x020d, .WBSCL_DEST_SIZE = 0x000034C0 + 0x020e , .WBSCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x020f, .WBSCL_HORZ_FILTER_INIT_Y_RGB = 0x000034C0 + 0x0210, .WBSCL_HORZ_FILTER_INIT_CBCR = 0x000034C0 + 0x0211, .WBSCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0212 , .WBSCL_VERT_FILTER_INIT_Y_RGB = 0x000034C0 + 0x0213, .WBSCL_VERT_FILTER_INIT_CBCR = 0x000034C0 + 0x0214, .WBSCL_ROUND_OFFSET = 0x000034C0 + 0x0215 , .WBSCL_OVERFLOW_STATUS = 0x000034C0 + 0x0216, .WBSCL_COEF_RAM_CONFLICT_STATUS = 0x000034C0 + 0x0217, .WBSCL_TEST_CNTL = 0x000034C0 + 0x0218 , .WBSCL_TEST_CRC_RED = 0x000034C0 + 0x0219, .WBSCL_TEST_CRC_GREEN = 0x000034C0 + 0x021a, .WBSCL_TEST_CRC_BLUE = 0x000034C0 + 0x021b , .WBSCL_BACKPRESSURE_CNT_EN = 0x000034C0 + 0x021c, .WB_MCIF_BACKPRESSURE_CNT = 0x000034C0 + 0x021d, .WBSCL_CLAMP_Y_RGB = 0x000034C0 + 0x021e , .WBSCL_CLAMP_CBCR = 0x000034C0 + 0x021f, .WBSCL_OUTSIDE_PIX_STRATEGY = 0x000034C0 + 0x0220, .WBSCL_OUTSIDE_PIX_STRATEGY_CBCR = 0x000034C0 + 0x0221, .WBSCL_DEBUG = 0x000034C0 + 0x0222, .WBSCL_TEST_DEBUG_INDEX = 0x000034C0 + 0x0223, .WBSCL_TEST_DEBUG_DATA = 0x000034C0 + 0x0224, .WB_DEBUG_CTRL = 0x000034C0 + 0x01f2, .WB_DBG_MODE = 0x000034C0 + 0x01f3, .WB_HW_DEBUG = 0x000034C0 + 0x01f4, .CNV_TEST_DEBUG_INDEX = 0x000034C0 + 0x01f8, .CNV_TEST_DEBUG_DATA = 0x000034C0 + 0x01f9 , .WB_SOFT_RESET = 0x000034C0 + 0x01f5, .WB_WARM_UP_MODE_CTL1 = 0x000034C0 + 0x01f6, .WB_WARM_UP_MODE_CTL2 = 0x000034C0 + 0x01f7,\ | |||
795 | } | |||
796 | ||||
797 | static const struct dcn20_dwbc_registers dwbc20_regs[] = { | |||
798 | dwbc_regs_dcn2(0)[0] = { .WB_ENABLE = 0x000034C0 + 0x01da, .WB_EC_CONFIG = 0x000034C0 + 0x01db, .CNV_MODE = 0x000034C0 + 0x01dc, .CNV_WINDOW_START = 0x000034C0 + 0x01dd, .CNV_WINDOW_SIZE = 0x000034C0 + 0x01de , .CNV_UPDATE = 0x000034C0 + 0x01df, .CNV_SOURCE_SIZE = 0x000034C0 + 0x01e0, .CNV_TEST_CNTL = 0x000034C0 + 0x01ee, .CNV_TEST_CRC_RED = 0x000034C0 + 0x01ef, .CNV_TEST_CRC_GREEN = 0x000034C0 + 0x01f0 , .CNV_TEST_CRC_BLUE = 0x000034C0 + 0x01f1, .WBSCL_COEF_RAM_SELECT = 0x000034C0 + 0x020a, .WBSCL_COEF_RAM_TAP_DATA = 0x000034C0 + 0x020b, .WBSCL_MODE = 0x000034C0 + 0x020c, .WBSCL_TAP_CONTROL = 0x000034C0 + 0x020d, .WBSCL_DEST_SIZE = 0x000034C0 + 0x020e , .WBSCL_HORZ_FILTER_SCALE_RATIO = 0x000034C0 + 0x020f, .WBSCL_HORZ_FILTER_INIT_Y_RGB = 0x000034C0 + 0x0210, .WBSCL_HORZ_FILTER_INIT_CBCR = 0x000034C0 + 0x0211, .WBSCL_VERT_FILTER_SCALE_RATIO = 0x000034C0 + 0x0212 , .WBSCL_VERT_FILTER_INIT_Y_RGB = 0x000034C0 + 0x0213, .WBSCL_VERT_FILTER_INIT_CBCR = 0x000034C0 + 0x0214, .WBSCL_ROUND_OFFSET = 0x000034C0 + 0x0215 , .WBSCL_OVERFLOW_STATUS = 0x000034C0 + 0x0216, .WBSCL_COEF_RAM_CONFLICT_STATUS = 0x000034C0 + 0x0217, .WBSCL_TEST_CNTL = 0x000034C0 + 0x0218 , .WBSCL_TEST_CRC_RED = 0x000034C0 + 0x0219, .WBSCL_TEST_CRC_GREEN = 0x000034C0 + 0x021a, .WBSCL_TEST_CRC_BLUE = 0x000034C0 + 0x021b , .WBSCL_BACKPRESSURE_CNT_EN = 0x000034C0 + 0x021c, .WB_MCIF_BACKPRESSURE_CNT = 0x000034C0 + 0x021d, .WBSCL_CLAMP_Y_RGB = 0x000034C0 + 0x021e , .WBSCL_CLAMP_CBCR = 0x000034C0 + 0x021f, .WBSCL_OUTSIDE_PIX_STRATEGY = 0x000034C0 + 0x0220, .WBSCL_OUTSIDE_PIX_STRATEGY_CBCR = 0x000034C0 + 0x0221, .WBSCL_DEBUG = 0x000034C0 + 0x0222, .WBSCL_TEST_DEBUG_INDEX = 0x000034C0 + 0x0223, .WBSCL_TEST_DEBUG_DATA = 0x000034C0 + 0x0224, .WB_DEBUG_CTRL = 0x000034C0 + 0x01f2, .WB_DBG_MODE = 0x000034C0 + 0x01f3, .WB_HW_DEBUG = 0x000034C0 + 0x01f4, .CNV_TEST_DEBUG_INDEX = 0x000034C0 + 0x01f8, .CNV_TEST_DEBUG_DATA = 0x000034C0 + 0x01f9 , .WB_SOFT_RESET = 0x000034C0 + 0x01f5, .WB_WARM_UP_MODE_CTL1 = 0x000034C0 + 0x01f6, .WB_WARM_UP_MODE_CTL2 = 0x000034C0 + 0x01f7 , }, | |||
799 | }; | |||
800 | ||||
801 | static const struct dcn20_dwbc_shift dwbc20_shift = { | |||
802 | DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT).WB_ENABLE = 0x0, .DISPCLK_R_WB_GATE_DIS = 0x0, .DISPCLK_G_WB_GATE_DIS = 0x1, .DISPCLK_G_WBSCL_GATE_DIS = 0x2, .WB_TEST_CLK_SEL = 0x3 , .WB_LB_LS_DIS = 0x7, .WB_LB_SD_DIS = 0x8, .WB_LUT_LS_DIS = 0x9 , .WBSCL_LB_MEM_PWR_MODE_SEL = 0xc, .WBSCL_LB_MEM_PWR_DIS = 0xe , .WBSCL_LB_MEM_PWR_FORCE = 0xf, .WBSCL_LB_MEM_PWR_STATE = 0x15 , .WB_RAM_PW_SAVE_MODE = 0x17, .WBSCL_LUT_MEM_PWR_STATE = 0x18 , .CNV_OUT_BPC = 0x4, .CNV_FRAME_CAPTURE_RATE = 0x8, .CNV_WINDOW_CROP_EN = 0xc, .CNV_STEREO_TYPE = 0xd, .CNV_INTERLACED_MODE = 0xf, . CNV_EYE_SELECTION = 0x10, .CNV_STEREO_POLARITY = 0x12, .CNV_INTERLACED_FIELD_ORDER = 0x13, .CNV_STEREO_SPLIT = 0x14, .CNV_NEW_CONTENT = 0x18, . CNV_FRAME_CAPTURE_EN_CURRENT = 0x1e, .CNV_FRAME_CAPTURE_EN = 0x1f , .CNV_WINDOW_START_X = 0x0, .CNV_WINDOW_START_Y = 0x10, .CNV_WINDOW_WIDTH = 0x0, .CNV_WINDOW_HEIGHT = 0x10, .CNV_UPDATE_PENDING = 0x0, .CNV_UPDATE_TAKEN = 0x8, .CNV_UPDATE_LOCK = 0x10, .CNV_SOURCE_WIDTH = 0x0, .CNV_SOURCE_HEIGHT = 0x10, .CNV_TEST_CRC_EN = 0x4, .CNV_TEST_CRC_CONT_EN = 0x8, .CNV_TEST_CRC_RED_MASK = 0x4, .CNV_TEST_CRC_SIG_RED = 0x10, .CNV_TEST_CRC_GREEN_MASK = 0x4, .CNV_TEST_CRC_SIG_GREEN = 0x10, .CNV_TEST_CRC_BLUE_MASK = 0x4, .CNV_TEST_CRC_SIG_BLUE = 0x10, .WB_DEBUG_EN = 0x0, .WB_DEBUG_SEL = 0x6, .WB_DBG_MODE_EN = 0x0, .WB_DBG_DIN_FMT = 0x1, .WB_DBG_36MODE = 0x2, .WB_DBG_CMAP = 0x3, .WB_DBG_PXLRATE_ERROR = 0x8, .WB_DBG_SOURCE_WIDTH = 0x10 , .WB_HW_DEBUG = 0x0, .WB_SOFT_RESET = 0x0, .CNV_TEST_DEBUG_INDEX = 0x0, .CNV_TEST_DEBUG_WRITE_EN = 0x8, .CNV_TEST_DEBUG_DATA = 0x0, .WBSCL_COEF_RAM_TAP_PAIR_IDX = 0x0, .WBSCL_COEF_RAM_PHASE = 0x8, .WBSCL_COEF_RAM_FILTER_TYPE = 0x10, .WBSCL_COEF_RAM_EVEN_TAP_COEF = 0x0, .WBSCL_COEF_RAM_EVEN_TAP_COEF_EN = 0xf, .WBSCL_COEF_RAM_ODD_TAP_COEF = 0x10, .WBSCL_COEF_RAM_ODD_TAP_COEF_EN = 0x1f, .WBSCL_MODE = 0x0, .WBSCL_OUT_BIT_DEPTH = 0x4, .WBSCL_V_NUM_OF_TAPS_Y_RGB = 0x0, .WBSCL_V_NUM_OF_TAPS_CBCR = 0x4, .WBSCL_H_NUM_OF_TAPS_Y_RGB = 0x8, .WBSCL_H_NUM_OF_TAPS_CBCR = 0xc, .WBSCL_DEST_HEIGHT = 0x0, .WBSCL_DEST_WIDTH = 0x10, .WBSCL_H_SCALE_RATIO = 0x0, . WBSCL_H_INIT_FRAC_Y_RGB = 0x0, .WBSCL_H_INIT_INT_Y_RGB = 0x18 , .WBSCL_H_INIT_FRAC_CBCR = 0x0, .WBSCL_H_INIT_INT_CBCR = 0x18 , .WBSCL_V_SCALE_RATIO = 0x0, .WBSCL_V_INIT_FRAC_Y_RGB = 0x0, .WBSCL_V_INIT_INT_Y_RGB = 0x18, .WBSCL_V_INIT_FRAC_CBCR = 0x0 , .WBSCL_V_INIT_INT_CBCR = 0x18, .WBSCL_ROUND_OFFSET_Y_RGB = 0x0 , .WBSCL_ROUND_OFFSET_CBCR = 0x10, .WBSCL_DATA_OVERFLOW_FLAG = 0x0, .WBSCL_DATA_OVERFLOW_ACK = 0x8, .WBSCL_DATA_OVERFLOW_MASK = 0xc, .WBSCL_DATA_OVERFLOW_INT_STATUS = 0x10, .WBSCL_DATA_OVERFLOW_INT_TYPE = 0x14, .WBSCL_HOST_CONFLICT_FLAG = 0x0, .WBSCL_HOST_CONFLICT_ACK = 0x8, .WBSCL_HOST_CONFLICT_MASK = 0xc, .WBSCL_HOST_CONFLICT_INT_STATUS = 0x10, .WBSCL_HOST_CONFLICT_INT_TYPE = 0x14, .WBSCL_TEST_CRC_EN = 0x4, .WBSCL_TEST_CRC_CONT_EN = 0x8, .WBSCL_TEST_CRC_RED_MASK = 0x0, .WBSCL_TEST_CRC_SIG_RED = 0x10, .WBSCL_TEST_CRC_GREEN_MASK = 0x0, .WBSCL_TEST_CRC_SIG_GREEN = 0x10, .WBSCL_TEST_CRC_BLUE_MASK = 0x0, .WBSCL_TEST_CRC_SIG_BLUE = 0x10, .WBSCL_BACKPRESSURE_CNT_EN = 0x0, .WB_MCIF_Y_MAX_BACKPRESSURE = 0x0, .WB_MCIF_C_MAX_BACKPRESSURE = 0x10, .WBSCL_CLAMP_UPPER_Y_RGB = 0x0, .WBSCL_CLAMP_LOWER_Y_RGB = 0x10, .WBSCL_CLAMP_UPPER_CBCR = 0x0, .WBSCL_CLAMP_LOWER_CBCR = 0x10, .WBSCL_OUTSIDE_PIX_STRATEGY = 0x0, .WBSCL_BLACK_COLOR_G_Y = 0x10, .WBSCL_BLACK_COLOR_B_CB = 0x0, .WBSCL_BLACK_COLOR_R_CR = 0x10, .WBSCL_DEBUG = 0x0, .WBSCL_TEST_DEBUG_INDEX = 0x0, . WBSCL_TEST_DEBUG_WRITE_EN = 0x8, .WBSCL_TEST_DEBUG_DATA = 0x0 , .WIDTH_WARMUP = 0x0, .HEIGHT_WARMUP = 0x10, .GMC_WARM_UP_ENABLE = 0x1f, .DATA_VALUE_WARMUP = 0x0, .MODE_WARMUP = 0x10, .DATA_DEPTH_WARMUP = 0x14 | |||
803 | }; | |||
804 | ||||
805 | static const struct dcn20_dwbc_mask dwbc20_mask = { | |||
806 | DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK).WB_ENABLE = 0x00000001L, .DISPCLK_R_WB_GATE_DIS = 0x00000001L , .DISPCLK_G_WB_GATE_DIS = 0x00000002L, .DISPCLK_G_WBSCL_GATE_DIS = 0x00000004L, .WB_TEST_CLK_SEL = 0x00000078L, .WB_LB_LS_DIS = 0x00000080L, .WB_LB_SD_DIS = 0x00000100L, .WB_LUT_LS_DIS = 0x00000200L, .WBSCL_LB_MEM_PWR_MODE_SEL = 0x00003000L, .WBSCL_LB_MEM_PWR_DIS = 0x00004000L, .WBSCL_LB_MEM_PWR_FORCE = 0x00018000L, .WBSCL_LB_MEM_PWR_STATE = 0x00600000L, .WB_RAM_PW_SAVE_MODE = 0x00800000L, .WBSCL_LUT_MEM_PWR_STATE = 0x03000000L, .CNV_OUT_BPC = 0x00000010L, .CNV_FRAME_CAPTURE_RATE = 0x00000300L, .CNV_WINDOW_CROP_EN = 0x00001000L, .CNV_STEREO_TYPE = 0x00006000L, .CNV_INTERLACED_MODE = 0x00008000L, .CNV_EYE_SELECTION = 0x00030000L, .CNV_STEREO_POLARITY = 0x00040000L, .CNV_INTERLACED_FIELD_ORDER = 0x00080000L, .CNV_STEREO_SPLIT = 0x00100000L, .CNV_NEW_CONTENT = 0x01000000L, .CNV_FRAME_CAPTURE_EN_CURRENT = 0x40000000L, . CNV_FRAME_CAPTURE_EN = 0x80000000L, .CNV_WINDOW_START_X = 0x00000FFFL , .CNV_WINDOW_START_Y = 0x0FFF0000L, .CNV_WINDOW_WIDTH = 0x00000FFFL , .CNV_WINDOW_HEIGHT = 0x0FFF0000L, .CNV_UPDATE_PENDING = 0x00000001L , .CNV_UPDATE_TAKEN = 0x00000100L, .CNV_UPDATE_LOCK = 0x00010000L , .CNV_SOURCE_WIDTH = 0x00007FFFL, .CNV_SOURCE_HEIGHT = 0x7FFF0000L , .CNV_TEST_CRC_EN = 0x00000010L, .CNV_TEST_CRC_CONT_EN = 0x00000100L , .CNV_TEST_CRC_RED_MASK = 0x0000FFF0L, .CNV_TEST_CRC_SIG_RED = 0xFFFF0000L, .CNV_TEST_CRC_GREEN_MASK = 0x0000FFF0L, .CNV_TEST_CRC_SIG_GREEN = 0xFFFF0000L, .CNV_TEST_CRC_BLUE_MASK = 0x0000FFF0L, .CNV_TEST_CRC_SIG_BLUE = 0xFFFF0000L, .WB_DEBUG_EN = 0x00000001L, .WB_DEBUG_SEL = 0x000000C0L , .WB_DBG_MODE_EN = 0x00000001L, .WB_DBG_DIN_FMT = 0x00000002L , .WB_DBG_36MODE = 0x00000004L, .WB_DBG_CMAP = 0x00000008L, . WB_DBG_PXLRATE_ERROR = 0x00000100L, .WB_DBG_SOURCE_WIDTH = 0x7FFF0000L , .WB_HW_DEBUG = 0xFFFFFFFFL, .WB_SOFT_RESET = 0x00000001L, . CNV_TEST_DEBUG_INDEX = 0x000000FFL, .CNV_TEST_DEBUG_WRITE_EN = 0x00000100L, .CNV_TEST_DEBUG_DATA = 0xFFFFFFFFL, .WBSCL_COEF_RAM_TAP_PAIR_IDX = 0x00000007L, .WBSCL_COEF_RAM_PHASE = 0x00000F00L, .WBSCL_COEF_RAM_FILTER_TYPE = 0x00030000L, .WBSCL_COEF_RAM_EVEN_TAP_COEF = 0x00003FFFL, . WBSCL_COEF_RAM_EVEN_TAP_COEF_EN = 0x00008000L, .WBSCL_COEF_RAM_ODD_TAP_COEF = 0x3FFF0000L, .WBSCL_COEF_RAM_ODD_TAP_COEF_EN = 0x80000000L , .WBSCL_MODE = 0x00000003L, .WBSCL_OUT_BIT_DEPTH = 0x00000010L , .WBSCL_V_NUM_OF_TAPS_Y_RGB = 0x0000000FL, .WBSCL_V_NUM_OF_TAPS_CBCR = 0x000000F0L, .WBSCL_H_NUM_OF_TAPS_Y_RGB = 0x00000F00L, .WBSCL_H_NUM_OF_TAPS_CBCR = 0x0000F000L, .WBSCL_DEST_HEIGHT = 0x00007FFFL, .WBSCL_DEST_WIDTH = 0x7FFF0000L, .WBSCL_H_SCALE_RATIO = 0x07FFFFFFL, .WBSCL_H_INIT_FRAC_Y_RGB = 0x00FFFFFFL, .WBSCL_H_INIT_INT_Y_RGB = 0x1F000000L, .WBSCL_H_INIT_FRAC_CBCR = 0x00FFFFFFL, .WBSCL_H_INIT_INT_CBCR = 0x1F000000L, .WBSCL_V_SCALE_RATIO = 0x07FFFFFFL, .WBSCL_V_INIT_FRAC_Y_RGB = 0x00FFFFFFL, .WBSCL_V_INIT_INT_Y_RGB = 0x1F000000L, .WBSCL_V_INIT_FRAC_CBCR = 0x00FFFFFFL, .WBSCL_V_INIT_INT_CBCR = 0x1F000000L, .WBSCL_ROUND_OFFSET_Y_RGB = 0x000003FFL, .WBSCL_ROUND_OFFSET_CBCR = 0x03FF0000L, .WBSCL_DATA_OVERFLOW_FLAG = 0x00000001L, .WBSCL_DATA_OVERFLOW_ACK = 0x00000100L, .WBSCL_DATA_OVERFLOW_MASK = 0x00001000L, .WBSCL_DATA_OVERFLOW_INT_STATUS = 0x00010000L, .WBSCL_DATA_OVERFLOW_INT_TYPE = 0x00100000L, . WBSCL_HOST_CONFLICT_FLAG = 0x00000001L, .WBSCL_HOST_CONFLICT_ACK = 0x00000100L, .WBSCL_HOST_CONFLICT_MASK = 0x00001000L, .WBSCL_HOST_CONFLICT_INT_STATUS = 0x00010000L, .WBSCL_HOST_CONFLICT_INT_TYPE = 0x00100000L, . WBSCL_TEST_CRC_EN = 0x00000010L, .WBSCL_TEST_CRC_CONT_EN = 0x00000100L , .WBSCL_TEST_CRC_RED_MASK = 0x000003FFL, .WBSCL_TEST_CRC_SIG_RED = 0xFFFF0000L, .WBSCL_TEST_CRC_GREEN_MASK = 0x0000FFFFL, .WBSCL_TEST_CRC_SIG_GREEN = 0xFFFF0000L, .WBSCL_TEST_CRC_BLUE_MASK = 0x000003FFL, .WBSCL_TEST_CRC_SIG_BLUE = 0xFFFF0000L, .WBSCL_BACKPRESSURE_CNT_EN = 0x00000001L, .WB_MCIF_Y_MAX_BACKPRESSURE = 0x0000FFFFL, .WB_MCIF_C_MAX_BACKPRESSURE = 0xFFFF0000L, .WBSCL_CLAMP_UPPER_Y_RGB = 0x000003FFL, .WBSCL_CLAMP_LOWER_Y_RGB = 0x03FF0000L, .WBSCL_CLAMP_UPPER_CBCR = 0x000003FFL, .WBSCL_CLAMP_LOWER_CBCR = 0x03FF0000L, .WBSCL_OUTSIDE_PIX_STRATEGY = 0x00000001L, .WBSCL_BLACK_COLOR_G_Y = 0x03FF0000L, .WBSCL_BLACK_COLOR_B_CB = 0x000003FFL, .WBSCL_BLACK_COLOR_R_CR = 0x03FF0000L, .WBSCL_DEBUG = 0xFFFFFFFFL, .WBSCL_TEST_DEBUG_INDEX = 0x000000FFL, .WBSCL_TEST_DEBUG_WRITE_EN = 0x00000100L, .WBSCL_TEST_DEBUG_DATA = 0xFFFFFFFFL, .WIDTH_WARMUP = 0x00007FFFL, .HEIGHT_WARMUP = 0x7FFF0000L, .GMC_WARM_UP_ENABLE = 0x80000000L, .DATA_VALUE_WARMUP = 0x000003FFL, .MODE_WARMUP = 0x00010000L, .DATA_DEPTH_WARMUP = 0x00100000L | |||
807 | }; | |||
808 | ||||
809 | #define mcif_wb_regs_dcn2(id)[id] = { .MCIF_WB_BUFMGR_SW_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUFMGR_SW_CONTROL, .MCIF_WB_BUFMGR_CUR_LINE_R = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUFMGR_CUR_LINE_R, .MCIF_WB_BUFMGR_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUFMGR_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUFMGR_STATUS, .MCIF_WB_BUF_PITCH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_PITCH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_PITCH, .MCIF_WB_BUF_1_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_STATUS, .MCIF_WB_BUF_1_STATUS2 = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_STATUS2_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_STATUS2, .MCIF_WB_BUF_2_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_STATUS, .MCIF_WB_BUF_2_STATUS2 = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_STATUS2_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_STATUS2, .MCIF_WB_BUF_3_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_STATUS, .MCIF_WB_BUF_3_STATUS2 = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_STATUS2_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_STATUS2, .MCIF_WB_BUF_4_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_STATUS, .MCIF_WB_BUF_4_STATUS2 = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_STATUS2_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_STATUS2, .MCIF_WB_ARBITRATION_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_ARBITRATION_CONTROL, .MCIF_WB_SCLK_CHANGE = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_SCLK_CHANGE_BASE_IDX + mmMCIF_WBid_MCIF_WB_SCLK_CHANGE, .MCIF_WB_TEST_DEBUG_INDEX = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX + mmMCIF_WBid_MCIF_WB_TEST_DEBUG_INDEX, .MCIF_WB_TEST_DEBUG_DATA = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX + mmMCIF_WBid_MCIF_WB_TEST_DEBUG_DATA, .MCIF_WB_BUF_1_ADDR_Y = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y, .MCIF_WB_BUF_1_ADDR_Y_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_OFFSET, .MCIF_WB_BUF_1_ADDR_C = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C, .MCIF_WB_BUF_1_ADDR_C_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_OFFSET, .MCIF_WB_BUF_2_ADDR_Y = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y, .MCIF_WB_BUF_2_ADDR_Y_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_OFFSET, .MCIF_WB_BUF_2_ADDR_C = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C, .MCIF_WB_BUF_2_ADDR_C_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_OFFSET, .MCIF_WB_BUF_3_ADDR_Y = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y, .MCIF_WB_BUF_3_ADDR_Y_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_OFFSET, .MCIF_WB_BUF_3_ADDR_C = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C, .MCIF_WB_BUF_3_ADDR_C_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_OFFSET, .MCIF_WB_BUF_4_ADDR_Y = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y, .MCIF_WB_BUF_4_ADDR_Y_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_OFFSET, .MCIF_WB_BUF_4_ADDR_C = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C, .MCIF_WB_BUF_4_ADDR_C_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_OFFSET, .MCIF_WB_BUFMGR_VCE_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUFMGR_VCE_CONTROL, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX + mmMCIF_WBid_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, .MCIF_WB_NB_PSTATE_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_NB_PSTATE_CONTROL, .MCIF_WB_WATERMARK = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_WATERMARK_BASE_IDX + mmMCIF_WBid_MCIF_WB_WATERMARK , .MCIF_WB_CLOCK_GATER_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_CLOCK_GATER_CONTROL, .MCIF_WB_WARM_UP_CNTL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_WARM_UP_CNTL_BASE_IDX + mmMCIF_WBid_MCIF_WB_WARM_UP_CNTL, .MCIF_WB_SELF_REFRESH_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_SELF_REFRESH_CONTROL, .MULTI_LEVEL_QOS_CTRL = DCN_BASE__INST0_SEGmmMCIF_WBid_MULTI_LEVEL_QOS_CTRL_BASE_IDX + mmMCIF_WBid_MULTI_LEVEL_QOS_CTRL, .MCIF_WB_SECURITY_LEVEL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_SECURITY_LEVEL_BASE_IDX + mmMCIF_WBid_MCIF_WB_SECURITY_LEVEL, .MCIF_WB_BUF_LUMA_SIZE = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_LUMA_SIZE, .MCIF_WB_BUF_CHROMA_SIZE = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_CHROMA_SIZE, .MCIF_WB_BUF_1_ADDR_Y_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_HIGH, .MCIF_WB_BUF_1_ADDR_C_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_HIGH, .MCIF_WB_BUF_2_ADDR_Y_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_HIGH, .MCIF_WB_BUF_2_ADDR_C_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_HIGH, .MCIF_WB_BUF_3_ADDR_Y_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_HIGH, .MCIF_WB_BUF_3_ADDR_C_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_HIGH, .MCIF_WB_BUF_4_ADDR_Y_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_HIGH, .MCIF_WB_BUF_4_ADDR_C_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_HIGH, .MCIF_WB_BUF_1_RESOLUTION = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_RESOLUTION, .MCIF_WB_BUF_2_RESOLUTION = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_RESOLUTION, .MCIF_WB_BUF_3_RESOLUTION = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_RESOLUTION, .MCIF_WB_BUF_4_RESOLUTION = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_RESOLUTION, .SMU_WM_CONTROL = DCN_BASE__INST0_SEGmmWBIFid_SMU_WM_CONTROL_BASE_IDX + mmWBIFid_SMU_WM_CONTROL, }\ | |||
810 | [id] = {\ | |||
811 | MCIF_WB_COMMON_REG_LIST_DCN2_0(id).MCIF_WB_BUFMGR_SW_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUFMGR_SW_CONTROL, .MCIF_WB_BUFMGR_CUR_LINE_R = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUFMGR_CUR_LINE_R, .MCIF_WB_BUFMGR_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUFMGR_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUFMGR_STATUS, .MCIF_WB_BUF_PITCH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_PITCH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_PITCH, .MCIF_WB_BUF_1_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_STATUS, .MCIF_WB_BUF_1_STATUS2 = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_STATUS2_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_STATUS2, .MCIF_WB_BUF_2_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_STATUS, .MCIF_WB_BUF_2_STATUS2 = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_STATUS2_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_STATUS2, .MCIF_WB_BUF_3_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_STATUS, .MCIF_WB_BUF_3_STATUS2 = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_STATUS2_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_STATUS2, .MCIF_WB_BUF_4_STATUS = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_STATUS_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_STATUS, .MCIF_WB_BUF_4_STATUS2 = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_STATUS2_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_STATUS2, .MCIF_WB_ARBITRATION_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_ARBITRATION_CONTROL, .MCIF_WB_SCLK_CHANGE = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_SCLK_CHANGE_BASE_IDX + mmMCIF_WBid_MCIF_WB_SCLK_CHANGE, .MCIF_WB_TEST_DEBUG_INDEX = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX + mmMCIF_WBid_MCIF_WB_TEST_DEBUG_INDEX, .MCIF_WB_TEST_DEBUG_DATA = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX + mmMCIF_WBid_MCIF_WB_TEST_DEBUG_DATA, .MCIF_WB_BUF_1_ADDR_Y = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y, .MCIF_WB_BUF_1_ADDR_Y_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_OFFSET, .MCIF_WB_BUF_1_ADDR_C = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C, .MCIF_WB_BUF_1_ADDR_C_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_OFFSET, .MCIF_WB_BUF_2_ADDR_Y = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y, .MCIF_WB_BUF_2_ADDR_Y_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_OFFSET, .MCIF_WB_BUF_2_ADDR_C = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C, .MCIF_WB_BUF_2_ADDR_C_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_OFFSET, .MCIF_WB_BUF_3_ADDR_Y = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y, .MCIF_WB_BUF_3_ADDR_Y_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_OFFSET, .MCIF_WB_BUF_3_ADDR_C = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C, .MCIF_WB_BUF_3_ADDR_C_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_OFFSET, .MCIF_WB_BUF_4_ADDR_Y = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y, .MCIF_WB_BUF_4_ADDR_Y_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_OFFSET, .MCIF_WB_BUF_4_ADDR_C = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C, .MCIF_WB_BUF_4_ADDR_C_OFFSET = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_OFFSET, .MCIF_WB_BUFMGR_VCE_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUFMGR_VCE_CONTROL, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX + mmMCIF_WBid_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, .MCIF_WB_NB_PSTATE_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_NB_PSTATE_CONTROL, .MCIF_WB_WATERMARK = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_WATERMARK_BASE_IDX + mmMCIF_WBid_MCIF_WB_WATERMARK , .MCIF_WB_CLOCK_GATER_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_CLOCK_GATER_CONTROL, .MCIF_WB_WARM_UP_CNTL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_WARM_UP_CNTL_BASE_IDX + mmMCIF_WBid_MCIF_WB_WARM_UP_CNTL, .MCIF_WB_SELF_REFRESH_CONTROL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX + mmMCIF_WBid_MCIF_WB_SELF_REFRESH_CONTROL, .MULTI_LEVEL_QOS_CTRL = DCN_BASE__INST0_SEGmmMCIF_WBid_MULTI_LEVEL_QOS_CTRL_BASE_IDX + mmMCIF_WBid_MULTI_LEVEL_QOS_CTRL, .MCIF_WB_SECURITY_LEVEL = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_SECURITY_LEVEL_BASE_IDX + mmMCIF_WBid_MCIF_WB_SECURITY_LEVEL, .MCIF_WB_BUF_LUMA_SIZE = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_LUMA_SIZE, .MCIF_WB_BUF_CHROMA_SIZE = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_CHROMA_SIZE, .MCIF_WB_BUF_1_ADDR_Y_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_Y_HIGH, .MCIF_WB_BUF_1_ADDR_C_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_ADDR_C_HIGH, .MCIF_WB_BUF_2_ADDR_Y_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_Y_HIGH, .MCIF_WB_BUF_2_ADDR_C_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_ADDR_C_HIGH, .MCIF_WB_BUF_3_ADDR_Y_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_Y_HIGH, .MCIF_WB_BUF_3_ADDR_C_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_ADDR_C_HIGH, .MCIF_WB_BUF_4_ADDR_Y_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_Y_HIGH, .MCIF_WB_BUF_4_ADDR_C_HIGH = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_ADDR_C_HIGH, .MCIF_WB_BUF_1_RESOLUTION = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_1_RESOLUTION, .MCIF_WB_BUF_2_RESOLUTION = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_2_RESOLUTION, .MCIF_WB_BUF_3_RESOLUTION = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_3_RESOLUTION, .MCIF_WB_BUF_4_RESOLUTION = DCN_BASE__INST0_SEGmmMCIF_WBid_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX + mmMCIF_WBid_MCIF_WB_BUF_4_RESOLUTION, .SMU_WM_CONTROL = DCN_BASE__INST0_SEGmmWBIFid_SMU_WM_CONTROL_BASE_IDX + mmWBIFid_SMU_WM_CONTROL,\ | |||
812 | } | |||
813 | ||||
814 | static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { | |||
815 | mcif_wb_regs_dcn2(0)[0] = { .MCIF_WB_BUFMGR_SW_CONTROL = 0x000034C0 + 0x02b2, .MCIF_WB_BUFMGR_CUR_LINE_R = 0x000034C0 + 0x02b3, .MCIF_WB_BUFMGR_STATUS = 0x000034C0 + 0x02b4, .MCIF_WB_BUF_PITCH = 0x000034C0 + 0x02b5, .MCIF_WB_BUF_1_STATUS = 0x000034C0 + 0x02b6, .MCIF_WB_BUF_1_STATUS2 = 0x000034C0 + 0x02b7, .MCIF_WB_BUF_2_STATUS = 0x000034C0 + 0x02b8, .MCIF_WB_BUF_2_STATUS2 = 0x000034C0 + 0x02b9, .MCIF_WB_BUF_3_STATUS = 0x000034C0 + 0x02ba , .MCIF_WB_BUF_3_STATUS2 = 0x000034C0 + 0x02bb, .MCIF_WB_BUF_4_STATUS = 0x000034C0 + 0x02bc, .MCIF_WB_BUF_4_STATUS2 = 0x000034C0 + 0x02bd, .MCIF_WB_ARBITRATION_CONTROL = 0x000034C0 + 0x02be, . MCIF_WB_SCLK_CHANGE = 0x000034C0 + 0x02bf, .MCIF_WB_TEST_DEBUG_INDEX = 0x000034C0 + 0x02c0, .MCIF_WB_TEST_DEBUG_DATA = 0x000034C0 + 0x02c1, .MCIF_WB_BUF_1_ADDR_Y = 0x000034C0 + 0x02c2, .MCIF_WB_BUF_1_ADDR_Y_OFFSET = 0x000034C0 + 0x02c3, .MCIF_WB_BUF_1_ADDR_C = 0x000034C0 + 0x02c4 , .MCIF_WB_BUF_1_ADDR_C_OFFSET = 0x000034C0 + 0x02c5, .MCIF_WB_BUF_2_ADDR_Y = 0x000034C0 + 0x02c6, .MCIF_WB_BUF_2_ADDR_Y_OFFSET = 0x000034C0 + 0x02c7, .MCIF_WB_BUF_2_ADDR_C = 0x000034C0 + 0x02c8, .MCIF_WB_BUF_2_ADDR_C_OFFSET = 0x000034C0 + 0x02c9, .MCIF_WB_BUF_3_ADDR_Y = 0x000034C0 + 0x02ca , .MCIF_WB_BUF_3_ADDR_Y_OFFSET = 0x000034C0 + 0x02cb, .MCIF_WB_BUF_3_ADDR_C = 0x000034C0 + 0x02cc, .MCIF_WB_BUF_3_ADDR_C_OFFSET = 0x000034C0 + 0x02cd, .MCIF_WB_BUF_4_ADDR_Y = 0x000034C0 + 0x02ce, .MCIF_WB_BUF_4_ADDR_Y_OFFSET = 0x000034C0 + 0x02cf, .MCIF_WB_BUF_4_ADDR_C = 0x000034C0 + 0x02d0 , .MCIF_WB_BUF_4_ADDR_C_OFFSET = 0x000034C0 + 0x02d1, .MCIF_WB_BUFMGR_VCE_CONTROL = 0x000034C0 + 0x02d2, .MCIF_WB_NB_PSTATE_LATENCY_WATERMARK = 0x000034C0 + 0x02d3, .MCIF_WB_NB_PSTATE_CONTROL = 0x000034C0 + 0x02d4, .MCIF_WB_WATERMARK = 0x000034C0 + 0x02d5, .MCIF_WB_CLOCK_GATER_CONTROL = 0x000034C0 + 0x02d6, .MCIF_WB_WARM_UP_CNTL = 0x000034C0 + 0x02d7 , .MCIF_WB_SELF_REFRESH_CONTROL = 0x000034C0 + 0x02d8, .MULTI_LEVEL_QOS_CTRL = 0x000034C0 + 0x02d9, .MCIF_WB_SECURITY_LEVEL = 0x000034C0 + 0x02da, .MCIF_WB_BUF_LUMA_SIZE = 0x000034C0 + 0x02db, .MCIF_WB_BUF_CHROMA_SIZE = 0x000034C0 + 0x02dc, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000034C0 + 0x02dd, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000034C0 + 0x02de, . MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x000034C0 + 0x02df, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000034C0 + 0x02e0, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000034C0 + 0x02e1, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000034C0 + 0x02e2, . MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x000034C0 + 0x02e3, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000034C0 + 0x02e4, .MCIF_WB_BUF_1_RESOLUTION = 0x000034C0 + 0x02e5, .MCIF_WB_BUF_2_RESOLUTION = 0x000034C0 + 0x02e6, . MCIF_WB_BUF_3_RESOLUTION = 0x000034C0 + 0x02e7, .MCIF_WB_BUF_4_RESOLUTION = 0x000034C0 + 0x02e8, .SMU_WM_CONTROL = 0x000034C0 + 0x0334 , }, | |||
816 | }; | |||
817 | ||||
818 | static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { | |||
819 | MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT).MCIF_WB_BUFMGR_ENABLE = 0x0, .MCIF_WB_BUFMGR_SW_INT_EN = 0x4 , .MCIF_WB_BUFMGR_SW_INT_ACK = 0x5, .MCIF_WB_BUFMGR_SW_SLICE_INT_EN = 0x6, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN = 0x7, .MCIF_WB_BUFMGR_SW_LOCK = 0x8, .MCIF_WB_P_VMID = 0x10, .MCIF_WB_BUF_ADDR_FENCE_EN = 0x18 , .MCIF_WB_BUFMGR_CUR_LINE_R = 0x0, .MCIF_WB_BUFMGR_VCE_INT_STATUS = 0x0, .MCIF_WB_BUFMGR_SW_INT_STATUS = 0x1, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS = 0x2, .MCIF_WB_BUFMGR_CUR_BUF = 0x4, .MCIF_WB_BUFMGR_BUFTAG = 0x8, .MCIF_WB_BUFMGR_CUR_LINE_L = 0xc, .MCIF_WB_BUFMGR_NEXT_BUF = 0x1c, .MCIF_WB_BUF_LUMA_PITCH = 0x8, .MCIF_WB_BUF_CHROMA_PITCH = 0x18, .MCIF_WB_BUF_1_ACTIVE = 0x0, .MCIF_WB_BUF_1_SW_LOCKED = 0x1, .MCIF_WB_BUF_1_VCE_LOCKED = 0x2, .MCIF_WB_BUF_1_OVERFLOW = 0x3, .MCIF_WB_BUF_1_DISABLE = 0x4, .MCIF_WB_BUF_1_MODE = 0x5 , .MCIF_WB_BUF_1_BUFTAG = 0x8, .MCIF_WB_BUF_1_NXT_BUF = 0xc, . MCIF_WB_BUF_1_FIELD = 0xf, .MCIF_WB_BUF_1_CUR_LINE_L = 0x10, . MCIF_WB_BUF_1_LONG_LINE_ERROR = 0x1d, .MCIF_WB_BUF_1_SHORT_LINE_ERROR = 0x1e, .MCIF_WB_BUF_1_FRAME_LENGTH_ERROR = 0x1f, .MCIF_WB_BUF_1_CUR_LINE_R = 0x0, .MCIF_WB_BUF_1_NEW_CONTENT = 0xd, .MCIF_WB_BUF_1_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_1_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_1_TMZ = 0x10, .MCIF_WB_BUF_1_Y_OVERRUN = 0x11, .MCIF_WB_BUF_1_C_OVERRUN = 0x12, .MCIF_WB_BUF_2_ACTIVE = 0x0, .MCIF_WB_BUF_2_SW_LOCKED = 0x1, .MCIF_WB_BUF_2_VCE_LOCKED = 0x2, .MCIF_WB_BUF_2_OVERFLOW = 0x3, .MCIF_WB_BUF_2_DISABLE = 0x4, .MCIF_WB_BUF_2_MODE = 0x5 , .MCIF_WB_BUF_2_BUFTAG = 0x8, .MCIF_WB_BUF_2_NXT_BUF = 0xc, . MCIF_WB_BUF_2_FIELD = 0xf, .MCIF_WB_BUF_2_CUR_LINE_L = 0x10, . MCIF_WB_BUF_2_LONG_LINE_ERROR = 0x1d, .MCIF_WB_BUF_2_SHORT_LINE_ERROR = 0x1e, .MCIF_WB_BUF_2_FRAME_LENGTH_ERROR = 0x1f, .MCIF_WB_BUF_2_CUR_LINE_R = 0x0, .MCIF_WB_BUF_2_NEW_CONTENT = 0xd, .MCIF_WB_BUF_2_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_2_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_2_TMZ = 0x10, .MCIF_WB_BUF_2_Y_OVERRUN = 0x11, .MCIF_WB_BUF_2_C_OVERRUN = 0x12, .MCIF_WB_BUF_3_ACTIVE = 0x0, .MCIF_WB_BUF_3_SW_LOCKED = 0x1, .MCIF_WB_BUF_3_VCE_LOCKED = 0x2, .MCIF_WB_BUF_3_OVERFLOW = 0x3, .MCIF_WB_BUF_3_DISABLE = 0x4, .MCIF_WB_BUF_3_MODE = 0x5 , .MCIF_WB_BUF_3_BUFTAG = 0x8, .MCIF_WB_BUF_3_NXT_BUF = 0xc, . MCIF_WB_BUF_3_FIELD = 0xf, .MCIF_WB_BUF_3_CUR_LINE_L = 0x10, . MCIF_WB_BUF_3_LONG_LINE_ERROR = 0x1d, .MCIF_WB_BUF_3_SHORT_LINE_ERROR = 0x1e, .MCIF_WB_BUF_3_FRAME_LENGTH_ERROR = 0x1f, .MCIF_WB_BUF_3_CUR_LINE_R = 0x0, .MCIF_WB_BUF_3_NEW_CONTENT = 0xd, .MCIF_WB_BUF_3_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_3_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_3_TMZ = 0x10, .MCIF_WB_BUF_3_Y_OVERRUN = 0x11, .MCIF_WB_BUF_3_C_OVERRUN = 0x12, .MCIF_WB_BUF_4_ACTIVE = 0x0, .MCIF_WB_BUF_4_SW_LOCKED = 0x1, .MCIF_WB_BUF_4_VCE_LOCKED = 0x2, .MCIF_WB_BUF_4_OVERFLOW = 0x3, .MCIF_WB_BUF_4_DISABLE = 0x4, .MCIF_WB_BUF_4_MODE = 0x5 , .MCIF_WB_BUF_4_BUFTAG = 0x8, .MCIF_WB_BUF_4_NXT_BUF = 0xc, . MCIF_WB_BUF_4_FIELD = 0xf, .MCIF_WB_BUF_4_CUR_LINE_L = 0x10, . MCIF_WB_BUF_4_LONG_LINE_ERROR = 0x1d, .MCIF_WB_BUF_4_SHORT_LINE_ERROR = 0x1e, .MCIF_WB_BUF_4_FRAME_LENGTH_ERROR = 0x1f, .MCIF_WB_BUF_4_CUR_LINE_R = 0x0, .MCIF_WB_BUF_4_NEW_CONTENT = 0xd, .MCIF_WB_BUF_4_COLOR_DEPTH = 0xe, .MCIF_WB_BUF_4_TMZ_BLACK_PIXEL = 0xf, .MCIF_WB_BUF_4_TMZ = 0x10, .MCIF_WB_BUF_4_Y_OVERRUN = 0x11, .MCIF_WB_BUF_4_C_OVERRUN = 0x12, .MCIF_WB_CLIENT_ARBITRATION_SLICE = 0x0, .MCIF_WB_TIME_PER_PIXEL = 0x16, .WM_CHANGE_ACK_FORCE_ON = 0x0, .MCIF_WB_CLI_WATERMARK_MASK = 0x1, .MCIF_WB_TEST_DEBUG_INDEX = 0x0, .MCIF_WB_TEST_DEBUG_DATA = 0x0, .MCIF_WB_BUF_1_ADDR_Y = 0x0, .MCIF_WB_BUF_1_ADDR_Y_OFFSET = 0x0, .MCIF_WB_BUF_1_ADDR_C = 0x0, .MCIF_WB_BUF_1_ADDR_C_OFFSET = 0x0, .MCIF_WB_BUF_2_ADDR_Y = 0x0, .MCIF_WB_BUF_2_ADDR_Y_OFFSET = 0x0, .MCIF_WB_BUF_2_ADDR_C = 0x0, .MCIF_WB_BUF_2_ADDR_C_OFFSET = 0x0, .MCIF_WB_BUF_3_ADDR_Y = 0x0, .MCIF_WB_BUF_3_ADDR_Y_OFFSET = 0x0, .MCIF_WB_BUF_3_ADDR_C = 0x0, .MCIF_WB_BUF_3_ADDR_C_OFFSET = 0x0, .MCIF_WB_BUF_4_ADDR_Y = 0x0, .MCIF_WB_BUF_4_ADDR_Y_OFFSET = 0x0, .MCIF_WB_BUF_4_ADDR_C = 0x0, .MCIF_WB_BUF_4_ADDR_C_OFFSET = 0x0, .MCIF_WB_BUFMGR_VCE_LOCK_IGNORE = 0x0, .MCIF_WB_BUFMGR_VCE_INT_EN = 0x4, .MCIF_WB_BUFMGR_VCE_INT_ACK = 0x5, .MCIF_WB_BUFMGR_VCE_SLICE_INT_EN = 0x6, .MCIF_WB_BUFMGR_VCE_LOCK = 0x8, .MCIF_WB_BUFMGR_SLICE_SIZE = 0x10, .NB_PSTATE_CHANGE_REFRESH_WATERMARK = 0x0, .NB_PSTATE_CHANGE_URGENT_DURING_REQUEST = 0x0, .NB_PSTATE_CHANGE_FORCE_ON = 0x1, .NB_PSTATE_ALLOW_FOR_URGENT = 0x2, .NB_PSTATE_CHANGE_WATERMARK_MASK = 0x4, .MCIF_WB_CLI_WATERMARK = 0x0, .MCIF_WB_CLI_CLOCK_GATER_OVERRIDE = 0x0, .MCIF_WB_PITCH_SIZE_WARMUP = 0x8, .DIS_REFRESH_UNDER_NBPREQ = 0x0, .PERFRAME_SELF_REFRESH = 0x1, .MAX_SCALED_TIME_TO_URGENT = 0x0, .MCIF_WB_SECURITY_LEVEL = 0x0, .MCIF_WB_BUF_LUMA_SIZE = 0x0, .MCIF_WB_BUF_CHROMA_SIZE = 0x0, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x0, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x0, .MCIF_WB_BUF_1_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_1_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_2_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_2_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_3_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_3_RESOLUTION_HEIGHT = 0x10, .MCIF_WB_BUF_4_RESOLUTION_WIDTH = 0x0, .MCIF_WB_BUF_4_RESOLUTION_HEIGHT = 0x10, .MCIF_WB0_WM_CHG_SEL = 0x14, .MCIF_WB0_WM_CHG_REQ = 0x16 , .MCIF_WB0_WM_CHG_ACK_INT_DIS = 0x18, .MCIF_WB0_WM_CHG_ACK_INT_STATUS = 0x19 | |||
820 | }; | |||
821 | ||||
822 | static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { | |||
823 | MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK).MCIF_WB_BUFMGR_ENABLE = 0x00000001L, .MCIF_WB_BUFMGR_SW_INT_EN = 0x00000010L, .MCIF_WB_BUFMGR_SW_INT_ACK = 0x00000020L, .MCIF_WB_BUFMGR_SW_SLICE_INT_EN = 0x00000040L, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN = 0x00000080L , .MCIF_WB_BUFMGR_SW_LOCK = 0x00000F00L, .MCIF_WB_P_VMID = 0x000F0000L , .MCIF_WB_BUF_ADDR_FENCE_EN = 0x01000000L, .MCIF_WB_BUFMGR_CUR_LINE_R = 0x00001FFFL, .MCIF_WB_BUFMGR_VCE_INT_STATUS = 0x00000001L, .MCIF_WB_BUFMGR_SW_INT_STATUS = 0x00000002L, .MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS = 0x00000004L, .MCIF_WB_BUFMGR_CUR_BUF = 0x00000070L, .MCIF_WB_BUFMGR_BUFTAG = 0x00000F00L, .MCIF_WB_BUFMGR_CUR_LINE_L = 0x01FFF000L, .MCIF_WB_BUFMGR_NEXT_BUF = 0x70000000L, .MCIF_WB_BUF_LUMA_PITCH = 0x0000FF00L, .MCIF_WB_BUF_CHROMA_PITCH = 0xFF000000L, .MCIF_WB_BUF_1_ACTIVE = 0x00000001L, .MCIF_WB_BUF_1_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_1_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_1_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_1_DISABLE = 0x00000010L, .MCIF_WB_BUF_1_MODE = 0x000000E0L, .MCIF_WB_BUF_1_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_1_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_1_FIELD = 0x00008000L, .MCIF_WB_BUF_1_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_1_LONG_LINE_ERROR = 0x20000000L, .MCIF_WB_BUF_1_SHORT_LINE_ERROR = 0x40000000L, .MCIF_WB_BUF_1_FRAME_LENGTH_ERROR = 0x80000000L, .MCIF_WB_BUF_1_CUR_LINE_R = 0x00001FFFL, .MCIF_WB_BUF_1_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_1_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_1_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_1_TMZ = 0x00010000L, .MCIF_WB_BUF_1_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_1_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_2_ACTIVE = 0x00000001L, .MCIF_WB_BUF_2_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_2_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_2_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_2_DISABLE = 0x00000010L, .MCIF_WB_BUF_2_MODE = 0x000000E0L, .MCIF_WB_BUF_2_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_2_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_2_FIELD = 0x00008000L, .MCIF_WB_BUF_2_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_2_LONG_LINE_ERROR = 0x20000000L, .MCIF_WB_BUF_2_SHORT_LINE_ERROR = 0x40000000L , .MCIF_WB_BUF_2_FRAME_LENGTH_ERROR = 0x80000000L, .MCIF_WB_BUF_2_CUR_LINE_R = 0x00001FFFL, .MCIF_WB_BUF_2_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_2_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_2_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_2_TMZ = 0x00010000L, .MCIF_WB_BUF_2_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_2_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_3_ACTIVE = 0x00000001L, .MCIF_WB_BUF_3_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_3_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_3_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_3_DISABLE = 0x00000010L, .MCIF_WB_BUF_3_MODE = 0x000000E0L, .MCIF_WB_BUF_3_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_3_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_3_FIELD = 0x00008000L, .MCIF_WB_BUF_3_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_3_LONG_LINE_ERROR = 0x20000000L, .MCIF_WB_BUF_3_SHORT_LINE_ERROR = 0x40000000L , .MCIF_WB_BUF_3_FRAME_LENGTH_ERROR = 0x80000000L, .MCIF_WB_BUF_3_CUR_LINE_R = 0x00001FFFL, .MCIF_WB_BUF_3_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_3_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_3_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_3_TMZ = 0x00010000L, .MCIF_WB_BUF_3_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_3_C_OVERRUN = 0x00040000L, .MCIF_WB_BUF_4_ACTIVE = 0x00000001L, .MCIF_WB_BUF_4_SW_LOCKED = 0x00000002L, .MCIF_WB_BUF_4_VCE_LOCKED = 0x00000004L, .MCIF_WB_BUF_4_OVERFLOW = 0x00000008L, .MCIF_WB_BUF_4_DISABLE = 0x00000010L, .MCIF_WB_BUF_4_MODE = 0x000000E0L, .MCIF_WB_BUF_4_BUFTAG = 0x00000F00L, .MCIF_WB_BUF_4_NXT_BUF = 0x00007000L, .MCIF_WB_BUF_4_FIELD = 0x00008000L, .MCIF_WB_BUF_4_CUR_LINE_L = 0x1FFF0000L, .MCIF_WB_BUF_4_LONG_LINE_ERROR = 0x20000000L, .MCIF_WB_BUF_4_SHORT_LINE_ERROR = 0x40000000L , .MCIF_WB_BUF_4_FRAME_LENGTH_ERROR = 0x80000000L, .MCIF_WB_BUF_4_CUR_LINE_R = 0x00001FFFL, .MCIF_WB_BUF_4_NEW_CONTENT = 0x00002000L, .MCIF_WB_BUF_4_COLOR_DEPTH = 0x00004000L, .MCIF_WB_BUF_4_TMZ_BLACK_PIXEL = 0x00008000L, .MCIF_WB_BUF_4_TMZ = 0x00010000L, .MCIF_WB_BUF_4_Y_OVERRUN = 0x00020000L, .MCIF_WB_BUF_4_C_OVERRUN = 0x00040000L, .MCIF_WB_CLIENT_ARBITRATION_SLICE = 0x00000003L, .MCIF_WB_TIME_PER_PIXEL = 0xFFC00000L, .WM_CHANGE_ACK_FORCE_ON = 0x00000001L, .MCIF_WB_CLI_WATERMARK_MASK = 0x0000000EL, .MCIF_WB_TEST_DEBUG_INDEX = 0x000000FFL, .MCIF_WB_TEST_DEBUG_DATA = 0xFFFFFFFFL, .MCIF_WB_BUF_1_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_1_ADDR_Y_OFFSET = 0x0003FFFFL, . MCIF_WB_BUF_1_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_1_ADDR_C_OFFSET = 0x0003FFFFL, .MCIF_WB_BUF_2_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_2_ADDR_Y_OFFSET = 0x0003FFFFL, .MCIF_WB_BUF_2_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_2_ADDR_C_OFFSET = 0x0003FFFFL, .MCIF_WB_BUF_3_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_3_ADDR_Y_OFFSET = 0x0003FFFFL, .MCIF_WB_BUF_3_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_3_ADDR_C_OFFSET = 0x0003FFFFL, .MCIF_WB_BUF_4_ADDR_Y = 0xFFFFFFFFL, .MCIF_WB_BUF_4_ADDR_Y_OFFSET = 0x0003FFFFL, .MCIF_WB_BUF_4_ADDR_C = 0xFFFFFFFFL, .MCIF_WB_BUF_4_ADDR_C_OFFSET = 0x0003FFFFL, .MCIF_WB_BUFMGR_VCE_LOCK_IGNORE = 0x00000001L , .MCIF_WB_BUFMGR_VCE_INT_EN = 0x00000010L, .MCIF_WB_BUFMGR_VCE_INT_ACK = 0x00000020L, .MCIF_WB_BUFMGR_VCE_SLICE_INT_EN = 0x00000040L , .MCIF_WB_BUFMGR_VCE_LOCK = 0x00000F00L, .MCIF_WB_BUFMGR_SLICE_SIZE = 0x1FFF0000L, .NB_PSTATE_CHANGE_REFRESH_WATERMARK = 0x0007FFFFL , .NB_PSTATE_CHANGE_URGENT_DURING_REQUEST = 0x00000001L, .NB_PSTATE_CHANGE_FORCE_ON = 0x00000002L, .NB_PSTATE_ALLOW_FOR_URGENT = 0x00000004L, .NB_PSTATE_CHANGE_WATERMARK_MASK = 0x00000070L, .MCIF_WB_CLI_WATERMARK = 0x0000FFFFL, .MCIF_WB_CLI_CLOCK_GATER_OVERRIDE = 0x00000001L, .MCIF_WB_PITCH_SIZE_WARMUP = 0x0000FF00L, .DIS_REFRESH_UNDER_NBPREQ = 0x00000001L, .PERFRAME_SELF_REFRESH = 0x00000002L, .MAX_SCALED_TIME_TO_URGENT = 0x003FFFFFL, .MCIF_WB_SECURITY_LEVEL = 0x00000007L, .MCIF_WB_BUF_LUMA_SIZE = 0x000FFFFFL, .MCIF_WB_BUF_CHROMA_SIZE = 0x000FFFFFL, .MCIF_WB_BUF_1_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_1_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_2_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_2_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_3_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_3_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_4_ADDR_Y_HIGH = 0x000000FFL, .MCIF_WB_BUF_4_ADDR_C_HIGH = 0x000000FFL, .MCIF_WB_BUF_1_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_1_RESOLUTION_HEIGHT = 0x1FFF0000L , .MCIF_WB_BUF_2_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_2_RESOLUTION_HEIGHT = 0x1FFF0000L, .MCIF_WB_BUF_3_RESOLUTION_WIDTH = 0x00001FFFL , .MCIF_WB_BUF_3_RESOLUTION_HEIGHT = 0x1FFF0000L, .MCIF_WB_BUF_4_RESOLUTION_WIDTH = 0x00001FFFL, .MCIF_WB_BUF_4_RESOLUTION_HEIGHT = 0x1FFF0000L , .MCIF_WB0_WM_CHG_SEL = 0x00300000L, .MCIF_WB0_WM_CHG_REQ = 0x00400000L , .MCIF_WB0_WM_CHG_ACK_INT_DIS = 0x01000000L, .MCIF_WB0_WM_CHG_ACK_INT_STATUS = 0x02000000L | |||
824 | }; | |||
825 | ||||
826 | static const struct dcn20_mpc_registers mpc_regs = { | |||
827 | MPC_REG_LIST_DCN2_0(0).MPCC_TOP_SEL[0] = 0x000034C0 + 0x1271, .MPCC_BOT_SEL[0] = 0x000034C0 + 0x1272, .MPCC_CONTROL[0] = 0x000034C0 + 0x1274, .MPCC_STATUS [0] = 0x000034C0 + 0x127f, .MPCC_OPP_ID[0] = 0x000034C0 + 0x1273 , .MPCC_BG_G_Y[0] = 0x000034C0 + 0x127b, .MPCC_BG_R_CR[0] = 0x000034C0 + 0x127a, .MPCC_BG_B_CB[0] = 0x000034C0 + 0x127c, .MPCC_SM_CONTROL [0] = 0x000034C0 + 0x1275, .MPCC_UPDATE_LOCK_SEL[0] = 0x000034C0 + 0x1276, .MPCC_TOP_GAIN[0] = 0x000034C0 + 0x1277, .MPCC_BOT_GAIN_INSIDE [0] = 0x000034C0 + 0x1278, .MPCC_BOT_GAIN_OUTSIDE[0] = 0x000034C0 + 0x1279, .MPCC_OGAM_RAMA_START_CNTL_B[0] = 0x000034C0 + 0x13b2 , .MPCC_OGAM_RAMA_START_CNTL_G[0] = 0x000034C0 + 0x13b3, .MPCC_OGAM_RAMA_START_CNTL_R [0] = 0x000034C0 + 0x13b4, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[0] = 0x000034C0 + 0x13b5, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[0] = 0x000034C0 + 0x13b6 , .MPCC_OGAM_RAMA_SLOPE_CNTL_R[0] = 0x000034C0 + 0x13b7, .MPCC_OGAM_RAMA_END_CNTL1_B [0] = 0x000034C0 + 0x13b8, .MPCC_OGAM_RAMA_END_CNTL2_B[0] = 0x000034C0 + 0x13b9, .MPCC_OGAM_RAMA_END_CNTL1_G[0] = 0x000034C0 + 0x13ba , .MPCC_OGAM_RAMA_END_CNTL2_G[0] = 0x000034C0 + 0x13bb, .MPCC_OGAM_RAMA_END_CNTL1_R [0] = 0x000034C0 + 0x13bc, .MPCC_OGAM_RAMA_END_CNTL2_R[0] = 0x000034C0 + 0x13bd, .MPCC_OGAM_RAMA_REGION_0_1[0] = 0x000034C0 + 0x13be , .MPCC_OGAM_RAMA_REGION_32_33[0] = 0x000034C0 + 0x13ce, .MPCC_OGAM_RAMB_START_CNTL_B [0] = 0x000034C0 + 0x13cf, .MPCC_OGAM_RAMB_START_CNTL_G[0] = 0x000034C0 + 0x13d0, .MPCC_OGAM_RAMB_START_CNTL_R[0] = 0x000034C0 + 0x13d1 , .MPCC_OGAM_RAMB_SLOPE_CNTL_B[0] = 0x000034C0 + 0x13d2, .MPCC_OGAM_RAMB_SLOPE_CNTL_G [0] = 0x000034C0 + 0x13d3, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[0] = 0x000034C0 + 0x13d4, .MPCC_OGAM_RAMB_END_CNTL1_B[0] = 0x000034C0 + 0x13d5 , .MPCC_OGAM_RAMB_END_CNTL2_B[0] = 0x000034C0 + 0x13d6, .MPCC_OGAM_RAMB_END_CNTL1_G [0] = 0x000034C0 + 0x13d7, .MPCC_OGAM_RAMB_END_CNTL2_G[0] = 0x000034C0 + 0x13d8, .MPCC_OGAM_RAMB_END_CNTL1_R[0] = 0x000034C0 + 0x13d9 , .MPCC_OGAM_RAMB_END_CNTL2_R[0] = 0x000034C0 + 0x13da, .MPCC_OGAM_RAMB_REGION_0_1 [0] = 0x000034C0 + 0x13db, .MPCC_OGAM_RAMB_REGION_32_33[0] = 0x000034C0 + 0x13eb, .MPCC_MEM_PWR_CTRL[0] = 0x000034C0 + 0x127d, .MPCC_OGAM_LUT_INDEX [0] = 0x000034C0 + 0x13af, .MPCC_OGAM_LUT_RAM_CONTROL[0] = 0x000034C0 + 0x13b1, .MPCC_OGAM_LUT_DATA[0] = 0x000034C0 + 0x13b0, .MPCC_OGAM_MODE [0] = 0x000034C0 + 0x13ae, | |||
828 | MPC_REG_LIST_DCN2_0(1).MPCC_TOP_SEL[1] = 0x000034C0 + 0x128c, .MPCC_BOT_SEL[1] = 0x000034C0 + 0x128d, .MPCC_CONTROL[1] = 0x000034C0 + 0x128f, .MPCC_STATUS [1] = 0x000034C0 + 0x129a, .MPCC_OPP_ID[1] = 0x000034C0 + 0x128e , .MPCC_BG_G_Y[1] = 0x000034C0 + 0x1296, .MPCC_BG_R_CR[1] = 0x000034C0 + 0x1295, .MPCC_BG_B_CB[1] = 0x000034C0 + 0x1297, .MPCC_SM_CONTROL [1] = 0x000034C0 + 0x1290, .MPCC_UPDATE_LOCK_SEL[1] = 0x000034C0 + 0x1291, .MPCC_TOP_GAIN[1] = 0x000034C0 + 0x1292, .MPCC_BOT_GAIN_INSIDE [1] = 0x000034C0 + 0x1293, .MPCC_BOT_GAIN_OUTSIDE[1] = 0x000034C0 + 0x1294, .MPCC_OGAM_RAMA_START_CNTL_B[1] = 0x000034C0 + 0x13f3 , .MPCC_OGAM_RAMA_START_CNTL_G[1] = 0x000034C0 + 0x13f4, .MPCC_OGAM_RAMA_START_CNTL_R [1] = 0x000034C0 + 0x13f5, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[1] = 0x000034C0 + 0x13f6, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[1] = 0x000034C0 + 0x13f7 , .MPCC_OGAM_RAMA_SLOPE_CNTL_R[1] = 0x000034C0 + 0x13f8, .MPCC_OGAM_RAMA_END_CNTL1_B [1] = 0x000034C0 + 0x13f9, .MPCC_OGAM_RAMA_END_CNTL2_B[1] = 0x000034C0 + 0x13fa, .MPCC_OGAM_RAMA_END_CNTL1_G[1] = 0x000034C0 + 0x13fb , .MPCC_OGAM_RAMA_END_CNTL2_G[1] = 0x000034C0 + 0x13fc, .MPCC_OGAM_RAMA_END_CNTL1_R [1] = 0x000034C0 + 0x13fd, .MPCC_OGAM_RAMA_END_CNTL2_R[1] = 0x000034C0 + 0x13fe, .MPCC_OGAM_RAMA_REGION_0_1[1] = 0x000034C0 + 0x13ff , .MPCC_OGAM_RAMA_REGION_32_33[1] = 0x000034C0 + 0x140f, .MPCC_OGAM_RAMB_START_CNTL_B [1] = 0x000034C0 + 0x1410, .MPCC_OGAM_RAMB_START_CNTL_G[1] = 0x000034C0 + 0x1411, .MPCC_OGAM_RAMB_START_CNTL_R[1] = 0x000034C0 + 0x1412 , .MPCC_OGAM_RAMB_SLOPE_CNTL_B[1] = 0x000034C0 + 0x1413, .MPCC_OGAM_RAMB_SLOPE_CNTL_G [1] = 0x000034C0 + 0x1414, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[1] = 0x000034C0 + 0x1415, .MPCC_OGAM_RAMB_END_CNTL1_B[1] = 0x000034C0 + 0x1416 , .MPCC_OGAM_RAMB_END_CNTL2_B[1] = 0x000034C0 + 0x1417, .MPCC_OGAM_RAMB_END_CNTL1_G [1] = 0x000034C0 + 0x1418, .MPCC_OGAM_RAMB_END_CNTL2_G[1] = 0x000034C0 + 0x1419, .MPCC_OGAM_RAMB_END_CNTL1_R[1] = 0x000034C0 + 0x141a , .MPCC_OGAM_RAMB_END_CNTL2_R[1] = 0x000034C0 + 0x141b, .MPCC_OGAM_RAMB_REGION_0_1 [1] = 0x000034C0 + 0x141c, .MPCC_OGAM_RAMB_REGION_32_33[1] = 0x000034C0 + 0x142c, .MPCC_MEM_PWR_CTRL[1] = 0x000034C0 + 0x1298, .MPCC_OGAM_LUT_INDEX [1] = 0x000034C0 + 0x13f0, .MPCC_OGAM_LUT_RAM_CONTROL[1] = 0x000034C0 + 0x13f2, .MPCC_OGAM_LUT_DATA[1] = 0x000034C0 + 0x13f1, .MPCC_OGAM_MODE [1] = 0x000034C0 + 0x13ef, | |||
829 | MPC_REG_LIST_DCN2_0(2).MPCC_TOP_SEL[2] = 0x000034C0 + 0x12a7, .MPCC_BOT_SEL[2] = 0x000034C0 + 0x12a8, .MPCC_CONTROL[2] = 0x000034C0 + 0x12aa, .MPCC_STATUS [2] = 0x000034C0 + 0x12b5, .MPCC_OPP_ID[2] = 0x000034C0 + 0x12a9 , .MPCC_BG_G_Y[2] = 0x000034C0 + 0x12b1, .MPCC_BG_R_CR[2] = 0x000034C0 + 0x12b0, .MPCC_BG_B_CB[2] = 0x000034C0 + 0x12b2, .MPCC_SM_CONTROL [2] = 0x000034C0 + 0x12ab, .MPCC_UPDATE_LOCK_SEL[2] = 0x000034C0 + 0x12ac, .MPCC_TOP_GAIN[2] = 0x000034C0 + 0x12ad, .MPCC_BOT_GAIN_INSIDE [2] = 0x000034C0 + 0x12ae, .MPCC_BOT_GAIN_OUTSIDE[2] = 0x000034C0 + 0x12af, .MPCC_OGAM_RAMA_START_CNTL_B[2] = 0x000034C0 + 0x1434 , .MPCC_OGAM_RAMA_START_CNTL_G[2] = 0x000034C0 + 0x1435, .MPCC_OGAM_RAMA_START_CNTL_R [2] = 0x000034C0 + 0x1436, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[2] = 0x000034C0 + 0x1437, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[2] = 0x000034C0 + 0x1438 , .MPCC_OGAM_RAMA_SLOPE_CNTL_R[2] = 0x000034C0 + 0x1439, .MPCC_OGAM_RAMA_END_CNTL1_B [2] = 0x000034C0 + 0x143a, .MPCC_OGAM_RAMA_END_CNTL2_B[2] = 0x000034C0 + 0x143b, .MPCC_OGAM_RAMA_END_CNTL1_G[2] = 0x000034C0 + 0x143c , .MPCC_OGAM_RAMA_END_CNTL2_G[2] = 0x000034C0 + 0x143d, .MPCC_OGAM_RAMA_END_CNTL1_R [2] = 0x000034C0 + 0x143e, .MPCC_OGAM_RAMA_END_CNTL2_R[2] = 0x000034C0 + 0x143f, .MPCC_OGAM_RAMA_REGION_0_1[2] = 0x000034C0 + 0x1440 , .MPCC_OGAM_RAMA_REGION_32_33[2] = 0x000034C0 + 0x1450, .MPCC_OGAM_RAMB_START_CNTL_B [2] = 0x000034C0 + 0x1451, .MPCC_OGAM_RAMB_START_CNTL_G[2] = 0x000034C0 + 0x1452, .MPCC_OGAM_RAMB_START_CNTL_R[2] = 0x000034C0 + 0x1453 , .MPCC_OGAM_RAMB_SLOPE_CNTL_B[2] = 0x000034C0 + 0x1454, .MPCC_OGAM_RAMB_SLOPE_CNTL_G [2] = 0x000034C0 + 0x1455, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[2] = 0x000034C0 + 0x1456, .MPCC_OGAM_RAMB_END_CNTL1_B[2] = 0x000034C0 + 0x1457 , .MPCC_OGAM_RAMB_END_CNTL2_B[2] = 0x000034C0 + 0x1458, .MPCC_OGAM_RAMB_END_CNTL1_G [2] = 0x000034C0 + 0x1459, .MPCC_OGAM_RAMB_END_CNTL2_G[2] = 0x000034C0 + 0x145a, .MPCC_OGAM_RAMB_END_CNTL1_R[2] = 0x000034C0 + 0x145b , .MPCC_OGAM_RAMB_END_CNTL2_R[2] = 0x000034C0 + 0x145c, .MPCC_OGAM_RAMB_REGION_0_1 [2] = 0x000034C0 + 0x145d, .MPCC_OGAM_RAMB_REGION_32_33[2] = 0x000034C0 + 0x146d, .MPCC_MEM_PWR_CTRL[2] = 0x000034C0 + 0x12b3, .MPCC_OGAM_LUT_INDEX [2] = 0x000034C0 + 0x1431, .MPCC_OGAM_LUT_RAM_CONTROL[2] = 0x000034C0 + 0x1433, .MPCC_OGAM_LUT_DATA[2] = 0x000034C0 + 0x1432, .MPCC_OGAM_MODE [2] = 0x000034C0 + 0x1430, | |||
830 | MPC_REG_LIST_DCN2_0(3).MPCC_TOP_SEL[3] = 0x000034C0 + 0x12c2, .MPCC_BOT_SEL[3] = 0x000034C0 + 0x12c3, .MPCC_CONTROL[3] = 0x000034C0 + 0x12c5, .MPCC_STATUS [3] = 0x000034C0 + 0x12d0, .MPCC_OPP_ID[3] = 0x000034C0 + 0x12c4 , .MPCC_BG_G_Y[3] = 0x000034C0 + 0x12cc, .MPCC_BG_R_CR[3] = 0x000034C0 + 0x12cb, .MPCC_BG_B_CB[3] = 0x000034C0 + 0x12cd, .MPCC_SM_CONTROL [3] = 0x000034C0 + 0x12c6, .MPCC_UPDATE_LOCK_SEL[3] = 0x000034C0 + 0x12c7, .MPCC_TOP_GAIN[3] = 0x000034C0 + 0x12c8, .MPCC_BOT_GAIN_INSIDE [3] = 0x000034C0 + 0x12c9, .MPCC_BOT_GAIN_OUTSIDE[3] = 0x000034C0 + 0x12ca, .MPCC_OGAM_RAMA_START_CNTL_B[3] = 0x000034C0 + 0x1475 , .MPCC_OGAM_RAMA_START_CNTL_G[3] = 0x000034C0 + 0x1476, .MPCC_OGAM_RAMA_START_CNTL_R [3] = 0x000034C0 + 0x1477, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[3] = 0x000034C0 + 0x1478, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[3] = 0x000034C0 + 0x1479 , .MPCC_OGAM_RAMA_SLOPE_CNTL_R[3] = 0x000034C0 + 0x147a, .MPCC_OGAM_RAMA_END_CNTL1_B [3] = 0x000034C0 + 0x147b, .MPCC_OGAM_RAMA_END_CNTL2_B[3] = 0x000034C0 + 0x147c, .MPCC_OGAM_RAMA_END_CNTL1_G[3] = 0x000034C0 + 0x147d , .MPCC_OGAM_RAMA_END_CNTL2_G[3] = 0x000034C0 + 0x147e, .MPCC_OGAM_RAMA_END_CNTL1_R [3] = 0x000034C0 + 0x147f, .MPCC_OGAM_RAMA_END_CNTL2_R[3] = 0x000034C0 + 0x1480, .MPCC_OGAM_RAMA_REGION_0_1[3] = 0x000034C0 + 0x1481 , .MPCC_OGAM_RAMA_REGION_32_33[3] = 0x000034C0 + 0x1491, .MPCC_OGAM_RAMB_START_CNTL_B [3] = 0x000034C0 + 0x1492, .MPCC_OGAM_RAMB_START_CNTL_G[3] = 0x000034C0 + 0x1493, .MPCC_OGAM_RAMB_START_CNTL_R[3] = 0x000034C0 + 0x1494 , .MPCC_OGAM_RAMB_SLOPE_CNTL_B[3] = 0x000034C0 + 0x1495, .MPCC_OGAM_RAMB_SLOPE_CNTL_G [3] = 0x000034C0 + 0x1496, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[3] = 0x000034C0 + 0x1497, .MPCC_OGAM_RAMB_END_CNTL1_B[3] = 0x000034C0 + 0x1498 , .MPCC_OGAM_RAMB_END_CNTL2_B[3] = 0x000034C0 + 0x1499, .MPCC_OGAM_RAMB_END_CNTL1_G [3] = 0x000034C0 + 0x149a, .MPCC_OGAM_RAMB_END_CNTL2_G[3] = 0x000034C0 + 0x149b, .MPCC_OGAM_RAMB_END_CNTL1_R[3] = 0x000034C0 + 0x149c , .MPCC_OGAM_RAMB_END_CNTL2_R[3] = 0x000034C0 + 0x149d, .MPCC_OGAM_RAMB_REGION_0_1 [3] = 0x000034C0 + 0x149e, .MPCC_OGAM_RAMB_REGION_32_33[3] = 0x000034C0 + 0x14ae, .MPCC_MEM_PWR_CTRL[3] = 0x000034C0 + 0x12ce, .MPCC_OGAM_LUT_INDEX [3] = 0x000034C0 + 0x1472, .MPCC_OGAM_LUT_RAM_CONTROL[3] = 0x000034C0 + 0x1474, .MPCC_OGAM_LUT_DATA[3] = 0x000034C0 + 0x1473, .MPCC_OGAM_MODE [3] = 0x000034C0 + 0x1471, | |||
831 | MPC_REG_LIST_DCN2_0(4).MPCC_TOP_SEL[4] = 0x000034C0 + 0x12dd, .MPCC_BOT_SEL[4] = 0x000034C0 + 0x12de, .MPCC_CONTROL[4] = 0x000034C0 + 0x12e0, .MPCC_STATUS [4] = 0x000034C0 + 0x12eb, .MPCC_OPP_ID[4] = 0x000034C0 + 0x12df , .MPCC_BG_G_Y[4] = 0x000034C0 + 0x12e7, .MPCC_BG_R_CR[4] = 0x000034C0 + 0x12e6, .MPCC_BG_B_CB[4] = 0x000034C0 + 0x12e8, .MPCC_SM_CONTROL [4] = 0x000034C0 + 0x12e1, .MPCC_UPDATE_LOCK_SEL[4] = 0x000034C0 + 0x12e2, .MPCC_TOP_GAIN[4] = 0x000034C0 + 0x12e3, .MPCC_BOT_GAIN_INSIDE [4] = 0x000034C0 + 0x12e4, .MPCC_BOT_GAIN_OUTSIDE[4] = 0x000034C0 + 0x12e5, .MPCC_OGAM_RAMA_START_CNTL_B[4] = 0x000034C0 + 0x14b6 , .MPCC_OGAM_RAMA_START_CNTL_G[4] = 0x000034C0 + 0x14b7, .MPCC_OGAM_RAMA_START_CNTL_R [4] = 0x000034C0 + 0x14b8, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[4] = 0x000034C0 + 0x14b9, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[4] = 0x000034C0 + 0x14ba , .MPCC_OGAM_RAMA_SLOPE_CNTL_R[4] = 0x000034C0 + 0x14bb, .MPCC_OGAM_RAMA_END_CNTL1_B [4] = 0x000034C0 + 0x14bc, .MPCC_OGAM_RAMA_END_CNTL2_B[4] = 0x000034C0 + 0x14bd, .MPCC_OGAM_RAMA_END_CNTL1_G[4] = 0x000034C0 + 0x14be , .MPCC_OGAM_RAMA_END_CNTL2_G[4] = 0x000034C0 + 0x14bf, .MPCC_OGAM_RAMA_END_CNTL1_R [4] = 0x000034C0 + 0x14c0, .MPCC_OGAM_RAMA_END_CNTL2_R[4] = 0x000034C0 + 0x14c1, .MPCC_OGAM_RAMA_REGION_0_1[4] = 0x000034C0 + 0x14c2 , .MPCC_OGAM_RAMA_REGION_32_33[4] = 0x000034C0 + 0x14d2, .MPCC_OGAM_RAMB_START_CNTL_B [4] = 0x000034C0 + 0x14d3, .MPCC_OGAM_RAMB_START_CNTL_G[4] = 0x000034C0 + 0x14d4, .MPCC_OGAM_RAMB_START_CNTL_R[4] = 0x000034C0 + 0x14d5 , .MPCC_OGAM_RAMB_SLOPE_CNTL_B[4] = 0x000034C0 + 0x14d6, .MPCC_OGAM_RAMB_SLOPE_CNTL_G [4] = 0x000034C0 + 0x14d7, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[4] = 0x000034C0 + 0x14d8, .MPCC_OGAM_RAMB_END_CNTL1_B[4] = 0x000034C0 + 0x14d9 , .MPCC_OGAM_RAMB_END_CNTL2_B[4] = 0x000034C0 + 0x14da, .MPCC_OGAM_RAMB_END_CNTL1_G [4] = 0x000034C0 + 0x14db, .MPCC_OGAM_RAMB_END_CNTL2_G[4] = 0x000034C0 + 0x14dc, .MPCC_OGAM_RAMB_END_CNTL1_R[4] = 0x000034C0 + 0x14dd , .MPCC_OGAM_RAMB_END_CNTL2_R[4] = 0x000034C0 + 0x14de, .MPCC_OGAM_RAMB_REGION_0_1 [4] = 0x000034C0 + 0x14df, .MPCC_OGAM_RAMB_REGION_32_33[4] = 0x000034C0 + 0x14ef, .MPCC_MEM_PWR_CTRL[4] = 0x000034C0 + 0x12e9, .MPCC_OGAM_LUT_INDEX [4] = 0x000034C0 + 0x14b3, .MPCC_OGAM_LUT_RAM_CONTROL[4] = 0x000034C0 + 0x14b5, .MPCC_OGAM_LUT_DATA[4] = 0x000034C0 + 0x14b4, .MPCC_OGAM_MODE [4] = 0x000034C0 + 0x14b2, | |||
832 | MPC_REG_LIST_DCN2_0(5).MPCC_TOP_SEL[5] = 0x000034C0 + 0x12f8, .MPCC_BOT_SEL[5] = 0x000034C0 + 0x12f9, .MPCC_CONTROL[5] = 0x000034C0 + 0x12fb, .MPCC_STATUS [5] = 0x000034C0 + 0x1306, .MPCC_OPP_ID[5] = 0x000034C0 + 0x12fa , .MPCC_BG_G_Y[5] = 0x000034C0 + 0x1302, .MPCC_BG_R_CR[5] = 0x000034C0 + 0x1301, .MPCC_BG_B_CB[5] = 0x000034C0 + 0x1303, .MPCC_SM_CONTROL [5] = 0x000034C0 + 0x12fc, .MPCC_UPDATE_LOCK_SEL[5] = 0x000034C0 + 0x12fd, .MPCC_TOP_GAIN[5] = 0x000034C0 + 0x12fe, .MPCC_BOT_GAIN_INSIDE [5] = 0x000034C0 + 0x12ff, .MPCC_BOT_GAIN_OUTSIDE[5] = 0x000034C0 + 0x1300, .MPCC_OGAM_RAMA_START_CNTL_B[5] = 0x000034C0 + 0x14f7 , .MPCC_OGAM_RAMA_START_CNTL_G[5] = 0x000034C0 + 0x14f8, .MPCC_OGAM_RAMA_START_CNTL_R [5] = 0x000034C0 + 0x14f9, .MPCC_OGAM_RAMA_SLOPE_CNTL_B[5] = 0x000034C0 + 0x14fa, .MPCC_OGAM_RAMA_SLOPE_CNTL_G[5] = 0x000034C0 + 0x14fb , .MPCC_OGAM_RAMA_SLOPE_CNTL_R[5] = 0x000034C0 + 0x14fc, .MPCC_OGAM_RAMA_END_CNTL1_B [5] = 0x000034C0 + 0x14fd, .MPCC_OGAM_RAMA_END_CNTL2_B[5] = 0x000034C0 + 0x14fe, .MPCC_OGAM_RAMA_END_CNTL1_G[5] = 0x000034C0 + 0x14ff , .MPCC_OGAM_RAMA_END_CNTL2_G[5] = 0x000034C0 + 0x1500, .MPCC_OGAM_RAMA_END_CNTL1_R [5] = 0x000034C0 + 0x1501, .MPCC_OGAM_RAMA_END_CNTL2_R[5] = 0x000034C0 + 0x1502, .MPCC_OGAM_RAMA_REGION_0_1[5] = 0x000034C0 + 0x1503 , .MPCC_OGAM_RAMA_REGION_32_33[5] = 0x000034C0 + 0x1513, .MPCC_OGAM_RAMB_START_CNTL_B [5] = 0x000034C0 + 0x1514, .MPCC_OGAM_RAMB_START_CNTL_G[5] = 0x000034C0 + 0x1515, .MPCC_OGAM_RAMB_START_CNTL_R[5] = 0x000034C0 + 0x1516 , .MPCC_OGAM_RAMB_SLOPE_CNTL_B[5] = 0x000034C0 + 0x1517, .MPCC_OGAM_RAMB_SLOPE_CNTL_G [5] = 0x000034C0 + 0x1518, .MPCC_OGAM_RAMB_SLOPE_CNTL_R[5] = 0x000034C0 + 0x1519, .MPCC_OGAM_RAMB_END_CNTL1_B[5] = 0x000034C0 + 0x151a , .MPCC_OGAM_RAMB_END_CNTL2_B[5] = 0x000034C0 + 0x151b, .MPCC_OGAM_RAMB_END_CNTL1_G [5] = 0x000034C0 + 0x151c, .MPCC_OGAM_RAMB_END_CNTL2_G[5] = 0x000034C0 + 0x151d, .MPCC_OGAM_RAMB_END_CNTL1_R[5] = 0x000034C0 + 0x151e , .MPCC_OGAM_RAMB_END_CNTL2_R[5] = 0x000034C0 + 0x151f, .MPCC_OGAM_RAMB_REGION_0_1 [5] = 0x000034C0 + 0x1520, .MPCC_OGAM_RAMB_REGION_32_33[5] = 0x000034C0 + 0x1530, .MPCC_MEM_PWR_CTRL[5] = 0x000034C0 + 0x1304, .MPCC_OGAM_LUT_INDEX [5] = 0x000034C0 + 0x14f4, .MPCC_OGAM_LUT_RAM_CONTROL[5] = 0x000034C0 + 0x14f6, .MPCC_OGAM_LUT_DATA[5] = 0x000034C0 + 0x14f5, .MPCC_OGAM_MODE [5] = 0x000034C0 + 0x14f3, | |||
833 | MPC_OUT_MUX_REG_LIST_DCN2_0(0).MUX[0] = 0x000034C0 + 0x1385, .CUR[0] = 0x000034C0 + 0x1361, .CSC_MODE[0] = 0x000034C0 + 0x15b7, .CSC_C11_C12_A[0] = 0x000034C0 + 0x15b8, .CSC_C33_C34_A[0] = 0x000034C0 + 0x15bd, .CSC_C11_C12_B [0] = 0x000034C0 + 0x15be, .CSC_C33_C34_B[0] = 0x000034C0 + 0x15c3 , .DENORM_CONTROL[0] = 0x000034C0 + 0x1386, .DENORM_CLAMP_G_Y [0] = 0x000034C0 + 0x1387, .DENORM_CLAMP_B_CB[0] = 0x000034C0 + 0x1388, | |||
834 | MPC_OUT_MUX_REG_LIST_DCN2_0(1).MUX[1] = 0x000034C0 + 0x1389, .CUR[1] = 0x000034C0 + 0x1366, .CSC_MODE[1] = 0x000034C0 + 0x15c4, .CSC_C11_C12_A[1] = 0x000034C0 + 0x15c5, .CSC_C33_C34_A[1] = 0x000034C0 + 0x15ca, .CSC_C11_C12_B [1] = 0x000034C0 + 0x15cb, .CSC_C33_C34_B[1] = 0x000034C0 + 0x15d0 , .DENORM_CONTROL[1] = 0x000034C0 + 0x138a, .DENORM_CLAMP_G_Y [1] = 0x000034C0 + 0x138b, .DENORM_CLAMP_B_CB[1] = 0x000034C0 + 0x138c, | |||
835 | MPC_OUT_MUX_REG_LIST_DCN2_0(2).MUX[2] = 0x000034C0 + 0x138d, .CUR[2] = 0x000034C0 + 0x136b, .CSC_MODE[2] = 0x000034C0 + 0x15d1, .CSC_C11_C12_A[2] = 0x000034C0 + 0x15d2, .CSC_C33_C34_A[2] = 0x000034C0 + 0x15d7, .CSC_C11_C12_B [2] = 0x000034C0 + 0x15d8, .CSC_C33_C34_B[2] = 0x000034C0 + 0x15dd , .DENORM_CONTROL[2] = 0x000034C0 + 0x138e, .DENORM_CLAMP_G_Y [2] = 0x000034C0 + 0x138f, .DENORM_CLAMP_B_CB[2] = 0x000034C0 + 0x1390, | |||
836 | MPC_OUT_MUX_REG_LIST_DCN2_0(3).MUX[3] = 0x000034C0 + 0x1391, .CUR[3] = 0x000034C0 + 0x1370, .CSC_MODE[3] = 0x000034C0 + 0x15de, .CSC_C11_C12_A[3] = 0x000034C0 + 0x15df, .CSC_C33_C34_A[3] = 0x000034C0 + 0x15e4, .CSC_C11_C12_B [3] = 0x000034C0 + 0x15e5, .CSC_C33_C34_B[3] = 0x000034C0 + 0x15ea , .DENORM_CONTROL[3] = 0x000034C0 + 0x1392, .DENORM_CLAMP_G_Y [3] = 0x000034C0 + 0x1393, .DENORM_CLAMP_B_CB[3] = 0x000034C0 + 0x1394, | |||
837 | MPC_OUT_MUX_REG_LIST_DCN2_0(4).MUX[4] = 0x000034C0 + 0x1395, .CUR[4] = 0x000034C0 + 0x1375, .CSC_MODE[4] = 0x000034C0 + 0x15eb, .CSC_C11_C12_A[4] = 0x000034C0 + 0x15ec, .CSC_C33_C34_A[4] = 0x000034C0 + 0x15f1, .CSC_C11_C12_B [4] = 0x000034C0 + 0x15f2, .CSC_C33_C34_B[4] = 0x000034C0 + 0x15f7 , .DENORM_CONTROL[4] = 0x000034C0 + 0x1396, .DENORM_CLAMP_G_Y [4] = 0x000034C0 + 0x1397, .DENORM_CLAMP_B_CB[4] = 0x000034C0 + 0x1398, | |||
838 | MPC_OUT_MUX_REG_LIST_DCN2_0(5).MUX[5] = 0x000034C0 + 0x1399, .CUR[5] = 0x000034C0 + 0x137a, .CSC_MODE[5] = 0x000034C0 + 0x15f8, .CSC_C11_C12_A[5] = 0x000034C0 + 0x15f9, .CSC_C33_C34_A[5] = 0x000034C0 + 0x15fe, .CSC_C11_C12_B [5] = 0x000034C0 + 0x15ff, .CSC_C33_C34_B[5] = 0x000034C0 + 0x1604 , .DENORM_CONTROL[5] = 0x000034C0 + 0x139a, .DENORM_CLAMP_G_Y [5] = 0x000034C0 + 0x139b, .DENORM_CLAMP_B_CB[5] = 0x000034C0 + 0x139c, | |||
839 | MPC_DBG_REG_LIST_DCN2_0().MPC_OCSC_TEST_DEBUG_DATA = 0x000034C0 + 0x163c, .MPC_OCSC_TEST_DEBUG_INDEX = 0x000034C0 + 0x163b | |||
840 | }; | |||
841 | ||||
842 | static const struct dcn20_mpc_shift mpc_shift = { | |||
843 | MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT).MPCC_TOP_SEL = 0x0, .MPCC_BOT_SEL = 0x0, .MPCC_MODE = 0x0, . MPCC_ALPHA_BLND_MODE = 0x4, .MPCC_ALPHA_MULTIPLIED_MODE = 0x6 , .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x7, .MPCC_GLOBAL_ALPHA = 0x10 , .MPCC_GLOBAL_GAIN = 0x18, .MPCC_IDLE = 0x0, .MPCC_BUSY = 0x1 , .MPCC_OPP_ID = 0x0, .MPCC_BG_G_Y = 0x0, .MPCC_BG_R_CR = 0x0 , .MPCC_BG_B_CB = 0x0, .MPCC_SM_EN = 0x0, .MPCC_SM_MODE = 0x1 , .MPCC_SM_FRAME_ALT = 0x4, .MPCC_SM_FIELD_ALT = 0x5, .MPCC_SM_FORCE_NEXT_FRAME_POL = 0x8, .MPCC_SM_FORCE_NEXT_TOP_POL = 0x10, .MPC_OUT_MUX = 0x0 , .MPCC_UPDATE_LOCK_SEL = 0x0, .MPCC_BG_BPC = 0x8, .MPCC_BOT_GAIN_MODE = 0xb, .MPCC_TOP_GAIN = 0x0, .MPCC_BOT_GAIN_INSIDE = 0x0, .MPCC_BOT_GAIN_OUTSIDE = 0x0, .MPC_OCSC_TEST_DEBUG_INDEX = 0x0, .MPC_OCSC_MODE = 0x0 , .MPC_OCSC_C11_A = 0x0, .MPC_OCSC_C12_A = 0x10, .MPCC_DISABLED = 0x2, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x0, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0xc, .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x10, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x1c, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B = 0x10, .MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x14, .MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x0, .MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0xc, .MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x10, .MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x1c, .MPCC_OGAM_RAMB_EXP_REGION_END_B = 0x0, .MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0, .MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B = 0x10, .MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0, .MPCC_OGAM_RAMB_EXP_REGION_START_B = 0x0, .MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x14, .MPCC_OGAM_MEM_PWR_FORCE = 0x0, .MPCC_OGAM_MEM_PWR_DIS = 0x2, .MPCC_OGAM_LUT_INDEX = 0x0, .MPCC_OGAM_LUT_WRITE_EN_MASK = 0x0, .MPCC_OGAM_LUT_RAM_SEL = 0x3, .MPCC_OGAM_CONFIG_STATUS = 0x4, .MPCC_OGAM_LUT_DATA = 0x0, .MPCC_OGAM_MODE = 0x0, .MPC_OUT_DENORM_MODE = 0x18, .MPC_OUT_DENORM_CLAMP_MAX_R_CR = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_R_CR = 0x0, .MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_G_Y = 0x0, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0xc, .MPC_OUT_DENORM_CLAMP_MIN_B_CB = 0x0, .CUR_VUPDATE_LOCK_SET = 0x0, | |||
844 | MPC_DEBUG_REG_LIST_SH_DCN20.MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0 | |||
845 | }; | |||
846 | ||||
847 | static const struct dcn20_mpc_mask mpc_mask = { | |||
848 | MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK).MPCC_TOP_SEL = 0x0000000FL, .MPCC_BOT_SEL = 0x0000000FL, .MPCC_MODE = 0x00000003L, .MPCC_ALPHA_BLND_MODE = 0x00000030L, .MPCC_ALPHA_MULTIPLIED_MODE = 0x00000040L, .MPCC_BLND_ACTIVE_OVERLAP_ONLY = 0x00000080L, .MPCC_GLOBAL_ALPHA = 0x00FF0000L, .MPCC_GLOBAL_GAIN = 0xFF000000L , .MPCC_IDLE = 0x00000001L, .MPCC_BUSY = 0x00000002L, .MPCC_OPP_ID = 0x0000000FL, .MPCC_BG_G_Y = 0x00000FFFL, .MPCC_BG_R_CR = 0x00000FFFL , .MPCC_BG_B_CB = 0x00000FFFL, .MPCC_SM_EN = 0x00000001L, .MPCC_SM_MODE = 0x0000000EL, .MPCC_SM_FRAME_ALT = 0x00000010L, .MPCC_SM_FIELD_ALT = 0x00000020L, .MPCC_SM_FORCE_NEXT_FRAME_POL = 0x00000300L, . MPCC_SM_FORCE_NEXT_TOP_POL = 0x00030000L, .MPC_OUT_MUX = 0x0000000FL , .MPCC_UPDATE_LOCK_SEL = 0x0000000FL, .MPCC_BG_BPC = 0x00000700L , .MPCC_BOT_GAIN_MODE = 0x00000800L, .MPCC_TOP_GAIN = 0x0007FFFFL , .MPCC_BOT_GAIN_INSIDE = 0x0007FFFFL, .MPCC_BOT_GAIN_OUTSIDE = 0x0007FFFFL, .MPC_OCSC_TEST_DEBUG_INDEX = 0x000000FFL, .MPC_OCSC_MODE = 0x00000003L, .MPC_OCSC_C11_A = 0x0000FFFFL, .MPC_OCSC_C12_A = 0xFFFF0000L, .MPCC_DISABLED = 0x00000004L, .MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET = 0x000001FFL, .MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS = 0x00007000L , .MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS = 0x70000000L, .MPCC_OGAM_RAMA_EXP_REGION_END_B = 0x0000FFFFL , .MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B = 0x0000FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B = 0xFFFF0000L, .MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL , .MPCC_OGAM_RAMA_EXP_REGION_START_B = 0x0003FFFFL, .MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B = 0x07F00000L, .MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET = 0x000001FFL , .MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS = 0x00007000L, .MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET = 0x01FF0000L, .MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS = 0x70000000L , .MPCC_OGAM_RAMB_EXP_REGION_END_B = 0x0000FFFFL, .MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B = 0x0000FFFFL, .MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B = 0xFFFF0000L , .MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B = 0x0003FFFFL, .MPCC_OGAM_RAMB_EXP_REGION_START_B = 0x0003FFFFL, .MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B = 0x07F00000L , .MPCC_OGAM_MEM_PWR_FORCE = 0x00000003L, .MPCC_OGAM_MEM_PWR_DIS = 0x00000004L, .MPCC_OGAM_LUT_INDEX = 0x000001FFL, .MPCC_OGAM_LUT_WRITE_EN_MASK = 0x00000007L, .MPCC_OGAM_LUT_RAM_SEL = 0x00000008L, .MPCC_OGAM_CONFIG_STATUS = 0x00000030L, .MPCC_OGAM_LUT_DATA = 0x0007FFFFL, .MPCC_OGAM_MODE = 0x00000003L, .MPC_OUT_DENORM_MODE = 0x07000000L, .MPC_OUT_DENORM_CLAMP_MAX_R_CR = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_R_CR = 0x00000FFFL, .MPC_OUT_DENORM_CLAMP_MAX_G_Y = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_G_Y = 0x00000FFFL, .MPC_OUT_DENORM_CLAMP_MAX_B_CB = 0x00FFF000L, .MPC_OUT_DENORM_CLAMP_MIN_B_CB = 0x00000FFFL, .CUR_VUPDATE_LOCK_SET = 0x00000001L, | |||
849 | MPC_DEBUG_REG_LIST_MASK_DCN20.MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0x3 | |||
850 | }; | |||
851 | ||||
852 | #define tg_regs(id)[id] = {.OTG_VSTARTUP_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VSTARTUP_PARAM_BASE_IDX + mmOTGid_OTG_VSTARTUP_PARAM, .OTG_VUPDATE_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_PARAM_BASE_IDX + mmOTGid_OTG_VUPDATE_PARAM, .OTG_VREADY_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VREADY_PARAM_BASE_IDX + mmOTGid_OTG_VREADY_PARAM, .OTG_BLANK_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_BLANK_CONTROL_BASE_IDX + mmOTGid_OTG_BLANK_CONTROL, .OTG_MASTER_UPDATE_LOCK = DCN_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX + mmOTGid_OTG_MASTER_UPDATE_LOCK, .OTG_GLOBAL_CONTROL0 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX + mmOTGid_OTG_GLOBAL_CONTROL0, .OTG_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX + mmOTGid_OTG_DOUBLE_BUFFER_CONTROL, .OTG_H_TOTAL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_TOTAL_BASE_IDX + mmOTGid_OTG_H_TOTAL, .OTG_H_BLANK_START_END = DCN_BASE__INST0_SEGmmOTGid_OTG_H_BLANK_START_END_BASE_IDX + mmOTGid_OTG_H_BLANK_START_END, .OTG_H_SYNC_A = DCN_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_BASE_IDX + mmOTGid_OTG_H_SYNC_A, .OTG_H_SYNC_A_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX + mmOTGid_OTG_H_SYNC_A_CNTL, .OTG_H_TIMING_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_TIMING_CNTL_BASE_IDX + mmOTGid_OTG_H_TIMING_CNTL, .OTG_V_TOTAL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_BASE_IDX + mmOTGid_OTG_V_TOTAL, .OTG_V_BLANK_START_END = DCN_BASE__INST0_SEGmmOTGid_OTG_V_BLANK_START_END_BASE_IDX + mmOTGid_OTG_V_BLANK_START_END, .OTG_V_SYNC_A = DCN_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_BASE_IDX + mmOTGid_OTG_V_SYNC_A, .OTG_V_SYNC_A_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX + mmOTGid_OTG_V_SYNC_A_CNTL, .OTG_INTERLACE_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_INTERLACE_CONTROL_BASE_IDX + mmOTGid_OTG_INTERLACE_CONTROL, .OTG_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CONTROL_BASE_IDX + mmOTGid_OTG_CONTROL, .OTG_STEREO_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_STEREO_CONTROL_BASE_IDX + mmOTGid_OTG_STEREO_CONTROL, .OTG_3D_STRUCTURE_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX + mmOTGid_OTG_3D_STRUCTURE_CONTROL, .OTG_STEREO_STATUS = DCN_BASE__INST0_SEGmmOTGid_OTG_STEREO_STATUS_BASE_IDX + mmOTGid_OTG_STEREO_STATUS, .OTG_V_TOTAL_MAX = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MAX_BASE_IDX + mmOTGid_OTG_V_TOTAL_MAX, .OTG_V_TOTAL_MID = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MID_BASE_IDX + mmOTGid_OTG_V_TOTAL_MID, .OTG_V_TOTAL_MIN = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MIN_BASE_IDX + mmOTGid_OTG_V_TOTAL_MIN, .OTG_V_TOTAL_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX + mmOTGid_OTG_V_TOTAL_CONTROL, .OTG_TRIGA_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_TRIGA_CNTL_BASE_IDX + mmOTGid_OTG_TRIGA_CNTL, .OTG_FORCE_COUNT_NOW_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX + mmOTGid_OTG_FORCE_COUNT_NOW_CNTL, .OTG_STATIC_SCREEN_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX + mmOTGid_OTG_STATIC_SCREEN_CONTROL, .OTG_STATUS_FRAME_COUNT = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX + mmOTGid_OTG_STATUS_FRAME_COUNT, .OTG_STATUS = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_BASE_IDX + mmOTGid_OTG_STATUS, .OTG_STATUS_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_POSITION_BASE_IDX + mmOTGid_OTG_STATUS_POSITION, .OTG_NOM_VERT_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_NOM_VERT_POSITION_BASE_IDX + mmOTGid_OTG_NOM_VERT_POSITION, .OTG_BLACK_COLOR = DCN_BASE__INST0_SEGmmOTGid_OTG_BLACK_COLOR_BASE_IDX + mmOTGid_OTG_BLACK_COLOR, .OTG_CLOCK_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CLOCK_CONTROL_BASE_IDX + mmOTGid_OTG_CLOCK_CONTROL, .OTG_VERTICAL_INTERRUPT0_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, .OTG_VERTICAL_INTERRUPT0_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, .OTG_VERTICAL_INTERRUPT1_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, .OTG_VERTICAL_INTERRUPT1_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, .OTG_VERTICAL_INTERRUPT2_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, .OTG_VERTICAL_INTERRUPT2_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, .OPTC_INPUT_CLOCK_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX + mmODMid_OPTC_INPUT_CLOCK_CONTROL, .OPTC_DATA_SOURCE_SELECT = DCN_BASE__INST0_SEGmmODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX + mmODMid_OPTC_DATA_SOURCE_SELECT, .OPTC_INPUT_GLOBAL_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX + mmODMid_OPTC_INPUT_GLOBAL_CONTROL, .CONTROL = DCN_BASE__INST0_SEGmmVTGid_CONTROL_BASE_IDX + mmVTGid_CONTROL, .OTG_VERT_SYNC_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX + mmOTGid_OTG_VERT_SYNC_CONTROL, .OTG_MASTER_UPDATE_MODE = DCN_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_MODE_BASE_IDX + mmOTGid_OTG_MASTER_UPDATE_MODE, .OTG_GSL_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_CONTROL_BASE_IDX + mmOTGid_OTG_GSL_CONTROL, .OTG_CRC_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL_BASE_IDX + mmOTGid_OTG_CRC_CNTL, .OTG_CRC0_DATA_RG = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_RG_BASE_IDX + mmOTGid_OTG_CRC0_DATA_RG, .OTG_CRC0_DATA_B = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_B_BASE_IDX + mmOTGid_OTG_CRC0_DATA_B, .OTG_CRC0_WINDOWA_X_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX + mmOTGid_OTG_CRC0_WINDOWA_X_CONTROL, .OTG_CRC0_WINDOWA_Y_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX + mmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, .OTG_CRC0_WINDOWB_X_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX + mmOTGid_OTG_CRC0_WINDOWB_X_CONTROL, .OTG_CRC0_WINDOWB_Y_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX + mmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX + mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_TRIGA_MANUAL_TRIG = DCN_BASE__INST0_SEGmmOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX + mmOTGid_OTG_TRIGA_MANUAL_TRIG, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX + mmOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX + mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_GSL_WINDOW_X = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_X_BASE_IDX + mmOTGid_OTG_GSL_WINDOW_X, .OTG_GSL_WINDOW_Y = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_Y_BASE_IDX + mmOTGid_OTG_GSL_WINDOW_Y, .OTG_VUPDATE_KEEPOUT = DCN_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX + mmOTGid_OTG_VUPDATE_KEEPOUT, .OTG_DSC_START_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_DSC_START_POSITION_BASE_IDX + mmOTGid_OTG_DSC_START_POSITION, .OTG_CRC_CNTL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL2_BASE_IDX + mmOTGid_OTG_CRC_CNTL2, .OPTC_DATA_FORMAT_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX + mmODMid_OPTC_DATA_FORMAT_CONTROL, .OPTC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGmmODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX + mmODMid_OPTC_BYTES_PER_PIXEL, .OPTC_WIDTH_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_WIDTH_CONTROL_BASE_IDX + mmODMid_OPTC_WIDTH_CONTROL, .OPTC_MEMORY_CONFIG = DCN_BASE__INST0_SEGmmODMid_OPTC_MEMORY_CONFIG_BASE_IDX + mmODMid_OPTC_MEMORY_CONFIG, .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_MANUAL_FLOW_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_MANUAL_FLOW_CONTROL_BASE_IDX + mmOTGid_OTG_MANUAL_FLOW_CONTROL}\ | |||
853 | [id] = {TG_COMMON_REG_LIST_DCN2_0(id).OTG_VSTARTUP_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VSTARTUP_PARAM_BASE_IDX + mmOTGid_OTG_VSTARTUP_PARAM, .OTG_VUPDATE_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_PARAM_BASE_IDX + mmOTGid_OTG_VUPDATE_PARAM, .OTG_VREADY_PARAM = DCN_BASE__INST0_SEGmmOTGid_OTG_VREADY_PARAM_BASE_IDX + mmOTGid_OTG_VREADY_PARAM, .OTG_BLANK_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_BLANK_CONTROL_BASE_IDX + mmOTGid_OTG_BLANK_CONTROL, .OTG_MASTER_UPDATE_LOCK = DCN_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_LOCK_BASE_IDX + mmOTGid_OTG_MASTER_UPDATE_LOCK, .OTG_GLOBAL_CONTROL0 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL0_BASE_IDX + mmOTGid_OTG_GLOBAL_CONTROL0, .OTG_DOUBLE_BUFFER_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX + mmOTGid_OTG_DOUBLE_BUFFER_CONTROL, .OTG_H_TOTAL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_TOTAL_BASE_IDX + mmOTGid_OTG_H_TOTAL, .OTG_H_BLANK_START_END = DCN_BASE__INST0_SEGmmOTGid_OTG_H_BLANK_START_END_BASE_IDX + mmOTGid_OTG_H_BLANK_START_END, .OTG_H_SYNC_A = DCN_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_BASE_IDX + mmOTGid_OTG_H_SYNC_A, .OTG_H_SYNC_A_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_SYNC_A_CNTL_BASE_IDX + mmOTGid_OTG_H_SYNC_A_CNTL, .OTG_H_TIMING_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_H_TIMING_CNTL_BASE_IDX + mmOTGid_OTG_H_TIMING_CNTL, .OTG_V_TOTAL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_BASE_IDX + mmOTGid_OTG_V_TOTAL, .OTG_V_BLANK_START_END = DCN_BASE__INST0_SEGmmOTGid_OTG_V_BLANK_START_END_BASE_IDX + mmOTGid_OTG_V_BLANK_START_END, .OTG_V_SYNC_A = DCN_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_BASE_IDX + mmOTGid_OTG_V_SYNC_A, .OTG_V_SYNC_A_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_SYNC_A_CNTL_BASE_IDX + mmOTGid_OTG_V_SYNC_A_CNTL, .OTG_INTERLACE_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_INTERLACE_CONTROL_BASE_IDX + mmOTGid_OTG_INTERLACE_CONTROL, .OTG_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CONTROL_BASE_IDX + mmOTGid_OTG_CONTROL, .OTG_STEREO_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_STEREO_CONTROL_BASE_IDX + mmOTGid_OTG_STEREO_CONTROL, .OTG_3D_STRUCTURE_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_3D_STRUCTURE_CONTROL_BASE_IDX + mmOTGid_OTG_3D_STRUCTURE_CONTROL, .OTG_STEREO_STATUS = DCN_BASE__INST0_SEGmmOTGid_OTG_STEREO_STATUS_BASE_IDX + mmOTGid_OTG_STEREO_STATUS, .OTG_V_TOTAL_MAX = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MAX_BASE_IDX + mmOTGid_OTG_V_TOTAL_MAX, .OTG_V_TOTAL_MID = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MID_BASE_IDX + mmOTGid_OTG_V_TOTAL_MID, .OTG_V_TOTAL_MIN = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_MIN_BASE_IDX + mmOTGid_OTG_V_TOTAL_MIN, .OTG_V_TOTAL_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_V_TOTAL_CONTROL_BASE_IDX + mmOTGid_OTG_V_TOTAL_CONTROL, .OTG_TRIGA_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_TRIGA_CNTL_BASE_IDX + mmOTGid_OTG_TRIGA_CNTL, .OTG_FORCE_COUNT_NOW_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX + mmOTGid_OTG_FORCE_COUNT_NOW_CNTL, .OTG_STATIC_SCREEN_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_STATIC_SCREEN_CONTROL_BASE_IDX + mmOTGid_OTG_STATIC_SCREEN_CONTROL, .OTG_STATUS_FRAME_COUNT = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_FRAME_COUNT_BASE_IDX + mmOTGid_OTG_STATUS_FRAME_COUNT, .OTG_STATUS = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_BASE_IDX + mmOTGid_OTG_STATUS, .OTG_STATUS_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_STATUS_POSITION_BASE_IDX + mmOTGid_OTG_STATUS_POSITION, .OTG_NOM_VERT_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_NOM_VERT_POSITION_BASE_IDX + mmOTGid_OTG_NOM_VERT_POSITION, .OTG_BLACK_COLOR = DCN_BASE__INST0_SEGmmOTGid_OTG_BLACK_COLOR_BASE_IDX + mmOTGid_OTG_BLACK_COLOR, .OTG_CLOCK_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CLOCK_CONTROL_BASE_IDX + mmOTGid_OTG_CLOCK_CONTROL, .OTG_VERTICAL_INTERRUPT0_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT0_CONTROL, .OTG_VERTICAL_INTERRUPT0_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT0_POSITION, .OTG_VERTICAL_INTERRUPT1_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT1_CONTROL, .OTG_VERTICAL_INTERRUPT1_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT1_POSITION, .OTG_VERTICAL_INTERRUPT2_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT2_CONTROL, .OTG_VERTICAL_INTERRUPT2_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX + mmOTGid_OTG_VERTICAL_INTERRUPT2_POSITION, .OPTC_INPUT_CLOCK_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX + mmODMid_OPTC_INPUT_CLOCK_CONTROL, .OPTC_DATA_SOURCE_SELECT = DCN_BASE__INST0_SEGmmODMid_OPTC_DATA_SOURCE_SELECT_BASE_IDX + mmODMid_OPTC_DATA_SOURCE_SELECT, .OPTC_INPUT_GLOBAL_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX + mmODMid_OPTC_INPUT_GLOBAL_CONTROL, .CONTROL = DCN_BASE__INST0_SEGmmVTGid_CONTROL_BASE_IDX + mmVTGid_CONTROL, .OTG_VERT_SYNC_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_VERT_SYNC_CONTROL_BASE_IDX + mmOTGid_OTG_VERT_SYNC_CONTROL, .OTG_MASTER_UPDATE_MODE = DCN_BASE__INST0_SEGmmOTGid_OTG_MASTER_UPDATE_MODE_BASE_IDX + mmOTGid_OTG_MASTER_UPDATE_MODE, .OTG_GSL_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_CONTROL_BASE_IDX + mmOTGid_OTG_GSL_CONTROL, .OTG_CRC_CNTL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL_BASE_IDX + mmOTGid_OTG_CRC_CNTL, .OTG_CRC0_DATA_RG = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_RG_BASE_IDX + mmOTGid_OTG_CRC0_DATA_RG, .OTG_CRC0_DATA_B = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_DATA_B_BASE_IDX + mmOTGid_OTG_CRC0_DATA_B, .OTG_CRC0_WINDOWA_X_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX + mmOTGid_OTG_CRC0_WINDOWA_X_CONTROL, .OTG_CRC0_WINDOWA_Y_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX + mmOTGid_OTG_CRC0_WINDOWA_Y_CONTROL, .OTG_CRC0_WINDOWB_X_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX + mmOTGid_OTG_CRC0_WINDOWB_X_CONTROL, .OTG_CRC0_WINDOWB_Y_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX + mmOTGid_OTG_CRC0_WINDOWB_Y_CONTROL, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX + mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_TRIGA_MANUAL_TRIG = DCN_BASE__INST0_SEGmmOTGid_OTG_TRIGA_MANUAL_TRIG_BASE_IDX + mmOTGid_OTG_TRIGA_MANUAL_TRIG, .OTG_GLOBAL_CONTROL1 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL1_BASE_IDX + mmOTGid_OTG_GLOBAL_CONTROL1, .OTG_GLOBAL_CONTROL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_GLOBAL_CONTROL2_BASE_IDX + mmOTGid_OTG_GLOBAL_CONTROL2, .OTG_GSL_WINDOW_X = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_X_BASE_IDX + mmOTGid_OTG_GSL_WINDOW_X, .OTG_GSL_WINDOW_Y = DCN_BASE__INST0_SEGmmOTGid_OTG_GSL_WINDOW_Y_BASE_IDX + mmOTGid_OTG_GSL_WINDOW_Y, .OTG_VUPDATE_KEEPOUT = DCN_BASE__INST0_SEGmmOTGid_OTG_VUPDATE_KEEPOUT_BASE_IDX + mmOTGid_OTG_VUPDATE_KEEPOUT, .OTG_DSC_START_POSITION = DCN_BASE__INST0_SEGmmOTGid_OTG_DSC_START_POSITION_BASE_IDX + mmOTGid_OTG_DSC_START_POSITION, .OTG_CRC_CNTL2 = DCN_BASE__INST0_SEGmmOTGid_OTG_CRC_CNTL2_BASE_IDX + mmOTGid_OTG_CRC_CNTL2, .OPTC_DATA_FORMAT_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_DATA_FORMAT_CONTROL_BASE_IDX + mmODMid_OPTC_DATA_FORMAT_CONTROL, .OPTC_BYTES_PER_PIXEL = DCN_BASE__INST0_SEGmmODMid_OPTC_BYTES_PER_PIXEL_BASE_IDX + mmODMid_OPTC_BYTES_PER_PIXEL, .OPTC_WIDTH_CONTROL = DCN_BASE__INST0_SEGmmODMid_OPTC_WIDTH_CONTROL_BASE_IDX + mmODMid_OPTC_WIDTH_CONTROL, .OPTC_MEMORY_CONFIG = DCN_BASE__INST0_SEGmmODMid_OPTC_MEMORY_CONFIG_BASE_IDX + mmODMid_OPTC_MEMORY_CONFIG, .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_MANUAL_FLOW_CONTROL = DCN_BASE__INST0_SEGmmOTGid_OTG_MANUAL_FLOW_CONTROL_BASE_IDX + mmOTGid_OTG_MANUAL_FLOW_CONTROL} | |||
854 | ||||
855 | ||||
856 | static const struct dcn_optc_registers tg_regs[] = { | |||
857 | tg_regs(0)[0] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1b87, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1b88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1b89 , .OTG_BLANK_CONTROL = 0x000034C0 + 0x1b42, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1b8b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1b90 , .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1b5b, .OTG_H_TOTAL = 0x000034C0 + 0x1b2a, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1b2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1b2c, .OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1b2d, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1b2e , .OTG_V_TOTAL = 0x000034C0 + 0x1b2f, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1b36, .OTG_V_SYNC_A = 0x000034C0 + 0x1b37, .OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1b38, .OTG_INTERLACE_CONTROL = 0x000034C0 + 0x1b44, .OTG_CONTROL = 0x000034C0 + 0x1b41, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1b54, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1b83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1b53, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1b31, .OTG_V_TOTAL_MID = 0x000034C0 + 0x1b32 , .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1b30, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1b33, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1b39 , .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1b3d, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1b82, .OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1b4c, .OTG_STATUS = 0x000034C0 + 0x1b49, .OTG_STATUS_POSITION = 0x000034C0 + 0x1b4a, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1b4b, .OTG_BLACK_COLOR = 0x000034C0 + 0x1b60, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1b86, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1b63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1b62 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1b65, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1b64, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1b67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1b66 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1acf, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1acb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1aca, .CONTROL = 0x000034C0 + 0x0528, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1b52, .OTG_MASTER_UPDATE_MODE = 0x000034C0 + 0x1b85, .OTG_GSL_CONTROL = 0x000034C0 + 0x1b8c, .OTG_CRC_CNTL = 0x000034C0 + 0x1b68, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1b6e , .OTG_CRC0_DATA_B = 0x000034C0 + 0x1b6f, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1b6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1b6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1b6c, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1b6d, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1b92 , .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1b3a, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1b91, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1b92 , .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1b8d, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1b8e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1b8f , .OTG_DSC_START_POSITION = 0x000034C0 + 0x1b99, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1b69, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1acc, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1acd, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1ace, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1ad0 , .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_MANUAL_FLOW_CONTROL = 0x000034C0 + 0x1b95}, | |||
858 | tg_regs(1)[1] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1c07, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1c08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1c09 , .OTG_BLANK_CONTROL = 0x000034C0 + 0x1bc2, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1c0b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1c10 , .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1bdb, .OTG_H_TOTAL = 0x000034C0 + 0x1baa, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1bab, .OTG_H_SYNC_A = 0x000034C0 + 0x1bac, .OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1bad, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1bae , .OTG_V_TOTAL = 0x000034C0 + 0x1baf, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1bb6, .OTG_V_SYNC_A = 0x000034C0 + 0x1bb7, .OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1bb8, .OTG_INTERLACE_CONTROL = 0x000034C0 + 0x1bc4, .OTG_CONTROL = 0x000034C0 + 0x1bc1, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1bd4, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1c03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1bd3, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1bb1, .OTG_V_TOTAL_MID = 0x000034C0 + 0x1bb2 , .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1bb0, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1bb3, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1bb9 , .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1bbd, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1c02, .OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1bcc, .OTG_STATUS = 0x000034C0 + 0x1bc9, .OTG_STATUS_POSITION = 0x000034C0 + 0x1bca, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1bcb, .OTG_BLACK_COLOR = 0x000034C0 + 0x1be0, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1c06, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1be3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1be2 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1be5, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1be4, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1be7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1be6 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1adf, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1adb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1ada, .CONTROL = 0x000034C0 + 0x0529, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1bd2, .OTG_MASTER_UPDATE_MODE = 0x000034C0 + 0x1c05, .OTG_GSL_CONTROL = 0x000034C0 + 0x1c0c, .OTG_CRC_CNTL = 0x000034C0 + 0x1be8, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1bee , .OTG_CRC0_DATA_B = 0x000034C0 + 0x1bef, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1bea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1beb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1bec, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1bed, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c12 , .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1bba, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c11, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c12 , .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1c0d, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1c0e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1c0f , .OTG_DSC_START_POSITION = 0x000034C0 + 0x1c19, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1be9, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1adc, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1add, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1ade, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1ae0 , .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_MANUAL_FLOW_CONTROL = 0x000034C0 + 0x1c15}, | |||
859 | tg_regs(2)[2] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1c87, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1c88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1c89 , .OTG_BLANK_CONTROL = 0x000034C0 + 0x1c42, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1c8b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1c90 , .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1c5b, .OTG_H_TOTAL = 0x000034C0 + 0x1c2a, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1c2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1c2c, .OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1c2d, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1c2e , .OTG_V_TOTAL = 0x000034C0 + 0x1c2f, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1c36, .OTG_V_SYNC_A = 0x000034C0 + 0x1c37, .OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1c38, .OTG_INTERLACE_CONTROL = 0x000034C0 + 0x1c44, .OTG_CONTROL = 0x000034C0 + 0x1c41, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1c54, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1c83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1c53, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1c31, .OTG_V_TOTAL_MID = 0x000034C0 + 0x1c32 , .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1c30, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1c33, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1c39 , .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1c3d, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1c82, .OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1c4c, .OTG_STATUS = 0x000034C0 + 0x1c49, .OTG_STATUS_POSITION = 0x000034C0 + 0x1c4a, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1c4b, .OTG_BLACK_COLOR = 0x000034C0 + 0x1c60, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1c86, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1c63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1c62 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1c65, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1c64, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1c67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1c66 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1aef, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1aeb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1aea, .CONTROL = 0x000034C0 + 0x052a, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1c52, .OTG_MASTER_UPDATE_MODE = 0x000034C0 + 0x1c85, .OTG_GSL_CONTROL = 0x000034C0 + 0x1c8c, .OTG_CRC_CNTL = 0x000034C0 + 0x1c68, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1c6e , .OTG_CRC0_DATA_B = 0x000034C0 + 0x1c6f, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1c6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1c6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1c6c, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1c6d, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c92 , .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1c3a, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1c91, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1c92 , .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1c8d, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1c8e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1c8f , .OTG_DSC_START_POSITION = 0x000034C0 + 0x1c99, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1c69, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1aec, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1aed, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1aee, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1af0 , .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_MANUAL_FLOW_CONTROL = 0x000034C0 + 0x1c95}, | |||
860 | tg_regs(3)[3] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1d07, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1d08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1d09 , .OTG_BLANK_CONTROL = 0x000034C0 + 0x1cc2, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1d0b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1d10 , .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1cdb, .OTG_H_TOTAL = 0x000034C0 + 0x1caa, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1cab, .OTG_H_SYNC_A = 0x000034C0 + 0x1cac, .OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1cad, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1cae , .OTG_V_TOTAL = 0x000034C0 + 0x1caf, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1cb6, .OTG_V_SYNC_A = 0x000034C0 + 0x1cb7, .OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1cb8, .OTG_INTERLACE_CONTROL = 0x000034C0 + 0x1cc4, .OTG_CONTROL = 0x000034C0 + 0x1cc1, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1cd4, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1d03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1cd3, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1cb1, .OTG_V_TOTAL_MID = 0x000034C0 + 0x1cb2 , .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1cb0, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1cb3, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1cb9 , .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1cbd, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1d02, .OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1ccc, .OTG_STATUS = 0x000034C0 + 0x1cc9, .OTG_STATUS_POSITION = 0x000034C0 + 0x1cca, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1ccb, .OTG_BLACK_COLOR = 0x000034C0 + 0x1ce0, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1d06, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1ce3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1ce2 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1ce5, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1ce4, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1ce7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1ce6 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1aff, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1afb, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1afa, .CONTROL = 0x000034C0 + 0x052b, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1cd2, .OTG_MASTER_UPDATE_MODE = 0x000034C0 + 0x1d05, .OTG_GSL_CONTROL = 0x000034C0 + 0x1d0c, .OTG_CRC_CNTL = 0x000034C0 + 0x1ce8, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1cee , .OTG_CRC0_DATA_B = 0x000034C0 + 0x1cef, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1cea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1ceb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1cec, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1ced, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1d12 , .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1cba, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1d11, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1d12 , .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1d0d, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1d0e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1d0f , .OTG_DSC_START_POSITION = 0x000034C0 + 0x1d19, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1ce9, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1afc, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1afd, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1afe, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1b00 , .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_MANUAL_FLOW_CONTROL = 0x000034C0 + 0x1d15}, | |||
861 | tg_regs(4)[4] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1d87, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1d88, .OTG_VREADY_PARAM = 0x000034C0 + 0x1d89 , .OTG_BLANK_CONTROL = 0x000034C0 + 0x1d42, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1d8b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1d90 , .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1d5b, .OTG_H_TOTAL = 0x000034C0 + 0x1d2a, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1d2b, .OTG_H_SYNC_A = 0x000034C0 + 0x1d2c, .OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1d2d, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1d2e , .OTG_V_TOTAL = 0x000034C0 + 0x1d2f, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1d36, .OTG_V_SYNC_A = 0x000034C0 + 0x1d37, .OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1d38, .OTG_INTERLACE_CONTROL = 0x000034C0 + 0x1d44, .OTG_CONTROL = 0x000034C0 + 0x1d41, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1d54, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1d83, .OTG_STEREO_STATUS = 0x000034C0 + 0x1d53, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1d31, .OTG_V_TOTAL_MID = 0x000034C0 + 0x1d32 , .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1d30, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1d33, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1d39 , .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1d3d, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1d82, .OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1d4c, .OTG_STATUS = 0x000034C0 + 0x1d49, .OTG_STATUS_POSITION = 0x000034C0 + 0x1d4a, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1d4b, .OTG_BLACK_COLOR = 0x000034C0 + 0x1d60, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1d86, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1d63, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1d62 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1d65, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1d64, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1d67, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1d66 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1b0f, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1b0b, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1b0a, .CONTROL = 0x000034C0 + 0x052c, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1d52, .OTG_MASTER_UPDATE_MODE = 0x000034C0 + 0x1d85, .OTG_GSL_CONTROL = 0x000034C0 + 0x1d8c, .OTG_CRC_CNTL = 0x000034C0 + 0x1d68, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1d6e , .OTG_CRC0_DATA_B = 0x000034C0 + 0x1d6f, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1d6a, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1d6b, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1d6c, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1d6d, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1d92 , .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1d3a, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1d91, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1d92 , .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1d8d, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1d8e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1d8f , .OTG_DSC_START_POSITION = 0x000034C0 + 0x1d99, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1d69, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1b0c, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1b0d, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1b0e, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1b10 , .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_MANUAL_FLOW_CONTROL = 0x000034C0 + 0x1d95}, | |||
862 | tg_regs(5)[5] = {.OTG_VSTARTUP_PARAM = 0x000034C0 + 0x1e07, .OTG_VUPDATE_PARAM = 0x000034C0 + 0x1e08, .OTG_VREADY_PARAM = 0x000034C0 + 0x1e09 , .OTG_BLANK_CONTROL = 0x000034C0 + 0x1dc2, .OTG_MASTER_UPDATE_LOCK = 0x000034C0 + 0x1e0b, .OTG_GLOBAL_CONTROL0 = 0x000034C0 + 0x1e10 , .OTG_DOUBLE_BUFFER_CONTROL = 0x000034C0 + 0x1ddb, .OTG_H_TOTAL = 0x000034C0 + 0x1daa, .OTG_H_BLANK_START_END = 0x000034C0 + 0x1dab, .OTG_H_SYNC_A = 0x000034C0 + 0x1dac, .OTG_H_SYNC_A_CNTL = 0x000034C0 + 0x1dad, .OTG_H_TIMING_CNTL = 0x000034C0 + 0x1dae , .OTG_V_TOTAL = 0x000034C0 + 0x1daf, .OTG_V_BLANK_START_END = 0x000034C0 + 0x1db6, .OTG_V_SYNC_A = 0x000034C0 + 0x1db7, .OTG_V_SYNC_A_CNTL = 0x000034C0 + 0x1db8, .OTG_INTERLACE_CONTROL = 0x000034C0 + 0x1dc4, .OTG_CONTROL = 0x000034C0 + 0x1dc1, .OTG_STEREO_CONTROL = 0x000034C0 + 0x1dd4, .OTG_3D_STRUCTURE_CONTROL = 0x000034C0 + 0x1e03, .OTG_STEREO_STATUS = 0x000034C0 + 0x1dd3, .OTG_V_TOTAL_MAX = 0x000034C0 + 0x1db1, .OTG_V_TOTAL_MID = 0x000034C0 + 0x1db2 , .OTG_V_TOTAL_MIN = 0x000034C0 + 0x1db0, .OTG_V_TOTAL_CONTROL = 0x000034C0 + 0x1db3, .OTG_TRIGA_CNTL = 0x000034C0 + 0x1db9 , .OTG_FORCE_COUNT_NOW_CNTL = 0x000034C0 + 0x1dbd, .OTG_STATIC_SCREEN_CONTROL = 0x000034C0 + 0x1e02, .OTG_STATUS_FRAME_COUNT = 0x000034C0 + 0x1dcc, .OTG_STATUS = 0x000034C0 + 0x1dc9, .OTG_STATUS_POSITION = 0x000034C0 + 0x1dca, .OTG_NOM_VERT_POSITION = 0x000034C0 + 0x1dcb, .OTG_BLACK_COLOR = 0x000034C0 + 0x1de0, .OTG_CLOCK_CONTROL = 0x000034C0 + 0x1e06, .OTG_VERTICAL_INTERRUPT0_CONTROL = 0x000034C0 + 0x1de3, .OTG_VERTICAL_INTERRUPT0_POSITION = 0x000034C0 + 0x1de2 , .OTG_VERTICAL_INTERRUPT1_CONTROL = 0x000034C0 + 0x1de5, .OTG_VERTICAL_INTERRUPT1_POSITION = 0x000034C0 + 0x1de4, .OTG_VERTICAL_INTERRUPT2_CONTROL = 0x000034C0 + 0x1de7, .OTG_VERTICAL_INTERRUPT2_POSITION = 0x000034C0 + 0x1de6 , .OPTC_INPUT_CLOCK_CONTROL = 0x000034C0 + 0x1b1f, .OPTC_DATA_SOURCE_SELECT = 0x000034C0 + 0x1b1b, .OPTC_INPUT_GLOBAL_CONTROL = 0x000034C0 + 0x1b1a, .CONTROL = 0x000034C0 + 0x052d, .OTG_VERT_SYNC_CONTROL = 0x000034C0 + 0x1dd2, .OTG_MASTER_UPDATE_MODE = 0x000034C0 + 0x1e05, .OTG_GSL_CONTROL = 0x000034C0 + 0x1e0c, .OTG_CRC_CNTL = 0x000034C0 + 0x1de8, .OTG_CRC0_DATA_RG = 0x000034C0 + 0x1dee , .OTG_CRC0_DATA_B = 0x000034C0 + 0x1def, .OTG_CRC0_WINDOWA_X_CONTROL = 0x000034C0 + 0x1dea, .OTG_CRC0_WINDOWA_Y_CONTROL = 0x000034C0 + 0x1deb, .OTG_CRC0_WINDOWB_X_CONTROL = 0x000034C0 + 0x1dec, .OTG_CRC0_WINDOWB_Y_CONTROL = 0x000034C0 + 0x1ded, .GSL_SOURCE_SELECT = 0x000034C0 + 0x1e2b, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1e12 , .OTG_TRIGA_MANUAL_TRIG = 0x000034C0 + 0x1dba, .OTG_GLOBAL_CONTROL1 = 0x000034C0 + 0x1e11, .OTG_GLOBAL_CONTROL2 = 0x000034C0 + 0x1e12 , .OTG_GSL_WINDOW_X = 0x000034C0 + 0x1e0d, .OTG_GSL_WINDOW_Y = 0x000034C0 + 0x1e0e, .OTG_VUPDATE_KEEPOUT = 0x000034C0 + 0x1e0f , .OTG_DSC_START_POSITION = 0x000034C0 + 0x1e19, .OTG_CRC_CNTL2 = 0x000034C0 + 0x1de9, .OPTC_DATA_FORMAT_CONTROL = 0x000034C0 + 0x1b1c, .OPTC_BYTES_PER_PIXEL = 0x000034C0 + 0x1b1d, .OPTC_WIDTH_CONTROL = 0x000034C0 + 0x1b1e, .OPTC_MEMORY_CONFIG = 0x000034C0 + 0x1b20 , .DWB_SOURCE_SELECT = 0x000034C0 + 0x1e2a, .OTG_MANUAL_FLOW_CONTROL = 0x000034C0 + 0x1e15} | |||
863 | }; | |||
864 | ||||
865 | static const struct dcn_optc_shift tg_shift = { | |||
866 | TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT).VSTARTUP_START = 0x0, .VUPDATE_OFFSET = 0x0, .VUPDATE_WIDTH = 0x10, .VREADY_OFFSET = 0x0, .OTG_BLANK_DATA_EN = 0x8, .OTG_BLANK_DE_MODE = 0x10, .OTG_CURRENT_BLANK_STATE = 0x0, .OTG_MASTER_UPDATE_LOCK = 0x0, .UPDATE_LOCK_STATUS = 0x8, .OTG_MASTER_UPDATE_LOCK_SEL = 0x19, .OTG_UPDATE_PENDING = 0x0, .OTG_BLANK_DATA_DOUBLE_BUFFER_EN = 0x10, .OTG_RANGE_TIMING_DBUF_UPDATE_MODE = 0x18, .OTG_H_TOTAL = 0x0, .OTG_H_BLANK_START = 0x0, .OTG_H_BLANK_END = 0x10, .OTG_H_SYNC_A_START = 0x0, .OTG_H_SYNC_A_END = 0x10, .OTG_H_SYNC_A_POL = 0x0, .OTG_H_TIMING_DIV_BY2 = 0x0, .OTG_V_TOTAL = 0x0, .OTG_V_BLANK_START = 0x0, .OTG_V_BLANK_END = 0x10, .OTG_V_SYNC_A_START = 0x0, .OTG_V_SYNC_A_END = 0x10, .OTG_V_SYNC_A_POL = 0x0, .OTG_INTERLACE_ENABLE = 0x0, .OTG_MASTER_EN = 0x0, .OTG_START_POINT_CNTL = 0xc, .OTG_DISABLE_POINT_CNTL = 0x8, .OTG_FIELD_NUMBER_CNTL = 0xd, .OTG_STEREO_EN = 0x18, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM = 0x0, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0xf, .OTG_STEREO_EYE_FLAG_POLARITY = 0x11, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x12, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x12, .OTG_STEREO_CURRENT_EYE = 0x0, .OTG_3D_STRUCTURE_EN = 0x0, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x8, .OTG_3D_STRUCTURE_STEREO_SEL_OVR = 0xc, .OTG_V_TOTAL_MAX = 0x0, .OTG_V_TOTAL_MID = 0x0, .OTG_V_TOTAL_MIN = 0x0, .OTG_V_TOTAL_MIN_SEL = 0x0, .OTG_V_TOTAL_MAX_SEL = 0x1 , .OTG_FORCE_LOCK_ON_EVENT = 0x4, .OTG_SET_V_TOTAL_MIN_MASK_EN = 0x7, .OTG_SET_V_TOTAL_MIN_MASK = 0x10, .OTG_VTOTAL_MID_REPLACING_MAX_EN = 0x2, .OTG_VTOTAL_MID_FRAME_NUM = 0x8, .OTG_FORCE_COUNT_NOW_CLEAR = 0x18, .OTG_FORCE_COUNT_NOW_MODE = 0x0, .OTG_FORCE_COUNT_NOW_OCCURRED = 0x10, .OTG_TRIGA_SOURCE_SELECT = 0x0, .OTG_TRIGA_SOURCE_PIPE_SELECT = 0x5, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x10, .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x12, .OTG_TRIGA_POLARITY_SELECT = 0x8, .OTG_TRIGA_FREQUENCY_SELECT = 0x14, .OTG_TRIGA_DELAY = 0x18, .OTG_TRIGA_CLEAR = 0x1f, .OTG_TRIGA_MANUAL_TRIG = 0x0, .OTG_STATIC_SCREEN_EVENT_MASK = 0x0, .OTG_STATIC_SCREEN_FRAME_COUNT = 0x10, .OTG_FRAME_COUNT = 0x0, .OTG_V_BLANK = 0x0, .OTG_V_ACTIVE_DISP = 0x1, .OTG_HORZ_COUNT = 0x10, .OTG_VERT_COUNT = 0x0, .OTG_VERT_COUNT_NOM = 0x0, .OTG_BLACK_COLOR_B_CB = 0x0, .OTG_BLACK_COLOR_G_Y = 0xa , .OTG_BLACK_COLOR_R_CR = 0x14, .OTG_BUSY = 0x10, .OTG_CLOCK_EN = 0x0, .OTG_CLOCK_ON = 0x8, .OTG_CLOCK_GATE_DIS = 0x1, .OTG_VERTICAL_INTERRUPT0_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT0_LINE_START = 0x0, .OTG_VERTICAL_INTERRUPT0_LINE_END = 0x10, .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT1_LINE_START = 0x0, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x8, .OTG_VERTICAL_INTERRUPT2_LINE_START = 0x0, .OPTC_INPUT_CLK_EN = 0x1, .OPTC_INPUT_CLK_ON = 0x2, . OPTC_INPUT_CLK_GATE_DIS = 0x0, .OPTC_UNDERFLOW_OCCURRED_STATUS = 0xa, .OPTC_UNDERFLOW_CLEAR = 0xc, .VTG0_ENABLE = 0x1f, .VTG0_FP2 = 0x0, .VTG0_VCOUNT_INIT = 0x10, .OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED = 0x0, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = 0x8, .OTG_AUTO_FORCE_VSYNC_MODE = 0x10, .MASTER_UPDATE_INTERLACED_MODE = 0x0, .OTG_GSL0_EN = 0x0, .OTG_GSL1_EN = 0x1, .OTG_GSL2_EN = 0x2, .OTG_GSL_MASTER_EN = 0x3, .OTG_GSL_FORCE_DELAY = 0x10, .OTG_GSL_CHECK_ALL_FIELDS = 0x1c, .OTG_CRC_CONT_EN = 0x4, .OTG_CRC0_SELECT = 0x14, .OTG_CRC_EN = 0x0, .CRC0_R_CR = 0x0, .CRC0_G_Y = 0x10, .CRC0_B_CB = 0x0, .OTG_CRC0_WINDOWA_X_START = 0x0, .OTG_CRC0_WINDOWA_X_END = 0x10 , .OTG_CRC0_WINDOWA_Y_START = 0x0, .OTG_CRC0_WINDOWA_Y_END = 0x10 , .OTG_CRC0_WINDOWB_X_START = 0x0, .OTG_CRC0_WINDOWB_X_END = 0x10 , .OTG_CRC0_WINDOWB_Y_START = 0x0, .OTG_CRC0_WINDOWB_Y_END = 0x10 , .GSL0_READY_SOURCE_SEL = 0x0, .GSL1_READY_SOURCE_SEL = 0x4, .GSL2_READY_SOURCE_SEL = 0x8, .MANUAL_FLOW_CONTROL_SEL = 0x10 , .MASTER_UPDATE_LOCK_DB_X = 0x0, .MASTER_UPDATE_LOCK_DB_Y = 0x10 , .MASTER_UPDATE_LOCK_DB_EN = 0x1f, .GLOBAL_UPDATE_LOCK_EN = 0xa , .DIG_UPDATE_LOCATION = 0x0, .OTG_RANGE_TIMING_DBUF_UPDATE_MODE = 0x18, .OTG_GSL_WINDOW_START_X = 0x0, .OTG_GSL_WINDOW_END_X = 0x10, .OTG_GSL_WINDOW_START_Y = 0x0, .OTG_GSL_WINDOW_END_Y = 0x10, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x1f, . MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0, .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x10, .OTG_GSL_MASTER_MODE = 0x4, .OTG_MASTER_UPDATE_LOCK_GSL_EN = 0x1f, .OTG_DSC_START_POSITION_X = 0x0, .OTG_DSC_START_POSITION_LINE_NUM = 0x10, .OTG_CRC_DSC_MODE = 0x0, .OTG_CRC_DATA_STREAM_COMBINE_MODE = 0x1, .OTG_CRC_DATA_STREAM_SPLIT_MODE = 0x4, .OTG_CRC_DATA_FORMAT = 0x8, .OPTC_SEG0_SRC_SEL = 0x8, .OPTC_SEG1_SRC_SEL = 0xc, . OPTC_NUM_OF_INPUT_SEGMENT = 0x0, .OPTC_MEM_SEL = 0x0, .OPTC_DATA_FORMAT = 0x0, .OPTC_DSC_MODE = 0x4, .OPTC_DSC_BYTES_PER_PIXEL = 0x0 , .OPTC_DSC_SLICE_WIDTH = 0x10, .OPTC_SEGMENT_WIDTH = 0x0, .OPTC_DWB0_SOURCE_SELECT = 0x0, .OPTC_DWB1_SOURCE_SELECT = 0x3, .MANUAL_FLOW_CONTROL = 0x0 | |||
867 | }; | |||
868 | ||||
869 | static const struct dcn_optc_mask tg_mask = { | |||
870 | TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK).VSTARTUP_START = 0x000003FFL, .VUPDATE_OFFSET = 0x0000FFFFL, .VUPDATE_WIDTH = 0x03FF0000L, .VREADY_OFFSET = 0x0000FFFFL, . OTG_BLANK_DATA_EN = 0x00000100L, .OTG_BLANK_DE_MODE = 0x00010000L , .OTG_CURRENT_BLANK_STATE = 0x00000001L, .OTG_MASTER_UPDATE_LOCK = 0x00000001L, .UPDATE_LOCK_STATUS = 0x00000100L, .OTG_MASTER_UPDATE_LOCK_SEL = 0x0E000000L, .OTG_UPDATE_PENDING = 0x00000001L, .OTG_BLANK_DATA_DOUBLE_BUFFER_EN = 0x00010000L, .OTG_RANGE_TIMING_DBUF_UPDATE_MODE = 0x03000000L , .OTG_H_TOTAL = 0x00007FFFL, .OTG_H_BLANK_START = 0x00007FFFL , .OTG_H_BLANK_END = 0x7FFF0000L, .OTG_H_SYNC_A_START = 0x00007FFFL , .OTG_H_SYNC_A_END = 0x7FFF0000L, .OTG_H_SYNC_A_POL = 0x00000001L , .OTG_H_TIMING_DIV_BY2 = 0x00000001L, .OTG_V_TOTAL = 0x00007FFFL , .OTG_V_BLANK_START = 0x00007FFFL, .OTG_V_BLANK_END = 0x7FFF0000L , .OTG_V_SYNC_A_START = 0x00007FFFL, .OTG_V_SYNC_A_END = 0x7FFF0000L , .OTG_V_SYNC_A_POL = 0x00000001L, .OTG_INTERLACE_ENABLE = 0x00000001L , .OTG_MASTER_EN = 0x00000001L, .OTG_START_POINT_CNTL = 0x00001000L , .OTG_DISABLE_POINT_CNTL = 0x00000300L, .OTG_FIELD_NUMBER_CNTL = 0x00002000L, .OTG_STEREO_EN = 0x01000000L, .OTG_STEREO_SYNC_OUTPUT_LINE_NUM = 0x00007FFFL, .OTG_STEREO_SYNC_OUTPUT_POLARITY = 0x00008000L , .OTG_STEREO_EYE_FLAG_POLARITY = 0x00020000L, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x00040000L, .OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP = 0x00040000L , .OTG_STEREO_CURRENT_EYE = 0x00000001L, .OTG_3D_STRUCTURE_EN = 0x00000001L, .OTG_3D_STRUCTURE_V_UPDATE_MODE = 0x00000300L , .OTG_3D_STRUCTURE_STEREO_SEL_OVR = 0x00001000L, .OTG_V_TOTAL_MAX = 0x00007FFFL, .OTG_V_TOTAL_MID = 0x00007FFFL, .OTG_V_TOTAL_MIN = 0x00007FFFL, .OTG_V_TOTAL_MIN_SEL = 0x00000001L, .OTG_V_TOTAL_MAX_SEL = 0x00000002L, .OTG_FORCE_LOCK_ON_EVENT = 0x00000010L, .OTG_SET_V_TOTAL_MIN_MASK_EN = 0x00000080L, .OTG_SET_V_TOTAL_MIN_MASK = 0xFFFF0000L, .OTG_VTOTAL_MID_REPLACING_MAX_EN = 0x00000004L, .OTG_VTOTAL_MID_FRAME_NUM = 0x0000FF00L, .OTG_FORCE_COUNT_NOW_CLEAR = 0x01000000L, .OTG_FORCE_COUNT_NOW_MODE = 0x00000003L, .OTG_FORCE_COUNT_NOW_OCCURRED = 0x00010000L, .OTG_TRIGA_SOURCE_SELECT = 0x0000001FL, .OTG_TRIGA_SOURCE_PIPE_SELECT = 0x000000E0L, .OTG_TRIGA_RISING_EDGE_DETECT_CNTL = 0x00030000L , .OTG_TRIGA_FALLING_EDGE_DETECT_CNTL = 0x000C0000L, .OTG_TRIGA_POLARITY_SELECT = 0x00000700L, .OTG_TRIGA_FREQUENCY_SELECT = 0x00300000L, .OTG_TRIGA_DELAY = 0x1F000000L, .OTG_TRIGA_CLEAR = 0x80000000L, .OTG_TRIGA_MANUAL_TRIG = 0x00000001L, .OTG_STATIC_SCREEN_EVENT_MASK = 0x0000FFFFL, . OTG_STATIC_SCREEN_FRAME_COUNT = 0x00FF0000L, .OTG_FRAME_COUNT = 0x00FFFFFFL, .OTG_V_BLANK = 0x00000001L, .OTG_V_ACTIVE_DISP = 0x00000002L, .OTG_HORZ_COUNT = 0x7FFF0000L, .OTG_VERT_COUNT = 0x00007FFFL, .OTG_VERT_COUNT_NOM = 0x00007FFFL, .OTG_BLACK_COLOR_B_CB = 0x000003FFL, .OTG_BLACK_COLOR_G_Y = 0x000FFC00L, .OTG_BLACK_COLOR_R_CR = 0x3FF00000L, .OTG_BUSY = 0x00010000L, .OTG_CLOCK_EN = 0x00000001L , .OTG_CLOCK_ON = 0x00000100L, .OTG_CLOCK_GATE_DIS = 0x00000002L , .OTG_VERTICAL_INTERRUPT0_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT0_LINE_START = 0x00007FFFL, .OTG_VERTICAL_INTERRUPT0_LINE_END = 0x7FFF0000L , .OTG_VERTICAL_INTERRUPT1_INT_ENABLE = 0x00000100L, .OTG_VERTICAL_INTERRUPT1_LINE_START = 0x00007FFFL, .OTG_VERTICAL_INTERRUPT2_INT_ENABLE = 0x00000100L , .OTG_VERTICAL_INTERRUPT2_LINE_START = 0x00007FFFL, .OPTC_INPUT_CLK_EN = 0x00000002L, .OPTC_INPUT_CLK_ON = 0x00000004L, .OPTC_INPUT_CLK_GATE_DIS = 0x00000001L, .OPTC_UNDERFLOW_OCCURRED_STATUS = 0x00000400L , .OPTC_UNDERFLOW_CLEAR = 0x00001000L, .VTG0_ENABLE = 0x80000000L , .VTG0_FP2 = 0x00007FFFL, .VTG0_VCOUNT_INIT = 0x7FFF0000L, . OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED = 0x00000001L, .OTG_FORCE_VSYNC_NEXT_LINE_CLEAR = 0x00000100L, .OTG_AUTO_FORCE_VSYNC_MODE = 0x00030000L, .MASTER_UPDATE_INTERLACED_MODE = 0x00000003L, .OTG_GSL0_EN = 0x00000001L, .OTG_GSL1_EN = 0x00000002L , .OTG_GSL2_EN = 0x00000004L, .OTG_GSL_MASTER_EN = 0x00000008L , .OTG_GSL_FORCE_DELAY = 0x001F0000L, .OTG_GSL_CHECK_ALL_FIELDS = 0x10000000L, .OTG_CRC_CONT_EN = 0x00000010L, .OTG_CRC0_SELECT = 0x00700000L, .OTG_CRC_EN = 0x00000001L, .CRC0_R_CR = 0x0000FFFFL , .CRC0_G_Y = 0xFFFF0000L, .CRC0_B_CB = 0x0000FFFFL, .OTG_CRC0_WINDOWA_X_START = 0x00007FFFL, .OTG_CRC0_WINDOWA_X_END = 0x7FFF0000L, .OTG_CRC0_WINDOWA_Y_START = 0x00007FFFL, .OTG_CRC0_WINDOWA_Y_END = 0x7FFF0000L, .OTG_CRC0_WINDOWB_X_START = 0x00007FFFL, .OTG_CRC0_WINDOWB_X_END = 0x7FFF0000L, .OTG_CRC0_WINDOWB_Y_START = 0x00007FFFL, .OTG_CRC0_WINDOWB_Y_END = 0x7FFF0000L, .GSL0_READY_SOURCE_SEL = 0x00000007L, .GSL1_READY_SOURCE_SEL = 0x00000070L, .GSL2_READY_SOURCE_SEL = 0x00000700L, .MANUAL_FLOW_CONTROL_SEL = 0x00070000L, .MASTER_UPDATE_LOCK_DB_X = 0x00007FFFL, .MASTER_UPDATE_LOCK_DB_Y = 0x7FFF0000L, .MASTER_UPDATE_LOCK_DB_EN = 0x80000000L, .GLOBAL_UPDATE_LOCK_EN = 0x00000400L, .DIG_UPDATE_LOCATION = 0x000003FFL, .OTG_RANGE_TIMING_DBUF_UPDATE_MODE = 0x03000000L , .OTG_GSL_WINDOW_START_X = 0x00007FFFL, .OTG_GSL_WINDOW_END_X = 0x7FFF0000L, .OTG_GSL_WINDOW_START_Y = 0x00007FFFL, .OTG_GSL_WINDOW_END_Y = 0x7FFF0000L, .OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN = 0x80000000L , .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET = 0x0000FFFFL , .MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET = 0x03FF0000L , .OTG_GSL_MASTER_MODE = 0x00000030L, .OTG_MASTER_UPDATE_LOCK_GSL_EN = 0x80000000L, .OTG_DSC_START_POSITION_X = 0x00007FFFL, .OTG_DSC_START_POSITION_LINE_NUM = 0x03FF0000L, .OTG_CRC_DSC_MODE = 0x00000001L, .OTG_CRC_DATA_STREAM_COMBINE_MODE = 0x00000002L, .OTG_CRC_DATA_STREAM_SPLIT_MODE = 0x00000030L , .OTG_CRC_DATA_FORMAT = 0x00000300L, .OPTC_SEG0_SRC_SEL = 0x00000F00L , .OPTC_SEG1_SRC_SEL = 0x0000F000L, .OPTC_NUM_OF_INPUT_SEGMENT = 0x00000001L, .OPTC_MEM_SEL = 0x0000FFFFL, .OPTC_DATA_FORMAT = 0x00000003L, .OPTC_DSC_MODE = 0x00000030L, .OPTC_DSC_BYTES_PER_PIXEL = 0x7FFFFFFFL, .OPTC_DSC_SLICE_WIDTH = 0x1FFF0000L, .OPTC_SEGMENT_WIDTH = 0x00001FFFL, .OPTC_DWB0_SOURCE_SELECT = 0x00000007L, .OPTC_DWB1_SOURCE_SELECT = 0x00000038L, .MANUAL_FLOW_CONTROL = 0x00000001L | |||
871 | }; | |||
872 | ||||
873 | #define hubp_regs(id)[id] = { .DCHUBP_CNTL = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_CNTL_BASE_IDX + mmHUBPid_DCHUBP_CNTL, .HUBPREQ_DEBUG_DB = DCN_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX + mmHUBPid_HUBPREQ_DEBUG_DB, .HUBPREQ_DEBUG = DCN_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_BASE_IDX + mmHUBPid_HUBPREQ_DEBUG, .DCSURF_ADDR_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX + mmHUBPid_DCSURF_ADDR_CONFIG, .DCSURF_TILING_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_TILING_CONFIG_BASE_IDX + mmHUBPid_DCSURF_TILING_CONFIG, .DCSURF_SURFACE_PITCH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_PITCH, .DCSURF_SURFACE_PITCH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_PITCH_C, .DCSURF_SURFACE_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX + mmHUBPid_DCSURF_SURFACE_CONFIG, .DCSURF_FLIP_CONTROL = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX + mmHUBPREQid_DCSURF_FLIP_CONTROL, .DCSURF_PRI_VIEWPORT_DIMENSION = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX + mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION, .DCSURF_PRI_VIEWPORT_START = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX + mmHUBPid_DCSURF_PRI_VIEWPORT_START, .DCSURF_SEC_VIEWPORT_DIMENSION = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX + mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION, .DCSURF_SEC_VIEWPORT_START = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX + mmHUBPid_DCSURF_SEC_VIEWPORT_START, .DCSURF_PRI_VIEWPORT_DIMENSION_C = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX + mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C, .DCSURF_PRI_VIEWPORT_START_C = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX + mmHUBPid_DCSURF_PRI_VIEWPORT_START_C, .DCSURF_SEC_VIEWPORT_DIMENSION_C = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX + mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C, .DCSURF_SEC_VIEWPORT_START_C = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX + mmHUBPid_DCSURF_SEC_VIEWPORT_START_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, . DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, .DCSURF_SURFACE_INUSE = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_INUSE, .DCSURF_SURFACE_INUSE_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, .DCSURF_SURFACE_INUSE_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_INUSE_C, .DCSURF_SURFACE_INUSE_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, .DCSURF_SURFACE_EARLIEST_INUSE = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, .DCSURF_SURFACE_EARLIEST_INUSE_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, .DCSURF_SURFACE_CONTROL = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_CONTROL, .HUBPRET_CONTROL = DCN_BASE__INST0_SEGmmHUBPRETid_HUBPRET_CONTROL_BASE_IDX + mmHUBPRETid_HUBPRET_CONTROL, .DCN_EXPANSION_MODE = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX + mmHUBPREQid_DCN_EXPANSION_MODE, .DCHUBP_REQ_SIZE_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX + mmHUBPid_DCHUBP_REQ_SIZE_CONFIG, .DCHUBP_REQ_SIZE_CONFIG_C = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX + mmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, .BLANK_OFFSET_0 = DCN_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_0_BASE_IDX + mmHUBPREQid_BLANK_OFFSET_0, .BLANK_OFFSET_1 = DCN_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_1_BASE_IDX + mmHUBPREQid_BLANK_OFFSET_1, .DST_DIMENSIONS = DCN_BASE__INST0_SEGmmHUBPREQid_DST_DIMENSIONS_BASE_IDX + mmHUBPREQid_DST_DIMENSIONS, .DST_AFTER_SCALER = DCN_BASE__INST0_SEGmmHUBPREQid_DST_AFTER_SCALER_BASE_IDX + mmHUBPREQid_DST_AFTER_SCALER, .VBLANK_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_0, .REF_FREQ_TO_PIX_FREQ = DCN_BASE__INST0_SEGmmHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX + mmHUBPREQid_REF_FREQ_TO_PIX_FREQ, .VBLANK_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_1, .VBLANK_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_3, .NOM_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_4_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_4, .NOM_PARAMETERS_5 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_5_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_5, .PER_LINE_DELIVERY_PRE = DCN_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX + mmHUBPREQid_PER_LINE_DELIVERY_PRE, .PER_LINE_DELIVERY = DCN_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_BASE_IDX + mmHUBPREQid_PER_LINE_DELIVERY, .VBLANK_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_2, .VBLANK_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_4, .NOM_PARAMETERS_6 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_6_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_6, .NOM_PARAMETERS_7 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_7_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_7, .DCN_TTU_QOS_WM = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX + mmHUBPREQid_DCN_TTU_QOS_WM, .DCN_GLOBAL_TTU_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX + mmHUBPREQid_DCN_GLOBAL_TTU_CNTL, .DCN_SURF0_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX + mmHUBPREQid_DCN_SURF0_TTU_CNTL0, .DCN_SURF0_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX + mmHUBPREQid_DCN_SURF0_TTU_CNTL1, .DCN_SURF1_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX + mmHUBPREQid_DCN_SURF1_TTU_CNTL0, .DCN_SURF1_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX + mmHUBPREQid_DCN_SURF1_TTU_CNTL1, .DCN_CUR0_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX + mmHUBPREQid_DCN_CUR0_TTU_CNTL0, .DCN_CUR0_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX + mmHUBPREQid_DCN_CUR0_TTU_CNTL1, .HUBP_CLK_CNTL = DCN_BASE__INST0_SEGmmHUBPid_HUBP_CLK_CNTL_BASE_IDX + mmHUBPid_HUBP_CLK_CNTL, .NOM_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_0_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_0, .NOM_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_1_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_1, .NOM_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_2_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_2, .NOM_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_3_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_3, .DCN_VM_MX_L1_TLB_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX + mmHUBPREQid_DCN_VM_MX_L1_TLB_CNTL, .PREFETCH_SETTINGS = DCN_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_BASE_IDX + mmHUBPREQid_PREFETCH_SETTINGS, .PREFETCH_SETTINGS_C = DCN_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX + mmHUBPREQid_PREFETCH_SETTINGS_C, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX + mmHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX + mmHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, .CURSOR_SETTINGS = DCN_BASE__INST0_SEGmmHUBPREQid_CURSOR_SETTINGS_BASE_IDX + mmHUBPREQid_CURSOR_SETTINGS , .CURSOR_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX + mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX + mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX + mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX + mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX + mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX + mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX + mmCURSOR0_id_CURSOR_DST_OFFSET, .DMDATA_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX + mmCURSOR0_id_DMDATA_ADDRESS_HIGH, .DMDATA_ADDRESS_LOW = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX + mmCURSOR0_id_DMDATA_ADDRESS_LOW, .DMDATA_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_CNTL_BASE_IDX + mmCURSOR0_id_DMDATA_CNTL, .DMDATA_SW_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX + mmCURSOR0_id_DMDATA_SW_CNTL, .DMDATA_QOS_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX + mmCURSOR0_id_DMDATA_QOS_CNTL, .DMDATA_SW_DATA = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_DATA_BASE_IDX + mmCURSOR0_id_DMDATA_SW_DATA, .DMDATA_STATUS = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_STATUS_BASE_IDX + mmCURSOR0_id_DMDATA_STATUS, .FLIP_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX + mmHUBPREQid_FLIP_PARAMETERS_0, .FLIP_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_1_BASE_IDX + mmHUBPREQid_FLIP_PARAMETERS_1, .FLIP_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX + mmHUBPREQid_FLIP_PARAMETERS_2, .DCN_CUR1_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR1_TTU_CNTL0_BASE_IDX + mmHUBPREQid_DCN_CUR1_TTU_CNTL0, .DCN_CUR1_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR1_TTU_CNTL1_BASE_IDX + mmHUBPREQid_DCN_CUR1_TTU_CNTL1, .DCSURF_FLIP_CONTROL2 = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX + mmHUBPREQid_DCSURF_FLIP_CONTROL2, .VMID_SETTINGS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_VMID_SETTINGS_0_BASE_IDX + mmHUBPREQid_VMID_SETTINGS_0, .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05c9, .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05ca}\ | |||
874 | [id] = {\ | |||
875 | HUBP_REG_LIST_DCN20(id).DCHUBP_CNTL = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_CNTL_BASE_IDX + mmHUBPid_DCHUBP_CNTL, .HUBPREQ_DEBUG_DB = DCN_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_DB_BASE_IDX + mmHUBPid_HUBPREQ_DEBUG_DB, .HUBPREQ_DEBUG = DCN_BASE__INST0_SEGmmHUBPid_HUBPREQ_DEBUG_BASE_IDX + mmHUBPid_HUBPREQ_DEBUG, .DCSURF_ADDR_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_ADDR_CONFIG_BASE_IDX + mmHUBPid_DCSURF_ADDR_CONFIG, .DCSURF_TILING_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_TILING_CONFIG_BASE_IDX + mmHUBPid_DCSURF_TILING_CONFIG, .DCSURF_SURFACE_PITCH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_PITCH, .DCSURF_SURFACE_PITCH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_PITCH_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_PITCH_C, .DCSURF_SURFACE_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SURFACE_CONFIG_BASE_IDX + mmHUBPid_DCSURF_SURFACE_CONFIG, .DCSURF_FLIP_CONTROL = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL_BASE_IDX + mmHUBPREQid_DCSURF_FLIP_CONTROL, .DCSURF_PRI_VIEWPORT_DIMENSION = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX + mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION, .DCSURF_PRI_VIEWPORT_START = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_BASE_IDX + mmHUBPid_DCSURF_PRI_VIEWPORT_START, .DCSURF_SEC_VIEWPORT_DIMENSION = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX + mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION, .DCSURF_SEC_VIEWPORT_START = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_BASE_IDX + mmHUBPid_DCSURF_SEC_VIEWPORT_START, .DCSURF_PRI_VIEWPORT_DIMENSION_C = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX + mmHUBPid_DCSURF_PRI_VIEWPORT_DIMENSION_C, .DCSURF_PRI_VIEWPORT_START_C = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX + mmHUBPid_DCSURF_PRI_VIEWPORT_START_C, .DCSURF_SEC_VIEWPORT_DIMENSION_C = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX + mmHUBPid_DCSURF_SEC_VIEWPORT_DIMENSION_C, .DCSURF_SEC_VIEWPORT_START_C = DCN_BASE__INST0_SEGmmHUBPid_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX + mmHUBPid_DCSURF_SEC_VIEWPORT_START_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, .DCSURF_SECONDARY_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_SURFACE_ADDRESS_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX + mmHUBPREQid_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, . DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX + mmHUBPREQid_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, .DCSURF_SURFACE_INUSE = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_INUSE, .DCSURF_SURFACE_INUSE_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH, .DCSURF_SURFACE_INUSE_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_INUSE_C, .DCSURF_SURFACE_INUSE_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_INUSE_HIGH_C, .DCSURF_SURFACE_EARLIEST_INUSE = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, .DCSURF_SURFACE_EARLIEST_INUSE_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_C, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, .DCSURF_SURFACE_CONTROL = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_SURFACE_CONTROL_BASE_IDX + mmHUBPREQid_DCSURF_SURFACE_CONTROL, .HUBPRET_CONTROL = DCN_BASE__INST0_SEGmmHUBPRETid_HUBPRET_CONTROL_BASE_IDX + mmHUBPRETid_HUBPRET_CONTROL, .DCN_EXPANSION_MODE = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_EXPANSION_MODE_BASE_IDX + mmHUBPREQid_DCN_EXPANSION_MODE, .DCHUBP_REQ_SIZE_CONFIG = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX + mmHUBPid_DCHUBP_REQ_SIZE_CONFIG, .DCHUBP_REQ_SIZE_CONFIG_C = DCN_BASE__INST0_SEGmmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX + mmHUBPid_DCHUBP_REQ_SIZE_CONFIG_C, .BLANK_OFFSET_0 = DCN_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_0_BASE_IDX + mmHUBPREQid_BLANK_OFFSET_0, .BLANK_OFFSET_1 = DCN_BASE__INST0_SEGmmHUBPREQid_BLANK_OFFSET_1_BASE_IDX + mmHUBPREQid_BLANK_OFFSET_1, .DST_DIMENSIONS = DCN_BASE__INST0_SEGmmHUBPREQid_DST_DIMENSIONS_BASE_IDX + mmHUBPREQid_DST_DIMENSIONS, .DST_AFTER_SCALER = DCN_BASE__INST0_SEGmmHUBPREQid_DST_AFTER_SCALER_BASE_IDX + mmHUBPREQid_DST_AFTER_SCALER, .VBLANK_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_0_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_0, .REF_FREQ_TO_PIX_FREQ = DCN_BASE__INST0_SEGmmHUBPREQid_REF_FREQ_TO_PIX_FREQ_BASE_IDX + mmHUBPREQid_REF_FREQ_TO_PIX_FREQ, .VBLANK_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_1_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_1, .VBLANK_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_3_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_3, .NOM_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_4_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_4, .NOM_PARAMETERS_5 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_5_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_5, .PER_LINE_DELIVERY_PRE = DCN_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_PRE_BASE_IDX + mmHUBPREQid_PER_LINE_DELIVERY_PRE, .PER_LINE_DELIVERY = DCN_BASE__INST0_SEGmmHUBPREQid_PER_LINE_DELIVERY_BASE_IDX + mmHUBPREQid_PER_LINE_DELIVERY, .VBLANK_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_2_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_2, .VBLANK_PARAMETERS_4 = DCN_BASE__INST0_SEGmmHUBPREQid_VBLANK_PARAMETERS_4_BASE_IDX + mmHUBPREQid_VBLANK_PARAMETERS_4, .NOM_PARAMETERS_6 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_6_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_6, .NOM_PARAMETERS_7 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_7_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_7, .DCN_TTU_QOS_WM = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_TTU_QOS_WM_BASE_IDX + mmHUBPREQid_DCN_TTU_QOS_WM, .DCN_GLOBAL_TTU_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_GLOBAL_TTU_CNTL_BASE_IDX + mmHUBPREQid_DCN_GLOBAL_TTU_CNTL, .DCN_SURF0_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL0_BASE_IDX + mmHUBPREQid_DCN_SURF0_TTU_CNTL0, .DCN_SURF0_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF0_TTU_CNTL1_BASE_IDX + mmHUBPREQid_DCN_SURF0_TTU_CNTL1, .DCN_SURF1_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL0_BASE_IDX + mmHUBPREQid_DCN_SURF1_TTU_CNTL0, .DCN_SURF1_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_SURF1_TTU_CNTL1_BASE_IDX + mmHUBPREQid_DCN_SURF1_TTU_CNTL1, .DCN_CUR0_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL0_BASE_IDX + mmHUBPREQid_DCN_CUR0_TTU_CNTL0, .DCN_CUR0_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR0_TTU_CNTL1_BASE_IDX + mmHUBPREQid_DCN_CUR0_TTU_CNTL1, .HUBP_CLK_CNTL = DCN_BASE__INST0_SEGmmHUBPid_HUBP_CLK_CNTL_BASE_IDX + mmHUBPid_HUBP_CLK_CNTL, .NOM_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_0_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_0, .NOM_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_1_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_1, .NOM_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_2_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_2, .NOM_PARAMETERS_3 = DCN_BASE__INST0_SEGmmHUBPREQid_NOM_PARAMETERS_3_BASE_IDX + mmHUBPREQid_NOM_PARAMETERS_3, .DCN_VM_MX_L1_TLB_CNTL = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX + mmHUBPREQid_DCN_VM_MX_L1_TLB_CNTL, .PREFETCH_SETTINGS = DCN_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_BASE_IDX + mmHUBPREQid_PREFETCH_SETTINGS, .PREFETCH_SETTINGS_C = DCN_BASE__INST0_SEGmmHUBPREQid_PREFETCH_SETTINGS_C_BASE_IDX + mmHUBPREQid_PREFETCH_SETTINGS_C, .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX + mmHUBPREQid_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX + mmHUBPREQid_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, .CURSOR_SETTINGS = DCN_BASE__INST0_SEGmmHUBPREQid_CURSOR_SETTINGS_BASE_IDX + mmHUBPREQid_CURSOR_SETTINGS , .CURSOR_SURFACE_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX + mmCURSOR0_id_CURSOR_SURFACE_ADDRESS_HIGH, .CURSOR_SURFACE_ADDRESS = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SURFACE_ADDRESS_BASE_IDX + mmCURSOR0_id_CURSOR_SURFACE_ADDRESS, .CURSOR_SIZE = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_SIZE_BASE_IDX + mmCURSOR0_id_CURSOR_SIZE, .CURSOR_CONTROL = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_CONTROL_BASE_IDX + mmCURSOR0_id_CURSOR_CONTROL, .CURSOR_POSITION = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_POSITION_BASE_IDX + mmCURSOR0_id_CURSOR_POSITION, .CURSOR_HOT_SPOT = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_HOT_SPOT_BASE_IDX + mmCURSOR0_id_CURSOR_HOT_SPOT, .CURSOR_DST_OFFSET = DCN_BASE__INST0_SEGmmCURSOR0_id_CURSOR_DST_OFFSET_BASE_IDX + mmCURSOR0_id_CURSOR_DST_OFFSET, .DMDATA_ADDRESS_HIGH = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_HIGH_BASE_IDX + mmCURSOR0_id_DMDATA_ADDRESS_HIGH, .DMDATA_ADDRESS_LOW = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_ADDRESS_LOW_BASE_IDX + mmCURSOR0_id_DMDATA_ADDRESS_LOW, .DMDATA_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_CNTL_BASE_IDX + mmCURSOR0_id_DMDATA_CNTL, .DMDATA_SW_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_CNTL_BASE_IDX + mmCURSOR0_id_DMDATA_SW_CNTL, .DMDATA_QOS_CNTL = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_QOS_CNTL_BASE_IDX + mmCURSOR0_id_DMDATA_QOS_CNTL, .DMDATA_SW_DATA = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_SW_DATA_BASE_IDX + mmCURSOR0_id_DMDATA_SW_DATA, .DMDATA_STATUS = DCN_BASE__INST0_SEGmmCURSOR0_id_DMDATA_STATUS_BASE_IDX + mmCURSOR0_id_DMDATA_STATUS, .FLIP_PARAMETERS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_0_BASE_IDX + mmHUBPREQid_FLIP_PARAMETERS_0, .FLIP_PARAMETERS_1 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_1_BASE_IDX + mmHUBPREQid_FLIP_PARAMETERS_1, .FLIP_PARAMETERS_2 = DCN_BASE__INST0_SEGmmHUBPREQid_FLIP_PARAMETERS_2_BASE_IDX + mmHUBPREQid_FLIP_PARAMETERS_2, .DCN_CUR1_TTU_CNTL0 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR1_TTU_CNTL0_BASE_IDX + mmHUBPREQid_DCN_CUR1_TTU_CNTL0, .DCN_CUR1_TTU_CNTL1 = DCN_BASE__INST0_SEGmmHUBPREQid_DCN_CUR1_TTU_CNTL1_BASE_IDX + mmHUBPREQid_DCN_CUR1_TTU_CNTL1, .DCSURF_FLIP_CONTROL2 = DCN_BASE__INST0_SEGmmHUBPREQid_DCSURF_FLIP_CONTROL2_BASE_IDX + mmHUBPREQid_DCSURF_FLIP_CONTROL2, .VMID_SETTINGS_0 = DCN_BASE__INST0_SEGmmHUBPREQid_VMID_SETTINGS_0_BASE_IDX + mmHUBPREQid_VMID_SETTINGS_0, .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05c9, .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05ca\ | |||
876 | } | |||
877 | ||||
878 | static const struct dcn_hubp2_registers hubp_regs[] = { | |||
879 | hubp_regs(0)[0] = { .DCHUBP_CNTL = 0x000034C0 + 0x05f3, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x05f6, .HUBPREQ_DEBUG = 0x000034C0 + 0x05f7, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x05e6, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x05e7, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x0607 , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x0608, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x05e5, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x061b , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x05ea, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x05e9, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x05ee, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x05ed, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x05ec, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x05eb, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x05f0, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x05ef , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x060b, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x060a, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x060f, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x060e, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0613, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x0612, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0617, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x0616, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x060d, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x060c , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0611 , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0610, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0615 , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0614 , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0619, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0618, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x0621, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x0622, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x0623, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0624, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0625, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x0626, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x0627, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x0628, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x061a, .HUBPRET_CONTROL = 0x000034C0 + 0x066c, .DCN_EXPANSION_MODE = 0x000034C0 + 0x062c , .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x05f1, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x05f2, .BLANK_OFFSET_0 = 0x000034C0 + 0x0646 , .BLANK_OFFSET_1 = 0x000034C0 + 0x0647, .DST_DIMENSIONS = 0x000034C0 + 0x0648, .DST_AFTER_SCALER = 0x000034C0 + 0x0649, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x064c, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x065f , .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x064d, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x064f, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0658 , .NOM_PARAMETERS_5 = 0x000034C0 + 0x0659, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x065c, .PER_LINE_DELIVERY = 0x000034C0 + 0x065d , .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x064e, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x0650, .NOM_PARAMETERS_6 = 0x000034C0 + 0x065a , .NOM_PARAMETERS_7 = 0x000034C0 + 0x065b, .DCN_TTU_QOS_WM = 0x000034C0 + 0x062d, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x062e, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x062f, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x0630 , .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x0631, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x0632, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x0633 , .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x0634, .HUBP_CLK_CNTL = 0x000034C0 + 0x05f4, .NOM_PARAMETERS_0 = 0x000034C0 + 0x0654 , .NOM_PARAMETERS_1 = 0x000034C0 + 0x0655, .NOM_PARAMETERS_2 = 0x000034C0 + 0x0656, .NOM_PARAMETERS_3 = 0x000034C0 + 0x0657 , .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x0645, .PREFETCH_SETTINGS = 0x000034C0 + 0x064a, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x064b , .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x0637, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x0638, .CURSOR_SETTINGS = 0x000034C0 + 0x065e , .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x067a, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0679, .CURSOR_SIZE = 0x000034C0 + 0x067b, . CURSOR_CONTROL = 0x000034C0 + 0x0678, .CURSOR_POSITION = 0x000034C0 + 0x067c, .CURSOR_HOT_SPOT = 0x000034C0 + 0x067d, .CURSOR_DST_OFFSET = 0x000034C0 + 0x067f, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0682 , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0683, .DMDATA_CNTL = 0x000034C0 + 0x0684, .DMDATA_SW_CNTL = 0x000034C0 + 0x0687, .DMDATA_QOS_CNTL = 0x000034C0 + 0x0685, .DMDATA_SW_DATA = 0x000034C0 + 0x0688 , .DMDATA_STATUS = 0x000034C0 + 0x0686, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x0651, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x0652, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x0653, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x0635 , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x0636, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x061c, .VMID_SETTINGS_0 = 0x000034C0 + 0x0609 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05c9 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05ca }, | |||
880 | hubp_regs(1)[1] = { .DCHUBP_CNTL = 0x000034C0 + 0x06cf, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x06d2, .HUBPREQ_DEBUG = 0x000034C0 + 0x06d3, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x06c2, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x06c3, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x06e3 , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x06e4, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x06c1, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x06f7 , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x06c6, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x06c5, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x06ca, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x06c9, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x06c8, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x06c7, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x06cc, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x06cb , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06e7, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x06e6, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06eb, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x06ea, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06ef, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x06ee, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x06f3, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x06f2, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06e9, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x06e8 , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06ed , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x06ec, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06f1 , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x06f0 , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x06f5, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x06f4, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x06fd, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x06fe, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x06ff, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0700, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0701, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x0702, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x0703, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x0704, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x06f6, .HUBPRET_CONTROL = 0x000034C0 + 0x0748, .DCN_EXPANSION_MODE = 0x000034C0 + 0x0708 , .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x06cd, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x06ce, .BLANK_OFFSET_0 = 0x000034C0 + 0x0722 , .BLANK_OFFSET_1 = 0x000034C0 + 0x0723, .DST_DIMENSIONS = 0x000034C0 + 0x0724, .DST_AFTER_SCALER = 0x000034C0 + 0x0725, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x0728, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x073b , .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0729, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x072b, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0734 , .NOM_PARAMETERS_5 = 0x000034C0 + 0x0735, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x0738, .PER_LINE_DELIVERY = 0x000034C0 + 0x0739 , .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x072a, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x072c, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0736 , .NOM_PARAMETERS_7 = 0x000034C0 + 0x0737, .DCN_TTU_QOS_WM = 0x000034C0 + 0x0709, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x070a, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x070b, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x070c , .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x070d, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x070e, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x070f , .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x0710, .HUBP_CLK_CNTL = 0x000034C0 + 0x06d0, .NOM_PARAMETERS_0 = 0x000034C0 + 0x0730 , .NOM_PARAMETERS_1 = 0x000034C0 + 0x0731, .NOM_PARAMETERS_2 = 0x000034C0 + 0x0732, .NOM_PARAMETERS_3 = 0x000034C0 + 0x0733 , .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x0721, .PREFETCH_SETTINGS = 0x000034C0 + 0x0726, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0727 , .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x0713, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x0714, .CURSOR_SETTINGS = 0x000034C0 + 0x073a , .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0756, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0755, .CURSOR_SIZE = 0x000034C0 + 0x0757, . CURSOR_CONTROL = 0x000034C0 + 0x0754, .CURSOR_POSITION = 0x000034C0 + 0x0758, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0759, .CURSOR_DST_OFFSET = 0x000034C0 + 0x075b, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x075e , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x075f, .DMDATA_CNTL = 0x000034C0 + 0x0760, .DMDATA_SW_CNTL = 0x000034C0 + 0x0763, .DMDATA_QOS_CNTL = 0x000034C0 + 0x0761, .DMDATA_SW_DATA = 0x000034C0 + 0x0764 , .DMDATA_STATUS = 0x000034C0 + 0x0762, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x072d, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x072e, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x072f, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x0711 , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x0712, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x06f8, .VMID_SETTINGS_0 = 0x000034C0 + 0x06e5 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05c9 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05ca }, | |||
881 | hubp_regs(2)[2] = { .DCHUBP_CNTL = 0x000034C0 + 0x07ab, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x07ae, .HUBPREQ_DEBUG = 0x000034C0 + 0x07af, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x079e, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x079f, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x07bf , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x07c0, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x079d, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x07d3 , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x07a2, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x07a1, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x07a6, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x07a5, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x07a4, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x07a3, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x07a8, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x07a7 , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07c3, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x07c2, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07c7, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x07c6, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07cb, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x07ca, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x07cf, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x07ce, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07c5, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x07c4 , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07c9 , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x07c8, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07cd , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x07cc , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x07d1, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x07d0, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x07d9, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x07da, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x07db, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x07dc, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x07dd, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x07de, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x07df, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x07e0, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x07d2, .HUBPRET_CONTROL = 0x000034C0 + 0x0824, .DCN_EXPANSION_MODE = 0x000034C0 + 0x07e4 , .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x07a9, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x07aa, .BLANK_OFFSET_0 = 0x000034C0 + 0x07fe , .BLANK_OFFSET_1 = 0x000034C0 + 0x07ff, .DST_DIMENSIONS = 0x000034C0 + 0x0800, .DST_AFTER_SCALER = 0x000034C0 + 0x0801, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x0804, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x0817 , .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0805, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x0807, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0810 , .NOM_PARAMETERS_5 = 0x000034C0 + 0x0811, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x0814, .PER_LINE_DELIVERY = 0x000034C0 + 0x0815 , .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x0806, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x0808, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0812 , .NOM_PARAMETERS_7 = 0x000034C0 + 0x0813, .DCN_TTU_QOS_WM = 0x000034C0 + 0x07e5, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x07e6, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x07e7, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x07e8 , .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x07e9, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x07ea, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x07eb , .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x07ec, .HUBP_CLK_CNTL = 0x000034C0 + 0x07ac, .NOM_PARAMETERS_0 = 0x000034C0 + 0x080c , .NOM_PARAMETERS_1 = 0x000034C0 + 0x080d, .NOM_PARAMETERS_2 = 0x000034C0 + 0x080e, .NOM_PARAMETERS_3 = 0x000034C0 + 0x080f , .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x07fd, .PREFETCH_SETTINGS = 0x000034C0 + 0x0802, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0803 , .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x07ef, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x07f0, .CURSOR_SETTINGS = 0x000034C0 + 0x0816 , .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0832, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0831, .CURSOR_SIZE = 0x000034C0 + 0x0833, . CURSOR_CONTROL = 0x000034C0 + 0x0830, .CURSOR_POSITION = 0x000034C0 + 0x0834, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0835, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0837, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x083a , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x083b, .DMDATA_CNTL = 0x000034C0 + 0x083c, .DMDATA_SW_CNTL = 0x000034C0 + 0x083f, .DMDATA_QOS_CNTL = 0x000034C0 + 0x083d, .DMDATA_SW_DATA = 0x000034C0 + 0x0840 , .DMDATA_STATUS = 0x000034C0 + 0x083e, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x0809, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x080a, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x080b, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x07ed , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x07ee, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x07d4, .VMID_SETTINGS_0 = 0x000034C0 + 0x07c1 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05c9 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05ca }, | |||
882 | hubp_regs(3)[3] = { .DCHUBP_CNTL = 0x000034C0 + 0x0887, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x088a, .HUBPREQ_DEBUG = 0x000034C0 + 0x088b, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x087a, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x087b, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x089b , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x089c, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x0879, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x08af , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x087e, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x087d, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x0882, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x0881, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0880, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x087f, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0884, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x0883 , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x089f, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x089e, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x08a3, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x08a2, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x08a7, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x08a6, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x08ab, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x08aa, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a1, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a0 , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a5 , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a4, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08a9 , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x08a8 , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x08ad, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x08ac, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x08b5, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x08b6, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x08b7, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x08b8, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x08b9, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x08ba, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x08bb, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x08bc, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x08ae, .HUBPRET_CONTROL = 0x000034C0 + 0x0900, .DCN_EXPANSION_MODE = 0x000034C0 + 0x08c0 , .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x0885, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x0886, .BLANK_OFFSET_0 = 0x000034C0 + 0x08da , .BLANK_OFFSET_1 = 0x000034C0 + 0x08db, .DST_DIMENSIONS = 0x000034C0 + 0x08dc, .DST_AFTER_SCALER = 0x000034C0 + 0x08dd, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x08e0, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x08f3 , .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x08e1, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x08e3, .NOM_PARAMETERS_4 = 0x000034C0 + 0x08ec , .NOM_PARAMETERS_5 = 0x000034C0 + 0x08ed, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x08f0, .PER_LINE_DELIVERY = 0x000034C0 + 0x08f1 , .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x08e2, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x08e4, .NOM_PARAMETERS_6 = 0x000034C0 + 0x08ee , .NOM_PARAMETERS_7 = 0x000034C0 + 0x08ef, .DCN_TTU_QOS_WM = 0x000034C0 + 0x08c1, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x08c2, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x08c3, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x08c4 , .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x08c5, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x08c6, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x08c7 , .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x08c8, .HUBP_CLK_CNTL = 0x000034C0 + 0x0888, .NOM_PARAMETERS_0 = 0x000034C0 + 0x08e8 , .NOM_PARAMETERS_1 = 0x000034C0 + 0x08e9, .NOM_PARAMETERS_2 = 0x000034C0 + 0x08ea, .NOM_PARAMETERS_3 = 0x000034C0 + 0x08eb , .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x08d9, .PREFETCH_SETTINGS = 0x000034C0 + 0x08de, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x08df , .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x08cb, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x08cc, .CURSOR_SETTINGS = 0x000034C0 + 0x08f2 , .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x090e, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x090d, .CURSOR_SIZE = 0x000034C0 + 0x090f, . CURSOR_CONTROL = 0x000034C0 + 0x090c, .CURSOR_POSITION = 0x000034C0 + 0x0910, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0911, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0913, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0916 , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0917, .DMDATA_CNTL = 0x000034C0 + 0x0918, .DMDATA_SW_CNTL = 0x000034C0 + 0x091b, .DMDATA_QOS_CNTL = 0x000034C0 + 0x0919, .DMDATA_SW_DATA = 0x000034C0 + 0x091c , .DMDATA_STATUS = 0x000034C0 + 0x091a, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x08e5, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x08e6, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x08e7, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x08c9 , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x08ca, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x08b0, .VMID_SETTINGS_0 = 0x000034C0 + 0x089d , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05c9 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05ca }, | |||
883 | hubp_regs(4)[4] = { .DCHUBP_CNTL = 0x000034C0 + 0x0963, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x0966, .HUBPREQ_DEBUG = 0x000034C0 + 0x0967, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x0956, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x0957, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x0977 , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x0978, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x0955, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x098b , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x095a, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x0959, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x095e, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x095d, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x095c, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x095b, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0960, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x095f , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x097b, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x097a, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x097f, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x097e, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0983, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x0982, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0987, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x0986, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x097d, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x097c , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0981 , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0980, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0985 , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0984 , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0989, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0988, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x0991, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x0992, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x0993, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0994, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0995, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x0996, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x0997, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x0998, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x098a, .HUBPRET_CONTROL = 0x000034C0 + 0x09dc, .DCN_EXPANSION_MODE = 0x000034C0 + 0x099c , .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x0961, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x0962, .BLANK_OFFSET_0 = 0x000034C0 + 0x09b6 , .BLANK_OFFSET_1 = 0x000034C0 + 0x09b7, .DST_DIMENSIONS = 0x000034C0 + 0x09b8, .DST_AFTER_SCALER = 0x000034C0 + 0x09b9, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x09bc, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x09cf , .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x09bd, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x09bf, .NOM_PARAMETERS_4 = 0x000034C0 + 0x09c8 , .NOM_PARAMETERS_5 = 0x000034C0 + 0x09c9, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x09cc, .PER_LINE_DELIVERY = 0x000034C0 + 0x09cd , .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x09be, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x09c0, .NOM_PARAMETERS_6 = 0x000034C0 + 0x09ca , .NOM_PARAMETERS_7 = 0x000034C0 + 0x09cb, .DCN_TTU_QOS_WM = 0x000034C0 + 0x099d, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x099e, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x099f, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x09a0 , .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x09a1, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x09a2, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x09a3 , .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x09a4, .HUBP_CLK_CNTL = 0x000034C0 + 0x0964, .NOM_PARAMETERS_0 = 0x000034C0 + 0x09c4 , .NOM_PARAMETERS_1 = 0x000034C0 + 0x09c5, .NOM_PARAMETERS_2 = 0x000034C0 + 0x09c6, .NOM_PARAMETERS_3 = 0x000034C0 + 0x09c7 , .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x09b5, .PREFETCH_SETTINGS = 0x000034C0 + 0x09ba, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x09bb , .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x09a7, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x09a8, .CURSOR_SETTINGS = 0x000034C0 + 0x09ce , .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x09ea, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x09e9, .CURSOR_SIZE = 0x000034C0 + 0x09eb, . CURSOR_CONTROL = 0x000034C0 + 0x09e8, .CURSOR_POSITION = 0x000034C0 + 0x09ec, .CURSOR_HOT_SPOT = 0x000034C0 + 0x09ed, .CURSOR_DST_OFFSET = 0x000034C0 + 0x09ef, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x09f2 , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x09f3, .DMDATA_CNTL = 0x000034C0 + 0x09f4, .DMDATA_SW_CNTL = 0x000034C0 + 0x09f7, .DMDATA_QOS_CNTL = 0x000034C0 + 0x09f5, .DMDATA_SW_DATA = 0x000034C0 + 0x09f8 , .DMDATA_STATUS = 0x000034C0 + 0x09f6, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x09c1, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x09c2, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x09c3, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x09a5 , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x09a6, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x098c, .VMID_SETTINGS_0 = 0x000034C0 + 0x0979 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05c9 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05ca }, | |||
884 | hubp_regs(5)[5] = { .DCHUBP_CNTL = 0x000034C0 + 0x0a3f, .HUBPREQ_DEBUG_DB = 0x000034C0 + 0x0a42, .HUBPREQ_DEBUG = 0x000034C0 + 0x0a43, .DCSURF_ADDR_CONFIG = 0x000034C0 + 0x0a32, .DCSURF_TILING_CONFIG = 0x000034C0 + 0x0a33, .DCSURF_SURFACE_PITCH = 0x000034C0 + 0x0a53 , .DCSURF_SURFACE_PITCH_C = 0x000034C0 + 0x0a54, .DCSURF_SURFACE_CONFIG = 0x000034C0 + 0x0a31, .DCSURF_FLIP_CONTROL = 0x000034C0 + 0x0a67 , .DCSURF_PRI_VIEWPORT_DIMENSION = 0x000034C0 + 0x0a36, .DCSURF_PRI_VIEWPORT_START = 0x000034C0 + 0x0a35, .DCSURF_SEC_VIEWPORT_DIMENSION = 0x000034C0 + 0x0a3a, .DCSURF_SEC_VIEWPORT_START = 0x000034C0 + 0x0a39, . DCSURF_PRI_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0a38, .DCSURF_PRI_VIEWPORT_START_C = 0x000034C0 + 0x0a37, .DCSURF_SEC_VIEWPORT_DIMENSION_C = 0x000034C0 + 0x0a3c, .DCSURF_SEC_VIEWPORT_START_C = 0x000034C0 + 0x0a3b , .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0a57, .DCSURF_PRIMARY_SURFACE_ADDRESS = 0x000034C0 + 0x0a56, .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0a5b, .DCSURF_SECONDARY_SURFACE_ADDRESS = 0x000034C0 + 0x0a5a, .DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0a5f, .DCSURF_PRIMARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x0a5e, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0a63, .DCSURF_SECONDARY_META_SURFACE_ADDRESS = 0x000034C0 + 0x0a62, .DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0a59, .DCSURF_PRIMARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0a58 , .DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0a5d , .DCSURF_SECONDARY_SURFACE_ADDRESS_C = 0x000034C0 + 0x0a5c, . DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0a61 , .DCSURF_PRIMARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0a60 , .DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x000034C0 + 0x0a65, .DCSURF_SECONDARY_META_SURFACE_ADDRESS_C = 0x000034C0 + 0x0a64, .DCSURF_SURFACE_INUSE = 0x000034C0 + 0x0a6d, .DCSURF_SURFACE_INUSE_HIGH = 0x000034C0 + 0x0a6e, .DCSURF_SURFACE_INUSE_C = 0x000034C0 + 0x0a6f, .DCSURF_SURFACE_INUSE_HIGH_C = 0x000034C0 + 0x0a70, . DCSURF_SURFACE_EARLIEST_INUSE = 0x000034C0 + 0x0a71, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH = 0x000034C0 + 0x0a72, .DCSURF_SURFACE_EARLIEST_INUSE_C = 0x000034C0 + 0x0a73, .DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C = 0x000034C0 + 0x0a74, .DCSURF_SURFACE_CONTROL = 0x000034C0 + 0x0a66, .HUBPRET_CONTROL = 0x000034C0 + 0x0ab8, .DCN_EXPANSION_MODE = 0x000034C0 + 0x0a78 , .DCHUBP_REQ_SIZE_CONFIG = 0x000034C0 + 0x0a3d, .DCHUBP_REQ_SIZE_CONFIG_C = 0x000034C0 + 0x0a3e, .BLANK_OFFSET_0 = 0x000034C0 + 0x0a92 , .BLANK_OFFSET_1 = 0x000034C0 + 0x0a93, .DST_DIMENSIONS = 0x000034C0 + 0x0a94, .DST_AFTER_SCALER = 0x000034C0 + 0x0a95, .VBLANK_PARAMETERS_0 = 0x000034C0 + 0x0a98, .REF_FREQ_TO_PIX_FREQ = 0x000034C0 + 0x0aab , .VBLANK_PARAMETERS_1 = 0x000034C0 + 0x0a99, .VBLANK_PARAMETERS_3 = 0x000034C0 + 0x0a9b, .NOM_PARAMETERS_4 = 0x000034C0 + 0x0aa4 , .NOM_PARAMETERS_5 = 0x000034C0 + 0x0aa5, .PER_LINE_DELIVERY_PRE = 0x000034C0 + 0x0aa8, .PER_LINE_DELIVERY = 0x000034C0 + 0x0aa9 , .VBLANK_PARAMETERS_2 = 0x000034C0 + 0x0a9a, .VBLANK_PARAMETERS_4 = 0x000034C0 + 0x0a9c, .NOM_PARAMETERS_6 = 0x000034C0 + 0x0aa6 , .NOM_PARAMETERS_7 = 0x000034C0 + 0x0aa7, .DCN_TTU_QOS_WM = 0x000034C0 + 0x0a79, .DCN_GLOBAL_TTU_CNTL = 0x000034C0 + 0x0a7a, .DCN_SURF0_TTU_CNTL0 = 0x000034C0 + 0x0a7b, .DCN_SURF0_TTU_CNTL1 = 0x000034C0 + 0x0a7c , .DCN_SURF1_TTU_CNTL0 = 0x000034C0 + 0x0a7d, .DCN_SURF1_TTU_CNTL1 = 0x000034C0 + 0x0a7e, .DCN_CUR0_TTU_CNTL0 = 0x000034C0 + 0x0a7f , .DCN_CUR0_TTU_CNTL1 = 0x000034C0 + 0x0a80, .HUBP_CLK_CNTL = 0x000034C0 + 0x0a40, .NOM_PARAMETERS_0 = 0x000034C0 + 0x0aa0 , .NOM_PARAMETERS_1 = 0x000034C0 + 0x0aa1, .NOM_PARAMETERS_2 = 0x000034C0 + 0x0aa2, .NOM_PARAMETERS_3 = 0x000034C0 + 0x0aa3 , .DCN_VM_MX_L1_TLB_CNTL = 0x000034C0 + 0x0a91, .PREFETCH_SETTINGS = 0x000034C0 + 0x0a96, .PREFETCH_SETTINGS_C = 0x000034C0 + 0x0a97 , .DCN_VM_SYSTEM_APERTURE_LOW_ADDR = 0x000034C0 + 0x0a83, .DCN_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x000034C0 + 0x0a84, .CURSOR_SETTINGS = 0x000034C0 + 0x0aaa , .CURSOR_SURFACE_ADDRESS_HIGH = 0x000034C0 + 0x0ac6, .CURSOR_SURFACE_ADDRESS = 0x000034C0 + 0x0ac5, .CURSOR_SIZE = 0x000034C0 + 0x0ac7, . CURSOR_CONTROL = 0x000034C0 + 0x0ac4, .CURSOR_POSITION = 0x000034C0 + 0x0ac8, .CURSOR_HOT_SPOT = 0x000034C0 + 0x0ac9, .CURSOR_DST_OFFSET = 0x000034C0 + 0x0acb, .DMDATA_ADDRESS_HIGH = 0x000034C0 + 0x0ace , .DMDATA_ADDRESS_LOW = 0x000034C0 + 0x0acf, .DMDATA_CNTL = 0x000034C0 + 0x0ad0, .DMDATA_SW_CNTL = 0x000034C0 + 0x0ad3, .DMDATA_QOS_CNTL = 0x000034C0 + 0x0ad1, .DMDATA_SW_DATA = 0x000034C0 + 0x0ad4 , .DMDATA_STATUS = 0x000034C0 + 0x0ad2, .FLIP_PARAMETERS_0 = 0x000034C0 + 0x0a9d, .FLIP_PARAMETERS_1 = 0x000034C0 + 0x0a9e, .FLIP_PARAMETERS_2 = 0x000034C0 + 0x0a9f, .DCN_CUR1_TTU_CNTL0 = 0x000034C0 + 0x0a81 , .DCN_CUR1_TTU_CNTL1 = 0x000034C0 + 0x0a82, .DCSURF_FLIP_CONTROL2 = 0x000034C0 + 0x0a68, .VMID_SETTINGS_0 = 0x000034C0 + 0x0a55 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05c9 , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05ca } | |||
885 | }; | |||
886 | ||||
887 | static const struct dcn_hubp2_shift hubp_shift = { | |||
888 | HUBP_MASK_SH_LIST_DCN20(__SHIFT).HUBP_BLANK_EN = 0x0, .HUBP_TTU_DISABLE = 0xc, .HUBP_UNDERFLOW_STATUS = 0x1c, .HUBP_UNDERFLOW_CLEAR = 0x1f, .HUBP_NO_OUTSTANDING_REQ = 0x1, .HUBP_VTG_SEL = 0x4, .HUBP_DISABLE = 0x2, .NUM_PIPES = 0x0, .NUM_BANKS = 0x3, .PIPE_INTERLEAVE = 0x6, .NUM_SE = 0x8 , .NUM_RB_PER_SE = 0xa, .MAX_COMPRESSED_FRAGS = 0xc, .SW_MODE = 0x0, .META_LINEAR = 0x9, .PIPE_ALIGNED = 0xb, .PITCH = 0x0 , .META_PITCH = 0x10, .PITCH_C = 0x0, .META_PITCH_C = 0x10, . SURFACE_PIXEL_FORMAT = 0x0, .SURFACE_FLIP_TYPE = 0x1, .SURFACE_FLIP_MODE_FOR_STEREOSYNC = 0xc, .SURFACE_FLIP_IN_STEREOSYNC = 0x10, .SURFACE_FLIP_PENDING = 0x8, .SURFACE_UPDATE_LOCK = 0x0, .PRI_VIEWPORT_WIDTH = 0x0 , .PRI_VIEWPORT_HEIGHT = 0x10, .PRI_VIEWPORT_X_START = 0x0, . PRI_VIEWPORT_Y_START = 0x10, .SEC_VIEWPORT_WIDTH = 0x0, .SEC_VIEWPORT_HEIGHT = 0x10, .SEC_VIEWPORT_X_START = 0x0, .SEC_VIEWPORT_Y_START = 0x10, .PRI_VIEWPORT_WIDTH_C = 0x0, .PRI_VIEWPORT_HEIGHT_C = 0x10 , .PRI_VIEWPORT_X_START_C = 0x0, .PRI_VIEWPORT_Y_START_C = 0x10 , .SEC_VIEWPORT_WIDTH_C = 0x0, .SEC_VIEWPORT_HEIGHT_C = 0x10, .SEC_VIEWPORT_X_START_C = 0x0, .SEC_VIEWPORT_Y_START_C = 0x10 , .PRIMARY_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_SURFACE_ADDRESS = 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_SURFACE_ADDRESS = 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x0, .PRIMARY_META_SURFACE_ADDRESS = 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0, .SECONDARY_META_SURFACE_ADDRESS = 0x0, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_SURFACE_ADDRESS_C = 0x0, .SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_SURFACE_ADDRESS_C = 0x0, .PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .PRIMARY_META_SURFACE_ADDRESS_C = 0x0, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0, .SECONDARY_META_SURFACE_ADDRESS_C = 0x0, .SURFACE_INUSE_ADDRESS = 0x0, .SURFACE_INUSE_ADDRESS_HIGH = 0x0, .SURFACE_INUSE_ADDRESS_C = 0x0, .SURFACE_INUSE_ADDRESS_HIGH_C = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0x0, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C = 0x0, .PRIMARY_SURFACE_TMZ = 0x0, .PRIMARY_SURFACE_TMZ_C = 0x4 , .PRIMARY_META_SURFACE_TMZ = 0x10, .PRIMARY_META_SURFACE_TMZ_C = 0x11, .PRIMARY_SURFACE_DCC_EN = 0x1, .PRIMARY_SURFACE_DCC_IND_64B_BLK = 0x2, .SECONDARY_SURFACE_TMZ = 0x8, .SECONDARY_SURFACE_TMZ_C = 0xc, .SECONDARY_META_SURFACE_TMZ = 0x12, .SECONDARY_META_SURFACE_TMZ_C = 0x13, .SECONDARY_SURFACE_DCC_EN = 0x9, .SECONDARY_SURFACE_DCC_IND_64B_BLK = 0xa, .DET_BUF_PLANE1_BASE_ADDRESS = 0x0, .CROSSBAR_SRC_CB_B = 0x14, .CROSSBAR_SRC_CR_R = 0x16, .DRQ_EXPANSION_MODE = 0x0 , .PRQ_EXPANSION_MODE = 0x6, .MRQ_EXPANSION_MODE = 0x4, .CRQ_EXPANSION_MODE = 0x2, .CHUNK_SIZE = 0x8, .MIN_CHUNK_SIZE = 0xb, .META_CHUNK_SIZE = 0x10, .MIN_META_CHUNK_SIZE = 0x12, .DPTE_GROUP_SIZE = 0x14 , .SWATH_HEIGHT = 0x0, .PTE_ROW_HEIGHT_LINEAR = 0x4, .CHUNK_SIZE_C = 0x8, .MIN_CHUNK_SIZE_C = 0xb, .META_CHUNK_SIZE_C = 0x10, . MIN_META_CHUNK_SIZE_C = 0x12, .DPTE_GROUP_SIZE_C = 0x14, .SWATH_HEIGHT_C = 0x0, .PTE_ROW_HEIGHT_LINEAR_C = 0x4, .REFCYC_H_BLANK_END = 0x0, .DLG_V_BLANK_END = 0x10, .MIN_DST_Y_NEXT_START = 0x0, . REFCYC_PER_HTOTAL = 0x0, .REFCYC_X_AFTER_SCALER = 0x0, .DST_Y_AFTER_SCALER = 0x10, .DST_Y_PER_VM_VBLANK = 0x0, .DST_Y_PER_ROW_VBLANK = 0x8 , .REF_FREQ_TO_PIX_FREQ = 0x0, .REFCYC_PER_PTE_GROUP_VBLANK_L = 0x0, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x0, .DST_Y_PER_META_ROW_NOM_L = 0x0, .REFCYC_PER_META_CHUNK_NOM_L = 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_L = 0x0, .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x10, .REFCYC_PER_LINE_DELIVERY_L = 0x0, .REFCYC_PER_LINE_DELIVERY_C = 0x10, .REFCYC_PER_PTE_GROUP_VBLANK_C = 0x0, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x0, .DST_Y_PER_META_ROW_NOM_C = 0x0, .REFCYC_PER_META_CHUNK_NOM_C = 0x0, .QoS_LEVEL_LOW_WM = 0x0, .QoS_LEVEL_HIGH_WM = 0x10, .MIN_TTU_VBLANK = 0x0, .QoS_LEVEL_FLIP = 0x1c, .REFCYC_PER_REQ_DELIVERY = 0x0, .QoS_LEVEL_FIXED = 0x18 , .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE = 0x0 , .HUBP_CLOCK_ENABLE = 0x0, .DST_Y_PER_PTE_ROW_NOM_L = 0x0, . REFCYC_PER_PTE_GROUP_NOM_L = 0x0, .DST_Y_PER_PTE_ROW_NOM_C = 0x0 , .REFCYC_PER_PTE_GROUP_NOM_C = 0x0, .ENABLE_L1_TLB = 0x0, .SYSTEM_ACCESS_MODE = 0x3, .REFCYC_PER_REQ_DELIVERY = 0x0, .QoS_LEVEL_FIXED = 0x18 , .QoS_RAMP_DISABLE = 0x1c, .REFCYC_PER_REQ_DELIVERY_PRE = 0x0 , .ROTATION_ANGLE = 0x8, .H_MIRROR_EN = 0xa, .DST_Y_PREFETCH = 0x18, .VRATIO_PREFETCH = 0x0, .VRATIO_PREFETCH_C = 0x0, .MC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x0, .MC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x0, .CURSOR0_DST_Y_OFFSET = 0x0, .CURSOR0_CHUNK_HDL_ADJUST = 0x8, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0, .CURSOR_SURFACE_ADDRESS = 0x0, .CURSOR_WIDTH = 0x10, . CURSOR_HEIGHT = 0x0, .CURSOR_MODE = 0x8, .CURSOR_2X_MAGNIFY = 0x4, .CURSOR_PITCH = 0x10, .CURSOR_LINES_PER_CHUNK = 0x18, . CURSOR_ENABLE = 0x0, .CURSOR_X_POSITION = 0x10, .CURSOR_Y_POSITION = 0x0, .CURSOR_HOT_SPOT_X = 0x10, .CURSOR_HOT_SPOT_Y = 0x0, . CURSOR_DST_X_OFFSET = 0x0, .DMDATA_ADDRESS_HIGH = 0x0, .DMDATA_MODE = 0x2, .DMDATA_UPDATED = 0x0, .DMDATA_REPEAT = 0x1, .DMDATA_SIZE = 0x10, .DMDATA_SW_UPDATED = 0x0, .DMDATA_SW_REPEAT = 0x1, . DMDATA_SW_SIZE = 0x10, .DMDATA_QOS_MODE = 0x0, .DMDATA_QOS_LEVEL = 0x4, .DMDATA_DL_DELTA = 0x10, .DMDATA_DONE = 0x0, .DST_Y_PER_VM_FLIP = 0x0, .DST_Y_PER_ROW_FLIP = 0x8, .REFCYC_PER_PTE_GROUP_FLIP_L = 0x0, .REFCYC_PER_META_CHUNK_FLIP_L = 0x0, .HUBP_VREADY_AT_OR_AFTER_VSYNC = 0x8, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x9, .HUBPREQ_MASTER_UPDATE_LOCK_STATUS = 0x9, .SURFACE_GSL_ENABLE = 0x8, .SURFACE_TRIPLE_BUFFER_ENABLE = 0xa, .VMID = 0x0, .RB_ALIGNED = 0xa, .MPTE_GROUP_SIZE = 0x18 , .MPTE_GROUP_SIZE_C = 0x18, .DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM = 0x1c, .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x0, .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0x0 | |||
889 | }; | |||
890 | ||||
891 | static const struct dcn_hubp2_mask hubp_mask = { | |||
892 | HUBP_MASK_SH_LIST_DCN20(_MASK).HUBP_BLANK_EN = 0x00000001L, .HUBP_TTU_DISABLE = 0x00001000L , .HUBP_UNDERFLOW_STATUS = 0x70000000L, .HUBP_UNDERFLOW_CLEAR = 0x80000000L, .HUBP_NO_OUTSTANDING_REQ = 0x00000002L, .HUBP_VTG_SEL = 0x000000F0L, .HUBP_DISABLE = 0x00000004L, .NUM_PIPES = 0x00000007L , .NUM_BANKS = 0x00000038L, .PIPE_INTERLEAVE = 0x000000C0L, . NUM_SE = 0x00000300L, .NUM_RB_PER_SE = 0x00000C00L, .MAX_COMPRESSED_FRAGS = 0x00003000L, .SW_MODE = 0x0000001FL, .META_LINEAR = 0x00000200L , .PIPE_ALIGNED = 0x00000800L, .PITCH = 0x00003FFFL, .META_PITCH = 0x3FFF0000L, .PITCH_C = 0x00003FFFL, .META_PITCH_C = 0x3FFF0000L , .SURFACE_PIXEL_FORMAT = 0x0000007FL, .SURFACE_FLIP_TYPE = 0x00000002L , .SURFACE_FLIP_MODE_FOR_STEREOSYNC = 0x00003000L, .SURFACE_FLIP_IN_STEREOSYNC = 0x00010000L, .SURFACE_FLIP_PENDING = 0x00000100L, .SURFACE_UPDATE_LOCK = 0x00000001L, .PRI_VIEWPORT_WIDTH = 0x00003FFFL, .PRI_VIEWPORT_HEIGHT = 0x3FFF0000L, .PRI_VIEWPORT_X_START = 0x00003FFFL, .PRI_VIEWPORT_Y_START = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH = 0x00003FFFL, .SEC_VIEWPORT_HEIGHT = 0x3FFF0000L, .SEC_VIEWPORT_X_START = 0x00003FFFL, .SEC_VIEWPORT_Y_START = 0x3FFF0000L, .PRI_VIEWPORT_WIDTH_C = 0x00003FFFL, .PRI_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .PRI_VIEWPORT_X_START_C = 0x00003FFFL, .PRI_VIEWPORT_Y_START_C = 0x3FFF0000L, .SEC_VIEWPORT_WIDTH_C = 0x00003FFFL, .SEC_VIEWPORT_HEIGHT_C = 0x3FFF0000L, .SEC_VIEWPORT_X_START_C = 0x00003FFFL, .SEC_VIEWPORT_Y_START_C = 0x3FFF0000L, .PRIMARY_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, . PRIMARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS = 0xFFFFFFFFL, .PRIMARY_META_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS = 0xFFFFFFFFL, . SECONDARY_META_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .SECONDARY_META_SURFACE_ADDRESS = 0xFFFFFFFFL, .PRIMARY_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL , .PRIMARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SECONDARY_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL, .SECONDARY_SURFACE_ADDRESS_C = 0xFFFFFFFFL, . PRIMARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_META_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SECONDARY_META_SURFACE_ADDRESS_HIGH_C = 0x0000FFFFL , .SECONDARY_META_SURFACE_ADDRESS_C = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH = 0x0000FFFFL, .SURFACE_INUSE_ADDRESS_C = 0xFFFFFFFFL, .SURFACE_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, . SURFACE_EARLIEST_INUSE_ADDRESS = 0xFFFFFFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH = 0x0000FFFFL, .SURFACE_EARLIEST_INUSE_ADDRESS_C = 0xFFFFFFFFL , .SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C = 0x0000FFFFL, .PRIMARY_SURFACE_TMZ = 0x00000001L, .PRIMARY_SURFACE_TMZ_C = 0x00000010L, .PRIMARY_META_SURFACE_TMZ = 0x00010000L, .PRIMARY_META_SURFACE_TMZ_C = 0x00020000L, .PRIMARY_SURFACE_DCC_EN = 0x00000002L, .PRIMARY_SURFACE_DCC_IND_64B_BLK = 0x00000004L , .SECONDARY_SURFACE_TMZ = 0x00000100L, .SECONDARY_SURFACE_TMZ_C = 0x00001000L, .SECONDARY_META_SURFACE_TMZ = 0x00040000L, .SECONDARY_META_SURFACE_TMZ_C = 0x00080000L, .SECONDARY_SURFACE_DCC_EN = 0x00000200L, .SECONDARY_SURFACE_DCC_IND_64B_BLK = 0x00000400L, .DET_BUF_PLANE1_BASE_ADDRESS = 0x00000FFFL, . CROSSBAR_SRC_CB_B = 0x00300000L, .CROSSBAR_SRC_CR_R = 0x00C00000L , .DRQ_EXPANSION_MODE = 0x00000003L, .PRQ_EXPANSION_MODE = 0x000000C0L , .MRQ_EXPANSION_MODE = 0x00000030L, .CRQ_EXPANSION_MODE = 0x0000000CL , .CHUNK_SIZE = 0x00000700L, .MIN_CHUNK_SIZE = 0x00001800L, . META_CHUNK_SIZE = 0x00030000L, .MIN_META_CHUNK_SIZE = 0x000C0000L , .DPTE_GROUP_SIZE = 0x00700000L, .SWATH_HEIGHT = 0x00000007L , .PTE_ROW_HEIGHT_LINEAR = 0x00000070L, .CHUNK_SIZE_C = 0x00000700L , .MIN_CHUNK_SIZE_C = 0x00001800L, .META_CHUNK_SIZE_C = 0x00030000L , .MIN_META_CHUNK_SIZE_C = 0x000C0000L, .DPTE_GROUP_SIZE_C = 0x00700000L , .SWATH_HEIGHT_C = 0x00000007L, .PTE_ROW_HEIGHT_LINEAR_C = 0x00000070L , .REFCYC_H_BLANK_END = 0x00001FFFL, .DLG_V_BLANK_END = 0x7FFF0000L , .MIN_DST_Y_NEXT_START = 0x0003FFFFL, .REFCYC_PER_HTOTAL = 0x001FFFFFL , .REFCYC_X_AFTER_SCALER = 0x00001FFFL, .DST_Y_AFTER_SCALER = 0x00070000L, .DST_Y_PER_VM_VBLANK = 0x0000001FL, .DST_Y_PER_ROW_VBLANK = 0x00003F00L, .REF_FREQ_TO_PIX_FREQ = 0x001FFFFFL, .REFCYC_PER_PTE_GROUP_VBLANK_L = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_VBLANK_L = 0x007FFFFFL , .DST_Y_PER_META_ROW_NOM_L = 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_L = 0x007FFFFFL, .REFCYC_PER_LINE_DELIVERY_PRE_L = 0x00001FFFL , .REFCYC_PER_LINE_DELIVERY_PRE_C = 0x1FFF0000L, .REFCYC_PER_LINE_DELIVERY_L = 0x00001FFFL, .REFCYC_PER_LINE_DELIVERY_C = 0x1FFF0000L, .REFCYC_PER_PTE_GROUP_VBLANK_C = 0x007FFFFFL, .REFCYC_PER_META_CHUNK_VBLANK_C = 0x007FFFFFL , .DST_Y_PER_META_ROW_NOM_C = 0x0001FFFFL, .REFCYC_PER_META_CHUNK_NOM_C = 0x007FFFFFL, .QoS_LEVEL_LOW_WM = 0x00003FFFL, .QoS_LEVEL_HIGH_WM = 0x3FFF0000L, .MIN_TTU_VBLANK = 0x00FFFFFFL, .QoS_LEVEL_FLIP = 0xF0000000L, .REFCYC_PER_REQ_DELIVERY = 0x007FFFFFL, .QoS_LEVEL_FIXED = 0x0F000000L, .QoS_RAMP_DISABLE = 0x10000000L, .REFCYC_PER_REQ_DELIVERY_PRE = 0x007FFFFFL, .HUBP_CLOCK_ENABLE = 0x00000001L, .DST_Y_PER_PTE_ROW_NOM_L = 0x0001FFFFL, .REFCYC_PER_PTE_GROUP_NOM_L = 0x007FFFFFL, .DST_Y_PER_PTE_ROW_NOM_C = 0x0001FFFFL, .REFCYC_PER_PTE_GROUP_NOM_C = 0x007FFFFFL, .ENABLE_L1_TLB = 0x00000001L, .SYSTEM_ACCESS_MODE = 0x00000018L, .REFCYC_PER_REQ_DELIVERY = 0x007FFFFFL, .QoS_LEVEL_FIXED = 0x0F000000L, .QoS_RAMP_DISABLE = 0x10000000L, .REFCYC_PER_REQ_DELIVERY_PRE = 0x007FFFFFL, . ROTATION_ANGLE = 0x00000300L, .H_MIRROR_EN = 0x00000400L, .DST_Y_PREFETCH = 0xFF000000L, .VRATIO_PREFETCH = 0x003FFFFFL, .VRATIO_PREFETCH_C = 0x003FFFFFL, .MC_VM_SYSTEM_APERTURE_LOW_ADDR = 0x3FFFFFFFL , .MC_VM_SYSTEM_APERTURE_HIGH_ADDR = 0x3FFFFFFFL, .CURSOR0_DST_Y_OFFSET = 0x000000FFL, .CURSOR0_CHUNK_HDL_ADJUST = 0x00000300L, .CURSOR_SURFACE_ADDRESS_HIGH = 0x0000FFFFL, .CURSOR_SURFACE_ADDRESS = 0xFFFFFFFFL, .CURSOR_WIDTH = 0x01FF0000L, .CURSOR_HEIGHT = 0x000001FFL, .CURSOR_MODE = 0x00000700L , .CURSOR_2X_MAGNIFY = 0x00000010L, .CURSOR_PITCH = 0x00030000L , .CURSOR_LINES_PER_CHUNK = 0x1F000000L, .CURSOR_ENABLE = 0x00000001L , .CURSOR_X_POSITION = 0x3FFF0000L, .CURSOR_Y_POSITION = 0x00003FFFL , .CURSOR_HOT_SPOT_X = 0x00FF0000L, .CURSOR_HOT_SPOT_Y = 0x000000FFL , .CURSOR_DST_X_OFFSET = 0x00001FFFL, .DMDATA_ADDRESS_HIGH = 0x0000FFFFL , .DMDATA_MODE = 0x00000004L, .DMDATA_UPDATED = 0x00000001L, . DMDATA_REPEAT = 0x00000002L, .DMDATA_SIZE = 0x0FFF0000L, .DMDATA_SW_UPDATED = 0x00000001L, .DMDATA_SW_REPEAT = 0x00000002L, .DMDATA_SW_SIZE = 0x0FFF0000L, .DMDATA_QOS_MODE = 0x00000001L, .DMDATA_QOS_LEVEL = 0x000000F0L, .DMDATA_DL_DELTA = 0xFFFF0000L, .DMDATA_DONE = 0x00000001L, .DST_Y_PER_VM_FLIP = 0x0000001FL, .DST_Y_PER_ROW_FLIP = 0x00003F00L, .REFCYC_PER_PTE_GROUP_FLIP_L = 0x007FFFFFL, . REFCYC_PER_META_CHUNK_FLIP_L = 0x007FFFFFL, .HUBP_VREADY_AT_OR_AFTER_VSYNC = 0x00000100L, .HUBP_DISABLE_STOP_DATA_DURING_VM = 0x00000200L , .HUBPREQ_MASTER_UPDATE_LOCK_STATUS = 0x00000200L, .SURFACE_GSL_ENABLE = 0x00000100L, .SURFACE_TRIPLE_BUFFER_ENABLE = 0x00000400L, . VMID = 0x0000000FL, .RB_ALIGNED = 0x00000400L, .MPTE_GROUP_SIZE = 0x07000000L, .MPTE_GROUP_SIZE_C = 0x07000000L, .DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM = 0x10000000L, .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB = 0x0000000FL , .DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB = 0xFFFFFFFFL | |||
893 | }; | |||
894 | ||||
895 | static const struct dcn_hubbub_registers hubbub_reg = { | |||
896 | HUBBUB_REG_LIST_DCN20(0).DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x000034C0 + 0x0509, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x000034C0 + 0x050d, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x000034C0 + 0x050e, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x000034C0 + 0x0512, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x000034C0 + 0x0513, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x000034C0 + 0x0517, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x000034C0 + 0x0518, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x000034C0 + 0x051c, .DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL = 0x000034C0 + 0x051d, .DCHUBBUB_ARB_DRAM_STATE_CNTL = 0x000034C0 + 0x0508, .DCHUBBUB_ARB_SAT_LEVEL = 0x000034C0 + 0x0506, .DCHUBBUB_ARB_DF_REQ_OUTSTAND = 0x000034C0 + 0x0505, .DCHUBBUB_GLOBAL_TIMER_CNTL = 0x000034C0 + 0x051f, .DCHUBBUB_TEST_DEBUG_INDEX = 0x000034C0 + 0x053d, . DCHUBBUB_TEST_DEBUG_DATA = 0x000034C0 + 0x053e, .DCHUBBUB_SOFT_RESET = 0x000034C0 + 0x052e, .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04f1 , .DCN_VM_FB_LOCATION_BASE = 0x000034C0 + 0x0493, .DCN_VM_FB_LOCATION_TOP = 0x000034C0 + 0x0494, .DCN_VM_FB_OFFSET = 0x000034C0 + 0x0495 , .DCN_VM_AGP_BOT = 0x000034C0 + 0x0496, .DCN_VM_AGP_TOP = 0x000034C0 + 0x0497, .DCN_VM_AGP_BASE = 0x000034C0 + 0x0498, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x000034C0 + 0x050b, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x000034C0 + 0x050c, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = 0x000034C0 + 0x0510, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x000034C0 + 0x0511, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x000034C0 + 0x0515, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x000034C0 + 0x0516, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x000034C0 + 0x051a, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = 0x000034C0 + 0x051b, .DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A = 0x000034C0 + 0x050a, .DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B = 0x000034C0 + 0x050f, .DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C = 0x000034C0 + 0x0514, .DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D = 0x000034C0 + 0x0519, .DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB = 0x000034C0 + 0x05cb, .DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB = 0x000034C0 + 0x05cc | |||
897 | }; | |||
898 | ||||
899 | static const struct dcn_hubbub_shift hubbub_shift = { | |||
900 | HUBBUB_MASK_SH_LIST_DCN20(__SHIFT).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCHUBBUB_GLOBAL_SOFT_RESET = 0x0, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x8, .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE = 0x4, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x0, . DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x1, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE = 0x4, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x5, .DCHUBBUB_ARB_SAT_LEVEL = 0x0, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND = 0x10, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x0, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x0 , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x0 , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x0, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0, .FB_BASE = 0x0, . FB_TOP = 0x0, .FB_OFFSET = 0x0, .AGP_BOT = 0x0, .AGP_TOP = 0x0 , .AGP_BASE = 0x0, .DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB = 0x0, .DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB = 0x0 | |||
901 | }; | |||
902 | ||||
903 | static const struct dcn_hubbub_mask hubbub_mask = { | |||
904 | HUBBUB_MASK_SH_LIST_DCN20(_MASK).DCHUBBUB_GLOBAL_TIMER_ENABLE = 0x00001000L, .DCHUBBUB_GLOBAL_SOFT_RESET = 0x00000001L, .DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST = 0x00000100L , .DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE = 0x00000010L , .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE = 0x00000001L, .DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0x00000002L, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE = 0x00000010L, .DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE = 0x00000020L , .DCHUBBUB_ARB_SAT_LEVEL = 0xFFFFFFFFL, .DCHUBBUB_ARB_MIN_REQ_OUTSTAND = 0x01FF0000L, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A = 0x001FFFFFL , .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B = 0x001FFFFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C = 0x001FFFFFL, .DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D = 0x001FFFFFL , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A = 0x001FFFFFL , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B = 0x001FFFFFL , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C = 0x001FFFFFL , .DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D = 0x001FFFFFL , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A = 0x001FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B = 0x001FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C = 0x001FFFFFL , .DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D = 0x001FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A = 0x001FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B = 0x001FFFFFL , .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C = 0x001FFFFFL, .DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D = 0x001FFFFFL, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, . FB_BASE = 0x00FFFFFFL, .FB_TOP = 0x00FFFFFFL, .FB_OFFSET = 0x00FFFFFFL , .AGP_BOT = 0x00FFFFFFL, .AGP_TOP = 0x00FFFFFFL, .AGP_BASE = 0x00FFFFFFL, .DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB = 0x0000000FL , .DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB = 0xFFFFFFFFL | |||
905 | }; | |||
906 | ||||
907 | #define vmid_regs(id)[id] = { .CNTL = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_CNTL_BASE_IDX + mmDCN_VM_CONTEXTid_CNTL, .PAGE_TABLE_BASE_ADDR_HI32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32, .PAGE_TABLE_BASE_ADDR_LO32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32, .PAGE_TABLE_START_ADDR_HI32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32, .PAGE_TABLE_START_ADDR_LO32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32, .PAGE_TABLE_END_ADDR_HI32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32, .PAGE_TABLE_END_ADDR_LO32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32}\ | |||
908 | [id] = {\ | |||
909 | DCN20_VMID_REG_LIST(id).CNTL = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_CNTL_BASE_IDX + mmDCN_VM_CONTEXTid_CNTL, .PAGE_TABLE_BASE_ADDR_HI32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_HI32, .PAGE_TABLE_BASE_ADDR_LO32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_BASE_ADDR_LO32, .PAGE_TABLE_START_ADDR_HI32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_HI32, .PAGE_TABLE_START_ADDR_LO32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_START_ADDR_LO32, .PAGE_TABLE_END_ADDR_HI32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_HI32, .PAGE_TABLE_END_ADDR_LO32 = DCN_BASE__INST0_SEGmmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32_BASE_IDX + mmDCN_VM_CONTEXTid_PAGE_TABLE_END_ADDR_LO32\ | |||
910 | } | |||
911 | ||||
912 | static const struct dcn_vmid_registers vmid_regs[] = { | |||
913 | vmid_regs(0)[0] = { .CNTL = 0x000034C0 + 0x0559, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x055a, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x055b, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x055c, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x055d, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x055e, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x055f}, | |||
914 | vmid_regs(1)[1] = { .CNTL = 0x000034C0 + 0x0560, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0561, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0562, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0563, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0564, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0565, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0566}, | |||
915 | vmid_regs(2)[2] = { .CNTL = 0x000034C0 + 0x0567, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0568, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0569, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x056a, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x056b, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x056c, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x056d}, | |||
916 | vmid_regs(3)[3] = { .CNTL = 0x000034C0 + 0x056e, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x056f, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0570, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0571, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0572, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0573, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0574}, | |||
917 | vmid_regs(4)[4] = { .CNTL = 0x000034C0 + 0x0575, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0576, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0577, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0578, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0579, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x057a, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x057b}, | |||
918 | vmid_regs(5)[5] = { .CNTL = 0x000034C0 + 0x057c, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x057d, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x057e, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x057f, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0580, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0581, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0582}, | |||
919 | vmid_regs(6)[6] = { .CNTL = 0x000034C0 + 0x0583, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0584, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0585, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0586, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0587, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0588, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0589}, | |||
920 | vmid_regs(7)[7] = { .CNTL = 0x000034C0 + 0x058a, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x058b, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x058c, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x058d, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x058e, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x058f, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0590}, | |||
921 | vmid_regs(8)[8] = { .CNTL = 0x000034C0 + 0x0591, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0592, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x0593, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x0594, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x0595, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x0596, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x0597}, | |||
922 | vmid_regs(9)[9] = { .CNTL = 0x000034C0 + 0x0598, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x0599, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x059a, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x059b, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x059c, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x059d, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x059e}, | |||
923 | vmid_regs(10)[10] = { .CNTL = 0x000034C0 + 0x059f, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05a0, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05a1, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05a2, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05a3, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05a4, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05a5}, | |||
924 | vmid_regs(11)[11] = { .CNTL = 0x000034C0 + 0x05a6, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05a7, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05a8, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05a9, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05aa, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05ab, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05ac}, | |||
925 | vmid_regs(12)[12] = { .CNTL = 0x000034C0 + 0x05ad, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05ae, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05af, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05b0, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05b1, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05b2, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05b3}, | |||
926 | vmid_regs(13)[13] = { .CNTL = 0x000034C0 + 0x05b4, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05b5, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05b6, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05b7, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05b8, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05b9, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05ba}, | |||
927 | vmid_regs(14)[14] = { .CNTL = 0x000034C0 + 0x05bb, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05bc, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05bd, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05be, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05bf, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05c0, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05c1}, | |||
928 | vmid_regs(15)[15] = { .CNTL = 0x000034C0 + 0x05c2, .PAGE_TABLE_BASE_ADDR_HI32 = 0x000034C0 + 0x05c3, .PAGE_TABLE_BASE_ADDR_LO32 = 0x000034C0 + 0x05c4, .PAGE_TABLE_START_ADDR_HI32 = 0x000034C0 + 0x05c5, .PAGE_TABLE_START_ADDR_LO32 = 0x000034C0 + 0x05c6, .PAGE_TABLE_END_ADDR_HI32 = 0x000034C0 + 0x05c7, .PAGE_TABLE_END_ADDR_LO32 = 0x000034C0 + 0x05c8} | |||
929 | }; | |||
930 | ||||
931 | static const struct dcn20_vmid_shift vmid_shifts = { | |||
932 | DCN20_VMID_MASK_SH_LIST(__SHIFT).VM_CONTEXT0_PAGE_TABLE_DEPTH = 0x1, .VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE = 0x3, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 = 0x0, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 = 0x0, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 = 0x0, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 = 0x0, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 = 0x0, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 = 0x0 | |||
933 | }; | |||
934 | ||||
935 | static const struct dcn20_vmid_mask vmid_masks = { | |||
936 | DCN20_VMID_MASK_SH_LIST(_MASK).VM_CONTEXT0_PAGE_TABLE_DEPTH = 0x00000006L, .VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE = 0x00000078L, .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32 = 0xFFFFFFFFL , .VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32 = 0xFFFFFFFFL, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4 = 0x0000000FL, .VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32 = 0xFFFFFFFFL, .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4 = 0x0000000FL , .VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 = 0xFFFFFFFFL | |||
937 | }; | |||
938 | ||||
939 | static const struct dce110_aux_registers_shift aux_shift = { | |||
940 | DCN_AUX_MASK_SH_LIST(__SHIFT).AUX_EN = 0x0, .AUX_RESET = 0x4, .AUX_RESET_DONE = 0x5, .AUX_REG_RW_CNTL_STATUS = 0x2, .AUX_SW_USE_AUX_REG_REQ = 0x10, .AUX_SW_DONE_USING_AUX_REG = 0x11, .AUX_SW_START_DELAY = 0x4, .AUX_SW_WR_BYTES = 0x10, . AUX_SW_GO = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_DATA_RW = 0x0, .AUX_SW_AUTOINCREMENT_DISABLE = 0x1f, .AUX_SW_INDEX = 0x10, .AUX_SW_DATA = 0x8, .AUX_SW_REPLY_BYTE_COUNT = 0x18, . AUX_SW_DONE = 0x0, .AUX_SW_DONE_ACK = 0x1, .AUX_RX_TIMEOUT_LEN = 0x8, .AUX_RX_TIMEOUT_LEN_MUL = 0xf | |||
941 | }; | |||
942 | ||||
943 | static const struct dce110_aux_registers_mask aux_mask = { | |||
944 | DCN_AUX_MASK_SH_LIST(_MASK).AUX_EN = 0x00000001L, .AUX_RESET = 0x00000010L, .AUX_RESET_DONE = 0x00000020L, .AUX_REG_RW_CNTL_STATUS = 0x0000000CL, .AUX_SW_USE_AUX_REG_REQ = 0x00010000L, .AUX_SW_DONE_USING_AUX_REG = 0x00020000L, .AUX_SW_START_DELAY = 0x000000F0L, .AUX_SW_WR_BYTES = 0x001F0000L, .AUX_SW_GO = 0x00000001L , .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, .AUX_SW_DATA_RW = 0x00000001L, .AUX_SW_AUTOINCREMENT_DISABLE = 0x80000000L, . AUX_SW_INDEX = 0x001F0000L, .AUX_SW_DATA = 0x0000FF00L, .AUX_SW_REPLY_BYTE_COUNT = 0x1F000000L, .AUX_SW_DONE = 0x00000001L, .AUX_SW_DONE_ACK = 0x00000002L, .AUX_RX_TIMEOUT_LEN = 0x00007F00L, .AUX_RX_TIMEOUT_LEN_MUL = 0x00018000L | |||
945 | }; | |||
946 | ||||
947 | static int map_transmitter_id_to_phy_instance( | |||
948 | enum transmitter transmitter) | |||
949 | { | |||
950 | switch (transmitter) { | |||
951 | case TRANSMITTER_UNIPHY_A: | |||
952 | return 0; | |||
953 | break; | |||
954 | case TRANSMITTER_UNIPHY_B: | |||
955 | return 1; | |||
956 | break; | |||
957 | case TRANSMITTER_UNIPHY_C: | |||
958 | return 2; | |||
959 | break; | |||
960 | case TRANSMITTER_UNIPHY_D: | |||
961 | return 3; | |||
962 | break; | |||
963 | case TRANSMITTER_UNIPHY_E: | |||
964 | return 4; | |||
965 | break; | |||
966 | case TRANSMITTER_UNIPHY_F: | |||
967 | return 5; | |||
968 | break; | |||
969 | default: | |||
970 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 970); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
971 | return 0; | |||
972 | } | |||
973 | } | |||
974 | ||||
975 | #define dsc_regsDCN20(id)[id] = { .DSC_TOP_CONTROL = DCN_BASE__INST0_SEGmmDSC_TOPid_DSC_TOP_CONTROL_BASE_IDX + mmDSC_TOPid_DSC_TOP_CONTROL, .DSC_DEBUG_CONTROL = DCN_BASE__INST0_SEGmmDSC_TOPid_DSC_DEBUG_CONTROL_BASE_IDX + mmDSC_TOPid_DSC_DEBUG_CONTROL, .DSCC_CONFIG0 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_CONFIG0_BASE_IDX + mmDSCCid_DSCC_CONFIG0, .DSCC_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_CONFIG1_BASE_IDX + mmDSCCid_DSCC_CONFIG1, .DSCC_STATUS = DCN_BASE__INST0_SEGmmDSCCid_DSCC_STATUS_BASE_IDX + mmDSCCid_DSCC_STATUS, .DSCC_INTERRUPT_CONTROL_STATUS = DCN_BASE__INST0_SEGmmDSCCid_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX + mmDSCCid_DSCC_INTERRUPT_CONTROL_STATUS, .DSCC_PPS_CONFIG0 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG0_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG0 , .DSCC_PPS_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG1_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG1, .DSCC_PPS_CONFIG2 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG2_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG2, .DSCC_PPS_CONFIG3 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG3_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG3, .DSCC_PPS_CONFIG4 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG4_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG4, .DSCC_PPS_CONFIG5 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG5_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG5, .DSCC_PPS_CONFIG6 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG6_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG6, .DSCC_PPS_CONFIG7 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG7_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG7, .DSCC_PPS_CONFIG8 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG8_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG8, .DSCC_PPS_CONFIG9 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG9_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG9, .DSCC_PPS_CONFIG10 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG10_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG10, .DSCC_PPS_CONFIG11 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG11_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG11, .DSCC_PPS_CONFIG12 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG12_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG12, .DSCC_PPS_CONFIG13 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG13_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG13, .DSCC_PPS_CONFIG14 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG14_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG14, .DSCC_PPS_CONFIG15 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG15_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG15, .DSCC_PPS_CONFIG16 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG16_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG16, .DSCC_PPS_CONFIG17 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG17_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG17, .DSCC_PPS_CONFIG18 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG18_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG18, .DSCC_PPS_CONFIG19 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG19_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG19, .DSCC_PPS_CONFIG20 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG20_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG20, .DSCC_PPS_CONFIG21 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG21_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG21, .DSCC_PPS_CONFIG22 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG22_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG22, .DSCC_MEM_POWER_CONTROL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MEM_POWER_CONTROL_BASE_IDX + mmDSCCid_DSCC_MEM_POWER_CONTROL, .DSCC_R_Y_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX + mmDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER, .DSCC_R_Y_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX + mmDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER, .DSCC_G_CB_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX + mmDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER, .DSCC_G_CB_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX + mmDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER, .DSCC_B_CR_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX + mmDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER, .DSCC_B_CR_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX + mmDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER, .DSCC_MAX_ABS_ERROR0 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MAX_ABS_ERROR0_BASE_IDX + mmDSCCid_DSCC_MAX_ABS_ERROR0, .DSCC_MAX_ABS_ERROR1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MAX_ABS_ERROR1_BASE_IDX + mmDSCCid_DSCC_MAX_ABS_ERROR1, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, .DSCCIF_CONFIG0 = DCN_BASE__INST0_SEGmmDSCCIFid_DSCCIF_CONFIG0_BASE_IDX + mmDSCCIFid_DSCCIF_CONFIG0 , .DSCCIF_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCIFid_DSCCIF_CONFIG1_BASE_IDX + mmDSCCIFid_DSCCIF_CONFIG1, .DSCRM_DSC_FORWARD_CONFIG = DCN_BASE__INST0_SEGmmDSCRMid_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX + mmDSCRMid_DSCRM_DSC_FORWARD_CONFIG}\ | |||
976 | [id] = {\ | |||
977 | DSC_REG_LIST_DCN20(id).DSC_TOP_CONTROL = DCN_BASE__INST0_SEGmmDSC_TOPid_DSC_TOP_CONTROL_BASE_IDX + mmDSC_TOPid_DSC_TOP_CONTROL, .DSC_DEBUG_CONTROL = DCN_BASE__INST0_SEGmmDSC_TOPid_DSC_DEBUG_CONTROL_BASE_IDX + mmDSC_TOPid_DSC_DEBUG_CONTROL, .DSCC_CONFIG0 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_CONFIG0_BASE_IDX + mmDSCCid_DSCC_CONFIG0, .DSCC_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_CONFIG1_BASE_IDX + mmDSCCid_DSCC_CONFIG1, .DSCC_STATUS = DCN_BASE__INST0_SEGmmDSCCid_DSCC_STATUS_BASE_IDX + mmDSCCid_DSCC_STATUS, .DSCC_INTERRUPT_CONTROL_STATUS = DCN_BASE__INST0_SEGmmDSCCid_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX + mmDSCCid_DSCC_INTERRUPT_CONTROL_STATUS, .DSCC_PPS_CONFIG0 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG0_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG0 , .DSCC_PPS_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG1_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG1, .DSCC_PPS_CONFIG2 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG2_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG2, .DSCC_PPS_CONFIG3 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG3_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG3, .DSCC_PPS_CONFIG4 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG4_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG4, .DSCC_PPS_CONFIG5 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG5_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG5, .DSCC_PPS_CONFIG6 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG6_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG6, .DSCC_PPS_CONFIG7 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG7_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG7, .DSCC_PPS_CONFIG8 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG8_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG8, .DSCC_PPS_CONFIG9 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG9_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG9, .DSCC_PPS_CONFIG10 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG10_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG10, .DSCC_PPS_CONFIG11 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG11_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG11, .DSCC_PPS_CONFIG12 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG12_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG12, .DSCC_PPS_CONFIG13 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG13_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG13, .DSCC_PPS_CONFIG14 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG14_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG14, .DSCC_PPS_CONFIG15 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG15_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG15, .DSCC_PPS_CONFIG16 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG16_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG16, .DSCC_PPS_CONFIG17 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG17_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG17, .DSCC_PPS_CONFIG18 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG18_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG18, .DSCC_PPS_CONFIG19 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG19_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG19, .DSCC_PPS_CONFIG20 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG20_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG20, .DSCC_PPS_CONFIG21 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG21_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG21, .DSCC_PPS_CONFIG22 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_PPS_CONFIG22_BASE_IDX + mmDSCCid_DSCC_PPS_CONFIG22, .DSCC_MEM_POWER_CONTROL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MEM_POWER_CONTROL_BASE_IDX + mmDSCCid_DSCC_MEM_POWER_CONTROL, .DSCC_R_Y_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX + mmDSCCid_DSCC_R_Y_SQUARED_ERROR_LOWER, .DSCC_R_Y_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX + mmDSCCid_DSCC_R_Y_SQUARED_ERROR_UPPER, .DSCC_G_CB_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX + mmDSCCid_DSCC_G_CB_SQUARED_ERROR_LOWER, .DSCC_G_CB_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX + mmDSCCid_DSCC_G_CB_SQUARED_ERROR_UPPER, .DSCC_B_CR_SQUARED_ERROR_LOWER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX + mmDSCCid_DSCC_B_CR_SQUARED_ERROR_LOWER, .DSCC_B_CR_SQUARED_ERROR_UPPER = DCN_BASE__INST0_SEGmmDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX + mmDSCCid_DSCC_B_CR_SQUARED_ERROR_UPPER, .DSCC_MAX_ABS_ERROR0 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MAX_ABS_ERROR0_BASE_IDX + mmDSCCid_DSCC_MAX_ABS_ERROR0, .DSCC_MAX_ABS_ERROR1 = DCN_BASE__INST0_SEGmmDSCCid_DSCC_MAX_ABS_ERROR1_BASE_IDX + mmDSCCid_DSCC_MAX_ABS_ERROR1, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = DCN_BASE__INST0_SEGmmDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX + mmDSCCid_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, .DSCCIF_CONFIG0 = DCN_BASE__INST0_SEGmmDSCCIFid_DSCCIF_CONFIG0_BASE_IDX + mmDSCCIFid_DSCCIF_CONFIG0 , .DSCCIF_CONFIG1 = DCN_BASE__INST0_SEGmmDSCCIFid_DSCCIF_CONFIG1_BASE_IDX + mmDSCCIFid_DSCCIF_CONFIG1, .DSCRM_DSC_FORWARD_CONFIG = DCN_BASE__INST0_SEGmmDSCRMid_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX + mmDSCRMid_DSCRM_DSC_FORWARD_CONFIG\ | |||
978 | } | |||
979 | ||||
980 | static const struct dcn20_dsc_registers dsc_regs[] = { | |||
981 | dsc_regsDCN20(0)[0] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x3000, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x3001, .DSCC_CONFIG0 = 0x000034C0 + 0x300a, . DSCC_CONFIG1 = 0x000034C0 + 0x300b, .DSCC_STATUS = 0x000034C0 + 0x300c, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x300d , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x300e, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x300f, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x3010 , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x3011, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x3012, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x3013 , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3014, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x3015, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x3016 , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x3017, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x3018, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x3019 , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x301a, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x301b, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x301c , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x301d, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x301e, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x301f , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x3020, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x3021, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x3022 , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x3023, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x3024, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x3025, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3026, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3027, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3028, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3029, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x302a , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x302b, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x302c, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x302d , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x302e , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x302f , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3030 , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3031 , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3032, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3033, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3034, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3035, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3005, .DSCCIF_CONFIG1 = 0x000034C0 + 0x3006, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a64}, | |||
982 | dsc_regsDCN20(1)[1] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x305c, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x305d, .DSCC_CONFIG0 = 0x000034C0 + 0x3066, . DSCC_CONFIG1 = 0x000034C0 + 0x3067, .DSCC_STATUS = 0x000034C0 + 0x3068, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x3069 , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x306a, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x306b, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x306c , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x306d, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x306e, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x306f , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3070, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x3071, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x3072 , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x3073, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x3074, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x3075 , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x3076, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x3077, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x3078 , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x3079, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x307a, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x307b , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x307c, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x307d, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x307e , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x307f, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x3080, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x3081, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3082, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3083, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3084, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3085, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3086 , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3087, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x3088, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x3089 , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308a , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308b , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308c , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308d , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308e, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x308f, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3090, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3091, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3061, .DSCCIF_CONFIG1 = 0x000034C0 + 0x3062, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a65}, | |||
983 | dsc_regsDCN20(2)[2] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x30b8, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x30b9, .DSCC_CONFIG0 = 0x000034C0 + 0x30c2, . DSCC_CONFIG1 = 0x000034C0 + 0x30c3, .DSCC_STATUS = 0x000034C0 + 0x30c4, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x30c5 , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x30c6, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x30c7, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x30c8 , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x30c9, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x30ca, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x30cb , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x30cc, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x30cd, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x30ce , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x30cf, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x30d0, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x30d1 , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x30d2, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x30d3, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x30d4 , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x30d5, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x30d6, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x30d7 , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x30d8, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x30d9, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x30da , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x30db, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x30dc, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x30dd, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x30de, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x30df, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x30e0, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x30e1, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x30e2 , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x30e3, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x30e4, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x30e5 , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e6 , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e7 , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e8 , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30e9 , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30ea, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30eb, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30ec, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x30ed, .DSCCIF_CONFIG0 = 0x000034C0 + 0x30bd, .DSCCIF_CONFIG1 = 0x000034C0 + 0x30be, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a66}, | |||
984 | dsc_regsDCN20(3)[3] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x3114, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x3115, .DSCC_CONFIG0 = 0x000034C0 + 0x311e, . DSCC_CONFIG1 = 0x000034C0 + 0x311f, .DSCC_STATUS = 0x000034C0 + 0x3120, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x3121 , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x3122, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x3123, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x3124 , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x3125, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x3126, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x3127 , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3128, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x3129, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x312a , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x312b, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x312c, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x312d , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x312e, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x312f, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x3130 , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x3131, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x3132, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x3133 , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x3134, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x3135, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x3136 , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x3137, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x3138, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x3139, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x313a, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x313b, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x313c, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x313d, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x313e , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x313f, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x3140, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x3141 , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3142 , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3143 , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3144 , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3145 , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3146, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3147, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3148, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3149, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3119, .DSCCIF_CONFIG1 = 0x000034C0 + 0x311a, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a67}, | |||
985 | dsc_regsDCN20(4)[4] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x3170, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x3171, .DSCC_CONFIG0 = 0x000034C0 + 0x317a, . DSCC_CONFIG1 = 0x000034C0 + 0x317b, .DSCC_STATUS = 0x000034C0 + 0x317c, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x317d , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x317e, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x317f, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x3180 , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x3181, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x3182, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x3183 , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x3184, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x3185, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x3186 , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x3187, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x3188, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x3189 , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x318a, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x318b, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x318c , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x318d, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x318e, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x318f , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x3190, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x3191, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x3192 , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x3193, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x3194, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x3195, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3196, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3197, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x3198, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x3199, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x319a , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x319b, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x319c, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x319d , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x319e , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x319f , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31a0 , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31a1 , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31a2, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31a3, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31a4, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31a5, .DSCCIF_CONFIG0 = 0x000034C0 + 0x3175, .DSCCIF_CONFIG1 = 0x000034C0 + 0x3176, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a68}, | |||
986 | dsc_regsDCN20(5)[5] = { .DSC_TOP_CONTROL = 0x000034C0 + 0x31cc, .DSC_DEBUG_CONTROL = 0x000034C0 + 0x31cd, .DSCC_CONFIG0 = 0x000034C0 + 0x31d6, . DSCC_CONFIG1 = 0x000034C0 + 0x31d7, .DSCC_STATUS = 0x000034C0 + 0x31d8, .DSCC_INTERRUPT_CONTROL_STATUS = 0x000034C0 + 0x31d9 , .DSCC_PPS_CONFIG0 = 0x000034C0 + 0x31da, .DSCC_PPS_CONFIG1 = 0x000034C0 + 0x31db, .DSCC_PPS_CONFIG2 = 0x000034C0 + 0x31dc , .DSCC_PPS_CONFIG3 = 0x000034C0 + 0x31dd, .DSCC_PPS_CONFIG4 = 0x000034C0 + 0x31de, .DSCC_PPS_CONFIG5 = 0x000034C0 + 0x31df , .DSCC_PPS_CONFIG6 = 0x000034C0 + 0x31e0, .DSCC_PPS_CONFIG7 = 0x000034C0 + 0x31e1, .DSCC_PPS_CONFIG8 = 0x000034C0 + 0x31e2 , .DSCC_PPS_CONFIG9 = 0x000034C0 + 0x31e3, .DSCC_PPS_CONFIG10 = 0x000034C0 + 0x31e4, .DSCC_PPS_CONFIG11 = 0x000034C0 + 0x31e5 , .DSCC_PPS_CONFIG12 = 0x000034C0 + 0x31e6, .DSCC_PPS_CONFIG13 = 0x000034C0 + 0x31e7, .DSCC_PPS_CONFIG14 = 0x000034C0 + 0x31e8 , .DSCC_PPS_CONFIG15 = 0x000034C0 + 0x31e9, .DSCC_PPS_CONFIG16 = 0x000034C0 + 0x31ea, .DSCC_PPS_CONFIG17 = 0x000034C0 + 0x31eb , .DSCC_PPS_CONFIG18 = 0x000034C0 + 0x31ec, .DSCC_PPS_CONFIG19 = 0x000034C0 + 0x31ed, .DSCC_PPS_CONFIG20 = 0x000034C0 + 0x31ee , .DSCC_PPS_CONFIG21 = 0x000034C0 + 0x31ef, .DSCC_PPS_CONFIG22 = 0x000034C0 + 0x31f0, .DSCC_MEM_POWER_CONTROL = 0x000034C0 + 0x31f1, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x000034C0 + 0x31f2, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x000034C0 + 0x31f3, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x000034C0 + 0x31f4, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x000034C0 + 0x31f5, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x000034C0 + 0x31f6 , .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x000034C0 + 0x31f7, .DSCC_MAX_ABS_ERROR0 = 0x000034C0 + 0x31f8, .DSCC_MAX_ABS_ERROR1 = 0x000034C0 + 0x31f9 , .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fa , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fb , .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fc , .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fd , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31fe, .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x31ff, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3200, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x000034C0 + 0x3201, .DSCCIF_CONFIG0 = 0x000034C0 + 0x31d1, .DSCCIF_CONFIG1 = 0x000034C0 + 0x31d2, .DSCRM_DSC_FORWARD_CONFIG = 0x000034C0 + 0x1a69} | |||
987 | }; | |||
988 | ||||
989 | static const struct dcn20_dsc_shift dsc_shift = { | |||
990 | DSC_REG_LIST_SH_MASK_DCN20(__SHIFT).DSC_CLOCK_EN = 0x0, .DSC_DISPCLK_R_GATE_DIS = 0x4, .DSC_DSCCLK_R_GATE_DIS = 0x8, .DSC_DBG_EN = 0x0, .ICH_RESET_AT_END_OF_LINE = 0x0, . NUMBER_OF_SLICES_PER_LINE = 0x4, .ALTERNATE_ICH_ENCODING_EN = 0x8, .NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION = 0x10, .DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE = 0x0, .DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x0, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED = 0x0, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED = 0x1, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED = 0x2, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED = 0x3, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED = 0x4, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED = 0x5, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED = 0x6, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED = 0x7, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED = 0x8, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED = 0x9 , .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED = 0xa, . DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED = 0xb, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN = 0x10, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN = 0x11, . DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN = 0x12, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN = 0x13, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN = 0x14, .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN = 0x15, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN = 0x16, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN = 0x17, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN = 0x18 , .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN = 0x19, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN = 0x1a, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN = 0x1b, .DSC_VERSION_MINOR = 0x0, .DSC_VERSION_MAJOR = 0x4, . PPS_IDENTIFIER = 0x8, .LINEBUF_DEPTH = 0x18, .DSCC_PPS_CONFIG0__BITS_PER_COMPONENT = 0x1c, .BITS_PER_PIXEL = 0x0, .VBR_ENABLE = 0xa, .SIMPLE_422 = 0xb, .CONVERT_RGB = 0xc, .BLOCK_PRED_ENABLE = 0xd, .NATIVE_422 = 0xe, .NATIVE_420 = 0xf, .CHUNK_SIZE = 0x10, .PIC_WIDTH = 0x0 , .PIC_HEIGHT = 0x10, .SLICE_WIDTH = 0x0, .SLICE_HEIGHT = 0x10 , .INITIAL_XMIT_DELAY = 0x0, .INITIAL_DEC_DELAY = 0x10, .INITIAL_SCALE_VALUE = 0x0, .SCALE_INCREMENT_INTERVAL = 0x10, .SCALE_DECREMENT_INTERVAL = 0x0, .FIRST_LINE_BPG_OFFSET = 0x10, .SECOND_LINE_BPG_OFFSET = 0x18, .NFL_BPG_OFFSET = 0x0, .SLICE_BPG_OFFSET = 0x10, .NSL_BPG_OFFSET = 0x0, .SECOND_LINE_OFFSET_ADJ = 0x10, .INITIAL_OFFSET = 0x0 , .FINAL_OFFSET = 0x10, .FLATNESS_MIN_QP = 0x0, .FLATNESS_MAX_QP = 0x8, .RC_MODEL_SIZE = 0x10, .RC_EDGE_FACTOR = 0x0, .RC_QUANT_INCR_LIMIT0 = 0x8, .RC_QUANT_INCR_LIMIT1 = 0x10, .RC_TGT_OFFSET_LO = 0x18 , .RC_TGT_OFFSET_HI = 0x1c, .RC_BUF_THRESH0 = 0x0, .RC_BUF_THRESH1 = 0x8, .RC_BUF_THRESH2 = 0x10, .RC_BUF_THRESH3 = 0x18, .RC_BUF_THRESH4 = 0x0, .RC_BUF_THRESH5 = 0x8, .RC_BUF_THRESH6 = 0x10, .RC_BUF_THRESH7 = 0x18, .RC_BUF_THRESH8 = 0x0, .RC_BUF_THRESH9 = 0x8, .RC_BUF_THRESH10 = 0x10, .RC_BUF_THRESH11 = 0x18, .RC_BUF_THRESH12 = 0x0, .RC_BUF_THRESH13 = 0x8, .RANGE_MIN_QP0 = 0x10, .RANGE_MAX_QP0 = 0x15, .RANGE_BPG_OFFSET0 = 0x1a, .RANGE_MIN_QP1 = 0x0, .RANGE_MAX_QP1 = 0x5, .RANGE_BPG_OFFSET1 = 0xa, .RANGE_MIN_QP2 = 0x10, .RANGE_MAX_QP2 = 0x15, .RANGE_BPG_OFFSET2 = 0x1a, .RANGE_MIN_QP3 = 0x0, .RANGE_MAX_QP3 = 0x5, .RANGE_BPG_OFFSET3 = 0xa, .RANGE_MIN_QP4 = 0x10, .RANGE_MAX_QP4 = 0x15, .RANGE_BPG_OFFSET4 = 0x1a, .RANGE_MIN_QP5 = 0x0, .RANGE_MAX_QP5 = 0x5, .RANGE_BPG_OFFSET5 = 0xa, .RANGE_MIN_QP6 = 0x10, .RANGE_MAX_QP6 = 0x15, .RANGE_BPG_OFFSET6 = 0x1a, .RANGE_MIN_QP7 = 0x0, .RANGE_MAX_QP7 = 0x5, .RANGE_BPG_OFFSET7 = 0xa, .RANGE_MIN_QP8 = 0x10, .RANGE_MAX_QP8 = 0x15, .RANGE_BPG_OFFSET8 = 0x1a, .RANGE_MIN_QP9 = 0x0, .RANGE_MAX_QP9 = 0x5, .RANGE_BPG_OFFSET9 = 0xa, .RANGE_MIN_QP10 = 0x10, .RANGE_MAX_QP10 = 0x15, .RANGE_BPG_OFFSET10 = 0x1a, .RANGE_MIN_QP11 = 0x0, .RANGE_MAX_QP11 = 0x5, .RANGE_BPG_OFFSET11 = 0xa, .RANGE_MIN_QP12 = 0x10, .RANGE_MAX_QP12 = 0x15, .RANGE_BPG_OFFSET12 = 0x1a, .RANGE_MIN_QP13 = 0x0, .RANGE_MAX_QP13 = 0x5, .RANGE_BPG_OFFSET13 = 0xa, .RANGE_MIN_QP14 = 0x10, .RANGE_MAX_QP14 = 0x15, .RANGE_BPG_OFFSET14 = 0x1a, .DSCC_DEFAULT_MEM_LOW_POWER_STATE = 0x0, .DSCC_MEM_PWR_FORCE = 0x4, .DSCC_MEM_PWR_DIS = 0x8, .DSCC_MEM_PWR_STATE = 0x10, . DSCC_NATIVE_422_MEM_PWR_FORCE = 0x14, .DSCC_NATIVE_422_MEM_PWR_DIS = 0x18, .DSCC_NATIVE_422_MEM_PWR_STATE = 0x1c, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0x0, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0x0, .DSCC_G_CB_SQUARED_ERROR_LOWER = 0x0, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0x0, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0x0, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0x0, .DSCC_R_Y_MAX_ABS_ERROR = 0x0, .DSCC_G_CB_MAX_ABS_ERROR = 0x10, .DSCC_B_CR_MAX_ABS_ERROR = 0x0, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x0, . DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x0, .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x0, . INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN = 0x0, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN = 0x4, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS = 0x8, .INPUT_PIXEL_FORMAT = 0xc, .DSCCIF_CONFIG0__BITS_PER_COMPONENT = 0x10, .DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x18, .PIC_WIDTH = 0x0, .PIC_HEIGHT = 0x10, .DSCRM_DSC_FORWARD_EN = 0x0, .DSCRM_DSC_OPP_PIPE_SOURCE = 0x4 | |||
991 | }; | |||
992 | ||||
993 | static const struct dcn20_dsc_mask dsc_mask = { | |||
994 | DSC_REG_LIST_SH_MASK_DCN20(_MASK).DSC_CLOCK_EN = 0x00000001L, .DSC_DISPCLK_R_GATE_DIS = 0x00000010L , .DSC_DSCCLK_R_GATE_DIS = 0x00000100L, .DSC_DBG_EN = 0x00000001L , .ICH_RESET_AT_END_OF_LINE = 0x0000000FL, .NUMBER_OF_SLICES_PER_LINE = 0x00000030L, .ALTERNATE_ICH_ENCODING_EN = 0x00000100L, .NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION = 0xFFFF0000L, .DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE = 0x0003FFFFL , .DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x00000001L, .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED = 0x00000001L, .DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED = 0x00000002L , .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED = 0x00000004L, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED = 0x00000008L, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED = 0x00000010L , .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED = 0x00000020L, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED = 0x00000040L, .DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED = 0x00000080L , .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED = 0x00000100L , .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED = 0x00000200L , .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED = 0x00000400L , .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED = 0x00000800L , .DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN = 0x00010000L, . DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN = 0x00020000L, .DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN = 0x00040000L, .DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN = 0x00080000L, .DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN = 0x00100000L , .DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN = 0x00200000L, .DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN = 0x00400000L, . DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN = 0x00800000L, .DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN = 0x01000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN = 0x02000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN = 0x04000000L, .DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN = 0x08000000L, .DSC_VERSION_MINOR = 0x0000000FL, .DSC_VERSION_MAJOR = 0x000000F0L, .PPS_IDENTIFIER = 0x0000FF00L, .LINEBUF_DEPTH = 0x0F000000L, .DSCC_PPS_CONFIG0__BITS_PER_COMPONENT = 0xF0000000L , .BITS_PER_PIXEL = 0x000003FFL, .VBR_ENABLE = 0x00000400L, . SIMPLE_422 = 0x00000800L, .CONVERT_RGB = 0x00001000L, .BLOCK_PRED_ENABLE = 0x00002000L, .NATIVE_422 = 0x00004000L, .NATIVE_420 = 0x00008000L , .CHUNK_SIZE = 0xFFFF0000L, .PIC_WIDTH = 0x0000FFFFL, .PIC_HEIGHT = 0xFFFF0000L, .SLICE_WIDTH = 0x0000FFFFL, .SLICE_HEIGHT = 0xFFFF0000L , .INITIAL_XMIT_DELAY = 0x000003FFL, .INITIAL_DEC_DELAY = 0xFFFF0000L , .INITIAL_SCALE_VALUE = 0x0000003FL, .SCALE_INCREMENT_INTERVAL = 0xFFFF0000L, .SCALE_DECREMENT_INTERVAL = 0x00000FFFL, .FIRST_LINE_BPG_OFFSET = 0x001F0000L, .SECOND_LINE_BPG_OFFSET = 0x1F000000L, .NFL_BPG_OFFSET = 0x0000FFFFL, .SLICE_BPG_OFFSET = 0xFFFF0000L, .NSL_BPG_OFFSET = 0x0000FFFFL, .SECOND_LINE_OFFSET_ADJ = 0xFFFF0000L, .INITIAL_OFFSET = 0x0000FFFFL, .FINAL_OFFSET = 0xFFFF0000L, .FLATNESS_MIN_QP = 0x0000001FL, .FLATNESS_MAX_QP = 0x00001F00L, .RC_MODEL_SIZE = 0xFFFF0000L, .RC_EDGE_FACTOR = 0x0000000FL, .RC_QUANT_INCR_LIMIT0 = 0x00001F00L, .RC_QUANT_INCR_LIMIT1 = 0x001F0000L, .RC_TGT_OFFSET_LO = 0x0F000000L, .RC_TGT_OFFSET_HI = 0xF0000000L, .RC_BUF_THRESH0 = 0x000000FFL, .RC_BUF_THRESH1 = 0x0000FF00L, .RC_BUF_THRESH2 = 0x00FF0000L, .RC_BUF_THRESH3 = 0xFF000000L, .RC_BUF_THRESH4 = 0x000000FFL, .RC_BUF_THRESH5 = 0x0000FF00L, .RC_BUF_THRESH6 = 0x00FF0000L, .RC_BUF_THRESH7 = 0xFF000000L, .RC_BUF_THRESH8 = 0x000000FFL, .RC_BUF_THRESH9 = 0x0000FF00L, .RC_BUF_THRESH10 = 0x00FF0000L, .RC_BUF_THRESH11 = 0xFF000000L, .RC_BUF_THRESH12 = 0x000000FFL, .RC_BUF_THRESH13 = 0x0000FF00L, .RANGE_MIN_QP0 = 0x001F0000L, .RANGE_MAX_QP0 = 0x03E00000L, .RANGE_BPG_OFFSET0 = 0xFC000000L, .RANGE_MIN_QP1 = 0x0000001FL, .RANGE_MAX_QP1 = 0x000003E0L, .RANGE_BPG_OFFSET1 = 0x0000FC00L, .RANGE_MIN_QP2 = 0x001F0000L, .RANGE_MAX_QP2 = 0x03E00000L, .RANGE_BPG_OFFSET2 = 0xFC000000L, .RANGE_MIN_QP3 = 0x0000001FL, .RANGE_MAX_QP3 = 0x000003E0L, .RANGE_BPG_OFFSET3 = 0x0000FC00L, .RANGE_MIN_QP4 = 0x001F0000L, .RANGE_MAX_QP4 = 0x03E00000L, .RANGE_BPG_OFFSET4 = 0xFC000000L, .RANGE_MIN_QP5 = 0x0000001FL, .RANGE_MAX_QP5 = 0x000003E0L, .RANGE_BPG_OFFSET5 = 0x0000FC00L, .RANGE_MIN_QP6 = 0x001F0000L, .RANGE_MAX_QP6 = 0x03E00000L, .RANGE_BPG_OFFSET6 = 0xFC000000L, .RANGE_MIN_QP7 = 0x0000001FL, .RANGE_MAX_QP7 = 0x000003E0L, .RANGE_BPG_OFFSET7 = 0x0000FC00L, .RANGE_MIN_QP8 = 0x001F0000L, .RANGE_MAX_QP8 = 0x03E00000L, .RANGE_BPG_OFFSET8 = 0xFC000000L, .RANGE_MIN_QP9 = 0x0000001FL, .RANGE_MAX_QP9 = 0x000003E0L, .RANGE_BPG_OFFSET9 = 0x0000FC00L, .RANGE_MIN_QP10 = 0x001F0000L, .RANGE_MAX_QP10 = 0x03E00000L, .RANGE_BPG_OFFSET10 = 0xFC000000L, .RANGE_MIN_QP11 = 0x0000001FL, .RANGE_MAX_QP11 = 0x000003E0L, .RANGE_BPG_OFFSET11 = 0x0000FC00L, .RANGE_MIN_QP12 = 0x001F0000L, .RANGE_MAX_QP12 = 0x03E00000L, .RANGE_BPG_OFFSET12 = 0xFC000000L, .RANGE_MIN_QP13 = 0x0000001FL, .RANGE_MAX_QP13 = 0x000003E0L, .RANGE_BPG_OFFSET13 = 0x0000FC00L, .RANGE_MIN_QP14 = 0x001F0000L, .RANGE_MAX_QP14 = 0x03E00000L, .RANGE_BPG_OFFSET14 = 0xFC000000L, .DSCC_DEFAULT_MEM_LOW_POWER_STATE = 0x00000003L , .DSCC_MEM_PWR_FORCE = 0x00000030L, .DSCC_MEM_PWR_DIS = 0x00000100L , .DSCC_MEM_PWR_STATE = 0x00030000L, .DSCC_NATIVE_422_MEM_PWR_FORCE = 0x00300000L, .DSCC_NATIVE_422_MEM_PWR_DIS = 0x01000000L, . DSCC_NATIVE_422_MEM_PWR_STATE = 0x30000000L, .DSCC_R_Y_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_R_Y_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, . DSCC_G_CB_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_G_CB_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, .DSCC_B_CR_SQUARED_ERROR_LOWER = 0xFFFFFFFFL, .DSCC_B_CR_SQUARED_ERROR_UPPER = 0xFFFFFFFFL, .DSCC_R_Y_MAX_ABS_ERROR = 0x0000FFFFL, .DSCC_G_CB_MAX_ABS_ERROR = 0xFFFF0000L, .DSCC_B_CR_MAX_ABS_ERROR = 0x0000FFFFL, .DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL = 0x0003FFFFL, .DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL = 0x0003FFFFL, .DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL = 0x0003FFFFL , .INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN = 0x00000001L, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN = 0x00000010L, .INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS = 0x00000100L , .INPUT_PIXEL_FORMAT = 0x00007000L, .DSCCIF_CONFIG0__BITS_PER_COMPONENT = 0x000F0000L, .DOUBLE_BUFFER_REG_UPDATE_PENDING = 0x01000000L , .PIC_WIDTH = 0x0000FFFFL, .PIC_HEIGHT = 0xFFFF0000L, .DSCRM_DSC_FORWARD_EN = 0x00000001L, .DSCRM_DSC_OPP_PIPE_SOURCE = 0x00000070L | |||
995 | }; | |||
996 | ||||
997 | static const struct dccg_registers dccg_regs = { | |||
998 | DCCG_REG_LIST_DCN2().DPPCLK_DTO_CTRL = 0x000000C0 + 0x00b6, .DPPCLK_DTO_PARAM[0] = 0x000000C0 + 0x0099, .DPPCLK_DTO_PARAM[1] = 0x000000C0 + 0x009a , .DPPCLK_DTO_PARAM[2] = 0x000000C0 + 0x009b, .DPPCLK_DTO_PARAM [3] = 0x000000C0 + 0x009c, .REFCLK_CNTL = 0x000000C0 + 0x0049 , .DPPCLK_DTO_PARAM[4] = 0x000000C0 + 0x009d, .DPPCLK_DTO_PARAM [5] = 0x000000C0 + 0x009e | |||
999 | }; | |||
1000 | ||||
1001 | static const struct dccg_shift dccg_shift = { | |||
1002 | DCCG_MASK_SH_LIST_DCN2(__SHIFT).DPPCLK_DTO_ENABLE[0] = 0x0, .DPPCLK_DTO_DB_EN[0] = 0x1, .DPPCLK_DTO_ENABLE [1] = 0x4, .DPPCLK_DTO_DB_EN[1] = 0x5, .DPPCLK_DTO_ENABLE[2] = 0x8, .DPPCLK_DTO_DB_EN[2] = 0x9, .DPPCLK_DTO_ENABLE[3] = 0xc , .DPPCLK_DTO_DB_EN[3] = 0xd, .DPPCLK0_DTO_PHASE = 0x0, .DPPCLK0_DTO_MODULO = 0x10, .REFCLK_CLOCK_EN = 0x0, .REFCLK_SRC_SEL = 0x1, .DPPCLK_DTO_ENABLE [4] = 0x10, .DPPCLK_DTO_DB_EN[4] = 0x11, .DPPCLK_DTO_ENABLE[5 ] = 0x14, .DPPCLK_DTO_DB_EN[5] = 0x15 | |||
1003 | }; | |||
1004 | ||||
1005 | static const struct dccg_mask dccg_mask = { | |||
1006 | DCCG_MASK_SH_LIST_DCN2(_MASK).DPPCLK_DTO_ENABLE[0] = 0x00000001L, .DPPCLK_DTO_DB_EN[0] = 0x00000002L , .DPPCLK_DTO_ENABLE[1] = 0x00000010L, .DPPCLK_DTO_DB_EN[1] = 0x00000020L, .DPPCLK_DTO_ENABLE[2] = 0x00000100L, .DPPCLK_DTO_DB_EN [2] = 0x00000200L, .DPPCLK_DTO_ENABLE[3] = 0x00001000L, .DPPCLK_DTO_DB_EN [3] = 0x00002000L, .DPPCLK0_DTO_PHASE = 0x000000FFL, .DPPCLK0_DTO_MODULO = 0x00FF0000L, .REFCLK_CLOCK_EN = 0x00000001L, .REFCLK_SRC_SEL = 0x00000002L, .DPPCLK_DTO_ENABLE[4] = 0x00010000L, .DPPCLK_DTO_DB_EN [4] = 0x00020000L, .DPPCLK_DTO_ENABLE[5] = 0x00100000L, .DPPCLK_DTO_DB_EN [5] = 0x00200000L | |||
1007 | }; | |||
1008 | ||||
1009 | static const struct resource_caps res_cap_nv10 = { | |||
1010 | .num_timing_generator = 6, | |||
1011 | .num_opp = 6, | |||
1012 | .num_video_plane = 6, | |||
1013 | .num_audio = 7, | |||
1014 | .num_stream_encoder = 6, | |||
1015 | .num_pll = 6, | |||
1016 | .num_dwb = 1, | |||
1017 | .num_ddc = 6, | |||
1018 | .num_vmid = 16, | |||
1019 | .num_dsc = 6, | |||
1020 | }; | |||
1021 | ||||
1022 | static const struct dc_plane_cap plane_cap = { | |||
1023 | .type = DC_PLANE_TYPE_DCN_UNIVERSAL, | |||
1024 | .blends_with_above = true1, | |||
1025 | .blends_with_below = true1, | |||
1026 | .per_pixel_alpha = true1, | |||
1027 | ||||
1028 | .pixel_format_support = { | |||
1029 | .argb8888 = true1, | |||
1030 | .nv12 = true1, | |||
1031 | .fp16 = true1, | |||
1032 | .p010 = true1 | |||
1033 | }, | |||
1034 | ||||
1035 | .max_upscale_factor = { | |||
1036 | .argb8888 = 16000, | |||
1037 | .nv12 = 16000, | |||
1038 | .fp16 = 1 | |||
1039 | }, | |||
1040 | ||||
1041 | .max_downscale_factor = { | |||
1042 | .argb8888 = 250, | |||
1043 | .nv12 = 250, | |||
1044 | .fp16 = 1 | |||
1045 | }, | |||
1046 | 16, | |||
1047 | 16 | |||
1048 | }; | |||
1049 | static const struct resource_caps res_cap_nv14 = { | |||
1050 | .num_timing_generator = 5, | |||
1051 | .num_opp = 5, | |||
1052 | .num_video_plane = 5, | |||
1053 | .num_audio = 6, | |||
1054 | .num_stream_encoder = 5, | |||
1055 | .num_pll = 5, | |||
1056 | .num_dwb = 1, | |||
1057 | .num_ddc = 5, | |||
1058 | .num_vmid = 16, | |||
1059 | .num_dsc = 5, | |||
1060 | }; | |||
1061 | ||||
1062 | static const struct dc_debug_options debug_defaults_drv = { | |||
1063 | .disable_dmcu = false0, | |||
1064 | .force_abm_enable = false0, | |||
1065 | .timing_trace = false0, | |||
1066 | .clock_trace = true1, | |||
1067 | .disable_pplib_clock_request = true1, | |||
1068 | .pipe_split_policy = MPC_SPLIT_DYNAMIC, | |||
1069 | .force_single_disp_pipe_split = false0, | |||
1070 | .disable_dcc = DCC_ENABLE, | |||
1071 | .vsr_support = true1, | |||
1072 | .performance_trace = false0, | |||
1073 | .max_downscale_src_width = 5120,/*upto 5K*/ | |||
1074 | .disable_pplib_wm_range = false0, | |||
1075 | .scl_reset_length10 = true1, | |||
1076 | .sanity_checks = false0, | |||
1077 | .underflow_assert_delay_us = 0xFFFFFFFF, | |||
1078 | }; | |||
1079 | ||||
1080 | static const struct dc_debug_options debug_defaults_diags = { | |||
1081 | .disable_dmcu = false0, | |||
1082 | .force_abm_enable = false0, | |||
1083 | .timing_trace = true1, | |||
1084 | .clock_trace = true1, | |||
1085 | .disable_dpp_power_gate = true1, | |||
1086 | .disable_hubp_power_gate = true1, | |||
1087 | .disable_clock_gate = true1, | |||
1088 | .disable_pplib_clock_request = true1, | |||
1089 | .disable_pplib_wm_range = true1, | |||
1090 | .disable_stutter = true1, | |||
1091 | .scl_reset_length10 = true1, | |||
1092 | .underflow_assert_delay_us = 0xFFFFFFFF, | |||
1093 | .enable_tri_buf = true1, | |||
1094 | }; | |||
1095 | ||||
1096 | void dcn20_dpp_destroy(struct dpp **dpp) | |||
1097 | { | |||
1098 | kfree(TO_DCN20_DPP(*dpp)({ const __typeof( ((struct dcn20_dpp *)0)->base ) *__mptr = (*dpp); (struct dcn20_dpp *)( (char *)__mptr - __builtin_offsetof (struct dcn20_dpp, base) );})); | |||
1099 | *dpp = NULL((void *)0); | |||
1100 | } | |||
1101 | ||||
1102 | struct dpp *dcn20_dpp_create( | |||
1103 | struct dc_context *ctx, | |||
1104 | uint32_t inst) | |||
1105 | { | |||
1106 | struct dcn20_dpp *dpp = | |||
1107 | kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC0x0002); | |||
1108 | ||||
1109 | if (!dpp) | |||
1110 | return NULL((void *)0); | |||
1111 | ||||
1112 | if (dpp2_construct(dpp, ctx, inst, | |||
1113 | &tf_regs[inst], &tf_shift, &tf_mask)) | |||
1114 | return &dpp->base; | |||
1115 | ||||
1116 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1116); do {} while (0); } while (0); | |||
1117 | kfree(dpp); | |||
1118 | return NULL((void *)0); | |||
1119 | } | |||
1120 | ||||
1121 | struct input_pixel_processor *dcn20_ipp_create( | |||
1122 | struct dc_context *ctx, uint32_t inst) | |||
1123 | { | |||
1124 | struct dcn10_ipp *ipp = | |||
1125 | kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC0x0002); | |||
1126 | ||||
1127 | if (!ipp) { | |||
1128 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1128); do {} while (0); } while (0); | |||
1129 | return NULL((void *)0); | |||
1130 | } | |||
1131 | ||||
1132 | dcn20_ipp_construct(ipp, ctx, inst, | |||
1133 | &ipp_regs[inst], &ipp_shift, &ipp_mask); | |||
1134 | return &ipp->base; | |||
1135 | } | |||
1136 | ||||
1137 | ||||
1138 | struct output_pixel_processor *dcn20_opp_create( | |||
1139 | struct dc_context *ctx, uint32_t inst) | |||
1140 | { | |||
1141 | struct dcn20_opp *opp = | |||
1142 | kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC0x0002); | |||
1143 | ||||
1144 | if (!opp) { | |||
1145 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1145); do {} while (0); } while (0); | |||
1146 | return NULL((void *)0); | |||
1147 | } | |||
1148 | ||||
1149 | dcn20_opp_construct(opp, ctx, inst, | |||
1150 | &opp_regs[inst], &opp_shift, &opp_mask); | |||
1151 | return &opp->base; | |||
1152 | } | |||
1153 | ||||
1154 | struct dce_aux *dcn20_aux_engine_create( | |||
1155 | struct dc_context *ctx, | |||
1156 | uint32_t inst) | |||
1157 | { | |||
1158 | struct aux_engine_dce110 *aux_engine = | |||
1159 | kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC0x0002); | |||
1160 | ||||
1161 | if (!aux_engine) | |||
1162 | return NULL((void *)0); | |||
1163 | ||||
1164 | dce110_aux_engine_construct(aux_engine, ctx, inst, | |||
1165 | SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, | |||
1166 | &aux_engine_regs[inst], | |||
1167 | &aux_mask, | |||
1168 | &aux_shift, | |||
1169 | ctx->dc->caps.extended_aux_timeout_support); | |||
1170 | ||||
1171 | return &aux_engine->base; | |||
1172 | } | |||
1173 | #define i2c_inst_regs(id){ .SETUP = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_SETUP_BASE_IDX + mmDC_I2C_DDCid_SETUP, .SPEED = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_SPEED_BASE_IDX + mmDC_I2C_DDCid_SPEED, .HW_STATUS = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_HW_STATUS_BASE_IDX + mmDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b } { I2C_HW_ENGINE_COMMON_REG_LIST(id).SETUP = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_SETUP_BASE_IDX + mmDC_I2C_DDCid_SETUP , .SPEED = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_SPEED_BASE_IDX + mmDC_I2C_DDCid_SPEED, .HW_STATUS = DCN_BASE__INST0_SEGmmDC_I2C_DDCid_HW_STATUS_BASE_IDX + mmDC_I2C_DDCid_HW_STATUS, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b } | |||
1174 | ||||
1175 | static const struct dce_i2c_registers i2c_hw_regs[] = { | |||
1176 | i2c_inst_regs(1){ .SETUP = 0x000034C0 + 0x1ea3, .SPEED = 0x000034C0 + 0x1ea2, .HW_STATUS = 0x000034C0 + 0x1e9c, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b }, | |||
1177 | i2c_inst_regs(2){ .SETUP = 0x000034C0 + 0x1ea5, .SPEED = 0x000034C0 + 0x1ea4, .HW_STATUS = 0x000034C0 + 0x1e9d, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b }, | |||
1178 | i2c_inst_regs(3){ .SETUP = 0x000034C0 + 0x1ea7, .SPEED = 0x000034C0 + 0x1ea6, .HW_STATUS = 0x000034C0 + 0x1e9e, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b }, | |||
1179 | i2c_inst_regs(4){ .SETUP = 0x000034C0 + 0x1ea9, .SPEED = 0x000034C0 + 0x1ea8, .HW_STATUS = 0x000034C0 + 0x1e9f, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b }, | |||
1180 | i2c_inst_regs(5){ .SETUP = 0x000034C0 + 0x1eab, .SPEED = 0x000034C0 + 0x1eaa, .HW_STATUS = 0x000034C0 + 0x1ea0, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b }, | |||
1181 | i2c_inst_regs(6){ .SETUP = 0x000034C0 + 0x1ead, .SPEED = 0x000034C0 + 0x1eac, .HW_STATUS = 0x000034C0 + 0x1ea1, .DC_I2C_ARBITRATION = 0x000034C0 + 0x1e99, .DC_I2C_CONTROL = 0x000034C0 + 0x1e98, .DC_I2C_SW_STATUS = 0x000034C0 + 0x1e9b, .DC_I2C_TRANSACTION0 = 0x000034C0 + 0x1eae , .DC_I2C_TRANSACTION1 = 0x000034C0 + 0x1eaf, .DC_I2C_TRANSACTION2 = 0x000034C0 + 0x1eb0, .DC_I2C_TRANSACTION3 = 0x000034C0 + 0x1eb1 , .DC_I2C_DATA = 0x000034C0 + 0x1eb2, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b }, | |||
1182 | }; | |||
1183 | ||||
1184 | static const struct dce_i2c_shift i2c_shifts = { | |||
1185 | I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT).DC_I2C_DDC1_ENABLE = 0x6, .DC_I2C_DDC1_TIME_LIMIT = 0x18, .DC_I2C_DDC1_DATA_DRIVE_EN = 0x0, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x7, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x1, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x10, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0x8, .DC_I2C_DDC1_HW_STATUS = 0x0, .DC_I2C_SW_USE_I2C_REG_REQ = 0x14, .DC_I2C_SW_DONE_USING_I2C_REG = 0x15, .DC_I2C_NO_QUEUED_SW_GO = 0x4, .DC_I2C_SW_PRIORITY = 0x0, .DC_I2C_SOFT_RESET = 0x1, . DC_I2C_SW_STATUS_RESET = 0x3, .DC_I2C_GO = 0x0, .DC_I2C_SEND_RESET = 0x2, .DC_I2C_TRANSACTION_COUNT = 0x14, .DC_I2C_DDC_SELECT = 0x8, .DC_I2C_DDC1_PRESCALE = 0x10, .DC_I2C_DDC1_THRESHOLD = 0x0 , .DC_I2C_SW_STOPPED_ON_NACK = 0x8, .DC_I2C_SW_TIMEOUT = 0x5, .DC_I2C_SW_ABORTED = 0x4, .DC_I2C_SW_DONE = 0x2, .DC_I2C_SW_STATUS = 0x0, .DC_I2C_STOP_ON_NACK0 = 0x8, .DC_I2C_START0 = 0xc, .DC_I2C_RW0 = 0x0, .DC_I2C_STOP0 = 0xd, .DC_I2C_COUNT0 = 0x10, .DC_I2C_DATA_RW = 0x0, .DC_I2C_DATA = 0x8, .DC_I2C_INDEX = 0x10, .DC_I2C_INDEX_WRITE = 0x1f, .XTAL_REF_DIV = 0x8, .DC_I2C_REG_RW_CNTL_STATUS = 0x2 , .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x8, .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x2 | |||
1186 | }; | |||
1187 | ||||
1188 | static const struct dce_i2c_mask i2c_masks = { | |||
1189 | I2C_COMMON_MASK_SH_LIST_DCN2(_MASK).DC_I2C_DDC1_ENABLE = 0x00000040L, .DC_I2C_DDC1_TIME_LIMIT = 0xFF000000L , .DC_I2C_DDC1_DATA_DRIVE_EN = 0x00000001L, .DC_I2C_DDC1_CLK_DRIVE_EN = 0x00000080L, .DC_I2C_DDC1_DATA_DRIVE_SEL = 0x00000002L, .DC_I2C_DDC1_INTRA_TRANSACTION_DELAY = 0x00FF0000L, .DC_I2C_DDC1_INTRA_BYTE_DELAY = 0x0000FF00L, . DC_I2C_DDC1_HW_STATUS = 0x00000003L, .DC_I2C_SW_USE_I2C_REG_REQ = 0x00100000L, .DC_I2C_SW_DONE_USING_I2C_REG = 0x00200000L, . DC_I2C_NO_QUEUED_SW_GO = 0x00000010L, .DC_I2C_SW_PRIORITY = 0x00000003L , .DC_I2C_SOFT_RESET = 0x00000002L, .DC_I2C_SW_STATUS_RESET = 0x00000008L, .DC_I2C_GO = 0x00000001L, .DC_I2C_SEND_RESET = 0x00000004L , .DC_I2C_TRANSACTION_COUNT = 0x00300000L, .DC_I2C_DDC_SELECT = 0x00000700L, .DC_I2C_DDC1_PRESCALE = 0xFFFF0000L, .DC_I2C_DDC1_THRESHOLD = 0x00000003L, .DC_I2C_SW_STOPPED_ON_NACK = 0x00000100L, .DC_I2C_SW_TIMEOUT = 0x00000020L, .DC_I2C_SW_ABORTED = 0x00000010L, .DC_I2C_SW_DONE = 0x00000004L, .DC_I2C_SW_STATUS = 0x00000003L, .DC_I2C_STOP_ON_NACK0 = 0x00000100L, .DC_I2C_START0 = 0x00001000L, .DC_I2C_RW0 = 0x00000001L , .DC_I2C_STOP0 = 0x00002000L, .DC_I2C_COUNT0 = 0x03FF0000L, . DC_I2C_DATA_RW = 0x00000001L, .DC_I2C_DATA = 0x0000FF00L, .DC_I2C_INDEX = 0x03FF0000L, .DC_I2C_INDEX_WRITE = 0x80000000L, .XTAL_REF_DIV = 0x00007F00L, .DC_I2C_REG_RW_CNTL_STATUS = 0x0000000CL, .DC_I2C_DDC1_START_STOP_TIMING_CNTL = 0x00000300L, .DC_I2C_DDC1_SEND_RESET_LENGTH = 0x00000004L | |||
1190 | }; | |||
1191 | ||||
1192 | struct dce_i2c_hw *dcn20_i2c_hw_create( | |||
1193 | struct dc_context *ctx, | |||
1194 | uint32_t inst) | |||
1195 | { | |||
1196 | struct dce_i2c_hw *dce_i2c_hw = | |||
1197 | kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC0x0002); | |||
1198 | ||||
1199 | if (!dce_i2c_hw) | |||
1200 | return NULL((void *)0); | |||
1201 | ||||
1202 | dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, | |||
1203 | &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); | |||
1204 | ||||
1205 | return dce_i2c_hw; | |||
1206 | } | |||
1207 | struct mpc *dcn20_mpc_create(struct dc_context *ctx) | |||
1208 | { | |||
1209 | struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), | |||
1210 | GFP_ATOMIC0x0002); | |||
1211 | ||||
1212 | if (!mpc20) | |||
1213 | return NULL((void *)0); | |||
1214 | ||||
1215 | dcn20_mpc_construct(mpc20, ctx, | |||
1216 | &mpc_regs, | |||
1217 | &mpc_shift, | |||
1218 | &mpc_mask, | |||
1219 | 6); | |||
1220 | ||||
1221 | return &mpc20->base; | |||
1222 | } | |||
1223 | ||||
1224 | struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) | |||
1225 | { | |||
1226 | int i; | |||
1227 | struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), | |||
1228 | GFP_ATOMIC0x0002); | |||
1229 | ||||
1230 | if (!hubbub) | |||
1231 | return NULL((void *)0); | |||
1232 | ||||
1233 | hubbub2_construct(hubbub, ctx, | |||
1234 | &hubbub_reg, | |||
1235 | &hubbub_shift, | |||
1236 | &hubbub_mask); | |||
1237 | ||||
1238 | for (i = 0; i < res_cap_nv10.num_vmid; i++) { | |||
1239 | struct dcn20_vmid *vmid = &hubbub->vmid[i]; | |||
1240 | ||||
1241 | vmid->ctx = ctx; | |||
1242 | ||||
1243 | vmid->regs = &vmid_regs[i]; | |||
1244 | vmid->shifts = &vmid_shifts; | |||
1245 | vmid->masks = &vmid_masks; | |||
1246 | } | |||
1247 | ||||
1248 | return &hubbub->base; | |||
1249 | } | |||
1250 | ||||
1251 | struct timing_generator *dcn20_timing_generator_create( | |||
1252 | struct dc_context *ctx, | |||
1253 | uint32_t instance) | |||
1254 | { | |||
1255 | struct optc *tgn10 = | |||
1256 | kzalloc(sizeof(struct optc), GFP_ATOMIC0x0002); | |||
1257 | ||||
1258 | if (!tgn10) | |||
1259 | return NULL((void *)0); | |||
1260 | ||||
1261 | tgn10->base.inst = instance; | |||
1262 | tgn10->base.ctx = ctx; | |||
1263 | ||||
1264 | tgn10->tg_regs = &tg_regs[instance]; | |||
1265 | tgn10->tg_shift = &tg_shift; | |||
1266 | tgn10->tg_mask = &tg_mask; | |||
1267 | ||||
1268 | dcn20_timing_generator_init(tgn10); | |||
1269 | ||||
1270 | return &tgn10->base; | |||
1271 | } | |||
1272 | ||||
1273 | static const struct encoder_feature_support link_enc_feature = { | |||
1274 | .max_hdmi_deep_color = COLOR_DEPTH_121212, | |||
1275 | .max_hdmi_pixel_clock = 600000, | |||
1276 | .hdmi_ycbcr420_supported = true1, | |||
1277 | .dp_ycbcr420_supported = true1, | |||
1278 | .fec_supported = true1, | |||
1279 | .flags.bits.IS_HBR2_CAPABLE = true1, | |||
1280 | .flags.bits.IS_HBR3_CAPABLE = true1, | |||
1281 | .flags.bits.IS_TPS3_CAPABLE = true1, | |||
1282 | .flags.bits.IS_TPS4_CAPABLE = true1 | |||
1283 | }; | |||
1284 | ||||
1285 | struct link_encoder *dcn20_link_encoder_create( | |||
1286 | const struct encoder_init_data *enc_init_data) | |||
1287 | { | |||
1288 | struct dcn20_link_encoder *enc20 = | |||
1289 | kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL(0x0001 | 0x0004)); | |||
1290 | int link_regs_id; | |||
1291 | ||||
1292 | if (!enc20) | |||
1293 | return NULL((void *)0); | |||
1294 | ||||
1295 | link_regs_id = | |||
1296 | map_transmitter_id_to_phy_instance(enc_init_data->transmitter); | |||
1297 | ||||
1298 | dcn20_link_encoder_construct(enc20, | |||
1299 | enc_init_data, | |||
1300 | &link_enc_feature, | |||
1301 | &link_enc_regs[link_regs_id], | |||
1302 | &link_enc_aux_regs[enc_init_data->channel - 1], | |||
1303 | &link_enc_hpd_regs[enc_init_data->hpd_source], | |||
1304 | &le_shift, | |||
1305 | &le_mask); | |||
1306 | ||||
1307 | return &enc20->enc10.base; | |||
1308 | } | |||
1309 | ||||
1310 | static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data) | |||
1311 | { | |||
1312 | struct dce_panel_cntl *panel_cntl = | |||
1313 | kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL(0x0001 | 0x0004)); | |||
1314 | ||||
1315 | if (!panel_cntl) | |||
1316 | return NULL((void *)0); | |||
1317 | ||||
1318 | dce_panel_cntl_construct(panel_cntl, | |||
1319 | init_data, | |||
1320 | &panel_cntl_regs[init_data->inst], | |||
1321 | &panel_cntl_shift, | |||
1322 | &panel_cntl_mask); | |||
1323 | ||||
1324 | return &panel_cntl->base; | |||
1325 | } | |||
1326 | ||||
1327 | static struct clock_source *dcn20_clock_source_create( | |||
1328 | struct dc_context *ctx, | |||
1329 | struct dc_bios *bios, | |||
1330 | enum clock_source_id id, | |||
1331 | const struct dce110_clk_src_regs *regs, | |||
1332 | bool_Bool dp_clk_src) | |||
1333 | { | |||
1334 | struct dce110_clk_src *clk_src = | |||
1335 | kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC0x0002); | |||
1336 | ||||
1337 | if (!clk_src) | |||
1338 | return NULL((void *)0); | |||
1339 | ||||
1340 | if (dcn20_clk_src_construct(clk_src, ctx, bios, id, | |||
1341 | regs, &cs_shift, &cs_mask)) { | |||
1342 | clk_src->base.dp_clk_src = dp_clk_src; | |||
1343 | return &clk_src->base; | |||
1344 | } | |||
1345 | ||||
1346 | kfree(clk_src); | |||
1347 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1347); do {} while (0); } while (0); | |||
1348 | return NULL((void *)0); | |||
1349 | } | |||
1350 | ||||
1351 | static void read_dce_straps( | |||
1352 | struct dc_context *ctx, | |||
1353 | struct resource_straps *straps) | |||
1354 | { | |||
1355 | generic_reg_get(ctx, mmDC_PINSTRAPS0x2880 + BASE(mmDC_PINSTRAPS_BASE_IDX)0x000034C0, | |||
1356 | FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO)0xe, 0x0000C000L, &straps->dc_pinstraps_audio); | |||
1357 | } | |||
1358 | ||||
1359 | static struct audio *dcn20_create_audio( | |||
1360 | struct dc_context *ctx, unsigned int inst) | |||
1361 | { | |||
1362 | return dce_audio_create(ctx, inst, | |||
1363 | &audio_regs[inst], &audio_shift, &audio_mask); | |||
1364 | } | |||
1365 | ||||
1366 | struct stream_encoder *dcn20_stream_encoder_create( | |||
1367 | enum engine_id eng_id, | |||
1368 | struct dc_context *ctx) | |||
1369 | { | |||
1370 | struct dcn10_stream_encoder *enc1 = | |||
1371 | kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL(0x0001 | 0x0004)); | |||
1372 | ||||
1373 | if (!enc1) | |||
1374 | return NULL((void *)0); | |||
1375 | ||||
1376 | if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)((ctx->asic_id.hw_internal_rev >= NV_NAVI14_M_A0) && (ctx->asic_id.hw_internal_rev < NV_UNKNOWN))) { | |||
1377 | if (eng_id >= ENGINE_ID_DIGD) | |||
1378 | eng_id++; | |||
1379 | } | |||
1380 | ||||
1381 | dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, | |||
1382 | &stream_enc_regs[eng_id], | |||
1383 | &se_shift, &se_mask); | |||
1384 | ||||
1385 | return &enc1->base; | |||
1386 | } | |||
1387 | ||||
1388 | static const struct dce_hwseq_registers hwseq_reg = { | |||
1389 | HWSEQ_DCN2_REG_LIST().REFCLK_CNTL = 0x000000C0 + 0x0049, .DCHUBBUB_GLOBAL_TIMER_CNTL = 0x000034C0 + 0x051f, .DIO_MEM_PWR_CTRL = 0x000034C0 + 0x1ede , .DCCG_GATE_DISABLE_CNTL = 0x000000C0 + 0x0074, .DCCG_GATE_DISABLE_CNTL2 = 0x000000C0 + 0x007c, .DCFCLK_CNTL = 0x000034C0 + 0x0530, . DCFCLK_CNTL = 0x000034C0 + 0x0530, .DC_MEM_GLOBAL_PWR_REQ_CNTL = 0x000000C0 + 0x0072, .PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0080 , .PHYPLL_PIXEL_RATE_CNTL[0] = 0x000000C0 + 0x0083, .PIXEL_RATE_CNTL [1] = 0x000000C0 + 0x0084, .PHYPLL_PIXEL_RATE_CNTL[1] = 0x000000C0 + 0x0087, .PIXEL_RATE_CNTL[2] = 0x000000C0 + 0x0088, .PHYPLL_PIXEL_RATE_CNTL [2] = 0x000000C0 + 0x008b, .PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008c, .PHYPLL_PIXEL_RATE_CNTL[3] = 0x000000C0 + 0x008f, .PIXEL_RATE_CNTL [4] = 0x000000C0 + 0x0090, .PHYPLL_PIXEL_RATE_CNTL[4] = 0x000000C0 + 0x0093, .PIXEL_RATE_CNTL[5] = 0x000000C0 + 0x0094, .PHYPLL_PIXEL_RATE_CNTL [5] = 0x000000C0 + 0x0097, .MICROSECOND_TIME_BASE_DIV = 0x000000C0 + 0x007b, .MILLISECOND_TIME_BASE_DIV = 0x000000C0 + 0x0070, . DISPCLK_FREQ_CHANGE_CNTL = 0x000000C0 + 0x0071, .RBBMIF_TIMEOUT_DIS = 0x000034C0 + 0x005f, .RBBMIF_TIMEOUT_DIS_2 = 0x000034C0 + 0x0060 , .DCHUBBUB_CRC_CTRL = 0x000034C0 + 0x04f1, .DPP_TOP0_DPP_CRC_CTRL = 0x000034C0 + 0x0cc9, .DPP_TOP0_DPP_CRC_VAL_B_A = 0x000034C0 + 0x0cc8, .DPP_TOP0_DPP_CRC_VAL_R_G = 0x000034C0 + 0x0cc7, . MPC_CRC_CTRL = 0x000034C0 + 0x134b, .MPC_CRC_RESULT_GB = 0x000034C0 + 0x134e, .MPC_CRC_RESULT_C = 0x000034C0 + 0x134f, .MPC_CRC_RESULT_AR = 0x000034C0 + 0x134d, .DOMAIN0_PG_CONFIG = 0x000034C0 + 0x0080 , .DOMAIN1_PG_CONFIG = 0x000034C0 + 0x0082, .DOMAIN2_PG_CONFIG = 0x000034C0 + 0x0084, .DOMAIN3_PG_CONFIG = 0x000034C0 + 0x0086 , .DOMAIN4_PG_CONFIG = 0x000034C0 + 0x0088, .DOMAIN5_PG_CONFIG = 0x000034C0 + 0x008a, .DOMAIN6_PG_CONFIG = 0x000034C0 + 0x008c , .DOMAIN7_PG_CONFIG = 0x000034C0 + 0x008e, .DOMAIN8_PG_CONFIG = 0x000034C0 + 0x0090, .DOMAIN9_PG_CONFIG = 0x000034C0 + 0x0092 , .DOMAIN16_PG_CONFIG = 0x000034C0 + 0x00a1, .DOMAIN17_PG_CONFIG = 0x000034C0 + 0x00a3, .DOMAIN18_PG_CONFIG = 0x000034C0 + 0x00a5 , .DOMAIN19_PG_CONFIG = 0x000034C0 + 0x00a7, .DOMAIN20_PG_CONFIG = 0x000034C0 + 0x00a9, .DOMAIN21_PG_CONFIG = 0x000034C0 + 0x00ab , .DOMAIN0_PG_STATUS = 0x000034C0 + 0x0081, .DOMAIN1_PG_STATUS = 0x000034C0 + 0x0083, .DOMAIN2_PG_STATUS = 0x000034C0 + 0x0085 , .DOMAIN3_PG_STATUS = 0x000034C0 + 0x0087, .DOMAIN4_PG_STATUS = 0x000034C0 + 0x0089, .DOMAIN5_PG_STATUS = 0x000034C0 + 0x008b , .DOMAIN6_PG_STATUS = 0x000034C0 + 0x008d, .DOMAIN7_PG_STATUS = 0x000034C0 + 0x008f, .DOMAIN8_PG_STATUS = 0x000034C0 + 0x0091 , .DOMAIN9_PG_STATUS = 0x000034C0 + 0x0093, .DOMAIN10_PG_STATUS = 0x000034C0 + 0x0095, .DOMAIN11_PG_STATUS = 0x000034C0 + 0x0097 , .DOMAIN16_PG_STATUS = 0x000034C0 + 0x00a2, .DOMAIN17_PG_STATUS = 0x000034C0 + 0x00a4, .DOMAIN18_PG_STATUS = 0x000034C0 + 0x00a6 , .DOMAIN19_PG_STATUS = 0x000034C0 + 0x00a8, .DOMAIN20_PG_STATUS = 0x000034C0 + 0x00aa, .DOMAIN21_PG_STATUS = 0x000034C0 + 0x00ac , .D1VGA_CONTROL = 0x000000C0 + 0x000c, .D2VGA_CONTROL = 0x000000C0 + 0x000e, .D3VGA_CONTROL = 0x000000C0 + 0x0038, .D4VGA_CONTROL = 0x000000C0 + 0x0039, .D5VGA_CONTROL = 0x000000C0 + 0x003a, .D6VGA_CONTROL = 0x000000C0 + 0x003b, .DC_IP_REQUEST_CNTL = 0x000034C0 + 0x00b2 | |||
1390 | }; | |||
1391 | ||||
1392 | static const struct dce_hwseq_shift hwseq_shift = { | |||
1393 | HWSEQ_DCN2_MASK_SH_LIST(__SHIFT).PIXEL_RATE_SOURCE = 0x0, .DP_DTO0_ENABLE = 0x4, .PHYPLL_PIXEL_RATE_SOURCE = 0x0, .DCHUBBUB_GLOBAL_TIMER_ENABLE = 0xc, .DCFCLK_GATE_DIS = 0x1f, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x0, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0, .DOMAIN0_POWER_FORCEON = 0x0, .DOMAIN0_POWER_GATE = 0x8 , .DOMAIN1_POWER_FORCEON = 0x0, .DOMAIN1_POWER_GATE = 0x8, .DOMAIN2_POWER_FORCEON = 0x0, .DOMAIN2_POWER_GATE = 0x8, .DOMAIN3_POWER_FORCEON = 0x0 , .DOMAIN3_POWER_GATE = 0x8, .DOMAIN4_POWER_FORCEON = 0x0, .DOMAIN4_POWER_GATE = 0x8, .DOMAIN5_POWER_FORCEON = 0x0, .DOMAIN5_POWER_GATE = 0x8 , .DOMAIN6_POWER_FORCEON = 0x0, .DOMAIN6_POWER_GATE = 0x8, .DOMAIN7_POWER_FORCEON = 0x0, .DOMAIN7_POWER_GATE = 0x8, .DOMAIN8_POWER_FORCEON = 0x0 , .DOMAIN8_POWER_GATE = 0x8, .DOMAIN9_POWER_FORCEON = 0x0, .DOMAIN9_POWER_GATE = 0x8, .DOMAIN10_POWER_FORCEON = 0x0, .DOMAIN10_POWER_GATE = 0x8, .DOMAIN11_POWER_FORCEON = 0x0, .DOMAIN11_POWER_GATE = 0x8 , .DOMAIN16_POWER_FORCEON = 0x0, .DOMAIN16_POWER_GATE = 0x8, . DOMAIN17_POWER_FORCEON = 0x0, .DOMAIN17_POWER_GATE = 0x8, .DOMAIN18_POWER_FORCEON = 0x0, .DOMAIN18_POWER_GATE = 0x8, .DOMAIN19_POWER_FORCEON = 0x0, .DOMAIN19_POWER_GATE = 0x8, .DOMAIN20_POWER_FORCEON = 0x0 , .DOMAIN20_POWER_GATE = 0x8, .DOMAIN21_POWER_FORCEON = 0x0, . DOMAIN21_POWER_GATE = 0x8, .DOMAIN0_PGFSM_PWR_STATUS = 0x1e, . DOMAIN1_PGFSM_PWR_STATUS = 0x1e, .DOMAIN2_PGFSM_PWR_STATUS = 0x1e , .DOMAIN3_PGFSM_PWR_STATUS = 0x1e, .DOMAIN4_PGFSM_PWR_STATUS = 0x1e, .DOMAIN5_PGFSM_PWR_STATUS = 0x1e, .DOMAIN6_PGFSM_PWR_STATUS = 0x1e, .DOMAIN7_PGFSM_PWR_STATUS = 0x1e, .DOMAIN8_PGFSM_PWR_STATUS = 0x1e, .DOMAIN9_PGFSM_PWR_STATUS = 0x1e, .DOMAIN10_PGFSM_PWR_STATUS = 0x1e, .DOMAIN11_PGFSM_PWR_STATUS = 0x1e, .DOMAIN16_PGFSM_PWR_STATUS = 0x1e, .DOMAIN17_PGFSM_PWR_STATUS = 0x1e, .DOMAIN18_PGFSM_PWR_STATUS = 0x1e, .DOMAIN19_PGFSM_PWR_STATUS = 0x1e, .DOMAIN20_PGFSM_PWR_STATUS = 0x1e, .DOMAIN21_PGFSM_PWR_STATUS = 0x1e, .IP_REQUEST_EN = 0x0 | |||
1394 | }; | |||
1395 | ||||
1396 | static const struct dce_hwseq_mask hwseq_mask = { | |||
1397 | HWSEQ_DCN2_MASK_SH_LIST(_MASK).PIXEL_RATE_SOURCE = 0x00000003L, .DP_DTO0_ENABLE = 0x00000010L , .PHYPLL_PIXEL_RATE_SOURCE = 0x00000007L, .DCHUBBUB_GLOBAL_TIMER_ENABLE = 0x00001000L, .DCFCLK_GATE_DIS = 0x80000000L, .DC_MEM_GLOBAL_PWR_REQ_DIS = 0x00000001L, .DCHUBBUB_GLOBAL_TIMER_REFDIV = 0x0000000FL, . DOMAIN0_POWER_FORCEON = 0x00000001L, .DOMAIN0_POWER_GATE = 0x00000100L , .DOMAIN1_POWER_FORCEON = 0x00000001L, .DOMAIN1_POWER_GATE = 0x00000100L, .DOMAIN2_POWER_FORCEON = 0x00000001L, .DOMAIN2_POWER_GATE = 0x00000100L, .DOMAIN3_POWER_FORCEON = 0x00000001L, .DOMAIN3_POWER_GATE = 0x00000100L, .DOMAIN4_POWER_FORCEON = 0x00000001L, .DOMAIN4_POWER_GATE = 0x00000100L, .DOMAIN5_POWER_FORCEON = 0x00000001L, .DOMAIN5_POWER_GATE = 0x00000100L, .DOMAIN6_POWER_FORCEON = 0x00000001L, .DOMAIN6_POWER_GATE = 0x00000100L, .DOMAIN7_POWER_FORCEON = 0x00000001L, .DOMAIN7_POWER_GATE = 0x00000100L, .DOMAIN8_POWER_FORCEON = 0x00000001L, .DOMAIN8_POWER_GATE = 0x00000100L, .DOMAIN9_POWER_FORCEON = 0x00000001L, .DOMAIN9_POWER_GATE = 0x00000100L, .DOMAIN10_POWER_FORCEON = 0x00000001L, .DOMAIN10_POWER_GATE = 0x00000100L, .DOMAIN11_POWER_FORCEON = 0x00000001L, .DOMAIN11_POWER_GATE = 0x00000100L, .DOMAIN16_POWER_FORCEON = 0x00000001L, .DOMAIN16_POWER_GATE = 0x00000100L, .DOMAIN17_POWER_FORCEON = 0x00000001L, .DOMAIN17_POWER_GATE = 0x00000100L, .DOMAIN18_POWER_FORCEON = 0x00000001L, .DOMAIN18_POWER_GATE = 0x00000100L, .DOMAIN19_POWER_FORCEON = 0x00000001L, .DOMAIN19_POWER_GATE = 0x00000100L, .DOMAIN20_POWER_FORCEON = 0x00000001L, .DOMAIN20_POWER_GATE = 0x00000100L, .DOMAIN21_POWER_FORCEON = 0x00000001L, .DOMAIN21_POWER_GATE = 0x00000100L, .DOMAIN0_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN1_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN2_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN3_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN4_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN5_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN6_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN7_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN8_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN9_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN10_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN11_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN16_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN17_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN18_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN19_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN20_PGFSM_PWR_STATUS = 0xC0000000L, .DOMAIN21_PGFSM_PWR_STATUS = 0xC0000000L, .IP_REQUEST_EN = 0x00000001L | |||
1398 | }; | |||
1399 | ||||
1400 | struct dce_hwseq *dcn20_hwseq_create( | |||
1401 | struct dc_context *ctx) | |||
1402 | { | |||
1403 | struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL(0x0001 | 0x0004)); | |||
1404 | ||||
1405 | if (hws) { | |||
1406 | hws->ctx = ctx; | |||
1407 | hws->regs = &hwseq_reg; | |||
1408 | hws->shifts = &hwseq_shift; | |||
1409 | hws->masks = &hwseq_mask; | |||
1410 | } | |||
1411 | return hws; | |||
1412 | } | |||
1413 | ||||
1414 | static const struct resource_create_funcs res_create_funcs = { | |||
1415 | .read_dce_straps = read_dce_straps, | |||
1416 | .create_audio = dcn20_create_audio, | |||
1417 | .create_stream_encoder = dcn20_stream_encoder_create, | |||
1418 | .create_hwseq = dcn20_hwseq_create, | |||
1419 | }; | |||
1420 | ||||
1421 | static const struct resource_create_funcs res_create_maximus_funcs = { | |||
1422 | .read_dce_straps = NULL((void *)0), | |||
1423 | .create_audio = NULL((void *)0), | |||
1424 | .create_stream_encoder = NULL((void *)0), | |||
1425 | .create_hwseq = dcn20_hwseq_create, | |||
1426 | }; | |||
1427 | ||||
1428 | static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); | |||
1429 | ||||
1430 | void dcn20_clock_source_destroy(struct clock_source **clk_src) | |||
1431 | { | |||
1432 | kfree(TO_DCE110_CLK_SRC(*clk_src)({ const __typeof( ((struct dce110_clk_src *)0)->base ) *__mptr = (*clk_src); (struct dce110_clk_src *)( (char *)__mptr - __builtin_offsetof (struct dce110_clk_src, base) );})); | |||
1433 | *clk_src = NULL((void *)0); | |||
1434 | } | |||
1435 | ||||
1436 | ||||
1437 | struct display_stream_compressor *dcn20_dsc_create( | |||
1438 | struct dc_context *ctx, uint32_t inst) | |||
1439 | { | |||
1440 | struct dcn20_dsc *dsc = | |||
1441 | kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC0x0002); | |||
1442 | ||||
1443 | if (!dsc) { | |||
1444 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1444); do {} while (0); } while (0); | |||
1445 | return NULL((void *)0); | |||
1446 | } | |||
1447 | ||||
1448 | dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); | |||
1449 | return &dsc->base; | |||
1450 | } | |||
1451 | ||||
1452 | void dcn20_dsc_destroy(struct display_stream_compressor **dsc) | |||
1453 | { | |||
1454 | kfree(container_of(*dsc, struct dcn20_dsc, base)({ const __typeof( ((struct dcn20_dsc *)0)->base ) *__mptr = (*dsc); (struct dcn20_dsc *)( (char *)__mptr - __builtin_offsetof (struct dcn20_dsc, base) );})); | |||
1455 | *dsc = NULL((void *)0); | |||
1456 | } | |||
1457 | ||||
1458 | ||||
1459 | static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) | |||
1460 | { | |||
1461 | unsigned int i; | |||
1462 | ||||
1463 | for (i = 0; i < pool->base.stream_enc_count; i++) { | |||
1464 | if (pool->base.stream_enc[i] != NULL((void *)0)) { | |||
1465 | kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])({ const __typeof( ((struct dcn10_stream_encoder *)0)->base ) *__mptr = (pool->base.stream_enc[i]); (struct dcn10_stream_encoder *)( (char *)__mptr - __builtin_offsetof(struct dcn10_stream_encoder , base) );})); | |||
1466 | pool->base.stream_enc[i] = NULL((void *)0); | |||
1467 | } | |||
1468 | } | |||
1469 | ||||
1470 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { | |||
1471 | if (pool->base.dscs[i] != NULL((void *)0)) | |||
1472 | dcn20_dsc_destroy(&pool->base.dscs[i]); | |||
1473 | } | |||
1474 | ||||
1475 | if (pool->base.mpc != NULL((void *)0)) { | |||
1476 | kfree(TO_DCN20_MPC(pool->base.mpc)({ const __typeof( ((struct dcn20_mpc *)0)->base ) *__mptr = (pool->base.mpc); (struct dcn20_mpc *)( (char *)__mptr - __builtin_offsetof(struct dcn20_mpc, base) );})); | |||
1477 | pool->base.mpc = NULL((void *)0); | |||
1478 | } | |||
1479 | if (pool->base.hubbub != NULL((void *)0)) { | |||
1480 | kfree(pool->base.hubbub); | |||
1481 | pool->base.hubbub = NULL((void *)0); | |||
1482 | } | |||
1483 | for (i = 0; i < pool->base.pipe_count; i++) { | |||
1484 | if (pool->base.dpps[i] != NULL((void *)0)) | |||
1485 | dcn20_dpp_destroy(&pool->base.dpps[i]); | |||
1486 | ||||
1487 | if (pool->base.ipps[i] != NULL((void *)0)) | |||
1488 | pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); | |||
1489 | ||||
1490 | if (pool->base.hubps[i] != NULL((void *)0)) { | |||
1491 | kfree(TO_DCN20_HUBP(pool->base.hubps[i])({ const __typeof( ((struct dcn20_hubp *)0)->base ) *__mptr = (pool->base.hubps[i]); (struct dcn20_hubp *)( (char *)__mptr - __builtin_offsetof(struct dcn20_hubp, base) );})); | |||
1492 | pool->base.hubps[i] = NULL((void *)0); | |||
1493 | } | |||
1494 | ||||
1495 | if (pool->base.irqs != NULL((void *)0)) { | |||
1496 | dal_irq_service_destroy(&pool->base.irqs); | |||
1497 | } | |||
1498 | } | |||
1499 | ||||
1500 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | |||
1501 | if (pool->base.engines[i] != NULL((void *)0)) | |||
1502 | dce110_engine_destroy(&pool->base.engines[i]); | |||
1503 | if (pool->base.hw_i2cs[i] != NULL((void *)0)) { | |||
1504 | kfree(pool->base.hw_i2cs[i]); | |||
1505 | pool->base.hw_i2cs[i] = NULL((void *)0); | |||
1506 | } | |||
1507 | if (pool->base.sw_i2cs[i] != NULL((void *)0)) { | |||
1508 | kfree(pool->base.sw_i2cs[i]); | |||
1509 | pool->base.sw_i2cs[i] = NULL((void *)0); | |||
1510 | } | |||
1511 | } | |||
1512 | ||||
1513 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | |||
1514 | if (pool->base.opps[i] != NULL((void *)0)) | |||
1515 | pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); | |||
1516 | } | |||
1517 | ||||
1518 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |||
1519 | if (pool->base.timing_generators[i] != NULL((void *)0)) { | |||
1520 | kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])({ const __typeof( ((struct optc *)0)->base ) *__mptr = (pool ->base.timing_generators[i]); (struct optc *)( (char *)__mptr - __builtin_offsetof(struct optc, base) );})); | |||
1521 | pool->base.timing_generators[i] = NULL((void *)0); | |||
1522 | } | |||
1523 | } | |||
1524 | ||||
1525 | for (i = 0; i < pool->base.res_cap->num_dwb; i++) { | |||
1526 | if (pool->base.dwbc[i] != NULL((void *)0)) { | |||
1527 | kfree(TO_DCN20_DWBC(pool->base.dwbc[i])({ const __typeof( ((struct dcn20_dwbc *)0)->base ) *__mptr = (pool->base.dwbc[i]); (struct dcn20_dwbc *)( (char *)__mptr - __builtin_offsetof(struct dcn20_dwbc, base) );})); | |||
1528 | pool->base.dwbc[i] = NULL((void *)0); | |||
1529 | } | |||
1530 | if (pool->base.mcif_wb[i] != NULL((void *)0)) { | |||
1531 | kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])({ const __typeof( ((struct dcn20_mmhubbub *)0)->base ) *__mptr = (pool->base.mcif_wb[i]); (struct dcn20_mmhubbub *)( (char *)__mptr - __builtin_offsetof(struct dcn20_mmhubbub, base) ) ;})); | |||
1532 | pool->base.mcif_wb[i] = NULL((void *)0); | |||
1533 | } | |||
1534 | } | |||
1535 | ||||
1536 | for (i = 0; i < pool->base.audio_count; i++) { | |||
1537 | if (pool->base.audios[i]) | |||
1538 | dce_aud_destroy(&pool->base.audios[i]); | |||
1539 | } | |||
1540 | ||||
1541 | for (i = 0; i < pool->base.clk_src_count; i++) { | |||
1542 | if (pool->base.clock_sources[i] != NULL((void *)0)) { | |||
1543 | dcn20_clock_source_destroy(&pool->base.clock_sources[i]); | |||
1544 | pool->base.clock_sources[i] = NULL((void *)0); | |||
1545 | } | |||
1546 | } | |||
1547 | ||||
1548 | if (pool->base.dp_clock_source != NULL((void *)0)) { | |||
1549 | dcn20_clock_source_destroy(&pool->base.dp_clock_source); | |||
1550 | pool->base.dp_clock_source = NULL((void *)0); | |||
1551 | } | |||
1552 | ||||
1553 | ||||
1554 | if (pool->base.abm != NULL((void *)0)) | |||
1555 | dce_abm_destroy(&pool->base.abm); | |||
1556 | ||||
1557 | if (pool->base.dmcu != NULL((void *)0)) | |||
1558 | dce_dmcu_destroy(&pool->base.dmcu); | |||
1559 | ||||
1560 | if (pool->base.dccg != NULL((void *)0)) | |||
1561 | dcn_dccg_destroy(&pool->base.dccg); | |||
1562 | ||||
1563 | if (pool->base.pp_smu != NULL((void *)0)) | |||
1564 | dcn20_pp_smu_destroy(&pool->base.pp_smu); | |||
1565 | ||||
1566 | if (pool->base.oem_device != NULL((void *)0)) | |||
1567 | dal_ddc_service_destroy(&pool->base.oem_device); | |||
1568 | } | |||
1569 | ||||
1570 | struct hubp *dcn20_hubp_create( | |||
1571 | struct dc_context *ctx, | |||
1572 | uint32_t inst) | |||
1573 | { | |||
1574 | struct dcn20_hubp *hubp2 = | |||
1575 | kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC0x0002); | |||
1576 | ||||
1577 | if (!hubp2) | |||
1578 | return NULL((void *)0); | |||
1579 | ||||
1580 | if (hubp2_construct(hubp2, ctx, inst, | |||
1581 | &hubp_regs[inst], &hubp_shift, &hubp_mask)) | |||
1582 | return &hubp2->base; | |||
1583 | ||||
1584 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1584); do {} while (0); } while (0); | |||
1585 | kfree(hubp2); | |||
1586 | return NULL((void *)0); | |||
1587 | } | |||
1588 | ||||
1589 | static void get_pixel_clock_parameters( | |||
1590 | struct pipe_ctx *pipe_ctx, | |||
1591 | struct pixel_clk_params *pixel_clk_params) | |||
1592 | { | |||
1593 | const struct dc_stream_state *stream = pipe_ctx->stream; | |||
1594 | struct pipe_ctx *odm_pipe; | |||
1595 | int opp_cnt = 1; | |||
1596 | ||||
1597 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) | |||
1598 | opp_cnt++; | |||
1599 | ||||
1600 | pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; | |||
1601 | pixel_clk_params->encoder_object_id = stream->link->link_enc->id; | |||
1602 | pixel_clk_params->signal_type = pipe_ctx->stream->signal; | |||
1603 | pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; | |||
1604 | /* TODO: un-hardcode*/ | |||
1605 | pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * | |||
1606 | LINK_RATE_REF_FREQ_IN_KHZ; | |||
1607 | pixel_clk_params->flags.ENABLE_SS = 0; | |||
1608 | pixel_clk_params->color_depth = | |||
1609 | stream->timing.display_color_depth; | |||
1610 | pixel_clk_params->flags.DISPLAY_BLANKED = 1; | |||
1611 | pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; | |||
1612 | ||||
1613 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) | |||
1614 | pixel_clk_params->color_depth = COLOR_DEPTH_888; | |||
1615 | ||||
1616 | if (opp_cnt == 4) | |||
1617 | pixel_clk_params->requested_pix_clk_100hz /= 4; | |||
1618 | else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) | |||
1619 | pixel_clk_params->requested_pix_clk_100hz /= 2; | |||
1620 | ||||
1621 | if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) | |||
1622 | pixel_clk_params->requested_pix_clk_100hz *= 2; | |||
1623 | ||||
1624 | } | |||
1625 | ||||
1626 | static void build_clamping_params(struct dc_stream_state *stream) | |||
1627 | { | |||
1628 | stream->clamping.clamping_level = CLAMPING_FULL_RANGE; | |||
1629 | stream->clamping.c_depth = stream->timing.display_color_depth; | |||
1630 | stream->clamping.pixel_encoding = stream->timing.pixel_encoding; | |||
1631 | } | |||
1632 | ||||
1633 | static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) | |||
1634 | { | |||
1635 | ||||
1636 | get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); | |||
1637 | ||||
1638 | pipe_ctx->clock_source->funcs->get_pix_clk_dividers( | |||
1639 | pipe_ctx->clock_source, | |||
1640 | &pipe_ctx->stream_res.pix_clk_params, | |||
1641 | &pipe_ctx->pll_settings); | |||
1642 | ||||
1643 | pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; | |||
1644 | ||||
1645 | resource_build_bit_depth_reduction_params(pipe_ctx->stream, | |||
1646 | &pipe_ctx->stream->bit_depth_params); | |||
1647 | build_clamping_params(pipe_ctx->stream); | |||
1648 | ||||
1649 | return DC_OK; | |||
1650 | } | |||
1651 | ||||
1652 | enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) | |||
1653 | { | |||
1654 | enum dc_status status = DC_OK; | |||
1655 | struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); | |||
1656 | ||||
1657 | if (!pipe_ctx) | |||
1658 | return DC_ERROR_UNEXPECTED; | |||
1659 | ||||
1660 | ||||
1661 | status = build_pipe_hw_param(pipe_ctx); | |||
1662 | ||||
1663 | return status; | |||
1664 | } | |||
1665 | ||||
1666 | ||||
1667 | void dcn20_acquire_dsc(const struct dc *dc, | |||
1668 | struct resource_context *res_ctx, | |||
1669 | struct display_stream_compressor **dsc, | |||
1670 | int pipe_idx) | |||
1671 | { | |||
1672 | int i; | |||
1673 | const struct resource_pool *pool = dc->res_pool; | |||
1674 | struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; | |||
1675 | ||||
1676 | ASSERT(*dsc == NULL)do { if (({ static int __warned; int __ret = !!(!(*dsc == ((void *)0))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(*dsc == ((void *)0))", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 1676); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* If this ASSERT fails, dsc was not released properly */ | |||
1677 | *dsc = NULL((void *)0); | |||
1678 | ||||
1679 | /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */ | |||
1680 | if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { | |||
1681 | *dsc = pool->dscs[pipe_idx]; | |||
1682 | res_ctx->is_dsc_acquired[pipe_idx] = true1; | |||
1683 | return; | |||
1684 | } | |||
1685 | ||||
1686 | /* Return old DSC to avoid the need for re-programming */ | |||
1687 | if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { | |||
1688 | *dsc = dsc_old; | |||
1689 | res_ctx->is_dsc_acquired[dsc_old->inst] = true1; | |||
1690 | return ; | |||
1691 | } | |||
1692 | ||||
1693 | /* Find first free DSC */ | |||
1694 | for (i = 0; i < pool->res_cap->num_dsc; i++) | |||
1695 | if (!res_ctx->is_dsc_acquired[i]) { | |||
1696 | *dsc = pool->dscs[i]; | |||
1697 | res_ctx->is_dsc_acquired[i] = true1; | |||
1698 | break; | |||
1699 | } | |||
1700 | } | |||
1701 | ||||
1702 | void dcn20_release_dsc(struct resource_context *res_ctx, | |||
1703 | const struct resource_pool *pool, | |||
1704 | struct display_stream_compressor **dsc) | |||
1705 | { | |||
1706 | int i; | |||
1707 | ||||
1708 | for (i = 0; i < pool->res_cap->num_dsc; i++) | |||
1709 | if (pool->dscs[i] == *dsc) { | |||
1710 | res_ctx->is_dsc_acquired[i] = false0; | |||
1711 | *dsc = NULL((void *)0); | |||
1712 | break; | |||
1713 | } | |||
1714 | } | |||
1715 | ||||
1716 | ||||
1717 | ||||
1718 | enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, | |||
1719 | struct dc_state *dc_ctx, | |||
1720 | struct dc_stream_state *dc_stream) | |||
1721 | { | |||
1722 | enum dc_status result = DC_OK; | |||
1723 | int i; | |||
1724 | ||||
1725 | /* Get a DSC if required and available */ | |||
1726 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
1727 | struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; | |||
1728 | ||||
1729 | if (pipe_ctx->stream != dc_stream) | |||
1730 | continue; | |||
1731 | ||||
1732 | if (pipe_ctx->stream_res.dsc) | |||
1733 | continue; | |||
1734 | ||||
1735 | dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); | |||
1736 | ||||
1737 | /* The number of DSCs can be less than the number of pipes */ | |||
1738 | if (!pipe_ctx->stream_res.dsc) { | |||
1739 | result = DC_NO_DSC_RESOURCE; | |||
1740 | } | |||
1741 | ||||
1742 | break; | |||
1743 | } | |||
1744 | ||||
1745 | return result; | |||
1746 | } | |||
1747 | ||||
1748 | ||||
1749 | static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, | |||
1750 | struct dc_state *new_ctx, | |||
1751 | struct dc_stream_state *dc_stream) | |||
1752 | { | |||
1753 | struct pipe_ctx *pipe_ctx = NULL((void *)0); | |||
1754 | int i; | |||
1755 | ||||
1756 | for (i = 0; i < MAX_PIPES6; i++) { | |||
1757 | if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { | |||
1758 | pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; | |||
1759 | ||||
1760 | if (pipe_ctx->stream_res.dsc) | |||
1761 | dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); | |||
1762 | } | |||
1763 | } | |||
1764 | ||||
1765 | if (!pipe_ctx) | |||
1766 | return DC_ERROR_UNEXPECTED; | |||
1767 | else | |||
1768 | return DC_OK; | |||
1769 | } | |||
1770 | ||||
1771 | ||||
1772 | enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) | |||
1773 | { | |||
1774 | enum dc_status result = DC_ERROR_UNEXPECTED; | |||
1775 | ||||
1776 | result = resource_map_pool_resources(dc, new_ctx, dc_stream); | |||
1777 | ||||
1778 | if (result == DC_OK) | |||
1779 | result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); | |||
1780 | ||||
1781 | /* Get a DSC if required and available */ | |||
1782 | if (result == DC_OK && dc_stream->timing.flags.DSC) | |||
1783 | result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); | |||
1784 | ||||
1785 | if (result == DC_OK) | |||
1786 | result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); | |||
1787 | ||||
1788 | return result; | |||
1789 | } | |||
1790 | ||||
1791 | ||||
1792 | enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) | |||
1793 | { | |||
1794 | enum dc_status result = DC_OK; | |||
1795 | ||||
1796 | result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); | |||
1797 | ||||
1798 | return result; | |||
1799 | } | |||
1800 | ||||
1801 | ||||
1802 | static void swizzle_to_dml_params( | |||
1803 | enum swizzle_mode_values swizzle, | |||
1804 | unsigned int *sw_mode) | |||
1805 | { | |||
1806 | switch (swizzle) { | |||
1807 | case DC_SW_LINEAR: | |||
1808 | *sw_mode = dm_sw_linear; | |||
1809 | break; | |||
1810 | case DC_SW_4KB_S: | |||
1811 | *sw_mode = dm_sw_4kb_s; | |||
1812 | break; | |||
1813 | case DC_SW_4KB_S_X: | |||
1814 | *sw_mode = dm_sw_4kb_s_x; | |||
1815 | break; | |||
1816 | case DC_SW_4KB_D: | |||
1817 | *sw_mode = dm_sw_4kb_d; | |||
1818 | break; | |||
1819 | case DC_SW_4KB_D_X: | |||
1820 | *sw_mode = dm_sw_4kb_d_x; | |||
1821 | break; | |||
1822 | case DC_SW_64KB_S: | |||
1823 | *sw_mode = dm_sw_64kb_s; | |||
1824 | break; | |||
1825 | case DC_SW_64KB_S_X: | |||
1826 | *sw_mode = dm_sw_64kb_s_x; | |||
1827 | break; | |||
1828 | case DC_SW_64KB_S_T: | |||
1829 | *sw_mode = dm_sw_64kb_s_t; | |||
1830 | break; | |||
1831 | case DC_SW_64KB_D: | |||
1832 | *sw_mode = dm_sw_64kb_d; | |||
1833 | break; | |||
1834 | case DC_SW_64KB_D_X: | |||
1835 | *sw_mode = dm_sw_64kb_d_x; | |||
1836 | break; | |||
1837 | case DC_SW_64KB_D_T: | |||
1838 | *sw_mode = dm_sw_64kb_d_t; | |||
1839 | break; | |||
1840 | case DC_SW_64KB_R_X: | |||
1841 | *sw_mode = dm_sw_64kb_r_x; | |||
1842 | break; | |||
1843 | case DC_SW_VAR_S: | |||
1844 | *sw_mode = dm_sw_var_s; | |||
1845 | break; | |||
1846 | case DC_SW_VAR_S_X: | |||
1847 | *sw_mode = dm_sw_var_s_x; | |||
1848 | break; | |||
1849 | case DC_SW_VAR_D: | |||
1850 | *sw_mode = dm_sw_var_d; | |||
1851 | break; | |||
1852 | case DC_SW_VAR_D_X: | |||
1853 | *sw_mode = dm_sw_var_d_x; | |||
1854 | break; | |||
1855 | case DC_SW_VAR_R_X: | |||
1856 | *sw_mode = dm_sw_var_r_x; | |||
1857 | break; | |||
1858 | default: | |||
1859 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 1859); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* Not supported */ | |||
1860 | break; | |||
1861 | } | |||
1862 | } | |||
1863 | ||||
1864 | bool_Bool dcn20_split_stream_for_odm( | |||
1865 | const struct dc *dc, | |||
1866 | struct resource_context *res_ctx, | |||
1867 | struct pipe_ctx *prev_odm_pipe, | |||
1868 | struct pipe_ctx *next_odm_pipe) | |||
1869 | { | |||
1870 | int pipe_idx = next_odm_pipe->pipe_idx; | |||
1871 | const struct resource_pool *pool = dc->res_pool; | |||
1872 | ||||
1873 | *next_odm_pipe = *prev_odm_pipe; | |||
1874 | ||||
1875 | next_odm_pipe->pipe_idx = pipe_idx; | |||
1876 | next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; | |||
1877 | next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; | |||
1878 | next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; | |||
1879 | next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; | |||
1880 | next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; | |||
1881 | next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; | |||
1882 | next_odm_pipe->stream_res.dsc = NULL((void *)0); | |||
1883 | if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { | |||
1884 | next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; | |||
1885 | next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; | |||
1886 | } | |||
1887 | prev_odm_pipe->next_odm_pipe = next_odm_pipe; | |||
1888 | next_odm_pipe->prev_odm_pipe = prev_odm_pipe; | |||
1889 | ASSERT(next_odm_pipe->top_pipe == NULL)do { if (({ static int __warned; int __ret = !!(!(next_odm_pipe ->top_pipe == ((void *)0))); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(next_odm_pipe->top_pipe == ((void *)0))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 1889); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1890 | ||||
1891 | if (prev_odm_pipe->plane_state) { | |||
1892 | struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; | |||
1893 | int new_width; | |||
1894 | ||||
1895 | /* HACTIVE halved for odm combine */ | |||
1896 | sd->h_active /= 2; | |||
1897 | /* Calculate new vp and recout for left pipe */ | |||
1898 | /* Need at least 16 pixels width per side */ | |||
1899 | if (sd->recout.x + 16 >= sd->h_active) | |||
1900 | return false0; | |||
1901 | new_width = sd->h_active - sd->recout.x; | |||
1902 | sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |||
1903 | sd->ratios.horz, sd->recout.width - new_width)); | |||
1904 | sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |||
1905 | sd->ratios.horz_c, sd->recout.width - new_width)); | |||
1906 | sd->recout.width = new_width; | |||
1907 | ||||
1908 | /* Calculate new vp and recout for right pipe */ | |||
1909 | sd = &next_odm_pipe->plane_res.scl_data; | |||
1910 | /* HACTIVE halved for odm combine */ | |||
1911 | sd->h_active /= 2; | |||
1912 | /* Need at least 16 pixels width per side */ | |||
1913 | if (new_width <= 16) | |||
1914 | return false0; | |||
1915 | new_width = sd->recout.width + sd->recout.x - sd->h_active; | |||
1916 | sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |||
1917 | sd->ratios.horz, sd->recout.width - new_width)); | |||
1918 | sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( | |||
1919 | sd->ratios.horz_c, sd->recout.width - new_width)); | |||
1920 | sd->recout.width = new_width; | |||
1921 | sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( | |||
1922 | sd->ratios.horz, sd->h_active - sd->recout.x)); | |||
1923 | sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( | |||
1924 | sd->ratios.horz_c, sd->h_active - sd->recout.x)); | |||
1925 | sd->recout.x = 0; | |||
1926 | } | |||
1927 | next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; | |||
1928 | if (next_odm_pipe->stream->timing.flags.DSC == 1) { | |||
1929 | dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); | |||
1930 | ASSERT(next_odm_pipe->stream_res.dsc)do { if (({ static int __warned; int __ret = !!(!(next_odm_pipe ->stream_res.dsc)); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(next_odm_pipe->stream_res.dsc)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 1930); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1931 | if (next_odm_pipe->stream_res.dsc == NULL((void *)0)) | |||
1932 | return false0; | |||
1933 | } | |||
1934 | ||||
1935 | return true1; | |||
1936 | } | |||
1937 | ||||
1938 | void dcn20_split_stream_for_mpc( | |||
1939 | struct resource_context *res_ctx, | |||
1940 | const struct resource_pool *pool, | |||
1941 | struct pipe_ctx *primary_pipe, | |||
1942 | struct pipe_ctx *secondary_pipe) | |||
1943 | { | |||
1944 | int pipe_idx = secondary_pipe->pipe_idx; | |||
1945 | struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; | |||
1946 | ||||
1947 | *secondary_pipe = *primary_pipe; | |||
1948 | secondary_pipe->bottom_pipe = sec_bot_pipe; | |||
1949 | ||||
1950 | secondary_pipe->pipe_idx = pipe_idx; | |||
1951 | secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; | |||
1952 | secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; | |||
1953 | secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; | |||
1954 | secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; | |||
1955 | secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; | |||
1956 | secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; | |||
1957 | secondary_pipe->stream_res.dsc = NULL((void *)0); | |||
1958 | if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { | |||
1959 | ASSERT(!secondary_pipe->bottom_pipe)do { if (({ static int __warned; int __ret = !!(!(!secondary_pipe ->bottom_pipe)); if (__ret && !__warned) { printf( "WARNING %s failed at %s:%d\n", "!(!secondary_pipe->bottom_pipe)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 1959); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1960 | secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; | |||
1961 | secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; | |||
1962 | } | |||
1963 | primary_pipe->bottom_pipe = secondary_pipe; | |||
1964 | secondary_pipe->top_pipe = primary_pipe; | |||
1965 | ||||
1966 | ASSERT(primary_pipe->plane_state)do { if (({ static int __warned; int __ret = !!(!(primary_pipe ->plane_state)); if (__ret && !__warned) { printf( "WARNING %s failed at %s:%d\n", "!(primary_pipe->plane_state)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 1966); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1967 | } | |||
1968 | ||||
1969 | void dcn20_populate_dml_writeback_from_context( | |||
1970 | struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) | |||
1971 | { | |||
1972 | int pipe_cnt, i; | |||
1973 | ||||
1974 | for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { | |||
1975 | struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; | |||
1976 | ||||
1977 | if (!res_ctx->pipe_ctx[i].stream) | |||
1978 | continue; | |||
1979 | ||||
1980 | /* Set writeback information */ | |||
1981 | pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true1) ? 1 : 0; | |||
1982 | pipes[pipe_cnt].dout.num_active_wb++; | |||
1983 | pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; | |||
1984 | pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; | |||
1985 | pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; | |||
1986 | pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; | |||
1987 | pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; | |||
1988 | pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; | |||
1989 | pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; | |||
1990 | pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; | |||
1991 | pipes[pipe_cnt].dout.wb.wb_hratio = 1.0; | |||
1992 | pipes[pipe_cnt].dout.wb.wb_vratio = 1.0; | |||
1993 | if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { | |||
1994 | if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) | |||
1995 | pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8; | |||
1996 | else | |||
1997 | pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10; | |||
1998 | } else | |||
1999 | pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32; | |||
2000 | ||||
2001 | pipe_cnt++; | |||
2002 | } | |||
2003 | ||||
2004 | } | |||
2005 | ||||
2006 | int dcn20_populate_dml_pipes_from_context( | |||
2007 | struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) | |||
2008 | { | |||
2009 | int pipe_cnt, i; | |||
2010 | bool_Bool synchronized_vblank = true1; | |||
2011 | struct resource_context *res_ctx = &context->res_ctx; | |||
2012 | ||||
2013 | for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { | |||
2014 | if (!res_ctx->pipe_ctx[i].stream) | |||
2015 | continue; | |||
2016 | ||||
2017 | if (pipe_cnt < 0) { | |||
2018 | pipe_cnt = i; | |||
2019 | continue; | |||
2020 | } | |||
2021 | ||||
2022 | if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream) | |||
2023 | continue; | |||
2024 | ||||
2025 | if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable( | |||
2026 | res_ctx->pipe_ctx[pipe_cnt].stream, | |||
2027 | res_ctx->pipe_ctx[i].stream)) { | |||
2028 | synchronized_vblank = false0; | |||
2029 | break; | |||
2030 | } | |||
2031 | } | |||
2032 | ||||
2033 | for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { | |||
2034 | struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; | |||
2035 | unsigned int v_total; | |||
2036 | unsigned int front_porch; | |||
2037 | int output_bpc; | |||
2038 | ||||
2039 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) | |||
2040 | struct audio_check aud_check = {0}; | |||
2041 | #endif | |||
2042 | if (!res_ctx->pipe_ctx[i].stream) | |||
2043 | continue; | |||
2044 | ||||
2045 | v_total = timing->v_total; | |||
2046 | front_porch = timing->v_front_porch; | |||
2047 | /* todo: | |||
2048 | pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; | |||
2049 | pipes[pipe_cnt].pipe.src.dcc = 0; | |||
2050 | pipes[pipe_cnt].pipe.src.vm = 0;*/ | |||
2051 | ||||
2052 | pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; | |||
2053 | ||||
2054 | pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC; | |||
2055 | /* todo: rotation?*/ | |||
2056 | pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; | |||
2057 | if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) { | |||
2058 | pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true1; | |||
2059 | /* 1/2 vblank */ | |||
2060 | pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active = | |||
2061 | (v_total - timing->v_addressable | |||
2062 | - timing->v_border_top - timing->v_border_bottom) / 2; | |||
2063 | /* 36 bytes dp, 32 hdmi */ | |||
2064 | pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes = | |||
2065 | dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32; | |||
2066 | } | |||
2067 | pipes[pipe_cnt].pipe.src.dcc = false0; | |||
2068 | pipes[pipe_cnt].pipe.src.dcc_rate = 1; | |||
2069 | pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank; | |||
2070 | pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch; | |||
2071 | pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start | |||
2072 | - timing->h_addressable | |||
2073 | - timing->h_border_left | |||
2074 | - timing->h_border_right; | |||
2075 | pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch; | |||
2076 | pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start | |||
2077 | - timing->v_addressable | |||
2078 | - timing->v_border_top | |||
2079 | - timing->v_border_bottom; | |||
2080 | pipes[pipe_cnt].pipe.dest.htotal = timing->h_total; | |||
2081 | pipes[pipe_cnt].pipe.dest.vtotal = v_total; | |||
2082 | pipes[pipe_cnt].pipe.dest.hactive = | |||
2083 | timing->h_addressable + timing->h_border_left + timing->h_border_right; | |||
2084 | pipes[pipe_cnt].pipe.dest.vactive = | |||
2085 | timing->v_addressable + timing->v_border_top + timing->v_border_bottom; | |||
2086 | pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE; | |||
2087 | pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0; | |||
2088 | if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) | |||
2089 | pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2; | |||
2090 | pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst; | |||
2091 | pipes[pipe_cnt].dout.dp_lanes = 4; | |||
2092 | pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min; | |||
2093 | pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max; | |||
2094 | switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) { | |||
2095 | case 1: | |||
2096 | pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1; | |||
2097 | break; | |||
2098 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) | |||
2099 | case 3: | |||
2100 | pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1; | |||
2101 | break; | |||
2102 | #endif | |||
2103 | default: | |||
2104 | pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled; | |||
2105 | } | |||
2106 | pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; | |||
2107 | if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state | |||
2108 | == res_ctx->pipe_ctx[i].plane_state) { | |||
2109 | struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; | |||
2110 | int split_idx = 0; | |||
2111 | ||||
2112 | while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state | |||
2113 | == res_ctx->pipe_ctx[i].plane_state) { | |||
2114 | first_pipe = first_pipe->top_pipe; | |||
2115 | split_idx++; | |||
2116 | } | |||
2117 | /* Treat 4to1 mpc combine as an mpo of 2 2-to-1 combines */ | |||
2118 | if (split_idx == 0) | |||
2119 | pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; | |||
2120 | else if (split_idx == 1) | |||
2121 | pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; | |||
2122 | else if (split_idx == 2) | |||
2123 | pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; | |||
2124 | } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) { | |||
2125 | struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe; | |||
2126 | ||||
2127 | while (first_pipe->prev_odm_pipe) | |||
2128 | first_pipe = first_pipe->prev_odm_pipe; | |||
2129 | pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; | |||
2130 | } | |||
2131 | ||||
2132 | switch (res_ctx->pipe_ctx[i].stream->signal) { | |||
2133 | case SIGNAL_TYPE_DISPLAY_PORT_MST: | |||
2134 | case SIGNAL_TYPE_DISPLAY_PORT: | |||
2135 | pipes[pipe_cnt].dout.output_type = dm_dp; | |||
2136 | break; | |||
2137 | case SIGNAL_TYPE_EDP: | |||
2138 | pipes[pipe_cnt].dout.output_type = dm_edp; | |||
2139 | break; | |||
2140 | case SIGNAL_TYPE_HDMI_TYPE_A: | |||
2141 | case SIGNAL_TYPE_DVI_SINGLE_LINK: | |||
2142 | case SIGNAL_TYPE_DVI_DUAL_LINK: | |||
2143 | pipes[pipe_cnt].dout.output_type = dm_hdmi; | |||
2144 | break; | |||
2145 | default: | |||
2146 | /* In case there is no signal, set dp with 4 lanes to allow max config */ | |||
2147 | pipes[pipe_cnt].dout.output_type = dm_dp; | |||
2148 | pipes[pipe_cnt].dout.dp_lanes = 4; | |||
2149 | } | |||
2150 | ||||
2151 | switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) { | |||
2152 | case COLOR_DEPTH_666: | |||
2153 | output_bpc = 6; | |||
2154 | break; | |||
2155 | case COLOR_DEPTH_888: | |||
2156 | output_bpc = 8; | |||
2157 | break; | |||
2158 | case COLOR_DEPTH_101010: | |||
2159 | output_bpc = 10; | |||
2160 | break; | |||
2161 | case COLOR_DEPTH_121212: | |||
2162 | output_bpc = 12; | |||
2163 | break; | |||
2164 | case COLOR_DEPTH_141414: | |||
2165 | output_bpc = 14; | |||
2166 | break; | |||
2167 | case COLOR_DEPTH_161616: | |||
2168 | output_bpc = 16; | |||
2169 | break; | |||
2170 | case COLOR_DEPTH_999: | |||
2171 | output_bpc = 9; | |||
2172 | break; | |||
2173 | case COLOR_DEPTH_111111: | |||
2174 | output_bpc = 11; | |||
2175 | break; | |||
2176 | default: | |||
2177 | output_bpc = 8; | |||
2178 | break; | |||
2179 | } | |||
2180 | ||||
2181 | switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) { | |||
2182 | case PIXEL_ENCODING_RGB: | |||
2183 | case PIXEL_ENCODING_YCBCR444: | |||
2184 | pipes[pipe_cnt].dout.output_format = dm_444; | |||
2185 | pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; | |||
2186 | break; | |||
2187 | case PIXEL_ENCODING_YCBCR420: | |||
2188 | pipes[pipe_cnt].dout.output_format = dm_420; | |||
2189 | pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2; | |||
2190 | break; | |||
2191 | case PIXEL_ENCODING_YCBCR422: | |||
2192 | if (true1) /* todo */ | |||
2193 | pipes[pipe_cnt].dout.output_format = dm_s422; | |||
2194 | else | |||
2195 | pipes[pipe_cnt].dout.output_format = dm_n422; | |||
2196 | pipes[pipe_cnt].dout.output_bpp = output_bpc * 2; | |||
2197 | break; | |||
2198 | default: | |||
2199 | pipes[pipe_cnt].dout.output_format = dm_444; | |||
2200 | pipes[pipe_cnt].dout.output_bpp = output_bpc * 3; | |||
2201 | } | |||
2202 | ||||
2203 | if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC) | |||
2204 | pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0; | |||
2205 | ||||
2206 | /* todo: default max for now, until there is logic reflecting this in dc*/ | |||
2207 | pipes[pipe_cnt].dout.output_bpc = 12; | |||
2208 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) | |||
2209 | /*fill up the audio sample rate (unit in kHz)*/ | |||
2210 | get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check); | |||
2211 | pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000; | |||
2212 | #endif | |||
2213 | /* | |||
2214 | * For graphic plane, cursor number is 1, nv12 is 0 | |||
2215 | * bw calculations due to cursor on/off | |||
2216 | */ | |||
2217 | if (res_ctx->pipe_ctx[i].plane_state && | |||
2218 | res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) | |||
2219 | pipes[pipe_cnt].pipe.src.num_cursors = 0; | |||
2220 | else | |||
2221 | pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors; | |||
2222 | ||||
2223 | pipes[pipe_cnt].pipe.src.cur0_src_width = 256; | |||
2224 | pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit; | |||
2225 | ||||
2226 | if (!res_ctx->pipe_ctx[i].plane_state) { | |||
2227 | pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; | |||
2228 | pipes[pipe_cnt].pipe.src.source_scan = dm_horz; | |||
2229 | pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s; | |||
2230 | pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile; | |||
2231 | pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; | |||
2232 | if (pipes[pipe_cnt].pipe.src.viewport_width > 1920) | |||
2233 | pipes[pipe_cnt].pipe.src.viewport_width = 1920; | |||
2234 | pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable; | |||
2235 | if (pipes[pipe_cnt].pipe.src.viewport_height > 1080) | |||
2236 | pipes[pipe_cnt].pipe.src.viewport_height = 1080; | |||
2237 | pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height; | |||
2238 | pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width; | |||
2239 | pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height; | |||
2240 | pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width; | |||
2241 | pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256; | |||
2242 | pipes[pipe_cnt].pipe.src.source_format = dm_444_32; | |||
2243 | pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/ | |||
2244 | pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/ | |||
2245 | pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/ | |||
2246 | pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/ | |||
2247 | pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; | |||
2248 | pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0; | |||
2249 | pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0; | |||
2250 | pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/ | |||
2251 | pipes[pipe_cnt].pipe.scale_taps.htaps = 1; | |||
2252 | pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; | |||
2253 | pipes[pipe_cnt].pipe.dest.vtotal_min = v_total; | |||
2254 | pipes[pipe_cnt].pipe.dest.vtotal_max = v_total; | |||
2255 | ||||
2256 | if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) { | |||
2257 | pipes[pipe_cnt].pipe.src.viewport_width /= 2; | |||
2258 | pipes[pipe_cnt].pipe.dest.recout_width /= 2; | |||
2259 | } | |||
2260 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) | |||
2261 | else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) { | |||
2262 | pipes[pipe_cnt].pipe.src.viewport_width /= 4; | |||
2263 | pipes[pipe_cnt].pipe.dest.recout_width /= 4; | |||
2264 | } | |||
2265 | #endif | |||
2266 | } else { | |||
2267 | struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; | |||
2268 | struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; | |||
2269 | ||||
2270 | pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; | |||
2271 | pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) | |||
2272 | || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) | |||
2273 | || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled; | |||
2274 | ||||
2275 | /* stereo is not split */ | |||
2276 | if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || | |||
2277 | pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { | |||
2278 | pipes[pipe_cnt].pipe.src.is_hsplit = false0; | |||
2279 | pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; | |||
2280 | } | |||
2281 | ||||
2282 | pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90 | |||
2283 | || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz; | |||
2284 | pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport_unadjusted.y; | |||
2285 | pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c_unadjusted.y; | |||
2286 | pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport_unadjusted.width; | |||
2287 | pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c_unadjusted.width; | |||
2288 | pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport_unadjusted.height; | |||
2289 | pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c_unadjusted.height; | |||
2290 | pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width; | |||
2291 | pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height; | |||
2292 | pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width; | |||
2293 | pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height; | |||
2294 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) | |||
2295 | if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA | |||
2296 | || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { | |||
2297 | #else | |||
2298 | if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { | |||
2299 | #endif | |||
2300 | pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; | |||
2301 | pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch; | |||
2302 | pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; | |||
2303 | pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c; | |||
2304 | } else { | |||
2305 | pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch; | |||
2306 | pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch; | |||
2307 | } | |||
2308 | pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable; | |||
2309 | pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width; | |||
2310 | pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height; | |||
2311 | pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height; | |||
2312 | pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; | |||
2313 | if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) | |||
2314 | pipes[pipe_cnt].pipe.dest.full_recout_width *= 2; | |||
2315 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) | |||
2316 | else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) | |||
2317 | pipes[pipe_cnt].pipe.dest.full_recout_width *= 4; | |||
2318 | #endif | |||
2319 | else { | |||
2320 | struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe; | |||
2321 | ||||
2322 | while (split_pipe && split_pipe->plane_state == pln) { | |||
2323 | pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; | |||
2324 | split_pipe = split_pipe->bottom_pipe; | |||
2325 | } | |||
2326 | split_pipe = res_ctx->pipe_ctx[i].top_pipe; | |||
2327 | while (split_pipe && split_pipe->plane_state == pln) { | |||
2328 | pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; | |||
2329 | split_pipe = split_pipe->top_pipe; | |||
2330 | } | |||
2331 | } | |||
2332 | ||||
2333 | pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16; | |||
2334 | pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32); | |||
2335 | pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32); | |||
2336 | pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32); | |||
2337 | pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32); | |||
2338 | pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = | |||
2339 | scl->ratios.vert.value != dc_fixpt_one.value | |||
2340 | || scl->ratios.horz.value != dc_fixpt_one.value | |||
2341 | || scl->ratios.vert_c.value != dc_fixpt_one.value | |||
2342 | || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/ | |||
2343 | || dc->debug.always_scale; /*support always scale*/ | |||
2344 | pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; | |||
2345 | pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c; | |||
2346 | pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; | |||
2347 | pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; | |||
2348 | ||||
2349 | pipes[pipe_cnt].pipe.src.macro_tile_size = | |||
2350 | swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); | |||
2351 | swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, | |||
2352 | &pipes[pipe_cnt].pipe.src.sw_mode); | |||
2353 | ||||
2354 | switch (pln->format) { | |||
2355 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: | |||
2356 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: | |||
2357 | pipes[pipe_cnt].pipe.src.source_format = dm_420_8; | |||
2358 | break; | |||
2359 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: | |||
2360 | case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: | |||
2361 | pipes[pipe_cnt].pipe.src.source_format = dm_420_10; | |||
2362 | break; | |||
2363 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: | |||
2364 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: | |||
2365 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: | |||
2366 | pipes[pipe_cnt].pipe.src.source_format = dm_444_64; | |||
2367 | break; | |||
2368 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: | |||
2369 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: | |||
2370 | pipes[pipe_cnt].pipe.src.source_format = dm_444_16; | |||
2371 | break; | |||
2372 | case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: | |||
2373 | pipes[pipe_cnt].pipe.src.source_format = dm_444_8; | |||
2374 | break; | |||
2375 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) | |||
2376 | case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: | |||
2377 | pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha; | |||
2378 | break; | |||
2379 | #endif | |||
2380 | default: | |||
2381 | pipes[pipe_cnt].pipe.src.source_format = dm_444_32; | |||
2382 | break; | |||
2383 | } | |||
2384 | } | |||
2385 | ||||
2386 | pipe_cnt++; | |||
2387 | } | |||
2388 | ||||
2389 | /* populate writeback information */ | |||
2390 | dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes); | |||
2391 | ||||
2392 | return pipe_cnt; | |||
2393 | } | |||
2394 | ||||
2395 | unsigned int dcn20_calc_max_scaled_time( | |||
2396 | unsigned int time_per_pixel, | |||
2397 | enum mmhubbub_wbif_mode mode, | |||
2398 | unsigned int urgent_watermark) | |||
2399 | { | |||
2400 | unsigned int time_per_byte = 0; | |||
2401 | unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ | |||
2402 | unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ | |||
2403 | unsigned int small_free_entry, max_free_entry; | |||
2404 | unsigned int buf_lh_capability; | |||
2405 | unsigned int max_scaled_time; | |||
2406 | ||||
2407 | if (mode == PACKED_444) /* packed mode */ | |||
2408 | time_per_byte = time_per_pixel/4; | |||
2409 | else if (mode == PLANAR_420_8BPC) | |||
2410 | time_per_byte = time_per_pixel; | |||
2411 | else if (mode == PLANAR_420_10BPC) /* p010 */ | |||
2412 | time_per_byte = time_per_pixel * 819/1024; | |||
2413 | ||||
2414 | if (time_per_byte == 0) | |||
2415 | time_per_byte = 1; | |||
2416 | ||||
2417 | small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; | |||
2418 | max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; | |||
2419 | buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ | |||
2420 | max_scaled_time = buf_lh_capability - urgent_watermark; | |||
2421 | return max_scaled_time; | |||
2422 | } | |||
2423 | ||||
2424 | void dcn20_set_mcif_arb_params( | |||
2425 | struct dc *dc, | |||
2426 | struct dc_state *context, | |||
2427 | display_e2e_pipe_params_st *pipes, | |||
2428 | int pipe_cnt) | |||
2429 | { | |||
2430 | enum mmhubbub_wbif_mode wbif_mode; | |||
2431 | struct mcif_arb_params *wb_arb_params; | |||
2432 | int i, j, k, dwb_pipe; | |||
2433 | ||||
2434 | /* Writeback MCIF_WB arbitration parameters */ | |||
2435 | dwb_pipe = 0; | |||
2436 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2437 | ||||
2438 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
2439 | continue; | |||
2440 | ||||
2441 | for (j = 0; j < MAX_DWB_PIPES1; j++) { | |||
2442 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false0) | |||
2443 | continue; | |||
2444 | ||||
2445 | //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; | |||
2446 | wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; | |||
2447 | ||||
2448 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { | |||
2449 | if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) | |||
2450 | wbif_mode = PLANAR_420_8BPC; | |||
2451 | else | |||
2452 | wbif_mode = PLANAR_420_10BPC; | |||
2453 | } else | |||
2454 | wbif_mode = PACKED_444; | |||
2455 | ||||
2456 | for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { | |||
2457 | wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
2458 | wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
2459 | } | |||
2460 | wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */ | |||
2461 | wb_arb_params->slice_lines = 32; | |||
2462 | wb_arb_params->arbitration_slice = 2; | |||
2463 | wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, | |||
2464 | wbif_mode, | |||
2465 | wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ | |||
2466 | ||||
2467 | dwb_pipe++; | |||
2468 | ||||
2469 | if (dwb_pipe >= MAX_DWB_PIPES1) | |||
2470 | return; | |||
2471 | } | |||
2472 | if (dwb_pipe >= MAX_DWB_PIPES1) | |||
2473 | return; | |||
2474 | } | |||
2475 | } | |||
2476 | ||||
2477 | bool_Bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) | |||
2478 | { | |||
2479 | int i; | |||
2480 | ||||
2481 | /* Validate DSC config, dsc count validation is already done */ | |||
2482 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2483 | struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; | |||
2484 | struct dc_stream_state *stream = pipe_ctx->stream; | |||
2485 | struct dsc_config dsc_cfg; | |||
2486 | struct pipe_ctx *odm_pipe; | |||
2487 | int opp_cnt = 1; | |||
2488 | ||||
2489 | for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) | |||
2490 | opp_cnt++; | |||
2491 | ||||
2492 | /* Only need to validate top pipe */ | |||
2493 | if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) | |||
2494 | continue; | |||
2495 | ||||
2496 | dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left | |||
2497 | + stream->timing.h_border_right) / opp_cnt; | |||
2498 | dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top | |||
2499 | + stream->timing.v_border_bottom; | |||
2500 | dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; | |||
2501 | dsc_cfg.color_depth = stream->timing.display_color_depth; | |||
2502 | dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true1 : false0; | |||
2503 | dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; | |||
2504 | dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; | |||
2505 | ||||
2506 | if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) | |||
2507 | return false0; | |||
2508 | } | |||
2509 | return true1; | |||
2510 | } | |||
2511 | ||||
2512 | struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, | |||
2513 | struct resource_context *res_ctx, | |||
2514 | const struct resource_pool *pool, | |||
2515 | const struct pipe_ctx *primary_pipe) | |||
2516 | { | |||
2517 | struct pipe_ctx *secondary_pipe = NULL((void *)0); | |||
2518 | ||||
2519 | if (dc && primary_pipe) { | |||
2520 | int j; | |||
2521 | int preferred_pipe_idx = 0; | |||
2522 | ||||
2523 | /* first check the prev dc state: | |||
2524 | * if this primary pipe has a bottom pipe in prev. state | |||
2525 | * and if the bottom pipe is still available (which it should be), | |||
2526 | * pick that pipe as secondary | |||
2527 | * Same logic applies for ODM pipes | |||
2528 | */ | |||
2529 | if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { | |||
2530 | preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; | |||
2531 | if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL((void *)0)) { | |||
2532 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; | |||
2533 | secondary_pipe->pipe_idx = preferred_pipe_idx; | |||
2534 | } | |||
2535 | } | |||
2536 | if (secondary_pipe == NULL((void *)0) && | |||
2537 | dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { | |||
2538 | preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; | |||
2539 | if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL((void *)0)) { | |||
2540 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; | |||
2541 | secondary_pipe->pipe_idx = preferred_pipe_idx; | |||
2542 | } | |||
2543 | } | |||
2544 | ||||
2545 | /* | |||
2546 | * if this primary pipe does not have a bottom pipe in prev. state | |||
2547 | * start backward and find a pipe that did not used to be a bottom pipe in | |||
2548 | * prev. dc state. This way we make sure we keep the same assignment as | |||
2549 | * last state and will not have to reprogram every pipe | |||
2550 | */ | |||
2551 | if (secondary_pipe == NULL((void *)0)) { | |||
2552 | for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { | |||
2553 | if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL((void *)0) | |||
2554 | && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL((void *)0)) { | |||
2555 | preferred_pipe_idx = j; | |||
2556 | ||||
2557 | if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL((void *)0)) { | |||
2558 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; | |||
2559 | secondary_pipe->pipe_idx = preferred_pipe_idx; | |||
2560 | break; | |||
2561 | } | |||
2562 | } | |||
2563 | } | |||
2564 | } | |||
2565 | /* | |||
2566 | * We should never hit this assert unless assignments are shuffled around | |||
2567 | * if this happens we will prob. hit a vsync tdr | |||
2568 | */ | |||
2569 | ASSERT(secondary_pipe)do { if (({ static int __warned; int __ret = !!(!(secondary_pipe )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(secondary_pipe)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2569); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
2570 | /* | |||
2571 | * search backwards for the second pipe to keep pipe | |||
2572 | * assignment more consistent | |||
2573 | */ | |||
2574 | if (secondary_pipe == NULL((void *)0)) { | |||
2575 | for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { | |||
2576 | preferred_pipe_idx = j; | |||
2577 | ||||
2578 | if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL((void *)0)) { | |||
2579 | secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; | |||
2580 | secondary_pipe->pipe_idx = preferred_pipe_idx; | |||
2581 | break; | |||
2582 | } | |||
2583 | } | |||
2584 | } | |||
2585 | } | |||
2586 | ||||
2587 | return secondary_pipe; | |||
2588 | } | |||
2589 | ||||
2590 | static void dcn20_merge_pipes_for_validate( | |||
2591 | struct dc *dc, | |||
2592 | struct dc_state *context) | |||
2593 | { | |||
2594 | int i; | |||
2595 | ||||
2596 | /* merge previously split odm pipes since mode support needs to make the decision */ | |||
2597 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2598 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
2599 | struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; | |||
2600 | ||||
2601 | if (pipe->prev_odm_pipe) | |||
2602 | continue; | |||
2603 | ||||
2604 | pipe->next_odm_pipe = NULL((void *)0); | |||
2605 | while (odm_pipe) { | |||
2606 | struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; | |||
2607 | ||||
2608 | odm_pipe->plane_state = NULL((void *)0); | |||
2609 | odm_pipe->stream = NULL((void *)0); | |||
2610 | odm_pipe->top_pipe = NULL((void *)0); | |||
2611 | odm_pipe->bottom_pipe = NULL((void *)0); | |||
2612 | odm_pipe->prev_odm_pipe = NULL((void *)0); | |||
2613 | odm_pipe->next_odm_pipe = NULL((void *)0); | |||
2614 | if (odm_pipe->stream_res.dsc) | |||
2615 | dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); | |||
2616 | /* Clear plane_res and stream_res */ | |||
2617 | memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res))__builtin_memset((&odm_pipe->plane_res), (0), (sizeof( odm_pipe->plane_res))); | |||
2618 | memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res))__builtin_memset((&odm_pipe->stream_res), (0), (sizeof (odm_pipe->stream_res))); | |||
2619 | odm_pipe = next_odm_pipe; | |||
2620 | } | |||
2621 | if (pipe->plane_state) | |||
2622 | resource_build_scaling_params(pipe); | |||
2623 | } | |||
2624 | ||||
2625 | /* merge previously mpc split pipes since mode support needs to make the decision */ | |||
2626 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2627 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
2628 | struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; | |||
2629 | ||||
2630 | if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) | |||
2631 | continue; | |||
2632 | ||||
2633 | pipe->bottom_pipe = hsplit_pipe->bottom_pipe; | |||
2634 | if (hsplit_pipe->bottom_pipe) | |||
2635 | hsplit_pipe->bottom_pipe->top_pipe = pipe; | |||
2636 | hsplit_pipe->plane_state = NULL((void *)0); | |||
2637 | hsplit_pipe->stream = NULL((void *)0); | |||
2638 | hsplit_pipe->top_pipe = NULL((void *)0); | |||
2639 | hsplit_pipe->bottom_pipe = NULL((void *)0); | |||
2640 | ||||
2641 | /* Clear plane_res and stream_res */ | |||
2642 | memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res))__builtin_memset((&hsplit_pipe->plane_res), (0), (sizeof (hsplit_pipe->plane_res))); | |||
2643 | memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res))__builtin_memset((&hsplit_pipe->stream_res), (0), (sizeof (hsplit_pipe->stream_res))); | |||
2644 | if (pipe->plane_state) | |||
2645 | resource_build_scaling_params(pipe); | |||
2646 | } | |||
2647 | } | |||
2648 | ||||
2649 | int dcn20_validate_apply_pipe_split_flags( | |||
2650 | struct dc *dc, | |||
2651 | struct dc_state *context, | |||
2652 | int vlevel, | |||
2653 | int *split, | |||
2654 | bool_Bool *merge) | |||
2655 | { | |||
2656 | int i, pipe_idx, vlevel_split; | |||
2657 | int plane_count = 0; | |||
2658 | bool_Bool force_split = false0; | |||
2659 | bool_Bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; | |||
2660 | struct vba_vars_st *v = &context->bw_ctx.dml.vba; | |||
2661 | int max_mpc_comb = v->maxMpcComb; | |||
2662 | ||||
2663 | if (context->stream_count > 1) { | |||
2664 | if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) | |||
2665 | avoid_split = true1; | |||
2666 | } else if (dc->debug.force_single_disp_pipe_split) | |||
2667 | force_split = true1; | |||
2668 | ||||
2669 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2670 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
2671 | ||||
2672 | /** | |||
2673 | * Workaround for avoiding pipe-split in cases where we'd split | |||
2674 | * planes that are too small, resulting in splits that aren't | |||
2675 | * valid for the scaler. | |||
2676 | */ | |||
2677 | if (pipe->plane_state && | |||
2678 | (pipe->plane_state->dst_rect.width <= 16 || | |||
2679 | pipe->plane_state->dst_rect.height <= 16 || | |||
2680 | pipe->plane_state->src_rect.width <= 16 || | |||
2681 | pipe->plane_state->src_rect.height <= 16)) | |||
2682 | avoid_split = true1; | |||
2683 | ||||
2684 | /* TODO: fix dc bugs and remove this split threshold thing */ | |||
2685 | if (pipe->stream && !pipe->prev_odm_pipe && | |||
2686 | (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) | |||
2687 | ++plane_count; | |||
2688 | } | |||
2689 | if (plane_count > dc->res_pool->pipe_count / 2) | |||
2690 | avoid_split = true1; | |||
2691 | ||||
2692 | /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ | |||
2693 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
2694 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
2695 | struct dc_crtc_timing timing; | |||
2696 | ||||
2697 | if (!pipe->stream) | |||
2698 | continue; | |||
2699 | else { | |||
2700 | timing = pipe->stream->timing; | |||
2701 | if (timing.h_border_left + timing.h_border_right | |||
2702 | + timing.v_border_top + timing.v_border_bottom > 0) { | |||
2703 | avoid_split = true1; | |||
2704 | break; | |||
2705 | } | |||
2706 | } | |||
2707 | } | |||
2708 | ||||
2709 | /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ | |||
2710 | if (avoid_split) { | |||
2711 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
2712 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
2713 | continue; | |||
2714 | ||||
2715 | for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) | |||
2716 | if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && | |||
2717 | v->ModeSupport[vlevel][0]) | |||
2718 | break; | |||
2719 | /* Impossible to not split this pipe */ | |||
2720 | if (vlevel > context->bw_ctx.dml.soc.num_states) | |||
2721 | vlevel = vlevel_split; | |||
2722 | else | |||
2723 | max_mpc_comb = 0; | |||
2724 | pipe_idx++; | |||
2725 | } | |||
2726 | v->maxMpcComb = max_mpc_comb; | |||
2727 | } | |||
2728 | ||||
2729 | /* Split loop sets which pipe should be split based on dml outputs and dc flags */ | |||
2730 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
2731 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
2732 | int pipe_plane = v->pipe_plane[pipe_idx]; | |||
2733 | bool_Bool split4mpc = context->stream_count == 1 && plane_count == 1 | |||
2734 | && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4; | |||
2735 | ||||
2736 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
2737 | continue; | |||
2738 | ||||
2739 | if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) | |||
2740 | split[i] = 4; | |||
2741 | else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) | |||
2742 | split[i] = 2; | |||
2743 | ||||
2744 | if ((pipe->stream->view_format == | |||
2745 | VIEW_3D_FORMAT_SIDE_BY_SIDE || | |||
2746 | pipe->stream->view_format == | |||
2747 | VIEW_3D_FORMAT_TOP_AND_BOTTOM) && | |||
2748 | (pipe->stream->timing.timing_3d_format == | |||
2749 | TIMING_3D_FORMAT_TOP_AND_BOTTOM || | |||
2750 | pipe->stream->timing.timing_3d_format == | |||
2751 | TIMING_3D_FORMAT_SIDE_BY_SIDE)) | |||
2752 | split[i] = 2; | |||
2753 | if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { | |||
2754 | split[i] = 2; | |||
2755 | v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; | |||
2756 | } | |||
2757 | #if defined(CONFIG_DRM_AMD_DC_DCN3_01) | |||
2758 | if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) { | |||
2759 | split[i] = 4; | |||
2760 | v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; | |||
2761 | } | |||
2762 | /*420 format workaround*/ | |||
2763 | if (pipe->stream->timing.h_addressable > 7680 && | |||
2764 | pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { | |||
2765 | split[i] = 4; | |||
2766 | } | |||
2767 | #endif | |||
2768 | v->ODMCombineEnabled[pipe_plane] = | |||
2769 | v->ODMCombineEnablePerState[vlevel][pipe_plane]; | |||
2770 | ||||
2771 | if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { | |||
2772 | if (get_num_mpc_splits(pipe) == 1) { | |||
2773 | /*If need split for mpc but 2 way split already*/ | |||
2774 | if (split[i] == 4) | |||
2775 | split[i] = 2; /* 2 -> 4 MPC */ | |||
2776 | else if (split[i] == 2) | |||
2777 | split[i] = 0; /* 2 -> 2 MPC */ | |||
2778 | else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) | |||
2779 | merge[i] = true1; /* 2 -> 1 MPC */ | |||
2780 | } else if (get_num_mpc_splits(pipe) == 3) { | |||
2781 | /*If need split for mpc but 4 way split already*/ | |||
2782 | if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) | |||
2783 | || !pipe->bottom_pipe)) { | |||
2784 | merge[i] = true1; /* 4 -> 2 MPC */ | |||
2785 | } else if (split[i] == 0 && pipe->top_pipe && | |||
2786 | pipe->top_pipe->plane_state == pipe->plane_state) | |||
2787 | merge[i] = true1; /* 4 -> 1 MPC */ | |||
2788 | split[i] = 0; | |||
2789 | } else if (get_num_odm_splits(pipe)) { | |||
2790 | /* ODM -> MPC transition */ | |||
2791 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2791); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* NOT expected yet */ | |||
2792 | if (pipe->prev_odm_pipe) { | |||
2793 | split[i] = 0; | |||
2794 | merge[i] = true1; | |||
2795 | } | |||
2796 | } | |||
2797 | } else { | |||
2798 | if (get_num_odm_splits(pipe) == 1) { | |||
2799 | /*If need split for odm but 2 way split already*/ | |||
2800 | if (split[i] == 4) | |||
2801 | split[i] = 2; /* 2 -> 4 ODM */ | |||
2802 | else if (split[i] == 2) | |||
2803 | split[i] = 0; /* 2 -> 2 ODM */ | |||
2804 | else if (pipe->prev_odm_pipe) { | |||
2805 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2805); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* NOT expected yet */ | |||
2806 | merge[i] = true1; /* exit ODM */ | |||
2807 | } | |||
2808 | } else if (get_num_odm_splits(pipe) == 3) { | |||
2809 | /*If need split for odm but 4 way split already*/ | |||
2810 | if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe) | |||
2811 | || !pipe->next_odm_pipe)) { | |||
2812 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2812); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* NOT expected yet */ | |||
2813 | merge[i] = true1; /* 4 -> 2 ODM */ | |||
2814 | } else if (split[i] == 0 && pipe->prev_odm_pipe) { | |||
2815 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2815); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* NOT expected yet */ | |||
2816 | merge[i] = true1; /* exit ODM */ | |||
2817 | } | |||
2818 | split[i] = 0; | |||
2819 | } else if (get_num_mpc_splits(pipe)) { | |||
2820 | /* MPC -> ODM transition */ | |||
2821 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2821); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); /* NOT expected yet */ | |||
2822 | if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { | |||
2823 | split[i] = 0; | |||
2824 | merge[i] = true1; | |||
2825 | } | |||
2826 | } | |||
2827 | } | |||
2828 | ||||
2829 | /* Adjust dppclk when split is forced, do not bother with dispclk */ | |||
2830 | if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) | |||
2831 | v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2; | |||
2832 | pipe_idx++; | |||
2833 | } | |||
2834 | ||||
2835 | return vlevel; | |||
2836 | } | |||
2837 | ||||
2838 | bool_Bool dcn20_fast_validate_bw( | |||
2839 | struct dc *dc, | |||
2840 | struct dc_state *context, | |||
2841 | display_e2e_pipe_params_st *pipes, | |||
2842 | int *pipe_cnt_out, | |||
2843 | int *pipe_split_from, | |||
2844 | int *vlevel_out) | |||
2845 | { | |||
2846 | bool_Bool out = false0; | |||
2847 | int split[MAX_PIPES6] = { 0 }; | |||
2848 | int pipe_cnt, i, pipe_idx, vlevel; | |||
2849 | ||||
2850 | ASSERT(pipes)do { if (({ static int __warned; int __ret = !!(!(pipes)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipes)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2850); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
2851 | if (!pipes) | |||
2852 | return false0; | |||
2853 | ||||
2854 | dcn20_merge_pipes_for_validate(dc, context); | |||
2855 | ||||
2856 | pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes); | |||
2857 | ||||
2858 | *pipe_cnt_out = pipe_cnt; | |||
2859 | ||||
2860 | if (!pipe_cnt) { | |||
2861 | out = true1; | |||
2862 | goto validate_out; | |||
2863 | } | |||
2864 | ||||
2865 | vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); | |||
2866 | ||||
2867 | if (vlevel > context->bw_ctx.dml.soc.num_states) | |||
2868 | goto validate_fail; | |||
2869 | ||||
2870 | vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL((void *)0)); | |||
2871 | ||||
2872 | /*initialize pipe_just_split_from to invalid idx*/ | |||
2873 | for (i = 0; i < MAX_PIPES6; i++) | |||
2874 | pipe_split_from[i] = -1; | |||
2875 | ||||
2876 | for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { | |||
2877 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; | |||
2878 | struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; | |||
2879 | ||||
2880 | if (!pipe->stream || pipe_split_from[i] >= 0) | |||
2881 | continue; | |||
2882 | ||||
2883 | pipe_idx++; | |||
2884 | ||||
2885 | if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { | |||
2886 | hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); | |||
2887 | ASSERT(hsplit_pipe)do { if (({ static int __warned; int __ret = !!(!(hsplit_pipe )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(hsplit_pipe)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2887); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
2888 | if (!dcn20_split_stream_for_odm( | |||
2889 | dc, &context->res_ctx, | |||
2890 | pipe, hsplit_pipe)) | |||
2891 | goto validate_fail; | |||
2892 | pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; | |||
2893 | dcn20_build_mapped_resource(dc, context, pipe->stream); | |||
2894 | } | |||
2895 | ||||
2896 | if (!pipe->plane_state) | |||
2897 | continue; | |||
2898 | /* Skip 2nd half of already split pipe */ | |||
2899 | if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) | |||
2900 | continue; | |||
2901 | ||||
2902 | /* We do not support mpo + odm at the moment */ | |||
2903 | if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state | |||
2904 | && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) | |||
2905 | goto validate_fail; | |||
2906 | ||||
2907 | if (split[i] == 2) { | |||
2908 | if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { | |||
2909 | /* pipe not split previously needs split */ | |||
2910 | hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); | |||
2911 | ASSERT(hsplit_pipe)do { if (({ static int __warned; int __ret = !!(!(hsplit_pipe )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(hsplit_pipe)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2911); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
2912 | if (!hsplit_pipe) { | |||
2913 | context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; | |||
2914 | continue; | |||
2915 | } | |||
2916 | if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { | |||
2917 | if (!dcn20_split_stream_for_odm( | |||
2918 | dc, &context->res_ctx, | |||
2919 | pipe, hsplit_pipe)) | |||
2920 | goto validate_fail; | |||
2921 | dcn20_build_mapped_resource(dc, context, pipe->stream); | |||
2922 | } else { | |||
2923 | dcn20_split_stream_for_mpc( | |||
2924 | &context->res_ctx, dc->res_pool, | |||
2925 | pipe, hsplit_pipe); | |||
2926 | resource_build_scaling_params(pipe); | |||
2927 | resource_build_scaling_params(hsplit_pipe); | |||
2928 | } | |||
2929 | pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; | |||
2930 | } | |||
2931 | } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { | |||
2932 | /* merge should already have been done */ | |||
2933 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 2933); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
2934 | } | |||
2935 | } | |||
2936 | /* Actual dsc count per stream dsc validation*/ | |||
2937 | if (!dcn20_validate_dsc(dc, context)) { | |||
2938 | context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = | |||
2939 | DML_FAIL_DSC_VALIDATION_FAILURE; | |||
2940 | goto validate_fail; | |||
2941 | } | |||
2942 | ||||
2943 | *vlevel_out = vlevel; | |||
2944 | ||||
2945 | out = true1; | |||
2946 | goto validate_out; | |||
2947 | ||||
2948 | validate_fail: | |||
2949 | out = false0; | |||
2950 | ||||
2951 | validate_out: | |||
2952 | return out; | |||
2953 | } | |||
2954 | ||||
2955 | static void dcn20_calculate_wm( | |||
2956 | struct dc *dc, struct dc_state *context, | |||
2957 | display_e2e_pipe_params_st *pipes, | |||
2958 | int *out_pipe_cnt, | |||
2959 | int *pipe_split_from, | |||
2960 | int vlevel) | |||
2961 | { | |||
2962 | int pipe_cnt, i, pipe_idx; | |||
2963 | ||||
2964 | for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { | |||
2965 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
2966 | continue; | |||
2967 | ||||
2968 | pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; | |||
2969 | pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; | |||
2970 | ||||
2971 | if (pipe_split_from[i] < 0) { | |||
2972 | pipes[pipe_cnt].clks_cfg.dppclk_mhz = | |||
2973 | context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; | |||
2974 | if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) | |||
2975 | pipes[pipe_cnt].pipe.dest.odm_combine = | |||
2976 | context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]; | |||
2977 | else | |||
2978 | pipes[pipe_cnt].pipe.dest.odm_combine = 0; | |||
2979 | pipe_idx++; | |||
2980 | } else { | |||
2981 | pipes[pipe_cnt].clks_cfg.dppclk_mhz = | |||
2982 | context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]]; | |||
2983 | if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i]) | |||
2984 | pipes[pipe_cnt].pipe.dest.odm_combine = | |||
2985 | context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]]; | |||
2986 | else | |||
2987 | pipes[pipe_cnt].pipe.dest.odm_combine = 0; | |||
2988 | } | |||
2989 | ||||
2990 | if (dc->config.forced_clocks) { | |||
2991 | pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; | |||
2992 | pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; | |||
2993 | } | |||
2994 | if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000) | |||
2995 | pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; | |||
2996 | if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000) | |||
2997 | pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; | |||
2998 | ||||
2999 | pipe_cnt++; | |||
3000 | } | |||
3001 | ||||
3002 | if (pipe_cnt != pipe_idx) { | |||
3003 | if (dc->res_pool->funcs->populate_dml_pipes) | |||
3004 | pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, | |||
3005 | context, pipes); | |||
3006 | else | |||
3007 | pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, | |||
3008 | context, pipes); | |||
3009 | } | |||
3010 | ||||
3011 | *out_pipe_cnt = pipe_cnt; | |||
3012 | ||||
3013 | pipes[0].clks_cfg.voltage = vlevel; | |||
3014 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; | |||
3015 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; | |||
3016 | ||||
3017 | /* only pipe 0 is read for voltage and dcf/soc clocks */ | |||
3018 | if (vlevel < 1) { | |||
3019 | pipes[0].clks_cfg.voltage = 1; | |||
3020 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz; | |||
3021 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz; | |||
3022 | } | |||
3023 | context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3024 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3025 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3026 | context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3027 | context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3028 | context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3029 | context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3030 | context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3031 | ||||
3032 | if (vlevel < 2) { | |||
3033 | pipes[0].clks_cfg.voltage = 2; | |||
3034 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; | |||
3035 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; | |||
3036 | } | |||
3037 | context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3038 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3039 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3040 | context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3041 | context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3042 | context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3043 | context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3044 | ||||
3045 | if (vlevel < 3) { | |||
3046 | pipes[0].clks_cfg.voltage = 3; | |||
3047 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz; | |||
3048 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz; | |||
3049 | } | |||
3050 | context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3051 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3052 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3053 | context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3054 | context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3055 | context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3056 | context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3057 | ||||
3058 | pipes[0].clks_cfg.voltage = vlevel; | |||
3059 | pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; | |||
3060 | pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; | |||
3061 | context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3062 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3063 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3064 | context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3065 | context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3066 | context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3067 | context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; | |||
3068 | } | |||
3069 | ||||
3070 | void dcn20_calculate_dlg_params( | |||
3071 | struct dc *dc, struct dc_state *context, | |||
3072 | display_e2e_pipe_params_st *pipes, | |||
3073 | int pipe_cnt, | |||
3074 | int vlevel) | |||
3075 | { | |||
3076 | int i, pipe_idx; | |||
3077 | ||||
3078 | /* Writeback MCIF_WB arbitration parameters */ | |||
3079 | dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt); | |||
3080 | ||||
3081 | context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; | |||
3082 | context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; | |||
3083 | context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; | |||
3084 | context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; | |||
3085 | context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; | |||
3086 | context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; | |||
3087 | context->bw_ctx.bw.dcn.clk.p_state_change_support = | |||
3088 | context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] | |||
3089 | != dm_dram_clock_change_unsupported; | |||
3090 | context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; | |||
3091 | ||||
3092 | if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) | |||
3093 | context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; | |||
3094 | ||||
3095 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
3096 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
3097 | continue; | |||
3098 | pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
3099 | pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
3100 | pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
3101 | pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); | |||
3102 | if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) | |||
3103 | context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; | |||
3104 | context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = | |||
3105 | pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; | |||
3106 | context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; | |||
3107 | pipe_idx++; | |||
3108 | } | |||
3109 | /*save a original dppclock copy*/ | |||
3110 | context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; | |||
3111 | context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; | |||
3112 | context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000; | |||
3113 | context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000; | |||
3114 | ||||
3115 | for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { | |||
3116 | bool_Bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2; | |||
3117 | ||||
3118 | if (!context->res_ctx.pipe_ctx[i].stream) | |||
3119 | continue; | |||
3120 | ||||
3121 | context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, | |||
3122 | &context->res_ctx.pipe_ctx[i].dlg_regs, | |||
3123 | &context->res_ctx.pipe_ctx[i].ttu_regs, | |||
3124 | pipes, | |||
3125 | pipe_cnt, | |||
3126 | pipe_idx, | |||
3127 | cstate_en, | |||
3128 | context->bw_ctx.bw.dcn.clk.p_state_change_support, | |||
3129 | false0, false0, true1); | |||
3130 | ||||
3131 | context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, | |||
3132 | &context->res_ctx.pipe_ctx[i].rq_regs, | |||
3133 | pipes[pipe_idx].pipe); | |||
3134 | pipe_idx++; | |||
3135 | } | |||
3136 | } | |||
3137 | ||||
3138 | static bool_Bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, | |||
3139 | bool_Bool fast_validate) | |||
3140 | { | |||
3141 | bool_Bool out = false0; | |||
3142 | ||||
3143 | BW_VAL_TRACE_SETUP()unsigned long long end_tick = 0; unsigned long long voltage_level_tick = 0; unsigned long long watermark_tick = 0; unsigned long long start_tick = dc->debug.bw_val_profile.enable ? dm_get_timestamp (dc->ctx) : 0; | |||
3144 | ||||
3145 | int vlevel = 0; | |||
3146 | int pipe_split_from[MAX_PIPES6]; | |||
3147 | int pipe_cnt = 0; | |||
3148 | display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC0x0002); | |||
3149 | DC_LOGGER_INIT(dc->ctx->logger); | |||
3150 | ||||
3151 | BW_VAL_TRACE_COUNT()if (dc->debug.bw_val_profile.enable) dc->debug.bw_val_profile .total_count++; | |||
3152 | ||||
3153 | out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel); | |||
3154 | ||||
3155 | if (pipe_cnt == 0) | |||
3156 | goto validate_out; | |||
3157 | ||||
3158 | if (!out) | |||
3159 | goto validate_fail; | |||
3160 | ||||
3161 | BW_VAL_TRACE_END_VOLTAGE_LEVEL()if (dc->debug.bw_val_profile.enable) voltage_level_tick = dm_get_timestamp (dc->ctx); | |||
3162 | ||||
3163 | if (fast_validate) { | |||
3164 | BW_VAL_TRACE_SKIP(fast)if (dc->debug.bw_val_profile.enable) { if (!voltage_level_tick ) voltage_level_tick = dm_get_timestamp(dc->ctx); dc->debug .bw_val_profile.skip_fast_count++; }; | |||
3165 | goto validate_out; | |||
3166 | } | |||
3167 | ||||
3168 | dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel); | |||
3169 | dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); | |||
3170 | ||||
3171 | BW_VAL_TRACE_END_WATERMARKS()if (dc->debug.bw_val_profile.enable) watermark_tick = dm_get_timestamp (dc->ctx); | |||
3172 | ||||
3173 | goto validate_out; | |||
3174 | ||||
3175 | validate_fail: | |||
3176 | DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",printk("\0014" "[" "drm" "] " "Mode Validation Warning: %s failed validation.\n" , dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus [context->bw_ctx.dml.vba.soc.num_states])) | |||
3177 | dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]))printk("\0014" "[" "drm" "] " "Mode Validation Warning: %s failed validation.\n" , dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus [context->bw_ctx.dml.vba.soc.num_states])); | |||
3178 | ||||
3179 | BW_VAL_TRACE_SKIP(fail)if (dc->debug.bw_val_profile.enable) { if (!voltage_level_tick ) voltage_level_tick = dm_get_timestamp(dc->ctx); dc->debug .bw_val_profile.skip_fail_count++; }; | |||
3180 | out = false0; | |||
3181 | ||||
3182 | validate_out: | |||
3183 | kfree(pipes); | |||
3184 | ||||
3185 | BW_VAL_TRACE_FINISH()if (dc->debug.bw_val_profile.enable) { end_tick = dm_get_timestamp (dc->ctx); dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; if (watermark_tick) { dc ->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; } }; | |||
3186 | ||||
3187 | return out; | |||
3188 | } | |||
3189 | ||||
3190 | /* | |||
3191 | * This must be noinline to ensure anything that deals with FP registers | |||
3192 | * is contained within this call; previously our compiling with hard-float | |||
3193 | * would result in fp instructions being emitted outside of the boundaries | |||
3194 | * of the DC_FP_START/END macros, which makes sense as the compiler has no | |||
3195 | * idea about what is wrapped and what is not | |||
3196 | * | |||
3197 | * This is largely just a workaround to avoid breakage introduced with 5.6, | |||
3198 | * ideally all fp-using code should be moved into its own file, only that | |||
3199 | * should be compiled with hard-float, and all code exported from there | |||
3200 | * should be strictly wrapped with DC_FP_START/END | |||
3201 | */ | |||
3202 | static noinline__attribute__((__noinline__)) bool_Bool dcn20_validate_bandwidth_fp(struct dc *dc, | |||
3203 | struct dc_state *context, bool_Bool fast_validate) | |||
3204 | { | |||
3205 | bool_Bool voltage_supported = false0; | |||
3206 | bool_Bool full_pstate_supported = false0; | |||
3207 | bool_Bool dummy_pstate_supported = false0; | |||
3208 | double p_state_latency_us; | |||
3209 | ||||
3210 | p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; | |||
3211 | context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support = | |||
3212 | dc->debug.disable_dram_clock_change_vactive_support; | |||
3213 | context->bw_ctx.dml.soc.allow_dram_clock_one_display_vactive = | |||
3214 | dc->debug.enable_dram_clock_change_one_display_vactive; | |||
3215 | ||||
3216 | /*Unsafe due to current pipe merge and split logic*/ | |||
3217 | ASSERT(context != dc->current_state)do { if (({ static int __warned; int __ret = !!(!(context != dc ->current_state)); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(context != dc->current_state)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 3217); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
3218 | ||||
3219 | if (fast_validate) { | |||
3220 | return dcn20_validate_bandwidth_internal(dc, context, true1); | |||
3221 | } | |||
3222 | ||||
3223 | // Best case, we support full UCLK switch latency | |||
3224 | voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false0); | |||
3225 | full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; | |||
3226 | ||||
3227 | if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 || | |||
3228 | (voltage_supported && full_pstate_supported)) { | |||
3229 | context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported; | |||
3230 | goto restore_dml_state; | |||
3231 | } | |||
3232 | ||||
3233 | // Fallback: Try to only support G6 temperature read latency | |||
3234 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us; | |||
3235 | ||||
3236 | voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false0); | |||
3237 | dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support; | |||
3238 | ||||
3239 | if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) { | |||
3240 | context->bw_ctx.bw.dcn.clk.p_state_change_support = false0; | |||
3241 | goto restore_dml_state; | |||
3242 | } | |||
3243 | ||||
3244 | // ERROR: fallback is supposed to always work. | |||
3245 | ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 3245); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
3246 | ||||
3247 | restore_dml_state: | |||
3248 | context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; | |||
3249 | return voltage_supported; | |||
3250 | } | |||
3251 | ||||
3252 | bool_Bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, | |||
3253 | bool_Bool fast_validate) | |||
3254 | { | |||
3255 | bool_Bool voltage_supported; | |||
3256 | DC_FP_START()fpu_kernel_enter(); | |||
3257 | voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate); | |||
3258 | DC_FP_END()fpu_kernel_exit(); | |||
3259 | return voltage_supported; | |||
3260 | } | |||
3261 | ||||
3262 | struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer( | |||
3263 | struct dc_state *state, | |||
3264 | const struct resource_pool *pool, | |||
3265 | struct dc_stream_state *stream) | |||
3266 | { | |||
3267 | struct resource_context *res_ctx = &state->res_ctx; | |||
3268 | struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); | |||
| ||||
3269 | struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe); | |||
3270 | ||||
3271 | if (!head_pipe) | |||
3272 | ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 3272); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
3273 | ||||
3274 | if (!idle_pipe) | |||
3275 | return NULL((void *)0); | |||
3276 | ||||
3277 | idle_pipe->stream = head_pipe->stream; | |||
| ||||
3278 | idle_pipe->stream_res.tg = head_pipe->stream_res.tg; | |||
3279 | idle_pipe->stream_res.opp = head_pipe->stream_res.opp; | |||
3280 | ||||
3281 | idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; | |||
3282 | idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; | |||
3283 | idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; | |||
3284 | idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; | |||
3285 | ||||
3286 | return idle_pipe; | |||
3287 | } | |||
3288 | ||||
3289 | bool_Bool dcn20_get_dcc_compression_cap(const struct dc *dc, | |||
3290 | const struct dc_dcc_surface_param *input, | |||
3291 | struct dc_surface_dcc_cap *output) | |||
3292 | { | |||
3293 | return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( | |||
3294 | dc->res_pool->hubbub, | |||
3295 | input, | |||
3296 | output); | |||
3297 | } | |||
3298 | ||||
3299 | static void dcn20_destroy_resource_pool(struct resource_pool **pool) | |||
3300 | { | |||
3301 | struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool)({ const __typeof( ((struct dcn20_resource_pool *)0)->base ) *__mptr = (*pool); (struct dcn20_resource_pool *)( (char * )__mptr - __builtin_offsetof(struct dcn20_resource_pool, base ) );}); | |||
3302 | ||||
3303 | dcn20_resource_destruct(dcn20_pool); | |||
3304 | kfree(dcn20_pool); | |||
3305 | *pool = NULL((void *)0); | |||
3306 | } | |||
3307 | ||||
3308 | ||||
3309 | static struct dc_cap_funcs cap_funcs = { | |||
3310 | .get_dcc_compression_cap = dcn20_get_dcc_compression_cap | |||
3311 | }; | |||
3312 | ||||
3313 | ||||
3314 | enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) | |||
3315 | { | |||
3316 | enum surface_pixel_format surf_pix_format = plane_state->format; | |||
3317 | unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); | |||
3318 | ||||
3319 | enum swizzle_mode_values swizzle = DC_SW_LINEAR; | |||
3320 | ||||
3321 | if (bpp == 64) | |||
3322 | swizzle = DC_SW_64KB_D; | |||
3323 | else | |||
3324 | swizzle = DC_SW_64KB_S; | |||
3325 | ||||
3326 | plane_state->tiling_info.gfx9.swizzle = swizzle; | |||
3327 | return DC_OK; | |||
3328 | } | |||
3329 | ||||
3330 | static const struct resource_funcs dcn20_res_pool_funcs = { | |||
3331 | .destroy = dcn20_destroy_resource_pool, | |||
3332 | .link_enc_create = dcn20_link_encoder_create, | |||
3333 | .panel_cntl_create = dcn20_panel_cntl_create, | |||
3334 | .validate_bandwidth = dcn20_validate_bandwidth, | |||
3335 | .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, | |||
3336 | .add_stream_to_ctx = dcn20_add_stream_to_ctx, | |||
3337 | .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, | |||
3338 | .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, | |||
3339 | .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, | |||
3340 | .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, | |||
3341 | .set_mcif_arb_params = dcn20_set_mcif_arb_params, | |||
3342 | .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, | |||
3343 | .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link | |||
3344 | }; | |||
3345 | ||||
3346 | bool_Bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) | |||
3347 | { | |||
3348 | int i; | |||
3349 | uint32_t pipe_count = pool->res_cap->num_dwb; | |||
3350 | ||||
3351 | for (i = 0; i < pipe_count; i++) { | |||
3352 | struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), | |||
3353 | GFP_KERNEL(0x0001 | 0x0004)); | |||
3354 | ||||
3355 | if (!dwbc20) { | |||
3356 | dm_error("DC: failed to create dwbc20!\n")__drm_err("DC: failed to create dwbc20!\n"); | |||
3357 | return false0; | |||
3358 | } | |||
3359 | dcn20_dwbc_construct(dwbc20, ctx, | |||
3360 | &dwbc20_regs[i], | |||
3361 | &dwbc20_shift, | |||
3362 | &dwbc20_mask, | |||
3363 | i); | |||
3364 | pool->dwbc[i] = &dwbc20->base; | |||
3365 | } | |||
3366 | return true1; | |||
3367 | } | |||
3368 | ||||
3369 | bool_Bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) | |||
3370 | { | |||
3371 | int i; | |||
3372 | uint32_t pipe_count = pool->res_cap->num_dwb; | |||
3373 | ||||
3374 | ASSERT(pipe_count > 0)do { if (({ static int __warned; int __ret = !!(!(pipe_count > 0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipe_count > 0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_resource.c" , 3374); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
3375 | ||||
3376 | for (i = 0; i < pipe_count; i++) { | |||
3377 | struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), | |||
3378 | GFP_KERNEL(0x0001 | 0x0004)); | |||
3379 | ||||
3380 | if (!mcif_wb20) { | |||
3381 | dm_error("DC: failed to create mcif_wb20!\n")__drm_err("DC: failed to create mcif_wb20!\n"); | |||
3382 | return false0; | |||
3383 | } | |||
3384 | ||||
3385 | dcn20_mmhubbub_construct(mcif_wb20, ctx, | |||
3386 | &mcif_wb20_regs[i], | |||
3387 | &mcif_wb20_shift, | |||
3388 | &mcif_wb20_mask, | |||
3389 | i); | |||
3390 | ||||
3391 | pool->mcif_wb[i] = &mcif_wb20->base; | |||
3392 | } | |||
3393 | return true1; | |||
3394 | } | |||
3395 | ||||
3396 | static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) | |||
3397 | { | |||
3398 | struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC0x0002); | |||
3399 | ||||
3400 | if (!pp_smu) | |||
3401 | return pp_smu; | |||
3402 | ||||
3403 | dm_pp_get_funcs(ctx, pp_smu); | |||
3404 | ||||
3405 | if (pp_smu->ctx.ver != PP_SMU_VER_NV) | |||
3406 | pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs))__builtin_memset((pp_smu), (0), (sizeof(struct pp_smu_funcs)) ); | |||
3407 | ||||
3408 | return pp_smu; | |||
3409 | } | |||
3410 | ||||
3411 | static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) | |||
3412 | { | |||
3413 | if (pp_smu && *pp_smu) { | |||
3414 | kfree(*pp_smu); | |||
3415 | *pp_smu = NULL((void *)0); | |||
3416 | } | |||
3417 | } | |||
3418 | ||||
3419 | void dcn20_cap_soc_clocks( | |||
3420 | struct _vcs_dpi_soc_bounding_box_st *bb, | |||
3421 | struct pp_smu_nv_clock_table max_clocks) | |||
3422 | { | |||
3423 | int i; | |||
3424 | ||||
3425 | // First pass - cap all clocks higher than the reported max | |||
3426 | for (i = 0; i < bb->num_states; i++) { | |||
3427 | if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000)) | |||
3428 | && max_clocks.dcfClockInKhz != 0) | |||
3429 | bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000); | |||
3430 | ||||
3431 | if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16) | |||
3432 | && max_clocks.uClockInKhz != 0) | |||
3433 | bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16; | |||
3434 | ||||
3435 | if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000)) | |||
3436 | && max_clocks.fabricClockInKhz != 0) | |||
3437 | bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000); | |||
3438 | ||||
3439 | if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000)) | |||
3440 | && max_clocks.displayClockInKhz != 0) | |||
3441 | bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000); | |||
3442 | ||||
3443 | if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000)) | |||
3444 | && max_clocks.dppClockInKhz != 0) | |||
3445 | bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000); | |||
3446 | ||||
3447 | if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000)) | |||
3448 | && max_clocks.phyClockInKhz != 0) | |||
3449 | bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000); | |||
3450 | ||||
3451 | if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000)) | |||
3452 | && max_clocks.socClockInKhz != 0) | |||
3453 | bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000); | |||
3454 | ||||
3455 | if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000)) | |||
3456 | && max_clocks.dscClockInKhz != 0) | |||
3457 | bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000); | |||
3458 | } | |||
3459 | ||||
3460 | // Second pass - remove all duplicate clock states | |||
3461 | for (i = bb->num_states - 1; i > 1; i--) { | |||
3462 | bool_Bool duplicate = true1; | |||
3463 | ||||
3464 | if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) | |||
3465 | duplicate = false0; | |||
3466 | if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) | |||
3467 | duplicate = false0; | |||
3468 | if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) | |||
3469 | duplicate = false0; | |||
3470 | if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) | |||
3471 | duplicate = false0; | |||
3472 | if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) | |||
3473 | duplicate = false0; | |||
3474 | if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) | |||
3475 | duplicate = false0; | |||
3476 | if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) | |||
3477 | duplicate = false0; | |||
3478 | if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) | |||
3479 | duplicate = false0; | |||
3480 | ||||
3481 | if (duplicate) | |||
3482 | bb->num_states--; | |||
3483 | } | |||
3484 | } | |||
3485 | ||||
3486 | void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, | |||
3487 | struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) | |||
3488 | { | |||
3489 | struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES9]; | |||
3490 | int i; | |||
3491 | int num_calculated_states = 0; | |||
3492 | int min_dcfclk = 0; | |||
3493 | ||||
3494 | if (num_states == 0) | |||
3495 | return; | |||
3496 | ||||
3497 | memset(calculated_states, 0, sizeof(calculated_states))__builtin_memset((calculated_states), (0), (sizeof(calculated_states ))); | |||
3498 | ||||
3499 | if (dc->bb_overrides.min_dcfclk_mhz > 0) | |||
3500 | min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; | |||
3501 | else { | |||
3502 | if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)((dc->ctx->asic_id.hw_internal_rev >= NV_NAVI12_P_A0 ) && (dc->ctx->asic_id.hw_internal_rev < NV_NAVI14_M_A0 ))) | |||
3503 | min_dcfclk = 310; | |||
3504 | else | |||
3505 | // Accounting for SOC/DCF relationship, we can go as high as | |||
3506 | // 506Mhz in Vmin. | |||
3507 | min_dcfclk = 506; | |||
3508 | } | |||
3509 | ||||
3510 | for (i = 0; i < num_states; i++) { | |||
3511 | int min_fclk_required_by_uclk; | |||
3512 | calculated_states[i].state = i; | |||
3513 | calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000; | |||
3514 | ||||
3515 | // FCLK:UCLK ratio is 1.08 | |||
3516 | min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32)(1ULL << (32)) * 1080 / 1000000, uclk_states[i], 32); | |||
3517 | ||||
3518 | calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ? | |||
3519 | min_dcfclk : min_fclk_required_by_uclk; | |||
3520 | ||||
3521 | calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ? | |||
3522 | max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; | |||
3523 | ||||
3524 | calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ? | |||
3525 | max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz; | |||
3526 | ||||
3527 | calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000; | |||
3528 | calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000; | |||
3529 | calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3); | |||
3530 | ||||
3531 | calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000; | |||
3532 | ||||
3533 | num_calculated_states++; | |||
3534 | } | |||
3535 | ||||
3536 | calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000; | |||
3537 | calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000; | |||
3538 | calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000; | |||
3539 | ||||
3540 | memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits))__builtin_memcpy((bb->clock_limits), (calculated_states), ( sizeof(bb->clock_limits))); | |||
3541 | bb->num_states = num_calculated_states; | |||
3542 | ||||
3543 | // Duplicate the last state, DML always an extra state identical to max state to work | |||
3544 | memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st))__builtin_memcpy((&bb->clock_limits[num_calculated_states ]), (&bb->clock_limits[num_calculated_states - 1]), (sizeof (struct _vcs_dpi_voltage_scaling_st))); | |||
3545 | bb->clock_limits[num_calculated_states].state = bb->num_states; | |||
3546 | } | |||
3547 | ||||
3548 | void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) | |||
3549 | { | |||
3550 | if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns | |||
3551 | && dc->bb_overrides.sr_exit_time_ns) { | |||
3552 | bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0; | |||
3553 | } | |||
3554 | ||||
3555 | if ((int)(bb->sr_enter_plus_exit_time_us * 1000) | |||
3556 | != dc->bb_overrides.sr_enter_plus_exit_time_ns | |||
3557 | && dc->bb_overrides.sr_enter_plus_exit_time_ns) { | |||
3558 | bb->sr_enter_plus_exit_time_us = | |||
3559 | dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0; | |||
3560 | } | |||
3561 | ||||
3562 | if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns | |||
3563 | && dc->bb_overrides.urgent_latency_ns) { | |||
3564 | bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0; | |||
3565 | } | |||
3566 | ||||
3567 | if ((int)(bb->dram_clock_change_latency_us * 1000) | |||
3568 | != dc->bb_overrides.dram_clock_change_latency_ns | |||
3569 | && dc->bb_overrides.dram_clock_change_latency_ns) { | |||
3570 | bb->dram_clock_change_latency_us = | |||
3571 | dc->bb_overrides.dram_clock_change_latency_ns / 1000.0; | |||
3572 | } | |||
3573 | ||||
3574 | if ((int)(bb->dummy_pstate_latency_us * 1000) | |||
3575 | != dc->bb_overrides.dummy_clock_change_latency_ns | |||
3576 | && dc->bb_overrides.dummy_clock_change_latency_ns) { | |||
3577 | bb->dummy_pstate_latency_us = | |||
3578 | dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0; | |||
3579 | } | |||
3580 | } | |||
3581 | ||||
3582 | static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( | |||
3583 | uint32_t hw_internal_rev) | |||
3584 | { | |||
3585 | if (ASICREV_IS_NAVI14_M(hw_internal_rev)((hw_internal_rev >= NV_NAVI14_M_A0) && (hw_internal_rev < NV_UNKNOWN))) | |||
3586 | return &dcn2_0_nv14_soc; | |||
3587 | ||||
3588 | if (ASICREV_IS_NAVI12_P(hw_internal_rev)((hw_internal_rev >= NV_NAVI12_P_A0) && (hw_internal_rev < NV_NAVI14_M_A0))) | |||
3589 | return &dcn2_0_nv12_soc; | |||
3590 | ||||
3591 | return &dcn2_0_soc; | |||
3592 | } | |||
3593 | ||||
3594 | static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( | |||
3595 | uint32_t hw_internal_rev) | |||
3596 | { | |||
3597 | /* NV14 */ | |||
3598 | if (ASICREV_IS_NAVI14_M(hw_internal_rev)((hw_internal_rev >= NV_NAVI14_M_A0) && (hw_internal_rev < NV_UNKNOWN))) | |||
3599 | return &dcn2_0_nv14_ip; | |||
3600 | ||||
3601 | /* NV12 and NV10 */ | |||
3602 | return &dcn2_0_ip; | |||
3603 | } | |||
3604 | ||||
3605 | static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) | |||
3606 | { | |||
3607 | return DML_PROJECT_NAVI10v2; | |||
3608 | } | |||
3609 | ||||
3610 | #define fixed16_to_double(x)(((double) x) / ((double) (1 << 16))) (((double) x) / ((double) (1 << 16))) | |||
3611 | #define fixed16_to_double_to_cpu(x)(((double) ((__uint32_t)(x))) / ((double) (1 << 16))) fixed16_to_double(le32_to_cpu(x))(((double) ((__uint32_t)(x))) / ((double) (1 << 16))) | |||
3612 | ||||
3613 | static bool_Bool init_soc_bounding_box(struct dc *dc, | |||
3614 | struct dcn20_resource_pool *pool) | |||
3615 | { | |||
3616 | const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; | |||
3617 | struct _vcs_dpi_soc_bounding_box_st *loaded_bb = | |||
3618 | get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); | |||
3619 | struct _vcs_dpi_ip_params_st *loaded_ip = | |||
3620 | get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); | |||
3621 | ||||
3622 | DC_LOGGER_INIT(dc->ctx->logger); | |||
3623 | ||||
3624 | /* TODO: upstream NV12 bounding box when its launched */ | |||
3625 | if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)((dc->ctx->asic_id.hw_internal_rev >= NV_NAVI12_P_A0 ) && (dc->ctx->asic_id.hw_internal_rev < NV_NAVI14_M_A0 ))) { | |||
3626 | DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__)__drm_err("%s: not valid soc bounding box/n", __func__); | |||
3627 | return false0; | |||
3628 | } | |||
3629 | ||||
3630 | if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)((dc->ctx->asic_id.hw_internal_rev >= NV_NAVI12_P_A0 ) && (dc->ctx->asic_id.hw_internal_rev < NV_NAVI14_M_A0 ))) { | |||
3631 | int i; | |||
3632 | ||||
3633 | dcn2_0_nv12_soc.sr_exit_time_us = | |||
3634 | fixed16_to_double_to_cpu(bb->sr_exit_time_us)(((double) ((__uint32_t)(bb->sr_exit_time_us))) / ((double ) (1 << 16))); | |||
3635 | dcn2_0_nv12_soc.sr_enter_plus_exit_time_us = | |||
3636 | fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us)(((double) ((__uint32_t)(bb->sr_enter_plus_exit_time_us))) / ((double) (1 << 16))); | |||
3637 | dcn2_0_nv12_soc.urgent_latency_us = | |||
3638 | fixed16_to_double_to_cpu(bb->urgent_latency_us)(((double) ((__uint32_t)(bb->urgent_latency_us))) / ((double ) (1 << 16))); | |||
3639 | dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us = | |||
3640 | fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us)(((double) ((__uint32_t)(bb->urgent_latency_pixel_data_only_us ))) / ((double) (1 << 16))); | |||
3641 | dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us = | |||
3642 | fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us)(((double) ((__uint32_t)(bb->urgent_latency_pixel_mixed_with_vm_data_us ))) / ((double) (1 << 16))); | |||
3643 | dcn2_0_nv12_soc.urgent_latency_vm_data_only_us = | |||
3644 | fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us)(((double) ((__uint32_t)(bb->urgent_latency_vm_data_only_us ))) / ((double) (1 << 16))); | |||
3645 | dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = | |||
3646 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes)((__uint32_t)(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes )); | |||
3647 | dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = | |||
3648 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes)((__uint32_t)(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes )); | |||
3649 | dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = | |||
3650 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes)((__uint32_t)(bb->urgent_out_of_order_return_per_channel_vm_only_bytes )); | |||
3651 | dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = | |||
3652 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only)(((double) ((__uint32_t)(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only ))) / ((double) (1 << 16))); | |||
3653 | dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = | |||
3654 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm)(((double) ((__uint32_t)(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm ))) / ((double) (1 << 16))); | |||
3655 | dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = | |||
3656 | fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only)(((double) ((__uint32_t)(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only ))) / ((double) (1 << 16))); | |||
3657 | dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent = | |||
3658 | fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent)(((double) ((__uint32_t)(bb->max_avg_sdp_bw_use_normal_percent ))) / ((double) (1 << 16))); | |||
3659 | dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent = | |||
3660 | fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent)(((double) ((__uint32_t)(bb->max_avg_dram_bw_use_normal_percent ))) / ((double) (1 << 16))); | |||
3661 | dcn2_0_nv12_soc.writeback_latency_us = | |||
3662 | fixed16_to_double_to_cpu(bb->writeback_latency_us)(((double) ((__uint32_t)(bb->writeback_latency_us))) / ((double ) (1 << 16))); | |||
3663 | dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent = | |||
3664 | fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent)(((double) ((__uint32_t)(bb->ideal_dram_bw_after_urgent_percent ))) / ((double) (1 << 16))); | |||
3665 | dcn2_0_nv12_soc.max_request_size_bytes = | |||
3666 | le32_to_cpu(bb->max_request_size_bytes)((__uint32_t)(bb->max_request_size_bytes)); | |||
3667 | dcn2_0_nv12_soc.dram_channel_width_bytes = | |||
3668 | le32_to_cpu(bb->dram_channel_width_bytes)((__uint32_t)(bb->dram_channel_width_bytes)); | |||
3669 | dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes = | |||
3670 | le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes)((__uint32_t)(bb->fabric_datapath_to_dcn_data_return_bytes )); | |||
3671 | dcn2_0_nv12_soc.dcn_downspread_percent = | |||
3672 | fixed16_to_double_to_cpu(bb->dcn_downspread_percent)(((double) ((__uint32_t)(bb->dcn_downspread_percent))) / ( (double) (1 << 16))); | |||
3673 | dcn2_0_nv12_soc.downspread_percent = | |||
3674 | fixed16_to_double_to_cpu(bb->downspread_percent)(((double) ((__uint32_t)(bb->downspread_percent))) / ((double ) (1 << 16))); | |||
3675 | dcn2_0_nv12_soc.dram_page_open_time_ns = | |||
3676 | fixed16_to_double_to_cpu(bb->dram_page_open_time_ns)(((double) ((__uint32_t)(bb->dram_page_open_time_ns))) / ( (double) (1 << 16))); | |||
3677 | dcn2_0_nv12_soc.dram_rw_turnaround_time_ns = | |||
3678 | fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns)(((double) ((__uint32_t)(bb->dram_rw_turnaround_time_ns))) / ((double) (1 << 16))); | |||
3679 | dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes = | |||
3680 | le32_to_cpu(bb->dram_return_buffer_per_channel_bytes)((__uint32_t)(bb->dram_return_buffer_per_channel_bytes)); | |||
3681 | dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles = | |||
3682 | le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles)((__uint32_t)(bb->round_trip_ping_latency_dcfclk_cycles)); | |||
3683 | dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes = | |||
3684 | le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes)((__uint32_t)(bb->urgent_out_of_order_return_per_channel_bytes )); | |||
3685 | dcn2_0_nv12_soc.channel_interleave_bytes = | |||
3686 | le32_to_cpu(bb->channel_interleave_bytes)((__uint32_t)(bb->channel_interleave_bytes)); | |||
3687 | dcn2_0_nv12_soc.num_banks = | |||
3688 | le32_to_cpu(bb->num_banks)((__uint32_t)(bb->num_banks)); | |||
3689 | dcn2_0_nv12_soc.num_chans = | |||
3690 | le32_to_cpu(bb->num_chans)((__uint32_t)(bb->num_chans)); | |||
3691 | dcn2_0_nv12_soc.vmm_page_size_bytes = | |||
3692 | le32_to_cpu(bb->vmm_page_size_bytes)((__uint32_t)(bb->vmm_page_size_bytes)); | |||
3693 | dcn2_0_nv12_soc.dram_clock_change_latency_us = | |||
3694 | fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us)(((double) ((__uint32_t)(bb->dram_clock_change_latency_us) )) / ((double) (1 << 16))); | |||
3695 | // HACK!! Lower uclock latency switch time so we don't switch | |||
3696 | dcn2_0_nv12_soc.dram_clock_change_latency_us = 10; | |||
3697 | dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us = | |||
3698 | fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us)(((double) ((__uint32_t)(bb->writeback_dram_clock_change_latency_us ))) / ((double) (1 << 16))); | |||
3699 | dcn2_0_nv12_soc.return_bus_width_bytes = | |||
3700 | le32_to_cpu(bb->return_bus_width_bytes)((__uint32_t)(bb->return_bus_width_bytes)); | |||
3701 | dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz = | |||
3702 | le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz)((__uint32_t)(bb->dispclk_dppclk_vco_speed_mhz)); | |||
3703 | dcn2_0_nv12_soc.xfc_bus_transport_time_us = | |||
3704 | le32_to_cpu(bb->xfc_bus_transport_time_us)((__uint32_t)(bb->xfc_bus_transport_time_us)); | |||
3705 | dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us = | |||
3706 | le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us)((__uint32_t)(bb->xfc_xbuf_latency_tolerance_us)); | |||
3707 | dcn2_0_nv12_soc.use_urgent_burst_bw = | |||
3708 | le32_to_cpu(bb->use_urgent_burst_bw)((__uint32_t)(bb->use_urgent_burst_bw)); | |||
3709 | dcn2_0_nv12_soc.num_states = | |||
3710 | le32_to_cpu(bb->num_states)((__uint32_t)(bb->num_states)); | |||
3711 | ||||
3712 | for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) { | |||
3713 | dcn2_0_nv12_soc.clock_limits[i].state = | |||
3714 | le32_to_cpu(bb->clock_limits[i].state)((__uint32_t)(bb->clock_limits[i].state)); | |||
3715 | dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz = | |||
3716 | fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].dcfclk_mhz))) / ((double) (1 << 16))); | |||
3717 | dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz = | |||
3718 | fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].fabricclk_mhz ))) / ((double) (1 << 16))); | |||
3719 | dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz = | |||
3720 | fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].dispclk_mhz)) ) / ((double) (1 << 16))); | |||
3721 | dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz = | |||
3722 | fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].dppclk_mhz))) / ((double) (1 << 16))); | |||
3723 | dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz = | |||
3724 | fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].phyclk_mhz))) / ((double) (1 << 16))); | |||
3725 | dcn2_0_nv12_soc.clock_limits[i].socclk_mhz = | |||
3726 | fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].socclk_mhz))) / ((double) (1 << 16))); | |||
3727 | dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz = | |||
3728 | fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz)(((double) ((__uint32_t)(bb->clock_limits[i].dscclk_mhz))) / ((double) (1 << 16))); | |||
3729 | dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts = | |||
3730 | fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts)(((double) ((__uint32_t)(bb->clock_limits[i].dram_speed_mts ))) / ((double) (1 << 16))); | |||
3731 | } | |||
3732 | } | |||
3733 | ||||
3734 | if (pool->base.pp_smu) { | |||
3735 | struct pp_smu_nv_clock_table max_clocks = {0}; | |||
3736 | unsigned int uclk_states[8] = {0}; | |||
3737 | unsigned int num_states = 0; | |||
3738 | enum pp_smu_status status; | |||
3739 | bool_Bool clock_limits_available = false0; | |||
3740 | bool_Bool uclk_states_available = false0; | |||
3741 | ||||
3742 | if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { | |||
3743 | status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) | |||
3744 | (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); | |||
3745 | ||||
3746 | uclk_states_available = (status == PP_SMU_RESULT_OK); | |||
3747 | } | |||
3748 | ||||
3749 | if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { | |||
3750 | status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) | |||
3751 | (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); | |||
3752 | /* SMU cannot set DCF clock to anything equal to or higher than SOC clock | |||
3753 | */ | |||
3754 | if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) | |||
3755 | max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; | |||
3756 | clock_limits_available = (status == PP_SMU_RESULT_OK); | |||
3757 | } | |||
3758 | ||||
3759 | if (clock_limits_available && uclk_states_available && num_states) { | |||
3760 | DC_FP_START()fpu_kernel_enter(); | |||
3761 | dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); | |||
3762 | DC_FP_END()fpu_kernel_exit(); | |||
3763 | } else if (clock_limits_available) { | |||
3764 | DC_FP_START()fpu_kernel_enter(); | |||
3765 | dcn20_cap_soc_clocks(loaded_bb, max_clocks); | |||
3766 | DC_FP_END()fpu_kernel_exit(); | |||
3767 | } | |||
3768 | } | |||
3769 | ||||
3770 | loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; | |||
3771 | loaded_ip->max_num_dpp = pool->base.pipe_count; | |||
3772 | DC_FP_START()fpu_kernel_enter(); | |||
3773 | dcn20_patch_bounding_box(dc, loaded_bb); | |||
3774 | DC_FP_END()fpu_kernel_exit(); | |||
3775 | return true1; | |||
3776 | } | |||
3777 | ||||
3778 | static bool_Bool dcn20_resource_construct( | |||
3779 | uint8_t num_virtual_links, | |||
3780 | struct dc *dc, | |||
3781 | struct dcn20_resource_pool *pool) | |||
3782 | { | |||
3783 | int i; | |||
3784 | struct dc_context *ctx = dc->ctx; | |||
3785 | struct irq_service_init_data init_data; | |||
3786 | struct ddc_service_init_data ddc_init_data; | |||
3787 | struct _vcs_dpi_soc_bounding_box_st *loaded_bb = | |||
3788 | get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); | |||
3789 | struct _vcs_dpi_ip_params_st *loaded_ip = | |||
3790 | get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); | |||
3791 | enum dml_project dml_project_version = | |||
3792 | get_dml_project_version(ctx->asic_id.hw_internal_rev); | |||
3793 | ||||
3794 | ctx->dc_bios->regs = &bios_regs; | |||
3795 | pool->base.funcs = &dcn20_res_pool_funcs; | |||
3796 | ||||
3797 | if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)((ctx->asic_id.hw_internal_rev >= NV_NAVI14_M_A0) && (ctx->asic_id.hw_internal_rev < NV_UNKNOWN))) { | |||
3798 | pool->base.res_cap = &res_cap_nv14; | |||
3799 | pool->base.pipe_count = 5; | |||
3800 | pool->base.mpcc_count = 5; | |||
3801 | } else { | |||
3802 | pool->base.res_cap = &res_cap_nv10; | |||
3803 | pool->base.pipe_count = 6; | |||
3804 | pool->base.mpcc_count = 6; | |||
3805 | } | |||
3806 | /************************************************* | |||
3807 | * Resource + asic cap harcoding * | |||
3808 | *************************************************/ | |||
3809 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE-1; | |||
3810 | ||||
3811 | dc->caps.max_downscale_ratio = 200; | |||
3812 | dc->caps.i2c_speed_in_khz = 100; | |||
3813 | dc->caps.max_cursor_size = 256; | |||
3814 | dc->caps.dmdata_alloc_size = 2048; | |||
3815 | ||||
3816 | dc->caps.max_slave_planes = 1; | |||
3817 | dc->caps.post_blend_color_processing = true1; | |||
3818 | dc->caps.force_dp_tps4_for_cp2520 = true1; | |||
3819 | dc->caps.extended_aux_timeout_support = true1; | |||
3820 | ||||
3821 | /* Color pipeline capabilities */ | |||
3822 | dc->caps.color.dpp.dcn_arch = 1; | |||
3823 | dc->caps.color.dpp.input_lut_shared = 0; | |||
3824 | dc->caps.color.dpp.icsc = 1; | |||
3825 | dc->caps.color.dpp.dgam_ram = 1; | |||
3826 | dc->caps.color.dpp.dgam_rom_caps.srgb = 1; | |||
3827 | dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; | |||
3828 | dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; | |||
3829 | dc->caps.color.dpp.dgam_rom_caps.pq = 0; | |||
3830 | dc->caps.color.dpp.dgam_rom_caps.hlg = 0; | |||
3831 | dc->caps.color.dpp.post_csc = 0; | |||
3832 | dc->caps.color.dpp.gamma_corr = 0; | |||
3833 | ||||
3834 | dc->caps.color.dpp.hw_3d_lut = 1; | |||
3835 | dc->caps.color.dpp.ogam_ram = 1; | |||
3836 | // no OGAM ROM on DCN2, only MPC ROM | |||
3837 | dc->caps.color.dpp.ogam_rom_caps.srgb = 0; | |||
3838 | dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; | |||
3839 | dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; | |||
3840 | dc->caps.color.dpp.ogam_rom_caps.pq = 0; | |||
3841 | dc->caps.color.dpp.ogam_rom_caps.hlg = 0; | |||
3842 | dc->caps.color.dpp.ocsc = 0; | |||
3843 | ||||
3844 | dc->caps.color.mpc.gamut_remap = 0; | |||
3845 | dc->caps.color.mpc.num_3dluts = 0; | |||
3846 | dc->caps.color.mpc.shared_3d_lut = 0; | |||
3847 | dc->caps.color.mpc.ogam_ram = 1; | |||
3848 | dc->caps.color.mpc.ogam_rom_caps.srgb = 0; | |||
3849 | dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; | |||
3850 | dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; | |||
3851 | dc->caps.color.mpc.ogam_rom_caps.pq = 0; | |||
3852 | dc->caps.color.mpc.ogam_rom_caps.hlg = 0; | |||
3853 | dc->caps.color.mpc.ocsc = 1; | |||
3854 | ||||
3855 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) { | |||
3856 | dc->debug = debug_defaults_drv; | |||
3857 | } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { | |||
3858 | pool->base.pipe_count = 4; | |||
3859 | pool->base.mpcc_count = pool->base.pipe_count; | |||
3860 | dc->debug = debug_defaults_diags; | |||
3861 | } else { | |||
3862 | dc->debug = debug_defaults_diags; | |||
3863 | } | |||
3864 | //dcn2.0x | |||
3865 | dc->work_arounds.dedcn20_305_wa = true1; | |||
3866 | ||||
3867 | // Init the vm_helper | |||
3868 | if (dc->vm_helper) | |||
3869 | vm_helper_init(dc->vm_helper, 16); | |||
3870 | ||||
3871 | /************************************************* | |||
3872 | * Create resources * | |||
3873 | *************************************************/ | |||
3874 | ||||
3875 | pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = | |||
3876 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |||
3877 | CLOCK_SOURCE_COMBO_PHY_PLL0, | |||
3878 | &clk_src_regs[0], false0); | |||
3879 | pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = | |||
3880 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |||
3881 | CLOCK_SOURCE_COMBO_PHY_PLL1, | |||
3882 | &clk_src_regs[1], false0); | |||
3883 | pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = | |||
3884 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |||
3885 | CLOCK_SOURCE_COMBO_PHY_PLL2, | |||
3886 | &clk_src_regs[2], false0); | |||
3887 | pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = | |||
3888 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |||
3889 | CLOCK_SOURCE_COMBO_PHY_PLL3, | |||
3890 | &clk_src_regs[3], false0); | |||
3891 | pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = | |||
3892 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |||
3893 | CLOCK_SOURCE_COMBO_PHY_PLL4, | |||
3894 | &clk_src_regs[4], false0); | |||
3895 | pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = | |||
3896 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |||
3897 | CLOCK_SOURCE_COMBO_PHY_PLL5, | |||
3898 | &clk_src_regs[5], false0); | |||
3899 | pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; | |||
3900 | /* todo: not reuse phy_pll registers */ | |||
3901 | pool->base.dp_clock_source = | |||
3902 | dcn20_clock_source_create(ctx, ctx->dc_bios, | |||
3903 | CLOCK_SOURCE_ID_DP_DTO, | |||
3904 | &clk_src_regs[0], true1); | |||
3905 | ||||
3906 | for (i = 0; i < pool->base.clk_src_count; i++) { | |||
3907 | if (pool->base.clock_sources[i] == NULL((void *)0)) { | |||
3908 | dm_error("DC: failed to create clock sources!\n")__drm_err("DC: failed to create clock sources!\n"); | |||
3909 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 3909); do {} while (0); } while (0); | |||
3910 | goto create_fail; | |||
3911 | } | |||
3912 | } | |||
3913 | ||||
3914 | pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); | |||
3915 | if (pool->base.dccg == NULL((void *)0)) { | |||
3916 | dm_error("DC: failed to create dccg!\n")__drm_err("DC: failed to create dccg!\n"); | |||
3917 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 3917); do {} while (0); } while (0); | |||
3918 | goto create_fail; | |||
3919 | } | |||
3920 | ||||
3921 | pool->base.dmcu = dcn20_dmcu_create(ctx, | |||
3922 | &dmcu_regs, | |||
3923 | &dmcu_shift, | |||
3924 | &dmcu_mask); | |||
3925 | if (pool->base.dmcu == NULL((void *)0)) { | |||
3926 | dm_error("DC: failed to create dmcu!\n")__drm_err("DC: failed to create dmcu!\n"); | |||
3927 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 3927); do {} while (0); } while (0); | |||
3928 | goto create_fail; | |||
3929 | } | |||
3930 | ||||
3931 | pool->base.abm = dce_abm_create(ctx, | |||
3932 | &abm_regs, | |||
3933 | &abm_shift, | |||
3934 | &abm_mask); | |||
3935 | if (pool->base.abm == NULL((void *)0)) { | |||
3936 | dm_error("DC: failed to create abm!\n")__drm_err("DC: failed to create abm!\n"); | |||
3937 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 3937); do {} while (0); } while (0); | |||
3938 | goto create_fail; | |||
3939 | } | |||
3940 | ||||
3941 | pool->base.pp_smu = dcn20_pp_smu_create(ctx); | |||
3942 | ||||
3943 | ||||
3944 | if (!init_soc_bounding_box(dc, pool)) { | |||
3945 | dm_error("DC: failed to initialize soc bounding box!\n")__drm_err("DC: failed to initialize soc bounding box!\n"); | |||
3946 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 3946); do {} while (0); } while (0); | |||
3947 | goto create_fail; | |||
3948 | } | |||
3949 | ||||
3950 | dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); | |||
3951 | ||||
3952 | if (!dc->debug.disable_pplib_wm_range) { | |||
3953 | struct pp_smu_wm_range_sets ranges = {0}; | |||
3954 | int i = 0; | |||
3955 | ||||
3956 | ranges.num_reader_wm_sets = 0; | |||
3957 | ||||
3958 | if (loaded_bb->num_states == 1) { | |||
3959 | ranges.reader_wm_sets[0].wm_inst = i; | |||
3960 | ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN0x0; | |||
3961 | ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX0xFFFF; | |||
3962 | ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN0x0; | |||
3963 | ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX0xFFFF; | |||
3964 | ||||
3965 | ranges.num_reader_wm_sets = 1; | |||
3966 | } else if (loaded_bb->num_states > 1) { | |||
3967 | for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { | |||
3968 | ranges.reader_wm_sets[i].wm_inst = i; | |||
3969 | ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN0x0; | |||
3970 | ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX0xFFFF; | |||
3971 | ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; | |||
3972 | ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; | |||
3973 | ||||
3974 | ranges.num_reader_wm_sets = i + 1; | |||
3975 | } | |||
3976 | ||||
3977 | ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN0x0; | |||
3978 | ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX0xFFFF; | |||
3979 | } | |||
3980 | ||||
3981 | ranges.num_writer_wm_sets = 1; | |||
3982 | ||||
3983 | ranges.writer_wm_sets[0].wm_inst = 0; | |||
3984 | ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN0x0; | |||
3985 | ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX0xFFFF; | |||
3986 | ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN0x0; | |||
3987 | ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX0xFFFF; | |||
3988 | ||||
3989 | /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ | |||
3990 | if (pool->base.pp_smu->nv_funcs.set_wm_ranges) | |||
3991 | pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); | |||
3992 | } | |||
3993 | ||||
3994 | init_data.ctx = dc->ctx; | |||
3995 | pool->base.irqs = dal_irq_service_dcn20_create(&init_data); | |||
3996 | if (!pool->base.irqs) | |||
3997 | goto create_fail; | |||
3998 | ||||
3999 | /* mem input -> ipp -> dpp -> opp -> TG */ | |||
4000 | for (i = 0; i < pool->base.pipe_count; i++) { | |||
4001 | pool->base.hubps[i] = dcn20_hubp_create(ctx, i); | |||
4002 | if (pool->base.hubps[i] == NULL((void *)0)) { | |||
4003 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4003); do {} while (0); } while (0); | |||
4004 | dm_error(__drm_err("DC: failed to create memory input!\n") | |||
4005 | "DC: failed to create memory input!\n")__drm_err("DC: failed to create memory input!\n"); | |||
4006 | goto create_fail; | |||
4007 | } | |||
4008 | ||||
4009 | pool->base.ipps[i] = dcn20_ipp_create(ctx, i); | |||
4010 | if (pool->base.ipps[i] == NULL((void *)0)) { | |||
4011 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4011); do {} while (0); } while (0); | |||
4012 | dm_error(__drm_err("DC: failed to create input pixel processor!\n") | |||
4013 | "DC: failed to create input pixel processor!\n")__drm_err("DC: failed to create input pixel processor!\n"); | |||
4014 | goto create_fail; | |||
4015 | } | |||
4016 | ||||
4017 | pool->base.dpps[i] = dcn20_dpp_create(ctx, i); | |||
4018 | if (pool->base.dpps[i] == NULL((void *)0)) { | |||
4019 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4019); do {} while (0); } while (0); | |||
4020 | dm_error(__drm_err("DC: failed to create dpps!\n") | |||
4021 | "DC: failed to create dpps!\n")__drm_err("DC: failed to create dpps!\n"); | |||
4022 | goto create_fail; | |||
4023 | } | |||
4024 | } | |||
4025 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { | |||
4026 | pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); | |||
4027 | if (pool->base.engines[i] == NULL((void *)0)) { | |||
4028 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4028); do {} while (0); } while (0); | |||
4029 | dm_error(__drm_err("DC:failed to create aux engine!!\n") | |||
4030 | "DC:failed to create aux engine!!\n")__drm_err("DC:failed to create aux engine!!\n"); | |||
4031 | goto create_fail; | |||
4032 | } | |||
4033 | pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); | |||
4034 | if (pool->base.hw_i2cs[i] == NULL((void *)0)) { | |||
4035 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4035); do {} while (0); } while (0); | |||
4036 | dm_error(__drm_err("DC:failed to create hw i2c!!\n") | |||
4037 | "DC:failed to create hw i2c!!\n")__drm_err("DC:failed to create hw i2c!!\n"); | |||
4038 | goto create_fail; | |||
4039 | } | |||
4040 | pool->base.sw_i2cs[i] = NULL((void *)0); | |||
4041 | } | |||
4042 | ||||
4043 | for (i = 0; i < pool->base.res_cap->num_opp; i++) { | |||
4044 | pool->base.opps[i] = dcn20_opp_create(ctx, i); | |||
4045 | if (pool->base.opps[i] == NULL((void *)0)) { | |||
4046 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4046); do {} while (0); } while (0); | |||
4047 | dm_error(__drm_err("DC: failed to create output pixel processor!\n") | |||
4048 | "DC: failed to create output pixel processor!\n")__drm_err("DC: failed to create output pixel processor!\n"); | |||
4049 | goto create_fail; | |||
4050 | } | |||
4051 | } | |||
4052 | ||||
4053 | for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { | |||
4054 | pool->base.timing_generators[i] = dcn20_timing_generator_create( | |||
4055 | ctx, i); | |||
4056 | if (pool->base.timing_generators[i] == NULL((void *)0)) { | |||
4057 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4057); do {} while (0); } while (0); | |||
4058 | dm_error("DC: failed to create tg!\n")__drm_err("DC: failed to create tg!\n"); | |||
4059 | goto create_fail; | |||
4060 | } | |||
4061 | } | |||
4062 | ||||
4063 | pool->base.timing_generator_count = i; | |||
4064 | ||||
4065 | pool->base.mpc = dcn20_mpc_create(ctx); | |||
4066 | if (pool->base.mpc == NULL((void *)0)) { | |||
4067 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4067); do {} while (0); } while (0); | |||
4068 | dm_error("DC: failed to create mpc!\n")__drm_err("DC: failed to create mpc!\n"); | |||
4069 | goto create_fail; | |||
4070 | } | |||
4071 | ||||
4072 | pool->base.hubbub = dcn20_hubbub_create(ctx); | |||
4073 | if (pool->base.hubbub == NULL((void *)0)) { | |||
4074 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4074); do {} while (0); } while (0); | |||
4075 | dm_error("DC: failed to create hubbub!\n")__drm_err("DC: failed to create hubbub!\n"); | |||
4076 | goto create_fail; | |||
4077 | } | |||
4078 | ||||
4079 | for (i = 0; i < pool->base.res_cap->num_dsc; i++) { | |||
4080 | pool->base.dscs[i] = dcn20_dsc_create(ctx, i); | |||
4081 | if (pool->base.dscs[i] == NULL((void *)0)) { | |||
4082 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4082); do {} while (0); } while (0); | |||
4083 | dm_error("DC: failed to create display stream compressor %d!\n", i)__drm_err("DC: failed to create display stream compressor %d!\n" , i); | |||
4084 | goto create_fail; | |||
4085 | } | |||
4086 | } | |||
4087 | ||||
4088 | if (!dcn20_dwbc_create(ctx, &pool->base)) { | |||
4089 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4089); do {} while (0); } while (0); | |||
4090 | dm_error("DC: failed to create dwbc!\n")__drm_err("DC: failed to create dwbc!\n"); | |||
4091 | goto create_fail; | |||
4092 | } | |||
4093 | if (!dcn20_mmhubbub_create(ctx, &pool->base)) { | |||
4094 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4094); do {} while (0); } while (0); | |||
4095 | dm_error("DC: failed to create mcif_wb!\n")__drm_err("DC: failed to create mcif_wb!\n"); | |||
4096 | goto create_fail; | |||
4097 | } | |||
4098 | ||||
4099 | if (!resource_construct(num_virtual_links, dc, &pool->base, | |||
4100 | (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) ? | |||
4101 | &res_create_funcs : &res_create_maximus_funcs))) | |||
4102 | goto create_fail; | |||
4103 | ||||
4104 | dcn20_hw_sequencer_construct(dc); | |||
4105 | ||||
4106 | // IF NV12, set PG function pointer to NULL. It's not that | |||
4107 | // PG isn't supported for NV12, it's that we don't want to | |||
4108 | // program the registers because that will cause more power | |||
4109 | // to be consumed. We could have created dcn20_init_hw to get | |||
4110 | // the same effect by checking ASIC rev, but there was a | |||
4111 | // request at some point to not check ASIC rev on hw sequencer. | |||
4112 | if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)((dc->ctx->asic_id.hw_internal_rev >= NV_NAVI12_P_A0 ) && (dc->ctx->asic_id.hw_internal_rev < NV_NAVI14_M_A0 ))) { | |||
4113 | dc->hwseq->funcs.enable_power_gating_plane = NULL((void *)0); | |||
4114 | dc->debug.disable_dpp_power_gate = true1; | |||
4115 | dc->debug.disable_hubp_power_gate = true1; | |||
4116 | } | |||
4117 | ||||
4118 | ||||
4119 | dc->caps.max_planes = pool->base.pipe_count; | |||
4120 | ||||
4121 | for (i = 0; i < dc->caps.max_planes; ++i) | |||
4122 | dc->caps.planes[i] = plane_cap; | |||
4123 | ||||
4124 | dc->cap_funcs = cap_funcs; | |||
4125 | ||||
4126 | if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { | |||
4127 | ddc_init_data.ctx = dc->ctx; | |||
4128 | ddc_init_data.link = NULL((void *)0); | |||
4129 | ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; | |||
4130 | ddc_init_data.id.enum_id = 0; | |||
4131 | ddc_init_data.id.type = OBJECT_TYPE_GENERIC; | |||
4132 | pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); | |||
4133 | } else { | |||
4134 | pool->base.oem_device = NULL((void *)0); | |||
4135 | } | |||
4136 | ||||
4137 | return true1; | |||
4138 | ||||
4139 | create_fail: | |||
4140 | ||||
4141 | dcn20_resource_destruct(pool); | |||
4142 | ||||
4143 | return false0; | |||
4144 | } | |||
4145 | ||||
4146 | struct resource_pool *dcn20_create_resource_pool( | |||
4147 | const struct dc_init_data *init_data, | |||
4148 | struct dc *dc) | |||
4149 | { | |||
4150 | struct dcn20_resource_pool *pool = | |||
4151 | kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC0x0002); | |||
4152 | ||||
4153 | if (!pool) | |||
4154 | return NULL((void *)0); | |||
4155 | ||||
4156 | if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) | |||
4157 | return &pool->base; | |||
4158 | ||||
4159 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 4159); do {} while (0); } while (0); | |||
4160 | kfree(pool); | |||
4161 | return NULL((void *)0); | |||
4162 | } |