File: | dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c |
Warning: | line 213, column 2 Called function pointer is null (null dereference) |
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1 | /* | |||
2 | * Copyright 2020 Advanced Micro Devices, Inc. | |||
3 | * | |||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
5 | * copy of this software and associated documentation files (the "Software"), | |||
6 | * to deal in the Software without restriction, including without limitation | |||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
8 | * and/or sell copies of the Software, and to permit persons to whom the | |||
9 | * Software is furnished to do so, subject to the following conditions: | |||
10 | * | |||
11 | * The above copyright notice and this permission notice shall be included in | |||
12 | * all copies or substantial portions of the Software. | |||
13 | * | |||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
20 | * OTHER DEALINGS IN THE SOFTWARE. | |||
21 | * | |||
22 | * Authors: AMD | |||
23 | * | |||
24 | */ | |||
25 | ||||
26 | ||||
27 | #include "dm_services.h" | |||
28 | #include "dm_helpers.h" | |||
29 | #include "core_types.h" | |||
30 | #include "resource.h" | |||
31 | #include "dcn30_hwseq.h" | |||
32 | #include "dccg.h" | |||
33 | #include "dce/dce_hwseq.h" | |||
34 | #include "dcn30_mpc.h" | |||
35 | #include "dcn30_dpp.h" | |||
36 | #include "dcn10/dcn10_cm_common.h" | |||
37 | #include "dcn30_cm_common.h" | |||
38 | #include "reg_helper.h" | |||
39 | #include "abm.h" | |||
40 | #include "clk_mgr.h" | |||
41 | #include "hubp.h" | |||
42 | #include "dchubbub.h" | |||
43 | #include "timing_generator.h" | |||
44 | #include "opp.h" | |||
45 | #include "ipp.h" | |||
46 | #include "mpc.h" | |||
47 | #include "mcif_wb.h" | |||
48 | #include "dc_dmub_srv.h" | |||
49 | #include "link_hwss.h" | |||
50 | #include "dpcd_defs.h" | |||
51 | ||||
52 | ||||
53 | ||||
54 | ||||
55 | #define DC_LOGGER_INIT(logger) | |||
56 | ||||
57 | #define CTXhws->ctx \ | |||
58 | hws->ctx | |||
59 | #define REG(reg)hws->regs->reg\ | |||
60 | hws->regs->reg | |||
61 | #define DC_LOGGERdc->ctx->logger \ | |||
62 | dc->ctx->logger | |||
63 | ||||
64 | ||||
65 | #undef FN | |||
66 | #define FN(reg_name, field_name)hws->shifts->field_name, hws->masks->field_name \ | |||
67 | hws->shifts->field_name, hws->masks->field_name | |||
68 | ||||
69 | bool_Bool dcn30_set_blend_lut( | |||
70 | struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) | |||
71 | { | |||
72 | struct dpp *dpp_base = pipe_ctx->plane_res.dpp; | |||
73 | bool_Bool result = true1; | |||
74 | struct pwl_params *blend_lut = NULL((void *)0); | |||
75 | ||||
76 | if (plane_state->blend_tf) { | |||
77 | if (plane_state->blend_tf->type == TF_TYPE_HWPWL) | |||
78 | blend_lut = &plane_state->blend_tf->pwl; | |||
79 | else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { | |||
80 | cm3_helper_translate_curve_to_hw_format( | |||
81 | plane_state->blend_tf, &dpp_base->regamma_params, false0); | |||
82 | blend_lut = &dpp_base->regamma_params; | |||
83 | } | |||
84 | } | |||
85 | result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); | |||
86 | ||||
87 | return result; | |||
88 | } | |||
89 | ||||
90 | static bool_Bool dcn30_set_mpc_shaper_3dlut( | |||
91 | struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) | |||
92 | { | |||
93 | struct dpp *dpp_base = pipe_ctx->plane_res.dpp; | |||
94 | int mpcc_id = pipe_ctx->plane_res.hubp->inst; | |||
95 | struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; | |||
96 | bool_Bool result = false0; | |||
97 | int acquired_rmu = 0; | |||
98 | int mpcc_id_projected = 0; | |||
99 | ||||
100 | const struct pwl_params *shaper_lut = NULL((void *)0); | |||
101 | //get the shaper lut params | |||
102 | if (stream->func_shaper) { | |||
103 | if (stream->func_shaper->type == TF_TYPE_HWPWL) | |||
104 | shaper_lut = &stream->func_shaper->pwl; | |||
105 | else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { | |||
106 | cm_helper_translate_curve_to_hw_format( | |||
107 | stream->func_shaper, | |||
108 | &dpp_base->shaper_params, true1); | |||
109 | shaper_lut = &dpp_base->shaper_params; | |||
110 | } | |||
111 | } | |||
112 | ||||
113 | if (stream->lut3d_func && | |||
114 | stream->lut3d_func->state.bits.initialized == 1 && | |||
115 | stream->lut3d_func->state.bits.rmu_idx_valid == 1) { | |||
116 | if (stream->lut3d_func->state.bits.rmu_mux_num == 0) | |||
117 | mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux; | |||
118 | else if (stream->lut3d_func->state.bits.rmu_mux_num == 1) | |||
119 | mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux; | |||
120 | else if (stream->lut3d_func->state.bits.rmu_mux_num == 2) | |||
121 | mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux; | |||
122 | if (mpcc_id_projected != mpcc_id) | |||
123 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 123); do {} while (0); } while (0); | |||
124 | /*find the reason why logical layer assigned a differant mpcc_id into acquire_post_bldn_3dlut*/ | |||
125 | acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, | |||
126 | stream->lut3d_func->state.bits.rmu_mux_num); | |||
127 | if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num) | |||
128 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 128); do {} while (0); } while (0); | |||
129 | result = mpc->funcs->program_3dlut(mpc, | |||
130 | &stream->lut3d_func->lut_3d, | |||
131 | stream->lut3d_func->state.bits.rmu_mux_num); | |||
132 | result = mpc->funcs->program_shaper(mpc, shaper_lut, | |||
133 | stream->lut3d_func->state.bits.rmu_mux_num); | |||
134 | } else | |||
135 | /*loop through the available mux and release the requested mpcc_id*/ | |||
136 | mpc->funcs->release_rmu(mpc, mpcc_id); | |||
137 | ||||
138 | ||||
139 | return result; | |||
140 | } | |||
141 | ||||
142 | bool_Bool dcn30_set_input_transfer_func(struct dc *dc, | |||
143 | struct pipe_ctx *pipe_ctx, | |||
144 | const struct dc_plane_state *plane_state) | |||
145 | { | |||
146 | struct dce_hwseq *hws = dc->hwseq; | |||
147 | struct dpp *dpp_base = pipe_ctx->plane_res.dpp; | |||
148 | enum dc_transfer_func_predefined tf; | |||
149 | bool_Bool result = true1; | |||
150 | struct pwl_params *params = NULL((void *)0); | |||
151 | ||||
152 | if (dpp_base == NULL((void *)0) || plane_state == NULL((void *)0)) | |||
153 | return false0; | |||
154 | ||||
155 | tf = TRANSFER_FUNCTION_UNITY; | |||
156 | ||||
157 | if (plane_state->in_transfer_func && | |||
158 | plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) | |||
159 | tf = plane_state->in_transfer_func->tf; | |||
160 | ||||
161 | dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); | |||
162 | ||||
163 | if (plane_state->in_transfer_func) { | |||
164 | if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) | |||
165 | params = &plane_state->in_transfer_func->pwl; | |||
166 | else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && | |||
167 | cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, | |||
168 | &dpp_base->degamma_params, false0)) | |||
169 | params = &dpp_base->degamma_params; | |||
170 | } | |||
171 | ||||
172 | result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); | |||
173 | ||||
174 | if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { | |||
175 | if (dpp_base->funcs->dpp_program_blnd_lut) | |||
176 | hws->funcs.set_blend_lut(pipe_ctx, plane_state); | |||
177 | if (dpp_base->funcs->dpp_program_shaper_lut && | |||
178 | dpp_base->funcs->dpp_program_3dlut) | |||
179 | hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); | |||
180 | } | |||
181 | ||||
182 | return result; | |||
183 | } | |||
184 | ||||
185 | bool_Bool dcn30_set_output_transfer_func(struct dc *dc, | |||
186 | struct pipe_ctx *pipe_ctx, | |||
187 | const struct dc_stream_state *stream) | |||
188 | { | |||
189 | int mpcc_id = pipe_ctx->plane_res.hubp->inst; | |||
190 | struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; | |||
191 | struct pwl_params *params = NULL((void *)0); | |||
192 | bool_Bool ret = false0; | |||
193 | ||||
194 | /* program OGAM or 3DLUT only for the top pipe*/ | |||
195 | if (pipe_ctx->top_pipe == NULL((void *)0)) { | |||
| ||||
196 | /*program rmu shaper and 3dlut in MPC*/ | |||
197 | ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream); | |||
198 | if (ret
| |||
199 | if (stream->out_transfer_func->type == TF_TYPE_HWPWL) | |||
200 | params = &stream->out_transfer_func->pwl; | |||
201 | else if (pipe_ctx->stream->out_transfer_func->type == | |||
202 | TF_TYPE_DISTRIBUTED_POINTS && | |||
203 | cm3_helper_translate_curve_to_hw_format( | |||
204 | stream->out_transfer_func, | |||
205 | &mpc->blender_params, false0)) | |||
206 | params = &mpc->blender_params; | |||
207 | /* there are no ROM LUTs in OUTGAM */ | |||
208 | if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) | |||
209 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 209); do {} while (0); } while (0); | |||
210 | } | |||
211 | } | |||
212 | ||||
213 | mpc->funcs->set_output_gamma(mpc, mpcc_id, params); | |||
| ||||
214 | return ret; | |||
215 | } | |||
216 | ||||
217 | static void dcn30_set_writeback( | |||
218 | struct dc *dc, | |||
219 | struct dc_writeback_info *wb_info, | |||
220 | struct dc_state *context) | |||
221 | { | |||
222 | struct mcif_wb *mcif_wb; | |||
223 | struct mcif_buf_params *mcif_buf_params; | |||
224 | ||||
225 | ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES)do { if (({ static int __warned; int __ret = !!(!(wb_info-> dwb_pipe_inst < 1)); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(wb_info->dwb_pipe_inst < 1)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 225); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
226 | ASSERT(wb_info->wb_enabled)do { if (({ static int __warned; int __ret = !!(!(wb_info-> wb_enabled)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(wb_info->wb_enabled)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 226); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
227 | ASSERT(wb_info->mpcc_inst >= 0)do { if (({ static int __warned; int __ret = !!(!(wb_info-> mpcc_inst >= 0)); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(wb_info->mpcc_inst >= 0)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 227); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
228 | ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count)do { if (({ static int __warned; int __ret = !!(!(wb_info-> mpcc_inst < dc->res_pool->mpcc_count)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(wb_info->mpcc_inst < dc->res_pool->mpcc_count)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 228); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
229 | mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; | |||
230 | mcif_buf_params = &wb_info->mcif_buf_params; | |||
231 | ||||
232 | /* set DWB MPC mux */ | |||
233 | dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, | |||
234 | wb_info->dwb_pipe_inst, wb_info->mpcc_inst); | |||
235 | /* set MCIF_WB buffer and arbitration configuration */ | |||
236 | mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height); | |||
237 | mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); | |||
238 | } | |||
239 | ||||
240 | void dcn30_update_writeback( | |||
241 | struct dc *dc, | |||
242 | struct dc_writeback_info *wb_info, | |||
243 | struct dc_state *context) | |||
244 | { | |||
245 | struct dwbc *dwb; | |||
246 | dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; | |||
247 | DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\__drm_dbg(DRM_UT_KMS, "%s dwb_pipe_inst = %d, mpcc_inst = %d" , __func__, wb_info->dwb_pipe_inst, wb_info->mpcc_inst) | |||
248 | __func__, wb_info->dwb_pipe_inst,\__drm_dbg(DRM_UT_KMS, "%s dwb_pipe_inst = %d, mpcc_inst = %d" , __func__, wb_info->dwb_pipe_inst, wb_info->mpcc_inst) | |||
249 | wb_info->mpcc_inst)__drm_dbg(DRM_UT_KMS, "%s dwb_pipe_inst = %d, mpcc_inst = %d" , __func__, wb_info->dwb_pipe_inst, wb_info->mpcc_inst); | |||
250 | ||||
251 | dcn30_set_writeback(dc, wb_info, context); | |||
252 | ||||
253 | /* update DWB */ | |||
254 | dwb->funcs->update(dwb, &wb_info->dwb_params); | |||
255 | } | |||
256 | ||||
257 | bool_Bool dcn30_mmhubbub_warmup( | |||
258 | struct dc *dc, | |||
259 | unsigned int num_dwb, | |||
260 | struct dc_writeback_info *wb_info) | |||
261 | { | |||
262 | struct dwbc *dwb; | |||
263 | struct mcif_wb *mcif_wb; | |||
264 | struct mcif_warmup_params warmup_params = {0}; | |||
265 | unsigned int i, i_buf; | |||
266 | /*make sure there is no active DWB eanbled */ | |||
267 | for (i = 0; i < num_dwb; i++) { | |||
268 | dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; | |||
269 | if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) { | |||
270 | /*can not do warmup while any dwb enabled*/ | |||
271 | return false0; | |||
272 | } | |||
273 | } | |||
274 | ||||
275 | if (wb_info->mcif_warmup_params.p_vmid == 0) | |||
276 | return false0; | |||
277 | ||||
278 | /*check whether this is new interface: warmup big buffer once*/ | |||
279 | if (wb_info->mcif_warmup_params.start_address.quad_part != 0 && | |||
280 | wb_info->mcif_warmup_params.region_size != 0) { | |||
281 | /*mmhubbub is shared, so it does not matter which MCIF*/ | |||
282 | mcif_wb = dc->res_pool->mcif_wb[0]; | |||
283 | /*warmup a big chunk of VM buffer at once*/ | |||
284 | warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part; | |||
285 | warmup_params.address_increment = wb_info->mcif_warmup_params.region_size; | |||
286 | warmup_params.region_size = wb_info->mcif_warmup_params.region_size; | |||
287 | warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid; | |||
288 | ||||
289 | if (warmup_params.address_increment == 0) | |||
290 | warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; | |||
291 | ||||
292 | mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params); | |||
293 | return true1; | |||
294 | } | |||
295 | /*following is the original: warmup each DWB's mcif buffer*/ | |||
296 | for (i = 0; i < num_dwb; i++) { | |||
297 | dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; | |||
298 | mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; | |||
299 | /*warmup is for VM mode only*/ | |||
300 | if (wb_info[i].mcif_buf_params.p_vmid == 0) | |||
301 | return false0; | |||
302 | ||||
303 | /* Warmup MCIF_WB */ | |||
304 | for (i_buf = 0; i_buf < MCIF_BUF_COUNT4; i_buf++) { | |||
305 | warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf]; | |||
306 | warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; | |||
307 | warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height; | |||
308 | warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid; | |||
309 | mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params); | |||
310 | } | |||
311 | } | |||
312 | return true1; | |||
313 | } | |||
314 | ||||
315 | void dcn30_enable_writeback( | |||
316 | struct dc *dc, | |||
317 | struct dc_writeback_info *wb_info, | |||
318 | struct dc_state *context) | |||
319 | { | |||
320 | struct dwbc *dwb; | |||
321 | struct mcif_wb *mcif_wb; | |||
322 | struct timing_generator *optc; | |||
323 | ||||
324 | dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; | |||
325 | mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; | |||
326 | ||||
327 | /* set the OPTC source mux */ | |||
328 | optc = dc->res_pool->timing_generators[dwb->otg_inst]; | |||
329 | DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\__drm_dbg(DRM_UT_KMS, "%s dwb_pipe_inst = %d, mpcc_inst = %d" , __func__, wb_info->dwb_pipe_inst, wb_info->mpcc_inst) | |||
330 | __func__, wb_info->dwb_pipe_inst,\__drm_dbg(DRM_UT_KMS, "%s dwb_pipe_inst = %d, mpcc_inst = %d" , __func__, wb_info->dwb_pipe_inst, wb_info->mpcc_inst) | |||
331 | wb_info->mpcc_inst)__drm_dbg(DRM_UT_KMS, "%s dwb_pipe_inst = %d, mpcc_inst = %d" , __func__, wb_info->dwb_pipe_inst, wb_info->mpcc_inst); | |||
332 | if (IS_DIAG_DC(dc->ctx->dce_environment)((dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) || ( dc->ctx->dce_environment == DCE_ENV_DIAG))) { | |||
333 | /*till diags switch to warmup interface*/ | |||
334 | dcn30_mmhubbub_warmup(dc, 1, wb_info); | |||
335 | } | |||
336 | /* Update writeback pipe */ | |||
337 | dcn30_set_writeback(dc, wb_info, context); | |||
338 | ||||
339 | /* Enable MCIF_WB */ | |||
340 | mcif_wb->funcs->enable_mcif(mcif_wb); | |||
341 | /* Enable DWB */ | |||
342 | dwb->funcs->enable(dwb, &wb_info->dwb_params); | |||
343 | } | |||
344 | ||||
345 | void dcn30_disable_writeback( | |||
346 | struct dc *dc, | |||
347 | unsigned int dwb_pipe_inst) | |||
348 | { | |||
349 | struct dwbc *dwb; | |||
350 | struct mcif_wb *mcif_wb; | |||
351 | ||||
352 | ASSERT(dwb_pipe_inst < MAX_DWB_PIPES)do { if (({ static int __warned; int __ret = !!(!(dwb_pipe_inst < 1)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dwb_pipe_inst < 1)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 352); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
353 | dwb = dc->res_pool->dwbc[dwb_pipe_inst]; | |||
354 | mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; | |||
355 | DC_LOG_DWB("%s dwb_pipe_inst = %d",\__drm_dbg(DRM_UT_KMS, "%s dwb_pipe_inst = %d", __func__, dwb_pipe_inst ) | |||
356 | __func__, dwb_pipe_inst)__drm_dbg(DRM_UT_KMS, "%s dwb_pipe_inst = %d", __func__, dwb_pipe_inst ); | |||
357 | ||||
358 | /* disable DWB */ | |||
359 | dwb->funcs->disable(dwb); | |||
360 | /* disable MCIF */ | |||
361 | mcif_wb->funcs->disable_mcif(mcif_wb); | |||
362 | /* disable MPC DWB mux */ | |||
363 | dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst); | |||
364 | } | |||
365 | ||||
366 | void dcn30_program_all_writeback_pipes_in_tree( | |||
367 | struct dc *dc, | |||
368 | const struct dc_stream_state *stream, | |||
369 | struct dc_state *context) | |||
370 | { | |||
371 | struct dc_writeback_info wb_info; | |||
372 | struct dwbc *dwb; | |||
373 | struct dc_stream_status *stream_status = NULL((void *)0); | |||
374 | int i_wb, i_pipe, i_stream; | |||
375 | DC_LOG_DWB("%s", __func__)__drm_dbg(DRM_UT_KMS, "%s", __func__); | |||
376 | ||||
377 | ASSERT(stream)do { if (({ static int __warned; int __ret = !!(!(stream)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(stream)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 377); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
378 | for (i_stream = 0; i_stream < context->stream_count; i_stream++) { | |||
379 | if (context->streams[i_stream] == stream) { | |||
380 | stream_status = &context->stream_status[i_stream]; | |||
381 | break; | |||
382 | } | |||
383 | } | |||
384 | ASSERT(stream_status)do { if (({ static int __warned; int __ret = !!(!(stream_status )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(stream_status)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 384); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
385 | ||||
386 | ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb)do { if (({ static int __warned; int __ret = !!(!(stream-> num_wb_info <= dc->res_pool->res_cap->num_dwb)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 386); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
387 | /* For each writeback pipe */ | |||
388 | for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) { | |||
389 | ||||
390 | /* copy writeback info to local non-const so mpcc_inst can be set */ | |||
391 | wb_info = stream->writeback_info[i_wb]; | |||
392 | if (wb_info.wb_enabled) { | |||
393 | ||||
394 | /* get the MPCC instance for writeback_source_plane */ | |||
395 | wb_info.mpcc_inst = -1; | |||
396 | for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { | |||
397 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; | |||
398 | ||||
399 | if (!pipe_ctx->plane_state) | |||
400 | continue; | |||
401 | ||||
402 | if (pipe_ctx->plane_state == wb_info.writeback_source_plane) { | |||
403 | wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; | |||
404 | break; | |||
405 | } | |||
406 | } | |||
407 | ||||
408 | if (wb_info.mpcc_inst == -1) { | |||
409 | /* Disable writeback pipe and disconnect from MPCC | |||
410 | * if source plane has been removed | |||
411 | */ | |||
412 | dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); | |||
413 | continue; | |||
414 | } | |||
415 | ||||
416 | ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb)do { if (({ static int __warned; int __ret = !!(!(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 416); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
417 | dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst]; | |||
418 | if (dwb->funcs->is_enabled(dwb)) { | |||
419 | /* writeback pipe already enabled, only need to update */ | |||
420 | dc->hwss.update_writeback(dc, &wb_info, context); | |||
421 | } else { | |||
422 | /* Enable writeback pipe and connect to MPCC */ | |||
423 | dc->hwss.enable_writeback(dc, &wb_info, context); | |||
424 | } | |||
425 | } else { | |||
426 | /* Disable writeback pipe and disconnect from MPCC */ | |||
427 | dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); | |||
428 | } | |||
429 | } | |||
430 | } | |||
431 | ||||
432 | void dcn30_init_hw(struct dc *dc) | |||
433 | { | |||
434 | int i, j; | |||
435 | struct abm **abms = dc->res_pool->multiple_abms; | |||
436 | struct dce_hwseq *hws = dc->hwseq; | |||
437 | struct dc_bios *dcb = dc->ctx->dc_bios; | |||
438 | struct resource_pool *res_pool = dc->res_pool; | |||
439 | uint32_t backlight = MAX_BACKLIGHT_LEVEL0xFFFF; | |||
440 | ||||
441 | if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) | |||
442 | dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); | |||
443 | ||||
444 | // Initialize the dccg | |||
445 | if (res_pool->dccg->funcs->dccg_init) | |||
446 | res_pool->dccg->funcs->dccg_init(res_pool->dccg); | |||
447 | ||||
448 | if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) { | |||
449 | ||||
450 | REG_WRITE(REFCLK_CNTL, 0)dm_write_reg_func(hws->ctx, hws->regs->REFCLK_CNTL, 0 , __func__); | |||
451 | REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1)generic_reg_update_ex(hws->ctx, hws->regs->DCHUBBUB_GLOBAL_TIMER_CNTL , 1, hws->shifts->DCHUBBUB_GLOBAL_TIMER_ENABLE, hws-> masks->DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); | |||
452 | REG_WRITE(DIO_MEM_PWR_CTRL, 0)dm_write_reg_func(hws->ctx, hws->regs->DIO_MEM_PWR_CTRL , 0, __func__); | |||
453 | ||||
454 | if (!dc->debug.disable_clock_gate) { | |||
455 | /* enable all DCN clock gating */ | |||
456 | REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0)dm_write_reg_func(hws->ctx, hws->regs->DCCG_GATE_DISABLE_CNTL , 0, __func__); | |||
457 | ||||
458 | REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0)dm_write_reg_func(hws->ctx, hws->regs->DCCG_GATE_DISABLE_CNTL2 , 0, __func__); | |||
459 | ||||
460 | REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0)generic_reg_update_ex(hws->ctx, hws->regs->DCFCLK_CNTL , 1, hws->shifts->DCFCLK_GATE_DIS, hws->masks->DCFCLK_GATE_DIS , 0); | |||
461 | } | |||
462 | ||||
463 | //Enable ability to power gate / don't force power on permanently | |||
464 | if (hws->funcs.enable_power_gating_plane) | |||
465 | hws->funcs.enable_power_gating_plane(hws, true1); | |||
466 | ||||
467 | return; | |||
468 | } | |||
469 | ||||
470 | if (!dcb->funcs->is_accelerated_mode(dcb)) { | |||
471 | hws->funcs.bios_golden_init(dc); | |||
472 | hws->funcs.disable_vga(dc->hwseq); | |||
473 | } | |||
474 | ||||
475 | if (dc->ctx->dc_bios->fw_info_valid) { | |||
476 | res_pool->ref_clocks.xtalin_clock_inKhz = | |||
477 | dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; | |||
478 | ||||
479 | if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)(dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) { | |||
480 | if (res_pool->dccg && res_pool->hubbub) { | |||
481 | ||||
482 | (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, | |||
483 | dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, | |||
484 | &res_pool->ref_clocks.dccg_ref_clock_inKhz); | |||
485 | ||||
486 | (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, | |||
487 | res_pool->ref_clocks.dccg_ref_clock_inKhz, | |||
488 | &res_pool->ref_clocks.dchub_ref_clock_inKhz); | |||
489 | } else { | |||
490 | // Not all ASICs have DCCG sw component | |||
491 | res_pool->ref_clocks.dccg_ref_clock_inKhz = | |||
492 | res_pool->ref_clocks.xtalin_clock_inKhz; | |||
493 | res_pool->ref_clocks.dchub_ref_clock_inKhz = | |||
494 | res_pool->ref_clocks.xtalin_clock_inKhz; | |||
495 | } | |||
496 | } | |||
497 | } else | |||
498 | ASSERT_CRITICAL(false)do { if (({ int __ret = !!(!(0)); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 498); __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
499 | ||||
500 | for (i = 0; i < dc->link_count; i++) { | |||
501 | /* Power up AND update implementation according to the | |||
502 | * required signal (which may be different from the | |||
503 | * default signal on connector). | |||
504 | */ | |||
505 | struct dc_link *link = dc->links[i]; | |||
506 | ||||
507 | link->link_enc->funcs->hw_init(link->link_enc); | |||
508 | ||||
509 | /* Check for enabled DIG to identify enabled display */ | |||
510 | if (link->link_enc->funcs->is_dig_enabled && | |||
511 | link->link_enc->funcs->is_dig_enabled(link->link_enc)) | |||
512 | link->link_status.link_active = true1; | |||
513 | } | |||
514 | ||||
515 | /* Power gate DSCs */ | |||
516 | for (i = 0; i < res_pool->res_cap->num_dsc; i++) | |||
517 | if (hws->funcs.dsc_pg_control != NULL((void *)0)) | |||
518 | hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false0); | |||
519 | ||||
520 | /* we want to turn off all dp displays before doing detection */ | |||
521 | if (dc->config.power_down_display_on_boot) { | |||
522 | uint8_t dpcd_power_state = '\0'; | |||
523 | enum dc_status status = DC_ERROR_UNEXPECTED; | |||
524 | ||||
525 | for (i = 0; i < dc->link_count; i++) { | |||
526 | if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) | |||
527 | continue; | |||
528 | ||||
529 | /* if any of the displays are lit up turn them off */ | |||
530 | status = core_link_read_dpcd(dc->links[i], DP_SET_POWER0x600, | |||
531 | &dpcd_power_state, sizeof(dpcd_power_state)); | |||
532 | if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { | |||
533 | /* blank dp stream before power off receiver*/ | |||
534 | if (dc->links[i]->link_enc->funcs->get_dig_frontend) { | |||
535 | unsigned int fe; | |||
536 | ||||
537 | fe = dc->links[i]->link_enc->funcs->get_dig_frontend( | |||
538 | dc->links[i]->link_enc); | |||
539 | if (fe == ENGINE_ID_UNKNOWN) | |||
540 | continue; | |||
541 | ||||
542 | for (j = 0; j < dc->res_pool->stream_enc_count; j++) { | |||
543 | if (fe == dc->res_pool->stream_enc[j]->id) { | |||
544 | dc->res_pool->stream_enc[j]->funcs->dp_blank( | |||
545 | dc->res_pool->stream_enc[j]); | |||
546 | break; | |||
547 | } | |||
548 | } | |||
549 | } | |||
550 | dp_receiver_power_ctrl(dc->links[i], false0); | |||
551 | } | |||
552 | } | |||
553 | } | |||
554 | ||||
555 | /* If taking control over from VBIOS, we may want to optimize our first | |||
556 | * mode set, so we need to skip powering down pipes until we know which | |||
557 | * pipes we want to use. | |||
558 | * Otherwise, if taking control is not possible, we need to power | |||
559 | * everything down. | |||
560 | */ | |||
561 | if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { | |||
562 | hws->funcs.init_pipes(dc, dc->current_state); | |||
563 | if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) | |||
564 | dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, | |||
565 | !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); | |||
566 | } | |||
567 | ||||
568 | /* In headless boot cases, DIG may be turned | |||
569 | * on which causes HW/SW discrepancies. | |||
570 | * To avoid this, power down hardware on boot | |||
571 | * if DIG is turned on and seamless boot not enabled | |||
572 | */ | |||
573 | if (dc->config.power_down_display_on_boot) { | |||
574 | struct dc_link *edp_link = get_edp_link(dc); | |||
575 | ||||
576 | if (edp_link && | |||
577 | edp_link->link_enc->funcs->is_dig_enabled && | |||
578 | edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && | |||
579 | dc->hwss.edp_backlight_control && | |||
580 | dc->hwss.power_down && | |||
581 | dc->hwss.edp_power_control) { | |||
582 | dc->hwss.edp_backlight_control(edp_link, false0); | |||
583 | dc->hwss.power_down(dc); | |||
584 | dc->hwss.edp_power_control(edp_link, false0); | |||
585 | } else { | |||
586 | for (i = 0; i < dc->link_count; i++) { | |||
587 | struct dc_link *link = dc->links[i]; | |||
588 | ||||
589 | if (link->link_enc->funcs->is_dig_enabled && | |||
590 | link->link_enc->funcs->is_dig_enabled(link->link_enc) && | |||
591 | dc->hwss.power_down) { | |||
592 | dc->hwss.power_down(dc); | |||
593 | break; | |||
594 | } | |||
595 | ||||
596 | } | |||
597 | } | |||
598 | } | |||
599 | ||||
600 | for (i = 0; i < res_pool->audio_count; i++) { | |||
601 | struct audio *audio = res_pool->audios[i]; | |||
602 | ||||
603 | audio->funcs->hw_init(audio); | |||
604 | } | |||
605 | ||||
606 | for (i = 0; i < dc->link_count; i++) { | |||
607 | struct dc_link *link = dc->links[i]; | |||
608 | ||||
609 | if (link->panel_cntl) | |||
610 | backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); | |||
611 | } | |||
612 | ||||
613 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | |||
614 | if (abms[i] != NULL((void *)0)) | |||
615 | abms[i]->funcs->abm_init(abms[i], backlight); | |||
616 | } | |||
617 | ||||
618 | /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ | |||
619 | REG_WRITE(DIO_MEM_PWR_CTRL, 0)dm_write_reg_func(hws->ctx, hws->regs->DIO_MEM_PWR_CTRL , 0, __func__); | |||
620 | ||||
621 | if (!dc->debug.disable_clock_gate) { | |||
622 | /* enable all DCN clock gating */ | |||
623 | REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0)dm_write_reg_func(hws->ctx, hws->regs->DCCG_GATE_DISABLE_CNTL , 0, __func__); | |||
624 | ||||
625 | REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0)dm_write_reg_func(hws->ctx, hws->regs->DCCG_GATE_DISABLE_CNTL2 , 0, __func__); | |||
626 | ||||
627 | REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0)generic_reg_update_ex(hws->ctx, hws->regs->DCFCLK_CNTL , 1, hws->shifts->DCFCLK_GATE_DIS, hws->masks->DCFCLK_GATE_DIS , 0); | |||
628 | } | |||
629 | if (hws->funcs.enable_power_gating_plane) | |||
630 | hws->funcs.enable_power_gating_plane(dc->hwseq, true1); | |||
631 | ||||
632 | if (dc->clk_mgr->funcs->notify_wm_ranges) | |||
633 | dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); | |||
634 | ||||
635 | if (dc->clk_mgr->funcs->set_hard_max_memclk) | |||
636 | dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); | |||
637 | } | |||
638 | ||||
639 | void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool_Bool enable) | |||
640 | { | |||
641 | if (pipe_ctx == NULL((void *)0)) | |||
642 | return; | |||
643 | ||||
644 | if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL((void *)0)) | |||
645 | pipe_ctx->stream_res.stream_enc->funcs->set_avmute( | |||
646 | pipe_ctx->stream_res.stream_enc, | |||
647 | enable); | |||
648 | } | |||
649 | ||||
650 | void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx) | |||
651 | { | |||
652 | bool_Bool is_hdmi_tmds; | |||
653 | bool_Bool is_dp; | |||
654 | ||||
655 | ASSERT(pipe_ctx->stream)do { if (({ static int __warned; int __ret = !!(!(pipe_ctx-> stream)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipe_ctx->stream)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_hwseq.c" , 655); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
656 | ||||
657 | if (pipe_ctx->stream_res.stream_enc == NULL((void *)0)) | |||
658 | return; /* this is not root pipe */ | |||
659 | ||||
660 | is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); | |||
661 | is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); | |||
662 | ||||
663 | if (!is_hdmi_tmds) | |||
664 | return; | |||
665 | ||||
666 | if (is_hdmi_tmds) | |||
667 | pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( | |||
668 | pipe_ctx->stream_res.stream_enc, | |||
669 | &pipe_ctx->stream_res.encoder_info_frame); | |||
670 | else | |||
671 | pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( | |||
672 | pipe_ctx->stream_res.stream_enc, | |||
673 | &pipe_ctx->stream_res.encoder_info_frame); | |||
674 | } | |||
675 | ||||
676 | void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx) | |||
677 | { | |||
678 | struct dc_stream_state *stream = pipe_ctx->stream; | |||
679 | struct hubp *hubp = pipe_ctx->plane_res.hubp; | |||
680 | bool_Bool enable = false0; | |||
681 | struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; | |||
682 | enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) | |||
683 | ? dmdata_dp | |||
684 | : dmdata_hdmi; | |||
685 | ||||
686 | /* if using dynamic meta, don't set up generic infopackets */ | |||
687 | if (pipe_ctx->stream->dmdata_address.quad_part != 0) { | |||
688 | pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false0; | |||
689 | enable = true1; | |||
690 | } | |||
691 | ||||
692 | if (!hubp) | |||
693 | return; | |||
694 | ||||
695 | if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) | |||
696 | return; | |||
697 | ||||
698 | stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, | |||
699 | hubp->inst, mode); | |||
700 | } | |||
701 | ||||
702 | bool_Bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool_Bool enable) | |||
703 | { | |||
704 | if (!dc->ctx->dmub_srv) | |||
705 | return false0; | |||
706 | ||||
707 | if (enable) { | |||
708 | if (dc->current_state) { | |||
709 | int i; | |||
710 | ||||
711 | /* First, check no-memory-requests case */ | |||
712 | for (i = 0; i < dc->current_state->stream_count; i++) { | |||
713 | if (dc->current_state->stream_status[i] | |||
714 | .plane_count) | |||
715 | /* Fail eligibility on a visible stream */ | |||
716 | break; | |||
717 | } | |||
718 | } | |||
719 | ||||
720 | /* No applicable optimizations */ | |||
721 | return false0; | |||
722 | } | |||
723 | ||||
724 | return true1; | |||
725 | } |