Bug Summary

File:dev/pci/drm/amd/amdgpu/iceland_ih.c
Warning:line 389, column 3
Value stored to 'tmp' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name iceland_ih.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "vid.h"
29
30#include "oss/oss_2_4_d.h"
31#include "oss/oss_2_4_sh_mask.h"
32
33#include "bif/bif_5_1_d.h"
34#include "bif/bif_5_1_sh_mask.h"
35
36/*
37 * Interrupts
38 * Starting with r6xx, interrupts are handled via a ring buffer.
39 * Ring buffers are areas of GPU accessible memory that the GPU
40 * writes interrupt vectors into and the host reads vectors out of.
41 * There is a rptr (read pointer) that determines where the
42 * host is currently reading, and a wptr (write pointer)
43 * which determines where the GPU has written. When the
44 * pointers are equal, the ring is idle. When the GPU
45 * writes vectors to the ring buffer, it increments the
46 * wptr. When there is an interrupt, the host then starts
47 * fetching commands and processing them until the pointers are
48 * equal again at which point it updates the rptr.
49 */
50
51static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev);
52
53/**
54 * iceland_ih_enable_interrupts - Enable the interrupt ring buffer
55 *
56 * @adev: amdgpu_device pointer
57 *
58 * Enable the interrupt ring buffer (VI).
59 */
60static void iceland_ih_enable_interrupts(struct amdgpu_device *adev)
61{
62 u32 ih_cntl = RREG32(mmIH_CNTL)amdgpu_device_rreg(adev, (0xe36), 0);
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL)amdgpu_device_rreg(adev, (0xe30), 0);
64
65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1)(((ih_cntl) & ~0x1) | (0x1 & ((1) << 0x0)));
66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1)(((ih_rb_cntl) & ~0x1) | (0x1 & ((1) << 0x0)));
67 WREG32(mmIH_CNTL, ih_cntl)amdgpu_device_wreg(adev, (0xe36), (ih_cntl), 0);
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl)amdgpu_device_wreg(adev, (0xe30), (ih_rb_cntl), 0);
69 adev->irq.ih.enabled = true1;
70}
71
72/**
73 * iceland_ih_disable_interrupts - Disable the interrupt ring buffer
74 *
75 * @adev: amdgpu_device pointer
76 *
77 * Disable the interrupt ring buffer (VI).
78 */
79static void iceland_ih_disable_interrupts(struct amdgpu_device *adev)
80{
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL)amdgpu_device_rreg(adev, (0xe30), 0);
82 u32 ih_cntl = RREG32(mmIH_CNTL)amdgpu_device_rreg(adev, (0xe36), 0);
83
84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0)(((ih_rb_cntl) & ~0x1) | (0x1 & ((0) << 0x0)));
85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0)(((ih_cntl) & ~0x1) | (0x1 & ((0) << 0x0)));
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl)amdgpu_device_wreg(adev, (0xe30), (ih_rb_cntl), 0);
87 WREG32(mmIH_CNTL, ih_cntl)amdgpu_device_wreg(adev, (0xe36), (ih_cntl), 0);
88 /* set rptr, wptr to 0 */
89 WREG32(mmIH_RB_RPTR, 0)amdgpu_device_wreg(adev, (0xe32), (0), 0);
90 WREG32(mmIH_RB_WPTR, 0)amdgpu_device_wreg(adev, (0xe33), (0), 0);
91 adev->irq.ih.enabled = false0;
92 adev->irq.ih.rptr = 0;
93}
94
95/**
96 * iceland_ih_irq_init - init and enable the interrupt ring
97 *
98 * @adev: amdgpu_device pointer
99 *
100 * Allocate a ring buffer for the interrupt controller,
101 * enable the RLC, disable interrupts, enable the IH
102 * ring buffer and enable it (VI).
103 * Called at device load and reume.
104 * Returns 0 for success, errors for failure.
105 */
106static int iceland_ih_irq_init(struct amdgpu_device *adev)
107{
108 struct amdgpu_ih_ring *ih = &adev->irq.ih;
109 int rb_bufsz;
110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
111
112 /* disable irqs */
113 iceland_ih_disable_interrupts(adev);
114
115 /* setup interrupt control */
116 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8)amdgpu_device_wreg(adev, (0x151b), (adev->dummy_page_addr >>
8), 0)
;
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL)amdgpu_device_rreg(adev, (0x151a), 0);
118 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
119 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
120 */
121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0)(((interrupt_cntl) & ~0x1) | (0x1 & ((0) << 0x0
)))
;
122 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
123 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0)(((interrupt_cntl) & ~0x8) | (0x8 & ((0) << 0x3
)))
;
124 WREG32(mmINTERRUPT_CNTL, interrupt_cntl)amdgpu_device_wreg(adev, (0x151a), (interrupt_cntl), 0);
125
126 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8)amdgpu_device_wreg(adev, (0xe31), (adev->irq.ih.gpu_addr >>
8), 0)
;
128
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4)drm_order(adev->irq.ih.ring_size / 4);
130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1)(((0) & ~0x10000) | (0x10000 & ((1) << 0x10)));
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1)(((ih_rb_cntl) & ~0x80000000) | (0x80000000 & ((1) <<
0x1f)))
;
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz)(((ih_rb_cntl) & ~0x3e) | (0x3e & ((rb_bufsz) <<
0x1)))
;
133
134 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1)(((ih_rb_cntl) & ~0x100) | (0x100 & ((1) << 0x8
)))
;
136
137 /* set the writeback address whether it's enabled or not */
138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr))amdgpu_device_wreg(adev, (0xe35), (((u32)(ih->wptr_addr)))
, 0)
;
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF)amdgpu_device_wreg(adev, (0xe34), (((u32)(((ih->wptr_addr)
>> 16) >> 16)) & 0xFF), 0)
;
140
141 WREG32(mmIH_RB_CNTL, ih_rb_cntl)amdgpu_device_wreg(adev, (0xe30), (ih_rb_cntl), 0);
142
143 /* set rptr, wptr to 0 */
144 WREG32(mmIH_RB_RPTR, 0)amdgpu_device_wreg(adev, (0xe32), (0), 0);
145 WREG32(mmIH_RB_WPTR, 0)amdgpu_device_wreg(adev, (0xe33), (0), 0);
146
147 /* Default settings for IH_CNTL (disabled at first) */
148 ih_cntl = RREG32(mmIH_CNTL)amdgpu_device_rreg(adev, (0xe36), 0);
149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0)(((ih_cntl) & ~0x1e000000) | (0x1e000000 & ((0) <<
0x19)))
;
150
151 if (adev->irq.msi_enabled)
152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1)(((ih_cntl) & ~0x10) | (0x10 & ((1) << 0x4)));
153 WREG32(mmIH_CNTL, ih_cntl)amdgpu_device_wreg(adev, (0xe36), (ih_cntl), 0);
154
155 pci_set_master(adev->pdev);
156
157 /* enable interrupts */
158 iceland_ih_enable_interrupts(adev);
159
160 return 0;
161}
162
163/**
164 * iceland_ih_irq_disable - disable interrupts
165 *
166 * @adev: amdgpu_device pointer
167 *
168 * Disable interrupts on the hw (VI).
169 */
170static void iceland_ih_irq_disable(struct amdgpu_device *adev)
171{
172 iceland_ih_disable_interrupts(adev);
173
174 /* Wait and acknowledge irq */
175 mdelay(1);
176}
177
178/**
179 * iceland_ih_get_wptr - get the IH ring buffer wptr
180 *
181 * @adev: amdgpu_device pointer
182 *
183 * Get the IH ring buffer wptr from either the register
184 * or the writeback memory buffer (VI). Also check for
185 * ring buffer overflow and deal with it.
186 * Used by cz_irq_process(VI).
187 * Returns the value of the wptr.
188 */
189static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
190 struct amdgpu_ih_ring *ih)
191{
192 u32 wptr, tmp;
193
194 wptr = le32_to_cpu(*ih->wptr_cpu)((__uint32_t)(*ih->wptr_cpu));
195
196 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)(((wptr) & 0x1) >> 0x0))
197 goto out;
198
199 /* Double check that the overflow wasn't already cleared. */
200 wptr = RREG32(mmIH_RB_WPTR)amdgpu_device_rreg(adev, (0xe33), 0);
201
202 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)(((wptr) & 0x1) >> 0x0))
203 goto out;
204
205 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0)(((wptr) & ~0x1) | (0x1 & ((0) << 0x0)));
206 /* When a ring buffer overflow happen start parsing interrupt
207 * from the last not overwritten vector (wptr + 16). Hopefully
208 * this should allow us to catchup.
209 */
210 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , wptr, ih
->rptr, (wptr + 16) & ih->ptr_mask)
211 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask)printf("drm:pid%d:%s *WARNING* " "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , wptr, ih
->rptr, (wptr + 16) & ih->ptr_mask)
;
212 ih->rptr = (wptr + 16) & ih->ptr_mask;
213 tmp = RREG32(mmIH_RB_CNTL)amdgpu_device_rreg(adev, (0xe30), 0);
214 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1)(((tmp) & ~0x80000000) | (0x80000000 & ((1) << 0x1f
)))
;
215 WREG32(mmIH_RB_CNTL, tmp)amdgpu_device_wreg(adev, (0xe30), (tmp), 0);
216
217
218out:
219 return (wptr & ih->ptr_mask);
220}
221
222/**
223 * iceland_ih_decode_iv - decode an interrupt vector
224 *
225 * @adev: amdgpu_device pointer
226 *
227 * Decodes the interrupt vector at the current rptr
228 * position and also advance the position.
229 */
230static void iceland_ih_decode_iv(struct amdgpu_device *adev,
231 struct amdgpu_ih_ring *ih,
232 struct amdgpu_iv_entry *entry)
233{
234 /* wptr/rptr are in bytes! */
235 u32 ring_index = ih->rptr >> 2;
236 uint32_t dw[4];
237
238 dw[0] = le32_to_cpu(ih->ring[ring_index + 0])((__uint32_t)(ih->ring[ring_index + 0]));
239 dw[1] = le32_to_cpu(ih->ring[ring_index + 1])((__uint32_t)(ih->ring[ring_index + 1]));
240 dw[2] = le32_to_cpu(ih->ring[ring_index + 2])((__uint32_t)(ih->ring[ring_index + 2]));
241 dw[3] = le32_to_cpu(ih->ring[ring_index + 3])((__uint32_t)(ih->ring[ring_index + 3]));
242
243 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY0;
244 entry->src_id = dw[0] & 0xff;
245 entry->src_data[0] = dw[1] & 0xfffffff;
246 entry->ring_id = dw[2] & 0xff;
247 entry->vmid = (dw[2] >> 8) & 0xff;
248 entry->pasid = (dw[2] >> 16) & 0xffff;
249
250 /* wptr/rptr are in bytes! */
251 ih->rptr += 16;
252}
253
254/**
255 * iceland_ih_set_rptr - set the IH ring buffer rptr
256 *
257 * @adev: amdgpu_device pointer
258 *
259 * Set the IH ring buffer rptr.
260 */
261static void iceland_ih_set_rptr(struct amdgpu_device *adev,
262 struct amdgpu_ih_ring *ih)
263{
264 WREG32(mmIH_RB_RPTR, ih->rptr)amdgpu_device_wreg(adev, (0xe32), (ih->rptr), 0);
265}
266
267static int iceland_ih_early_init(void *handle)
268{
269 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
270 int ret;
271
272 ret = amdgpu_irq_add_domain(adev);
273 if (ret)
274 return ret;
275
276 iceland_ih_set_interrupt_funcs(adev);
277
278 return 0;
279}
280
281static int iceland_ih_sw_init(void *handle)
282{
283 int r;
284 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
285
286 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false0);
287 if (r)
288 return r;
289
290 r = amdgpu_irq_init(adev);
291
292 return r;
293}
294
295static int iceland_ih_sw_fini(void *handle)
296{
297 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
298
299 amdgpu_irq_fini(adev);
300 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
301 amdgpu_irq_remove_domain(adev);
302
303 return 0;
304}
305
306static int iceland_ih_hw_init(void *handle)
307{
308 int r;
309 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
310
311 r = iceland_ih_irq_init(adev);
312 if (r)
313 return r;
314
315 return 0;
316}
317
318static int iceland_ih_hw_fini(void *handle)
319{
320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
321
322 iceland_ih_irq_disable(adev);
323
324 return 0;
325}
326
327static int iceland_ih_suspend(void *handle)
328{
329 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
330
331 return iceland_ih_hw_fini(adev);
332}
333
334static int iceland_ih_resume(void *handle)
335{
336 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
337
338 return iceland_ih_hw_init(adev);
339}
340
341static bool_Bool iceland_ih_is_idle(void *handle)
342{
343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
344 u32 tmp = RREG32(mmSRBM_STATUS)amdgpu_device_rreg(adev, (0x394), 0);
345
346 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)(((tmp) & 0x20000) >> 0x11))
347 return false0;
348
349 return true1;
350}
351
352static int iceland_ih_wait_for_idle(void *handle)
353{
354 unsigned i;
355 u32 tmp;
356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
357
358 for (i = 0; i < adev->usec_timeout; i++) {
359 /* read MC_STATUS */
360 tmp = RREG32(mmSRBM_STATUS)amdgpu_device_rreg(adev, (0x394), 0);
361 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)(((tmp) & 0x20000) >> 0x11))
362 return 0;
363 udelay(1);
364 }
365 return -ETIMEDOUT60;
366}
367
368static int iceland_ih_soft_reset(void *handle)
369{
370 u32 srbm_soft_reset = 0;
371 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
372 u32 tmp = RREG32(mmSRBM_STATUS)amdgpu_device_rreg(adev, (0x394), 0);
373
374 if (tmp & SRBM_STATUS__IH_BUSY_MASK0x20000)
375 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,(((srbm_soft_reset) & ~0x400) | (0x400 & ((1) <<
0xa)))
376 SOFT_RESET_IH, 1)(((srbm_soft_reset) & ~0x400) | (0x400 & ((1) <<
0xa)))
;
377
378 if (srbm_soft_reset) {
379 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
380 tmp |= srbm_soft_reset;
381 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
382 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
383 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
384
385 udelay(50);
386
387 tmp &= ~srbm_soft_reset;
388 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
389 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
Value stored to 'tmp' is never read
390
391 /* Wait a little for things to settle down */
392 udelay(50);
393 }
394
395 return 0;
396}
397
398static int iceland_ih_set_clockgating_state(void *handle,
399 enum amd_clockgating_state state)
400{
401 return 0;
402}
403
404static int iceland_ih_set_powergating_state(void *handle,
405 enum amd_powergating_state state)
406{
407 return 0;
408}
409
410static const struct amd_ip_funcs iceland_ih_ip_funcs = {
411 .name = "iceland_ih",
412 .early_init = iceland_ih_early_init,
413 .late_init = NULL((void *)0),
414 .sw_init = iceland_ih_sw_init,
415 .sw_fini = iceland_ih_sw_fini,
416 .hw_init = iceland_ih_hw_init,
417 .hw_fini = iceland_ih_hw_fini,
418 .suspend = iceland_ih_suspend,
419 .resume = iceland_ih_resume,
420 .is_idle = iceland_ih_is_idle,
421 .wait_for_idle = iceland_ih_wait_for_idle,
422 .soft_reset = iceland_ih_soft_reset,
423 .set_clockgating_state = iceland_ih_set_clockgating_state,
424 .set_powergating_state = iceland_ih_set_powergating_state,
425};
426
427static const struct amdgpu_ih_funcs iceland_ih_funcs = {
428 .get_wptr = iceland_ih_get_wptr,
429 .decode_iv = iceland_ih_decode_iv,
430 .set_rptr = iceland_ih_set_rptr
431};
432
433static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev)
434{
435 adev->irq.ih_funcs = &iceland_ih_funcs;
436}
437
438const struct amdgpu_ip_block_version iceland_ih_ip_block =
439{
440 .type = AMD_IP_BLOCK_TYPE_IH,
441 .major = 2,
442 .minor = 4,
443 .rev = 0,
444 .funcs = &iceland_ih_ip_funcs,
445};