File: | dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c |
Warning: | line 890, column 5 Value stored to 'bp_result' is never read |
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1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include <linux/delay.h> |
27 | |
28 | #include "dm_services.h" |
29 | #include "dc.h" |
30 | #include "dc_bios_types.h" |
31 | #include "core_types.h" |
32 | #include "core_status.h" |
33 | #include "resource.h" |
34 | #include "dm_helpers.h" |
35 | #include "dce110_hw_sequencer.h" |
36 | #include "dce110_timing_generator.h" |
37 | #include "dce/dce_hwseq.h" |
38 | #include "gpio_service_interface.h" |
39 | |
40 | #include "dce110_compressor.h" |
41 | |
42 | #include "bios/bios_parser_helper.h" |
43 | #include "timing_generator.h" |
44 | #include "mem_input.h" |
45 | #include "opp.h" |
46 | #include "ipp.h" |
47 | #include "transform.h" |
48 | #include "stream_encoder.h" |
49 | #include "link_encoder.h" |
50 | #include "link_hwss.h" |
51 | #include "clock_source.h" |
52 | #include "clk_mgr.h" |
53 | #include "abm.h" |
54 | #include <hw/audio.h> |
55 | #include "reg_helper.h" |
56 | #include "panel_cntl.h" |
57 | |
58 | /* include DCE11 register header files */ |
59 | #include "dce/dce_11_0_d.h" |
60 | #include "dce/dce_11_0_sh_mask.h" |
61 | #include "custom_float.h" |
62 | |
63 | #include "atomfirmware.h" |
64 | |
65 | #define GAMMA_HW_POINTS_NUM256 256 |
66 | |
67 | /* |
68 | * All values are in milliseconds; |
69 | * For eDP, after power-up/power/down, |
70 | * 300/500 msec max. delay from LCDVCC to black video generation |
71 | */ |
72 | #define PANEL_POWER_UP_TIMEOUT300 300 |
73 | #define PANEL_POWER_DOWN_TIMEOUT500 500 |
74 | #define HPD_CHECK_INTERVAL10 10 |
75 | #define OLED_POST_T7_DELAY100 100 |
76 | #define OLED_PRE_T11_DELAY150 150 |
77 | |
78 | #define CTXhws->ctx \ |
79 | hws->ctx |
80 | |
81 | #define DC_LOGGER_INIT() |
82 | |
83 | #define REG(reg)hws->regs->reg\ |
84 | hws->regs->reg |
85 | |
86 | #undef FN |
87 | #define FN(reg_name, field_name)hws->shifts->field_name, hws->masks->field_name \ |
88 | hws->shifts->field_name, hws->masks->field_name |
89 | |
90 | struct dce110_hw_seq_reg_offsets { |
91 | uint32_t crtc; |
92 | }; |
93 | |
94 | static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { |
95 | { |
96 | .crtc = (mmCRTC0_CRTC_GSL_CONTROL0x1b7b - mmCRTC_GSL_CONTROL0x1b7b), |
97 | }, |
98 | { |
99 | .crtc = (mmCRTC1_CRTC_GSL_CONTROL0x1d7b - mmCRTC_GSL_CONTROL0x1b7b), |
100 | }, |
101 | { |
102 | .crtc = (mmCRTC2_CRTC_GSL_CONTROL0x1f7b - mmCRTC_GSL_CONTROL0x1b7b), |
103 | }, |
104 | { |
105 | .crtc = (mmCRTCV_GSL_CONTROL0x477b - mmCRTC_GSL_CONTROL0x1b7b), |
106 | } |
107 | }; |
108 | |
109 | #define HW_REG_BLND(reg, id)(reg + reg_offsets[id].blnd)\ |
110 | (reg + reg_offsets[id].blnd) |
111 | |
112 | #define HW_REG_CRTC(reg, id)(reg + reg_offsets[id].crtc)\ |
113 | (reg + reg_offsets[id].crtc) |
114 | |
115 | #define MAX_WATERMARK0xFFFF 0xFFFF |
116 | #define SAFE_NBP_MARK0x7FFF 0x7FFF |
117 | |
118 | /******************************************************************************* |
119 | * Private definitions |
120 | ******************************************************************************/ |
121 | /***************************PIPE_CONTROL***********************************/ |
122 | static void dce110_init_pte(struct dc_context *ctx) |
123 | { |
124 | uint32_t addr; |
125 | uint32_t value = 0; |
126 | uint32_t chunk_int = 0; |
127 | uint32_t chunk_mul = 0; |
128 | |
129 | addr = mmUNP_DVMM_PTE_CONTROL0x4629; |
130 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
131 | |
132 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) |
133 | value,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) |
134 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) |
135 | DVMM_PTE_CONTROL,(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0) |
136 | DVMM_USE_SINGLE_PTE)(value) = set_reg_field_value_ex( (value), (0), 0x1, 0x0); |
137 | |
138 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ) |
139 | value,(value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ) |
140 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ) |
141 | DVMM_PTE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ) |
142 | DVMM_PTE_BUFFER_MODE0)(value) = set_reg_field_value_ex( (value), (1), 0x100000, 0x14 ); |
143 | |
144 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ) |
145 | value,(value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ) |
146 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ) |
147 | DVMM_PTE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ) |
148 | DVMM_PTE_BUFFER_MODE1)(value) = set_reg_field_value_ex( (value), (1), 0x200000, 0x15 ); |
149 | |
150 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
151 | |
152 | addr = mmDVMM_PTE_REQ0x330; |
153 | value = dm_read_reg(ctx, addr)dm_read_reg_func(ctx, addr, __func__); |
154 | |
155 | chunk_int = get_reg_field_value(get_reg_field_value_ex( (value), 0xff00, 0x8) |
156 | value,get_reg_field_value_ex( (value), 0xff00, 0x8) |
157 | DVMM_PTE_REQ,get_reg_field_value_ex( (value), 0xff00, 0x8) |
158 | HFLIP_PTEREQ_PER_CHUNK_INT)get_reg_field_value_ex( (value), 0xff00, 0x8); |
159 | |
160 | chunk_mul = get_reg_field_value(get_reg_field_value_ex( (value), 0x3f0000, 0x10) |
161 | value,get_reg_field_value_ex( (value), 0x3f0000, 0x10) |
162 | DVMM_PTE_REQ,get_reg_field_value_ex( (value), 0x3f0000, 0x10) |
163 | HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER)get_reg_field_value_ex( (value), 0x3f0000, 0x10); |
164 | |
165 | if (chunk_int != 0x4 || chunk_mul != 0x4) { |
166 | |
167 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0) |
168 | value,(value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0) |
169 | 255,(value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0) |
170 | DVMM_PTE_REQ,(value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0) |
171 | MAX_PTEREQ_TO_ISSUE)(value) = set_reg_field_value_ex( (value), (255), 0xff, 0x0); |
172 | |
173 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8) |
174 | value,(value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8) |
175 | 4,(value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8) |
176 | DVMM_PTE_REQ,(value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8) |
177 | HFLIP_PTEREQ_PER_CHUNK_INT)(value) = set_reg_field_value_ex( (value), (4), 0xff00, 0x8); |
178 | |
179 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ) |
180 | value,(value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ) |
181 | 4,(value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ) |
182 | DVMM_PTE_REQ,(value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ) |
183 | HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER)(value) = set_reg_field_value_ex( (value), (4), 0x3f0000, 0x10 ); |
184 | |
185 | dm_write_reg(ctx, addr, value)dm_write_reg_func(ctx, addr, value, __func__); |
186 | } |
187 | } |
188 | /**************************************************************************/ |
189 | |
190 | static void enable_display_pipe_clock_gating( |
191 | struct dc_context *ctx, |
192 | bool_Bool clock_gating) |
193 | { |
194 | /*TODO*/ |
195 | } |
196 | |
197 | static bool_Bool dce110_enable_display_power_gating( |
198 | struct dc *dc, |
199 | uint8_t controller_id, |
200 | struct dc_bios *dcb, |
201 | enum pipe_gating_control power_gating) |
202 | { |
203 | enum bp_result bp_result = BP_RESULT_OK; |
204 | enum bp_pipe_control_action cntl; |
205 | struct dc_context *ctx = dc->ctx; |
206 | unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; |
207 | |
208 | if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)(ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) |
209 | return true1; |
210 | |
211 | if (power_gating == PIPE_GATING_CONTROL_INIT) |
212 | cntl = ASIC_PIPE_INIT; |
213 | else if (power_gating == PIPE_GATING_CONTROL_ENABLE) |
214 | cntl = ASIC_PIPE_ENABLE; |
215 | else |
216 | cntl = ASIC_PIPE_DISABLE; |
217 | |
218 | if (controller_id == underlay_idx) |
219 | controller_id = CONTROLLER_ID_UNDERLAY0 - 1; |
220 | |
221 | if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ |
222 | |
223 | bp_result = dcb->funcs->enable_disp_power_gating( |
224 | dcb, controller_id + 1, cntl); |
225 | |
226 | /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 |
227 | * by default when command table is called |
228 | * |
229 | * Bios parser accepts controller_id = 6 as indicative of |
230 | * underlay pipe in dce110. But we do not support more |
231 | * than 3. |
232 | */ |
233 | if (controller_id < CONTROLLER_ID_MAX - 1) |
234 | dm_write_reg(ctx,dm_write_reg_func(ctx, (0x1bbe + reg_offsets[controller_id].crtc ), 0, __func__) |
235 | HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),dm_write_reg_func(ctx, (0x1bbe + reg_offsets[controller_id].crtc ), 0, __func__) |
236 | 0)dm_write_reg_func(ctx, (0x1bbe + reg_offsets[controller_id].crtc ), 0, __func__); |
237 | } |
238 | |
239 | if (power_gating != PIPE_GATING_CONTROL_ENABLE) |
240 | dce110_init_pte(ctx); |
241 | |
242 | if (bp_result == BP_RESULT_OK) |
243 | return true1; |
244 | else |
245 | return false0; |
246 | } |
247 | |
248 | static void build_prescale_params(struct ipp_prescale_params *prescale_params, |
249 | const struct dc_plane_state *plane_state) |
250 | { |
251 | prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; |
252 | |
253 | switch (plane_state->format) { |
254 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: |
255 | prescale_params->scale = 0x2082; |
256 | break; |
257 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: |
258 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: |
259 | prescale_params->scale = 0x2020; |
260 | break; |
261 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: |
262 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: |
263 | prescale_params->scale = 0x2008; |
264 | break; |
265 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: |
266 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: |
267 | prescale_params->scale = 0x2000; |
268 | break; |
269 | default: |
270 | ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c" , 270); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
271 | break; |
272 | } |
273 | } |
274 | |
275 | static bool_Bool |
276 | dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, |
277 | const struct dc_plane_state *plane_state) |
278 | { |
279 | struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; |
280 | const struct dc_transfer_func *tf = NULL((void *)0); |
281 | struct ipp_prescale_params prescale_params = { 0 }; |
282 | bool_Bool result = true1; |
283 | |
284 | if (ipp == NULL((void *)0)) |
285 | return false0; |
286 | |
287 | if (plane_state->in_transfer_func) |
288 | tf = plane_state->in_transfer_func; |
289 | |
290 | build_prescale_params(&prescale_params, plane_state); |
291 | ipp->funcs->ipp_program_prescale(ipp, &prescale_params); |
292 | |
293 | if (plane_state->gamma_correction && |
294 | !plane_state->gamma_correction->is_identity && |
295 | dce_use_lut(plane_state->format)) |
296 | ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); |
297 | |
298 | if (tf == NULL((void *)0)) { |
299 | /* Default case if no input transfer function specified */ |
300 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); |
301 | } else if (tf->type == TF_TYPE_PREDEFINED) { |
302 | switch (tf->tf) { |
303 | case TRANSFER_FUNCTION_SRGB: |
304 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); |
305 | break; |
306 | case TRANSFER_FUNCTION_BT709: |
307 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); |
308 | break; |
309 | case TRANSFER_FUNCTION_LINEAR: |
310 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); |
311 | break; |
312 | case TRANSFER_FUNCTION_PQ: |
313 | default: |
314 | result = false0; |
315 | break; |
316 | } |
317 | } else if (tf->type == TF_TYPE_BYPASS) { |
318 | ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); |
319 | } else { |
320 | /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ |
321 | result = false0; |
322 | } |
323 | |
324 | return result; |
325 | } |
326 | |
327 | static bool_Bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, |
328 | struct curve_points *arr_points, |
329 | uint32_t hw_points_num) |
330 | { |
331 | struct custom_float_format fmt; |
332 | |
333 | struct pwl_result_data *rgb = rgb_resulted; |
334 | |
335 | uint32_t i = 0; |
336 | |
337 | fmt.exponenta_bits = 6; |
338 | fmt.mantissa_bits = 12; |
339 | fmt.sign = true1; |
340 | |
341 | if (!convert_to_custom_float_format(arr_points[0].x, &fmt, |
342 | &arr_points[0].custom_float_x)) { |
343 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 343); do {} while (0); } while (0); |
344 | return false0; |
345 | } |
346 | |
347 | if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, |
348 | &arr_points[0].custom_float_offset)) { |
349 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 349); do {} while (0); } while (0); |
350 | return false0; |
351 | } |
352 | |
353 | if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, |
354 | &arr_points[0].custom_float_slope)) { |
355 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 355); do {} while (0); } while (0); |
356 | return false0; |
357 | } |
358 | |
359 | fmt.mantissa_bits = 10; |
360 | fmt.sign = false0; |
361 | |
362 | if (!convert_to_custom_float_format(arr_points[1].x, &fmt, |
363 | &arr_points[1].custom_float_x)) { |
364 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 364); do {} while (0); } while (0); |
365 | return false0; |
366 | } |
367 | |
368 | if (!convert_to_custom_float_format(arr_points[1].y, &fmt, |
369 | &arr_points[1].custom_float_y)) { |
370 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 370); do {} while (0); } while (0); |
371 | return false0; |
372 | } |
373 | |
374 | if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, |
375 | &arr_points[1].custom_float_slope)) { |
376 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 376); do {} while (0); } while (0); |
377 | return false0; |
378 | } |
379 | |
380 | fmt.mantissa_bits = 12; |
381 | fmt.sign = true1; |
382 | |
383 | while (i != hw_points_num) { |
384 | if (!convert_to_custom_float_format(rgb->red, &fmt, |
385 | &rgb->red_reg)) { |
386 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 386); do {} while (0); } while (0); |
387 | return false0; |
388 | } |
389 | |
390 | if (!convert_to_custom_float_format(rgb->green, &fmt, |
391 | &rgb->green_reg)) { |
392 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 392); do {} while (0); } while (0); |
393 | return false0; |
394 | } |
395 | |
396 | if (!convert_to_custom_float_format(rgb->blue, &fmt, |
397 | &rgb->blue_reg)) { |
398 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 398); do {} while (0); } while (0); |
399 | return false0; |
400 | } |
401 | |
402 | if (!convert_to_custom_float_format(rgb->delta_red, &fmt, |
403 | &rgb->delta_red_reg)) { |
404 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 404); do {} while (0); } while (0); |
405 | return false0; |
406 | } |
407 | |
408 | if (!convert_to_custom_float_format(rgb->delta_green, &fmt, |
409 | &rgb->delta_green_reg)) { |
410 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 410); do {} while (0); } while (0); |
411 | return false0; |
412 | } |
413 | |
414 | if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, |
415 | &rgb->delta_blue_reg)) { |
416 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 416); do {} while (0); } while (0); |
417 | return false0; |
418 | } |
419 | |
420 | ++rgb; |
421 | ++i; |
422 | } |
423 | |
424 | return true1; |
425 | } |
426 | |
427 | #define MAX_LOW_POINT25 25 |
428 | #define NUMBER_REGIONS16 16 |
429 | #define NUMBER_SW_SEGMENTS16 16 |
430 | |
431 | static bool_Bool |
432 | dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, |
433 | struct pwl_params *regamma_params) |
434 | { |
435 | struct curve_points *arr_points; |
436 | struct pwl_result_data *rgb_resulted; |
437 | struct pwl_result_data *rgb; |
438 | struct pwl_result_data *rgb_plus_1; |
439 | struct fixed31_32 y_r; |
440 | struct fixed31_32 y_g; |
441 | struct fixed31_32 y_b; |
442 | struct fixed31_32 y1_min; |
443 | struct fixed31_32 y3_max; |
444 | |
445 | int32_t region_start, region_end; |
446 | uint32_t i, j, k, seg_distr[NUMBER_REGIONS16], increment, start_index, hw_points; |
447 | |
448 | if (output_tf == NULL((void *)0) || regamma_params == NULL((void *)0) || output_tf->type == TF_TYPE_BYPASS) |
449 | return false0; |
450 | |
451 | arr_points = regamma_params->arr_points; |
452 | rgb_resulted = regamma_params->rgb_resulted; |
453 | hw_points = 0; |
454 | |
455 | memset(regamma_params, 0, sizeof(struct pwl_params))__builtin_memset((regamma_params), (0), (sizeof(struct pwl_params ))); |
456 | |
457 | if (output_tf->tf == TRANSFER_FUNCTION_PQ) { |
458 | /* 16 segments |
459 | * segments are from 2^-11 to 2^5 |
460 | */ |
461 | region_start = -11; |
462 | region_end = region_start + NUMBER_REGIONS16; |
463 | |
464 | for (i = 0; i < NUMBER_REGIONS16; i++) |
465 | seg_distr[i] = 4; |
466 | |
467 | } else { |
468 | /* 10 segments |
469 | * segment is from 2^-10 to 2^1 |
470 | * We include an extra segment for range [2^0, 2^1). This is to |
471 | * ensure that colors with normalized values of 1 don't miss the |
472 | * LUT. |
473 | */ |
474 | region_start = -10; |
475 | region_end = 1; |
476 | |
477 | seg_distr[0] = 4; |
478 | seg_distr[1] = 4; |
479 | seg_distr[2] = 4; |
480 | seg_distr[3] = 4; |
481 | seg_distr[4] = 4; |
482 | seg_distr[5] = 4; |
483 | seg_distr[6] = 4; |
484 | seg_distr[7] = 4; |
485 | seg_distr[8] = 4; |
486 | seg_distr[9] = 4; |
487 | seg_distr[10] = 0; |
488 | seg_distr[11] = -1; |
489 | seg_distr[12] = -1; |
490 | seg_distr[13] = -1; |
491 | seg_distr[14] = -1; |
492 | seg_distr[15] = -1; |
493 | } |
494 | |
495 | for (k = 0; k < 16; k++) { |
496 | if (seg_distr[k] != -1) |
497 | hw_points += (1 << seg_distr[k]); |
498 | } |
499 | |
500 | j = 0; |
501 | for (k = 0; k < (region_end - region_start); k++) { |
502 | increment = NUMBER_SW_SEGMENTS16 / (1 << seg_distr[k]); |
503 | start_index = (region_start + k + MAX_LOW_POINT25) * |
504 | NUMBER_SW_SEGMENTS16; |
505 | for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS16; |
506 | i += increment) { |
507 | if (j == hw_points - 1) |
508 | break; |
509 | rgb_resulted[j].red = output_tf->tf_pts.red[i]; |
510 | rgb_resulted[j].green = output_tf->tf_pts.green[i]; |
511 | rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; |
512 | j++; |
513 | } |
514 | } |
515 | |
516 | /* last point */ |
517 | start_index = (region_end + MAX_LOW_POINT25) * NUMBER_SW_SEGMENTS16; |
518 | rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; |
519 | rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; |
520 | rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; |
521 | |
522 | arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), |
523 | dc_fixpt_from_int(region_start)); |
524 | arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), |
525 | dc_fixpt_from_int(region_end)); |
526 | |
527 | y_r = rgb_resulted[0].red; |
528 | y_g = rgb_resulted[0].green; |
529 | y_b = rgb_resulted[0].blue; |
530 | |
531 | y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); |
532 | |
533 | arr_points[0].y = y1_min; |
534 | arr_points[0].slope = dc_fixpt_div(arr_points[0].y, |
535 | arr_points[0].x); |
536 | |
537 | y_r = rgb_resulted[hw_points - 1].red; |
538 | y_g = rgb_resulted[hw_points - 1].green; |
539 | y_b = rgb_resulted[hw_points - 1].blue; |
540 | |
541 | /* see comment above, m_arrPoints[1].y should be the Y value for the |
542 | * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) |
543 | */ |
544 | y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); |
545 | |
546 | arr_points[1].y = y3_max; |
547 | |
548 | arr_points[1].slope = dc_fixpt_zero; |
549 | |
550 | if (output_tf->tf == TRANSFER_FUNCTION_PQ) { |
551 | /* for PQ, we want to have a straight line from last HW X point, |
552 | * and the slope to be such that we hit 1.0 at 10000 nits. |
553 | */ |
554 | const struct fixed31_32 end_value = dc_fixpt_from_int(125); |
555 | |
556 | arr_points[1].slope = dc_fixpt_div( |
557 | dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), |
558 | dc_fixpt_sub(end_value, arr_points[1].x)); |
559 | } |
560 | |
561 | regamma_params->hw_points_num = hw_points; |
562 | |
563 | k = 0; |
564 | for (i = 1; i < 16; i++) { |
565 | if (seg_distr[k] != -1) { |
566 | regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; |
567 | regamma_params->arr_curve_points[i].offset = |
568 | regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); |
569 | } |
570 | k++; |
571 | } |
572 | |
573 | if (seg_distr[k] != -1) |
574 | regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; |
575 | |
576 | rgb = rgb_resulted; |
577 | rgb_plus_1 = rgb_resulted + 1; |
578 | |
579 | i = 1; |
580 | |
581 | while (i != hw_points + 1) { |
582 | if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) |
583 | rgb_plus_1->red = rgb->red; |
584 | if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) |
585 | rgb_plus_1->green = rgb->green; |
586 | if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) |
587 | rgb_plus_1->blue = rgb->blue; |
588 | |
589 | rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); |
590 | rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); |
591 | rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); |
592 | |
593 | ++rgb_plus_1; |
594 | ++rgb; |
595 | ++i; |
596 | } |
597 | |
598 | convert_to_custom_float(rgb_resulted, arr_points, hw_points); |
599 | |
600 | return true1; |
601 | } |
602 | |
603 | static bool_Bool |
604 | dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, |
605 | const struct dc_stream_state *stream) |
606 | { |
607 | struct transform *xfm = pipe_ctx->plane_res.xfm; |
608 | |
609 | xfm->funcs->opp_power_on_regamma_lut(xfm, true1); |
610 | xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM256; |
611 | |
612 | if (stream->out_transfer_func && |
613 | stream->out_transfer_func->type == TF_TYPE_PREDEFINED && |
614 | stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { |
615 | xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); |
616 | } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func, |
617 | &xfm->regamma_params)) { |
618 | xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); |
619 | xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); |
620 | } else { |
621 | xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); |
622 | } |
623 | |
624 | xfm->funcs->opp_power_on_regamma_lut(xfm, false0); |
625 | |
626 | return true1; |
627 | } |
628 | |
629 | void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) |
630 | { |
631 | bool_Bool is_hdmi_tmds; |
632 | bool_Bool is_dp; |
633 | |
634 | ASSERT(pipe_ctx->stream)do { if (({ static int __warned; int __ret = !!(!(pipe_ctx-> stream)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(pipe_ctx->stream)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c" , 634); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
635 | |
636 | if (pipe_ctx->stream_res.stream_enc == NULL((void *)0)) |
637 | return; /* this is not root pipe */ |
638 | |
639 | is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); |
640 | is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); |
641 | |
642 | if (!is_hdmi_tmds && !is_dp) |
643 | return; |
644 | |
645 | if (is_hdmi_tmds) |
646 | pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( |
647 | pipe_ctx->stream_res.stream_enc, |
648 | &pipe_ctx->stream_res.encoder_info_frame); |
649 | else |
650 | pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( |
651 | pipe_ctx->stream_res.stream_enc, |
652 | &pipe_ctx->stream_res.encoder_info_frame); |
653 | } |
654 | |
655 | void dce110_enable_stream(struct pipe_ctx *pipe_ctx) |
656 | { |
657 | enum dc_lane_count lane_count = |
658 | pipe_ctx->stream->link->cur_link_settings.lane_count; |
659 | struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; |
660 | struct dc_link *link = pipe_ctx->stream->link; |
661 | const struct dc *dc = link->dc; |
662 | |
663 | uint32_t active_total_with_borders; |
664 | uint32_t early_control = 0; |
665 | struct timing_generator *tg = pipe_ctx->stream_res.tg; |
666 | |
667 | /* For MST, there are multiply stream go to only one link. |
668 | * connect DIG back_end to front_end while enable_stream and |
669 | * disconnect them during disable_stream |
670 | * BY this, it is logic clean to separate stream and link */ |
671 | link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, |
672 | pipe_ctx->stream_res.stream_enc->id, true1); |
673 | |
674 | dc->hwss.update_info_frame(pipe_ctx); |
675 | |
676 | /* enable early control to avoid corruption on DP monitor*/ |
677 | active_total_with_borders = |
678 | timing->h_addressable |
679 | + timing->h_border_left |
680 | + timing->h_border_right; |
681 | |
682 | if (lane_count != 0) |
683 | early_control = active_total_with_borders % lane_count; |
684 | |
685 | if (early_control == 0) |
686 | early_control = lane_count; |
687 | |
688 | tg->funcs->set_early_control(tg, early_control); |
689 | |
690 | /* enable audio only within mode set */ |
691 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { |
692 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) |
693 | pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc); |
694 | } |
695 | |
696 | |
697 | |
698 | |
699 | } |
700 | |
701 | static enum bp_result link_transmitter_control( |
702 | struct dc_bios *bios, |
703 | struct bp_transmitter_control *cntl) |
704 | { |
705 | enum bp_result result; |
706 | |
707 | result = bios->funcs->transmitter_control(bios, cntl); |
708 | |
709 | return result; |
710 | } |
711 | |
712 | /* |
713 | * @brief |
714 | * eDP only. |
715 | */ |
716 | void dce110_edp_wait_for_hpd_ready( |
717 | struct dc_link *link, |
718 | bool_Bool power_up) |
719 | { |
720 | struct dc_context *ctx = link->ctx; |
721 | struct graphics_object_id connector = link->link_enc->connector; |
722 | struct gpio *hpd; |
723 | struct dc_sink *sink = link->local_sink; |
724 | bool_Bool edp_hpd_high = false0; |
725 | uint32_t time_elapsed = 0; |
726 | uint32_t timeout = power_up ? |
727 | PANEL_POWER_UP_TIMEOUT300 : PANEL_POWER_DOWN_TIMEOUT500; |
728 | |
729 | if (dal_graphics_object_id_get_connector_id(connector) |
730 | != CONNECTOR_ID_EDP) { |
731 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 731); do {} while (0); } while (0); |
732 | return; |
733 | } |
734 | |
735 | if (!power_up) |
736 | /* |
737 | * From KV, we will not HPD low after turning off VCC - |
738 | * instead, we will check the SW timer in power_up(). |
739 | */ |
740 | return; |
741 | |
742 | /* |
743 | * When we power on/off the eDP panel, |
744 | * we need to wait until SENSE bit is high/low. |
745 | */ |
746 | |
747 | /* obtain HPD */ |
748 | /* TODO what to do with this? */ |
749 | hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); |
750 | |
751 | if (!hpd) { |
752 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 752); do {} while (0); } while (0); |
753 | return; |
754 | } |
755 | |
756 | if (sink != NULL((void *)0)) { |
757 | if (sink->edid_caps.panel_patch.extra_t3_ms > 0) { |
758 | int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms; |
759 | |
760 | drm_msleep(extra_t3_in_ms)mdelay(extra_t3_in_ms); |
761 | } |
762 | } |
763 | |
764 | dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); |
765 | |
766 | /* wait until timeout or panel detected */ |
767 | |
768 | do { |
769 | uint32_t detected = 0; |
770 | |
771 | dal_gpio_get_value(hpd, &detected); |
772 | |
773 | if (!(detected ^ power_up)) { |
774 | edp_hpd_high = true1; |
775 | break; |
776 | } |
777 | |
778 | drm_msleep(HPD_CHECK_INTERVAL)mdelay(10); |
779 | |
780 | time_elapsed += HPD_CHECK_INTERVAL10; |
781 | } while (time_elapsed < timeout); |
782 | |
783 | dal_gpio_close(hpd); |
784 | |
785 | dal_gpio_destroy_irq(&hpd); |
786 | |
787 | if (false0 == edp_hpd_high) { |
788 | DC_LOG_ERROR(__drm_err("%s: wait timed out!\n", __func__) |
789 | "%s: wait timed out!\n", __func__)__drm_err("%s: wait timed out!\n", __func__); |
790 | } |
791 | } |
792 | |
793 | void dce110_edp_power_control( |
794 | struct dc_link *link, |
795 | bool_Bool power_up) |
796 | { |
797 | struct dc_context *ctx = link->ctx; |
798 | struct bp_transmitter_control cntl = { 0 }; |
799 | enum bp_result bp_result; |
800 | |
801 | |
802 | if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) |
803 | != CONNECTOR_ID_EDP) { |
804 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 804); do {} while (0); } while (0); |
805 | return; |
806 | } |
807 | |
808 | if (!link->panel_cntl) |
809 | return; |
810 | |
811 | if (power_up != |
812 | link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { |
813 | |
814 | unsigned long long current_ts = dm_get_timestamp(ctx); |
815 | unsigned long long time_since_edp_poweroff_ms = |
816 | div64_u64(dm_get_elapse_time_in_ns( |
817 | ctx, |
818 | current_ts, |
819 | link->link_trace.time_stamp.edp_poweroff), 1000000); |
820 | unsigned long long time_since_edp_poweron_ms = |
821 | div64_u64(dm_get_elapse_time_in_ns( |
822 | ctx, |
823 | current_ts, |
824 | link->link_trace.time_stamp.edp_poweron), 1000000); |
825 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms) |
826 | "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms) |
827 | __func__,__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms) |
828 | power_up,__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms) |
829 | current_ts,__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms) |
830 | link->link_trace.time_stamp.edp_poweroff,__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms) |
831 | link->link_trace.time_stamp.edp_poweron,__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms) |
832 | time_since_edp_poweroff_ms,__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms) |
833 | time_since_edp_poweron_ms)__drm_dbg(DRM_UT_KMS, "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu" , __func__, power_up, current_ts, link->link_trace.time_stamp .edp_poweroff, link->link_trace.time_stamp.edp_poweron, time_since_edp_poweroff_ms , time_since_edp_poweron_ms); |
834 | |
835 | /* Send VBIOS command to prompt eDP panel power */ |
836 | if (power_up) { |
837 | /* edp requires a min of 500ms from LCDVDD off to on */ |
838 | unsigned long long remaining_min_edp_poweroff_time_ms = 500; |
839 | |
840 | /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ |
841 | if (link->local_sink != NULL((void *)0)) |
842 | remaining_min_edp_poweroff_time_ms += |
843 | link->local_sink->edid_caps.panel_patch.extra_t12_ms; |
844 | |
845 | /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ |
846 | if (link->link_trace.time_stamp.edp_poweroff != 0) { |
847 | if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) |
848 | remaining_min_edp_poweroff_time_ms = |
849 | remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; |
850 | else |
851 | remaining_min_edp_poweroff_time_ms = 0; |
852 | } |
853 | |
854 | if (remaining_min_edp_poweroff_time_ms) { |
855 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n" , __func__, remaining_min_edp_poweroff_time_ms) |
856 | "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n" , __func__, remaining_min_edp_poweroff_time_ms) |
857 | __func__, remaining_min_edp_poweroff_time_ms)__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n" , __func__, remaining_min_edp_poweroff_time_ms); |
858 | drm_msleep(remaining_min_edp_poweroff_time_ms)mdelay(remaining_min_edp_poweroff_time_ms); |
859 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n" , __func__, remaining_min_edp_poweroff_time_ms) |
860 | "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n" , __func__, remaining_min_edp_poweroff_time_ms) |
861 | __func__, remaining_min_edp_poweroff_time_ms)__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n" , __func__, remaining_min_edp_poweroff_time_ms); |
862 | dm_output_to_console("%s: wait %lld ms to power on eDP.\n",__drm_dbg(DRM_UT_KMS, "%s: wait %lld ms to power on eDP.\n", __func__ , remaining_min_edp_poweroff_time_ms) |
863 | __func__, remaining_min_edp_poweroff_time_ms)__drm_dbg(DRM_UT_KMS, "%s: wait %lld ms to power on eDP.\n", __func__ , remaining_min_edp_poweroff_time_ms); |
864 | } else { |
865 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n" , __func__, remaining_min_edp_poweroff_time_ms) |
866 | "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n" , __func__, remaining_min_edp_poweroff_time_ms) |
867 | __func__, remaining_min_edp_poweroff_time_ms)__drm_dbg(DRM_UT_KMS, "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n" , __func__, remaining_min_edp_poweroff_time_ms); |
868 | } |
869 | } |
870 | |
871 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: BEGIN: Panel Power action: %s\n", __func__ , (power_up ? "On":"Off")) |
872 | "%s: BEGIN: Panel Power action: %s\n",__drm_dbg(DRM_UT_KMS, "%s: BEGIN: Panel Power action: %s\n", __func__ , (power_up ? "On":"Off")) |
873 | __func__, (power_up ? "On":"Off"))__drm_dbg(DRM_UT_KMS, "%s: BEGIN: Panel Power action: %s\n", __func__ , (power_up ? "On":"Off")); |
874 | |
875 | cntl.action = power_up ? |
876 | TRANSMITTER_CONTROL_POWER_ON : |
877 | TRANSMITTER_CONTROL_POWER_OFF; |
878 | cntl.transmitter = link->link_enc->transmitter; |
879 | cntl.connector_obj_id = link->link_enc->connector; |
880 | cntl.coherent = false0; |
881 | cntl.lanes_number = LANE_COUNT_FOUR; |
882 | cntl.hpd_sel = link->link_enc->hpd_source; |
883 | |
884 | if (ctx->dc->ctx->dmub_srv && |
885 | ctx->dc->debug.dmub_command_table) { |
886 | if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) |
887 | bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, |
888 | LVTMA_CONTROL_POWER_ON); |
889 | else |
890 | bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, |
Value stored to 'bp_result' is never read | |
891 | LVTMA_CONTROL_POWER_OFF); |
892 | } |
893 | |
894 | bp_result = link_transmitter_control(ctx->dc_bios, &cntl); |
895 | |
896 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: END: Panel Power action: %s bp_result=%u\n" , __func__, (power_up ? "On":"Off"), bp_result) |
897 | "%s: END: Panel Power action: %s bp_result=%u\n",__drm_dbg(DRM_UT_KMS, "%s: END: Panel Power action: %s bp_result=%u\n" , __func__, (power_up ? "On":"Off"), bp_result) |
898 | __func__, (power_up ? "On":"Off"),__drm_dbg(DRM_UT_KMS, "%s: END: Panel Power action: %s bp_result=%u\n" , __func__, (power_up ? "On":"Off"), bp_result) |
899 | bp_result)__drm_dbg(DRM_UT_KMS, "%s: END: Panel Power action: %s bp_result=%u\n" , __func__, (power_up ? "On":"Off"), bp_result); |
900 | |
901 | if (!power_up) |
902 | /*save driver power off time stamp*/ |
903 | link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx); |
904 | else |
905 | link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx); |
906 | |
907 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, link->link_trace.time_stamp.edp_poweroff, link ->link_trace.time_stamp.edp_poweron) |
908 | "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",__drm_dbg(DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, link->link_trace.time_stamp.edp_poweroff, link ->link_trace.time_stamp.edp_poweron) |
909 | __func__,__drm_dbg(DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, link->link_trace.time_stamp.edp_poweroff, link ->link_trace.time_stamp.edp_poweron) |
910 | link->link_trace.time_stamp.edp_poweroff,__drm_dbg(DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, link->link_trace.time_stamp.edp_poweroff, link ->link_trace.time_stamp.edp_poweron) |
911 | link->link_trace.time_stamp.edp_poweron)__drm_dbg(DRM_UT_KMS, "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n" , __func__, link->link_trace.time_stamp.edp_poweroff, link ->link_trace.time_stamp.edp_poweron); |
912 | |
913 | if (bp_result != BP_RESULT_OK) |
914 | DC_LOG_ERROR(__drm_err("%s: Panel Power bp_result: %d\n", __func__, bp_result ) |
915 | "%s: Panel Power bp_result: %d\n",__drm_err("%s: Panel Power bp_result: %d\n", __func__, bp_result ) |
916 | __func__, bp_result)__drm_err("%s: Panel Power bp_result: %d\n", __func__, bp_result ); |
917 | } else { |
918 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: Skipping Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")) |
919 | "%s: Skipping Panel Power action: %s\n",__drm_dbg(DRM_UT_KMS, "%s: Skipping Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")) |
920 | __func__, (power_up ? "On":"Off"))__drm_dbg(DRM_UT_KMS, "%s: Skipping Panel Power action: %s\n" , __func__, (power_up ? "On":"Off")); |
921 | } |
922 | } |
923 | |
924 | /*todo: cloned in stream enc, fix*/ |
925 | /* |
926 | * @brief |
927 | * eDP only. Control the backlight of the eDP panel |
928 | */ |
929 | void dce110_edp_backlight_control( |
930 | struct dc_link *link, |
931 | bool_Bool enable) |
932 | { |
933 | struct dc_context *ctx = link->ctx; |
934 | struct bp_transmitter_control cntl = { 0 }; |
935 | |
936 | if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) |
937 | != CONNECTOR_ID_EDP) { |
938 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 938); do {} while (0); } while (0); |
939 | return; |
940 | } |
941 | |
942 | if (enable && link->panel_cntl && |
943 | link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl)) { |
944 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: panel already powered up. Do nothing.\n" , __func__) |
945 | "%s: panel already powered up. Do nothing.\n",__drm_dbg(DRM_UT_KMS, "%s: panel already powered up. Do nothing.\n" , __func__) |
946 | __func__)__drm_dbg(DRM_UT_KMS, "%s: panel already powered up. Do nothing.\n" , __func__); |
947 | return; |
948 | } |
949 | |
950 | /* Send VBIOS command to control eDP panel backlight */ |
951 | |
952 | DC_LOG_HW_RESUME_S3(__drm_dbg(DRM_UT_KMS, "%s: backlight action: %s\n", __func__, (enable ? "On":"Off")) |
953 | "%s: backlight action: %s\n",__drm_dbg(DRM_UT_KMS, "%s: backlight action: %s\n", __func__, (enable ? "On":"Off")) |
954 | __func__, (enable ? "On":"Off"))__drm_dbg(DRM_UT_KMS, "%s: backlight action: %s\n", __func__, (enable ? "On":"Off")); |
955 | |
956 | cntl.action = enable ? |
957 | TRANSMITTER_CONTROL_BACKLIGHT_ON : |
958 | TRANSMITTER_CONTROL_BACKLIGHT_OFF; |
959 | |
960 | /*cntl.engine_id = ctx->engine;*/ |
961 | cntl.transmitter = link->link_enc->transmitter; |
962 | cntl.connector_obj_id = link->link_enc->connector; |
963 | /*todo: unhardcode*/ |
964 | cntl.lanes_number = LANE_COUNT_FOUR; |
965 | cntl.hpd_sel = link->link_enc->hpd_source; |
966 | cntl.signal = SIGNAL_TYPE_EDP; |
967 | |
968 | /* For eDP, the following delays might need to be considered |
969 | * after link training completed: |
970 | * idle period - min. accounts for required BS-Idle pattern, |
971 | * max. allows for source frame synchronization); |
972 | * 50 msec max. delay from valid video data from source |
973 | * to video on dislpay or backlight enable. |
974 | * |
975 | * Disable the delay for now. |
976 | * Enable it in the future if necessary. |
977 | */ |
978 | /* dc_service_sleep_in_milliseconds(50); */ |
979 | /*edp 1.2*/ |
980 | if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) |
981 | edp_receiver_ready_T7(link); |
982 | |
983 | if (ctx->dc->ctx->dmub_srv && |
984 | ctx->dc->debug.dmub_command_table) { |
985 | if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) |
986 | ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, |
987 | LVTMA_CONTROL_LCD_BLON); |
988 | else |
989 | ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, |
990 | LVTMA_CONTROL_LCD_BLOFF); |
991 | } |
992 | |
993 | link_transmitter_control(ctx->dc_bios, &cntl); |
994 | |
995 | |
996 | |
997 | if (enable && link->dpcd_sink_ext_caps.bits.oled) |
998 | drm_msleep(OLED_POST_T7_DELAY)mdelay(100); |
999 | |
1000 | if (link->dpcd_sink_ext_caps.bits.oled || |
1001 | link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || |
1002 | link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) |
1003 | dc_link_backlight_enable_aux(link, enable); |
1004 | |
1005 | /*edp 1.2*/ |
1006 | if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) |
1007 | edp_receiver_ready_T9(link); |
1008 | |
1009 | if (!enable && link->dpcd_sink_ext_caps.bits.oled) |
1010 | drm_msleep(OLED_PRE_T11_DELAY)mdelay(150); |
1011 | } |
1012 | |
1013 | void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) |
1014 | { |
1015 | /* notify audio driver for audio modes of monitor */ |
1016 | struct dc *dc; |
1017 | struct clk_mgr *clk_mgr; |
1018 | unsigned int i, num_audio = 1; |
1019 | |
1020 | if (!pipe_ctx->stream) |
1021 | return; |
1022 | |
1023 | dc = pipe_ctx->stream->ctx->dc; |
1024 | clk_mgr = dc->clk_mgr; |
1025 | |
1026 | if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true1) |
1027 | return; |
1028 | |
1029 | if (pipe_ctx->stream_res.audio) { |
1030 | for (i = 0; i < MAX_PIPES6; i++) { |
1031 | /*current_state not updated yet*/ |
1032 | if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL((void *)0)) |
1033 | num_audio++; |
1034 | } |
1035 | |
1036 | pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); |
1037 | |
1038 | if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) |
1039 | /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ |
1040 | clk_mgr->funcs->enable_pme_wa(clk_mgr); |
1041 | /* un-mute audio */ |
1042 | /* TODO: audio should be per stream rather than per link */ |
1043 | pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( |
1044 | pipe_ctx->stream_res.stream_enc, false0); |
1045 | if (pipe_ctx->stream_res.audio) |
1046 | pipe_ctx->stream_res.audio->enabled = true1; |
1047 | } |
1048 | } |
1049 | |
1050 | void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) |
1051 | { |
1052 | struct dc *dc; |
1053 | struct clk_mgr *clk_mgr; |
1054 | |
1055 | if (!pipe_ctx || !pipe_ctx->stream) |
1056 | return; |
1057 | |
1058 | dc = pipe_ctx->stream->ctx->dc; |
1059 | clk_mgr = dc->clk_mgr; |
1060 | |
1061 | if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false0) |
1062 | return; |
1063 | |
1064 | pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( |
1065 | pipe_ctx->stream_res.stream_enc, true1); |
1066 | if (pipe_ctx->stream_res.audio) { |
1067 | pipe_ctx->stream_res.audio->enabled = false0; |
1068 | |
1069 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) |
1070 | pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable( |
1071 | pipe_ctx->stream_res.stream_enc); |
1072 | else |
1073 | pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable( |
1074 | pipe_ctx->stream_res.stream_enc); |
1075 | |
1076 | if (clk_mgr->funcs->enable_pme_wa) |
1077 | /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ |
1078 | clk_mgr->funcs->enable_pme_wa(clk_mgr); |
1079 | |
1080 | /* TODO: notify audio driver for if audio modes list changed |
1081 | * add audio mode list change flag */ |
1082 | /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, |
1083 | * stream->stream_engine_id); |
1084 | */ |
1085 | } |
1086 | } |
1087 | |
1088 | void dce110_disable_stream(struct pipe_ctx *pipe_ctx) |
1089 | { |
1090 | struct dc_stream_state *stream = pipe_ctx->stream; |
1091 | struct dc_link *link = stream->link; |
1092 | struct dc *dc = pipe_ctx->stream->ctx->dc; |
1093 | |
1094 | if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { |
1095 | pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( |
1096 | pipe_ctx->stream_res.stream_enc); |
1097 | pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( |
1098 | pipe_ctx->stream_res.stream_enc); |
1099 | } |
1100 | |
1101 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) |
1102 | pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( |
1103 | pipe_ctx->stream_res.stream_enc); |
1104 | |
1105 | dc->hwss.disable_audio_stream(pipe_ctx); |
1106 | |
1107 | link->link_enc->funcs->connect_dig_be_to_fe( |
1108 | link->link_enc, |
1109 | pipe_ctx->stream_res.stream_enc->id, |
1110 | false0); |
1111 | |
1112 | } |
1113 | |
1114 | void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, |
1115 | struct dc_link_settings *link_settings) |
1116 | { |
1117 | struct encoder_unblank_param params = { { 0 } }; |
1118 | struct dc_stream_state *stream = pipe_ctx->stream; |
1119 | struct dc_link *link = stream->link; |
1120 | struct dce_hwseq *hws = link->dc->hwseq; |
1121 | |
1122 | /* only 3 items below are used by unblank */ |
1123 | params.timing = pipe_ctx->stream->timing; |
1124 | params.link_settings.link_rate = link_settings->link_rate; |
1125 | |
1126 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) |
1127 | pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, ¶ms); |
1128 | |
1129 | if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { |
1130 | hws->funcs.edp_backlight_control(link, true1); |
1131 | } |
1132 | } |
1133 | |
1134 | void dce110_blank_stream(struct pipe_ctx *pipe_ctx) |
1135 | { |
1136 | struct dc_stream_state *stream = pipe_ctx->stream; |
1137 | struct dc_link *link = stream->link; |
1138 | struct dce_hwseq *hws = link->dc->hwseq; |
1139 | |
1140 | if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { |
1141 | hws->funcs.edp_backlight_control(link, false0); |
1142 | link->dc->hwss.set_abm_immediate_disable(pipe_ctx); |
1143 | } |
1144 | |
1145 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) { |
1146 | pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); |
1147 | |
1148 | /* |
1149 | * After output is idle pattern some sinks need time to recognize the stream |
1150 | * has changed or they enter protection state and hang. |
1151 | */ |
1152 | if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) |
1153 | drm_msleep(60)mdelay(60); |
1154 | } |
1155 | |
1156 | } |
1157 | |
1158 | |
1159 | void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool_Bool enable) |
1160 | { |
1161 | if (pipe_ctx != NULL((void *)0) && pipe_ctx->stream_res.stream_enc != NULL((void *)0)) |
1162 | pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); |
1163 | } |
1164 | |
1165 | static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) |
1166 | { |
1167 | switch (crtc_id) { |
1168 | case CONTROLLER_ID_D0: |
1169 | return DTO_SOURCE_ID0; |
1170 | case CONTROLLER_ID_D1: |
1171 | return DTO_SOURCE_ID1; |
1172 | case CONTROLLER_ID_D2: |
1173 | return DTO_SOURCE_ID2; |
1174 | case CONTROLLER_ID_D3: |
1175 | return DTO_SOURCE_ID3; |
1176 | case CONTROLLER_ID_D4: |
1177 | return DTO_SOURCE_ID4; |
1178 | case CONTROLLER_ID_D5: |
1179 | return DTO_SOURCE_ID5; |
1180 | default: |
1181 | return DTO_SOURCE_UNKNOWN; |
1182 | } |
1183 | } |
1184 | |
1185 | static void build_audio_output( |
1186 | struct dc_state *state, |
1187 | const struct pipe_ctx *pipe_ctx, |
1188 | struct audio_output *audio_output) |
1189 | { |
1190 | const struct dc_stream_state *stream = pipe_ctx->stream; |
1191 | audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; |
1192 | |
1193 | audio_output->signal = pipe_ctx->stream->signal; |
1194 | |
1195 | /* audio_crtc_info */ |
1196 | |
1197 | audio_output->crtc_info.h_total = |
1198 | stream->timing.h_total; |
1199 | |
1200 | /* |
1201 | * Audio packets are sent during actual CRTC blank physical signal, we |
1202 | * need to specify actual active signal portion |
1203 | */ |
1204 | audio_output->crtc_info.h_active = |
1205 | stream->timing.h_addressable |
1206 | + stream->timing.h_border_left |
1207 | + stream->timing.h_border_right; |
1208 | |
1209 | audio_output->crtc_info.v_active = |
1210 | stream->timing.v_addressable |
1211 | + stream->timing.v_border_top |
1212 | + stream->timing.v_border_bottom; |
1213 | |
1214 | audio_output->crtc_info.pixel_repetition = 1; |
1215 | |
1216 | audio_output->crtc_info.interlaced = |
1217 | stream->timing.flags.INTERLACE; |
1218 | |
1219 | audio_output->crtc_info.refresh_rate = |
1220 | (stream->timing.pix_clk_100hz*100)/ |
1221 | (stream->timing.h_total*stream->timing.v_total); |
1222 | |
1223 | audio_output->crtc_info.color_depth = |
1224 | stream->timing.display_color_depth; |
1225 | |
1226 | audio_output->crtc_info.requested_pixel_clock_100Hz = |
1227 | pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; |
1228 | |
1229 | audio_output->crtc_info.calculated_pixel_clock_100Hz = |
1230 | pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; |
1231 | |
1232 | /*for HDMI, audio ACR is with deep color ratio factor*/ |
1233 | if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && |
1234 | audio_output->crtc_info.requested_pixel_clock_100Hz == |
1235 | (stream->timing.pix_clk_100hz)) { |
1236 | if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { |
1237 | audio_output->crtc_info.requested_pixel_clock_100Hz = |
1238 | audio_output->crtc_info.requested_pixel_clock_100Hz/2; |
1239 | audio_output->crtc_info.calculated_pixel_clock_100Hz = |
1240 | pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; |
1241 | |
1242 | } |
1243 | } |
1244 | |
1245 | if (state->clk_mgr && |
1246 | (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || |
1247 | pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { |
1248 | audio_output->pll_info.dp_dto_source_clock_in_khz = |
1249 | state->clk_mgr->funcs->get_dp_ref_clk_frequency( |
1250 | state->clk_mgr); |
1251 | } |
1252 | |
1253 | audio_output->pll_info.feed_back_divider = |
1254 | pipe_ctx->pll_settings.feedback_divider; |
1255 | |
1256 | audio_output->pll_info.dto_source = |
1257 | translate_to_dto_source( |
1258 | pipe_ctx->stream_res.tg->inst + 1); |
1259 | |
1260 | /* TODO hard code to enable for now. Need get from stream */ |
1261 | audio_output->pll_info.ss_enabled = true1; |
1262 | |
1263 | audio_output->pll_info.ss_percentage = |
1264 | pipe_ctx->pll_settings.ss_percentage; |
1265 | } |
1266 | |
1267 | static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx, |
1268 | struct tg_color *color) |
1269 | { |
1270 | uint32_t color_value = MAX_TG_COLOR_VALUE0x3FF * (4 - pipe_ctx->stream_res.tg->inst) / 4; |
1271 | |
1272 | switch (pipe_ctx->plane_res.scl_data.format) { |
1273 | case PIXEL_FORMAT_ARGB8888: |
1274 | /* set boarder color to red */ |
1275 | color->color_r_cr = color_value; |
1276 | break; |
1277 | |
1278 | case PIXEL_FORMAT_ARGB2101010: |
1279 | /* set boarder color to blue */ |
1280 | color->color_b_cb = color_value; |
1281 | break; |
1282 | case PIXEL_FORMAT_420BPP8: |
1283 | /* set boarder color to green */ |
1284 | color->color_g_y = color_value; |
1285 | break; |
1286 | case PIXEL_FORMAT_420BPP10: |
1287 | /* set boarder color to yellow */ |
1288 | color->color_g_y = color_value; |
1289 | color->color_r_cr = color_value; |
1290 | break; |
1291 | case PIXEL_FORMAT_FP16: |
1292 | /* set boarder color to white */ |
1293 | color->color_r_cr = color_value; |
1294 | color->color_b_cb = color_value; |
1295 | color->color_g_y = color_value; |
1296 | break; |
1297 | default: |
1298 | break; |
1299 | } |
1300 | } |
1301 | |
1302 | static void program_scaler(const struct dc *dc, |
1303 | const struct pipe_ctx *pipe_ctx) |
1304 | { |
1305 | struct tg_color color = {0}; |
1306 | |
1307 | #if defined(CONFIG_DRM_AMD_DC_DCN1) |
1308 | /* TOFPGA */ |
1309 | if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL((void *)0)) |
1310 | return; |
1311 | #endif |
1312 | |
1313 | if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) |
1314 | get_surface_visual_confirm_color(pipe_ctx, &color); |
1315 | else |
1316 | color_space_to_black_color(dc, |
1317 | pipe_ctx->stream->output_color_space, |
1318 | &color); |
1319 | |
1320 | pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( |
1321 | pipe_ctx->plane_res.xfm, |
1322 | pipe_ctx->plane_res.scl_data.lb_params.depth, |
1323 | &pipe_ctx->stream->bit_depth_params); |
1324 | |
1325 | if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { |
1326 | /* |
1327 | * The way 420 is packed, 2 channels carry Y component, 1 channel |
1328 | * alternate between Cb and Cr, so both channels need the pixel |
1329 | * value for Y |
1330 | */ |
1331 | if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) |
1332 | color.color_r_cr = color.color_g_y; |
1333 | |
1334 | pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( |
1335 | pipe_ctx->stream_res.tg, |
1336 | &color); |
1337 | } |
1338 | |
1339 | pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, |
1340 | &pipe_ctx->plane_res.scl_data); |
1341 | } |
1342 | |
1343 | static enum dc_status dce110_enable_stream_timing( |
1344 | struct pipe_ctx *pipe_ctx, |
1345 | struct dc_state *context, |
1346 | struct dc *dc) |
1347 | { |
1348 | struct dc_stream_state *stream = pipe_ctx->stream; |
1349 | struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. |
1350 | pipe_ctx[pipe_ctx->pipe_idx]; |
1351 | struct tg_color black_color = {0}; |
1352 | |
1353 | if (!pipe_ctx_old->stream) { |
1354 | |
1355 | /* program blank color */ |
1356 | color_space_to_black_color(dc, |
1357 | stream->output_color_space, &black_color); |
1358 | pipe_ctx->stream_res.tg->funcs->set_blank_color( |
1359 | pipe_ctx->stream_res.tg, |
1360 | &black_color); |
1361 | |
1362 | /* |
1363 | * Must blank CRTC after disabling power gating and before any |
1364 | * programming, otherwise CRTC will be hung in bad state |
1365 | */ |
1366 | pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true1); |
1367 | |
1368 | if (false0 == pipe_ctx->clock_source->funcs->program_pix_clk( |
1369 | pipe_ctx->clock_source, |
1370 | &pipe_ctx->stream_res.pix_clk_params, |
1371 | &pipe_ctx->pll_settings)) { |
1372 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1372); do {} while (0); } while (0); |
1373 | return DC_ERROR_UNEXPECTED; |
1374 | } |
1375 | |
1376 | pipe_ctx->stream_res.tg->funcs->program_timing( |
1377 | pipe_ctx->stream_res.tg, |
1378 | &stream->timing, |
1379 | 0, |
1380 | 0, |
1381 | 0, |
1382 | 0, |
1383 | pipe_ctx->stream->signal, |
1384 | true1); |
1385 | } |
1386 | |
1387 | if (!pipe_ctx_old->stream) { |
1388 | if (false0 == pipe_ctx->stream_res.tg->funcs->enable_crtc( |
1389 | pipe_ctx->stream_res.tg)) { |
1390 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1390); do {} while (0); } while (0); |
1391 | return DC_ERROR_UNEXPECTED; |
1392 | } |
1393 | } |
1394 | |
1395 | return DC_OK; |
1396 | } |
1397 | |
1398 | static enum dc_status apply_single_controller_ctx_to_hw( |
1399 | struct pipe_ctx *pipe_ctx, |
1400 | struct dc_state *context, |
1401 | struct dc *dc) |
1402 | { |
1403 | struct dc_stream_state *stream = pipe_ctx->stream; |
1404 | struct drr_params params = {0}; |
1405 | unsigned int event_triggers = 0; |
1406 | struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; |
1407 | struct dce_hwseq *hws = dc->hwseq; |
1408 | |
1409 | if (hws->funcs.disable_stream_gating) { |
1410 | hws->funcs.disable_stream_gating(dc, pipe_ctx); |
1411 | } |
1412 | |
1413 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { |
1414 | struct audio_output audio_output; |
1415 | |
1416 | build_audio_output(context, pipe_ctx, &audio_output); |
1417 | |
1418 | if (dc_is_dp_signal(pipe_ctx->stream->signal)) |
1419 | pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( |
1420 | pipe_ctx->stream_res.stream_enc, |
1421 | pipe_ctx->stream_res.audio->inst, |
1422 | &pipe_ctx->stream->audio_info); |
1423 | else |
1424 | pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup( |
1425 | pipe_ctx->stream_res.stream_enc, |
1426 | pipe_ctx->stream_res.audio->inst, |
1427 | &pipe_ctx->stream->audio_info, |
1428 | &audio_output.crtc_info); |
1429 | |
1430 | pipe_ctx->stream_res.audio->funcs->az_configure( |
1431 | pipe_ctx->stream_res.audio, |
1432 | pipe_ctx->stream->signal, |
1433 | &audio_output.crtc_info, |
1434 | &pipe_ctx->stream->audio_info); |
1435 | } |
1436 | |
1437 | /* */ |
1438 | /* Do not touch stream timing on seamless boot optimization. */ |
1439 | if (!pipe_ctx->stream->apply_seamless_boot_optimization) |
1440 | hws->funcs.enable_stream_timing(pipe_ctx, context, dc); |
1441 | |
1442 | if (hws->funcs.setup_vupdate_interrupt) |
1443 | hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); |
1444 | |
1445 | params.vertical_total_min = stream->adjust.v_total_min; |
1446 | params.vertical_total_max = stream->adjust.v_total_max; |
1447 | if (pipe_ctx->stream_res.tg->funcs->set_drr) |
1448 | pipe_ctx->stream_res.tg->funcs->set_drr( |
1449 | pipe_ctx->stream_res.tg, ¶ms); |
1450 | |
1451 | // DRR should set trigger event to monitor surface update event |
1452 | if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) |
1453 | event_triggers = 0x80; |
1454 | /* Event triggers and num frames initialized for DRR, but can be |
1455 | * later updated for PSR use. Note DRR trigger events are generated |
1456 | * regardless of whether num frames met. |
1457 | */ |
1458 | if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) |
1459 | pipe_ctx->stream_res.tg->funcs->set_static_screen_control( |
1460 | pipe_ctx->stream_res.tg, event_triggers, 2); |
1461 | |
1462 | if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) |
1463 | pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( |
1464 | pipe_ctx->stream_res.stream_enc, |
1465 | pipe_ctx->stream_res.tg->inst); |
1466 | |
1467 | pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( |
1468 | pipe_ctx->stream_res.opp, |
1469 | COLOR_SPACE_YCBCR601, |
1470 | stream->timing.display_color_depth, |
1471 | stream->signal); |
1472 | |
1473 | pipe_ctx->stream_res.opp->funcs->opp_program_fmt( |
1474 | pipe_ctx->stream_res.opp, |
1475 | &stream->bit_depth_params, |
1476 | &stream->clamping); |
1477 | while (odm_pipe) { |
1478 | odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( |
1479 | odm_pipe->stream_res.opp, |
1480 | COLOR_SPACE_YCBCR601, |
1481 | stream->timing.display_color_depth, |
1482 | stream->signal); |
1483 | |
1484 | odm_pipe->stream_res.opp->funcs->opp_program_fmt( |
1485 | odm_pipe->stream_res.opp, |
1486 | &stream->bit_depth_params, |
1487 | &stream->clamping); |
1488 | odm_pipe = odm_pipe->next_odm_pipe; |
1489 | } |
1490 | |
1491 | if (!stream->dpms_off) |
1492 | core_link_enable_stream(context, pipe_ctx); |
1493 | |
1494 | pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; |
1495 | |
1496 | pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false0; |
1497 | |
1498 | return DC_OK; |
1499 | } |
1500 | |
1501 | /******************************************************************************/ |
1502 | |
1503 | static void power_down_encoders(struct dc *dc) |
1504 | { |
1505 | int i; |
1506 | |
1507 | /* do not know BIOS back-front mapping, simply blank all. It will not |
1508 | * hurt for non-DP |
1509 | */ |
1510 | for (i = 0; i < dc->res_pool->stream_enc_count; i++) { |
1511 | dc->res_pool->stream_enc[i]->funcs->dp_blank( |
1512 | dc->res_pool->stream_enc[i]); |
1513 | } |
1514 | |
1515 | for (i = 0; i < dc->link_count; i++) { |
1516 | enum amd_signal_type signal = dc->links[i]->connector_signal; |
1517 | |
1518 | if ((signal == SIGNAL_TYPE_EDP) || |
1519 | (signal == SIGNAL_TYPE_DISPLAY_PORT)) |
1520 | if (!dc->links[i]->wa_flags.dp_keep_receiver_powered) |
1521 | dp_receiver_power_ctrl(dc->links[i], false0); |
1522 | |
1523 | if (signal != SIGNAL_TYPE_EDP) |
1524 | signal = SIGNAL_TYPE_NONE; |
1525 | |
1526 | dc->links[i]->link_enc->funcs->disable_output( |
1527 | dc->links[i]->link_enc, signal); |
1528 | |
1529 | dc->links[i]->link_status.link_active = false0; |
1530 | } |
1531 | } |
1532 | |
1533 | static void power_down_controllers(struct dc *dc) |
1534 | { |
1535 | int i; |
1536 | |
1537 | for (i = 0; i < dc->res_pool->timing_generator_count; i++) { |
1538 | dc->res_pool->timing_generators[i]->funcs->disable_crtc( |
1539 | dc->res_pool->timing_generators[i]); |
1540 | } |
1541 | } |
1542 | |
1543 | static void power_down_clock_sources(struct dc *dc) |
1544 | { |
1545 | int i; |
1546 | |
1547 | if (dc->res_pool->dp_clock_source->funcs->cs_power_down( |
1548 | dc->res_pool->dp_clock_source) == false0) |
1549 | dm_error("Failed to power down pll! (dp clk src)\n")__drm_err("Failed to power down pll! (dp clk src)\n"); |
1550 | |
1551 | for (i = 0; i < dc->res_pool->clk_src_count; i++) { |
1552 | if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( |
1553 | dc->res_pool->clock_sources[i]) == false0) |
1554 | dm_error("Failed to power down pll! (clk src index=%d)\n", i)__drm_err("Failed to power down pll! (clk src index=%d)\n", i ); |
1555 | } |
1556 | } |
1557 | |
1558 | static void power_down_all_hw_blocks(struct dc *dc) |
1559 | { |
1560 | power_down_encoders(dc); |
1561 | |
1562 | power_down_controllers(dc); |
1563 | |
1564 | power_down_clock_sources(dc); |
1565 | |
1566 | if (dc->fbc_compressor) |
1567 | dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); |
1568 | } |
1569 | |
1570 | static void disable_vga_and_power_gate_all_controllers( |
1571 | struct dc *dc) |
1572 | { |
1573 | int i; |
1574 | struct timing_generator *tg; |
1575 | struct dc_context *ctx = dc->ctx; |
1576 | |
1577 | for (i = 0; i < dc->res_pool->timing_generator_count; i++) { |
1578 | tg = dc->res_pool->timing_generators[i]; |
1579 | |
1580 | if (tg->funcs->disable_vga) |
1581 | tg->funcs->disable_vga(tg); |
1582 | } |
1583 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
1584 | /* Enable CLOCK gating for each pipe BEFORE controller |
1585 | * powergating. */ |
1586 | enable_display_pipe_clock_gating(ctx, |
1587 | true1); |
1588 | |
1589 | dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; |
1590 | dc->hwss.disable_plane(dc, |
1591 | &dc->current_state->res_ctx.pipe_ctx[i]); |
1592 | } |
1593 | } |
1594 | |
1595 | |
1596 | static struct dc_stream_state *get_edp_stream(struct dc_state *context) |
1597 | { |
1598 | int i; |
1599 | |
1600 | for (i = 0; i < context->stream_count; i++) { |
1601 | if (context->streams[i]->signal == SIGNAL_TYPE_EDP) |
1602 | return context->streams[i]; |
1603 | } |
1604 | return NULL((void *)0); |
1605 | } |
1606 | |
1607 | static struct dc_link *get_edp_link_with_sink( |
1608 | struct dc *dc, |
1609 | struct dc_state *context) |
1610 | { |
1611 | int i; |
1612 | struct dc_link *link = NULL((void *)0); |
1613 | |
1614 | /* check if there is an eDP panel not in use */ |
1615 | for (i = 0; i < dc->link_count; i++) { |
1616 | if (dc->links[i]->local_sink && |
1617 | dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { |
1618 | link = dc->links[i]; |
1619 | break; |
1620 | } |
1621 | } |
1622 | |
1623 | return link; |
1624 | } |
1625 | |
1626 | /** |
1627 | * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: |
1628 | * 1. Power down all DC HW blocks |
1629 | * 2. Disable VGA engine on all controllers |
1630 | * 3. Enable power gating for controller |
1631 | * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) |
1632 | */ |
1633 | void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) |
1634 | { |
1635 | int i; |
1636 | struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context); |
1637 | struct dc_link *edp_link = get_edp_link(dc); |
1638 | struct dc_stream_state *edp_stream = NULL((void *)0); |
1639 | bool_Bool can_apply_edp_fast_boot = false0; |
1640 | bool_Bool can_apply_seamless_boot = false0; |
1641 | bool_Bool keep_edp_vdd_on = false0; |
1642 | struct dce_hwseq *hws = dc->hwseq; |
1643 | |
1644 | if (hws->funcs.init_pipes) |
1645 | hws->funcs.init_pipes(dc, context); |
1646 | |
1647 | edp_stream = get_edp_stream(context); |
1648 | |
1649 | // Check fastboot support, disable on DCE8 because of blank screens |
1650 | if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 && |
1651 | dc->ctx->dce_version != DCE_VERSION_8_1 && |
1652 | dc->ctx->dce_version != DCE_VERSION_8_3) { |
1653 | |
1654 | // enable fastboot if backend is enabled on eDP |
1655 | if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) { |
1656 | /* Set optimization flag on eDP stream*/ |
1657 | if (edp_stream && edp_link->link_status.link_active) { |
1658 | edp_stream->apply_edp_fast_boot_optimization = true1; |
1659 | can_apply_edp_fast_boot = true1; |
1660 | } |
1661 | } |
1662 | |
1663 | // We are trying to enable eDP, don't power down VDD |
1664 | if (edp_stream) |
1665 | keep_edp_vdd_on = true1; |
1666 | } |
1667 | |
1668 | // Check seamless boot support |
1669 | for (i = 0; i < context->stream_count; i++) { |
1670 | if (context->streams[i]->apply_seamless_boot_optimization) { |
1671 | can_apply_seamless_boot = true1; |
1672 | break; |
1673 | } |
1674 | } |
1675 | |
1676 | /* eDP should not have stream in resume from S4 and so even with VBios post |
1677 | * it should get turned off |
1678 | */ |
1679 | if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { |
1680 | if (edp_link_with_sink && !keep_edp_vdd_on) { |
1681 | /*turn off backlight before DP_blank and encoder powered down*/ |
1682 | hws->funcs.edp_backlight_control(edp_link_with_sink, false0); |
1683 | } |
1684 | /*resume from S3, no vbios posting, no need to power down again*/ |
1685 | power_down_all_hw_blocks(dc); |
1686 | disable_vga_and_power_gate_all_controllers(dc); |
1687 | if (edp_link_with_sink && !keep_edp_vdd_on) |
1688 | dc->hwss.edp_power_control(edp_link_with_sink, false0); |
1689 | } |
1690 | bios_set_scratch_acc_mode_change(dc->ctx->dc_bios); |
1691 | } |
1692 | |
1693 | static uint32_t compute_pstate_blackout_duration( |
1694 | struct bw_fixed blackout_duration, |
1695 | const struct dc_stream_state *stream) |
1696 | { |
1697 | uint32_t total_dest_line_time_ns; |
1698 | uint32_t pstate_blackout_duration_ns; |
1699 | |
1700 | pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; |
1701 | |
1702 | total_dest_line_time_ns = 1000000UL * |
1703 | (stream->timing.h_total * 10) / |
1704 | stream->timing.pix_clk_100hz + |
1705 | pstate_blackout_duration_ns; |
1706 | |
1707 | return total_dest_line_time_ns; |
1708 | } |
1709 | |
1710 | static void dce110_set_displaymarks( |
1711 | const struct dc *dc, |
1712 | struct dc_state *context) |
1713 | { |
1714 | uint8_t i, num_pipes; |
1715 | unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; |
1716 | |
1717 | for (i = 0, num_pipes = 0; i < MAX_PIPES6; i++) { |
1718 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
1719 | uint32_t total_dest_line_time_ns; |
1720 | |
1721 | if (pipe_ctx->stream == NULL((void *)0)) |
1722 | continue; |
1723 | |
1724 | total_dest_line_time_ns = compute_pstate_blackout_duration( |
1725 | dc->bw_vbios->blackout_duration, pipe_ctx->stream); |
1726 | pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( |
1727 | pipe_ctx->plane_res.mi, |
1728 | context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], |
1729 | context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], |
1730 | context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], |
1731 | context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], |
1732 | total_dest_line_time_ns); |
1733 | if (i == underlay_idx) { |
1734 | num_pipes++; |
1735 | pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( |
1736 | pipe_ctx->plane_res.mi, |
1737 | context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], |
1738 | context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], |
1739 | context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], |
1740 | total_dest_line_time_ns); |
1741 | } |
1742 | num_pipes++; |
1743 | } |
1744 | } |
1745 | |
1746 | void dce110_set_safe_displaymarks( |
1747 | struct resource_context *res_ctx, |
1748 | const struct resource_pool *pool) |
1749 | { |
1750 | int i; |
1751 | int underlay_idx = pool->underlay_pipe_index; |
1752 | struct dce_watermarks max_marks = { |
1753 | MAX_WATERMARK0xFFFF, MAX_WATERMARK0xFFFF, MAX_WATERMARK0xFFFF, MAX_WATERMARK0xFFFF }; |
1754 | struct dce_watermarks nbp_marks = { |
1755 | SAFE_NBP_MARK0x7FFF, SAFE_NBP_MARK0x7FFF, SAFE_NBP_MARK0x7FFF, SAFE_NBP_MARK0x7FFF }; |
1756 | struct dce_watermarks min_marks = { 0, 0, 0, 0}; |
1757 | |
1758 | for (i = 0; i < MAX_PIPES6; i++) { |
1759 | if (res_ctx->pipe_ctx[i].stream == NULL((void *)0) || res_ctx->pipe_ctx[i].plane_res.mi == NULL((void *)0)) |
1760 | continue; |
1761 | |
1762 | res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( |
1763 | res_ctx->pipe_ctx[i].plane_res.mi, |
1764 | nbp_marks, |
1765 | max_marks, |
1766 | min_marks, |
1767 | max_marks, |
1768 | MAX_WATERMARK0xFFFF); |
1769 | |
1770 | if (i == underlay_idx) |
1771 | res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( |
1772 | res_ctx->pipe_ctx[i].plane_res.mi, |
1773 | nbp_marks, |
1774 | max_marks, |
1775 | max_marks, |
1776 | MAX_WATERMARK0xFFFF); |
1777 | |
1778 | } |
1779 | } |
1780 | |
1781 | /******************************************************************************* |
1782 | * Public functions |
1783 | ******************************************************************************/ |
1784 | |
1785 | static void set_drr(struct pipe_ctx **pipe_ctx, |
1786 | int num_pipes, unsigned int vmin, unsigned int vmax, |
1787 | unsigned int vmid, unsigned int vmid_frame_number) |
1788 | { |
1789 | int i = 0; |
1790 | struct drr_params params = {0}; |
1791 | // DRR should set trigger event to monitor surface update event |
1792 | unsigned int event_triggers = 0x80; |
1793 | // Note DRR trigger events are generated regardless of whether num frames met. |
1794 | unsigned int num_frames = 2; |
1795 | |
1796 | params.vertical_total_max = vmax; |
1797 | params.vertical_total_min = vmin; |
1798 | |
1799 | /* TODO: If multiple pipes are to be supported, you need |
1800 | * some GSL stuff. Static screen triggers may be programmed differently |
1801 | * as well. |
1802 | */ |
1803 | for (i = 0; i < num_pipes; i++) { |
1804 | pipe_ctx[i]->stream_res.tg->funcs->set_drr( |
1805 | pipe_ctx[i]->stream_res.tg, ¶ms); |
1806 | |
1807 | if (vmax != 0 && vmin != 0) |
1808 | pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( |
1809 | pipe_ctx[i]->stream_res.tg, |
1810 | event_triggers, num_frames); |
1811 | } |
1812 | } |
1813 | |
1814 | static void get_position(struct pipe_ctx **pipe_ctx, |
1815 | int num_pipes, |
1816 | struct crtc_position *position) |
1817 | { |
1818 | int i = 0; |
1819 | |
1820 | /* TODO: handle pipes > 1 |
1821 | */ |
1822 | for (i = 0; i < num_pipes; i++) |
1823 | pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); |
1824 | } |
1825 | |
1826 | static void set_static_screen_control(struct pipe_ctx **pipe_ctx, |
1827 | int num_pipes, const struct dc_static_screen_params *params) |
1828 | { |
1829 | unsigned int i; |
1830 | unsigned int triggers = 0; |
1831 | |
1832 | if (params->triggers.overlay_update) |
1833 | triggers |= 0x100; |
1834 | if (params->triggers.surface_update) |
1835 | triggers |= 0x80; |
1836 | if (params->triggers.cursor_update) |
1837 | triggers |= 0x2; |
1838 | if (params->triggers.force_trigger) |
1839 | triggers |= 0x1; |
1840 | |
1841 | if (num_pipes) { |
1842 | struct dc *dc = pipe_ctx[0]->stream->ctx->dc; |
1843 | |
1844 | if (dc->fbc_compressor) |
1845 | triggers |= 0x84; |
1846 | } |
1847 | |
1848 | for (i = 0; i < num_pipes; i++) |
1849 | pipe_ctx[i]->stream_res.tg->funcs-> |
1850 | set_static_screen_control(pipe_ctx[i]->stream_res.tg, |
1851 | triggers, params->num_frames); |
1852 | } |
1853 | |
1854 | /* |
1855 | * Check if FBC can be enabled |
1856 | */ |
1857 | static bool_Bool should_enable_fbc(struct dc *dc, |
1858 | struct dc_state *context, |
1859 | uint32_t *pipe_idx) |
1860 | { |
1861 | uint32_t i; |
1862 | struct pipe_ctx *pipe_ctx = NULL((void *)0); |
1863 | struct resource_context *res_ctx = &context->res_ctx; |
1864 | unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; |
1865 | |
1866 | |
1867 | ASSERT(dc->fbc_compressor)do { if (({ static int __warned; int __ret = !!(!(dc->fbc_compressor )); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dc->fbc_compressor)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c" , 1867); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
1868 | |
1869 | /* FBC memory should be allocated */ |
1870 | if (!dc->ctx->fbc_gpu_addr) |
1871 | return false0; |
1872 | |
1873 | /* Only supports single display */ |
1874 | if (context->stream_count != 1) |
1875 | return false0; |
1876 | |
1877 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
1878 | if (res_ctx->pipe_ctx[i].stream) { |
1879 | |
1880 | pipe_ctx = &res_ctx->pipe_ctx[i]; |
1881 | |
1882 | if (!pipe_ctx) |
1883 | continue; |
1884 | |
1885 | /* fbc not applicable on underlay pipe */ |
1886 | if (pipe_ctx->pipe_idx != underlay_idx) { |
1887 | *pipe_idx = i; |
1888 | break; |
1889 | } |
1890 | } |
1891 | } |
1892 | |
1893 | if (i == dc->res_pool->pipe_count) |
1894 | return false0; |
1895 | |
1896 | if (!pipe_ctx->stream->link) |
1897 | return false0; |
1898 | |
1899 | /* Only supports eDP */ |
1900 | if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) |
1901 | return false0; |
1902 | |
1903 | /* PSR should not be enabled */ |
1904 | if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) |
1905 | return false0; |
1906 | |
1907 | /* Nothing to compress */ |
1908 | if (!pipe_ctx->plane_state) |
1909 | return false0; |
1910 | |
1911 | /* Only for non-linear tiling */ |
1912 | if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) |
1913 | return false0; |
1914 | |
1915 | return true1; |
1916 | } |
1917 | |
1918 | /* |
1919 | * Enable FBC |
1920 | */ |
1921 | static void enable_fbc( |
1922 | struct dc *dc, |
1923 | struct dc_state *context) |
1924 | { |
1925 | uint32_t pipe_idx = 0; |
1926 | |
1927 | if (should_enable_fbc(dc, context, &pipe_idx)) { |
1928 | /* Program GRPH COMPRESSED ADDRESS and PITCH */ |
1929 | struct compr_addr_and_pitch_params params = {0, 0, 0}; |
1930 | struct compressor *compr = dc->fbc_compressor; |
1931 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; |
1932 | |
1933 | params.source_view_width = pipe_ctx->stream->timing.h_addressable; |
1934 | params.source_view_height = pipe_ctx->stream->timing.v_addressable; |
1935 | params.inst = pipe_ctx->stream_res.tg->inst; |
1936 | compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; |
1937 | |
1938 | compr->funcs->surface_address_and_pitch(compr, ¶ms); |
1939 | compr->funcs->set_fbc_invalidation_triggers(compr, 1); |
1940 | |
1941 | compr->funcs->enable_fbc(compr, ¶ms); |
1942 | } |
1943 | } |
1944 | |
1945 | static void dce110_reset_hw_ctx_wrap( |
1946 | struct dc *dc, |
1947 | struct dc_state *context) |
1948 | { |
1949 | int i; |
1950 | |
1951 | /* Reset old context */ |
1952 | /* look up the targets that have been removed since last commit */ |
1953 | for (i = 0; i < MAX_PIPES6; i++) { |
1954 | struct pipe_ctx *pipe_ctx_old = |
1955 | &dc->current_state->res_ctx.pipe_ctx[i]; |
1956 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
1957 | |
1958 | /* Note: We need to disable output if clock sources change, |
1959 | * since bios does optimization and doesn't apply if changing |
1960 | * PHY when not already disabled. |
1961 | */ |
1962 | |
1963 | /* Skip underlay pipe since it will be handled in commit surface*/ |
1964 | if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) |
1965 | continue; |
1966 | |
1967 | if (!pipe_ctx->stream || |
1968 | pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { |
1969 | struct clock_source *old_clk = pipe_ctx_old->clock_source; |
1970 | |
1971 | /* Disable if new stream is null. O/w, if stream is |
1972 | * disabled already, no need to disable again. |
1973 | */ |
1974 | if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { |
1975 | core_link_disable_stream(pipe_ctx_old); |
1976 | |
1977 | /* free acquired resources*/ |
1978 | if (pipe_ctx_old->stream_res.audio) { |
1979 | /*disable az_endpoint*/ |
1980 | pipe_ctx_old->stream_res.audio->funcs-> |
1981 | az_disable(pipe_ctx_old->stream_res.audio); |
1982 | |
1983 | /*free audio*/ |
1984 | if (dc->caps.dynamic_audio == true1) { |
1985 | /*we have to dynamic arbitrate the audio endpoints*/ |
1986 | /*we free the resource, need reset is_audio_acquired*/ |
1987 | update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, |
1988 | pipe_ctx_old->stream_res.audio, false0); |
1989 | pipe_ctx_old->stream_res.audio = NULL((void *)0); |
1990 | } |
1991 | } |
1992 | } |
1993 | |
1994 | pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true1); |
1995 | if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { |
1996 | dm_error("DC: failed to blank crtc!\n")__drm_err("DC: failed to blank crtc!\n"); |
1997 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 1997); do {} while (0); } while (0); |
1998 | } |
1999 | pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); |
2000 | pipe_ctx_old->plane_res.mi->funcs->free_mem_input( |
2001 | pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); |
2002 | |
2003 | if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, |
2004 | dc->res_pool, |
2005 | old_clk)) |
2006 | old_clk->funcs->cs_power_down(old_clk); |
2007 | |
2008 | dc->hwss.disable_plane(dc, pipe_ctx_old); |
2009 | |
2010 | pipe_ctx_old->stream = NULL((void *)0); |
2011 | } |
2012 | } |
2013 | } |
2014 | |
2015 | static void dce110_setup_audio_dto( |
2016 | struct dc *dc, |
2017 | struct dc_state *context) |
2018 | { |
2019 | int i; |
2020 | |
2021 | /* program audio wall clock. use HDMI as clock source if HDMI |
2022 | * audio active. Otherwise, use DP as clock source |
2023 | * first, loop to find any HDMI audio, if not, loop find DP audio |
2024 | */ |
2025 | /* Setup audio rate clock source */ |
2026 | /* Issue: |
2027 | * Audio lag happened on DP monitor when unplug a HDMI monitor |
2028 | * |
2029 | * Cause: |
2030 | * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL |
2031 | * is set to either dto0 or dto1, audio should work fine. |
2032 | * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, |
2033 | * set to dto0 will cause audio lag. |
2034 | * |
2035 | * Solution: |
2036 | * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, |
2037 | * find first available pipe with audio, setup audio wall DTO per topology |
2038 | * instead of per pipe. |
2039 | */ |
2040 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
2041 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
2042 | |
2043 | if (pipe_ctx->stream == NULL((void *)0)) |
2044 | continue; |
2045 | |
2046 | if (pipe_ctx->top_pipe) |
2047 | continue; |
2048 | if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A) |
2049 | continue; |
2050 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { |
2051 | struct audio_output audio_output; |
2052 | |
2053 | build_audio_output(context, pipe_ctx, &audio_output); |
2054 | |
2055 | pipe_ctx->stream_res.audio->funcs->wall_dto_setup( |
2056 | pipe_ctx->stream_res.audio, |
2057 | pipe_ctx->stream->signal, |
2058 | &audio_output.crtc_info, |
2059 | &audio_output.pll_info); |
2060 | break; |
2061 | } |
2062 | } |
2063 | |
2064 | /* no HDMI audio is found, try DP audio */ |
2065 | if (i == dc->res_pool->pipe_count) { |
2066 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
2067 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
2068 | |
2069 | if (pipe_ctx->stream == NULL((void *)0)) |
2070 | continue; |
2071 | |
2072 | if (pipe_ctx->top_pipe) |
2073 | continue; |
2074 | |
2075 | if (!dc_is_dp_signal(pipe_ctx->stream->signal)) |
2076 | continue; |
2077 | |
2078 | if (pipe_ctx->stream_res.audio != NULL((void *)0)) { |
2079 | struct audio_output audio_output; |
2080 | |
2081 | build_audio_output(context, pipe_ctx, &audio_output); |
2082 | |
2083 | pipe_ctx->stream_res.audio->funcs->wall_dto_setup( |
2084 | pipe_ctx->stream_res.audio, |
2085 | pipe_ctx->stream->signal, |
2086 | &audio_output.crtc_info, |
2087 | &audio_output.pll_info); |
2088 | break; |
2089 | } |
2090 | } |
2091 | } |
2092 | } |
2093 | |
2094 | enum dc_status dce110_apply_ctx_to_hw( |
2095 | struct dc *dc, |
2096 | struct dc_state *context) |
2097 | { |
2098 | struct dce_hwseq *hws = dc->hwseq; |
2099 | struct dc_bios *dcb = dc->ctx->dc_bios; |
2100 | enum dc_status status; |
2101 | int i; |
2102 | |
2103 | /* Reset old context */ |
2104 | /* look up the targets that have been removed since last commit */ |
2105 | hws->funcs.reset_hw_ctx_wrap(dc, context); |
2106 | |
2107 | /* Skip applying if no targets */ |
2108 | if (context->stream_count <= 0) |
2109 | return DC_OK; |
2110 | |
2111 | /* Apply new context */ |
2112 | dcb->funcs->set_scratch_critical_state(dcb, true1); |
2113 | |
2114 | /* below is for real asic only */ |
2115 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
2116 | struct pipe_ctx *pipe_ctx_old = |
2117 | &dc->current_state->res_ctx.pipe_ctx[i]; |
2118 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
2119 | |
2120 | if (pipe_ctx->stream == NULL((void *)0) || pipe_ctx->top_pipe) |
2121 | continue; |
2122 | |
2123 | if (pipe_ctx->stream == pipe_ctx_old->stream) { |
2124 | if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) |
2125 | dce_crtc_switch_to_clk_src(dc->hwseq, |
2126 | pipe_ctx->clock_source, i); |
2127 | continue; |
2128 | } |
2129 | |
2130 | hws->funcs.enable_display_power_gating( |
2131 | dc, i, dc->ctx->dc_bios, |
2132 | PIPE_GATING_CONTROL_DISABLE); |
2133 | } |
2134 | |
2135 | if (dc->fbc_compressor) |
2136 | dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); |
2137 | |
2138 | dce110_setup_audio_dto(dc, context); |
2139 | |
2140 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
2141 | struct pipe_ctx *pipe_ctx_old = |
2142 | &dc->current_state->res_ctx.pipe_ctx[i]; |
2143 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
2144 | |
2145 | if (pipe_ctx->stream == NULL((void *)0)) |
2146 | continue; |
2147 | |
2148 | if (pipe_ctx->stream == pipe_ctx_old->stream && |
2149 | pipe_ctx->stream->link->link_state_valid) { |
2150 | continue; |
2151 | } |
2152 | |
2153 | if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) |
2154 | continue; |
2155 | |
2156 | if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) |
2157 | continue; |
2158 | |
2159 | status = apply_single_controller_ctx_to_hw( |
2160 | pipe_ctx, |
2161 | context, |
2162 | dc); |
2163 | |
2164 | if (DC_OK != status) |
2165 | return status; |
2166 | } |
2167 | |
2168 | if (dc->fbc_compressor) |
2169 | enable_fbc(dc, dc->current_state); |
2170 | |
2171 | dcb->funcs->set_scratch_critical_state(dcb, false0); |
2172 | |
2173 | return DC_OK; |
2174 | } |
2175 | |
2176 | /******************************************************************************* |
2177 | * Front End programming |
2178 | ******************************************************************************/ |
2179 | static void set_default_colors(struct pipe_ctx *pipe_ctx) |
2180 | { |
2181 | struct default_adjustment default_adjust = { 0 }; |
2182 | |
2183 | default_adjust.force_hw_default = false0; |
2184 | default_adjust.in_color_space = pipe_ctx->plane_state->color_space; |
2185 | default_adjust.out_color_space = pipe_ctx->stream->output_color_space; |
2186 | default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; |
2187 | default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; |
2188 | |
2189 | /* display color depth */ |
2190 | default_adjust.color_depth = |
2191 | pipe_ctx->stream->timing.display_color_depth; |
2192 | |
2193 | /* Lb color depth */ |
2194 | default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; |
2195 | |
2196 | pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( |
2197 | pipe_ctx->plane_res.xfm, &default_adjust); |
2198 | } |
2199 | |
2200 | |
2201 | /******************************************************************************* |
2202 | * In order to turn on/off specific surface we will program |
2203 | * Blender + CRTC |
2204 | * |
2205 | * In case that we have two surfaces and they have a different visibility |
2206 | * we can't turn off the CRTC since it will turn off the entire display |
2207 | * |
2208 | * |----------------------------------------------- | |
2209 | * |bottom pipe|curr pipe | | | |
2210 | * |Surface |Surface | Blender | CRCT | |
2211 | * |visibility |visibility | Configuration| | |
2212 | * |------------------------------------------------| |
2213 | * | off | off | CURRENT_PIPE | blank | |
2214 | * | off | on | CURRENT_PIPE | unblank | |
2215 | * | on | off | OTHER_PIPE | unblank | |
2216 | * | on | on | BLENDING | unblank | |
2217 | * -------------------------------------------------| |
2218 | * |
2219 | ******************************************************************************/ |
2220 | static void program_surface_visibility(const struct dc *dc, |
2221 | struct pipe_ctx *pipe_ctx) |
2222 | { |
2223 | enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; |
2224 | bool_Bool blank_target = false0; |
2225 | |
2226 | if (pipe_ctx->bottom_pipe) { |
2227 | |
2228 | /* For now we are supporting only two pipes */ |
2229 | ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL)do { if (({ static int __warned; int __ret = !!(!(pipe_ctx-> bottom_pipe->bottom_pipe == ((void *)0))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(pipe_ctx->bottom_pipe->bottom_pipe == ((void *)0))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c" , 2229); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); |
2230 | |
2231 | if (pipe_ctx->bottom_pipe->plane_state->visible) { |
2232 | if (pipe_ctx->plane_state->visible) |
2233 | blender_mode = BLND_MODE_BLENDING; |
2234 | else |
2235 | blender_mode = BLND_MODE_OTHER_PIPE; |
2236 | |
2237 | } else if (!pipe_ctx->plane_state->visible) |
2238 | blank_target = true1; |
2239 | |
2240 | } else if (!pipe_ctx->plane_state->visible) |
2241 | blank_target = true1; |
2242 | |
2243 | dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); |
2244 | pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); |
2245 | |
2246 | } |
2247 | |
2248 | static void program_gamut_remap(struct pipe_ctx *pipe_ctx) |
2249 | { |
2250 | int i = 0; |
2251 | struct xfm_grph_csc_adjustment adjust; |
2252 | memset(&adjust, 0, sizeof(adjust))__builtin_memset((&adjust), (0), (sizeof(adjust))); |
2253 | adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; |
2254 | |
2255 | |
2256 | if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true1) { |
2257 | adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; |
2258 | |
2259 | for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE12; i++) |
2260 | adjust.temperature_matrix[i] = |
2261 | pipe_ctx->stream->gamut_remap_matrix.matrix[i]; |
2262 | } |
2263 | |
2264 | pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); |
2265 | } |
2266 | static void update_plane_addr(const struct dc *dc, |
2267 | struct pipe_ctx *pipe_ctx) |
2268 | { |
2269 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
2270 | |
2271 | if (plane_state == NULL((void *)0)) |
2272 | return; |
2273 | |
2274 | pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( |
2275 | pipe_ctx->plane_res.mi, |
2276 | &plane_state->address, |
2277 | plane_state->flip_immediate); |
2278 | |
2279 | plane_state->status.requested_address = plane_state->address; |
2280 | } |
2281 | |
2282 | static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) |
2283 | { |
2284 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
2285 | |
2286 | if (plane_state == NULL((void *)0)) |
2287 | return; |
2288 | |
2289 | plane_state->status.is_flip_pending = |
2290 | pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( |
2291 | pipe_ctx->plane_res.mi); |
2292 | |
2293 | if (plane_state->status.is_flip_pending && !plane_state->visible) |
2294 | pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; |
2295 | |
2296 | plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; |
2297 | if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && |
2298 | pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { |
2299 | plane_state->status.is_right_eye =\ |
2300 | !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); |
2301 | } |
2302 | } |
2303 | |
2304 | void dce110_power_down(struct dc *dc) |
2305 | { |
2306 | power_down_all_hw_blocks(dc); |
2307 | disable_vga_and_power_gate_all_controllers(dc); |
2308 | } |
2309 | |
2310 | static bool_Bool wait_for_reset_trigger_to_occur( |
2311 | struct dc_context *dc_ctx, |
2312 | struct timing_generator *tg) |
2313 | { |
2314 | bool_Bool rc = false0; |
2315 | |
2316 | /* To avoid endless loop we wait at most |
2317 | * frames_to_wait_on_triggered_reset frames for the reset to occur. */ |
2318 | const uint32_t frames_to_wait_on_triggered_reset = 10; |
2319 | uint32_t i; |
2320 | |
2321 | for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { |
2322 | |
2323 | if (!tg->funcs->is_counter_moving(tg)) { |
2324 | DC_ERROR("TG counter is not moving!\n")do { (void)(dc_ctx); __drm_err("TG counter is not moving!\n") ; } while (0); |
2325 | break; |
2326 | } |
2327 | |
2328 | if (tg->funcs->did_triggered_reset_occur(tg)) { |
2329 | rc = true1; |
2330 | /* usually occurs at i=1 */ |
2331 | DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: reset occurred at wait count: %d\n" , i); } while (0) |
2332 | i)do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: reset occurred at wait count: %d\n" , i); } while (0); |
2333 | break; |
2334 | } |
2335 | |
2336 | /* Wait for one frame. */ |
2337 | tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); |
2338 | tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); |
2339 | } |
2340 | |
2341 | if (false0 == rc) |
2342 | DC_ERROR("GSL: Timeout on reset trigger!\n")do { (void)(dc_ctx); __drm_err("GSL: Timeout on reset trigger!\n" ); } while (0); |
2343 | |
2344 | return rc; |
2345 | } |
2346 | |
2347 | /* Enable timing synchronization for a group of Timing Generators. */ |
2348 | static void dce110_enable_timing_synchronization( |
2349 | struct dc *dc, |
2350 | int group_index, |
2351 | int group_size, |
2352 | struct pipe_ctx *grouped_pipes[]) |
2353 | { |
2354 | struct dc_context *dc_ctx = dc->ctx; |
2355 | struct dcp_gsl_params gsl_params = { 0 }; |
2356 | int i; |
2357 | |
2358 | DC_SYNC_INFO("GSL: Setting-up...\n")do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: Setting-up...\n" ); } while (0); |
2359 | |
2360 | /* Designate a single TG in the group as a master. |
2361 | * Since HW doesn't care which one, we always assign |
2362 | * the 1st one in the group. */ |
2363 | gsl_params.gsl_group = 0; |
2364 | gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; |
2365 | |
2366 | for (i = 0; i < group_size; i++) |
2367 | grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( |
2368 | grouped_pipes[i]->stream_res.tg, &gsl_params); |
2369 | |
2370 | /* Reset slave controllers on master VSync */ |
2371 | DC_SYNC_INFO("GSL: enabling trigger-reset\n")do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: enabling trigger-reset\n" ); } while (0); |
2372 | |
2373 | for (i = 1 /* skip the master */; i < group_size; i++) |
2374 | grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( |
2375 | grouped_pipes[i]->stream_res.tg, |
2376 | gsl_params.gsl_group); |
2377 | |
2378 | for (i = 1 /* skip the master */; i < group_size; i++) { |
2379 | DC_SYNC_INFO("GSL: waiting for reset to occur.\n")do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: waiting for reset to occur.\n" ); } while (0); |
2380 | wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); |
2381 | grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( |
2382 | grouped_pipes[i]->stream_res.tg); |
2383 | } |
2384 | |
2385 | /* GSL Vblank synchronization is a one time sync mechanism, assumption |
2386 | * is that the sync'ed displays will not drift out of sync over time*/ |
2387 | DC_SYNC_INFO("GSL: Restoring register states.\n")do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: Restoring register states.\n" ); } while (0); |
2388 | for (i = 0; i < group_size; i++) |
2389 | grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); |
2390 | |
2391 | DC_SYNC_INFO("GSL: Set-up complete.\n")do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: Set-up complete.\n" ); } while (0); |
2392 | } |
2393 | |
2394 | static void dce110_enable_per_frame_crtc_position_reset( |
2395 | struct dc *dc, |
2396 | int group_size, |
2397 | struct pipe_ctx *grouped_pipes[]) |
2398 | { |
2399 | struct dc_context *dc_ctx = dc->ctx; |
2400 | struct dcp_gsl_params gsl_params = { 0 }; |
2401 | int i; |
2402 | |
2403 | gsl_params.gsl_group = 0; |
2404 | gsl_params.gsl_master = 0; |
2405 | |
2406 | for (i = 0; i < group_size; i++) |
2407 | grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( |
2408 | grouped_pipes[i]->stream_res.tg, &gsl_params); |
2409 | |
2410 | DC_SYNC_INFO("GSL: enabling trigger-reset\n")do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: enabling trigger-reset\n" ); } while (0); |
2411 | |
2412 | for (i = 1; i < group_size; i++) |
2413 | grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( |
2414 | grouped_pipes[i]->stream_res.tg, |
2415 | gsl_params.gsl_master, |
2416 | &grouped_pipes[i]->stream->triggered_crtc_reset); |
2417 | |
2418 | DC_SYNC_INFO("GSL: waiting for reset to occur.\n")do { (void)(dc_ctx); __drm_dbg(DRM_UT_KMS, "GSL: waiting for reset to occur.\n" ); } while (0); |
2419 | for (i = 1; i < group_size; i++) |
2420 | wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); |
2421 | |
2422 | for (i = 0; i < group_size; i++) |
2423 | grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); |
2424 | |
2425 | } |
2426 | |
2427 | static void init_pipes(struct dc *dc, struct dc_state *context) |
2428 | { |
2429 | // Do nothing |
2430 | } |
2431 | |
2432 | static void init_hw(struct dc *dc) |
2433 | { |
2434 | int i; |
2435 | struct dc_bios *bp; |
2436 | struct transform *xfm; |
2437 | struct abm *abm; |
2438 | struct dmcu *dmcu; |
2439 | struct dce_hwseq *hws = dc->hwseq; |
2440 | uint32_t backlight = MAX_BACKLIGHT_LEVEL0xFFFF; |
2441 | |
2442 | bp = dc->ctx->dc_bios; |
2443 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
2444 | xfm = dc->res_pool->transforms[i]; |
2445 | xfm->funcs->transform_reset(xfm); |
2446 | |
2447 | hws->funcs.enable_display_power_gating( |
2448 | dc, i, bp, |
2449 | PIPE_GATING_CONTROL_INIT); |
2450 | hws->funcs.enable_display_power_gating( |
2451 | dc, i, bp, |
2452 | PIPE_GATING_CONTROL_DISABLE); |
2453 | hws->funcs.enable_display_pipe_clock_gating( |
2454 | dc->ctx, |
2455 | true1); |
2456 | } |
2457 | |
2458 | dce_clock_gating_power_up(dc->hwseq, false0); |
2459 | /***************************************/ |
2460 | |
2461 | for (i = 0; i < dc->link_count; i++) { |
2462 | /****************************************/ |
2463 | /* Power up AND update implementation according to the |
2464 | * required signal (which may be different from the |
2465 | * default signal on connector). */ |
2466 | struct dc_link *link = dc->links[i]; |
2467 | |
2468 | link->link_enc->funcs->hw_init(link->link_enc); |
2469 | } |
2470 | |
2471 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
2472 | struct timing_generator *tg = dc->res_pool->timing_generators[i]; |
2473 | |
2474 | tg->funcs->disable_vga(tg); |
2475 | |
2476 | /* Blank controller using driver code instead of |
2477 | * command table. */ |
2478 | tg->funcs->set_blank(tg, true1); |
2479 | hwss_wait_for_blank_complete(tg); |
2480 | } |
2481 | |
2482 | for (i = 0; i < dc->res_pool->audio_count; i++) { |
2483 | struct audio *audio = dc->res_pool->audios[i]; |
2484 | audio->funcs->hw_init(audio); |
2485 | } |
2486 | |
2487 | for (i = 0; i < dc->link_count; i++) { |
2488 | struct dc_link *link = dc->links[i]; |
2489 | |
2490 | if (link->panel_cntl) |
2491 | backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); |
2492 | } |
2493 | |
2494 | abm = dc->res_pool->abm; |
2495 | if (abm != NULL((void *)0)) |
2496 | abm->funcs->abm_init(abm, backlight); |
2497 | |
2498 | dmcu = dc->res_pool->dmcu; |
2499 | if (dmcu != NULL((void *)0) && abm != NULL((void *)0)) |
2500 | abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); |
2501 | |
2502 | if (dc->fbc_compressor) |
2503 | dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); |
2504 | |
2505 | } |
2506 | |
2507 | |
2508 | void dce110_prepare_bandwidth( |
2509 | struct dc *dc, |
2510 | struct dc_state *context) |
2511 | { |
2512 | struct clk_mgr *dccg = dc->clk_mgr; |
2513 | |
2514 | dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); |
2515 | |
2516 | dccg->funcs->update_clocks( |
2517 | dccg, |
2518 | context, |
2519 | false0); |
2520 | } |
2521 | |
2522 | void dce110_optimize_bandwidth( |
2523 | struct dc *dc, |
2524 | struct dc_state *context) |
2525 | { |
2526 | struct clk_mgr *dccg = dc->clk_mgr; |
2527 | |
2528 | dce110_set_displaymarks(dc, context); |
2529 | |
2530 | dccg->funcs->update_clocks( |
2531 | dccg, |
2532 | context, |
2533 | true1); |
2534 | } |
2535 | |
2536 | static void dce110_program_front_end_for_pipe( |
2537 | struct dc *dc, struct pipe_ctx *pipe_ctx) |
2538 | { |
2539 | struct mem_input *mi = pipe_ctx->plane_res.mi; |
2540 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
2541 | struct xfm_grph_csc_adjustment adjust; |
2542 | struct out_csc_color_matrix tbl_entry; |
2543 | unsigned int i; |
2544 | struct dce_hwseq *hws = dc->hwseq; |
2545 | |
2546 | DC_LOGGER_INIT(); |
2547 | memset(&tbl_entry, 0, sizeof(tbl_entry))__builtin_memset((&tbl_entry), (0), (sizeof(tbl_entry))); |
2548 | |
2549 | memset(&adjust, 0, sizeof(adjust))__builtin_memset((&adjust), (0), (sizeof(adjust))); |
2550 | adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; |
2551 | |
2552 | dce_enable_fe_clock(dc->hwseq, mi->inst, true1); |
2553 | |
2554 | set_default_colors(pipe_ctx); |
2555 | if (pipe_ctx->stream->csc_color_matrix.enable_adjustment |
2556 | == true1) { |
2557 | tbl_entry.color_space = |
2558 | pipe_ctx->stream->output_color_space; |
2559 | |
2560 | for (i = 0; i < 12; i++) |
2561 | tbl_entry.regval[i] = |
2562 | pipe_ctx->stream->csc_color_matrix.matrix[i]; |
2563 | |
2564 | pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment |
2565 | (pipe_ctx->plane_res.xfm, &tbl_entry); |
2566 | } |
2567 | |
2568 | if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true1) { |
2569 | adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; |
2570 | |
2571 | for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE12; i++) |
2572 | adjust.temperature_matrix[i] = |
2573 | pipe_ctx->stream->gamut_remap_matrix.matrix[i]; |
2574 | } |
2575 | |
2576 | pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); |
2577 | |
2578 | pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; |
2579 | |
2580 | program_scaler(dc, pipe_ctx); |
2581 | |
2582 | mi->funcs->mem_input_program_surface_config( |
2583 | mi, |
2584 | plane_state->format, |
2585 | &plane_state->tiling_info, |
2586 | &plane_state->plane_size, |
2587 | plane_state->rotation, |
2588 | NULL((void *)0), |
2589 | false0); |
2590 | if (mi->funcs->set_blank) |
2591 | mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); |
2592 | |
2593 | if (dc->config.gpu_vm_support) |
2594 | mi->funcs->mem_input_program_pte_vm( |
2595 | pipe_ctx->plane_res.mi, |
2596 | plane_state->format, |
2597 | &plane_state->tiling_info, |
2598 | plane_state->rotation); |
2599 | |
2600 | /* Moved programming gamma from dc to hwss */ |
2601 | if (pipe_ctx->plane_state->update_flags.bits.full_update || |
2602 | pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || |
2603 | pipe_ctx->plane_state->update_flags.bits.gamma_change) |
2604 | hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); |
2605 | |
2606 | if (pipe_ctx->plane_state->update_flags.bits.full_update) |
2607 | hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); |
2608 | |
2609 | DC_LOG_SURFACE(do { } while(0) |
2610 | "Pipe:%d %p: addr hi:0x%x, "do { } while(0) |
2611 | "addr low:0x%x, "do { } while(0) |
2612 | "src: %d, %d, %d,"do { } while(0) |
2613 | " %d; dst: %d, %d, %d, %d;"do { } while(0) |
2614 | "clip: %d, %d, %d, %d\n",do { } while(0) |
2615 | pipe_ctx->pipe_idx,do { } while(0) |
2616 | (void *) pipe_ctx->plane_state,do { } while(0) |
2617 | pipe_ctx->plane_state->address.grph.addr.high_part,do { } while(0) |
2618 | pipe_ctx->plane_state->address.grph.addr.low_part,do { } while(0) |
2619 | pipe_ctx->plane_state->src_rect.x,do { } while(0) |
2620 | pipe_ctx->plane_state->src_rect.y,do { } while(0) |
2621 | pipe_ctx->plane_state->src_rect.width,do { } while(0) |
2622 | pipe_ctx->plane_state->src_rect.height,do { } while(0) |
2623 | pipe_ctx->plane_state->dst_rect.x,do { } while(0) |
2624 | pipe_ctx->plane_state->dst_rect.y,do { } while(0) |
2625 | pipe_ctx->plane_state->dst_rect.width,do { } while(0) |
2626 | pipe_ctx->plane_state->dst_rect.height,do { } while(0) |
2627 | pipe_ctx->plane_state->clip_rect.x,do { } while(0) |
2628 | pipe_ctx->plane_state->clip_rect.y,do { } while(0) |
2629 | pipe_ctx->plane_state->clip_rect.width,do { } while(0) |
2630 | pipe_ctx->plane_state->clip_rect.height)do { } while(0); |
2631 | |
2632 | DC_LOG_SURFACE(do { } while(0) |
2633 | "Pipe %d: width, height, x, y\n"do { } while(0) |
2634 | "viewport:%d, %d, %d, %d\n"do { } while(0) |
2635 | "recout: %d, %d, %d, %d\n",do { } while(0) |
2636 | pipe_ctx->pipe_idx,do { } while(0) |
2637 | pipe_ctx->plane_res.scl_data.viewport.width,do { } while(0) |
2638 | pipe_ctx->plane_res.scl_data.viewport.height,do { } while(0) |
2639 | pipe_ctx->plane_res.scl_data.viewport.x,do { } while(0) |
2640 | pipe_ctx->plane_res.scl_data.viewport.y,do { } while(0) |
2641 | pipe_ctx->plane_res.scl_data.recout.width,do { } while(0) |
2642 | pipe_ctx->plane_res.scl_data.recout.height,do { } while(0) |
2643 | pipe_ctx->plane_res.scl_data.recout.x,do { } while(0) |
2644 | pipe_ctx->plane_res.scl_data.recout.y)do { } while(0); |
2645 | } |
2646 | |
2647 | static void dce110_apply_ctx_for_surface( |
2648 | struct dc *dc, |
2649 | const struct dc_stream_state *stream, |
2650 | int num_planes, |
2651 | struct dc_state *context) |
2652 | { |
2653 | int i; |
2654 | |
2655 | if (num_planes == 0) |
2656 | return; |
2657 | |
2658 | if (dc->fbc_compressor) |
2659 | dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); |
2660 | |
2661 | for (i = 0; i < dc->res_pool->pipe_count; i++) { |
2662 | struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; |
2663 | |
2664 | if (pipe_ctx->stream != stream) |
2665 | continue; |
2666 | |
2667 | /* Need to allocate mem before program front end for Fiji */ |
2668 | pipe_ctx->plane_res.mi->funcs->allocate_mem_input( |
2669 | pipe_ctx->plane_res.mi, |
2670 | pipe_ctx->stream->timing.h_total, |
2671 | pipe_ctx->stream->timing.v_total, |
2672 | pipe_ctx->stream->timing.pix_clk_100hz / 10, |
2673 | context->stream_count); |
2674 | |
2675 | dce110_program_front_end_for_pipe(dc, pipe_ctx); |
2676 | |
2677 | dc->hwss.update_plane_addr(dc, pipe_ctx); |
2678 | |
2679 | program_surface_visibility(dc, pipe_ctx); |
2680 | |
2681 | } |
2682 | |
2683 | if (dc->fbc_compressor) |
2684 | enable_fbc(dc, context); |
2685 | } |
2686 | |
2687 | static void dce110_post_unlock_program_front_end( |
2688 | struct dc *dc, |
2689 | struct dc_state *context) |
2690 | { |
2691 | } |
2692 | |
2693 | static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx) |
2694 | { |
2695 | struct dce_hwseq *hws = dc->hwseq; |
2696 | int fe_idx = pipe_ctx->plane_res.mi ? |
2697 | pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; |
2698 | |
2699 | /* Do not power down fe when stream is active on dce*/ |
2700 | if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) |
2701 | return; |
2702 | |
2703 | hws->funcs.enable_display_power_gating( |
2704 | dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); |
2705 | |
2706 | dc->res_pool->transforms[fe_idx]->funcs->transform_reset( |
2707 | dc->res_pool->transforms[fe_idx]); |
2708 | } |
2709 | |
2710 | static void dce110_wait_for_mpcc_disconnect( |
2711 | struct dc *dc, |
2712 | struct resource_pool *res_pool, |
2713 | struct pipe_ctx *pipe_ctx) |
2714 | { |
2715 | /* do nothing*/ |
2716 | } |
2717 | |
2718 | static void program_output_csc(struct dc *dc, |
2719 | struct pipe_ctx *pipe_ctx, |
2720 | enum dc_color_space colorspace, |
2721 | uint16_t *matrix, |
2722 | int opp_id) |
2723 | { |
2724 | int i; |
2725 | struct out_csc_color_matrix tbl_entry; |
2726 | |
2727 | if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true1) { |
2728 | enum dc_color_space color_space = pipe_ctx->stream->output_color_space; |
2729 | |
2730 | for (i = 0; i < 12; i++) |
2731 | tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; |
2732 | |
2733 | tbl_entry.color_space = color_space; |
2734 | |
2735 | pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( |
2736 | pipe_ctx->plane_res.xfm, &tbl_entry); |
2737 | } |
2738 | } |
2739 | |
2740 | static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) |
2741 | { |
2742 | struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; |
2743 | struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; |
2744 | struct mem_input *mi = pipe_ctx->plane_res.mi; |
2745 | struct dc_cursor_mi_param param = { |
2746 | .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, |
2747 | .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, |
2748 | .viewport = pipe_ctx->plane_res.scl_data.viewport, |
2749 | .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, |
2750 | .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, |
2751 | .rotation = pipe_ctx->plane_state->rotation, |
2752 | .mirror = pipe_ctx->plane_state->horizontal_mirror |
2753 | }; |
2754 | |
2755 | /** |
2756 | * If the cursor's source viewport is clipped then we need to |
2757 | * translate the cursor to appear in the correct position on |
2758 | * the screen. |
2759 | * |
2760 | * This translation isn't affected by scaling so it needs to be |
2761 | * done *after* we adjust the position for the scale factor. |
2762 | * |
2763 | * This is only done by opt-in for now since there are still |
2764 | * some usecases like tiled display that might enable the |
2765 | * cursor on both streams while expecting dc to clip it. |
2766 | */ |
2767 | if (pos_cpy.translate_by_source) { |
2768 | pos_cpy.x += pipe_ctx->plane_state->src_rect.x; |
2769 | pos_cpy.y += pipe_ctx->plane_state->src_rect.y; |
2770 | } |
2771 | |
2772 | if (pipe_ctx->plane_state->address.type |
2773 | == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) |
2774 | pos_cpy.enable = false0; |
2775 | |
2776 | if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) |
2777 | pos_cpy.enable = false0; |
2778 | |
2779 | if (ipp->funcs->ipp_cursor_set_position) |
2780 | ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); |
2781 | if (mi->funcs->set_cursor_position) |
2782 | mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); |
2783 | } |
2784 | |
2785 | static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) |
2786 | { |
2787 | struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; |
2788 | |
2789 | if (pipe_ctx->plane_res.ipp && |
2790 | pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) |
2791 | pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( |
2792 | pipe_ctx->plane_res.ipp, attributes); |
2793 | |
2794 | if (pipe_ctx->plane_res.mi && |
2795 | pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) |
2796 | pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( |
2797 | pipe_ctx->plane_res.mi, attributes); |
2798 | |
2799 | if (pipe_ctx->plane_res.xfm && |
2800 | pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) |
2801 | pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( |
2802 | pipe_ctx->plane_res.xfm, attributes); |
2803 | } |
2804 | |
2805 | bool_Bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, |
2806 | uint32_t backlight_pwm_u16_16, |
2807 | uint32_t frame_ramp) |
2808 | { |
2809 | struct dc_link *link = pipe_ctx->stream->link; |
2810 | struct dc *dc = link->ctx->dc; |
2811 | struct abm *abm = pipe_ctx->stream_res.abm; |
2812 | struct panel_cntl *panel_cntl = link->panel_cntl; |
2813 | struct dmcu *dmcu = dc->res_pool->dmcu; |
2814 | bool_Bool fw_set_brightness = true1; |
2815 | /* DMCU -1 for all controller id values, |
2816 | * therefore +1 here |
2817 | */ |
2818 | uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; |
2819 | |
2820 | if (abm == NULL((void *)0) || panel_cntl == NULL((void *)0) || (abm->funcs->set_backlight_level_pwm == NULL((void *)0))) |
2821 | return false0; |
2822 | |
2823 | if (dmcu) |
2824 | fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); |
2825 | |
2826 | if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) |
2827 | panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); |
2828 | else |
2829 | abm->funcs->set_backlight_level_pwm( |
2830 | abm, |
2831 | backlight_pwm_u16_16, |
2832 | frame_ramp, |
2833 | controller_id, |
2834 | link->panel_cntl->inst); |
2835 | |
2836 | return true1; |
2837 | } |
2838 | |
2839 | void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) |
2840 | { |
2841 | struct abm *abm = pipe_ctx->stream_res.abm; |
2842 | struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; |
2843 | |
2844 | if (abm) |
2845 | abm->funcs->set_abm_immediate_disable(abm, |
2846 | pipe_ctx->stream->link->panel_cntl->inst); |
2847 | |
2848 | if (panel_cntl) |
2849 | panel_cntl->funcs->store_backlight_level(panel_cntl); |
2850 | } |
2851 | |
2852 | void dce110_set_pipe(struct pipe_ctx *pipe_ctx) |
2853 | { |
2854 | struct abm *abm = pipe_ctx->stream_res.abm; |
2855 | struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; |
2856 | uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; |
2857 | |
2858 | if (abm && panel_cntl) |
2859 | abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); |
2860 | } |
2861 | |
2862 | static const struct hw_sequencer_funcs dce110_funcs = { |
2863 | .program_gamut_remap = program_gamut_remap, |
2864 | .program_output_csc = program_output_csc, |
2865 | .init_hw = init_hw, |
2866 | .apply_ctx_to_hw = dce110_apply_ctx_to_hw, |
2867 | .apply_ctx_for_surface = dce110_apply_ctx_for_surface, |
2868 | .post_unlock_program_front_end = dce110_post_unlock_program_front_end, |
2869 | .update_plane_addr = update_plane_addr, |
2870 | .update_pending_status = dce110_update_pending_status, |
2871 | .enable_accelerated_mode = dce110_enable_accelerated_mode, |
2872 | .enable_timing_synchronization = dce110_enable_timing_synchronization, |
2873 | .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, |
2874 | .update_info_frame = dce110_update_info_frame, |
2875 | .enable_stream = dce110_enable_stream, |
2876 | .disable_stream = dce110_disable_stream, |
2877 | .unblank_stream = dce110_unblank_stream, |
2878 | .blank_stream = dce110_blank_stream, |
2879 | .enable_audio_stream = dce110_enable_audio_stream, |
2880 | .disable_audio_stream = dce110_disable_audio_stream, |
2881 | .disable_plane = dce110_power_down_fe, |
2882 | .pipe_control_lock = dce_pipe_control_lock, |
2883 | .interdependent_update_lock = NULL((void *)0), |
2884 | .cursor_lock = dce_pipe_control_lock, |
2885 | .prepare_bandwidth = dce110_prepare_bandwidth, |
2886 | .optimize_bandwidth = dce110_optimize_bandwidth, |
2887 | .set_drr = set_drr, |
2888 | .get_position = get_position, |
2889 | .set_static_screen_control = set_static_screen_control, |
2890 | .setup_stereo = NULL((void *)0), |
2891 | .set_avmute = dce110_set_avmute, |
2892 | .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, |
2893 | .edp_backlight_control = dce110_edp_backlight_control, |
2894 | .edp_power_control = dce110_edp_power_control, |
2895 | .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, |
2896 | .set_cursor_position = dce110_set_cursor_position, |
2897 | .set_cursor_attribute = dce110_set_cursor_attribute, |
2898 | .set_backlight_level = dce110_set_backlight_level, |
2899 | .set_abm_immediate_disable = dce110_set_abm_immediate_disable, |
2900 | .set_pipe = dce110_set_pipe, |
2901 | }; |
2902 | |
2903 | static const struct hwseq_private_funcs dce110_private_funcs = { |
2904 | .init_pipes = init_pipes, |
2905 | .update_plane_addr = update_plane_addr, |
2906 | .set_input_transfer_func = dce110_set_input_transfer_func, |
2907 | .set_output_transfer_func = dce110_set_output_transfer_func, |
2908 | .power_down = dce110_power_down, |
2909 | .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, |
2910 | .enable_display_power_gating = dce110_enable_display_power_gating, |
2911 | .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, |
2912 | .enable_stream_timing = dce110_enable_stream_timing, |
2913 | .disable_stream_gating = NULL((void *)0), |
2914 | .enable_stream_gating = NULL((void *)0), |
2915 | .edp_backlight_control = dce110_edp_backlight_control, |
2916 | }; |
2917 | |
2918 | void dce110_hw_sequencer_construct(struct dc *dc) |
2919 | { |
2920 | dc->hwss = dce110_funcs; |
2921 | dc->hwseq->funcs = dce110_private_funcs; |
2922 | } |
2923 |